diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..9ef326ac1
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "suite/auto-sync/vendor/tree-sitter-cpp"]
+	path = suite/auto-sync/vendor/tree-sitter-cpp
+	url = https://github.com/tree-sitter/tree-sitter-cpp.git
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 7a986a08a..be87e6b88 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -101,6 +101,7 @@ set(SOURCES_ENGINE
     Mapping.c
     MCInst.c
     MCInstrDesc.c
+    MCInstPrinter.c
     MCRegisterInfo.c
     SStream.c
     utils.c
@@ -115,6 +116,7 @@ set(HEADERS_ENGINE
     MCFixedLenDisassembler.h
     MCInst.h
     MCInstrDesc.h
+    MCInstPrinter.h
     MCRegisterInfo.h
     SStream.h
     utils.h
@@ -141,6 +143,7 @@ set(HEADERS_COMMON
     include/capstone/sh.h
     include/capstone/tricore.h
     include/capstone/platform.h
+    include/capstone/sh.h
 )
 
 set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
@@ -149,7 +152,9 @@ set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
 if(CAPSTONE_ARM_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_ARM)
     set(SOURCES_ARM
+        arch/ARM/ARMBaseInfo.c
         arch/ARM/ARMDisassembler.c
+        arch/ARM/ARMDisassemblerExtension.c
         arch/ARM/ARMInstPrinter.c
         arch/ARM/ARMMapping.c
         arch/ARM/ARMModule.c
@@ -157,20 +162,20 @@ if(CAPSTONE_ARM_SUPPORT)
     set(HEADERS_ARM
         arch/ARM/ARMAddressingModes.h
         arch/ARM/ARMBaseInfo.h
-        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMDisassemblerExtension.h
         arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMLinkage.h
         arch/ARM/ARMMapping.h
         arch/ARM/ARMGenAsmWriter.inc
         arch/ARM/ARMGenDisassemblerTables.inc
         arch/ARM/ARMGenInstrInfo.inc
         arch/ARM/ARMGenRegisterInfo.inc
         arch/ARM/ARMGenSubtargetInfo.inc
-        arch/ARM/ARMMappingInsn.inc
-        arch/ARM/ARMMappingInsnOp.inc
-        arch/ARM/ARMGenRegisterName.inc
-        arch/ARM/ARMGenRegisterName_digit.inc
+        arch/ARM/ARMGenCSFeatureName.inc
+        arch/ARM/ARMGenCSMappingInsn.inc
+        arch/ARM/ARMGenCSMappingInsnOp.inc
+        arch/ARM/ARMGenCSMappingInsnName.inc
         arch/ARM/ARMGenSystemRegister.inc
-        arch/ARM/ARMMappingInsnName.inc
     )
     set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
 endif()
@@ -696,6 +701,7 @@ if(CAPSTONE_INSTALL)
     include("GNUInstallDirs")
 
     install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone)
+    install(FILES ${HEADERS_INC} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone/inc)
 
     configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY)
     install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig)
diff --git a/HACK.TXT b/HACK.TXT
index 76c56551f..4e786d29d 100644
--- a/HACK.TXT
+++ b/HACK.TXT
@@ -61,10 +61,35 @@ Coding style
 - C code follows Linux kernel coding style, using tabs for indentation.
 - Python code uses 4 spaces for indentation.
 
+Updating an Architecture
+------------------------
+
+The update tool for Capstone is called `auto-sync` and can be found in `suite/auto-sync`.
+
+Not all architectures are supported yet.
+Run `suite/auto-sync/Update-Arch.sh -h` to get a list of currently supported architectures.
+
+The documentation how to update with `auto-sync` or refactor an architecture module
+can be found in [docs/AutoSync.md](docs/AutoSync.md).
+
+If a module does not support `auto-sync` yet, it is highly recommended to refactor it
+instead of attempting to update it manually.
+Refactoring will take less time and updates it during the procedure.
+
+The one exception is `x86`. In LLVM we use several emitter backends to generate C code.
+One of those LLVM backends (the `DecoderEmitter`) has two versions.
+One for `x86` and another for all the other architectures.
+Until now it was not worth it to refactoring this unique `x86` backend. So `x86` is not
+supported currently.
 
 Adding an architecture
 ----------------------
 
+If your architecture is supported in LLVM or one of its forks, you can use `auto-sync` to
+add the new module.
+
+<!-- TODO: Move this info to the auto-sync docs -->
+
 Obviously, you first need to write all the logic and put it in a new directory arch/newarch
 Then, you have to modify other files.
 (You can look for one architecture such as EVM in these files to get what you need to do)
diff --git a/MCInst.c b/MCInst.c
index 1e876ce29..74112e6dc 100644
--- a/MCInst.c
+++ b/MCInst.c
@@ -27,7 +27,6 @@ void MCInst_Init(MCInst *inst)
 	inst->size = 0;
 	inst->has_imm = false;
 	inst->op1_size = 0;
-	inst->writeback = false;
 	inst->ac_idx = 0;
 	inst->popcode_adjust = 0;
 	inst->assembly[0] = '\0';
@@ -268,3 +267,16 @@ bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum)
 	assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
 	return MI->tied_op_idx[OpNum] != -1;
 }
+
+/// Returns the value of the @MCInst operand at index @OpNum.
+uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
+{
+	assert(OpNum < MAX_MC_OPS);
+	MCOperand *op = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isReg(op))
+		return MCOperand_getReg(op);
+	else if (MCOperand_isImm(op))
+		return MCOperand_getImm(op);
+	else
+		assert(0 && "Operand type not handled in this getter.");
+}
diff --git a/MCInst.h b/MCInst.h
index e3ecf4299..5a03b9368 100644
--- a/MCInst.h
+++ b/MCInst.h
@@ -38,7 +38,6 @@ struct MCOperand {
 		kDFPImmediate, ///< Double-Floating-point immediate operand.
 		kExpr,	       ///< Relocatable immediate operand.
 		kInst	       ///< Sub-instruction operand.
-
 	} MachineOperandType;
 	unsigned char Kind;
 
@@ -162,4 +161,6 @@ bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);
 
 bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum);
 
+uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum);
+
 #endif
diff --git a/MCInstPrinter.c b/MCInstPrinter.c
new file mode 100644
index 000000000..501b46642
--- /dev/null
+++ b/MCInstPrinter.c
@@ -0,0 +1,227 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+#include "MCInstPrinter.h"
+#include "cs_priv.h"
+#include <capstone/platform.h>
+
+extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
+
+static bool testFeatureBits(const MCInst *MI, uint32_t Value)
+{
+	assert(MI && MI->csh);
+	switch (MI->csh->arch) {
+	default:
+		assert(0 && "Not implemented for current arch.");
+	case CS_ARCH_ARM:
+		return ARM_getFeatureBits(MI->csh->mode, Value);
+	}
+}
+
+static bool matchAliasCondition(MCInst *MI, const MCRegisterInfo *MRI,
+								unsigned *OpIdx, const AliasMatchingData *M,
+								const AliasPatternCond *C,
+								bool *OrPredicateResult)
+{
+	// Feature tests are special, they don't consume operands.
+	if (C->Kind == AliasPatternCond_K_Feature)
+		return testFeatureBits(MI, C->Value);
+	if (C->Kind == AliasPatternCond_K_NegFeature)
+		return !testFeatureBits(MI, C->Value);
+	// For feature tests where just one feature is required in a list, set the
+	// predicate result bit to whether the expression will return true, and only
+	// return the real result at the end of list marker.
+	if (C->Kind == AliasPatternCond_K_OrFeature) {
+		*OrPredicateResult |= testFeatureBits(MI, C->Value);
+		return true;
+	}
+	if (C->Kind == AliasPatternCond_K_OrNegFeature) {
+		*OrPredicateResult |= !(testFeatureBits(MI, C->Value));
+		return true;
+	}
+	if (C->Kind == AliasPatternCond_K_EndOrFeatures) {
+		bool Res = *OrPredicateResult;
+		*OrPredicateResult = false;
+		return Res;
+	}
+
+	// Get and consume an operand.
+	MCOperand *Opnd = MCInst_getOperand(MI, *OpIdx);
+	++(*OpIdx);
+
+	// Check the specific condition for the operand.
+	switch (C->Kind) {
+	case AliasPatternCond_K_Imm:
+		// Operand must be a specific immediate.
+		return MCOperand_isImm(Opnd) &&
+			   MCOperand_getImm(Opnd) == (int32_t)C->Value;
+	case AliasPatternCond_K_Reg:
+		// Operand must be a specific register.
+		return MCOperand_isReg(Opnd) && MCOperand_getReg(Opnd) == C->Value;
+	case AliasPatternCond_K_TiedReg:
+		// Operand must match the register of another operand.
+		return MCOperand_isReg(Opnd) &&
+			   MCOperand_getReg(Opnd) ==
+				   MCOperand_getReg(MCInst_getOperand(MI, C->Value));
+	case AliasPatternCond_K_RegClass:
+		// Operand must be a register in this class. Value is a register class
+		// id.
+		return MCOperand_isReg(Opnd) &&
+			   MCRegisterClass_contains(
+				   MCRegisterInfo_getRegClass(MRI, C->Value),
+				   MCOperand_getReg(Opnd));
+	case AliasPatternCond_K_Custom:
+		// Operand must match some custom criteria.
+		assert(M->ValidateMCOperand && "A custom validator should be set but isn't.");
+		return M->ValidateMCOperand(Opnd, C->Value);
+	case AliasPatternCond_K_Ignore:
+		// Operand can be anything.
+		return true;
+	case AliasPatternCond_K_Feature:
+	case AliasPatternCond_K_NegFeature:
+	case AliasPatternCond_K_OrFeature:
+	case AliasPatternCond_K_OrNegFeature:
+	case AliasPatternCond_K_EndOrFeatures:
+		assert(0 && "handled earlier");
+	}
+	assert(0 && "invalid kind");
+}
+
+/// Check if PatternsForOpcode is all zero.
+static inline bool validOpToPatter(const PatternsForOpcode *P)
+{
+	return !(P->Opcode == 0 && P->PatternStart == 0 && P->NumPatterns == 0);
+}
+
+const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M)
+{
+	// TODO Rewrite to C
+
+	// auto It = lower_bound(M.OpToPatterns, MI->getOpcode(),
+	//                       [](const PatternsForOpcode &L, unsigned Opcode) {
+	//                         return L.Opcode < Opcode;
+	//                       });
+	// if (It == M.OpToPatterns.end() || It->Opcode != MI->getOpcode())
+	//   return nullptr;
+
+	// Binary search by opcode. Return false if there are no aliases for this
+	// opcode.
+	unsigned MIOpcode = MI->Opcode;
+	size_t i = 0;
+	uint32_t PatternOpcode = M->OpToPatterns[i].Opcode;
+	while (PatternOpcode < MIOpcode && validOpToPatter(&M->OpToPatterns[i]))
+		PatternOpcode = M->OpToPatterns[++i].Opcode;
+	if (PatternOpcode != MI->Opcode || !validOpToPatter(&M->OpToPatterns[i]))
+		return NULL;
+
+	// // Try all patterns for this opcode.
+	uint32_t AsmStrOffset = ~0U;
+	const AliasPattern *Patterns = M->Patterns + M->OpToPatterns[i].PatternStart;
+	for (const AliasPattern *P = Patterns;
+		P != Patterns + M->OpToPatterns[i].NumPatterns; ++P) {
+		// Check operand count first.
+		if (MCInst_getNumOperands(MI) != P->NumOperands)
+			return NULL;
+
+		// Test all conditions for this pattern.
+		const AliasPatternCond *Conds = M->PatternConds + P->AliasCondStart;
+		unsigned OpIdx = 0;
+		bool OrPredicateResult = false;
+		bool allMatch = true;
+		for (const AliasPatternCond *C = Conds; C != Conds + P->NumConds; ++C) {
+			if (!matchAliasCondition(MI, MI->MRI, &OpIdx, M, C, &OrPredicateResult)) {
+				allMatch = false;
+				break;
+			}
+		}
+		if (allMatch) {
+			AsmStrOffset = P->AsmStrOffset;
+			break;
+		}
+	}
+	// If no alias matched, don't print an alias.
+	if (AsmStrOffset == ~0U)
+		return NULL;
+
+	// Go to offset AsmStrOffset and use the null terminated string there. The
+	// offset should point to the beginning of an alias string, so it should
+	// either be zero or be preceded by a null byte.
+	return M->AsmStrings + AsmStrOffset;
+}
+
+// TODO Add functionality to toggle the flag.
+bool getUseMarkup(void) { return false; }
+
+/// Utility functions to make adding mark ups simpler.
+const char *markup(const char *s)
+{
+	static const char *no_markup = "";
+	if (getUseMarkup())
+		return s;
+	else
+		return no_markup;
+}
+
+// binary search for encoding in IndexType array
+// return -1 if not found, or index if found
+unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding)
+{
+	// binary searching since the index is sorted in encoding order
+	size_t left, right, m;
+
+	right = size - 1;
+
+	if (encoding < index[0].encoding || encoding > index[right].encoding)
+		// not found
+		return -1;
+
+	left = 0;
+
+	while(left <= right) {
+		m = (left + right) / 2;
+		if (encoding == index[m].encoding) {
+			return m;
+		}
+
+		if (encoding < index[m].encoding)
+			right = m - 1;
+		else
+			left = m + 1;
+	}
+
+	// not found
+	return -1;
+}
+
+// binary search for encoding in IndexTypeStr array
+// return -1 if not found, or index if found
+unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name)
+{
+	// binary searching since the index is sorted in encoding order
+	size_t left, right, m;
+
+	right = size - 1;
+
+	size_t str_left_cmp = strcmp(name, index[0].name);
+	size_t str_right_cmp = strcmp(name, index[right].name);
+	if (str_left_cmp < 0 || str_right_cmp > 0)
+		// not found
+		return -1;
+
+	left = 0;
+
+	while(left <= right) {
+		m = (left + right) / 2;
+		if (strcmp(name, index[m].name) == 0) {
+			return m;
+		}
+
+		if (strcmp(name, index[m].name) < 0)
+			right = m - 1;
+		else
+			left = m + 1;
+	}
+
+	// not found
+	return -1;
+}
diff --git a/MCInstPrinter.h b/MCInstPrinter.h
new file mode 100644
index 000000000..d8c69fc46
--- /dev/null
+++ b/MCInstPrinter.h
@@ -0,0 +1,84 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+#ifndef CS_MCINSTPRINTER_H
+#define CS_MCINSTPRINTER_H
+
+#include "MCInst.h"
+#include <assert.h>
+#include <capstone/platform.h>
+
+/// Returned by getMnemonic() of the AsmPrinters.
+typedef struct {
+	const char *first; // Menmonic
+	uint64_t second;   // Bits
+} MnemonicBitsInfo;
+
+/// Map from opcode to pattern list by binary search.
+typedef struct {
+	uint32_t Opcode;
+	uint16_t PatternStart;
+	uint16_t NumPatterns;
+} PatternsForOpcode;
+
+/// Data for each alias pattern. Includes feature bits, string, number of
+/// operands, and a variadic list of conditions to check.
+typedef struct {
+	uint32_t AsmStrOffset;
+	uint32_t AliasCondStart;
+	uint8_t NumOperands;
+	uint8_t NumConds;
+} AliasPattern;
+
+typedef enum {
+	AliasPatternCond_K_Feature,	   // Match only if a feature is enabled.
+	AliasPatternCond_K_NegFeature, // Match only if a feature is disabled.
+	AliasPatternCond_K_OrFeature,  // Match only if one of a set of features is
+								   // enabled.
+	AliasPatternCond_K_OrNegFeature,  // Match only if one of a set of features
+									 // is disabled.
+	AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features.
+	AliasPatternCond_K_Ignore,		  // Match any operand.
+	AliasPatternCond_K_Reg,			  // Match a specific register.
+	AliasPatternCond_K_TiedReg,		  // Match another already matched register.
+	AliasPatternCond_K_Imm,			  // Match a specific immediate.
+	AliasPatternCond_K_RegClass,	  // Match registers in a class.
+	AliasPatternCond_K_Custom,		  // Call custom matcher by index.
+} AliasPatternCond_CondKind;
+
+typedef struct {
+	AliasPatternCond_CondKind Kind;
+	uint32_t Value;
+} AliasPatternCond;
+
+typedef bool (*ValidateMCOperandFunc)(const MCOperand *MCOp, unsigned PredicateIndex);
+
+/// Tablegenerated data structures needed to match alias patterns.
+typedef struct {
+	const PatternsForOpcode *OpToPatterns;
+	const AliasPattern *Patterns;
+	const AliasPatternCond *PatternConds;
+	const char *AsmStrings;
+	const ValidateMCOperandFunc ValidateMCOperand;
+} AliasMatchingData;
+
+const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M);
+bool getUseMarkup(void);
+const char *markup(const char *s);
+
+struct IndexType {
+	uint16_t encoding;
+	unsigned index;
+};
+
+struct IndexTypeStr {
+	const char *name;
+	unsigned index;
+};
+
+// binary search for encoding in IndexType array
+// return -1 if not found, or index if found
+unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding);
+unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name);
+
+#endif // CS_MCINSTPRINTER_H
diff --git a/MCInstrDesc.h b/MCInstrDesc.h
index 001059c78..e9e6fcd13 100644
--- a/MCInstrDesc.h
+++ b/MCInstrDesc.h
@@ -91,9 +91,9 @@ typedef struct MCOperandInfo {
 	/// Information about the type of the operand.
 	uint8_t OperandType;
 
-	/// The lower 16 bits are used to specify which constraints are set.
-	/// The higher 16 bits are used to specify the value of constraints (4 bits each).
-	uint32_t Constraints;
+	/// The lower 3 bits are used to specify which constraints are set.
+	/// The higher 13 bits are used to specify the value of constraints (4 bits each).
+	uint16_t Constraints;
 	/// Currently no other information.
 } MCOperandInfo;
 
diff --git a/Makefile b/Makefile
index f84d43c1f..b986d5df0 100644
--- a/Makefile
+++ b/Makefile
@@ -326,7 +326,7 @@ endif
 
 
 LIBOBJ =
-LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/Mapping.o
+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
 LIBOBJ += $(LIBOBJ_TRICORE)
diff --git a/Mapping.c b/Mapping.c
index f887293cb..305e61696 100644
--- a/Mapping.c
+++ b/Mapping.c
@@ -85,6 +85,30 @@ void map_add_implicit_write(MCInst *MI, uint32_t Reg)
 	}
 }
 
+/// Removes a register from the implicit write register list.
+void map_remove_implicit_write(MCInst *MI, uint32_t Reg)
+{
+	if (!MI->flat_insn->detail)
+		return;
+
+	uint16_t *regs_write = MI->flat_insn->detail->regs_write;
+	bool shorten_list = false;
+	for (int i = 0; i < MAX_IMPL_W_REGS; ++i) {
+		if (shorten_list) {
+			regs_write[i - 1] = regs_write[i];
+		}
+		if (i >= MI->flat_insn->detail->regs_write_count)
+			return;
+
+		if (regs_write[i] == Reg) {
+			MI->flat_insn->detail->regs_write_count--;
+			// The register should exist only once in the list.
+			assert(!shorten_list);
+			shorten_list = true;
+		}
+	}
+}
+
 /// Copies the implicit read registers of @imap to @MI->flat_insn.
 /// Already present registers will be preserved.
 void map_implicit_reads(MCInst *MI, const insn_map *imap)
@@ -135,6 +159,21 @@ void map_implicit_writes(MCInst *MI, const insn_map *imap)
 #endif // CAPSTONE_DIET
 }
 
+/// Adds a given group to @MI->flat_insn.
+void add_group(MCInst *MI, unsigned /* arch_group */ group) {
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+
+	cs_detail *detail = MI->flat_insn->detail;
+	if (detail->groups_count >= MAX_NUM_GROUPS) {
+		printf("ERROR: Too many groups defined.\n");
+		return;
+	}
+	detail->groups[detail->groups_count++] = group;
+#endif // CAPSTONE_DIET
+}
+
 /// Copies the groups from @imap to @MI->flat_insn.
 /// Already present groups will be preserved.
 void map_groups(MCInst *MI, const insn_map *imap)
diff --git a/Mapping.h b/Mapping.h
index 87e4d085d..87aaa1e4b 100644
--- a/Mapping.h
+++ b/Mapping.h
@@ -98,11 +98,14 @@ int name2id(const name_map *map, int max, const char *name);
 const char *id2name(const name_map *map, int max, const unsigned int id);
 
 void map_add_implicit_write(MCInst *MI, uint32_t Reg);
+void map_remove_implicit_write(MCInst *MI, uint32_t Reg);
 
 void map_implicit_reads(MCInst *MI, const insn_map *imap);
 
 void map_implicit_writes(MCInst *MI, const insn_map *imap);
 
+void add_group(MCInst *MI, unsigned /* arch_group */ group);
+
 void map_groups(MCInst *MI, const insn_map *imap);
 
 void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);
diff --git a/MathExtras.h b/MathExtras.h
index e9f18689b..fa73e578a 100644
--- a/MathExtras.h
+++ b/MathExtras.h
@@ -203,6 +203,18 @@ static inline unsigned CountTrailingZeros_32(uint32_t Value) {
 #endif
 }
 
+// Count trailing zeros as in:
+// https://graphics.stanford.edu/~seander/bithacks.html#ZerosOnRightParallel
+static inline unsigned CountTrailingZeros_8(uint8_t Value) {
+	uint8_t c = 8;
+	Value &= -((int8_t)Value);
+	if (Value) c--;
+	if (Value & 0x0F) c -= 4;
+	if (Value & 0x33) c -= 2;
+	if (Value & 0x55) c -= 1;
+	return c;
+}
+
 /// CountTrailingOnes_32 - this function performs the operation of
 /// counting the number of ones from the least significant bit to the first zero
 /// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
diff --git a/SStream.c b/SStream.c
index 4a50a14cf..b0544c423 100644
--- a/SStream.c
+++ b/SStream.c
@@ -28,9 +28,14 @@ void SStream_Init(SStream *ss)
 	ss->buffer[0] = '\0';
 }
 
+/**
+ * Copy the string \p s to the buffer of \p ss and terminate it with a '\\0' byte.
+ */
 void SStream_concat0(SStream *ss, const char *s)
 {
 #ifndef CAPSTONE_DIET
+	if (s[0] == '\0')
+		return;
 	unsigned int len = (unsigned int) strlen(s);
 
 	memcpy(ss->buffer + ss->index, s, len);
@@ -39,15 +44,23 @@ void SStream_concat0(SStream *ss, const char *s)
 #endif
 }
 
+/**
+ * Copy the single char \p c to the buffer of \p ss.
+ */
 void SStream_concat1(SStream *ss, const char c)
 {
 #ifndef CAPSTONE_DIET
+	if (c == '\0')
+		return;
 	ss->buffer[ss->index] = c;
 	ss->index++;
 	ss->buffer[ss->index] = '\0';
 #endif
 }
 
+/**
+ * Copy all strings given to the buffer of \p ss according to formatting \p fmt.
+ */
 void SStream_concat(SStream *ss, const char *fmt, ...)
 {
 #ifndef CAPSTONE_DIET
@@ -179,3 +192,13 @@ void printUInt32(SStream *O, uint32_t val)
 	else
 		SStream_concat(O, "%u", val);
 }
+
+void printFloat(SStream *O, float val)
+{
+	SStream_concat(O, "%e", val);
+}
+
+void printFloatBang(SStream *O, float val)
+{
+	SStream_concat(O, "#%e", val);
+}
diff --git a/SStream.h b/SStream.h
index e70a3141b..d000a0cc7 100644
--- a/SStream.h
+++ b/SStream.h
@@ -37,4 +37,8 @@ void printUInt32(SStream *O, uint32_t val);
 // print number in decimal mode
 void printInt32BangDec(SStream *O, int32_t val);
 
+void printFloat(SStream *O, float val);
+
+void printFloatBang(SStream *O, float val);
+
 #endif
diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h
index 69acf4210..cfd2a2e16 100644
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@@ -22,6 +22,8 @@
 
 #include <ctype.h>
 #include <string.h>
+
+#include "../../MCInstPrinter.h"
 #include "AArch64Mapping.h"
 
 #ifndef __cplusplus
@@ -541,45 +543,6 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
 // These are required for the updated printAliasInstr() function in
 // $ARCHGenAsmWriter.inc
 
-/// Map from opcode to pattern list by binary search.
-typedef struct PatternsForOpcode {
-  uint32_t Opcode;
-  uint16_t PatternStart;
-  uint16_t NumPatterns;
-} PatternsForOpcode;
-
-/// Data for each alias pattern. Includes feature bits, string, number of
-/// operands, and a variadic list of conditions to check.
-typedef struct AliasPattern {
-  uint32_t AsmStrOffset;
-  uint32_t AliasCondStart;
-  uint8_t NumOperands;
-  uint8_t NumConds;
-} AliasPattern;
-
-enum CondKind {
-  AliasPatternCond_K_Feature,	      // Match only if a feature is enabled.
-  AliasPatternCond_K_NegFeature,    // Match only if a feature is disabled.
-  AliasPatternCond_K_OrFeature,	    // Match only if one of a set of features is
-				                            // enabled.
-  AliasPatternCond_K_OrNegFeature,  // Match only if one of a set of features is
-				                            // disabled.
-  AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features.
-  AliasPatternCond_K_Ignore,	      // Match any operand.
-  AliasPatternCond_K_Reg,	          // Match a specific register.
-  AliasPatternCond_K_TiedReg,	      // Match another already matched register.
-  AliasPatternCond_K_Imm,	          // Match a specific immediate.
-  AliasPatternCond_K_RegClass,	    // Match registers in a class.
-  AliasPatternCond_K_Custom,	      // Call custom matcher by index.
-};
-
-typedef struct AliasPatternCond {
-  int Kind;
-  uint32_t Value;
-} AliasPatternCond;
-
-// ---------------------------------------------------------------------------
-
 #include "AArch64GenSystemOperands_enum.inc"
 
 #endif
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index a987af684..e536675b2 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "AArch64Mapping.h"
diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h
index c4a2f98ab..bd5887db8 100644
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@@ -1,9 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
 //===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
@@ -11,29 +24,32 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+#ifndef CS_ARM_ADDRESSINGMODES_H
+#define CS_ARM_ADDRESSINGMODES_H
 
-#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
-#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
-#include "capstone/platform.h"
 #include "../../MathExtras.h"
+#include <assert.h>
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
 
 /// ARM_AM - ARM Addressing Mode Stuff
-typedef enum ARM_AM_ShiftOpc {
+typedef enum ShiftOpc {
 	ARM_AM_no_shift = 0,
 	ARM_AM_asr,
 	ARM_AM_lsl,
 	ARM_AM_lsr,
 	ARM_AM_ror,
-	ARM_AM_rrx
+	ARM_AM_rrx,
+	ARM_AM_uxtw
 } ARM_AM_ShiftOpc;
 
-typedef enum ARM_AM_AddrOpc {
-	ARM_AM_sub = 0,
-	ARM_AM_add
-} ARM_AM_AddrOpc;
+typedef enum AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc;
 
 static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
 {
@@ -43,59 +59,77 @@ static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
 static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
 {
 	switch (Op) {
-		default: return "";	//llvm_unreachable("Unknown shift opc!");
-		case ARM_AM_asr: return "asr";
-		case ARM_AM_lsl: return "lsl";
-		case ARM_AM_lsr: return "lsr";
-		case ARM_AM_ror: return "ror";
-		case ARM_AM_rrx: return "rrx";
+	default:
+		assert(0 && "Unknown shift opc!");
+	case ARM_AM_asr:
+		return "asr";
+	case ARM_AM_lsl:
+		return "lsl";
+	case ARM_AM_lsr:
+		return "lsr";
+	case ARM_AM_ror:
+		return "ror";
+	case ARM_AM_rrx:
+		return "rrx";
+	case ARM_AM_uxtw:
+		return "uxtw";
 	}
 }
 
 static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
 {
 	switch (Op) {
-		default: return (unsigned int)-1;	//llvm_unreachable("Unknown shift opc!");
-		case ARM_AM_asr: return 2;
-		case ARM_AM_lsl: return 0;
-		case ARM_AM_lsr: return 1;
-		case ARM_AM_ror: return 3;
+	default:
+		assert(0 && "Unknown shift opc!");
+	case ARM_AM_asr:
+		return 2;
+	case ARM_AM_lsl:
+		return 0;
+	case ARM_AM_lsr:
+		return 1;
+	case ARM_AM_ror:
+		return 3;
 	}
 }
 
-typedef enum ARM_AM_AMSubMode {
+typedef enum AMSubMode {
 	ARM_AM_bad_am_submode = 0,
 	ARM_AM_ia,
 	ARM_AM_ib,
 	ARM_AM_da,
 	ARM_AM_db
-} ARM_AM_AMSubMode;
+} ARM_AM_SubMode;
 
-static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode)
+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode)
 {
 	switch (Mode) {
-		default: return "";
-		case ARM_AM_ia: return "ia";
-		case ARM_AM_ib: return "ib";
-		case ARM_AM_da: return "da";
-		case ARM_AM_db: return "db";
+	default:
+		assert(0 && "Unknown addressing sub-mode!");
+	case ARM_AM_ia:
+		return "ia";
+	case ARM_AM_ib:
+		return "ib";
+	case ARM_AM_da:
+		return "da";
+	case ARM_AM_db:
+		return "db";
 	}
 }
 
 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
 ///
-static inline unsigned rotr32(unsigned Val, unsigned Amt)
+static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
 {
-	//assert(Amt < 32 && "Invalid rotate amount");
-	return (Val >> Amt) | (Val << ((32-Amt)&31));
+
+	return (Val >> Amt) | (Val << ((32 - Amt) & 31));
 }
 
 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
 ///
-static inline unsigned rotl32(unsigned Val, unsigned Amt)
+static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
 {
-	//assert(Amt < 32 && "Invalid rotate amount");
-	return (Val << Amt) | (Val >> ((32-Amt)&31));
+
+	return (Val << Amt) | (Val >> ((32 - Amt) & 31));
 }
 
 //===--------------------------------------------------------------------===//
@@ -112,15 +146,12 @@ static inline unsigned rotl32(unsigned Val, unsigned Amt)
 // reg, the second is the shift amount (or reg0 if not present or imm).  The
 // third operand encodes the shift opcode and the imm if a reg isn't present.
 //
-static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
+static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
 {
 	return ShOp | (Imm << 3);
 }
 
-static inline unsigned getSORegOffset(unsigned Op)
-{
-	return Op >> 3;
-}
+static inline unsigned ARM_AM_getSORegOffset(unsigned Op) { return Op >> 3; }
 
 static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
 {
@@ -129,14 +160,14 @@ static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
 
 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
 /// the 8-bit imm value.
-static inline unsigned getSOImmValImm(unsigned Imm)
+static inline unsigned ARM_AM_getSOImmValImm(unsigned Imm)
 {
 	return Imm & 0xFF;
 }
 
 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
 /// the rotate amount.
-static inline unsigned getSOImmValRot(unsigned Imm)
+static inline unsigned ARM_AM_getSOImmValRot(unsigned Imm)
 {
 	return (Imm >> 8) * 2;
 }
@@ -145,99 +176,115 @@ static inline unsigned getSOImmValRot(unsigned Imm)
 /// computing the rotate amount to use.  If this immediate value cannot be
 /// handled with a single shifter-op, determine a good rotate amount that will
 /// take a maximal chunk of bits out of the immediate.
-static inline unsigned getSOImmValRotate(unsigned Imm)
+static inline unsigned ARM_AM_getSOImmValRotate(unsigned Imm)
 {
-	unsigned TZ, RotAmt;
 	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
 	// of zero.
-	if ((Imm & ~255U) == 0) return 0;
+	if ((Imm & ~255U) == 0)
+		return 0;
 
 	// Use CTZ to compute the rotate amount.
-	TZ = CountTrailingZeros_32(Imm);
+	unsigned TZ = CountTrailingZeros_32(Imm);
 
 	// Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
 	// not 9.
-	RotAmt = TZ & ~1;
+	unsigned RotAmt = TZ & ~1;
 
 	// If we can handle this spread, return it.
-	if ((rotr32(Imm, RotAmt) & ~255U) == 0)
-		return (32-RotAmt)&31;  // HW rotates right, not left.
+	if ((ARM_AM_rotr32(Imm, RotAmt) & ~255U) == 0)
+		return (32 - RotAmt) & 31; // HW rotates right, not left.
 
 	// For values like 0xF000000F, we should ignore the low 6 bits, then
 	// retry the hunt.
 	if (Imm & 63U) {
 		unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
 		unsigned RotAmt2 = TZ2 & ~1;
-		if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
-			return (32-RotAmt2)&31;  // HW rotates right, not left.
+		if ((ARM_AM_rotr32(Imm, RotAmt2) & ~255U) == 0)
+			return (32 - RotAmt2) & 31; // HW rotates right, not left.
 	}
 
 	// Otherwise, we have no way to cover this span of bits with a single
 	// shifter_op immediate.  Return a chunk of bits that will be useful to
 	// handle.
-	return (32-RotAmt)&31;  // HW rotates right, not left.
+	return (32 - RotAmt) & 31; // HW rotates right, not left.
 }
 
 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
 /// into an shifter_operand immediate operand, return the 12-bit encoding for
 /// it.  If not, return -1.
-static inline int getSOImmVal(unsigned Arg)
+static inline int ARM_AM_getSOImmVal(unsigned Arg)
 {
-	unsigned RotAmt;
 	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
 	// of zero.
-	if ((Arg & ~255U) == 0) return Arg;
+	if ((Arg & ~255U) == 0)
+		return Arg;
 
-	RotAmt = getSOImmValRotate(Arg);
+	unsigned RotAmt = ARM_AM_getSOImmValRotate(Arg);
 
 	// If this cannot be handled with a single shifter_op, bail out.
-	if (rotr32(~255U, RotAmt) & Arg)
+	if (ARM_AM_rotr32(~255U, RotAmt) & Arg)
 		return -1;
 
 	// Encode this correctly.
-	return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
+	return ARM_AM_rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8);
 }
 
 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
 /// or'ing together two SOImmVal's.
-static inline bool isSOImmTwoPartVal(unsigned V)
+static inline bool ARM_AM_isSOImmTwoPartVal(unsigned V)
 {
 	// If this can be handled with a single shifter_op, bail out.
-	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
 	if (V == 0)
 		return false;
 
 	// If this can be handled with two shifter_op's, accept.
-	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
 	return V == 0;
 }
 
 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
 /// return the first chunk of it.
-static inline unsigned getSOImmTwoPartFirst(unsigned V)
+static inline unsigned ARM_AM_getSOImmTwoPartFirst(unsigned V)
 {
-	return rotr32(255U, getSOImmValRotate(V)) & V;
+	return ARM_AM_rotr32(255U, ARM_AM_getSOImmValRotate(V)) & V;
 }
 
 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
 /// return the second chunk of it.
-static inline unsigned getSOImmTwoPartSecond(unsigned V)
+static inline unsigned ARM_AM_getSOImmTwoPartSecond(unsigned V)
 {
 	// Mask out the first hunk.
-	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
 
 	// Take what's left.
-	//assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
+
 	return V;
 }
 
+/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
+/// by two SOImmVal, that -V = First + Second.
+/// "R+V" can be optimized to (sub (sub R, First), Second).
+/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
+static inline bool ARM_AM_isSOImmTwoPartValNeg(unsigned V)
+{
+	unsigned First;
+	if (!ARM_AM_isSOImmTwoPartVal(-V))
+		return false;
+	// Return false if ~(-First) is not a SoImmval.
+	First = ARM_AM_getSOImmTwoPartFirst(-V);
+	First = ~(-First);
+	return !(ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(First)) & First);
+}
+
 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
 /// by a left shift. Returns the shift amount to use.
-static inline unsigned getThumbImmValShift(unsigned Imm)
+static inline unsigned ARM_AM_getThumbImmValShift(unsigned Imm)
 {
 	// 8-bit (or less) immediates are trivially immediate operand with a shift
 	// of zero.
-	if ((Imm & ~255U) == 0) return 0;
+	if ((Imm & ~255U) == 0)
+		return 0;
 
 	// Use CTZ to compute the shift amount.
 	return CountTrailingZeros_32(Imm);
@@ -245,20 +292,21 @@ static inline unsigned getThumbImmValShift(unsigned Imm)
 
 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
 /// by left shifting a 8-bit immediate.
-static inline bool isThumbImmShiftedVal(unsigned V)
+static inline bool ARM_AM_isThumbImmShiftedVal(unsigned V)
 {
 	// If this can be handled with
-	V = (~255U << getThumbImmValShift(V)) & V;
+	V = (~255U << ARM_AM_getThumbImmValShift(V)) & V;
 	return V == 0;
 }
 
 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
 /// by a left shift. Returns the shift amount to use.
-static inline unsigned getThumbImm16ValShift(unsigned Imm)
+static inline unsigned ARM_AM_getThumbImm16ValShift(unsigned Imm)
 {
 	// 16-bit (or less) immediates are trivially immediate operand with a shift
 	// of zero.
-	if ((Imm & ~65535U) == 0) return 0;
+	if ((Imm & ~65535U) == 0)
+		return 0;
 
 	// Use CTZ to compute the shift amount.
 	return CountTrailingZeros_32(Imm);
@@ -266,21 +314,20 @@ static inline unsigned getThumbImm16ValShift(unsigned Imm)
 
 /// isThumbImm16ShiftedVal - Return true if the specified value can be
 /// obtained by left shifting a 16-bit immediate.
-static inline bool isThumbImm16ShiftedVal(unsigned V)
+static inline bool ARM_AM_isThumbImm16ShiftedVal(unsigned V)
 {
 	// If this can be handled with
-	V = (~65535U << getThumbImm16ValShift(V)) & V;
+	V = (~65535U << ARM_AM_getThumbImm16ValShift(V)) & V;
 	return V == 0;
 }
 
 /// getThumbImmNonShiftedVal - If V is a value that satisfies
 /// isThumbImmShiftedVal, return the non-shiftd value.
-static inline unsigned getThumbImmNonShiftedVal(unsigned V)
+static inline unsigned ARM_AM_getThumbImmNonShiftedVal(unsigned V)
 {
-	return V >> getThumbImmValShift(V);
+	return V >> ARM_AM_getThumbImmValShift(V);
 }
 
-
 /// getT2SOImmValSplat - Return the 12-bit encoded representation
 /// if the specified value can be obtained by splatting the low 8 bits
 /// into every other byte or every byte of a 32-bit value. i.e.,
@@ -290,7 +337,7 @@ static inline unsigned getThumbImmNonShiftedVal(unsigned V)
 ///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
 /// Return -1 if none of the above apply.
 /// See ARM Reference Manual A6.3.2.
-static inline int getT2SOImmValSplatVal(unsigned V)
+static inline int ARM_AM_getT2SOImmValSplatVal(unsigned V)
 {
 	unsigned u, Vs, Imm;
 	// control = 0
@@ -319,15 +366,15 @@ static inline int getT2SOImmValSplatVal(unsigned V)
 /// specified value is a rotated 8-bit value. Return -1 if no rotation
 /// encoding is possible.
 /// See ARM Reference Manual A6.3.2.
-static inline int getT2SOImmValRotateVal(unsigned V)
+static inline int ARM_AM_getT2SOImmValRotateVal(unsigned V)
 {
 	unsigned RotAmt = CountLeadingZeros_32(V);
 	if (RotAmt >= 24)
 		return -1;
 
 	// If 'Arg' can be handled with a single shifter_op return the value.
-	if ((rotr32(0xff000000U, RotAmt) & V) == V)
-		return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
+	if ((ARM_AM_rotr32(0xff000000U, RotAmt) & V) == V)
+		return (ARM_AM_rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
 
 	return -1;
 }
@@ -336,91 +383,87 @@ static inline int getT2SOImmValRotateVal(unsigned V)
 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
 /// encoding for it.  If not, return -1.
 /// See ARM Reference Manual A6.3.2.
-static inline int getT2SOImmVal(unsigned Arg)
+static inline int ARM_AM_getT2SOImmVal(unsigned Arg)
 {
-	int Rot;
 	// If 'Arg' is an 8-bit splat, then get the encoded value.
-	int Splat = getT2SOImmValSplatVal(Arg);
+	int Splat = ARM_AM_getT2SOImmValSplatVal(Arg);
 	if (Splat != -1)
 		return Splat;
 
 	// If 'Arg' can be handled with a single shifter_op return the value.
-	Rot = getT2SOImmValRotateVal(Arg);
+	int Rot = ARM_AM_getT2SOImmValRotateVal(Arg);
 	if (Rot != -1)
 		return Rot;
 
 	return -1;
 }
 
-static inline unsigned getT2SOImmValRotate(unsigned V)
+static inline unsigned ARM_AM_getT2SOImmValRotate(unsigned V)
 {
-	unsigned RotAmt;
-
 	if ((V & ~255U) == 0)
 		return 0;
-
 	// Use CTZ to compute the rotate amount.
-	RotAmt = CountTrailingZeros_32(V);
+	unsigned RotAmt = CountTrailingZeros_32(V);
 	return (32 - RotAmt) & 31;
 }
 
-static inline bool isT2SOImmTwoPartVal (unsigned Imm)
+static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm)
 {
 	unsigned V = Imm;
 	// Passing values can be any combination of splat values and shifter
 	// values. If this can be handled with a single shifter or splat, bail
 	// out. Those should be handled directly, not with a two-part val.
-	if (getT2SOImmValSplatVal(V) != -1)
+	if (ARM_AM_getT2SOImmValSplatVal(V) != -1)
 		return false;
-	V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getT2SOImmValRotate(V)) & V;
 	if (V == 0)
 		return false;
 
 	// If this can be handled as an immediate, accept.
-	if (getT2SOImmVal(V) != -1) return true;
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return true;
 
 	// Likewise, try masking out a splat value first.
 	V = Imm;
-	if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+	if (ARM_AM_getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
 		V &= ~0xff00ff00U;
-	else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+	else if (ARM_AM_getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
 		V &= ~0x00ff00ffU;
 	// If what's left can be handled as an immediate, accept.
-	if (getT2SOImmVal(V) != -1) return true;
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return true;
 
 	// Otherwise, do not accept.
 	return false;
 }
 
-static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
+static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
 {
-	//assert (isT2SOImmTwoPartVal(Imm) &&
-	//        "Immedate cannot be encoded as two part immediate!");
+
 	// Try a shifter operand as one part
-	unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
+	unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm;
 	// If the rest is encodable as an immediate, then return it.
-	if (getT2SOImmVal(V) != -1) return V;
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return V;
 
 	// Try masking out a splat value first.
-	if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+	if (ARM_AM_getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
 		return Imm & 0xff00ff00U;
 
 	// The other splat is all that's left as an option.
-	//assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+
 	return Imm & 0x00ff00ffU;
 }
 
-static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
+static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
 {
 	// Mask out the first hunk
-	Imm ^= getT2SOImmTwoPartFirst(Imm);
+	Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm);
 	// Return what's left
-	//assert (getT2SOImmVal(Imm) != -1 &&
-	//        "Unable to encode second part of T2 two part SO immediate");
+
 	return Imm;
 }
 
-
 //===--------------------------------------------------------------------===//
 // Addressing Mode #2
 //===--------------------------------------------------------------------===//
@@ -439,30 +482,30 @@ static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
 // and code rewriting), this operand will have the form:  FI#, reg0, <offs>
 // with no shift amount for the frame offset.
 //
-static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO,
-		unsigned IdxMode)
+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12,
+										ARM_AM_ShiftOpc SO, unsigned IdxMode)
 {
-	//assert(Imm12 < (1 << 12) && "Imm too large!");
+
 	bool isSub = Opc == ARM_AM_sub;
-	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
+	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16);
 }
 
-static inline unsigned getAM2Offset(unsigned AM2Opc)
+static inline unsigned ARM_AM_getAM2Offset(unsigned AM2Opc)
 {
-	return AM2Opc & ((1 << 12)-1);
+	return AM2Opc & ((1 << 12) - 1);
 }
 
-static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc)
+static inline ARM_AM_AddrOpc ARM_AM_getAM2Op(unsigned AM2Opc)
 {
 	return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
-static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
+static inline ARM_AM_ShiftOpc ARM_AM_getAM2ShiftOpc(unsigned AM2Opc)
 {
 	return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
 }
 
-static inline unsigned getAM2IdxMode(unsigned AM2Opc)
+static inline unsigned ARM_AM_getAM2IdxMode(unsigned AM2Opc)
 {
 	return (AM2Opc >> 16);
 }
@@ -480,26 +523,25 @@ static inline unsigned getAM2IdxMode(unsigned AM2Opc)
 // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
 // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
 // index mode.
-
 /// getAM3Opc - This function encodes the addrmode3 opc field.
-static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset,
-		unsigned IdxMode)
+static inline unsigned ARM_AM_getAM3Opc(ARM_AM_AddrOpc Opc,
+										unsigned char Offset, unsigned IdxMode)
 {
 	bool isSub = Opc == ARM_AM_sub;
 	return ((int)isSub << 8) | Offset | (IdxMode << 9);
 }
 
-static inline unsigned char getAM3Offset(unsigned AM3Opc)
+static inline unsigned char ARM_AM_getAM3Offset(unsigned AM3Opc)
 {
 	return AM3Opc & 0xFF;
 }
 
-static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc)
+static inline ARM_AM_AddrOpc ARM_AM_getAM3Op(unsigned AM3Opc)
 {
 	return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
-static inline unsigned getAM3IdxMode(unsigned AM3Opc)
+static inline unsigned ARM_AM_getAM3IdxMode(unsigned AM3Opc)
 {
 	return (AM3Opc >> 9);
 }
@@ -518,13 +560,12 @@ static inline unsigned getAM3IdxMode(unsigned AM3Opc)
 //    DA - Decrement after
 //    DB - Decrement before
 // For VFP instructions, only the IA and DB modes are valid.
-
-static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode)
+static inline ARM_AM_SubMode ARM_AM_getAM4SubMode(unsigned Mode)
 {
-	return (ARM_AM_AMSubMode)(Mode & 0x7);
+	return (ARM_AM_SubMode)(Mode & 0x7);
 }
 
-static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
+static inline unsigned ARM_AM_getAM4ModeImm(ARM_AM_SubMode SubMode)
 {
 	return (int)SubMode;
 }
@@ -538,18 +579,20 @@ static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
 // addrmode5 := reg +/- imm8*4
 //
 // The first operand is always a Reg.  The second operand encodes the
-// operation in bit 8 and the immediate in bits 0-7.
-
+// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
 /// getAM5Opc - This function encodes the addrmode5 opc field.
-static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc,
+										unsigned char Offset)
 {
 	bool isSub = Opc == ARM_AM_sub;
 	return ((int)isSub << 8) | Offset;
 }
+
 static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
 {
 	return AM5Opc & 0xFF;
 }
+
 static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
 {
 	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
@@ -565,20 +608,20 @@ static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
 //
 // The first operand is always a Reg.  The second operand encodes the
 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
-
 /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
-static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
+static inline unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc,
+											unsigned char Offset)
 {
 	bool isSub = Opc == ARM_AM_sub;
 	return ((int)isSub << 8) | Offset;
 }
 
-static inline unsigned char getAM5FP16Offset(unsigned AM5Opc)
+static inline unsigned char ARM_AM_getAM5FP16Offset(unsigned AM5Opc)
 {
 	return AM5Opc & 0xFF;
 }
 
-static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc)
+static inline ARM_AM_AddrOpc ARM_AM_getAM5FP16Op(unsigned AM5Opc)
 {
 	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
@@ -595,41 +638,41 @@ static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc)
 // address register.  The second operand is the value of the alignment
 // specifier in bytes or zero if no explicit alignment.
 // Valid alignments depend on the specific instruction.
-
 //===--------------------------------------------------------------------===//
-// NEON Modified Immediates
+// NEON/MVE Modified Immediates
 //===--------------------------------------------------------------------===//
 //
-// Several NEON instructions (e.g., VMOV) take a "modified immediate"
+// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
 // vector operand, where a small immediate encoded in the instruction
 // specifies a full NEON vector value.  These modified immediates are
 // represented here as encoded integers.  The low 8 bits hold the immediate
 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
 // the "Cmode" field of the instruction.  The interfaces below treat the
 // Op and Cmode values as a single 5-bit value.
-
-static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
+static inline unsigned ARM_AM_createVMOVModImm(unsigned OpCmode, unsigned Val)
 {
 	return (OpCmode << 8) | Val;
 }
-static inline unsigned getNEONModImmOpCmode(unsigned ModImm)
+
+static inline unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm)
 {
 	return (ModImm >> 8) & 0x1f;
 }
-static inline unsigned getNEONModImmVal(unsigned ModImm)
+
+static inline unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm)
 {
 	return ModImm & 0xff;
 }
 
-/// decodeNEONModImm - Decode a NEON modified immediate value into the
+/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
 /// element value and the element size in bits.  (If the element size is
 /// smaller than the vector, it is splatted into all the elements.)
-static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits)
+static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm,
+											   unsigned *EltBits)
 {
-	unsigned OpCmode = getNEONModImmOpCmode(ModImm);
-	unsigned Imm8 = getNEONModImmVal(ModImm);
+	unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm);
+	unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm);
 	uint64_t Val = 0;
-	unsigned ByteNum;
 
 	if (OpCmode == 0xe) {
 		// 8-bit vector elements
@@ -637,62 +680,107 @@ static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBit
 		*EltBits = 8;
 	} else if ((OpCmode & 0xc) == 0x8) {
 		// 16-bit vector elements
-		ByteNum = (OpCmode & 0x6) >> 1;
-		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		unsigned ByteNum = (OpCmode & 0x6) >> 1;
+		Val = Imm8 << (8 * ByteNum);
 		*EltBits = 16;
 	} else if ((OpCmode & 0x8) == 0) {
 		// 32-bit vector elements, zero with one byte set
-		ByteNum = (OpCmode & 0x6) >> 1;
-		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		unsigned ByteNum = (OpCmode & 0x6) >> 1;
+		Val = Imm8 << (8 * ByteNum);
 		*EltBits = 32;
 	} else if ((OpCmode & 0xe) == 0xc) {
 		// 32-bit vector elements, one byte with low bits set
-		ByteNum = 1 + (OpCmode & 0x1);
+		unsigned ByteNum = 1 + (OpCmode & 0x1);
 		Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
 		*EltBits = 32;
 	} else if (OpCmode == 0x1e) {
 		// 64-bit vector elements
-		for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
+		for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
 			if ((ModImm >> ByteNum) & 1)
 				Val |= (uint64_t)0xff << (8 * ByteNum);
 		}
 		*EltBits = 64;
 	} else {
-		//llvm_unreachable("Unsupported NEON immediate");
+		assert(0 && "Unsupported VMOV immediate");
 	}
 	return Val;
 }
 
-ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
+// Generic validation for single-byte immediate (0X00, 00X0, etc).
+static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size)
+{
+
+	unsigned count = 0;
+	for (unsigned i = 0; i < Size; ++i) {
+		if (Value & 0xff)
+			count++;
+		Value >>= 8;
+	}
+	return count == 1;
+}
+
+/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
+static inline bool ARM_AM_isNEONi16splat(unsigned Value)
+{
+	if (Value > 0xffff)
+		return false;
+	// i16 value with set bits only in one byte X0 or 0X.
+	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 2);
+}
+
+// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
+static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value)
+{
+
+	if (Value >= 0x100)
+		Value = (Value >> 8) | 0xa00;
+	else
+		Value |= 0x800;
+	return Value;
+}
+
+/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
+static inline bool ARM_AM_isNEONi32splat(unsigned Value)
+{
+	// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
+	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 4);
+}
+
+/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
+static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value)
+{
+
+	if (Value >= 0x100 && Value <= 0xff00)
+		Value = (Value >> 8) | 0x200;
+	else if (Value > 0xffff && Value <= 0xff0000)
+		Value = (Value >> 16) | 0x400;
+	else if (Value > 0xffffff)
+		Value = (Value >> 24) | 0x600;
+	return Value;
+}
 
 //===--------------------------------------------------------------------===//
 // Floating-point Immediates
 //
-static inline float getFPImmFloat(unsigned Imm)
+static inline float ARM_AM_getFPImmFloat(unsigned Imm)
 {
 	// We expect an 8-bit binary encoding of a floating-point number here.
-	union {
-		uint32_t I;
-		float F;
-	} FPUnion;
 
 	uint8_t Sign = (Imm >> 7) & 0x1;
 	uint8_t Exp = (Imm >> 4) & 0x7;
 	uint8_t Mantissa = Imm & 0xf;
 
-	//   8-bit FP    iEEEE Float Encoding
+	//   8-bit FP    IEEE Float Encoding
 	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
 	//
 	// where B = NOT(b);
-
-	FPUnion.I = 0;
-	FPUnion.I |= ((uint32_t) Sign) << 31;
-	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
-	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
-	FPUnion.I |= (Exp & 0x3) << 23;
-	FPUnion.I |= Mantissa << 19;
-	return FPUnion.F;
+	uint32_t I = 0;
+	I |= Sign << 31;
+	I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	I |= (Exp & 0x3) << 23;
+	I |= Mantissa << 19;
+	return BitsToFloat(I);
 }
 
-#endif
-
+#endif // CS_ARM_ADDRESSINGMODES_H
diff --git a/arch/ARM/ARMBaseInfo.c b/arch/ARM/ARMBaseInfo.c
new file mode 100644
index 000000000..09b4e37d5
--- /dev/null
+++ b/arch/ARM/ARMBaseInfo.c
@@ -0,0 +1,96 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for ARM.
+//
+//===----------------------------------------------------------------------===//
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "ARMBaseInfo.h"
+#include "ARMMapping.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+const char *get_pred_mask(ARM_PredBlockMask pred_mask)
+{
+	switch (pred_mask) {
+	default:
+		assert(0 && "pred_mask not handled.");
+	case ARM_T:
+		return "T";
+	case ARM_TT:
+		return "TT";
+	case ARM_TE:
+		return "TE";
+	case ARM_TTT:
+		return "TTT";
+	case ARM_TTE:
+		return "TTE";
+	case ARM_TEE:
+		return "TEE";
+	case ARM_TET:
+		return "TET";
+	case ARM_TTTT:
+		return "TTTT";
+	case ARM_TTTE:
+		return "TTTE";
+	case ARM_TTEE:
+		return "TTEE";
+	case ARM_TTET:
+		return "TTET";
+	case ARM_TEEE:
+		return "TEEE";
+	case ARM_TEET:
+		return "TEET";
+	case ARM_TETT:
+		return "TETT";
+	case ARM_TETE:
+		return "TETE";
+	}
+}
+
+#define GET_MCLASSSYSREG_IMPL
+#include "ARMGenSystemRegister.inc"
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
+}
+
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) | (SYSm & 0xFF));
+}
+
+// lookup system registers using 8-bit SYSm value
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) | (SYSm & 0xFF));
+}
diff --git a/arch/ARM/ARMBaseInfo.h b/arch/ARM/ARMBaseInfo.h
index b7279569f..0d559024c 100644
--- a/arch/ARM/ARMBaseInfo.h
+++ b/arch/ARM/ARMBaseInfo.h
@@ -1,9 +1,8 @@
-//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
+//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
@@ -14,180 +13,239 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+#ifndef CS_ARM_BASEINFO_H
+#define CS_ARM_BASEINFO_H
 
-#ifndef CS_ARMBASEINFO_H
-#define CS_ARMBASEINFO_H
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
 
+#include "../../MCInstPrinter.h"
+#include "../../utils.h"
 #include "capstone/arm.h"
 
-// Defines symbolic names for ARM registers.  This defines a mapping from
-// register name to register number.
-//
-#define GET_REGINFO_ENUM
-#include "ARMGenRegisterInfo.inc"
+#define GET_INSTRINFO_ENUM
+#include "ARMGenInstrInfo.inc"
 
-// Enums corresponding to ARM condition codes
-// The CondCodes constants map directly to the 4-bit encoding of the
-// condition field for predicated instructions.
-typedef enum ARMCC_CondCodes { // Meaning (integer)          Meaning (floating-point)
-	ARMCC_EQ,            // Equal                      Equal
-	ARMCC_NE,            // Not equal                  Not equal, or unordered
-	ARMCC_HS,            // Carry set                  >, ==, or unordered
-	ARMCC_LO,            // Carry clear                Less than
-	ARMCC_MI,            // Minus, negative            Less than
-	ARMCC_PL,            // Plus, positive or zero     >, ==, or unordered
-	ARMCC_VS,            // Overflow                   Unordered
-	ARMCC_VC,            // No overflow                Not unordered
-	ARMCC_HI,            // Unsigned higher            Greater than, or unordered
-	ARMCC_LS,            // Unsigned lower or same     Less than or equal
-	ARMCC_GE,            // Greater than or equal      Greater than or equal
-	ARMCC_LT,            // Less than                  Less than, or unordered
-	ARMCC_GT,            // Greater than               Greater than
-	ARMCC_LE,            // Less than or equal         <, ==, or unordered
-	ARMCC_AL             // Always (unconditional)     Always (unconditional)
-} ARMCC_CondCodes;
+// System Registers
+typedef struct MClassSysReg {
+	const char *Name;
+	arm_sysop_reg sysreg;
+	uint16_t M1Encoding12;
+	uint16_t M2M3Encoding8;
+	uint16_t Encoding;
+	int FeaturesRequired[2];
+} ARMSysReg_MClassSysReg;
 
-inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
+// return true if FeaturesRequired are all present in ActiveFeatures
+static inline bool hasRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg, int ActiveFeatures)
 {
-	switch (CC) {
-		case ARMCC_EQ: return ARMCC_NE;
-		case ARMCC_NE: return ARMCC_EQ;
-		case ARMCC_HS: return ARMCC_LO;
-		case ARMCC_LO: return ARMCC_HS;
-		case ARMCC_MI: return ARMCC_PL;
-		case ARMCC_PL: return ARMCC_MI;
-		case ARMCC_VS: return ARMCC_VC;
-		case ARMCC_VC: return ARMCC_VS;
-		case ARMCC_HI: return ARMCC_LS;
-		case ARMCC_LS: return ARMCC_HI;
-		case ARMCC_GE: return ARMCC_LT;
-		case ARMCC_LT: return ARMCC_GE;
-		case ARMCC_GT: return ARMCC_LE;
-		case ARMCC_LE: return ARMCC_GT;
-		default: return ARMCC_AL;
-	}
+	return (TheReg->FeaturesRequired[0] == ActiveFeatures ||
+			TheReg->FeaturesRequired[1] == ActiveFeatures);
 }
 
-inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
+// returns true if TestFeatures are all present in FeaturesRequired
+static inline bool MClassSysReg_isInRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
+													 int TestFeatures)
 {
-	switch (CC) {
-		case ARMCC_EQ:  return "eq";
-		case ARMCC_NE:  return "ne";
-		case ARMCC_HS:  return "hs";
-		case ARMCC_LO:  return "lo";
-		case ARMCC_MI:  return "mi";
-		case ARMCC_PL:  return "pl";
-		case ARMCC_VS:  return "vs";
-		case ARMCC_VC:  return "vc";
-		case ARMCC_HI:  return "hi";
-		case ARMCC_LS:  return "ls";
-		case ARMCC_GE:  return "ge";
-		case ARMCC_LT:  return "lt";
-		case ARMCC_GT:  return "gt";
-		case ARMCC_LE:  return "le";
-		case ARMCC_AL:  return "al";
-		default: return "";
-	}
+	return (TheReg->FeaturesRequired[0] == TestFeatures ||
+			TheReg->FeaturesRequired[1] == TestFeatures);
 }
 
+#define GET_SUBTARGETINFO_ENUM
+#include "ARMGenSubtargetInfo.inc"
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
+// lookup system registers using 8-bit SYSm value
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
+// end namespace ARMSysReg
+
+// Banked Registers
+typedef struct BankedReg {
+	const char *Name;
+	arm_sysop_reg sysreg;
+	uint16_t Encoding;
+} ARMBankedReg_BankedReg;
+
+#define GET_BANKEDREG_DECL
+#define GET_MCLASSSYSREG_DECL
+#include "ARMGenSystemRegister.inc"
+
+typedef enum IMod { ARM_PROC_IE = 2, ARM_PROC_ID = 3 } ARM_PROC_IMod;
+
+typedef enum IFlags {
+	ARM_PROC_F = 1,
+	ARM_PROC_I = 2,
+	ARM_PROC_A = 4
+} ARM_PROC_IFlags;
+
 inline static const char *ARM_PROC_IFlagsToString(unsigned val)
 {
 	switch (val) {
-		case ARM_CPSFLAG_F: return "f";
-		case ARM_CPSFLAG_I: return "i";
-		case ARM_CPSFLAG_A: return "a";
-		default: return "";
+	default:
+		// llvm_unreachable("Unknown iflags operand");
+	case ARM_PROC_F:
+		return "f";
+	case ARM_PROC_I:
+		return "i";
+	case ARM_PROC_A:
+		return "a";
 	}
 }
 
 inline static const char *ARM_PROC_IModToString(unsigned val)
 {
 	switch (val) {
-		case ARM_CPSMODE_IE: return "ie";
-		case ARM_CPSMODE_ID: return "id";
-		default: return "";
+	default:
+		// llvm_unreachable("Unknown imod operand");
+		assert(0);
+	case ARM_PROC_IE:
+		return "ie";
+	case ARM_PROC_ID:
+		return "id";
 	}
 }
 
 inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
 {
-	// TODO: add details
-	switch (val + 1) {
-		default: return "BUGBUG";
-		case ARM_MB_SY:    return "sy";
-		case ARM_MB_ST:    return "st";
-		case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
-		case ARM_MB_RESERVED_12: return "#0xc";
-		case ARM_MB_ISH:   return "ish";
-		case ARM_MB_ISHST: return "ishst";
-		case ARM_MB_ISHLD: return HasV8 ?  "ishld" : "#9";
-		case ARM_MB_RESERVED_8: return "#8";
-		case ARM_MB_NSH:   return "nsh";
-		case ARM_MB_NSHST: return "nshst";
-		case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5";
-		case ARM_MB_RESERVED_4: return "#4";
-		case ARM_MB_OSH:   return "osh";
-		case ARM_MB_OSHST: return "oshst";
-		case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1";
-		case ARM_MB_RESERVED_0: return "#0";
+	switch (val) {
+	default:
+		// llvm_unreachable("Unknown memory operation");
+		assert(0);
+	case ARM_MB_SY:
+		return "sy";
+	case ARM_MB_ST:
+		return "st";
+	case ARM_MB_LD:
+		return HasV8 ? "ld" : "#0xd";
+	case ARM_MB_RESERVED_12:
+		return "#0xc";
+	case ARM_MB_ISH:
+		return "ish";
+	case ARM_MB_ISHST:
+		return "ishst";
+	case ARM_MB_ISHLD:
+		return HasV8 ? "ishld" : "#0x9";
+	case ARM_MB_RESERVED_8:
+		return "#0x8";
+	case ARM_MB_NSH:
+		return "nsh";
+	case ARM_MB_NSHST:
+		return "nshst";
+	case ARM_MB_NSHLD:
+		return HasV8 ? "nshld" : "#0x5";
+	case ARM_MB_RESERVED_4:
+		return "#0x4";
+	case ARM_MB_OSH:
+		return "osh";
+	case ARM_MB_OSHST:
+		return "oshst";
+	case ARM_MB_OSHLD:
+		return HasV8 ? "oshld" : "#0x1";
+	case ARM_MB_RESERVED_0:
+		return "#0x0";
 	}
 }
 
-enum ARM_ISB_InstSyncBOpt {
-    ARM_ISB_RESERVED_0 = 0,
-    ARM_ISB_RESERVED_1 = 1,
-    ARM_ISB_RESERVED_2 = 2,
-    ARM_ISB_RESERVED_3 = 3,
-    ARM_ISB_RESERVED_4 = 4,
-    ARM_ISB_RESERVED_5 = 5,
-    ARM_ISB_RESERVED_6 = 6,
-    ARM_ISB_RESERVED_7 = 7,
-    ARM_ISB_RESERVED_8 = 8,
-    ARM_ISB_RESERVED_9 = 9,
-    ARM_ISB_RESERVED_10 = 10,
-    ARM_ISB_RESERVED_11 = 11,
-    ARM_ISB_RESERVED_12 = 12,
-    ARM_ISB_RESERVED_13 = 13,
-    ARM_ISB_RESERVED_14 = 14,
-    ARM_ISB_SY = 15
-};
+typedef enum TraceSyncBOpt { ARM_TSB_CSYNC = 0 } ARM_TSB_TraceSyncBOpt;
+
+inline static const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
+{
+	switch (val) {
+	default:
+		// llvm_unreachable("Unknown trace synchronization barrier operation");
+		assert(0);
+	case ARM_TSB_CSYNC:
+		return "csync";
+	}
+}
+
+typedef enum InstSyncBOpt {
+	ARM_ISB_RESERVED_0 = 0,
+	ARM_ISB_RESERVED_1 = 1,
+	ARM_ISB_RESERVED_2 = 2,
+	ARM_ISB_RESERVED_3 = 3,
+	ARM_ISB_RESERVED_4 = 4,
+	ARM_ISB_RESERVED_5 = 5,
+	ARM_ISB_RESERVED_6 = 6,
+	ARM_ISB_RESERVED_7 = 7,
+	ARM_ISB_RESERVED_8 = 8,
+	ARM_ISB_RESERVED_9 = 9,
+	ARM_ISB_RESERVED_10 = 10,
+	ARM_ISB_RESERVED_11 = 11,
+	ARM_ISB_RESERVED_12 = 12,
+	ARM_ISB_RESERVED_13 = 13,
+	ARM_ISB_RESERVED_14 = 14,
+	ARM_ISB_SY = 15
+} ARM_ISB_InstSyncBOpt;
 
 inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
 {
 	switch (val) {
-		default: // never reach
-		case ARM_ISB_RESERVED_0:  return "#0x0";
-		case ARM_ISB_RESERVED_1:  return "#0x1";
-		case ARM_ISB_RESERVED_2:  return "#0x2";
-		case ARM_ISB_RESERVED_3:  return "#0x3";
-		case ARM_ISB_RESERVED_4:  return "#0x4";
-		case ARM_ISB_RESERVED_5:  return "#0x5";
-		case ARM_ISB_RESERVED_6:  return "#0x6";
-		case ARM_ISB_RESERVED_7:  return "#0x7";
-		case ARM_ISB_RESERVED_8:  return "#0x8";
-		case ARM_ISB_RESERVED_9:  return "#0x9";
-		case ARM_ISB_RESERVED_10: return "#0xa";
-		case ARM_ISB_RESERVED_11: return "#0xb";
-		case ARM_ISB_RESERVED_12: return "#0xc";
-		case ARM_ISB_RESERVED_13: return "#0xd";
-		case ARM_ISB_RESERVED_14: return "#0xe";
-		case ARM_ISB_SY:          return "sy";
+	default:
+		// llvm_unreachable("Unknown memory operation");
+		assert(0);
+	case ARM_ISB_RESERVED_0:
+		return "#0x0";
+	case ARM_ISB_RESERVED_1:
+		return "#0x1";
+	case ARM_ISB_RESERVED_2:
+		return "#0x2";
+	case ARM_ISB_RESERVED_3:
+		return "#0x3";
+	case ARM_ISB_RESERVED_4:
+		return "#0x4";
+	case ARM_ISB_RESERVED_5:
+		return "#0x5";
+	case ARM_ISB_RESERVED_6:
+		return "#0x6";
+	case ARM_ISB_RESERVED_7:
+		return "#0x7";
+	case ARM_ISB_RESERVED_8:
+		return "#0x8";
+	case ARM_ISB_RESERVED_9:
+		return "#0x9";
+	case ARM_ISB_RESERVED_10:
+		return "#0xa";
+	case ARM_ISB_RESERVED_11:
+		return "#0xb";
+	case ARM_ISB_RESERVED_12:
+		return "#0xc";
+	case ARM_ISB_RESERVED_13:
+		return "#0xd";
+	case ARM_ISB_RESERVED_14:
+		return "#0xe";
+	case ARM_ISB_SY:
+		return "sy";
 	}
 }
 
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
+
 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
 ///
 static inline bool isARMLowRegister(unsigned Reg)
 {
-	//using namespace ARM;
+
 	switch (Reg) {
-		case ARM_R0:  case ARM_R1:  case ARM_R2:  case ARM_R3:
-		case ARM_R4:  case ARM_R5:  case ARM_R6:  case ARM_R7:
-			return true;
-		default:
-			return false;
+	case ARM_R0:
+	case ARM_R1:
+	case ARM_R2:
+	case ARM_R3:
+	case ARM_R4:
+	case ARM_R5:
+	case ARM_R6:
+	case ARM_R7:
+		return true;
+	default:
+		return false;
 	}
 }
 
@@ -195,99 +253,150 @@ static inline bool isARMLowRegister(unsigned Reg)
 /// instruction info tracks.
 ///
 /// ARM Index Modes
-enum ARMII_IndexMode {
-	ARMII_IndexModeNone  = 0,
-	ARMII_IndexModePre   = 1,
-	ARMII_IndexModePost  = 2,
-	ARMII_IndexModeUpd   = 3
-};
+typedef enum IndexMode {
+	ARMII_IndexModeNone = 0,
+	ARMII_IndexModePre = 1,
+	ARMII_IndexModePost = 2,
+	ARMII_IndexModeUpd = 3
+} ARMII_IndexMode;
 
 /// ARM Addressing Modes
-typedef enum ARMII_AddrMode {
-	ARMII_AddrModeNone    = 0,
-	ARMII_AddrMode1       = 1,
-	ARMII_AddrMode2       = 2,
-	ARMII_AddrMode3       = 3,
-	ARMII_AddrMode4       = 4,
-	ARMII_AddrMode5       = 5,
-	ARMII_AddrMode6       = 6,
-	ARMII_AddrModeT1_1    = 7,
-	ARMII_AddrModeT1_2    = 8,
-	ARMII_AddrModeT1_4    = 9,
-	ARMII_AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
-	ARMII_AddrModeT2_i12  = 11,
-	ARMII_AddrModeT2_i8   = 12,
-	ARMII_AddrModeT2_so   = 13,
-	ARMII_AddrModeT2_pc   = 14, // +/- i12 for pc relative data
-	ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
-	ARMII_AddrMode_i12    = 16
+typedef enum AddrMode {
+	ARMII_AddrModeNone = 0,
+	ARMII_AddrMode1 = 1,
+	ARMII_AddrMode2 = 2,
+	ARMII_AddrMode3 = 3,
+	ARMII_AddrMode4 = 4,
+	ARMII_AddrMode5 = 5,
+	ARMII_AddrMode6 = 6,
+	ARMII_AddrModeT1_1 = 7,
+	ARMII_AddrModeT1_2 = 8,
+	ARMII_AddrModeT1_4 = 9,
+	ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
+	ARMII_AddrModeT2_i12 = 11,
+	ARMII_AddrModeT2_i8 = 12,	 // +/- i8
+	ARMII_AddrModeT2_i8pos = 13, // + i8
+	ARMII_AddrModeT2_i8neg = 14, // - i8
+	ARMII_AddrModeT2_so = 15,
+	ARMII_AddrModeT2_pc = 16,	// +/- i12 for pc relative data
+	ARMII_AddrModeT2_i8s4 = 17, // i8 * 4
+	ARMII_AddrMode_i12 = 18,
+	ARMII_AddrMode5FP16 = 19,	 // i8 * 2
+	ARMII_AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst
+	ARMII_AddrModeT2_i7s4 = 21,	 // i7 * 4
+	ARMII_AddrModeT2_i7s2 = 22,	 // i7 * 2
+	ARMII_AddrModeT2_i7 = 23,	 // i7 * 1
 } ARMII_AddrMode;
 
 inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
 {
 	switch (addrmode) {
-		case ARMII_AddrModeNone:    return "AddrModeNone";
-		case ARMII_AddrMode1:       return "AddrMode1";
-		case ARMII_AddrMode2:       return "AddrMode2";
-		case ARMII_AddrMode3:       return "AddrMode3";
-		case ARMII_AddrMode4:       return "AddrMode4";
-		case ARMII_AddrMode5:       return "AddrMode5";
-		case ARMII_AddrMode6:       return "AddrMode6";
-		case ARMII_AddrModeT1_1:    return "AddrModeT1_1";
-		case ARMII_AddrModeT1_2:    return "AddrModeT1_2";
-		case ARMII_AddrModeT1_4:    return "AddrModeT1_4";
-		case ARMII_AddrModeT1_s:    return "AddrModeT1_s";
-		case ARMII_AddrModeT2_i12:  return "AddrModeT2_i12";
-		case ARMII_AddrModeT2_i8:   return "AddrModeT2_i8";
-		case ARMII_AddrModeT2_so:   return "AddrModeT2_so";
-		case ARMII_AddrModeT2_pc:   return "AddrModeT2_pc";
-		case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
-		case ARMII_AddrMode_i12:    return "AddrMode_i12";
+	case ARMII_AddrModeNone:
+		return "AddrModeNone";
+	case ARMII_AddrMode1:
+		return "AddrMode1";
+	case ARMII_AddrMode2:
+		return "AddrMode2";
+	case ARMII_AddrMode3:
+		return "AddrMode3";
+	case ARMII_AddrMode4:
+		return "AddrMode4";
+	case ARMII_AddrMode5:
+		return "AddrMode5";
+	case ARMII_AddrMode5FP16:
+		return "AddrMode5FP16";
+	case ARMII_AddrMode6:
+		return "AddrMode6";
+	case ARMII_AddrModeT1_1:
+		return "AddrModeT1_1";
+	case ARMII_AddrModeT1_2:
+		return "AddrModeT1_2";
+	case ARMII_AddrModeT1_4:
+		return "AddrModeT1_4";
+	case ARMII_AddrModeT1_s:
+		return "AddrModeT1_s";
+	case ARMII_AddrModeT2_i12:
+		return "AddrModeT2_i12";
+	case ARMII_AddrModeT2_i8:
+		return "AddrModeT2_i8";
+	case ARMII_AddrModeT2_i8pos:
+		return "AddrModeT2_i8pos";
+	case ARMII_AddrModeT2_i8neg:
+		return "AddrModeT2_i8neg";
+	case ARMII_AddrModeT2_so:
+		return "AddrModeT2_so";
+	case ARMII_AddrModeT2_pc:
+		return "AddrModeT2_pc";
+	case ARMII_AddrModeT2_i8s4:
+		return "AddrModeT2_i8s4";
+	case ARMII_AddrMode_i12:
+		return "AddrMode_i12";
+	case ARMII_AddrModeT2_ldrex:
+		return "AddrModeT2_ldrex";
+	case ARMII_AddrModeT2_i7s4:
+		return "AddrModeT2_i7s4";
+	case ARMII_AddrModeT2_i7s2:
+		return "AddrModeT2_i7s2";
+	case ARMII_AddrModeT2_i7:
+		return "AddrModeT2_i7";
 	}
 }
 
 /// Target Operand Flag enum.
-enum ARMII_TOF {
+typedef enum TOF {
 	//===------------------------------------------------------------------===//
 	// ARM Specific MachineOperand flags.
 
-	ARMII_MO_NO_FLAG,
+	ARMII_MO_NO_FLAG = 0,
 
 	/// MO_LO16 - On a symbol operand, this represents a relocation containing
 	/// lower 16 bit of the address. Used only via movw instruction.
-	ARMII_MO_LO16,
+	ARMII_MO_LO16 = 0x1,
 
 	/// MO_HI16 - On a symbol operand, this represents a relocation containing
 	/// higher 16 bit of the address. Used only via movt instruction.
-	ARMII_MO_HI16,
+	ARMII_MO_HI16 = 0x2,
 
-	/// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
-	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
-	/// i.e. "FOO$non_lazy_ptr".
-	/// Used only via movw instruction.
-	ARMII_MO_LO16_NONLAZY,
+	/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
+	/// just that part of the flag set.
+	ARMII_MO_OPTION_MASK = 0x3,
 
-	/// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
-	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
-	/// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
-	ARMII_MO_HI16_NONLAZY,
+	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
+	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
+	/// stub symbols on windows.
+	ARMII_MO_COFFSTUB = 0x4,
 
-	/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
-	/// relocation containing lower 16 bit of the PC relative address of the
-	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
-	/// Used only via movw instruction.
-	ARMII_MO_LO16_NONLAZY_PIC,
+	/// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
+	ARMII_MO_GOT = 0x8,
 
-	/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
-	/// relocation containing lower 16 bit of the PC relative address of the
-	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
-	/// Used only via movt instruction.
-	ARMII_MO_HI16_NONLAZY_PIC,
+	/// MO_SBREL - On a symbol operand, this represents a static base relative
+	/// relocation. Used in movw and movt instructions.
+	ARMII_MO_SBREL = 0x10,
 
-	/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
-	/// call operand.
-	ARMII_MO_PLT
-};
+	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
+	/// to the symbol is for an import stub.  This is used for DLL import
+	/// storage class indication on Windows.
+	ARMII_MO_DLLIMPORT = 0x20,
+
+	/// MO_SECREL - On a symbol operand this indicates that the immediate is
+	/// the offset from beginning of section.
+	///
+	/// This is the TLS offset for the COFF/Windows TLS mechanism.
+	ARMII_MO_SECREL = 0x40,
+
+	/// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
+	/// represents a symbol which, if indirect, will get special Darwin mangling
+	/// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
+	/// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
+	/// example).
+	ARMII_MO_NONLAZY = 0x80,
+
+	// It's undefined behaviour if an enum overflows the range between its
+	// smallest and largest values, but since these are |ed together, it can
+	// happen. Put a sentinel in (values of this enum are stored as "unsigned
+	// char").
+	ARMII_MO_UNUSED_MAXIMUM = 0xff
+} ARMII_TOF;
 
 enum {
 	//===------------------------------------------------------------------===//
@@ -295,110 +404,136 @@ enum {
 
 	//===------------------------------------------------------------------===//
 	// This four-bit field describes the addressing mode used.
-	ARMII_AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+	ARMII_AddrModeMask =
+		0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
 
 	// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
 	// and store ops only.  Generic "updating" flag is used for ld/st multiple.
 	// The index mode enums are declared in ARMBaseInfo.h
 	ARMII_IndexModeShift = 5,
-	ARMII_IndexModeMask  = 3 << ARMII_IndexModeShift,
+	ARMII_IndexModeMask = 3 << ARMII_IndexModeShift,
 
 	//===------------------------------------------------------------------===//
 	// Instruction encoding formats.
 	//
-	ARMII_FormShift     = 7,
-	ARMII_FormMask      = 0x3f << ARMII_FormShift,
+	ARMII_FormShift = 7,
+	ARMII_FormMask = 0x3f << ARMII_FormShift,
 
 	// Pseudo instructions
-	ARMII_Pseudo        = 0  << ARMII_FormShift,
+	ARMII_Pseudo = 0 << ARMII_FormShift,
 
 	// Multiply instructions
-	ARMII_MulFrm        = 1  << ARMII_FormShift,
+	ARMII_MulFrm = 1 << ARMII_FormShift,
 
 	// Branch instructions
-	ARMII_BrFrm         = 2  << ARMII_FormShift,
-	ARMII_BrMiscFrm     = 3  << ARMII_FormShift,
+	ARMII_BrFrm = 2 << ARMII_FormShift,
+	ARMII_BrMiscFrm = 3 << ARMII_FormShift,
 
 	// Data Processing instructions
-	ARMII_DPFrm         = 4  << ARMII_FormShift,
-	ARMII_DPSoRegFrm    = 5  << ARMII_FormShift,
+	ARMII_DPFrm = 4 << ARMII_FormShift,
+	ARMII_DPSoRegFrm = 5 << ARMII_FormShift,
 
 	// Load and Store
-	ARMII_LdFrm         = 6  << ARMII_FormShift,
-	ARMII_StFrm         = 7  << ARMII_FormShift,
-	ARMII_LdMiscFrm     = 8  << ARMII_FormShift,
-	ARMII_StMiscFrm     = 9  << ARMII_FormShift,
-	ARMII_LdStMulFrm    = 10 << ARMII_FormShift,
+	ARMII_LdFrm = 6 << ARMII_FormShift,
+	ARMII_StFrm = 7 << ARMII_FormShift,
+	ARMII_LdMiscFrm = 8 << ARMII_FormShift,
+	ARMII_StMiscFrm = 9 << ARMII_FormShift,
+	ARMII_LdStMulFrm = 10 << ARMII_FormShift,
 
-	ARMII_LdStExFrm     = 11 << ARMII_FormShift,
+	ARMII_LdStExFrm = 11 << ARMII_FormShift,
 
 	// Miscellaneous arithmetic instructions
-	ARMII_ArithMiscFrm  = 12 << ARMII_FormShift,
-	ARMII_SatFrm        = 13 << ARMII_FormShift,
+	ARMII_ArithMiscFrm = 12 << ARMII_FormShift,
+	ARMII_SatFrm = 13 << ARMII_FormShift,
 
 	// Extend instructions
-	ARMII_ExtFrm        = 14 << ARMII_FormShift,
+	ARMII_ExtFrm = 14 << ARMII_FormShift,
 
 	// VFP formats
-	ARMII_VFPUnaryFrm   = 15 << ARMII_FormShift,
-	ARMII_VFPBinaryFrm  = 16 << ARMII_FormShift,
-	ARMII_VFPConv1Frm   = 17 << ARMII_FormShift,
-	ARMII_VFPConv2Frm   = 18 << ARMII_FormShift,
-	ARMII_VFPConv3Frm   = 19 << ARMII_FormShift,
-	ARMII_VFPConv4Frm   = 20 << ARMII_FormShift,
-	ARMII_VFPConv5Frm   = 21 << ARMII_FormShift,
-	ARMII_VFPLdStFrm    = 22 << ARMII_FormShift,
+	ARMII_VFPUnaryFrm = 15 << ARMII_FormShift,
+	ARMII_VFPBinaryFrm = 16 << ARMII_FormShift,
+	ARMII_VFPConv1Frm = 17 << ARMII_FormShift,
+	ARMII_VFPConv2Frm = 18 << ARMII_FormShift,
+	ARMII_VFPConv3Frm = 19 << ARMII_FormShift,
+	ARMII_VFPConv4Frm = 20 << ARMII_FormShift,
+	ARMII_VFPConv5Frm = 21 << ARMII_FormShift,
+	ARMII_VFPLdStFrm = 22 << ARMII_FormShift,
 	ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
-	ARMII_VFPMiscFrm    = 24 << ARMII_FormShift,
+	ARMII_VFPMiscFrm = 24 << ARMII_FormShift,
 
 	// Thumb format
-	ARMII_ThumbFrm      = 25 << ARMII_FormShift,
+	ARMII_ThumbFrm = 25 << ARMII_FormShift,
 
 	// Miscelleaneous format
-	ARMII_MiscFrm       = 26 << ARMII_FormShift,
+	ARMII_MiscFrm = 26 << ARMII_FormShift,
 
 	// NEON formats
-	ARMII_NGetLnFrm     = 27 << ARMII_FormShift,
-	ARMII_NSetLnFrm     = 28 << ARMII_FormShift,
-	ARMII_NDupFrm       = 29 << ARMII_FormShift,
-	ARMII_NLdStFrm      = 30 << ARMII_FormShift,
-	ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
-	ARMII_N2RegFrm      = 32 << ARMII_FormShift,
-	ARMII_NVCVTFrm      = 33 << ARMII_FormShift,
-	ARMII_NVDupLnFrm    = 34 << ARMII_FormShift,
-	ARMII_N2RegVShLFrm  = 35 << ARMII_FormShift,
-	ARMII_N2RegVShRFrm  = 36 << ARMII_FormShift,
-	ARMII_N3RegFrm      = 37 << ARMII_FormShift,
-	ARMII_N3RegVShFrm   = 38 << ARMII_FormShift,
-	ARMII_NVExtFrm      = 39 << ARMII_FormShift,
-	ARMII_NVMulSLFrm    = 40 << ARMII_FormShift,
-	ARMII_NVTBLFrm      = 41 << ARMII_FormShift,
+	ARMII_NGetLnFrm = 27 << ARMII_FormShift,
+	ARMII_NSetLnFrm = 28 << ARMII_FormShift,
+	ARMII_NDupFrm = 29 << ARMII_FormShift,
+	ARMII_NLdStFrm = 30 << ARMII_FormShift,
+	ARMII_N1RegModImmFrm = 31 << ARMII_FormShift,
+	ARMII_N2RegFrm = 32 << ARMII_FormShift,
+	ARMII_NVCVTFrm = 33 << ARMII_FormShift,
+	ARMII_NVDupLnFrm = 34 << ARMII_FormShift,
+	ARMII_N2RegVShLFrm = 35 << ARMII_FormShift,
+	ARMII_N2RegVShRFrm = 36 << ARMII_FormShift,
+	ARMII_N3RegFrm = 37 << ARMII_FormShift,
+	ARMII_N3RegVShFrm = 38 << ARMII_FormShift,
+	ARMII_NVExtFrm = 39 << ARMII_FormShift,
+	ARMII_NVMulSLFrm = 40 << ARMII_FormShift,
+	ARMII_NVTBLFrm = 41 << ARMII_FormShift,
+	ARMII_N3RegCplxFrm = 43 << ARMII_FormShift,
 
 	//===------------------------------------------------------------------===//
 	// Misc flags.
 
 	// UnaryDP - Indicates this is a unary data processing instruction, i.e.
 	// it doesn't have a Rn operand.
-	ARMII_UnaryDP       = 1 << 13,
+	ARMII_UnaryDP = 1 << 13,
 
 	// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
 	// a 16-bit Thumb instruction if certain conditions are met.
-	ARMII_Xform16Bit    = 1 << 14,
+	ARMII_Xform16Bit = 1 << 14,
 
 	// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
 	// instruction. Used by the parser to determine whether to require the 'S'
 	// suffix on the mnemonic (when not in an IT block) or preclude it (when
 	// in an IT block).
-	ARMII_ThumbArithFlagSetting = 1 << 18,
+	ARMII_ThumbArithFlagSetting = 1 << 19,
+
+	// Whether an instruction can be included in an MVE tail-predicated loop,
+	// though extra validity checks may need to be performed too.
+	ARMII_ValidForTailPredication = 1 << 20,
+
+	// Whether an instruction writes to the top/bottom half of a vector element
+	// and leaves the other half untouched.
+	ARMII_RetainsPreviousHalfElement = 1 << 21,
+
+	// Whether the instruction produces a scalar result from vector operands.
+	ARMII_HorizontalReduction = 1 << 22,
+
+	// Whether this instruction produces a vector result that is larger than
+	// its input, typically reading from the top/bottom halves of the input(s).
+	ARMII_DoubleWidthResult = 1 << 23,
+
+	// The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32
+	// and 11 = i64. This is the largest type if multiple are present, so a
+	// MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are
+	// some caveats so cannot be used blindly, such as exchanging VMLADAVA's and
+	// complex instructions, which may use different input lanes.
+	ARMII_VecSizeShift = 24,
+	ARMII_VecSize = 3 << ARMII_VecSizeShift,
 
 	//===------------------------------------------------------------------===//
 	// Code domain.
-	ARMII_DomainShift   = 15,
-	ARMII_DomainMask    = 7 << ARMII_DomainShift,
+	ARMII_DomainShift = 15,
+	ARMII_DomainMask = 15 << ARMII_DomainShift,
 	ARMII_DomainGeneral = 0 << ARMII_DomainShift,
-	ARMII_DomainVFP     = 1 << ARMII_DomainShift,
-	ARMII_DomainNEON    = 2 << ARMII_DomainShift,
-	ARMII_DomainNEONA8  = 4 << ARMII_DomainShift,
+	ARMII_DomainVFP = 1 << ARMII_DomainShift,
+	ARMII_DomainNEON = 2 << ARMII_DomainShift,
+	ARMII_DomainNEONA8 = 4 << ARMII_DomainShift,
+	ARMII_DomainMVE = 8 << ARMII_DomainShift,
 
 	//===------------------------------------------------------------------===//
 	// Field shifts - such shifts are used to set field while generating
@@ -408,79 +543,28 @@ enum {
 	// takes shape and the ARMCodeEmitter.cpp bits go away.
 	ARMII_ShiftTypeShift = 4,
 
-	ARMII_M_BitShift     = 5,
-	ARMII_ShiftImmShift  = 5,
-	ARMII_ShiftShift     = 7,
-	ARMII_N_BitShift     = 7,
-	ARMII_ImmHiShift     = 8,
-	ARMII_SoRotImmShift  = 8,
-	ARMII_RegRsShift     = 8,
+	ARMII_M_BitShift = 5,
+	ARMII_ShiftImmShift = 5,
+	ARMII_ShiftShift = 7,
+	ARMII_N_BitShift = 7,
+	ARMII_ImmHiShift = 8,
+	ARMII_SoRotImmShift = 8,
+	ARMII_RegRsShift = 8,
 	ARMII_ExtRotImmShift = 10,
-	ARMII_RegRdLoShift   = 12,
-	ARMII_RegRdShift     = 12,
-	ARMII_RegRdHiShift   = 16,
-	ARMII_RegRnShift     = 16,
-	ARMII_S_BitShift     = 20,
-	ARMII_W_BitShift     = 21,
+	ARMII_RegRdLoShift = 12,
+	ARMII_RegRdShift = 12,
+	ARMII_RegRdHiShift = 16,
+	ARMII_RegRnShift = 16,
+	ARMII_S_BitShift = 20,
+	ARMII_W_BitShift = 21,
 	ARMII_AM3_I_BitShift = 22,
-	ARMII_D_BitShift     = 22,
-	ARMII_U_BitShift     = 23,
-	ARMII_P_BitShift     = 24,
-	ARMII_I_BitShift     = 25,
-	ARMII_CondShift      = 28
+	ARMII_D_BitShift = 22,
+	ARMII_U_BitShift = 23,
+	ARMII_P_BitShift = 24,
+	ARMII_I_BitShift = 25,
+	ARMII_CondShift = 28
 };
 
-typedef struct MClassSysReg {
-	const char *Name;
-	arm_sysreg sysreg;
-	uint16_t M1Encoding12;
-	uint16_t M2M3Encoding8;
-	uint16_t Encoding;
-	int FeaturesRequired[2];	// 2 is enough for MClassSysRegsList
-} MClassSysReg;
+const char *get_pred_mask(ARM_PredBlockMask pred_mask);
 
-enum TraceSyncBOpt {
-	CSYNC = 0
-};
-
-const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
-const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
-
-// returns APSR with _<bits> qualifier.
-// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
-static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
-{
-	return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF));
-}
-
-static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
-{
-	return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF));
-}
-
-// returns true if TestFeatures are all present in FeaturesRequired
-static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures)
-{
-	return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures);
-}
-
-// lookup system register using 12-bit SYSm value.
-// Note: the search is uniqued using M1 mask
-static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
-{
-  return lookupMClassSysRegByM1Encoding12(SYSm);
-}
-
-static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
-{
-	switch (val) {
-		default:
-			// llvm_unreachable("Unknown trace synchronization barrier operation");
-			return NULL;
-
-		case CSYNC:
-			return "csync";
-	}
-}
-
-#endif
+#endif // CS_ARM_BASEINFO_H
diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c
index b2e5723af..e338e5a2b 100644
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@@ -1,613 +1,780 @@
-//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifdef CAPSTONE_HAS_ARM
-
-#include <stdio.h>
-#include <string.h>
-#include <stdlib.h>
 #include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
-#include "ARMAddressingModes.h"
-#include "ARMBaseInfo.h"
+#include "../../LEB128.h"
+#include "../../MCDisassembler.h"
 #include "../../MCFixedLenDisassembler.h"
 #include "../../MCInst.h"
 #include "../../MCInstrDesc.h"
 #include "../../MCRegisterInfo.h"
-#include "../../LEB128.h"
-#include "../../MCDisassembler.h"
+#include "../../MathExtras.h"
 #include "../../cs_priv.h"
 #include "../../utils.h"
-
-#include "ARMDisassembler.h"
+#include "ARMLinkage.h"
+#include "ARMAddressingModes.h"
+#include "ARMBaseInfo.h"
+#include "ARMDisassemblerExtension.h"
 #include "ARMMapping.h"
 
-#define GET_SUBTARGETINFO_ENUM
-#include "ARMGenSubtargetInfo.inc"
-
 #define GET_INSTRINFO_MC_DESC
 #include "ARMGenInstrInfo.inc"
 
-#define GET_INSTRINFO_ENUM
-#include "ARMGenInstrInfo.inc"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
 
-static bool ITStatus_push_back(ARM_ITStatus *it, char v)
-{
-	if (it->size >= sizeof(it->ITStates)) {
-		// TODO: consider warning user.
-		it->size = 0;
-	}
-	it->ITStates[it->size] = v;
-	it->size++;
-
-	return true;
-}
-
-// Returns true if the current instruction is in an IT block
-static bool ITStatus_instrInITBlock(ARM_ITStatus *it)
-{
-	//return !ITStates.empty();
-	return (it->size > 0);
-}
-
-// Returns true if current instruction is the last instruction in an IT block
-static bool ITStatus_instrLastInITBlock(ARM_ITStatus *it)
-{
-	return (it->size == 1);
-}
+#define DEBUG_TYPE "arm-disassembler"
 
 // Handles the condition code status of instructions in IT blocks
+;
 
-// Returns the condition code for instruction in IT block
-static unsigned ITStatus_getITCC(ARM_ITStatus *it)
-{
-	unsigned CC = ARMCC_AL;
+;
 
-	if (ITStatus_instrInITBlock(it))
-		//CC = ITStates.back();
-		CC = it->ITStates[it->size-1];
+/// ARM disassembler for all ARM platforms.;
+static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
+							MCInst *MI, uint16_t *Size, uint64_t Address,
+							void *Info);
+DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
+							   MCInst *MI, uint16_t *Size, uint64_t Address,
+							   void *Info);
+DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t ByteLen,
+								 MCInst *MI, uint16_t *Size, uint64_t Address,
+								 void *Info);
+DecodeStatus AddThumbPredicate(MCInst *);
+void UpdateThumbVFPPredicate(DecodeStatus, MCInst *);
+;
 
-	return CC;
-}
-
-// Advances the IT block state to the next T or E
-static void ITStatus_advanceITState(ARM_ITStatus *it)
-{
-	//ITStates.pop_back();
-	it->size--;
-}
-
-// Called when decoding an IT instruction. Sets the IT state for the following
-// instructions that for the IT block. Firstcond and Mask correspond to the 
-// fields in the IT instruction encoding.
-static void ITStatus_setITState(ARM_ITStatus *it, char Firstcond, char Mask)
-{
-	// (3 - the number of trailing zeros) is the number of then / else.
-	unsigned CondBit0 = Firstcond & 1;
-	unsigned NumTZ = CountTrailingZeros_32(Mask);
-	unsigned char CCBits = (unsigned char)Firstcond & 0xf;
-	unsigned Pos;
-
-	//assert(NumTZ <= 3 && "Invalid IT mask!");
-	// push condition codes onto the stack the correct order for the pops
-	for (Pos = NumTZ + 1; Pos <= 3; ++Pos) {
-		bool T = ((Mask >> Pos) & 1) == (int)CondBit0;
-
-		if (T)
-			ITStatus_push_back(it, CCBits);
-		else
-			ITStatus_push_back(it, CCBits ^ 1);
-	}
-
-	ITStatus_push_back(it, CCBits);
-}
-
-/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
-
-static bool Check(DecodeStatus *Out, DecodeStatus In)
-{
-	switch (In) {
-		case MCDisassembler_Success:
-			// Out stays the same.
-			return true;
-		case MCDisassembler_SoftFail:
-			*Out = In;
-			return true;
-		case MCDisassembler_Fail:
-			*Out = In;
-			return false;
-		default:	// never reached
-			return false;
-	}
-}
+// end anonymous namespace
 
 // Forward declare these because the autogenerated code will reference them.
 // Definitions are further down.
 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, const void *Decoder);
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo,
+												uint64_t Address,
+												const void *Decoder);
+static DecodeStatus
+DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst, unsigned RegNo,
+										uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeGPRnospRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
+												   uint64_t Address,
+												   const void *Decoder);
+static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo,
+												 uint64_t Address,
+												 const void *Decoder);
+static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst,
+													 unsigned RegNo,
+													 uint64_t Address,
+													 const void *Decoder);
 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
+											uint64_t Address,
+											const void *Decoder);
 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
+											 uint64_t Address,
+											 const void *Decoder);
 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
+											uint64_t Address,
+											const void *Decoder);
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, const void *Decoder);
-static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst,
-		unsigned Insn, uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst,unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst * Inst,
-		unsigned Insn, uint64_t Adddress, const void *Decoder);
-static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst,unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst,unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder);
-static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder);
-static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder);
-static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder);
-static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst,unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst,unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst,unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder);
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo,
+												   uint64_t Address,
+												   const void *Decoder);
+static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder);
 static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder);
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
+												uint64_t Address,
+												const void *Decoder);
+static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo,
+												   uint64_t Address,
+												   const void *Decoder);
 
-// Hacky: enable all features for disassembler
-bool ARM_getFeatureBits(unsigned int mode, unsigned int feature)
-{
-	if ((mode & CS_MODE_V8) == 0) {
-		// not V8 mode
-		if (feature == ARM_HasV8Ops || feature == ARM_HasV8_1aOps ||
-			feature == ARM_HasV8_4aOps || feature == ARM_HasV8_3aOps)
-			// HasV8MBaselineOps
-			return false;
-	} else {
-		if (feature == ARM_FeatureVFPOnlySP)
-			return false;
-	}
+static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
+									   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
 
-	if ((mode & CS_MODE_MCLASS) == 0) {
-		if (feature == ARM_FeatureMClass)
-			return false;
-	}
+static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Insn,
+											  uint64_t Address,
+											  const void *Decoder);
+static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
+												  uint64_t Address,
+												  const void *Decoder);
+static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Insn,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeTSBInstruction(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Insn,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Insn,
+										  uint64_t Address,
+										  const void *Decoder);
 
-	if ((mode & CS_MODE_THUMB) == 0) {
-		// not Thumb
-		if (feature == ARM_FeatureThumb2 || feature == ARM_ModeThumb)
-			return false;
-		// FIXME: what mode enables D16?
-		if (feature == ARM_FeatureD16)
-			return false;
-	} else {
-		// Thumb
-		if (feature == ARM_FeatureD16)
-			return false;
-	}
+static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
+														  unsigned Insn,
+														  uint64_t Adddress,
+														  const void *Decoder);
+static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
+											  uint64_t Address,
+											  const void *Decoder);
+static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeT2HintSpaceInstruction(MCInst *Inst, unsigned Insn,
+												 uint64_t Address,
+												 const void *Decoder);
+static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Val,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Val,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Val,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Val,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Val,
+												uint64_t Address,
+												const void *Decoder);
+static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Val,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Val,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
+									 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn,
+										uint64_t Address, const void *Decoder);
+#define DECLARE_DecodeMveAddrModeQ(shift)                                      \
+	static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)(                     \
+		MCInst * Inst, unsigned Insn, uint64_t Address, const void *Decoder);
+DECLARE_DecodeMveAddrModeQ(2) DECLARE_DecodeMveAddrModeQ(3)
 
-	if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0)
-		return false;
+	static DecodeStatus
+	DecodeCoprocessor(MCInst *Inst, unsigned Insn, uint64_t Address,
+					  const void *Decoder);
+static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Insn,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
+												uint64_t Address,
+												const void *Decoder);
+static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder);
+static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
+									uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
+										uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
+									uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
+									uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
+									uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
+									uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder);
+static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder);
+static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address,
+							   const void *Decoder);
+static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address,
+								const void *Decoder);
+static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address,
+								const void *Decoder);
+static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst,
+													   unsigned Val,
+													   uint64_t Address,
+													   const void *Decoder);
 
-	// we support everything
-	return true;
-}
+static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
+											 uint64_t Address,
+											 const void *Decoder);
+static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
+									  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Val,
+									  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
+									 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
+									  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder);
+static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
+									  uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address,
+								   const void *Decoder);
+static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address,
+								   const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val,
+												uint64_t Address,
+												const void *Decoder);
+static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address,
+								 const void *Decoder);
+#define DECLARE_DecodeT2Imm7(shift)                                            \
+	static DecodeStatus CONCAT(DecodeT2Imm7, shift)(                           \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+DECLARE_DecodeT2Imm7(0) DECLARE_DecodeT2Imm7(1) DECLARE_DecodeT2Imm7(2)
+
+	static DecodeStatus
+	DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address,
+						 const void *Decoder);
+#define DECLARE_DecodeTAddrModeImm7(shift)                                     \
+	static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+DECLARE_DecodeTAddrModeImm7(0) DECLARE_DecodeTAddrModeImm7(1)
+
+#define DECLARE_DecodeT2AddrModeImm7(shift, WriteBack)                         \
+	static DecodeStatus CONCAT(DecodeT2AddrModeImm7,                           \
+							   CONCAT(shift, WriteBack))(                      \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+	DECLARE_DecodeT2AddrModeImm7(0, 0) DECLARE_DecodeT2AddrModeImm7(1, 0)
+		DECLARE_DecodeT2AddrModeImm7(2, 0) DECLARE_DecodeT2AddrModeImm7(0, 1)
+			DECLARE_DecodeT2AddrModeImm7(1, 1)
+				DECLARE_DecodeT2AddrModeImm7(2, 1)
+
+					static DecodeStatus
+	DecodeThumbAddSPImm(MCInst *Inst, uint16_t Val, uint64_t Address,
+						const void *Decoder);
+static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
+										uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
+								   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Val,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address,
+								  const void *Decoder);
+static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val,
+												uint64_t Address,
+												const void *Decoder);
+static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeIT(MCInst *Inst, unsigned Val, uint64_t Address,
+							 const void *Decoder);
+static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
+											   uint64_t Address,
+											   const void *Decoder);
+static DecodeStatus DecodeT2Adr(MCInst *Inst, unsigned Val, uint64_t Address,
+								const void *Decoder);
+static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Val,
+									uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, unsigned Val,
+											  uint64_t Address,
+											  const void *Decoder);
+
+static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address,
+							  const void *Decoder);
+static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
+											uint64_t Address,
+											const void *Decoder);
+static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+
+#define DECLARE_DecodeBFLabelOperand(isSigned, isNeg, zeroPermitted, size)     \
+	static DecodeStatus CONCAT(                                                \
+		DecodeBFLabelOperand,                                                  \
+		CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))(         \
+		MCInst * Inst, unsigned val, uint64_t Address, const void *Decoder);
+DECLARE_DecodeBFLabelOperand(false, false, false, 4)
+	DECLARE_DecodeBFLabelOperand(true, false, true, 18)
+		DECLARE_DecodeBFLabelOperand(true, false, true, 12)
+			DECLARE_DecodeBFLabelOperand(true, false, true, 16)
+				DECLARE_DecodeBFLabelOperand(false, true, true, 11)
+					DECLARE_DecodeBFLabelOperand(false, false, true, 11)
+
+						static DecodeStatus
+	DecodeBFAfterTargetOperand(MCInst *Inst, unsigned val, uint64_t Address,
+							   const void *Decoder);
+static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val,
+										  uint64_t Address,
+										  const void *Decoder);
+static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder);
+static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder);
+static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder);
+static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned Val,
+										uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst,
+													  unsigned Val,
+													  uint64_t Address,
+													  const void *Decoder);
+static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst,
+													  unsigned Val,
+													  uint64_t Address,
+													  const void *Decoder);
+static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst,
+													  unsigned Val,
+													  uint64_t Address,
+													  const void *Decoder);
+static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst,
+													   unsigned Val,
+													   uint64_t Address,
+													   const void *Decoder);
+#define DECLARE_DecodeVSTRVLDR_SYSREG(Writeback)                               \
+	static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)(              \
+		MCInst * Inst, unsigned Insn, uint64_t Address, const void *Decoder);
+DECLARE_DecodeVSTRVLDR_SYSREG(false) DECLARE_DecodeVSTRVLDR_SYSREG(true)
+
+#define DECLARE_DecodeMVE_MEM_1_pre(shift)                                     \
+	static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+	DECLARE_DecodeMVE_MEM_1_pre(0) DECLARE_DecodeMVE_MEM_1_pre(1)
+
+#define DECLARE_DecodeMVE_MEM_2_pre(shift)                                     \
+	static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+		DECLARE_DecodeMVE_MEM_2_pre(0) DECLARE_DecodeMVE_MEM_2_pre(1)
+			DECLARE_DecodeMVE_MEM_2_pre(2)
+
+#define DECLARE_DecodeMVE_MEM_3_pre(shift)                                     \
+	static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+				DECLARE_DecodeMVE_MEM_3_pre(2) DECLARE_DecodeMVE_MEM_3_pre(3)
+
+#define DECLARE_DecodePowerTwoOperand(MinLog, MaxLog)                          \
+	static DecodeStatus CONCAT(DecodePowerTwoOperand, CONCAT(MinLog, MaxLog))( \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+					DECLARE_DecodePowerTwoOperand(0, 3)
+
+#define DECLARE_DecodeMVEPairVectorIndexOperand(start)                         \
+	static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)(        \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder);
+						DECLARE_DecodeMVEPairVectorIndexOperand(2)
+							DECLARE_DecodeMVEPairVectorIndexOperand(0)
+
+								static DecodeStatus
+	DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address,
+						 const void *Decoder);
+static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn,
+									  uint64_t Address, const void *Decoder);
+typedef DecodeStatus OperandDecoder(MCInst *Inst, unsigned Val,
+									uint64_t Address, const void *Decoder);
+#define DECLARE_DecodeMVEVCMP(scalar, predicate_decoder)                       \
+	static DecodeStatus CONCAT(DecodeMVEVCMP,                                  \
+							   CONCAT(scalar, predicate_decoder))(             \
+		MCInst * Inst, unsigned Insn, uint64_t Address, const void *Decoder);
+DECLARE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand)
+	DECLARE_DecodeMVEVCMP(false, DecodeRestrictedUPredicateOperand)
+		DECLARE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand)
+			DECLARE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand)
+				DECLARE_DecodeMVEVCMP(true, DecodeRestrictedUPredicateOperand)
+					DECLARE_DecodeMVEVCMP(true,
+										  DecodeRestrictedSPredicateOperand)
+						DECLARE_DecodeMVEVCMP(
+							false, DecodeRestrictedFPPredicateOperand)
+							DECLARE_DecodeMVEVCMP(
+								true, DecodeRestrictedFPPredicateOperand)
+
+								static DecodeStatus
+	DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
+				  const void *Decoder);
+static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn,
+								   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn,
+												  uint64_t Address,
+												  const void *Decoder);
+static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn,
+										uint64_t Address, const void *Decoder);
 
 #include "ARMGenDisassemblerTables.inc"
 
-static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
-{
-	if (Val == 0xF) return MCDisassembler_Fail;
-
-	// AL predicate is not allowed on Thumb1 branches.
-	if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, Val);
-
-	if (Val == ARMCC_AL) {
-		MCOperand_CreateReg0(Inst, 0);
-	} else
-		MCOperand_CreateReg0(Inst, ARM_CPSR);
-
-	return MCDisassembler_Success;
-}
-
-#define GET_REGINFO_MC_DESC
-#include "ARMGenRegisterInfo.inc"
-void ARM_init(MCRegisterInfo *MRI)
-{
-	/* 
-		InitMCRegisterInfo(ARMRegDesc, 289,
-		RA, PC,
-		ARMMCRegisterClasses, 103,
-		ARMRegUnitRoots, 77, ARMRegDiffLists, ARMRegStrings,
-		ARMSubRegIdxLists, 57,
-		ARMSubRegIdxRanges, ARMRegEncodingTable);
-	 */
-
-	MCRegisterInfo_InitMCRegisterInfo(MRI, ARMRegDesc, 289,
-			0, 0, 
-			ARMMCRegisterClasses, 103,
-			0, 0, ARMRegDiffLists, 0, 
-			ARMSubRegIdxLists, 57,
-			0);
-}
-
 // Post-decoding checks
-static DecodeStatus checkDecodedInstruction(MCInst *MI,
-		uint32_t Insn,
-		DecodeStatus Result)
+static DecodeStatus checkDecodedInstruction(MCInst *MI, uint32_t Insn,
+											DecodeStatus Result)
 {
 	switch (MCInst_getOpcode(MI)) {
-		case ARM_HVC: {
-			  // HVC is undefined if condition = 0xf otherwise upredictable
-			  // if condition != 0xe
-			  uint32_t Cond = (Insn >> 28) & 0xF;
-
-			  if (Cond == 0xF)
-				  return MCDisassembler_Fail;
-
-			  if (Cond != 0xE)
-				  return MCDisassembler_SoftFail;
-
-			  return Result;
-		  }
-		default:
-			   return Result;
+	case ARM_HVC: {
+		// HVC is undefined if condition = 0xf otherwise upredictable
+		// if condition != 0xe
+		uint32_t Cond = (Insn >> 28) & 0xF;
+		if (Cond == 0xF)
+			return MCDisassembler_Fail;
+		if (Cond != 0xE)
+			return MCDisassembler_SoftFail;
+		return Result;
+	}
+	case ARM_t2ADDri:
+	case ARM_t2ADDri12:
+	case ARM_t2ADDrr:
+	case ARM_t2ADDrs:
+	case ARM_t2SUBri:
+	case ARM_t2SUBri12:
+	case ARM_t2SUBrr:
+	case ARM_t2SUBrs:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP &&
+			MCOperand_getReg(MCInst_getOperand(MI, (1))) != ARM_SP)
+			return MCDisassembler_SoftFail;
+		return Result;
+	default:
+		return Result;
 	}
 }
 
-static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
-		uint16_t *Size, uint64_t Address)
+static DecodeStatus getInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
+							MCInst *MI, uint16_t *Size, uint64_t Address,
+							void *Info)
 {
-	uint32_t insn;
-	DecodeStatus result;
+	DecodeStatus Result = MCDisassembler_Fail;
+	if (MI->csh->mode & CS_MODE_THUMB)
+		Result =
+			getThumbInstruction(ud, Bytes, BytesLen, MI, Size, Address, Info);
+	else
+		Result =
+			getARMInstruction(ud, Bytes, BytesLen, MI, Size, Address, Info);
+	MCInst_handleWriteback(MI, ARMInsts);
+	return Result;
+}
 
-	*Size = 0;
+static inline uint32_t endianSensitiveOpcode32(MCInst *MI, const uint8_t *Bytes)
+{
+	uint32_t Insn;
+	if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
+		Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
+			   ((uint32_t)Bytes[0] << 24);
+	else
+		Insn = ((uint32_t)Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) |
+			   (Bytes[0] << 0);
+	return Insn;
+}
 
-	if (code_len < 4)
-		// not enough data
+static inline uint16_t endianSensitiveOpcode16(MCInst *MI, const uint8_t *Bytes)
+{
+	uint16_t Insn;
+	if (MODE_IS_BIG_ENDIAN(MI->csh->mode))
+		Insn = (Bytes[0] << 8) | Bytes[1];
+	else
+		Insn = (Bytes[1] << 8) | Bytes[0];
+
+	return Insn;
+}
+
+DecodeStatus getARMInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
+							   MCInst *MI, uint16_t *Size, uint64_t Address,
+							   void *Info)
+{
+	// We want to read exactly 4 bytes of data.
+	if (BytesLen < 4) {
+		*Size = 0;
 		return MCDisassembler_Fail;
+	}
 
-	if (MI->flat_insn->detail) {
-		unsigned int i;
+	// Encoded as a 32-bit word in the stream.
+	uint32_t Insn = endianSensitiveOpcode32(MI, Bytes);
 
-		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm) + sizeof(cs_arm));
+	// Calling the auto-generated decoder function.
+	DecodeStatus Result =
+		decodeInstruction_4(DecoderTableARM32, MI, Insn, Address);
+	if (Result != MCDisassembler_Fail) {
+		*Size = 4;
+		return checkDecodedInstruction(MI, Insn, Result);
+	}
 
-		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
-			MI->flat_insn->detail->arm.operands[i].vector_index = -1;
-			MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
+	typedef struct DecodeTable {
+		const uint8_t *P;
+		bool DecodePred;
+	} DecodeTable;
+
+	const DecodeTable Tables[] = {
+		{DecoderTableVFP32, false},		 {DecoderTableVFPV832, false},
+		{DecoderTableNEONData32, true},	 {DecoderTableNEONLoadStore32, true},
+		{DecoderTableNEONDup32, true},	 {DecoderTablev8NEON32, false},
+		{DecoderTablev8Crypto32, false},
+	};
+
+	for (int i = 0; i < (sizeof(Tables) / sizeof(Tables[0])); ++i) {
+		MCInst_clear(MI);
+		DecodeTable Table = Tables[i];
+		Result = decodeInstruction_4(Table.P, MI, Insn, Address);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			// Add a fake predicate operand, because we share these instruction
+			// definitions with Thumb2 where these instructions are predicable.
+			if (Table.DecodePred &&
+				!DecodePredicateOperand(MI, 0xE, Address, Table.P))
+				return MCDisassembler_Fail;
+			return Result;
 		}
 	}
 
-	if (MODE_IS_BIG_ENDIAN(ud->mode))
-		insn = (code[3] << 0) | (code[2] << 8) |
-			(code[1] <<  16) | ((uint32_t) code[0] << 24);
-	else
-		insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
-			(code[1] <<  8) | (code[0] <<  0);
-
-	// Calling the auto-generated decoder function.
-	result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		result = checkDecodedInstruction(MI, insn, result);
-		if (result != MCDisassembler_Fail)
-			*Size = 4;
-
-		return result;
-	}
-
-	// VFP and NEON instructions, similarly, are shared between ARM
-	// and Thumb modes.
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableVFP32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
+	Result = decodeInstruction_4(DecoderTableCoProc32, MI, Insn, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
-		return result;
+		return checkDecodedInstruction(MI, Insn, Result);
 	}
 
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableVFPV832, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		return result;
-	}
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableNEONData32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		// Add a fake predicate operand, because we share these instruction
-		// definitions with Thumb2 where these instructions are predicable.
-		if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
-			return MCDisassembler_Fail;
-		return result;
-	}
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		// Add a fake predicate operand, because we share these instruction
-		// definitions with Thumb2 where these instructions are predicable.
-		if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
-			return MCDisassembler_Fail;
-		return result;
-	}
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		// Add a fake predicate operand, because we share these instruction
-		// definitions with Thumb2 where these instructions are predicable.
-		if (!DecodePredicateOperand(MI, 0xE, Address, NULL))
-			return MCDisassembler_Fail;
-		return result;
-	}
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTablev8NEON32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		return result;
-	}
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTablev8Crypto32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		return result;
-	}
-
-	result = decodeInstruction_4(DecoderTableCoProc32, MI, insn, Address);
-	if (result != MCDisassembler_Fail) {
-		result = checkDecodedInstruction(MI, insn, result);
-		if (result != MCDisassembler_Fail)
-			*Size = 4;
-
-		return result;
-	}
-
-	MCInst_clear(MI);
-	*Size = 0;
+	*Size = 4;
 	return MCDisassembler_Fail;
 }
 
-// Thumb1 instructions don't have explicit S bits. Rather, they
-// implicitly set CPSR. Since it's not represented in the encoding, the
-// auto-generated decoder won't inject the CPSR operand. We need to fix
+extern const MCInstrDesc ARMInsts[];
+
+/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
+/// immediate Value in the MCInst.  The immediate Value has had any PC
+/// adjustment made by the caller.  If the instruction is a branch instruction
+/// then isBranch is true, else false.  If the getOpInfo() function was set as
+/// part of the setupForSymbolicDisassembly() call then that function is called
+/// to get any symbolic information at the Address for this instruction.  If
+/// that returns non-zero then the symbolic information it returns is used to
+/// create an MCExpr and that is added as an operand to the MCInst.  If
+/// getOpInfo() returns zero and isBranch is true then a symbol look up for
+/// Value is done and if a symbol is found an MCExpr is created with that, else
+/// an MCExpr with Value is created.  This function returns true if it adds an
+/// operand to the MCInst and false otherwise.
+static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
+									 bool isBranch, uint64_t InstSize,
+									 MCInst *MI, const void *Decoder)
+{
+	// FIXME: Does it make sense for value to be negative?
+	// return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address,
+	// 			   isBranch, /*Offset=*/0, /*OpSize=*/0,
+	// 			   InstSize);
+	return false;
+}
+
+/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
+/// referenced by a load instruction with the base register that is the Pc.
+/// These can often be values in a literal pool near the Address of the
+/// instruction.  The Address of the instruction and its immediate Value are
+/// used as a possible literal pool entry.  The SymbolLookUp call back will
+/// return the name of a symbol referenced by the literal pool's entry if
+/// the referenced address is that of a symbol.  Or it will return a pointer to
+/// a literal 'C' string if the referenced address of the literal pool's entry
+/// is an address into a section with 'C' string literals.
+static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
+											const void *Decoder)
+{
+	// Decoder->tryAddingPcLoadReferenceComment(Value, Address);
+}
+
+// Thumb1 instructions don't have explicit S bits.  Rather, they
+// implicitly set CPSR.  Since it's not represented in the encoding, the
+// auto-generated decoder won't inject the CPSR operand.  We need to fix
 // that as a post-pass.
 static void AddThumb1SBit(MCInst *MI, bool InITBlock)
 {
@@ -616,129 +783,182 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock)
 	unsigned i;
 
 	for (i = 0; i < NumOps; ++i) {
-		if (i == MCInst_getNumOperands(MI)) break;
-
-		if (MCOperandInfo_isOptionalDef(&OpInfo[i]) && OpInfo[i].RegClass == ARM_CCRRegClassID) {
-			if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1])) continue;
-			MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
+		if (i == MCInst_getNumOperands(MI))
+			break;
+		if (MCOperandInfo_isOptionalDef(&OpInfo[i]) &&
+			OpInfo[i].RegClass == ARM_CCRRegClassID) {
+			if (i > 0 && MCOperandInfo_isPredicate(&OpInfo[i - 1]))
+				continue;
+			MCInst_insert0(
+				MI, i, MCOperand_CreateReg1(MI, (InITBlock ? 0 : ARM_CPSR)));
 			return;
 		}
 	}
 
-	//MI.insert(I, MCOperand_CreateReg0(Inst, InITBlock ? 0 : ARM_CPSR));
-	MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, InITBlock ? 0 : ARM_CPSR));
+	MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, (InITBlock ? 0 : ARM_CPSR)));
+}
+
+static bool isVectorPredicable(unsigned Opcode)
+{
+	const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+	unsigned short NumOps = ARMInsts[Opcode].NumOperands;
+	for (unsigned i = 0; i < NumOps; ++i) {
+		if (ARM_isVpred(OpInfo[i].OperandType))
+			return true;
+	}
+	return false;
 }
 
 // Most Thumb instructions don't have explicit predicates in the
-// encoding, but rather get their predicates from IT context. We need
+// encoding, but rather get their predicates from IT context.  We need
 // to fix up the predicate operands using this context information as a
 // post-pass.
-static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
+DecodeStatus AddThumbPredicate(MCInst *MI)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	const MCOperandInfo *OpInfo;
-	unsigned short NumOps;
-	unsigned int i;
-	unsigned CC;
 
-	// A few instructions actually have predicates encoded in them. Don't
+	// A few instructions actually have predicates encoded in them.  Don't
 	// try to overwrite it if we're seeing one of those.
 	switch (MCInst_getOpcode(MI)) {
-		case ARM_tBcc:
-		case ARM_t2Bcc:
-		case ARM_tCBZ:
-		case ARM_tCBNZ:
-		case ARM_tCPS:
-		case ARM_t2CPS3p:
-		case ARM_t2CPS2p:
-		case ARM_t2CPS1p:
-		case ARM_tMOVSr:
-		case ARM_tSETEND:
-			// Some instructions (mostly conditional branches) are not
-			// allowed in IT blocks.
-			if (ITStatus_instrInITBlock(&(ud->ITBlock)))
-				S = MCDisassembler_SoftFail;
-			else
-				return MCDisassembler_Success;
-			break;
-
-		case ARM_t2HINT:
-			if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0x10)
-				S = MCDisassembler_SoftFail;
-			break;
-
-		case ARM_tB:
-		case ARM_t2B:
-		case ARM_t2TBB:
-		case ARM_t2TBH:
-			// Some instructions (mostly unconditional branches) can
-			// only appears at the end of, or outside of, an IT.
-			// if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
-			if (ITStatus_instrInITBlock(&(ud->ITBlock)) && !ITStatus_instrLastInITBlock(&(ud->ITBlock)))
-				S = MCDisassembler_SoftFail;
-			break;
-		default:
-			break;
+	case ARM_tBcc:
+	case ARM_t2Bcc:
+	case ARM_tCBZ:
+	case ARM_tCBNZ:
+	case ARM_tCPS:
+	case ARM_t2CPS3p:
+	case ARM_t2CPS2p:
+	case ARM_t2CPS1p:
+	case ARM_t2CSEL:
+	case ARM_t2CSINC:
+	case ARM_t2CSINV:
+	case ARM_t2CSNEG:
+	case ARM_tMOVSr:
+	case ARM_tSETEND:
+		// Some instructions (mostly conditional branches) are not
+		// allowed in IT blocks.
+		if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)))
+			S = MCDisassembler_SoftFail;
+		else
+			return MCDisassembler_Success;
+		break;
+	case ARM_t2HINT:
+		if (MCOperand_getImm(MCInst_getOperand(MI, (0))) == 0x10 &&
+			(ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) != 0)
+			S = MCDisassembler_SoftFail;
+		break;
+	case ARM_tB:
+	case ARM_t2B:
+	case ARM_t2TBB:
+	case ARM_t2TBH:
+		// Some instructions (mostly unconditional branches) can
+		// only appears at the end of, or outside of, an IT.
+		if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)) &&
+			!ITBlock_instrLastInITBlock(&(MI->csh->ITBlock)))
+			S = MCDisassembler_SoftFail;
+		break;
+	default:
+		break;
 	}
 
-	// If we're in an IT block, base the predicate on that.  Otherwise,
+	// Warn on non-VPT predicable instruction in a VPT block and a VPT
+	// predicable instruction in an IT block
+	if ((!isVectorPredicable(MCInst_getOpcode(MI)) &&
+		 VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) ||
+		(isVectorPredicable(MCInst_getOpcode(MI)) &&
+		 ITBlock_instrInITBlock(&(MI->csh->ITBlock))))
+		S = MCDisassembler_SoftFail;
+
+	// If we're in an IT/VPT block, base the predicate on that.  Otherwise,
 	// assume a predicate of AL.
-	CC = ITStatus_getITCC(&(ud->ITBlock));
-	if (CC == 0xF) 
-		CC = ARMCC_AL;
-
-	if (ITStatus_instrInITBlock(&(ud->ITBlock)))
-		ITStatus_advanceITState(&(ud->ITBlock));
-
-	OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-	NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
-
-	for (i = 0; i < NumOps; ++i) {
-		if (i == MCInst_getNumOperands(MI)) break;
-
-		if (MCOperandInfo_isPredicate(&OpInfo[i])) {
-			MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
-
-			if (CC == ARMCC_AL)
-				MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, 0));
-			else
-				MCInst_insert0(MI, i+1, MCOperand_CreateReg1(MI, ARM_CPSR));
-
-			return S;
-		}
+	unsigned CC = ARMCC_AL;
+	unsigned VCC = ARMVCC_None;
+	if (ITBlock_instrInITBlock(&(MI->csh->ITBlock))) {
+		CC = ITBlock_getITCC(&(MI->csh->ITBlock));
+		ITBlock_advanceITState(&(MI->csh->ITBlock));
+	} else if (VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) {
+		VCC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock));
+		VPTBlock_advanceVPTState(&(MI->csh->VPTBlock));
 	}
 
-	MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, CC));
+	const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+	unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
 
-	if (CC == ARMCC_AL)
-		MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, 0));
-	else
-		MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, ARM_CPSR));
+	unsigned i;
+	for (i = 0; i < NumOps; ++i) {
+		if (MCOperandInfo_isPredicate(&OpInfo[i]) ||
+			i == MCInst_getNumOperands(MI))
+			break;
+	}
+
+	if (MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(MI)])) {
+		MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, (CC)));
+
+		if (CC == ARMCC_AL)
+			MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, (0)));
+		else
+			MCInst_insert0(MI, i + 1, MCOperand_CreateReg1(MI, (ARM_CPSR)));
+	} else if (CC != ARMCC_AL) {
+		Check(&S, MCDisassembler_SoftFail);
+	}
+
+	unsigned VCCPos;
+	for (VCCPos = 0; VCCPos < NumOps; ++VCCPos) {
+		if (ARM_isVpred(OpInfo[VCCPos].OperandType) ||
+			VCCPos == MCInst_getNumOperands(MI))
+			break;
+	}
+
+	if (isVectorPredicable(MCInst_getOpcode(MI))) {
+		MCInst_insert0(MI, VCCPos, MCOperand_CreateImm1(MI, (VCC)));
+
+		if (VCC == ARMVCC_None)
+			MCInst_insert0(MI, VCCPos + 1, MCOperand_CreateReg1(MI, (0)));
+		else
+			MCInst_insert0(MI, VCCPos + 1, MCOperand_CreateReg1(MI, (ARM_P0)));
+		MCInst_insert0(MI, VCCPos + 2, MCOperand_CreateReg1(MI, (0)));
+		if (OpInfo[VCCPos].OperandType == ARM_OP_VPRED_R) {
+			int TiedOp = MCOperandInfo_getOperandConstraint(
+				&ARMInsts[MCInst_getOpcode(MI)], VCCPos + 3, MCOI_TIED_TO);
+			assert(TiedOp >= 0 &&
+				   "Inactive register in vpred_r is not tied to an output!");
+			// Copy the operand to ensure it's not invalidated when MI grows.
+			MCOperand *Op = malloc(sizeof(MCOperand));
+			memcpy(Op, MCInst_getOperand(MI, TiedOp), sizeof(MCOperand));
+			MCInst_insert0(MI, VCCPos + 3, Op);
+			free(Op);
+		}
+	} else if (VCC != ARMVCC_None) {
+		Check(&S, MCDisassembler_SoftFail);
+	}
 
 	return S;
 }
 
-// Thumb VFP instructions are a special case. Because we share their
+// Thumb VFP instructions are a special case.  Because we share their
 // encodings between ARM and Thumb modes, and they are predicable in ARM
 // mode, the auto-generated decoder will give them an (incorrect)
-// predicate operand. We need to rewrite these operands based on the IT
+// predicate operand.  We need to rewrite these operands based on the IT
 // context as a post-pass.
-static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
+void UpdateThumbVFPPredicate(DecodeStatus S, MCInst *MI)
 {
 	unsigned CC;
-	unsigned short NumOps;
-	const MCOperandInfo *OpInfo;
-	unsigned i;
+	CC = ITBlock_getITCC(&(MI->csh->ITBlock));
+	if (CC == 0xF)
+		CC = ARMCC_AL;
+	if (ITBlock_instrInITBlock(&(MI->csh->ITBlock)))
+		ITBlock_advanceITState(&(MI->csh->ITBlock));
+	else if (VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))) {
+		CC = VPTBlock_getVPTPred(&(MI->csh->VPTBlock));
+		VPTBlock_advanceVPTState(&(MI->csh->VPTBlock));
+	}
 
-	CC = ITStatus_getITCC(&(ud->ITBlock));
-	if (ITStatus_instrInITBlock(&(ud->ITBlock)))
-		ITStatus_advanceITState(&(ud->ITBlock));
-
-	OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
-	NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
-
-	for (i = 0; i < NumOps; ++i) {
+	const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
+	unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
+	for (unsigned i = 0; i < NumOps; ++i) {
 		if (MCOperandInfo_isPredicate(&OpInfo[i])) {
+			if (CC != ARMCC_AL &&
+				!MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(MI)]))
+				Check(&S, MCDisassembler_SoftFail);
 			MCOperand_setImm(MCInst_getOperand(MI, i), CC);
 
 			if (CC == ARMCC_AL)
@@ -751,247 +971,252 @@ static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
 	}
 }
 
-static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
-		uint16_t *Size, uint64_t Address)
+DecodeStatus getThumbInstruction(csh ud, const uint8_t *Bytes, size_t BytesLen,
+								 MCInst *MI, uint16_t *Size, uint64_t Address,
+								 void *Info)
 {
-	uint16_t insn16;
-	DecodeStatus result;
-	bool InITBlock;
-	unsigned Firstcond, Mask; 
-	uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
-	size_t i;
-
 	// We want to read exactly 2 bytes of data.
-	if (code_len < 2)
-		// not enough data
+	if (BytesLen < 2) {
+		*Size = 0;
 		return MCDisassembler_Fail;
-
-	if (MI->flat_insn->detail) {
-		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
-		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
-			MI->flat_insn->detail->arm.operands[i].vector_index = -1;
-			MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
-		}
 	}
 
-	if (MODE_IS_BIG_ENDIAN(ud->mode))
-		insn16 = (code[0] << 8) | code[1];
-	else
-		insn16 = (code[1] << 8) | code[0];
-
-	result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address);
-	if (result != MCDisassembler_Fail) {
+	uint16_t Insn16 = endianSensitiveOpcode16(MI, Bytes);
+	DecodeStatus Result =
+		decodeInstruction_2(DecoderTableThumb16, MI, Insn16, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 2;
-		Check(&result, AddThumbPredicate(ud, MI));
-		return result;
+		Check(&Result, AddThumbPredicate(MI));
+		return Result;
 	}
 
-	MCInst_clear(MI);
-	result = decodeInstruction_2(DecoderTableThumbSBit16, MI, insn16, Address);
-	if (result) {
+	Result = decodeInstruction_2(DecoderTableThumbSBit16, MI, Insn16, Address);
+	if (Result) {
 		*Size = 2;
-		InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
-		Check(&result, AddThumbPredicate(ud, MI));
+		bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock));
+		Check(&Result, AddThumbPredicate(MI));
 		AddThumb1SBit(MI, InITBlock);
-		return result;
+		return Result;
 	}
 
-	MCInst_clear(MI);
-	result = decodeInstruction_2(DecoderTableThumb216, MI, insn16, Address);
-	if (result != MCDisassembler_Fail) {
+	Result = decodeInstruction_2(DecoderTableThumb216, MI, Insn16, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 2;
 
 		// Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
 		// the Thumb predicate.
-		if (MCInst_getOpcode(MI) == ARM_t2IT && ITStatus_instrInITBlock(&(ud->ITBlock)))
-			return MCDisassembler_SoftFail;
+		if (MCInst_getOpcode(MI) == ARM_t2IT &&
+			ITBlock_instrInITBlock(&(MI->csh->ITBlock)))
+			Result = MCDisassembler_SoftFail;
 
-		Check(&result, AddThumbPredicate(ud, MI));
+		Check(&Result, AddThumbPredicate(MI));
 
 		// If we find an IT instruction, we need to parse its condition
 		// code and mask operands so that we can apply them correctly
 		// to the subsequent instructions.
 		if (MCInst_getOpcode(MI) == ARM_t2IT) {
-			Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 0));
-			Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, 1));
-			ITStatus_setITState(&(ud->ITBlock), (char)Firstcond, (char)Mask);
+			unsigned Firstcond = MCOperand_getImm(MCInst_getOperand(MI, (0)));
+			unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (1)));
+			ITBlock_setITState(&(MI->csh->ITBlock), (char)Firstcond,
+							   (char)Mask);
 
-			// An IT instruction that would give a 'NV' predicate is unpredictable.
-			// if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask))
-			// 	CS << "unpredictable IT predicate sequence";
+			// An IT instruction that would give a 'NV' predicate is
+			// unpredictable. if (Firstcond == ARMCC_AL && !isPowerOf2_32(Mask))
+			//	SStream_concat0(CS, "unpredictable IT predicate sequence");
 		}
 
-		return result;
+		return Result;
 	}
 
 	// We want to read exactly 4 bytes of data.
-	if (code_len < 4)
-		// not enough data
+	if (BytesLen < 4) {
+		*Size = 0;
 		return MCDisassembler_Fail;
+	}
+	uint32_t Insn32 =
+		(uint32_t)Insn16 << 16 | endianSensitiveOpcode16(MI, Bytes + 2);
 
-	if (MODE_IS_BIG_ENDIAN(ud->mode))
-		insn32 = (code[3] <<  0) | (code[2] <<  8) |
-			(code[1] << 16) | ((uint32_t) code[0] << 24);
-	else
-		insn32 = (code[3] <<  8) | (code[2] <<  0) |
-			((uint32_t) code[1] << 24) | (code[0] << 16);
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address);
-	if (result != MCDisassembler_Fail) {
+	Result = decodeInstruction_4(DecoderTableMVE32, MI, Insn32, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
-		InITBlock = ITStatus_instrInITBlock(&(ud->ITBlock));
-		Check(&result, AddThumbPredicate(ud, MI));
+
+		// Nested VPT blocks are UNPREDICTABLE. Must be checked before we add
+		// the VPT predicate.
+		if (isVPTOpcode(MCInst_getOpcode(MI)) &&
+			VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock)))
+			Result = MCDisassembler_SoftFail;
+
+		Check(&Result, AddThumbPredicate(MI));
+
+		if (isVPTOpcode(MCInst_getOpcode(MI))) {
+			unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (0)));
+			VPTBlock_setVPTState(&(MI->csh->VPTBlock), Mask);
+		}
+
+		return Result;
+	}
+
+	Result = decodeInstruction_4(DecoderTableThumb32, MI, Insn32, Address);
+	if (Result != MCDisassembler_Fail) {
+		*Size = 4;
+		bool InITBlock = ITBlock_instrInITBlock(&(MI->csh->ITBlock));
+		Check(&Result, AddThumbPredicate(MI));
 		AddThumb1SBit(MI, InITBlock);
-
-		return result;
+		return Result;
 	}
 
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableThumb232, MI, insn32, Address);
-	if (result != MCDisassembler_Fail) {
+	Result = decodeInstruction_4(DecoderTableThumb232, MI, Insn32, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
-		Check(&result, AddThumbPredicate(ud, MI));
-		return result;
+		Check(&Result, AddThumbPredicate(MI));
+		return checkDecodedInstruction(MI, Insn32, Result);
 	}
 
-	if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
-		MCInst_clear(MI);
-		result = decodeInstruction_4(DecoderTableVFP32, MI, insn32, Address);
-		if (result != MCDisassembler_Fail) {
+	if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) {
+		Result = decodeInstruction_4(DecoderTableVFP32, MI, Insn32, Address);
+		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
-			UpdateThumbVFPPredicate(ud, MI);
-			return result;
+			UpdateThumbVFPPredicate(Result, MI);
+			return Result;
 		}
 	}
 
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableVFPV832, MI, insn32, Address);
-	if (result != MCDisassembler_Fail) {
+	Result = decodeInstruction_4(DecoderTableVFPV832, MI, Insn32, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
-		return result;
+		return Result;
 	}
 
-	if (fieldFromInstruction_4(insn32, 28, 4) == 0xE) {
-		MCInst_clear(MI);
-		result = decodeInstruction_4(DecoderTableNEONDup32, MI, insn32, Address);
-		if (result != MCDisassembler_Fail) {
+	if (fieldFromInstruction_4(Insn32, 28, 4) == 0xE) {
+		Result =
+			decodeInstruction_4(DecoderTableNEONDup32, MI, Insn32, Address);
+		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
-			Check(&result, AddThumbPredicate(ud, MI));
-			return result;
+			Check(&Result, AddThumbPredicate(MI));
+			return Result;
 		}
 	}
 
-	if (fieldFromInstruction_4(insn32, 24, 8) == 0xF9) {
-		MCInst_clear(MI);
-		NEONLdStInsn = insn32;
+	if (fieldFromInstruction_4(Insn32, 24, 8) == 0xF9) {
+		uint32_t NEONLdStInsn = Insn32;
 		NEONLdStInsn &= 0xF0FFFFFF;
 		NEONLdStInsn |= 0x04000000;
-		result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, Address);
-		if (result != MCDisassembler_Fail) {
+		Result = decodeInstruction_4(DecoderTableNEONLoadStore32, MI,
+									 NEONLdStInsn, Address);
+		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
-			Check(&result, AddThumbPredicate(ud, MI));
-			return result;
+			Check(&Result, AddThumbPredicate(MI));
+			return Result;
 		}
 	}
 
-	if (fieldFromInstruction_4(insn32, 24, 4) == 0xF) {
-		MCInst_clear(MI);
-		NEONDataInsn = insn32;
+	if (fieldFromInstruction_4(Insn32, 24, 4) == 0xF) {
+		uint32_t NEONDataInsn = Insn32;
 		NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
-		NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
-		NEONDataInsn |= 0x12000000; // Set bits 28 and 25
-		result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn, Address);
-		if (result != MCDisassembler_Fail) {
+		NEONDataInsn |=
+			(NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
+		NEONDataInsn |= 0x12000000;			  // Set bits 28 and 25
+		Result = decodeInstruction_4(DecoderTableNEONData32, MI, NEONDataInsn,
+									 Address);
+		if (Result != MCDisassembler_Fail) {
 			*Size = 4;
-			Check(&result, AddThumbPredicate(ud, MI));
-			return result;
+			Check(&Result, AddThumbPredicate(MI));
+			return Result;
+		}
+
+		uint32_t NEONCryptoInsn = Insn32;
+		NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
+		NEONCryptoInsn |=
+			(NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
+		NEONCryptoInsn |= 0x12000000;			// Set bits 28 and 25
+		Result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
+									 Address);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
+		}
+
+		uint32_t NEONv8Insn = Insn32;
+		NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
+		Result =
+			decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
 		}
 	}
 
-	MCInst_clear(MI);
-	NEONCryptoInsn = insn32;
-	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
-	NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
-	NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
-	result = decodeInstruction_4(DecoderTablev8Crypto32, MI, NEONCryptoInsn, Address);
-	if (result != MCDisassembler_Fail) {
+	uint32_t Coproc = fieldFromInstruction_4(Insn32, 8, 4);
+	const uint8_t *DecoderTable = ARM_isCDECoproc(Coproc, MI)
+									  ? DecoderTableThumb2CDE32
+									  : DecoderTableThumb2CoProc32;
+	Result = decodeInstruction_4(DecoderTable, MI, Insn32, Address);
+	if (Result != MCDisassembler_Fail) {
 		*Size = 4;
-		return result;
+		Check(&Result, AddThumbPredicate(MI));
+		return Result;
 	}
 
-	MCInst_clear(MI);
-	NEONv8Insn = insn32;
-	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
-	result = decodeInstruction_4(DecoderTablev8NEON32, MI, NEONv8Insn, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		return result;
-	}
-
-	MCInst_clear(MI);
-	result = decodeInstruction_4(DecoderTableThumb2CoProc32, MI, insn32, Address);
-	if (result != MCDisassembler_Fail) {
-		*Size = 4;
-		Check(&result, AddThumbPredicate(ud, MI));
-		return result;
-	}
-
-	MCInst_clear(MI);
 	*Size = 0;
-
 	return MCDisassembler_Fail;
 }
 
-bool Thumb_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
-{
-	DecodeStatus status = _Thumb_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
-
-	// TODO: fix table gen to eliminate these special cases
-	if (instr->Opcode == ARM_t__brkdiv0)
-		return false;
-
-	//return status == MCDisassembler_Success;
-	return status != MCDisassembler_Fail;
-}
-
-bool ARM_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
-{
-	DecodeStatus status = _ARM_getInstruction((cs_struct *)ud, instr, code, code_len, size, address);
-
-	//return status == MCDisassembler_Success;
-	return status != MCDisassembler_Fail;
-}
-
 static const uint16_t GPRDecoderTable[] = {
-	ARM_R0, ARM_R1, ARM_R2, ARM_R3,
-	ARM_R4, ARM_R5, ARM_R6, ARM_R7,
-	ARM_R8, ARM_R9, ARM_R10, ARM_R11,
-	ARM_R12, ARM_SP, ARM_LR, ARM_PC
-};
+	ARM_R0, ARM_R1, ARM_R2,	 ARM_R3,  ARM_R4,  ARM_R5, ARM_R6, ARM_R7,
+	ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC};
+
+static const uint16_t CLRMGPRDecoderTable[] = {
+	ARM_R0, ARM_R1, ARM_R2,	 ARM_R3,  ARM_R4,  ARM_R5, ARM_R6, ARM_R7,
+	ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, 0,	   ARM_LR, ARM_APSR};
 
 static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
-	unsigned Register;
-
 	if (RegNo > 15)
 		return MCDisassembler_Fail;
 
-	Register = GPRDecoderTable[RegNo];
-	MCOperand_CreateReg0(Inst, Register);
+	unsigned Register = GPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
 
+static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder)
+{
+	if (RegNo > 15)
+		return MCDisassembler_Fail;
+
+	unsigned Register = CLRMGPRDecoderTable[RegNo];
+	if (Register == 0)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
-	if (RegNo == 15) 
+	if (RegNo == 15)
+		S = MCDisassembler_SoftFail;
+
+	Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+
+	return S;
+}
+
+static DecodeStatus DecodeGPRnospRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	if (RegNo == 13)
 		S = MCDisassembler_SoftFail;
 
 	Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
@@ -1000,13 +1225,13 @@ static DecodeStatus DecodeGPRnopcRegisterClass(MCInst *Inst, unsigned RegNo,
 }
 
 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+												   uint64_t Address,
+												   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
 	if (RegNo == 15) {
-		MCOperand_CreateReg0(Inst, ARM_APSR_NZCV);
-
+		MCOperand_CreateReg0(Inst, (ARM_APSR_NZCV));
 		return MCDisassembler_Success;
 	}
 
@@ -1014,246 +1239,307 @@ static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst *Inst, unsigned RegNo,
 	return S;
 }
 
+static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst *Inst, unsigned RegNo,
+												 uint64_t Address,
+												 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	if (RegNo == 15) {
+		MCOperand_CreateReg0(Inst, (ARM_ZR));
+		return MCDisassembler_Success;
+	}
+
+	if (RegNo == 13)
+		Check(&S, MCDisassembler_SoftFail);
+
+	Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+	return S;
+}
+
+static DecodeStatus DecodeGPRwithZRnospRegisterClass(MCInst *Inst,
+													 unsigned RegNo,
+													 uint64_t Address,
+													 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	if (RegNo == 13)
+		return MCDisassembler_Fail;
+	Check(&S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
+	return S;
+}
+
 static DecodeStatus DecodetGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
 	if (RegNo > 7)
 		return MCDisassembler_Fail;
-
 	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t GPRPairDecoderTable[] = {
-	ARM_R0_R1, ARM_R2_R3,   ARM_R4_R5,  ARM_R6_R7,
-	ARM_R8_R9, ARM_R10_R11, ARM_R12_SP
-};
+	ARM_R0_R1, ARM_R2_R3,	ARM_R4_R5, ARM_R6_R7,
+	ARM_R8_R9, ARM_R10_R11, ARM_R12_SP};
 
 static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
-	unsigned RegisterPair;
 	DecodeStatus S = MCDisassembler_Success;
 
+	// According to the Arm ARM RegNo = 14 is undefined, but we return fail
+	// rather than SoftFail as there is no GPRPair table entry for index 7.
 	if (RegNo > 13)
 		return MCDisassembler_Fail;
 
-	if ((RegNo & 1) || RegNo == 0xe)
+	if (RegNo & 1)
 		S = MCDisassembler_SoftFail;
 
-	RegisterPair = GPRPairDecoderTable[RegNo / 2];
-	MCOperand_CreateReg0(Inst, RegisterPair);
-
+	unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2];
+	MCOperand_CreateReg0(Inst, (RegisterPair));
 	return S;
 }
 
+static DecodeStatus DecodeGPRPairnospRegisterClass(MCInst *Inst, unsigned RegNo,
+												   uint64_t Address,
+												   const void *Decoder)
+{
+	if (RegNo > 13)
+		return MCDisassembler_Fail;
+
+	unsigned RegisterPair = GPRPairDecoderTable[RegNo / 2];
+	MCOperand_CreateReg0(Inst, (RegisterPair));
+
+	if ((RegNo & 1) || RegNo > 10)
+		return MCDisassembler_SoftFail;
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRspRegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder)
+{
+	if (RegNo != 13)
+		return MCDisassembler_Fail;
+
+	unsigned Register = GPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodetcGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	unsigned Register = 0;
-
 	switch (RegNo) {
-		case 0:
-			Register = ARM_R0;
-			break;
-		case 1:
-			Register = ARM_R1;
-			break;
-		case 2:
-			Register = ARM_R2;
-			break;
-		case 3:
-			Register = ARM_R3;
-			break;
-		case 9:
-			Register = ARM_R9;
-			break;
-		case 12:
-			Register = ARM_R12;
-			break;
-		default:
-			return MCDisassembler_Fail;
+	case 0:
+		Register = ARM_R0;
+		break;
+	case 1:
+		Register = ARM_R1;
+		break;
+	case 2:
+		Register = ARM_R2;
+		break;
+	case 3:
+		Register = ARM_R3;
+		break;
+	case 9:
+		Register = ARM_R9;
+		break;
+	case 12:
+		Register = ARM_R12;
+		break;
+	default:
+		return MCDisassembler_Fail;
 	}
 
-	MCOperand_CreateReg0(Inst, Register);
-
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecoderGPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
-	if ((RegNo == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) || RegNo == 15)
+	if ((RegNo == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) ||
+		RegNo == 15)
 		S = MCDisassembler_SoftFail;
 
 	Check(&S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
-
 	return S;
 }
 
 static const uint16_t SPRDecoderTable[] = {
-	ARM_S0,  ARM_S1,  ARM_S2,  ARM_S3,
-	ARM_S4,  ARM_S5,  ARM_S6,  ARM_S7,
-	ARM_S8,  ARM_S9, ARM_S10, ARM_S11,
-	ARM_S12, ARM_S13, ARM_S14, ARM_S15,
-	ARM_S16, ARM_S17, ARM_S18, ARM_S19,
-	ARM_S20, ARM_S21, ARM_S22, ARM_S23,
-	ARM_S24, ARM_S25, ARM_S26, ARM_S27,
-	ARM_S28, ARM_S29, ARM_S30, ARM_S31
-};
+	ARM_S0,	 ARM_S1,  ARM_S2,  ARM_S3,	ARM_S4,	 ARM_S5,  ARM_S6,  ARM_S7,
+	ARM_S8,	 ARM_S9,  ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15,
+	ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23,
+	ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31};
 
 static DecodeStatus DecodeSPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
-	unsigned Register;
-
 	if (RegNo > 31)
 		return MCDisassembler_Fail;
 
-	Register = SPRDecoderTable[RegNo];
-	MCOperand_CreateReg0(Inst, Register);
-
+	unsigned Register = SPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeHPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t DPRDecoderTable[] = {
-	ARM_D0,  ARM_D1,  ARM_D2,  ARM_D3,
-	ARM_D4,  ARM_D5,  ARM_D6,  ARM_D7,
-	ARM_D8,  ARM_D9, ARM_D10, ARM_D11,
-	ARM_D12, ARM_D13, ARM_D14, ARM_D15,
-	ARM_D16, ARM_D17, ARM_D18, ARM_D19,
-	ARM_D20, ARM_D21, ARM_D22, ARM_D23,
-	ARM_D24, ARM_D25, ARM_D26, ARM_D27,
-	ARM_D28, ARM_D29, ARM_D30, ARM_D31
-};
+	ARM_D0,	 ARM_D1,  ARM_D2,  ARM_D3,	ARM_D4,	 ARM_D5,  ARM_D6,  ARM_D7,
+	ARM_D8,	 ARM_D9,  ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15,
+	ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23,
+	ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31};
 
 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
-	unsigned Register;
 
-	if (RegNo > 31 || (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD16) && RegNo > 15))
+	bool hasD32 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureD32);
+
+	if (RegNo > 31 || (!hasD32 && RegNo > 15))
 		return MCDisassembler_Fail;
 
-	Register = DPRDecoderTable[RegNo];
-	MCOperand_CreateReg0(Inst, Register);
-
+	unsigned Register = DPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeDPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	if (RegNo > 7)
 		return MCDisassembler_Fail;
-
 	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
-static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeSPR_8RegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	if (RegNo > 15)
 		return MCDisassembler_Fail;
+	return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
+}
 
+static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst *Inst, unsigned RegNo,
+												uint64_t Address,
+												const void *Decoder)
+{
+	if (RegNo > 15)
+		return MCDisassembler_Fail;
 	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
 }
 
 static const uint16_t QPRDecoderTable[] = {
-	ARM_Q0,  ARM_Q1,  ARM_Q2,  ARM_Q3,
-	ARM_Q4,  ARM_Q5,  ARM_Q6,  ARM_Q7,
-	ARM_Q8,  ARM_Q9, ARM_Q10, ARM_Q11,
-	ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15
-};
+	ARM_Q0, ARM_Q1, ARM_Q2,	 ARM_Q3,  ARM_Q4,  ARM_Q5,	ARM_Q6,	 ARM_Q7,
+	ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15};
 
 static DecodeStatus DecodeQPRRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
-	unsigned Register;
-
 	if (RegNo > 31 || (RegNo & 1) != 0)
 		return MCDisassembler_Fail;
-
 	RegNo >>= 1;
 
-	Register = QPRDecoderTable[RegNo];
-	MCOperand_CreateReg0(Inst, Register);
-
+	unsigned Register = QPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
 static const uint16_t DPairDecoderTable[] = {
-	ARM_Q0,  ARM_D1_D2,   ARM_Q1,  ARM_D3_D4,   ARM_Q2,  ARM_D5_D6,
-	ARM_Q3,  ARM_D7_D8,   ARM_Q4,  ARM_D9_D10,  ARM_Q5,  ARM_D11_D12,
-	ARM_Q6,  ARM_D13_D14, ARM_Q7,  ARM_D15_D16, ARM_Q8,  ARM_D17_D18,
-	ARM_Q9,  ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24,
+	ARM_Q0,	 ARM_D1_D2,	  ARM_Q1,  ARM_D3_D4,	ARM_Q2,	 ARM_D5_D6,
+	ARM_Q3,	 ARM_D7_D8,	  ARM_Q4,  ARM_D9_D10,	ARM_Q5,	 ARM_D11_D12,
+	ARM_Q6,	 ARM_D13_D14, ARM_Q7,  ARM_D15_D16, ARM_Q8,	 ARM_D17_D18,
+	ARM_Q9,	 ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24,
 	ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30,
-	ARM_Q15
-};
+	ARM_Q15};
 
 static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
-	unsigned Register;
-
 	if (RegNo > 30)
 		return MCDisassembler_Fail;
 
-	Register = DPairDecoderTable[RegNo];
-	MCOperand_CreateReg0(Inst, Register);
-
+	unsigned Register = DPairDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
 static const uint16_t DPairSpacedDecoderTable[] = {
-	ARM_D0_D2,   ARM_D1_D3,   ARM_D2_D4,   ARM_D3_D5,
-	ARM_D4_D6,   ARM_D5_D7,   ARM_D6_D8,   ARM_D7_D9,
-	ARM_D8_D10,  ARM_D9_D11,  ARM_D10_D12, ARM_D11_D13,
-	ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
-	ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21,
-	ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25,
-	ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29,
-	ARM_D28_D30, ARM_D29_D31
-};
+	ARM_D0_D2,	 ARM_D1_D3,	  ARM_D2_D4,   ARM_D3_D5,	ARM_D4_D6,
+	ARM_D5_D7,	 ARM_D6_D8,	  ARM_D7_D9,   ARM_D8_D10,	ARM_D9_D11,
+	ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16,
+	ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21,
+	ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26,
+	ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31};
 
-static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst,
-		unsigned RegNo, uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst *Inst, unsigned RegNo,
+												   uint64_t Address,
+												   const void *Decoder)
 {
-	unsigned Register;
-
 	if (RegNo > 29)
 		return MCDisassembler_Fail;
 
-	Register = DPairSpacedDecoderTable[RegNo];
-	MCOperand_CreateReg0(Inst, Register);
-
+	unsigned Register = DPairSpacedDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	if (Val == 0xF)
+		return MCDisassembler_Fail;
+	// AL predicate is not allowed on Thumb1 branches.
+	if (MCInst_getOpcode(Inst) == ARM_tBcc && Val == 0xE)
+		return MCDisassembler_Fail;
+	if (Val != ARMCC_AL &&
+		!MCInst_isPredicable(&ARMInsts[MCInst_getOpcode(Inst)]))
+		Check(&S, MCDisassembler_SoftFail);
+	MCOperand_CreateImm0(Inst, (Val));
+	if (Val == ARMCC_AL) {
+		MCOperand_CreateReg0(Inst, (0));
+	} else
+		MCOperand_CreateReg0(Inst, (ARM_CPSR));
+	return S;
+}
+
 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+									   uint64_t Address, const void *Decoder)
 {
 	if (Val)
-		MCOperand_CreateReg0(Inst, ARM_CPSR);
+		MCOperand_CreateReg0(Inst, (ARM_CPSR));
 	else
-		MCOperand_CreateReg0(Inst, 0);
-
+		MCOperand_CreateReg0(Inst, (0));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	ARM_AM_ShiftOpc Shift;
-	unsigned Op;
+
 	unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
 	unsigned type = fieldFromInstruction_4(Val, 5, 2);
 	unsigned imm = fieldFromInstruction_4(Val, 7, 5);
@@ -1262,36 +1548,35 @@ static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	Shift = ARM_AM_lsl;
+	ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
 	switch (type) {
-		case 0:
-			Shift = ARM_AM_lsl;
-			break;
-		case 1:
-			Shift = ARM_AM_lsr;
-			break;
-		case 2:
-			Shift = ARM_AM_asr;
-			break;
-		case 3:
-			Shift = ARM_AM_ror;
-			break;
+	case 0:
+		Shift = ARM_AM_lsl;
+		break;
+	case 1:
+		Shift = ARM_AM_lsr;
+		break;
+	case 2:
+		Shift = ARM_AM_asr;
+		break;
+	case 3:
+		Shift = ARM_AM_ror;
+		break;
 	}
 
 	if (Shift == ARM_AM_ror && imm == 0)
 		Shift = ARM_AM_rrx;
 
-	Op = Shift | (imm << 3);
-	MCOperand_CreateImm0(Inst, Op);
+	unsigned Op = Shift | (imm << 3);
+	MCOperand_CreateImm0(Inst, (Op));
 
 	return S;
 }
 
 static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	ARM_AM_ShiftOpc Shift;
 
 	unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
 	unsigned type = fieldFromInstruction_4(Val, 5, 2);
@@ -1303,65 +1588,74 @@ static DecodeStatus DecodeSORegRegOperand(MCInst *Inst, unsigned Val,
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	Shift = ARM_AM_lsl;
+	ARM_AM_ShiftOpc Shift = ARM_AM_lsl;
 	switch (type) {
-		case 0:
-			Shift = ARM_AM_lsl;
-			break;
-		case 1:
-			Shift = ARM_AM_lsr;
-			break;
-		case 2:
-			Shift = ARM_AM_asr;
-			break;
-		case 3:
-			Shift = ARM_AM_ror;
-			break;
+	case 0:
+		Shift = ARM_AM_lsl;
+		break;
+	case 1:
+		Shift = ARM_AM_lsr;
+		break;
+	case 2:
+		Shift = ARM_AM_asr;
+		break;
+	case 3:
+		Shift = ARM_AM_ror;
+		break;
 	}
 
-	MCOperand_CreateImm0(Inst, Shift);
+	MCOperand_CreateImm0(Inst, (Shift));
 
 	return S;
 }
 
 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
-	unsigned i;
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned opcode;
+
 	bool NeedDisjointWriteback = false;
 	unsigned WritebackReg = 0;
-
-	opcode = MCInst_getOpcode(Inst);
-	switch (opcode) {
-		default:
-			break;
-
-		case ARM_LDMIA_UPD:
-		case ARM_LDMDB_UPD:
-		case ARM_LDMIB_UPD:
-		case ARM_LDMDA_UPD:
-		case ARM_t2LDMIA_UPD:
-		case ARM_t2LDMDB_UPD:
-		case ARM_t2STMIA_UPD:
-		case ARM_t2STMDB_UPD:
-			NeedDisjointWriteback = true;
-			WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, 0));
-			break;
+	bool CLRM = false;
+	switch (MCInst_getOpcode(Inst)) {
+	default:
+		break;
+	case ARM_LDMIA_UPD:
+	case ARM_LDMDB_UPD:
+	case ARM_LDMIB_UPD:
+	case ARM_LDMDA_UPD:
+	case ARM_t2LDMIA_UPD:
+	case ARM_t2LDMDB_UPD:
+	case ARM_t2STMIA_UPD:
+	case ARM_t2STMDB_UPD:
+		NeedDisjointWriteback = true;
+		WritebackReg = MCOperand_getReg(MCInst_getOperand(Inst, (0)));
+		break;
+	case ARM_t2CLRM:
+		CLRM = true;
+		break;
 	}
 
 	// Empty register lists are not allowed.
-	if (Val == 0) return MCDisassembler_Fail;
-
-	for (i = 0; i < 16; ++i) {
+	if (Val == 0)
+		return MCDisassembler_Fail;
+	for (unsigned i = 0; i < 16; ++i) {
 		if (Val & (1 << i)) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
-				return MCDisassembler_Fail;
-
-			// Writeback not allowed if Rn is in the target list.
-			if (NeedDisjointWriteback && WritebackReg == MCOperand_getReg(&(Inst->Operands[Inst->size - 1])))
-				Check(&S, MCDisassembler_SoftFail);
+			if (CLRM) {
+				if (!Check(&S, DecodeCLRMGPRRegisterClass(Inst, i, Address,
+														  Decoder))) {
+					return MCDisassembler_Fail;
+				}
+			} else {
+				if (!Check(&S,
+						   DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
+					return MCDisassembler_Fail;
+				// Writeback not allowed if Rn is in the target list.
+				if (NeedDisjointWriteback &&
+					WritebackReg ==
+						MCOperand_getReg(&(Inst->Operands[Inst->size - 1])))
+					Check(&S, MCDisassembler_SoftFail);
+			}
 		}
 	}
 
@@ -1369,24 +1663,24 @@ static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
 }
 
 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned i;
+
 	unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
 	unsigned regs = fieldFromInstruction_4(Val, 0, 8);
 
 	// In case of unpredictable encoding, tweak the operands.
 	if (regs == 0 || (Vd + regs) > 32) {
 		regs = Vd + regs > 32 ? 32 - Vd : regs;
-		regs = (1u > regs? 1u : regs);
+		regs = regs > 1u ? regs : 1u;
 		S = MCDisassembler_SoftFail;
 	}
 
 	if (!Check(&S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	for (i = 0; i < (regs - 1); ++i) {
+	for (unsigned i = 0; i < (regs - 1); ++i) {
 		if (!Check(&S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
 			return MCDisassembler_Fail;
 	}
@@ -1395,25 +1689,25 @@ static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
 }
 
 static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned i;
+
 	unsigned Vd = fieldFromInstruction_4(Val, 8, 5);
 	unsigned regs = fieldFromInstruction_4(Val, 1, 7);
 
 	// In case of unpredictable encoding, tweak the operands.
 	if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
 		regs = Vd + regs > 32 ? 32 - Vd : regs;
-		regs = (1u > regs? 1u : regs);
-		regs = (16u > regs? regs : 16u);
+		regs = regs > 1u ? regs : 1u;
+		regs = regs < 16u ? regs : 16u;
 		S = MCDisassembler_SoftFail;
 	}
 
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	for (i = 0; i < (regs - 1); ++i) {
+	for (unsigned i = 0; i < (regs - 1); ++i) {
 		if (!Check(&S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
 			return MCDisassembler_Fail;
 	}
@@ -1422,7 +1716,8 @@ static DecodeStatus DecodeDPRRegListOperand(MCInst *Inst, unsigned Val,
 }
 
 static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											  uint64_t Address,
+											  const void *Decoder)
 {
 	// This operand encodes a mask of contiguous zeros between a specified MSB
 	// and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
@@ -1431,7 +1726,6 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
 	// create the final mask.
 	unsigned msb = fieldFromInstruction_4(Val, 5, 5);
 	unsigned lsb = fieldFromInstruction_4(Val, 0, 5);
-	uint32_t lsb_mask, msb_mask;
 
 	DecodeStatus S = MCDisassembler_Success;
 	if (lsb > msb) {
@@ -1442,19 +1736,23 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst *Inst, unsigned Val,
 		lsb = msb;
 	}
 
-	msb_mask = 0xFFFFFFFF;
-	if (msb != 31) msb_mask = (1U << (msb + 1)) - 1;
-	lsb_mask = (1U << lsb) - 1;
+	uint32_t msb_mask = 0xFFFFFFFF;
+	if (msb != 31)
+		msb_mask = (1U << (msb + 1)) - 1;
+	uint32_t lsb_mask = (1U << lsb) - 1;
 
-	MCOperand_CreateImm0(Inst, ~(msb_mask ^ lsb_mask));
+	MCOperand_CreateImm0(Inst, (~(msb_mask ^ lsb_mask)));
 	return S;
 }
 
 static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
+	unsigned P = fieldFromInstruction_4(Insn, 24, 1);
+	unsigned W = fieldFromInstruction_4(Insn, 21, 1);
 	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 	unsigned CRd = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned coproc = fieldFromInstruction_4(Insn, 8, 4);
@@ -1462,149 +1760,184 @@ static DecodeStatus DecodeCopMemInstruction(MCInst *Inst, unsigned Insn,
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned U = fieldFromInstruction_4(Insn, 23, 1);
 
+	// Pre-Indexed implies writeback to Rn
+	bool IsPreIndexed = (P == 1) && (W == 1);
+
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_LDC_OFFSET:
-		case ARM_LDC_PRE:
-		case ARM_LDC_POST:
-		case ARM_LDC_OPTION:
-		case ARM_LDCL_OFFSET:
-		case ARM_LDCL_PRE:
-		case ARM_LDCL_POST:
-		case ARM_LDCL_OPTION:
-		case ARM_STC_OFFSET:
-		case ARM_STC_PRE:
-		case ARM_STC_POST:
-		case ARM_STC_OPTION:
-		case ARM_STCL_OFFSET:
-		case ARM_STCL_PRE:
-		case ARM_STCL_POST:
-		case ARM_STCL_OPTION:
-		case ARM_t2LDC_OFFSET:
-		case ARM_t2LDC_PRE:
-		case ARM_t2LDC_POST:
-		case ARM_t2LDC_OPTION:
-		case ARM_t2LDCL_OFFSET:
-		case ARM_t2LDCL_PRE:
-		case ARM_t2LDCL_POST:
-		case ARM_t2LDCL_OPTION:
-		case ARM_t2STC_OFFSET:
-		case ARM_t2STC_PRE:
-		case ARM_t2STC_POST:
-		case ARM_t2STC_OPTION:
-		case ARM_t2STCL_OFFSET:
-		case ARM_t2STCL_PRE:
-		case ARM_t2STCL_POST:
-		case ARM_t2STCL_OPTION:
-			if (coproc == 0xA || coproc == 0xB)
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_LDC_OFFSET:
+	case ARM_LDC_PRE:
+	case ARM_LDC_POST:
+	case ARM_LDC_OPTION:
+	case ARM_LDCL_OFFSET:
+	case ARM_LDCL_PRE:
+	case ARM_LDCL_POST:
+	case ARM_LDCL_OPTION:
+	case ARM_STC_OFFSET:
+	case ARM_STC_PRE:
+	case ARM_STC_POST:
+	case ARM_STC_OPTION:
+	case ARM_STCL_OFFSET:
+	case ARM_STCL_PRE:
+	case ARM_STCL_POST:
+	case ARM_STCL_OPTION:
+	case ARM_t2LDC_OFFSET:
+	case ARM_t2LDC_PRE:
+	case ARM_t2LDC_POST:
+	case ARM_t2LDC_OPTION:
+	case ARM_t2LDCL_OFFSET:
+	case ARM_t2LDCL_PRE:
+	case ARM_t2LDCL_POST:
+	case ARM_t2LDCL_OPTION:
+	case ARM_t2STC_OFFSET:
+	case ARM_t2STC_PRE:
+	case ARM_t2STC_POST:
+	case ARM_t2STC_OPTION:
+	case ARM_t2STCL_OFFSET:
+	case ARM_t2STCL_PRE:
+	case ARM_t2STCL_POST:
+	case ARM_t2STCL_OPTION:
+	case ARM_t2LDC2_OFFSET:
+	case ARM_t2LDC2L_OFFSET:
+	case ARM_t2LDC2_PRE:
+	case ARM_t2LDC2L_PRE:
+	case ARM_t2STC2_OFFSET:
+	case ARM_t2STC2L_OFFSET:
+	case ARM_t2STC2_PRE:
+	case ARM_t2STC2L_PRE:
+	case ARM_LDC2_OFFSET:
+	case ARM_LDC2L_OFFSET:
+	case ARM_LDC2_PRE:
+	case ARM_LDC2L_PRE:
+	case ARM_STC2_OFFSET:
+	case ARM_STC2L_OFFSET:
+	case ARM_STC2_PRE:
+	case ARM_STC2L_PRE:
+	case ARM_t2LDC2_OPTION:
+	case ARM_t2STC2_OPTION:
+	case ARM_t2LDC2_POST:
+	case ARM_t2LDC2L_POST:
+	case ARM_t2STC2_POST:
+	case ARM_t2STC2L_POST:
+	case ARM_LDC2_POST:
+	case ARM_LDC2L_POST:
+	case ARM_STC2_POST:
+	case ARM_STC2L_POST:
+		if (coproc == 0xA || coproc == 0xB ||
+			(ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) &&
+			 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA ||
+			  coproc == 0xB || coproc == 0xE || coproc == 0xF)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (coproc != 14))
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, coproc);
-	MCOperand_CreateImm0(Inst, CRd);
+	if (IsPreIndexed)
+		// Dummy operand for Rn_wb.
+		MCOperand_CreateImm0(Inst, (0));
+
+	MCOperand_CreateImm0(Inst, (coproc));
+	MCOperand_CreateImm0(Inst, (CRd));
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2LDC2_OFFSET:
-		case ARM_t2LDC2L_OFFSET:
-		case ARM_t2LDC2_PRE:
-		case ARM_t2LDC2L_PRE:
-		case ARM_t2STC2_OFFSET:
-		case ARM_t2STC2L_OFFSET:
-		case ARM_t2STC2_PRE:
-		case ARM_t2STC2L_PRE:
-		case ARM_LDC2_OFFSET:
-		case ARM_LDC2L_OFFSET:
-		case ARM_LDC2_PRE:
-		case ARM_LDC2L_PRE:
-		case ARM_STC2_OFFSET:
-		case ARM_STC2L_OFFSET:
-		case ARM_STC2_PRE:
-		case ARM_STC2L_PRE:
-		case ARM_t2LDC_OFFSET:
-		case ARM_t2LDCL_OFFSET:
-		case ARM_t2LDC_PRE:
-		case ARM_t2LDCL_PRE:
-		case ARM_t2STC_OFFSET:
-		case ARM_t2STCL_OFFSET:
-		case ARM_t2STC_PRE:
-		case ARM_t2STCL_PRE:
-		case ARM_LDC_OFFSET:
-		case ARM_LDCL_OFFSET:
-		case ARM_LDC_PRE:
-		case ARM_LDCL_PRE:
-		case ARM_STC_OFFSET:
-		case ARM_STCL_OFFSET:
-		case ARM_STC_PRE:
-		case ARM_STCL_PRE:
-			imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, (unsigned char)imm);
-			MCOperand_CreateImm0(Inst, imm);
-			break;
-		case ARM_t2LDC2_POST:
-		case ARM_t2LDC2L_POST:
-		case ARM_t2STC2_POST:
-		case ARM_t2STC2L_POST:
-		case ARM_LDC2_POST:
-		case ARM_LDC2L_POST:
-		case ARM_STC2_POST:
-		case ARM_STC2L_POST:
-		case ARM_t2LDC_POST:
-		case ARM_t2LDCL_POST:
-		case ARM_t2STC_POST:
-		case ARM_t2STCL_POST:
-		case ARM_LDC_POST:
-		case ARM_LDCL_POST:
-		case ARM_STC_POST:
-		case ARM_STCL_POST:
-			imm |= U << 8;
-			// fall through.
-		default:
-			// The 'option' variant doesn't encode 'U' in the immediate since
-			// the immediate is unsigned [0,255].
-			MCOperand_CreateImm0(Inst, imm);
-			break;
+	case ARM_t2LDC2_OFFSET:
+	case ARM_t2LDC2L_OFFSET:
+	case ARM_t2LDC2_PRE:
+	case ARM_t2LDC2L_PRE:
+	case ARM_t2STC2_OFFSET:
+	case ARM_t2STC2L_OFFSET:
+	case ARM_t2STC2_PRE:
+	case ARM_t2STC2L_PRE:
+	case ARM_LDC2_OFFSET:
+	case ARM_LDC2L_OFFSET:
+	case ARM_LDC2_PRE:
+	case ARM_LDC2L_PRE:
+	case ARM_STC2_OFFSET:
+	case ARM_STC2L_OFFSET:
+	case ARM_STC2_PRE:
+	case ARM_STC2L_PRE:
+	case ARM_t2LDC_OFFSET:
+	case ARM_t2LDCL_OFFSET:
+	case ARM_t2LDC_PRE:
+	case ARM_t2LDCL_PRE:
+	case ARM_t2STC_OFFSET:
+	case ARM_t2STCL_OFFSET:
+	case ARM_t2STC_PRE:
+	case ARM_t2STCL_PRE:
+	case ARM_LDC_OFFSET:
+	case ARM_LDCL_OFFSET:
+	case ARM_LDC_PRE:
+	case ARM_LDCL_PRE:
+	case ARM_STC_OFFSET:
+	case ARM_STCL_OFFSET:
+	case ARM_STC_PRE:
+	case ARM_STCL_PRE:
+		imm = ARM_AM_getAM5Opc(U ? ARM_AM_add : ARM_AM_sub, imm);
+		MCOperand_CreateImm0(Inst, (imm));
+		break;
+	case ARM_t2LDC2_POST:
+	case ARM_t2LDC2L_POST:
+	case ARM_t2STC2_POST:
+	case ARM_t2STC2L_POST:
+	case ARM_LDC2_POST:
+	case ARM_LDC2L_POST:
+	case ARM_STC2_POST:
+	case ARM_STC2L_POST:
+	case ARM_t2LDC_POST:
+	case ARM_t2LDCL_POST:
+	case ARM_t2STC_POST:
+	case ARM_t2STCL_POST:
+	case ARM_LDC_POST:
+	case ARM_LDCL_POST:
+	case ARM_STC_POST:
+	case ARM_STCL_POST:
+		imm |= U << 8;
+		// fall through
+	default:
+		// The 'option' variant doesn't encode 'U' in the immediate since
+		// the immediate is unsigned [0,255].
+		MCOperand_CreateImm0(Inst, (imm));
+		break;
 	}
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_LDC_OFFSET:
-		case ARM_LDC_PRE:
-		case ARM_LDC_POST:
-		case ARM_LDC_OPTION:
-		case ARM_LDCL_OFFSET:
-		case ARM_LDCL_PRE:
-		case ARM_LDCL_POST:
-		case ARM_LDCL_OPTION:
-		case ARM_STC_OFFSET:
-		case ARM_STC_PRE:
-		case ARM_STC_POST:
-		case ARM_STC_OPTION:
-		case ARM_STCL_OFFSET:
-		case ARM_STCL_PRE:
-		case ARM_STCL_POST:
-		case ARM_STCL_OPTION:
-			if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_LDC_OFFSET:
+	case ARM_LDC_PRE:
+	case ARM_LDC_POST:
+	case ARM_LDC_OPTION:
+	case ARM_LDCL_OFFSET:
+	case ARM_LDCL_PRE:
+	case ARM_LDCL_POST:
+	case ARM_LDCL_OPTION:
+	case ARM_STC_OFFSET:
+	case ARM_STC_PRE:
+	case ARM_STC_POST:
+	case ARM_STC_OPTION:
+	case ARM_STCL_OFFSET:
+	case ARM_STCL_PRE:
+	case ARM_STCL_POST:
+	case ARM_STCL_OPTION:
+		if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	return S;
 }
 
 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+												  uint64_t Address,
+												  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	ARM_AM_AddrOpc Op;
-	ARM_AM_ShiftOpc Opc;
-	bool writeback;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
@@ -1613,23 +1946,22 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
 	unsigned reg = fieldFromInstruction_4(Insn, 25, 1);
 	unsigned P = fieldFromInstruction_4(Insn, 24, 1);
 	unsigned W = fieldFromInstruction_4(Insn, 21, 1);
-	unsigned idx_mode = 0, amt, tmp;
 
 	// On stores, the writeback operand precedes Rt.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_STR_POST_IMM:
-		case ARM_STR_POST_REG:
-		case ARM_STRB_POST_IMM:
-		case ARM_STRB_POST_REG:
-		case ARM_STRT_POST_REG:
-		case ARM_STRT_POST_IMM:
-		case ARM_STRBT_POST_REG:
-		case ARM_STRBT_POST_IMM:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_STR_POST_IMM:
+	case ARM_STR_POST_REG:
+	case ARM_STRB_POST_IMM:
+	case ARM_STRB_POST_REG:
+	case ARM_STRT_POST_REG:
+	case ARM_STRT_POST_IMM:
+	case ARM_STRBT_POST_REG:
+	case ARM_STRBT_POST_IMM:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@@ -1637,29 +1969,30 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
 
 	// On loads, the writeback operand comes after Rt.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_LDR_POST_IMM:
-		case ARM_LDR_POST_REG:
-		case ARM_LDRB_POST_IMM:
-		case ARM_LDRB_POST_REG:
-		case ARM_LDRBT_POST_REG:
-		case ARM_LDRBT_POST_IMM:
-		case ARM_LDRT_POST_REG:
-		case ARM_LDRT_POST_IMM:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_LDR_POST_IMM:
+	case ARM_LDR_POST_REG:
+	case ARM_LDRB_POST_IMM:
+	case ARM_LDRB_POST_REG:
+	case ARM_LDRBT_POST_REG:
+	case ARM_LDRBT_POST_IMM:
+	case ARM_LDRT_POST_REG:
+	case ARM_LDRT_POST_IMM:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	Op = ARM_AM_add;
+	ARM_AM_AddrOpc Op = ARM_AM_add;
 	if (!fieldFromInstruction_4(Insn, 23, 1))
 		Op = ARM_AM_sub;
 
-	writeback = (P == 0) || (W == 1);
+	bool writeback = (P == 0) || (W == 1);
+	unsigned idx_mode = 0;
 	if (P && writeback)
 		idx_mode = ARMII_IndexModePre;
 	else if (!P && writeback)
@@ -1671,36 +2004,33 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
 	if (reg) {
 		if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
 			return MCDisassembler_Fail;
-
-		Opc = ARM_AM_lsl;
-		switch(fieldFromInstruction_4(Insn, 5, 2)) {
-			case 0:
-				Opc = ARM_AM_lsl;
-				break;
-			case 1:
-				Opc = ARM_AM_lsr;
-				break;
-			case 2:
-				Opc = ARM_AM_asr;
-				break;
-			case 3:
-				Opc = ARM_AM_ror;
-				break;
-			default:
-				return MCDisassembler_Fail;
+		ARM_AM_ShiftOpc Opc = ARM_AM_lsl;
+		switch (fieldFromInstruction_4(Insn, 5, 2)) {
+		case 0:
+			Opc = ARM_AM_lsl;
+			break;
+		case 1:
+			Opc = ARM_AM_lsr;
+			break;
+		case 2:
+			Opc = ARM_AM_asr;
+			break;
+		case 3:
+			Opc = ARM_AM_ror;
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
-
-		amt = fieldFromInstruction_4(Insn, 7, 5);
+		unsigned amt = fieldFromInstruction_4(Insn, 7, 5);
 		if (Opc == ARM_AM_ror && amt == 0)
 			Opc = ARM_AM_rrx;
+		unsigned imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
 
-		imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode);
-
-		MCOperand_CreateImm0(Inst, imm);
+		MCOperand_CreateImm0(Inst, (imm));
 	} else {
-		MCOperand_CreateReg0(Inst, 0);
-		tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
-		MCOperand_CreateImm0(Inst, tmp);
+		MCOperand_CreateReg0(Inst, (0));
+		unsigned tmp = ARM_AM_getAM2Opc(Op, imm, ARM_AM_lsl, idx_mode);
+		MCOperand_CreateImm0(Inst, (tmp));
 	}
 
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1710,31 +2040,30 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	ARM_AM_ShiftOpc ShOp;
-	unsigned shift;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
-	unsigned Rm = fieldFromInstruction_4(Val,  0, 4);
+	unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
 	unsigned type = fieldFromInstruction_4(Val, 5, 2);
 	unsigned imm = fieldFromInstruction_4(Val, 7, 5);
 	unsigned U = fieldFromInstruction_4(Val, 12, 1);
 
-	ShOp = ARM_AM_lsl;
+	ARM_AM_ShiftOpc ShOp = ARM_AM_lsl;
 	switch (type) {
-		case 0:
-			ShOp = ARM_AM_lsl;
-			break;
-		case 1:
-			ShOp = ARM_AM_lsr;
-			break;
-		case 2:
-			ShOp = ARM_AM_asr;
-			break;
-		case 3:
-			ShOp = ARM_AM_ror;
-			break;
+	case 0:
+		ShOp = ARM_AM_lsl;
+		break;
+	case 1:
+		ShOp = ARM_AM_lsr;
+		break;
+	case 2:
+		ShOp = ARM_AM_asr;
+		break;
+	case 3:
+		ShOp = ARM_AM_ror;
+		break;
 	}
 
 	if (ShOp == ARM_AM_ror && imm == 0)
@@ -1742,22 +2071,35 @@ static DecodeStatus DecodeSORegMemOperand(MCInst *Inst, unsigned Val,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
+	unsigned shift;
 	if (U)
 		shift = ARM_AM_getAM2Opc(ARM_AM_add, imm, ShOp, 0);
 	else
 		shift = ARM_AM_getAM2Opc(ARM_AM_sub, imm, ShOp, 0);
-
-	MCOperand_CreateImm0(Inst, shift);
+	MCOperand_CreateImm0(Inst, (shift));
 
 	return S;
 }
 
+static DecodeStatus DecodeTSBInstruction(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder)
+{
+	if (MCInst_getOpcode(Inst) != ARM_TSB &&
+		MCInst_getOpcode(Inst) != ARM_t2TSB)
+		return MCDisassembler_Fail;
+
+	// The "csync" operand is not encoded into the "tsb" instruction (as this is
+	// the only available operand), but LLVM expects the instruction to have one
+	// operand, so we need to add the csync when decoding.
+	MCOperand_CreateImm0(Inst, (ARM_TSB_CSYNC));
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -1776,126 +2118,99 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
 
 	// For {LD,ST}RD, Rt must be even, else undefined.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_STRD:
-		case ARM_STRD_PRE:
-		case ARM_STRD_POST:
-		case ARM_LDRD:
-		case ARM_LDRD_PRE:
-		case ARM_LDRD_POST:
-			if (Rt & 0x1)
-				S = MCDisassembler_SoftFail;
-			break;
-		default:
-			break;
+	case ARM_STRD:
+	case ARM_STRD_PRE:
+	case ARM_STRD_POST:
+	case ARM_LDRD:
+	case ARM_LDRD_PRE:
+	case ARM_LDRD_POST:
+		if (Rt & 0x1)
+			S = MCDisassembler_SoftFail;
+		break;
+	default:
+		break;
 	}
-
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_STRD:
-		case ARM_STRD_PRE:
-		case ARM_STRD_POST:
-			if (P == 0 && W == 1)
-				S = MCDisassembler_SoftFail;
-
-			if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
-				S = MCDisassembler_SoftFail;
-
-			if (type && Rm == 15)
-				S = MCDisassembler_SoftFail;
+	case ARM_STRD:
+	case ARM_STRD_PRE:
+	case ARM_STRD_POST:
+		if (P == 0 && W == 1)
+			S = MCDisassembler_SoftFail;
 
+		if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
+			S = MCDisassembler_SoftFail;
+		if (type && Rm == 15)
+			S = MCDisassembler_SoftFail;
+		if (Rt2 == 15)
+			S = MCDisassembler_SoftFail;
+		if (!type && fieldFromInstruction_4(Insn, 8, 4))
+			S = MCDisassembler_SoftFail;
+		break;
+	case ARM_STRH:
+	case ARM_STRH_PRE:
+	case ARM_STRH_POST:
+		if (Rt == 15)
+			S = MCDisassembler_SoftFail;
+		if (writeback && (Rn == 15 || Rn == Rt))
+			S = MCDisassembler_SoftFail;
+		if (!type && Rm == 15)
+			S = MCDisassembler_SoftFail;
+		break;
+	case ARM_LDRD:
+	case ARM_LDRD_PRE:
+	case ARM_LDRD_POST:
+		if (type && Rn == 15) {
 			if (Rt2 == 15)
 				S = MCDisassembler_SoftFail;
-
-			if (!type && fieldFromInstruction_4(Insn, 8, 4))
-				S = MCDisassembler_SoftFail;
-
 			break;
-
-		case ARM_STRH:
-		case ARM_STRH_PRE:
-		case ARM_STRH_POST:
+		}
+		if (P == 0 && W == 1)
+			S = MCDisassembler_SoftFail;
+		if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
+			S = MCDisassembler_SoftFail;
+		if (!type && writeback && Rn == 15)
+			S = MCDisassembler_SoftFail;
+		if (writeback && (Rn == Rt || Rn == Rt2))
+			S = MCDisassembler_SoftFail;
+		break;
+	case ARM_LDRH:
+	case ARM_LDRH_PRE:
+	case ARM_LDRH_POST:
+		if (type && Rn == 15) {
 			if (Rt == 15)
 				S = MCDisassembler_SoftFail;
-
-			if (writeback && (Rn == 15 || Rn == Rt))
-				S = MCDisassembler_SoftFail;
-
-			if (!type && Rm == 15)
-				S = MCDisassembler_SoftFail;
-
 			break;
-
-		case ARM_LDRD:
-		case ARM_LDRD_PRE:
-		case ARM_LDRD_POST:
-			if (type && Rn == 15) {
-				if (Rt2 == 15)
-					S = MCDisassembler_SoftFail;
-				break;
-			}
-
-			if (P == 0 && W == 1)
-				S = MCDisassembler_SoftFail;
-
-			if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
-				S = MCDisassembler_SoftFail;
-
-			if (!type && writeback && Rn == 15)
-				S = MCDisassembler_SoftFail;
-
-			if (writeback && (Rn == Rt || Rn == Rt2))
-				S = MCDisassembler_SoftFail;
-
-			break;
-
-		case ARM_LDRH:
-		case ARM_LDRH_PRE:
-		case ARM_LDRH_POST:
-			if (type && Rn == 15) {
-				if (Rt == 15)
-					S = MCDisassembler_SoftFail;
-				break;
-			}
-
+		}
+		if (Rt == 15)
+			S = MCDisassembler_SoftFail;
+		if (!type && Rm == 15)
+			S = MCDisassembler_SoftFail;
+		if (!type && writeback && (Rn == 15 || Rn == Rt))
+			S = MCDisassembler_SoftFail;
+		break;
+	case ARM_LDRSH:
+	case ARM_LDRSH_PRE:
+	case ARM_LDRSH_POST:
+	case ARM_LDRSB:
+	case ARM_LDRSB_PRE:
+	case ARM_LDRSB_POST:
+		if (type && Rn == 15) {
 			if (Rt == 15)
 				S = MCDisassembler_SoftFail;
-
-			if (!type && Rm == 15)
-				S = MCDisassembler_SoftFail;
-
-			if (!type && writeback && (Rn == 15 || Rn == Rt))
-				S = MCDisassembler_SoftFail;
-			break;
-
-		case ARM_LDRSH:
-		case ARM_LDRSH_PRE:
-		case ARM_LDRSH_POST:
-		case ARM_LDRSB:
-		case ARM_LDRSB_PRE:
-		case ARM_LDRSB_POST:
-			if (type && Rn == 15){
-				if (Rt == 15)
-					S = MCDisassembler_SoftFail;
-				break;
-			}
-
-			if (type && (Rt == 15 || (writeback && Rn == Rt)))
-				S = MCDisassembler_SoftFail;
-
-			if (!type && (Rt == 15 || Rm == 15))
-				S = MCDisassembler_SoftFail;
-
-			if (!type && writeback && (Rn == 15 || Rn == Rt))
-				S = MCDisassembler_SoftFail;
-
-			break;
-
-		default:
 			break;
+		}
+		if (type && (Rt == 15 || (writeback && Rn == Rt)))
+			S = MCDisassembler_SoftFail;
+		if (!type && (Rt == 15 || Rm == 15))
+			S = MCDisassembler_SoftFail;
+		if (!type && writeback && (Rn == 15 || Rn == Rt))
+			S = MCDisassembler_SoftFail;
+		break;
+	default:
+		break;
 	}
 
 	if (writeback) { // Writeback
-		Inst->writeback = true;
-
 		if (P)
 			U |= ARMII_IndexModePre << 9;
 		else
@@ -1903,59 +2218,58 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
 
 		// On stores, the writeback operand precedes Rt.
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_STRD:
-			case ARM_STRD_PRE:
-			case ARM_STRD_POST:
-			case ARM_STRH:
-			case ARM_STRH_PRE:
-			case ARM_STRH_POST:
-				if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-					return MCDisassembler_Fail;
-				break;
-			default:
-				break;
+		case ARM_STRD:
+		case ARM_STRD_PRE:
+		case ARM_STRD_POST:
+		case ARM_STRH:
+		case ARM_STRH_PRE:
+		case ARM_STRH_POST:
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+				return MCDisassembler_Fail;
+			break;
+		default:
+			break;
 		}
 	}
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_STRD:
-		case ARM_STRD_PRE:
-		case ARM_STRD_POST:
-		case ARM_LDRD:
-		case ARM_LDRD_PRE:
-		case ARM_LDRD_POST:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_STRD:
+	case ARM_STRD_PRE:
+	case ARM_STRD_POST:
+	case ARM_LDRD:
+	case ARM_LDRD_PRE:
+	case ARM_LDRD_POST:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt + 1, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	if (writeback) {
 		// On loads, the writeback operand comes after Rt.
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_LDRD:
-			case ARM_LDRD_PRE:
-			case ARM_LDRD_POST:
-			case ARM_LDRH:
-			case ARM_LDRH_PRE:
-			case ARM_LDRH_POST:
-			case ARM_LDRSH:
-			case ARM_LDRSH_PRE:
-			case ARM_LDRSH_POST:
-			case ARM_LDRSB:
-			case ARM_LDRSB_PRE:
-			case ARM_LDRSB_POST:
-			case ARM_LDRHTr:
-			case ARM_LDRSBTr:
-				if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-					return MCDisassembler_Fail;
-				break;
-			default:
-				break;
+		case ARM_LDRD:
+		case ARM_LDRD_PRE:
+		case ARM_LDRD_POST:
+		case ARM_LDRH:
+		case ARM_LDRH_PRE:
+		case ARM_LDRH_POST:
+		case ARM_LDRSH:
+		case ARM_LDRSH_PRE:
+		case ARM_LDRSH_POST:
+		case ARM_LDRSB:
+		case ARM_LDRSB_PRE:
+		case ARM_LDRSB_POST:
+		case ARM_LDRHTr:
+		case ARM_LDRSBTr:
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+				return MCDisassembler_Fail;
+			break;
+		default:
+			break;
 		}
 	}
 
@@ -1963,13 +2277,12 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
 		return MCDisassembler_Fail;
 
 	if (type) {
-		MCOperand_CreateReg0(Inst, 0);
-		MCOperand_CreateImm0(Inst, U | (imm << 4) | Rm);
+		MCOperand_CreateReg0(Inst, (0));
+		MCOperand_CreateImm0(Inst, (U | (imm << 4) | Rm));
 	} else {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 			return MCDisassembler_Fail;
-
-		MCOperand_CreateImm0(Inst, U);
+		MCOperand_CreateImm0(Inst, (U));
 	}
 
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1979,7 +2292,7 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -1987,22 +2300,21 @@ static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn,
 	unsigned mode = fieldFromInstruction_4(Insn, 23, 2);
 
 	switch (mode) {
-		case 0:
-			mode = ARM_AM_da;
-			break;
-		case 1:
-			mode = ARM_AM_ia;
-			break;
-		case 2:
-			mode = ARM_AM_db;
-			break;
-		case 3:
-			mode = ARM_AM_ib;
-			break;
+	case 0:
+		mode = ARM_AM_da;
+		break;
+	case 1:
+		mode = ARM_AM_ia;
+		break;
+	case 2:
+		mode = ARM_AM_db;
+		break;
+	case 3:
+		mode = ARM_AM_ib;
+		break;
 	}
 
-	MCOperand_CreateImm0(Inst, mode);
-
+	MCOperand_CreateImm0(Inst, (mode));
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -2010,7 +2322,7 @@ static DecodeStatus DecodeRFEInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2024,21 +2336,19 @@ static DecodeStatus DecodeQADDInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	return S;
 }
 
 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
-		unsigned Insn, uint64_t Address, const void *Decoder)
+														  unsigned Insn,
+														  uint64_t Address,
+														  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2049,66 +2359,66 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
 	if (pred == 0xF) {
 		// Ambiguous with RFE and SRS
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_LDMDA:
-				MCInst_setOpcode(Inst, ARM_RFEDA);
-				break;
-			case ARM_LDMDA_UPD:
-				MCInst_setOpcode(Inst, ARM_RFEDA_UPD);
-				break;
-			case ARM_LDMDB:
-				MCInst_setOpcode(Inst, ARM_RFEDB);
-				break;
-			case ARM_LDMDB_UPD:
-				MCInst_setOpcode(Inst, ARM_RFEDB_UPD);
-				break;
-			case ARM_LDMIA:
-				MCInst_setOpcode(Inst, ARM_RFEIA);
-				break;
-			case ARM_LDMIA_UPD:
-				MCInst_setOpcode(Inst, ARM_RFEIA_UPD);
-				break;
-			case ARM_LDMIB:
-				MCInst_setOpcode(Inst, ARM_RFEIB);
-				break;
-			case ARM_LDMIB_UPD:
-				MCInst_setOpcode(Inst, ARM_RFEIB_UPD);
-				break;
-			case ARM_STMDA:
-				MCInst_setOpcode(Inst, ARM_SRSDA);
-				break;
-			case ARM_STMDA_UPD:
-				MCInst_setOpcode(Inst, ARM_SRSDA_UPD);
-				break;
-			case ARM_STMDB:
-				MCInst_setOpcode(Inst, ARM_SRSDB);
-				break;
-			case ARM_STMDB_UPD:
-				MCInst_setOpcode(Inst, ARM_SRSDB_UPD);
-				break;
-			case ARM_STMIA:
-				MCInst_setOpcode(Inst, ARM_SRSIA);
-				break;
-			case ARM_STMIA_UPD:
-				MCInst_setOpcode(Inst, ARM_SRSIA_UPD);
-				break;
-			case ARM_STMIB:
-				MCInst_setOpcode(Inst, ARM_SRSIB);
-				break;
-			case ARM_STMIB_UPD:
-				MCInst_setOpcode(Inst, ARM_SRSIB_UPD);
-				break;
-			default:
-				return MCDisassembler_Fail;
+		case ARM_LDMDA:
+			MCInst_setOpcode(Inst, (ARM_RFEDA));
+			break;
+		case ARM_LDMDA_UPD:
+			MCInst_setOpcode(Inst, (ARM_RFEDA_UPD));
+			break;
+		case ARM_LDMDB:
+			MCInst_setOpcode(Inst, (ARM_RFEDB));
+			break;
+		case ARM_LDMDB_UPD:
+			MCInst_setOpcode(Inst, (ARM_RFEDB_UPD));
+			break;
+		case ARM_LDMIA:
+			MCInst_setOpcode(Inst, (ARM_RFEIA));
+			break;
+		case ARM_LDMIA_UPD:
+			MCInst_setOpcode(Inst, (ARM_RFEIA_UPD));
+			break;
+		case ARM_LDMIB:
+			MCInst_setOpcode(Inst, (ARM_RFEIB));
+			break;
+		case ARM_LDMIB_UPD:
+			MCInst_setOpcode(Inst, (ARM_RFEIB_UPD));
+			break;
+		case ARM_STMDA:
+			MCInst_setOpcode(Inst, (ARM_SRSDA));
+			break;
+		case ARM_STMDA_UPD:
+			MCInst_setOpcode(Inst, (ARM_SRSDA_UPD));
+			break;
+		case ARM_STMDB:
+			MCInst_setOpcode(Inst, (ARM_SRSDB));
+			break;
+		case ARM_STMDB_UPD:
+			MCInst_setOpcode(Inst, (ARM_SRSDB_UPD));
+			break;
+		case ARM_STMIA:
+			MCInst_setOpcode(Inst, (ARM_SRSIA));
+			break;
+		case ARM_STMIA_UPD:
+			MCInst_setOpcode(Inst, (ARM_SRSIA_UPD));
+			break;
+		case ARM_STMIB:
+			MCInst_setOpcode(Inst, (ARM_SRSIB));
+			break;
+		case ARM_STMIB_UPD:
+			MCInst_setOpcode(Inst, (ARM_SRSIB_UPD));
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
 
 		// For stores (which become SRS's, the only operand is the mode.
 		if (fieldFromInstruction_4(Insn, 20, 1) == 0) {
 			// Check SRS encoding constraints
 			if (!(fieldFromInstruction_4(Insn, 22, 1) == 1 &&
-						fieldFromInstruction_4(Insn, 20, 1) == 0))
+				  fieldFromInstruction_4(Insn, 20, 1) == 0))
 				return MCDisassembler_Fail;
 
-			MCOperand_CreateImm0(Inst, fieldFromInstruction_4(Insn, 0, 4));
+			MCOperand_CreateImm0(Inst, (fieldFromInstruction_4(Insn, 0, 4)));
 			return S;
 		}
 
@@ -2117,13 +2427,10 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail; // Tied
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -2132,27 +2439,29 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst *Inst,
 
 // Check for UNPREDICTABLE predicated ESB instruction
 static DecodeStatus DecodeHINTInstruction(MCInst *Inst, unsigned Insn,
-                                 uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 	unsigned imm8 = fieldFromInstruction_4(Insn, 0, 8);
-	DecodeStatus result = MCDisassembler_Success;
 
-	MCOperand_CreateImm0(Inst, imm8);
+	DecodeStatus S = MCDisassembler_Success;
 
-	if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+	MCOperand_CreateImm0(Inst, (imm8));
+
+	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	// ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
-	// so all predicates should be allowed.
-	if (imm8 == 0x10 && pred != 0xe && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS))
-		result = MCDisassembler_SoftFail;
+	// ESB is unpredictable if pred != AL. Without the RAS extension, it is a
+	// NOP, so all predicates should be allowed.
+	if (imm8 == 0x10 && pred != 0xe &&
+		((ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureRAS)) != 0))
+		S = MCDisassembler_SoftFail;
 
-	return result;
+	return S;
 }
 
 static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	unsigned imod = fieldFromInstruction_4(Insn, 18, 2);
 	unsigned M = fieldFromInstruction_4(Insn, 17, 1);
@@ -2164,8 +2473,8 @@ static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
 	// This decoder is called from multiple location that do not check
 	// the full encoding is valid before they do.
 	if (fieldFromInstruction_4(Insn, 5, 1) != 0 ||
-			fieldFromInstruction_4(Insn, 16, 1) != 0 ||
-			fieldFromInstruction_4(Insn, 20, 8) != 0x10)
+		fieldFromInstruction_4(Insn, 16, 1) != 0 ||
+		fieldFromInstruction_4(Insn, 20, 8) != 0x10)
 		return MCDisassembler_Fail;
 
 	// imod == '01' --> UNPREDICTABLE
@@ -2173,26 +2482,29 @@ static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
 	// return failure here.  The '01' imod value is unprintable, so there's
 	// nothing useful we could do even if we returned UNPREDICTABLE.
 
-	if (imod == 1) return MCDisassembler_Fail;
+	if (imod == 1)
+		return MCDisassembler_Fail;
 
 	if (imod && M) {
-		MCInst_setOpcode(Inst, ARM_CPS3p);
-		MCOperand_CreateImm0(Inst, imod);
-		MCOperand_CreateImm0(Inst, iflags);
-		MCOperand_CreateImm0(Inst, mode);
+		MCInst_setOpcode(Inst, (ARM_CPS3p));
+		MCOperand_CreateImm0(Inst, (imod));
+		MCOperand_CreateImm0(Inst, (iflags));
+		MCOperand_CreateImm0(Inst, (mode));
 	} else if (imod && !M) {
-		MCInst_setOpcode(Inst, ARM_CPS2p);
-		MCOperand_CreateImm0(Inst, imod);
-		MCOperand_CreateImm0(Inst, iflags);
-		if (mode) S = MCDisassembler_SoftFail;
+		MCInst_setOpcode(Inst, (ARM_CPS2p));
+		MCOperand_CreateImm0(Inst, (imod));
+		MCOperand_CreateImm0(Inst, (iflags));
+		if (mode)
+			S = MCDisassembler_SoftFail;
 	} else if (!imod && M) {
-		MCInst_setOpcode(Inst, ARM_CPS1p);
-		MCOperand_CreateImm0(Inst, mode);
-		if (iflags) S = MCDisassembler_SoftFail;
+		MCInst_setOpcode(Inst, (ARM_CPS1p));
+		MCOperand_CreateImm0(Inst, (mode));
+		if (iflags)
+			S = MCDisassembler_SoftFail;
 	} else {
 		// imod == '00' && M == '0' --> UNPREDICTABLE
-		MCInst_setOpcode(Inst, ARM_CPS1p);
-		MCOperand_CreateImm0(Inst, mode);
+		MCInst_setOpcode(Inst, (ARM_CPS1p));
+		MCOperand_CreateImm0(Inst, (mode));
 		S = MCDisassembler_SoftFail;
 	}
 
@@ -2200,7 +2512,8 @@ static DecodeStatus DecodeCPSInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	unsigned imod = fieldFromInstruction_4(Insn, 9, 2);
 	unsigned M = fieldFromInstruction_4(Insn, 8, 1);
@@ -2214,37 +2527,67 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst *Inst, unsigned Insn,
 	// return failure here.  The '01' imod value is unprintable, so there's
 	// nothing useful we could do even if we returned UNPREDICTABLE.
 
-	if (imod == 1) return MCDisassembler_Fail;
+	if (imod == 1)
+		return MCDisassembler_Fail;
 
 	if (imod && M) {
-		MCInst_setOpcode(Inst, ARM_t2CPS3p);
-		MCOperand_CreateImm0(Inst, imod);
-		MCOperand_CreateImm0(Inst, iflags);
-		MCOperand_CreateImm0(Inst, mode);
+		MCInst_setOpcode(Inst, (ARM_t2CPS3p));
+		MCOperand_CreateImm0(Inst, (imod));
+		MCOperand_CreateImm0(Inst, (iflags));
+		MCOperand_CreateImm0(Inst, (mode));
 	} else if (imod && !M) {
-		MCInst_setOpcode(Inst, ARM_t2CPS2p);
-		MCOperand_CreateImm0(Inst, imod);
-		MCOperand_CreateImm0(Inst, iflags);
-		if (mode) S = MCDisassembler_SoftFail;
+		MCInst_setOpcode(Inst, (ARM_t2CPS2p));
+		MCOperand_CreateImm0(Inst, (imod));
+		MCOperand_CreateImm0(Inst, (iflags));
+		if (mode)
+			S = MCDisassembler_SoftFail;
 	} else if (!imod && M) {
-		MCInst_setOpcode(Inst, ARM_t2CPS1p);
-		MCOperand_CreateImm0(Inst, mode);
-		if (iflags) S = MCDisassembler_SoftFail;
+		MCInst_setOpcode(Inst, (ARM_t2CPS1p));
+		MCOperand_CreateImm0(Inst, (mode));
+		if (iflags)
+			S = MCDisassembler_SoftFail;
 	} else {
 		// imod == '00' && M == '0' --> this is a HINT instruction
 		int imm = fieldFromInstruction_4(Insn, 0, 8);
 		// HINT are defined only for immediate in [0..4]
-		if (imm > 4) return MCDisassembler_Fail;
-
-		MCInst_setOpcode(Inst, ARM_t2HINT);
-		MCOperand_CreateImm0(Inst, imm);
+		if (imm > 4)
+			return MCDisassembler_Fail;
+		MCInst_setOpcode(Inst, (ARM_t2HINT));
+		MCOperand_CreateImm0(Inst, (imm));
 	}
 
 	return S;
 }
 
+static DecodeStatus DecodeT2HintSpaceInstruction(MCInst *Inst, unsigned Insn,
+												 uint64_t Address,
+												 const void *Decoder)
+{
+	unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
+
+	unsigned Opcode = ARM_t2HINT;
+
+	if (imm == 0x0D) {
+		Opcode = ARM_t2PACBTI;
+	} else if (imm == 0x1D) {
+		Opcode = ARM_t2PAC;
+	} else if (imm == 0x2D) {
+		Opcode = ARM_t2AUT;
+	} else if (imm == 0x0F) {
+		Opcode = ARM_t2BTI;
+	}
+
+	MCInst_setOpcode(Inst, (Opcode));
+	if (Opcode == ARM_t2HINT) {
+		MCOperand_CreateImm0(Inst, (imm));
+	}
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2259,17 +2602,18 @@ static DecodeStatus DecodeT2MOVTWInstruction(MCInst *Inst, unsigned Insn,
 	if (MCInst_getOpcode(Inst) == ARM_t2MOVTi16)
 		if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
 			return MCDisassembler_Fail;
-
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, imm);
+	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (imm));
 
 	return S;
 }
 
 static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											  uint64_t Address,
+											  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2287,7 +2631,8 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, imm);
+	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (imm));
 
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
@@ -2296,7 +2641,7 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2311,13 +2656,10 @@ static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -2328,9 +2670,10 @@ static DecodeStatus DecodeSMLAInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Pred = fieldFromInstruction_4(Insn, 28, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
@@ -2340,10 +2683,8 @@ static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -2351,34 +2692,38 @@ static DecodeStatus DecodeTSTInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeSETPANInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Imm = fieldFromInstruction_4(Insn, 9, 1);
 
-	if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) || !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops))
+	if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps) ||
+		!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops))
 		return MCDisassembler_Fail;
 
 	// Decoder can be called from DecodeTST, which does not check the full
 	// encoding is valid.
 	if (fieldFromInstruction_4(Insn, 20, 12) != 0xf11 ||
-			fieldFromInstruction_4(Insn, 4, 4) != 0)
+		fieldFromInstruction_4(Insn, 4, 4) != 0)
 		return MCDisassembler_Fail;
-
 	if (fieldFromInstruction_4(Insn, 10, 10) != 0 ||
-			fieldFromInstruction_4(Insn, 0, 4) != 0)
+		fieldFromInstruction_4(Insn, 0, 4) != 0)
 		S = MCDisassembler_SoftFail;
 
-	MCInst_setOpcode(Inst, ARM_SETPAN);
-	MCOperand_CreateImm0(Inst, Imm);
+	MCInst_setOpcode(Inst, (ARM_SETPAN));
+	MCOperand_CreateImm0(Inst, (Imm));
 
 	return S;
 }
 
 static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned add = fieldFromInstruction_4(Val, 12, 1);
 	unsigned imm = fieldFromInstruction_4(Val, 0, 12);
 	unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
@@ -2386,20 +2731,23 @@ static DecodeStatus DecodeAddrModeImm12Operand(MCInst *Inst, unsigned Val,
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	if (!add) imm *= (unsigned int)-1;
-	if (imm == 0 && !add) imm = (unsigned int)INT32_MIN;
-
-	MCOperand_CreateImm0(Inst, imm);
-	//if (Rn == 15)
-	//  tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
+	if (!add)
+		imm *= -1;
+	if (imm == 0 && !add)
+		imm = INT32_MIN;
+	MCOperand_CreateImm0(Inst, (imm));
+	if (Rn == 15)
+		tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
 
 	return S;
 }
 
 static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
 	// U == 1 to add imm, 0 to subtract it.
 	unsigned U = fieldFromInstruction_4(Val, 8, 1);
@@ -2409,17 +2757,19 @@ static DecodeStatus DecodeAddrMode5Operand(MCInst *Inst, unsigned Val,
 		return MCDisassembler_Fail;
 
 	if (U)
-		MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_add, (unsigned char)imm));
+		MCOperand_CreateImm0(Inst, (ARM_AM_getAM5Opc(ARM_AM_add, imm)));
 	else
-		MCOperand_CreateImm0(Inst, ARM_AM_getAM5Opc(ARM_AM_sub, (unsigned char)imm));
+		MCOperand_CreateImm0(Inst, (ARM_AM_getAM5Opc(ARM_AM_sub, imm)));
 
 	return S;
 }
 
 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
 	// U == 1 to add imm, 0 to subtract it.
 	unsigned U = fieldFromInstruction_4(Val, 8, 1);
@@ -2429,21 +2779,22 @@ static DecodeStatus DecodeAddrMode5FP16Operand(MCInst *Inst, unsigned Val,
 		return MCDisassembler_Fail;
 
 	if (U)
-		MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_add, imm));
+		MCOperand_CreateImm0(Inst, (ARM_AM_getAM5FP16Opc(ARM_AM_add, imm)));
 	else
-		MCOperand_CreateImm0(Inst, getAM5FP16Opc(ARM_AM_sub, imm));
+		MCOperand_CreateImm0(Inst, (ARM_AM_getAM5FP16Opc(ARM_AM_sub, imm)));
 
 	return S;
 }
 
 static DecodeStatus DecodeAddrMode7Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
 }
 
 static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus Status = MCDisassembler_Success;
 
@@ -2461,15 +2812,17 @@ static DecodeStatus DecodeT2BInstruction(MCInst *Inst, unsigned Insn,
 	unsigned imm10 = fieldFromInstruction_4(Insn, 16, 10);
 	unsigned imm11 = fieldFromInstruction_4(Insn, 0, 11);
 	unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
-	int imm32 = SignExtend32(tmp << 1, 25);
-
-	MCOperand_CreateImm0(Inst, imm32);
+	int imm32 = SignExtend32((tmp << 1), 25);
+	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, Inst,
+								  Decoder))
+		MCOperand_CreateImm0(Inst, (imm32));
 
 	return Status;
 }
 
 static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2477,23 +2830,32 @@ static DecodeStatus DecodeBranchImmInstruction(MCInst *Inst, unsigned Insn,
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 24) << 2;
 
 	if (pred == 0xF) {
-		MCInst_setOpcode(Inst, ARM_BLXi);
+		MCInst_setOpcode(Inst, (ARM_BLXi));
 		imm |= fieldFromInstruction_4(Insn, 24, 1) << 1;
-		MCOperand_CreateImm0(Inst, SignExtend32(imm, 26));
+		if (!tryAddingSymbolicOperand(Address,
+									  Address + SignExtend32((imm), 26) + 8,
+									  true, 4, Inst, Decoder))
+			MCOperand_CreateImm0(Inst, (SignExtend32((imm), 26)));
 		return S;
 	}
 
-	MCOperand_CreateImm0(Inst, SignExtend32(imm, 26));
+	if (!tryAddingSymbolicOperand(Address,
+								  Address + SignExtend32((imm), 26) + 8, true,
+								  4, Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (SignExtend32((imm), 26)));
 
-	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
-		return MCDisassembler_Fail;
+	// We already have BL_pred for BL w/ predicate, no need to add addition
+	// predicate opreands for BL
+	if (MCInst_getOpcode(Inst) != ARM_BL)
+		if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+			return MCDisassembler_Fail;
 
 	return S;
 }
 
-
 static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -2502,230 +2864,243 @@ static DecodeStatus DecodeAddrMode6Operand(MCInst *Inst, unsigned Val,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!align)
-		MCOperand_CreateImm0(Inst, 0);
+		MCOperand_CreateImm0(Inst, (0));
 	else
-		MCOperand_CreateImm0(Inst, 4 << align);
+		MCOperand_CreateImm0(Inst, (4 << align));
 
 	return S;
 }
 
 static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned wb, Rn, Rm;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	wb = fieldFromInstruction_4(Insn, 16, 4);
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned wb = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
 
 	// First output register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VLD1q16: case ARM_VLD1q32: case ARM_VLD1q64: case ARM_VLD1q8:
-		case ARM_VLD1q16wb_fixed: case ARM_VLD1q16wb_register:
-		case ARM_VLD1q32wb_fixed: case ARM_VLD1q32wb_register:
-		case ARM_VLD1q64wb_fixed: case ARM_VLD1q64wb_register:
-		case ARM_VLD1q8wb_fixed: case ARM_VLD1q8wb_register:
-		case ARM_VLD2d16: case ARM_VLD2d32: case ARM_VLD2d8:
-		case ARM_VLD2d16wb_fixed: case ARM_VLD2d16wb_register:
-		case ARM_VLD2d32wb_fixed: case ARM_VLD2d32wb_register:
-		case ARM_VLD2d8wb_fixed: case ARM_VLD2d8wb_register:
-			if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VLD2b16:
-		case ARM_VLD2b32:
-		case ARM_VLD2b8:
-		case ARM_VLD2b16wb_fixed:
-		case ARM_VLD2b16wb_register:
-		case ARM_VLD2b32wb_fixed:
-		case ARM_VLD2b32wb_register:
-		case ARM_VLD2b8wb_fixed:
-		case ARM_VLD2b8wb_register:
-			if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		default:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
+	case ARM_VLD1q16:
+	case ARM_VLD1q32:
+	case ARM_VLD1q64:
+	case ARM_VLD1q8:
+	case ARM_VLD1q16wb_fixed:
+	case ARM_VLD1q16wb_register:
+	case ARM_VLD1q32wb_fixed:
+	case ARM_VLD1q32wb_register:
+	case ARM_VLD1q64wb_fixed:
+	case ARM_VLD1q64wb_register:
+	case ARM_VLD1q8wb_fixed:
+	case ARM_VLD1q8wb_register:
+	case ARM_VLD2d16:
+	case ARM_VLD2d32:
+	case ARM_VLD2d8:
+	case ARM_VLD2d16wb_fixed:
+	case ARM_VLD2d16wb_register:
+	case ARM_VLD2d32wb_fixed:
+	case ARM_VLD2d32wb_register:
+	case ARM_VLD2d8wb_fixed:
+	case ARM_VLD2d8wb_register:
+		if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VLD2b16:
+	case ARM_VLD2b32:
+	case ARM_VLD2b8:
+	case ARM_VLD2b16wb_fixed:
+	case ARM_VLD2b16wb_register:
+	case ARM_VLD2b32wb_fixed:
+	case ARM_VLD2b32wb_register:
+	case ARM_VLD2b8wb_fixed:
+	case ARM_VLD2b8wb_register:
+		if (!Check(&S,
+				   DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
 	// Second output register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VLD3d8:
-		case ARM_VLD3d16:
-		case ARM_VLD3d32:
-		case ARM_VLD3d8_UPD:
-		case ARM_VLD3d16_UPD:
-		case ARM_VLD3d32_UPD:
-		case ARM_VLD4d8:
-		case ARM_VLD4d16:
-		case ARM_VLD4d32:
-		case ARM_VLD4d8_UPD:
-		case ARM_VLD4d16_UPD:
-		case ARM_VLD4d32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VLD3q8:
-		case ARM_VLD3q16:
-		case ARM_VLD3q32:
-		case ARM_VLD3q8_UPD:
-		case ARM_VLD3q16_UPD:
-		case ARM_VLD3q32_UPD:
-		case ARM_VLD4q8:
-		case ARM_VLD4q16:
-		case ARM_VLD4q32:
-		case ARM_VLD4q8_UPD:
-		case ARM_VLD4q16_UPD:
-		case ARM_VLD4q32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-
-		default:
-			break;
+	case ARM_VLD3d8:
+	case ARM_VLD3d16:
+	case ARM_VLD3d32:
+	case ARM_VLD3d8_UPD:
+	case ARM_VLD3d16_UPD:
+	case ARM_VLD3d32_UPD:
+	case ARM_VLD4d8:
+	case ARM_VLD4d16:
+	case ARM_VLD4d32:
+	case ARM_VLD4d8_UPD:
+	case ARM_VLD4d16_UPD:
+	case ARM_VLD4d32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VLD3q8:
+	case ARM_VLD3q16:
+	case ARM_VLD3q32:
+	case ARM_VLD3q8_UPD:
+	case ARM_VLD3q16_UPD:
+	case ARM_VLD3q32_UPD:
+	case ARM_VLD4q8:
+	case ARM_VLD4q16:
+	case ARM_VLD4q32:
+	case ARM_VLD4q8_UPD:
+	case ARM_VLD4q16_UPD:
+	case ARM_VLD4q32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// Third output register
-	switch(MCInst_getOpcode(Inst)) {
-		case ARM_VLD3d8:
-		case ARM_VLD3d16:
-		case ARM_VLD3d32:
-		case ARM_VLD3d8_UPD:
-		case ARM_VLD3d16_UPD:
-		case ARM_VLD3d32_UPD:
-		case ARM_VLD4d8:
-		case ARM_VLD4d16:
-		case ARM_VLD4d32:
-		case ARM_VLD4d8_UPD:
-		case ARM_VLD4d16_UPD:
-		case ARM_VLD4d32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		case ARM_VLD3q8:
-		case ARM_VLD3q16:
-		case ARM_VLD3q32:
-		case ARM_VLD3q8_UPD:
-		case ARM_VLD3q16_UPD:
-		case ARM_VLD3q32_UPD:
-		case ARM_VLD4q8:
-		case ARM_VLD4q16:
-		case ARM_VLD4q32:
-		case ARM_VLD4q8_UPD:
-		case ARM_VLD4q16_UPD:
-		case ARM_VLD4q32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	switch (MCInst_getOpcode(Inst)) {
+	case ARM_VLD3d8:
+	case ARM_VLD3d16:
+	case ARM_VLD3d32:
+	case ARM_VLD3d8_UPD:
+	case ARM_VLD3d16_UPD:
+	case ARM_VLD3d32_UPD:
+	case ARM_VLD4d8:
+	case ARM_VLD4d16:
+	case ARM_VLD4d32:
+	case ARM_VLD4d8_UPD:
+	case ARM_VLD4d16_UPD:
+	case ARM_VLD4d32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VLD3q8:
+	case ARM_VLD3q16:
+	case ARM_VLD3q32:
+	case ARM_VLD3q8_UPD:
+	case ARM_VLD3q16_UPD:
+	case ARM_VLD3q32_UPD:
+	case ARM_VLD4q8:
+	case ARM_VLD4q16:
+	case ARM_VLD4q32:
+	case ARM_VLD4q8_UPD:
+	case ARM_VLD4q16_UPD:
+	case ARM_VLD4q32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// Fourth output register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VLD4d8:
-		case ARM_VLD4d16:
-		case ARM_VLD4d32:
-		case ARM_VLD4d8_UPD:
-		case ARM_VLD4d16_UPD:
-		case ARM_VLD4d32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		case ARM_VLD4q8:
-		case ARM_VLD4q16:
-		case ARM_VLD4q32:
-		case ARM_VLD4q8_UPD:
-		case ARM_VLD4q16_UPD:
-		case ARM_VLD4q32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_VLD4d8:
+	case ARM_VLD4d16:
+	case ARM_VLD4d32:
+	case ARM_VLD4d8_UPD:
+	case ARM_VLD4d16_UPD:
+	case ARM_VLD4d32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VLD4q8:
+	case ARM_VLD4q16:
+	case ARM_VLD4q32:
+	case ARM_VLD4q8_UPD:
+	case ARM_VLD4q16_UPD:
+	case ARM_VLD4q32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// Writeback operand
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VLD1d8wb_fixed:
-		case ARM_VLD1d16wb_fixed:
-		case ARM_VLD1d32wb_fixed:
-		case ARM_VLD1d64wb_fixed:
-		case ARM_VLD1d8wb_register:
-		case ARM_VLD1d16wb_register:
-		case ARM_VLD1d32wb_register:
-		case ARM_VLD1d64wb_register:
-		case ARM_VLD1q8wb_fixed:
-		case ARM_VLD1q16wb_fixed:
-		case ARM_VLD1q32wb_fixed:
-		case ARM_VLD1q64wb_fixed:
-		case ARM_VLD1q8wb_register:
-		case ARM_VLD1q16wb_register:
-		case ARM_VLD1q32wb_register:
-		case ARM_VLD1q64wb_register:
-		case ARM_VLD1d8Twb_fixed:
-		case ARM_VLD1d8Twb_register:
-		case ARM_VLD1d16Twb_fixed:
-		case ARM_VLD1d16Twb_register:
-		case ARM_VLD1d32Twb_fixed:
-		case ARM_VLD1d32Twb_register:
-		case ARM_VLD1d64Twb_fixed:
-		case ARM_VLD1d64Twb_register:
-		case ARM_VLD1d8Qwb_fixed:
-		case ARM_VLD1d8Qwb_register:
-		case ARM_VLD1d16Qwb_fixed:
-		case ARM_VLD1d16Qwb_register:
-		case ARM_VLD1d32Qwb_fixed:
-		case ARM_VLD1d32Qwb_register:
-		case ARM_VLD1d64Qwb_fixed:
-		case ARM_VLD1d64Qwb_register:
-		case ARM_VLD2d8wb_fixed:
-		case ARM_VLD2d16wb_fixed:
-		case ARM_VLD2d32wb_fixed:
-		case ARM_VLD2q8wb_fixed:
-		case ARM_VLD2q16wb_fixed:
-		case ARM_VLD2q32wb_fixed:
-		case ARM_VLD2d8wb_register:
-		case ARM_VLD2d16wb_register:
-		case ARM_VLD2d32wb_register:
-		case ARM_VLD2q8wb_register:
-		case ARM_VLD2q16wb_register:
-		case ARM_VLD2q32wb_register:
-		case ARM_VLD2b8wb_fixed:
-		case ARM_VLD2b16wb_fixed:
-		case ARM_VLD2b32wb_fixed:
-		case ARM_VLD2b8wb_register:
-		case ARM_VLD2b16wb_register:
-		case ARM_VLD2b32wb_register:
-			MCOperand_CreateImm0(Inst, 0);
-			break;
-
-		case ARM_VLD3d8_UPD:
-		case ARM_VLD3d16_UPD:
-		case ARM_VLD3d32_UPD:
-		case ARM_VLD3q8_UPD:
-		case ARM_VLD3q16_UPD:
-		case ARM_VLD3q32_UPD:
-		case ARM_VLD4d8_UPD:
-		case ARM_VLD4d16_UPD:
-		case ARM_VLD4d32_UPD:
-		case ARM_VLD4q8_UPD:
-		case ARM_VLD4q16_UPD:
-		case ARM_VLD4q32_UPD:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		default:
-			break;
+	case ARM_VLD1d8wb_fixed:
+	case ARM_VLD1d16wb_fixed:
+	case ARM_VLD1d32wb_fixed:
+	case ARM_VLD1d64wb_fixed:
+	case ARM_VLD1d8wb_register:
+	case ARM_VLD1d16wb_register:
+	case ARM_VLD1d32wb_register:
+	case ARM_VLD1d64wb_register:
+	case ARM_VLD1q8wb_fixed:
+	case ARM_VLD1q16wb_fixed:
+	case ARM_VLD1q32wb_fixed:
+	case ARM_VLD1q64wb_fixed:
+	case ARM_VLD1q8wb_register:
+	case ARM_VLD1q16wb_register:
+	case ARM_VLD1q32wb_register:
+	case ARM_VLD1q64wb_register:
+	case ARM_VLD1d8Twb_fixed:
+	case ARM_VLD1d8Twb_register:
+	case ARM_VLD1d16Twb_fixed:
+	case ARM_VLD1d16Twb_register:
+	case ARM_VLD1d32Twb_fixed:
+	case ARM_VLD1d32Twb_register:
+	case ARM_VLD1d64Twb_fixed:
+	case ARM_VLD1d64Twb_register:
+	case ARM_VLD1d8Qwb_fixed:
+	case ARM_VLD1d8Qwb_register:
+	case ARM_VLD1d16Qwb_fixed:
+	case ARM_VLD1d16Qwb_register:
+	case ARM_VLD1d32Qwb_fixed:
+	case ARM_VLD1d32Qwb_register:
+	case ARM_VLD1d64Qwb_fixed:
+	case ARM_VLD1d64Qwb_register:
+	case ARM_VLD2d8wb_fixed:
+	case ARM_VLD2d16wb_fixed:
+	case ARM_VLD2d32wb_fixed:
+	case ARM_VLD2q8wb_fixed:
+	case ARM_VLD2q16wb_fixed:
+	case ARM_VLD2q32wb_fixed:
+	case ARM_VLD2d8wb_register:
+	case ARM_VLD2d16wb_register:
+	case ARM_VLD2d32wb_register:
+	case ARM_VLD2q8wb_register:
+	case ARM_VLD2q16wb_register:
+	case ARM_VLD2q32wb_register:
+	case ARM_VLD2b8wb_fixed:
+	case ARM_VLD2b16wb_fixed:
+	case ARM_VLD2b32wb_fixed:
+	case ARM_VLD2b8wb_register:
+	case ARM_VLD2b16wb_register:
+	case ARM_VLD2b32wb_register:
+		MCOperand_CreateImm0(Inst, (0));
+		break;
+	case ARM_VLD3d8_UPD:
+	case ARM_VLD3d16_UPD:
+	case ARM_VLD3d32_UPD:
+	case ARM_VLD3q8_UPD:
+	case ARM_VLD3q16_UPD:
+	case ARM_VLD3q32_UPD:
+	case ARM_VLD4d8_UPD:
+	case ARM_VLD4d16_UPD:
+	case ARM_VLD4d32_UPD:
+	case ARM_VLD4q8_UPD:
+	case ARM_VLD4q16_UPD:
+	case ARM_VLD4q32_UPD:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// AddrMode6 Base (register+alignment)
@@ -2734,214 +3109,218 @@ static DecodeStatus DecodeVLDInstruction(MCInst *Inst, unsigned Insn,
 
 	// AddrMode6 Offset (register)
 	switch (MCInst_getOpcode(Inst)) {
-		default:
-			// The below have been updated to have explicit am6offset split
-			// between fixed and register offset. For those instructions not
-			// yet updated, we need to add an additional reg0 operand for the
-			// fixed variant.
-			//
-			// The fixed offset encodes as Rm == 0xd, so we check for that.
-			if (Rm == 0xd) {
-				MCOperand_CreateReg0(Inst, 0);
-				break;
-			}
-			// Fall through to handle the register offset variant.
-
-		case ARM_VLD1d8wb_fixed:
-		case ARM_VLD1d16wb_fixed:
-		case ARM_VLD1d32wb_fixed:
-		case ARM_VLD1d64wb_fixed:
-		case ARM_VLD1d8Twb_fixed:
-		case ARM_VLD1d16Twb_fixed:
-		case ARM_VLD1d32Twb_fixed:
-		case ARM_VLD1d64Twb_fixed:
-		case ARM_VLD1d8Qwb_fixed:
-		case ARM_VLD1d16Qwb_fixed:
-		case ARM_VLD1d32Qwb_fixed:
-		case ARM_VLD1d64Qwb_fixed:
-		case ARM_VLD1d8wb_register:
-		case ARM_VLD1d16wb_register:
-		case ARM_VLD1d32wb_register:
-		case ARM_VLD1d64wb_register:
-		case ARM_VLD1q8wb_fixed:
-		case ARM_VLD1q16wb_fixed:
-		case ARM_VLD1q32wb_fixed:
-		case ARM_VLD1q64wb_fixed:
-		case ARM_VLD1q8wb_register:
-		case ARM_VLD1q16wb_register:
-		case ARM_VLD1q32wb_register:
-		case ARM_VLD1q64wb_register:
-			// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
-			// variant encodes Rm == 0xf. Anything else is a register offset post-
-			// increment and we need to add the register operand to the instruction.
-			if (Rm != 0xD && Rm != 0xF &&
-					!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VLD2d8wb_fixed:
-		case ARM_VLD2d16wb_fixed:
-		case ARM_VLD2d32wb_fixed:
-		case ARM_VLD2b8wb_fixed:
-		case ARM_VLD2b16wb_fixed:
-		case ARM_VLD2b32wb_fixed:
-		case ARM_VLD2q8wb_fixed:
-		case ARM_VLD2q16wb_fixed:
-		case ARM_VLD2q32wb_fixed:
+	default:
+		// The below have been updated to have explicit am6offset split
+		// between fixed and register offset. For those instructions not
+		// yet updated, we need to add an additional reg0 operand for the
+		// fixed variant.
+		//
+		// The fixed offset encodes as Rm == 0xd, so we check for that.
+		if (Rm == 0xd) {
+			MCOperand_CreateReg0(Inst, (0));
 			break;
+		}
+		// Fall through to handle the register offset variant.
+		// fall through
+	case ARM_VLD1d8wb_fixed:
+	case ARM_VLD1d16wb_fixed:
+	case ARM_VLD1d32wb_fixed:
+	case ARM_VLD1d64wb_fixed:
+	case ARM_VLD1d8Twb_fixed:
+	case ARM_VLD1d16Twb_fixed:
+	case ARM_VLD1d32Twb_fixed:
+	case ARM_VLD1d64Twb_fixed:
+	case ARM_VLD1d8Qwb_fixed:
+	case ARM_VLD1d16Qwb_fixed:
+	case ARM_VLD1d32Qwb_fixed:
+	case ARM_VLD1d64Qwb_fixed:
+	case ARM_VLD1d8wb_register:
+	case ARM_VLD1d16wb_register:
+	case ARM_VLD1d32wb_register:
+	case ARM_VLD1d64wb_register:
+	case ARM_VLD1q8wb_fixed:
+	case ARM_VLD1q16wb_fixed:
+	case ARM_VLD1q32wb_fixed:
+	case ARM_VLD1q64wb_fixed:
+	case ARM_VLD1q8wb_register:
+	case ARM_VLD1q16wb_register:
+	case ARM_VLD1q32wb_register:
+	case ARM_VLD1q64wb_register:
+		// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
+		// variant encodes Rm == 0xf. Anything else is a register offset post-
+		// increment and we need to add the register operand to the instruction.
+		if (Rm != 0xD && Rm != 0xF &&
+			!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VLD2d8wb_fixed:
+	case ARM_VLD2d16wb_fixed:
+	case ARM_VLD2d32wb_fixed:
+	case ARM_VLD2b8wb_fixed:
+	case ARM_VLD2b16wb_fixed:
+	case ARM_VLD2b32wb_fixed:
+	case ARM_VLD2q8wb_fixed:
+	case ARM_VLD2q16wb_fixed:
+	case ARM_VLD2q32wb_fixed:
+		break;
 	}
 
 	return S;
 }
 
 static DecodeStatus DecodeVLDST1Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
-	unsigned load;
 	unsigned type = fieldFromInstruction_4(Insn, 8, 4);
 	unsigned align = fieldFromInstruction_4(Insn, 4, 2);
-	if (type == 6 && (align & 2)) return MCDisassembler_Fail;
-	if (type == 7 && (align & 2)) return MCDisassembler_Fail;
-	if (type == 10 && align == 3) return MCDisassembler_Fail;
-
-	load = fieldFromInstruction_4(Insn, 21, 1);
+	if (type == 6 && (align & 2))
+		return MCDisassembler_Fail;
+	if (type == 7 && (align & 2))
+		return MCDisassembler_Fail;
+	if (type == 10 && align == 3)
+		return MCDisassembler_Fail;
 
+	unsigned load = fieldFromInstruction_4(Insn, 21, 1);
 	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
-		: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
+				: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVLDST2Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
-	unsigned type, align, load;
 	unsigned size = fieldFromInstruction_4(Insn, 6, 2);
-	if (size == 3) return MCDisassembler_Fail;
+	if (size == 3)
+		return MCDisassembler_Fail;
 
-	type = fieldFromInstruction_4(Insn, 8, 4);
-	align = fieldFromInstruction_4(Insn, 4, 2);
-	if (type == 8 && align == 3) return MCDisassembler_Fail;
-	if (type == 9 && align == 3) return MCDisassembler_Fail;
-
-	load = fieldFromInstruction_4(Insn, 21, 1);
+	unsigned type = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned align = fieldFromInstruction_4(Insn, 4, 2);
+	if (type == 8 && align == 3)
+		return MCDisassembler_Fail;
+	if (type == 9 && align == 3)
+		return MCDisassembler_Fail;
 
+	unsigned load = fieldFromInstruction_4(Insn, 21, 1);
 	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
-		: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
+				: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVLDST3Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
-	unsigned align, load;
 	unsigned size = fieldFromInstruction_4(Insn, 6, 2);
-	if (size == 3) return MCDisassembler_Fail;
+	if (size == 3)
+		return MCDisassembler_Fail;
 
-	align = fieldFromInstruction_4(Insn, 4, 2);
-	if (align & 2) return MCDisassembler_Fail;
-
-	load = fieldFromInstruction_4(Insn, 21, 1);
+	unsigned align = fieldFromInstruction_4(Insn, 4, 2);
+	if (align & 2)
+		return MCDisassembler_Fail;
 
+	unsigned load = fieldFromInstruction_4(Insn, 21, 1);
 	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
-		: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
+				: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVLDST4Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
-	unsigned load;
 	unsigned size = fieldFromInstruction_4(Insn, 6, 2);
-	if (size == 3) return MCDisassembler_Fail;
-
-	load = fieldFromInstruction_4(Insn, 21, 1);
+	if (size == 3)
+		return MCDisassembler_Fail;
 
+	unsigned load = fieldFromInstruction_4(Insn, 21, 1);
 	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
-		: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
+				: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
 }
 
 static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned wb, Rn, Rm;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	wb = fieldFromInstruction_4(Insn, 16, 4);
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned wb = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	Rn |= fieldFromInstruction_4(Insn, 4, 2) << 4;
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
 
 	// Writeback Operand
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VST1d8wb_fixed:
-		case ARM_VST1d16wb_fixed:
-		case ARM_VST1d32wb_fixed:
-		case ARM_VST1d64wb_fixed:
-		case ARM_VST1d8wb_register:
-		case ARM_VST1d16wb_register:
-		case ARM_VST1d32wb_register:
-		case ARM_VST1d64wb_register:
-		case ARM_VST1q8wb_fixed:
-		case ARM_VST1q16wb_fixed:
-		case ARM_VST1q32wb_fixed:
-		case ARM_VST1q64wb_fixed:
-		case ARM_VST1q8wb_register:
-		case ARM_VST1q16wb_register:
-		case ARM_VST1q32wb_register:
-		case ARM_VST1q64wb_register:
-		case ARM_VST1d8Twb_fixed:
-		case ARM_VST1d16Twb_fixed:
-		case ARM_VST1d32Twb_fixed:
-		case ARM_VST1d64Twb_fixed:
-		case ARM_VST1d8Twb_register:
-		case ARM_VST1d16Twb_register:
-		case ARM_VST1d32Twb_register:
-		case ARM_VST1d64Twb_register:
-		case ARM_VST1d8Qwb_fixed:
-		case ARM_VST1d16Qwb_fixed:
-		case ARM_VST1d32Qwb_fixed:
-		case ARM_VST1d64Qwb_fixed:
-		case ARM_VST1d8Qwb_register:
-		case ARM_VST1d16Qwb_register:
-		case ARM_VST1d32Qwb_register:
-		case ARM_VST1d64Qwb_register:
-		case ARM_VST2d8wb_fixed:
-		case ARM_VST2d16wb_fixed:
-		case ARM_VST2d32wb_fixed:
-		case ARM_VST2d8wb_register:
-		case ARM_VST2d16wb_register:
-		case ARM_VST2d32wb_register:
-		case ARM_VST2q8wb_fixed:
-		case ARM_VST2q16wb_fixed:
-		case ARM_VST2q32wb_fixed:
-		case ARM_VST2q8wb_register:
-		case ARM_VST2q16wb_register:
-		case ARM_VST2q32wb_register:
-		case ARM_VST2b8wb_fixed:
-		case ARM_VST2b16wb_fixed:
-		case ARM_VST2b32wb_fixed:
-		case ARM_VST2b8wb_register:
-		case ARM_VST2b16wb_register:
-		case ARM_VST2b32wb_register:
-			if (Rm == 0xF)
-				return MCDisassembler_Fail;
-			MCOperand_CreateImm0(Inst, 0);
-			break;
-		case ARM_VST3d8_UPD:
-		case ARM_VST3d16_UPD:
-		case ARM_VST3d32_UPD:
-		case ARM_VST3q8_UPD:
-		case ARM_VST3q16_UPD:
-		case ARM_VST3q32_UPD:
-		case ARM_VST4d8_UPD:
-		case ARM_VST4d16_UPD:
-		case ARM_VST4d32_UPD:
-		case ARM_VST4q8_UPD:
-		case ARM_VST4q16_UPD:
-		case ARM_VST4q32_UPD:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_VST1d8wb_fixed:
+	case ARM_VST1d16wb_fixed:
+	case ARM_VST1d32wb_fixed:
+	case ARM_VST1d64wb_fixed:
+	case ARM_VST1d8wb_register:
+	case ARM_VST1d16wb_register:
+	case ARM_VST1d32wb_register:
+	case ARM_VST1d64wb_register:
+	case ARM_VST1q8wb_fixed:
+	case ARM_VST1q16wb_fixed:
+	case ARM_VST1q32wb_fixed:
+	case ARM_VST1q64wb_fixed:
+	case ARM_VST1q8wb_register:
+	case ARM_VST1q16wb_register:
+	case ARM_VST1q32wb_register:
+	case ARM_VST1q64wb_register:
+	case ARM_VST1d8Twb_fixed:
+	case ARM_VST1d16Twb_fixed:
+	case ARM_VST1d32Twb_fixed:
+	case ARM_VST1d64Twb_fixed:
+	case ARM_VST1d8Twb_register:
+	case ARM_VST1d16Twb_register:
+	case ARM_VST1d32Twb_register:
+	case ARM_VST1d64Twb_register:
+	case ARM_VST1d8Qwb_fixed:
+	case ARM_VST1d16Qwb_fixed:
+	case ARM_VST1d32Qwb_fixed:
+	case ARM_VST1d64Qwb_fixed:
+	case ARM_VST1d8Qwb_register:
+	case ARM_VST1d16Qwb_register:
+	case ARM_VST1d32Qwb_register:
+	case ARM_VST1d64Qwb_register:
+	case ARM_VST2d8wb_fixed:
+	case ARM_VST2d16wb_fixed:
+	case ARM_VST2d32wb_fixed:
+	case ARM_VST2d8wb_register:
+	case ARM_VST2d16wb_register:
+	case ARM_VST2d32wb_register:
+	case ARM_VST2q8wb_fixed:
+	case ARM_VST2q16wb_fixed:
+	case ARM_VST2q32wb_fixed:
+	case ARM_VST2q8wb_register:
+	case ARM_VST2q16wb_register:
+	case ARM_VST2q32wb_register:
+	case ARM_VST2b8wb_fixed:
+	case ARM_VST2b16wb_fixed:
+	case ARM_VST2b32wb_fixed:
+	case ARM_VST2b8wb_register:
+	case ARM_VST2b16wb_register:
+	case ARM_VST2b32wb_register:
+		if (Rm == 0xF)
+			return MCDisassembler_Fail;
+		MCOperand_CreateImm0(Inst, (0));
+		break;
+	case ARM_VST3d8_UPD:
+	case ARM_VST3d16_UPD:
+	case ARM_VST3d32_UPD:
+	case ARM_VST3q8_UPD:
+	case ARM_VST3q16_UPD:
+	case ARM_VST3q32_UPD:
+	case ARM_VST4d8_UPD:
+	case ARM_VST4d16_UPD:
+	case ARM_VST4d32_UPD:
+	case ARM_VST4q8_UPD:
+	case ARM_VST4q16_UPD:
+	case ARM_VST4q32_UPD:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// AddrMode6 Base (register+alignment)
@@ -2950,223 +3329,226 @@ static DecodeStatus DecodeVSTInstruction(MCInst *Inst, unsigned Insn,
 
 	// AddrMode6 Offset (register)
 	switch (MCInst_getOpcode(Inst)) {
-		default:
-			if (Rm == 0xD)
-				MCOperand_CreateReg0(Inst, 0);
-			else if (Rm != 0xF) {
-				if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-					return MCDisassembler_Fail;
-			}
-			break;
-
-		case ARM_VST1d8wb_fixed:
-		case ARM_VST1d16wb_fixed:
-		case ARM_VST1d32wb_fixed:
-		case ARM_VST1d64wb_fixed:
-		case ARM_VST1q8wb_fixed:
-		case ARM_VST1q16wb_fixed:
-		case ARM_VST1q32wb_fixed:
-		case ARM_VST1q64wb_fixed:
-		case ARM_VST1d8Twb_fixed:
-		case ARM_VST1d16Twb_fixed:
-		case ARM_VST1d32Twb_fixed:
-		case ARM_VST1d64Twb_fixed:
-		case ARM_VST1d8Qwb_fixed:
-		case ARM_VST1d16Qwb_fixed:
-		case ARM_VST1d32Qwb_fixed:
-		case ARM_VST1d64Qwb_fixed:
-		case ARM_VST2d8wb_fixed:
-		case ARM_VST2d16wb_fixed:
-		case ARM_VST2d32wb_fixed:
-		case ARM_VST2q8wb_fixed:
-		case ARM_VST2q16wb_fixed:
-		case ARM_VST2q32wb_fixed:
-		case ARM_VST2b8wb_fixed:
-		case ARM_VST2b16wb_fixed:
-		case ARM_VST2b32wb_fixed:
-			break;
+	default:
+		if (Rm == 0xD)
+			MCOperand_CreateReg0(Inst, (0));
+		else if (Rm != 0xF) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		}
+		break;
+	case ARM_VST1d8wb_fixed:
+	case ARM_VST1d16wb_fixed:
+	case ARM_VST1d32wb_fixed:
+	case ARM_VST1d64wb_fixed:
+	case ARM_VST1q8wb_fixed:
+	case ARM_VST1q16wb_fixed:
+	case ARM_VST1q32wb_fixed:
+	case ARM_VST1q64wb_fixed:
+	case ARM_VST1d8Twb_fixed:
+	case ARM_VST1d16Twb_fixed:
+	case ARM_VST1d32Twb_fixed:
+	case ARM_VST1d64Twb_fixed:
+	case ARM_VST1d8Qwb_fixed:
+	case ARM_VST1d16Qwb_fixed:
+	case ARM_VST1d32Qwb_fixed:
+	case ARM_VST1d64Qwb_fixed:
+	case ARM_VST2d8wb_fixed:
+	case ARM_VST2d16wb_fixed:
+	case ARM_VST2d32wb_fixed:
+	case ARM_VST2q8wb_fixed:
+	case ARM_VST2q16wb_fixed:
+	case ARM_VST2q32wb_fixed:
+	case ARM_VST2b8wb_fixed:
+	case ARM_VST2b16wb_fixed:
+	case ARM_VST2b32wb_fixed:
+		break;
 	}
 
-
 	// First input register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VST1q16:
-		case ARM_VST1q32:
-		case ARM_VST1q64:
-		case ARM_VST1q8:
-		case ARM_VST1q16wb_fixed:
-		case ARM_VST1q16wb_register:
-		case ARM_VST1q32wb_fixed:
-		case ARM_VST1q32wb_register:
-		case ARM_VST1q64wb_fixed:
-		case ARM_VST1q64wb_register:
-		case ARM_VST1q8wb_fixed:
-		case ARM_VST1q8wb_register:
-		case ARM_VST2d16:
-		case ARM_VST2d32:
-		case ARM_VST2d8:
-		case ARM_VST2d16wb_fixed:
-		case ARM_VST2d16wb_register:
-		case ARM_VST2d32wb_fixed:
-		case ARM_VST2d32wb_register:
-		case ARM_VST2d8wb_fixed:
-		case ARM_VST2d8wb_register:
-			if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VST2b16:
-		case ARM_VST2b32:
-		case ARM_VST2b8:
-		case ARM_VST2b16wb_fixed:
-		case ARM_VST2b16wb_register:
-		case ARM_VST2b32wb_fixed:
-		case ARM_VST2b32wb_register:
-		case ARM_VST2b8wb_fixed:
-		case ARM_VST2b8wb_register:
-			if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		default:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
+	case ARM_VST1q16:
+	case ARM_VST1q32:
+	case ARM_VST1q64:
+	case ARM_VST1q8:
+	case ARM_VST1q16wb_fixed:
+	case ARM_VST1q16wb_register:
+	case ARM_VST1q32wb_fixed:
+	case ARM_VST1q32wb_register:
+	case ARM_VST1q64wb_fixed:
+	case ARM_VST1q64wb_register:
+	case ARM_VST1q8wb_fixed:
+	case ARM_VST1q8wb_register:
+	case ARM_VST2d16:
+	case ARM_VST2d32:
+	case ARM_VST2d8:
+	case ARM_VST2d16wb_fixed:
+	case ARM_VST2d16wb_register:
+	case ARM_VST2d32wb_fixed:
+	case ARM_VST2d32wb_register:
+	case ARM_VST2d8wb_fixed:
+	case ARM_VST2d8wb_register:
+		if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VST2b16:
+	case ARM_VST2b32:
+	case ARM_VST2b8:
+	case ARM_VST2b16wb_fixed:
+	case ARM_VST2b16wb_register:
+	case ARM_VST2b32wb_fixed:
+	case ARM_VST2b32wb_register:
+	case ARM_VST2b8wb_fixed:
+	case ARM_VST2b8wb_register:
+		if (!Check(&S,
+				   DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
 	// Second input register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VST3d8:
-		case ARM_VST3d16:
-		case ARM_VST3d32:
-		case ARM_VST3d8_UPD:
-		case ARM_VST3d16_UPD:
-		case ARM_VST3d32_UPD:
-		case ARM_VST4d8:
-		case ARM_VST4d16:
-		case ARM_VST4d32:
-		case ARM_VST4d8_UPD:
-		case ARM_VST4d16_UPD:
-		case ARM_VST4d32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VST3q8:
-		case ARM_VST3q16:
-		case ARM_VST3q32:
-		case ARM_VST3q8_UPD:
-		case ARM_VST3q16_UPD:
-		case ARM_VST3q32_UPD:
-		case ARM_VST4q8:
-		case ARM_VST4q16:
-		case ARM_VST4q32:
-		case ARM_VST4q8_UPD:
-		case ARM_VST4q16_UPD:
-		case ARM_VST4q32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_VST3d8:
+	case ARM_VST3d16:
+	case ARM_VST3d32:
+	case ARM_VST3d8_UPD:
+	case ARM_VST3d16_UPD:
+	case ARM_VST3d32_UPD:
+	case ARM_VST4d8:
+	case ARM_VST4d16:
+	case ARM_VST4d32:
+	case ARM_VST4d8_UPD:
+	case ARM_VST4d16_UPD:
+	case ARM_VST4d32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 1) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VST3q8:
+	case ARM_VST3q16:
+	case ARM_VST3q32:
+	case ARM_VST3q8_UPD:
+	case ARM_VST3q16_UPD:
+	case ARM_VST3q32_UPD:
+	case ARM_VST4q8:
+	case ARM_VST4q16:
+	case ARM_VST4q32:
+	case ARM_VST4q8_UPD:
+	case ARM_VST4q16_UPD:
+	case ARM_VST4q32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// Third input register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VST3d8:
-		case ARM_VST3d16:
-		case ARM_VST3d32:
-		case ARM_VST3d8_UPD:
-		case ARM_VST3d16_UPD:
-		case ARM_VST3d32_UPD:
-		case ARM_VST4d8:
-		case ARM_VST4d16:
-		case ARM_VST4d32:
-		case ARM_VST4d8_UPD:
-		case ARM_VST4d16_UPD:
-		case ARM_VST4d32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VST3q8:
-		case ARM_VST3q16:
-		case ARM_VST3q32:
-		case ARM_VST3q8_UPD:
-		case ARM_VST3q16_UPD:
-		case ARM_VST3q32_UPD:
-		case ARM_VST4q8:
-		case ARM_VST4q16:
-		case ARM_VST4q32:
-		case ARM_VST4q8_UPD:
-		case ARM_VST4q16_UPD:
-		case ARM_VST4q32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_VST3d8:
+	case ARM_VST3d16:
+	case ARM_VST3d32:
+	case ARM_VST3d8_UPD:
+	case ARM_VST3d16_UPD:
+	case ARM_VST3d32_UPD:
+	case ARM_VST4d8:
+	case ARM_VST4d16:
+	case ARM_VST4d32:
+	case ARM_VST4d8_UPD:
+	case ARM_VST4d16_UPD:
+	case ARM_VST4d32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VST3q8:
+	case ARM_VST3q16:
+	case ARM_VST3q32:
+	case ARM_VST3q8_UPD:
+	case ARM_VST3q16_UPD:
+	case ARM_VST3q32_UPD:
+	case ARM_VST4q8:
+	case ARM_VST4q16:
+	case ARM_VST4q32:
+	case ARM_VST4q8_UPD:
+	case ARM_VST4q16_UPD:
+	case ARM_VST4q32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 4) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// Fourth input register
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VST4d8:
-		case ARM_VST4d16:
-		case ARM_VST4d32:
-		case ARM_VST4d8_UPD:
-		case ARM_VST4d16_UPD:
-		case ARM_VST4d32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VST4q8:
-		case ARM_VST4q16:
-		case ARM_VST4q32:
-		case ARM_VST4q8_UPD:
-		case ARM_VST4q16_UPD:
-		case ARM_VST4q32_UPD:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_VST4d8:
+	case ARM_VST4d16:
+	case ARM_VST4d32:
+	case ARM_VST4d8_UPD:
+	case ARM_VST4d16_UPD:
+	case ARM_VST4d32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VST4q8:
+	case ARM_VST4q16:
+	case ARM_VST4q32:
+	case ARM_VST4q8_UPD:
+	case ARM_VST4q16_UPD:
+	case ARM_VST4q32_UPD:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 6) % 32, Address,
+											  Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	return S;
 }
 
 static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rn, Rm, align, size;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
-	align = fieldFromInstruction_4(Insn, 4, 1);
-	size = fieldFromInstruction_4(Insn, 6, 2);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned align = fieldFromInstruction_4(Insn, 4, 1);
+	unsigned size = fieldFromInstruction_4(Insn, 6, 2);
 
 	if (size == 0 && align == 1)
 		return MCDisassembler_Fail;
-
 	align *= (1 << size);
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VLD1DUPq16: case ARM_VLD1DUPq32: case ARM_VLD1DUPq8:
-		case ARM_VLD1DUPq16wb_fixed: case ARM_VLD1DUPq16wb_register:
-		case ARM_VLD1DUPq32wb_fixed: case ARM_VLD1DUPq32wb_register:
-		case ARM_VLD1DUPq8wb_fixed: case ARM_VLD1DUPq8wb_register:
-			if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		default:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
+	case ARM_VLD1DUPq16:
+	case ARM_VLD1DUPq32:
+	case ARM_VLD1DUPq8:
+	case ARM_VLD1DUPq16wb_fixed:
+	case ARM_VLD1DUPq16wb_register:
+	case ARM_VLD1DUPq32wb_fixed:
+	case ARM_VLD1DUPq32wb_register:
+	case ARM_VLD1DUPq8wb_fixed:
+	case ARM_VLD1DUPq8wb_register:
+		if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
 	}
-
 	if (Rm != 0xF) {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 			return MCDisassembler_Fail;
@@ -3174,62 +3556,70 @@ static DecodeStatus DecodeVLD1DupInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
+	MCOperand_CreateImm0(Inst, (align));
 
 	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
 	// variant encodes Rm == 0xf. Anything else is a register offset post-
 	// increment and we need to add the register operand to the instruction.
 	if (Rm != 0xD && Rm != 0xF &&
-			!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+		!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
 
 	return S;
 }
 
 static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rn, Rm, align, size;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
-	align = fieldFromInstruction_4(Insn, 4, 1);
-	size = 1 << fieldFromInstruction_4(Insn, 6, 2);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned align = fieldFromInstruction_4(Insn, 4, 1);
+	unsigned size = 1 << fieldFromInstruction_4(Insn, 6, 2);
 	align *= 2 * size;
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VLD2DUPd16: case ARM_VLD2DUPd32: case ARM_VLD2DUPd8:
-		case ARM_VLD2DUPd16wb_fixed: case ARM_VLD2DUPd16wb_register:
-		case ARM_VLD2DUPd32wb_fixed: case ARM_VLD2DUPd32wb_register:
-		case ARM_VLD2DUPd8wb_fixed: case ARM_VLD2DUPd8wb_register:
-			if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		case ARM_VLD2DUPd16x2: case ARM_VLD2DUPd32x2: case ARM_VLD2DUPd8x2:
-		case ARM_VLD2DUPd16x2wb_fixed: case ARM_VLD2DUPd16x2wb_register:
-		case ARM_VLD2DUPd32x2wb_fixed: case ARM_VLD2DUPd32x2wb_register:
-		case ARM_VLD2DUPd8x2wb_fixed: case ARM_VLD2DUPd8x2wb_register:
-			if (!Check(&S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-
-		default:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
+	case ARM_VLD2DUPd16:
+	case ARM_VLD2DUPd32:
+	case ARM_VLD2DUPd8:
+	case ARM_VLD2DUPd16wb_fixed:
+	case ARM_VLD2DUPd16wb_register:
+	case ARM_VLD2DUPd32wb_fixed:
+	case ARM_VLD2DUPd32wb_register:
+	case ARM_VLD2DUPd8wb_fixed:
+	case ARM_VLD2DUPd8wb_register:
+		if (!Check(&S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VLD2DUPd16x2:
+	case ARM_VLD2DUPd32x2:
+	case ARM_VLD2DUPd8x2:
+	case ARM_VLD2DUPd16x2wb_fixed:
+	case ARM_VLD2DUPd16x2wb_register:
+	case ARM_VLD2DUPd32x2wb_fixed:
+	case ARM_VLD2DUPd32x2wb_register:
+	case ARM_VLD2DUPd8x2wb_fixed:
+	case ARM_VLD2DUPd8x2wb_register:
+		if (!Check(&S,
+				   DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
 	}
 
 	if (Rm != 0xF)
-		MCOperand_CreateImm0(Inst, 0);
+		MCOperand_CreateImm0(Inst, (0));
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
+	MCOperand_CreateImm0(Inst, (align));
 
 	if (Rm != 0xD && Rm != 0xF) {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
@@ -3240,25 +3630,25 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rn, Rm, inc;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
-	inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
 
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder)))
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder)))
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address,
+										  Decoder)))
 		return MCDisassembler_Fail;
-
 	if (Rm != 0xF) {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 			return MCDisassembler_Fail;
@@ -3266,11 +3656,10 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, 0);
+	MCOperand_CreateImm0(Inst, (0));
 
 	if (Rm == 0xD)
-		MCOperand_CreateReg0(Inst, 0);
+		MCOperand_CreateReg0(Inst, (0));
 	else if (Rm != 0xF) {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 			return MCDisassembler_Fail;
@@ -3280,17 +3669,18 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rn, Rm, size, inc, align;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
-	size = fieldFromInstruction_4(Insn, 6, 2);
-	inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
-	align = fieldFromInstruction_4(Insn, 4, 1);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned size = fieldFromInstruction_4(Insn, 6, 2);
+	unsigned inc = fieldFromInstruction_4(Insn, 5, 1) + 1;
+	unsigned align = fieldFromInstruction_4(Insn, 4, 1);
 
 	if (size == 0x3) {
 		if (align == 0)
@@ -3307,16 +3697,15 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder)))
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, (Rd + inc) % 32, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2*inc) % 32, Address, Decoder)))
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 2 * inc) % 32, Address,
+										  Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3*inc) % 32, Address, Decoder)))
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, (Rd + 3 * inc) % 32, Address,
+										  Decoder)))
 		return MCDisassembler_Fail;
-
 	if (Rm != 0xF) {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 			return MCDisassembler_Fail;
@@ -3324,11 +3713,10 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
+	MCOperand_CreateImm0(Inst, (align));
 
 	if (Rm == 0xD)
-		MCOperand_CreateReg0(Inst, 0);
+		MCOperand_CreateReg0(Inst, (0));
 	else if (Rm != 0xF) {
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 			return MCDisassembler_Fail;
@@ -3337,19 +3725,20 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst *Inst, unsigned Insn,
 	return S;
 }
 
-static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeVMOVModImmInstruction(MCInst *Inst, unsigned Insn,
+												uint64_t Address,
+												const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned imm, Q;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	imm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
 	imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
 	imm |= fieldFromInstruction_4(Insn, 24, 1) << 7;
 	imm |= fieldFromInstruction_4(Insn, 8, 4) << 8;
 	imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
-	Q = fieldFromInstruction_4(Insn, 6, 1);
+	unsigned Q = fieldFromInstruction_4(Insn, 6, 1);
 
 	if (Q) {
 		if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -3359,114 +3748,165 @@ static DecodeStatus DecodeNEONModImmInstruction(MCInst *Inst, unsigned Insn,
 			return MCDisassembler_Fail;
 	}
 
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VORRiv4i16:
-		case ARM_VORRiv2i32:
-		case ARM_VBICiv4i16:
-		case ARM_VBICiv2i32:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		case ARM_VORRiv8i16:
-		case ARM_VORRiv4i32:
-		case ARM_VBICiv8i16:
-		case ARM_VBICiv4i32:
-			if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_VORRiv4i16:
+	case ARM_VORRiv2i32:
+	case ARM_VBICiv4i16:
+	case ARM_VBICiv2i32:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_VORRiv8i16:
+	case ARM_VORRiv4i32:
+	case ARM_VBICiv8i16:
+	case ARM_VBICiv4i32:
+		if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	return S;
 }
 
-static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeMVEModImmInstruction(MCInst *Inst, unsigned Insn,
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rm, size;
+
+	unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
+				   fieldFromInstruction_4(Insn, 13, 3));
+	unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
+	imm |= fieldFromInstruction_4(Insn, 16, 3) << 4;
+	imm |= fieldFromInstruction_4(Insn, 28, 1) << 7;
+	imm |= cmode << 8;
+	imm |= fieldFromInstruction_4(Insn, 5, 1) << 12;
+
+	if (cmode == 0xF && MCInst_getOpcode(Inst) == ARM_MVE_VMVNimmi32)
+		return MCDisassembler_Fail;
+
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateImm0(Inst, (imm));
+
+	MCOperand_CreateImm0(Inst, (ARMVCC_None));
+	MCOperand_CreateReg0(Inst, (0));
+	MCOperand_CreateImm0(Inst, (0));
+
+	return S;
+}
+
+static DecodeStatus DecodeMVEVADCInstruction(MCInst *Inst, unsigned Insn,
+											 uint64_t Address,
+											 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Qd = fieldFromInstruction_4(Insn, 13, 3);
+	Qd |= fieldFromInstruction_4(Insn, 22, 1) << 3;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
+
+	unsigned Qn = fieldFromInstruction_4(Insn, 17, 3);
+	Qn |= fieldFromInstruction_4(Insn, 7, 1) << 3;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	unsigned Qm = fieldFromInstruction_4(Insn, 1, 3);
+	Qm |= fieldFromInstruction_4(Insn, 5, 1) << 3;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!fieldFromInstruction_4(Insn, 12, 1)) // I bit clear => need input FPSCR
+		MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
+	MCOperand_CreateImm0(Inst, (Qd));
+
+	return S;
+}
+
+static DecodeStatus DecodeVSHLMaxInstruction(MCInst *Inst, unsigned Insn,
+											 uint64_t Address,
+											 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
 	Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 18, 2);
+	unsigned size = fieldFromInstruction_4(Insn, 18, 2);
 
 	if (!Check(&S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, 8 << size);
+	MCOperand_CreateImm0(Inst, (8 << size));
 
 	return S;
 }
 
 static DecodeStatus DecodeShiftRight8Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, 8 - Val);
-
+	MCOperand_CreateImm0(Inst, (8 - Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeShiftRight16Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, 16 - Val);
-
+	MCOperand_CreateImm0(Inst, (16 - Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeShiftRight32Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, 32 - Val);
-
+	MCOperand_CreateImm0(Inst, (32 - Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeShiftRight64Imm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, 64 - Val);
-
+	MCOperand_CreateImm0(Inst, (64 - Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rn, Rm, op;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	Rn |= fieldFromInstruction_4(Insn, 7, 1) << 4;
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
 	Rm |= fieldFromInstruction_4(Insn, 5, 1) << 4;
-	op = fieldFromInstruction_4(Insn, 6, 1);
+	unsigned op = fieldFromInstruction_4(Insn, 6, 1);
 
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (op) {
 		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
 			return MCDisassembler_Fail; // Writeback
 	}
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_VTBL2:
-		case ARM_VTBX2:
-			if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
-				return MCDisassembler_Fail;
-			break;
-		default:
-			if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
-				return MCDisassembler_Fail;
+	case ARM_VTBL2:
+	case ARM_VTBX2:
+		if (!Check(&S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
@@ -3476,64 +3916,71 @@ static DecodeStatus DecodeTBLInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeThumbAddSpecialReg(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder)
+											 uint64_t Address,
+											 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned dst = fieldFromInstruction_2(Insn, 8, 3);
 	unsigned imm = fieldFromInstruction_2(Insn, 0, 8);
 
 	if (!Check(&S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	switch(MCInst_getOpcode(Inst)) {
-		default:
-			return MCDisassembler_Fail;
-		case ARM_tADR:
-			break; // tADR does not explicitly represent the PC as an operand.
-		case ARM_tADDrSPi:
-			MCOperand_CreateReg0(Inst, ARM_SP);
-			break;
+	switch (MCInst_getOpcode(Inst)) {
+	default:
+		return MCDisassembler_Fail;
+	case ARM_tADR:
+		break; // tADR does not explicitly represent the PC as an operand.
+	case ARM_tADDrSPi:
+		MCOperand_CreateReg0(Inst, (ARM_SP));
+		break;
 	}
 
-	MCOperand_CreateImm0(Inst, imm);
-
+	MCOperand_CreateImm0(Inst, (imm));
 	return S;
 }
 
 static DecodeStatus DecodeThumbBROperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 12));
-
+	if (!tryAddingSymbolicOperand(Address,
+								  Address + SignExtend32((Val << 1), 12) + 4,
+								  true, 2, Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (SignExtend32((Val << 1), 12)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeT2BROperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+									  uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, SignExtend32(Val, 21));
-
+	if (!tryAddingSymbolicOperand(Address,
+								  Address + SignExtend32((Val), 21) + 4, true,
+								  4, Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (SignExtend32((Val), 21)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbCmpBROperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, Val << 1);
-
+	if (!tryAddingSymbolicOperand(Address, Address + (Val << 1) + 4, true, 2,
+								  Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (Val << 1));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
 	unsigned Rm = fieldFromInstruction_4(Val, 3, 3);
 
 	if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -3541,105 +3988,107 @@ static DecodeStatus DecodeThumbAddrModeRR(MCInst *Inst, unsigned Val,
 }
 
 static DecodeStatus DecodeThumbAddrModeIS(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 0, 3);
 	unsigned imm = fieldFromInstruction_4(Val, 3, 5);
 
 	if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return S;
 }
 
 static DecodeStatus DecodeThumbAddrModePC(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	unsigned imm = Val << 2;
 
-	MCOperand_CreateImm0(Inst, imm);
-	//tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
+	MCOperand_CreateImm0(Inst, (imm));
+	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4,
+									Decoder);
 
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbAddrModeSP(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
-	MCOperand_CreateReg0(Inst, ARM_SP);
-	MCOperand_CreateImm0(Inst, Val);
+	MCOperand_CreateReg0(Inst, (ARM_SP));
+	MCOperand_CreateImm0(Inst, (Val));
 
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeT2AddrModeSOReg(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 6, 4);
 	unsigned Rm = fieldFromInstruction_4(Val, 2, 4);
 	unsigned imm = fieldFromInstruction_4(Val, 0, 2);
 
 	// Thumb stores cannot use PC as dest register.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2STRHs:
-		case ARM_t2STRBs:
-		case ARM_t2STRs:
-			if (Rn == 15)
-				return MCDisassembler_Fail;
-		default:
-			break;
+	case ARM_t2STRHs:
+	case ARM_t2STRBs:
+	case ARM_t2STRs:
+		if (Rn == 15)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return S;
 }
 
 static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+									  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned addrmode;
+
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+
 	bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP);
 	bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
 
 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRBs:
-				MCInst_setOpcode(Inst, ARM_t2LDRBpci);
-				break;
-			case ARM_t2LDRHs:
-				MCInst_setOpcode(Inst, ARM_t2LDRHpci);
-				break;
-			case ARM_t2LDRSHs:
-				MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
-				break;
-			case ARM_t2LDRSBs:
-				MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
-				break;
-			case ARM_t2LDRs:
-				MCInst_setOpcode(Inst, ARM_t2LDRpci);
-				break;
-			case ARM_t2PLDs:
-				MCInst_setOpcode(Inst, ARM_t2PLDpci);
-				break;
-			case ARM_t2PLIs:
-				MCInst_setOpcode(Inst, ARM_t2PLIpci);
-				break;
-			default:
-				return MCDisassembler_Fail;
+		case ARM_t2LDRBs:
+			MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
+			break;
+		case ARM_t2LDRHs:
+			MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
+			break;
+		case ARM_t2LDRSHs:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
+			break;
+		case ARM_t2LDRSBs:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
+			break;
+		case ARM_t2LDRs:
+			MCInst_setOpcode(Inst, (ARM_t2LDRpci));
+			break;
+		case ARM_t2PLDs:
+			MCInst_setOpcode(Inst, (ARM_t2PLDpci));
+			break;
+		case ARM_t2PLIs:
+			MCInst_setOpcode(Inst, (ARM_t2PLIpci));
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
 
 		return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
@@ -3647,38 +4096,38 @@ static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
 
 	if (Rt == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRSHs:
-				return MCDisassembler_Fail;
-			case ARM_t2LDRHs:
-				MCInst_setOpcode(Inst, ARM_t2PLDWs);
-				break;
-			case ARM_t2LDRSBs:
-				MCInst_setOpcode(Inst, ARM_t2PLIs);
-			default:
-				break;
+		case ARM_t2LDRSHs:
+			return MCDisassembler_Fail;
+		case ARM_t2LDRHs:
+			MCInst_setOpcode(Inst, (ARM_t2PLDWs));
+			break;
+		case ARM_t2LDRSBs:
+			MCInst_setOpcode(Inst, (ARM_t2PLIs));
+			break;
+		default:
+			break;
 		}
 	}
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2PLDs:
-			break;
-		case ARM_t2PLIs:
-			if (!hasV7Ops)
-				return MCDisassembler_Fail;
-			break;
-		case ARM_t2PLDWs:
-			if (!hasV7Ops || !hasMP)
-				return MCDisassembler_Fail;
-			break;
-		default:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
-				return MCDisassembler_Fail;
+	case ARM_t2PLDs:
+		break;
+	case ARM_t2PLIs:
+		if (!hasV7Ops)
+			return MCDisassembler_Fail;
+		break;
+	case ARM_t2PLDWs:
+		if (!hasV7Ops || !hasMP)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
-	addrmode = fieldFromInstruction_4(Insn, 4, 2);
+	unsigned addrmode = fieldFromInstruction_4(Insn, 4, 2);
 	addrmode |= fieldFromInstruction_4(Insn, 0, 4) << 2;
 	addrmode |= fieldFromInstruction_4(Insn, 16, 4) << 6;
-
 	if (!Check(&S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -3686,168 +4135,167 @@ static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder)
+									 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned U = fieldFromInstruction_4(Insn, 9, 1);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
+	imm |= (U << 8);
+	imm |= (Rn << 9);
 	unsigned add = fieldFromInstruction_4(Insn, 9, 1);
+
 	bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP);
 	bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
 
-	imm |= (U << 8);
-	imm |= (Rn << 9);
-
 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRi8:
-				MCInst_setOpcode(Inst, ARM_t2LDRpci);
-				break;
-			case ARM_t2LDRBi8:
-				MCInst_setOpcode(Inst, ARM_t2LDRBpci);
-				break;
-			case ARM_t2LDRSBi8:
-				MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
-				break;
-			case ARM_t2LDRHi8:
-				MCInst_setOpcode(Inst, ARM_t2LDRHpci);
-				break;
-			case ARM_t2LDRSHi8:
-				MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
-				break;
-			case ARM_t2PLDi8:
-				MCInst_setOpcode(Inst, ARM_t2PLDpci);
-				break;
-			case ARM_t2PLIi8:
-				MCInst_setOpcode(Inst, ARM_t2PLIpci);
-				break;
-			default:
-				return MCDisassembler_Fail;
+		case ARM_t2LDRi8:
+			MCInst_setOpcode(Inst, (ARM_t2LDRpci));
+			break;
+		case ARM_t2LDRBi8:
+			MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
+			break;
+		case ARM_t2LDRSBi8:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
+			break;
+		case ARM_t2LDRHi8:
+			MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
+			break;
+		case ARM_t2LDRSHi8:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
+			break;
+		case ARM_t2PLDi8:
+			MCInst_setOpcode(Inst, (ARM_t2PLDpci));
+			break;
+		case ARM_t2PLIi8:
+			MCInst_setOpcode(Inst, (ARM_t2PLIpci));
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
-
 		return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
 	}
 
 	if (Rt == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRSHi8:
-				return MCDisassembler_Fail;
-			case ARM_t2LDRHi8:
-				if (!add)
-					MCInst_setOpcode(Inst, ARM_t2PLDWi8);
-				break;
-			case ARM_t2LDRSBi8:
-				MCInst_setOpcode(Inst, ARM_t2PLIi8);
-				break;
-			default:
-				break;
+		case ARM_t2LDRSHi8:
+			return MCDisassembler_Fail;
+		case ARM_t2LDRHi8:
+			if (!add)
+				MCInst_setOpcode(Inst, (ARM_t2PLDWi8));
+			break;
+		case ARM_t2LDRSBi8:
+			MCInst_setOpcode(Inst, (ARM_t2PLIi8));
+			break;
+		default:
+			break;
 		}
 	}
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2PLDi8:
-			break;
-		case ARM_t2PLIi8:
-			if (!hasV7Ops)
-				return MCDisassembler_Fail;
-			break;
-		case ARM_t2PLDWi8:
-			if (!hasV7Ops || !hasMP)
-				return MCDisassembler_Fail;
-			break;
-		default:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
-				return MCDisassembler_Fail;
+	case ARM_t2PLDi8:
+		break;
+	case ARM_t2PLIi8:
+		if (!hasV7Ops)
+			return MCDisassembler_Fail;
+		break;
+	case ARM_t2PLDWi8:
+		if (!hasV7Ops || !hasMP)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
 	if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	return S;
 }
 
 static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder)
+									  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
+	imm |= (Rn << 13);
+
 	bool hasMP = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP);
 	bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
 
-	imm |= (Rn << 13);
-
 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRi12:
-				MCInst_setOpcode(Inst, ARM_t2LDRpci);
-				break;
-			case ARM_t2LDRHi12:
-				MCInst_setOpcode(Inst, ARM_t2LDRHpci);
-				break;
-			case ARM_t2LDRSHi12:
-				MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
-				break;
-			case ARM_t2LDRBi12:
-				MCInst_setOpcode(Inst, ARM_t2LDRBpci);
-				break;
-			case ARM_t2LDRSBi12:
-				MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
-				break;
-			case ARM_t2PLDi12:
-				MCInst_setOpcode(Inst, ARM_t2PLDpci);
-				break;
-			case ARM_t2PLIi12:
-				MCInst_setOpcode(Inst, ARM_t2PLIpci);
-				break;
-			default:
-				return MCDisassembler_Fail;
+		case ARM_t2LDRi12:
+			MCInst_setOpcode(Inst, (ARM_t2LDRpci));
+			break;
+		case ARM_t2LDRHi12:
+			MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
+			break;
+		case ARM_t2LDRSHi12:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
+			break;
+		case ARM_t2LDRBi12:
+			MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
+			break;
+		case ARM_t2LDRSBi12:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
+			break;
+		case ARM_t2PLDi12:
+			MCInst_setOpcode(Inst, (ARM_t2PLDpci));
+			break;
+		case ARM_t2PLIi12:
+			MCInst_setOpcode(Inst, (ARM_t2PLIpci));
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
 		return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
 	}
 
 	if (Rt == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRSHi12:
-				return MCDisassembler_Fail;
-			case ARM_t2LDRHi12:
-				MCInst_setOpcode(Inst, ARM_t2PLDWi12);
-				break;
-			case ARM_t2LDRSBi12:
-				MCInst_setOpcode(Inst, ARM_t2PLIi12);
-				break;
-			default:
-				break;
+		case ARM_t2LDRSHi12:
+			return MCDisassembler_Fail;
+		case ARM_t2LDRHi12:
+			MCInst_setOpcode(Inst, (ARM_t2PLDWi12));
+			break;
+		case ARM_t2LDRSBi12:
+			MCInst_setOpcode(Inst, (ARM_t2PLIi12));
+			break;
+		default:
+			break;
 		}
 	}
 
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2PLDi12:
-			break;
-		case ARM_t2PLIi12:
-			if (!hasV7Ops)
-				return MCDisassembler_Fail;
-			break;
-		case ARM_t2PLDWi12:
-			if (!hasV7Ops || !hasMP)
-				return MCDisassembler_Fail;
-			break;
-		default:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
-				return MCDisassembler_Fail;
+	case ARM_t2PLDi12:
+		break;
+	case ARM_t2PLIi12:
+		if (!hasV7Ops)
+			return MCDisassembler_Fail;
+		break;
+	case ARM_t2PLDWi12:
+		if (!hasV7Ops || !hasMP)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
 	if (!Check(&S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	return S;
 }
 
-static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder)
+static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -3858,72 +4306,71 @@ static DecodeStatus DecodeT2LoadT(MCInst *Inst, unsigned Insn,
 
 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRT:
-				MCInst_setOpcode(Inst, ARM_t2LDRpci);
-				break;
-			case ARM_t2LDRBT:
-				MCInst_setOpcode(Inst, ARM_t2LDRBpci);
-				break;
-			case ARM_t2LDRHT:
-				MCInst_setOpcode(Inst, ARM_t2LDRHpci);
-				break;
-			case ARM_t2LDRSBT:
-				MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
-				break;
-			case ARM_t2LDRSHT:
-				MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
-				break;
-			default:
-				return MCDisassembler_Fail;
+		case ARM_t2LDRT:
+			MCInst_setOpcode(Inst, (ARM_t2LDRpci));
+			break;
+		case ARM_t2LDRBT:
+			MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
+			break;
+		case ARM_t2LDRHT:
+			MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
+			break;
+		case ARM_t2LDRSBT:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
+			break;
+		case ARM_t2LDRSHT:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
-
 		return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
 	}
 
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	return S;
 }
 
 static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void* Decoder)
+									  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned U = fieldFromInstruction_4(Insn, 23, 1);
 	int imm = fieldFromInstruction_4(Insn, 0, 12);
+
 	bool hasV7Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops);
 
 	if (Rt == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDRBpci:
-			case ARM_t2LDRHpci:
-				MCInst_setOpcode(Inst, ARM_t2PLDpci);
-				break;
-			case ARM_t2LDRSBpci:
-				MCInst_setOpcode(Inst, ARM_t2PLIpci);
-				break;
-			case ARM_t2LDRSHpci:
-				return MCDisassembler_Fail;
-			default:
-				break;
+		case ARM_t2LDRBpci:
+		case ARM_t2LDRHpci:
+			MCInst_setOpcode(Inst, (ARM_t2PLDpci));
+			break;
+		case ARM_t2LDRSBpci:
+			MCInst_setOpcode(Inst, (ARM_t2PLIpci));
+			break;
+		case ARM_t2LDRSHpci:
+			return MCDisassembler_Fail;
+		default:
+			break;
 		}
 	}
 
-	switch(MCInst_getOpcode(Inst)) {
-		case ARM_t2PLDpci:
-			break;
-		case ARM_t2PLIpci:
-			if (!hasV7Ops)
-				return MCDisassembler_Fail;
-			break;
-		default:
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
-				return MCDisassembler_Fail;
+	switch (MCInst_getOpcode(Inst)) {
+	case ARM_t2PLDpci:
+		break;
+	case ARM_t2PLIpci:
+		if (!hasV7Ops)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+			return MCDisassembler_Fail;
 	}
 
 	if (!U) {
@@ -3933,76 +4380,127 @@ static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
 		else
 			imm = -imm;
 	}
-
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return S;
 }
 
-static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeT2Imm8S4(MCInst *Inst, unsigned Val, uint64_t Address,
+								   const void *Decoder)
 {
 	if (Val == 0)
-		MCOperand_CreateImm0(Inst, INT32_MIN);
+		MCOperand_CreateImm0(Inst, (INT32_MIN));
 	else {
 		int imm = Val & 0xFF;
 
-		if (!(Val & 0x100)) imm *= -1;
+		if (!(Val & 0x100))
+			imm *= -1;
+		MCOperand_CreateImm0(Inst, (imm * 4));
+	}
 
-		MCOperand_CreateImm0(Inst, imm * 4);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeT2Imm7S4(MCInst *Inst, unsigned Val, uint64_t Address,
+								   const void *Decoder)
+{
+	if (Val == 0)
+		MCOperand_CreateImm0(Inst, (INT32_MIN));
+	else {
+		int imm = Val & 0x7F;
+
+		if (!(Val & 0x80))
+			imm *= -1;
+		MCOperand_CreateImm0(Inst, (imm * 4));
 	}
 
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 9, 4);
 	unsigned imm = fieldFromInstruction_4(Val, 0, 9);
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
 
 	return S;
 }
 
-static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst,unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeT2AddrModeImm7s4(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
+	unsigned imm = fieldFromInstruction_4(Val, 0, 8);
+
+	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst *Inst, unsigned Val,
+												uint64_t Address,
+												const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 8, 4);
 	unsigned imm = fieldFromInstruction_4(Val, 0, 8);
 
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return S;
 }
 
-static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeT2Imm8(MCInst *Inst, unsigned Val, uint64_t Address,
+								 const void *Decoder)
 {
 	int imm = Val & 0xFF;
-
 	if (Val == 0)
 		imm = INT32_MIN;
 	else if (!(Val & 0x100))
 		imm *= -1;
-
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return MCDisassembler_Success;
 }
 
-static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+#define DEFINE_DecodeT2Imm7(shift)                                             \
+	static DecodeStatus CONCAT(DecodeT2Imm7, shift)(                           \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		int imm = Val & 0x7F;                                                  \
+		if (Val == 0)                                                          \
+			imm = INT32_MIN;                                                   \
+		else if (!(Val & 0x80))                                                \
+			imm *= -1;                                                         \
+		if (imm != INT32_MIN)                                                  \
+			imm *= (1U << shift);                                              \
+		MCOperand_CreateImm0(Inst, (imm));                                     \
+                                                                               \
+		return MCDisassembler_Success;                                         \
+	}
+DEFINE_DecodeT2Imm7(0) DEFINE_DecodeT2Imm7(1) DEFINE_DecodeT2Imm7(2)
+
+	static DecodeStatus
+	DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val, uint64_t Address,
+						 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -4011,85 +4509,129 @@ static DecodeStatus DecodeT2AddrModeImm8(MCInst *Inst, unsigned Val,
 
 	// Thumb stores cannot use PC as dest register.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2STRT:
-		case ARM_t2STRBT:
-		case ARM_t2STRHT:
-		case ARM_t2STRi8:
-		case ARM_t2STRHi8:
-		case ARM_t2STRBi8:
-			if (Rn == 15)
-				return MCDisassembler_Fail;
-			break;
-		default:
-			break;
+	case ARM_t2STRT:
+	case ARM_t2STRBT:
+	case ARM_t2STRHT:
+	case ARM_t2STRi8:
+	case ARM_t2STRHi8:
+	case ARM_t2STRBi8:
+		if (Rn == 15)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	// Some instructions always use an additive offset.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2LDRT:
-		case ARM_t2LDRBT:
-		case ARM_t2LDRHT:
-		case ARM_t2LDRSBT:
-		case ARM_t2LDRSHT:
-		case ARM_t2STRT:
-		case ARM_t2STRBT:
-		case ARM_t2STRHT:
-			imm |= 0x100;
-			break;
-		default:
-			break;
+	case ARM_t2LDRT:
+	case ARM_t2LDRBT:
+	case ARM_t2LDRHT:
+	case ARM_t2LDRSBT:
+	case ARM_t2LDRSHT:
+	case ARM_t2STRT:
+	case ARM_t2STRBT:
+	case ARM_t2STRHT:
+		imm |= 0x100;
+		break;
+	default:
+		break;
 	}
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
 
 	return S;
 }
 
-static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+#define DEFINE_DecodeTAddrModeImm7(shift)                                      \
+	static DecodeStatus CONCAT(DecodeTAddrModeImm7, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+                                                                               \
+		unsigned Rn = fieldFromInstruction_4(Val, 8, 3);                       \
+		unsigned imm = fieldFromInstruction_4(Val, 0, 8);                      \
+                                                                               \
+		if (!Check(&S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))   \
+			return MCDisassembler_Fail;                                        \
+		if (!Check(&S,                                                         \
+				   CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, Decoder)))  \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		return S;                                                              \
+	}
+DEFINE_DecodeTAddrModeImm7(0) DEFINE_DecodeTAddrModeImm7(1)
+
+#define DEFINE_DecodeT2AddrModeImm7(shift, WriteBack)                          \
+	static DecodeStatus CONCAT(DecodeT2AddrModeImm7,                           \
+							   CONCAT(shift, WriteBack))(                      \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+                                                                               \
+		unsigned Rn = fieldFromInstruction_4(Val, 8, 4);                       \
+		unsigned imm = fieldFromInstruction_4(Val, 0, 8);                      \
+		if (WriteBack) {                                                       \
+			if (!Check(&S,                                                     \
+					   DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))   \
+				return MCDisassembler_Fail;                                    \
+		} else if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address,    \
+														 Decoder)))            \
+			return MCDisassembler_Fail;                                        \
+		if (!Check(&S,                                                         \
+				   CONCAT(DecodeT2Imm7, shift)(Inst, imm, Address, Decoder)))  \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		return S;                                                              \
+	}
+	DEFINE_DecodeT2AddrModeImm7(0, 0) DEFINE_DecodeT2AddrModeImm7(1, 0)
+		DEFINE_DecodeT2AddrModeImm7(2, 0) DEFINE_DecodeT2AddrModeImm7(0, 1)
+			DEFINE_DecodeT2AddrModeImm7(1, 1) DEFINE_DecodeT2AddrModeImm7(2, 1)
+
+				static DecodeStatus
+	DecodeT2LdStPre(MCInst *Inst, unsigned Insn, uint64_t Address,
+					const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned load;
+
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned addr = fieldFromInstruction_4(Insn, 0, 8);
 	addr |= fieldFromInstruction_4(Insn, 9, 1) << 8;
 	addr |= Rn << 9;
-	load = fieldFromInstruction_4(Insn, 20, 1);
+	unsigned load = fieldFromInstruction_4(Insn, 20, 1);
 
 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
-			case ARM_t2LDR_PRE:
-			case ARM_t2LDR_POST:
-				MCInst_setOpcode(Inst, ARM_t2LDRpci);
-				break;
-			case ARM_t2LDRB_PRE:
-			case ARM_t2LDRB_POST:
-				MCInst_setOpcode(Inst, ARM_t2LDRBpci);
-				break;
-			case ARM_t2LDRH_PRE:
-			case ARM_t2LDRH_POST:
-				MCInst_setOpcode(Inst, ARM_t2LDRHpci);
-				break;
-			case ARM_t2LDRSB_PRE:
-			case ARM_t2LDRSB_POST:
-				if (Rt == 15)
-					MCInst_setOpcode(Inst, ARM_t2PLIpci);
-				else
-					MCInst_setOpcode(Inst, ARM_t2LDRSBpci);
-				break;
-			case ARM_t2LDRSH_PRE:
-			case ARM_t2LDRSH_POST:
-				MCInst_setOpcode(Inst, ARM_t2LDRSHpci);
-				break;
-			default:
-				return MCDisassembler_Fail;
+		case ARM_t2LDR_PRE:
+		case ARM_t2LDR_POST:
+			MCInst_setOpcode(Inst, (ARM_t2LDRpci));
+			break;
+		case ARM_t2LDRB_PRE:
+		case ARM_t2LDRB_POST:
+			MCInst_setOpcode(Inst, (ARM_t2LDRBpci));
+			break;
+		case ARM_t2LDRH_PRE:
+		case ARM_t2LDRH_POST:
+			MCInst_setOpcode(Inst, (ARM_t2LDRHpci));
+			break;
+		case ARM_t2LDRSB_PRE:
+		case ARM_t2LDRSB_POST:
+			if (Rt == 15)
+				MCInst_setOpcode(Inst, (ARM_t2PLIpci));
+			else
+				MCInst_setOpcode(Inst, (ARM_t2LDRSBpci));
+			break;
+		case ARM_t2LDRSH_PRE:
+		case ARM_t2LDRSH_POST:
+			MCInst_setOpcode(Inst, (ARM_t2LDRSHpci));
+			break;
+		default:
+			return MCDisassembler_Fail;
 		}
-
 		return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
 	}
 
@@ -4113,45 +4655,46 @@ static DecodeStatus DecodeT2LdStPre(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeT2AddrModeImm12(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										  uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 13, 4);
 	unsigned imm = fieldFromInstruction_4(Val, 0, 12);
 
 	// Thumb stores cannot use PC as dest register.
 	switch (MCInst_getOpcode(Inst)) {
-		case ARM_t2STRi12:
-		case ARM_t2STRBi12:
-		case ARM_t2STRHi12:
-			if (Rn == 15)
-				return MCDisassembler_Fail;
-		default:
-			break;
+	case ARM_t2STRi12:
+	case ARM_t2STRBi12:
+	case ARM_t2STRHi12:
+		if (Rn == 15)
+			return MCDisassembler_Fail;
+		break;
+	default:
+		break;
 	}
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return S;
 }
 
 static DecodeStatus DecodeThumbAddSPImm(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder)
+										uint64_t Address, const void *Decoder)
 {
 	unsigned imm = fieldFromInstruction_2(Insn, 0, 7);
 
-	MCOperand_CreateReg0(Inst, ARM_SP);
-	MCOperand_CreateReg0(Inst, ARM_SP);
-	MCOperand_CreateImm0(Inst, imm);
+	MCOperand_CreateReg0(Inst, (ARM_SP));
+	MCOperand_CreateReg0(Inst, (ARM_SP));
+	MCOperand_CreateImm0(Inst, (imm));
 
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder)
+										uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -4161,17 +4704,14 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
 
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
 			return MCDisassembler_Fail;
-
-		MCOperand_CreateReg0(Inst, ARM_SP);
-
+		MCOperand_CreateReg0(Inst, (ARM_SP));
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
 			return MCDisassembler_Fail;
 	} else if (MCInst_getOpcode(Inst) == ARM_tADDspr) {
 		unsigned Rm = fieldFromInstruction_2(Insn, 3, 4);
 
-		MCOperand_CreateReg0(Inst, ARM_SP);
-		MCOperand_CreateReg0(Inst, ARM_SP);
-
+		MCOperand_CreateReg0(Inst, (ARM_SP));
+		MCOperand_CreateReg0(Inst, (ARM_SP));
 		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
 			return MCDisassembler_Fail;
 	}
@@ -4180,19 +4720,19 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst *Inst, uint16_t Insn,
 }
 
 static DecodeStatus DecodeThumbCPS(MCInst *Inst, uint16_t Insn,
-		uint64_t Address, const void *Decoder)
+								   uint64_t Address, const void *Decoder)
 {
 	unsigned imod = fieldFromInstruction_2(Insn, 4, 1) | 0x2;
 	unsigned flags = fieldFromInstruction_2(Insn, 0, 3);
 
-	MCOperand_CreateImm0(Inst, imod);
-	MCOperand_CreateImm0(Inst, flags);
+	MCOperand_CreateImm0(Inst, (imod));
+	MCOperand_CreateImm0(Inst, (flags));
 
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+									 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
@@ -4200,14 +4740,54 @@ static DecodeStatus DecodePostIdxReg(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, add);
+	MCOperand_CreateImm0(Inst, (add));
 
 	return S;
 }
 
-static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeMveAddrModeRQ(MCInst *Inst, unsigned Insn,
+										uint64_t Address, const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	unsigned Rn = fieldFromInstruction_4(Insn, 3, 4);
+	unsigned Qm = fieldFromInstruction_4(Insn, 0, 3);
+
+	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+#define DEFINE_DecodeMveAddrModeQ(shift)                                       \
+	static DecodeStatus CONCAT(DecodeMveAddrModeQ, shift)(                     \
+		MCInst * Inst, unsigned Insn, uint64_t Address, const void *Decoder)   \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+		unsigned Qm = fieldFromInstruction_4(Insn, 8, 3);                      \
+		int imm = fieldFromInstruction_4(Insn, 0, 7);                          \
+                                                                               \
+		if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))   \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		if (!fieldFromInstruction_4(Insn, 7, 1)) {                             \
+			if (imm == 0)                                                      \
+				imm = INT32_MIN;                                               \
+			else                                                               \
+				imm *= -1;                                                     \
+		}                                                                      \
+		if (imm != INT32_MIN)                                                  \
+			imm *= (1U << shift);                                              \
+		MCOperand_CreateImm0(Inst, (imm));                                     \
+                                                                               \
+		return S;                                                              \
+	}
+DEFINE_DecodeMveAddrModeQ(2) DEFINE_DecodeMveAddrModeQ(3)
+
+	static DecodeStatus
+	DecodeThumbBLXOffset(MCInst *Inst, unsigned Val, uint64_t Address,
+						 const void *Decoder)
 {
 	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
 	// Note only one trailing zero not two.  Also the J1 and J2 values are from
@@ -4222,74 +4802,74 @@ static DecodeStatus DecodeThumbBLXOffset(MCInst *Inst, unsigned Val,
 	unsigned I1 = !(J1 ^ S);
 	unsigned I2 = !(J2 ^ S);
 	unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
-	int imm32 = SignExtend32(tmp << 1, 25);
-
-	MCOperand_CreateImm0(Inst, imm32);
+	int imm32 = SignExtend32((tmp << 1), 25);
 
+	if (!tryAddingSymbolicOperand(Address, (Address & ~2u) + imm32 + 4, true, 4,
+								  Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (imm32));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeCoprocessor(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+									  uint64_t Address, const void *Decoder)
 {
 	if (Val == 0xA || Val == 0xB)
 		return MCDisassembler_Fail;
 
-	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && !(Val == 14 || Val == 15))
+	if (!isValidCoprocessorNumber(Inst, Val))
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, Val);
-
+	MCOperand_CreateImm0(Inst, (Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbTableBranch(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
+
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
 
-	if (Rn == ARM_SP) S = MCDisassembler_SoftFail;
-
+	if (Rn == 13 && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops))
+		S = MCDisassembler_SoftFail;
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	return S;
 }
 
 static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned brtarget;
-	unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
 
+	unsigned pred = fieldFromInstruction_4(Insn, 22, 4);
 	if (pred == 0xE || pred == 0xF) {
-		unsigned imm;
 		unsigned opc = fieldFromInstruction_4(Insn, 4, 28);
 		switch (opc) {
-			default:
-				return MCDisassembler_Fail;
-			case 0xf3bf8f4:
-				MCInst_setOpcode(Inst, ARM_t2DSB);
-				break;
-			case 0xf3bf8f5:
-				MCInst_setOpcode(Inst, ARM_t2DMB);
-				break;
-			case 0xf3bf8f6:
-				MCInst_setOpcode(Inst, ARM_t2ISB);
-				break;
+		default:
+			return MCDisassembler_Fail;
+		case 0xf3bf8f4:
+			MCInst_setOpcode(Inst, (ARM_t2DSB));
+			break;
+		case 0xf3bf8f5:
+			MCInst_setOpcode(Inst, (ARM_t2DMB));
+			break;
+		case 0xf3bf8f6:
+			MCInst_setOpcode(Inst, (ARM_t2ISB));
+			break;
 		}
 
-		imm = fieldFromInstruction_4(Insn, 0, 4);
+		unsigned imm = fieldFromInstruction_4(Insn, 0, 4);
 		return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
 	}
 
-	brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
+	unsigned brtarget = fieldFromInstruction_4(Insn, 0, 11) << 1;
 	brtarget |= fieldFromInstruction_4(Insn, 11, 1) << 19;
 	brtarget |= fieldFromInstruction_4(Insn, 13, 1) << 18;
 	brtarget |= fieldFromInstruction_4(Insn, 16, 6) << 12;
@@ -4297,7 +4877,6 @@ static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -4307,50 +4886,52 @@ static DecodeStatus DecodeThumb2BCCInstruction(MCInst *Inst, unsigned Insn,
 // Decode a shifted immediate operand.  These basically consist
 // of an 8-bit value, and a 4-bit directive that specifies either
 // a splat operation or a rotation.
-static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeT2SOImm(MCInst *Inst, unsigned Val, uint64_t Address,
+								  const void *Decoder)
 {
 	unsigned ctrl = fieldFromInstruction_4(Val, 10, 2);
-
 	if (ctrl == 0) {
 		unsigned byte = fieldFromInstruction_4(Val, 8, 2);
 		unsigned imm = fieldFromInstruction_4(Val, 0, 8);
-
 		switch (byte) {
-			case 0:
-				MCOperand_CreateImm0(Inst, imm);
-				break;
-			case 1:
-				MCOperand_CreateImm0(Inst, (imm << 16) | imm);
-				break;
-			case 2:
-				MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 8));
-				break;
-			case 3:
-				MCOperand_CreateImm0(Inst, (imm << 24) | (imm << 16) | (imm << 8)  |  imm);
-				break;
+		case 0:
+			MCOperand_CreateImm0(Inst, (imm));
+			break;
+		case 1:
+			MCOperand_CreateImm0(Inst, ((imm << 16) | imm));
+			break;
+		case 2:
+			MCOperand_CreateImm0(Inst, ((imm << 24) | (imm << 8)));
+			break;
+		case 3:
+			MCOperand_CreateImm0(
+				Inst, ((imm << 24) | (imm << 16) | (imm << 8) | imm));
+			break;
 		}
 	} else {
 		unsigned unrot = fieldFromInstruction_4(Val, 0, 7) | 0x80;
 		unsigned rot = fieldFromInstruction_4(Val, 7, 5);
 		unsigned imm = (unrot >> rot) | (unrot << ((32 - rot) & 31));
-
-		MCOperand_CreateImm0(Inst, imm);
+		MCOperand_CreateImm0(Inst, (imm));
 	}
 
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+												uint64_t Address,
+												const void *Decoder)
 {
-	MCOperand_CreateImm0(Inst, SignExtend32(Val << 1, 9));
-
+	if (!tryAddingSymbolicOperand(Address,
+								  Address + SignExtend32((Val << 1), 9) + 4,
+								  true, 2, Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (SignExtend32((Val << 1), 9)));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	// Val is passed in as S:J1:J2:imm10:imm11
 	// Note no trailing zero after imm11.  Also the J1 and J2 values are from
@@ -4365,37 +4946,38 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst *Inst, unsigned Val,
 	unsigned I1 = !(J1 ^ S);
 	unsigned I2 = !(J2 ^ S);
 	unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
-	int imm32 = SignExtend32(tmp << 1, 25);
-
-	MCOperand_CreateImm0(Inst, imm32);
+	int imm32 = SignExtend32((tmp << 1), 25);
 
+	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, Inst,
+								  Decoder))
+		MCOperand_CreateImm0(Inst, (imm32));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeMemBarrierOption(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										   uint64_t Address,
+										   const void *Decoder)
 {
 	if (Val & ~0xf)
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, Val);
-
+	MCOperand_CreateImm0(Inst, (Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+												uint64_t Address,
+												const void *Decoder)
 {
 	if (Val & ~0xf)
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, Val);
-
+	MCOperand_CreateImm0(Inst, (Val));
 	return MCDisassembler_Success;
 }
 
-static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val, uint64_t Address,
+								  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 
@@ -4404,62 +4986,86 @@ static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
 
 		// Validate the SYSm value first.
 		switch (ValLow) {
-			case  0: // apsr
-			case  1: // iapsr
-			case  2: // eapsr
-			case  3: // xpsr
-			case  5: // ipsr
-			case  6: // epsr
-			case  7: // iepsr
-			case  8: // msp
-			case  9: // psp
-			case 16: // primask
-			case 20: // control
-				break;
-			case 17: // basepri
-			case 18: // basepri_max
-			case 19: // faultmask
-				if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops))
-					// Values basepri, basepri_max and faultmask are only valid for v7m.
-					return MCDisassembler_Fail;
-				break;
-			case 0x8a: // msplim_ns
-			case 0x8b: // psplim_ns
-			case 0x91: // basepri_ns
-			case 0x93: // faultmask_ns
-				if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps))
-					return MCDisassembler_Fail;
-				// LLVM_FALLTHROUGH;
-			case 10:   // msplim
-			case 11:   // psplim
-			case 0x88: // msp_ns
-			case 0x89: // psp_ns
-			case 0x90: // primask_ns
-			case 0x94: // control_ns
-			case 0x98: // sp_ns
-				if (!ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt))
-					return MCDisassembler_Fail;
-				break;
-			default:
-				return MCDisassembler_SoftFail;
+		case 0:	 // apsr
+		case 1:	 // iapsr
+		case 2:	 // eapsr
+		case 3:	 // xpsr
+		case 5:	 // ipsr
+		case 6:	 // epsr
+		case 7:	 // iepsr
+		case 8:	 // msp
+		case 9:	 // psp
+		case 16: // primask
+		case 20: // control
+			break;
+		case 17: // basepri
+		case 18: // basepri_max
+		case 19: // faultmask
+			if (!(ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)))
+				// Values basepri, basepri_max and faultmask are only valid for
+				// v7m.
+				return MCDisassembler_Fail;
+			break;
+		case 0x8a: // msplim_ns
+		case 0x8b: // psplim_ns
+		case 0x91: // basepri_ns
+		case 0x93: // faultmask_ns
+			if (!(ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps)))
+				return MCDisassembler_Fail;
+			// fall through
+		case 10:   // msplim
+		case 11:   // psplim
+		case 0x88: // msp_ns
+		case 0x89: // psp_ns
+		case 0x90: // primask_ns
+		case 0x94: // control_ns
+		case 0x98: // sp_ns
+			if (!(ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt)))
+				return MCDisassembler_Fail;
+			break;
+		case 0x20: // pac_key_p_0
+		case 0x21: // pac_key_p_1
+		case 0x22: // pac_key_p_2
+		case 0x23: // pac_key_p_3
+		case 0x24: // pac_key_u_0
+		case 0x25: // pac_key_u_1
+		case 0x26: // pac_key_u_2
+		case 0x27: // pac_key_u_3
+		case 0xa0: // pac_key_p_0_ns
+		case 0xa1: // pac_key_p_1_ns
+		case 0xa2: // pac_key_p_2_ns
+		case 0xa3: // pac_key_p_3_ns
+		case 0xa4: // pac_key_u_0_ns
+		case 0xa5: // pac_key_u_1_ns
+		case 0xa6: // pac_key_u_2_ns
+		case 0xa7: // pac_key_u_3_ns
+			if (!(ARM_getFeatureBits(Inst->csh->mode, ARM_FeaturePACBTI)))
+				return MCDisassembler_Fail;
+			break;
+		default:
+			// Architecturally defined as unpredictable
+			S = MCDisassembler_SoftFail;
+			break;
 		}
 
 		if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
 			unsigned Mask = fieldFromInstruction_4(Val, 10, 2);
-			if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops)) {
-				// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
-				// unpredictable.
+			if (!(ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops))) {
+				// The ARMv6-M MSR bits {11-10} can be only 0b10, other values
+				// are unpredictable.
 				if (Mask != 2)
 					S = MCDisassembler_SoftFail;
 			} else {
-				// The ARMv7-M architecture stores an additional 2-bit mask value in
-				// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
-				// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
-				// the NZCVQ bits should be moved by the instruction. Bit mask{0}
-				// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
-				// only if the processor includes the DSP extension.
+				// The ARMv7-M architecture stores an additional 2-bit mask
+				// value in MSR bits {11-10}. The mask is used only with apsr,
+				// iapsr, eapsr and xpsr, it has to be 0b10 in other cases. Bit
+				// mask{1} indicates if the NZCVQ bits should be moved by the
+				// instruction. Bit mask{0} indicates the move for the GE{3:0}
+				// bits, the mask{0} bit can be set only if the processor
+				// includes the DSP extension.
 				if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
-						(!ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && (Mask & 1)))
+					(!(ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP)) &&
+					 (Mask & 1)))
 					S = MCDisassembler_SoftFail;
 			}
 		}
@@ -4468,32 +5074,31 @@ static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
 		if (Val == 0)
 			return MCDisassembler_Fail;
 	}
-
-	MCOperand_CreateImm0(Inst, Val);
+	MCOperand_CreateImm0(Inst, (Val));
 	return S;
 }
 
 static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+									uint64_t Address, const void *Decoder)
 {
 	unsigned R = fieldFromInstruction_4(Val, 5, 1);
 	unsigned SysM = fieldFromInstruction_4(Val, 0, 5);
 
-	// The table of encodings for these banked registers comes from B9.2.3 of the
-	// ARM ARM. There are patterns, but nothing regular enough to make this logic
-	// neater. So by fiat, these values are UNPREDICTABLE:
-	if (!lookupBankedRegByEncoding((R << 5) | SysM))
+	// The table of encodings for these banked registers comes from B9.2.3 of
+	// the ARM ARM. There are patterns, but nothing regular enough to make this
+	// logic neater. So by fiat, these values are UNPREDICTABLE:
+	if (!ARMBankedReg_lookupBankedRegByEncoding((R << 5) | SysM))
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, Val);
-
+	MCOperand_CreateImm0(Inst, (Val));
 	return MCDisassembler_Success;
 }
 
 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
@@ -4503,10 +5108,8 @@ static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -4514,9 +5117,10 @@ static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
@@ -4530,10 +5134,8 @@ static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
 
 	if (!Check(&S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -4541,28 +5143,26 @@ static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+									uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned pred;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
 	imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
 	imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
-	pred = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 
-	if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
+	if (Rn == 0xF || Rn == Rt)
+		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -4570,30 +5170,29 @@ static DecodeStatus DecodeLDRPreImm(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+									uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned pred, Rm;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
 	imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
 	imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
-	pred = fieldFromInstruction_4(Insn, 28, 4);
-	Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
 
-	if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
-	if (Rm == 0xF) S = MCDisassembler_SoftFail;
+	if (Rn == 0xF || Rn == Rt)
+		S = MCDisassembler_SoftFail;
+	if (Rm == 0xF)
+		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -4601,28 +5200,26 @@ static DecodeStatus DecodeLDRPreReg(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+									uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned pred;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
 	imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
 	imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
-	pred = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 
-	if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
+	if (Rn == 0xF || Rn == Rt)
+		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -4630,688 +5227,661 @@ static DecodeStatus DecodeSTRPreImm(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeSTRPreReg(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+									uint64_t Address, const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned pred;
+
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
 	imm |= fieldFromInstruction_4(Insn, 16, 4) << 13;
 	imm |= fieldFromInstruction_4(Insn, 23, 1) << 12;
-	pred = fieldFromInstruction_4(Insn, 28, 4);
+	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 
-	if (Rn == 0xF || Rn == Rt) S = MCDisassembler_SoftFail;
+	if (Rn == 0xF || Rn == Rt)
+		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		break;
+	case 1:
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 2;
+		break;
+	case 2:
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 7, 1);
+
+		switch (fieldFromInstruction_4(Insn, 4, 2)) {
+		case 0:
+			align = 0;
+			break;
+		case 3:
+			align = 4;
+			break;
+		default:
+			return MCDisassembler_Fail;
+		}
+		break;
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		break;
+	case 1:
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 2;
+		break;
+	case 2:
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 7, 1);
+
+		switch (fieldFromInstruction_4(Insn, 4, 2)) {
+		case 0:
+			align = 0;
+			break;
+		case 3:
+			align = 4;
+			break;
+		default:
+			return MCDisassembler_Fail;
+		}
+		break;
+	}
+
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	unsigned inc = 1;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 2;
+		break;
+	case 1:
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 4;
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			inc = 2;
+		break;
+	case 2:
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 7, 1);
+		if (fieldFromInstruction_4(Insn, 4, 1) != 0)
+			align = 8;
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			inc = 2;
+		break;
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	unsigned inc = 1;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 2;
+		break;
+	case 1:
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 4;
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			inc = 2;
+		break;
+	case 2:
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 7, 1);
+		if (fieldFromInstruction_4(Insn, 4, 1) != 0)
+			align = 8;
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			inc = 2;
+		break;
+	}
+
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	unsigned inc = 1;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		break;
+	case 1:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			inc = 2;
+		break;
+	case 2:
+		if (fieldFromInstruction_4(Insn, 4, 2))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 7, 1);
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			inc = 2;
+		break;
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	unsigned inc = 1;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		break;
+	case 1:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			inc = 2;
+		break;
+	case 2:
+		if (fieldFromInstruction_4(Insn, 4, 2))
+			return MCDisassembler_Fail; // UNDEFINED
+		index = fieldFromInstruction_4(Insn, 7, 1);
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			inc = 2;
+		break;
+	}
+
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	unsigned inc = 1;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 4;
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		break;
+	case 1:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 8;
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			inc = 2;
+		break;
+	case 2:
+		switch (fieldFromInstruction_4(Insn, 4, 2)) {
+		case 0:
+			align = 0;
+			break;
+		case 3:
+			return MCDisassembler_Fail;
+		default:
+			align = 4 << fieldFromInstruction_4(Insn, 4, 2);
+			break;
+		}
+
+		index = fieldFromInstruction_4(Insn, 7, 1);
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			inc = 2;
+		break;
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
+	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
+	unsigned size = fieldFromInstruction_4(Insn, 10, 2);
+
+	unsigned align = 0;
+	unsigned index = 0;
+	unsigned inc = 1;
+	switch (size) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 4;
+		index = fieldFromInstruction_4(Insn, 5, 3);
+		break;
+	case 1:
+		if (fieldFromInstruction_4(Insn, 4, 1))
+			align = 8;
+		index = fieldFromInstruction_4(Insn, 6, 2);
+		if (fieldFromInstruction_4(Insn, 5, 1))
+			inc = 2;
+		break;
+	case 2:
+		switch (fieldFromInstruction_4(Insn, 4, 2)) {
+		case 0:
+			align = 0;
+			break;
+		case 3:
+			return MCDisassembler_Fail;
+		default:
+			align = 4 << fieldFromInstruction_4(Insn, 4, 2);
+			break;
+		}
+
+		index = fieldFromInstruction_4(Insn, 7, 1);
+		if (fieldFromInstruction_4(Insn, 6, 1))
+			inc = 2;
+		break;
+	}
+
+	if (Rm != 0xF) { // Writeback
+		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+			return MCDisassembler_Fail;
+	}
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (align));
+	if (Rm != 0xF) {
+		if (Rm != 0xD) {
+			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+				return MCDisassembler_Fail;
+		} else
+			MCOperand_CreateReg0(Inst, (0));
+	}
+
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 2 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S,
+			   DecodeDPRRegisterClass(Inst, Rd + 3 * inc, Address, Decoder)))
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (index));
+
+	return S;
+}
+
+static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
+	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
+	Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
+
+	if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
+		S = MCDisassembler_SoftFail;
+
+	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rm = fieldFromInstruction_4(Insn, 5, 1);
+	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
+	Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
+
+	if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
+		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	return S;
-}
-
-static DecodeStatus DecodeVLD1LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			break;
-		case 1:
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 2;
-			break;
-		case 2:
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-
-			index = fieldFromInstruction_4(Insn, 7, 1);
-
-			switch (fieldFromInstruction_4(Insn, 4, 2)) {
-				case 0 :
-					align = 0; break;
-				case 3:
-					align = 4; break;
-				default:
-					return MCDisassembler_Fail;
-			}
-			break;
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVST1LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			break;
-		case 1:
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 2;
-			break;
-		case 2:
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-
-			index = fieldFromInstruction_4(Insn, 7, 1);
-
-			switch (fieldFromInstruction_4(Insn, 4, 2)) {
-				case 0: 
-					align = 0; break;
-				case 3:
-					align = 4; break;
-				default:
-					return MCDisassembler_Fail;
-			}
-			break;
-	}
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVLD2LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0, inc = 1;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 2;
-			break;
-		case 1:
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 4;
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				inc = 2;
-			break;
-		case 2:
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-
-			index = fieldFromInstruction_4(Insn, 7, 1);
-			if (fieldFromInstruction_4(Insn, 4, 1) != 0)
-				align = 8;
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				inc = 2;
-			break;
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVST2LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0, inc = 1;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 2;
-			break;
-		case 1:
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 4;
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				inc = 2;
-			break;
-		case 2:
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-
-			index = fieldFromInstruction_4(Insn, 7, 1);
-			if (fieldFromInstruction_4(Insn, 4, 1) != 0)
-				align = 8;
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				inc = 2;
-			break;
-	}
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVLD3LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0, inc = 1;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			break;
-		case 1:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				inc = 2;
-			break;
-		case 2:
-			if (fieldFromInstruction_4(Insn, 4, 2))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 7, 1);
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				inc = 2;
-			break;
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVST3LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0, inc = 1;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			break;
-		case 1:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				inc = 2;
-			break;
-		case 2:
-			if (fieldFromInstruction_4(Insn, 4, 2))
-				return MCDisassembler_Fail; // UNDEFINED
-			index = fieldFromInstruction_4(Insn, 7, 1);
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				inc = 2;
-			break;
-	}
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVLD4LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0, inc = 1;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 4;
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			break;
-		case 1:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 8;
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				inc = 2;
-			break;
-		case 2:
-			switch (fieldFromInstruction_4(Insn, 4, 2)) {
-				case 0:
-					align = 0; break;
-				case 3:
-					return MCDisassembler_Fail;
-				default:
-					align = 4 << fieldFromInstruction_4(Insn, 4, 2); break;
-			}
-
-			index = fieldFromInstruction_4(Insn, 7, 1);
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				inc = 2;
-			break;
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVST4LN(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned size, align = 0, index = 0, inc = 1;
-	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);
-	unsigned Rd = fieldFromInstruction_4(Insn, 12, 4);
-	Rd |= fieldFromInstruction_4(Insn, 22, 1) << 4;
-	size = fieldFromInstruction_4(Insn, 10, 2);
-
-	switch (size) {
-		default:
-			return MCDisassembler_Fail;
-		case 0:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 4;
-			index = fieldFromInstruction_4(Insn, 5, 3);
-			break;
-		case 1:
-			if (fieldFromInstruction_4(Insn, 4, 1))
-				align = 8;
-			index = fieldFromInstruction_4(Insn, 6, 2);
-			if (fieldFromInstruction_4(Insn, 5, 1))
-				inc = 2;
-			break;
-		case 2:
-			switch (fieldFromInstruction_4(Insn, 4, 2)) {
-				case 0:
-					align = 0; break;
-				case 3:
-					return MCDisassembler_Fail;
-				default:
-					align = 4 << fieldFromInstruction_4(Insn, 4, 2); break;
-			}
-
-			index = fieldFromInstruction_4(Insn, 7, 1);
-			if (fieldFromInstruction_4(Insn, 6, 1))
-				inc = 2;
-			break;
-	}
-
-	if (Rm != 0xF) { // Writeback
-		if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, align);
-
-	if (Rm != 0xF) {
-		if (Rm != 0xD) {
-			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
-				return MCDisassembler_Fail;
-		} else
-			MCOperand_CreateReg0(Inst, 0);
-	}
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 2*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeDPRRegisterClass(Inst, Rd + 3*inc, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, index);
-
-	return S;
-}
-
-static DecodeStatus DecodeVMOVSRR(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rt  = fieldFromInstruction_4(Insn, 12, 4);
-	unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm  = fieldFromInstruction_4(Insn,  5, 1);
-	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
-	Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
-
-	if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
-		S = MCDisassembler_SoftFail;
-
-	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
-		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
-		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
 	return S;
 }
 
-static DecodeStatus DecodeVMOVRRS(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
-{
-	DecodeStatus S = MCDisassembler_Success;
-	unsigned Rt  = fieldFromInstruction_4(Insn, 12, 4);
-	unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
-	unsigned Rm  = fieldFromInstruction_4(Insn,  5, 1);
-	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
-	Rm |= fieldFromInstruction_4(Insn, 0, 4) << 1;
-
-	if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
-		S = MCDisassembler_SoftFail;
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeSPRRegisterClass(Inst, Rm + 1, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
-		return MCDisassembler_Fail;
-
-	return S;
-}
-
-static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn, uint64_t Address,
+							 const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
 	unsigned pred = fieldFromInstruction_4(Insn, 4, 4);
@@ -5325,16 +5895,27 @@ static DecodeStatus DecodeIT(MCInst *Inst, unsigned Insn,
 	if (mask == 0x0)
 		return MCDisassembler_Fail;
 
-	MCOperand_CreateImm0(Inst, pred);
-	MCOperand_CreateImm0(Inst, mask);
+	// IT masks are encoded as a sequence of replacement low-order bits
+	// for the condition code. So if the low bit of the starting
+	// condition code is 1, then we have to flip all the bits above the
+	// terminating bit (which is the lowest 1 bit).
+	if (pred & 1) {
+		unsigned LowBit = mask & -mask;
+		unsigned BitsAboveLowBit = 0xF & (-LowBit << 1);
+		mask ^= BitsAboveLowBit;
+	}
 
+	MCOperand_CreateImm0(Inst, (pred));
+	MCOperand_CreateImm0(Inst, (mask));
 	return S;
 }
 
 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
@@ -5348,22 +5929,18 @@ static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
 
 	if (writeback && (Rn == Rt || Rn == Rt2))
 		Check(&S, MCDisassembler_SoftFail);
-
 	if (Rt == Rt2)
 		Check(&S, MCDisassembler_SoftFail);
 
 	// Rt
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	// Rt2
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	// Writeback operand
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	// addr
 	if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
 		return MCDisassembler_Fail;
@@ -5372,9 +5949,11 @@ static DecodeStatus DecodeT2LDRDPreInstruction(MCInst *Inst, unsigned Insn,
 }
 
 static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+											   uint64_t Address,
+											   const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rt2 = fieldFromInstruction_4(Insn, 8, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
@@ -5392,15 +5971,12 @@ static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
 	// Writeback operand
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	// Rt
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	// Rt2
 	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	// addr
 	if (!Check(&S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
 		return MCDisassembler_Fail;
@@ -5408,276 +5984,257 @@ static DecodeStatus DecodeT2STRDPreInstruction(MCInst *Inst, unsigned Insn,
 	return S;
 }
 
-static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeT2Adr(MCInst *Inst, uint32_t Insn, uint64_t Address,
+								const void *Decoder)
 {
-	unsigned Val;
 	unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
 	unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
+	if (sign1 != sign2)
+		return MCDisassembler_Fail;
+	const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
 
-	if (sign1 != sign2) return MCDisassembler_Fail;
+	DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
 
-	Val = fieldFromInstruction_4(Insn, 0, 8);
+	unsigned Val = fieldFromInstruction_4(Insn, 0, 8);
 	Val |= fieldFromInstruction_4(Insn, 12, 3) << 8;
 	Val |= fieldFromInstruction_4(Insn, 26, 1) << 11;
-	Val |= sign1 << 12;
-
-	MCOperand_CreateImm0(Inst, SignExtend32(Val, 13));
-
-	return MCDisassembler_Success;
+	// If sign, then it is decreasing the address.
+	if (sign1) {
+		// Following ARMv7 Architecture Manual, when the offset
+		// is zero, it is decoded as a subw, not as a adr.w
+		if (!Val) {
+			MCInst_setOpcode(Inst, (ARM_t2SUBri12));
+			MCOperand_CreateReg0(Inst, (ARM_PC));
+		} else
+			Val = -Val;
+	}
+	MCOperand_CreateImm0(Inst, (Val));
+	return S;
 }
 
 static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
-		uint64_t Address, const void *Decoder)
+											  uint64_t Address,
+											  const void *Decoder)
 {
+	DecodeStatus S = MCDisassembler_Success;
+
 	// Shift of "asr #32" is not allowed in Thumb2 mode.
 	if (Val == 0x20)
-		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, Val);
-
-	return MCDisassembler_Success;
+		S = MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (Val));
+	return S;
 }
 
-static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeSwap(MCInst *Inst, unsigned Insn, uint64_t Address,
+							   const void *Decoder)
 {
-	DecodeStatus S;
-	unsigned Rt   = fieldFromInstruction_4(Insn, 12, 4);
-	unsigned Rt2  = fieldFromInstruction_4(Insn, 0,  4);
-	unsigned Rn   = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
+	unsigned Rt2 = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned pred = fieldFromInstruction_4(Insn, 28, 4);
 
 	if (pred == 0xF)
 		return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
 
-	S = MCDisassembler_Success;
+	DecodeStatus S = MCDisassembler_Success;
 
 	if (Rt == Rn || Rn == Rt2)
 		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 		return MCDisassembler_Fail;
 
 	return S;
 }
 
-static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeVCVTD(MCInst *Inst, unsigned Insn, uint64_t Address,
+								const void *Decoder)
 {
-	DecodeStatus S = MCDisassembler_Success;
-	bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16);
-	unsigned Vm, imm, cmode, op;
-	unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
 
+	bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16);
+
+	unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
 	Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
-	Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
+	unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
 	Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
-	imm = fieldFromInstruction_4(Insn, 16, 6);
-	cmode = fieldFromInstruction_4(Insn, 8, 4);
-	op = fieldFromInstruction_4(Insn, 5, 1);
+	unsigned imm = fieldFromInstruction_4(Insn, 16, 6);
+	unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned op = fieldFromInstruction_4(Insn, 5, 1);
+
+	DecodeStatus S = MCDisassembler_Success;
 
 	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
 	if (!(imm & 0x38)) {
 		if (cmode == 0xF) {
-			if (op == 1) return MCDisassembler_Fail;
-			MCInst_setOpcode(Inst, ARM_VMOVv2f32);
+			if (op == 1)
+				return MCDisassembler_Fail;
+			MCInst_setOpcode(Inst, (ARM_VMOVv2f32));
 		}
-
 		if (hasFullFP16) {
 			if (cmode == 0xE) {
 				if (op == 1) {
-					MCInst_setOpcode(Inst, ARM_VMOVv1i64);
+					MCInst_setOpcode(Inst, (ARM_VMOVv1i64));
 				} else {
-					MCInst_setOpcode(Inst, ARM_VMOVv8i8);
+					MCInst_setOpcode(Inst, (ARM_VMOVv8i8));
 				}
 			}
-
 			if (cmode == 0xD) {
 				if (op == 1) {
-					MCInst_setOpcode(Inst, ARM_VMVNv2i32);
+					MCInst_setOpcode(Inst, (ARM_VMVNv2i32));
 				} else {
-					MCInst_setOpcode(Inst, ARM_VMOVv2i32);
+					MCInst_setOpcode(Inst, (ARM_VMOVv2i32));
 				}
 			}
-
 			if (cmode == 0xC) {
 				if (op == 1) {
-					MCInst_setOpcode(Inst, ARM_VMVNv2i32);
+					MCInst_setOpcode(Inst, (ARM_VMVNv2i32));
 				} else {
-					MCInst_setOpcode(Inst, ARM_VMOVv2i32);
+					MCInst_setOpcode(Inst, (ARM_VMOVv2i32));
 				}
 			}
 		}
-
-		return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
+		return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
 	}
 
-	if (!(imm & 0x20)) return MCDisassembler_Fail;
+	if (!(imm & 0x20))
+		return MCDisassembler_Fail;
 
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, 64 - imm);
+	MCOperand_CreateImm0(Inst, (64 - imm));
 
 	return S;
 }
 
-static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeVCVTQ(MCInst *Inst, unsigned Insn, uint64_t Address,
+								const void *Decoder)
 {
-	DecodeStatus S = MCDisassembler_Success;
+
 	bool hasFullFP16 = ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16);
-	unsigned Vm, imm, cmode, op;
+
 	unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
-
 	Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
-	Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
+	unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
 	Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
-	imm = fieldFromInstruction_4(Insn, 16, 6);
-	cmode = fieldFromInstruction_4(Insn, 8, 4);
-	op = fieldFromInstruction_4(Insn, 5, 1);
+	unsigned imm = fieldFromInstruction_4(Insn, 16, 6);
+	unsigned cmode = fieldFromInstruction_4(Insn, 8, 4);
+	unsigned op = fieldFromInstruction_4(Insn, 5, 1);
 
-	// VMOVv4f32 is ambiguous with these decodings.
-	if (!(imm & 0x38) && cmode == 0xF) {
-		if (op == 1) return MCDisassembler_Fail;
-		MCInst_setOpcode(Inst, ARM_VMOVv4f32);
-		return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
-	}
+	DecodeStatus S = MCDisassembler_Success;
 
 	// If the top 3 bits of imm are clear, this is a VMOV (immediate)
 	if (!(imm & 0x38)) {
 		if (cmode == 0xF) {
-			if (op == 1) return MCDisassembler_Fail;
-			MCInst_setOpcode(Inst, ARM_VMOVv4f32);
+			if (op == 1)
+				return MCDisassembler_Fail;
+			MCInst_setOpcode(Inst, (ARM_VMOVv4f32));
 		}
-
 		if (hasFullFP16) {
 			if (cmode == 0xE) {
 				if (op == 1) {
-					MCInst_setOpcode(Inst, ARM_VMOVv2i64);
+					MCInst_setOpcode(Inst, (ARM_VMOVv2i64));
 				} else {
-					MCInst_setOpcode(Inst, ARM_VMOVv16i8);
+					MCInst_setOpcode(Inst, (ARM_VMOVv16i8));
 				}
 			}
-
 			if (cmode == 0xD) {
 				if (op == 1) {
-					MCInst_setOpcode(Inst, ARM_VMVNv4i32);
+					MCInst_setOpcode(Inst, (ARM_VMVNv4i32));
 				} else {
-					MCInst_setOpcode(Inst, ARM_VMOVv4i32);
+					MCInst_setOpcode(Inst, (ARM_VMOVv4i32));
 				}
 			}
-
 			if (cmode == 0xC) {
 				if (op == 1) {
-					MCInst_setOpcode(Inst, ARM_VMVNv4i32);
+					MCInst_setOpcode(Inst, (ARM_VMVNv4i32));
 				} else {
-					MCInst_setOpcode(Inst, ARM_VMOVv4i32);
+					MCInst_setOpcode(Inst, (ARM_VMOVv4i32));
 				}
 			}
 		}
-
-		return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
+		return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
 	}
 
-	if (!(imm & 0x20)) return MCDisassembler_Fail;
+	if (!(imm & 0x20))
+		return MCDisassembler_Fail;
 
 	if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	MCOperand_CreateImm0(Inst, 64 - imm);
+	MCOperand_CreateImm0(Inst, (64 - imm));
 
 	return S;
 }
 
-static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst *Inst,
+													   unsigned Insn,
+													   uint64_t Address,
+													   const void *Decoder)
 {
-	DecodeStatus S = MCDisassembler_Success;
 	unsigned Vd = (fieldFromInstruction_4(Insn, 12, 4) << 0);
+	Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
 	unsigned Vn = (fieldFromInstruction_4(Insn, 16, 4) << 0);
+	Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4);
 	unsigned Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0);
+	Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
 	unsigned q = (fieldFromInstruction_4(Insn, 6, 1) << 0);
 	unsigned rotate = (fieldFromInstruction_4(Insn, 20, 2) << 0);
 
-	Vd |= (fieldFromInstruction_4(Insn, 22, 1) << 4);
-	Vn |= (fieldFromInstruction_4(Insn, 7, 1) << 4);
-	Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4);
+	DecodeStatus S = MCDisassembler_Success;
 
-	if (q) {
-		if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
-			return MCDisassembler_Fail;
+	typedef DecodeStatus (*DecoderFunction)(
+		MCInst * Inst, unsigned RegNo, uint64_t Address, const void *Decoder);
 
-		if (!Check(&S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
-			return MCDisassembler_Fail;
-
-		if (!Check(&S, DecodeQPRRegisterClass(Inst, Vn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	} else {
-		if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
-			return MCDisassembler_Fail;
-
-		if (!Check(&S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
-			return MCDisassembler_Fail;
-
-		if (!Check(&S, DecodeDPRRegisterClass(Inst, Vn, Address, Decoder)))
-			return MCDisassembler_Fail;
-	}
+	DecoderFunction DestRegDecoder =
+		q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
 
+	if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DestRegDecoder(Inst, Vd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DestRegDecoder(Inst, Vn, Address, Decoder)))
+		return MCDisassembler_Fail;
 	if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	// The lane index does not have any bits in the encoding, because it can only
-	// be 0.
-	MCOperand_CreateImm0(Inst, 0);
-	MCOperand_CreateImm0(Inst, rotate);
+	// The lane index does not have any bits in the encoding, because it can
+	// only be 0.
+	MCOperand_CreateImm0(Inst, (0));
+	MCOperand_CreateImm0(Inst, (rotate));
 
 	return S;
 }
 
-static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val, uint64_t Address,
+							  const void *Decoder)
 {
 	DecodeStatus S = MCDisassembler_Success;
-	unsigned Cond;
+
 	unsigned Rn = fieldFromInstruction_4(Val, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
 	unsigned Rm = fieldFromInstruction_4(Val, 0, 4);
-
 	Rm |= (fieldFromInstruction_4(Val, 23, 1) << 4);
-	Cond = fieldFromInstruction_4(Val, 28, 4);
+	unsigned Cond = fieldFromInstruction_4(Val, 28, 4);
 
 	if (fieldFromInstruction_4(Val, 8, 4) != 0 || Rn == Rt)
 		S = MCDisassembler_SoftFail;
 
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
-	if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 
+	if (!Check(&S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
 		return MCDisassembler_Fail;
-
 	if (!Check(&S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
 		return MCDisassembler_Fail;
 
@@ -5685,9 +6242,11 @@ static DecodeStatus DecodeLDR(MCInst *Inst, unsigned Val,
 }
 
 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+											uint64_t Address,
+											const void *Decoder)
 {
-	DecodeStatus result = MCDisassembler_Success;
+	DecodeStatus S = MCDisassembler_Success;
+
 	unsigned CRm = fieldFromInstruction_4(Val, 0, 4);
 	unsigned opc1 = fieldFromInstruction_4(Val, 4, 4);
 	unsigned cop = fieldFromInstruction_4(Val, 8, 4);
@@ -5698,7 +6257,7 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
 		return MCDisassembler_Fail;
 
 	if (Rt == Rt2)
-		result = MCDisassembler_SoftFail;
+		S = MCDisassembler_SoftFail;
 
 	// We have to check if the instruction is MRRC2
 	// or MCRR2 when constructing the operands for
@@ -5711,54 +6270,883 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val,
 	// and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
 
 	if (MCInst_getOpcode(Inst) == ARM_MRRC2) {
-		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+		if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
 			return MCDisassembler_Fail;
-
-		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+		if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
 			return MCDisassembler_Fail;
 	}
-
-	MCOperand_CreateImm0(Inst, cop);
-	MCOperand_CreateImm0(Inst, opc1);
-
+	MCOperand_CreateImm0(Inst, (cop));
+	MCOperand_CreateImm0(Inst, (opc1));
 	if (MCInst_getOpcode(Inst) == ARM_MCRR2) {
-		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
+		if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
 			return MCDisassembler_Fail;
-
-		if (!Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
+		if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
 			return MCDisassembler_Fail;
 	}
+	MCOperand_CreateImm0(Inst, (CRm));
 
-	MCOperand_CreateImm0(Inst, CRm);
-
-	return result;
+	return S;
 }
 
 static DecodeStatus DecodeForVMRSandVMSR(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
+										 uint64_t Address, const void *Decoder)
 {
-	DecodeStatus result = MCDisassembler_Success;
-	bool HasV8Ops = ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops);
-	unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
 
-	if ((Inst->csh->mode & CS_MODE_THUMB) && !HasV8Ops)  {
-		if (Rt == 13 || Rt == 15)
-			result = MCDisassembler_SoftFail;
+	DecodeStatus S = MCDisassembler_Success;
 
-		Check(&result, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
-	} else
-		Check(&result, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
+	// Add explicit operand for the destination sysreg, for cases where
+	// we have to model it for code generation purposes.
+	switch (MCInst_getOpcode(Inst)) {
+	case ARM_VMSR_FPSCR_NZCVQC:
+		MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
+		break;
+	case ARM_VMSR_P0:
+		MCOperand_CreateReg0(Inst, (ARM_VPR));
+		break;
+	}
 
-	if (Inst->csh->mode & CS_MODE_THUMB) {
-		MCOperand_CreateImm0(Inst, ARMCC_AL);
-		MCOperand_CreateReg0(Inst, 0);
+	if (MCInst_getOpcode(Inst) != ARM_FMSTAT) {
+		unsigned Rt = fieldFromInstruction_4(Val, 12, 4);
+
+		if (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) &&
+			!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops)) {
+			if (Rt == 13 || Rt == 15)
+				S = MCDisassembler_SoftFail;
+			Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+		} else
+			Check(&S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
+	}
+
+	// Add explicit operand for the source sysreg, similarly to above.
+	switch (MCInst_getOpcode(Inst)) {
+	case ARM_VMRS_FPSCR_NZCVQC:
+		MCOperand_CreateReg0(Inst, (ARM_FPSCR_NZCV));
+		break;
+	case ARM_VMRS_P0:
+		MCOperand_CreateReg0(Inst, (ARM_VPR));
+		break;
+	}
+
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb)) {
+		MCOperand_CreateImm0(Inst, (ARMCC_AL));
+		MCOperand_CreateReg0(Inst, (0));
 	} else {
 		unsigned pred = fieldFromInstruction_4(Val, 28, 4);
-		if (!Check(&result, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+		if (!Check(&S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
 			return MCDisassembler_Fail;
 	}
 
-	return result;
+	return S;
 }
 
-#endif
+#define DEFINE_DecodeBFLabelOperand(isSigned, isNeg, zeroPermitted, size)      \
+	static DecodeStatus CONCAT(                                                \
+		DecodeBFLabelOperand,                                                  \
+		CONCAT(isSigned, CONCAT(isNeg, CONCAT(zeroPermitted, size))))(         \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+		if (Val == 0 && !zeroPermitted)                                        \
+			S = MCDisassembler_Fail;                                           \
+                                                                               \
+		uint64_t DecVal;                                                       \
+		if (isSigned)                                                          \
+			DecVal = SignExtend32((Val << 1), size + 1);                       \
+		else                                                                   \
+			DecVal = (Val << 1);                                               \
+                                                                               \
+		if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4,  \
+									  Inst, Decoder))                          \
+			MCOperand_CreateImm0(Inst, (isNeg ? -DecVal : DecVal));            \
+		return S;                                                              \
+	}
+DEFINE_DecodeBFLabelOperand(false, false, false, 4)
+	DEFINE_DecodeBFLabelOperand(true, false, true, 18)
+		DEFINE_DecodeBFLabelOperand(true, false, true, 12)
+			DEFINE_DecodeBFLabelOperand(true, false, true, 16)
+				DEFINE_DecodeBFLabelOperand(false, true, true, 11)
+					DEFINE_DecodeBFLabelOperand(false, false, true, 11)
+
+						static DecodeStatus
+	DecodeBFAfterTargetOperand(MCInst *Inst, unsigned Val, uint64_t Address,
+							   const void *Decoder)
+{
+
+	uint64_t LocImm = MCOperand_getImm(MCInst_getOperand(Inst, (0)));
+	Val = LocImm + (2 << Val);
+	if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
+								  Decoder))
+		MCOperand_CreateImm0(Inst, (Val));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodePredNoALOperand(MCInst *Inst, unsigned Val,
+										  uint64_t Address, const void *Decoder)
+{
+	if (Val >= ARMCC_AL) // also exclude the non-condition NV
+		return MCDisassembler_Fail;
+	MCOperand_CreateImm0(Inst, (Val));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLOLoop(MCInst *Inst, unsigned Insn, uint64_t Address,
+								 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	if (MCInst_getOpcode(Inst) == ARM_MVE_LCTP)
+		return S;
+
+	unsigned Imm = fieldFromInstruction_4(Insn, 11, 1) |
+				   fieldFromInstruction_4(Insn, 1, 10) << 1;
+	switch (MCInst_getOpcode(Inst)) {
+	case ARM_t2LEUpdate:
+	case ARM_MVE_LETP:
+		MCOperand_CreateReg0(Inst, (ARM_LR));
+		MCOperand_CreateReg0(Inst, (ARM_LR));
+		// fall through
+	case ARM_t2LE:
+		if (!Check(&S, CONCAT(DecodeBFLabelOperand,
+							  CONCAT(false, CONCAT(true, CONCAT(true, 11))))(
+						   Inst, Imm, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_t2WLS:
+	case ARM_MVE_WLSTP_8:
+	case ARM_MVE_WLSTP_16:
+	case ARM_MVE_WLSTP_32:
+	case ARM_MVE_WLSTP_64:
+		MCOperand_CreateReg0(Inst, (ARM_LR));
+		if (!Check(&S, DecoderGPRRegisterClass(
+						   Inst, fieldFromInstruction_4(Insn, 16, 4), Address,
+						   Decoder)) ||
+			!Check(&S, CONCAT(DecodeBFLabelOperand,
+							  CONCAT(false, CONCAT(false, CONCAT(true, 11))))(
+						   Inst, Imm, Address, Decoder)))
+			return MCDisassembler_Fail;
+		break;
+	case ARM_t2DLS:
+	case ARM_MVE_DLSTP_8:
+	case ARM_MVE_DLSTP_16:
+	case ARM_MVE_DLSTP_32:
+	case ARM_MVE_DLSTP_64: {
+		unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+		if (Rn == 0xF) {
+			// Enforce all the rest of the instruction bits in LCTP, which
+			// won't have been reliably checked based on LCTP's own tablegen
+			// record, because we came to this decode by a roundabout route.
+			uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
+			if ((Insn & ~SBZMask) != CanonicalLCTP)
+				return MCDisassembler_Fail; // a mandatory bit is wrong: hard
+											// fail
+			if (Insn != CanonicalLCTP)
+				Check(
+					&S,
+					MCDisassembler_SoftFail); // an SBZ bit is wrong: soft fail
+
+			MCInst_setOpcode(Inst, (ARM_MVE_LCTP));
+		} else {
+			MCOperand_CreateReg0(Inst, (ARM_LR));
+			if (!Check(&S, DecoderGPRRegisterClass(
+							   Inst, fieldFromInstruction_4(Insn, 16, 4),
+							   Address, Decoder)))
+				return MCDisassembler_Fail;
+		}
+		break;
+	}
+	}
+	return S;
+}
+
+static DecodeStatus DecodeLongShiftOperand(MCInst *Inst, unsigned Val,
+										   uint64_t Address,
+										   const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	if (Val == 0)
+		Val = 32;
+
+	MCOperand_CreateImm0(Inst, (Val));
+
+	return S;
+}
+
+static DecodeStatus DecodetGPROddRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder)
+{
+	if ((RegNo) + 1 > 11)
+		return MCDisassembler_Fail;
+
+	unsigned Register = GPRDecoderTable[(RegNo) + 1];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodetGPREvenRegisterClass(MCInst *Inst, unsigned RegNo,
+												uint64_t Address,
+												const void *Decoder)
+{
+	if ((RegNo) > 14)
+		return MCDisassembler_Fail;
+
+	unsigned Register = GPRDecoderTable[(RegNo)];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst *Inst,
+															unsigned RegNo,
+															uint64_t Address,
+															const void *Decoder)
+{
+	if (RegNo == 15) {
+		MCOperand_CreateReg0(Inst, (ARM_APSR_NZCV));
+		return MCDisassembler_Success;
+	}
+
+	unsigned Register = GPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+
+	if (RegNo == 13)
+		return MCDisassembler_SoftFail;
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeVSCCLRM(MCInst *Inst, unsigned Insn, uint64_t Address,
+								  const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	MCOperand_CreateImm0(Inst, (ARMCC_AL));
+	MCOperand_CreateReg0(Inst, (0));
+	if (MCInst_getOpcode(Inst) == ARM_VSCCLRMD) {
+		unsigned reglist = (fieldFromInstruction_4(Insn, 1, 7) << 1) |
+						   (fieldFromInstruction_4(Insn, 12, 4) << 8) |
+						   (fieldFromInstruction_4(Insn, 22, 1) << 12);
+		if (!Check(&S,
+				   DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
+			return MCDisassembler_Fail;
+		}
+	} else {
+		unsigned reglist = fieldFromInstruction_4(Insn, 0, 8) |
+						   (fieldFromInstruction_4(Insn, 22, 1) << 8) |
+						   (fieldFromInstruction_4(Insn, 12, 4) << 9);
+		if (!Check(&S,
+				   DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) {
+			return MCDisassembler_Fail;
+		}
+	}
+	MCOperand_CreateReg0(Inst, (ARM_VPR));
+
+	return S;
+}
+
+static DecodeStatus DecodeMQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											uint64_t Address,
+											const void *Decoder)
+{
+	if (RegNo > 7)
+		return MCDisassembler_Fail;
+
+	unsigned Register = QPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static const uint16_t QQPRDecoderTable[] = {ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3,
+											ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6,
+											ARM_Q6_Q7};
+
+static DecodeStatus DecodeMQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											 uint64_t Address,
+											 const void *Decoder)
+{
+	if (RegNo > 6)
+		return MCDisassembler_Fail;
+
+	unsigned Register = QQPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static const uint16_t QQQQPRDecoderTable[] = {ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4,
+											  ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6,
+											  ARM_Q4_Q5_Q6_Q7};
+
+static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst *Inst, unsigned RegNo,
+											   uint64_t Address,
+											   const void *Decoder)
+{
+	if (RegNo > 4)
+		return MCDisassembler_Fail;
+
+	unsigned Register = QQQQPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Register));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeVPTMaskOperand(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	// Parse VPT mask and encode it in the MCInst as an immediate with the same
+	// format as the it_mask.  That is, from the second 'e|t' encode 'e' as 1
+	// and 't' as 0 and finish with a 1.
+	unsigned Imm = 0;
+	// We always start with a 't'.
+	unsigned CurBit = 0;
+	for (int i = 3; i >= 0; --i) {
+		// If the bit we are looking at is not the same as last one, invert the
+		// CurBit, if it is the same leave it as is.
+		CurBit ^= (Val >> i) & 1U;
+
+		// Encode the CurBit at the right place in the immediate.
+		Imm |= (CurBit << i);
+
+		// If we are done, finish the encoding with a 1.
+		if ((Val & ~(~0U << i)) == 0) {
+			Imm |= 1U << i;
+			break;
+		}
+	}
+
+	MCOperand_CreateImm0(Inst, (Imm));
+
+	return S;
+}
+
+static DecodeStatus DecodeVpredROperand(MCInst *Inst, unsigned RegNo,
+										uint64_t Address, const void *Decoder)
+{
+	// The vpred_r operand type includes an MQPR register field derived
+	// from the encoding. But we don't actually want to add an operand
+	// to the MCInst at this stage, because AddThumbPredicate will do it
+	// later, and will infer the register number from the TIED_TO
+	// constraint. So this is a deliberately empty decoder method that
+	// will inhibit the auto-generated disassembly code from adding an
+	// operand at all.
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRestrictedIPredicateOperand(MCInst *Inst,
+													  unsigned Val,
+													  uint64_t Address,
+													  const void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, ((Val & 0x1) == 0 ? ARMCC_EQ : ARMCC_NE));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRestrictedSPredicateOperand(MCInst *Inst,
+													  unsigned Val,
+													  uint64_t Address,
+													  const void *Decoder)
+{
+	unsigned Code;
+	switch (Val & 0x3) {
+	case 0:
+		Code = ARMCC_GE;
+		break;
+	case 1:
+		Code = ARMCC_LT;
+		break;
+	case 2:
+		Code = ARMCC_GT;
+		break;
+	case 3:
+		Code = ARMCC_LE;
+		break;
+	}
+	MCOperand_CreateImm0(Inst, (Code));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRestrictedUPredicateOperand(MCInst *Inst,
+													  unsigned Val,
+													  uint64_t Address,
+													  const void *Decoder)
+{
+	MCOperand_CreateImm0(Inst, ((Val & 0x1) == 0 ? ARMCC_HS : ARMCC_HI));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst *Inst,
+													   unsigned Val,
+													   uint64_t Address,
+													   const void *Decoder)
+{
+	unsigned Code;
+	switch (Val) {
+	default:
+		return MCDisassembler_Fail;
+	case 0:
+		Code = ARMCC_EQ;
+		break;
+	case 1:
+		Code = ARMCC_NE;
+		break;
+	case 4:
+		Code = ARMCC_GE;
+		break;
+	case 5:
+		Code = ARMCC_LT;
+		break;
+	case 6:
+		Code = ARMCC_GT;
+		break;
+	case 7:
+		Code = ARMCC_LE;
+		break;
+	}
+
+	MCOperand_CreateImm0(Inst, (Code));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeVCVTImmOperand(MCInst *Inst, unsigned Val,
+										 uint64_t Address, const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned DecodedVal = 64 - Val;
+
+	switch (MCInst_getOpcode(Inst)) {
+	case ARM_MVE_VCVTf16s16_fix:
+	case ARM_MVE_VCVTs16f16_fix:
+	case ARM_MVE_VCVTf16u16_fix:
+	case ARM_MVE_VCVTu16f16_fix:
+		if (DecodedVal > 16)
+			return MCDisassembler_Fail;
+		break;
+	case ARM_MVE_VCVTf32s32_fix:
+	case ARM_MVE_VCVTs32f32_fix:
+	case ARM_MVE_VCVTf32u32_fix:
+	case ARM_MVE_VCVTu32f32_fix:
+		if (DecodedVal > 32)
+			return MCDisassembler_Fail;
+		break;
+	}
+
+	MCOperand_CreateImm0(Inst, (64 - Val));
+
+	return S;
+}
+
+static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode)
+{
+	switch (Opcode) {
+	case ARM_VSTR_P0_off:
+	case ARM_VSTR_P0_pre:
+	case ARM_VSTR_P0_post:
+	case ARM_VLDR_P0_off:
+	case ARM_VLDR_P0_pre:
+	case ARM_VLDR_P0_post:
+		return ARM_P0;
+	default:
+		return 0;
+	}
+}
+
+#define DEFINE_DecodeVSTRVLDR_SYSREG(Writeback)                                \
+	static DecodeStatus CONCAT(DecodeVSTRVLDR_SYSREG, Writeback)(              \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		switch (MCInst_getOpcode(Inst)) {                                      \
+		case ARM_VSTR_FPSCR_pre:                                               \
+		case ARM_VSTR_FPSCR_NZCVQC_pre:                                        \
+		case ARM_VLDR_FPSCR_pre:                                               \
+		case ARM_VLDR_FPSCR_NZCVQC_pre:                                        \
+		case ARM_VSTR_FPSCR_off:                                               \
+		case ARM_VSTR_FPSCR_NZCVQC_off:                                        \
+		case ARM_VLDR_FPSCR_off:                                               \
+		case ARM_VLDR_FPSCR_NZCVQC_off:                                        \
+		case ARM_VSTR_FPSCR_post:                                              \
+		case ARM_VSTR_FPSCR_NZCVQC_post:                                       \
+		case ARM_VLDR_FPSCR_post:                                              \
+		case ARM_VLDR_FPSCR_NZCVQC_post:                                       \
+                                                                               \
+			if (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasMVEIntegerOps) &&  \
+				!ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP2))         \
+				return MCDisassembler_Fail;                                    \
+		}                                                                      \
+                                                                               \
+		DecodeStatus S = MCDisassembler_Success;                               \
+		unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(MCInst_getOpcode(Inst));  \
+		if (Sysreg)                                                            \
+			MCOperand_CreateReg0(Inst, (Sysreg));                              \
+		unsigned Rn = fieldFromInstruction_4(Val, 16, 4);                      \
+		unsigned addr = fieldFromInstruction_4(Val, 0, 7) |                    \
+						(fieldFromInstruction_4(Val, 23, 1) << 7) | (Rn << 8); \
+                                                                               \
+		if (Writeback) {                                                       \
+			if (!Check(&S, DecodeGPRnopcRegisterClass(Inst, Rn, Address,       \
+													  Decoder)))               \
+				return MCDisassembler_Fail;                                    \
+		}                                                                      \
+		if (!Check(&S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))  \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		MCOperand_CreateImm0(Inst, (ARMCC_AL));                                \
+		MCOperand_CreateReg0(Inst, (0));                                       \
+                                                                               \
+		return S;                                                              \
+	}
+DEFINE_DecodeVSTRVLDR_SYSREG(false) DEFINE_DecodeVSTRVLDR_SYSREG(true)
+
+	static inline DecodeStatus
+	DecodeMVE_MEM_pre(MCInst *Inst, unsigned Val, uint64_t Address,
+					  const void *Decoder, unsigned Rn,
+					  OperandDecoder RnDecoder, OperandDecoder AddrDecoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned Qd = fieldFromInstruction_4(Val, 13, 3);
+	unsigned addr = fieldFromInstruction_4(Val, 0, 7) |
+					(fieldFromInstruction_4(Val, 23, 1) << 7) | (Rn << 8);
+
+	if (!Check(&S, RnDecoder(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, AddrDecoder(Inst, addr, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+#define DEFINE_DecodeMVE_MEM_1_pre(shift)                                      \
+	static DecodeStatus CONCAT(DecodeMVE_MEM_1_pre, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		return DecodeMVE_MEM_pre(                                              \
+			Inst, Val, Address, Decoder, fieldFromInstruction_4(Val, 16, 3),   \
+			DecodetGPRRegisterClass, CONCAT(DecodeTAddrModeImm7, shift));      \
+	}
+DEFINE_DecodeMVE_MEM_1_pre(0) DEFINE_DecodeMVE_MEM_1_pre(1)
+
+#define DEFINE_DecodeMVE_MEM_2_pre(shift)                                      \
+	static DecodeStatus CONCAT(DecodeMVE_MEM_2_pre, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		return DecodeMVE_MEM_pre(                                              \
+			Inst, Val, Address, Decoder, fieldFromInstruction_4(Val, 16, 4),   \
+			DecoderGPRRegisterClass,                                           \
+			CONCAT(DecodeT2AddrModeImm7, CONCAT(shift, 1)));                   \
+	}
+	DEFINE_DecodeMVE_MEM_2_pre(0) DEFINE_DecodeMVE_MEM_2_pre(1)
+		DEFINE_DecodeMVE_MEM_2_pre(2)
+
+#define DEFINE_DecodeMVE_MEM_3_pre(shift)                                      \
+	static DecodeStatus CONCAT(DecodeMVE_MEM_3_pre, shift)(                    \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		return DecodeMVE_MEM_pre(                                              \
+			Inst, Val, Address, Decoder, fieldFromInstruction_4(Val, 17, 3),   \
+			DecodeMQPRRegisterClass, CONCAT(DecodeMveAddrModeQ, shift));       \
+	}
+			DEFINE_DecodeMVE_MEM_3_pre(2) DEFINE_DecodeMVE_MEM_3_pre(3)
+
+#define DEFINE_DecodePowerTwoOperand(MinLog, MaxLog)                           \
+	static DecodeStatus CONCAT(DecodePowerTwoOperand, CONCAT(MinLog, MaxLog))( \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+                                                                               \
+		if (Val < MinLog || Val > MaxLog)                                      \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		MCOperand_CreateImm0(Inst, (1LL << Val));                              \
+		return S;                                                              \
+	}
+				DEFINE_DecodePowerTwoOperand(0, 3)
+
+#define DEFINE_DecodeMVEPairVectorIndexOperand(start)                          \
+	static DecodeStatus CONCAT(DecodeMVEPairVectorIndexOperand, start)(        \
+		MCInst * Inst, unsigned Val, uint64_t Address, const void *Decoder)    \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+                                                                               \
+		MCOperand_CreateImm0(Inst, (start + Val));                             \
+                                                                               \
+		return S;                                                              \
+	}
+					DEFINE_DecodeMVEPairVectorIndexOperand(2)
+						DEFINE_DecodeMVEPairVectorIndexOperand(0)
+
+							static DecodeStatus
+	DecodeMVEVMOVQtoDReg(MCInst *Inst, unsigned Insn, uint64_t Address,
+						 const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
+				   fieldFromInstruction_4(Insn, 13, 3));
+	unsigned index = fieldFromInstruction_4(Insn, 4, 1);
+
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
+						  2)(Inst, index, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
+						  0)(Inst, index, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst *Inst, unsigned Insn,
+										 uint64_t Address, const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	unsigned Rt = fieldFromInstruction_4(Insn, 0, 4);
+	unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4);
+	unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
+				   fieldFromInstruction_4(Insn, 13, 3));
+	unsigned index = fieldFromInstruction_4(Insn, 4, 1);
+
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
+						  2)(Inst, index, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, CONCAT(DecodeMVEPairVectorIndexOperand,
+						  0)(Inst, index, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+static DecodeStatus DecodeMVEOverlappingLongShift(MCInst *Inst, unsigned Insn,
+												  uint64_t Address,
+												  const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+
+	unsigned RdaLo = fieldFromInstruction_4(Insn, 17, 3) << 1;
+	unsigned RdaHi = fieldFromInstruction_4(Insn, 9, 3) << 1;
+	unsigned Rm = fieldFromInstruction_4(Insn, 12, 4);
+
+	if (RdaHi == 14) {
+		// This value of RdaHi (really indicating pc, because RdaHi has to
+		// be an odd-numbered register, so the low bit will be set by the
+		// decode function below) indicates that we must decode as SQRSHR
+		// or UQRSHL, which both have a single Rda register field with all
+		// four bits.
+		unsigned Rda = fieldFromInstruction_4(Insn, 16, 4);
+
+		switch (MCInst_getOpcode(Inst)) {
+		case ARM_MVE_ASRLr:
+		case ARM_MVE_SQRSHRL:
+			MCInst_setOpcode(Inst, (ARM_MVE_SQRSHR));
+			break;
+		case ARM_MVE_LSLLr:
+		case ARM_MVE_UQRSHLL:
+			MCInst_setOpcode(Inst, (ARM_MVE_UQRSHL));
+			break;
+		default:
+			// llvm_unreachable("Unexpected starting opcode!");
+			break;
+		}
+
+		// Rda as output parameter
+		if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
+			return MCDisassembler_Fail;
+
+		// Rda again as input parameter
+		if (!Check(&S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
+			return MCDisassembler_Fail;
+
+		// Rm, the amount to shift by
+		if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+			return MCDisassembler_Fail;
+
+		if (fieldFromInstruction_4(Insn, 6, 3) != 4)
+			return MCDisassembler_SoftFail;
+
+		if (Rda == Rm)
+			return MCDisassembler_SoftFail;
+
+		return S;
+	}
+
+	// Otherwise, we decode as whichever opcode our caller has already
+	// put into Inst. Those all look the same:
+
+	// RdaLo,RdaHi as output parameters
+	if (!Check(&S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	// RdaLo,RdaHi again as input parameters
+	if (!Check(&S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	// Rm, the amount to shift by
+	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	if (MCInst_getOpcode(Inst) == ARM_MVE_SQRSHRL ||
+		MCInst_getOpcode(Inst) == ARM_MVE_UQRSHLL) {
+		unsigned Saturate = fieldFromInstruction_4(Insn, 7, 1);
+		// Saturate, the bit position for saturation
+		MCOperand_CreateImm0(Inst, (Saturate));
+	}
+
+	return S;
+}
+
+static DecodeStatus DecodeMVEVCVTt1fp(MCInst *Inst, unsigned Insn,
+									  uint64_t Address, const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	unsigned Qd = ((fieldFromInstruction_4(Insn, 22, 1) << 3) |
+				   fieldFromInstruction_4(Insn, 13, 3));
+	unsigned Qm = ((fieldFromInstruction_4(Insn, 5, 1) << 3) |
+				   fieldFromInstruction_4(Insn, 1, 3));
+	unsigned imm6 = fieldFromInstruction_4(Insn, 16, 6);
+
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
+		return MCDisassembler_Fail;
+	if (!Check(&S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
+		return MCDisassembler_Fail;
+
+	return S;
+}
+
+#define DEFINE_DecodeMVEVCMP(scalar, predicate_decoder)                        \
+	static DecodeStatus CONCAT(DecodeMVEVCMP,                                  \
+							   CONCAT(scalar, predicate_decoder))(             \
+		MCInst * Inst, unsigned Insn, uint64_t Address, const void *Decoder)   \
+	{                                                                          \
+		DecodeStatus S = MCDisassembler_Success;                               \
+		MCOperand_CreateReg0(Inst, (ARM_VPR));                                 \
+		unsigned Qn = fieldFromInstruction_4(Insn, 17, 3);                     \
+		if (!Check(&S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))   \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		unsigned fc;                                                           \
+                                                                               \
+		if (scalar) {                                                          \
+			fc = fieldFromInstruction_4(Insn, 12, 1) << 2 |                    \
+				 fieldFromInstruction_4(Insn, 7, 1) |                          \
+				 fieldFromInstruction_4(Insn, 5, 1) << 1;                      \
+			unsigned Rm = fieldFromInstruction_4(Insn, 0, 4);                  \
+			if (!Check(&S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address,     \
+														Decoder)))             \
+				return MCDisassembler_Fail;                                    \
+		} else {                                                               \
+			fc = fieldFromInstruction_4(Insn, 12, 1) << 2 |                    \
+				 fieldFromInstruction_4(Insn, 7, 1) |                          \
+				 fieldFromInstruction_4(Insn, 0, 1) << 1;                      \
+			unsigned Qm = fieldFromInstruction_4(Insn, 5, 1) << 4 |            \
+						  fieldFromInstruction_4(Insn, 1, 3);                  \
+			if (!Check(&S,                                                     \
+					   DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))   \
+				return MCDisassembler_Fail;                                    \
+		}                                                                      \
+                                                                               \
+		if (!Check(&S, predicate_decoder(Inst, fc, Address, Decoder)))         \
+			return MCDisassembler_Fail;                                        \
+                                                                               \
+		MCOperand_CreateImm0(Inst, (ARMVCC_None));                             \
+		MCOperand_CreateReg0(Inst, (0));                                       \
+		MCOperand_CreateImm0(Inst, (0));                                       \
+                                                                               \
+		return S;                                                              \
+	}
+DEFINE_DecodeMVEVCMP(false, DecodeRestrictedIPredicateOperand)
+	DEFINE_DecodeMVEVCMP(false, DecodeRestrictedUPredicateOperand)
+		DEFINE_DecodeMVEVCMP(false, DecodeRestrictedSPredicateOperand)
+			DEFINE_DecodeMVEVCMP(true, DecodeRestrictedIPredicateOperand)
+				DEFINE_DecodeMVEVCMP(true, DecodeRestrictedUPredicateOperand)
+					DEFINE_DecodeMVEVCMP(true,
+										 DecodeRestrictedSPredicateOperand)
+						DEFINE_DecodeMVEVCMP(false,
+											 DecodeRestrictedFPPredicateOperand)
+							DEFINE_DecodeMVEVCMP(
+								true, DecodeRestrictedFPPredicateOperand)
+
+								static DecodeStatus
+	DecodeMveVCTP(MCInst *Inst, unsigned Insn, uint64_t Address,
+				  const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	MCOperand_CreateReg0(Inst, (ARM_VPR));
+	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	if (!Check(&S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+		return MCDisassembler_Fail;
+	return S;
+}
+
+static DecodeStatus DecodeMVEVPNOT(MCInst *Inst, unsigned Insn,
+								   uint64_t Address, const void *Decoder)
+{
+	DecodeStatus S = MCDisassembler_Success;
+	MCOperand_CreateReg0(Inst, (ARM_VPR));
+	MCOperand_CreateReg0(Inst, (ARM_VPR));
+	return S;
+}
+
+static DecodeStatus DecodeT2AddSubSPImm(MCInst *Inst, unsigned Insn,
+										uint64_t Address, const void *Decoder)
+{
+	const unsigned Rd = fieldFromInstruction_4(Insn, 8, 4);
+	const unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	const unsigned Imm12 = fieldFromInstruction_4(Insn, 26, 1) << 11 |
+						   fieldFromInstruction_4(Insn, 12, 3) << 8 |
+						   fieldFromInstruction_4(Insn, 0, 8);
+	const unsigned TypeT3 = fieldFromInstruction_4(Insn, 25, 1);
+	unsigned sign1 = fieldFromInstruction_4(Insn, 21, 1);
+	unsigned sign2 = fieldFromInstruction_4(Insn, 23, 1);
+	unsigned S = fieldFromInstruction_4(Insn, 20, 1);
+	if (sign1 != sign2)
+		return MCDisassembler_Fail;
+
+	// T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm)
+	DecodeStatus DS = MCDisassembler_Success;
+	if ((!Check(&DS,
+				DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
+		(!Check(&DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
+		return MCDisassembler_Fail;
+	if (TypeT3) {
+		MCInst_setOpcode(Inst, (sign1 ? ARM_t2SUBspImm12 : ARM_t2ADDspImm12));
+		MCOperand_CreateImm0(Inst, (Imm12)); // zext imm12
+	} else {
+		MCInst_setOpcode(Inst, (sign1 ? ARM_t2SUBspImm : ARM_t2ADDspImm));
+		if (!Check(&DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
+			return MCDisassembler_Fail;
+		if (!Check(&DS,
+				   DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
+			return MCDisassembler_Fail;
+	}
+
+	return DS;
+}
+
+DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+						MCInst *instr, uint16_t *size, uint64_t address,
+						void *info) {
+	return getInstruction(handle, code, code_len, instr, size, address,
+								 info);
+}
diff --git a/arch/ARM/ARMDisassembler.h b/arch/ARM/ARMDisassembler.h
deleted file mode 100644
index 35e75c9c9..000000000
--- a/arch/ARM/ARMDisassembler.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_ARMDISASSEMBLER_H
-#define CS_ARMDISASSEMBLER_H
-
-#include "capstone/capstone.h"
-#include "../../MCRegisterInfo.h"
-
-void ARM_init(MCRegisterInfo *MRI);
-
-bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
-
-bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
-
-bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
-
-#endif
diff --git a/arch/ARM/ARMDisassemblerExtension.c b/arch/ARM/ARMDisassemblerExtension.c
new file mode 100644
index 000000000..6e7d8245c
--- /dev/null
+++ b/arch/ARM/ARMDisassemblerExtension.c
@@ -0,0 +1,227 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#include "ARMDisassemblerExtension.h"
+#include "ARMBaseInfo.h"
+
+bool ITBlock_push_back(ARM_ITBlock *it, char v)
+{
+	if (it->size >= sizeof(it->ITStates)) {
+		// TODO: consider warning user.
+		it->size = 0;
+	}
+	it->ITStates[it->size] = v;
+	it->size++;
+
+	return true;
+}
+
+// Returns true if the current instruction is in an IT block
+bool ITBlock_instrInITBlock(ARM_ITBlock *it)
+{
+	return (it->size > 0);
+}
+
+// Returns true if current instruction is the last instruction in an IT block
+bool ITBlock_instrLastInITBlock(ARM_ITBlock *it) { return (it->size == 1); }
+
+// Returns the condition code for instruction in IT block
+unsigned ITBlock_getITCC(ARM_ITBlock *it)
+{
+	unsigned CC = ARMCC_AL;
+
+	if (ITBlock_instrInITBlock(it))
+		CC = it->ITStates[it->size - 1];
+
+	return CC;
+}
+
+// Advances the IT block state to the next T or E
+void ITBlock_advanceITState(ARM_ITBlock *it)
+{
+	it->size--;
+}
+
+// Called when decoding an IT instruction. Sets the IT state for the following
+// instructions that for the IT block. Firstcond and Mask correspond to the
+// fields in the IT instruction encoding.
+void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask)
+{
+	// (3 - the number of trailing zeros) is the number of then / else.
+	unsigned NumTZ = CountTrailingZeros_8(Mask);
+	unsigned char CCBits = (unsigned char)(Firstcond & 0xf);
+	assert(NumTZ <= 3 && "Invalid IT mask!");
+	// push condition codes onto the stack the correct order for the pops
+	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
+		unsigned Else = (Mask >> Pos) & 1;
+		ITBlock_push_back(it, CCBits ^ Else);
+	}
+	ITBlock_push_back(it, CCBits);
+}
+
+bool VPTBlock_push_back(ARM_VPTBlock *it, char v)
+{
+	if (it->size >= sizeof(it->VPTStates)) {
+		// TODO: consider warning user.
+		it->size = 0;
+	}
+	it->VPTStates[it->size] = v;
+	it->size++;
+
+	return true;
+}
+
+bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT) { return VPT->size > 0; }
+
+unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT)
+{
+	unsigned Pred = ARMVCC_None;
+	if (VPTBlock_instrInVPTBlock(VPT))
+		Pred = VPT->VPTStates[VPT->size - 1];
+	return Pred;
+}
+
+void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT) { VPT->size--; }
+
+void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask)
+{
+	// (3 - the number of trailing zeros) is the number of then / else.
+	unsigned NumTZ = CountTrailingZeros_8(Mask);
+	assert(NumTZ <= 3 && "Invalid VPT mask!");
+	// push predicates onto the stack the correct order for the pops
+	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
+		bool T = ((Mask >> Pos) & 1) == 0;
+		if (T)
+			VPTBlock_push_back(VPT, ARMVCC_Then);
+		else
+			VPTBlock_push_back(VPT, ARMVCC_Else);
+	}
+	VPTBlock_push_back(VPT, ARMVCC_Then);
+}
+
+/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
+
+bool Check(DecodeStatus *Out, DecodeStatus In)
+{
+	switch (In) {
+	case MCDisassembler_Success:
+		// Out stays the same.
+		return true;
+	case MCDisassembler_SoftFail:
+		*Out = In;
+		return true;
+	case MCDisassembler_Fail:
+		*Out = In;
+		return false;
+	default: // never reached
+		return false;
+	}
+}
+
+// Imported from ARMBaseInstrInfo.h
+//
+/// isValidCoprocessorNumber - decide whether an explicit coprocessor
+/// number is legal in generic instructions like CDP. The answer can
+/// vary with the subtarget.
+bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num)
+{
+	// In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
+	// coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
+	// useful for code which is shared with older architectures which do not
+	// know the new VFP/NEON mnemonics.
+
+	// Armv8-A disallows everything *other* than 111x (CP14 and CP15).
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (Num & 0xE) != 0xE)
+		return false;
+
+	// Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
+	// which clash with MVE.
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) &&
+		((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
+		return false;
+
+	return true;
+}
+
+// Imported from ARMMCTargetDesc.h
+bool ARM_isVpred(arm_op_type op)
+{
+	return op == ARM_OP_VPRED_R || op == ARM_OP_VPRED_N;
+}
+
+// Imported from ARMBaseInstrInfo.h
+//
+// This table shows the VPT instruction variants, i.e. the different
+// mask field encodings, see also B5.6. Predication/conditional execution in
+// the ArmARM.
+bool isVPTOpcode(int Opc)
+{
+	return Opc == ARM_MVE_VPTv16i8 || Opc == ARM_MVE_VPTv16u8 ||
+		   Opc == ARM_MVE_VPTv16s8 || Opc == ARM_MVE_VPTv8i16 ||
+		   Opc == ARM_MVE_VPTv8u16 || Opc == ARM_MVE_VPTv8s16 ||
+		   Opc == ARM_MVE_VPTv4i32 || Opc == ARM_MVE_VPTv4u32 ||
+		   Opc == ARM_MVE_VPTv4s32 || Opc == ARM_MVE_VPTv4f32 ||
+		   Opc == ARM_MVE_VPTv8f16 || Opc == ARM_MVE_VPTv16i8r ||
+		   Opc == ARM_MVE_VPTv16u8r || Opc == ARM_MVE_VPTv16s8r ||
+		   Opc == ARM_MVE_VPTv8i16r || Opc == ARM_MVE_VPTv8u16r ||
+		   Opc == ARM_MVE_VPTv8s16r || Opc == ARM_MVE_VPTv4i32r ||
+		   Opc == ARM_MVE_VPTv4u32r || Opc == ARM_MVE_VPTv4s32r ||
+		   Opc == ARM_MVE_VPTv4f32r || Opc == ARM_MVE_VPTv8f16r ||
+		   Opc == ARM_MVE_VPST;
+}
+
+// Imported from ARMMCTargetDesc.cpp
+bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI)
+{
+	// Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
+	// to rely on feature bits.
+	if (Coproc >= 8)
+		return false;
+
+	return ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCoprocCDE0 + Coproc);
+}
+
+// Hacky: enable all features for disassembler
+bool ARM_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+
+	if (feature == ARM_ModeThumb) {
+		if (mode & CS_MODE_THUMB)
+			return true;
+		return false;
+	}
+
+	if (feature == ARM_FeatureDFB)
+		return false;
+
+	if (feature == ARM_FeatureRAS)
+		return false;
+
+	if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0)
+		return false;
+
+	if ((feature == ARM_HasMVEIntegerOps || feature == ARM_HasMVEFloatOps ||
+		 feature == ARM_FeatureMVEVectorCostFactor1 ||
+		 feature == ARM_FeatureMVEVectorCostFactor2 ||
+		 feature == ARM_FeatureMVEVectorCostFactor4) &&
+		(mode & CS_MODE_MCLASS) == 0)
+		return false;
+
+	if ((feature == ARM_HasV8Ops || feature == ARM_HasV8_1MMainlineOps ||
+		 feature == ARM_HasV8_1aOps || feature == ARM_HasV8_2aOps ||
+		 feature == ARM_HasV8_3aOps || feature == ARM_HasV8_4aOps ||
+		 feature == ARM_HasV8_5aOps || feature == ARM_HasV8_6aOps ||
+		 feature == ARM_HasV8_7aOps || feature == ARM_HasV8_8aOps ||
+		 feature == ARM_HasV8_9aOps) &&
+		(mode & CS_MODE_V8) == 0)
+		return false;
+
+	if (feature >= ARM_FeatureCoprocCDE0 && feature <= ARM_FeatureCoprocCDE7)
+		// We currently have no way to detect CDE (Custom-Datapath-Extension)
+		// coprocessors.
+		return false;
+
+	// we support everything
+	return true;
+}
diff --git a/arch/ARM/ARMDisassemblerExtension.h b/arch/ARM/ARMDisassemblerExtension.h
new file mode 100644
index 000000000..6d1be4636
--- /dev/null
+++ b/arch/ARM/ARMDisassemblerExtension.h
@@ -0,0 +1,51 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_ARM_DISASSEMBLER_EXTENSION_H
+#define CS_ARM_DISASSEMBLER_EXTENSION_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../cs_priv.h"
+#include "ARMAddressingModes.h"
+#include "capstone/capstone.h"
+
+unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset);
+
+bool ITBlock_push_back(ARM_ITBlock *it, char v);
+
+bool ITBlock_instrInITBlock(ARM_ITBlock *it);
+
+bool ITBlock_instrLastInITBlock(ARM_ITBlock *it);
+
+unsigned ITBlock_getITCC(ARM_ITBlock *it);
+
+void ITBlock_advanceITState(ARM_ITBlock *it);
+
+void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask);
+
+bool Check(DecodeStatus *Out, DecodeStatus In);
+
+bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num);
+
+bool ARM_isVpred(arm_op_type op);
+
+bool isVPTOpcode(int Opc);
+
+bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI);
+
+bool VPTBlock_push_back(ARM_VPTBlock *it, char v);
+
+bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT);
+
+unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT);
+
+void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT);
+
+void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask);
+
+bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif // CS_ARM_DISASSEMBLER_EXTENSION_H
diff --git a/arch/ARM/ARMFeatureEnum.inc b/arch/ARM/ARMFeatureEnum.inc
new file mode 100644
index 000000000..c74656626
--- /dev/null
+++ b/arch/ARM/ARMFeatureEnum.inc
@@ -0,0 +1,61 @@
+  ARM_FEATURE_IsThumb = 128,
+  ARM_FEATURE_IsARM,
+  ARM_FEATURE_UseNegativeImmediates,
+  ARM_FEATURE_IsThumb2,
+  ARM_FEATURE_HasV8,
+  ARM_FEATURE_HasAES,
+  ARM_FEATURE_HasV8_1MMainline,
+  ARM_FEATURE_HasMVEInt,
+  ARM_FEATURE_HasV7,
+  ARM_FEATURE_IsMClass,
+  ARM_FEATURE_HasPACBTI,
+  ARM_FEATURE_HasV8MBaseline,
+  ARM_FEATURE_HasLOB,
+  ARM_FEATURE_HasV6T2,
+  ARM_FEATURE_HasV5T,
+  ARM_FEATURE_IsNotMClass,
+  ARM_FEATURE_Has8MSecExt,
+  ARM_FEATURE_HasV4T,
+  ARM_FEATURE_PreV8,
+  ARM_FEATURE_HasCLRBHB,
+  ARM_FEATURE_HasV6K,
+  ARM_FEATURE_HasV7Clrex,
+  ARM_FEATURE_HasCRC,
+  ARM_FEATURE_HasCDE,
+  ARM_FEATURE_HasDFB,
+  ARM_FEATURE_HasDB,
+  ARM_FEATURE_HasVirtualization,
+  ARM_FEATURE_HasRAS,
+  ARM_FEATURE_HasVFP2,
+  ARM_FEATURE_HasDPVFP,
+  ARM_FEATURE_HasVFP3,
+  ARM_FEATURE_HasFPRegs,
+  ARM_FEATURE_HasV6M,
+  ARM_FEATURE_HasV6,
+  ARM_FEATURE_HasAcquireRelease,
+  ARM_FEATURE_HasV5TE,
+  ARM_FEATURE_HasDSP,
+  ARM_FEATURE_HasMP,
+  ARM_FEATURE_HasSB,
+  ARM_FEATURE_HasDivideInThumb,
+  ARM_FEATURE_HasDivideInARM,
+  ARM_FEATURE_HasV8_1a,
+  ARM_FEATURE_HasSHA2,
+  ARM_FEATURE_HasTrustZone,
+  ARM_FEATURE_UseNaClTrap,
+  ARM_FEATURE_HasV8_4a,
+  ARM_FEATURE_HasNEON,
+  ARM_FEATURE_HasFullFP16,
+  ARM_FEATURE_HasMVEFloat,
+  ARM_FEATURE_HasV8_3a,
+  ARM_FEATURE_HasFP16,
+  ARM_FEATURE_HasBF16,
+  ARM_FEATURE_HasFPARMv8,
+  ARM_FEATURE_HasVFP4,
+  ARM_FEATURE_HasFP16FML,
+  ARM_FEATURE_HasFPRegs16,
+  ARM_FEATURE_HasV8MMainline,
+  ARM_FEATURE_HasFPRegs64,
+  ARM_FEATURE_HasFPRegsV8_1M,
+  ARM_FEATURE_HasDotProd,
+  ARM_FEATURE_HasMatMulInt8,
diff --git a/arch/ARM/ARMGenAsmWriter.inc b/arch/ARM/ARMGenAsmWriter.inc
index 78ea52ff4..16788e33d 100644
--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
@@ -1,530 +1,756 @@
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
-|*                                                                            *|
-|* Assembly Writer Source Fragment                                            *|
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
-/// printInstruction - This method is automatically generated by tablegen
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#include <capstone/platform.h>
+#include <assert.h>
+
+/// getMnemonic - This method is automatically generated by tablegen
 /// from the instruction set description.
-static void printInstruction(MCInst *MI, SStream *O)
-{
+static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
 #ifndef CAPSTONE_DIET
   static const char AsmStrs[] = {
-  /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0,
-  /* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0,
-  /* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0,
-  /* 38 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', '.', '3', '2', 9, 0,
-  /* 52 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', '.', '3', '2', 9, 0,
-  /* 65 */ 's', 'h', 'a', '1', 'c', '.', '3', '2', 9, 0,
-  /* 75 */ 's', 'h', 'a', '1', 'h', '.', '3', '2', 9, 0,
-  /* 85 */ 's', 'h', 'a', '2', '5', '6', 'h', '.', '3', '2', 9, 0,
-  /* 97 */ 's', 'h', 'a', '1', 'm', '.', '3', '2', 9, 0,
-  /* 107 */ 's', 'h', 'a', '1', 'p', '.', '3', '2', 9, 0,
-  /* 117 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 132 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 147 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 162 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 177 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 192 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 207 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 222 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '3', '2', 9, 0,
-  /* 237 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '3', '2', 9, 0,
-  /* 248 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '3', '2', 9, 0,
-  /* 260 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '3', '2', 9, 0,
-  /* 271 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '3', '2', 9, 0,
-  /* 283 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '3', '2', 9, 0,
-  /* 295 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '3', '2', 9, 0,
-  /* 307 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '3', '2', 9, 0,
-  /* 319 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '3', '2', 9, 0,
-  /* 331 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '3', '2', 9, 0,
-  /* 343 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '3', '2', 9, 0,
-  /* 355 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '3', '2', 9, 0,
-  /* 367 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '3', '2', 9, 0,
-  /* 379 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '3', '2', 9, 0,
-  /* 391 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '3', '2', 9, 0,
-  /* 403 */ 'l', 'd', 'c', '2', 9, 0,
-  /* 409 */ 'm', 'r', 'c', '2', 9, 0,
-  /* 415 */ 'm', 'r', 'r', 'c', '2', 9, 0,
-  /* 422 */ 's', 't', 'c', '2', 9, 0,
-  /* 428 */ 'c', 'd', 'p', '2', 9, 0,
-  /* 434 */ 'm', 'c', 'r', '2', 9, 0,
-  /* 440 */ 'm', 'c', 'r', 'r', '2', 9, 0,
-  /* 447 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 462 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 477 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 492 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 507 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 522 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 537 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 552 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '6', '4', 9, 0,
-  /* 567 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '6', '4', 9, 0,
-  /* 579 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '6', '4', 9, 0,
-  /* 591 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '6', '4', 9, 0,
-  /* 603 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '6', '4', 9, 0,
-  /* 615 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '6', '4', 9, 0,
-  /* 627 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '6', '4', 9, 0,
-  /* 639 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '6', '4', 9, 0,
-  /* 651 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '6', '4', 9, 0,
-  /* 663 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '6', '4', 9, 0,
-  /* 675 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '6', '4', 9, 0,
-  /* 687 */ 'v', 'm', 'u', 'l', 'l', '.', 'p', '6', '4', 9, 0,
-  /* 698 */ 'v', 'c', 'v', 't', 'a', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 713 */ 'v', 'c', 'v', 't', 'm', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 728 */ 'v', 'c', 'v', 't', 'n', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 743 */ 'v', 'c', 'v', 't', 'p', '.', 's', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 758 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 773 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 788 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 803 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '3', '2', '.', 'f', '1', '6', 9, 0,
-  /* 818 */ 'v', 'c', 'v', 't', 'a', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 833 */ 'v', 'c', 'v', 't', 'm', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 848 */ 'v', 'c', 'v', 't', 'n', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 863 */ 'v', 'c', 'v', 't', 'p', '.', 's', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 878 */ 'v', 'c', 'v', 't', 'a', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 893 */ 'v', 'c', 'v', 't', 'm', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 908 */ 'v', 'c', 'v', 't', 'n', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 923 */ 'v', 'c', 'v', 't', 'p', '.', 'u', '1', '6', '.', 'f', '1', '6', 9, 0,
-  /* 938 */ 'v', 'c', 'm', 'l', 'a', '.', 'f', '1', '6', 9, 0,
-  /* 949 */ 'v', 'r', 'i', 'n', 't', 'a', '.', 'f', '1', '6', 9, 0,
-  /* 961 */ 'v', 'c', 'a', 'd', 'd', '.', 'f', '1', '6', 9, 0,
-  /* 972 */ 'v', 's', 'e', 'l', 'g', 'e', '.', 'f', '1', '6', 9, 0,
-  /* 984 */ 'v', 'm', 'i', 'n', 'n', 'm', '.', 'f', '1', '6', 9, 0,
-  /* 996 */ 'v', 'm', 'a', 'x', 'n', 'm', '.', 'f', '1', '6', 9, 0,
-  /* 1008 */ 'v', 'r', 'i', 'n', 't', 'm', '.', 'f', '1', '6', 9, 0,
-  /* 1020 */ 'v', 'r', 'i', 'n', 't', 'n', '.', 'f', '1', '6', 9, 0,
-  /* 1032 */ 'v', 'r', 'i', 'n', 't', 'p', '.', 'f', '1', '6', 9, 0,
-  /* 1044 */ 'v', 's', 'e', 'l', 'e', 'q', '.', 'f', '1', '6', 9, 0,
-  /* 1056 */ 'v', 'i', 'n', 's', '.', 'f', '1', '6', 9, 0,
-  /* 1066 */ 'v', 's', 'e', 'l', 'v', 's', '.', 'f', '1', '6', 9, 0,
-  /* 1078 */ 'v', 's', 'e', 'l', 'g', 't', '.', 'f', '1', '6', 9, 0,
-  /* 1090 */ 'v', 'r', 'i', 'n', 't', 'x', '.', 'f', '1', '6', 9, 0,
-  /* 1102 */ 'v', 'm', 'o', 'v', 'x', '.', 'f', '1', '6', 9, 0,
-  /* 1113 */ 'v', 'r', 'i', 'n', 't', 'z', '.', 'f', '1', '6', 9, 0,
-  /* 1125 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '8', 9, 0,
-  /* 1135 */ 'a', 'e', 's', 'm', 'c', '.', '8', 9, 0,
-  /* 1144 */ 'a', 'e', 's', 'd', '.', '8', 9, 0,
-  /* 1152 */ 'a', 'e', 's', 'e', '.', '8', 9, 0,
-  /* 1160 */ 'v', 's', 'd', 'o', 't', '.', 's', '8', 9, 0,
-  /* 1170 */ 'v', 'u', 'd', 'o', 't', '.', 'u', '8', 9, 0,
-  /* 1180 */ 'r', 'f', 'e', 'd', 'a', 9, 0,
-  /* 1187 */ 'r', 'f', 'e', 'i', 'a', 9, 0,
-  /* 1194 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0,
-  /* 1202 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0,
-  /* 1211 */ 'r', 'f', 'e', 'd', 'b', 9, 0,
-  /* 1218 */ 'r', 'f', 'e', 'i', 'b', 9, 0,
-  /* 1225 */ 'd', 'm', 'b', 9, 0,
-  /* 1230 */ 'd', 's', 'b', 9, 0,
-  /* 1235 */ 'i', 's', 'b', 9, 0,
-  /* 1240 */ 't', 's', 'b', 9, 0,
-  /* 1245 */ 'h', 'v', 'c', 9, 0,
-  /* 1250 */ 'p', 'l', 'd', 9, 0,
-  /* 1255 */ 's', 'e', 't', 'e', 'n', 'd', 9, 0,
-  /* 1263 */ 'u', 'd', 'f', 9, 0,
-  /* 1268 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0,
-  /* 1276 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0,
-  /* 1285 */ 'p', 'l', 'i', 9, 0,
-  /* 1290 */ 'l', 'd', 'c', '2', 'l', 9, 0,
-  /* 1297 */ 's', 't', 'c', '2', 'l', 9, 0,
-  /* 1304 */ 'b', 'l', 9, 0,
-  /* 1308 */ 's', 'e', 't', 'p', 'a', 'n', 9, 0,
-  /* 1316 */ 'c', 'p', 's', 9, 0,
-  /* 1321 */ 'm', 'o', 'v', 's', 9, 0,
-  /* 1327 */ 'h', 'l', 't', 9, 0,
-  /* 1332 */ 'b', 'k', 'p', 't', 9, 0,
-  /* 1338 */ 'h', 'v', 'c', '.', 'w', 9, 0,
-  /* 1345 */ 'u', 'd', 'f', '.', 'w', 9, 0,
-  /* 1352 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0,
-  /* 1360 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0,
-  /* 1369 */ 'p', 'l', 'd', 'w', 9, 0,
-  /* 1375 */ 'b', 'x', 9, 0,
-  /* 1379 */ 'b', 'l', 'x', 9, 0,
-  /* 1384 */ 'c', 'b', 'z', 9, 0,
-  /* 1389 */ 'c', 'b', 'n', 'z', 9, 0,
-  /* 1395 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', '!', ',', 32, 0,
-  /* 1407 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', '!', ',', 32, 0,
-  /* 1419 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', '!', ',', 32, 0,
-  /* 1431 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', '!', ',', 32, 0,
-  /* 1443 */ 's', 'r', 's', 'd', 'a', 9, 's', 'p', ',', 32, 0,
-  /* 1454 */ 's', 'r', 's', 'i', 'a', 9, 's', 'p', ',', 32, 0,
-  /* 1465 */ 's', 'r', 's', 'd', 'b', 9, 's', 'p', ',', 32, 0,
-  /* 1476 */ 's', 'r', 's', 'i', 'b', 9, 's', 'p', ',', 32, 0,
-  /* 1487 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0,
-  /* 1518 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
-  /* 1542 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0,
-  /* 1567 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0,
-  /* 1590 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0,
-  /* 1613 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0,
-  /* 1635 */ '_', '_', 'b', 'r', 'k', 'd', 'i', 'v', '0', 0,
-  /* 1645 */ 'v', 'l', 'd', '1', 0,
-  /* 1650 */ 'd', 'c', 'p', 's', '1', 0,
-  /* 1656 */ 'v', 's', 't', '1', 0,
-  /* 1661 */ 'v', 'r', 'e', 'v', '3', '2', 0,
-  /* 1668 */ 'l', 'd', 'c', '2', 0,
-  /* 1673 */ 'm', 'r', 'c', '2', 0,
-  /* 1678 */ 'm', 'r', 'r', 'c', '2', 0,
-  /* 1684 */ 's', 't', 'c', '2', 0,
-  /* 1689 */ 'v', 'l', 'd', '2', 0,
-  /* 1694 */ 'c', 'd', 'p', '2', 0,
-  /* 1699 */ 'm', 'c', 'r', '2', 0,
-  /* 1704 */ 'm', 'c', 'r', 'r', '2', 0,
-  /* 1710 */ 'd', 'c', 'p', 's', '2', 0,
-  /* 1716 */ 'v', 's', 't', '2', 0,
-  /* 1721 */ 'v', 'l', 'd', '3', 0,
-  /* 1726 */ 'd', 'c', 'p', 's', '3', 0,
-  /* 1732 */ 'v', 's', 't', '3', 0,
-  /* 1737 */ 'v', 'r', 'e', 'v', '6', '4', 0,
-  /* 1744 */ 'v', 'l', 'd', '4', 0,
-  /* 1749 */ 'v', 's', 't', '4', 0,
-  /* 1754 */ 's', 'x', 't', 'a', 'b', '1', '6', 0,
-  /* 1762 */ 'u', 'x', 't', 'a', 'b', '1', '6', 0,
-  /* 1770 */ 's', 'x', 't', 'b', '1', '6', 0,
-  /* 1777 */ 'u', 'x', 't', 'b', '1', '6', 0,
-  /* 1784 */ 's', 'h', 's', 'u', 'b', '1', '6', 0,
-  /* 1792 */ 'u', 'h', 's', 'u', 'b', '1', '6', 0,
-  /* 1800 */ 'u', 'q', 's', 'u', 'b', '1', '6', 0,
-  /* 1808 */ 's', 's', 'u', 'b', '1', '6', 0,
-  /* 1815 */ 'u', 's', 'u', 'b', '1', '6', 0,
-  /* 1822 */ 's', 'h', 'a', 'd', 'd', '1', '6', 0,
-  /* 1830 */ 'u', 'h', 'a', 'd', 'd', '1', '6', 0,
-  /* 1838 */ 'u', 'q', 'a', 'd', 'd', '1', '6', 0,
-  /* 1846 */ 's', 'a', 'd', 'd', '1', '6', 0,
-  /* 1853 */ 'u', 'a', 'd', 'd', '1', '6', 0,
-  /* 1860 */ 's', 's', 'a', 't', '1', '6', 0,
-  /* 1867 */ 'u', 's', 'a', 't', '1', '6', 0,
-  /* 1874 */ 'v', 'r', 'e', 'v', '1', '6', 0,
-  /* 1881 */ 'u', 's', 'a', 'd', 'a', '8', 0,
-  /* 1888 */ 's', 'h', 's', 'u', 'b', '8', 0,
-  /* 1895 */ 'u', 'h', 's', 'u', 'b', '8', 0,
-  /* 1902 */ 'u', 'q', 's', 'u', 'b', '8', 0,
-  /* 1909 */ 's', 's', 'u', 'b', '8', 0,
-  /* 1915 */ 'u', 's', 'u', 'b', '8', 0,
-  /* 1921 */ 'u', 's', 'a', 'd', '8', 0,
-  /* 1927 */ 's', 'h', 'a', 'd', 'd', '8', 0,
-  /* 1934 */ 'u', 'h', 'a', 'd', 'd', '8', 0,
-  /* 1941 */ 'u', 'q', 'a', 'd', 'd', '8', 0,
-  /* 1948 */ 's', 'a', 'd', 'd', '8', 0,
-  /* 1954 */ 'u', 'a', 'd', 'd', '8', 0,
-  /* 1960 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
-  /* 1973 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
-  /* 1980 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
-  /* 1990 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0,
-  /* 2000 */ '@', 32, 'C', 'O', 'M', 'P', 'I', 'L', 'E', 'R', 32, 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0,
-  /* 2019 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
-  /* 2034 */ 'v', 'a', 'b', 'a', 0,
-  /* 2039 */ 'l', 'd', 'a', 0,
-  /* 2043 */ 'l', 'd', 'm', 'd', 'a', 0,
-  /* 2049 */ 's', 't', 'm', 'd', 'a', 0,
-  /* 2055 */ 'r', 'f', 'e', 'i', 'a', 0,
-  /* 2061 */ 'v', 'l', 'd', 'm', 'i', 'a', 0,
-  /* 2068 */ 'v', 's', 't', 'm', 'i', 'a', 0,
-  /* 2075 */ 's', 'r', 's', 'i', 'a', 0,
-  /* 2081 */ 's', 'm', 'm', 'l', 'a', 0,
-  /* 2087 */ 'v', 'n', 'm', 'l', 'a', 0,
-  /* 2093 */ 'v', 'm', 'l', 'a', 0,
-  /* 2098 */ 'v', 'f', 'm', 'a', 0,
-  /* 2103 */ 'v', 'f', 'n', 'm', 'a', 0,
-  /* 2109 */ 'v', 'r', 's', 'r', 'a', 0,
-  /* 2115 */ 'v', 's', 'r', 'a', 0,
-  /* 2120 */ 't', 't', 'a', 0,
-  /* 2124 */ 'l', 'd', 'a', 'b', 0,
-  /* 2129 */ 's', 'x', 't', 'a', 'b', 0,
-  /* 2135 */ 'u', 'x', 't', 'a', 'b', 0,
-  /* 2141 */ 's', 'm', 'l', 'a', 'b', 'b', 0,
-  /* 2148 */ 's', 'm', 'l', 'a', 'l', 'b', 'b', 0,
-  /* 2156 */ 's', 'm', 'u', 'l', 'b', 'b', 0,
-  /* 2163 */ 't', 'b', 'b', 0,
-  /* 2167 */ 'r', 'f', 'e', 'd', 'b', 0,
-  /* 2173 */ 'v', 'l', 'd', 'm', 'd', 'b', 0,
-  /* 2180 */ 'v', 's', 't', 'm', 'd', 'b', 0,
-  /* 2187 */ 's', 'r', 's', 'd', 'b', 0,
-  /* 2193 */ 'l', 'd', 'm', 'i', 'b', 0,
-  /* 2199 */ 's', 't', 'm', 'i', 'b', 0,
-  /* 2205 */ 's', 't', 'l', 'b', 0,
-  /* 2210 */ 'd', 'm', 'b', 0,
-  /* 2214 */ 's', 'w', 'p', 'b', 0,
-  /* 2219 */ 'l', 'd', 'r', 'b', 0,
-  /* 2224 */ 's', 't', 'r', 'b', 0,
-  /* 2229 */ 'd', 's', 'b', 0,
-  /* 2233 */ 'i', 's', 'b', 0,
-  /* 2237 */ 'l', 'd', 'r', 's', 'b', 0,
-  /* 2243 */ 't', 's', 'b', 0,
-  /* 2247 */ 's', 'm', 'l', 'a', 't', 'b', 0,
-  /* 2254 */ 'p', 'k', 'h', 't', 'b', 0,
-  /* 2260 */ 's', 'm', 'l', 'a', 'l', 't', 'b', 0,
-  /* 2268 */ 's', 'm', 'u', 'l', 't', 'b', 0,
-  /* 2275 */ 'v', 'c', 'v', 't', 'b', 0,
-  /* 2281 */ 's', 'x', 't', 'b', 0,
-  /* 2286 */ 'u', 'x', 't', 'b', 0,
-  /* 2291 */ 'q', 'd', 's', 'u', 'b', 0,
-  /* 2297 */ 'v', 'h', 's', 'u', 'b', 0,
-  /* 2303 */ 'v', 'q', 's', 'u', 'b', 0,
-  /* 2309 */ 'v', 's', 'u', 'b', 0,
-  /* 2314 */ 's', 'm', 'l', 'a', 'w', 'b', 0,
-  /* 2321 */ 's', 'm', 'u', 'l', 'w', 'b', 0,
-  /* 2328 */ 'l', 'd', 'a', 'e', 'x', 'b', 0,
-  /* 2335 */ 's', 't', 'l', 'e', 'x', 'b', 0,
-  /* 2342 */ 'l', 'd', 'r', 'e', 'x', 'b', 0,
-  /* 2349 */ 's', 't', 'r', 'e', 'x', 'b', 0,
-  /* 2356 */ 's', 'b', 'c', 0,
-  /* 2360 */ 'a', 'd', 'c', 0,
-  /* 2364 */ 'l', 'd', 'c', 0,
-  /* 2368 */ 'b', 'f', 'c', 0,
-  /* 2372 */ 'v', 'b', 'i', 'c', 0,
-  /* 2377 */ 's', 'm', 'c', 0,
-  /* 2381 */ 'm', 'r', 'c', 0,
-  /* 2385 */ 'm', 'r', 'r', 'c', 0,
-  /* 2390 */ 'r', 's', 'c', 0,
-  /* 2394 */ 's', 't', 'c', 0,
-  /* 2398 */ 's', 'v', 'c', 0,
-  /* 2402 */ 's', 'm', 'l', 'a', 'd', 0,
-  /* 2408 */ 's', 'm', 'u', 'a', 'd', 0,
-  /* 2414 */ 'v', 'a', 'b', 'd', 0,
-  /* 2419 */ 'q', 'd', 'a', 'd', 'd', 0,
-  /* 2425 */ 'v', 'r', 'h', 'a', 'd', 'd', 0,
-  /* 2432 */ 'v', 'h', 'a', 'd', 'd', 0,
-  /* 2438 */ 'v', 'p', 'a', 'd', 'd', 0,
-  /* 2444 */ 'v', 'q', 'a', 'd', 'd', 0,
-  /* 2450 */ 'v', 'a', 'd', 'd', 0,
-  /* 2455 */ 's', 'm', 'l', 'a', 'l', 'd', 0,
-  /* 2462 */ 'p', 'l', 'd', 0,
-  /* 2466 */ 's', 'm', 'l', 's', 'l', 'd', 0,
-  /* 2473 */ 'v', 'a', 'n', 'd', 0,
-  /* 2478 */ 'l', 'd', 'r', 'd', 0,
-  /* 2483 */ 's', 't', 'r', 'd', 0,
-  /* 2488 */ 's', 'm', 'l', 's', 'd', 0,
-  /* 2494 */ 's', 'm', 'u', 's', 'd', 0,
-  /* 2500 */ 'l', 'd', 'a', 'e', 'x', 'd', 0,
-  /* 2507 */ 's', 't', 'l', 'e', 'x', 'd', 0,
-  /* 2514 */ 'l', 'd', 'r', 'e', 'x', 'd', 0,
-  /* 2521 */ 's', 't', 'r', 'e', 'x', 'd', 0,
-  /* 2528 */ 'v', 'a', 'c', 'g', 'e', 0,
-  /* 2534 */ 'v', 'c', 'g', 'e', 0,
-  /* 2539 */ 'v', 'c', 'l', 'e', 0,
-  /* 2544 */ 'v', 'r', 'e', 'c', 'p', 'e', 0,
-  /* 2551 */ 'v', 'c', 'm', 'p', 'e', 0,
-  /* 2557 */ 'v', 'r', 's', 'q', 'r', 't', 'e', 0,
-  /* 2565 */ 'v', 'b', 'i', 'f', 0,
-  /* 2570 */ 'd', 'b', 'g', 0,
-  /* 2574 */ 'v', 'q', 'n', 'e', 'g', 0,
-  /* 2580 */ 'v', 'n', 'e', 'g', 0,
-  /* 2585 */ 's', 'g', 0,
-  /* 2588 */ 'l', 'd', 'a', 'h', 0,
-  /* 2593 */ 'v', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 0,
-  /* 2602 */ 's', 'x', 't', 'a', 'h', 0,
-  /* 2608 */ 'u', 'x', 't', 'a', 'h', 0,
-  /* 2614 */ 't', 'b', 'h', 0,
-  /* 2618 */ 's', 't', 'l', 'h', 0,
-  /* 2623 */ 'v', 'q', 'd', 'm', 'u', 'l', 'h', 0,
-  /* 2631 */ 'v', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 0,
-  /* 2640 */ 'l', 'd', 'r', 'h', 0,
-  /* 2645 */ 's', 't', 'r', 'h', 0,
-  /* 2650 */ 'v', 'q', 'r', 'd', 'm', 'l', 's', 'h', 0,
-  /* 2659 */ 'l', 'd', 'r', 's', 'h', 0,
-  /* 2665 */ 'p', 'u', 's', 'h', 0,
-  /* 2670 */ 'r', 'e', 'v', 's', 'h', 0,
-  /* 2676 */ 's', 'x', 't', 'h', 0,
-  /* 2681 */ 'u', 'x', 't', 'h', 0,
-  /* 2686 */ 'l', 'd', 'a', 'e', 'x', 'h', 0,
-  /* 2693 */ 's', 't', 'l', 'e', 'x', 'h', 0,
-  /* 2700 */ 'l', 'd', 'r', 'e', 'x', 'h', 0,
-  /* 2707 */ 's', 't', 'r', 'e', 'x', 'h', 0,
-  /* 2714 */ 'b', 'f', 'i', 0,
-  /* 2718 */ 'p', 'l', 'i', 0,
-  /* 2722 */ 'v', 's', 'l', 'i', 0,
-  /* 2727 */ 'v', 's', 'r', 'i', 0,
-  /* 2732 */ 'b', 'x', 'j', 0,
-  /* 2736 */ 'l', 'd', 'c', '2', 'l', 0,
-  /* 2742 */ 's', 't', 'c', '2', 'l', 0,
-  /* 2748 */ 'u', 'm', 'a', 'a', 'l', 0,
-  /* 2754 */ 'v', 'a', 'b', 'a', 'l', 0,
-  /* 2760 */ 'v', 'p', 'a', 'd', 'a', 'l', 0,
-  /* 2767 */ 'v', 'q', 'd', 'm', 'l', 'a', 'l', 0,
-  /* 2775 */ 's', 'm', 'l', 'a', 'l', 0,
-  /* 2781 */ 'u', 'm', 'l', 'a', 'l', 0,
-  /* 2787 */ 'v', 'm', 'l', 'a', 'l', 0,
-  /* 2793 */ 'v', 't', 'b', 'l', 0,
-  /* 2798 */ 'v', 's', 'u', 'b', 'l', 0,
-  /* 2804 */ 'l', 'd', 'c', 'l', 0,
-  /* 2809 */ 's', 't', 'c', 'l', 0,
-  /* 2814 */ 'v', 'a', 'b', 'd', 'l', 0,
-  /* 2820 */ 'v', 'p', 'a', 'd', 'd', 'l', 0,
-  /* 2827 */ 'v', 'a', 'd', 'd', 'l', 0,
-  /* 2833 */ 's', 'e', 'l', 0,
-  /* 2837 */ 'v', 'q', 's', 'h', 'l', 0,
-  /* 2843 */ 'v', 'q', 'r', 's', 'h', 'l', 0,
-  /* 2850 */ 'v', 'r', 's', 'h', 'l', 0,
-  /* 2856 */ 'v', 's', 'h', 'l', 0,
-  /* 2861 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0,
-  /* 2875 */ 'v', 's', 'h', 'l', 'l', 0,
-  /* 2881 */ 'v', 'q', 'd', 'm', 'u', 'l', 'l', 0,
-  /* 2889 */ 's', 'm', 'u', 'l', 'l', 0,
-  /* 2895 */ 'u', 'm', 'u', 'l', 'l', 0,
-  /* 2901 */ 'v', 'm', 'u', 'l', 'l', 0,
-  /* 2907 */ 'v', 'b', 's', 'l', 0,
-  /* 2912 */ 'v', 'q', 'd', 'm', 'l', 's', 'l', 0,
-  /* 2920 */ 'v', 'm', 'l', 's', 'l', 0,
-  /* 2926 */ 's', 't', 'l', 0,
-  /* 2930 */ 's', 'm', 'm', 'u', 'l', 0,
-  /* 2936 */ 'v', 'n', 'm', 'u', 'l', 0,
-  /* 2942 */ 'v', 'm', 'u', 'l', 0,
-  /* 2947 */ 'v', 'm', 'o', 'v', 'l', 0,
-  /* 2953 */ 'v', 'l', 'l', 'd', 'm', 0,
-  /* 2959 */ 'v', 'l', 's', 't', 'm', 0,
-  /* 2965 */ 'v', 'r', 's', 'u', 'b', 'h', 'n', 0,
-  /* 2973 */ 'v', 's', 'u', 'b', 'h', 'n', 0,
-  /* 2980 */ 'v', 'r', 'a', 'd', 'd', 'h', 'n', 0,
-  /* 2988 */ 'v', 'a', 'd', 'd', 'h', 'n', 0,
-  /* 2995 */ 'v', 'p', 'm', 'i', 'n', 0,
-  /* 3001 */ 'v', 'm', 'i', 'n', 0,
-  /* 3006 */ 'c', 'm', 'n', 0,
-  /* 3010 */ 'v', 'q', 's', 'h', 'r', 'n', 0,
-  /* 3017 */ 'v', 'q', 'r', 's', 'h', 'r', 'n', 0,
-  /* 3025 */ 'v', 'r', 's', 'h', 'r', 'n', 0,
-  /* 3032 */ 'v', 's', 'h', 'r', 'n', 0,
-  /* 3038 */ 'v', 'o', 'r', 'n', 0,
-  /* 3043 */ 'v', 't', 'r', 'n', 0,
-  /* 3048 */ 'v', 'q', 's', 'h', 'r', 'u', 'n', 0,
-  /* 3056 */ 'v', 'q', 'r', 's', 'h', 'r', 'u', 'n', 0,
-  /* 3065 */ 'v', 'q', 'm', 'o', 'v', 'u', 'n', 0,
-  /* 3073 */ 'v', 'm', 'v', 'n', 0,
-  /* 3078 */ 'v', 'q', 'm', 'o', 'v', 'n', 0,
-  /* 3085 */ 'v', 'm', 'o', 'v', 'n', 0,
-  /* 3091 */ 't', 'r', 'a', 'p', 0,
-  /* 3096 */ 'c', 'd', 'p', 0,
-  /* 3100 */ 'v', 'z', 'i', 'p', 0,
-  /* 3105 */ 'v', 'c', 'm', 'p', 0,
-  /* 3110 */ 'p', 'o', 'p', 0,
-  /* 3114 */ 'v', 'd', 'u', 'p', 0,
-  /* 3119 */ 'v', 's', 'w', 'p', 0,
-  /* 3124 */ 'v', 'u', 'z', 'p', 0,
-  /* 3129 */ 'v', 'c', 'e', 'q', 0,
-  /* 3134 */ 't', 'e', 'q', 0,
-  /* 3138 */ 's', 'm', 'm', 'l', 'a', 'r', 0,
-  /* 3145 */ 'm', 'c', 'r', 0,
-  /* 3149 */ 'a', 'd', 'r', 0,
-  /* 3153 */ 'v', 'l', 'd', 'r', 0,
-  /* 3158 */ 'v', 'r', 's', 'h', 'r', 0,
-  /* 3164 */ 'v', 's', 'h', 'r', 0,
-  /* 3169 */ 's', 'm', 'm', 'u', 'l', 'r', 0,
-  /* 3176 */ 'v', 'e', 'o', 'r', 0,
-  /* 3181 */ 'r', 'o', 'r', 0,
-  /* 3185 */ 'm', 'c', 'r', 'r', 0,
-  /* 3190 */ 'v', 'o', 'r', 'r', 0,
-  /* 3195 */ 'a', 's', 'r', 0,
-  /* 3199 */ 's', 'm', 'm', 'l', 's', 'r', 0,
-  /* 3206 */ 'v', 'm', 's', 'r', 0,
-  /* 3211 */ 'v', 'r', 'i', 'n', 't', 'r', 0,
-  /* 3218 */ 'v', 's', 't', 'r', 0,
-  /* 3223 */ 'v', 'c', 'v', 't', 'r', 0,
-  /* 3229 */ 'v', 'q', 'a', 'b', 's', 0,
-  /* 3235 */ 'v', 'a', 'b', 's', 0,
-  /* 3240 */ 's', 'u', 'b', 's', 0,
-  /* 3245 */ 'v', 'c', 'l', 's', 0,
-  /* 3250 */ 's', 'm', 'm', 'l', 's', 0,
-  /* 3256 */ 'v', 'n', 'm', 'l', 's', 0,
-  /* 3262 */ 'v', 'm', 'l', 's', 0,
-  /* 3267 */ 'v', 'f', 'm', 's', 0,
-  /* 3272 */ 'v', 'f', 'n', 'm', 's', 0,
-  /* 3278 */ 'b', 'x', 'n', 's', 0,
-  /* 3283 */ 'b', 'l', 'x', 'n', 's', 0,
-  /* 3289 */ 'v', 'r', 'e', 'c', 'p', 's', 0,
-  /* 3296 */ 'v', 'm', 'r', 's', 0,
-  /* 3301 */ 'a', 's', 'r', 's', 0,
-  /* 3306 */ 'l', 's', 'r', 's', 0,
-  /* 3311 */ 'v', 'r', 's', 'q', 'r', 't', 's', 0,
-  /* 3319 */ 'm', 'o', 'v', 's', 0,
-  /* 3324 */ 's', 's', 'a', 't', 0,
-  /* 3329 */ 'u', 's', 'a', 't', 0,
-  /* 3334 */ 't', 't', 'a', 't', 0,
-  /* 3339 */ 's', 'm', 'l', 'a', 'b', 't', 0,
-  /* 3346 */ 'p', 'k', 'h', 'b', 't', 0,
-  /* 3352 */ 's', 'm', 'l', 'a', 'l', 'b', 't', 0,
-  /* 3360 */ 's', 'm', 'u', 'l', 'b', 't', 0,
-  /* 3367 */ 'l', 'd', 'r', 'b', 't', 0,
-  /* 3373 */ 's', 't', 'r', 'b', 't', 0,
-  /* 3379 */ 'l', 'd', 'r', 's', 'b', 't', 0,
-  /* 3386 */ 'e', 'r', 'e', 't', 0,
-  /* 3391 */ 'v', 'a', 'c', 'g', 't', 0,
-  /* 3397 */ 'v', 'c', 'g', 't', 0,
-  /* 3402 */ 'l', 'd', 'r', 'h', 't', 0,
-  /* 3408 */ 's', 't', 'r', 'h', 't', 0,
-  /* 3414 */ 'l', 'd', 'r', 's', 'h', 't', 0,
-  /* 3421 */ 'r', 'b', 'i', 't', 0,
-  /* 3426 */ 'v', 'b', 'i', 't', 0,
-  /* 3431 */ 'v', 'c', 'l', 't', 0,
-  /* 3436 */ 'v', 'c', 'n', 't', 0,
-  /* 3441 */ 'h', 'i', 'n', 't', 0,
-  /* 3446 */ 'l', 'd', 'r', 't', 0,
-  /* 3451 */ 'v', 's', 'q', 'r', 't', 0,
-  /* 3457 */ 's', 't', 'r', 't', 0,
-  /* 3462 */ 'v', 't', 's', 't', 0,
-  /* 3467 */ 's', 'm', 'l', 'a', 't', 't', 0,
-  /* 3474 */ 's', 'm', 'l', 'a', 'l', 't', 't', 0,
-  /* 3482 */ 's', 'm', 'u', 'l', 't', 't', 0,
-  /* 3489 */ 't', 't', 't', 0,
-  /* 3493 */ 'v', 'c', 'v', 't', 't', 0,
-  /* 3499 */ 'v', 'j', 'c', 'v', 't', 0,
-  /* 3505 */ 'v', 'c', 'v', 't', 0,
-  /* 3510 */ 'm', 'o', 'v', 't', 0,
-  /* 3515 */ 's', 'm', 'l', 'a', 'w', 't', 0,
-  /* 3522 */ 's', 'm', 'u', 'l', 'w', 't', 0,
-  /* 3529 */ 'v', 'e', 'x', 't', 0,
-  /* 3534 */ 'v', 'q', 's', 'h', 'l', 'u', 0,
-  /* 3541 */ 'r', 'e', 'v', 0,
-  /* 3545 */ 's', 'd', 'i', 'v', 0,
-  /* 3550 */ 'u', 'd', 'i', 'v', 0,
-  /* 3555 */ 'v', 'd', 'i', 'v', 0,
-  /* 3560 */ 'v', 'm', 'o', 'v', 0,
-  /* 3565 */ 'v', 's', 'u', 'b', 'w', 0,
-  /* 3571 */ 'v', 'a', 'd', 'd', 'w', 0,
-  /* 3577 */ 'p', 'l', 'd', 'w', 0,
-  /* 3582 */ 'm', 'o', 'v', 'w', 0,
-  /* 3587 */ 'f', 'l', 'd', 'm', 'i', 'a', 'x', 0,
-  /* 3595 */ 'f', 's', 't', 'm', 'i', 'a', 'x', 0,
-  /* 3603 */ 'v', 'p', 'm', 'a', 'x', 0,
-  /* 3609 */ 'v', 'm', 'a', 'x', 0,
-  /* 3614 */ 's', 'h', 's', 'a', 'x', 0,
-  /* 3620 */ 'u', 'h', 's', 'a', 'x', 0,
-  /* 3626 */ 'u', 'q', 's', 'a', 'x', 0,
-  /* 3632 */ 's', 's', 'a', 'x', 0,
-  /* 3637 */ 'u', 's', 'a', 'x', 0,
-  /* 3642 */ 'f', 'l', 'd', 'm', 'd', 'b', 'x', 0,
-  /* 3650 */ 'f', 's', 't', 'm', 'd', 'b', 'x', 0,
-  /* 3658 */ 'v', 't', 'b', 'x', 0,
-  /* 3663 */ 's', 'm', 'l', 'a', 'd', 'x', 0,
-  /* 3670 */ 's', 'm', 'u', 'a', 'd', 'x', 0,
-  /* 3677 */ 's', 'm', 'l', 'a', 'l', 'd', 'x', 0,
-  /* 3685 */ 's', 'm', 'l', 's', 'l', 'd', 'x', 0,
-  /* 3693 */ 's', 'm', 'l', 's', 'd', 'x', 0,
-  /* 3700 */ 's', 'm', 'u', 's', 'd', 'x', 0,
-  /* 3707 */ 'l', 'd', 'a', 'e', 'x', 0,
-  /* 3713 */ 's', 't', 'l', 'e', 'x', 0,
-  /* 3719 */ 'l', 'd', 'r', 'e', 'x', 0,
-  /* 3725 */ 'c', 'l', 'r', 'e', 'x', 0,
-  /* 3731 */ 's', 't', 'r', 'e', 'x', 0,
-  /* 3737 */ 's', 'b', 'f', 'x', 0,
-  /* 3742 */ 'u', 'b', 'f', 'x', 0,
-  /* 3747 */ 'b', 'l', 'x', 0,
-  /* 3751 */ 'r', 'r', 'x', 0,
-  /* 3755 */ 's', 'h', 'a', 's', 'x', 0,
-  /* 3761 */ 'u', 'h', 'a', 's', 'x', 0,
-  /* 3767 */ 'u', 'q', 'a', 's', 'x', 0,
-  /* 3773 */ 's', 'a', 's', 'x', 0,
-  /* 3778 */ 'u', 'a', 's', 'x', 0,
-  /* 3783 */ 'v', 'r', 'i', 'n', 't', 'x', 0,
-  /* 3790 */ 'v', 'c', 'l', 'z', 0,
-  /* 3795 */ 'v', 'r', 'i', 'n', 't', 'z', 0,
-  };
-#endif
+  /* 0 */ "vcx1\t\0"
+  /* 6 */ "vld20.32\t\0"
+  /* 16 */ "vst20.32\t\0"
+  /* 26 */ "vld40.32\t\0"
+  /* 36 */ "vst40.32\t\0"
+  /* 46 */ "sha1su0.32\t\0"
+  /* 58 */ "sha256su0.32\t\0"
+  /* 72 */ "vld21.32\t\0"
+  /* 82 */ "vst21.32\t\0"
+  /* 92 */ "vld41.32\t\0"
+  /* 102 */ "vst41.32\t\0"
+  /* 112 */ "sha1su1.32\t\0"
+  /* 124 */ "sha256su1.32\t\0"
+  /* 138 */ "vld42.32\t\0"
+  /* 148 */ "vst42.32\t\0"
+  /* 158 */ "sha256h2.32\t\0"
+  /* 171 */ "vld43.32\t\0"
+  /* 181 */ "vst43.32\t\0"
+  /* 191 */ "sha1c.32\t\0"
+  /* 201 */ "sha1h.32\t\0"
+  /* 211 */ "sha256h.32\t\0"
+  /* 223 */ "sha1m.32\t\0"
+  /* 233 */ "sha1p.32\t\0"
+  /* 243 */ "dlstp.32\t\0"
+  /* 253 */ "wlstp.32\t\0"
+  /* 263 */ "vcvta.s32.f32\t\0"
+  /* 278 */ "vcvtm.s32.f32\t\0"
+  /* 293 */ "vcvtn.s32.f32\t\0"
+  /* 308 */ "vcvtp.s32.f32\t\0"
+  /* 323 */ "vcvta.u32.f32\t\0"
+  /* 338 */ "vcvtm.u32.f32\t\0"
+  /* 353 */ "vcvtn.u32.f32\t\0"
+  /* 368 */ "vcvtp.u32.f32\t\0"
+  /* 383 */ "vcmla.f32\t\0"
+  /* 394 */ "vrinta.f32\t\0"
+  /* 406 */ "vcadd.f32\t\0"
+  /* 417 */ "vselge.f32\t\0"
+  /* 429 */ "vminnm.f32\t\0"
+  /* 441 */ "vmaxnm.f32\t\0"
+  /* 453 */ "vrintm.f32\t\0"
+  /* 465 */ "vrintn.f32\t\0"
+  /* 477 */ "vrintp.f32\t\0"
+  /* 489 */ "vseleq.f32\t\0"
+  /* 501 */ "vselvs.f32\t\0"
+  /* 513 */ "vselgt.f32\t\0"
+  /* 525 */ "vrintx.f32\t\0"
+  /* 537 */ "vrintz.f32\t\0"
+  /* 549 */ "ldc2\t\0"
+  /* 555 */ "mrc2\t\0"
+  /* 561 */ "mrrc2\t\0"
+  /* 568 */ "stc2\t\0"
+  /* 574 */ "cdp2\t\0"
+  /* 580 */ "mcr2\t\0"
+  /* 586 */ "mcrr2\t\0"
+  /* 593 */ "vcx2\t\0"
+  /* 599 */ "vcx3\t\0"
+  /* 605 */ "dlstp.64\t\0"
+  /* 615 */ "wlstp.64\t\0"
+  /* 625 */ "vcvta.s32.f64\t\0"
+  /* 640 */ "vcvtm.s32.f64\t\0"
+  /* 655 */ "vcvtn.s32.f64\t\0"
+  /* 670 */ "vcvtp.s32.f64\t\0"
+  /* 685 */ "vcvta.u32.f64\t\0"
+  /* 700 */ "vcvtm.u32.f64\t\0"
+  /* 715 */ "vcvtn.u32.f64\t\0"
+  /* 730 */ "vcvtp.u32.f64\t\0"
+  /* 745 */ "vrinta.f64\t\0"
+  /* 757 */ "vselge.f64\t\0"
+  /* 769 */ "vminnm.f64\t\0"
+  /* 781 */ "vmaxnm.f64\t\0"
+  /* 793 */ "vrintm.f64\t\0"
+  /* 805 */ "vrintn.f64\t\0"
+  /* 817 */ "vrintp.f64\t\0"
+  /* 829 */ "vseleq.f64\t\0"
+  /* 841 */ "vselvs.f64\t\0"
+  /* 853 */ "vselgt.f64\t\0"
+  /* 865 */ "vmull.p64\t\0"
+  /* 876 */ "vld20.16\t\0"
+  /* 886 */ "vst20.16\t\0"
+  /* 896 */ "vld40.16\t\0"
+  /* 906 */ "vst40.16\t\0"
+  /* 916 */ "vld21.16\t\0"
+  /* 926 */ "vst21.16\t\0"
+  /* 936 */ "vld41.16\t\0"
+  /* 946 */ "vst41.16\t\0"
+  /* 956 */ "vld42.16\t\0"
+  /* 966 */ "vst42.16\t\0"
+  /* 976 */ "vld43.16\t\0"
+  /* 986 */ "vst43.16\t\0"
+  /* 996 */ "dlstp.16\t\0"
+  /* 1006 */ "wlstp.16\t\0"
+  /* 1016 */ "vcvta.s32.f16\t\0"
+  /* 1031 */ "vcvtm.s32.f16\t\0"
+  /* 1046 */ "vcvtn.s32.f16\t\0"
+  /* 1061 */ "vcvtp.s32.f16\t\0"
+  /* 1076 */ "vcvta.u32.f16\t\0"
+  /* 1091 */ "vcvtm.u32.f16\t\0"
+  /* 1106 */ "vcvtn.u32.f16\t\0"
+  /* 1121 */ "vcvtp.u32.f16\t\0"
+  /* 1136 */ "vcvta.s16.f16\t\0"
+  /* 1151 */ "vcvtm.s16.f16\t\0"
+  /* 1166 */ "vcvtn.s16.f16\t\0"
+  /* 1181 */ "vcvtp.s16.f16\t\0"
+  /* 1196 */ "vcvta.u16.f16\t\0"
+  /* 1211 */ "vcvtm.u16.f16\t\0"
+  /* 1226 */ "vcvtn.u16.f16\t\0"
+  /* 1241 */ "vcvtp.u16.f16\t\0"
+  /* 1256 */ "vcmla.f16\t\0"
+  /* 1267 */ "vrinta.f16\t\0"
+  /* 1279 */ "vcadd.f16\t\0"
+  /* 1290 */ "vselge.f16\t\0"
+  /* 1302 */ "vfmal.f16\t\0"
+  /* 1313 */ "vfmsl.f16\t\0"
+  /* 1324 */ "vminnm.f16\t\0"
+  /* 1336 */ "vmaxnm.f16\t\0"
+  /* 1348 */ "vrintm.f16\t\0"
+  /* 1360 */ "vrintn.f16\t\0"
+  /* 1372 */ "vrintp.f16\t\0"
+  /* 1384 */ "vseleq.f16\t\0"
+  /* 1396 */ "vins.f16\t\0"
+  /* 1406 */ "vselvs.f16\t\0"
+  /* 1418 */ "vselgt.f16\t\0"
+  /* 1430 */ "vrintx.f16\t\0"
+  /* 1442 */ "vmovx.f16\t\0"
+  /* 1453 */ "vrintz.f16\t\0"
+  /* 1465 */ "vmmla.bf16\t\0"
+  /* 1477 */ "vfmab.bf16\t\0"
+  /* 1489 */ "vfmat.bf16\t\0"
+  /* 1501 */ "vdot.bf16\t\0"
+  /* 1512 */ "vld20.8\t\0"
+  /* 1521 */ "vst20.8\t\0"
+  /* 1530 */ "vld40.8\t\0"
+  /* 1539 */ "vst40.8\t\0"
+  /* 1548 */ "vld21.8\t\0"
+  /* 1557 */ "vst21.8\t\0"
+  /* 1566 */ "vld41.8\t\0"
+  /* 1575 */ "vst41.8\t\0"
+  /* 1584 */ "vld42.8\t\0"
+  /* 1593 */ "vst42.8\t\0"
+  /* 1602 */ "vld43.8\t\0"
+  /* 1611 */ "vst43.8\t\0"
+  /* 1620 */ "aesimc.8\t\0"
+  /* 1630 */ "aesmc.8\t\0"
+  /* 1639 */ "aesd.8\t\0"
+  /* 1647 */ "aese.8\t\0"
+  /* 1655 */ "dlstp.8\t\0"
+  /* 1664 */ "wlstp.8\t\0"
+  /* 1673 */ "vusmmla.s8\t\0"
+  /* 1685 */ "vsmmla.s8\t\0"
+  /* 1696 */ "vusdot.s8\t\0"
+  /* 1707 */ "vsdot.s8\t\0"
+  /* 1717 */ "vummla.u8\t\0"
+  /* 1728 */ "vsudot.u8\t\0"
+  /* 1739 */ "vudot.u8\t\0"
+  /* 1749 */ "vcx1a\t\0"
+  /* 1756 */ "vcx2a\t\0"
+  /* 1763 */ "vcx3a\t\0"
+  /* 1770 */ "rfeda\t\0"
+  /* 1777 */ "rfeia\t\0"
+  /* 1784 */ "crc32b\t\0"
+  /* 1792 */ "crc32cb\t\0"
+  /* 1801 */ "rfedb\t\0"
+  /* 1808 */ "rfeib\t\0"
+  /* 1815 */ "dmb\t\0"
+  /* 1820 */ "dsb\t\0"
+  /* 1825 */ "isb\t\0"
+  /* 1830 */ "tsb\t\0"
+  /* 1835 */ "csinc\t\0"
+  /* 1842 */ "hvc\t\0"
+  /* 1847 */ "cx1d\t\0"
+  /* 1853 */ "cx2d\t\0"
+  /* 1859 */ "cx3d\t\0"
+  /* 1865 */ "pld\t\0"
+  /* 1870 */ "setend\t\0"
+  /* 1878 */ "le\t\0"
+  /* 1882 */ "udf\t\0"
+  /* 1887 */ "csneg\t\0"
+  /* 1894 */ "crc32h\t\0"
+  /* 1902 */ "crc32ch\t\0"
+  /* 1911 */ "pli\t\0"
+  /* 1916 */ "bti\t\0"
+  /* 1921 */ "ldc2l\t\0"
+  /* 1928 */ "stc2l\t\0"
+  /* 1935 */ "bl\t\0"
+  /* 1939 */ "bfcsel\t\0"
+  /* 1947 */ "setpan\t\0"
+  /* 1955 */ "letp\t\0"
+  /* 1961 */ "dls\t\0"
+  /* 1966 */ "wls\t\0"
+  /* 1971 */ "cps\t\0"
+  /* 1976 */ "movs\t\0"
+  /* 1982 */ "hlt\t\0"
+  /* 1987 */ "bkpt\t\0"
+  /* 1993 */ "csinv\t\0"
+  /* 2000 */ "hvc.w\t\0"
+  /* 2007 */ "udf.w\t\0"
+  /* 2014 */ "crc32w\t\0"
+  /* 2022 */ "crc32cw\t\0"
+  /* 2031 */ "pldw\t\0"
+  /* 2037 */ "bx\t\0"
+  /* 2041 */ "blx\t\0"
+  /* 2046 */ "cbz\t\0"
+  /* 2051 */ "cbnz\t\0"
+  /* 2057 */ "srsda\tsp!, \0"
+  /* 2069 */ "srsia\tsp!, \0"
+  /* 2081 */ "srsdb\tsp!, \0"
+  /* 2093 */ "srsib\tsp!, \0"
+  /* 2105 */ "srsda\tsp, \0"
+  /* 2116 */ "srsia\tsp, \0"
+  /* 2127 */ "srsdb\tsp, \0"
+  /* 2138 */ "srsib\tsp, \0"
+  /* 2149 */ "# XRay Function Patchable RET.\0"
+  /* 2180 */ "# XRay Typed Event Log.\0"
+  /* 2204 */ "# XRay Custom Event Log.\0"
+  /* 2229 */ "# XRay Function Enter.\0"
+  /* 2252 */ "# XRay Tail Call Exit.\0"
+  /* 2275 */ "# XRay Function Exit.\0"
+  /* 2297 */ "__brkdiv0\0"
+  /* 2307 */ "vld1\0"
+  /* 2312 */ "dcps1\0"
+  /* 2318 */ "vst1\0"
+  /* 2323 */ "vcx1\0"
+  /* 2328 */ "vrev32\0"
+  /* 2335 */ "ldc2\0"
+  /* 2340 */ "mrc2\0"
+  /* 2345 */ "mrrc2\0"
+  /* 2351 */ "stc2\0"
+  /* 2356 */ "vld2\0"
+  /* 2361 */ "cdp2\0"
+  /* 2366 */ "mcr2\0"
+  /* 2371 */ "mcrr2\0"
+  /* 2377 */ "dcps2\0"
+  /* 2383 */ "vst2\0"
+  /* 2388 */ "vcx2\0"
+  /* 2393 */ "vld3\0"
+  /* 2398 */ "dcps3\0"
+  /* 2404 */ "vst3\0"
+  /* 2409 */ "vcx3\0"
+  /* 2414 */ "vrev64\0"
+  /* 2421 */ "vld4\0"
+  /* 2426 */ "vst4\0"
+  /* 2431 */ "sxtab16\0"
+  /* 2439 */ "uxtab16\0"
+  /* 2447 */ "sxtb16\0"
+  /* 2454 */ "uxtb16\0"
+  /* 2461 */ "shsub16\0"
+  /* 2469 */ "uhsub16\0"
+  /* 2477 */ "uqsub16\0"
+  /* 2485 */ "ssub16\0"
+  /* 2492 */ "usub16\0"
+  /* 2499 */ "shadd16\0"
+  /* 2507 */ "uhadd16\0"
+  /* 2515 */ "uqadd16\0"
+  /* 2523 */ "sadd16\0"
+  /* 2530 */ "uadd16\0"
+  /* 2537 */ "ssat16\0"
+  /* 2544 */ "usat16\0"
+  /* 2551 */ "vrev16\0"
+  /* 2558 */ "usada8\0"
+  /* 2565 */ "shsub8\0"
+  /* 2572 */ "uhsub8\0"
+  /* 2579 */ "uqsub8\0"
+  /* 2586 */ "ssub8\0"
+  /* 2592 */ "usub8\0"
+  /* 2598 */ "usad8\0"
+  /* 2604 */ "shadd8\0"
+  /* 2611 */ "uhadd8\0"
+  /* 2618 */ "uqadd8\0"
+  /* 2625 */ "sadd8\0"
+  /* 2631 */ "uadd8\0"
+  /* 2637 */ "LIFETIME_END\0"
+  /* 2650 */ "PSEUDO_PROBE\0"
+  /* 2663 */ "BUNDLE\0"
+  /* 2670 */ "DBG_VALUE\0"
+  /* 2680 */ "DBG_INSTR_REF\0"
+  /* 2694 */ "DBG_PHI\0"
+  /* 2702 */ "DBG_LABEL\0"
+  /* 2712 */ "LIFETIME_START\0"
+  /* 2727 */ "DBG_VALUE_LIST\0"
+  /* 2742 */ "vcx1a\0"
+  /* 2748 */ "vcx2a\0"
+  /* 2754 */ "vcx3a\0"
+  /* 2760 */ "vaba\0"
+  /* 2765 */ "cx1da\0"
+  /* 2771 */ "cx2da\0"
+  /* 2777 */ "cx3da\0"
+  /* 2783 */ "lda\0"
+  /* 2787 */ "ldmda\0"
+  /* 2793 */ "stmda\0"
+  /* 2799 */ "vrmlaldavha\0"
+  /* 2811 */ "vrmlsldavha\0"
+  /* 2823 */ "rfeia\0"
+  /* 2829 */ "vldmia\0"
+  /* 2836 */ "vstmia\0"
+  /* 2843 */ "srsia\0"
+  /* 2849 */ "vcmla\0"
+  /* 2855 */ "smmla\0"
+  /* 2861 */ "vnmla\0"
+  /* 2867 */ "vmla\0"
+  /* 2872 */ "vfma\0"
+  /* 2877 */ "vfnma\0"
+  /* 2883 */ "vminnma\0"
+  /* 2891 */ "vmaxnma\0"
+  /* 2899 */ "vmina\0"
+  /* 2905 */ "vrsra\0"
+  /* 2911 */ "vsra\0"
+  /* 2916 */ "vrinta\0"
+  /* 2923 */ "tta\0"
+  /* 2927 */ "vcvta\0"
+  /* 2933 */ "vmladava\0"
+  /* 2942 */ "vmlaldava\0"
+  /* 2952 */ "vmlsldava\0"
+  /* 2962 */ "vmlsdava\0"
+  /* 2971 */ "vaddva\0"
+  /* 2978 */ "vaddlva\0"
+  /* 2986 */ "vmaxa\0"
+  /* 2992 */ "ldab\0"
+  /* 2997 */ "sxtab\0"
+  /* 3003 */ "uxtab\0"
+  /* 3009 */ "smlabb\0"
+  /* 3016 */ "smlalbb\0"
+  /* 3024 */ "smulbb\0"
+  /* 3031 */ "tbb\0"
+  /* 3035 */ "rfedb\0"
+  /* 3041 */ "vldmdb\0"
+  /* 3048 */ "vstmdb\0"
+  /* 3055 */ "srsdb\0"
+  /* 3061 */ "ldmib\0"
+  /* 3067 */ "stmib\0"
+  /* 3073 */ "vshllb\0"
+  /* 3080 */ "vqdmullb\0"
+  /* 3089 */ "vmullb\0"
+  /* 3096 */ "stlb\0"
+  /* 3101 */ "vmovlb\0"
+  /* 3108 */ "dmb\0"
+  /* 3112 */ "vqshrnb\0"
+  /* 3120 */ "vqrshrnb\0"
+  /* 3129 */ "vrshrnb\0"
+  /* 3137 */ "vshrnb\0"
+  /* 3144 */ "vqshrunb\0"
+  /* 3153 */ "vqrshrunb\0"
+  /* 3163 */ "vqmovunb\0"
+  /* 3172 */ "vqmovnb\0"
+  /* 3180 */ "vmovnb\0"
+  /* 3187 */ "swpb\0"
+  /* 3192 */ "vldrb\0"
+  /* 3198 */ "vstrb\0"
+  /* 3204 */ "dsb\0"
+  /* 3208 */ "isb\0"
+  /* 3212 */ "ldrsb\0"
+  /* 3218 */ "tsb\0"
+  /* 3222 */ "smlatb\0"
+  /* 3229 */ "pkhtb\0"
+  /* 3235 */ "smlaltb\0"
+  /* 3243 */ "smultb\0"
+  /* 3250 */ "vcvtb\0"
+  /* 3256 */ "sxtb\0"
+  /* 3261 */ "uxtb\0"
+  /* 3266 */ "qdsub\0"
+  /* 3272 */ "vhsub\0"
+  /* 3278 */ "vqsub\0"
+  /* 3284 */ "vsub\0"
+  /* 3289 */ "smlawb\0"
+  /* 3296 */ "smulwb\0"
+  /* 3303 */ "ldaexb\0"
+  /* 3310 */ "stlexb\0"
+  /* 3317 */ "ldrexb\0"
+  /* 3324 */ "strexb\0"
+  /* 3331 */ "vsbc\0"
+  /* 3336 */ "vadc\0"
+  /* 3341 */ "ldc\0"
+  /* 3345 */ "bfc\0"
+  /* 3349 */ "vbic\0"
+  /* 3354 */ "vshlc\0"
+  /* 3360 */ "smc\0"
+  /* 3364 */ "mrc\0"
+  /* 3368 */ "mrrc\0"
+  /* 3373 */ "rsc\0"
+  /* 3377 */ "stc\0"
+  /* 3381 */ "svc\0"
+  /* 3385 */ "smlad\0"
+  /* 3391 */ "smuad\0"
+  /* 3397 */ "vabd\0"
+  /* 3402 */ "vhcadd\0"
+  /* 3409 */ "vcadd\0"
+  /* 3415 */ "qdadd\0"
+  /* 3421 */ "vrhadd\0"
+  /* 3428 */ "vhadd\0"
+  /* 3434 */ "vpadd\0"
+  /* 3440 */ "vqadd\0"
+  /* 3446 */ "vadd\0"
+  /* 3451 */ "smlald\0"
+  /* 3458 */ "pld\0"
+  /* 3462 */ "smlsld\0"
+  /* 3469 */ "vand\0"
+  /* 3474 */ "vldrd\0"
+  /* 3480 */ "vstrd\0"
+  /* 3486 */ "smlsd\0"
+  /* 3492 */ "smusd\0"
+  /* 3498 */ "ldaexd\0"
+  /* 3505 */ "stlexd\0"
+  /* 3512 */ "ldrexd\0"
+  /* 3519 */ "strexd\0"
+  /* 3526 */ "vacge\0"
+  /* 3532 */ "vcge\0"
+  /* 3537 */ "vcle\0"
+  /* 3542 */ "vrecpe\0"
+  /* 3549 */ "vcmpe\0"
+  /* 3555 */ "vrsqrte\0"
+  /* 3563 */ "bf\0"
+  /* 3566 */ "vbif\0"
+  /* 3571 */ "dbg\0"
+  /* 3575 */ "pacg\0"
+  /* 3580 */ "vqneg\0"
+  /* 3586 */ "vneg\0"
+  /* 3591 */ "sg\0"
+  /* 3594 */ "autg\0"
+  /* 3599 */ "ldah\0"
+  /* 3604 */ "vqdmlah\0"
+  /* 3612 */ "vqrdmlah\0"
+  /* 3621 */ "sxtah\0"
+  /* 3627 */ "uxtah\0"
+  /* 3633 */ "tbh\0"
+  /* 3637 */ "vqdmladh\0"
+  /* 3646 */ "vqrdmladh\0"
+  /* 3656 */ "vqdmlsdh\0"
+  /* 3665 */ "vqrdmlsdh\0"
+  /* 3675 */ "stlh\0"
+  /* 3680 */ "vqdmulh\0"
+  /* 3688 */ "vqrdmulh\0"
+  /* 3697 */ "vrmulh\0"
+  /* 3704 */ "vmulh\0"
+  /* 3710 */ "vldrh\0"
+  /* 3716 */ "vstrh\0"
+  /* 3722 */ "vqdmlash\0"
+  /* 3731 */ "vqrdmlash\0"
+  /* 3741 */ "vqrdmlsh\0"
+  /* 3750 */ "ldrsh\0"
+  /* 3756 */ "push\0"
+  /* 3761 */ "revsh\0"
+  /* 3767 */ "sxth\0"
+  /* 3772 */ "uxth\0"
+  /* 3777 */ "vrmlaldavh\0"
+  /* 3788 */ "vrmlsldavh\0"
+  /* 3799 */ "ldaexh\0"
+  /* 3806 */ "stlexh\0"
+  /* 3813 */ "ldrexh\0"
+  /* 3820 */ "strexh\0"
+  /* 3827 */ "vsbci\0"
+  /* 3833 */ "vadci\0"
+  /* 3839 */ "bfi\0"
+  /* 3843 */ "pli\0"
+  /* 3847 */ "vsli\0"
+  /* 3852 */ "vsri\0"
+  /* 3857 */ "bxj\0"
+  /* 3861 */ "ldc2l\0"
+  /* 3867 */ "stc2l\0"
+  /* 3873 */ "umaal\0"
+  /* 3879 */ "vabal\0"
+  /* 3885 */ "vpadal\0"
+  /* 3892 */ "vqdmlal\0"
+  /* 3900 */ "smlal\0"
+  /* 3906 */ "umlal\0"
+  /* 3912 */ "vmlal\0"
+  /* 3918 */ "vtbl\0"
+  /* 3923 */ "vsubl\0"
+  /* 3929 */ "ldcl\0"
+  /* 3934 */ "stcl\0"
+  /* 3939 */ "vabdl\0"
+  /* 3945 */ "vpaddl\0"
+  /* 3952 */ "vaddl\0"
+  /* 3958 */ "vpsel\0"
+  /* 3964 */ "bfl\0"
+  /* 3968 */ "sqshl\0"
+  /* 3974 */ "uqshl\0"
+  /* 3980 */ "vqshl\0"
+  /* 3986 */ "uqrshl\0"
+  /* 3993 */ "vqrshl\0"
+  /* 4000 */ "vrshl\0"
+  /* 4006 */ "vshl\0"
+  /* 4011 */ "# FEntry call\0"
+  /* 4025 */ "sqshll\0"
+  /* 4032 */ "uqshll\0"
+  /* 4039 */ "uqrshll\0"
+  /* 4047 */ "vshll\0"
+  /* 4053 */ "lsll\0"
+  /* 4058 */ "vqdmull\0"
+  /* 4066 */ "smull\0"
+  /* 4072 */ "umull\0"
+  /* 4078 */ "vmull\0"
+  /* 4084 */ "sqrshrl\0"
+  /* 4092 */ "srshrl\0"
+  /* 4099 */ "urshrl\0"
+  /* 4106 */ "asrl\0"
+  /* 4111 */ "lsrl\0"
+  /* 4116 */ "vbsl\0"
+  /* 4121 */ "vqdmlsl\0"
+  /* 4129 */ "vmlsl\0"
+  /* 4135 */ "stl\0"
+  /* 4139 */ "vcmul\0"
+  /* 4145 */ "smmul\0"
+  /* 4151 */ "vnmul\0"
+  /* 4157 */ "vmul\0"
+  /* 4162 */ "vmovl\0"
+  /* 4168 */ "vlldm\0"
+  /* 4174 */ "vminnm\0"
+  /* 4181 */ "vmaxnm\0"
+  /* 4188 */ "vscclrm\0"
+  /* 4196 */ "vrintm\0"
+  /* 4203 */ "vlstm\0"
+  /* 4209 */ "vcvtm\0"
+  /* 4215 */ "vrsubhn\0"
+  /* 4223 */ "vsubhn\0"
+  /* 4230 */ "vraddhn\0"
+  /* 4238 */ "vaddhn\0"
+  /* 4245 */ "vpmin\0"
+  /* 4251 */ "vmin\0"
+  /* 4256 */ "cmn\0"
+  /* 4260 */ "vqshrn\0"
+  /* 4267 */ "vqrshrn\0"
+  /* 4275 */ "vrshrn\0"
+  /* 4282 */ "vshrn\0"
+  /* 4288 */ "vorn\0"
+  /* 4293 */ "vtrn\0"
+  /* 4298 */ "vrintn\0"
+  /* 4305 */ "vcvtn\0"
+  /* 4311 */ "vqshrun\0"
+  /* 4319 */ "vqrshrun\0"
+  /* 4328 */ "vqmovun\0"
+  /* 4336 */ "vmvn\0"
+  /* 4341 */ "vqmovn\0"
+  /* 4348 */ "vmovn\0"
+  /* 4354 */ "trap\0"
+  /* 4359 */ "cdp\0"
+  /* 4363 */ "vzip\0"
+  /* 4368 */ "vcmp\0"
+  /* 4373 */ "pop\0"
+  /* 4377 */ "pac\tr12, lr, sp\0"
+  /* 4393 */ "pacbti\tr12, lr, sp\0"
+  /* 4412 */ "aut\tr12, lr, sp\0"
+  /* 4428 */ "lctp\0"
+  /* 4433 */ "vctp\0"
+  /* 4438 */ "vrintp\0"
+  /* 4445 */ "vcvtp\0"
+  /* 4451 */ "vddup\0"
+  /* 4457 */ "vidup\0"
+  /* 4463 */ "vdup\0"
+  /* 4468 */ "vdwdup\0"
+  /* 4475 */ "viwdup\0"
+  /* 4482 */ "vswp\0"
+  /* 4487 */ "vuzp\0"
+  /* 4492 */ "vceq\0"
+  /* 4497 */ "teq\0"
+  /* 4501 */ "smmlar\0"
+  /* 4508 */ "mcr\0"
+  /* 4512 */ "adr\0"
+  /* 4516 */ "vldr\0"
+  /* 4521 */ "sqrshr\0"
+  /* 4528 */ "srshr\0"
+  /* 4534 */ "urshr\0"
+  /* 4540 */ "vrshr\0"
+  /* 4546 */ "vshr\0"
+  /* 4551 */ "smmulr\0"
+  /* 4558 */ "veor\0"
+  /* 4563 */ "ror\0"
+  /* 4567 */ "mcrr\0"
+  /* 4572 */ "vorr\0"
+  /* 4577 */ "asr\0"
+  /* 4581 */ "smmlsr\0"
+  /* 4588 */ "vmsr\0"
+  /* 4593 */ "vbrsr\0"
+  /* 4599 */ "vrintr\0"
+  /* 4606 */ "vstr\0"
+  /* 4611 */ "vcvtr\0"
+  /* 4617 */ "vmlas\0"
+  /* 4623 */ "vfmas\0"
+  /* 4629 */ "vqabs\0"
+  /* 4635 */ "vabs\0"
+  /* 4640 */ "subs\0"
+  /* 4645 */ "vcls\0"
+  /* 4650 */ "smmls\0"
+  /* 4656 */ "vnmls\0"
+  /* 4662 */ "vmls\0"
+  /* 4667 */ "vfms\0"
+  /* 4672 */ "vfnms\0"
+  /* 4678 */ "bxns\0"
+  /* 4683 */ "blxns\0"
+  /* 4689 */ "vrecps\0"
+  /* 4696 */ "vmrs\0"
+  /* 4701 */ "asrs\0"
+  /* 4706 */ "lsrs\0"
+  /* 4711 */ "vrsqrts\0"
+  /* 4719 */ "movs\0"
+  /* 4724 */ "ssat\0"
+  /* 4729 */ "usat\0"
+  /* 4734 */ "ttat\0"
+  /* 4739 */ "smlabt\0"
+  /* 4746 */ "pkhbt\0"
+  /* 4752 */ "smlalbt\0"
+  /* 4760 */ "smulbt\0"
+  /* 4767 */ "ldrbt\0"
+  /* 4773 */ "strbt\0"
+  /* 4779 */ "ldrsbt\0"
+  /* 4786 */ "eret\0"
+  /* 4791 */ "vacgt\0"
+  /* 4797 */ "vcgt\0"
+  /* 4802 */ "ldrht\0"
+  /* 4808 */ "strht\0"
+  /* 4814 */ "ldrsht\0"
+  /* 4821 */ "rbit\0"
+  /* 4826 */ "vbit\0"
+  /* 4831 */ "vclt\0"
+  /* 4836 */ "vshllt\0"
+  /* 4843 */ "vqdmullt\0"
+  /* 4852 */ "vmullt\0"
+  /* 4859 */ "vmovlt\0"
+  /* 4866 */ "vcnt\0"
+  /* 4871 */ "hint\0"
+  /* 4876 */ "vqshrnt\0"
+  /* 4884 */ "vqrshrnt\0"
+  /* 4893 */ "vrshrnt\0"
+  /* 4901 */ "vshrnt\0"
+  /* 4908 */ "vqshrunt\0"
+  /* 4917 */ "vqrshrunt\0"
+  /* 4927 */ "vqmovunt\0"
+  /* 4936 */ "vqmovnt\0"
+  /* 4944 */ "vmovnt\0"
+  /* 4951 */ "vpnot\0"
+  /* 4957 */ "vpt\0"
+  /* 4961 */ "ldrt\0"
+  /* 4966 */ "vsqrt\0"
+  /* 4972 */ "strt\0"
+  /* 4977 */ "vpst\0"
+  /* 4982 */ "vtst\0"
+  /* 4987 */ "smlatt\0"
+  /* 4994 */ "smlaltt\0"
+  /* 5002 */ "smultt\0"
+  /* 5009 */ "ttt\0"
+  /* 5013 */ "vcvtt\0"
+  /* 5019 */ "bxaut\0"
+  /* 5025 */ "vjcvt\0"
+  /* 5031 */ "vcvt\0"
+  /* 5036 */ "movt\0"
+  /* 5041 */ "smlawt\0"
+  /* 5048 */ "smulwt\0"
+  /* 5055 */ "vext\0"
+  /* 5060 */ "vqshlu\0"
+  /* 5067 */ "vabav\0"
+  /* 5073 */ "vmladav\0"
+  /* 5081 */ "vmlaldav\0"
+  /* 5090 */ "vmlsldav\0"
+  /* 5099 */ "vmlsdav\0"
+  /* 5107 */ "vminnmav\0"
+  /* 5116 */ "vmaxnmav\0"
+  /* 5125 */ "vminav\0"
+  /* 5132 */ "vmaxav\0"
+  /* 5139 */ "vaddv\0"
+  /* 5145 */ "rev\0"
+  /* 5149 */ "sdiv\0"
+  /* 5154 */ "udiv\0"
+  /* 5159 */ "vdiv\0"
+  /* 5164 */ "vaddlv\0"
+  /* 5171 */ "vminnmv\0"
+  /* 5179 */ "vmaxnmv\0"
+  /* 5187 */ "vminv\0"
+  /* 5193 */ "vmov\0"
+  /* 5198 */ "vmaxv\0"
+  /* 5204 */ "vsubw\0"
+  /* 5210 */ "vaddw\0"
+  /* 5216 */ "pldw\0"
+  /* 5221 */ "vldrw\0"
+  /* 5227 */ "vstrw\0"
+  /* 5233 */ "movw\0"
+  /* 5238 */ "vrmlaldavhax\0"
+  /* 5251 */ "vrmlsldavhax\0"
+  /* 5264 */ "fldmiax\0"
+  /* 5272 */ "fstmiax\0"
+  /* 5280 */ "vpmax\0"
+  /* 5286 */ "vmax\0"
+  /* 5291 */ "shsax\0"
+  /* 5297 */ "uhsax\0"
+  /* 5303 */ "uqsax\0"
+  /* 5309 */ "ssax\0"
+  /* 5314 */ "usax\0"
+  /* 5319 */ "vmladavax\0"
+  /* 5329 */ "vmlaldavax\0"
+  /* 5340 */ "vmlsldavax\0"
+  /* 5351 */ "vmlsdavax\0"
+  /* 5361 */ "fldmdbx\0"
+  /* 5369 */ "fstmdbx\0"
+  /* 5377 */ "vtbx\0"
+  /* 5382 */ "smladx\0"
+  /* 5389 */ "smuadx\0"
+  /* 5396 */ "smlaldx\0"
+  /* 5404 */ "smlsldx\0"
+  /* 5412 */ "smlsdx\0"
+  /* 5419 */ "smusdx\0"
+  /* 5426 */ "ldaex\0"
+  /* 5432 */ "stlex\0"
+  /* 5438 */ "ldrex\0"
+  /* 5444 */ "clrex\0"
+  /* 5450 */ "strex\0"
+  /* 5456 */ "sbfx\0"
+  /* 5461 */ "ubfx\0"
+  /* 5466 */ "vqdmladhx\0"
+  /* 5476 */ "vqrdmladhx\0"
+  /* 5487 */ "vqdmlsdhx\0"
+  /* 5497 */ "vqrdmlsdhx\0"
+  /* 5508 */ "vrmlaldavhx\0"
+  /* 5520 */ "vrmlsldavhx\0"
+  /* 5532 */ "blx\0"
+  /* 5536 */ "bflx\0"
+  /* 5541 */ "rrx\0"
+  /* 5545 */ "shasx\0"
+  /* 5551 */ "uhasx\0"
+  /* 5557 */ "uqasx\0"
+  /* 5563 */ "sasx\0"
+  /* 5568 */ "uasx\0"
+  /* 5573 */ "vrintx\0"
+  /* 5580 */ "vmladavx\0"
+  /* 5589 */ "vmlaldavx\0"
+  /* 5599 */ "vmlsldavx\0"
+  /* 5609 */ "vmlsdavx\0"
+  /* 5618 */ "vclz\0"
+  /* 5623 */ "vrintz\0"
+};
+#endif // CAPSTONE_DIET
 
   static const uint32_t OpInfo0[] = {
     0U,	// PHI
     0U,	// INLINEASM
+    0U,	// INLINEASM_BR
     0U,	// CFI_INSTRUCTION
     0U,	// EH_LABEL
     0U,	// GC_LABEL
@@ -535,28 +761,39 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// IMPLICIT_DEF
     0U,	// SUBREG_TO_REG
     0U,	// COPY_TO_REGCLASS
-    1981U,	// DBG_VALUE
-    1991U,	// DBG_LABEL
+    2671U,	// DBG_VALUE
+    2728U,	// DBG_VALUE_LIST
+    2681U,	// DBG_INSTR_REF
+    2695U,	// DBG_PHI
+    2703U,	// DBG_LABEL
     0U,	// REG_SEQUENCE
     0U,	// COPY
-    1974U,	// BUNDLE
-    2020U,	// LIFETIME_START
-    1961U,	// LIFETIME_END
+    2664U,	// BUNDLE
+    2713U,	// LIFETIME_START
+    2638U,	// LIFETIME_END
+    2651U,	// PSEUDO_PROBE
+    0U,	// ARITH_FENCE
     0U,	// STACKMAP
-    2862U,	// FENTRY_CALL
+    4012U,	// FENTRY_CALL
     0U,	// PATCHPOINT
     0U,	// LOAD_STACK_GUARD
+    0U,	// PREALLOCATED_SETUP
+    0U,	// PREALLOCATED_ARG
     0U,	// STATEPOINT
     0U,	// LOCAL_ESCAPE
     0U,	// FAULTING_OP
     0U,	// PATCHABLE_OP
-    1568U,	// PATCHABLE_FUNCTION_ENTER
-    1488U,	// PATCHABLE_RET
-    1614U,	// PATCHABLE_FUNCTION_EXIT
-    1591U,	// PATCHABLE_TAIL_CALL
-    1543U,	// PATCHABLE_EVENT_CALL
-    1519U,	// PATCHABLE_TYPED_EVENT_CALL
+    2230U,	// PATCHABLE_FUNCTION_ENTER
+    2150U,	// PATCHABLE_RET
+    2276U,	// PATCHABLE_FUNCTION_EXIT
+    2253U,	// PATCHABLE_TAIL_CALL
+    2205U,	// PATCHABLE_EVENT_CALL
+    2181U,	// PATCHABLE_TYPED_EVENT_CALL
     0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
+    0U,	// G_ASSERT_SEXT
+    0U,	// G_ASSERT_ZEXT
+    0U,	// G_ASSERT_ALIGN
     0U,	// G_ADD
     0U,	// G_SUB
     0U,	// G_MUL
@@ -564,6 +801,8 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_UDIV
     0U,	// G_SREM
     0U,	// G_UREM
+    0U,	// G_SDIVREM
+    0U,	// G_UDIVREM
     0U,	// G_AND
     0U,	// G_OR
     0U,	// G_XOR
@@ -575,13 +814,27 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_UNMERGE_VALUES
     0U,	// G_INSERT
     0U,	// G_MERGE_VALUES
+    0U,	// G_BUILD_VECTOR
+    0U,	// G_BUILD_VECTOR_TRUNC
+    0U,	// G_CONCAT_VECTORS
     0U,	// G_PTRTOINT
     0U,	// G_INTTOPTR
     0U,	// G_BITCAST
+    0U,	// G_FREEZE
+    0U,	// G_INTRINSIC_FPTRUNC_ROUND
+    0U,	// G_INTRINSIC_TRUNC
+    0U,	// G_INTRINSIC_ROUND
+    0U,	// G_INTRINSIC_LRINT
+    0U,	// G_INTRINSIC_ROUNDEVEN
+    0U,	// G_READCYCLECOUNTER
     0U,	// G_LOAD
     0U,	// G_SEXTLOAD
     0U,	// G_ZEXTLOAD
+    0U,	// G_INDEXED_LOAD
+    0U,	// G_INDEXED_SEXTLOAD
+    0U,	// G_INDEXED_ZEXTLOAD
     0U,	// G_STORE
+    0U,	// G_INDEXED_STORE
     0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
     0U,	// G_ATOMIC_CMPXCHG
     0U,	// G_ATOMICRMW_XCHG
@@ -595,8 +848,16 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_ATOMICRMW_MIN
     0U,	// G_ATOMICRMW_UMAX
     0U,	// G_ATOMICRMW_UMIN
+    0U,	// G_ATOMICRMW_FADD
+    0U,	// G_ATOMICRMW_FSUB
+    0U,	// G_ATOMICRMW_FMAX
+    0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
+    0U,	// G_FENCE
     0U,	// G_BRCOND
     0U,	// G_BRINDIRECT
+    0U,	// G_INVOKE_REGION_START
     0U,	// G_INTRINSIC
     0U,	// G_INTRINSIC_W_SIDE_EFFECTS
     0U,	// G_ANYEXT
@@ -606,32 +867,58 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_VASTART
     0U,	// G_VAARG
     0U,	// G_SEXT
+    0U,	// G_SEXT_INREG
     0U,	// G_ZEXT
     0U,	// G_SHL
     0U,	// G_LSHR
     0U,	// G_ASHR
+    0U,	// G_FSHL
+    0U,	// G_FSHR
+    0U,	// G_ROTR
+    0U,	// G_ROTL
     0U,	// G_ICMP
     0U,	// G_FCMP
     0U,	// G_SELECT
+    0U,	// G_UADDO
     0U,	// G_UADDE
+    0U,	// G_USUBO
     0U,	// G_USUBE
     0U,	// G_SADDO
+    0U,	// G_SADDE
     0U,	// G_SSUBO
+    0U,	// G_SSUBE
     0U,	// G_UMULO
     0U,	// G_SMULO
     0U,	// G_UMULH
     0U,	// G_SMULH
+    0U,	// G_UADDSAT
+    0U,	// G_SADDSAT
+    0U,	// G_USUBSAT
+    0U,	// G_SSUBSAT
+    0U,	// G_USHLSAT
+    0U,	// G_SSHLSAT
+    0U,	// G_SMULFIX
+    0U,	// G_UMULFIX
+    0U,	// G_SMULFIXSAT
+    0U,	// G_UMULFIXSAT
+    0U,	// G_SDIVFIX
+    0U,	// G_UDIVFIX
+    0U,	// G_SDIVFIXSAT
+    0U,	// G_UDIVFIXSAT
     0U,	// G_FADD
     0U,	// G_FSUB
     0U,	// G_FMUL
     0U,	// G_FMA
+    0U,	// G_FMAD
     0U,	// G_FDIV
     0U,	// G_FREM
     0U,	// G_FPOW
+    0U,	// G_FPOWI
     0U,	// G_FEXP
     0U,	// G_FEXP2
     0U,	// G_FLOG
     0U,	// G_FLOG2
+    0U,	// G_FLOG10
     0U,	// G_FNEG
     0U,	// G_FPEXT
     0U,	// G_FPTRUNC
@@ -640,15 +927,78 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_SITOFP
     0U,	// G_UITOFP
     0U,	// G_FABS
-    0U,	// G_GEP
-    0U,	// G_PTR_MASK
+    0U,	// G_FCOPYSIGN
+    0U,	// G_IS_FPCLASS
+    0U,	// G_FCANONICALIZE
+    0U,	// G_FMINNUM
+    0U,	// G_FMAXNUM
+    0U,	// G_FMINNUM_IEEE
+    0U,	// G_FMAXNUM_IEEE
+    0U,	// G_FMINIMUM
+    0U,	// G_FMAXIMUM
+    0U,	// G_PTR_ADD
+    0U,	// G_PTRMASK
+    0U,	// G_SMIN
+    0U,	// G_SMAX
+    0U,	// G_UMIN
+    0U,	// G_UMAX
+    0U,	// G_ABS
+    0U,	// G_LROUND
+    0U,	// G_LLROUND
     0U,	// G_BR
+    0U,	// G_BRJT
     0U,	// G_INSERT_VECTOR_ELT
     0U,	// G_EXTRACT_VECTOR_ELT
     0U,	// G_SHUFFLE_VECTOR
+    0U,	// G_CTTZ
+    0U,	// G_CTTZ_ZERO_UNDEF
+    0U,	// G_CTLZ
+    0U,	// G_CTLZ_ZERO_UNDEF
+    0U,	// G_CTPOP
     0U,	// G_BSWAP
+    0U,	// G_BITREVERSE
+    0U,	// G_FCEIL
+    0U,	// G_FCOS
+    0U,	// G_FSIN
+    0U,	// G_FSQRT
+    0U,	// G_FFLOOR
+    0U,	// G_FRINT
+    0U,	// G_FNEARBYINT
     0U,	// G_ADDRSPACE_CAST
     0U,	// G_BLOCK_ADDR
+    0U,	// G_JUMP_TABLE
+    0U,	// G_DYN_STACKALLOC
+    0U,	// G_STRICT_FADD
+    0U,	// G_STRICT_FSUB
+    0U,	// G_STRICT_FMUL
+    0U,	// G_STRICT_FDIV
+    0U,	// G_STRICT_FREM
+    0U,	// G_STRICT_FMA
+    0U,	// G_STRICT_FSQRT
+    0U,	// G_READ_REGISTER
+    0U,	// G_WRITE_REGISTER
+    0U,	// G_MEMCPY
+    0U,	// G_MEMCPY_INLINE
+    0U,	// G_MEMMOVE
+    0U,	// G_MEMSET
+    0U,	// G_BZERO
+    0U,	// G_VECREDUCE_SEQ_FADD
+    0U,	// G_VECREDUCE_SEQ_FMUL
+    0U,	// G_VECREDUCE_FADD
+    0U,	// G_VECREDUCE_FMUL
+    0U,	// G_VECREDUCE_FMAX
+    0U,	// G_VECREDUCE_FMIN
+    0U,	// G_VECREDUCE_ADD
+    0U,	// G_VECREDUCE_MUL
+    0U,	// G_VECREDUCE_AND
+    0U,	// G_VECREDUCE_OR
+    0U,	// G_VECREDUCE_XOR
+    0U,	// G_VECREDUCE_SMAX
+    0U,	// G_VECREDUCE_SMIN
+    0U,	// G_VECREDUCE_UMAX
+    0U,	// G_VECREDUCE_UMIN
+    0U,	// G_SBFX
+    0U,	// G_UBFX
     0U,	// ABS
     0U,	// ADDSri
     0U,	// ADDSrr
@@ -656,11 +1006,14 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// ADDSrsr
     0U,	// ADJCALLSTACKDOWN
     0U,	// ADJCALLSTACKUP
-    7292U,	// ASRi
-    7292U,	// ASRr
+    12770U,	// ASRi
+    12770U,	// ASRr
     0U,	// B
     0U,	// BCCZi64
     0U,	// BCCi64
+    0U,	// BLX_noip
+    0U,	// BLX_pred_noip
+    0U,	// BL_PUSHLR
     0U,	// BMOVPCB_CALL
     0U,	// BMOVPCRX_CALL
     0U,	// BR_JTadd
@@ -674,8 +1027,7 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// CMP_SWAP_8
     0U,	// CONSTPOOL_ENTRY
     0U,	// COPY_STRUCT_BYVAL_I32
-    2001U,	// CompilerBarrier
-    16788832U,	// ITasm
+    67130072U,	// ITasm
     0U,	// Int_eh_sjlj_dispatchsetup
     0U,	// Int_eh_sjlj_longjmp
     0U,	// Int_eh_sjlj_setjmp
@@ -686,18 +1038,22 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// JUMPTABLE_TBB
     0U,	// JUMPTABLE_TBH
     0U,	// LDMIA_RET
-    15656U,	// LDRBT_POST
-    15443U,	// LDRConstPool
+    29344U,	// LDRBT_POST
+    29094U,	// LDRConstPool
+    29379U,	// LDRHTii
     0U,	// LDRLIT_ga_abs
     0U,	// LDRLIT_ga_pcrel
     0U,	// LDRLIT_ga_pcrel_ldr
-    15735U,	// LDRT_POST
+    29356U,	// LDRSBTii
+    29391U,	// LDRSHTii
+    29538U,	// LDRT_POST
     0U,	// LEApcrel
     0U,	// LEApcrelJT
-    7013U,	// LSLi
-    7013U,	// LSLr
-    7299U,	// LSRi
-    7299U,	// LSRr
+    0U,	// LOADDUAL
+    12318U,	// LSLi
+    12318U,	// LSLr
+    12777U,	// LSRi
+    12777U,	// LSRr
     0U,	// MEMCPY
     0U,	// MLAv5
     0U,	// MOVCCi
@@ -714,7 +1070,14 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// MOVi32imm
     0U,	// MOVsra_flag
     0U,	// MOVsrl_flag
+    0U,	// MQPRCopy
+    0U,	// MQQPRLoad
+    0U,	// MQQPRStore
+    0U,	// MQQQQPRLoad
+    0U,	// MQQQQPRStore
     0U,	// MULv5
+    0U,	// MVE_MEMCPYLOOPINST
+    0U,	// MVE_MEMSETLOOPINST
     0U,	// MVNCCi
     0U,	// PICADD
     0U,	// PICLDR
@@ -725,21 +1088,33 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// PICSTR
     0U,	// PICSTRB
     0U,	// PICSTRH
-    7278U,	// RORi
-    7278U,	// RORr
+    12756U,	// RORi
+    12756U,	// RORr
     0U,	// RRX
-    20136U,	// RRXi
+    38310U,	// RRXi
     0U,	// RSBSri
     0U,	// RSBSrsi
     0U,	// RSBSrsr
+    0U,	// SEH_EpilogEnd
+    0U,	// SEH_EpilogStart
+    0U,	// SEH_Nop
+    0U,	// SEH_Nop_Ret
+    0U,	// SEH_PrologEnd
+    0U,	// SEH_SaveFRegs
+    0U,	// SEH_SaveLR
+    0U,	// SEH_SaveRegs
+    0U,	// SEH_SaveRegs_Ret
+    0U,	// SEH_SaveSP
+    0U,	// SEH_StackAlloc
     0U,	// SMLALv5
     0U,	// SMULLv5
     0U,	// SPACE
-    15662U,	// STRBT_POST
+    0U,	// STOREDUAL
+    29350U,	// STRBT_POST
     0U,	// STRBi_preidx
     0U,	// STRBr_preidx
     0U,	// STRH_preidx
-    15746U,	// STRT_POST
+    29549U,	// STRT_POST
     0U,	// STRi_preidx
     0U,	// STRr_preidx
     0U,	// SUBS_PC_LR
@@ -747,6 +1122,8 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// SUBSrr
     0U,	// SUBSrsi
     0U,	// SUBSrsr
+    0U,	// SpeculationBarrierISBDSBEndBB
+    0U,	// SpeculationBarrierSBEndBB
     0U,	// TAILJMPd
     0U,	// TAILJMPr
     0U,	// TAILJMPr4
@@ -755,243 +1132,254 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// TPsoft
     0U,	// UMLALv5
     0U,	// UMULLv5
-    153198U,	// VLD1LNdAsm_16
-    284270U,	// VLD1LNdAsm_32
-    415342U,	// VLD1LNdAsm_8
-    153198U,	// VLD1LNdWB_fixed_Asm_16
-    284270U,	// VLD1LNdWB_fixed_Asm_32
-    415342U,	// VLD1LNdWB_fixed_Asm_8
-    157294U,	// VLD1LNdWB_register_Asm_16
-    288366U,	// VLD1LNdWB_register_Asm_32
-    419438U,	// VLD1LNdWB_register_Asm_8
-    153242U,	// VLD2LNdAsm_16
-    284314U,	// VLD2LNdAsm_32
-    415386U,	// VLD2LNdAsm_8
-    153242U,	// VLD2LNdWB_fixed_Asm_16
-    284314U,	// VLD2LNdWB_fixed_Asm_32
-    415386U,	// VLD2LNdWB_fixed_Asm_8
-    157338U,	// VLD2LNdWB_register_Asm_16
-    288410U,	// VLD2LNdWB_register_Asm_32
-    419482U,	// VLD2LNdWB_register_Asm_8
-    153242U,	// VLD2LNqAsm_16
-    284314U,	// VLD2LNqAsm_32
-    153242U,	// VLD2LNqWB_fixed_Asm_16
-    284314U,	// VLD2LNqWB_fixed_Asm_32
-    157338U,	// VLD2LNqWB_register_Asm_16
-    288410U,	// VLD2LNqWB_register_Asm_32
-    1107457722U,	// VLD3DUPdAsm_16
-    1107588794U,	// VLD3DUPdAsm_32
-    1107719866U,	// VLD3DUPdAsm_8
-    2181199546U,	// VLD3DUPdWB_fixed_Asm_16
-    2181330618U,	// VLD3DUPdWB_fixed_Asm_32
-    2181461690U,	// VLD3DUPdWB_fixed_Asm_8
-    33707706U,	// VLD3DUPdWB_register_Asm_16
-    33838778U,	// VLD3DUPdWB_register_Asm_32
-    33969850U,	// VLD3DUPdWB_register_Asm_8
-    1124234938U,	// VLD3DUPqAsm_16
-    1124366010U,	// VLD3DUPqAsm_32
-    1124497082U,	// VLD3DUPqAsm_8
-    2197976762U,	// VLD3DUPqWB_fixed_Asm_16
-    2198107834U,	// VLD3DUPqWB_fixed_Asm_32
-    2198238906U,	// VLD3DUPqWB_fixed_Asm_8
-    50484922U,	// VLD3DUPqWB_register_Asm_16
-    50615994U,	// VLD3DUPqWB_register_Asm_32
-    50747066U,	// VLD3DUPqWB_register_Asm_8
-    153274U,	// VLD3LNdAsm_16
-    284346U,	// VLD3LNdAsm_32
-    415418U,	// VLD3LNdAsm_8
-    153274U,	// VLD3LNdWB_fixed_Asm_16
-    284346U,	// VLD3LNdWB_fixed_Asm_32
-    415418U,	// VLD3LNdWB_fixed_Asm_8
-    157370U,	// VLD3LNdWB_register_Asm_16
-    288442U,	// VLD3LNdWB_register_Asm_32
-    419514U,	// VLD3LNdWB_register_Asm_8
-    153274U,	// VLD3LNqAsm_16
-    284346U,	// VLD3LNqAsm_32
-    153274U,	// VLD3LNqWB_fixed_Asm_16
-    284346U,	// VLD3LNqWB_fixed_Asm_32
-    157370U,	// VLD3LNqWB_register_Asm_16
-    288442U,	// VLD3LNqWB_register_Asm_32
-    3288495802U,	// VLD3dAsm_16
-    3288626874U,	// VLD3dAsm_32
-    3288757946U,	// VLD3dAsm_8
-    3288495802U,	// VLD3dWB_fixed_Asm_16
-    3288626874U,	// VLD3dWB_fixed_Asm_32
-    3288757946U,	// VLD3dWB_fixed_Asm_8
-    3288487610U,	// VLD3dWB_register_Asm_16
-    3288618682U,	// VLD3dWB_register_Asm_32
-    3288749754U,	// VLD3dWB_register_Asm_8
-    1157789370U,	// VLD3qAsm_16
-    1157920442U,	// VLD3qAsm_32
-    1158051514U,	// VLD3qAsm_8
-    2231531194U,	// VLD3qWB_fixed_Asm_16
-    2231662266U,	// VLD3qWB_fixed_Asm_32
-    2231793338U,	// VLD3qWB_fixed_Asm_8
-    84039354U,	// VLD3qWB_register_Asm_16
-    84170426U,	// VLD3qWB_register_Asm_32
-    84301498U,	// VLD3qWB_register_Asm_8
-    1174566609U,	// VLD4DUPdAsm_16
-    1174697681U,	// VLD4DUPdAsm_32
-    1174828753U,	// VLD4DUPdAsm_8
-    2248308433U,	// VLD4DUPdWB_fixed_Asm_16
-    2248439505U,	// VLD4DUPdWB_fixed_Asm_32
-    2248570577U,	// VLD4DUPdWB_fixed_Asm_8
-    100816593U,	// VLD4DUPdWB_register_Asm_16
-    100947665U,	// VLD4DUPdWB_register_Asm_32
-    101078737U,	// VLD4DUPdWB_register_Asm_8
-    1191343825U,	// VLD4DUPqAsm_16
-    1191474897U,	// VLD4DUPqAsm_32
-    1191605969U,	// VLD4DUPqAsm_8
-    2265085649U,	// VLD4DUPqWB_fixed_Asm_16
-    2265216721U,	// VLD4DUPqWB_fixed_Asm_32
-    2265347793U,	// VLD4DUPqWB_fixed_Asm_8
-    117593809U,	// VLD4DUPqWB_register_Asm_16
-    117724881U,	// VLD4DUPqWB_register_Asm_32
-    117855953U,	// VLD4DUPqWB_register_Asm_8
-    153297U,	// VLD4LNdAsm_16
-    284369U,	// VLD4LNdAsm_32
-    415441U,	// VLD4LNdAsm_8
-    153297U,	// VLD4LNdWB_fixed_Asm_16
-    284369U,	// VLD4LNdWB_fixed_Asm_32
-    415441U,	// VLD4LNdWB_fixed_Asm_8
-    157393U,	// VLD4LNdWB_register_Asm_16
-    288465U,	// VLD4LNdWB_register_Asm_32
-    419537U,	// VLD4LNdWB_register_Asm_8
-    153297U,	// VLD4LNqAsm_16
-    284369U,	// VLD4LNqAsm_32
-    153297U,	// VLD4LNqWB_fixed_Asm_16
-    284369U,	// VLD4LNqWB_fixed_Asm_32
-    157393U,	// VLD4LNqWB_register_Asm_16
-    288465U,	// VLD4LNqWB_register_Asm_32
-    3355604689U,	// VLD4dAsm_16
-    3355735761U,	// VLD4dAsm_32
-    3355866833U,	// VLD4dAsm_8
-    3355604689U,	// VLD4dWB_fixed_Asm_16
-    3355735761U,	// VLD4dWB_fixed_Asm_32
-    3355866833U,	// VLD4dWB_fixed_Asm_8
-    3355596497U,	// VLD4dWB_register_Asm_16
-    3355727569U,	// VLD4dWB_register_Asm_32
-    3355858641U,	// VLD4dWB_register_Asm_8
-    1224898257U,	// VLD4qAsm_16
-    1225029329U,	// VLD4qAsm_32
-    1225160401U,	// VLD4qAsm_8
-    2298640081U,	// VLD4qWB_fixed_Asm_16
-    2298771153U,	// VLD4qWB_fixed_Asm_32
-    2298902225U,	// VLD4qWB_fixed_Asm_8
-    151148241U,	// VLD4qWB_register_Asm_16
-    151279313U,	// VLD4qWB_register_Asm_32
-    151410385U,	// VLD4qWB_register_Asm_8
+    567556U,	// VLD1LNdAsm_16
+    1091844U,	// VLD1LNdAsm_32
+    1616132U,	// VLD1LNdAsm_8
+    567556U,	// VLD1LNdWB_fixed_Asm_16
+    1091844U,	// VLD1LNdWB_fixed_Asm_32
+    1616132U,	// VLD1LNdWB_fixed_Asm_8
+    575748U,	// VLD1LNdWB_register_Asm_16
+    1100036U,	// VLD1LNdWB_register_Asm_32
+    1624324U,	// VLD1LNdWB_register_Asm_8
+    567605U,	// VLD2LNdAsm_16
+    1091893U,	// VLD2LNdAsm_32
+    1616181U,	// VLD2LNdAsm_8
+    567605U,	// VLD2LNdWB_fixed_Asm_16
+    1091893U,	// VLD2LNdWB_fixed_Asm_32
+    1616181U,	// VLD2LNdWB_fixed_Asm_8
+    575797U,	// VLD2LNdWB_register_Asm_16
+    1100085U,	// VLD2LNdWB_register_Asm_32
+    1624373U,	// VLD2LNdWB_register_Asm_8
+    567605U,	// VLD2LNqAsm_16
+    1091893U,	// VLD2LNqAsm_32
+    567605U,	// VLD2LNqWB_fixed_Asm_16
+    1091893U,	// VLD2LNqWB_fixed_Asm_32
+    575797U,	// VLD2LNqWB_register_Asm_16
+    1100085U,	// VLD2LNqWB_register_Asm_32
+    134801754U,	// VLD3DUPdAsm_16
+    135326042U,	// VLD3DUPdAsm_32
+    135850330U,	// VLD3DUPdAsm_8
+    134801754U,	// VLD3DUPdWB_fixed_Asm_16
+    135326042U,	// VLD3DUPdWB_fixed_Asm_32
+    135850330U,	// VLD3DUPdWB_fixed_Asm_8
+    134785370U,	// VLD3DUPdWB_register_Asm_16
+    135309658U,	// VLD3DUPdWB_register_Asm_32
+    135833946U,	// VLD3DUPdWB_register_Asm_8
+    201910618U,	// VLD3DUPqAsm_16
+    202434906U,	// VLD3DUPqAsm_32
+    202959194U,	// VLD3DUPqAsm_8
+    201910618U,	// VLD3DUPqWB_fixed_Asm_16
+    202434906U,	// VLD3DUPqWB_fixed_Asm_32
+    202959194U,	// VLD3DUPqWB_fixed_Asm_8
+    201894234U,	// VLD3DUPqWB_register_Asm_16
+    202418522U,	// VLD3DUPqWB_register_Asm_32
+    202942810U,	// VLD3DUPqWB_register_Asm_8
+    567642U,	// VLD3LNdAsm_16
+    1091930U,	// VLD3LNdAsm_32
+    1616218U,	// VLD3LNdAsm_8
+    567642U,	// VLD3LNdWB_fixed_Asm_16
+    1091930U,	// VLD3LNdWB_fixed_Asm_32
+    1616218U,	// VLD3LNdWB_fixed_Asm_8
+    575834U,	// VLD3LNdWB_register_Asm_16
+    1100122U,	// VLD3LNdWB_register_Asm_32
+    1624410U,	// VLD3LNdWB_register_Asm_8
+    567642U,	// VLD3LNqAsm_16
+    1091930U,	// VLD3LNqAsm_32
+    567642U,	// VLD3LNqWB_fixed_Asm_16
+    1091930U,	// VLD3LNqWB_fixed_Asm_32
+    575834U,	// VLD3LNqWB_register_Asm_16
+    1100122U,	// VLD3LNqWB_register_Asm_32
+    269019482U,	// VLD3dAsm_16
+    269543770U,	// VLD3dAsm_32
+    270068058U,	// VLD3dAsm_8
+    269019482U,	// VLD3dWB_fixed_Asm_16
+    269543770U,	// VLD3dWB_fixed_Asm_32
+    270068058U,	// VLD3dWB_fixed_Asm_8
+    269003098U,	// VLD3dWB_register_Asm_16
+    269527386U,	// VLD3dWB_register_Asm_32
+    270051674U,	// VLD3dWB_register_Asm_8
+    336128346U,	// VLD3qAsm_16
+    336652634U,	// VLD3qAsm_32
+    337176922U,	// VLD3qAsm_8
+    336128346U,	// VLD3qWB_fixed_Asm_16
+    336652634U,	// VLD3qWB_fixed_Asm_32
+    337176922U,	// VLD3qWB_fixed_Asm_8
+    336111962U,	// VLD3qWB_register_Asm_16
+    336636250U,	// VLD3qWB_register_Asm_32
+    337160538U,	// VLD3qWB_register_Asm_8
+    403237238U,	// VLD4DUPdAsm_16
+    403761526U,	// VLD4DUPdAsm_32
+    404285814U,	// VLD4DUPdAsm_8
+    403237238U,	// VLD4DUPdWB_fixed_Asm_16
+    403761526U,	// VLD4DUPdWB_fixed_Asm_32
+    404285814U,	// VLD4DUPdWB_fixed_Asm_8
+    403220854U,	// VLD4DUPdWB_register_Asm_16
+    403745142U,	// VLD4DUPdWB_register_Asm_32
+    404269430U,	// VLD4DUPdWB_register_Asm_8
+    470346102U,	// VLD4DUPqAsm_16
+    470870390U,	// VLD4DUPqAsm_32
+    471394678U,	// VLD4DUPqAsm_8
+    470346102U,	// VLD4DUPqWB_fixed_Asm_16
+    470870390U,	// VLD4DUPqWB_fixed_Asm_32
+    471394678U,	// VLD4DUPqWB_fixed_Asm_8
+    470329718U,	// VLD4DUPqWB_register_Asm_16
+    470854006U,	// VLD4DUPqWB_register_Asm_32
+    471378294U,	// VLD4DUPqWB_register_Asm_8
+    567670U,	// VLD4LNdAsm_16
+    1091958U,	// VLD4LNdAsm_32
+    1616246U,	// VLD4LNdAsm_8
+    567670U,	// VLD4LNdWB_fixed_Asm_16
+    1091958U,	// VLD4LNdWB_fixed_Asm_32
+    1616246U,	// VLD4LNdWB_fixed_Asm_8
+    575862U,	// VLD4LNdWB_register_Asm_16
+    1100150U,	// VLD4LNdWB_register_Asm_32
+    1624438U,	// VLD4LNdWB_register_Asm_8
+    567670U,	// VLD4LNqAsm_16
+    1091958U,	// VLD4LNqAsm_32
+    567670U,	// VLD4LNqWB_fixed_Asm_16
+    1091958U,	// VLD4LNqWB_fixed_Asm_32
+    575862U,	// VLD4LNqWB_register_Asm_16
+    1100150U,	// VLD4LNqWB_register_Asm_32
+    537454966U,	// VLD4dAsm_16
+    537979254U,	// VLD4dAsm_32
+    538503542U,	// VLD4dAsm_8
+    537454966U,	// VLD4dWB_fixed_Asm_16
+    537979254U,	// VLD4dWB_fixed_Asm_32
+    538503542U,	// VLD4dWB_fixed_Asm_8
+    537438582U,	// VLD4dWB_register_Asm_16
+    537962870U,	// VLD4dWB_register_Asm_32
+    538487158U,	// VLD4dWB_register_Asm_8
+    604563830U,	// VLD4qAsm_16
+    605088118U,	// VLD4qAsm_32
+    605612406U,	// VLD4qAsm_8
+    604563830U,	// VLD4qWB_fixed_Asm_16
+    605088118U,	// VLD4qWB_fixed_Asm_32
+    605612406U,	// VLD4qWB_fixed_Asm_8
+    604547446U,	// VLD4qWB_register_Asm_16
+    605071734U,	// VLD4qWB_register_Asm_32
+    605596022U,	// VLD4qWB_register_Asm_8
     0U,	// VMOVD0
     0U,	// VMOVDcc
+    0U,	// VMOVHcc
     0U,	// VMOVQ0
     0U,	// VMOVScc
-    153209U,	// VST1LNdAsm_16
-    284281U,	// VST1LNdAsm_32
-    415353U,	// VST1LNdAsm_8
-    153209U,	// VST1LNdWB_fixed_Asm_16
-    284281U,	// VST1LNdWB_fixed_Asm_32
-    415353U,	// VST1LNdWB_fixed_Asm_8
-    157305U,	// VST1LNdWB_register_Asm_16
-    288377U,	// VST1LNdWB_register_Asm_32
-    419449U,	// VST1LNdWB_register_Asm_8
-    153269U,	// VST2LNdAsm_16
-    284341U,	// VST2LNdAsm_32
-    415413U,	// VST2LNdAsm_8
-    153269U,	// VST2LNdWB_fixed_Asm_16
-    284341U,	// VST2LNdWB_fixed_Asm_32
-    415413U,	// VST2LNdWB_fixed_Asm_8
-    157365U,	// VST2LNdWB_register_Asm_16
-    288437U,	// VST2LNdWB_register_Asm_32
-    419509U,	// VST2LNdWB_register_Asm_8
-    153269U,	// VST2LNqAsm_16
-    284341U,	// VST2LNqAsm_32
-    153269U,	// VST2LNqWB_fixed_Asm_16
-    284341U,	// VST2LNqWB_fixed_Asm_32
-    157365U,	// VST2LNqWB_register_Asm_16
-    288437U,	// VST2LNqWB_register_Asm_32
-    153285U,	// VST3LNdAsm_16
-    284357U,	// VST3LNdAsm_32
-    415429U,	// VST3LNdAsm_8
-    153285U,	// VST3LNdWB_fixed_Asm_16
-    284357U,	// VST3LNdWB_fixed_Asm_32
-    415429U,	// VST3LNdWB_fixed_Asm_8
-    157381U,	// VST3LNdWB_register_Asm_16
-    288453U,	// VST3LNdWB_register_Asm_32
-    419525U,	// VST3LNdWB_register_Asm_8
-    153285U,	// VST3LNqAsm_16
-    284357U,	// VST3LNqAsm_32
-    153285U,	// VST3LNqWB_fixed_Asm_16
-    284357U,	// VST3LNqWB_fixed_Asm_32
-    157381U,	// VST3LNqWB_register_Asm_16
-    288453U,	// VST3LNqWB_register_Asm_32
-    3288495813U,	// VST3dAsm_16
-    3288626885U,	// VST3dAsm_32
-    3288757957U,	// VST3dAsm_8
-    3288495813U,	// VST3dWB_fixed_Asm_16
-    3288626885U,	// VST3dWB_fixed_Asm_32
-    3288757957U,	// VST3dWB_fixed_Asm_8
-    3288487621U,	// VST3dWB_register_Asm_16
-    3288618693U,	// VST3dWB_register_Asm_32
-    3288749765U,	// VST3dWB_register_Asm_8
-    1157789381U,	// VST3qAsm_16
-    1157920453U,	// VST3qAsm_32
-    1158051525U,	// VST3qAsm_8
-    2231531205U,	// VST3qWB_fixed_Asm_16
-    2231662277U,	// VST3qWB_fixed_Asm_32
-    2231793349U,	// VST3qWB_fixed_Asm_8
-    84039365U,	// VST3qWB_register_Asm_16
-    84170437U,	// VST3qWB_register_Asm_32
-    84301509U,	// VST3qWB_register_Asm_8
-    153302U,	// VST4LNdAsm_16
-    284374U,	// VST4LNdAsm_32
-    415446U,	// VST4LNdAsm_8
-    153302U,	// VST4LNdWB_fixed_Asm_16
-    284374U,	// VST4LNdWB_fixed_Asm_32
-    415446U,	// VST4LNdWB_fixed_Asm_8
-    157398U,	// VST4LNdWB_register_Asm_16
-    288470U,	// VST4LNdWB_register_Asm_32
-    419542U,	// VST4LNdWB_register_Asm_8
-    153302U,	// VST4LNqAsm_16
-    284374U,	// VST4LNqAsm_32
-    153302U,	// VST4LNqWB_fixed_Asm_16
-    284374U,	// VST4LNqWB_fixed_Asm_32
-    157398U,	// VST4LNqWB_register_Asm_16
-    288470U,	// VST4LNqWB_register_Asm_32
-    3355604694U,	// VST4dAsm_16
-    3355735766U,	// VST4dAsm_32
-    3355866838U,	// VST4dAsm_8
-    3355604694U,	// VST4dWB_fixed_Asm_16
-    3355735766U,	// VST4dWB_fixed_Asm_32
-    3355866838U,	// VST4dWB_fixed_Asm_8
-    3355596502U,	// VST4dWB_register_Asm_16
-    3355727574U,	// VST4dWB_register_Asm_32
-    3355858646U,	// VST4dWB_register_Asm_8
-    1224898262U,	// VST4qAsm_16
-    1225029334U,	// VST4qAsm_32
-    1225160406U,	// VST4qAsm_8
-    2298640086U,	// VST4qWB_fixed_Asm_16
-    2298771158U,	// VST4qWB_fixed_Asm_32
-    2298902230U,	// VST4qWB_fixed_Asm_8
-    151148246U,	// VST4qWB_register_Asm_16
-    151279318U,	// VST4qWB_register_Asm_32
-    151410390U,	// VST4qWB_register_Asm_8
+    567567U,	// VST1LNdAsm_16
+    1091855U,	// VST1LNdAsm_32
+    1616143U,	// VST1LNdAsm_8
+    567567U,	// VST1LNdWB_fixed_Asm_16
+    1091855U,	// VST1LNdWB_fixed_Asm_32
+    1616143U,	// VST1LNdWB_fixed_Asm_8
+    575759U,	// VST1LNdWB_register_Asm_16
+    1100047U,	// VST1LNdWB_register_Asm_32
+    1624335U,	// VST1LNdWB_register_Asm_8
+    567632U,	// VST2LNdAsm_16
+    1091920U,	// VST2LNdAsm_32
+    1616208U,	// VST2LNdAsm_8
+    567632U,	// VST2LNdWB_fixed_Asm_16
+    1091920U,	// VST2LNdWB_fixed_Asm_32
+    1616208U,	// VST2LNdWB_fixed_Asm_8
+    575824U,	// VST2LNdWB_register_Asm_16
+    1100112U,	// VST2LNdWB_register_Asm_32
+    1624400U,	// VST2LNdWB_register_Asm_8
+    567632U,	// VST2LNqAsm_16
+    1091920U,	// VST2LNqAsm_32
+    567632U,	// VST2LNqWB_fixed_Asm_16
+    1091920U,	// VST2LNqWB_fixed_Asm_32
+    575824U,	// VST2LNqWB_register_Asm_16
+    1100112U,	// VST2LNqWB_register_Asm_32
+    567653U,	// VST3LNdAsm_16
+    1091941U,	// VST3LNdAsm_32
+    1616229U,	// VST3LNdAsm_8
+    567653U,	// VST3LNdWB_fixed_Asm_16
+    1091941U,	// VST3LNdWB_fixed_Asm_32
+    1616229U,	// VST3LNdWB_fixed_Asm_8
+    575845U,	// VST3LNdWB_register_Asm_16
+    1100133U,	// VST3LNdWB_register_Asm_32
+    1624421U,	// VST3LNdWB_register_Asm_8
+    567653U,	// VST3LNqAsm_16
+    1091941U,	// VST3LNqAsm_32
+    567653U,	// VST3LNqWB_fixed_Asm_16
+    1091941U,	// VST3LNqWB_fixed_Asm_32
+    575845U,	// VST3LNqWB_register_Asm_16
+    1100133U,	// VST3LNqWB_register_Asm_32
+    269019493U,	// VST3dAsm_16
+    269543781U,	// VST3dAsm_32
+    270068069U,	// VST3dAsm_8
+    269019493U,	// VST3dWB_fixed_Asm_16
+    269543781U,	// VST3dWB_fixed_Asm_32
+    270068069U,	// VST3dWB_fixed_Asm_8
+    269003109U,	// VST3dWB_register_Asm_16
+    269527397U,	// VST3dWB_register_Asm_32
+    270051685U,	// VST3dWB_register_Asm_8
+    336128357U,	// VST3qAsm_16
+    336652645U,	// VST3qAsm_32
+    337176933U,	// VST3qAsm_8
+    336128357U,	// VST3qWB_fixed_Asm_16
+    336652645U,	// VST3qWB_fixed_Asm_32
+    337176933U,	// VST3qWB_fixed_Asm_8
+    336111973U,	// VST3qWB_register_Asm_16
+    336636261U,	// VST3qWB_register_Asm_32
+    337160549U,	// VST3qWB_register_Asm_8
+    567675U,	// VST4LNdAsm_16
+    1091963U,	// VST4LNdAsm_32
+    1616251U,	// VST4LNdAsm_8
+    567675U,	// VST4LNdWB_fixed_Asm_16
+    1091963U,	// VST4LNdWB_fixed_Asm_32
+    1616251U,	// VST4LNdWB_fixed_Asm_8
+    575867U,	// VST4LNdWB_register_Asm_16
+    1100155U,	// VST4LNdWB_register_Asm_32
+    1624443U,	// VST4LNdWB_register_Asm_8
+    567675U,	// VST4LNqAsm_16
+    1091963U,	// VST4LNqAsm_32
+    567675U,	// VST4LNqWB_fixed_Asm_16
+    1091963U,	// VST4LNqWB_fixed_Asm_32
+    575867U,	// VST4LNqWB_register_Asm_16
+    1100155U,	// VST4LNqWB_register_Asm_32
+    537454971U,	// VST4dAsm_16
+    537979259U,	// VST4dAsm_32
+    538503547U,	// VST4dAsm_8
+    537454971U,	// VST4dWB_fixed_Asm_16
+    537979259U,	// VST4dWB_fixed_Asm_32
+    538503547U,	// VST4dWB_fixed_Asm_8
+    537438587U,	// VST4dWB_register_Asm_16
+    537962875U,	// VST4dWB_register_Asm_32
+    538487163U,	// VST4dWB_register_Asm_8
+    604563835U,	// VST4qAsm_16
+    605088123U,	// VST4qAsm_32
+    605612411U,	// VST4qAsm_8
+    604563835U,	// VST4qWB_fixed_Asm_16
+    605088123U,	// VST4qWB_fixed_Asm_32
+    605612411U,	// VST4qWB_fixed_Asm_8
+    604547451U,	// VST4qWB_register_Asm_16
+    605071739U,	// VST4qWB_register_Asm_32
+    605596027U,	// VST4qWB_register_Asm_8
     0U,	// WIN__CHKSTK
     0U,	// WIN__DBZCHK
     0U,	// t2ABS
     0U,	// t2ADDSri
     0U,	// t2ADDSrr
     0U,	// t2ADDSrs
+    0U,	// t2BF_LabelPseudo
     0U,	// t2BR_JT
+    0U,	// t2CALL_BTI
+    0U,	// t2DoLoopStart
+    0U,	// t2DoLoopStartTP
     0U,	// t2LDMIA_RET
-    14508U,	// t2LDRBpcrel
-    15443U,	// t2LDRConstPool
-    14929U,	// t2LDRHpcrel
-    14526U,	// t2LDRSBpcrel
-    14948U,	// t2LDRSHpcrel
+    27770U,	// t2LDRBpcrel
+    29094U,	// t2LDRConstPool
+    28288U,	// t2LDRHpcrel
+    0U,	// t2LDRLIT_ga_pcrel
+    27789U,	// t2LDRSBpcrel
+    28327U,	// t2LDRSHpcrel
+    673247654U,	// t2LDR_POST_imm
+    740356518U,	// t2LDR_PRE_imm
     0U,	// t2LDRpci_pic
-    15443U,	// t2LDRpcrel
+    29094U,	// t2LDRpcrel
     0U,	// t2LEApcrel
     0U,	// t2LEApcrelJT
+    0U,	// t2LoopDec
+    0U,	// t2LoopEnd
+    0U,	// t2LoopEndDec
     0U,	// t2MOVCCasr
     0U,	// t2MOVCCi
     0U,	// t2MOVCCi16
@@ -1000,25 +1388,33 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2MOVCClsr
     0U,	// t2MOVCCr
     0U,	// t2MOVCCror
-    31992U,	// t2MOVSsi
-    23800U,	// t2MOVSsr
+    62064U,	// t2MOVSsi
+    45680U,	// t2MOVSsr
     0U,	// t2MOVTi16_ga_pcrel
     0U,	// t2MOV_ga_pcrel
     0U,	// t2MOVi16_ga_pcrel
     0U,	// t2MOVi32imm
-    32234U,	// t2MOVsi
-    24042U,	// t2MOVsr
+    62539U,	// t2MOVsi
+    46155U,	// t2MOVsr
     0U,	// t2MVNCCi
     0U,	// t2RSBSri
     0U,	// t2RSBSrs
     0U,	// t2STRB_preidx
     0U,	// t2STRH_preidx
+    673247744U,	// t2STR_POST_imm
+    740356608U,	// t2STR_PRE_imm
     0U,	// t2STR_preidx
     0U,	// t2SUBSri
     0U,	// t2SUBSrr
     0U,	// t2SUBSrs
+    0U,	// t2SpeculationBarrierISBDSBEndBB
+    0U,	// t2SpeculationBarrierSBEndBB
     0U,	// t2TBB_JT
     0U,	// t2TBH_JT
+    0U,	// t2WhileLoopSetup
+    0U,	// t2WhileLoopStart
+    0U,	// t2WhileLoopStartLR
+    0U,	// t2WhileLoopStartTP
     0U,	// tADCS
     0U,	// tADDSi3
     0U,	// tADDSi8
@@ -1026,22 +1422,31 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// tADDframe
     0U,	// tADJCALLSTACKDOWN
     0U,	// tADJCALLSTACKUP
+    0U,	// tBLXNS_CALL
+    0U,	// tBLXr_noip
+    0U,	// tBL_PUSHLR
     0U,	// tBRIND
     0U,	// tBR_JTr
+    0U,	// tBXNS_RET
     0U,	// tBX_CALL
     0U,	// tBX_RET
     0U,	// tBX_RET_vararg
     0U,	// tBfar
+    0U,	// tCMP_SWAP_16
+    0U,	// tCMP_SWAP_32
+    0U,	// tCMP_SWAP_8
     0U,	// tLDMIA_UPD
-    15443U,	// tLDRConstPool
+    29094U,	// tLDRConstPool
     0U,	// tLDRLIT_ga_abs
     0U,	// tLDRLIT_ga_pcrel
     0U,	// tLDR_postidx
     0U,	// tLDRpci_pic
     0U,	// tLEApcrel
     0U,	// tLEApcrelJT
+    0U,	// tLSLSri
     0U,	// tMOVCCr_pseudo
     0U,	// tPOP_RET
+    0U,	// tRSBS
     0U,	// tSBCS
     0U,	// tSUBSi3
     0U,	// tSUBSi8
@@ -1052,2699 +1457,3729 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// tTBB_JT
     0U,	// tTBH_JT
     0U,	// tTPsoft
-    530745U,	// ADCri
-    530745U,	// ADCrr
-    559417U,	// ADCrsi
-    39225U,	// ADCrsr
-    530806U,	// ADDri
-    530806U,	// ADDrr
-    559478U,	// ADDrsi
-    39286U,	// ADDrsr
-    539726U,	// ADR
-    1242211449U,	// AESD
-    1242211457U,	// AESE
-    1258988646U,	// AESIMC
-    1258988656U,	// AESMC
-    530859U,	// ANDri
-    530859U,	// ANDrr
-    559531U,	// ANDrsi
-    39339U,	// ANDrsr
-    555329U,	// BFC
-    547483U,	// BFI
-    530758U,	// BICri
-    530758U,	// BICrr
-    559430U,	// BICrsi
-    39238U,	// BICrsr
-    828725U,	// BKPT
-    828697U,	// BL
-    828772U,	// BLX
-    1074314916U,	// BLX_pred
-    828772U,	// BLXi
-    1074313964U,	// BL_pred
-    828768U,	// BX
-    1074313901U,	// BXJ
-    970304U,	// BX_RET
-    1074314816U,	// BX_pred
-    1074313296U,	// Bcc
-    201907225U,	// CDP
-    219210157U,	// CDP2
-    3726U,	// CLREX
-    540368U,	// CLZ
-    539583U,	// CMNri
-    539583U,	// CMNzrr
-    555967U,	// CMNzrsi
-    547775U,	// CMNzrsr
-    539683U,	// CMPri
-    539683U,	// CMPrr
-    556067U,	// CMPrsi
-    547875U,	// CMPrsr
-    828709U,	// CPS1p
-    1309211869U,	// CPS2p
-    235470045U,	// CPS3p
-    185246891U,	// CRC32B
-    185246899U,	// CRC32CB
-    185246973U,	// CRC32CH
-    185247057U,	// CRC32CW
-    185246965U,	// CRC32H
-    185247049U,	// CRC32W
-    1074313739U,	// DBG
-    66762U,	// DMB
-    66767U,	// DSB
-    531562U,	// EORri
-    531562U,	// EORrr
-    560234U,	// EORrsi
-    40042U,	// EORrsr
-    838971U,	// ERET
-    1326595561U,	// FCONSTD
-    1326726633U,	// FCONSTH
-    1326857705U,	// FCONSTS
-    2332573243U,	// FLDMXDB_UPD
-    572932U,	// FLDMXIA
-    2332573188U,	// FLDMXIA_UPD
-    1625313U,	// FMSTAT
-    2332573251U,	// FSTMXDB_UPD
-    572940U,	// FSTMXIA
-    2332573196U,	// FSTMXIA_UPD
-    1074314610U,	// HINT
-    828720U,	// HLT
-    828638U,	// HVC
-    70868U,	// ISB
-    538616U,	// LDA
-    538701U,	// LDAB
-    540284U,	// LDAEX
-    538905U,	// LDAEXB
-    268974533U,	// LDAEXD
-    539263U,	// LDAEXH
-    539165U,	// LDAH
-    286975243U,	// LDC2L_OFFSET
-    3524977931U,	// LDC2L_OPTION
-    303752459U,	// LDC2L_POST
-    320529675U,	// LDC2L_PRE
-    286974356U,	// LDC2_OFFSET
-    3524977044U,	// LDC2_OPTION
-    303751572U,	// LDC2_POST
-    320528788U,	// LDC2_PRE
-    1275615989U,	// LDCL_OFFSET
-    1275615989U,	// LDCL_OPTION
-    1275615989U,	// LDCL_POST
-    1275615989U,	// LDCL_PRE
-    1275615549U,	// LDC_OFFSET
-    1275615549U,	// LDC_OPTION
-    1275615549U,	// LDC_POST
-    1275615549U,	// LDC_PRE
-    571388U,	// LDMDA
-    2332571644U,	// LDMDA_UPD
-    571519U,	// LDMDB
-    2332571775U,	// LDMDB_UPD
-    572300U,	// LDMIA
-    2332572556U,	// LDMIA_UPD
-    571538U,	// LDMIB
-    2332571794U,	// LDMIB_UPD
-    552232U,	// LDRBT_POST_IMM
-    552232U,	// LDRBT_POST_REG
-    551084U,	// LDRB_POST_IMM
-    551084U,	// LDRB_POST_REG
-    546988U,	// LDRB_PRE_IMM
-    551084U,	// LDRB_PRE_REG
-    555180U,	// LDRBi12
-    546988U,	// LDRBrs
-    551343U,	// LDRD
-    580015U,	// LDRD_POST
-    580015U,	// LDRD_PRE
-    540296U,	// LDREX
-    538919U,	// LDREXB
-    268974547U,	// LDREXD
-    539277U,	// LDREXH
-    547409U,	// LDRH
-    548171U,	// LDRHTi
-    552267U,	// LDRHTr
-    551505U,	// LDRH_POST
-    551505U,	// LDRH_PRE
-    547006U,	// LDRSB
-    548148U,	// LDRSBTi
-    552244U,	// LDRSBTr
-    551102U,	// LDRSB_POST
-    551102U,	// LDRSB_PRE
-    547428U,	// LDRSH
-    548183U,	// LDRSHTi
-    552279U,	// LDRSHTr
-    551524U,	// LDRSH_POST
-    551524U,	// LDRSH_PRE
-    552311U,	// LDRT_POST_IMM
-    552311U,	// LDRT_POST_REG
-    552019U,	// LDR_POST_IMM
-    552019U,	// LDR_POST_REG
-    547923U,	// LDR_PRE_IMM
-    552019U,	// LDR_PRE_REG
-    556115U,	// LDRcp
-    556115U,	// LDRi12
-    547923U,	// LDRrs
-    201907274U,	// MCR
-    168878515U,	// MCR2
-    201878642U,	// MCRR
-    168878521U,	// MCRR2
-    559140U,	// MLA
-    548021U,	// MLS
-    1887722U,	// MOVPCLR
-    556471U,	// MOVTi16
-    544234U,	// MOVi
-    540159U,	// MOVi16
-    544234U,	// MOVr
-    544234U,	// MOVr_TC
-    531946U,	// MOVsi
-    560618U,	// MOVsr
-    336124238U,	// MRC
-    74138U,	// MRC2
-    352872786U,	// MRRC
-    78240U,	// MRRC2
-    2148056290U,	// MRS
-    539874U,	// MRSbanked
-    3221798114U,	// MRSsys
-    369638536U,	// MSR
-    386415752U,	// MSRbanked
-    369638536U,	// MSRi
-    531317U,	// MUL
-    543747U,	// MVNi
-    543747U,	// MVNr
-    531459U,	// MVNsi
-    560131U,	// MVNsr
-    531576U,	// ORRri
-    531576U,	// ORRrr
-    560248U,	// ORRrsi
-    40056U,	// ORRrsr
-    548115U,	// PKHBT
-    547023U,	// PKHTB
-    83290U,	// PLDWi12
-    87386U,	// PLDWrs
-    83171U,	// PLDi12
-    87267U,	// PLDrs
-    83206U,	// PLIi12
-    87302U,	// PLIrs
-    555406U,	// QADD
-    554800U,	// QADD16
-    554903U,	// QADD8
-    556729U,	// QASX
-    555380U,	// QDADD
-    555252U,	// QDSUB
-    556588U,	// QSAX
-    555265U,	// QSUB
-    554762U,	// QSUB16
-    554864U,	// QSUB8
-    539998U,	// RBIT
-    540118U,	// REV
-    538452U,	// REV16
-    539247U,	// REVSH
-    828573U,	// RFEDA
-    2008221U,	// RFEDA_UPD
-    828604U,	// RFEDB
-    2008252U,	// RFEDB_UPD
-    828580U,	// RFEIA
-    2008228U,	// RFEIA_UPD
-    828611U,	// RFEIB
-    2008259U,	// RFEIB_UPD
-    530624U,	// RSBri
-    530624U,	// RSBrr
-    559296U,	// RSBrsi
-    39104U,	// RSBrsr
-    530775U,	// RSCri
-    530775U,	// RSCrr
-    559447U,	// RSCrsi
-    39255U,	// RSCrsr
-    554807U,	// SADD16
-    554909U,	// SADD8
-    556734U,	// SASX
-    530741U,	// SBCri
-    530741U,	// SBCrr
-    559413U,	// SBCrsi
-    39221U,	// SBCrsr
-    548506U,	// SBFX
-    556506U,	// SDIV
-    555794U,	// SEL
-    91368U,	// SETEND
-    828701U,	// SETPAN
-    168468546U,	// SHA1C
-    1258987596U,	// SHA1H
-    168468578U,	// SHA1M
-    168468588U,	// SHA1P
-    168468481U,	// SHA1SU0
-    1242210331U,	// SHA1SU1
-    168468566U,	// SHA256H
-    168468533U,	// SHA256H2
-    1242210317U,	// SHA256SU0
-    168468519U,	// SHA256SU1
-    554783U,	// SHADD16
-    554888U,	// SHADD8
-    556716U,	// SHASX
-    556575U,	// SHSAX
-    554745U,	// SHSUB16
-    554849U,	// SHSUB8
-    1074313546U,	// SMC
-    546910U,	// SMLABB
-    548108U,	// SMLABT
-    547171U,	// SMLAD
-    548432U,	// SMLADX
-    96984U,	// SMLAL
-    579685U,	// SMLALBB
-    580889U,	// SMLALBT
-    579992U,	// SMLALD
-    581214U,	// SMLALDX
-    579797U,	// SMLALTB
-    581011U,	// SMLALTT
-    547016U,	// SMLATB
-    548236U,	// SMLATT
-    547083U,	// SMLAWB
-    548284U,	// SMLAWT
-    547257U,	// SMLSD
-    548462U,	// SMLSDX
-    580003U,	// SMLSLD
-    581222U,	// SMLSLDX
-    546850U,	// SMMLA
-    547907U,	// SMMLAR
-    548019U,	// SMMLS
-    547968U,	// SMMLSR
-    555891U,	// SMMUL
-    556130U,	// SMMULR
-    555369U,	// SMUAD
-    556631U,	// SMUADX
-    555117U,	// SMULBB
-    556321U,	// SMULBT
-    559946U,	// SMULL
-    555229U,	// SMULTB
-    556443U,	// SMULTT
-    555282U,	// SMULWB
-    556483U,	// SMULWT
-    555455U,	// SMUSD
-    556661U,	// SMUSDX
-    828836U,	// SRSDA
-    828788U,	// SRSDA_UPD
-    828858U,	// SRSDB
-    828812U,	// SRSDB_UPD
-    828847U,	// SRSIA
-    828800U,	// SRSIA_UPD
-    828869U,	// SRSIB
-    828824U,	// SRSIB_UPD
-    548093U,	// SSAT
-    554821U,	// SSAT16
-    556593U,	// SSAX
-    554769U,	// SSUB16
-    554870U,	// SSUB8
-    286975250U,	// STC2L_OFFSET
-    3524977938U,	// STC2L_OPTION
-    303752466U,	// STC2L_POST
-    320529682U,	// STC2L_PRE
-    286974375U,	// STC2_OFFSET
-    3524977063U,	// STC2_OPTION
-    303751591U,	// STC2_POST
-    320528807U,	// STC2_PRE
-    1275615994U,	// STCL_OFFSET
-    1275615994U,	// STCL_OPTION
-    1275615994U,	// STCL_POST
-    1275615994U,	// STCL_PRE
-    1275615579U,	// STC_OFFSET
-    1275615579U,	// STC_OPTION
-    1275615579U,	// STC_POST
-    1275615579U,	// STC_PRE
-    539503U,	// STL
-    538782U,	// STLB
-    556674U,	// STLEX
-    555296U,	// STLEXB
-    555468U,	// STLEXD
-    555654U,	// STLEXH
-    539195U,	// STLH
-    571394U,	// STMDA
-    2332571650U,	// STMDA_UPD
-    571526U,	// STMDB
-    2332571782U,	// STMDB_UPD
-    572306U,	// STMIA
-    2332572562U,	// STMIA_UPD
-    571544U,	// STMIB
-    2332571800U,	// STMIB_UPD
-    185101614U,	// STRBT_POST_IMM
-    185101614U,	// STRBT_POST_REG
-    185100465U,	// STRB_POST_IMM
-    185100465U,	// STRB_POST_REG
-    185096369U,	// STRB_PRE_IMM
-    185100465U,	// STRB_PRE_REG
-    555185U,	// STRBi12
-    546993U,	// STRBrs
-    551348U,	// STRD
-    185129396U,	// STRD_POST
-    185129396U,	// STRD_PRE
-    556692U,	// STREX
-    555310U,	// STREXB
-    555482U,	// STREXD
-    555668U,	// STREXH
-    547414U,	// STRH
-    185097553U,	// STRHTi
-    185101649U,	// STRHTr
-    185100886U,	// STRH_POST
-    185100886U,	// STRH_PRE
-    185101698U,	// STRT_POST_IMM
-    185101698U,	// STRT_POST_REG
-    185101460U,	// STR_POST_IMM
-    185101460U,	// STR_POST_REG
-    185097364U,	// STR_PRE_IMM
-    185101460U,	// STR_PRE_REG
-    556180U,	// STRi12
-    547988U,	// STRrs
-    530678U,	// SUBri
-    530678U,	// SUBrr
-    559350U,	// SUBrsi
-    39158U,	// SUBrsr
-    1074313567U,	// SVC
-    556081U,	// SWP
-    555175U,	// SWPB
-    546898U,	// SXTAB
-    546523U,	// SXTAB16
-    547371U,	// SXTAH
-    555242U,	// SXTB
-    554731U,	// SXTB16
-    555637U,	// SXTH
-    539711U,	// TEQri
-    539711U,	// TEQrr
-    556095U,	// TEQrsi
-    547903U,	// TEQrsr
-    3092U,	// TRAP
-    3092U,	// TRAPNaCl
-    99545U,	// TSB
-    540040U,	// TSTri
-    540040U,	// TSTrr
-    556424U,	// TSTrsi
-    548232U,	// TSTrsr
-    554814U,	// UADD16
-    554915U,	// UADD8
-    556739U,	// UASX
-    548511U,	// UBFX
-    828656U,	// UDF
-    556511U,	// UDIV
-    554791U,	// UHADD16
-    554895U,	// UHADD8
-    556722U,	// UHASX
-    556581U,	// UHSAX
-    554753U,	// UHSUB16
-    554856U,	// UHSUB8
-    580285U,	// UMAAL
-    96990U,	// UMLAL
-    559952U,	// UMULL
-    554799U,	// UQADD16
-    554902U,	// UQADD8
-    556728U,	// UQASX
-    556587U,	// UQSAX
-    554761U,	// UQSUB16
-    554863U,	// UQSUB8
-    554882U,	// USAD8
-    546650U,	// USADA8
-    548098U,	// USAT
-    554828U,	// USAT16
-    556598U,	// USAX
-    554776U,	// USUB16
-    554876U,	// USUB8
-    546904U,	// UXTAB
-    546531U,	// UXTAB16
-    547377U,	// UXTAH
-    555247U,	// UXTB
-    554738U,	// UXTB16
-    555642U,	// UXTH
-    169892547U,	// VABALsv2i64
-    170023619U,	// VABALsv4i32
-    170154691U,	// VABALsv8i16
-    170285763U,	// VABALuv2i64
-    170416835U,	// VABALuv4i32
-    170547907U,	// VABALuv8i16
-    170153971U,	// VABAsv16i8
-    169891827U,	// VABAsv2i32
-    170022899U,	// VABAsv4i16
-    169891827U,	// VABAsv4i32
-    170022899U,	// VABAsv8i16
-    170153971U,	// VABAsv8i8
-    170547187U,	// VABAuv16i8
-    170285043U,	// VABAuv2i32
-    170416115U,	// VABAuv4i16
-    170285043U,	// VABAuv4i32
-    170416115U,	// VABAuv8i16
-    170547187U,	// VABAuv8i8
-    186678015U,	// VABDLsv2i64
-    186809087U,	// VABDLsv4i32
-    186940159U,	// VABDLsv8i16
-    187071231U,	// VABDLuv2i64
-    187202303U,	// VABDLuv4i32
-    187333375U,	// VABDLuv8i16
-    253131119U,	// VABDfd
-    253131119U,	// VABDfq
-    253000047U,	// VABDhd
-    253000047U,	// VABDhq
-    186939759U,	// VABDsv16i8
-    186677615U,	// VABDsv2i32
-    186808687U,	// VABDsv4i16
-    186677615U,	// VABDsv4i32
-    186808687U,	// VABDsv8i16
-    186939759U,	// VABDsv8i8
-    187332975U,	// VABDuv16i8
-    187070831U,	// VABDuv2i32
-    187201903U,	// VABDuv4i16
-    187070831U,	// VABDuv4i32
-    187201903U,	// VABDuv8i16
-    187332975U,	// VABDuv8i8
-    252853412U,	// VABSD
-    252984484U,	// VABSH
-    253115556U,	// VABSS
-    253115556U,	// VABSfd
-    253115556U,	// VABSfq
-    252984484U,	// VABShd
-    252984484U,	// VABShq
-    1260666020U,	// VABSv16i8
-    1260403876U,	// VABSv2i32
-    1260534948U,	// VABSv4i16
-    1260403876U,	// VABSv4i32
-    1260534948U,	// VABSv8i16
-    1260666020U,	// VABSv8i8
-    253131233U,	// VACGEfd
-    253131233U,	// VACGEfq
-    253000161U,	// VACGEhd
-    253000161U,	// VACGEhq
-    253132096U,	// VACGTfd
-    253132096U,	// VACGTfq
-    253001024U,	// VACGThd
-    253001024U,	// VACGThq
-    252869011U,	// VADDD
-    253000083U,	// VADDH
-    187464621U,	// VADDHNv2i32
-    187595693U,	// VADDHNv4i16
-    187726765U,	// VADDHNv8i8
-    186678028U,	// VADDLsv2i64
-    186809100U,	// VADDLsv4i32
-    186940172U,	// VADDLsv8i16
-    187071244U,	// VADDLuv2i64
-    187202316U,	// VADDLuv4i32
-    187333388U,	// VADDLuv8i16
-    253131155U,	// VADDS
-    186678772U,	// VADDWsv2i64
-    186809844U,	// VADDWsv4i32
-    186940916U,	// VADDWsv8i16
-    187071988U,	// VADDWuv2i64
-    187203060U,	// VADDWuv4i32
-    187334132U,	// VADDWuv8i16
-    253131155U,	// VADDfd
-    253131155U,	// VADDfq
-    253000083U,	// VADDhd
-    253000083U,	// VADDhq
-    187857299U,	// VADDv16i8
-    187464083U,	// VADDv1i64
-    187595155U,	// VADDv2i32
-    187464083U,	// VADDv2i64
-    187726227U,	// VADDv4i16
-    187595155U,	// VADDv4i32
-    187726227U,	// VADDv8i16
-    187857299U,	// VADDv8i8
-    555434U,	// VANDd
-    555434U,	// VANDq
-    555333U,	// VBICd
-    405698885U,	// VBICiv2i32
-    405829957U,	// VBICiv4i16
-    405698885U,	// VBICiv4i32
-    405829957U,	// VBICiv8i16
-    555333U,	// VBICq
-    547334U,	// VBIFd
-    547334U,	// VBIFq
-    548195U,	// VBITd
-    548195U,	// VBITq
-    547676U,	// VBSLd
-    547676U,	// VBSLq
-    185245957U,	// VCADDv2f32
-    185246658U,	// VCADDv4f16
-    185245957U,	// VCADDv4f32
-    185246658U,	// VCADDv8f16
-    253131834U,	// VCEQfd
-    253131834U,	// VCEQfq
-    253000762U,	// VCEQhd
-    253000762U,	// VCEQhq
-    187857978U,	// VCEQv16i8
-    187595834U,	// VCEQv2i32
-    187726906U,	// VCEQv4i16
-    187595834U,	// VCEQv4i32
-    187726906U,	// VCEQv8i16
-    187857978U,	// VCEQv8i8
-    1261583418U,	// VCEQzv16i8
-    253115450U,	// VCEQzv2f32
-    1261321274U,	// VCEQzv2i32
-    252984378U,	// VCEQzv4f16
-    253115450U,	// VCEQzv4f32
-    1261452346U,	// VCEQzv4i16
-    1261321274U,	// VCEQzv4i32
-    252984378U,	// VCEQzv8f16
-    1261452346U,	// VCEQzv8i16
-    1261583418U,	// VCEQzv8i8
-    253131239U,	// VCGEfd
-    253131239U,	// VCGEfq
-    253000167U,	// VCGEhd
-    253000167U,	// VCGEhq
-    186939879U,	// VCGEsv16i8
-    186677735U,	// VCGEsv2i32
-    186808807U,	// VCGEsv4i16
-    186677735U,	// VCGEsv4i32
-    186808807U,	// VCGEsv8i16
-    186939879U,	// VCGEsv8i8
-    187333095U,	// VCGEuv16i8
-    187070951U,	// VCGEuv2i32
-    187202023U,	// VCGEuv4i16
-    187070951U,	// VCGEuv4i32
-    187202023U,	// VCGEuv8i16
-    187333095U,	// VCGEuv8i8
-    1260665319U,	// VCGEzv16i8
-    253114855U,	// VCGEzv2f32
-    1260403175U,	// VCGEzv2i32
-    252983783U,	// VCGEzv4f16
-    253114855U,	// VCGEzv4f32
-    1260534247U,	// VCGEzv4i16
-    1260403175U,	// VCGEzv4i32
-    252983783U,	// VCGEzv8f16
-    1260534247U,	// VCGEzv8i16
-    1260665319U,	// VCGEzv8i8
-    253132102U,	// VCGTfd
-    253132102U,	// VCGTfq
-    253001030U,	// VCGThd
-    253001030U,	// VCGThq
-    186940742U,	// VCGTsv16i8
-    186678598U,	// VCGTsv2i32
-    186809670U,	// VCGTsv4i16
-    186678598U,	// VCGTsv4i32
-    186809670U,	// VCGTsv8i16
-    186940742U,	// VCGTsv8i8
-    187333958U,	// VCGTuv16i8
-    187071814U,	// VCGTuv2i32
-    187202886U,	// VCGTuv4i16
-    187071814U,	// VCGTuv4i32
-    187202886U,	// VCGTuv8i16
-    187333958U,	// VCGTuv8i8
-    1260666182U,	// VCGTzv16i8
-    253115718U,	// VCGTzv2f32
-    1260404038U,	// VCGTzv2i32
-    252984646U,	// VCGTzv4f16
-    253115718U,	// VCGTzv4f32
-    1260535110U,	// VCGTzv4i16
-    1260404038U,	// VCGTzv4i32
-    252984646U,	// VCGTzv8f16
-    1260535110U,	// VCGTzv8i16
-    1260666182U,	// VCGTzv8i8
-    1260665324U,	// VCLEzv16i8
-    253114860U,	// VCLEzv2f32
-    1260403180U,	// VCLEzv2i32
-    252983788U,	// VCLEzv4f16
-    253114860U,	// VCLEzv4f32
-    1260534252U,	// VCLEzv4i16
-    1260403180U,	// VCLEzv4i32
-    252983788U,	// VCLEzv8f16
-    1260534252U,	// VCLEzv8i16
-    1260665324U,	// VCLEzv8i8
-    1260666030U,	// VCLSv16i8
-    1260403886U,	// VCLSv2i32
-    1260534958U,	// VCLSv4i16
-    1260403886U,	// VCLSv4i32
-    1260534958U,	// VCLSv8i16
-    1260666030U,	// VCLSv8i8
-    1260666216U,	// VCLTzv16i8
-    253115752U,	// VCLTzv2f32
-    1260404072U,	// VCLTzv2i32
-    252984680U,	// VCLTzv4f16
-    253115752U,	// VCLTzv4f32
-    1260535144U,	// VCLTzv4i16
-    1260404072U,	// VCLTzv4i32
-    252984680U,	// VCLTzv8f16
-    1260535144U,	// VCLTzv8i16
-    1260666216U,	// VCLTzv8i8
-    1261584079U,	// VCLZv16i8
-    1261321935U,	// VCLZv2i32
-    1261453007U,	// VCLZv4i16
-    1261321935U,	// VCLZv4i32
-    1261453007U,	// VCLZv8i16
-    1261584079U,	// VCLZv8i8
-    168468718U,	// VCMLAv2f32
-    168468718U,	// VCMLAv2f32_indexed
-    168469419U,	// VCMLAv4f16
-    168469419U,	// VCMLAv4f16_indexed
-    168468718U,	// VCMLAv4f32
-    168468718U,	// VCMLAv4f32_indexed
-    168469419U,	// VCMLAv8f16
-    168469419U,	// VCMLAv8f16_indexed
-    252853282U,	// VCMPD
-    252852728U,	// VCMPED
-    252983800U,	// VCMPEH
-    253114872U,	// VCMPES
-    420657656U,	// VCMPEZD
-    420788728U,	// VCMPEZH
-    420919800U,	// VCMPEZS
-    252984354U,	// VCMPH
-    253115426U,	// VCMPS
-    420658210U,	// VCMPZD
-    420789282U,	// VCMPZH
-    420920354U,	// VCMPZS
-    408941U,	// VCNTd
-    408941U,	// VCNTq
-    1258987638U,	// VCVTANSDf
-    1258988339U,	// VCVTANSDh
-    1258987638U,	// VCVTANSQf
-    1258988339U,	// VCVTANSQh
-    1258987698U,	// VCVTANUDf
-    1258988399U,	// VCVTANUDh
-    1258987698U,	// VCVTANUQf
-    1258988399U,	// VCVTANUQh
-    1258987968U,	// VCVTASD
-    1258988219U,	// VCVTASH
-    1258987638U,	// VCVTASS
-    1258988028U,	// VCVTAUD
-    1258988279U,	// VCVTAUH
-    1258987698U,	// VCVTAUS
-    3422436U,	// VCVTBDH
-    3553508U,	// VCVTBHD
-    3684580U,	// VCVTBHS
-    3815652U,	// VCVTBSH
-    3947954U,	// VCVTDS
-    1258987653U,	// VCVTMNSDf
-    1258988354U,	// VCVTMNSDh
-    1258987653U,	// VCVTMNSQf
-    1258988354U,	// VCVTMNSQh
-    1258987713U,	// VCVTMNUDf
-    1258988414U,	// VCVTMNUDh
-    1258987713U,	// VCVTMNUQf
-    1258988414U,	// VCVTMNUQh
-    1258987983U,	// VCVTMSD
-    1258988234U,	// VCVTMSH
-    1258987653U,	// VCVTMSS
-    1258988043U,	// VCVTMUD
-    1258988294U,	// VCVTMUH
-    1258987713U,	// VCVTMUS
-    1258987668U,	// VCVTNNSDf
-    1258988369U,	// VCVTNNSDh
-    1258987668U,	// VCVTNNSQf
-    1258988369U,	// VCVTNNSQh
-    1258987728U,	// VCVTNNUDf
-    1258988429U,	// VCVTNNUDh
-    1258987728U,	// VCVTNNUQf
-    1258988429U,	// VCVTNNUQh
-    1258987998U,	// VCVTNSD
-    1258988249U,	// VCVTNSH
-    1258987668U,	// VCVTNSS
-    1258988058U,	// VCVTNUD
-    1258988309U,	// VCVTNUH
-    1258987728U,	// VCVTNUS
-    1258987683U,	// VCVTPNSDf
-    1258988384U,	// VCVTPNSDh
-    1258987683U,	// VCVTPNSQf
-    1258988384U,	// VCVTPNSQh
-    1258987743U,	// VCVTPNUDf
-    1258988444U,	// VCVTPNUDh
-    1258987743U,	// VCVTPNUQf
-    1258988444U,	// VCVTPNUQh
-    1258988013U,	// VCVTPSD
-    1258988264U,	// VCVTPSH
-    1258987683U,	// VCVTPSS
-    1258988073U,	// VCVTPUD
-    1258988324U,	// VCVTPUH
-    1258987743U,	// VCVTPUS
-    4079026U,	// VCVTSD
-    3423654U,	// VCVTTDH
-    3554726U,	// VCVTTHD
-    3685798U,	// VCVTTHS
-    3816870U,	// VCVTTSH
-    3816882U,	// VCVTf2h
-    440417714U,	// VCVTf2sd
-    440417714U,	// VCVTf2sq
-    440548786U,	// VCVTf2ud
-    440548786U,	// VCVTf2uq
-    2403368370U,	// VCVTf2xsd
-    2403368370U,	// VCVTf2xsq
-    2403499442U,	// VCVTf2xud
-    2403499442U,	// VCVTf2xuq
-    3685810U,	// VCVTh2f
-    440679858U,	// VCVTh2sd
-    440679858U,	// VCVTh2sq
-    440810930U,	// VCVTh2ud
-    440810930U,	// VCVTh2uq
-    2403630514U,	// VCVTh2xsd
-    2403630514U,	// VCVTh2xsq
-    2403761586U,	// VCVTh2xud
-    2403761586U,	// VCVTh2xuq
-    440942002U,	// VCVTs2fd
-    440942002U,	// VCVTs2fq
-    441073074U,	// VCVTs2hd
-    441073074U,	// VCVTs2hq
-    441204146U,	// VCVTu2fd
-    441204146U,	// VCVTu2fq
-    441335218U,	// VCVTu2hd
-    441335218U,	// VCVTu2hq
-    2403892658U,	// VCVTxs2fd
-    2403892658U,	// VCVTxs2fq
-    2404023730U,	// VCVTxs2hd
-    2404023730U,	// VCVTxs2hq
-    2404154802U,	// VCVTxu2fd
-    2404154802U,	// VCVTxu2fq
-    2404285874U,	// VCVTxu2hd
-    2404285874U,	// VCVTxu2hq
-    252870116U,	// VDIVD
-    253001188U,	// VDIVH
-    253132260U,	// VDIVS
-    146475U,	// VDUP16d
-    146475U,	// VDUP16q
-    277547U,	// VDUP32d
-    277547U,	// VDUP32q
-    408619U,	// VDUP8d
-    408619U,	// VDUP8q
-    162859U,	// VDUPLN16d
-    162859U,	// VDUPLN16q
-    293931U,	// VDUPLN32d
-    293931U,	// VDUPLN32q
-    425003U,	// VDUPLN8d
-    425003U,	// VDUPLN8q
-    556137U,	// VEORd
-    556137U,	// VEORq
-    155082U,	// VEXTd16
-    286154U,	// VEXTd32
-    417226U,	// VEXTd8
-    155082U,	// VEXTq16
-    286154U,	// VEXTq32
-    5266890U,	// VEXTq64
-    417226U,	// VEXTq8
-    2400344115U,	// VFMAD
-    2400475187U,	// VFMAH
-    2400606259U,	// VFMAS
-    2400606259U,	// VFMAfd
-    2400606259U,	// VFMAfq
-    2400475187U,	// VFMAhd
-    2400475187U,	// VFMAhq
-    2400345284U,	// VFMSD
-    2400476356U,	// VFMSH
-    2400607428U,	// VFMSS
-    2400607428U,	// VFMSfd
-    2400607428U,	// VFMSfq
-    2400476356U,	// VFMShd
-    2400476356U,	// VFMShq
-    2400344120U,	// VFNMAD
-    2400475192U,	// VFNMAH
-    2400606264U,	// VFNMAS
-    2400345289U,	// VFNMSD
-    2400476361U,	// VFNMSH
-    2400607433U,	// VFNMSS
-    294377U,	// VGETLNi32
-    3408035305U,	// VGETLNs16
-    3408166377U,	// VGETLNs8
-    3408428521U,	// VGETLNu16
-    3408559593U,	// VGETLNu8
-    186939777U,	// VHADDsv16i8
-    186677633U,	// VHADDsv2i32
-    186808705U,	// VHADDsv4i16
-    186677633U,	// VHADDsv4i32
-    186808705U,	// VHADDsv8i16
-    186939777U,	// VHADDsv8i8
-    187332993U,	// VHADDuv16i8
-    187070849U,	// VHADDuv2i32
-    187201921U,	// VHADDuv4i16
-    187070849U,	// VHADDuv4i32
-    187201921U,	// VHADDuv8i16
-    187332993U,	// VHADDuv8i8
-    186939642U,	// VHSUBsv16i8
-    186677498U,	// VHSUBsv2i32
-    186808570U,	// VHSUBsv4i16
-    186677498U,	// VHSUBsv4i32
-    186808570U,	// VHSUBsv8i16
-    186939642U,	// VHSUBsv8i8
-    187332858U,	// VHSUBuv16i8
-    187070714U,	// VHSUBuv2i32
-    187201786U,	// VHSUBuv4i16
-    187070714U,	// VHSUBuv4i32
-    187201786U,	// VHSUBuv8i16
-    187332858U,	// VHSUBuv8i8
-    1258988577U,	// VINSH
-    441597356U,	// VJCVT
-    3674371694U,	// VLD1DUPd16
-    453138030U,	// VLD1DUPd16wb_fixed
-    453142126U,	// VLD1DUPd16wb_register
-    3674502766U,	// VLD1DUPd32
-    453269102U,	// VLD1DUPd32wb_fixed
-    453273198U,	// VLD1DUPd32wb_register
-    3674633838U,	// VLD1DUPd8
-    453400174U,	// VLD1DUPd8wb_fixed
-    453404270U,	// VLD1DUPd8wb_register
-    3691148910U,	// VLD1DUPq16
-    469915246U,	// VLD1DUPq16wb_fixed
-    469919342U,	// VLD1DUPq16wb_register
-    3691279982U,	// VLD1DUPq32
-    470046318U,	// VLD1DUPq32wb_fixed
-    470050414U,	// VLD1DUPq32wb_register
-    3691411054U,	// VLD1DUPq8
-    470177390U,	// VLD1DUPq8wb_fixed
-    470181486U,	// VLD1DUPq8wb_register
-    1079273070U,	// VLD1LNd16
-    1079350894U,	// VLD1LNd16_UPD
-    1079404142U,	// VLD1LNd32
-    1079481966U,	// VLD1LNd32_UPD
-    1079535214U,	// VLD1LNd8
-    1079613038U,	// VLD1LNd8_UPD
+    2632970U,	// ADCri
+    2632970U,	// ADCrr
+    2690314U,	// ADCrsi
+    77066U,	// ADCrsr
+    2633038U,	// ADDri
+    2633038U,	// ADDrr
+    2690382U,	// ADDrsi
+    77134U,	// ADDrsr
+    2650529U,	// ADR
+    808535656U,	// AESD
+    808535664U,	// AESE
+    875644501U,	// AESIMC
+    875644511U,	// AESMC
+    2633103U,	// ANDri
+    2633103U,	// ANDrr
+    2690447U,	// ANDrsi
+    77199U,	// ANDrsr
+    808543710U,	// BF16VDOTI_VDOTD
+    808543710U,	// BF16VDOTI_VDOTQ
+    808543710U,	// BF16VDOTS_VDOTD
+    808543710U,	// BF16VDOTS_VDOTQ
+    876114856U,	// BF16_VCVT
+    809036979U,	// BF16_VCVTB
+    809038742U,	// BF16_VCVTT
+    2682130U,	// BFC
+    2666240U,	// BFI
+    2632983U,	// BICri
+    2632983U,	// BICrr
+    2690327U,	// BICrsi
+    77079U,	// BICrsr
+    4278212U,	// BKPT
+    4294544U,	// BL
+    4278266U,	// BLX
+    2733469U,	// BLX_pred
+    4294650U,	// BLXi
+    942255953U,	// BL_pred
+    4278262U,	// BX
+    2731794U,	// BXJ
+    4838647U,	// BX_RET
+    2733303U,	// BX_pred
+    942255028U,	// Bcc
+    810672130U,	// CDE_CX1
+    1009298104U,	// CDE_CX1A
+    1079633720U,	// CDE_CX1D
+    1009298126U,	// CDE_CX1DA
+    810672723U,	// CDE_CX2
+    1009306302U,	// CDE_CX2A
+    1146742590U,	// CDE_CX2D
+    1009306324U,	// CDE_CX2DA
+    810672729U,	// CDE_CX3
+    1009388228U,	// CDE_CX3A
+    1146742596U,	// CDE_CX3D
+    1009388250U,	// CDE_CX3DA
+    1213327062U,	// CDE_VCX1A_fpdp
+    1213327062U,	// CDE_VCX1A_fpsp
+    1009396407U,	// CDE_VCX1A_vec
+    810672129U,	// CDE_VCX1_fpdp
+    810672129U,	// CDE_VCX1_fpsp
+    1009404180U,	// CDE_VCX1_vec
+    1213327069U,	// CDE_VCX2A_fpdp
+    1213327069U,	// CDE_VCX2A_fpsp
+    1009412797U,	// CDE_VCX2A_vec
+    810672722U,	// CDE_VCX2_fpdp
+    810672722U,	// CDE_VCX2_fpsp
+    1009396053U,	// CDE_VCX2_vec
+    1213327076U,	// CDE_VCX3A_fpdp
+    1213327076U,	// CDE_VCX3A_fpsp
+    1009420995U,	// CDE_VCX3A_vec
+    810672728U,	// CDE_VCX3_fpdp
+    810672728U,	// CDE_VCX3_fpsp
+    1009412458U,	// CDE_VCX3_vec
+    1277825288U,	// CDP
+    1348641343U,	// CDP2
+    5445U,	// CLREX
+    2651636U,	// CLZ
+    2650273U,	// CMNri
+    2650273U,	// CMNzrr
+    2683041U,	// CMNzrsi
+    2666657U,	// CMNzrsr
+    2650386U,	// CMPri
+    2650386U,	// CMPrr
+    2683154U,	// CMPrsi
+    2666770U,	// CMPrsr
+    4278196U,	// CPS1p
+    1412092501U,	// CPS2p
+    1412092501U,	// CPS3p
+    875644665U,	// CRC32B
+    875644673U,	// CRC32CB
+    875644783U,	// CRC32CH
+    875644903U,	// CRC32CW
+    875644775U,	// CRC32H
+    875644895U,	// CRC32W
+    2731508U,	// DBG
+    190232U,	// DMB
+    190237U,	// DSB
+    2634192U,	// EORri
+    2634192U,	// EORrr
+    2691536U,	// EORrsi
+    78288U,	// EORrsr
+    4313779U,	// ERET
+    1147696202U,	// FCONSTD
+    7369802U,	// FCONSTH
+    7894090U,	// FCONSTS
+    875066610U,	// FLDMXDB_UPD
+    2733201U,	// FLDMXIA
+    875066513U,	// FLDMXIA_UPD
+    8507993U,	// FMSTAT
+    875066618U,	// FSTMXDB_UPD
+    2733209U,	// FSTMXIA
+    875066521U,	// FSTMXIA_UPD
+    2732808U,	// HINT
+    4278207U,	// HLT
+    4278067U,	// HVC
+    198434U,	// ISB
+    2648800U,	// LDA
+    2649009U,	// LDAB
+    2651443U,	// LDAEX
+    2649320U,	// LDAEXB
+    1479044523U,	// LDAEXD
+    2649816U,	// LDAEXH
+    2649616U,	// LDAH
+    1552590722U,	// LDC2L_OFFSET
+    1619699586U,	// LDC2L_OPTION
+    1619699586U,	// LDC2L_POST
+    9561986U,	// LDC2L_PRE
+    1552589350U,	// LDC2_OFFSET
+    1619698214U,	// LDC2_OPTION
+    1619698214U,	// LDC2_POST
+    9560614U,	// LDC2_PRE
+    1277734746U,	// LDCL_OFFSET
+    1277734746U,	// LDCL_OPTION
+    1277734746U,	// LDCL_POST
+    1009307482U,	// LDCL_PRE
+    1277734158U,	// LDC_OFFSET
+    1277734158U,	// LDC_OPTION
+    1277734158U,	// LDC_POST
+    1009306894U,	// LDC_PRE
+    2730724U,	// LDMDA
+    875064036U,	// LDMDA_UPD
+    2730979U,	// LDMDB
+    875064291U,	// LDMDB_UPD
+    2732107U,	// LDMIA
+    875065419U,	// LDMIA_UPD
+    2730998U,	// LDMIB
+    875064310U,	// LDMIB_UPD
+    2675360U,	// LDRBT_POST_IMM
+    2675360U,	// LDRBT_POST_REG
+    2673786U,	// LDRB_POST_IMM
+    2673786U,	// LDRB_POST_REG
+    2665594U,	// LDRB_PRE_IMM
+    2673786U,	// LDRB_PRE_REG
+    2681978U,	// LDRBi12
+    2665594U,	// LDRBrs
+    2674068U,	// LDRD
+    2755988U,	// LDRD_POST
+    2755988U,	// LDRD_PRE
+    2651455U,	// LDREX
+    2649334U,	// LDREXB
+    1479044537U,	// LDREXD
+    2649830U,	// LDREXH
+    2666112U,	// LDRH
+    2667203U,	// LDRHTi
+    2675395U,	// LDRHTr
+    2674304U,	// LDRH_POST
+    2674304U,	// LDRH_PRE
+    2665613U,	// LDRSB
+    2667180U,	// LDRSBTi
+    2675372U,	// LDRSBTr
+    2673805U,	// LDRSB_POST
+    2673805U,	// LDRSB_PRE
+    2666151U,	// LDRSH
+    2667215U,	// LDRSHTi
+    2675407U,	// LDRSHTr
+    2674343U,	// LDRSH_POST
+    2674343U,	// LDRSH_PRE
+    2675554U,	// LDRT_POST_IMM
+    2675554U,	// LDRT_POST_REG
+    2675110U,	// LDR_POST_IMM
+    2675110U,	// LDR_POST_REG
+    2666918U,	// LDR_PRE_IMM
+    2675110U,	// LDR_PRE_REG
+    2683302U,	// LDRcp
+    2683302U,	// LDRi12
+    2666918U,	// LDRrs
+    1277825437U,	// MCR
+    811770437U,	// MCR2
+    1277743576U,	// MCRR
+    811770443U,	// MCRR2
+    2689828U,	// MLA
+    2667053U,	// MLS
+    10081355U,	// MOVPCLR
+    2683821U,	// MOVTi16
+    2659403U,	// MOVi
+    2651250U,	// MOVi16
+    2659403U,	// MOVr
+    2659403U,	// MOVr_TC
+    2634827U,	// MOVsi
+    2692171U,	// MOVsr
+    1009388837U,	// MRC
+    10609196U,	// MRC2
+    1680395561U,	// MRRC
+    205362U,	// MRRC2
+    2732634U,	// MRS
+    2650714U,	// MRSbanked
+    2732634U,	// MRSsys
+    1747481070U,	// MSR
+    1814589934U,	// MSRbanked
+    1747481070U,	// MSRi
+    2633774U,	// MUL
+    2674699U,	// MVE_ASRLi
+    2674699U,	// MVE_ASRLr
+    875643877U,	// MVE_DLSTP_16
+    875643124U,	// MVE_DLSTP_32
+    875643486U,	// MVE_DLSTP_64
+    875644536U,	// MVE_DLSTP_8
+    1076482381U,	// MVE_LCTP
+    1882285988U,	// MVE_LETP
+    2674646U,	// MVE_LSLLi
+    2674646U,	// MVE_LSLLr
+    2674704U,	// MVE_LSRL
+    875098538U,	// MVE_SQRSHR
+    2756597U,	// MVE_SQRSHRL
+    875097985U,	// MVE_SQSHL
+    2674618U,	// MVE_SQSHLL
+    875098545U,	// MVE_SRSHR
+    2674685U,	// MVE_SRSHRL
+    875098003U,	// MVE_UQRSHL
+    2756552U,	// MVE_UQRSHLL
+    875097991U,	// MVE_UQSHL
+    2674625U,	// MVE_UQSHLL
+    875098551U,	// MVE_URSHR
+    2674692U,	// MVE_URSHRL
+    11154380U,	// MVE_VABAVs16
+    11678668U,	// MVE_VABAVs32
+    12202956U,	// MVE_VABAVs8
+    12727244U,	// MVE_VABAVu16
+    13251532U,	// MVE_VABAVu32
+    13775820U,	// MVE_VABAVu8
+    7490886U,	// MVE_VABDf16
+    8015174U,	// MVE_VABDf32
+    11160902U,	// MVE_VABDs16
+    11685190U,	// MVE_VABDs32
+    12209478U,	// MVE_VABDs8
+    12733766U,	// MVE_VABDu16
+    13258054U,	// MVE_VABDu32
+    13782342U,	// MVE_VABDu8
+    7557660U,	// MVE_VABSf16
+    8081948U,	// MVE_VABSf32
+    11227676U,	// MVE_VABSs16
+    11751964U,	// MVE_VABSs32
+    12276252U,	// MVE_VABSs8
+    14314761U,	// MVE_VADC
+    14298874U,	// MVE_VADCI
+    11692963U,	// MVE_VADDLVs32acc
+    11686957U,	// MVE_VADDLVs32no_acc
+    13265827U,	// MVE_VADDLVu32acc
+    13259821U,	// MVE_VADDLVu32no_acc
+    11160476U,	// MVE_VADDVs16acc
+    11228180U,	// MVE_VADDVs16no_acc
+    11684764U,	// MVE_VADDVs32acc
+    11752468U,	// MVE_VADDVs32no_acc
+    12209052U,	// MVE_VADDVs8acc
+    12276756U,	// MVE_VADDVs8no_acc
+    12733340U,	// MVE_VADDVu16acc
+    12801044U,	// MVE_VADDVu16no_acc
+    13257628U,	// MVE_VADDVu32acc
+    13325332U,	// MVE_VADDVu32no_acc
+    13781916U,	// MVE_VADDVu8acc
+    13849620U,	// MVE_VADDVu8no_acc
+    7490935U,	// MVE_VADD_qr_f16
+    8015223U,	// MVE_VADD_qr_f32
+    14830967U,	// MVE_VADD_qr_i16
+    14306679U,	// MVE_VADD_qr_i32
+    15355255U,	// MVE_VADD_qr_i8
+    7490935U,	// MVE_VADDf16
+    8015223U,	// MVE_VADDf32
+    14830967U,	// MVE_VADDi16
+    14306679U,	// MVE_VADDi32
+    15355255U,	// MVE_VADDi8
+    2772366U,	// MVE_VAND
+    2772246U,	// MVE_VBIC
+    14830870U,	// MVE_VBICimmi16
+    14306582U,	// MVE_VBICimmi32
+    676338U,	// MVE_VBRSR16
+    1200626U,	// MVE_VBRSR32
+    1724914U,	// MVE_VBRSR8
+    7482706U,	// MVE_VCADDf16
+    8006994U,	// MVE_VCADDf32
+    14822738U,	// MVE_VCADDi16
+    14298450U,	// MVE_VCADDi32
+    15347026U,	// MVE_VCADDi8
+    11227686U,	// MVE_VCLSs16
+    11751974U,	// MVE_VCLSs32
+    12276262U,	// MVE_VCLSs8
+    14898675U,	// MVE_VCLZs16
+    14374387U,	// MVE_VCLZs32
+    15422963U,	// MVE_VCLZs8
+    7498530U,	// MVE_VCMLAf16
+    8022818U,	// MVE_VCMLAf32
+    1953640721U,	// MVE_VCMPf16
+    1953640721U,	// MVE_VCMPf16r
+    1954165009U,	// MVE_VCMPf32
+    1954165009U,	// MVE_VCMPf32r
+    1960980753U,	// MVE_VCMPi16
+    1960980753U,	// MVE_VCMPi16r
+    1960456465U,	// MVE_VCMPi32
+    1960456465U,	// MVE_VCMPi32r
+    1961505041U,	// MVE_VCMPi8
+    1961505041U,	// MVE_VCMPi8r
+    1957310737U,	// MVE_VCMPs16
+    1957310737U,	// MVE_VCMPs16r
+    1957835025U,	// MVE_VCMPs32
+    1957835025U,	// MVE_VCMPs32r
+    1958359313U,	// MVE_VCMPs8
+    1958359313U,	// MVE_VCMPs8r
+    1958883601U,	// MVE_VCMPu16
+    1958883601U,	// MVE_VCMPu16r
+    1959407889U,	// MVE_VCMPu32
+    1959407889U,	// MVE_VCMPu32r
+    1959932177U,	// MVE_VCMPu8
+    1959932177U,	// MVE_VCMPu8r
+    7483436U,	// MVE_VCMULf16
+    8007724U,	// MVE_VCMULf32
+    873156946U,	// MVE_VCTP16
+    873681234U,	// MVE_VCTP32
+    888361298U,	// MVE_VCTP64
+    874205522U,	// MVE_VCTP8
+    821710003U,	// MVE_VCVTf16f32bh
+    821711766U,	// MVE_VCVTf16f32th
+    1157780392U,	// MVE_VCVTf16s16_fix
+    1090737064U,	// MVE_VCVTf16s16n
+    1158304680U,	// MVE_VCVTf16u16_fix
+    1091261352U,	// MVE_VCVTf16u16n
+    18042035U,	// MVE_VCVTf32f16bh
+    18043798U,	// MVE_VCVTf32f16th
+    1159353256U,	// MVE_VCVTf32s32_fix
+    1092309928U,	// MVE_VCVTf32s32n
+    1159877544U,	// MVE_VCVTf32u32_fix
+    1092834216U,	// MVE_VCVTf32u32n
+    1160401832U,	// MVE_VCVTs16f16_fix
+    1093356400U,	// MVE_VCVTs16f16a
+    1093357682U,	// MVE_VCVTs16f16m
+    1093357778U,	// MVE_VCVTs16f16n
+    1093357918U,	// MVE_VCVTs16f16p
+    1093358504U,	// MVE_VCVTs16f16z
+    1160926120U,	// MVE_VCVTs32f32_fix
+    1093880688U,	// MVE_VCVTs32f32a
+    1093881970U,	// MVE_VCVTs32f32m
+    1093882066U,	// MVE_VCVTs32f32n
+    1093882206U,	// MVE_VCVTs32f32p
+    1093882792U,	// MVE_VCVTs32f32z
+    1161450408U,	// MVE_VCVTu16f16_fix
+    1094404976U,	// MVE_VCVTu16f16a
+    1094406258U,	// MVE_VCVTu16f16m
+    1094406354U,	// MVE_VCVTu16f16n
+    1094406494U,	// MVE_VCVTu16f16p
+    1094407080U,	// MVE_VCVTu16f16z
+    1161974696U,	// MVE_VCVTu32f32_fix
+    1094929264U,	// MVE_VCVTu32f32a
+    1094930546U,	// MVE_VCVTu32f32m
+    1094930642U,	// MVE_VCVTu32f32n
+    1094930782U,	// MVE_VCVTu32f32p
+    1094931368U,	// MVE_VCVTu32f32z
+    12726628U,	// MVE_VDDUPu16
+    13250916U,	// MVE_VDDUPu32
+    13775204U,	// MVE_VDDUPu8
+    741744U,	// MVE_VDUP16
+    1266032U,	// MVE_VDUP32
+    1790320U,	// MVE_VDUP8
+    12743029U,	// MVE_VDWDUPu16
+    13267317U,	// MVE_VDWDUPu32
+    13791605U,	// MVE_VDWDUPu8
+    2773455U,	// MVE_VEOR
+    7483920U,	// MVE_VFMA_qr_Sf16
+    8008208U,	// MVE_VFMA_qr_Sf32
+    7482169U,	// MVE_VFMA_qr_f16
+    8006457U,	// MVE_VFMA_qr_f32
+    7482169U,	// MVE_VFMAf16
+    8006457U,	// MVE_VFMAf32
+    7483964U,	// MVE_VFMSf16
+    8008252U,	// MVE_VFMSf32
+    11160933U,	// MVE_VHADD_qr_s16
+    11685221U,	// MVE_VHADD_qr_s32
+    12209509U,	// MVE_VHADD_qr_s8
+    12733797U,	// MVE_VHADD_qr_u16
+    13258085U,	// MVE_VHADD_qr_u32
+    13782373U,	// MVE_VHADD_qr_u8
+    11160933U,	// MVE_VHADDs16
+    11685221U,	// MVE_VHADDs32
+    12209509U,	// MVE_VHADDs8
+    12733797U,	// MVE_VHADDu16
+    13258085U,	// MVE_VHADDu32
+    13782373U,	// MVE_VHADDu8
+    11152715U,	// MVE_VHCADDs16
+    11677003U,	// MVE_VHCADDs32
+    12201291U,	// MVE_VHCADDs8
+    11160777U,	// MVE_VHSUB_qr_s16
+    11685065U,	// MVE_VHSUB_qr_s32
+    12209353U,	// MVE_VHSUB_qr_s8
+    12733641U,	// MVE_VHSUB_qr_u16
+    13257929U,	// MVE_VHSUB_qr_u32
+    13782217U,	// MVE_VHSUB_qr_u8
+    11160777U,	// MVE_VHSUBs16
+    11685065U,	// MVE_VHSUBs32
+    12209353U,	// MVE_VHSUBs8
+    12733641U,	// MVE_VHSUBu16
+    13257929U,	// MVE_VHSUBu32
+    13782217U,	// MVE_VHSUBu8
+    12726634U,	// MVE_VIDUPu16
+    13250922U,	// MVE_VIDUPu32
+    13775210U,	// MVE_VIDUPu8
+    12743036U,	// MVE_VIWDUPu16
+    13267324U,	// MVE_VIWDUPu32
+    13791612U,	// MVE_VIWDUPu8
+    21717869U,	// MVE_VLD20_16
+    22242157U,	// MVE_VLD20_16_wb
+    21716999U,	// MVE_VLD20_32
+    22241287U,	// MVE_VLD20_32_wb
+    21718505U,	// MVE_VLD20_8
+    22242793U,	// MVE_VLD20_8_wb
+    21717909U,	// MVE_VLD21_16
+    22242197U,	// MVE_VLD21_16_wb
+    21717065U,	// MVE_VLD21_32
+    22241353U,	// MVE_VLD21_32_wb
+    21718541U,	// MVE_VLD21_8
+    22242829U,	// MVE_VLD21_8_wb
+    21726081U,	// MVE_VLD40_16
+    22250369U,	// MVE_VLD40_16_wb
+    21725211U,	// MVE_VLD40_32
+    22249499U,	// MVE_VLD40_32_wb
+    21726715U,	// MVE_VLD40_8
+    22251003U,	// MVE_VLD40_8_wb
+    21726121U,	// MVE_VLD41_16
+    22250409U,	// MVE_VLD41_16_wb
+    21725277U,	// MVE_VLD41_32
+    22249565U,	// MVE_VLD41_32_wb
+    21726751U,	// MVE_VLD41_8
+    22251039U,	// MVE_VLD41_8_wb
+    21726141U,	// MVE_VLD42_16
+    22250429U,	// MVE_VLD42_16_wb
+    21725323U,	// MVE_VLD42_32
+    22249611U,	// MVE_VLD42_32_wb
+    21726769U,	// MVE_VLD42_8
+    22251057U,	// MVE_VLD42_8_wb
+    21726161U,	// MVE_VLD43_16
+    22250449U,	// MVE_VLD43_16_wb
+    21725356U,	// MVE_VLD43_32
+    22249644U,	// MVE_VLD43_32_wb
+    21726787U,	// MVE_VLD43_8
+    22251075U,	// MVE_VLD43_8_wb
+    11160697U,	// MVE_VLDRBS16
+    883567737U,	// MVE_VLDRBS16_post
+    883567737U,	// MVE_VLDRBS16_pre
+    11160697U,	// MVE_VLDRBS16_rq
+    11684985U,	// MVE_VLDRBS32
+    884092025U,	// MVE_VLDRBS32_post
+    884092025U,	// MVE_VLDRBS32_pre
+    11684985U,	// MVE_VLDRBS32_rq
+    12733561U,	// MVE_VLDRBU16
+    885140601U,	// MVE_VLDRBU16_post
+    885140601U,	// MVE_VLDRBU16_pre
+    12733561U,	// MVE_VLDRBU16_rq
+    13257849U,	// MVE_VLDRBU32
+    885664889U,	// MVE_VLDRBU32_post
+    885664889U,	// MVE_VLDRBU32_pre
+    13257849U,	// MVE_VLDRBU32_rq
+    13782137U,	// MVE_VLDRBU8
+    886189177U,	// MVE_VLDRBU8_post
+    886189177U,	// MVE_VLDRBU8_pre
+    13782137U,	// MVE_VLDRBU8_rq
+    22695315U,	// MVE_VLDRDU64_qi
+    895102355U,	// MVE_VLDRDU64_qi_pre
+    22695315U,	// MVE_VLDRDU64_rq
+    22695315U,	// MVE_VLDRDU64_rq_u
+    11685503U,	// MVE_VLDRHS32
+    884092543U,	// MVE_VLDRHS32_post
+    884092543U,	// MVE_VLDRHS32_pre
+    11685503U,	// MVE_VLDRHS32_rq
+    11685503U,	// MVE_VLDRHS32_rq_u
+    12734079U,	// MVE_VLDRHU16
+    885141119U,	// MVE_VLDRHU16_post
+    885141119U,	// MVE_VLDRHU16_pre
+    12734079U,	// MVE_VLDRHU16_rq
+    12734079U,	// MVE_VLDRHU16_rq_u
+    13258367U,	// MVE_VLDRHU32
+    885665407U,	// MVE_VLDRHU32_post
+    885665407U,	// MVE_VLDRHU32_pre
+    13258367U,	// MVE_VLDRHU32_rq
+    13258367U,	// MVE_VLDRHU32_rq_u
+    13259878U,	// MVE_VLDRWU32
+    885666918U,	// MVE_VLDRWU32_post
+    885666918U,	// MVE_VLDRWU32_pre
+    13259878U,	// MVE_VLDRWU32_qi
+    885666918U,	// MVE_VLDRWU32_qi_pre
+    13259878U,	// MVE_VLDRWU32_rq
+    13259878U,	// MVE_VLDRWU32_rq_u
+    883577869U,	// MVE_VMAXAVs16
+    884102157U,	// MVE_VMAXAVs32
+    884626445U,	// MVE_VMAXAVs8
+    11160491U,	// MVE_VMAXAs16
+    11684779U,	// MVE_VMAXAs32
+    12209067U,	// MVE_VMAXAs8
+    879907837U,	// MVE_VMAXNMAVf16
+    880432125U,	// MVE_VMAXNMAVf32
+    7490380U,	// MVE_VMAXNMAf16
+    8014668U,	// MVE_VMAXNMAf32
+    879907900U,	// MVE_VMAXNMVf16
+    880432188U,	// MVE_VMAXNMVf32
+    7491670U,	// MVE_VMAXNMf16
+    8015958U,	// MVE_VMAXNMf32
+    883577935U,	// MVE_VMAXVs16
+    884102223U,	// MVE_VMAXVs32
+    884626511U,	// MVE_VMAXVs8
+    885150799U,	// MVE_VMAXVu16
+    885675087U,	// MVE_VMAXVu32
+    886199375U,	// MVE_VMAXVu8
+    11162791U,	// MVE_VMAXs16
+    11687079U,	// MVE_VMAXs32
+    12211367U,	// MVE_VMAXs8
+    12735655U,	// MVE_VMAXu16
+    13259943U,	// MVE_VMAXu32
+    13784231U,	// MVE_VMAXu8
+    883577862U,	// MVE_VMINAVs16
+    884102150U,	// MVE_VMINAVs32
+    884626438U,	// MVE_VMINAVs8
+    11160404U,	// MVE_VMINAs16
+    11684692U,	// MVE_VMINAs32
+    12208980U,	// MVE_VMINAs8
+    879907828U,	// MVE_VMINNMAVf16
+    880432116U,	// MVE_VMINNMAVf32
+    7490372U,	// MVE_VMINNMAf16
+    8014660U,	// MVE_VMINNMAf32
+    879907892U,	// MVE_VMINNMVf16
+    880432180U,	// MVE_VMINNMVf32
+    7491663U,	// MVE_VMINNMf16
+    8015951U,	// MVE_VMINNMf32
+    883577924U,	// MVE_VMINVs16
+    884102212U,	// MVE_VMINVs32
+    884626500U,	// MVE_VMINVs8
+    885150788U,	// MVE_VMINVu16
+    885675076U,	// MVE_VMINVu32
+    886199364U,	// MVE_VMINVu8
+    11161756U,	// MVE_VMINs16
+    11686044U,	// MVE_VMINs32
+    12210332U,	// MVE_VMINs8
+    12734620U,	// MVE_VMINu16
+    13258908U,	// MVE_VMINu32
+    13783196U,	// MVE_VMINu8
+    11152246U,	// MVE_VMLADAVas16
+    11676534U,	// MVE_VMLADAVas32
+    12200822U,	// MVE_VMLADAVas8
+    12725110U,	// MVE_VMLADAVau16
+    13249398U,	// MVE_VMLADAVau32
+    13773686U,	// MVE_VMLADAVau8
+    11154632U,	// MVE_VMLADAVaxs16
+    11678920U,	// MVE_VMLADAVaxs32
+    12203208U,	// MVE_VMLADAVaxs8
+    11162578U,	// MVE_VMLADAVs16
+    11686866U,	// MVE_VMLADAVs32
+    12211154U,	// MVE_VMLADAVs8
+    12735442U,	// MVE_VMLADAVu16
+    13259730U,	// MVE_VMLADAVu32
+    13784018U,	// MVE_VMLADAVu8
+    11163085U,	// MVE_VMLADAVxs16
+    11687373U,	// MVE_VMLADAVxs32
+    12211661U,	// MVE_VMLADAVxs8
+    11176831U,	// MVE_VMLALDAVas16
+    11701119U,	// MVE_VMLALDAVas32
+    12749695U,	// MVE_VMLALDAVau16
+    13273983U,	// MVE_VMLALDAVau32
+    11179218U,	// MVE_VMLALDAVaxs16
+    11703506U,	// MVE_VMLALDAVaxs32
+    11154394U,	// MVE_VMLALDAVs16
+    11678682U,	// MVE_VMLALDAVs32
+    12727258U,	// MVE_VMLALDAVu16
+    13251546U,	// MVE_VMLALDAVu32
+    11154902U,	// MVE_VMLALDAVxs16
+    11679190U,	// MVE_VMLALDAVxs32
+    14823946U,	// MVE_VMLAS_qr_i16
+    14299658U,	// MVE_VMLAS_qr_i32
+    15348234U,	// MVE_VMLAS_qr_i8
+    14822196U,	// MVE_VMLA_qr_i16
+    14297908U,	// MVE_VMLA_qr_i32
+    15346484U,	// MVE_VMLA_qr_i8
+    11152275U,	// MVE_VMLSDAVas16
+    11676563U,	// MVE_VMLSDAVas32
+    12200851U,	// MVE_VMLSDAVas8
+    11154664U,	// MVE_VMLSDAVaxs16
+    11678952U,	// MVE_VMLSDAVaxs32
+    12203240U,	// MVE_VMLSDAVaxs8
+    11162604U,	// MVE_VMLSDAVs16
+    11686892U,	// MVE_VMLSDAVs32
+    12211180U,	// MVE_VMLSDAVs8
+    11163114U,	// MVE_VMLSDAVxs16
+    11687402U,	// MVE_VMLSDAVxs32
+    12211690U,	// MVE_VMLSDAVxs8
+    11176841U,	// MVE_VMLSLDAVas16
+    11701129U,	// MVE_VMLSLDAVas32
+    11179229U,	// MVE_VMLSLDAVaxs16
+    11703517U,	// MVE_VMLSLDAVaxs32
+    11154403U,	// MVE_VMLSLDAVs16
+    11678691U,	// MVE_VMLSLDAVs32
+    11154912U,	// MVE_VMLSLDAVxs16
+    11679200U,	// MVE_VMLSLDAVxs32
+    11226142U,	// MVE_VMOVLs16bh
+    11227900U,	// MVE_VMOVLs16th
+    12274718U,	// MVE_VMOVLs8bh
+    12276476U,	// MVE_VMOVLs8th
+    12799006U,	// MVE_VMOVLu16bh
+    12800764U,	// MVE_VMOVLu16th
+    13847582U,	// MVE_VMOVLu8bh
+    13849340U,	// MVE_VMOVLu8th
+    14830701U,	// MVE_VMOVNi16bh
+    14832465U,	// MVE_VMOVNi16th
+    14306413U,	// MVE_VMOVNi32bh
+    14308177U,	// MVE_VMOVNi32th
+    1111114U,	// MVE_VMOV_from_lane_32
+    11072586U,	// MVE_VMOV_from_lane_s16
+    12121162U,	// MVE_VMOV_from_lane_s8
+    12645450U,	// MVE_VMOV_from_lane_u16
+    13694026U,	// MVE_VMOV_from_lane_u8
+    2757706U,	// MVE_VMOV_q_rr
+    2675786U,	// MVE_VMOV_rr_q
+    570442U,	// MVE_VMOV_to_lane_16
+    1094730U,	// MVE_VMOV_to_lane_32
+    1619018U,	// MVE_VMOV_to_lane_8
+    8082506U,	// MVE_VMOVimmf32
+    14898250U,	// MVE_VMOVimmi16
+    14373962U,	// MVE_VMOVimmi32
+    2036552778U,	// MVE_VMOVimmi64
+    15422538U,	// MVE_VMOVimmi8
+    11161209U,	// MVE_VMULHs16
+    11685497U,	// MVE_VMULHs32
+    12209785U,	// MVE_VMULHs8
+    12734073U,	// MVE_VMULHu16
+    13258361U,	// MVE_VMULHu32
+    13782649U,	// MVE_VMULHu8
+    23743506U,	// MVE_VMULLBp16
+    24267794U,	// MVE_VMULLBp8
+    11160594U,	// MVE_VMULLBs16
+    11684882U,	// MVE_VMULLBs32
+    12209170U,	// MVE_VMULLBs8
+    12733458U,	// MVE_VMULLBu16
+    13257746U,	// MVE_VMULLBu32
+    13782034U,	// MVE_VMULLBu8
+    23745269U,	// MVE_VMULLTp16
+    24269557U,	// MVE_VMULLTp8
+    11162357U,	// MVE_VMULLTs16
+    11686645U,	// MVE_VMULLTs32
+    12210933U,	// MVE_VMULLTs8
+    12735221U,	// MVE_VMULLTu16
+    13259509U,	// MVE_VMULLTu32
+    13783797U,	// MVE_VMULLTu8
+    7491646U,	// MVE_VMUL_qr_f16
+    8015934U,	// MVE_VMUL_qr_f32
+    14831678U,	// MVE_VMUL_qr_i16
+    14307390U,	// MVE_VMUL_qr_i32
+    15355966U,	// MVE_VMUL_qr_i8
+    7491646U,	// MVE_VMULf16
+    8015934U,	// MVE_VMULf32
+    14831678U,	// MVE_VMULi16
+    14307390U,	// MVE_VMULi32
+    15355966U,	// MVE_VMULi8
+    2838769U,	// MVE_VMVN
+    14897393U,	// MVE_VMVNimmi16
+    14373105U,	// MVE_VMVNimmi32
+    7556611U,	// MVE_VNEGf16
+    8080899U,	// MVE_VNEGf32
+    11226627U,	// MVE_VNEGs16
+    11750915U,	// MVE_VNEGs32
+    12275203U,	// MVE_VNEGs8
+    2773185U,	// MVE_VORN
+    2773469U,	// MVE_VORR
+    14832093U,	// MVE_VORRimmi16
+    14307805U,	// MVE_VORRimmi32
+    1076581208U,	// MVE_VPNOT
+    2772855U,	// MVE_VPSEL
+    1076605810U,	// MVE_VPST
+    1961603934U,	// MVE_VPTv16i8
+    1961603934U,	// MVE_VPTv16i8r
+    1958458206U,	// MVE_VPTv16s8
+    1958458206U,	// MVE_VPTv16s8r
+    1960031070U,	// MVE_VPTv16u8
+    1960031070U,	// MVE_VPTv16u8r
+    1954263902U,	// MVE_VPTv4f32
+    1954263902U,	// MVE_VPTv4f32r
+    1960555358U,	// MVE_VPTv4i32
+    1960555358U,	// MVE_VPTv4i32r
+    1957933918U,	// MVE_VPTv4s32
+    1957933918U,	// MVE_VPTv4s32r
+    1959506782U,	// MVE_VPTv4u32
+    1959506782U,	// MVE_VPTv4u32r
+    1953739614U,	// MVE_VPTv8f16
+    1953739614U,	// MVE_VPTv8f16r
+    1961079646U,	// MVE_VPTv8i16
+    1961079646U,	// MVE_VPTv8i16r
+    1957409630U,	// MVE_VPTv8s16
+    1957409630U,	// MVE_VPTv8s16r
+    1958982494U,	// MVE_VPTv8u16
+    1958982494U,	// MVE_VPTv8u16r
+    11227670U,	// MVE_VQABSs16
+    11751958U,	// MVE_VQABSs32
+    12276246U,	// MVE_VQABSs8
+    11160945U,	// MVE_VQADD_qr_s16
+    11685233U,	// MVE_VQADD_qr_s32
+    12209521U,	// MVE_VQADD_qr_s8
+    12733809U,	// MVE_VQADD_qr_u16
+    13258097U,	// MVE_VQADD_qr_u32
+    13782385U,	// MVE_VQADD_qr_u8
+    11160945U,	// MVE_VQADDs16
+    11685233U,	// MVE_VQADDs32
+    12209521U,	// MVE_VQADDs8
+    12733809U,	// MVE_VQADDu16
+    13258097U,	// MVE_VQADDu32
+    13782385U,	// MVE_VQADDu8
+    11154779U,	// MVE_VQDMLADHXs16
+    11679067U,	// MVE_VQDMLADHXs32
+    12203355U,	// MVE_VQDMLADHXs8
+    11152950U,	// MVE_VQDMLADHs16
+    11677238U,	// MVE_VQDMLADHs32
+    12201526U,	// MVE_VQDMLADHs8
+    11152917U,	// MVE_VQDMLAH_qrs16
+    11677205U,	// MVE_VQDMLAH_qrs32
+    12201493U,	// MVE_VQDMLAH_qrs8
+    11153035U,	// MVE_VQDMLASH_qrs16
+    11677323U,	// MVE_VQDMLASH_qrs32
+    12201611U,	// MVE_VQDMLASH_qrs8
+    11154800U,	// MVE_VQDMLSDHXs16
+    11679088U,	// MVE_VQDMLSDHXs32
+    12203376U,	// MVE_VQDMLSDHXs8
+    11152969U,	// MVE_VQDMLSDHs16
+    11677257U,	// MVE_VQDMLSDHs32
+    12201545U,	// MVE_VQDMLSDHs8
+    11161185U,	// MVE_VQDMULH_qr_s16
+    11685473U,	// MVE_VQDMULH_qr_s32
+    12209761U,	// MVE_VQDMULH_qr_s8
+    11161185U,	// MVE_VQDMULHi16
+    11685473U,	// MVE_VQDMULHi32
+    12209761U,	// MVE_VQDMULHi8
+    11160585U,	// MVE_VQDMULL_qr_s16bh
+    11162348U,	// MVE_VQDMULL_qr_s16th
+    11684873U,	// MVE_VQDMULL_qr_s32bh
+    11686636U,	// MVE_VQDMULL_qr_s32th
+    11160585U,	// MVE_VQDMULLs16bh
+    11162348U,	// MVE_VQDMULLs16th
+    11684873U,	// MVE_VQDMULLs32bh
+    11686636U,	// MVE_VQDMULLs32th
+    11160677U,	// MVE_VQMOVNs16bh
+    11162441U,	// MVE_VQMOVNs16th
+    11684965U,	// MVE_VQMOVNs32bh
+    11686729U,	// MVE_VQMOVNs32th
+    12733541U,	// MVE_VQMOVNu16bh
+    12735305U,	// MVE_VQMOVNu16th
+    13257829U,	// MVE_VQMOVNu32bh
+    13259593U,	// MVE_VQMOVNu32th
+    11160668U,	// MVE_VQMOVUNs16bh
+    11162432U,	// MVE_VQMOVUNs16th
+    11684956U,	// MVE_VQMOVUNs32bh
+    11686720U,	// MVE_VQMOVUNs32th
+    11226621U,	// MVE_VQNEGs16
+    11750909U,	// MVE_VQNEGs32
+    12275197U,	// MVE_VQNEGs8
+    11154789U,	// MVE_VQRDMLADHXs16
+    11679077U,	// MVE_VQRDMLADHXs32
+    12203365U,	// MVE_VQRDMLADHXs8
+    11152959U,	// MVE_VQRDMLADHs16
+    11677247U,	// MVE_VQRDMLADHs32
+    12201535U,	// MVE_VQRDMLADHs8
+    11152925U,	// MVE_VQRDMLAH_qrs16
+    11677213U,	// MVE_VQRDMLAH_qrs32
+    12201501U,	// MVE_VQRDMLAH_qrs8
+    11153044U,	// MVE_VQRDMLASH_qrs16
+    11677332U,	// MVE_VQRDMLASH_qrs32
+    12201620U,	// MVE_VQRDMLASH_qrs8
+    11154810U,	// MVE_VQRDMLSDHXs16
+    11679098U,	// MVE_VQRDMLSDHXs32
+    12203386U,	// MVE_VQRDMLSDHXs8
+    11152978U,	// MVE_VQRDMLSDHs16
+    11677266U,	// MVE_VQRDMLSDHs32
+    12201554U,	// MVE_VQRDMLSDHs8
+    11161193U,	// MVE_VQRDMULH_qr_s16
+    11685481U,	// MVE_VQRDMULH_qr_s32
+    12209769U,	// MVE_VQRDMULH_qr_s8
+    11161193U,	// MVE_VQRDMULHi16
+    11685481U,	// MVE_VQRDMULHi32
+    12209769U,	// MVE_VQRDMULHi8
+    11161498U,	// MVE_VQRSHL_by_vecs16
+    11685786U,	// MVE_VQRSHL_by_vecs32
+    12210074U,	// MVE_VQRSHL_by_vecs8
+    12734362U,	// MVE_VQRSHL_by_vecu16
+    13258650U,	// MVE_VQRSHL_by_vecu32
+    13782938U,	// MVE_VQRSHL_by_vecu8
+    11161498U,	// MVE_VQRSHL_qrs16
+    11685786U,	// MVE_VQRSHL_qrs32
+    12210074U,	// MVE_VQRSHL_qrs8
+    12734362U,	// MVE_VQRSHL_qru16
+    13258650U,	// MVE_VQRSHL_qru32
+    13782938U,	// MVE_VQRSHL_qru8
+    11152433U,	// MVE_VQRSHRNbhs16
+    11676721U,	// MVE_VQRSHRNbhs32
+    12725297U,	// MVE_VQRSHRNbhu16
+    13249585U,	// MVE_VQRSHRNbhu32
+    11154197U,	// MVE_VQRSHRNths16
+    11678485U,	// MVE_VQRSHRNths32
+    12727061U,	// MVE_VQRSHRNthu16
+    13251349U,	// MVE_VQRSHRNthu32
+    11152466U,	// MVE_VQRSHRUNs16bh
+    11154230U,	// MVE_VQRSHRUNs16th
+    11676754U,	// MVE_VQRSHRUNs32bh
+    11678518U,	// MVE_VQRSHRUNs32th
+    11162565U,	// MVE_VQSHLU_imms16
+    11686853U,	// MVE_VQSHLU_imms32
+    12211141U,	// MVE_VQSHLU_imms8
+    11161485U,	// MVE_VQSHL_by_vecs16
+    11685773U,	// MVE_VQSHL_by_vecs32
+    12210061U,	// MVE_VQSHL_by_vecs8
+    12734349U,	// MVE_VQSHL_by_vecu16
+    13258637U,	// MVE_VQSHL_by_vecu32
+    13782925U,	// MVE_VQSHL_by_vecu8
+    11161485U,	// MVE_VQSHL_qrs16
+    11685773U,	// MVE_VQSHL_qrs32
+    12210061U,	// MVE_VQSHL_qrs8
+    12734349U,	// MVE_VQSHL_qru16
+    13258637U,	// MVE_VQSHL_qru32
+    13782925U,	// MVE_VQSHL_qru8
+    11161485U,	// MVE_VQSHLimms16
+    11685773U,	// MVE_VQSHLimms32
+    12210061U,	// MVE_VQSHLimms8
+    12734349U,	// MVE_VQSHLimmu16
+    13258637U,	// MVE_VQSHLimmu32
+    13782925U,	// MVE_VQSHLimmu8
+    11152425U,	// MVE_VQSHRNbhs16
+    11676713U,	// MVE_VQSHRNbhs32
+    12725289U,	// MVE_VQSHRNbhu16
+    13249577U,	// MVE_VQSHRNbhu32
+    11154189U,	// MVE_VQSHRNths16
+    11678477U,	// MVE_VQSHRNths32
+    12727053U,	// MVE_VQSHRNthu16
+    13251341U,	// MVE_VQSHRNthu32
+    11152457U,	// MVE_VQSHRUNs16bh
+    11154221U,	// MVE_VQSHRUNs16th
+    11676745U,	// MVE_VQSHRUNs32bh
+    11678509U,	// MVE_VQSHRUNs32th
+    11160783U,	// MVE_VQSUB_qr_s16
+    11685071U,	// MVE_VQSUB_qr_s32
+    12209359U,	// MVE_VQSUB_qr_s8
+    12733647U,	// MVE_VQSUB_qr_u16
+    13257935U,	// MVE_VQSUB_qr_u32
+    13782223U,	// MVE_VQSUB_qr_u8
+    11160783U,	// MVE_VQSUBs16
+    11685071U,	// MVE_VQSUBs32
+    12209359U,	// MVE_VQSUBs8
+    12733647U,	// MVE_VQSUBu16
+    13257935U,	// MVE_VQSUBu32
+    13782223U,	// MVE_VQSUBu8
+    1788408U,	// MVE_VREV16_8
+    739609U,	// MVE_VREV32_16
+    1788185U,	// MVE_VREV32_8
+    739695U,	// MVE_VREV64_16
+    1263983U,	// MVE_VREV64_32
+    1788271U,	// MVE_VREV64_8
+    11160926U,	// MVE_VRHADDs16
+    11685214U,	// MVE_VRHADDs32
+    12209502U,	// MVE_VRHADDs8
+    12733790U,	// MVE_VRHADDu16
+    13258078U,	// MVE_VRHADDu32
+    13782366U,	// MVE_VRHADDu8
+    7555941U,	// MVE_VRINTf16A
+    7557221U,	// MVE_VRINTf16M
+    7557323U,	// MVE_VRINTf16N
+    7557463U,	// MVE_VRINTf16P
+    7558598U,	// MVE_VRINTf16X
+    7558648U,	// MVE_VRINTf16Z
+    8080229U,	// MVE_VRINTf32A
+    8081509U,	// MVE_VRINTf32M
+    8081611U,	// MVE_VRINTf32N
+    8081751U,	// MVE_VRINTf32P
+    8082886U,	// MVE_VRINTf32X
+    8082936U,	// MVE_VRINTf32Z
+    11700976U,	// MVE_VRMLALDAVHas32
+    13273840U,	// MVE_VRMLALDAVHau32
+    11703415U,	// MVE_VRMLALDAVHaxs32
+    11677378U,	// MVE_VRMLALDAVHs32
+    13250242U,	// MVE_VRMLALDAVHu32
+    11679109U,	// MVE_VRMLALDAVHxs32
+    11700988U,	// MVE_VRMLSLDAVHas32
+    11703428U,	// MVE_VRMLSLDAVHaxs32
+    11677389U,	// MVE_VRMLSLDAVHs32
+    11679121U,	// MVE_VRMLSLDAVHxs32
+    11161202U,	// MVE_VRMULHs16
+    11685490U,	// MVE_VRMULHs32
+    12209778U,	// MVE_VRMULHs8
+    12734066U,	// MVE_VRMULHu16
+    13258354U,	// MVE_VRMULHu32
+    13782642U,	// MVE_VRMULHu8
+    11161505U,	// MVE_VRSHL_by_vecs16
+    11685793U,	// MVE_VRSHL_by_vecs32
+    12210081U,	// MVE_VRSHL_by_vecs8
+    12734369U,	// MVE_VRSHL_by_vecu16
+    13258657U,	// MVE_VRSHL_by_vecu32
+    13782945U,	// MVE_VRSHL_by_vecu8
+    11161505U,	// MVE_VRSHL_qrs16
+    11685793U,	// MVE_VRSHL_qrs32
+    12210081U,	// MVE_VRSHL_qrs8
+    12734369U,	// MVE_VRSHL_qru16
+    13258657U,	// MVE_VRSHL_qru32
+    13782945U,	// MVE_VRSHL_qru8
+    14822458U,	// MVE_VRSHRNi16bh
+    14824222U,	// MVE_VRSHRNi16th
+    14298170U,	// MVE_VRSHRNi32bh
+    14299934U,	// MVE_VRSHRNi32th
+    11162045U,	// MVE_VRSHR_imms16
+    11686333U,	// MVE_VRSHR_imms32
+    12210621U,	// MVE_VRSHR_imms8
+    12734909U,	// MVE_VRSHR_immu16
+    13259197U,	// MVE_VRSHR_immu32
+    13783485U,	// MVE_VRSHR_immu8
+    14314756U,	// MVE_VSBC
+    14298868U,	// MVE_VSBCI
+    808086811U,	// MVE_VSHLC
+    11160578U,	// MVE_VSHLL_imms16bh
+    11162341U,	// MVE_VSHLL_imms16th
+    12209154U,	// MVE_VSHLL_imms8bh
+    12210917U,	// MVE_VSHLL_imms8th
+    12733442U,	// MVE_VSHLL_immu16bh
+    12735205U,	// MVE_VSHLL_immu16th
+    13782018U,	// MVE_VSHLL_immu8bh
+    13783781U,	// MVE_VSHLL_immu8th
+    11226114U,	// MVE_VSHLL_lws16bh
+    11227877U,	// MVE_VSHLL_lws16th
+    12274690U,	// MVE_VSHLL_lws8bh
+    12276453U,	// MVE_VSHLL_lws8th
+    12798978U,	// MVE_VSHLL_lwu16bh
+    12800741U,	// MVE_VSHLL_lwu16th
+    13847554U,	// MVE_VSHLL_lwu8bh
+    13849317U,	// MVE_VSHLL_lwu8th
+    11161511U,	// MVE_VSHL_by_vecs16
+    11685799U,	// MVE_VSHL_by_vecs32
+    12210087U,	// MVE_VSHL_by_vecs8
+    12734375U,	// MVE_VSHL_by_vecu16
+    13258663U,	// MVE_VSHL_by_vecu32
+    13782951U,	// MVE_VSHL_by_vecu8
+    14831527U,	// MVE_VSHL_immi16
+    14307239U,	// MVE_VSHL_immi32
+    15355815U,	// MVE_VSHL_immi8
+    11161511U,	// MVE_VSHL_qrs16
+    11685799U,	// MVE_VSHL_qrs32
+    12210087U,	// MVE_VSHL_qrs8
+    12734375U,	// MVE_VSHL_qru16
+    13258663U,	// MVE_VSHL_qru32
+    13782951U,	// MVE_VSHL_qru8
+    14822466U,	// MVE_VSHRNi16bh
+    14824230U,	// MVE_VSHRNi16th
+    14298178U,	// MVE_VSHRNi32bh
+    14299942U,	// MVE_VSHRNi32th
+    11162051U,	// MVE_VSHR_imms16
+    11686339U,	// MVE_VSHR_imms32
+    12210627U,	// MVE_VSHR_imms8
+    12734915U,	// MVE_VSHR_immu16
+    13259203U,	// MVE_VSHR_immu32
+    13783491U,	// MVE_VSHR_immu8
+    667400U,	// MVE_VSLIimm16
+    1191688U,	// MVE_VSLIimm32
+    1715976U,	// MVE_VSLIimm8
+    667405U,	// MVE_VSRIimm16
+    1191693U,	// MVE_VSRIimm32
+    1715981U,	// MVE_VSRIimm8
+    24863607U,	// MVE_VST20_16
+    246647U,	// MVE_VST20_16_wb
+    24862737U,	// MVE_VST20_32
+    245777U,	// MVE_VST20_32_wb
+    24864242U,	// MVE_VST20_8
+    247282U,	// MVE_VST20_8_wb
+    24863647U,	// MVE_VST21_16
+    246687U,	// MVE_VST21_16_wb
+    24862803U,	// MVE_VST21_32
+    245843U,	// MVE_VST21_32_wb
+    24864278U,	// MVE_VST21_8
+    247318U,	// MVE_VST21_8_wb
+    24871819U,	// MVE_VST40_16
+    254859U,	// MVE_VST40_16_wb
+    24870949U,	// MVE_VST40_32
+    253989U,	// MVE_VST40_32_wb
+    24872452U,	// MVE_VST40_8
+    255492U,	// MVE_VST40_8_wb
+    24871859U,	// MVE_VST41_16
+    254899U,	// MVE_VST41_16_wb
+    24871015U,	// MVE_VST41_32
+    254055U,	// MVE_VST41_32_wb
+    24872488U,	// MVE_VST41_8
+    255528U,	// MVE_VST41_8_wb
+    24871879U,	// MVE_VST42_16
+    254919U,	// MVE_VST42_16_wb
+    24871061U,	// MVE_VST42_32
+    254101U,	// MVE_VST42_32_wb
+    24872506U,	// MVE_VST42_8
+    255546U,	// MVE_VST42_8_wb
+    24871899U,	// MVE_VST43_16
+    254939U,	// MVE_VST43_16_wb
+    24871094U,	// MVE_VST43_32
+    254134U,	// MVE_VST43_32_wb
+    24872524U,	// MVE_VST43_8
+    255564U,	// MVE_VST43_8_wb
+    674943U,	// MVE_VSTRB16
+    873081983U,	// MVE_VSTRB16_post
+    873081983U,	// MVE_VSTRB16_pre
+    674943U,	// MVE_VSTRB16_rq
+    1199231U,	// MVE_VSTRB32
+    873606271U,	// MVE_VSTRB32_post
+    873606271U,	// MVE_VSTRB32_pre
+    1199231U,	// MVE_VSTRB32_rq
+    1723519U,	// MVE_VSTRB8_rq
+    1723519U,	// MVE_VSTRBU8
+    874130559U,	// MVE_VSTRBU8_post
+    874130559U,	// MVE_VSTRBU8_pre
+    15879577U,	// MVE_VSTRD64_qi
+    888286617U,	// MVE_VSTRD64_qi_pre
+    15879577U,	// MVE_VSTRD64_rq
+    15879577U,	// MVE_VSTRD64_rq_u
+    675461U,	// MVE_VSTRH16_rq
+    675461U,	// MVE_VSTRH16_rq_u
+    1199749U,	// MVE_VSTRH32
+    873606789U,	// MVE_VSTRH32_post
+    873606789U,	// MVE_VSTRH32_pre
+    1199749U,	// MVE_VSTRH32_rq
+    1199749U,	// MVE_VSTRH32_rq_u
+    675461U,	// MVE_VSTRHU16
+    873082501U,	// MVE_VSTRHU16_post
+    873082501U,	// MVE_VSTRHU16_pre
+    1201260U,	// MVE_VSTRW32_qi
+    873608300U,	// MVE_VSTRW32_qi_pre
+    1201260U,	// MVE_VSTRW32_rq
+    1201260U,	// MVE_VSTRW32_rq_u
+    1201260U,	// MVE_VSTRWU32
+    873608300U,	// MVE_VSTRWU32_post
+    873608300U,	// MVE_VSTRWU32_pre
+    7490773U,	// MVE_VSUB_qr_f16
+    8015061U,	// MVE_VSUB_qr_f32
+    14830805U,	// MVE_VSUB_qr_i16
+    14306517U,	// MVE_VSUB_qr_i32
+    15355093U,	// MVE_VSUB_qr_i8
+    7490773U,	// MVE_VSUBf16
+    8015061U,	// MVE_VSUBf32
+    14830805U,	// MVE_VSUBi16
+    14306517U,	// MVE_VSUBi32
+    15355093U,	// MVE_VSUBi8
+    875643887U,	// MVE_WLSTP_16
+    875643134U,	// MVE_WLSTP_32
+    875643496U,	// MVE_WLSTP_64
+    875644545U,	// MVE_WLSTP_8
+    2658546U,	// MVNi
+    2658546U,	// MVNr
+    2633970U,	// MVNsi
+    2691314U,	// MVNsr
+    875643322U,	// NEON_VMAXNMNDf
+    875644217U,	// NEON_VMAXNMNDh
+    875643322U,	// NEON_VMAXNMNQf
+    875644217U,	// NEON_VMAXNMNQh
+    875643310U,	// NEON_VMINNMNDf
+    875644205U,	// NEON_VMINNMNDh
+    875643310U,	// NEON_VMINNMNQf
+    875644205U,	// NEON_VMINNMNQh
+    2634206U,	// ORRri
+    2634206U,	// ORRrr
+    2691550U,	// ORRrsi
+    78302U,	// ORRrsr
+    2667147U,	// PKHBT
+    2665630U,	// PKHTB
+    264176U,	// PLDWi12
+    272368U,	// PLDWrs
+    264010U,	// PLDi12
+    272202U,	// PLDrs
+    264056U,	// PLIi12
+    272248U,	// PLIrs
+    2682226U,	// QADD
+    2681301U,	// QADD16
+    2681404U,	// QADD8
+    2684343U,	// QASX
+    2682200U,	// QDADD
+    2682051U,	// QDSUB
+    2684089U,	// QSAX
+    2682064U,	// QSUB
+    2681263U,	// QSUB16
+    2681365U,	// QSUB8
+    2650838U,	// RBIT
+    2651162U,	// REV
+    2648569U,	// REV16
+    2649778U,	// REVSH
+    4277995U,	// RFEDA
+    25257707U,	// RFEDA_UPD
+    4278026U,	// RFEDB
+    25257738U,	// RFEDB_UPD
+    4278002U,	// RFEIA
+    25257714U,	// RFEIA_UPD
+    4278033U,	// RFEIB
+    25257745U,	// RFEIB_UPD
+    2632847U,	// RSBri
+    2632847U,	// RSBrr
+    2690191U,	// RSBrsi
+    76943U,	// RSBrsr
+    2633006U,	// RSCri
+    2633006U,	// RSCrr
+    2690350U,	// RSCrsi
+    77102U,	// RSCrsr
+    2681308U,	// SADD16
+    2681410U,	// SADD8
+    2684348U,	// SASX
+    3206U,	// SB
+    2632965U,	// SBCri
+    2632965U,	// SBCrr
+    2690309U,	// SBCrsi
+    77061U,	// SBCrsr
+    2667857U,	// SBFX
+    2683934U,	// SDIV
+    2682745U,	// SEL
+    280399U,	// SETEND
+    4278172U,	// SETPAN
+    808534208U,	// SHA1C
+    875643082U,	// SHA1H
+    808534240U,	// SHA1M
+    808534250U,	// SHA1P
+    808534063U,	// SHA1SU0
+    808534129U,	// SHA1SU1
+    808534228U,	// SHA256H
+    808534175U,	// SHA256H2
+    808534075U,	// SHA256SU0
+    808534141U,	// SHA256SU1
+    2681284U,	// SHADD16
+    2681389U,	// SHADD8
+    2684330U,	// SHASX
+    2684076U,	// SHSAX
+    2681246U,	// SHSUB16
+    2681350U,	// SHSUB8
+    2731297U,	// SMC
+    2665410U,	// SMLABB
+    2667140U,	// SMLABT
+    2665786U,	// SMLAD
+    2667783U,	// SMLADX
+    290621U,	// SMLAL
+    2755529U,	// SMLALBB
+    2757265U,	// SMLALBT
+    2755964U,	// SMLALD
+    2757909U,	// SMLALDX
+    2755748U,	// SMLALTB
+    2757507U,	// SMLALTT
+    2665623U,	// SMLATB
+    2667388U,	// SMLATT
+    2665690U,	// SMLAWB
+    2667442U,	// SMLAWT
+    2665887U,	// SMLSD
+    2667813U,	// SMLSDX
+    2755975U,	// SMLSLD
+    2757917U,	// SMLSLDX
+    2665256U,	// SMMLA
+    2666902U,	// SMMLAR
+    2667051U,	// SMMLS
+    2666982U,	// SMMLSR
+    2682930U,	// SMMUL
+    2683336U,	// SMMULR
+    2682176U,	// SMUAD
+    2684174U,	// SMUADX
+    2681809U,	// SMULBB
+    2683545U,	// SMULBT
+    2691043U,	// SMULL
+    2682028U,	// SMULTB
+    2683787U,	// SMULTT
+    2682081U,	// SMULWB
+    2683833U,	// SMULWT
+    2682277U,	// SMUSD
+    2684204U,	// SMUSDX
+    4278330U,	// SRSDA
+    4278282U,	// SRSDA_UPD
+    4278352U,	// SRSDB
+    4278306U,	// SRSDB_UPD
+    4278341U,	// SRSIA
+    4278294U,	// SRSIA_UPD
+    4278363U,	// SRSIB
+    4278318U,	// SRSIB_UPD
+    2667125U,	// SSAT
+    2681322U,	// SSAT16
+    2684094U,	// SSAX
+    2681270U,	// SSUB16
+    2681371U,	// SSUB8
+    1552590729U,	// STC2L_OFFSET
+    1619699593U,	// STC2L_OPTION
+    1619699593U,	// STC2L_POST
+    9561993U,	// STC2L_PRE
+    1552589369U,	// STC2_OFFSET
+    1619698233U,	// STC2_OPTION
+    1619698233U,	// STC2_POST
+    9560633U,	// STC2_PRE
+    1277734751U,	// STCL_OFFSET
+    1277734751U,	// STCL_OPTION
+    1277734751U,	// STCL_POST
+    1009307487U,	// STCL_PRE
+    1277734194U,	// STC_OFFSET
+    1277734194U,	// STC_OPTION
+    1277734194U,	// STC_POST
+    1009306930U,	// STC_PRE
+    2650152U,	// STL
+    2649113U,	// STLB
+    2684217U,	// STLEX
+    2682095U,	// STLEXB
+    2682290U,	// STLEXD
+    2682591U,	// STLEXH
+    2649692U,	// STLH
+    2730730U,	// STMDA
+    875064042U,	// STMDA_UPD
+    2730986U,	// STMDB
+    875064298U,	// STMDB_UPD
+    2732142U,	// STMIA
+    875065454U,	// STMIA_UPD
+    2731004U,	// STMIB
+    875064316U,	// STMIB_UPD
+    875090598U,	// STRBT_POST_IMM
+    875090598U,	// STRBT_POST_REG
+    875089024U,	// STRB_POST_IMM
+    875089024U,	// STRB_POST_REG
+    875080832U,	// STRB_PRE_IMM
+    875089024U,	// STRB_PRE_REG
+    2681984U,	// STRBi12
+    2665600U,	// STRBrs
+    2674074U,	// STRD
+    875171226U,	// STRD_POST
+    875171226U,	// STRD_PRE
+    2684235U,	// STREX
+    2682109U,	// STREXB
+    2682304U,	// STREXD
+    2682605U,	// STREXH
+    2666118U,	// STRH
+    875082441U,	// STRHTi
+    875090633U,	// STRHTr
+    875089542U,	// STRH_POST
+    875089542U,	// STRH_PRE
+    875090797U,	// STRT_POST_IMM
+    875090797U,	// STRT_POST_REG
+    875090432U,	// STR_POST_IMM
+    875090432U,	// STR_POST_REG
+    875082240U,	// STR_PRE_IMM
+    875090432U,	// STR_PRE_REG
+    2683392U,	// STRi12
+    2667008U,	// STRrs
+    2632901U,	// SUBri
+    2632901U,	// SUBrr
+    2690245U,	// SUBrsi
+    76997U,	// SUBrsr
+    2731318U,	// SVC
+    2683268U,	// SWP
+    2681972U,	// SWPB
+    2665398U,	// SXTAB
+    2664832U,	// SXTAB16
+    2666022U,	// SXTAH
+    2682041U,	// SXTB
+    2681232U,	// SXTB16
+    2682552U,	// SXTH
+    2650514U,	// TEQri
+    2650514U,	// TEQrr
+    2683282U,	// TEQrsi
+    2666898U,	// TEQrsr
+    4355U,	// TRAP
+    4355U,	// TRAPNaCl
+    296743U,	// TSB
+    2651000U,	// TSTri
+    2651000U,	// TSTrr
+    2683768U,	// TSTrsi
+    2667384U,	// TSTrsr
+    2681315U,	// UADD16
+    2681416U,	// UADD8
+    2684353U,	// UASX
+    2667862U,	// UBFX
+    4278107U,	// UDF
+    2683939U,	// UDIV
+    2681292U,	// UHADD16
+    2681396U,	// UHADD8
+    2684336U,	// UHASX
+    2684082U,	// UHSAX
+    2681254U,	// UHSUB16
+    2681357U,	// UHSUB8
+    2756386U,	// UMAAL
+    290627U,	// UMLAL
+    2691049U,	// UMULL
+    2681300U,	// UQADD16
+    2681403U,	// UQADD8
+    2684342U,	// UQASX
+    2684088U,	// UQSAX
+    2681262U,	// UQSUB16
+    2681364U,	// UQSUB8
+    2681383U,	// USAD8
+    2664959U,	// USADA8
+    2667130U,	// USAT
+    2681329U,	// USAT16
+    2684099U,	// USAX
+    2681277U,	// USUB16
+    2681377U,	// USUB8
+    2665404U,	// UXTAB
+    2664840U,	// UXTAB16
+    2666028U,	// UXTAH
+    2682046U,	// UXTB
+    2681239U,	// UXTB16
+    2682557U,	// UXTH
+    11579176U,	// VABALsv2i64
+    11054888U,	// VABALsv4i32
+    12103464U,	// VABALsv8i16
+    13152040U,	// VABALuv2i64
+    12627752U,	// VABALuv4i32
+    13676328U,	// VABALuv8i16
+    12102345U,	// VABAsv16i8
+    11578057U,	// VABAsv2i32
+    11053769U,	// VABAsv4i16
+    11578057U,	// VABAsv4i32
+    11053769U,	// VABAsv8i16
+    12102345U,	// VABAsv8i8
+    13675209U,	// VABAuv16i8
+    13150921U,	// VABAuv2i32
+    12626633U,	// VABAuv4i16
+    13150921U,	// VABAuv4i32
+    12626633U,	// VABAuv8i16
+    13675209U,	// VABAuv8i8
+    11595620U,	// VABDLsv2i64
+    11071332U,	// VABDLsv4i32
+    12119908U,	// VABDLsv8i16
+    13168484U,	// VABDLuv2i64
+    12644196U,	// VABDLuv4i32
+    13692772U,	// VABDLuv8i16
+    7925062U,	// VABDfd
+    7925062U,	// VABDfq
+    7400774U,	// VABDhd
+    7400774U,	// VABDhq
+    12119366U,	// VABDsv16i8
+    11595078U,	// VABDsv2i32
+    11070790U,	// VABDsv4i16
+    11595078U,	// VABDsv4i32
+    11070790U,	// VABDsv8i16
+    12119366U,	// VABDsv8i8
+    13692230U,	// VABDuv16i8
+    13167942U,	// VABDuv2i32
+    12643654U,	// VABDuv4i16
+    13167942U,	// VABDuv4i32
+    12643654U,	// VABDuv8i16
+    13692230U,	// VABDuv8i8
+    1147695644U,	// VABSD
+    7369244U,	// VABSH
+    7893532U,	// VABSS
+    7893532U,	// VABSfd
+    7893532U,	// VABSfq
+    7369244U,	// VABShd
+    7369244U,	// VABShq
+    12087836U,	// VABSv16i8
+    11563548U,	// VABSv2i32
+    11039260U,	// VABSv4i16
+    11563548U,	// VABSv4i32
+    11039260U,	// VABSv8i16
+    12087836U,	// VABSv8i8
+    7925191U,	// VACGEfd
+    7925191U,	// VACGEfq
+    7400903U,	// VACGEhd
+    7400903U,	// VACGEhq
+    7926456U,	// VACGTfd
+    7926456U,	// VACGTfq
+    7402168U,	// VACGThd
+    7402168U,	// VACGThq
+    1147727223U,	// VADDD
+    7400823U,	// VADDH
+    895545487U,	// VADDHNv2i32
+    14217359U,	// VADDHNv4i16
+    14741647U,	// VADDHNv8i8
+    11595633U,	// VADDLsv2i64
+    11071345U,	// VADDLsv4i32
+    12119921U,	// VADDLsv8i16
+    13168497U,	// VADDLuv2i64
+    12644209U,	// VADDLuv4i32
+    13692785U,	// VADDLuv8i16
+    7925111U,	// VADDS
+    11596891U,	// VADDWsv2i64
+    11072603U,	// VADDWsv4i32
+    12121179U,	// VADDWsv8i16
+    13169755U,	// VADDWuv2i64
+    12645467U,	// VADDWuv4i32
+    13694043U,	// VADDWuv8i16
+    7925111U,	// VADDfd
+    7925111U,	// VADDfq
+    7400823U,	// VADDhd
+    7400823U,	// VADDhq
+    15265143U,	// VADDv16i8
+    895544695U,	// VADDv1i64
+    14216567U,	// VADDv2i32
+    895544695U,	// VADDv2i64
+    14740855U,	// VADDv4i16
+    14216567U,	// VADDv4i32
+    14740855U,	// VADDv8i16
+    15265143U,	// VADDv8i8
+    2682254U,	// VANDd
+    2682254U,	// VANDq
+    808543686U,	// VBF16MALBQ
+    808543686U,	// VBF16MALBQI
+    808543698U,	// VBF16MALTQ
+    808543698U,	// VBF16MALTQI
+    2682134U,	// VBICd
+    14216470U,	// VBICiv2i32
+    14740758U,	// VBICiv4i16
+    14216470U,	// VBICiv4i32
+    14740758U,	// VBICiv8i16
+    2682134U,	// VBICq
+    2665967U,	// VBIFd
+    2665967U,	// VBIFq
+    2667227U,	// VBITd
+    2667227U,	// VBITq
+    2666517U,	// VBSLd
+    2666517U,	// VBSLq
+    0U,	// VBSPd
+    0U,	// VBSPq
+    875643287U,	// VCADDv2f32
+    875644160U,	// VCADDv4f16
+    875643287U,	// VCADDv4f32
+    875644160U,	// VCADDv8f16
+    7926157U,	// VCEQfd
+    7926157U,	// VCEQfq
+    7401869U,	// VCEQhd
+    7401869U,	// VCEQhq
+    15266189U,	// VCEQv16i8
+    14217613U,	// VCEQv2i32
+    14741901U,	// VCEQv4i16
+    14217613U,	// VCEQv4i32
+    14741901U,	// VCEQv8i16
+    15266189U,	// VCEQv8i8
+    15233421U,	// VCEQzv16i8
+    7893389U,	// VCEQzv2f32
+    14184845U,	// VCEQzv2i32
+    7369101U,	// VCEQzv4f16
+    7893389U,	// VCEQzv4f32
+    14709133U,	// VCEQzv4i16
+    14184845U,	// VCEQzv4i32
+    7369101U,	// VCEQzv8f16
+    14709133U,	// VCEQzv8i16
+    15233421U,	// VCEQzv8i8
+    7925197U,	// VCGEfd
+    7925197U,	// VCGEfq
+    7400909U,	// VCGEhd
+    7400909U,	// VCGEhq
+    12119501U,	// VCGEsv16i8
+    11595213U,	// VCGEsv2i32
+    11070925U,	// VCGEsv4i16
+    11595213U,	// VCGEsv4i32
+    11070925U,	// VCGEsv8i16
+    12119501U,	// VCGEsv8i8
+    13692365U,	// VCGEuv16i8
+    13168077U,	// VCGEuv2i32
+    12643789U,	// VCGEuv4i16
+    13168077U,	// VCGEuv4i32
+    12643789U,	// VCGEuv8i16
+    13692365U,	// VCGEuv8i8
+    12086733U,	// VCGEzv16i8
+    7892429U,	// VCGEzv2f32
+    11562445U,	// VCGEzv2i32
+    7368141U,	// VCGEzv4f16
+    7892429U,	// VCGEzv4f32
+    11038157U,	// VCGEzv4i16
+    11562445U,	// VCGEzv4i32
+    7368141U,	// VCGEzv8f16
+    11038157U,	// VCGEzv8i16
+    12086733U,	// VCGEzv8i8
+    7926462U,	// VCGTfd
+    7926462U,	// VCGTfq
+    7402174U,	// VCGThd
+    7402174U,	// VCGThq
+    12120766U,	// VCGTsv16i8
+    11596478U,	// VCGTsv2i32
+    11072190U,	// VCGTsv4i16
+    11596478U,	// VCGTsv4i32
+    11072190U,	// VCGTsv8i16
+    12120766U,	// VCGTsv8i8
+    13693630U,	// VCGTuv16i8
+    13169342U,	// VCGTuv2i32
+    12645054U,	// VCGTuv4i16
+    13169342U,	// VCGTuv4i32
+    12645054U,	// VCGTuv8i16
+    13693630U,	// VCGTuv8i8
+    12087998U,	// VCGTzv16i8
+    7893694U,	// VCGTzv2f32
+    11563710U,	// VCGTzv2i32
+    7369406U,	// VCGTzv4f16
+    7893694U,	// VCGTzv4f32
+    11039422U,	// VCGTzv4i16
+    11563710U,	// VCGTzv4i32
+    7369406U,	// VCGTzv8f16
+    11039422U,	// VCGTzv8i16
+    12087998U,	// VCGTzv8i8
+    12086738U,	// VCLEzv16i8
+    7892434U,	// VCLEzv2f32
+    11562450U,	// VCLEzv2i32
+    7368146U,	// VCLEzv4f16
+    7892434U,	// VCLEzv4f32
+    11038162U,	// VCLEzv4i16
+    11562450U,	// VCLEzv4i32
+    7368146U,	// VCLEzv8f16
+    11038162U,	// VCLEzv8i16
+    12086738U,	// VCLEzv8i8
+    12087846U,	// VCLSv16i8
+    11563558U,	// VCLSv2i32
+    11039270U,	// VCLSv4i16
+    11563558U,	// VCLSv4i32
+    11039270U,	// VCLSv8i16
+    12087846U,	// VCLSv8i8
+    12088032U,	// VCLTzv16i8
+    7893728U,	// VCLTzv2f32
+    11563744U,	// VCLTzv2i32
+    7369440U,	// VCLTzv4f16
+    7893728U,	// VCLTzv4f32
+    11039456U,	// VCLTzv4i16
+    11563744U,	// VCLTzv4i32
+    7369440U,	// VCLTzv8f16
+    11039456U,	// VCLTzv8i16
+    12088032U,	// VCLTzv8i8
+    15234547U,	// VCLZv16i8
+    14185971U,	// VCLZv2i32
+    14710259U,	// VCLZv4i16
+    14185971U,	// VCLZv4i32
+    14710259U,	// VCLZv8i16
+    15234547U,	// VCLZv8i8
+    808534400U,	// VCMLAv2f32
+    808534400U,	// VCMLAv2f32_indexed
+    808535273U,	// VCMLAv4f16
+    808535273U,	// VCMLAv4f16_indexed
+    808534400U,	// VCMLAv4f32
+    808534400U,	// VCMLAv4f32_indexed
+    808535273U,	// VCMLAv8f16
+    808535273U,	// VCMLAv8f16_indexed
+    1147695377U,	// VCMPD
+    1147694558U,	// VCMPED
+    7368158U,	// VCMPEH
+    7892446U,	// VCMPES
+    2087300574U,	// VCMPEZD
+    7450078U,	// VCMPEZH
+    7974366U,	// VCMPEZS
+    7368977U,	// VCMPH
+    7893265U,	// VCMPS
+    2087301393U,	// VCMPZD
+    7450897U,	// VCMPZH
+    7975185U,	// VCMPZS
+    1602307U,	// VCNTd
+    1602307U,	// VCNTq
+    875643144U,	// VCVTANSDf
+    875644017U,	// VCVTANSDh
+    875643144U,	// VCVTANSQf
+    875644017U,	// VCVTANSQh
+    875643204U,	// VCVTANUDf
+    875644077U,	// VCVTANUDh
+    875643204U,	// VCVTANUQf
+    875644077U,	// VCVTANUQh
+    875643506U,	// VCVTASD
+    875643897U,	// VCVTASH
+    875643144U,	// VCVTASS
+    875643566U,	// VCVTAUD
+    875643957U,	// VCVTAUH
+    875643204U,	// VCVTAUS
+    25750707U,	// VCVTBDH
+    26242227U,	// VCVTBHD
+    17853619U,	// VCVTBHS
+    821619891U,	// VCVTBSH
+    26768296U,	// VCVTDS
+    875643159U,	// VCVTMNSDf
+    875644032U,	// VCVTMNSDh
+    875643159U,	// VCVTMNSQf
+    875644032U,	// VCVTMNSQh
+    875643219U,	// VCVTMNUDf
+    875644092U,	// VCVTMNUDh
+    875643219U,	// VCVTMNUQf
+    875644092U,	// VCVTMNUQh
+    875643521U,	// VCVTMSD
+    875643912U,	// VCVTMSH
+    875643159U,	// VCVTMSS
+    875643581U,	// VCVTMUD
+    875643972U,	// VCVTMUH
+    875643219U,	// VCVTMUS
+    875643174U,	// VCVTNNSDf
+    875644047U,	// VCVTNNSDh
+    875643174U,	// VCVTNNSQf
+    875644047U,	// VCVTNNSQh
+    875643234U,	// VCVTNNUDf
+    875644107U,	// VCVTNNUDh
+    875643234U,	// VCVTNNUQf
+    875644107U,	// VCVTNNUQh
+    875643536U,	// VCVTNSD
+    875643927U,	// VCVTNSH
+    875643174U,	// VCVTNSS
+    875643596U,	// VCVTNUD
+    875643987U,	// VCVTNUH
+    875643234U,	// VCVTNUS
+    875643189U,	// VCVTPNSDf
+    875644062U,	// VCVTPNSDh
+    875643189U,	// VCVTPNSQf
+    875644062U,	// VCVTPNSQh
+    875643249U,	// VCVTPNUDf
+    875644122U,	// VCVTPNUDh
+    875643249U,	// VCVTPNUQf
+    875644122U,	// VCVTPNUQh
+    875643551U,	// VCVTPSD
+    875643942U,	// VCVTPSH
+    875643189U,	// VCVTPSS
+    875643611U,	// VCVTPUD
+    875644002U,	// VCVTPUH
+    875643249U,	// VCVTPUS
+    27292584U,	// VCVTSD
+    25752470U,	// VCVTTDH
+    26243990U,	// VCVTTHD
+    17855382U,	// VCVTTHS
+    821621654U,	// VCVTTSH
+    888697768U,	// VCVTf2h
+    1093694376U,	// VCVTf2sd
+    1093694376U,	// VCVTf2sq
+    1094742952U,	// VCVTf2ud
+    1094742952U,	// VCVTf2uq
+    1160836008U,	// VCVTf2xsd
+    1160836008U,	// VCVTf2xsq
+    1161884584U,	// VCVTf2xud
+    1161884584U,	// VCVTf2xuq
+    17855400U,	// VCVTh2f
+    1093170088U,	// VCVTh2sd
+    1093170088U,	// VCVTh2sq
+    1094218664U,	// VCVTh2ud
+    1094218664U,	// VCVTh2uq
+    1160311720U,	// VCVTh2xsd
+    1160311720U,	// VCVTh2xsq
+    1161360296U,	// VCVTh2xud
+    1161360296U,	// VCVTh2xuq
+    1092121512U,	// VCVTs2fd
+    1092121512U,	// VCVTs2fq
+    1090548648U,	// VCVTs2hd
+    1090548648U,	// VCVTs2hq
+    1092645800U,	// VCVTu2fd
+    1092645800U,	// VCVTu2fq
+    1091072936U,	// VCVTu2hd
+    1091072936U,	// VCVTu2hq
+    1159263144U,	// VCVTxs2fd
+    1159263144U,	// VCVTxs2fq
+    1157690280U,	// VCVTxs2hd
+    1157690280U,	// VCVTxs2hq
+    1159787432U,	// VCVTxu2fd
+    1159787432U,	// VCVTxu2fq
+    1158214568U,	// VCVTxu2hd
+    1158214568U,	// VCVTxu2hq
+    1147728936U,	// VDIVD
+    7402536U,	// VDIVH
+    7926824U,	// VDIVS
+    553328U,	// VDUP16d
+    553328U,	// VDUP16q
+    1077616U,	// VDUP32d
+    1077616U,	// VDUP32q
+    1601904U,	// VDUP8d
+    1601904U,	// VDUP8q
+    586096U,	// VDUPLN16d
+    586096U,	// VDUPLN16q
+    1110384U,	// VDUPLN32d
+    1110384U,	// VDUPLN32q
+    1634672U,	// VDUPLN8d
+    1634672U,	// VDUPLN8q
+    2683343U,	// VEORd
+    2683343U,	// VEORq
+    570304U,	// VEXTd16
+    1094592U,	// VEXTd32
+    1618880U,	// VEXTd8
+    570304U,	// VEXTq16
+    1094592U,	// VEXTq32
+    15774656U,	// VEXTq64
+    1618880U,	// VEXTq8
+    1147710265U,	// VFMAD
+    7383865U,	// VFMAH
+    875644183U,	// VFMALD
+    875644183U,	// VFMALDI
+    875644183U,	// VFMALQ
+    875644183U,	// VFMALQI
+    7908153U,	// VFMAS
+    7908153U,	// VFMAfd
+    7908153U,	// VFMAfq
+    7383865U,	// VFMAhd
+    7383865U,	// VFMAhq
+    1147712060U,	// VFMSD
+    7385660U,	// VFMSH
+    875644194U,	// VFMSLD
+    875644194U,	// VFMSLDI
+    875644194U,	// VFMSLQ
+    875644194U,	// VFMSLQI
+    7909948U,	// VFMSS
+    7909948U,	// VFMSfd
+    7909948U,	// VFMSfq
+    7385660U,	// VFMShd
+    7385660U,	// VFMShq
+    1147710270U,	// VFNMAD
+    7383870U,	// VFNMAH
+    7908158U,	// VFNMAS
+    1147712065U,	// VFNMSD
+    7385665U,	// VFNMSH
+    7909953U,	// VFNMSS
+    875643662U,	// VFP_VMAXNMD
+    875644217U,	// VFP_VMAXNMH
+    875643322U,	// VFP_VMAXNMS
+    875643650U,	// VFP_VMINNMD
+    875644205U,	// VFP_VMINNMH
+    875643310U,	// VFP_VMINNMS
+    1111114U,	// VGETLNi32
+    11072586U,	// VGETLNs16
+    12121162U,	// VGETLNs8
+    12645450U,	// VGETLNu16
+    13694026U,	// VGETLNu8
+    12119397U,	// VHADDsv16i8
+    11595109U,	// VHADDsv2i32
+    11070821U,	// VHADDsv4i16
+    11595109U,	// VHADDsv4i32
+    11070821U,	// VHADDsv8i16
+    12119397U,	// VHADDsv8i8
+    13692261U,	// VHADDuv16i8
+    13167973U,	// VHADDuv2i32
+    12643685U,	// VHADDuv4i16
+    13167973U,	// VHADDuv4i32
+    12643685U,	// VHADDuv8i16
+    13692261U,	// VHADDuv8i8
+    12119241U,	// VHSUBsv16i8
+    11594953U,	// VHSUBsv2i32
+    11070665U,	// VHSUBsv4i16
+    11594953U,	// VHSUBsv4i32
+    11070665U,	// VHSUBsv8i16
+    12119241U,	// VHSUBsv8i8
+    13692105U,	// VHSUBuv16i8
+    13167817U,	// VHSUBuv2i32
+    12643529U,	// VHSUBuv4i16
+    13167817U,	// VHSUBuv4i32
+    12643529U,	// VHSUBuv8i16
+    13692105U,	// VHSUBuv8i8
+    808535413U,	// VINSH
+    1101558690U,	// VJCVT
+    2148067588U,	// VLD1DUPd16
+    2148051204U,	// VLD1DUPd16wb_fixed
+    2148059396U,	// VLD1DUPd16wb_register
+    2148591876U,	// VLD1DUPd32
+    2148575492U,	// VLD1DUPd32wb_fixed
+    2148583684U,	// VLD1DUPd32wb_register
+    2149116164U,	// VLD1DUPd8
+    2149099780U,	// VLD1DUPd8wb_fixed
+    2149107972U,	// VLD1DUPd8wb_register
+    2215176452U,	// VLD1DUPq16
+    2215160068U,	// VLD1DUPq16wb_fixed
+    2215168260U,	// VLD1DUPq16wb_register
+    2215700740U,	// VLD1DUPq32
+    2215684356U,	// VLD1DUPq32wb_fixed
+    2215692548U,	// VLD1DUPq32wb_register
+    2216225028U,	// VLD1DUPq8
+    2216208644U,	// VLD1DUPq8wb_fixed
+    2216216836U,	// VLD1DUPq8wb_register
+    28363012U,	// VLD1LNd16
+    28616964U,	// VLD1LNd16_UPD
+    28887300U,	// VLD1LNd32
+    29141252U,	// VLD1LNd32_UPD
+    29411588U,	// VLD1LNd8
+    29665540U,	// VLD1LNd8_UPD
     0U,	// VLD1LNq16Pseudo
     0U,	// VLD1LNq16Pseudo_UPD
     0U,	// VLD1LNq32Pseudo
     0U,	// VLD1LNq32Pseudo_UPD
     0U,	// VLD1LNq8Pseudo
     0U,	// VLD1LNq8Pseudo_UPD
-    3707926126U,	// VLD1d16
-    3355604590U,	// VLD1d16Q
+    2282285316U,	// VLD1d16
+    537454852U,	// VLD1d16Q
     0U,	// VLD1d16QPseudo
-    134370926U,	// VLD1d16Qwb_fixed
-    134375022U,	// VLD1d16Qwb_register
-    3288495726U,	// VLD1d16T
+    0U,	// VLD1d16QPseudoWB_fixed
+    0U,	// VLD1d16QPseudoWB_register
+    537438468U,	// VLD1d16Qwb_fixed
+    537446660U,	// VLD1d16Qwb_register
+    269019396U,	// VLD1d16T
     0U,	// VLD1d16TPseudo
-    67262062U,	// VLD1d16Twb_fixed
-    67266158U,	// VLD1d16Twb_register
-    486692462U,	// VLD1d16wb_fixed
-    486696558U,	// VLD1d16wb_register
-    3708057198U,	// VLD1d32
-    3355735662U,	// VLD1d32Q
+    0U,	// VLD1d16TPseudoWB_fixed
+    0U,	// VLD1d16TPseudoWB_register
+    269003012U,	// VLD1d16Twb_fixed
+    269011204U,	// VLD1d16Twb_register
+    2282268932U,	// VLD1d16wb_fixed
+    2282277124U,	// VLD1d16wb_register
+    2282809604U,	// VLD1d32
+    537979140U,	// VLD1d32Q
     0U,	// VLD1d32QPseudo
-    134501998U,	// VLD1d32Qwb_fixed
-    134506094U,	// VLD1d32Qwb_register
-    3288626798U,	// VLD1d32T
+    0U,	// VLD1d32QPseudoWB_fixed
+    0U,	// VLD1d32QPseudoWB_register
+    537962756U,	// VLD1d32Qwb_fixed
+    537970948U,	// VLD1d32Qwb_register
+    269543684U,	// VLD1d32T
     0U,	// VLD1d32TPseudo
-    67393134U,	// VLD1d32Twb_fixed
-    67397230U,	// VLD1d32Twb_register
-    486823534U,	// VLD1d32wb_fixed
-    486827630U,	// VLD1d32wb_register
-    3713037934U,	// VLD1d64
-    3360716398U,	// VLD1d64Q
+    0U,	// VLD1d32TPseudoWB_fixed
+    0U,	// VLD1d32TPseudoWB_register
+    269527300U,	// VLD1d32Twb_fixed
+    269535492U,	// VLD1d32Twb_register
+    2282793220U,	// VLD1d32wb_fixed
+    2282801412U,	// VLD1d32wb_register
+    2297489668U,	// VLD1d64
+    552659204U,	// VLD1d64Q
     0U,	// VLD1d64QPseudo
     0U,	// VLD1d64QPseudoWB_fixed
     0U,	// VLD1d64QPseudoWB_register
-    139482734U,	// VLD1d64Qwb_fixed
-    139486830U,	// VLD1d64Qwb_register
-    3293607534U,	// VLD1d64T
+    552642820U,	// VLD1d64Qwb_fixed
+    552651012U,	// VLD1d64Qwb_register
+    284223748U,	// VLD1d64T
     0U,	// VLD1d64TPseudo
     0U,	// VLD1d64TPseudoWB_fixed
     0U,	// VLD1d64TPseudoWB_register
-    72373870U,	// VLD1d64Twb_fixed
-    72377966U,	// VLD1d64Twb_register
-    491804270U,	// VLD1d64wb_fixed
-    491808366U,	// VLD1d64wb_register
-    3708188270U,	// VLD1d8
-    3355866734U,	// VLD1d8Q
+    284207364U,	// VLD1d64Twb_fixed
+    284215556U,	// VLD1d64Twb_register
+    2297473284U,	// VLD1d64wb_fixed
+    2297481476U,	// VLD1d64wb_register
+    2283333892U,	// VLD1d8
+    538503428U,	// VLD1d8Q
     0U,	// VLD1d8QPseudo
-    134633070U,	// VLD1d8Qwb_fixed
-    134637166U,	// VLD1d8Qwb_register
-    3288757870U,	// VLD1d8T
+    0U,	// VLD1d8QPseudoWB_fixed
+    0U,	// VLD1d8QPseudoWB_register
+    538487044U,	// VLD1d8Qwb_fixed
+    538495236U,	// VLD1d8Qwb_register
+    270067972U,	// VLD1d8T
     0U,	// VLD1d8TPseudo
-    67524206U,	// VLD1d8Twb_fixed
-    67528302U,	// VLD1d8Twb_register
-    486954606U,	// VLD1d8wb_fixed
-    486958702U,	// VLD1d8wb_register
-    3724703342U,	// VLD1q16
+    0U,	// VLD1d8TPseudoWB_fixed
+    0U,	// VLD1d8TPseudoWB_register
+    270051588U,	// VLD1d8Twb_fixed
+    270059780U,	// VLD1d8Twb_register
+    2283317508U,	// VLD1d8wb_fixed
+    2283325700U,	// VLD1d8wb_register
+    2349394180U,	// VLD1q16
     0U,	// VLD1q16HighQPseudo
+    0U,	// VLD1q16HighQPseudo_UPD
     0U,	// VLD1q16HighTPseudo
+    0U,	// VLD1q16HighTPseudo_UPD
     0U,	// VLD1q16LowQPseudo_UPD
     0U,	// VLD1q16LowTPseudo_UPD
-    503469678U,	// VLD1q16wb_fixed
-    503473774U,	// VLD1q16wb_register
-    3724834414U,	// VLD1q32
+    2349377796U,	// VLD1q16wb_fixed
+    2349385988U,	// VLD1q16wb_register
+    2349918468U,	// VLD1q32
     0U,	// VLD1q32HighQPseudo
+    0U,	// VLD1q32HighQPseudo_UPD
     0U,	// VLD1q32HighTPseudo
+    0U,	// VLD1q32HighTPseudo_UPD
     0U,	// VLD1q32LowQPseudo_UPD
     0U,	// VLD1q32LowTPseudo_UPD
-    503600750U,	// VLD1q32wb_fixed
-    503604846U,	// VLD1q32wb_register
-    3729815150U,	// VLD1q64
+    2349902084U,	// VLD1q32wb_fixed
+    2349910276U,	// VLD1q32wb_register
+    2364598532U,	// VLD1q64
     0U,	// VLD1q64HighQPseudo
+    0U,	// VLD1q64HighQPseudo_UPD
     0U,	// VLD1q64HighTPseudo
+    0U,	// VLD1q64HighTPseudo_UPD
     0U,	// VLD1q64LowQPseudo_UPD
     0U,	// VLD1q64LowTPseudo_UPD
-    508581486U,	// VLD1q64wb_fixed
-    508585582U,	// VLD1q64wb_register
-    3724965486U,	// VLD1q8
+    2364582148U,	// VLD1q64wb_fixed
+    2364590340U,	// VLD1q64wb_register
+    2350442756U,	// VLD1q8
     0U,	// VLD1q8HighQPseudo
+    0U,	// VLD1q8HighQPseudo_UPD
     0U,	// VLD1q8HighTPseudo
+    0U,	// VLD1q8HighTPseudo_UPD
     0U,	// VLD1q8LowQPseudo_UPD
     0U,	// VLD1q8LowTPseudo_UPD
-    503731822U,	// VLD1q8wb_fixed
-    503735918U,	// VLD1q8wb_register
-    3691148954U,	// VLD2DUPd16
-    469915290U,	// VLD2DUPd16wb_fixed
-    469919386U,	// VLD2DUPd16wb_register
-    3741480602U,	// VLD2DUPd16x2
-    520246938U,	// VLD2DUPd16x2wb_fixed
-    520251034U,	// VLD2DUPd16x2wb_register
-    3691280026U,	// VLD2DUPd32
-    470046362U,	// VLD2DUPd32wb_fixed
-    470050458U,	// VLD2DUPd32wb_register
-    3741611674U,	// VLD2DUPd32x2
-    520378010U,	// VLD2DUPd32x2wb_fixed
-    520382106U,	// VLD2DUPd32x2wb_register
-    3691411098U,	// VLD2DUPd8
-    470177434U,	// VLD2DUPd8wb_fixed
-    470181530U,	// VLD2DUPd8wb_register
-    3741742746U,	// VLD2DUPd8x2
-    520509082U,	// VLD2DUPd8x2wb_fixed
-    520513178U,	// VLD2DUPd8x2wb_register
+    2350426372U,	// VLD1q8wb_fixed
+    2350434564U,	// VLD1q8wb_register
+    2215176501U,	// VLD2DUPd16
+    2215160117U,	// VLD2DUPd16wb_fixed
+    2215168309U,	// VLD2DUPd16wb_register
+    2416503093U,	// VLD2DUPd16x2
+    2416486709U,	// VLD2DUPd16x2wb_fixed
+    2416494901U,	// VLD2DUPd16x2wb_register
+    2215700789U,	// VLD2DUPd32
+    2215684405U,	// VLD2DUPd32wb_fixed
+    2215692597U,	// VLD2DUPd32wb_register
+    2417027381U,	// VLD2DUPd32x2
+    2417010997U,	// VLD2DUPd32x2wb_fixed
+    2417019189U,	// VLD2DUPd32x2wb_register
+    2216225077U,	// VLD2DUPd8
+    2216208693U,	// VLD2DUPd8wb_fixed
+    2216216885U,	// VLD2DUPd8wb_register
+    2417551669U,	// VLD2DUPd8x2
+    2417535285U,	// VLD2DUPd8x2wb_fixed
+    2417543477U,	// VLD2DUPd8x2wb_register
     0U,	// VLD2DUPq16EvenPseudo
     0U,	// VLD2DUPq16OddPseudo
+    0U,	// VLD2DUPq16OddPseudoWB_fixed
+    0U,	// VLD2DUPq16OddPseudoWB_register
     0U,	// VLD2DUPq32EvenPseudo
     0U,	// VLD2DUPq32OddPseudo
+    0U,	// VLD2DUPq32OddPseudoWB_fixed
+    0U,	// VLD2DUPq32OddPseudoWB_register
     0U,	// VLD2DUPq8EvenPseudo
     0U,	// VLD2DUPq8OddPseudo
-    1079350938U,	// VLD2LNd16
+    0U,	// VLD2DUPq8OddPseudoWB_fixed
+    0U,	// VLD2DUPq8OddPseudoWB_register
+    28617013U,	// VLD2LNd16
     0U,	// VLD2LNd16Pseudo
     0U,	// VLD2LNd16Pseudo_UPD
-    1079355034U,	// VLD2LNd16_UPD
-    1079482010U,	// VLD2LNd32
+    28625205U,	// VLD2LNd16_UPD
+    29141301U,	// VLD2LNd32
     0U,	// VLD2LNd32Pseudo
     0U,	// VLD2LNd32Pseudo_UPD
-    1079486106U,	// VLD2LNd32_UPD
-    1079613082U,	// VLD2LNd8
+    29149493U,	// VLD2LNd32_UPD
+    29665589U,	// VLD2LNd8
     0U,	// VLD2LNd8Pseudo
     0U,	// VLD2LNd8Pseudo_UPD
-    1079617178U,	// VLD2LNd8_UPD
-    1079350938U,	// VLD2LNq16
+    29673781U,	// VLD2LNd8_UPD
+    28617013U,	// VLD2LNq16
     0U,	// VLD2LNq16Pseudo
     0U,	// VLD2LNq16Pseudo_UPD
-    1079355034U,	// VLD2LNq16_UPD
-    1079482010U,	// VLD2LNq32
+    28625205U,	// VLD2LNq16_UPD
+    29141301U,	// VLD2LNq32
     0U,	// VLD2LNq32Pseudo
     0U,	// VLD2LNq32Pseudo_UPD
-    1079486106U,	// VLD2LNq32_UPD
-    3758257818U,	// VLD2b16
-    537024154U,	// VLD2b16wb_fixed
-    537028250U,	// VLD2b16wb_register
-    3758388890U,	// VLD2b32
-    537155226U,	// VLD2b32wb_fixed
-    537159322U,	// VLD2b32wb_register
-    3758519962U,	// VLD2b8
-    537286298U,	// VLD2b8wb_fixed
-    537290394U,	// VLD2b8wb_register
-    3724703386U,	// VLD2d16
-    503469722U,	// VLD2d16wb_fixed
-    503473818U,	// VLD2d16wb_register
-    3724834458U,	// VLD2d32
-    503600794U,	// VLD2d32wb_fixed
-    503604890U,	// VLD2d32wb_register
-    3724965530U,	// VLD2d8
-    503731866U,	// VLD2d8wb_fixed
-    503735962U,	// VLD2d8wb_register
-    3355604634U,	// VLD2q16
+    29149493U,	// VLD2LNq32_UPD
+    2483611957U,	// VLD2b16
+    2483595573U,	// VLD2b16wb_fixed
+    2483603765U,	// VLD2b16wb_register
+    2484136245U,	// VLD2b32
+    2484119861U,	// VLD2b32wb_fixed
+    2484128053U,	// VLD2b32wb_register
+    2484660533U,	// VLD2b8
+    2484644149U,	// VLD2b8wb_fixed
+    2484652341U,	// VLD2b8wb_register
+    2349394229U,	// VLD2d16
+    2349377845U,	// VLD2d16wb_fixed
+    2349386037U,	// VLD2d16wb_register
+    2349918517U,	// VLD2d32
+    2349902133U,	// VLD2d32wb_fixed
+    2349910325U,	// VLD2d32wb_register
+    2350442805U,	// VLD2d8
+    2350426421U,	// VLD2d8wb_fixed
+    2350434613U,	// VLD2d8wb_register
+    537454901U,	// VLD2q16
     0U,	// VLD2q16Pseudo
     0U,	// VLD2q16PseudoWB_fixed
     0U,	// VLD2q16PseudoWB_register
-    134370970U,	// VLD2q16wb_fixed
-    134375066U,	// VLD2q16wb_register
-    3355735706U,	// VLD2q32
+    537438517U,	// VLD2q16wb_fixed
+    537446709U,	// VLD2q16wb_register
+    537979189U,	// VLD2q32
     0U,	// VLD2q32Pseudo
     0U,	// VLD2q32PseudoWB_fixed
     0U,	// VLD2q32PseudoWB_register
-    134502042U,	// VLD2q32wb_fixed
-    134506138U,	// VLD2q32wb_register
-    3355866778U,	// VLD2q8
+    537962805U,	// VLD2q32wb_fixed
+    537970997U,	// VLD2q32wb_register
+    538503477U,	// VLD2q8
     0U,	// VLD2q8Pseudo
     0U,	// VLD2q8PseudoWB_fixed
     0U,	// VLD2q8PseudoWB_register
-    134633114U,	// VLD2q8wb_fixed
-    134637210U,	// VLD2q8wb_register
-    2153014970U,	// VLD3DUPd16
+    538487093U,	// VLD2q8wb_fixed
+    538495285U,	// VLD2q8wb_register
+    28363098U,	// VLD3DUPd16
     0U,	// VLD3DUPd16Pseudo
     0U,	// VLD3DUPd16Pseudo_UPD
-    2153092794U,	// VLD3DUPd16_UPD
-    2153146042U,	// VLD3DUPd32
+    28617050U,	// VLD3DUPd16_UPD
+    28887386U,	// VLD3DUPd32
     0U,	// VLD3DUPd32Pseudo
     0U,	// VLD3DUPd32Pseudo_UPD
-    2153223866U,	// VLD3DUPd32_UPD
-    2153277114U,	// VLD3DUPd8
+    29141338U,	// VLD3DUPd32_UPD
+    29411674U,	// VLD3DUPd8
     0U,	// VLD3DUPd8Pseudo
     0U,	// VLD3DUPd8Pseudo_UPD
-    2153354938U,	// VLD3DUPd8_UPD
-    2153014970U,	// VLD3DUPq16
+    29665626U,	// VLD3DUPd8_UPD
+    28363098U,	// VLD3DUPq16
     0U,	// VLD3DUPq16EvenPseudo
     0U,	// VLD3DUPq16OddPseudo
-    2153092794U,	// VLD3DUPq16_UPD
-    2153146042U,	// VLD3DUPq32
+    0U,	// VLD3DUPq16OddPseudo_UPD
+    28617050U,	// VLD3DUPq16_UPD
+    28887386U,	// VLD3DUPq32
     0U,	// VLD3DUPq32EvenPseudo
     0U,	// VLD3DUPq32OddPseudo
-    2153223866U,	// VLD3DUPq32_UPD
-    2153277114U,	// VLD3DUPq8
+    0U,	// VLD3DUPq32OddPseudo_UPD
+    29141338U,	// VLD3DUPq32_UPD
+    29411674U,	// VLD3DUPq8
     0U,	// VLD3DUPq8EvenPseudo
     0U,	// VLD3DUPq8OddPseudo
-    2153354938U,	// VLD3DUPq8_UPD
-    1079355066U,	// VLD3LNd16
+    0U,	// VLD3DUPq8OddPseudo_UPD
+    29665626U,	// VLD3DUPq8_UPD
+    28625242U,	// VLD3LNd16
     0U,	// VLD3LNd16Pseudo
     0U,	// VLD3LNd16Pseudo_UPD
-    1079359162U,	// VLD3LNd16_UPD
-    1079486138U,	// VLD3LNd32
+    28633434U,	// VLD3LNd16_UPD
+    29149530U,	// VLD3LNd32
     0U,	// VLD3LNd32Pseudo
     0U,	// VLD3LNd32Pseudo_UPD
-    1079490234U,	// VLD3LNd32_UPD
-    1079617210U,	// VLD3LNd8
+    29157722U,	// VLD3LNd32_UPD
+    29673818U,	// VLD3LNd8
     0U,	// VLD3LNd8Pseudo
     0U,	// VLD3LNd8Pseudo_UPD
-    1079621306U,	// VLD3LNd8_UPD
-    1079355066U,	// VLD3LNq16
+    29682010U,	// VLD3LNd8_UPD
+    28625242U,	// VLD3LNq16
     0U,	// VLD3LNq16Pseudo
     0U,	// VLD3LNq16Pseudo_UPD
-    1079359162U,	// VLD3LNq16_UPD
-    1079486138U,	// VLD3LNq32
+    28633434U,	// VLD3LNq16_UPD
+    29149530U,	// VLD3LNq32
     0U,	// VLD3LNq32Pseudo
     0U,	// VLD3LNq32Pseudo_UPD
-    1079490234U,	// VLD3LNq32_UPD
-    5531322U,	// VLD3d16
+    29157722U,	// VLD3LNq32_UPD
+    28363098U,	// VLD3d16
     0U,	// VLD3d16Pseudo
     0U,	// VLD3d16Pseudo_UPD
-    5609146U,	// VLD3d16_UPD
-    5662394U,	// VLD3d32
+    28617050U,	// VLD3d16_UPD
+    28887386U,	// VLD3d32
     0U,	// VLD3d32Pseudo
     0U,	// VLD3d32Pseudo_UPD
-    5740218U,	// VLD3d32_UPD
-    5793466U,	// VLD3d8
+    29141338U,	// VLD3d32_UPD
+    29411674U,	// VLD3d8
     0U,	// VLD3d8Pseudo
     0U,	// VLD3d8Pseudo_UPD
-    5871290U,	// VLD3d8_UPD
-    5531322U,	// VLD3q16
+    29665626U,	// VLD3d8_UPD
+    28363098U,	// VLD3q16
     0U,	// VLD3q16Pseudo_UPD
-    5609146U,	// VLD3q16_UPD
+    28617050U,	// VLD3q16_UPD
     0U,	// VLD3q16oddPseudo
     0U,	// VLD3q16oddPseudo_UPD
-    5662394U,	// VLD3q32
+    28887386U,	// VLD3q32
     0U,	// VLD3q32Pseudo_UPD
-    5740218U,	// VLD3q32_UPD
+    29141338U,	// VLD3q32_UPD
     0U,	// VLD3q32oddPseudo
     0U,	// VLD3q32oddPseudo_UPD
-    5793466U,	// VLD3q8
+    29411674U,	// VLD3q8
     0U,	// VLD3q8Pseudo_UPD
-    5871290U,	// VLD3q8_UPD
+    29665626U,	// VLD3q8_UPD
     0U,	// VLD3q8oddPseudo
     0U,	// VLD3q8oddPseudo_UPD
-    2153043665U,	// VLD4DUPd16
+    28445046U,	// VLD4DUPd16
     0U,	// VLD4DUPd16Pseudo
     0U,	// VLD4DUPd16Pseudo_UPD
-    2153105105U,	// VLD4DUPd16_UPD
-    2153174737U,	// VLD4DUPd32
+    28641654U,	// VLD4DUPd16_UPD
+    28969334U,	// VLD4DUPd32
     0U,	// VLD4DUPd32Pseudo
     0U,	// VLD4DUPd32Pseudo_UPD
-    2153236177U,	// VLD4DUPd32_UPD
-    2153305809U,	// VLD4DUPd8
+    29165942U,	// VLD4DUPd32_UPD
+    29493622U,	// VLD4DUPd8
     0U,	// VLD4DUPd8Pseudo
     0U,	// VLD4DUPd8Pseudo_UPD
-    2153367249U,	// VLD4DUPd8_UPD
-    2153043665U,	// VLD4DUPq16
+    29690230U,	// VLD4DUPd8_UPD
+    28445046U,	// VLD4DUPq16
     0U,	// VLD4DUPq16EvenPseudo
     0U,	// VLD4DUPq16OddPseudo
-    2153105105U,	// VLD4DUPq16_UPD
-    2153174737U,	// VLD4DUPq32
+    0U,	// VLD4DUPq16OddPseudo_UPD
+    28641654U,	// VLD4DUPq16_UPD
+    28969334U,	// VLD4DUPq32
     0U,	// VLD4DUPq32EvenPseudo
     0U,	// VLD4DUPq32OddPseudo
-    2153236177U,	// VLD4DUPq32_UPD
-    2153305809U,	// VLD4DUPq8
+    0U,	// VLD4DUPq32OddPseudo_UPD
+    29165942U,	// VLD4DUPq32_UPD
+    29493622U,	// VLD4DUPq8
     0U,	// VLD4DUPq8EvenPseudo
     0U,	// VLD4DUPq8OddPseudo
-    2153367249U,	// VLD4DUPq8_UPD
-    1079359185U,	// VLD4LNd16
+    0U,	// VLD4DUPq8OddPseudo_UPD
+    29690230U,	// VLD4DUPq8_UPD
+    28633462U,	// VLD4LNd16
     0U,	// VLD4LNd16Pseudo
     0U,	// VLD4LNd16Pseudo_UPD
-    1079367377U,	// VLD4LNd16_UPD
-    1079490257U,	// VLD4LNd32
+    28649846U,	// VLD4LNd16_UPD
+    29157750U,	// VLD4LNd32
     0U,	// VLD4LNd32Pseudo
     0U,	// VLD4LNd32Pseudo_UPD
-    1079498449U,	// VLD4LNd32_UPD
-    1079621329U,	// VLD4LNd8
+    29174134U,	// VLD4LNd32_UPD
+    29682038U,	// VLD4LNd8
     0U,	// VLD4LNd8Pseudo
     0U,	// VLD4LNd8Pseudo_UPD
-    1079629521U,	// VLD4LNd8_UPD
-    1079359185U,	// VLD4LNq16
+    29698422U,	// VLD4LNd8_UPD
+    28633462U,	// VLD4LNq16
     0U,	// VLD4LNq16Pseudo
     0U,	// VLD4LNq16Pseudo_UPD
-    1079367377U,	// VLD4LNq16_UPD
-    1079490257U,	// VLD4LNq32
+    28649846U,	// VLD4LNq16_UPD
+    29157750U,	// VLD4LNq32
     0U,	// VLD4LNq32Pseudo
     0U,	// VLD4LNq32Pseudo_UPD
-    1079498449U,	// VLD4LNq32_UPD
-    5560017U,	// VLD4d16
+    29174134U,	// VLD4LNq32_UPD
+    28445046U,	// VLD4d16
     0U,	// VLD4d16Pseudo
     0U,	// VLD4d16Pseudo_UPD
-    5621457U,	// VLD4d16_UPD
-    5691089U,	// VLD4d32
+    28641654U,	// VLD4d16_UPD
+    28969334U,	// VLD4d32
     0U,	// VLD4d32Pseudo
     0U,	// VLD4d32Pseudo_UPD
-    5752529U,	// VLD4d32_UPD
-    5822161U,	// VLD4d8
+    29165942U,	// VLD4d32_UPD
+    29493622U,	// VLD4d8
     0U,	// VLD4d8Pseudo
     0U,	// VLD4d8Pseudo_UPD
-    5883601U,	// VLD4d8_UPD
-    5560017U,	// VLD4q16
+    29690230U,	// VLD4d8_UPD
+    28445046U,	// VLD4q16
     0U,	// VLD4q16Pseudo_UPD
-    5621457U,	// VLD4q16_UPD
+    28641654U,	// VLD4q16_UPD
     0U,	// VLD4q16oddPseudo
     0U,	// VLD4q16oddPseudo_UPD
-    5691089U,	// VLD4q32
+    28969334U,	// VLD4q32
     0U,	// VLD4q32Pseudo_UPD
-    5752529U,	// VLD4q32_UPD
+    29165942U,	// VLD4q32_UPD
     0U,	// VLD4q32oddPseudo
     0U,	// VLD4q32oddPseudo_UPD
-    5822161U,	// VLD4q8
+    29493622U,	// VLD4q8
     0U,	// VLD4q8Pseudo_UPD
-    5883601U,	// VLD4q8_UPD
+    29690230U,	// VLD4q8_UPD
     0U,	// VLD4q8oddPseudo
     0U,	// VLD4q8oddPseudo_UPD
-    2332571774U,	// VLDMDDB_UPD
-    571406U,	// VLDMDIA
-    2332571662U,	// VLDMDIA_UPD
+    875064290U,	// VLDMDDB_UPD
+    2730766U,	// VLDMDIA
+    875064078U,	// VLDMDIA_UPD
     0U,	// VLDMQIA
-    2332571774U,	// VLDMSDB_UPD
-    571406U,	// VLDMSIA
-    2332571662U,	// VLDMSIA_UPD
-    556114U,	// VLDRD
-    162898U,	// VLDRH
-    556114U,	// VLDRS
-    1074314122U,	// VLLDM
-    1074314128U,	// VLSTM
-    185246300U,	// VMAXNMD
-    185246693U,	// VMAXNMH
-    185245992U,	// VMAXNMNDf
-    185246693U,	// VMAXNMNDh
-    185245992U,	// VMAXNMNQf
-    185246693U,	// VMAXNMNQh
-    185245992U,	// VMAXNMS
-    253132314U,	// VMAXfd
-    253132314U,	// VMAXfq
-    253001242U,	// VMAXhd
-    253001242U,	// VMAXhq
-    186940954U,	// VMAXsv16i8
-    186678810U,	// VMAXsv2i32
-    186809882U,	// VMAXsv4i16
-    186678810U,	// VMAXsv4i32
-    186809882U,	// VMAXsv8i16
-    186940954U,	// VMAXsv8i8
-    187334170U,	// VMAXuv16i8
-    187072026U,	// VMAXuv2i32
-    187203098U,	// VMAXuv4i16
-    187072026U,	// VMAXuv4i32
-    187203098U,	// VMAXuv8i16
-    187334170U,	// VMAXuv8i8
-    185246288U,	// VMINNMD
-    185246681U,	// VMINNMH
-    185245980U,	// VMINNMNDf
-    185246681U,	// VMINNMNDh
-    185245980U,	// VMINNMNQf
-    185246681U,	// VMINNMNQh
-    185245980U,	// VMINNMS
-    253131706U,	// VMINfd
-    253131706U,	// VMINfq
-    253000634U,	// VMINhd
-    253000634U,	// VMINhq
-    186940346U,	// VMINsv16i8
-    186678202U,	// VMINsv2i32
-    186809274U,	// VMINsv4i16
-    186678202U,	// VMINsv4i32
-    186809274U,	// VMINsv8i16
-    186940346U,	// VMINsv8i8
-    187333562U,	// VMINuv16i8
-    187071418U,	// VMINuv2i32
-    187202490U,	// VMINuv4i16
-    187071418U,	// VMINuv4i32
-    187202490U,	// VMINuv8i16
-    187333562U,	// VMINuv8i8
-    2400344110U,	// VMLAD
-    2400475182U,	// VMLAH
-    169896676U,	// VMLALslsv2i32
-    170027748U,	// VMLALslsv4i16
-    170289892U,	// VMLALsluv2i32
-    170420964U,	// VMLALsluv4i16
-    169892580U,	// VMLALsv2i64
-    170023652U,	// VMLALsv4i32
-    170154724U,	// VMLALsv8i16
-    170285796U,	// VMLALuv2i64
-    170416868U,	// VMLALuv4i32
-    170547940U,	// VMLALuv8i16
-    2400606254U,	// VMLAS
-    2400606254U,	// VMLAfd
-    2400606254U,	// VMLAfq
-    2400475182U,	// VMLAhd
-    2400475182U,	// VMLAhq
-    2400610350U,	// VMLAslfd
-    2400610350U,	// VMLAslfq
-    2400479278U,	// VMLAslhd
-    2400479278U,	// VMLAslhq
-    170813486U,	// VMLAslv2i32
-    170944558U,	// VMLAslv4i16
-    170813486U,	// VMLAslv4i32
-    170944558U,	// VMLAslv8i16
-    171071534U,	// VMLAv16i8
-    170809390U,	// VMLAv2i32
-    170940462U,	// VMLAv4i16
-    170809390U,	// VMLAv4i32
-    170940462U,	// VMLAv8i16
-    171071534U,	// VMLAv8i8
-    2400345279U,	// VMLSD
-    2400476351U,	// VMLSH
-    169896809U,	// VMLSLslsv2i32
-    170027881U,	// VMLSLslsv4i16
-    170290025U,	// VMLSLsluv2i32
-    170421097U,	// VMLSLsluv4i16
-    169892713U,	// VMLSLsv2i64
-    170023785U,	// VMLSLsv4i32
-    170154857U,	// VMLSLsv8i16
-    170285929U,	// VMLSLuv2i64
-    170417001U,	// VMLSLuv4i32
-    170548073U,	// VMLSLuv8i16
-    2400607423U,	// VMLSS
-    2400607423U,	// VMLSfd
-    2400607423U,	// VMLSfq
-    2400476351U,	// VMLShd
-    2400476351U,	// VMLShq
-    2400611519U,	// VMLSslfd
-    2400611519U,	// VMLSslfq
-    2400480447U,	// VMLSslhd
-    2400480447U,	// VMLSslhq
-    170814655U,	// VMLSslv2i32
-    170945727U,	// VMLSslv4i16
-    170814655U,	// VMLSslv4i32
-    170945727U,	// VMLSslv8i16
-    171072703U,	// VMLSv16i8
-    170810559U,	// VMLSv2i32
-    170941631U,	// VMLSv4i16
-    170810559U,	// VMLSv4i32
-    170941631U,	// VMLSv8i16
-    171072703U,	// VMLSv8i8
-    252853737U,	// VMOVD
-    556521U,	// VMOVDRR
-    1258988623U,	// VMOVH
-    252984809U,	// VMOVHR
-    1260403588U,	// VMOVLsv2i64
-    1260534660U,	// VMOVLsv4i32
-    1260665732U,	// VMOVLsv8i16
-    1260796804U,	// VMOVLuv2i64
-    1260927876U,	// VMOVLuv4i32
-    1261058948U,	// VMOVLuv8i16
-    1261190158U,	// VMOVNv2i32
-    1261321230U,	// VMOVNv4i16
-    1261452302U,	// VMOVNv8i8
-    252984809U,	// VMOVRH
-    556521U,	// VMOVRRD
-    548329U,	// VMOVRRS
-    540137U,	// VMOVRS
-    253115881U,	// VMOVS
-    540137U,	// VMOVSR
-    548329U,	// VMOVSRR
-    405945833U,	// VMOVv16i8
-    405552617U,	// VMOVv1i64
-    1326857705U,	// VMOVv2f32
-    405683689U,	// VMOVv2i32
-    405552617U,	// VMOVv2i64
-    1326857705U,	// VMOVv4f32
-    405814761U,	// VMOVv4i16
-    405683689U,	// VMOVv4i32
-    405814761U,	// VMOVv8i16
-    405945833U,	// VMOVv8i8
-    3221798113U,	// VMRS
-    572641U,	// VMRS_FPEXC
-    1074314465U,	// VMRS_FPINST
-    2148056289U,	// VMRS_FPINST2
-    3221798113U,	// VMRS_FPSID
-    572641U,	// VMRS_MVFR0
-    1074314465U,	// VMRS_MVFR1
-    2148056289U,	// VMRS_MVFR2
-    5946503U,	// VMSR
-    6077575U,	// VMSR_FPEXC
-    6208647U,	// VMSR_FPINST
-    6339719U,	// VMSR_FPINST2
-    6470791U,	// VMSR_FPSID
-    252869503U,	// VMULD
-    253000575U,	// VMULH
-    185246384U,	// VMULLp64
-    6585174U,	// VMULLp8
-    186669910U,	// VMULLslsv2i32
-    186800982U,	// VMULLslsv4i16
-    187063126U,	// VMULLsluv2i32
-    187194198U,	// VMULLsluv4i16
-    186678102U,	// VMULLsv2i64
-    186809174U,	// VMULLsv4i32
-    186940246U,	// VMULLsv8i16
-    187071318U,	// VMULLuv2i64
-    187202390U,	// VMULLuv4i32
-    187333462U,	// VMULLuv8i16
-    253131647U,	// VMULS
-    253131647U,	// VMULfd
-    253131647U,	// VMULfq
-    253000575U,	// VMULhd
-    253000575U,	// VMULhq
-    6585215U,	// VMULpd
-    6585215U,	// VMULpq
-    253123455U,	// VMULslfd
-    253123455U,	// VMULslfq
-    252992383U,	// VMULslhd
-    252992383U,	// VMULslhq
-    187587455U,	// VMULslv2i32
-    187718527U,	// VMULslv4i16
-    187587455U,	// VMULslv4i32
-    187718527U,	// VMULslv8i16
-    187857791U,	// VMULv16i8
-    187595647U,	// VMULv2i32
-    187726719U,	// VMULv4i16
-    187595647U,	// VMULv4i32
-    187726719U,	// VMULv8i16
-    187857791U,	// VMULv8i8
-    539650U,	// VMVNd
-    539650U,	// VMVNq
-    405683202U,	// VMVNv2i32
-    405814274U,	// VMVNv4i16
-    405683202U,	// VMVNv4i32
-    405814274U,	// VMVNv8i16
-    252852757U,	// VNEGD
-    252983829U,	// VNEGH
-    253114901U,	// VNEGS
-    253114901U,	// VNEGf32q
-    253114901U,	// VNEGfd
-    252983829U,	// VNEGhd
-    252983829U,	// VNEGhq
-    1260534293U,	// VNEGs16d
-    1260534293U,	// VNEGs16q
-    1260403221U,	// VNEGs32d
-    1260403221U,	// VNEGs32q
-    1260665365U,	// VNEGs8d
-    1260665365U,	// VNEGs8q
-    2400344104U,	// VNMLAD
-    2400475176U,	// VNMLAH
-    2400606248U,	// VNMLAS
-    2400345273U,	// VNMLSD
-    2400476345U,	// VNMLSH
-    2400607417U,	// VNMLSS
-    252869497U,	// VNMULD
-    253000569U,	// VNMULH
-    253131641U,	// VNMULS
-    555999U,	// VORNd
-    555999U,	// VORNq
-    556151U,	// VORRd
-    405699703U,	// VORRiv2i32
-    405830775U,	// VORRiv4i16
-    405699703U,	// VORRiv4i32
-    405830775U,	// VORRiv8i16
-    556151U,	// VORRq
-    1243904713U,	// VPADALsv16i8
-    1243642569U,	// VPADALsv2i32
-    1243773641U,	// VPADALsv4i16
-    1243642569U,	// VPADALsv4i32
-    1243773641U,	// VPADALsv8i16
-    1243904713U,	// VPADALsv8i8
-    1244297929U,	// VPADALuv16i8
-    1244035785U,	// VPADALuv2i32
-    1244166857U,	// VPADALuv4i16
-    1244035785U,	// VPADALuv4i32
-    1244166857U,	// VPADALuv8i16
-    1244297929U,	// VPADALuv8i8
-    1260665605U,	// VPADDLsv16i8
-    1260403461U,	// VPADDLsv2i32
-    1260534533U,	// VPADDLsv4i16
-    1260403461U,	// VPADDLsv4i32
-    1260534533U,	// VPADDLsv8i16
-    1260665605U,	// VPADDLsv8i8
-    1261058821U,	// VPADDLuv16i8
-    1260796677U,	// VPADDLuv2i32
-    1260927749U,	// VPADDLuv4i16
-    1260796677U,	// VPADDLuv4i32
-    1260927749U,	// VPADDLuv8i16
-    1261058821U,	// VPADDLuv8i8
-    253131143U,	// VPADDf
-    253000071U,	// VPADDh
-    187726215U,	// VPADDi16
-    187595143U,	// VPADDi32
-    187857287U,	// VPADDi8
-    253132308U,	// VPMAXf
-    253001236U,	// VPMAXh
-    186809876U,	// VPMAXs16
-    186678804U,	// VPMAXs32
-    186940948U,	// VPMAXs8
-    187203092U,	// VPMAXu16
-    187072020U,	// VPMAXu32
-    187334164U,	// VPMAXu8
-    253131700U,	// VPMINf
-    253000628U,	// VPMINh
-    186809268U,	// VPMINs16
-    186678196U,	// VPMINs32
-    186940340U,	// VPMINs8
-    187202484U,	// VPMINu16
-    187071412U,	// VPMINu32
-    187333556U,	// VPMINu8
-    1260666014U,	// VQABSv16i8
-    1260403870U,	// VQABSv2i32
-    1260534942U,	// VQABSv4i16
-    1260403870U,	// VQABSv4i32
-    1260534942U,	// VQABSv8i16
-    1260666014U,	// VQABSv8i8
-    186939789U,	// VQADDsv16i8
-    191265165U,	// VQADDsv1i64
-    186677645U,	// VQADDsv2i32
-    191265165U,	// VQADDsv2i64
-    186808717U,	// VQADDsv4i16
-    186677645U,	// VQADDsv4i32
-    186808717U,	// VQADDsv8i16
-    186939789U,	// VQADDsv8i8
-    187333005U,	// VQADDuv16i8
-    191396237U,	// VQADDuv1i64
-    187070861U,	// VQADDuv2i32
-    191396237U,	// VQADDuv2i64
-    187201933U,	// VQADDuv4i16
-    187070861U,	// VQADDuv4i32
-    187201933U,	// VQADDuv8i16
-    187333005U,	// VQADDuv8i8
-    169896656U,	// VQDMLALslv2i32
-    170027728U,	// VQDMLALslv4i16
-    169892560U,	// VQDMLALv2i64
-    170023632U,	// VQDMLALv4i32
-    169896801U,	// VQDMLSLslv2i32
-    170027873U,	// VQDMLSLslv4i16
-    169892705U,	// VQDMLSLv2i64
-    170023777U,	// VQDMLSLv4i32
-    186669632U,	// VQDMULHslv2i32
-    186800704U,	// VQDMULHslv4i16
-    186669632U,	// VQDMULHslv4i32
-    186800704U,	// VQDMULHslv8i16
-    186677824U,	// VQDMULHv2i32
-    186808896U,	// VQDMULHv4i16
-    186677824U,	// VQDMULHv4i32
-    186808896U,	// VQDMULHv8i16
-    186669890U,	// VQDMULLslv2i32
-    186800962U,	// VQDMULLslv4i16
-    186678082U,	// VQDMULLv2i64
-    186809154U,	// VQDMULLv4i32
-    1264991226U,	// VQMOVNsuv2i32
-    1260403706U,	// VQMOVNsuv4i16
-    1260534778U,	// VQMOVNsuv8i8
-    1264991239U,	// VQMOVNsv2i32
-    1260403719U,	// VQMOVNsv4i16
-    1260534791U,	// VQMOVNsv8i8
-    1265122311U,	// VQMOVNuv2i32
-    1260796935U,	// VQMOVNuv4i16
-    1260928007U,	// VQMOVNuv8i8
-    1260665359U,	// VQNEGv16i8
-    1260403215U,	// VQNEGv2i32
-    1260534287U,	// VQNEGv4i16
-    1260403215U,	// VQNEGv4i32
-    1260534287U,	// VQNEGv8i16
-    1260665359U,	// VQNEGv8i8
-    169896482U,	// VQRDMLAHslv2i32
-    170027554U,	// VQRDMLAHslv4i16
-    169896482U,	// VQRDMLAHslv4i32
-    170027554U,	// VQRDMLAHslv8i16
-    169892386U,	// VQRDMLAHv2i32
-    170023458U,	// VQRDMLAHv4i16
-    169892386U,	// VQRDMLAHv4i32
-    170023458U,	// VQRDMLAHv8i16
-    169896539U,	// VQRDMLSHslv2i32
-    170027611U,	// VQRDMLSHslv4i16
-    169896539U,	// VQRDMLSHslv4i32
-    170027611U,	// VQRDMLSHslv8i16
-    169892443U,	// VQRDMLSHv2i32
-    170023515U,	// VQRDMLSHv4i16
-    169892443U,	// VQRDMLSHv4i32
-    170023515U,	// VQRDMLSHv8i16
-    186669640U,	// VQRDMULHslv2i32
-    186800712U,	// VQRDMULHslv4i16
-    186669640U,	// VQRDMULHslv4i32
-    186800712U,	// VQRDMULHslv8i16
-    186677832U,	// VQRDMULHv2i32
-    186808904U,	// VQRDMULHv4i16
-    186677832U,	// VQRDMULHv4i32
-    186808904U,	// VQRDMULHv8i16
-    186940188U,	// VQRSHLsv16i8
-    191265564U,	// VQRSHLsv1i64
-    186678044U,	// VQRSHLsv2i32
-    191265564U,	// VQRSHLsv2i64
-    186809116U,	// VQRSHLsv4i16
-    186678044U,	// VQRSHLsv4i32
-    186809116U,	// VQRSHLsv8i16
-    186940188U,	// VQRSHLsv8i8
-    187333404U,	// VQRSHLuv16i8
-    191396636U,	// VQRSHLuv1i64
-    187071260U,	// VQRSHLuv2i32
-    191396636U,	// VQRSHLuv2i64
-    187202332U,	// VQRSHLuv4i16
-    187071260U,	// VQRSHLuv4i32
-    187202332U,	// VQRSHLuv8i16
-    187333404U,	// VQRSHLuv8i8
-    191265738U,	// VQRSHRNsv2i32
-    186678218U,	// VQRSHRNsv4i16
-    186809290U,	// VQRSHRNsv8i8
-    191396810U,	// VQRSHRNuv2i32
-    187071434U,	// VQRSHRNuv4i16
-    187202506U,	// VQRSHRNuv8i8
-    191265777U,	// VQRSHRUNv2i32
-    186678257U,	// VQRSHRUNv4i16
-    186809329U,	// VQRSHRUNv8i8
-    186940182U,	// VQSHLsiv16i8
-    191265558U,	// VQSHLsiv1i64
-    186678038U,	// VQSHLsiv2i32
-    191265558U,	// VQSHLsiv2i64
-    186809110U,	// VQSHLsiv4i16
-    186678038U,	// VQSHLsiv4i32
-    186809110U,	// VQSHLsiv8i16
-    186940182U,	// VQSHLsiv8i8
-    186940879U,	// VQSHLsuv16i8
-    191266255U,	// VQSHLsuv1i64
-    186678735U,	// VQSHLsuv2i32
-    191266255U,	// VQSHLsuv2i64
-    186809807U,	// VQSHLsuv4i16
-    186678735U,	// VQSHLsuv4i32
-    186809807U,	// VQSHLsuv8i16
-    186940879U,	// VQSHLsuv8i8
-    186940182U,	// VQSHLsv16i8
-    191265558U,	// VQSHLsv1i64
-    186678038U,	// VQSHLsv2i32
-    191265558U,	// VQSHLsv2i64
-    186809110U,	// VQSHLsv4i16
-    186678038U,	// VQSHLsv4i32
-    186809110U,	// VQSHLsv8i16
-    186940182U,	// VQSHLsv8i8
-    187333398U,	// VQSHLuiv16i8
-    191396630U,	// VQSHLuiv1i64
-    187071254U,	// VQSHLuiv2i32
-    191396630U,	// VQSHLuiv2i64
-    187202326U,	// VQSHLuiv4i16
-    187071254U,	// VQSHLuiv4i32
-    187202326U,	// VQSHLuiv8i16
-    187333398U,	// VQSHLuiv8i8
-    187333398U,	// VQSHLuv16i8
-    191396630U,	// VQSHLuv1i64
-    187071254U,	// VQSHLuv2i32
-    191396630U,	// VQSHLuv2i64
-    187202326U,	// VQSHLuv4i16
-    187071254U,	// VQSHLuv4i32
-    187202326U,	// VQSHLuv8i16
-    187333398U,	// VQSHLuv8i8
-    191265731U,	// VQSHRNsv2i32
-    186678211U,	// VQSHRNsv4i16
-    186809283U,	// VQSHRNsv8i8
-    191396803U,	// VQSHRNuv2i32
-    187071427U,	// VQSHRNuv4i16
-    187202499U,	// VQSHRNuv8i8
-    191265769U,	// VQSHRUNv2i32
-    186678249U,	// VQSHRUNv4i16
-    186809321U,	// VQSHRUNv8i8
-    186939648U,	// VQSUBsv16i8
-    191265024U,	// VQSUBsv1i64
-    186677504U,	// VQSUBsv2i32
-    191265024U,	// VQSUBsv2i64
-    186808576U,	// VQSUBsv4i16
-    186677504U,	// VQSUBsv4i32
-    186808576U,	// VQSUBsv8i16
-    186939648U,	// VQSUBsv8i8
-    187332864U,	// VQSUBuv16i8
-    191396096U,	// VQSUBuv1i64
-    187070720U,	// VQSUBuv2i32
-    191396096U,	// VQSUBuv2i64
-    187201792U,	// VQSUBuv4i16
-    187070720U,	// VQSUBuv4i32
-    187201792U,	// VQSUBuv8i16
-    187332864U,	// VQSUBuv8i8
-    187464613U,	// VRADDHNv2i32
-    187595685U,	// VRADDHNv4i16
-    187726757U,	// VRADDHNv8i8
-    1260796401U,	// VRECPEd
-    253114865U,	// VRECPEfd
-    253114865U,	// VRECPEfq
-    252983793U,	// VRECPEhd
-    252983793U,	// VRECPEhq
-    1260796401U,	// VRECPEq
-    253131994U,	// VRECPSfd
-    253131994U,	// VRECPSfq
-    253000922U,	// VRECPShd
-    253000922U,	// VRECPShq
-    407379U,	// VREV16d8
-    407379U,	// VREV16q8
-    145022U,	// VREV32d16
-    407166U,	// VREV32d8
-    145022U,	// VREV32q16
-    407166U,	// VREV32q8
-    145098U,	// VREV64d16
-    276170U,	// VREV64d32
-    407242U,	// VREV64d8
-    145098U,	// VREV64q16
-    276170U,	// VREV64q32
-    407242U,	// VREV64q8
-    186939770U,	// VRHADDsv16i8
-    186677626U,	// VRHADDsv2i32
-    186808698U,	// VRHADDsv4i16
-    186677626U,	// VRHADDsv4i32
-    186808698U,	// VRHADDsv8i16
-    186939770U,	// VRHADDsv8i8
-    187332986U,	// VRHADDuv16i8
-    187070842U,	// VRHADDuv2i32
-    187201914U,	// VRHADDuv4i16
-    187070842U,	// VRHADDuv4i32
-    187201914U,	// VRHADDuv8i16
-    187332986U,	// VRHADDuv8i8
-    1258988088U,	// VRINTAD
-    1258988470U,	// VRINTAH
-    1258987769U,	// VRINTANDf
-    1258988470U,	// VRINTANDh
-    1258987769U,	// VRINTANQf
-    1258988470U,	// VRINTANQh
-    1258987769U,	// VRINTAS
-    1258988136U,	// VRINTMD
-    1258988529U,	// VRINTMH
-    1258987828U,	// VRINTMNDf
-    1258988529U,	// VRINTMNDh
-    1258987828U,	// VRINTMNQf
-    1258988529U,	// VRINTMNQh
-    1258987828U,	// VRINTMS
-    1258988148U,	// VRINTND
-    1258988541U,	// VRINTNH
-    1258987840U,	// VRINTNNDf
-    1258988541U,	// VRINTNNDh
-    1258987840U,	// VRINTNNQf
-    1258988541U,	// VRINTNNQh
-    1258987840U,	// VRINTNS
-    1258988160U,	// VRINTPD
-    1258988553U,	// VRINTPH
-    1258987852U,	// VRINTPNDf
-    1258988553U,	// VRINTPNDh
-    1258987852U,	// VRINTPNQf
-    1258988553U,	// VRINTPNQh
-    1258987852U,	// VRINTPS
-    252853388U,	// VRINTRD
-    252984460U,	// VRINTRH
-    253115532U,	// VRINTRS
-    252853960U,	// VRINTXD
-    252985032U,	// VRINTXH
-    1258987900U,	// VRINTXNDf
-    1258988611U,	// VRINTXNDh
-    1258987900U,	// VRINTXNQf
-    1258988611U,	// VRINTXNQh
-    253116104U,	// VRINTXS
-    252853972U,	// VRINTZD
-    252985044U,	// VRINTZH
-    1258987912U,	// VRINTZNDf
-    1258988634U,	// VRINTZNDh
-    1258987912U,	// VRINTZNQf
-    1258988634U,	// VRINTZNQh
-    253116116U,	// VRINTZS
-    186940195U,	// VRSHLsv16i8
-    191265571U,	// VRSHLsv1i64
-    186678051U,	// VRSHLsv2i32
-    191265571U,	// VRSHLsv2i64
-    186809123U,	// VRSHLsv4i16
-    186678051U,	// VRSHLsv4i32
-    186809123U,	// VRSHLsv8i16
-    186940195U,	// VRSHLsv8i8
-    187333411U,	// VRSHLuv16i8
-    191396643U,	// VRSHLuv1i64
-    187071267U,	// VRSHLuv2i32
-    191396643U,	// VRSHLuv2i64
-    187202339U,	// VRSHLuv4i16
-    187071267U,	// VRSHLuv4i32
-    187202339U,	// VRSHLuv8i16
-    187333411U,	// VRSHLuv8i8
-    187464658U,	// VRSHRNv2i32
-    187595730U,	// VRSHRNv4i16
-    187726802U,	// VRSHRNv8i8
-    186940503U,	// VRSHRsv16i8
-    191265879U,	// VRSHRsv1i64
-    186678359U,	// VRSHRsv2i32
-    191265879U,	// VRSHRsv2i64
-    186809431U,	// VRSHRsv4i16
-    186678359U,	// VRSHRsv4i32
-    186809431U,	// VRSHRsv8i16
-    186940503U,	// VRSHRsv8i8
-    187333719U,	// VRSHRuv16i8
-    191396951U,	// VRSHRuv1i64
-    187071575U,	// VRSHRuv2i32
-    191396951U,	// VRSHRuv2i64
-    187202647U,	// VRSHRuv4i16
-    187071575U,	// VRSHRuv4i32
-    187202647U,	// VRSHRuv8i16
-    187333719U,	// VRSHRuv8i8
-    1260796414U,	// VRSQRTEd
-    253114878U,	// VRSQRTEfd
-    253114878U,	// VRSQRTEfq
-    252983806U,	// VRSQRTEhd
-    252983806U,	// VRSQRTEhq
-    1260796414U,	// VRSQRTEq
-    253132016U,	// VRSQRTSfd
-    253132016U,	// VRSQRTSfq
-    253000944U,	// VRSQRTShd
-    253000944U,	// VRSQRTShq
-    170154046U,	// VRSRAsv16i8
-    174479422U,	// VRSRAsv1i64
-    169891902U,	// VRSRAsv2i32
-    174479422U,	// VRSRAsv2i64
-    170022974U,	// VRSRAsv4i16
-    169891902U,	// VRSRAsv4i32
-    170022974U,	// VRSRAsv8i16
-    170154046U,	// VRSRAsv8i8
-    170547262U,	// VRSRAuv16i8
-    174610494U,	// VRSRAuv1i64
-    170285118U,	// VRSRAuv2i32
-    174610494U,	// VRSRAuv2i64
-    170416190U,	// VRSRAuv4i16
-    170285118U,	// VRSRAuv4i32
-    170416190U,	// VRSRAuv8i16
-    170547262U,	// VRSRAuv8i8
-    187464598U,	// VRSUBHNv2i32
-    187595670U,	// VRSUBHNv4i16
-    187726742U,	// VRSUBHNv8i8
-    910473U,	// VSDOTD
-    7070857U,	// VSDOTDI
-    910473U,	// VSDOTQ
-    7070857U,	// VSDOTQI
-    185246348U,	// VSELEQD
-    185246741U,	// VSELEQH
-    185246040U,	// VSELEQS
-    185246276U,	// VSELGED
-    185246669U,	// VSELGEH
-    185245968U,	// VSELGES
-    185246372U,	// VSELGTD
-    185246775U,	// VSELGTH
-    185246064U,	// VSELGTS
-    185246360U,	// VSELVSD
-    185246763U,	// VSELVSH
-    185246052U,	// VSELVSS
-    3221380585U,	// VSETLNi16
-    3221511657U,	// VSETLNi32
-    3221642729U,	// VSETLNi8
-    187726652U,	// VSHLLi16
-    187595580U,	// VSHLLi32
-    187857724U,	// VSHLLi8
-    186678076U,	// VSHLLsv2i64
-    186809148U,	// VSHLLsv4i32
-    186940220U,	// VSHLLsv8i16
-    187071292U,	// VSHLLuv2i64
-    187202364U,	// VSHLLuv4i32
-    187333436U,	// VSHLLuv8i16
-    187857705U,	// VSHLiv16i8
-    187464489U,	// VSHLiv1i64
-    187595561U,	// VSHLiv2i32
-    187464489U,	// VSHLiv2i64
-    187726633U,	// VSHLiv4i16
-    187595561U,	// VSHLiv4i32
-    187726633U,	// VSHLiv8i16
-    187857705U,	// VSHLiv8i8
-    186940201U,	// VSHLsv16i8
-    191265577U,	// VSHLsv1i64
-    186678057U,	// VSHLsv2i32
-    191265577U,	// VSHLsv2i64
-    186809129U,	// VSHLsv4i16
-    186678057U,	// VSHLsv4i32
-    186809129U,	// VSHLsv8i16
-    186940201U,	// VSHLsv8i8
-    187333417U,	// VSHLuv16i8
-    191396649U,	// VSHLuv1i64
-    187071273U,	// VSHLuv2i32
-    191396649U,	// VSHLuv2i64
-    187202345U,	// VSHLuv4i16
-    187071273U,	// VSHLuv4i32
-    187202345U,	// VSHLuv8i16
-    187333417U,	// VSHLuv8i8
-    187464665U,	// VSHRNv2i32
-    187595737U,	// VSHRNv4i16
-    187726809U,	// VSHRNv8i8
-    186940509U,	// VSHRsv16i8
-    191265885U,	// VSHRsv1i64
-    186678365U,	// VSHRsv2i32
-    191265885U,	// VSHRsv2i64
-    186809437U,	// VSHRsv4i16
-    186678365U,	// VSHRsv4i32
-    186809437U,	// VSHRsv8i16
-    186940509U,	// VSHRsv8i8
-    187333725U,	// VSHRuv16i8
-    191396957U,	// VSHRuv1i64
-    187071581U,	// VSHRuv2i32
-    191396957U,	// VSHRuv2i64
-    187202653U,	// VSHRuv4i16
-    187071581U,	// VSHRuv4i32
-    187202653U,	// VSHRuv8i16
-    187333725U,	// VSHRuv8i8
-    7110066U,	// VSHTOD
-    256540082U,	// VSHTOH
-    7241138U,	// VSHTOS
-    443563442U,	// VSITOD
-    443694514U,	// VSITOH
-    440942002U,	// VSITOS
-    416419U,	// VSLIv16i8
-    5266083U,	// VSLIv1i64
-    285347U,	// VSLIv2i32
-    5266083U,	// VSLIv2i64
-    154275U,	// VSLIv4i16
-    285347U,	// VSLIv4i32
-    154275U,	// VSLIv8i16
-    416419U,	// VSLIv8i8
-    1332772274U,	// VSLTOD
-    1332903346U,	// VSLTOH
-    1330150834U,	// VSLTOS
-    252853628U,	// VSQRTD
-    252984700U,	// VSQRTH
-    253115772U,	// VSQRTS
-    170154052U,	// VSRAsv16i8
-    174479428U,	// VSRAsv1i64
-    169891908U,	// VSRAsv2i32
-    174479428U,	// VSRAsv2i64
-    170022980U,	// VSRAsv4i16
-    169891908U,	// VSRAsv4i32
-    170022980U,	// VSRAsv8i16
-    170154052U,	// VSRAsv8i8
-    170547268U,	// VSRAuv16i8
-    174610500U,	// VSRAuv1i64
-    170285124U,	// VSRAuv2i32
-    174610500U,	// VSRAuv2i64
-    170416196U,	// VSRAuv4i16
-    170285124U,	// VSRAuv4i32
-    170416196U,	// VSRAuv8i16
-    170547268U,	// VSRAuv8i8
-    416424U,	// VSRIv16i8
-    5266088U,	// VSRIv1i64
-    285352U,	// VSRIv2i32
-    5266088U,	// VSRIv2i64
-    154280U,	// VSRIv4i16
-    285352U,	// VSRIv4i32
-    154280U,	// VSRIv8i16
-    416424U,	// VSRIv8i8
-    1247041145U,	// VST1LNd16
-    1632949881U,	// VST1LNd16_UPD
-    1247172217U,	// VST1LNd32
-    1633080953U,	// VST1LNd32_UPD
-    1247303289U,	// VST1LNd8
-    1633212025U,	// VST1LNd8_UPD
+    875064290U,	// VLDMSDB_UPD
+    2730766U,	// VLDMSIA
+    875064078U,	// VLDMSIA_UPD
+    2683301U,	// VLDRD
+    586149U,	// VLDRH
+    2683301U,	// VLDRS
+    2580050341U,	// VLDR_FPCXTNS_off
+    701034917U,	// VLDR_FPCXTNS_post
+    2647191973U,	// VLDR_FPCXTNS_pre
+    2580574629U,	// VLDR_FPCXTS_off
+    701559205U,	// VLDR_FPCXTS_post
+    2647716261U,	// VLDR_FPCXTS_pre
+    2581098917U,	// VLDR_FPSCR_NZCVQC_off
+    702083493U,	// VLDR_FPSCR_NZCVQC_post
+    2648240549U,	// VLDR_FPSCR_NZCVQC_pre
+    2581623205U,	// VLDR_FPSCR_off
+    702607781U,	// VLDR_FPSCR_post
+    2648764837U,	// VLDR_FPSCR_pre
+    2716397989U,	// VLDR_P0_off
+    1642639781U,	// VLDR_P0_post
+    2783490469U,	// VLDR_P0_pre
+    2582671781U,	// VLDR_VPR_off
+    703656357U,	// VLDR_VPR_post
+    2649813413U,	// VLDR_VPR_pre
+    2732105U,	// VLLDM
+    2732140U,	// VLSTM
+    7926951U,	// VMAXfd
+    7926951U,	// VMAXfq
+    7402663U,	// VMAXhd
+    7402663U,	// VMAXhq
+    12121255U,	// VMAXsv16i8
+    11596967U,	// VMAXsv2i32
+    11072679U,	// VMAXsv4i16
+    11596967U,	// VMAXsv4i32
+    11072679U,	// VMAXsv8i16
+    12121255U,	// VMAXsv8i8
+    13694119U,	// VMAXuv16i8
+    13169831U,	// VMAXuv2i32
+    12645543U,	// VMAXuv4i16
+    13169831U,	// VMAXuv4i32
+    12645543U,	// VMAXuv8i16
+    13694119U,	// VMAXuv8i8
+    7925916U,	// VMINfd
+    7925916U,	// VMINfq
+    7401628U,	// VMINhd
+    7401628U,	// VMINhq
+    12120220U,	// VMINsv16i8
+    11595932U,	// VMINsv2i32
+    11071644U,	// VMINsv4i16
+    11595932U,	// VMINsv4i32
+    11071644U,	// VMINsv8i16
+    12120220U,	// VMINsv8i8
+    13693084U,	// VMINuv16i8
+    13168796U,	// VMINuv2i32
+    12644508U,	// VMINuv4i16
+    13168796U,	// VMINuv4i32
+    12644508U,	// VMINuv8i16
+    13693084U,	// VMINuv8i8
+    1147710260U,	// VMLAD
+    7383860U,	// VMLAH
+    11587401U,	// VMLALslsv2i32
+    11063113U,	// VMLALslsv4i16
+    13160265U,	// VMLALsluv2i32
+    12635977U,	// VMLALsluv4i16
+    11579209U,	// VMLALsv2i64
+    11054921U,	// VMLALsv4i32
+    12103497U,	// VMLALsv8i16
+    13152073U,	// VMLALuv2i64
+    12627785U,	// VMLALuv4i32
+    13676361U,	// VMLALuv8i16
+    7908148U,	// VMLAS
+    7908148U,	// VMLAfd
+    7908148U,	// VMLAfq
+    7383860U,	// VMLAhd
+    7383860U,	// VMLAhq
+    7916340U,	// VMLAslfd
+    7916340U,	// VMLAslfq
+    7392052U,	// VMLAslhd
+    7392052U,	// VMLAslhq
+    14207796U,	// VMLAslv2i32
+    14732084U,	// VMLAslv4i16
+    14207796U,	// VMLAslv4i32
+    14732084U,	// VMLAslv8i16
+    15248180U,	// VMLAv16i8
+    14199604U,	// VMLAv2i32
+    14723892U,	// VMLAv4i16
+    14199604U,	// VMLAv4i32
+    14723892U,	// VMLAv8i16
+    15248180U,	// VMLAv8i8
+    1147712055U,	// VMLSD
+    7385655U,	// VMLSH
+    11587618U,	// VMLSLslsv2i32
+    11063330U,	// VMLSLslsv4i16
+    13160482U,	// VMLSLsluv2i32
+    12636194U,	// VMLSLsluv4i16
+    11579426U,	// VMLSLsv2i64
+    11055138U,	// VMLSLsv4i32
+    12103714U,	// VMLSLsv8i16
+    13152290U,	// VMLSLuv2i64
+    12628002U,	// VMLSLuv4i32
+    13676578U,	// VMLSLuv8i16
+    7909943U,	// VMLSS
+    7909943U,	// VMLSfd
+    7909943U,	// VMLSfq
+    7385655U,	// VMLShd
+    7385655U,	// VMLShq
+    7918135U,	// VMLSslfd
+    7918135U,	// VMLSslfq
+    7393847U,	// VMLSslhd
+    7393847U,	// VMLSslhq
+    14209591U,	// VMLSslv2i32
+    14733879U,	// VMLSslv4i16
+    14209591U,	// VMLSslv4i32
+    14733879U,	// VMLSslv8i16
+    15249975U,	// VMLSv16i8
+    14201399U,	// VMLSv2i32
+    14725687U,	// VMLSv4i16
+    14201399U,	// VMLSv4i32
+    14725687U,	// VMLSv8i16
+    15249975U,	// VMLSv8i8
+    808543674U,	// VMMLA
+    1147696202U,	// VMOVD
+    2683978U,	// VMOVDRR
+    875644323U,	// VMOVH
+    7369802U,	// VMOVHR
+    11563075U,	// VMOVLsv2i64
+    11038787U,	// VMOVLsv4i32
+    12087363U,	// VMOVLsv8i16
+    13135939U,	// VMOVLuv2i64
+    12611651U,	// VMOVLuv4i32
+    13660227U,	// VMOVLuv8i16
+    895512829U,	// VMOVNv2i32
+    14184701U,	// VMOVNv4i16
+    14708989U,	// VMOVNv8i8
+    7369802U,	// VMOVRH
+    2683978U,	// VMOVRRD
+    2667594U,	// VMOVRRS
+    2651210U,	// VMOVRS
+    7894090U,	// VMOVS
+    2651210U,	// VMOVSR
+    2667594U,	// VMOVSRR
+    15234122U,	// VMOVv16i8
+    2036364362U,	// VMOVv1i64
+    7894090U,	// VMOVv2f32
+    14185546U,	// VMOVv2i32
+    2036364362U,	// VMOVv2i64
+    7894090U,	// VMOVv4f32
+    14709834U,	// VMOVv4i16
+    14185546U,	// VMOVv4i32
+    14709834U,	// VMOVv8i16
+    15234122U,	// VMOVv8i8
+    2732633U,	// VMRS
+    2732633U,	// VMRS_FPCXTNS
+    2732633U,	// VMRS_FPCXTS
+    2732633U,	// VMRS_FPEXC
+    2732633U,	// VMRS_FPINST
+    2732633U,	// VMRS_FPINST2
+    2650713U,	// VMRS_FPSCR_NZCVQC
+    2732633U,	// VMRS_FPSID
+    2732633U,	// VMRS_MVFR0
+    2732633U,	// VMRS_MVFR1
+    2732633U,	// VMRS_MVFR2
+    2650713U,	// VMRS_P0
+    2732633U,	// VMRS_VPR
+    31568365U,	// VMSR
+    29995501U,	// VMSR_FPCXTNS
+    30519789U,	// VMSR_FPCXTS
+    33141229U,	// VMSR_FPEXC
+    33665517U,	// VMSR_FPINST
+    34189805U,	// VMSR_FPINST2
+    903377389U,	// VMSR_FPSCR_NZCVQC
+    34714093U,	// VMSR_FPSID
+    904425965U,	// VMSR_P0
+    32616941U,	// VMSR_VPR
+    1147727934U,	// VMULD
+    7401534U,	// VMULH
+    875643746U,	// VMULLp64
+    24178671U,	// VMULLp8
+    11579375U,	// VMULLslsv2i32
+    11055087U,	// VMULLslsv4i16
+    13152239U,	// VMULLsluv2i32
+    12627951U,	// VMULLsluv4i16
+    11595759U,	// VMULLsv2i64
+    11071471U,	// VMULLsv4i32
+    12120047U,	// VMULLsv8i16
+    13168623U,	// VMULLuv2i64
+    12644335U,	// VMULLuv4i32
+    13692911U,	// VMULLuv8i16
+    7925822U,	// VMULS
+    7925822U,	// VMULfd
+    7925822U,	// VMULfq
+    7401534U,	// VMULhd
+    7401534U,	// VMULhq
+    24178750U,	// VMULpd
+    24178750U,	// VMULpq
+    7909438U,	// VMULslfd
+    7909438U,	// VMULslfq
+    7385150U,	// VMULslhd
+    7385150U,	// VMULslhq
+    14200894U,	// VMULslv2i32
+    14725182U,	// VMULslv4i16
+    14200894U,	// VMULslv4i32
+    14725182U,	// VMULslv8i16
+    15265854U,	// VMULv16i8
+    14217278U,	// VMULv2i32
+    14741566U,	// VMULv4i16
+    14217278U,	// VMULv4i32
+    14741566U,	// VMULv8i16
+    15265854U,	// VMULv8i8
+    2650353U,	// VMVNd
+    2650353U,	// VMVNq
+    14184689U,	// VMVNv2i32
+    14708977U,	// VMVNv4i16
+    14184689U,	// VMVNv4i32
+    14708977U,	// VMVNv8i16
+    1147694595U,	// VNEGD
+    7368195U,	// VNEGH
+    7892483U,	// VNEGS
+    7892483U,	// VNEGf32q
+    7892483U,	// VNEGfd
+    7368195U,	// VNEGhd
+    7368195U,	// VNEGhq
+    11038211U,	// VNEGs16d
+    11038211U,	// VNEGs16q
+    11562499U,	// VNEGs32d
+    11562499U,	// VNEGs32q
+    12086787U,	// VNEGs8d
+    12086787U,	// VNEGs8q
+    1147710254U,	// VNMLAD
+    7383854U,	// VNMLAH
+    7908142U,	// VNMLAS
+    1147712049U,	// VNMLSD
+    7385649U,	// VNMLSH
+    7909937U,	// VNMLSS
+    1147727928U,	// VNMULD
+    7401528U,	// VNMULH
+    7925816U,	// VNMULS
+    2683073U,	// VORNd
+    2683073U,	// VORNq
+    2683357U,	// VORRd
+    14217693U,	// VORRiv2i32
+    14741981U,	// VORRiv4i16
+    14217693U,	// VORRiv4i32
+    14741981U,	// VORRiv8i16
+    2683357U,	// VORRq
+    12119854U,	// VPADALsv16i8
+    11595566U,	// VPADALsv2i32
+    11071278U,	// VPADALsv4i16
+    11595566U,	// VPADALsv4i32
+    11071278U,	// VPADALsv8i16
+    12119854U,	// VPADALsv8i8
+    13692718U,	// VPADALuv16i8
+    13168430U,	// VPADALuv2i32
+    12644142U,	// VPADALuv4i16
+    13168430U,	// VPADALuv4i32
+    12644142U,	// VPADALuv8i16
+    13692718U,	// VPADALuv8i8
+    12087146U,	// VPADDLsv16i8
+    11562858U,	// VPADDLsv2i32
+    11038570U,	// VPADDLsv4i16
+    11562858U,	// VPADDLsv4i32
+    11038570U,	// VPADDLsv8i16
+    12087146U,	// VPADDLsv8i8
+    13660010U,	// VPADDLuv16i8
+    13135722U,	// VPADDLuv2i32
+    12611434U,	// VPADDLuv4i16
+    13135722U,	// VPADDLuv4i32
+    12611434U,	// VPADDLuv8i16
+    13660010U,	// VPADDLuv8i8
+    7925099U,	// VPADDf
+    7400811U,	// VPADDh
+    14740843U,	// VPADDi16
+    14216555U,	// VPADDi32
+    15265131U,	// VPADDi8
+    7926945U,	// VPMAXf
+    7402657U,	// VPMAXh
+    11072673U,	// VPMAXs16
+    11596961U,	// VPMAXs32
+    12121249U,	// VPMAXs8
+    12645537U,	// VPMAXu16
+    13169825U,	// VPMAXu32
+    13694113U,	// VPMAXu8
+    7925910U,	// VPMINf
+    7401622U,	// VPMINh
+    11071638U,	// VPMINs16
+    11595926U,	// VPMINs32
+    12120214U,	// VPMINs8
+    12644502U,	// VPMINu16
+    13168790U,	// VPMINu32
+    13693078U,	// VPMINu8
+    12087830U,	// VQABSv16i8
+    11563542U,	// VQABSv2i32
+    11039254U,	// VQABSv4i16
+    11563542U,	// VQABSv4i32
+    11039254U,	// VQABSv8i16
+    12087830U,	// VQABSv8i8
+    12119409U,	// VQADDsv16i8
+    907603313U,	// VQADDsv1i64
+    11595121U,	// VQADDsv2i32
+    907603313U,	// VQADDsv2i64
+    11070833U,	// VQADDsv4i16
+    11595121U,	// VQADDsv4i32
+    11070833U,	// VQADDsv8i16
+    12119409U,	// VQADDsv8i8
+    13692273U,	// VQADDuv16i8
+    22605169U,	// VQADDuv1i64
+    13167985U,	// VQADDuv2i32
+    22605169U,	// VQADDuv2i64
+    12643697U,	// VQADDuv4i16
+    13167985U,	// VQADDuv4i32
+    12643697U,	// VQADDuv8i16
+    13692273U,	// VQADDuv8i8
+    11587381U,	// VQDMLALslv2i32
+    11063093U,	// VQDMLALslv4i16
+    11579189U,	// VQDMLALv2i64
+    11054901U,	// VQDMLALv4i32
+    11587610U,	// VQDMLSLslv2i32
+    11063322U,	// VQDMLSLslv4i16
+    11579418U,	// VQDMLSLv2i64
+    11055130U,	// VQDMLSLv4i32
+    11578977U,	// VQDMULHslv2i32
+    11054689U,	// VQDMULHslv4i16
+    11578977U,	// VQDMULHslv4i32
+    11054689U,	// VQDMULHslv8i16
+    11595361U,	// VQDMULHv2i32
+    11071073U,	// VQDMULHv4i16
+    11595361U,	// VQDMULHv4i32
+    11071073U,	// VQDMULHv8i16
+    11579355U,	// VQDMULLslv2i32
+    11055067U,	// VQDMULLslv4i16
+    11595739U,	// VQDMULLv2i64
+    11071451U,	// VQDMULLv4i32
+    907571433U,	// VQMOVNsuv2i32
+    11563241U,	// VQMOVNsuv4i16
+    11038953U,	// VQMOVNsuv8i8
+    907571446U,	// VQMOVNsv2i32
+    11563254U,	// VQMOVNsv4i16
+    11038966U,	// VQMOVNsv8i8
+    22573302U,	// VQMOVNuv2i32
+    13136118U,	// VQMOVNuv4i16
+    12611830U,	// VQMOVNuv8i8
+    12086781U,	// VQNEGv16i8
+    11562493U,	// VQNEGv2i32
+    11038205U,	// VQNEGv4i16
+    11562493U,	// VQNEGv4i32
+    11038205U,	// VQNEGv8i16
+    12086781U,	// VQNEGv8i8
+    11587101U,	// VQRDMLAHslv2i32
+    11062813U,	// VQRDMLAHslv4i16
+    11587101U,	// VQRDMLAHslv4i32
+    11062813U,	// VQRDMLAHslv8i16
+    11578909U,	// VQRDMLAHv2i32
+    11054621U,	// VQRDMLAHv4i16
+    11578909U,	// VQRDMLAHv4i32
+    11054621U,	// VQRDMLAHv8i16
+    11587230U,	// VQRDMLSHslv2i32
+    11062942U,	// VQRDMLSHslv4i16
+    11587230U,	// VQRDMLSHslv4i32
+    11062942U,	// VQRDMLSHslv8i16
+    11579038U,	// VQRDMLSHv2i32
+    11054750U,	// VQRDMLSHv4i16
+    11579038U,	// VQRDMLSHv4i32
+    11054750U,	// VQRDMLSHv8i16
+    11578985U,	// VQRDMULHslv2i32
+    11054697U,	// VQRDMULHslv4i16
+    11578985U,	// VQRDMULHslv4i32
+    11054697U,	// VQRDMULHslv8i16
+    11595369U,	// VQRDMULHv2i32
+    11071081U,	// VQRDMULHv4i16
+    11595369U,	// VQRDMULHv4i32
+    11071081U,	// VQRDMULHv8i16
+    12119962U,	// VQRSHLsv16i8
+    907603866U,	// VQRSHLsv1i64
+    11595674U,	// VQRSHLsv2i32
+    907603866U,	// VQRSHLsv2i64
+    11071386U,	// VQRSHLsv4i16
+    11595674U,	// VQRSHLsv4i32
+    11071386U,	// VQRSHLsv8i16
+    12119962U,	// VQRSHLsv8i8
+    13692826U,	// VQRSHLuv16i8
+    22605722U,	// VQRSHLuv1i64
+    13168538U,	// VQRSHLuv2i32
+    22605722U,	// VQRSHLuv2i64
+    12644250U,	// VQRSHLuv4i16
+    13168538U,	// VQRSHLuv4i32
+    12644250U,	// VQRSHLuv8i16
+    13692826U,	// VQRSHLuv8i8
+    907604140U,	// VQRSHRNsv2i32
+    11595948U,	// VQRSHRNsv4i16
+    11071660U,	// VQRSHRNsv8i8
+    22605996U,	// VQRSHRNuv2i32
+    13168812U,	// VQRSHRNuv4i16
+    12644524U,	// VQRSHRNuv8i8
+    907604192U,	// VQRSHRUNv2i32
+    11596000U,	// VQRSHRUNv4i16
+    11071712U,	// VQRSHRUNv8i8
+    12119949U,	// VQSHLsiv16i8
+    907603853U,	// VQSHLsiv1i64
+    11595661U,	// VQSHLsiv2i32
+    907603853U,	// VQSHLsiv2i64
+    11071373U,	// VQSHLsiv4i16
+    11595661U,	// VQSHLsiv4i32
+    11071373U,	// VQSHLsiv8i16
+    12119949U,	// VQSHLsiv8i8
+    12121029U,	// VQSHLsuv16i8
+    907604933U,	// VQSHLsuv1i64
+    11596741U,	// VQSHLsuv2i32
+    907604933U,	// VQSHLsuv2i64
+    11072453U,	// VQSHLsuv4i16
+    11596741U,	// VQSHLsuv4i32
+    11072453U,	// VQSHLsuv8i16
+    12121029U,	// VQSHLsuv8i8
+    12119949U,	// VQSHLsv16i8
+    907603853U,	// VQSHLsv1i64
+    11595661U,	// VQSHLsv2i32
+    907603853U,	// VQSHLsv2i64
+    11071373U,	// VQSHLsv4i16
+    11595661U,	// VQSHLsv4i32
+    11071373U,	// VQSHLsv8i16
+    12119949U,	// VQSHLsv8i8
+    13692813U,	// VQSHLuiv16i8
+    22605709U,	// VQSHLuiv1i64
+    13168525U,	// VQSHLuiv2i32
+    22605709U,	// VQSHLuiv2i64
+    12644237U,	// VQSHLuiv4i16
+    13168525U,	// VQSHLuiv4i32
+    12644237U,	// VQSHLuiv8i16
+    13692813U,	// VQSHLuiv8i8
+    13692813U,	// VQSHLuv16i8
+    22605709U,	// VQSHLuv1i64
+    13168525U,	// VQSHLuv2i32
+    22605709U,	// VQSHLuv2i64
+    12644237U,	// VQSHLuv4i16
+    13168525U,	// VQSHLuv4i32
+    12644237U,	// VQSHLuv8i16
+    13692813U,	// VQSHLuv8i8
+    907604133U,	// VQSHRNsv2i32
+    11595941U,	// VQSHRNsv4i16
+    11071653U,	// VQSHRNsv8i8
+    22605989U,	// VQSHRNuv2i32
+    13168805U,	// VQSHRNuv4i16
+    12644517U,	// VQSHRNuv8i8
+    907604184U,	// VQSHRUNv2i32
+    11595992U,	// VQSHRUNv4i16
+    11071704U,	// VQSHRUNv8i8
+    12119247U,	// VQSUBsv16i8
+    907603151U,	// VQSUBsv1i64
+    11594959U,	// VQSUBsv2i32
+    907603151U,	// VQSUBsv2i64
+    11070671U,	// VQSUBsv4i16
+    11594959U,	// VQSUBsv4i32
+    11070671U,	// VQSUBsv8i16
+    12119247U,	// VQSUBsv8i8
+    13692111U,	// VQSUBuv16i8
+    22605007U,	// VQSUBuv1i64
+    13167823U,	// VQSUBuv2i32
+    22605007U,	// VQSUBuv2i64
+    12643535U,	// VQSUBuv4i16
+    13167823U,	// VQSUBuv4i32
+    12643535U,	// VQSUBuv8i16
+    13692111U,	// VQSUBuv8i8
+    895545479U,	// VRADDHNv2i32
+    14217351U,	// VRADDHNv4i16
+    14741639U,	// VRADDHNv8i8
+    13135319U,	// VRECPEd
+    7892439U,	// VRECPEfd
+    7892439U,	// VRECPEfq
+    7368151U,	// VRECPEhd
+    7368151U,	// VRECPEhq
+    13135319U,	// VRECPEq
+    7926354U,	// VRECPSfd
+    7926354U,	// VRECPSfq
+    7402066U,	// VRECPShd
+    7402066U,	// VRECPShq
+    1599992U,	// VREV16d8
+    1599992U,	// VREV16q8
+    551193U,	// VREV32d16
+    1599769U,	// VREV32d8
+    551193U,	// VREV32q16
+    1599769U,	// VREV32q8
+    551279U,	// VREV64d16
+    1075567U,	// VREV64d32
+    1599855U,	// VREV64d8
+    551279U,	// VREV64q16
+    1075567U,	// VREV64q32
+    1599855U,	// VREV64q8
+    12119390U,	// VRHADDsv16i8
+    11595102U,	// VRHADDsv2i32
+    11070814U,	// VRHADDsv4i16
+    11595102U,	// VRHADDsv4i32
+    11070814U,	// VRHADDsv8i16
+    12119390U,	// VRHADDsv8i8
+    13692254U,	// VRHADDuv16i8
+    13167966U,	// VRHADDuv2i32
+    12643678U,	// VRHADDuv4i16
+    13167966U,	// VRHADDuv4i32
+    12643678U,	// VRHADDuv8i16
+    13692254U,	// VRHADDuv8i8
+    875643626U,	// VRINTAD
+    875644148U,	// VRINTAH
+    875643275U,	// VRINTANDf
+    875644148U,	// VRINTANDh
+    875643275U,	// VRINTANQf
+    875644148U,	// VRINTANQh
+    875643275U,	// VRINTAS
+    875643674U,	// VRINTMD
+    875644229U,	// VRINTMH
+    875643334U,	// VRINTMNDf
+    875644229U,	// VRINTMNDh
+    875643334U,	// VRINTMNQf
+    875644229U,	// VRINTMNQh
+    875643334U,	// VRINTMS
+    875643686U,	// VRINTND
+    875644241U,	// VRINTNH
+    875643346U,	// VRINTNNDf
+    875644241U,	// VRINTNNDh
+    875643346U,	// VRINTNNQf
+    875644241U,	// VRINTNNQh
+    875643346U,	// VRINTNS
+    875643698U,	// VRINTPD
+    875644253U,	// VRINTPH
+    875643358U,	// VRINTPNDf
+    875644253U,	// VRINTPNDh
+    875643358U,	// VRINTPNQf
+    875644253U,	// VRINTPNQh
+    875643358U,	// VRINTPS
+    1147695608U,	// VRINTRD
+    7369208U,	// VRINTRH
+    7893496U,	// VRINTRS
+    1147696582U,	// VRINTXD
+    7370182U,	// VRINTXH
+    875643406U,	// VRINTXNDf
+    875644311U,	// VRINTXNDh
+    875643406U,	// VRINTXNQf
+    875644311U,	// VRINTXNQh
+    7894470U,	// VRINTXS
+    1147696632U,	// VRINTZD
+    7370232U,	// VRINTZH
+    875643418U,	// VRINTZNDf
+    875644334U,	// VRINTZNDh
+    875643418U,	// VRINTZNQf
+    875644334U,	// VRINTZNQh
+    7894520U,	// VRINTZS
+    12119969U,	// VRSHLsv16i8
+    907603873U,	// VRSHLsv1i64
+    11595681U,	// VRSHLsv2i32
+    907603873U,	// VRSHLsv2i64
+    11071393U,	// VRSHLsv4i16
+    11595681U,	// VRSHLsv4i32
+    11071393U,	// VRSHLsv8i16
+    12119969U,	// VRSHLsv8i8
+    13692833U,	// VRSHLuv16i8
+    22605729U,	// VRSHLuv1i64
+    13168545U,	// VRSHLuv2i32
+    22605729U,	// VRSHLuv2i64
+    12644257U,	// VRSHLuv4i16
+    13168545U,	// VRSHLuv4i32
+    12644257U,	// VRSHLuv8i16
+    13692833U,	// VRSHLuv8i8
+    895545524U,	// VRSHRNv2i32
+    14217396U,	// VRSHRNv4i16
+    14741684U,	// VRSHRNv8i8
+    12120509U,	// VRSHRsv16i8
+    907604413U,	// VRSHRsv1i64
+    11596221U,	// VRSHRsv2i32
+    907604413U,	// VRSHRsv2i64
+    11071933U,	// VRSHRsv4i16
+    11596221U,	// VRSHRsv4i32
+    11071933U,	// VRSHRsv8i16
+    12120509U,	// VRSHRsv8i8
+    13693373U,	// VRSHRuv16i8
+    22606269U,	// VRSHRuv1i64
+    13169085U,	// VRSHRuv2i32
+    22606269U,	// VRSHRuv2i64
+    12644797U,	// VRSHRuv4i16
+    13169085U,	// VRSHRuv4i32
+    12644797U,	// VRSHRuv8i16
+    13693373U,	// VRSHRuv8i8
+    13135332U,	// VRSQRTEd
+    7892452U,	// VRSQRTEfd
+    7892452U,	// VRSQRTEfq
+    7368164U,	// VRSQRTEhd
+    7368164U,	// VRSQRTEhq
+    13135332U,	// VRSQRTEq
+    7926376U,	// VRSQRTSfd
+    7926376U,	// VRSQRTSfq
+    7402088U,	// VRSQRTShd
+    7402088U,	// VRSQRTShq
+    12102490U,	// VRSRAsv16i8
+    840477530U,	// VRSRAsv1i64
+    11578202U,	// VRSRAsv2i32
+    840477530U,	// VRSRAsv2i64
+    11053914U,	// VRSRAsv4i16
+    11578202U,	// VRSRAsv4i32
+    11053914U,	// VRSRAsv8i16
+    12102490U,	// VRSRAsv8i8
+    13675354U,	// VRSRAuv16i8
+    22588250U,	// VRSRAuv1i64
+    13151066U,	// VRSRAuv2i32
+    22588250U,	// VRSRAuv2i64
+    12626778U,	// VRSRAuv4i16
+    13151066U,	// VRSRAuv4i32
+    12626778U,	// VRSRAuv8i16
+    13675354U,	// VRSRAuv8i8
+    895545464U,	// VRSUBHNv2i32
+    14217336U,	// VRSUBHNv4i16
+    14741624U,	// VRSUBHNv8i8
+    2821312605U,	// VSCCLRMD
+    2821312605U,	// VSCCLRMS
+    808543916U,	// VSDOTD
+    808543916U,	// VSDOTDI
+    808543916U,	// VSDOTQ
+    808543916U,	// VSDOTQI
+    875643710U,	// VSELEQD
+    875644265U,	// VSELEQH
+    875643370U,	// VSELEQS
+    875643638U,	// VSELGED
+    875644171U,	// VSELGEH
+    875643298U,	// VSELGES
+    875643734U,	// VSELGTD
+    875644299U,	// VSELGTH
+    875643394U,	// VSELGTS
+    875643722U,	// VSELVSD
+    875644287U,	// VSELVSH
+    875643382U,	// VSELVSS
+    570442U,	// VSETLNi16
+    1094730U,	// VSETLNi32
+    1619018U,	// VSETLNi8
+    14741456U,	// VSHLLi16
+    14217168U,	// VSHLLi32
+    15265744U,	// VSHLLi8
+    11595728U,	// VSHLLsv2i64
+    11071440U,	// VSHLLsv4i32
+    12120016U,	// VSHLLsv8i16
+    13168592U,	// VSHLLuv2i64
+    12644304U,	// VSHLLuv4i32
+    13692880U,	// VSHLLuv8i16
+    15265703U,	// VSHLiv16i8
+    895545255U,	// VSHLiv1i64
+    14217127U,	// VSHLiv2i32
+    895545255U,	// VSHLiv2i64
+    14741415U,	// VSHLiv4i16
+    14217127U,	// VSHLiv4i32
+    14741415U,	// VSHLiv8i16
+    15265703U,	// VSHLiv8i8
+    12119975U,	// VSHLsv16i8
+    907603879U,	// VSHLsv1i64
+    11595687U,	// VSHLsv2i32
+    907603879U,	// VSHLsv2i64
+    11071399U,	// VSHLsv4i16
+    11595687U,	// VSHLsv4i32
+    11071399U,	// VSHLsv8i16
+    12119975U,	// VSHLsv8i8
+    13692839U,	// VSHLuv16i8
+    22605735U,	// VSHLuv1i64
+    13168551U,	// VSHLuv2i32
+    22605735U,	// VSHLuv2i64
+    12644263U,	// VSHLuv4i16
+    13168551U,	// VSHLuv4i32
+    12644263U,	// VSHLuv8i16
+    13692839U,	// VSHLuv8i8
+    895545531U,	// VSHRNv2i32
+    14217403U,	// VSHRNv4i16
+    14741691U,	// VSHRNv8i8
+    12120515U,	// VSHRsv16i8
+    907604419U,	// VSHRsv1i64
+    11596227U,	// VSHRsv2i32
+    907604419U,	// VSHRsv2i64
+    11071939U,	// VSHRsv4i16
+    11596227U,	// VSHRsv4i32
+    11071939U,	// VSHRsv8i16
+    12120515U,	// VSHRsv8i8
+    13693379U,	// VSHRuv16i8
+    22606275U,	// VSHRuv1i64
+    13169091U,	// VSHRuv2i32
+    22606275U,	// VSHRuv2i64
+    12644803U,	// VSHRuv4i16
+    13169091U,	// VSHRuv4i32
+    12644803U,	// VSHRuv8i16
+    13693379U,	// VSHRuv8i8
+    35713960U,	// VSHTOD
+    1157690280U,	// VSHTOH
+    36238248U,	// VSHTOS
+    1110471592U,	// VSITOD
+    1110995880U,	// VSITOH
+    1092121512U,	// VSITOS
+    1617672U,	// VSLIv16i8
+    15773448U,	// VSLIv1i64
+    1093384U,	// VSLIv2i32
+    15773448U,	// VSLIv2i64
+    569096U,	// VSLIv4i16
+    1093384U,	// VSLIv4i32
+    569096U,	// VSLIv8i16
+    1617672U,	// VSLIv8i8
+    1177613224U,	// VSLTOD
+    1178137512U,	// VSLTOH
+    1159263144U,	// VSLTOS
+    808543894U,	// VSMMLA
+    1147695975U,	// VSQRTD
+    7369575U,	// VSQRTH
+    7893863U,	// VSQRTS
+    12102496U,	// VSRAsv16i8
+    840477536U,	// VSRAsv1i64
+    11578208U,	// VSRAsv2i32
+    840477536U,	// VSRAsv2i64
+    11053920U,	// VSRAsv4i16
+    11578208U,	// VSRAsv4i32
+    11053920U,	// VSRAsv8i16
+    12102496U,	// VSRAsv8i8
+    13675360U,	// VSRAuv16i8
+    22588256U,	// VSRAuv1i64
+    13151072U,	// VSRAuv2i32
+    22588256U,	// VSRAuv2i64
+    12626784U,	// VSRAuv4i16
+    13151072U,	// VSRAuv4i32
+    12626784U,	// VSRAuv8i16
+    13675360U,	// VSRAuv8i8
+    1617677U,	// VSRIv16i8
+    15773453U,	// VSRIv1i64
+    1093389U,	// VSRIv2i32
+    15773453U,	// VSRIv2i64
+    569101U,	// VSRIv4i16
+    1093389U,	// VSRIv4i32
+    569101U,	// VSRIv8i16
+    1617677U,	// VSRIv8i8
+    833661199U,	// VST1LNd16
+    2914126095U,	// VST1LNd16_UPD
+    834185487U,	// VST1LNd32
+    2914650383U,	// VST1LNd32_UPD
+    834709775U,	// VST1LNd8
+    2915174671U,	// VST1LNd8_UPD
     0U,	// VST1LNq16Pseudo
     0U,	// VST1LNq16Pseudo_UPD
     0U,	// VST1LNq32Pseudo
     0U,	// VST1LNq32Pseudo_UPD
     0U,	// VST1LNq8Pseudo
     0U,	// VST1LNq8Pseudo_UPD
-    570586745U,	// VST1d16
-    587363961U,	// VST1d16Q
+    2953373967U,	// VST1d16
+    3020482831U,	// VST1d16Q
     0U,	// VST1d16QPseudo
-    604132985U,	// VST1d16Qwb_fixed
-    620914297U,	// VST1d16Qwb_register
-    637695609U,	// VST1d16T
+    0U,	// VST1d16QPseudoWB_fixed
+    0U,	// VST1d16QPseudoWB_register
+    3087575311U,	// VST1d16Qwb_fixed
+    3154692367U,	// VST1d16Qwb_register
+    3221809423U,	// VST1d16T
     0U,	// VST1d16TPseudo
-    654464633U,	// VST1d16Twb_fixed
-    671245945U,	// VST1d16Twb_register
-    688019065U,	// VST1d16wb_fixed
-    704800377U,	// VST1d16wb_register
-    570717817U,	// VST1d32
-    587495033U,	// VST1d32Q
+    0U,	// VST1d16TPseudoWB_fixed
+    0U,	// VST1d16TPseudoWB_register
+    3288901903U,	// VST1d16Twb_fixed
+    3356018959U,	// VST1d16Twb_register
+    3423119631U,	// VST1d16wb_fixed
+    3490236687U,	// VST1d16wb_register
+    2953898255U,	// VST1d32
+    3021007119U,	// VST1d32Q
     0U,	// VST1d32QPseudo
-    604264057U,	// VST1d32Qwb_fixed
-    621045369U,	// VST1d32Qwb_register
-    637826681U,	// VST1d32T
+    0U,	// VST1d32QPseudoWB_fixed
+    0U,	// VST1d32QPseudoWB_register
+    3088099599U,	// VST1d32Qwb_fixed
+    3155216655U,	// VST1d32Qwb_register
+    3222333711U,	// VST1d32T
     0U,	// VST1d32TPseudo
-    654595705U,	// VST1d32Twb_fixed
-    671377017U,	// VST1d32Twb_register
-    688150137U,	// VST1d32wb_fixed
-    704931449U,	// VST1d32wb_register
-    575698553U,	// VST1d64
-    592475769U,	// VST1d64Q
+    0U,	// VST1d32TPseudoWB_fixed
+    0U,	// VST1d32TPseudoWB_register
+    3289426191U,	// VST1d32Twb_fixed
+    3356543247U,	// VST1d32Twb_register
+    3423643919U,	// VST1d32wb_fixed
+    3490760975U,	// VST1d32wb_register
+    2968578319U,	// VST1d64
+    3035687183U,	// VST1d64Q
     0U,	// VST1d64QPseudo
     0U,	// VST1d64QPseudoWB_fixed
     0U,	// VST1d64QPseudoWB_register
-    609244793U,	// VST1d64Qwb_fixed
-    626026105U,	// VST1d64Qwb_register
-    642807417U,	// VST1d64T
+    3102779663U,	// VST1d64Qwb_fixed
+    3169896719U,	// VST1d64Qwb_register
+    3237013775U,	// VST1d64T
     0U,	// VST1d64TPseudo
     0U,	// VST1d64TPseudoWB_fixed
     0U,	// VST1d64TPseudoWB_register
-    659576441U,	// VST1d64Twb_fixed
-    676357753U,	// VST1d64Twb_register
-    693130873U,	// VST1d64wb_fixed
-    709912185U,	// VST1d64wb_register
-    570848889U,	// VST1d8
-    587626105U,	// VST1d8Q
+    3304106255U,	// VST1d64Twb_fixed
+    3371223311U,	// VST1d64Twb_register
+    3438323983U,	// VST1d64wb_fixed
+    3505441039U,	// VST1d64wb_register
+    2954422543U,	// VST1d8
+    3021531407U,	// VST1d8Q
     0U,	// VST1d8QPseudo
-    604395129U,	// VST1d8Qwb_fixed
-    621176441U,	// VST1d8Qwb_register
-    637957753U,	// VST1d8T
+    0U,	// VST1d8QPseudoWB_fixed
+    0U,	// VST1d8QPseudoWB_register
+    3088623887U,	// VST1d8Qwb_fixed
+    3155740943U,	// VST1d8Qwb_register
+    3222857999U,	// VST1d8T
     0U,	// VST1d8TPseudo
-    654726777U,	// VST1d8Twb_fixed
-    671508089U,	// VST1d8Twb_register
-    688281209U,	// VST1d8wb_fixed
-    705062521U,	// VST1d8wb_register
-    721581689U,	// VST1q16
+    0U,	// VST1d8TPseudoWB_fixed
+    0U,	// VST1d8TPseudoWB_register
+    3289950479U,	// VST1d8Twb_fixed
+    3357067535U,	// VST1d8Twb_register
+    3424168207U,	// VST1d8wb_fixed
+    3491285263U,	// VST1d8wb_register
+    3557353743U,	// VST1q16
     0U,	// VST1q16HighQPseudo
+    0U,	// VST1q16HighQPseudo_UPD
     0U,	// VST1q16HighTPseudo
+    0U,	// VST1q16HighTPseudo_UPD
     0U,	// VST1q16LowQPseudo_UPD
     0U,	// VST1q16LowTPseudo_UPD
-    738350713U,	// VST1q16wb_fixed
-    755132025U,	// VST1q16wb_register
-    721712761U,	// VST1q32
+    3624446223U,	// VST1q16wb_fixed
+    3691563279U,	// VST1q16wb_register
+    3557878031U,	// VST1q32
     0U,	// VST1q32HighQPseudo
+    0U,	// VST1q32HighQPseudo_UPD
     0U,	// VST1q32HighTPseudo
+    0U,	// VST1q32HighTPseudo_UPD
     0U,	// VST1q32LowQPseudo_UPD
     0U,	// VST1q32LowTPseudo_UPD
-    738481785U,	// VST1q32wb_fixed
-    755263097U,	// VST1q32wb_register
-    726693497U,	// VST1q64
+    3624970511U,	// VST1q32wb_fixed
+    3692087567U,	// VST1q32wb_register
+    3572558095U,	// VST1q64
     0U,	// VST1q64HighQPseudo
+    0U,	// VST1q64HighQPseudo_UPD
     0U,	// VST1q64HighTPseudo
+    0U,	// VST1q64HighTPseudo_UPD
     0U,	// VST1q64LowQPseudo_UPD
     0U,	// VST1q64LowTPseudo_UPD
-    743462521U,	// VST1q64wb_fixed
-    760243833U,	// VST1q64wb_register
-    721843833U,	// VST1q8
+    3639650575U,	// VST1q64wb_fixed
+    3706767631U,	// VST1q64wb_register
+    3558402319U,	// VST1q8
     0U,	// VST1q8HighQPseudo
+    0U,	// VST1q8HighQPseudo_UPD
     0U,	// VST1q8HighTPseudo
+    0U,	// VST1q8HighTPseudo_UPD
     0U,	// VST1q8LowQPseudo_UPD
     0U,	// VST1q8LowTPseudo_UPD
-    738612857U,	// VST1q8wb_fixed
-    755394169U,	// VST1q8wb_register
-    1247045301U,	// VST2LNd16
+    3625494799U,	// VST1q8wb_fixed
+    3692611855U,	// VST1q8wb_register
+    833669456U,	// VST2LNd16
     0U,	// VST2LNd16Pseudo
     0U,	// VST2LNd16Pseudo_UPD
-    1632999093U,	// VST2LNd16_UPD
-    1247176373U,	// VST2LNd32
+    2914298192U,	// VST2LNd16_UPD
+    834193744U,	// VST2LNd32
     0U,	// VST2LNd32Pseudo
     0U,	// VST2LNd32Pseudo_UPD
-    1633130165U,	// VST2LNd32_UPD
-    1247307445U,	// VST2LNd8
+    2914822480U,	// VST2LNd32_UPD
+    834718032U,	// VST2LNd8
     0U,	// VST2LNd8Pseudo
     0U,	// VST2LNd8Pseudo_UPD
-    1633261237U,	// VST2LNd8_UPD
-    1247045301U,	// VST2LNq16
+    2915346768U,	// VST2LNd8_UPD
+    833669456U,	// VST2LNq16
     0U,	// VST2LNq16Pseudo
     0U,	// VST2LNq16Pseudo_UPD
-    1632999093U,	// VST2LNq16_UPD
-    1247176373U,	// VST2LNq32
+    2914298192U,	// VST2LNq16_UPD
+    834193744U,	// VST2LNq32
     0U,	// VST2LNq32Pseudo
     0U,	// VST2LNq32Pseudo_UPD
-    1633130165U,	// VST2LNq32_UPD
-    771913397U,	// VST2b16
-    788682421U,	// VST2b16wb_fixed
-    805463733U,	// VST2b16wb_register
-    772044469U,	// VST2b32
-    788813493U,	// VST2b32wb_fixed
-    805594805U,	// VST2b32wb_register
-    772175541U,	// VST2b8
-    788944565U,	// VST2b8wb_fixed
-    805725877U,	// VST2b8wb_register
-    721581749U,	// VST2d16
-    738350773U,	// VST2d16wb_fixed
-    755132085U,	// VST2d16wb_register
-    721712821U,	// VST2d32
-    738481845U,	// VST2d32wb_fixed
-    755263157U,	// VST2d32wb_register
-    721843893U,	// VST2d8
-    738612917U,	// VST2d8wb_fixed
-    755394229U,	// VST2d8wb_register
-    587364021U,	// VST2q16
+    2914822480U,	// VST2LNq32_UPD
+    3758680400U,	// VST2b16
+    3825772880U,	// VST2b16wb_fixed
+    3892889936U,	// VST2b16wb_register
+    3759204688U,	// VST2b32
+    3826297168U,	// VST2b32wb_fixed
+    3893414224U,	// VST2b32wb_register
+    3759728976U,	// VST2b8
+    3826821456U,	// VST2b8wb_fixed
+    3893938512U,	// VST2b8wb_register
+    3557353808U,	// VST2d16
+    3624446288U,	// VST2d16wb_fixed
+    3691563344U,	// VST2d16wb_register
+    3557878096U,	// VST2d32
+    3624970576U,	// VST2d32wb_fixed
+    3692087632U,	// VST2d32wb_register
+    3558402384U,	// VST2d8
+    3625494864U,	// VST2d8wb_fixed
+    3692611920U,	// VST2d8wb_register
+    3020482896U,	// VST2q16
     0U,	// VST2q16Pseudo
     0U,	// VST2q16PseudoWB_fixed
     0U,	// VST2q16PseudoWB_register
-    604133045U,	// VST2q16wb_fixed
-    620914357U,	// VST2q16wb_register
-    587495093U,	// VST2q32
+    3087575376U,	// VST2q16wb_fixed
+    3154692432U,	// VST2q16wb_register
+    3021007184U,	// VST2q32
     0U,	// VST2q32Pseudo
     0U,	// VST2q32PseudoWB_fixed
     0U,	// VST2q32PseudoWB_register
-    604264117U,	// VST2q32wb_fixed
-    621045429U,	// VST2q32wb_register
-    587626165U,	// VST2q8
+    3088099664U,	// VST2q32wb_fixed
+    3155216720U,	// VST2q32wb_register
+    3021531472U,	// VST2q8
     0U,	// VST2q8Pseudo
     0U,	// VST2q8PseudoWB_fixed
     0U,	// VST2q8PseudoWB_register
-    604395189U,	// VST2q8wb_fixed
-    621176501U,	// VST2q8wb_register
-    1247073989U,	// VST3LNd16
+    3088623952U,	// VST2q8wb_fixed
+    3155741008U,	// VST2q8wb_register
+    833751397U,	// VST3LNd16
     0U,	// VST3LNd16Pseudo
     0U,	// VST3LNd16Pseudo_UPD
-    1633011397U,	// VST3LNd16_UPD
-    1247205061U,	// VST3LNd32
+    2914322789U,	// VST3LNd16_UPD
+    834275685U,	// VST3LNd32
     0U,	// VST3LNd32Pseudo
     0U,	// VST3LNd32Pseudo_UPD
-    1633142469U,	// VST3LNd32_UPD
-    1247336133U,	// VST3LNd8
+    2914847077U,	// VST3LNd32_UPD
+    834799973U,	// VST3LNd8
     0U,	// VST3LNd8Pseudo
     0U,	// VST3LNd8Pseudo_UPD
-    1633273541U,	// VST3LNd8_UPD
-    1247073989U,	// VST3LNq16
+    2915371365U,	// VST3LNd8_UPD
+    833751397U,	// VST3LNq16
     0U,	// VST3LNq16Pseudo
     0U,	// VST3LNq16Pseudo_UPD
-    1633011397U,	// VST3LNq16_UPD
-    1247205061U,	// VST3LNq32
+    2914322789U,	// VST3LNq16_UPD
+    834275685U,	// VST3LNq32
     0U,	// VST3LNq32Pseudo
     0U,	// VST3LNq32Pseudo_UPD
-    1633142469U,	// VST3LNq32_UPD
-    173303493U,	// VST3d16
+    2914847077U,	// VST3LNq32_UPD
+    833669477U,	// VST3d16
     0U,	// VST3d16Pseudo
     0U,	// VST3d16Pseudo_UPD
-    559257285U,	// VST3d16_UPD
-    173434565U,	// VST3d32
+    2914298213U,	// VST3d16_UPD
+    834193765U,	// VST3d32
     0U,	// VST3d32Pseudo
     0U,	// VST3d32Pseudo_UPD
-    559388357U,	// VST3d32_UPD
-    173565637U,	// VST3d8
+    2914822501U,	// VST3d32_UPD
+    834718053U,	// VST3d8
     0U,	// VST3d8Pseudo
     0U,	// VST3d8Pseudo_UPD
-    559519429U,	// VST3d8_UPD
-    173303493U,	// VST3q16
+    2915346789U,	// VST3d8_UPD
+    833669477U,	// VST3q16
     0U,	// VST3q16Pseudo_UPD
-    559257285U,	// VST3q16_UPD
+    2914298213U,	// VST3q16_UPD
     0U,	// VST3q16oddPseudo
     0U,	// VST3q16oddPseudo_UPD
-    173434565U,	// VST3q32
+    834193765U,	// VST3q32
     0U,	// VST3q32Pseudo_UPD
-    559388357U,	// VST3q32_UPD
+    2914822501U,	// VST3q32_UPD
     0U,	// VST3q32oddPseudo
     0U,	// VST3q32oddPseudo_UPD
-    173565637U,	// VST3q8
+    834718053U,	// VST3q8
     0U,	// VST3q8Pseudo_UPD
-    559519429U,	// VST3q8_UPD
+    2915346789U,	// VST3q8_UPD
     0U,	// VST3q8oddPseudo
     0U,	// VST3q8oddPseudo_UPD
-    1247123158U,	// VST4LNd16
+    833923451U,	// VST4LNd16
     0U,	// VST4LNd16Pseudo
     0U,	// VST4LNd16Pseudo_UPD
-    1633003222U,	// VST4LNd16_UPD
-    1247254230U,	// VST4LNd32
+    2914306427U,	// VST4LNd16_UPD
+    834447739U,	// VST4LNd32
     0U,	// VST4LNd32Pseudo
     0U,	// VST4LNd32Pseudo_UPD
-    1633134294U,	// VST4LNd32_UPD
-    1247385302U,	// VST4LNd8
+    2914830715U,	// VST4LNd32_UPD
+    834972027U,	// VST4LNd8
     0U,	// VST4LNd8Pseudo
     0U,	// VST4LNd8Pseudo_UPD
-    1633265366U,	// VST4LNd8_UPD
-    1247123158U,	// VST4LNq16
+    2915355003U,	// VST4LNd8_UPD
+    833923451U,	// VST4LNq16
     0U,	// VST4LNq16Pseudo
     0U,	// VST4LNq16Pseudo_UPD
-    1633003222U,	// VST4LNq16_UPD
-    1247254230U,	// VST4LNq32
+    2914306427U,	// VST4LNq16_UPD
+    834447739U,	// VST4LNq32
     0U,	// VST4LNq32Pseudo
     0U,	// VST4LNq32Pseudo_UPD
-    1633134294U,	// VST4LNq32_UPD
-    173332182U,	// VST4d16
+    2914830715U,	// VST4LNq32_UPD
+    833751419U,	// VST4d16
     0U,	// VST4d16Pseudo
     0U,	// VST4d16Pseudo_UPD
-    559269590U,	// VST4d16_UPD
-    173463254U,	// VST4d32
+    2914322811U,	// VST4d16_UPD
+    834275707U,	// VST4d32
     0U,	// VST4d32Pseudo
     0U,	// VST4d32Pseudo_UPD
-    559400662U,	// VST4d32_UPD
-    173594326U,	// VST4d8
+    2914847099U,	// VST4d32_UPD
+    834799995U,	// VST4d8
     0U,	// VST4d8Pseudo
     0U,	// VST4d8Pseudo_UPD
-    559531734U,	// VST4d8_UPD
-    173332182U,	// VST4q16
+    2915371387U,	// VST4d8_UPD
+    833751419U,	// VST4q16
     0U,	// VST4q16Pseudo_UPD
-    559269590U,	// VST4q16_UPD
+    2914322811U,	// VST4q16_UPD
     0U,	// VST4q16oddPseudo
     0U,	// VST4q16oddPseudo_UPD
-    173463254U,	// VST4q32
+    834275707U,	// VST4q32
     0U,	// VST4q32Pseudo_UPD
-    559400662U,	// VST4q32_UPD
+    2914847099U,	// VST4q32_UPD
     0U,	// VST4q32oddPseudo
     0U,	// VST4q32oddPseudo_UPD
-    173594326U,	// VST4q8
+    834799995U,	// VST4q8
     0U,	// VST4q8Pseudo_UPD
-    559531734U,	// VST4q8_UPD
+    2915371387U,	// VST4q8_UPD
     0U,	// VST4q8oddPseudo
     0U,	// VST4q8oddPseudo_UPD
-    2332571781U,	// VSTMDDB_UPD
-    571413U,	// VSTMDIA
-    2332571669U,	// VSTMDIA_UPD
+    875064297U,	// VSTMDDB_UPD
+    2730773U,	// VSTMDIA
+    875064085U,	// VSTMDIA_UPD
     0U,	// VSTMQIA
-    2332571781U,	// VSTMSDB_UPD
-    571413U,	// VSTMSIA
-    2332571669U,	// VSTMSIA_UPD
-    556179U,	// VSTRD
-    162963U,	// VSTRH
-    556179U,	// VSTRS
-    252868870U,	// VSUBD
-    252999942U,	// VSUBH
-    187464606U,	// VSUBHNv2i32
-    187595678U,	// VSUBHNv4i16
-    187726750U,	// VSUBHNv8i8
-    186677999U,	// VSUBLsv2i64
-    186809071U,	// VSUBLsv4i32
-    186940143U,	// VSUBLsv8i16
-    187071215U,	// VSUBLuv2i64
-    187202287U,	// VSUBLuv4i32
-    187333359U,	// VSUBLuv8i16
-    253131014U,	// VSUBS
-    186678766U,	// VSUBWsv2i64
-    186809838U,	// VSUBWsv4i32
-    186940910U,	// VSUBWsv8i16
-    187071982U,	// VSUBWuv2i64
-    187203054U,	// VSUBWuv4i32
-    187334126U,	// VSUBWuv8i16
-    253131014U,	// VSUBfd
-    253131014U,	// VSUBfq
-    252999942U,	// VSUBhd
-    252999942U,	// VSUBhq
-    187857158U,	// VSUBv16i8
-    187463942U,	// VSUBv1i64
-    187595014U,	// VSUBv2i32
-    187463942U,	// VSUBv2i64
-    187726086U,	// VSUBv4i16
-    187595014U,	// VSUBv4i32
-    187726086U,	// VSUBv8i16
-    187857158U,	// VSUBv8i8
-    547888U,	// VSWPd
-    547888U,	// VSWPq
-    424682U,	// VTBL1
-    424682U,	// VTBL2
-    424682U,	// VTBL3
+    875064297U,	// VSTMSDB_UPD
+    2730773U,	// VSTMSIA
+    875064085U,	// VSTMSIA_UPD
+    2683391U,	// VSTRD
+    586239U,	// VSTRH
+    2683391U,	// VSTRS
+    2580050431U,	// VSTR_FPCXTNS_off
+    701035007U,	// VSTR_FPCXTNS_post
+    2647192063U,	// VSTR_FPCXTNS_pre
+    2580574719U,	// VSTR_FPCXTS_off
+    701559295U,	// VSTR_FPCXTS_post
+    2647716351U,	// VSTR_FPCXTS_pre
+    2581099007U,	// VSTR_FPSCR_NZCVQC_off
+    702083583U,	// VSTR_FPSCR_NZCVQC_post
+    2648240639U,	// VSTR_FPSCR_NZCVQC_pre
+    2581623295U,	// VSTR_FPSCR_off
+    702607871U,	// VSTR_FPSCR_post
+    2648764927U,	// VSTR_FPSCR_pre
+    2716398079U,	// VSTR_P0_off
+    1642639871U,	// VSTR_P0_post
+    2783490559U,	// VSTR_P0_pre
+    2582671871U,	// VSTR_VPR_off
+    703656447U,	// VSTR_VPR_post
+    2649813503U,	// VSTR_VPR_pre
+    1147727061U,	// VSUBD
+    7400661U,	// VSUBH
+    895545472U,	// VSUBHNv2i32
+    14217344U,	// VSUBHNv4i16
+    14741632U,	// VSUBHNv8i8
+    11595604U,	// VSUBLsv2i64
+    11071316U,	// VSUBLsv4i32
+    12119892U,	// VSUBLsv8i16
+    13168468U,	// VSUBLuv2i64
+    12644180U,	// VSUBLuv4i32
+    13692756U,	// VSUBLuv8i16
+    7924949U,	// VSUBS
+    11596885U,	// VSUBWsv2i64
+    11072597U,	// VSUBWsv4i32
+    12121173U,	// VSUBWsv8i16
+    13169749U,	// VSUBWuv2i64
+    12645461U,	// VSUBWuv4i32
+    13694037U,	// VSUBWuv8i16
+    7924949U,	// VSUBfd
+    7924949U,	// VSUBfq
+    7400661U,	// VSUBhd
+    7400661U,	// VSUBhq
+    15264981U,	// VSUBv16i8
+    895544533U,	// VSUBv1i64
+    14216405U,	// VSUBv2i32
+    895544533U,	// VSUBv2i64
+    14740693U,	// VSUBv4i16
+    14216405U,	// VSUBv4i32
+    14740693U,	// VSUBv8i16
+    15264981U,	// VSUBv8i8
+    808543937U,	// VSUDOTDI
+    808543937U,	// VSUDOTQI
+    2666883U,	// VSWPd
+    2666883U,	// VSWPq
+    1634127U,	// VTBL1
+    1634127U,	// VTBL2
+    1634127U,	// VTBL3
     0U,	// VTBL3Pseudo
-    424682U,	// VTBL4
+    1634127U,	// VTBL4
     0U,	// VTBL4Pseudo
-    417355U,	// VTBX1
-    417355U,	// VTBX2
-    417355U,	// VTBX3
+    1619202U,	// VTBX1
+    1619202U,	// VTBX2
+    1619202U,	// VTBX3
     0U,	// VTBX3Pseudo
-    417355U,	// VTBX4
+    1619202U,	// VTBX4
     0U,	// VTBX4Pseudo
-    7634354U,	// VTOSHD
-    256146866U,	// VTOSHH
-    7765426U,	// VTOSHS
-    441597080U,	// VTOSIRD
-    444087448U,	// VTOSIRH
-    440417432U,	// VTOSIRS
-    441597362U,	// VTOSIZD
-    444087730U,	// VTOSIZH
-    440417714U,	// VTOSIZS
-    1330806194U,	// VTOSLD
-    1333296562U,	// VTOSLH
-    1329626546U,	// VTOSLS
-    8027570U,	// VTOUHD
-    256277938U,	// VTOUHH
-    8158642U,	// VTOUHS
-    444480664U,	// VTOUIRD
-    444611736U,	// VTOUIRH
-    440548504U,	// VTOUIRS
-    444480946U,	// VTOUIZD
-    444612018U,	// VTOUIZH
-    440548786U,	// VTOUIZS
-    1333689778U,	// VTOULD
-    1333820850U,	// VTOULH
-    1329757618U,	// VTOULS
-    154596U,	// VTRNd16
-    285668U,	// VTRNd32
-    416740U,	// VTRNd8
-    154596U,	// VTRNq16
-    285668U,	// VTRNq32
-    416740U,	// VTRNq8
-    425351U,	// VTSTv16i8
-    294279U,	// VTSTv2i32
-    163207U,	// VTSTv4i16
-    294279U,	// VTSTv4i32
-    163207U,	// VTSTv8i16
-    425351U,	// VTSTv8i8
-    910483U,	// VUDOTD
-    7070867U,	// VUDOTDI
-    910483U,	// VUDOTQ
-    7070867U,	// VUDOTQI
-    8551858U,	// VUHTOD
-    256802226U,	// VUHTOH
-    8682930U,	// VUHTOS
-    445005234U,	// VUITOD
-    445136306U,	// VUITOH
-    441204146U,	// VUITOS
-    1334214066U,	// VULTOD
-    1334345138U,	// VULTOH
-    1330412978U,	// VULTOS
-    154677U,	// VUZPd16
-    416821U,	// VUZPd8
-    154677U,	// VUZPq16
-    285749U,	// VUZPq32
-    416821U,	// VUZPq8
-    154653U,	// VZIPd16
-    416797U,	// VZIPd8
-    154653U,	// VZIPq16
-    285725U,	// VZIPq32
-    416797U,	// VZIPq8
-    571388U,	// sysLDMDA
-    2332571644U,	// sysLDMDA_UPD
-    571519U,	// sysLDMDB
-    2332571775U,	// sysLDMDB_UPD
-    572300U,	// sysLDMIA
-    2332572556U,	// sysLDMIA_UPD
-    571538U,	// sysLDMIB
-    2332571794U,	// sysLDMIB_UPD
-    571394U,	// sysSTMDA
-    2332571650U,	// sysSTMDA_UPD
-    571526U,	// sysSTMDB
-    2332571782U,	// sysSTMDB_UPD
-    572306U,	// sysSTMIA
-    2332572562U,	// sysSTMIA_UPD
-    571544U,	// sysSTMIB
-    2332571800U,	// sysSTMIB_UPD
-    530745U,	// t2ADCri
-    9050425U,	// t2ADCrr
-    9079097U,	// t2ADCrs
-    9050486U,	// t2ADDri
-    556533U,	// t2ADDri12
-    9050486U,	// t2ADDrr
-    9079158U,	// t2ADDrs
-    9059406U,	// t2ADR
-    530859U,	// t2ANDri
-    9050539U,	// t2ANDrr
-    9079211U,	// t2ANDrs
-    9051260U,	// t2ASRri
-    9051260U,	// t2ASRrr
-    1082832976U,	// t2B
-    555329U,	// t2BFC
-    547483U,	// t2BFI
-    530758U,	// t2BICri
-    9050438U,	// t2BICrr
-    9079110U,	// t2BICrs
-    1074313901U,	// t2BXJ
-    1082832976U,	// t2Bcc
-    201907225U,	// t2CDP
-    201905823U,	// t2CDP2
-    839310U,	// t2CLREX
-    540368U,	// t2CLZ
-    9059263U,	// t2CMNri
-    9059263U,	// t2CMNzrr
-    9075647U,	// t2CMNzrs
-    9059363U,	// t2CMPri
-    9059363U,	// t2CMPrr
-    9075747U,	// t2CMPrs
-    828709U,	// t2CPS1p
-    1317731549U,	// t2CPS2p
-    235470045U,	// t2CPS3p
-    185246891U,	// t2CRC32B
-    185246899U,	// t2CRC32CB
-    185246973U,	// t2CRC32CH
-    185247057U,	// t2CRC32CW
-    185246965U,	// t2CRC32H
-    185247049U,	// t2CRC32W
-    1074313739U,	// t2DBG
-    837235U,	// t2DCPS1
-    837295U,	// t2DCPS2
-    837311U,	// t2DCPS3
-    822655139U,	// t2DMB
-    822655158U,	// t2DSB
-    531562U,	// t2EORri
-    9051242U,	// t2EORrr
-    9079914U,	// t2EORrs
-    1082834290U,	// t2HINT
-    828731U,	// t2HVC
-    839432378U,	// t2ISB
-    17313120U,	// t2IT
+    37811112U,	// VTOSHD
+    1160311720U,	// VTOSHH
+    38335400U,	// VTOSHS
+    1101558276U,	// VTOSIRD
+    1112568324U,	// VTOSIRH
+    1093693956U,	// VTOSIRS
+    1101558696U,	// VTOSIZD
+    1112568744U,	// VTOSIZH
+    1093694376U,	// VTOSIZS
+    1168700328U,	// VTOSLD
+    1179710376U,	// VTOSLH
+    1160836008U,	// VTOSLS
+    39383976U,	// VTOUHD
+    1161360296U,	// VTOUHH
+    39908264U,	// VTOUHS
+    1114141188U,	// VTOUIRD
+    1114665476U,	// VTOUIRH
+    1094742532U,	// VTOUIRS
+    1114141608U,	// VTOUIZD
+    1114665896U,	// VTOUIZH
+    1094742952U,	// VTOUIZS
+    1181283240U,	// VTOULD
+    1181807528U,	// VTOULH
+    1161884584U,	// VTOULS
+    569542U,	// VTRNd16
+    1093830U,	// VTRNd32
+    1618118U,	// VTRNd8
+    569542U,	// VTRNq16
+    1093830U,	// VTRNq32
+    1618118U,	// VTRNq8
+    1635191U,	// VTSTv16i8
+    1110903U,	// VTSTv2i32
+    586615U,	// VTSTv4i16
+    1110903U,	// VTSTv4i32
+    586615U,	// VTSTv8i16
+    1635191U,	// VTSTv8i8
+    808543948U,	// VUDOTD
+    808543948U,	// VUDOTDI
+    808543948U,	// VUDOTQ
+    808543948U,	// VUDOTQI
+    41481128U,	// VUHTOD
+    1158214568U,	// VUHTOH
+    42005416U,	// VUHTOS
+    1116238760U,	// VUITOD
+    1116763048U,	// VUITOH
+    1092645800U,	// VUITOS
+    1183380392U,	// VULTOD
+    1183904680U,	// VULTOH
+    1159787432U,	// VULTOS
+    808543926U,	// VUMMLA
+    808543905U,	// VUSDOTD
+    808543905U,	// VUSDOTDI
+    808543905U,	// VUSDOTQ
+    808543905U,	// VUSDOTQI
+    808543882U,	// VUSMMLA
+    569736U,	// VUZPd16
+    1618312U,	// VUZPd8
+    569736U,	// VUZPq16
+    1094024U,	// VUZPq32
+    1618312U,	// VUZPq8
+    569612U,	// VZIPd16
+    1618188U,	// VZIPd8
+    569612U,	// VZIPq16
+    1093900U,	// VZIPq32
+    1618188U,	// VZIPq8
+    2730724U,	// sysLDMDA
+    875064036U,	// sysLDMDA_UPD
+    2730979U,	// sysLDMDB
+    875064291U,	// sysLDMDB_UPD
+    2732107U,	// sysLDMIA
+    875065419U,	// sysLDMIA_UPD
+    2730998U,	// sysLDMIB
+    875064310U,	// sysLDMIB_UPD
+    2730730U,	// sysSTMDA
+    875064042U,	// sysSTMDA_UPD
+    2730986U,	// sysSTMDB
+    875064298U,	// sysSTMDB_UPD
+    2732142U,	// sysSTMIA
+    875065454U,	// sysSTMIA_UPD
+    2731004U,	// sysSTMIB
+    875064316U,	// sysSTMIB_UPD
+    2632970U,	// t2ADCri
+    43527434U,	// t2ADCrr
+    43584778U,	// t2ADCrs
+    43527502U,	// t2ADDri
+    2683996U,	// t2ADDri12
+    43527502U,	// t2ADDrr
+    43584846U,	// t2ADDrs
+    43527502U,	// t2ADDspImm
+    2683996U,	// t2ADDspImm12
+    43544993U,	// t2ADR
+    2633103U,	// t2ANDri
+    43527567U,	// t2ANDrr
+    43584911U,	// t2ANDrs
+    43528674U,	// t2ASRri
+    43528674U,	// t2ASRrr
+    4413U,	// t2AUT
+    808046091U,	// t2AUTG
+    983149492U,	// t2B
+    2682130U,	// t2BFC
+    2666240U,	// t2BFI
+    942174077U,	// t2BFLi
+    942175649U,	// t2BFLr
+    942173676U,	// t2BFi
+    3962668948U,	// t2BFic
+    942175570U,	// t2BFr
+    2632983U,	// t2BICri
+    43527447U,	// t2BICrr
+    43584791U,	// t2BICrs
+    1917U,	// t2BTI
+    808047516U,	// t2BXAUT
+    2731794U,	// t2BXJ
+    983149492U,	// t2Bcc
+    1277825288U,	// t2CDP
+    1277823290U,	// t2CDP2
+    4314437U,	// t2CLREX
+    2821312608U,	// t2CLRM
+    2651636U,	// t2CLZ
+    43544737U,	// t2CMNri
+    43544737U,	// t2CMNzrr
+    43577505U,	// t2CMNzrs
+    43544850U,	// t2CMPri
+    43544850U,	// t2CMPrr
+    43577618U,	// t2CMPrs
+    4278196U,	// t2CPS1p
+    1452986965U,	// t2CPS2p
+    1412092501U,	// t2CPS3p
+    875644665U,	// t2CRC32B
+    875644673U,	// t2CRC32CB
+    875644783U,	// t2CRC32CH
+    875644903U,	// t2CRC32CW
+    875644775U,	// t2CRC32H
+    875644895U,	// t2CRC32W
+    875644822U,	// t2CSEL
+    875644716U,	// t2CSINC
+    875644874U,	// t2CSINV
+    875644768U,	// t2CSNEG
+    2731508U,	// t2DBG
+    4311305U,	// t2DCPS1
+    4311370U,	// t2DCPS2
+    4311391U,	// t2DCPS3
+    875644842U,	// t2DLS
+    4029262885U,	// t2DMB
+    4029262981U,	// t2DSB
+    2634192U,	// t2EORri
+    43528656U,	// t2EORrr
+    43586000U,	// t2EORrs
+    43627272U,	// t2HINT
+    4278225U,	// t2HVC
+    4096371849U,	// t2ISB
+    69751512U,	// t2IT
     0U,	// t2Int_eh_sjlj_setjmp
     0U,	// t2Int_eh_sjlj_setjmp_nofp
-    538616U,	// t2LDA
-    538701U,	// t2LDAB
-    540284U,	// t2LDAEX
-    538905U,	// t2LDAEXB
-    555461U,	// t2LDAEXD
-    539263U,	// t2LDAEXH
-    539165U,	// t2LDAH
-    1275615921U,	// t2LDC2L_OFFSET
-    1275615921U,	// t2LDC2L_OPTION
-    1275615921U,	// t2LDC2L_POST
-    1275615921U,	// t2LDC2L_PRE
-    1275614853U,	// t2LDC2_OFFSET
-    1275614853U,	// t2LDC2_OPTION
-    1275614853U,	// t2LDC2_POST
-    1275614853U,	// t2LDC2_PRE
-    1275615989U,	// t2LDCL_OFFSET
-    1275615989U,	// t2LDCL_OPTION
-    1275615989U,	// t2LDCL_POST
-    1275615989U,	// t2LDCL_PRE
-    1275615549U,	// t2LDC_OFFSET
-    1275615549U,	// t2LDC_OPTION
-    1275615549U,	// t2LDC_POST
-    1275615549U,	// t2LDC_PRE
-    571519U,	// t2LDMDB
-    2332571775U,	// t2LDMDB_UPD
-    9091980U,	// t2LDMIA
-    2341092236U,	// t2LDMIA_UPD
-    556328U,	// t2LDRBT
-    546988U,	// t2LDRB_POST
-    546988U,	// t2LDRB_PRE
-    9074860U,	// t2LDRBi12
-    555180U,	// t2LDRBi8
-    9058476U,	// t2LDRBpci
-    9066668U,	// t2LDRBs
-    551343U,	// t2LDRD_POST
-    551343U,	// t2LDRD_PRE
-    547247U,	// t2LDRDi8
-    556680U,	// t2LDREX
-    538919U,	// t2LDREXB
-    555475U,	// t2LDREXD
-    539277U,	// t2LDREXH
-    556363U,	// t2LDRHT
-    547409U,	// t2LDRH_POST
-    547409U,	// t2LDRH_PRE
-    9075281U,	// t2LDRHi12
-    555601U,	// t2LDRHi8
-    9058897U,	// t2LDRHpci
-    9067089U,	// t2LDRHs
-    556340U,	// t2LDRSBT
-    547006U,	// t2LDRSB_POST
-    547006U,	// t2LDRSB_PRE
-    9074878U,	// t2LDRSBi12
-    555198U,	// t2LDRSBi8
-    9058494U,	// t2LDRSBpci
-    9066686U,	// t2LDRSBs
-    556375U,	// t2LDRSHT
-    547428U,	// t2LDRSH_POST
-    547428U,	// t2LDRSH_PRE
-    9075300U,	// t2LDRSHi12
-    555620U,	// t2LDRSHi8
-    9058916U,	// t2LDRSHpci
-    9067108U,	// t2LDRSHs
-    556407U,	// t2LDRT
-    547923U,	// t2LDR_POST
-    547923U,	// t2LDR_PRE
-    9075795U,	// t2LDRi12
-    556115U,	// t2LDRi8
-    9059411U,	// t2LDRpci
-    9067603U,	// t2LDRs
-    9050981U,	// t2LSLri
-    9050981U,	// t2LSLrr
-    9051267U,	// t2LSRri
-    9051267U,	// t2LSRrr
-    201907274U,	// t2MCR
-    201905828U,	// t2MCR2
-    201878642U,	// t2MCRR
-    201877161U,	// t2MCRR2
-    546852U,	// t2MLA
-    548021U,	// t2MLS
-    556471U,	// t2MOVTi16
-    9063914U,	// t2MOVi
-    540159U,	// t2MOVi16
-    9063914U,	// t2MOVr
-    9059558U,	// t2MOVsra_flag
-    9059563U,	// t2MOVsrl_flag
-    336124238U,	// t2MRC
-    336123530U,	// t2MRC2
-    352872786U,	// t2MRRC
-    352872079U,	// t2MRRC2
-    2148056290U,	// t2MRS_AR
-    539874U,	// t2MRS_M
-    539874U,	// t2MRSbanked
-    3221798114U,	// t2MRSsys_AR
-    369638536U,	// t2MSR_AR
-    369638536U,	// t2MSR_M
-    386415752U,	// t2MSRbanked
-    555893U,	// t2MUL
-    543747U,	// t2MVNi
-    9063427U,	// t2MVNr
-    9051139U,	// t2MVNs
-    531424U,	// t2ORNri
-    531424U,	// t2ORNrr
-    560096U,	// t2ORNrs
-    531576U,	// t2ORRri
-    9051256U,	// t2ORRrr
-    9079928U,	// t2ORRrs
-    548115U,	// t2PKHBT
-    547023U,	// t2PKHTB
-    856178170U,	// t2PLDWi12
-    872955386U,	// t2PLDWi8
-    889748986U,	// t2PLDWs
-    856177055U,	// t2PLDi12
-    872954271U,	// t2PLDi8
-    906541471U,	// t2PLDpci
-    889747871U,	// t2PLDs
-    856177311U,	// t2PLIi12
-    872954527U,	// t2PLIi8
-    906541727U,	// t2PLIpci
-    889748127U,	// t2PLIs
-    555406U,	// t2QADD
-    554800U,	// t2QADD16
-    554903U,	// t2QADD8
-    556729U,	// t2QASX
-    555380U,	// t2QDADD
-    555252U,	// t2QDSUB
-    556588U,	// t2QSAX
-    555265U,	// t2QSUB
-    554762U,	// t2QSUB16
-    554864U,	// t2QSUB8
-    539998U,	// t2RBIT
-    9059798U,	// t2REV
-    9058132U,	// t2REV16
-    9058927U,	// t2REVSH
-    1074313336U,	// t2RFEDB
-    2148055160U,	// t2RFEDBW
-    1074313224U,	// t2RFEIA
-    2148055048U,	// t2RFEIAW
-    9051246U,	// t2RORri
-    9051246U,	// t2RORrr
-    544424U,	// t2RRX
-    9050304U,	// t2RSBri
-    530624U,	// t2RSBrr
-    559296U,	// t2RSBrs
-    554807U,	// t2SADD16
-    554909U,	// t2SADD8
-    556734U,	// t2SASX
-    530741U,	// t2SBCri
-    9050421U,	// t2SBCrr
-    9079093U,	// t2SBCrs
-    548506U,	// t2SBFX
-    556506U,	// t2SDIV
-    555794U,	// t2SEL
-    828701U,	// t2SETPAN
-    838170U,	// t2SG
-    554783U,	// t2SHADD16
-    554888U,	// t2SHADD8
-    556716U,	// t2SHASX
-    556575U,	// t2SHSAX
-    554745U,	// t2SHSUB16
-    554849U,	// t2SHSUB8
-    1074313546U,	// t2SMC
-    546910U,	// t2SMLABB
-    548108U,	// t2SMLABT
-    547171U,	// t2SMLAD
-    548432U,	// t2SMLADX
-    580312U,	// t2SMLAL
-    579685U,	// t2SMLALBB
-    580889U,	// t2SMLALBT
-    579992U,	// t2SMLALD
-    581214U,	// t2SMLALDX
-    579797U,	// t2SMLALTB
-    581011U,	// t2SMLALTT
-    547016U,	// t2SMLATB
-    548236U,	// t2SMLATT
-    547083U,	// t2SMLAWB
-    548284U,	// t2SMLAWT
-    547257U,	// t2SMLSD
-    548462U,	// t2SMLSDX
-    580003U,	// t2SMLSLD
-    581222U,	// t2SMLSLDX
-    546850U,	// t2SMMLA
-    547907U,	// t2SMMLAR
-    548019U,	// t2SMMLS
-    547968U,	// t2SMMLSR
-    555891U,	// t2SMMUL
-    556130U,	// t2SMMULR
-    555369U,	// t2SMUAD
-    556631U,	// t2SMUADX
-    555117U,	// t2SMULBB
-    556321U,	// t2SMULBT
-    547658U,	// t2SMULL
-    555229U,	// t2SMULTB
-    556443U,	// t2SMULTT
-    555282U,	// t2SMULWB
-    556483U,	// t2SMULWT
-    555455U,	// t2SMUSD
-    556661U,	// t2SMUSDX
-    9222284U,	// t2SRSDB
-    9353356U,	// t2SRSDB_UPD
-    9222172U,	// t2SRSIA
-    9353244U,	// t2SRSIA_UPD
-    548093U,	// t2SSAT
-    554821U,	// t2SSAT16
-    556593U,	// t2SSAX
-    554769U,	// t2SSUB16
-    554870U,	// t2SSUB8
-    1275615927U,	// t2STC2L_OFFSET
-    1275615927U,	// t2STC2L_OPTION
-    1275615927U,	// t2STC2L_POST
-    1275615927U,	// t2STC2L_PRE
-    1275614869U,	// t2STC2_OFFSET
-    1275614869U,	// t2STC2_OPTION
-    1275614869U,	// t2STC2_POST
-    1275614869U,	// t2STC2_PRE
-    1275615994U,	// t2STCL_OFFSET
-    1275615994U,	// t2STCL_OPTION
-    1275615994U,	// t2STCL_POST
-    1275615994U,	// t2STCL_PRE
-    1275615579U,	// t2STC_OFFSET
-    1275615579U,	// t2STC_OPTION
-    1275615579U,	// t2STC_POST
-    1275615579U,	// t2STC_PRE
-    539503U,	// t2STL
-    538782U,	// t2STLB
-    556674U,	// t2STLEX
-    555296U,	// t2STLEXB
-    547276U,	// t2STLEXD
-    555654U,	// t2STLEXH
-    539195U,	// t2STLH
-    571526U,	// t2STMDB
-    2332571782U,	// t2STMDB_UPD
-    9091986U,	// t2STMIA
-    2341092242U,	// t2STMIA_UPD
-    556334U,	// t2STRBT
-    185096369U,	// t2STRB_POST
-    185096369U,	// t2STRB_PRE
-    9074865U,	// t2STRBi12
-    555185U,	// t2STRBi8
-    9066673U,	// t2STRBs
-    185100724U,	// t2STRD_POST
-    185100724U,	// t2STRD_PRE
-    547252U,	// t2STRDi8
-    548500U,	// t2STREX
-    555310U,	// t2STREXB
-    547290U,	// t2STREXD
-    555668U,	// t2STREXH
-    556369U,	// t2STRHT
-    185096790U,	// t2STRH_POST
-    185096790U,	// t2STRH_PRE
-    9075286U,	// t2STRHi12
-    555606U,	// t2STRHi8
-    9067094U,	// t2STRHs
-    556418U,	// t2STRT
-    185097364U,	// t2STR_POST
-    185097364U,	// t2STR_PRE
-    9075860U,	// t2STRi12
-    556180U,	// t2STRi8
-    9067668U,	// t2STRs
-    9485481U,	// t2SUBS_PC_LR
-    9050358U,	// t2SUBri
-    556527U,	// t2SUBri12
-    9050358U,	// t2SUBrr
-    9079030U,	// t2SUBrs
-    546898U,	// t2SXTAB
-    546523U,	// t2SXTAB16
-    547371U,	// t2SXTAH
-    9074922U,	// t2SXTB
-    554731U,	// t2SXTB16
-    9075317U,	// t2SXTH
-    923285620U,	// t2TBB
-    940063287U,	// t2TBH
-    9059391U,	// t2TEQri
-    9059391U,	// t2TEQrr
-    9075775U,	// t2TEQrs
-    956872900U,	// t2TSB
-    9059720U,	// t2TSTri
-    9059720U,	// t2TSTrr
-    9076104U,	// t2TSTrs
-    540048U,	// t2TT
-    538697U,	// t2TTA
-    539911U,	// t2TTAT
-    540066U,	// t2TTT
-    554814U,	// t2UADD16
-    554915U,	// t2UADD8
-    556739U,	// t2UASX
-    548511U,	// t2UBFX
-    828738U,	// t2UDF
-    556511U,	// t2UDIV
-    554791U,	// t2UHADD16
-    554895U,	// t2UHADD8
-    556722U,	// t2UHASX
-    556581U,	// t2UHSAX
-    554753U,	// t2UHSUB16
-    554856U,	// t2UHSUB8
-    580285U,	// t2UMAAL
-    580318U,	// t2UMLAL
-    547664U,	// t2UMULL
-    554799U,	// t2UQADD16
-    554902U,	// t2UQADD8
-    556728U,	// t2UQASX
-    556587U,	// t2UQSAX
-    554761U,	// t2UQSUB16
-    554863U,	// t2UQSUB8
-    554882U,	// t2USAD8
-    546650U,	// t2USADA8
-    548098U,	// t2USAT
-    554828U,	// t2USAT16
-    556598U,	// t2USAX
-    554776U,	// t2USUB16
-    554876U,	// t2USUB8
-    546904U,	// t2UXTAB
-    546531U,	// t2UXTAB16
-    547377U,	// t2UXTAH
-    9074927U,	// t2UXTB
-    554738U,	// t2UXTB16
-    9075322U,	// t2UXTH
-    982776121U,	// tADC
-    555382U,	// tADDhirr
-    177469814U,	// tADDi3
-    982776182U,	// tADDi8
-    555382U,	// tADDrSP
-    555382U,	// tADDrSPi
-    177469814U,	// tADDrr
-    555382U,	// tADDspi
-    555382U,	// tADDspr
-    539726U,	// tADR
-    982776235U,	// tAND
-    177470588U,	// tASRri
-    982776956U,	// tASRrr
-    1074313296U,	// tB
-    982776134U,	// tBIC
-    828725U,	// tBKPT
-    1242090220U,	// tBL
-    1242090708U,	// tBLXNSr
-    1242091172U,	// tBLXi
-    1242091172U,	// tBLXr
-    1074314816U,	// tBX
-    1074314447U,	// tBXNS
-    1074313296U,	// tBcc
-    1258988910U,	// tCBNZ
-    1258988905U,	// tCBZ
-    539583U,	// tCMNz
-    539683U,	// tCMPhir
-    539683U,	// tCMPi8
-    539683U,	// tCMPr
-    1308687581U,	// tCPS
-    982776938U,	// tEOR
-    1074314610U,	// tHINT
-    828720U,	// tHLT
+    2648800U,	// t2LDA
+    2649009U,	// t2LDAB
+    2651443U,	// t2LDAEX
+    2649320U,	// t2LDAEXB
+    2682283U,	// t2LDAEXD
+    2649816U,	// t2LDAEXH
+    2649616U,	// t2LDAH
+    1277734678U,	// t2LDC2L_OFFSET
+    1277734678U,	// t2LDC2L_OPTION
+    1277734678U,	// t2LDC2L_POST
+    1009307414U,	// t2LDC2L_PRE
+    1277733152U,	// t2LDC2_OFFSET
+    1277733152U,	// t2LDC2_OPTION
+    1277733152U,	// t2LDC2_POST
+    1009305888U,	// t2LDC2_PRE
+    1277734746U,	// t2LDCL_OFFSET
+    1277734746U,	// t2LDCL_OPTION
+    1277734746U,	// t2LDCL_POST
+    1009307482U,	// t2LDCL_PRE
+    1277734158U,	// t2LDC_OFFSET
+    1277734158U,	// t2LDC_OPTION
+    1277734158U,	// t2LDC_POST
+    1009306894U,	// t2LDC_PRE
+    2730979U,	// t2LDMDB
+    875064291U,	// t2LDMDB_UPD
+    43626571U,	// t2LDMIA
+    915959883U,	// t2LDMIA_UPD
+    2683552U,	// t2LDRBT
+    2665594U,	// t2LDRB_POST
+    2665594U,	// t2LDRB_PRE
+    43576442U,	// t2LDRBi12
+    2681978U,	// t2LDRBi8
+    43543674U,	// t2LDRBpci
+    43560058U,	// t2LDRBs
+    2674068U,	// t2LDRD_POST
+    2674068U,	// t2LDRD_PRE
+    2665876U,	// t2LDRDi8
+    2684223U,	// t2LDREX
+    2649334U,	// t2LDREXB
+    2682297U,	// t2LDREXD
+    2649830U,	// t2LDREXH
+    2683587U,	// t2LDRHT
+    2666112U,	// t2LDRH_POST
+    2666112U,	// t2LDRH_PRE
+    43576960U,	// t2LDRHi12
+    2682496U,	// t2LDRHi8
+    43544192U,	// t2LDRHpci
+    43560576U,	// t2LDRHs
+    2683564U,	// t2LDRSBT
+    2665613U,	// t2LDRSB_POST
+    2665613U,	// t2LDRSB_PRE
+    43576461U,	// t2LDRSBi12
+    2681997U,	// t2LDRSBi8
+    43543693U,	// t2LDRSBpci
+    43560077U,	// t2LDRSBs
+    2683599U,	// t2LDRSHT
+    2666151U,	// t2LDRSH_POST
+    2666151U,	// t2LDRSH_PRE
+    43576999U,	// t2LDRSHi12
+    2682535U,	// t2LDRSHi8
+    43544231U,	// t2LDRSHpci
+    43560615U,	// t2LDRSHs
+    2683746U,	// t2LDRT
+    2666918U,	// t2LDR_POST
+    2666918U,	// t2LDR_PRE
+    43577766U,	// t2LDRi12
+    2683302U,	// t2LDRi8
+    43544998U,	// t2LDRpci
+    43561382U,	// t2LDRs
+    4294487U,	// t2LE
+    1882285911U,	// t2LEUpdate
+    43528222U,	// t2LSLri
+    43528222U,	// t2LSLrr
+    43528681U,	// t2LSRri
+    43528681U,	// t2LSRrr
+    1277825437U,	// t2MCR
+    1277823295U,	// t2MCR2
+    1277743576U,	// t2MCRR
+    1277741380U,	// t2MCRR2
+    2665252U,	// t2MLA
+    2667053U,	// t2MLS
+    2683821U,	// t2MOVTi16
+    43553867U,	// t2MOVi
+    2651250U,	// t2MOVi16
+    43553867U,	// t2MOVr
+    43545182U,	// t2MOVsra_flag
+    43545187U,	// t2MOVsrl_flag
+    1009388837U,	// t2MRC
+    1009387813U,	// t2MRC2
+    1680395561U,	// t2MRRC
+    1680394538U,	// t2MRRC2
+    2732634U,	// t2MRS_AR
+    2650714U,	// t2MRS_M
+    2650714U,	// t2MRSbanked
+    2732634U,	// t2MRSsys_AR
+    1747481070U,	// t2MSR_AR
+    1747481070U,	// t2MSR_M
+    1814589934U,	// t2MSRbanked
+    2682926U,	// t2MUL
+    2658546U,	// t2MVNi
+    43553010U,	// t2MVNr
+    43528434U,	// t2MVNs
+    2633922U,	// t2ORNri
+    2633922U,	// t2ORNrr
+    2691266U,	// t2ORNrs
+    2634206U,	// t2ORRri
+    43528670U,	// t2ORRrr
+    43586014U,	// t2ORRrs
+    4378U,	// t2PAC
+    4394U,	// t2PACBTI
+    2731512U,	// t2PACG
+    2667147U,	// t2PKHBT
+    2665630U,	// t2PKHTB
+    4163400801U,	// t2PLDWi12
+    4230509665U,	// t2PLDWi8
+    2684001U,	// t2PLDWs
+    4163399043U,	// t2PLDi12
+    4230507907U,	// t2PLDi8
+    69840259U,	// t2PLDpci
+    2682243U,	// t2PLDs
+    4163399428U,	// t2PLIi12
+    4230508292U,	// t2PLIi8
+    69840644U,	// t2PLIpci
+    2682628U,	// t2PLIs
+    2682226U,	// t2QADD
+    2681301U,	// t2QADD16
+    2681404U,	// t2QADD8
+    2684343U,	// t2QASX
+    2682200U,	// t2QDADD
+    2682051U,	// t2QDSUB
+    2684089U,	// t2QSAX
+    2682064U,	// t2QSUB
+    2681263U,	// t2QSUB16
+    2681365U,	// t2QSUB8
+    2650838U,	// t2RBIT
+    43545626U,	// t2REV
+    43543033U,	// t2REV16
+    43544242U,	// t2REVSH
+    2730972U,	// t2RFEDB
+    2730972U,	// t2RFEDBW
+    2730760U,	// t2RFEIA
+    2730760U,	// t2RFEIAW
+    43528660U,	// t2RORri
+    43528660U,	// t2RORrr
+    2659750U,	// t2RRX
+    43527311U,	// t2RSBri
+    2632847U,	// t2RSBrr
+    2690191U,	// t2RSBrs
+    2681308U,	// t2SADD16
+    2681410U,	// t2SADD8
+    2684348U,	// t2SASX
+    3206U,	// t2SB
+    2632965U,	// t2SBCri
+    43527429U,	// t2SBCrr
+    43584773U,	// t2SBCrs
+    2667857U,	// t2SBFX
+    2683934U,	// t2SDIV
+    2682745U,	// t2SEL
+    4278172U,	// t2SETPAN
+    4312584U,	// t2SG
+    2681284U,	// t2SHADD16
+    2681389U,	// t2SHADD8
+    2684330U,	// t2SHASX
+    2684076U,	// t2SHSAX
+    2681246U,	// t2SHSUB16
+    2681350U,	// t2SHSUB8
+    2731297U,	// t2SMC
+    2665410U,	// t2SMLABB
+    2667140U,	// t2SMLABT
+    2665786U,	// t2SMLAD
+    2667783U,	// t2SMLADX
+    2756413U,	// t2SMLAL
+    2755529U,	// t2SMLALBB
+    2757265U,	// t2SMLALBT
+    2755964U,	// t2SMLALD
+    2757909U,	// t2SMLALDX
+    2755748U,	// t2SMLALTB
+    2757507U,	// t2SMLALTT
+    2665623U,	// t2SMLATB
+    2667388U,	// t2SMLATT
+    2665690U,	// t2SMLAWB
+    2667442U,	// t2SMLAWT
+    2665887U,	// t2SMLSD
+    2667813U,	// t2SMLSDX
+    2755975U,	// t2SMLSLD
+    2757917U,	// t2SMLSLDX
+    2665256U,	// t2SMMLA
+    2666902U,	// t2SMMLAR
+    2667051U,	// t2SMMLS
+    2666982U,	// t2SMMLSR
+    2682930U,	// t2SMMUL
+    2683336U,	// t2SMMULR
+    2682176U,	// t2SMUAD
+    2684174U,	// t2SMUADX
+    2681809U,	// t2SMULBB
+    2683545U,	// t2SMULBT
+    2666467U,	// t2SMULL
+    2682028U,	// t2SMULTB
+    2683787U,	// t2SMULTT
+    2682081U,	// t2SMULWB
+    2683833U,	// t2SMULWT
+    2682277U,	// t2SMUSD
+    2684204U,	// t2SMUSDX
+    44149744U,	// t2SRSDB
+    44674032U,	// t2SRSDB_UPD
+    44149532U,	// t2SRSIA
+    44673820U,	// t2SRSIA_UPD
+    2667125U,	// t2SSAT
+    2681322U,	// t2SSAT16
+    2684094U,	// t2SSAX
+    2681270U,	// t2SSUB16
+    2681371U,	// t2SSUB8
+    1277734684U,	// t2STC2L_OFFSET
+    1277734684U,	// t2STC2L_OPTION
+    1277734684U,	// t2STC2L_POST
+    1009307420U,	// t2STC2L_PRE
+    1277733168U,	// t2STC2_OFFSET
+    1277733168U,	// t2STC2_OPTION
+    1277733168U,	// t2STC2_POST
+    1009305904U,	// t2STC2_PRE
+    1277734751U,	// t2STCL_OFFSET
+    1277734751U,	// t2STCL_OPTION
+    1277734751U,	// t2STCL_POST
+    1009307487U,	// t2STCL_PRE
+    1277734194U,	// t2STC_OFFSET
+    1277734194U,	// t2STC_OPTION
+    1277734194U,	// t2STC_POST
+    1009306930U,	// t2STC_PRE
+    2650152U,	// t2STL
+    2649113U,	// t2STLB
+    2684217U,	// t2STLEX
+    2682095U,	// t2STLEXB
+    2665906U,	// t2STLEXD
+    2682591U,	// t2STLEXH
+    2649692U,	// t2STLH
+    2730986U,	// t2STMDB
+    875064298U,	// t2STMDB_UPD
+    43626606U,	// t2STMIA
+    915959918U,	// t2STMIA_UPD
+    2683558U,	// t2STRBT
+    875080832U,	// t2STRB_POST
+    875080832U,	// t2STRB_PRE
+    43576448U,	// t2STRBi12
+    2681984U,	// t2STRBi8
+    43560064U,	// t2STRBs
+    875089306U,	// t2STRD_POST
+    875089306U,	// t2STRD_PRE
+    2665882U,	// t2STRDi8
+    2667851U,	// t2STREX
+    2682109U,	// t2STREXB
+    2665920U,	// t2STREXD
+    2682605U,	// t2STREXH
+    2683593U,	// t2STRHT
+    875081350U,	// t2STRH_POST
+    875081350U,	// t2STRH_PRE
+    43576966U,	// t2STRHi12
+    2682502U,	// t2STRHi8
+    43560582U,	// t2STRHs
+    2683757U,	// t2STRT
+    875082240U,	// t2STR_POST
+    875082240U,	// t2STR_PRE
+    43577856U,	// t2STRi12
+    2683392U,	// t2STRi8
+    43561472U,	// t2STRs
+    45199905U,	// t2SUBS_PC_LR
+    43527365U,	// t2SUBri
+    2683990U,	// t2SUBri12
+    43527365U,	// t2SUBrr
+    43584709U,	// t2SUBrs
+    43527365U,	// t2SUBspImm
+    2683990U,	// t2SUBspImm12
+    2665398U,	// t2SXTAB
+    2664832U,	// t2SXTAB16
+    2666022U,	// t2SXTAH
+    43576505U,	// t2SXTB
+    2681232U,	// t2SXTB16
+    43577016U,	// t2SXTH
+    136866776U,	// t2TBB
+    203976242U,	// t2TBH
+    43544978U,	// t2TEQri
+    43544978U,	// t2TEQrr
+    43577746U,	// t2TEQrs
+    271166611U,	// t2TSB
+    43545464U,	// t2TSTri
+    43545464U,	// t2TSTrr
+    43578232U,	// t2TSTrs
+    2651008U,	// t2TT
+    2648940U,	// t2TTA
+    2650751U,	// t2TTAT
+    2651026U,	// t2TTT
+    2681315U,	// t2UADD16
+    2681416U,	// t2UADD8
+    2684353U,	// t2UASX
+    2667862U,	// t2UBFX
+    4278232U,	// t2UDF
+    2683939U,	// t2UDIV
+    2681292U,	// t2UHADD16
+    2681396U,	// t2UHADD8
+    2684336U,	// t2UHASX
+    2684082U,	// t2UHSAX
+    2681254U,	// t2UHSUB16
+    2681357U,	// t2UHSUB8
+    2756386U,	// t2UMAAL
+    2756419U,	// t2UMLAL
+    2666473U,	// t2UMULL
+    2681300U,	// t2UQADD16
+    2681403U,	// t2UQADD8
+    2684342U,	// t2UQASX
+    2684088U,	// t2UQSAX
+    2681262U,	// t2UQSUB16
+    2681364U,	// t2UQSUB8
+    2681383U,	// t2USAD8
+    2664959U,	// t2USADA8
+    2667130U,	// t2USAT
+    2681329U,	// t2USAT16
+    2684099U,	// t2USAX
+    2681277U,	// t2USUB16
+    2681377U,	// t2USUB8
+    2665404U,	// t2UXTAB
+    2664840U,	// t2UXTAB16
+    2666028U,	// t2UXTAH
+    43576510U,	// t2UXTB
+    2681239U,	// t2UXTB16
+    43577021U,	// t2UXTH
+    875644847U,	// t2WLS
+    1253920010U,	// tADC
+    2682190U,	// tADDhirr
+    851266894U,	// tADDi3
+    1253920078U,	// tADDi8
+    2682190U,	// tADDrSP
+    2682190U,	// tADDrSPi
+    851266894U,	// tADDrr
+    2682190U,	// tADDspi
+    2682190U,	// tADDspr
+    2650529U,	// tADR
+    1253920143U,	// tAND
+    851268066U,	// tASRri
+    1253921250U,	// tASRrr
+    942255028U,	// tB
+    1253920023U,	// tBIC
+    4278212U,	// tBKPT
+    1881788241U,	// tBL
+    808047180U,	// tBLXNSr
+    1881789853U,	// tBLXi
+    808048029U,	// tBLXr
+    2733303U,	// tBX
+    2732615U,	// tBXNS
+    942255028U,	// tBcc
+    3962652676U,	// tCBNZ
+    3962652671U,	// tCBZ
+    2650273U,	// tCMNz
+    2650386U,	// tCMPhir
+    2650386U,	// tCMPi8
+    2650386U,	// tCMPr
+    1409471061U,	// tCPS
+    1253921232U,	// tEOR
+    2732808U,	// tHINT
+    4278207U,	// tHLT
     0U,	// tInt_WIN_eh_sjlj_longjmp
     0U,	// tInt_eh_sjlj_longjmp
     0U,	// tInt_eh_sjlj_setjmp
-    572300U,	// tLDMIA
-    555180U,	// tLDRBi
-    555180U,	// tLDRBr
-    555601U,	// tLDRHi
-    555601U,	// tLDRHr
-    555198U,	// tLDRSB
-    555620U,	// tLDRSH
-    556115U,	// tLDRi
-    539731U,	// tLDRpci
-    556115U,	// tLDRr
-    556115U,	// tLDRspi
-    177470309U,	// tLSLri
-    982776677U,	// tLSLrr
-    177470595U,	// tLSRri
-    982776963U,	// tLSRrr
-    1258988842U,	// tMOVSr
-    446037482U,	// tMOVi8
-    540138U,	// tMOVr
-    177470325U,	// tMUL
-    446036995U,	// tMVN
-    982776952U,	// tORR
+    2732107U,	// tLDMIA
+    2681978U,	// tLDRBi
+    2681978U,	// tLDRBr
+    2682496U,	// tLDRHi
+    2682496U,	// tLDRHr
+    2681997U,	// tLDRSB
+    2682535U,	// tLDRSH
+    2683302U,	// tLDRi
+    2650534U,	// tLDRpci
+    2683302U,	// tLDRr
+    2683302U,	// tLDRspi
+    851267614U,	// tLSLri
+    1253920798U,	// tLSLrr
+    851268073U,	// tLSRri
+    1253921257U,	// tLSRrr
+    875644857U,	// tMOVSr
+    1120228427U,	// tMOVi8
+    2651211U,	// tMOVr
+    851267630U,	// tMUL
+    1120227570U,	// tMVN
+    1253921246U,	// tORR
     0U,	// tPICADD
-    990432295U,	// tPOP
-    990431850U,	// tPUSH
-    540118U,	// tREV
-    538452U,	// tREV16
-    539247U,	// tREVSH
-    982776942U,	// tROR
-    429258944U,	// tRSB
-    982776117U,	// tSBC
-    91368U,	// tSETEND
-    2332572562U,	// tSTMIA_UPD
-    555185U,	// tSTRBi
-    555185U,	// tSTRBr
-    555606U,	// tSTRHi
-    555606U,	// tSTRHr
-    556180U,	// tSTRi
-    556180U,	// tSTRr
-    556180U,	// tSTRspi
-    177469686U,	// tSUBi3
-    982776054U,	// tSUBi8
-    177469686U,	// tSUBrr
-    555254U,	// tSUBspi
-    1074313567U,	// tSVC
-    538858U,	// tSXTB
-    539253U,	// tSXTH
-    3092U,	// tTRAP
-    540040U,	// tTST
-    828656U,	// tUDF
-    538863U,	// tUXTB
-    539258U,	// tUXTH
-    1636U,	// t__brkdiv0
+    2821312790U,	// tPOP
+    2821312173U,	// tPUSH
+    2651162U,	// tREV
+    2648569U,	// tREV16
+    2649778U,	// tREVSH
+    1253921236U,	// tROR
+    2126859407U,	// tRSB
+    1253920005U,	// tSBC
+    280399U,	// tSETEND
+    875065454U,	// tSTMIA_UPD
+    2681984U,	// tSTRBi
+    2681984U,	// tSTRBr
+    2682502U,	// tSTRHi
+    2682502U,	// tSTRHr
+    2683392U,	// tSTRi
+    2683392U,	// tSTRr
+    2683392U,	// tSTRspi
+    851266757U,	// tSUBi3
+    1253919941U,	// tSUBi8
+    851266757U,	// tSUBrr
+    2682053U,	// tSUBspi
+    2731318U,	// tSVC
+    2649273U,	// tSXTB
+    2649784U,	// tSXTH
+    4355U,	// tTRAP
+    2651000U,	// tTST
+    4278107U,	// tUDF
+    2649278U,	// tUXTB
+    2649789U,	// tUXTH
+    2298U,	// t__brkdiv0
   };
 
   static const uint32_t OpInfo1[] = {
     0U,	// PHI
     0U,	// INLINEASM
+    0U,	// INLINEASM_BR
     0U,	// CFI_INSTRUCTION
     0U,	// EH_LABEL
     0U,	// GC_LABEL
@@ -3756,16 +5191,23 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// SUBREG_TO_REG
     0U,	// COPY_TO_REGCLASS
     0U,	// DBG_VALUE
+    0U,	// DBG_VALUE_LIST
+    0U,	// DBG_INSTR_REF
+    0U,	// DBG_PHI
     0U,	// DBG_LABEL
     0U,	// REG_SEQUENCE
     0U,	// COPY
     0U,	// BUNDLE
     0U,	// LIFETIME_START
     0U,	// LIFETIME_END
+    0U,	// PSEUDO_PROBE
+    0U,	// ARITH_FENCE
     0U,	// STACKMAP
     0U,	// FENTRY_CALL
     0U,	// PATCHPOINT
     0U,	// LOAD_STACK_GUARD
+    0U,	// PREALLOCATED_SETUP
+    0U,	// PREALLOCATED_ARG
     0U,	// STATEPOINT
     0U,	// LOCAL_ESCAPE
     0U,	// FAULTING_OP
@@ -3777,6 +5219,10 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// PATCHABLE_EVENT_CALL
     0U,	// PATCHABLE_TYPED_EVENT_CALL
     0U,	// ICALL_BRANCH_FUNNEL
+    0U,	// MEMBARRIER
+    0U,	// G_ASSERT_SEXT
+    0U,	// G_ASSERT_ZEXT
+    0U,	// G_ASSERT_ALIGN
     0U,	// G_ADD
     0U,	// G_SUB
     0U,	// G_MUL
@@ -3784,6 +5230,8 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_UDIV
     0U,	// G_SREM
     0U,	// G_UREM
+    0U,	// G_SDIVREM
+    0U,	// G_UDIVREM
     0U,	// G_AND
     0U,	// G_OR
     0U,	// G_XOR
@@ -3795,13 +5243,27 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_UNMERGE_VALUES
     0U,	// G_INSERT
     0U,	// G_MERGE_VALUES
+    0U,	// G_BUILD_VECTOR
+    0U,	// G_BUILD_VECTOR_TRUNC
+    0U,	// G_CONCAT_VECTORS
     0U,	// G_PTRTOINT
     0U,	// G_INTTOPTR
     0U,	// G_BITCAST
+    0U,	// G_FREEZE
+    0U,	// G_INTRINSIC_FPTRUNC_ROUND
+    0U,	// G_INTRINSIC_TRUNC
+    0U,	// G_INTRINSIC_ROUND
+    0U,	// G_INTRINSIC_LRINT
+    0U,	// G_INTRINSIC_ROUNDEVEN
+    0U,	// G_READCYCLECOUNTER
     0U,	// G_LOAD
     0U,	// G_SEXTLOAD
     0U,	// G_ZEXTLOAD
+    0U,	// G_INDEXED_LOAD
+    0U,	// G_INDEXED_SEXTLOAD
+    0U,	// G_INDEXED_ZEXTLOAD
     0U,	// G_STORE
+    0U,	// G_INDEXED_STORE
     0U,	// G_ATOMIC_CMPXCHG_WITH_SUCCESS
     0U,	// G_ATOMIC_CMPXCHG
     0U,	// G_ATOMICRMW_XCHG
@@ -3815,8 +5277,16 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_ATOMICRMW_MIN
     0U,	// G_ATOMICRMW_UMAX
     0U,	// G_ATOMICRMW_UMIN
+    0U,	// G_ATOMICRMW_FADD
+    0U,	// G_ATOMICRMW_FSUB
+    0U,	// G_ATOMICRMW_FMAX
+    0U,	// G_ATOMICRMW_FMIN
+    0U,	// G_ATOMICRMW_UINC_WRAP
+    0U,	// G_ATOMICRMW_UDEC_WRAP
+    0U,	// G_FENCE
     0U,	// G_BRCOND
     0U,	// G_BRINDIRECT
+    0U,	// G_INVOKE_REGION_START
     0U,	// G_INTRINSIC
     0U,	// G_INTRINSIC_W_SIDE_EFFECTS
     0U,	// G_ANYEXT
@@ -3826,32 +5296,58 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_VASTART
     0U,	// G_VAARG
     0U,	// G_SEXT
+    0U,	// G_SEXT_INREG
     0U,	// G_ZEXT
     0U,	// G_SHL
     0U,	// G_LSHR
     0U,	// G_ASHR
+    0U,	// G_FSHL
+    0U,	// G_FSHR
+    0U,	// G_ROTR
+    0U,	// G_ROTL
     0U,	// G_ICMP
     0U,	// G_FCMP
     0U,	// G_SELECT
+    0U,	// G_UADDO
     0U,	// G_UADDE
+    0U,	// G_USUBO
     0U,	// G_USUBE
     0U,	// G_SADDO
+    0U,	// G_SADDE
     0U,	// G_SSUBO
+    0U,	// G_SSUBE
     0U,	// G_UMULO
     0U,	// G_SMULO
     0U,	// G_UMULH
     0U,	// G_SMULH
+    0U,	// G_UADDSAT
+    0U,	// G_SADDSAT
+    0U,	// G_USUBSAT
+    0U,	// G_SSUBSAT
+    0U,	// G_USHLSAT
+    0U,	// G_SSHLSAT
+    0U,	// G_SMULFIX
+    0U,	// G_UMULFIX
+    0U,	// G_SMULFIXSAT
+    0U,	// G_UMULFIXSAT
+    0U,	// G_SDIVFIX
+    0U,	// G_UDIVFIX
+    0U,	// G_SDIVFIXSAT
+    0U,	// G_UDIVFIXSAT
     0U,	// G_FADD
     0U,	// G_FSUB
     0U,	// G_FMUL
     0U,	// G_FMA
+    0U,	// G_FMAD
     0U,	// G_FDIV
     0U,	// G_FREM
     0U,	// G_FPOW
+    0U,	// G_FPOWI
     0U,	// G_FEXP
     0U,	// G_FEXP2
     0U,	// G_FLOG
     0U,	// G_FLOG2
+    0U,	// G_FLOG10
     0U,	// G_FNEG
     0U,	// G_FPEXT
     0U,	// G_FPTRUNC
@@ -3860,15 +5356,78 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// G_SITOFP
     0U,	// G_UITOFP
     0U,	// G_FABS
-    0U,	// G_GEP
-    0U,	// G_PTR_MASK
+    0U,	// G_FCOPYSIGN
+    0U,	// G_IS_FPCLASS
+    0U,	// G_FCANONICALIZE
+    0U,	// G_FMINNUM
+    0U,	// G_FMAXNUM
+    0U,	// G_FMINNUM_IEEE
+    0U,	// G_FMAXNUM_IEEE
+    0U,	// G_FMINIMUM
+    0U,	// G_FMAXIMUM
+    0U,	// G_PTR_ADD
+    0U,	// G_PTRMASK
+    0U,	// G_SMIN
+    0U,	// G_SMAX
+    0U,	// G_UMIN
+    0U,	// G_UMAX
+    0U,	// G_ABS
+    0U,	// G_LROUND
+    0U,	// G_LLROUND
     0U,	// G_BR
+    0U,	// G_BRJT
     0U,	// G_INSERT_VECTOR_ELT
     0U,	// G_EXTRACT_VECTOR_ELT
     0U,	// G_SHUFFLE_VECTOR
+    0U,	// G_CTTZ
+    0U,	// G_CTTZ_ZERO_UNDEF
+    0U,	// G_CTLZ
+    0U,	// G_CTLZ_ZERO_UNDEF
+    0U,	// G_CTPOP
     0U,	// G_BSWAP
+    0U,	// G_BITREVERSE
+    0U,	// G_FCEIL
+    0U,	// G_FCOS
+    0U,	// G_FSIN
+    0U,	// G_FSQRT
+    0U,	// G_FFLOOR
+    0U,	// G_FRINT
+    0U,	// G_FNEARBYINT
     0U,	// G_ADDRSPACE_CAST
     0U,	// G_BLOCK_ADDR
+    0U,	// G_JUMP_TABLE
+    0U,	// G_DYN_STACKALLOC
+    0U,	// G_STRICT_FADD
+    0U,	// G_STRICT_FSUB
+    0U,	// G_STRICT_FMUL
+    0U,	// G_STRICT_FDIV
+    0U,	// G_STRICT_FREM
+    0U,	// G_STRICT_FMA
+    0U,	// G_STRICT_FSQRT
+    0U,	// G_READ_REGISTER
+    0U,	// G_WRITE_REGISTER
+    0U,	// G_MEMCPY
+    0U,	// G_MEMCPY_INLINE
+    0U,	// G_MEMMOVE
+    0U,	// G_MEMSET
+    0U,	// G_BZERO
+    0U,	// G_VECREDUCE_SEQ_FADD
+    0U,	// G_VECREDUCE_SEQ_FMUL
+    0U,	// G_VECREDUCE_FADD
+    0U,	// G_VECREDUCE_FMUL
+    0U,	// G_VECREDUCE_FMAX
+    0U,	// G_VECREDUCE_FMIN
+    0U,	// G_VECREDUCE_ADD
+    0U,	// G_VECREDUCE_MUL
+    0U,	// G_VECREDUCE_AND
+    0U,	// G_VECREDUCE_OR
+    0U,	// G_VECREDUCE_XOR
+    0U,	// G_VECREDUCE_SMAX
+    0U,	// G_VECREDUCE_SMIN
+    0U,	// G_VECREDUCE_UMAX
+    0U,	// G_VECREDUCE_UMIN
+    0U,	// G_SBFX
+    0U,	// G_UBFX
     0U,	// ABS
     0U,	// ADDSri
     0U,	// ADDSrr
@@ -3881,6 +5440,9 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// B
     0U,	// BCCZi64
     0U,	// BCCi64
+    0U,	// BLX_noip
+    0U,	// BLX_pred_noip
+    0U,	// BL_PUSHLR
     0U,	// BMOVPCB_CALL
     0U,	// BMOVPCRX_CALL
     0U,	// BR_JTadd
@@ -3894,7 +5456,6 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// CMP_SWAP_8
     0U,	// CONSTPOOL_ENTRY
     0U,	// COPY_STRUCT_BYVAL_I32
-    0U,	// CompilerBarrier
     0U,	// ITasm
     0U,	// Int_eh_sjlj_dispatchsetup
     0U,	// Int_eh_sjlj_longjmp
@@ -3906,14 +5467,18 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// JUMPTABLE_TBB
     0U,	// JUMPTABLE_TBH
     0U,	// LDMIA_RET
-    8U,	// LDRBT_POST
-    1024U,	// LDRConstPool
+    128U,	// LDRBT_POST
+    16384U,	// LDRConstPool
+    128U,	// LDRHTii
     0U,	// LDRLIT_ga_abs
     0U,	// LDRLIT_ga_pcrel
     0U,	// LDRLIT_ga_pcrel_ldr
-    8U,	// LDRT_POST
+    128U,	// LDRSBTii
+    128U,	// LDRSHTii
+    128U,	// LDRT_POST
     0U,	// LEApcrel
     0U,	// LEApcrelJT
+    0U,	// LOADDUAL
     0U,	// LSLi
     0U,	// LSLr
     0U,	// LSRi
@@ -3934,7 +5499,14 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// MOVi32imm
     0U,	// MOVsra_flag
     0U,	// MOVsrl_flag
+    0U,	// MQPRCopy
+    0U,	// MQQPRLoad
+    0U,	// MQQPRStore
+    0U,	// MQQQQPRLoad
+    0U,	// MQQQQPRStore
     0U,	// MULv5
+    0U,	// MVE_MEMCPYLOOPINST
+    0U,	// MVE_MEMSETLOOPINST
     0U,	// MVNCCi
     0U,	// PICADD
     0U,	// PICLDR
@@ -3948,18 +5520,30 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// RORi
     0U,	// RORr
     0U,	// RRX
-    1024U,	// RRXi
+    16384U,	// RRXi
     0U,	// RSBSri
     0U,	// RSBSrsi
     0U,	// RSBSrsr
+    0U,	// SEH_EpilogEnd
+    0U,	// SEH_EpilogStart
+    0U,	// SEH_Nop
+    0U,	// SEH_Nop_Ret
+    0U,	// SEH_PrologEnd
+    0U,	// SEH_SaveFRegs
+    0U,	// SEH_SaveLR
+    0U,	// SEH_SaveRegs
+    0U,	// SEH_SaveRegs_Ret
+    0U,	// SEH_SaveSP
+    0U,	// SEH_StackAlloc
     0U,	// SMLALv5
     0U,	// SMULLv5
     0U,	// SPACE
-    8U,	// STRBT_POST
+    0U,	// STOREDUAL
+    128U,	// STRBT_POST
     0U,	// STRBi_preidx
     0U,	// STRBr_preidx
     0U,	// STRH_preidx
-    8U,	// STRT_POST
+    128U,	// STRT_POST
     0U,	// STRi_preidx
     0U,	// STRr_preidx
     0U,	// SUBS_PC_LR
@@ -3967,6 +5551,8 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// SUBSrr
     0U,	// SUBSrsi
     0U,	// SUBSrsr
+    0U,	// SpeculationBarrierISBDSBEndBB
+    0U,	// SpeculationBarrierSBEndBB
     0U,	// TAILJMPd
     0U,	// TAILJMPr
     0U,	// TAILJMPr4
@@ -3975,243 +5561,254 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// TPsoft
     0U,	// UMLALv5
     0U,	// UMULLv5
-    1040U,	// VLD1LNdAsm_16
-    1040U,	// VLD1LNdAsm_32
-    1040U,	// VLD1LNdAsm_8
-    2064U,	// VLD1LNdWB_fixed_Asm_16
-    2064U,	// VLD1LNdWB_fixed_Asm_32
-    2064U,	// VLD1LNdWB_fixed_Asm_8
-    32784U,	// VLD1LNdWB_register_Asm_16
-    32784U,	// VLD1LNdWB_register_Asm_32
-    32784U,	// VLD1LNdWB_register_Asm_8
-    1040U,	// VLD2LNdAsm_16
-    1040U,	// VLD2LNdAsm_32
-    1040U,	// VLD2LNdAsm_8
-    2064U,	// VLD2LNdWB_fixed_Asm_16
-    2064U,	// VLD2LNdWB_fixed_Asm_32
-    2064U,	// VLD2LNdWB_fixed_Asm_8
-    32784U,	// VLD2LNdWB_register_Asm_16
-    32784U,	// VLD2LNdWB_register_Asm_32
-    32784U,	// VLD2LNdWB_register_Asm_8
-    1040U,	// VLD2LNqAsm_16
-    1040U,	// VLD2LNqAsm_32
-    2064U,	// VLD2LNqWB_fixed_Asm_16
-    2064U,	// VLD2LNqWB_fixed_Asm_32
-    32784U,	// VLD2LNqWB_register_Asm_16
-    32784U,	// VLD2LNqWB_register_Asm_32
-    0U,	// VLD3DUPdAsm_16
-    0U,	// VLD3DUPdAsm_32
-    0U,	// VLD3DUPdAsm_8
-    0U,	// VLD3DUPdWB_fixed_Asm_16
-    0U,	// VLD3DUPdWB_fixed_Asm_32
-    0U,	// VLD3DUPdWB_fixed_Asm_8
-    1048U,	// VLD3DUPdWB_register_Asm_16
-    1048U,	// VLD3DUPdWB_register_Asm_32
-    1048U,	// VLD3DUPdWB_register_Asm_8
-    0U,	// VLD3DUPqAsm_16
-    0U,	// VLD3DUPqAsm_32
-    0U,	// VLD3DUPqAsm_8
-    0U,	// VLD3DUPqWB_fixed_Asm_16
-    0U,	// VLD3DUPqWB_fixed_Asm_32
-    0U,	// VLD3DUPqWB_fixed_Asm_8
-    1048U,	// VLD3DUPqWB_register_Asm_16
-    1048U,	// VLD3DUPqWB_register_Asm_32
-    1048U,	// VLD3DUPqWB_register_Asm_8
-    1040U,	// VLD3LNdAsm_16
-    1040U,	// VLD3LNdAsm_32
-    1040U,	// VLD3LNdAsm_8
-    2064U,	// VLD3LNdWB_fixed_Asm_16
-    2064U,	// VLD3LNdWB_fixed_Asm_32
-    2064U,	// VLD3LNdWB_fixed_Asm_8
-    32784U,	// VLD3LNdWB_register_Asm_16
-    32784U,	// VLD3LNdWB_register_Asm_32
-    32784U,	// VLD3LNdWB_register_Asm_8
-    1040U,	// VLD3LNqAsm_16
-    1040U,	// VLD3LNqAsm_32
-    2064U,	// VLD3LNqWB_fixed_Asm_16
-    2064U,	// VLD3LNqWB_fixed_Asm_32
-    32784U,	// VLD3LNqWB_register_Asm_16
-    32784U,	// VLD3LNqWB_register_Asm_32
-    32U,	// VLD3dAsm_16
-    32U,	// VLD3dAsm_32
-    32U,	// VLD3dAsm_8
-    40U,	// VLD3dWB_fixed_Asm_16
-    40U,	// VLD3dWB_fixed_Asm_32
-    40U,	// VLD3dWB_fixed_Asm_8
-    68656U,	// VLD3dWB_register_Asm_16
-    68656U,	// VLD3dWB_register_Asm_32
-    68656U,	// VLD3dWB_register_Asm_8
-    0U,	// VLD3qAsm_16
-    0U,	// VLD3qAsm_32
-    0U,	// VLD3qAsm_8
-    0U,	// VLD3qWB_fixed_Asm_16
-    0U,	// VLD3qWB_fixed_Asm_32
-    0U,	// VLD3qWB_fixed_Asm_8
-    1048U,	// VLD3qWB_register_Asm_16
-    1048U,	// VLD3qWB_register_Asm_32
-    1048U,	// VLD3qWB_register_Asm_8
-    0U,	// VLD4DUPdAsm_16
-    0U,	// VLD4DUPdAsm_32
-    0U,	// VLD4DUPdAsm_8
-    0U,	// VLD4DUPdWB_fixed_Asm_16
-    0U,	// VLD4DUPdWB_fixed_Asm_32
-    0U,	// VLD4DUPdWB_fixed_Asm_8
-    1048U,	// VLD4DUPdWB_register_Asm_16
-    1048U,	// VLD4DUPdWB_register_Asm_32
-    1048U,	// VLD4DUPdWB_register_Asm_8
-    0U,	// VLD4DUPqAsm_16
-    0U,	// VLD4DUPqAsm_32
-    0U,	// VLD4DUPqAsm_8
-    0U,	// VLD4DUPqWB_fixed_Asm_16
-    0U,	// VLD4DUPqWB_fixed_Asm_32
-    0U,	// VLD4DUPqWB_fixed_Asm_8
-    1048U,	// VLD4DUPqWB_register_Asm_16
-    1048U,	// VLD4DUPqWB_register_Asm_32
-    1048U,	// VLD4DUPqWB_register_Asm_8
-    1040U,	// VLD4LNdAsm_16
-    1040U,	// VLD4LNdAsm_32
-    1040U,	// VLD4LNdAsm_8
-    2064U,	// VLD4LNdWB_fixed_Asm_16
-    2064U,	// VLD4LNdWB_fixed_Asm_32
-    2064U,	// VLD4LNdWB_fixed_Asm_8
-    32784U,	// VLD4LNdWB_register_Asm_16
-    32784U,	// VLD4LNdWB_register_Asm_32
-    32784U,	// VLD4LNdWB_register_Asm_8
-    1040U,	// VLD4LNqAsm_16
-    1040U,	// VLD4LNqAsm_32
-    2064U,	// VLD4LNqWB_fixed_Asm_16
-    2064U,	// VLD4LNqWB_fixed_Asm_32
-    32784U,	// VLD4LNqWB_register_Asm_16
-    32784U,	// VLD4LNqWB_register_Asm_32
-    32U,	// VLD4dAsm_16
-    32U,	// VLD4dAsm_32
-    32U,	// VLD4dAsm_8
-    40U,	// VLD4dWB_fixed_Asm_16
-    40U,	// VLD4dWB_fixed_Asm_32
-    40U,	// VLD4dWB_fixed_Asm_8
-    68656U,	// VLD4dWB_register_Asm_16
-    68656U,	// VLD4dWB_register_Asm_32
-    68656U,	// VLD4dWB_register_Asm_8
-    0U,	// VLD4qAsm_16
-    0U,	// VLD4qAsm_32
-    0U,	// VLD4qAsm_8
-    0U,	// VLD4qWB_fixed_Asm_16
-    0U,	// VLD4qWB_fixed_Asm_32
-    0U,	// VLD4qWB_fixed_Asm_8
-    1048U,	// VLD4qWB_register_Asm_16
-    1048U,	// VLD4qWB_register_Asm_32
-    1048U,	// VLD4qWB_register_Asm_8
+    16640U,	// VLD1LNdAsm_16
+    16640U,	// VLD1LNdAsm_32
+    16640U,	// VLD1LNdAsm_8
+    33024U,	// VLD1LNdWB_fixed_Asm_16
+    33024U,	// VLD1LNdWB_fixed_Asm_32
+    33024U,	// VLD1LNdWB_fixed_Asm_8
+    524544U,	// VLD1LNdWB_register_Asm_16
+    524544U,	// VLD1LNdWB_register_Asm_32
+    524544U,	// VLD1LNdWB_register_Asm_8
+    16640U,	// VLD2LNdAsm_16
+    16640U,	// VLD2LNdAsm_32
+    16640U,	// VLD2LNdAsm_8
+    33024U,	// VLD2LNdWB_fixed_Asm_16
+    33024U,	// VLD2LNdWB_fixed_Asm_32
+    33024U,	// VLD2LNdWB_fixed_Asm_8
+    524544U,	// VLD2LNdWB_register_Asm_16
+    524544U,	// VLD2LNdWB_register_Asm_32
+    524544U,	// VLD2LNdWB_register_Asm_8
+    16640U,	// VLD2LNqAsm_16
+    16640U,	// VLD2LNqAsm_32
+    33024U,	// VLD2LNqWB_fixed_Asm_16
+    33024U,	// VLD2LNqWB_fixed_Asm_32
+    524544U,	// VLD2LNqWB_register_Asm_16
+    524544U,	// VLD2LNqWB_register_Asm_32
+    2U,	// VLD3DUPdAsm_16
+    2U,	// VLD3DUPdAsm_32
+    2U,	// VLD3DUPdAsm_8
+    4U,	// VLD3DUPdWB_fixed_Asm_16
+    4U,	// VLD3DUPdWB_fixed_Asm_32
+    4U,	// VLD3DUPdWB_fixed_Asm_8
+    16768U,	// VLD3DUPdWB_register_Asm_16
+    16768U,	// VLD3DUPdWB_register_Asm_32
+    16768U,	// VLD3DUPdWB_register_Asm_8
+    2U,	// VLD3DUPqAsm_16
+    2U,	// VLD3DUPqAsm_32
+    2U,	// VLD3DUPqAsm_8
+    4U,	// VLD3DUPqWB_fixed_Asm_16
+    4U,	// VLD3DUPqWB_fixed_Asm_32
+    4U,	// VLD3DUPqWB_fixed_Asm_8
+    16768U,	// VLD3DUPqWB_register_Asm_16
+    16768U,	// VLD3DUPqWB_register_Asm_32
+    16768U,	// VLD3DUPqWB_register_Asm_8
+    16640U,	// VLD3LNdAsm_16
+    16640U,	// VLD3LNdAsm_32
+    16640U,	// VLD3LNdAsm_8
+    33024U,	// VLD3LNdWB_fixed_Asm_16
+    33024U,	// VLD3LNdWB_fixed_Asm_32
+    33024U,	// VLD3LNdWB_fixed_Asm_8
+    524544U,	// VLD3LNdWB_register_Asm_16
+    524544U,	// VLD3LNdWB_register_Asm_32
+    524544U,	// VLD3LNdWB_register_Asm_8
+    16640U,	// VLD3LNqAsm_16
+    16640U,	// VLD3LNqAsm_32
+    33024U,	// VLD3LNqWB_fixed_Asm_16
+    33024U,	// VLD3LNqWB_fixed_Asm_32
+    524544U,	// VLD3LNqWB_register_Asm_16
+    524544U,	// VLD3LNqWB_register_Asm_32
+    518U,	// VLD3dAsm_16
+    518U,	// VLD3dAsm_32
+    518U,	// VLD3dAsm_8
+    646U,	// VLD3dWB_fixed_Asm_16
+    646U,	// VLD3dWB_fixed_Asm_32
+    646U,	// VLD3dWB_fixed_Asm_8
+    49926U,	// VLD3dWB_register_Asm_16
+    49926U,	// VLD3dWB_register_Asm_32
+    49926U,	// VLD3dWB_register_Asm_8
+    2U,	// VLD3qAsm_16
+    2U,	// VLD3qAsm_32
+    2U,	// VLD3qAsm_8
+    4U,	// VLD3qWB_fixed_Asm_16
+    4U,	// VLD3qWB_fixed_Asm_32
+    4U,	// VLD3qWB_fixed_Asm_8
+    16768U,	// VLD3qWB_register_Asm_16
+    16768U,	// VLD3qWB_register_Asm_32
+    16768U,	// VLD3qWB_register_Asm_8
+    2U,	// VLD4DUPdAsm_16
+    2U,	// VLD4DUPdAsm_32
+    2U,	// VLD4DUPdAsm_8
+    4U,	// VLD4DUPdWB_fixed_Asm_16
+    4U,	// VLD4DUPdWB_fixed_Asm_32
+    4U,	// VLD4DUPdWB_fixed_Asm_8
+    16768U,	// VLD4DUPdWB_register_Asm_16
+    16768U,	// VLD4DUPdWB_register_Asm_32
+    16768U,	// VLD4DUPdWB_register_Asm_8
+    2U,	// VLD4DUPqAsm_16
+    2U,	// VLD4DUPqAsm_32
+    2U,	// VLD4DUPqAsm_8
+    4U,	// VLD4DUPqWB_fixed_Asm_16
+    4U,	// VLD4DUPqWB_fixed_Asm_32
+    4U,	// VLD4DUPqWB_fixed_Asm_8
+    16768U,	// VLD4DUPqWB_register_Asm_16
+    16768U,	// VLD4DUPqWB_register_Asm_32
+    16768U,	// VLD4DUPqWB_register_Asm_8
+    16640U,	// VLD4LNdAsm_16
+    16640U,	// VLD4LNdAsm_32
+    16640U,	// VLD4LNdAsm_8
+    33024U,	// VLD4LNdWB_fixed_Asm_16
+    33024U,	// VLD4LNdWB_fixed_Asm_32
+    33024U,	// VLD4LNdWB_fixed_Asm_8
+    524544U,	// VLD4LNdWB_register_Asm_16
+    524544U,	// VLD4LNdWB_register_Asm_32
+    524544U,	// VLD4LNdWB_register_Asm_8
+    16640U,	// VLD4LNqAsm_16
+    16640U,	// VLD4LNqAsm_32
+    33024U,	// VLD4LNqWB_fixed_Asm_16
+    33024U,	// VLD4LNqWB_fixed_Asm_32
+    524544U,	// VLD4LNqWB_register_Asm_16
+    524544U,	// VLD4LNqWB_register_Asm_32
+    518U,	// VLD4dAsm_16
+    518U,	// VLD4dAsm_32
+    518U,	// VLD4dAsm_8
+    646U,	// VLD4dWB_fixed_Asm_16
+    646U,	// VLD4dWB_fixed_Asm_32
+    646U,	// VLD4dWB_fixed_Asm_8
+    49926U,	// VLD4dWB_register_Asm_16
+    49926U,	// VLD4dWB_register_Asm_32
+    49926U,	// VLD4dWB_register_Asm_8
+    2U,	// VLD4qAsm_16
+    2U,	// VLD4qAsm_32
+    2U,	// VLD4qAsm_8
+    4U,	// VLD4qWB_fixed_Asm_16
+    4U,	// VLD4qWB_fixed_Asm_32
+    4U,	// VLD4qWB_fixed_Asm_8
+    16768U,	// VLD4qWB_register_Asm_16
+    16768U,	// VLD4qWB_register_Asm_32
+    16768U,	// VLD4qWB_register_Asm_8
     0U,	// VMOVD0
     0U,	// VMOVDcc
+    0U,	// VMOVHcc
     0U,	// VMOVQ0
     0U,	// VMOVScc
-    1040U,	// VST1LNdAsm_16
-    1040U,	// VST1LNdAsm_32
-    1040U,	// VST1LNdAsm_8
-    2064U,	// VST1LNdWB_fixed_Asm_16
-    2064U,	// VST1LNdWB_fixed_Asm_32
-    2064U,	// VST1LNdWB_fixed_Asm_8
-    32784U,	// VST1LNdWB_register_Asm_16
-    32784U,	// VST1LNdWB_register_Asm_32
-    32784U,	// VST1LNdWB_register_Asm_8
-    1040U,	// VST2LNdAsm_16
-    1040U,	// VST2LNdAsm_32
-    1040U,	// VST2LNdAsm_8
-    2064U,	// VST2LNdWB_fixed_Asm_16
-    2064U,	// VST2LNdWB_fixed_Asm_32
-    2064U,	// VST2LNdWB_fixed_Asm_8
-    32784U,	// VST2LNdWB_register_Asm_16
-    32784U,	// VST2LNdWB_register_Asm_32
-    32784U,	// VST2LNdWB_register_Asm_8
-    1040U,	// VST2LNqAsm_16
-    1040U,	// VST2LNqAsm_32
-    2064U,	// VST2LNqWB_fixed_Asm_16
-    2064U,	// VST2LNqWB_fixed_Asm_32
-    32784U,	// VST2LNqWB_register_Asm_16
-    32784U,	// VST2LNqWB_register_Asm_32
-    1040U,	// VST3LNdAsm_16
-    1040U,	// VST3LNdAsm_32
-    1040U,	// VST3LNdAsm_8
-    2064U,	// VST3LNdWB_fixed_Asm_16
-    2064U,	// VST3LNdWB_fixed_Asm_32
-    2064U,	// VST3LNdWB_fixed_Asm_8
-    32784U,	// VST3LNdWB_register_Asm_16
-    32784U,	// VST3LNdWB_register_Asm_32
-    32784U,	// VST3LNdWB_register_Asm_8
-    1040U,	// VST3LNqAsm_16
-    1040U,	// VST3LNqAsm_32
-    2064U,	// VST3LNqWB_fixed_Asm_16
-    2064U,	// VST3LNqWB_fixed_Asm_32
-    32784U,	// VST3LNqWB_register_Asm_16
-    32784U,	// VST3LNqWB_register_Asm_32
-    32U,	// VST3dAsm_16
-    32U,	// VST3dAsm_32
-    32U,	// VST3dAsm_8
-    40U,	// VST3dWB_fixed_Asm_16
-    40U,	// VST3dWB_fixed_Asm_32
-    40U,	// VST3dWB_fixed_Asm_8
-    68656U,	// VST3dWB_register_Asm_16
-    68656U,	// VST3dWB_register_Asm_32
-    68656U,	// VST3dWB_register_Asm_8
-    0U,	// VST3qAsm_16
-    0U,	// VST3qAsm_32
-    0U,	// VST3qAsm_8
-    0U,	// VST3qWB_fixed_Asm_16
-    0U,	// VST3qWB_fixed_Asm_32
-    0U,	// VST3qWB_fixed_Asm_8
-    1048U,	// VST3qWB_register_Asm_16
-    1048U,	// VST3qWB_register_Asm_32
-    1048U,	// VST3qWB_register_Asm_8
-    1040U,	// VST4LNdAsm_16
-    1040U,	// VST4LNdAsm_32
-    1040U,	// VST4LNdAsm_8
-    2064U,	// VST4LNdWB_fixed_Asm_16
-    2064U,	// VST4LNdWB_fixed_Asm_32
-    2064U,	// VST4LNdWB_fixed_Asm_8
-    32784U,	// VST4LNdWB_register_Asm_16
-    32784U,	// VST4LNdWB_register_Asm_32
-    32784U,	// VST4LNdWB_register_Asm_8
-    1040U,	// VST4LNqAsm_16
-    1040U,	// VST4LNqAsm_32
-    2064U,	// VST4LNqWB_fixed_Asm_16
-    2064U,	// VST4LNqWB_fixed_Asm_32
-    32784U,	// VST4LNqWB_register_Asm_16
-    32784U,	// VST4LNqWB_register_Asm_32
-    32U,	// VST4dAsm_16
-    32U,	// VST4dAsm_32
-    32U,	// VST4dAsm_8
-    40U,	// VST4dWB_fixed_Asm_16
-    40U,	// VST4dWB_fixed_Asm_32
-    40U,	// VST4dWB_fixed_Asm_8
-    68656U,	// VST4dWB_register_Asm_16
-    68656U,	// VST4dWB_register_Asm_32
-    68656U,	// VST4dWB_register_Asm_8
-    0U,	// VST4qAsm_16
-    0U,	// VST4qAsm_32
-    0U,	// VST4qAsm_8
-    0U,	// VST4qWB_fixed_Asm_16
-    0U,	// VST4qWB_fixed_Asm_32
-    0U,	// VST4qWB_fixed_Asm_8
-    1048U,	// VST4qWB_register_Asm_16
-    1048U,	// VST4qWB_register_Asm_32
-    1048U,	// VST4qWB_register_Asm_8
+    16640U,	// VST1LNdAsm_16
+    16640U,	// VST1LNdAsm_32
+    16640U,	// VST1LNdAsm_8
+    33024U,	// VST1LNdWB_fixed_Asm_16
+    33024U,	// VST1LNdWB_fixed_Asm_32
+    33024U,	// VST1LNdWB_fixed_Asm_8
+    524544U,	// VST1LNdWB_register_Asm_16
+    524544U,	// VST1LNdWB_register_Asm_32
+    524544U,	// VST1LNdWB_register_Asm_8
+    16640U,	// VST2LNdAsm_16
+    16640U,	// VST2LNdAsm_32
+    16640U,	// VST2LNdAsm_8
+    33024U,	// VST2LNdWB_fixed_Asm_16
+    33024U,	// VST2LNdWB_fixed_Asm_32
+    33024U,	// VST2LNdWB_fixed_Asm_8
+    524544U,	// VST2LNdWB_register_Asm_16
+    524544U,	// VST2LNdWB_register_Asm_32
+    524544U,	// VST2LNdWB_register_Asm_8
+    16640U,	// VST2LNqAsm_16
+    16640U,	// VST2LNqAsm_32
+    33024U,	// VST2LNqWB_fixed_Asm_16
+    33024U,	// VST2LNqWB_fixed_Asm_32
+    524544U,	// VST2LNqWB_register_Asm_16
+    524544U,	// VST2LNqWB_register_Asm_32
+    16640U,	// VST3LNdAsm_16
+    16640U,	// VST3LNdAsm_32
+    16640U,	// VST3LNdAsm_8
+    33024U,	// VST3LNdWB_fixed_Asm_16
+    33024U,	// VST3LNdWB_fixed_Asm_32
+    33024U,	// VST3LNdWB_fixed_Asm_8
+    524544U,	// VST3LNdWB_register_Asm_16
+    524544U,	// VST3LNdWB_register_Asm_32
+    524544U,	// VST3LNdWB_register_Asm_8
+    16640U,	// VST3LNqAsm_16
+    16640U,	// VST3LNqAsm_32
+    33024U,	// VST3LNqWB_fixed_Asm_16
+    33024U,	// VST3LNqWB_fixed_Asm_32
+    524544U,	// VST3LNqWB_register_Asm_16
+    524544U,	// VST3LNqWB_register_Asm_32
+    518U,	// VST3dAsm_16
+    518U,	// VST3dAsm_32
+    518U,	// VST3dAsm_8
+    646U,	// VST3dWB_fixed_Asm_16
+    646U,	// VST3dWB_fixed_Asm_32
+    646U,	// VST3dWB_fixed_Asm_8
+    49926U,	// VST3dWB_register_Asm_16
+    49926U,	// VST3dWB_register_Asm_32
+    49926U,	// VST3dWB_register_Asm_8
+    2U,	// VST3qAsm_16
+    2U,	// VST3qAsm_32
+    2U,	// VST3qAsm_8
+    4U,	// VST3qWB_fixed_Asm_16
+    4U,	// VST3qWB_fixed_Asm_32
+    4U,	// VST3qWB_fixed_Asm_8
+    16768U,	// VST3qWB_register_Asm_16
+    16768U,	// VST3qWB_register_Asm_32
+    16768U,	// VST3qWB_register_Asm_8
+    16640U,	// VST4LNdAsm_16
+    16640U,	// VST4LNdAsm_32
+    16640U,	// VST4LNdAsm_8
+    33024U,	// VST4LNdWB_fixed_Asm_16
+    33024U,	// VST4LNdWB_fixed_Asm_32
+    33024U,	// VST4LNdWB_fixed_Asm_8
+    524544U,	// VST4LNdWB_register_Asm_16
+    524544U,	// VST4LNdWB_register_Asm_32
+    524544U,	// VST4LNdWB_register_Asm_8
+    16640U,	// VST4LNqAsm_16
+    16640U,	// VST4LNqAsm_32
+    33024U,	// VST4LNqWB_fixed_Asm_16
+    33024U,	// VST4LNqWB_fixed_Asm_32
+    524544U,	// VST4LNqWB_register_Asm_16
+    524544U,	// VST4LNqWB_register_Asm_32
+    518U,	// VST4dAsm_16
+    518U,	// VST4dAsm_32
+    518U,	// VST4dAsm_8
+    646U,	// VST4dWB_fixed_Asm_16
+    646U,	// VST4dWB_fixed_Asm_32
+    646U,	// VST4dWB_fixed_Asm_8
+    49926U,	// VST4dWB_register_Asm_16
+    49926U,	// VST4dWB_register_Asm_32
+    49926U,	// VST4dWB_register_Asm_8
+    2U,	// VST4qAsm_16
+    2U,	// VST4qAsm_32
+    2U,	// VST4qAsm_8
+    4U,	// VST4qWB_fixed_Asm_16
+    4U,	// VST4qWB_fixed_Asm_32
+    4U,	// VST4qWB_fixed_Asm_8
+    16768U,	// VST4qWB_register_Asm_16
+    16768U,	// VST4qWB_register_Asm_32
+    16768U,	// VST4qWB_register_Asm_8
     0U,	// WIN__CHKSTK
     0U,	// WIN__DBZCHK
     0U,	// t2ABS
     0U,	// t2ADDSri
     0U,	// t2ADDSrr
     0U,	// t2ADDSrs
+    0U,	// t2BF_LabelPseudo
     0U,	// t2BR_JT
+    0U,	// t2CALL_BTI
+    0U,	// t2DoLoopStart
+    0U,	// t2DoLoopStartTP
     0U,	// t2LDMIA_RET
-    1024U,	// t2LDRBpcrel
-    1024U,	// t2LDRConstPool
-    1024U,	// t2LDRHpcrel
-    1024U,	// t2LDRSBpcrel
-    1024U,	// t2LDRSHpcrel
+    16384U,	// t2LDRBpcrel
+    16384U,	// t2LDRConstPool
+    16384U,	// t2LDRHpcrel
+    0U,	// t2LDRLIT_ga_pcrel
+    16384U,	// t2LDRSBpcrel
+    16384U,	// t2LDRSHpcrel
+    896U,	// t2LDR_POST_imm
+    0U,	// t2LDR_PRE_imm
     0U,	// t2LDRpci_pic
-    1024U,	// t2LDRpcrel
+    16384U,	// t2LDRpcrel
     0U,	// t2LEApcrel
     0U,	// t2LEApcrelJT
+    0U,	// t2LoopDec
+    0U,	// t2LoopEnd
+    0U,	// t2LoopEndDec
     0U,	// t2MOVCCasr
     0U,	// t2MOVCCi
     0U,	// t2MOVCCi16
@@ -4220,25 +5817,33 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2MOVCClsr
     0U,	// t2MOVCCr
     0U,	// t2MOVCCror
-    56U,	// t2MOVSsi
-    64U,	// t2MOVSsr
+    1024U,	// t2MOVSsi
+    1152U,	// t2MOVSsr
     0U,	// t2MOVTi16_ga_pcrel
     0U,	// t2MOV_ga_pcrel
     0U,	// t2MOVi16_ga_pcrel
     0U,	// t2MOVi32imm
-    56U,	// t2MOVsi
-    64U,	// t2MOVsr
+    1024U,	// t2MOVsi
+    1152U,	// t2MOVsr
     0U,	// t2MVNCCi
     0U,	// t2RSBSri
     0U,	// t2RSBSrs
     0U,	// t2STRB_preidx
     0U,	// t2STRH_preidx
+    896U,	// t2STR_POST_imm
+    0U,	// t2STR_PRE_imm
     0U,	// t2STR_preidx
     0U,	// t2SUBSri
     0U,	// t2SUBSrr
     0U,	// t2SUBSrs
+    0U,	// t2SpeculationBarrierISBDSBEndBB
+    0U,	// t2SpeculationBarrierSBEndBB
     0U,	// t2TBB_JT
     0U,	// t2TBH_JT
+    0U,	// t2WhileLoopSetup
+    0U,	// t2WhileLoopStart
+    0U,	// t2WhileLoopStartLR
+    0U,	// t2WhileLoopStartTP
     0U,	// tADCS
     0U,	// tADDSi3
     0U,	// tADDSi8
@@ -4246,22 +5851,31 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// tADDframe
     0U,	// tADJCALLSTACKDOWN
     0U,	// tADJCALLSTACKUP
+    0U,	// tBLXNS_CALL
+    0U,	// tBLXr_noip
+    0U,	// tBL_PUSHLR
     0U,	// tBRIND
     0U,	// tBR_JTr
+    0U,	// tBXNS_RET
     0U,	// tBX_CALL
     0U,	// tBX_RET
     0U,	// tBX_RET_vararg
     0U,	// tBfar
+    0U,	// tCMP_SWAP_16
+    0U,	// tCMP_SWAP_32
+    0U,	// tCMP_SWAP_8
     0U,	// tLDMIA_UPD
-    1024U,	// tLDRConstPool
+    16384U,	// tLDRConstPool
     0U,	// tLDRLIT_ga_abs
     0U,	// tLDRLIT_ga_pcrel
     0U,	// tLDR_postidx
     0U,	// tLDRpci_pic
     0U,	// tLEApcrel
     0U,	// tLEApcrelJT
+    0U,	// tLSLSri
     0U,	// tMOVCCr_pseudo
     0U,	// tPOP_RET
+    0U,	// tRSBS
     0U,	// tSBCS
     0U,	// tSUBSi3
     0U,	// tSUBSi8
@@ -4272,188 +5886,1074 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// tTBB_JT
     0U,	// tTBH_JT
     0U,	// tTPsoft
-    98304U,	// ADCri
+    1048576U,	// ADCri
     0U,	// ADCrr
-    131072U,	// ADCrsi
+    1572864U,	// ADCrsi
     0U,	// ADCrsr
-    98304U,	// ADDri
+    1048576U,	// ADDri
     0U,	// ADDrr
-    131072U,	// ADDrsi
+    1572864U,	// ADDrsi
     0U,	// ADDrsr
-    72U,	// ADR
-    0U,	// AESD
-    0U,	// AESE
-    0U,	// AESIMC
-    0U,	// AESMC
-    98304U,	// ANDri
+    1280U,	// ADR
+    2U,	// AESD
+    2U,	// AESE
+    2U,	// AESIMC
+    2U,	// AESMC
+    1048576U,	// ANDri
     0U,	// ANDrr
-    131072U,	// ANDrsi
+    1572864U,	// ANDrsi
     0U,	// ANDrsr
-    80U,	// BFC
-    163928U,	// BFI
-    98304U,	// BICri
+    2163072U,	// BF16VDOTI_VDOTD
+    2163072U,	// BF16VDOTI_VDOTQ
+    16768U,	// BF16VDOTS_VDOTD
+    16768U,	// BF16VDOTS_VDOTQ
+    2U,	// BF16_VCVT
+    2U,	// BF16_VCVTB
+    2U,	// BF16_VCVTT
+    1408U,	// BFC
+    2622976U,	// BFI
+    1048576U,	// BICri
     0U,	// BICrr
-    131072U,	// BICrsi
+    1572864U,	// BICrsi
     0U,	// BICrsr
     0U,	// BKPT
     0U,	// BL
     0U,	// BLX
-    0U,	// BLX_pred
+    2U,	// BLX_pred
     0U,	// BLXi
-    0U,	// BL_pred
+    2U,	// BL_pred
     0U,	// BX
-    0U,	// BXJ
+    2U,	// BXJ
     0U,	// BX_RET
-    0U,	// BX_pred
-    0U,	// Bcc
-    4145U,	// CDP
+    2U,	// BX_pred
+    2U,	// Bcc
+    2U,	// CDE_CX1
+    16776U,	// CDE_CX1A
+    0U,	// CDE_CX1D
+    522U,	// CDE_CX1DA
+    16768U,	// CDE_CX2
+    524680U,	// CDE_CX2A
+    524U,	// CDE_CX2D
+    2179850U,	// CDE_CX2DA
+    524672U,	// CDE_CX3
+    34079112U,	// CDE_CX3A
+    2179852U,	// CDE_CX3D
+    70337290U,	// CDE_CX3DA
+    2U,	// CDE_VCX1A_fpdp
+    2U,	// CDE_VCX1A_fpsp
+    16776U,	// CDE_VCX1A_vec
+    2U,	// CDE_VCX1_fpdp
+    2U,	// CDE_VCX1_fpsp
+    17928U,	// CDE_VCX1_vec
+    18048U,	// CDE_VCX2A_fpdp
+    18048U,	// CDE_VCX2A_fpsp
+    524680U,	// CDE_VCX2A_vec
+    16768U,	// CDE_VCX2_fpdp
+    16768U,	// CDE_VCX2_fpsp
+    3671560U,	// CDE_VCX2_vec
+    4195968U,	// CDE_VCX3A_fpdp
+    4195968U,	// CDE_VCX3A_fpsp
+    34079112U,	// CDE_VCX3A_vec
+    524672U,	// CDE_VCX3_fpdp
+    524672U,	// CDE_VCX3_fpsp
+    37225992U,	// CDE_VCX3_vec
+    99086U,	// CDP
     0U,	// CDP2
     0U,	// CLREX
-    1024U,	// CLZ
-    96U,	// CMNri
-    1024U,	// CMNzrr
-    104U,	// CMNzrsi
-    64U,	// CMNzrsr
-    96U,	// CMPri
-    1024U,	// CMPrr
-    104U,	// CMPrsi
-    64U,	// CMPrsr
+    16384U,	// CLZ
+    1792U,	// CMNri
+    16384U,	// CMNzrr
+    1920U,	// CMNzrsi
+    1152U,	// CMNzrsr
+    1792U,	// CMPri
+    16384U,	// CMPrr
+    1920U,	// CMPrsi
+    1152U,	// CMPrsr
     0U,	// CPS1p
-    0U,	// CPS2p
-    1112U,	// CPS3p
-    1112U,	// CRC32B
-    1112U,	// CRC32CB
-    1112U,	// CRC32CH
-    1112U,	// CRC32CW
-    1112U,	// CRC32H
-    1112U,	// CRC32W
-    0U,	// DBG
+    2U,	// CPS2p
+    17920U,	// CPS3p
+    17920U,	// CRC32B
+    17920U,	// CRC32CB
+    17920U,	// CRC32CH
+    17920U,	// CRC32CW
+    17920U,	// CRC32H
+    17920U,	// CRC32W
+    2U,	// DBG
     0U,	// DMB
     0U,	// DSB
-    98304U,	// EORri
+    1048576U,	// EORri
     0U,	// EORrr
-    131072U,	// EORrsi
+    1572864U,	// EORrsi
     0U,	// EORrsr
     0U,	// ERET
-    1U,	// FCONSTD
-    1U,	// FCONSTH
-    1U,	// FCONSTS
-    33U,	// FLDMXDB_UPD
-    1136U,	// FLDMXIA
-    33U,	// FLDMXIA_UPD
+    16U,	// FCONSTD
+    2048U,	// FCONSTH
+    2048U,	// FCONSTS
+    530U,	// FLDMXDB_UPD
+    18560U,	// FLDMXIA
+    530U,	// FLDMXIA_UPD
     0U,	// FMSTAT
-    33U,	// FSTMXDB_UPD
-    1136U,	// FSTMXIA
-    33U,	// FSTMXIA_UPD
-    0U,	// HINT
+    530U,	// FSTMXDB_UPD
+    18560U,	// FSTMXIA
+    530U,	// FSTMXIA_UPD
+    2U,	// HINT
     0U,	// HLT
     0U,	// HVC
     0U,	// ISB
-    8U,	// LDA
-    8U,	// LDAB
-    8U,	// LDAEX
-    8U,	// LDAEXB
+    128U,	// LDA
+    128U,	// LDAB
+    128U,	// LDAEX
+    128U,	// LDAEXB
     0U,	// LDAEXD
-    8U,	// LDAEXH
-    8U,	// LDAH
+    128U,	// LDAEXH
+    128U,	// LDAH
     0U,	// LDC2L_OFFSET
-    1U,	// LDC2L_OPTION
-    2U,	// LDC2L_POST
+    2304U,	// LDC2L_OPTION
+    2432U,	// LDC2L_POST
     0U,	// LDC2L_PRE
     0U,	// LDC2_OFFSET
-    1U,	// LDC2_OPTION
-    2U,	// LDC2_POST
+    2304U,	// LDC2_OPTION
+    2432U,	// LDC2_POST
     0U,	// LDC2_PRE
-    122U,	// LDCL_OFFSET
-    196738U,	// LDCL_OPTION
-    229506U,	// LDCL_POST
-    138U,	// LDCL_PRE
-    122U,	// LDC_OFFSET
-    196738U,	// LDC_OPTION
-    229506U,	// LDC_POST
-    138U,	// LDC_PRE
-    1136U,	// LDMDA
-    33U,	// LDMDA_UPD
-    1136U,	// LDMDB
-    33U,	// LDMDB_UPD
-    1136U,	// LDMIA
-    33U,	// LDMIA_UPD
-    1136U,	// LDMIB
-    33U,	// LDMIB_UPD
-    262272U,	// LDRBT_POST_IMM
-    262272U,	// LDRBT_POST_REG
-    262272U,	// LDRB_POST_IMM
-    262272U,	// LDRB_POST_REG
-    144U,	// LDRB_PRE_IMM
-    152U,	// LDRB_PRE_REG
-    160U,	// LDRBi12
-    168U,	// LDRBrs
-    294912U,	// LDRD
-    2424832U,	// LDRD_POST
-    360448U,	// LDRD_PRE
-    8U,	// LDREX
-    8U,	// LDREXB
+    2580U,	// LDCL_OFFSET
+    4721300U,	// LDCL_OPTION
+    5245588U,	// LDCL_POST
+    22U,	// LDCL_PRE
+    2580U,	// LDC_OFFSET
+    4721300U,	// LDC_OPTION
+    5245588U,	// LDC_POST
+    22U,	// LDC_PRE
+    18560U,	// LDMDA
+    530U,	// LDMDA_UPD
+    18560U,	// LDMDB
+    530U,	// LDMDB_UPD
+    18560U,	// LDMIA
+    530U,	// LDMIA_UPD
+    18560U,	// LDMIB
+    530U,	// LDMIB_UPD
+    5769856U,	// LDRBT_POST_IMM
+    5769856U,	// LDRBT_POST_REG
+    5769856U,	// LDRB_POST_IMM
+    5769856U,	// LDRB_POST_REG
+    2816U,	// LDRB_PRE_IMM
+    2944U,	// LDRB_PRE_REG
+    3072U,	// LDRBi12
+    3200U,	// LDRBrs
+    6291456U,	// LDRD
+    40370176U,	// LDRD_POST
+    7340032U,	// LDRD_PRE
+    128U,	// LDREX
+    128U,	// LDREXB
     0U,	// LDREXD
-    8U,	// LDREXH
-    176U,	// LDRH
-    393344U,	// LDRHTi
-    426112U,	// LDRHTr
-    458880U,	// LDRH_POST
-    184U,	// LDRH_PRE
-    176U,	// LDRSB
-    393344U,	// LDRSBTi
-    426112U,	// LDRSBTr
-    458880U,	// LDRSB_POST
-    184U,	// LDRSB_PRE
-    176U,	// LDRSH
-    393344U,	// LDRSHTi
-    426112U,	// LDRSHTr
-    458880U,	// LDRSH_POST
-    184U,	// LDRSH_PRE
-    262272U,	// LDRT_POST_IMM
-    262272U,	// LDRT_POST_REG
-    262272U,	// LDR_POST_IMM
-    262272U,	// LDR_POST_REG
-    144U,	// LDR_PRE_IMM
-    152U,	// LDR_PRE_REG
-    160U,	// LDRcp
-    160U,	// LDRi12
-    168U,	// LDRrs
-    4690993U,	// MCR
-    192U,	// MCR2
-    6788145U,	// MCRR
-    524312U,	// MCRR2
-    35651584U,	// MLA
-    35651584U,	// MLS
+    128U,	// LDREXH
+    3328U,	// LDRH
+    7867008U,	// LDRHTi
+    8391296U,	// LDRHTr
+    8915584U,	// LDRH_POST
+    3456U,	// LDRH_PRE
+    3328U,	// LDRSB
+    7867008U,	// LDRSBTi
+    8391296U,	// LDRSBTr
+    8915584U,	// LDRSB_POST
+    3456U,	// LDRSB_PRE
+    3328U,	// LDRSH
+    7867008U,	// LDRSHTi
+    8391296U,	// LDRSHTr
+    8915584U,	// LDRSH_POST
+    3456U,	// LDRSH_PRE
+    5769856U,	// LDRT_POST_IMM
+    5769856U,	// LDRT_POST_REG
+    5769856U,	// LDR_POST_IMM
+    5769856U,	// LDR_POST_REG
+    2816U,	// LDR_PRE_IMM
+    2944U,	// LDR_PRE_REG
+    3072U,	// LDRcp
+    3072U,	// LDRi12
+    3200U,	// LDRrs
+    103924494U,	// MCR
+    3584U,	// MCR2
+    137478926U,	// MCRR
+    9437568U,	// MCRR2
+    33554432U,	// MLA
+    33554432U,	// MLS
     0U,	// MOVPCLR
-    1112U,	// MOVTi16
-    96U,	// MOVi
-    1024U,	// MOVi16
-    1024U,	// MOVr
-    1024U,	// MOVr_TC
-    104U,	// MOVsi
-    64U,	// MOVsr
-    0U,	// MRC
+    17920U,	// MOVTi16
+    1792U,	// MOVi
+    16384U,	// MOVi16
+    16384U,	// MOVr
+    16384U,	// MOVr_TC
+    1920U,	// MOVsi
+    1152U,	// MOVsr
+    131864U,	// MRC
     0U,	// MRC2
     0U,	// MRRC
     0U,	// MRRC2
-    2U,	// MRS
-    200U,	// MRSbanked
-    2U,	// MRSsys
-    33U,	// MSR
+    26U,	// MRS
+    3712U,	// MRSbanked
+    28U,	// MRSsys
+    526U,	// MSR
     0U,	// MSRbanked
-    3U,	// MSRi
+    30U,	// MSRi
     0U,	// MUL
-    96U,	// MVNi
-    1024U,	// MVNr
-    104U,	// MVNsi
-    64U,	// MVNsr
-    98304U,	// ORRri
+    524288U,	// MVE_ASRLi
+    524288U,	// MVE_ASRLr
+    2U,	// MVE_DLSTP_16
+    2U,	// MVE_DLSTP_32
+    2U,	// MVE_DLSTP_64
+    2U,	// MVE_DLSTP_8
+    0U,	// MVE_LCTP
+    0U,	// MVE_LETP
+    524288U,	// MVE_LSLLi
+    524288U,	// MVE_LSLLr
+    524288U,	// MVE_LSRL
+    17920U,	// MVE_SQRSHR
+    9961472U,	// MVE_SQRSHRL
+    17920U,	// MVE_SQSHL
+    524288U,	// MVE_SQSHLL
+    17920U,	// MVE_SRSHR
+    524288U,	// MVE_SRSHRL
+    17920U,	// MVE_UQRSHL
+    9961472U,	// MVE_UQRSHLL
+    17920U,	// MVE_UQSHL
+    524288U,	// MVE_UQSHLL
+    17920U,	// MVE_URSHR
+    524288U,	// MVE_URSHRL
+    3671552U,	// MVE_VABAVs16
+    3671552U,	// MVE_VABAVs32
+    3671552U,	// MVE_VABAVs8
+    3671552U,	// MVE_VABAVu16
+    3671552U,	// MVE_VABAVu32
+    3671552U,	// MVE_VABAVu8
+    0U,	// MVE_VABDf16
+    0U,	// MVE_VABDf32
+    0U,	// MVE_VABDs16
+    0U,	// MVE_VABDs32
+    0U,	// MVE_VABDs8
+    0U,	// MVE_VABDu16
+    0U,	// MVE_VABDu32
+    0U,	// MVE_VABDu8
+    16384U,	// MVE_VABSf16
+    16384U,	// MVE_VABSf32
+    16384U,	// MVE_VABSs16
+    16384U,	// MVE_VABSs32
+    16384U,	// MVE_VABSs8
+    3671552U,	// MVE_VADC
+    3671552U,	// MVE_VADCI
+    524288U,	// MVE_VADDLVs32acc
+    0U,	// MVE_VADDLVs32no_acc
+    524288U,	// MVE_VADDLVu32acc
+    0U,	// MVE_VADDLVu32no_acc
+    17920U,	// MVE_VADDVs16acc
+    16384U,	// MVE_VADDVs16no_acc
+    17920U,	// MVE_VADDVs32acc
+    16384U,	// MVE_VADDVs32no_acc
+    17920U,	// MVE_VADDVs8acc
+    16384U,	// MVE_VADDVs8no_acc
+    17920U,	// MVE_VADDVu16acc
+    16384U,	// MVE_VADDVu16no_acc
+    17920U,	// MVE_VADDVu32acc
+    16384U,	// MVE_VADDVu32no_acc
+    17920U,	// MVE_VADDVu8acc
+    16384U,	// MVE_VADDVu8no_acc
+    0U,	// MVE_VADD_qr_f16
+    0U,	// MVE_VADD_qr_f32
+    0U,	// MVE_VADD_qr_i16
+    0U,	// MVE_VADD_qr_i32
+    0U,	// MVE_VADD_qr_i8
+    0U,	// MVE_VADDf16
+    0U,	// MVE_VADDf32
+    0U,	// MVE_VADDi16
+    0U,	// MVE_VADDi32
+    0U,	// MVE_VADDi8
+    0U,	// MVE_VAND
+    0U,	// MVE_VBIC
+    3840U,	// MVE_VBICimmi16
+    3840U,	// MVE_VBICimmi32
+    0U,	// MVE_VBRSR16
+    0U,	// MVE_VBRSR32
+    0U,	// MVE_VBRSR8
+    33554432U,	// MVE_VCADDf16
+    33554432U,	// MVE_VCADDf32
+    33554432U,	// MVE_VCADDi16
+    33554432U,	// MVE_VCADDi32
+    33554432U,	// MVE_VCADDi8
+    16384U,	// MVE_VCLSs16
+    16384U,	// MVE_VCLSs32
+    16384U,	// MVE_VCLSs8
+    16384U,	// MVE_VCLZs16
+    16384U,	// MVE_VCLZs32
+    16384U,	// MVE_VCLZs8
+    37225984U,	// MVE_VCMLAf16
+    37225984U,	// MVE_VCMLAf32
+    0U,	// MVE_VCMPf16
+    0U,	// MVE_VCMPf16r
+    0U,	// MVE_VCMPf32
+    0U,	// MVE_VCMPf32r
+    0U,	// MVE_VCMPi16
+    0U,	// MVE_VCMPi16r
+    0U,	// MVE_VCMPi32
+    0U,	// MVE_VCMPi32r
+    0U,	// MVE_VCMPi8
+    0U,	// MVE_VCMPi8r
+    0U,	// MVE_VCMPs16
+    0U,	// MVE_VCMPs16r
+    0U,	// MVE_VCMPs32
+    0U,	// MVE_VCMPs32r
+    0U,	// MVE_VCMPs8
+    0U,	// MVE_VCMPs8r
+    0U,	// MVE_VCMPu16
+    0U,	// MVE_VCMPu16r
+    0U,	// MVE_VCMPu32
+    0U,	// MVE_VCMPu32r
+    0U,	// MVE_VCMPu8
+    0U,	// MVE_VCMPu8r
+    33554432U,	// MVE_VCMULf16
+    33554432U,	// MVE_VCMULf32
+    2U,	// MVE_VCTP16
+    2U,	// MVE_VCTP32
+    2U,	// MVE_VCTP64
+    2U,	// MVE_VCTP8
+    2U,	// MVE_VCVTf16f32bh
+    2U,	// MVE_VCVTf16f32th
+    536U,	// MVE_VCVTf16s16_fix
+    0U,	// MVE_VCVTf16s16n
+    536U,	// MVE_VCVTf16u16_fix
+    0U,	// MVE_VCVTf16u16n
+    0U,	// MVE_VCVTf32f16bh
+    0U,	// MVE_VCVTf32f16th
+    536U,	// MVE_VCVTf32s32_fix
+    0U,	// MVE_VCVTf32s32n
+    536U,	// MVE_VCVTf32u32_fix
+    0U,	// MVE_VCVTf32u32n
+    536U,	// MVE_VCVTs16f16_fix
+    0U,	// MVE_VCVTs16f16a
+    0U,	// MVE_VCVTs16f16m
+    0U,	// MVE_VCVTs16f16n
+    0U,	// MVE_VCVTs16f16p
+    0U,	// MVE_VCVTs16f16z
+    536U,	// MVE_VCVTs32f32_fix
+    0U,	// MVE_VCVTs32f32a
+    0U,	// MVE_VCVTs32f32m
+    0U,	// MVE_VCVTs32f32n
+    0U,	// MVE_VCVTs32f32p
+    0U,	// MVE_VCVTs32f32z
+    536U,	// MVE_VCVTu16f16_fix
+    0U,	// MVE_VCVTu16f16a
+    0U,	// MVE_VCVTu16f16m
+    0U,	// MVE_VCVTu16f16n
+    0U,	// MVE_VCVTu16f16p
+    0U,	// MVE_VCVTu16f16z
+    536U,	// MVE_VCVTu32f32_fix
+    0U,	// MVE_VCVTu32f32a
+    0U,	// MVE_VCVTu32f32m
+    0U,	// MVE_VCVTu32f32n
+    0U,	// MVE_VCVTu32f32p
+    0U,	// MVE_VCVTu32f32z
+    3670016U,	// MVE_VDDUPu16
+    3670016U,	// MVE_VDDUPu32
+    3670016U,	// MVE_VDDUPu8
+    16384U,	// MVE_VDUP16
+    16384U,	// MVE_VDUP32
+    16384U,	// MVE_VDUP8
+    37224448U,	// MVE_VDWDUPu16
+    37224448U,	// MVE_VDWDUPu32
+    37224448U,	// MVE_VDWDUPu8
+    0U,	// MVE_VEOR
+    3671552U,	// MVE_VFMA_qr_Sf16
+    3671552U,	// MVE_VFMA_qr_Sf32
+    3671552U,	// MVE_VFMA_qr_f16
+    3671552U,	// MVE_VFMA_qr_f32
+    3671552U,	// MVE_VFMAf16
+    3671552U,	// MVE_VFMAf32
+    3671552U,	// MVE_VFMSf16
+    3671552U,	// MVE_VFMSf32
+    0U,	// MVE_VHADD_qr_s16
+    0U,	// MVE_VHADD_qr_s32
+    0U,	// MVE_VHADD_qr_s8
+    0U,	// MVE_VHADD_qr_u16
+    0U,	// MVE_VHADD_qr_u32
+    0U,	// MVE_VHADD_qr_u8
+    0U,	// MVE_VHADDs16
+    0U,	// MVE_VHADDs32
+    0U,	// MVE_VHADDs8
+    0U,	// MVE_VHADDu16
+    0U,	// MVE_VHADDu32
+    0U,	// MVE_VHADDu8
+    33554432U,	// MVE_VHCADDs16
+    33554432U,	// MVE_VHCADDs32
+    33554432U,	// MVE_VHCADDs8
+    0U,	// MVE_VHSUB_qr_s16
+    0U,	// MVE_VHSUB_qr_s32
+    0U,	// MVE_VHSUB_qr_s8
+    0U,	// MVE_VHSUB_qr_u16
+    0U,	// MVE_VHSUB_qr_u32
+    0U,	// MVE_VHSUB_qr_u8
+    0U,	// MVE_VHSUBs16
+    0U,	// MVE_VHSUBs32
+    0U,	// MVE_VHSUBs8
+    0U,	// MVE_VHSUBu16
+    0U,	// MVE_VHSUBu32
+    0U,	// MVE_VHSUBu8
+    3670016U,	// MVE_VIDUPu16
+    3670016U,	// MVE_VIDUPu32
+    3670016U,	// MVE_VIDUPu8
+    37224448U,	// MVE_VIWDUPu16
+    37224448U,	// MVE_VIWDUPu32
+    37224448U,	// MVE_VIWDUPu8
+    0U,	// MVE_VLD20_16
+    0U,	// MVE_VLD20_16_wb
+    0U,	// MVE_VLD20_32
+    0U,	// MVE_VLD20_32_wb
+    0U,	// MVE_VLD20_8
+    0U,	// MVE_VLD20_8_wb
+    0U,	// MVE_VLD21_16
+    0U,	// MVE_VLD21_16_wb
+    0U,	// MVE_VLD21_32
+    0U,	// MVE_VLD21_32_wb
+    0U,	// MVE_VLD21_8
+    0U,	// MVE_VLD21_8_wb
+    0U,	// MVE_VLD40_16
+    0U,	// MVE_VLD40_16_wb
+    0U,	// MVE_VLD40_32
+    0U,	// MVE_VLD40_32_wb
+    0U,	// MVE_VLD40_8
+    0U,	// MVE_VLD40_8_wb
+    0U,	// MVE_VLD41_16
+    0U,	// MVE_VLD41_16_wb
+    0U,	// MVE_VLD41_32
+    0U,	// MVE_VLD41_32_wb
+    0U,	// MVE_VLD41_8
+    0U,	// MVE_VLD41_8_wb
+    0U,	// MVE_VLD42_16
+    0U,	// MVE_VLD42_16_wb
+    0U,	// MVE_VLD42_32
+    0U,	// MVE_VLD42_32_wb
+    0U,	// MVE_VLD42_8
+    0U,	// MVE_VLD42_8_wb
+    0U,	// MVE_VLD43_16
+    0U,	// MVE_VLD43_16_wb
+    0U,	// MVE_VLD43_32
+    0U,	// MVE_VLD43_32_wb
+    0U,	// MVE_VLD43_8
+    0U,	// MVE_VLD43_8_wb
+    3968U,	// MVE_VLDRBS16
+    150144U,	// MVE_VLDRBS16_post
+    4096U,	// MVE_VLDRBS16_pre
+    4224U,	// MVE_VLDRBS16_rq
+    3968U,	// MVE_VLDRBS32
+    150144U,	// MVE_VLDRBS32_post
+    4096U,	// MVE_VLDRBS32_pre
+    4224U,	// MVE_VLDRBS32_rq
+    3968U,	// MVE_VLDRBU16
+    150144U,	// MVE_VLDRBU16_post
+    4096U,	// MVE_VLDRBU16_pre
+    4224U,	// MVE_VLDRBU16_rq
+    3968U,	// MVE_VLDRBU32
+    150144U,	// MVE_VLDRBU32_post
+    4096U,	// MVE_VLDRBU32_pre
+    4224U,	// MVE_VLDRBU32_rq
+    3968U,	// MVE_VLDRBU8
+    150144U,	// MVE_VLDRBU8_post
+    4352U,	// MVE_VLDRBU8_pre
+    4224U,	// MVE_VLDRBU8_rq
+    3968U,	// MVE_VLDRDU64_qi
+    4096U,	// MVE_VLDRDU64_qi_pre
+    4480U,	// MVE_VLDRDU64_rq
+    4224U,	// MVE_VLDRDU64_rq_u
+    3968U,	// MVE_VLDRHS32
+    150144U,	// MVE_VLDRHS32_post
+    4096U,	// MVE_VLDRHS32_pre
+    4608U,	// MVE_VLDRHS32_rq
+    4224U,	// MVE_VLDRHS32_rq_u
+    3968U,	// MVE_VLDRHU16
+    150144U,	// MVE_VLDRHU16_post
+    4352U,	// MVE_VLDRHU16_pre
+    4608U,	// MVE_VLDRHU16_rq
+    4224U,	// MVE_VLDRHU16_rq_u
+    3968U,	// MVE_VLDRHU32
+    150144U,	// MVE_VLDRHU32_post
+    4096U,	// MVE_VLDRHU32_pre
+    4608U,	// MVE_VLDRHU32_rq
+    4224U,	// MVE_VLDRHU32_rq_u
+    3968U,	// MVE_VLDRWU32
+    150144U,	// MVE_VLDRWU32_post
+    4352U,	// MVE_VLDRWU32_pre
+    3968U,	// MVE_VLDRWU32_qi
+    4096U,	// MVE_VLDRWU32_qi_pre
+    4736U,	// MVE_VLDRWU32_rq
+    4224U,	// MVE_VLDRWU32_rq_u
+    17920U,	// MVE_VMAXAVs16
+    17920U,	// MVE_VMAXAVs32
+    17920U,	// MVE_VMAXAVs8
+    17920U,	// MVE_VMAXAs16
+    17920U,	// MVE_VMAXAs32
+    17920U,	// MVE_VMAXAs8
+    17920U,	// MVE_VMAXNMAVf16
+    17920U,	// MVE_VMAXNMAVf32
+    17920U,	// MVE_VMAXNMAf16
+    17920U,	// MVE_VMAXNMAf32
+    17920U,	// MVE_VMAXNMVf16
+    17920U,	// MVE_VMAXNMVf32
+    0U,	// MVE_VMAXNMf16
+    0U,	// MVE_VMAXNMf32
+    17920U,	// MVE_VMAXVs16
+    17920U,	// MVE_VMAXVs32
+    17920U,	// MVE_VMAXVs8
+    17920U,	// MVE_VMAXVu16
+    17920U,	// MVE_VMAXVu32
+    17920U,	// MVE_VMAXVu8
+    0U,	// MVE_VMAXs16
+    0U,	// MVE_VMAXs32
+    0U,	// MVE_VMAXs8
+    0U,	// MVE_VMAXu16
+    0U,	// MVE_VMAXu32
+    0U,	// MVE_VMAXu8
+    17920U,	// MVE_VMINAVs16
+    17920U,	// MVE_VMINAVs32
+    17920U,	// MVE_VMINAVs8
+    17920U,	// MVE_VMINAs16
+    17920U,	// MVE_VMINAs32
+    17920U,	// MVE_VMINAs8
+    17920U,	// MVE_VMINNMAVf16
+    17920U,	// MVE_VMINNMAVf32
+    17920U,	// MVE_VMINNMAf16
+    17920U,	// MVE_VMINNMAf32
+    17920U,	// MVE_VMINNMVf16
+    17920U,	// MVE_VMINNMVf32
+    0U,	// MVE_VMINNMf16
+    0U,	// MVE_VMINNMf32
+    17920U,	// MVE_VMINVs16
+    17920U,	// MVE_VMINVs32
+    17920U,	// MVE_VMINVs8
+    17920U,	// MVE_VMINVu16
+    17920U,	// MVE_VMINVu32
+    17920U,	// MVE_VMINVu8
+    0U,	// MVE_VMINs16
+    0U,	// MVE_VMINs32
+    0U,	// MVE_VMINs8
+    0U,	// MVE_VMINu16
+    0U,	// MVE_VMINu32
+    0U,	// MVE_VMINu8
+    3671552U,	// MVE_VMLADAVas16
+    3671552U,	// MVE_VMLADAVas32
+    3671552U,	// MVE_VMLADAVas8
+    3671552U,	// MVE_VMLADAVau16
+    3671552U,	// MVE_VMLADAVau32
+    3671552U,	// MVE_VMLADAVau8
+    3671552U,	// MVE_VMLADAVaxs16
+    3671552U,	// MVE_VMLADAVaxs32
+    3671552U,	// MVE_VMLADAVaxs8
+    0U,	// MVE_VMLADAVs16
+    0U,	// MVE_VMLADAVs32
+    0U,	// MVE_VMLADAVs8
+    0U,	// MVE_VMLADAVu16
+    0U,	// MVE_VMLADAVu32
+    0U,	// MVE_VMLADAVu8
+    0U,	// MVE_VMLADAVxs16
+    0U,	// MVE_VMLADAVxs32
+    0U,	// MVE_VMLADAVxs8
+    34078720U,	// MVE_VMLALDAVas16
+    34078720U,	// MVE_VMLALDAVas32
+    34078720U,	// MVE_VMLALDAVau16
+    34078720U,	// MVE_VMLALDAVau32
+    34078720U,	// MVE_VMLALDAVaxs16
+    34078720U,	// MVE_VMLALDAVaxs32
+    33554432U,	// MVE_VMLALDAVs16
+    33554432U,	// MVE_VMLALDAVs32
+    33554432U,	// MVE_VMLALDAVu16
+    33554432U,	// MVE_VMLALDAVu32
+    33554432U,	// MVE_VMLALDAVxs16
+    33554432U,	// MVE_VMLALDAVxs32
+    3671552U,	// MVE_VMLAS_qr_i16
+    3671552U,	// MVE_VMLAS_qr_i32
+    3671552U,	// MVE_VMLAS_qr_i8
+    3671552U,	// MVE_VMLA_qr_i16
+    3671552U,	// MVE_VMLA_qr_i32
+    3671552U,	// MVE_VMLA_qr_i8
+    3671552U,	// MVE_VMLSDAVas16
+    3671552U,	// MVE_VMLSDAVas32
+    3671552U,	// MVE_VMLSDAVas8
+    3671552U,	// MVE_VMLSDAVaxs16
+    3671552U,	// MVE_VMLSDAVaxs32
+    3671552U,	// MVE_VMLSDAVaxs8
+    0U,	// MVE_VMLSDAVs16
+    0U,	// MVE_VMLSDAVs32
+    0U,	// MVE_VMLSDAVs8
+    0U,	// MVE_VMLSDAVxs16
+    0U,	// MVE_VMLSDAVxs32
+    0U,	// MVE_VMLSDAVxs8
+    34078720U,	// MVE_VMLSLDAVas16
+    34078720U,	// MVE_VMLSLDAVas32
+    34078720U,	// MVE_VMLSLDAVaxs16
+    34078720U,	// MVE_VMLSLDAVaxs32
+    33554432U,	// MVE_VMLSLDAVs16
+    33554432U,	// MVE_VMLSLDAVs32
+    33554432U,	// MVE_VMLSLDAVxs16
+    33554432U,	// MVE_VMLSLDAVxs32
+    16384U,	// MVE_VMOVLs16bh
+    16384U,	// MVE_VMOVLs16th
+    16384U,	// MVE_VMOVLs8bh
+    16384U,	// MVE_VMOVLs8th
+    16384U,	// MVE_VMOVLu16bh
+    16384U,	// MVE_VMOVLu16th
+    16384U,	// MVE_VMOVLu8bh
+    16384U,	// MVE_VMOVLu8th
+    17920U,	// MVE_VMOVNi16bh
+    17920U,	// MVE_VMOVNi16th
+    17920U,	// MVE_VMOVNi32bh
+    17920U,	// MVE_VMOVNi32th
+    163840U,	// MVE_VMOV_from_lane_32
+    163840U,	// MVE_VMOV_from_lane_s16
+    163840U,	// MVE_VMOV_from_lane_s8
+    163840U,	// MVE_VMOV_from_lane_u16
+    163840U,	// MVE_VMOV_from_lane_u8
+    32U,	// MVE_VMOV_q_rr
+    167772160U,	// MVE_VMOV_rr_q
+    34U,	// MVE_VMOV_to_lane_16
+    34U,	// MVE_VMOV_to_lane_32
+    34U,	// MVE_VMOV_to_lane_8
+    2048U,	// MVE_VMOVimmf32
+    4864U,	// MVE_VMOVimmi16
+    4864U,	// MVE_VMOVimmi32
+    0U,	// MVE_VMOVimmi64
+    4864U,	// MVE_VMOVimmi8
+    0U,	// MVE_VMULHs16
+    0U,	// MVE_VMULHs32
+    0U,	// MVE_VMULHs8
+    0U,	// MVE_VMULHu16
+    0U,	// MVE_VMULHu32
+    0U,	// MVE_VMULHu8
+    0U,	// MVE_VMULLBp16
+    0U,	// MVE_VMULLBp8
+    0U,	// MVE_VMULLBs16
+    0U,	// MVE_VMULLBs32
+    0U,	// MVE_VMULLBs8
+    0U,	// MVE_VMULLBu16
+    0U,	// MVE_VMULLBu32
+    0U,	// MVE_VMULLBu8
+    0U,	// MVE_VMULLTp16
+    0U,	// MVE_VMULLTp8
+    0U,	// MVE_VMULLTs16
+    0U,	// MVE_VMULLTs32
+    0U,	// MVE_VMULLTs8
+    0U,	// MVE_VMULLTu16
+    0U,	// MVE_VMULLTu32
+    0U,	// MVE_VMULLTu8
+    0U,	// MVE_VMUL_qr_f16
+    0U,	// MVE_VMUL_qr_f32
+    0U,	// MVE_VMUL_qr_i16
+    0U,	// MVE_VMUL_qr_i32
+    0U,	// MVE_VMUL_qr_i8
+    0U,	// MVE_VMULf16
+    0U,	// MVE_VMULf32
+    0U,	// MVE_VMULi16
+    0U,	// MVE_VMULi32
+    0U,	// MVE_VMULi8
+    16384U,	// MVE_VMVN
+    4864U,	// MVE_VMVNimmi16
+    4864U,	// MVE_VMVNimmi32
+    16384U,	// MVE_VNEGf16
+    16384U,	// MVE_VNEGf32
+    16384U,	// MVE_VNEGs16
+    16384U,	// MVE_VNEGs32
+    16384U,	// MVE_VNEGs8
+    0U,	// MVE_VORN
+    0U,	// MVE_VORR
+    3840U,	// MVE_VORRimmi16
+    3840U,	// MVE_VORRimmi32
+    0U,	// MVE_VPNOT
+    0U,	// MVE_VPSEL
+    0U,	// MVE_VPST
+    0U,	// MVE_VPTv16i8
+    0U,	// MVE_VPTv16i8r
+    0U,	// MVE_VPTv16s8
+    0U,	// MVE_VPTv16s8r
+    0U,	// MVE_VPTv16u8
+    0U,	// MVE_VPTv16u8r
+    0U,	// MVE_VPTv4f32
+    0U,	// MVE_VPTv4f32r
+    0U,	// MVE_VPTv4i32
+    0U,	// MVE_VPTv4i32r
+    0U,	// MVE_VPTv4s32
+    0U,	// MVE_VPTv4s32r
+    0U,	// MVE_VPTv4u32
+    0U,	// MVE_VPTv4u32r
+    0U,	// MVE_VPTv8f16
+    0U,	// MVE_VPTv8f16r
+    0U,	// MVE_VPTv8i16
+    0U,	// MVE_VPTv8i16r
+    0U,	// MVE_VPTv8s16
+    0U,	// MVE_VPTv8s16r
+    0U,	// MVE_VPTv8u16
+    0U,	// MVE_VPTv8u16r
+    16384U,	// MVE_VQABSs16
+    16384U,	// MVE_VQABSs32
+    16384U,	// MVE_VQABSs8
+    0U,	// MVE_VQADD_qr_s16
+    0U,	// MVE_VQADD_qr_s32
+    0U,	// MVE_VQADD_qr_s8
+    0U,	// MVE_VQADD_qr_u16
+    0U,	// MVE_VQADD_qr_u32
+    0U,	// MVE_VQADD_qr_u8
+    0U,	// MVE_VQADDs16
+    0U,	// MVE_VQADDs32
+    0U,	// MVE_VQADDs8
+    0U,	// MVE_VQADDu16
+    0U,	// MVE_VQADDu32
+    0U,	// MVE_VQADDu8
+    3671552U,	// MVE_VQDMLADHXs16
+    3671552U,	// MVE_VQDMLADHXs32
+    3671552U,	// MVE_VQDMLADHXs8
+    3671552U,	// MVE_VQDMLADHs16
+    3671552U,	// MVE_VQDMLADHs32
+    3671552U,	// MVE_VQDMLADHs8
+    3671552U,	// MVE_VQDMLAH_qrs16
+    3671552U,	// MVE_VQDMLAH_qrs32
+    3671552U,	// MVE_VQDMLAH_qrs8
+    3671552U,	// MVE_VQDMLASH_qrs16
+    3671552U,	// MVE_VQDMLASH_qrs32
+    3671552U,	// MVE_VQDMLASH_qrs8
+    3671552U,	// MVE_VQDMLSDHXs16
+    3671552U,	// MVE_VQDMLSDHXs32
+    3671552U,	// MVE_VQDMLSDHXs8
+    3671552U,	// MVE_VQDMLSDHs16
+    3671552U,	// MVE_VQDMLSDHs32
+    3671552U,	// MVE_VQDMLSDHs8
+    0U,	// MVE_VQDMULH_qr_s16
+    0U,	// MVE_VQDMULH_qr_s32
+    0U,	// MVE_VQDMULH_qr_s8
+    0U,	// MVE_VQDMULHi16
+    0U,	// MVE_VQDMULHi32
+    0U,	// MVE_VQDMULHi8
+    0U,	// MVE_VQDMULL_qr_s16bh
+    0U,	// MVE_VQDMULL_qr_s16th
+    0U,	// MVE_VQDMULL_qr_s32bh
+    0U,	// MVE_VQDMULL_qr_s32th
+    0U,	// MVE_VQDMULLs16bh
+    0U,	// MVE_VQDMULLs16th
+    0U,	// MVE_VQDMULLs32bh
+    0U,	// MVE_VQDMULLs32th
+    17920U,	// MVE_VQMOVNs16bh
+    17920U,	// MVE_VQMOVNs16th
+    17920U,	// MVE_VQMOVNs32bh
+    17920U,	// MVE_VQMOVNs32th
+    17920U,	// MVE_VQMOVNu16bh
+    17920U,	// MVE_VQMOVNu16th
+    17920U,	// MVE_VQMOVNu32bh
+    17920U,	// MVE_VQMOVNu32th
+    17920U,	// MVE_VQMOVUNs16bh
+    17920U,	// MVE_VQMOVUNs16th
+    17920U,	// MVE_VQMOVUNs32bh
+    17920U,	// MVE_VQMOVUNs32th
+    16384U,	// MVE_VQNEGs16
+    16384U,	// MVE_VQNEGs32
+    16384U,	// MVE_VQNEGs8
+    3671552U,	// MVE_VQRDMLADHXs16
+    3671552U,	// MVE_VQRDMLADHXs32
+    3671552U,	// MVE_VQRDMLADHXs8
+    3671552U,	// MVE_VQRDMLADHs16
+    3671552U,	// MVE_VQRDMLADHs32
+    3671552U,	// MVE_VQRDMLADHs8
+    3671552U,	// MVE_VQRDMLAH_qrs16
+    3671552U,	// MVE_VQRDMLAH_qrs32
+    3671552U,	// MVE_VQRDMLAH_qrs8
+    3671552U,	// MVE_VQRDMLASH_qrs16
+    3671552U,	// MVE_VQRDMLASH_qrs32
+    3671552U,	// MVE_VQRDMLASH_qrs8
+    3671552U,	// MVE_VQRDMLSDHXs16
+    3671552U,	// MVE_VQRDMLSDHXs32
+    3671552U,	// MVE_VQRDMLSDHXs8
+    3671552U,	// MVE_VQRDMLSDHs16
+    3671552U,	// MVE_VQRDMLSDHs32
+    3671552U,	// MVE_VQRDMLSDHs8
+    0U,	// MVE_VQRDMULH_qr_s16
+    0U,	// MVE_VQRDMULH_qr_s32
+    0U,	// MVE_VQRDMULH_qr_s8
+    0U,	// MVE_VQRDMULHi16
+    0U,	// MVE_VQRDMULHi32
+    0U,	// MVE_VQRDMULHi8
+    0U,	// MVE_VQRSHL_by_vecs16
+    0U,	// MVE_VQRSHL_by_vecs32
+    0U,	// MVE_VQRSHL_by_vecs8
+    0U,	// MVE_VQRSHL_by_vecu16
+    0U,	// MVE_VQRSHL_by_vecu32
+    0U,	// MVE_VQRSHL_by_vecu8
+    17920U,	// MVE_VQRSHL_qrs16
+    17920U,	// MVE_VQRSHL_qrs32
+    17920U,	// MVE_VQRSHL_qrs8
+    17920U,	// MVE_VQRSHL_qru16
+    17920U,	// MVE_VQRSHL_qru32
+    17920U,	// MVE_VQRSHL_qru8
+    3671552U,	// MVE_VQRSHRNbhs16
+    3671552U,	// MVE_VQRSHRNbhs32
+    3671552U,	// MVE_VQRSHRNbhu16
+    3671552U,	// MVE_VQRSHRNbhu32
+    3671552U,	// MVE_VQRSHRNths16
+    3671552U,	// MVE_VQRSHRNths32
+    3671552U,	// MVE_VQRSHRNthu16
+    3671552U,	// MVE_VQRSHRNthu32
+    3671552U,	// MVE_VQRSHRUNs16bh
+    3671552U,	// MVE_VQRSHRUNs16th
+    3671552U,	// MVE_VQRSHRUNs32bh
+    3671552U,	// MVE_VQRSHRUNs32th
+    0U,	// MVE_VQSHLU_imms16
+    0U,	// MVE_VQSHLU_imms32
+    0U,	// MVE_VQSHLU_imms8
+    0U,	// MVE_VQSHL_by_vecs16
+    0U,	// MVE_VQSHL_by_vecs32
+    0U,	// MVE_VQSHL_by_vecs8
+    0U,	// MVE_VQSHL_by_vecu16
+    0U,	// MVE_VQSHL_by_vecu32
+    0U,	// MVE_VQSHL_by_vecu8
+    17920U,	// MVE_VQSHL_qrs16
+    17920U,	// MVE_VQSHL_qrs32
+    17920U,	// MVE_VQSHL_qrs8
+    17920U,	// MVE_VQSHL_qru16
+    17920U,	// MVE_VQSHL_qru32
+    17920U,	// MVE_VQSHL_qru8
+    0U,	// MVE_VQSHLimms16
+    0U,	// MVE_VQSHLimms32
+    0U,	// MVE_VQSHLimms8
+    0U,	// MVE_VQSHLimmu16
+    0U,	// MVE_VQSHLimmu32
+    0U,	// MVE_VQSHLimmu8
+    3671552U,	// MVE_VQSHRNbhs16
+    3671552U,	// MVE_VQSHRNbhs32
+    3671552U,	// MVE_VQSHRNbhu16
+    3671552U,	// MVE_VQSHRNbhu32
+    3671552U,	// MVE_VQSHRNths16
+    3671552U,	// MVE_VQSHRNths32
+    3671552U,	// MVE_VQSHRNthu16
+    3671552U,	// MVE_VQSHRNthu32
+    3671552U,	// MVE_VQSHRUNs16bh
+    3671552U,	// MVE_VQSHRUNs16th
+    3671552U,	// MVE_VQSHRUNs32bh
+    3671552U,	// MVE_VQSHRUNs32th
+    0U,	// MVE_VQSUB_qr_s16
+    0U,	// MVE_VQSUB_qr_s32
+    0U,	// MVE_VQSUB_qr_s8
+    0U,	// MVE_VQSUB_qr_u16
+    0U,	// MVE_VQSUB_qr_u32
+    0U,	// MVE_VQSUB_qr_u8
+    0U,	// MVE_VQSUBs16
+    0U,	// MVE_VQSUBs32
+    0U,	// MVE_VQSUBs8
+    0U,	// MVE_VQSUBu16
+    0U,	// MVE_VQSUBu32
+    0U,	// MVE_VQSUBu8
+    16384U,	// MVE_VREV16_8
+    16384U,	// MVE_VREV32_16
+    16384U,	// MVE_VREV32_8
+    16384U,	// MVE_VREV64_16
+    16384U,	// MVE_VREV64_32
+    16384U,	// MVE_VREV64_8
+    0U,	// MVE_VRHADDs16
+    0U,	// MVE_VRHADDs32
+    0U,	// MVE_VRHADDs8
+    0U,	// MVE_VRHADDu16
+    0U,	// MVE_VRHADDu32
+    0U,	// MVE_VRHADDu8
+    16384U,	// MVE_VRINTf16A
+    16384U,	// MVE_VRINTf16M
+    16384U,	// MVE_VRINTf16N
+    16384U,	// MVE_VRINTf16P
+    16384U,	// MVE_VRINTf16X
+    16384U,	// MVE_VRINTf16Z
+    16384U,	// MVE_VRINTf32A
+    16384U,	// MVE_VRINTf32M
+    16384U,	// MVE_VRINTf32N
+    16384U,	// MVE_VRINTf32P
+    16384U,	// MVE_VRINTf32X
+    16384U,	// MVE_VRINTf32Z
+    34078720U,	// MVE_VRMLALDAVHas32
+    34078720U,	// MVE_VRMLALDAVHau32
+    34078720U,	// MVE_VRMLALDAVHaxs32
+    33554432U,	// MVE_VRMLALDAVHs32
+    33554432U,	// MVE_VRMLALDAVHu32
+    33554432U,	// MVE_VRMLALDAVHxs32
+    34078720U,	// MVE_VRMLSLDAVHas32
+    34078720U,	// MVE_VRMLSLDAVHaxs32
+    33554432U,	// MVE_VRMLSLDAVHs32
+    33554432U,	// MVE_VRMLSLDAVHxs32
+    0U,	// MVE_VRMULHs16
+    0U,	// MVE_VRMULHs32
+    0U,	// MVE_VRMULHs8
+    0U,	// MVE_VRMULHu16
+    0U,	// MVE_VRMULHu32
+    0U,	// MVE_VRMULHu8
+    0U,	// MVE_VRSHL_by_vecs16
+    0U,	// MVE_VRSHL_by_vecs32
+    0U,	// MVE_VRSHL_by_vecs8
+    0U,	// MVE_VRSHL_by_vecu16
+    0U,	// MVE_VRSHL_by_vecu32
+    0U,	// MVE_VRSHL_by_vecu8
+    17920U,	// MVE_VRSHL_qrs16
+    17920U,	// MVE_VRSHL_qrs32
+    17920U,	// MVE_VRSHL_qrs8
+    17920U,	// MVE_VRSHL_qru16
+    17920U,	// MVE_VRSHL_qru32
+    17920U,	// MVE_VRSHL_qru8
+    3671552U,	// MVE_VRSHRNi16bh
+    3671552U,	// MVE_VRSHRNi16th
+    3671552U,	// MVE_VRSHRNi32bh
+    3671552U,	// MVE_VRSHRNi32th
+    0U,	// MVE_VRSHR_imms16
+    0U,	// MVE_VRSHR_imms32
+    0U,	// MVE_VRSHR_imms8
+    0U,	// MVE_VRSHR_immu16
+    0U,	// MVE_VRSHR_immu32
+    0U,	// MVE_VRSHR_immu8
+    3671552U,	// MVE_VSBC
+    3671552U,	// MVE_VSBCI
+    524672U,	// MVE_VSHLC
+    0U,	// MVE_VSHLL_imms16bh
+    0U,	// MVE_VSHLL_imms16th
+    0U,	// MVE_VSHLL_imms8bh
+    0U,	// MVE_VSHLL_imms8th
+    0U,	// MVE_VSHLL_immu16bh
+    0U,	// MVE_VSHLL_immu16th
+    0U,	// MVE_VSHLL_immu8bh
+    0U,	// MVE_VSHLL_immu8th
+    180224U,	// MVE_VSHLL_lws16bh
+    180224U,	// MVE_VSHLL_lws16th
+    196608U,	// MVE_VSHLL_lws8bh
+    196608U,	// MVE_VSHLL_lws8th
+    180224U,	// MVE_VSHLL_lwu16bh
+    180224U,	// MVE_VSHLL_lwu16th
+    196608U,	// MVE_VSHLL_lwu8bh
+    196608U,	// MVE_VSHLL_lwu8th
+    0U,	// MVE_VSHL_by_vecs16
+    0U,	// MVE_VSHL_by_vecs32
+    0U,	// MVE_VSHL_by_vecs8
+    0U,	// MVE_VSHL_by_vecu16
+    0U,	// MVE_VSHL_by_vecu32
+    0U,	// MVE_VSHL_by_vecu8
+    0U,	// MVE_VSHL_immi16
+    0U,	// MVE_VSHL_immi32
+    0U,	// MVE_VSHL_immi8
+    17920U,	// MVE_VSHL_qrs16
+    17920U,	// MVE_VSHL_qrs32
+    17920U,	// MVE_VSHL_qrs8
+    17920U,	// MVE_VSHL_qru16
+    17920U,	// MVE_VSHL_qru32
+    17920U,	// MVE_VSHL_qru8
+    3671552U,	// MVE_VSHRNi16bh
+    3671552U,	// MVE_VSHRNi16th
+    3671552U,	// MVE_VSHRNi32bh
+    3671552U,	// MVE_VSHRNi32th
+    0U,	// MVE_VSHR_imms16
+    0U,	// MVE_VSHR_imms32
+    0U,	// MVE_VSHR_imms8
+    0U,	// MVE_VSHR_immu16
+    0U,	// MVE_VSHR_immu32
+    0U,	// MVE_VSHR_immu8
+    3671552U,	// MVE_VSLIimm16
+    3671552U,	// MVE_VSLIimm32
+    3671552U,	// MVE_VSLIimm8
+    3671552U,	// MVE_VSRIimm16
+    3671552U,	// MVE_VSRIimm32
+    3671552U,	// MVE_VSRIimm8
+    0U,	// MVE_VST20_16
+    0U,	// MVE_VST20_16_wb
+    0U,	// MVE_VST20_32
+    0U,	// MVE_VST20_32_wb
+    0U,	// MVE_VST20_8
+    0U,	// MVE_VST20_8_wb
+    0U,	// MVE_VST21_16
+    0U,	// MVE_VST21_16_wb
+    0U,	// MVE_VST21_32
+    0U,	// MVE_VST21_32_wb
+    0U,	// MVE_VST21_8
+    0U,	// MVE_VST21_8_wb
+    0U,	// MVE_VST40_16
+    0U,	// MVE_VST40_16_wb
+    0U,	// MVE_VST40_32
+    0U,	// MVE_VST40_32_wb
+    0U,	// MVE_VST40_8
+    0U,	// MVE_VST40_8_wb
+    0U,	// MVE_VST41_16
+    0U,	// MVE_VST41_16_wb
+    0U,	// MVE_VST41_32
+    0U,	// MVE_VST41_32_wb
+    0U,	// MVE_VST41_8
+    0U,	// MVE_VST41_8_wb
+    0U,	// MVE_VST42_16
+    0U,	// MVE_VST42_16_wb
+    0U,	// MVE_VST42_32
+    0U,	// MVE_VST42_32_wb
+    0U,	// MVE_VST42_8
+    0U,	// MVE_VST42_8_wb
+    0U,	// MVE_VST43_16
+    0U,	// MVE_VST43_16_wb
+    0U,	// MVE_VST43_32
+    0U,	// MVE_VST43_32_wb
+    0U,	// MVE_VST43_8
+    0U,	// MVE_VST43_8_wb
+    3968U,	// MVE_VSTRB16
+    150144U,	// MVE_VSTRB16_post
+    4096U,	// MVE_VSTRB16_pre
+    4224U,	// MVE_VSTRB16_rq
+    3968U,	// MVE_VSTRB32
+    150144U,	// MVE_VSTRB32_post
+    4096U,	// MVE_VSTRB32_pre
+    4224U,	// MVE_VSTRB32_rq
+    4224U,	// MVE_VSTRB8_rq
+    3968U,	// MVE_VSTRBU8
+    150144U,	// MVE_VSTRBU8_post
+    4352U,	// MVE_VSTRBU8_pre
+    3968U,	// MVE_VSTRD64_qi
+    4096U,	// MVE_VSTRD64_qi_pre
+    4480U,	// MVE_VSTRD64_rq
+    4224U,	// MVE_VSTRD64_rq_u
+    4608U,	// MVE_VSTRH16_rq
+    4224U,	// MVE_VSTRH16_rq_u
+    3968U,	// MVE_VSTRH32
+    150144U,	// MVE_VSTRH32_post
+    4096U,	// MVE_VSTRH32_pre
+    4608U,	// MVE_VSTRH32_rq
+    4224U,	// MVE_VSTRH32_rq_u
+    3968U,	// MVE_VSTRHU16
+    150144U,	// MVE_VSTRHU16_post
+    4352U,	// MVE_VSTRHU16_pre
+    3968U,	// MVE_VSTRW32_qi
+    4096U,	// MVE_VSTRW32_qi_pre
+    4736U,	// MVE_VSTRW32_rq
+    4224U,	// MVE_VSTRW32_rq_u
+    3968U,	// MVE_VSTRWU32
+    150144U,	// MVE_VSTRWU32_post
+    4352U,	// MVE_VSTRWU32_pre
+    0U,	// MVE_VSUB_qr_f16
+    0U,	// MVE_VSUB_qr_f32
+    0U,	// MVE_VSUB_qr_i16
+    0U,	// MVE_VSUB_qr_i32
+    0U,	// MVE_VSUB_qr_i8
+    0U,	// MVE_VSUBf16
+    0U,	// MVE_VSUBf32
+    0U,	// MVE_VSUBi16
+    0U,	// MVE_VSUBi32
+    0U,	// MVE_VSUBi8
+    21376U,	// MVE_WLSTP_16
+    21376U,	// MVE_WLSTP_32
+    21376U,	// MVE_WLSTP_64
+    21376U,	// MVE_WLSTP_8
+    1792U,	// MVNi
+    16384U,	// MVNr
+    1920U,	// MVNsi
+    1152U,	// MVNsr
+    17920U,	// NEON_VMAXNMNDf
+    17920U,	// NEON_VMAXNMNDh
+    17920U,	// NEON_VMAXNMNQf
+    17920U,	// NEON_VMAXNMNQh
+    17920U,	// NEON_VMINNMNDf
+    17920U,	// NEON_VMINNMNDh
+    17920U,	// NEON_VMINNMNQf
+    17920U,	// NEON_VMINNMNQh
+    1048576U,	// ORRri
     0U,	// ORRrr
-    131072U,	// ORRrsi
+    1572864U,	// ORRrsi
     0U,	// ORRrsr
-    8388608U,	// PKHBT
-    10485760U,	// PKHTB
+    201326592U,	// PKHBT
+    234881024U,	// PKHTB
     0U,	// PLDWi12
     0U,	// PLDWrs
     0U,	// PLDi12
@@ -4470,10 +6970,10 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// QSUB
     0U,	// QSUB16
     0U,	// QSUB8
-    1024U,	// RBIT
-    1024U,	// REV
-    1024U,	// REV16
-    1024U,	// REVSH
+    16384U,	// RBIT
+    16384U,	// REV
+    16384U,	// REV16
+    16384U,	// REVSH
     0U,	// RFEDA
     0U,	// RFEDA_UPD
     0U,	// RFEDB
@@ -4482,73 +6982,74 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// RFEIA_UPD
     0U,	// RFEIB
     0U,	// RFEIB_UPD
-    98304U,	// RSBri
+    1048576U,	// RSBri
     0U,	// RSBrr
-    131072U,	// RSBrsi
+    1572864U,	// RSBrsi
     0U,	// RSBrsr
-    98304U,	// RSCri
+    1048576U,	// RSCri
     0U,	// RSCrr
-    131072U,	// RSCrsi
+    1572864U,	// RSCrsi
     0U,	// RSCrsr
     0U,	// SADD16
     0U,	// SADD8
     0U,	// SASX
-    98304U,	// SBCri
+    0U,	// SB
+    1048576U,	// SBCri
     0U,	// SBCrr
-    131072U,	// SBCrsi
+    1572864U,	// SBCrsi
     0U,	// SBCrsr
-    69206016U,	// SBFX
+    33554432U,	// SBFX
     0U,	// SDIV
     0U,	// SEL
     0U,	// SETEND
     0U,	// SETPAN
-    1048U,	// SHA1C
-    0U,	// SHA1H
-    1048U,	// SHA1M
-    1048U,	// SHA1P
-    1048U,	// SHA1SU0
-    0U,	// SHA1SU1
-    1048U,	// SHA256H
-    1048U,	// SHA256H2
-    0U,	// SHA256SU0
-    1048U,	// SHA256SU1
+    16768U,	// SHA1C
+    2U,	// SHA1H
+    16768U,	// SHA1M
+    16768U,	// SHA1P
+    16768U,	// SHA1SU0
+    2U,	// SHA1SU1
+    16768U,	// SHA256H
+    16768U,	// SHA256H2
+    2U,	// SHA256SU0
+    16768U,	// SHA256SU1
     0U,	// SHADD16
     0U,	// SHADD8
     0U,	// SHASX
     0U,	// SHSAX
     0U,	// SHSUB16
     0U,	// SHSUB8
-    0U,	// SMC
-    35651584U,	// SMLABB
-    35651584U,	// SMLABT
-    35651584U,	// SMLAD
-    35651584U,	// SMLADX
+    2U,	// SMC
+    33554432U,	// SMLABB
+    33554432U,	// SMLABT
+    33554432U,	// SMLAD
+    33554432U,	// SMLADX
     0U,	// SMLAL
-    35651584U,	// SMLALBB
-    35651584U,	// SMLALBT
-    35651584U,	// SMLALD
-    35651584U,	// SMLALDX
-    35651584U,	// SMLALTB
-    35651584U,	// SMLALTT
-    35651584U,	// SMLATB
-    35651584U,	// SMLATT
-    35651584U,	// SMLAWB
-    35651584U,	// SMLAWT
-    35651584U,	// SMLSD
-    35651584U,	// SMLSDX
-    35651584U,	// SMLSLD
-    35651584U,	// SMLSLDX
-    35651584U,	// SMMLA
-    35651584U,	// SMMLAR
-    35651584U,	// SMMLS
-    35651584U,	// SMMLSR
+    33554432U,	// SMLALBB
+    33554432U,	// SMLALBT
+    33554432U,	// SMLALD
+    33554432U,	// SMLALDX
+    33554432U,	// SMLALTB
+    33554432U,	// SMLALTT
+    33554432U,	// SMLATB
+    33554432U,	// SMLATT
+    33554432U,	// SMLAWB
+    33554432U,	// SMLAWT
+    33554432U,	// SMLSD
+    33554432U,	// SMLSDX
+    33554432U,	// SMLSLD
+    33554432U,	// SMLSLDX
+    33554432U,	// SMMLA
+    33554432U,	// SMMLAR
+    33554432U,	// SMMLS
+    33554432U,	// SMMLSR
     0U,	// SMMUL
     0U,	// SMMULR
     0U,	// SMUAD
     0U,	// SMUADX
     0U,	// SMULBB
     0U,	// SMULBT
-    35651584U,	// SMULL
+    33554432U,	// SMULL
     0U,	// SMULTB
     0U,	// SMULTT
     0U,	// SMULWB
@@ -4563,98 +7064,98 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// SRSIA_UPD
     0U,	// SRSIB
     0U,	// SRSIB_UPD
-    6352U,	// SSAT
-    1232U,	// SSAT16
+    218112U,	// SSAT
+    21504U,	// SSAT16
     0U,	// SSAX
     0U,	// SSUB16
     0U,	// SSUB8
     0U,	// STC2L_OFFSET
-    1U,	// STC2L_OPTION
-    2U,	// STC2L_POST
+    2304U,	// STC2L_OPTION
+    2432U,	// STC2L_POST
     0U,	// STC2L_PRE
     0U,	// STC2_OFFSET
-    1U,	// STC2_OPTION
-    2U,	// STC2_POST
+    2304U,	// STC2_OPTION
+    2432U,	// STC2_POST
     0U,	// STC2_PRE
-    122U,	// STCL_OFFSET
-    196738U,	// STCL_OPTION
-    229506U,	// STCL_POST
-    138U,	// STCL_PRE
-    122U,	// STC_OFFSET
-    196738U,	// STC_OPTION
-    229506U,	// STC_POST
-    138U,	// STC_PRE
-    8U,	// STL
-    8U,	// STLB
-    557056U,	// STLEX
-    557056U,	// STLEXB
-    216U,	// STLEXD
-    557056U,	// STLEXH
-    8U,	// STLH
-    1136U,	// STMDA
-    33U,	// STMDA_UPD
-    1136U,	// STMDB
-    33U,	// STMDB_UPD
-    1136U,	// STMIA
-    33U,	// STMIA_UPD
-    1136U,	// STMIB
-    33U,	// STMIB_UPD
-    262272U,	// STRBT_POST_IMM
-    262272U,	// STRBT_POST_REG
-    262272U,	// STRB_POST_IMM
-    262272U,	// STRB_POST_REG
-    144U,	// STRB_PRE_IMM
-    152U,	// STRB_PRE_REG
-    160U,	// STRBi12
-    168U,	// STRBrs
-    294912U,	// STRD
-    2424920U,	// STRD_POST
-    360536U,	// STRD_PRE
-    557056U,	// STREX
-    557056U,	// STREXB
-    216U,	// STREXD
-    557056U,	// STREXH
-    176U,	// STRH
-    393344U,	// STRHTi
-    426112U,	// STRHTr
-    458880U,	// STRH_POST
-    184U,	// STRH_PRE
-    262272U,	// STRT_POST_IMM
-    262272U,	// STRT_POST_REG
-    262272U,	// STR_POST_IMM
-    262272U,	// STR_POST_REG
-    144U,	// STR_PRE_IMM
-    152U,	// STR_PRE_REG
-    160U,	// STRi12
-    168U,	// STRrs
-    98304U,	// SUBri
+    2580U,	// STCL_OFFSET
+    4721300U,	// STCL_OPTION
+    5245588U,	// STCL_POST
+    22U,	// STCL_PRE
+    2580U,	// STC_OFFSET
+    4721300U,	// STC_OPTION
+    5245588U,	// STC_POST
+    22U,	// STC_PRE
+    128U,	// STL
+    128U,	// STLB
+    10485760U,	// STLEX
+    10485760U,	// STLEXB
+    5248U,	// STLEXD
+    10485760U,	// STLEXH
+    128U,	// STLH
+    18560U,	// STMDA
+    530U,	// STMDA_UPD
+    18560U,	// STMDB
+    530U,	// STMDB_UPD
+    18560U,	// STMIA
+    530U,	// STMIA_UPD
+    18560U,	// STMIB
+    530U,	// STMIB_UPD
+    5769856U,	// STRBT_POST_IMM
+    5769856U,	// STRBT_POST_REG
+    5769856U,	// STRB_POST_IMM
+    5769856U,	// STRB_POST_REG
+    2816U,	// STRB_PRE_IMM
+    2944U,	// STRB_PRE_REG
+    3072U,	// STRBi12
+    3200U,	// STRBrs
+    6291456U,	// STRD
+    40371712U,	// STRD_POST
+    7341568U,	// STRD_PRE
+    10485760U,	// STREX
+    10485760U,	// STREXB
+    5248U,	// STREXD
+    10485760U,	// STREXH
+    3328U,	// STRH
+    7867008U,	// STRHTi
+    8391296U,	// STRHTr
+    8915584U,	// STRH_POST
+    3456U,	// STRH_PRE
+    5769856U,	// STRT_POST_IMM
+    5769856U,	// STRT_POST_REG
+    5769856U,	// STR_POST_IMM
+    5769856U,	// STR_POST_REG
+    2816U,	// STR_PRE_IMM
+    2944U,	// STR_PRE_REG
+    3072U,	// STRi12
+    3200U,	// STRrs
+    1048576U,	// SUBri
     0U,	// SUBrr
-    131072U,	// SUBrsi
+    1572864U,	// SUBrsi
     0U,	// SUBrsr
-    0U,	// SVC
-    557056U,	// SWP
-    557056U,	// SWPB
-    12582912U,	// SXTAB
-    12582912U,	// SXTAB16
-    12582912U,	// SXTAH
-    7168U,	// SXTB
-    7168U,	// SXTB16
-    7168U,	// SXTH
-    96U,	// TEQri
-    1024U,	// TEQrr
-    104U,	// TEQrsi
-    64U,	// TEQrsr
+    2U,	// SVC
+    10485760U,	// SWP
+    10485760U,	// SWPB
+    268435456U,	// SXTAB
+    268435456U,	// SXTAB16
+    268435456U,	// SXTAH
+    229376U,	// SXTB
+    229376U,	// SXTB16
+    229376U,	// SXTH
+    1792U,	// TEQri
+    16384U,	// TEQrr
+    1920U,	// TEQrsi
+    1152U,	// TEQrsr
     0U,	// TRAP
     0U,	// TRAPNaCl
     0U,	// TSB
-    96U,	// TSTri
-    1024U,	// TSTrr
-    104U,	// TSTrsi
-    64U,	// TSTrsr
+    1792U,	// TSTri
+    16384U,	// TSTrr
+    1920U,	// TSTrsi
+    1152U,	// TSTrsr
     0U,	// UADD16
     0U,	// UADD8
     0U,	// UASX
-    69206016U,	// UBFX
+    33554432U,	// UBFX
     0U,	// UDF
     0U,	// UDIV
     0U,	// UHADD16
@@ -4663,9 +7164,9 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// UHSAX
     0U,	// UHSUB16
     0U,	// UHSUB8
-    35651584U,	// UMAAL
+    33554432U,	// UMAAL
     0U,	// UMLAL
-    35651584U,	// UMULL
+    33554432U,	// UMULL
     0U,	// UQADD16
     0U,	// UQADD8
     0U,	// UQASX
@@ -4673,337 +7174,343 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// UQSUB16
     0U,	// UQSUB8
     0U,	// USAD8
-    35651584U,	// USADA8
-    14680064U,	// USAT
+    33554432U,	// USADA8
+    301989888U,	// USAT
     0U,	// USAT16
     0U,	// USAX
     0U,	// USUB16
     0U,	// USUB8
-    12582912U,	// UXTAB
-    12582912U,	// UXTAB16
-    12582912U,	// UXTAH
-    7168U,	// UXTB
-    7168U,	// UXTB16
-    7168U,	// UXTH
-    1048U,	// VABALsv2i64
-    1048U,	// VABALsv4i32
-    1048U,	// VABALsv8i16
-    1048U,	// VABALuv2i64
-    1048U,	// VABALuv4i32
-    1048U,	// VABALuv8i16
-    1048U,	// VABAsv16i8
-    1048U,	// VABAsv2i32
-    1048U,	// VABAsv4i16
-    1048U,	// VABAsv4i32
-    1048U,	// VABAsv8i16
-    1048U,	// VABAsv8i8
-    1048U,	// VABAuv16i8
-    1048U,	// VABAuv2i32
-    1048U,	// VABAuv4i16
-    1048U,	// VABAuv4i32
-    1048U,	// VABAuv8i16
-    1048U,	// VABAuv8i8
-    1112U,	// VABDLsv2i64
-    1112U,	// VABDLsv4i32
-    1112U,	// VABDLsv8i16
-    1112U,	// VABDLuv2i64
-    1112U,	// VABDLuv4i32
-    1112U,	// VABDLuv8i16
-    70705U,	// VABDfd
-    70705U,	// VABDfq
-    70705U,	// VABDhd
-    70705U,	// VABDhq
-    1112U,	// VABDsv16i8
-    1112U,	// VABDsv2i32
-    1112U,	// VABDsv4i16
-    1112U,	// VABDsv4i32
-    1112U,	// VABDsv8i16
-    1112U,	// VABDsv8i8
-    1112U,	// VABDuv16i8
-    1112U,	// VABDuv2i32
-    1112U,	// VABDuv4i16
-    1112U,	// VABDuv4i32
-    1112U,	// VABDuv8i16
-    1112U,	// VABDuv8i8
-    33U,	// VABSD
-    33U,	// VABSH
-    33U,	// VABSS
-    33U,	// VABSfd
-    33U,	// VABSfq
-    33U,	// VABShd
-    33U,	// VABShq
-    0U,	// VABSv16i8
-    0U,	// VABSv2i32
-    0U,	// VABSv4i16
-    0U,	// VABSv4i32
-    0U,	// VABSv8i16
-    0U,	// VABSv8i8
-    70705U,	// VACGEfd
-    70705U,	// VACGEfq
-    70705U,	// VACGEhd
-    70705U,	// VACGEhq
-    70705U,	// VACGTfd
-    70705U,	// VACGTfq
-    70705U,	// VACGThd
-    70705U,	// VACGThq
-    70705U,	// VADDD
-    70705U,	// VADDH
-    1112U,	// VADDHNv2i32
-    1112U,	// VADDHNv4i16
-    1112U,	// VADDHNv8i8
-    1112U,	// VADDLsv2i64
-    1112U,	// VADDLsv4i32
-    1112U,	// VADDLsv8i16
-    1112U,	// VADDLuv2i64
-    1112U,	// VADDLuv4i32
-    1112U,	// VADDLuv8i16
-    70705U,	// VADDS
-    1112U,	// VADDWsv2i64
-    1112U,	// VADDWsv4i32
-    1112U,	// VADDWsv8i16
-    1112U,	// VADDWuv2i64
-    1112U,	// VADDWuv4i32
-    1112U,	// VADDWuv8i16
-    70705U,	// VADDfd
-    70705U,	// VADDfq
-    70705U,	// VADDhd
-    70705U,	// VADDhq
-    1112U,	// VADDv16i8
-    1112U,	// VADDv1i64
-    1112U,	// VADDv2i32
-    1112U,	// VADDv2i64
-    1112U,	// VADDv4i16
-    1112U,	// VADDv4i32
-    1112U,	// VADDv8i16
-    1112U,	// VADDv8i8
+    268435456U,	// UXTAB
+    268435456U,	// UXTAB16
+    268435456U,	// UXTAH
+    229376U,	// UXTB
+    229376U,	// UXTB16
+    229376U,	// UXTH
+    3671552U,	// VABALsv2i64
+    3671552U,	// VABALsv4i32
+    3671552U,	// VABALsv8i16
+    3671552U,	// VABALuv2i64
+    3671552U,	// VABALuv4i32
+    3671552U,	// VABALuv8i16
+    3671552U,	// VABAsv16i8
+    3671552U,	// VABAsv2i32
+    3671552U,	// VABAsv4i16
+    3671552U,	// VABAsv4i32
+    3671552U,	// VABAsv8i16
+    3671552U,	// VABAsv8i8
+    3671552U,	// VABAuv16i8
+    3671552U,	// VABAuv2i32
+    3671552U,	// VABAuv4i16
+    3671552U,	// VABAuv4i32
+    3671552U,	// VABAuv8i16
+    3671552U,	// VABAuv8i8
+    0U,	// VABDLsv2i64
+    0U,	// VABDLsv4i32
+    0U,	// VABDLsv8i16
+    0U,	// VABDLuv2i64
+    0U,	// VABDLuv4i32
+    0U,	// VABDLuv8i16
+    0U,	// VABDfd
+    0U,	// VABDfq
+    0U,	// VABDhd
+    0U,	// VABDhq
+    0U,	// VABDsv16i8
+    0U,	// VABDsv2i32
+    0U,	// VABDsv4i16
+    0U,	// VABDsv4i32
+    0U,	// VABDsv8i16
+    0U,	// VABDsv8i8
+    0U,	// VABDuv16i8
+    0U,	// VABDuv2i32
+    0U,	// VABDuv4i16
+    0U,	// VABDuv4i32
+    0U,	// VABDuv8i16
+    0U,	// VABDuv8i8
+    526U,	// VABSD
+    16384U,	// VABSH
+    16384U,	// VABSS
+    16384U,	// VABSfd
+    16384U,	// VABSfq
+    16384U,	// VABShd
+    16384U,	// VABShq
+    16384U,	// VABSv16i8
+    16384U,	// VABSv2i32
+    16384U,	// VABSv4i16
+    16384U,	// VABSv4i32
+    16384U,	// VABSv8i16
+    16384U,	// VABSv8i8
+    0U,	// VACGEfd
+    0U,	// VACGEfq
+    0U,	// VACGEhd
+    0U,	// VACGEhq
+    0U,	// VACGTfd
+    0U,	// VACGTfq
+    0U,	// VACGThd
+    0U,	// VACGThq
+    2212622U,	// VADDD
+    0U,	// VADDH
+    17920U,	// VADDHNv2i32
+    0U,	// VADDHNv4i16
+    0U,	// VADDHNv8i8
+    0U,	// VADDLsv2i64
+    0U,	// VADDLsv4i32
+    0U,	// VADDLsv8i16
+    0U,	// VADDLuv2i64
+    0U,	// VADDLuv4i32
+    0U,	// VADDLuv8i16
+    0U,	// VADDS
+    0U,	// VADDWsv2i64
+    0U,	// VADDWsv4i32
+    0U,	// VADDWsv8i16
+    0U,	// VADDWuv2i64
+    0U,	// VADDWuv4i32
+    0U,	// VADDWuv8i16
+    0U,	// VADDfd
+    0U,	// VADDfq
+    0U,	// VADDhd
+    0U,	// VADDhq
+    0U,	// VADDv16i8
+    17920U,	// VADDv1i64
+    0U,	// VADDv2i32
+    17920U,	// VADDv2i64
+    0U,	// VADDv4i16
+    0U,	// VADDv4i32
+    0U,	// VADDv8i16
+    0U,	// VADDv8i8
     0U,	// VANDd
     0U,	// VANDq
+    16768U,	// VBF16MALBQ
+    2163072U,	// VBF16MALBQI
+    16768U,	// VBF16MALTQ
+    2163072U,	// VBF16MALTQI
     0U,	// VBICd
-    0U,	// VBICiv2i32
-    0U,	// VBICiv4i16
-    0U,	// VBICiv4i32
-    0U,	// VBICiv8i16
+    4864U,	// VBICiv2i32
+    4864U,	// VBICiv4i16
+    4864U,	// VBICiv4i32
+    4864U,	// VBICiv8i16
     0U,	// VBICq
-    589912U,	// VBIFd
-    589912U,	// VBIFq
-    589912U,	// VBITd
-    589912U,	// VBITq
-    589912U,	// VBSLd
-    589912U,	// VBSLq
-    622680U,	// VCADDv2f32
-    622680U,	// VCADDv4f16
-    622680U,	// VCADDv4f32
-    622680U,	// VCADDv8f16
-    70705U,	// VCEQfd
-    70705U,	// VCEQfq
-    70705U,	// VCEQhd
-    70705U,	// VCEQhq
-    1112U,	// VCEQv16i8
-    1112U,	// VCEQv2i32
-    1112U,	// VCEQv4i16
-    1112U,	// VCEQv4i32
-    1112U,	// VCEQv8i16
-    1112U,	// VCEQv8i8
-    3U,	// VCEQzv16i8
-    225U,	// VCEQzv2f32
-    3U,	// VCEQzv2i32
-    225U,	// VCEQzv4f16
-    225U,	// VCEQzv4f32
-    3U,	// VCEQzv4i16
-    3U,	// VCEQzv4i32
-    225U,	// VCEQzv8f16
-    3U,	// VCEQzv8i16
-    3U,	// VCEQzv8i8
-    70705U,	// VCGEfd
-    70705U,	// VCGEfq
-    70705U,	// VCGEhd
-    70705U,	// VCGEhq
-    1112U,	// VCGEsv16i8
-    1112U,	// VCGEsv2i32
-    1112U,	// VCGEsv4i16
-    1112U,	// VCGEsv4i32
-    1112U,	// VCGEsv8i16
-    1112U,	// VCGEsv8i8
-    1112U,	// VCGEuv16i8
-    1112U,	// VCGEuv2i32
-    1112U,	// VCGEuv4i16
-    1112U,	// VCGEuv4i32
-    1112U,	// VCGEuv8i16
-    1112U,	// VCGEuv8i8
-    3U,	// VCGEzv16i8
-    225U,	// VCGEzv2f32
-    3U,	// VCGEzv2i32
-    225U,	// VCGEzv4f16
-    225U,	// VCGEzv4f32
-    3U,	// VCGEzv4i16
-    3U,	// VCGEzv4i32
-    225U,	// VCGEzv8f16
-    3U,	// VCGEzv8i16
-    3U,	// VCGEzv8i8
-    70705U,	// VCGTfd
-    70705U,	// VCGTfq
-    70705U,	// VCGThd
-    70705U,	// VCGThq
-    1112U,	// VCGTsv16i8
-    1112U,	// VCGTsv2i32
-    1112U,	// VCGTsv4i16
-    1112U,	// VCGTsv4i32
-    1112U,	// VCGTsv8i16
-    1112U,	// VCGTsv8i8
-    1112U,	// VCGTuv16i8
-    1112U,	// VCGTuv2i32
-    1112U,	// VCGTuv4i16
-    1112U,	// VCGTuv4i32
-    1112U,	// VCGTuv8i16
-    1112U,	// VCGTuv8i8
-    3U,	// VCGTzv16i8
-    225U,	// VCGTzv2f32
-    3U,	// VCGTzv2i32
-    225U,	// VCGTzv4f16
-    225U,	// VCGTzv4f32
-    3U,	// VCGTzv4i16
-    3U,	// VCGTzv4i32
-    225U,	// VCGTzv8f16
-    3U,	// VCGTzv8i16
-    3U,	// VCGTzv8i8
-    3U,	// VCLEzv16i8
-    225U,	// VCLEzv2f32
-    3U,	// VCLEzv2i32
-    225U,	// VCLEzv4f16
-    225U,	// VCLEzv4f32
-    3U,	// VCLEzv4i16
-    3U,	// VCLEzv4i32
-    225U,	// VCLEzv8f16
-    3U,	// VCLEzv8i16
-    3U,	// VCLEzv8i8
-    0U,	// VCLSv16i8
-    0U,	// VCLSv2i32
-    0U,	// VCLSv4i16
-    0U,	// VCLSv4i32
-    0U,	// VCLSv8i16
-    0U,	// VCLSv8i8
-    3U,	// VCLTzv16i8
-    225U,	// VCLTzv2f32
-    3U,	// VCLTzv2i32
-    225U,	// VCLTzv4f16
-    225U,	// VCLTzv4f32
-    3U,	// VCLTzv4i16
-    3U,	// VCLTzv4i32
-    225U,	// VCLTzv8f16
-    3U,	// VCLTzv8i16
-    3U,	// VCLTzv8i8
-    0U,	// VCLZv16i8
-    0U,	// VCLZv2i32
-    0U,	// VCLZv4i16
-    0U,	// VCLZv4i32
-    0U,	// VCLZv8i16
-    0U,	// VCLZv8i8
-    655384U,	// VCMLAv2f32
-    17276952U,	// VCMLAv2f32_indexed
-    655384U,	// VCMLAv4f16
-    17276952U,	// VCMLAv4f16_indexed
-    655384U,	// VCMLAv4f32
-    17276952U,	// VCMLAv4f32_indexed
-    655384U,	// VCMLAv8f16
-    17276952U,	// VCMLAv8f16_indexed
-    33U,	// VCMPD
-    33U,	// VCMPED
-    33U,	// VCMPEH
-    33U,	// VCMPES
+    3671552U,	// VBIFd
+    3671552U,	// VBIFq
+    3671552U,	// VBITd
+    3671552U,	// VBITq
+    3671552U,	// VBSLd
+    3671552U,	// VBSLq
+    0U,	// VBSPd
+    0U,	// VBSPq
+    11011584U,	// VCADDv2f32
+    11011584U,	// VCADDv4f16
+    11011584U,	// VCADDv4f32
+    11011584U,	// VCADDv8f16
+    0U,	// VCEQfd
+    0U,	// VCEQfq
+    0U,	// VCEQhd
+    0U,	// VCEQhq
+    0U,	// VCEQv16i8
+    0U,	// VCEQv2i32
+    0U,	// VCEQv4i16
+    0U,	// VCEQv4i32
+    0U,	// VCEQv8i16
+    0U,	// VCEQv8i8
+    245760U,	// VCEQzv16i8
+    245760U,	// VCEQzv2f32
+    245760U,	// VCEQzv2i32
+    245760U,	// VCEQzv4f16
+    245760U,	// VCEQzv4f32
+    245760U,	// VCEQzv4i16
+    245760U,	// VCEQzv4i32
+    245760U,	// VCEQzv8f16
+    245760U,	// VCEQzv8i16
+    245760U,	// VCEQzv8i8
+    0U,	// VCGEfd
+    0U,	// VCGEfq
+    0U,	// VCGEhd
+    0U,	// VCGEhq
+    0U,	// VCGEsv16i8
+    0U,	// VCGEsv2i32
+    0U,	// VCGEsv4i16
+    0U,	// VCGEsv4i32
+    0U,	// VCGEsv8i16
+    0U,	// VCGEsv8i8
+    0U,	// VCGEuv16i8
+    0U,	// VCGEuv2i32
+    0U,	// VCGEuv4i16
+    0U,	// VCGEuv4i32
+    0U,	// VCGEuv8i16
+    0U,	// VCGEuv8i8
+    245760U,	// VCGEzv16i8
+    245760U,	// VCGEzv2f32
+    245760U,	// VCGEzv2i32
+    245760U,	// VCGEzv4f16
+    245760U,	// VCGEzv4f32
+    245760U,	// VCGEzv4i16
+    245760U,	// VCGEzv4i32
+    245760U,	// VCGEzv8f16
+    245760U,	// VCGEzv8i16
+    245760U,	// VCGEzv8i8
+    0U,	// VCGTfd
+    0U,	// VCGTfq
+    0U,	// VCGThd
+    0U,	// VCGThq
+    0U,	// VCGTsv16i8
+    0U,	// VCGTsv2i32
+    0U,	// VCGTsv4i16
+    0U,	// VCGTsv4i32
+    0U,	// VCGTsv8i16
+    0U,	// VCGTsv8i8
+    0U,	// VCGTuv16i8
+    0U,	// VCGTuv2i32
+    0U,	// VCGTuv4i16
+    0U,	// VCGTuv4i32
+    0U,	// VCGTuv8i16
+    0U,	// VCGTuv8i8
+    245760U,	// VCGTzv16i8
+    245760U,	// VCGTzv2f32
+    245760U,	// VCGTzv2i32
+    245760U,	// VCGTzv4f16
+    245760U,	// VCGTzv4f32
+    245760U,	// VCGTzv4i16
+    245760U,	// VCGTzv4i32
+    245760U,	// VCGTzv8f16
+    245760U,	// VCGTzv8i16
+    245760U,	// VCGTzv8i8
+    245760U,	// VCLEzv16i8
+    245760U,	// VCLEzv2f32
+    245760U,	// VCLEzv2i32
+    245760U,	// VCLEzv4f16
+    245760U,	// VCLEzv4f32
+    245760U,	// VCLEzv4i16
+    245760U,	// VCLEzv4i32
+    245760U,	// VCLEzv8f16
+    245760U,	// VCLEzv8i16
+    245760U,	// VCLEzv8i8
+    16384U,	// VCLSv16i8
+    16384U,	// VCLSv2i32
+    16384U,	// VCLSv4i16
+    16384U,	// VCLSv4i32
+    16384U,	// VCLSv8i16
+    16384U,	// VCLSv8i8
+    245760U,	// VCLTzv16i8
+    245760U,	// VCLTzv2f32
+    245760U,	// VCLTzv2i32
+    245760U,	// VCLTzv4f16
+    245760U,	// VCLTzv4f32
+    245760U,	// VCLTzv4i16
+    245760U,	// VCLTzv4i32
+    245760U,	// VCLTzv8f16
+    245760U,	// VCLTzv8i16
+    245760U,	// VCLTzv8i8
+    16384U,	// VCLZv16i8
+    16384U,	// VCLZv2i32
+    16384U,	// VCLZv4i16
+    16384U,	// VCLZv4i32
+    16384U,	// VCLZv8i16
+    16384U,	// VCLZv8i8
+    11534720U,	// VCMLAv2f32
+    338755968U,	// VCMLAv2f32_indexed
+    11534720U,	// VCMLAv4f16
+    338755968U,	// VCMLAv4f16_indexed
+    11534720U,	// VCMLAv4f32
+    338755968U,	// VCMLAv4f32_indexed
+    11534720U,	// VCMLAv8f16
+    338755968U,	// VCMLAv8f16_indexed
+    526U,	// VCMPD
+    526U,	// VCMPED
+    16384U,	// VCMPEH
+    16384U,	// VCMPES
     0U,	// VCMPEZD
-    0U,	// VCMPEZH
-    0U,	// VCMPEZS
-    33U,	// VCMPH
-    33U,	// VCMPS
+    36U,	// VCMPEZH
+    36U,	// VCMPEZS
+    16384U,	// VCMPH
+    16384U,	// VCMPS
     0U,	// VCMPZD
-    0U,	// VCMPZH
-    0U,	// VCMPZS
-    1024U,	// VCNTd
-    1024U,	// VCNTq
-    0U,	// VCVTANSDf
-    0U,	// VCVTANSDh
-    0U,	// VCVTANSQf
-    0U,	// VCVTANSQh
-    0U,	// VCVTANUDf
-    0U,	// VCVTANUDh
-    0U,	// VCVTANUQf
-    0U,	// VCVTANUQh
-    0U,	// VCVTASD
-    0U,	// VCVTASH
-    0U,	// VCVTASS
-    0U,	// VCVTAUD
-    0U,	// VCVTAUH
-    0U,	// VCVTAUS
+    36U,	// VCMPZH
+    36U,	// VCMPZS
+    16384U,	// VCNTd
+    16384U,	// VCNTq
+    2U,	// VCVTANSDf
+    2U,	// VCVTANSDh
+    2U,	// VCVTANSQf
+    2U,	// VCVTANSQh
+    2U,	// VCVTANUDf
+    2U,	// VCVTANUDh
+    2U,	// VCVTANUQf
+    2U,	// VCVTANUQh
+    2U,	// VCVTASD
+    2U,	// VCVTASH
+    2U,	// VCVTASS
+    2U,	// VCVTAUD
+    2U,	// VCVTAUH
+    2U,	// VCVTAUS
     0U,	// VCVTBDH
     0U,	// VCVTBHD
     0U,	// VCVTBHS
-    0U,	// VCVTBSH
+    2U,	// VCVTBSH
     0U,	// VCVTDS
-    0U,	// VCVTMNSDf
-    0U,	// VCVTMNSDh
-    0U,	// VCVTMNSQf
-    0U,	// VCVTMNSQh
-    0U,	// VCVTMNUDf
-    0U,	// VCVTMNUDh
-    0U,	// VCVTMNUQf
-    0U,	// VCVTMNUQh
-    0U,	// VCVTMSD
-    0U,	// VCVTMSH
-    0U,	// VCVTMSS
-    0U,	// VCVTMUD
-    0U,	// VCVTMUH
-    0U,	// VCVTMUS
-    0U,	// VCVTNNSDf
-    0U,	// VCVTNNSDh
-    0U,	// VCVTNNSQf
-    0U,	// VCVTNNSQh
-    0U,	// VCVTNNUDf
-    0U,	// VCVTNNUDh
-    0U,	// VCVTNNUQf
-    0U,	// VCVTNNUQh
-    0U,	// VCVTNSD
-    0U,	// VCVTNSH
-    0U,	// VCVTNSS
-    0U,	// VCVTNUD
-    0U,	// VCVTNUH
-    0U,	// VCVTNUS
-    0U,	// VCVTPNSDf
-    0U,	// VCVTPNSDh
-    0U,	// VCVTPNSQf
-    0U,	// VCVTPNSQh
-    0U,	// VCVTPNUDf
-    0U,	// VCVTPNUDh
-    0U,	// VCVTPNUQf
-    0U,	// VCVTPNUQh
-    0U,	// VCVTPSD
-    0U,	// VCVTPSH
-    0U,	// VCVTPSS
-    0U,	// VCVTPUD
-    0U,	// VCVTPUH
-    0U,	// VCVTPUS
+    2U,	// VCVTMNSDf
+    2U,	// VCVTMNSDh
+    2U,	// VCVTMNSQf
+    2U,	// VCVTMNSQh
+    2U,	// VCVTMNUDf
+    2U,	// VCVTMNUDh
+    2U,	// VCVTMNUQf
+    2U,	// VCVTMNUQh
+    2U,	// VCVTMSD
+    2U,	// VCVTMSH
+    2U,	// VCVTMSS
+    2U,	// VCVTMUD
+    2U,	// VCVTMUH
+    2U,	// VCVTMUS
+    2U,	// VCVTNNSDf
+    2U,	// VCVTNNSDh
+    2U,	// VCVTNNSQf
+    2U,	// VCVTNNSQh
+    2U,	// VCVTNNUDf
+    2U,	// VCVTNNUDh
+    2U,	// VCVTNNUQf
+    2U,	// VCVTNNUQh
+    2U,	// VCVTNSD
+    2U,	// VCVTNSH
+    2U,	// VCVTNSS
+    2U,	// VCVTNUD
+    2U,	// VCVTNUH
+    2U,	// VCVTNUS
+    2U,	// VCVTPNSDf
+    2U,	// VCVTPNSDh
+    2U,	// VCVTPNSQf
+    2U,	// VCVTPNSQh
+    2U,	// VCVTPNUDf
+    2U,	// VCVTPNUDh
+    2U,	// VCVTPNUQf
+    2U,	// VCVTPNUQh
+    2U,	// VCVTPSD
+    2U,	// VCVTPSH
+    2U,	// VCVTPSS
+    2U,	// VCVTPUD
+    2U,	// VCVTPUH
+    2U,	// VCVTPUS
     0U,	// VCVTSD
     0U,	// VCVTTDH
     0U,	// VCVTTHD
     0U,	// VCVTTHS
-    0U,	// VCVTTSH
-    0U,	// VCVTf2h
+    2U,	// VCVTTSH
+    2U,	// VCVTf2h
     0U,	// VCVTf2sd
     0U,	// VCVTf2sq
     0U,	// VCVTf2ud
     0U,	// VCVTf2uq
-    35U,	// VCVTf2xsd
-    35U,	// VCVTf2xsq
-    35U,	// VCVTf2xud
-    35U,	// VCVTf2xuq
+    536U,	// VCVTf2xsd
+    536U,	// VCVTf2xsq
+    536U,	// VCVTf2xud
+    536U,	// VCVTf2xuq
     0U,	// VCVTh2f
     0U,	// VCVTh2sd
     0U,	// VCVTh2sq
     0U,	// VCVTh2ud
     0U,	// VCVTh2uq
-    35U,	// VCVTh2xsd
-    35U,	// VCVTh2xsq
-    35U,	// VCVTh2xud
-    35U,	// VCVTh2xuq
+    536U,	// VCVTh2xsd
+    536U,	// VCVTh2xsq
+    536U,	// VCVTh2xud
+    536U,	// VCVTh2xuq
     0U,	// VCVTs2fd
     0U,	// VCVTs2fq
     0U,	// VCVTs2hd
@@ -5012,1134 +7519,1198 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VCVTu2fq
     0U,	// VCVTu2hd
     0U,	// VCVTu2hq
-    35U,	// VCVTxs2fd
-    35U,	// VCVTxs2fq
-    35U,	// VCVTxs2hd
-    35U,	// VCVTxs2hq
-    35U,	// VCVTxu2fd
-    35U,	// VCVTxu2fq
-    35U,	// VCVTxu2hd
-    35U,	// VCVTxu2hq
-    70705U,	// VDIVD
-    70705U,	// VDIVH
-    70705U,	// VDIVS
-    1024U,	// VDUP16d
-    1024U,	// VDUP16q
-    1024U,	// VDUP32d
-    1024U,	// VDUP32q
-    1024U,	// VDUP8d
-    1024U,	// VDUP8q
-    9216U,	// VDUPLN16d
-    9216U,	// VDUPLN16q
-    9216U,	// VDUPLN32d
-    9216U,	// VDUPLN32q
-    9216U,	// VDUPLN8d
-    9216U,	// VDUPLN8q
+    536U,	// VCVTxs2fd
+    536U,	// VCVTxs2fq
+    536U,	// VCVTxs2hd
+    536U,	// VCVTxs2hq
+    536U,	// VCVTxu2fd
+    536U,	// VCVTxu2fq
+    536U,	// VCVTxu2hd
+    536U,	// VCVTxu2hq
+    2212622U,	// VDIVD
+    0U,	// VDIVH
+    0U,	// VDIVS
+    16384U,	// VDUP16d
+    16384U,	// VDUP16q
+    16384U,	// VDUP32d
+    16384U,	// VDUP32q
+    16384U,	// VDUP8d
+    16384U,	// VDUP8q
+    163840U,	// VDUPLN16d
+    163840U,	// VDUPLN16q
+    163840U,	// VDUPLN32d
+    163840U,	// VDUPLN32q
+    163840U,	// VDUPLN8d
+    163840U,	// VDUPLN8q
     0U,	// VEORd
     0U,	// VEORq
-    35651584U,	// VEXTd16
-    35651584U,	// VEXTd32
-    35651584U,	// VEXTd8
-    35651584U,	// VEXTq16
-    35651584U,	// VEXTq32
-    35651584U,	// VEXTq64
-    35651584U,	// VEXTq8
-    68659U,	// VFMAD
-    68659U,	// VFMAH
-    68659U,	// VFMAS
-    68659U,	// VFMAfd
-    68659U,	// VFMAfq
-    68659U,	// VFMAhd
-    68659U,	// VFMAhq
-    68659U,	// VFMSD
-    68659U,	// VFMSH
-    68659U,	// VFMSS
-    68659U,	// VFMSfd
-    68659U,	// VFMSfq
-    68659U,	// VFMShd
-    68659U,	// VFMShq
-    68659U,	// VFNMAD
-    68659U,	// VFNMAH
-    68659U,	// VFNMAS
-    68659U,	// VFNMSD
-    68659U,	// VFNMSH
-    68659U,	// VFNMSS
-    9216U,	// VGETLNi32
-    3U,	// VGETLNs16
-    3U,	// VGETLNs8
-    3U,	// VGETLNu16
-    3U,	// VGETLNu8
-    1112U,	// VHADDsv16i8
-    1112U,	// VHADDsv2i32
-    1112U,	// VHADDsv4i16
-    1112U,	// VHADDsv4i32
-    1112U,	// VHADDsv8i16
-    1112U,	// VHADDsv8i8
-    1112U,	// VHADDuv16i8
-    1112U,	// VHADDuv2i32
-    1112U,	// VHADDuv4i16
-    1112U,	// VHADDuv4i32
-    1112U,	// VHADDuv8i16
-    1112U,	// VHADDuv8i8
-    1112U,	// VHSUBsv16i8
-    1112U,	// VHSUBsv2i32
-    1112U,	// VHSUBsv4i16
-    1112U,	// VHSUBsv4i32
-    1112U,	// VHSUBsv8i16
-    1112U,	// VHSUBsv8i8
-    1112U,	// VHSUBuv16i8
-    1112U,	// VHSUBuv2i32
-    1112U,	// VHSUBuv4i16
-    1112U,	// VHSUBuv4i32
-    1112U,	// VHSUBuv8i16
-    1112U,	// VHSUBuv8i8
-    0U,	// VINSH
+    33554432U,	// VEXTd16
+    33554432U,	// VEXTd32
+    33554432U,	// VEXTd8
+    33554432U,	// VEXTq16
+    33554432U,	// VEXTq32
+    33554432U,	// VEXTq64
+    33554432U,	// VEXTq8
+    49944U,	// VFMAD
+    3671552U,	// VFMAH
+    17920U,	// VFMALD
+    263680U,	// VFMALDI
+    17920U,	// VFMALQ
+    263680U,	// VFMALQI
+    3671552U,	// VFMAS
+    3671552U,	// VFMAfd
+    3671552U,	// VFMAfq
+    3671552U,	// VFMAhd
+    3671552U,	// VFMAhq
+    49944U,	// VFMSD
+    3671552U,	// VFMSH
+    17920U,	// VFMSLD
+    263680U,	// VFMSLDI
+    17920U,	// VFMSLQ
+    263680U,	// VFMSLQI
+    3671552U,	// VFMSS
+    3671552U,	// VFMSfd
+    3671552U,	// VFMSfq
+    3671552U,	// VFMShd
+    3671552U,	// VFMShq
+    49944U,	// VFNMAD
+    3671552U,	// VFNMAH
+    3671552U,	// VFNMAS
+    49944U,	// VFNMSD
+    3671552U,	// VFNMSH
+    3671552U,	// VFNMSS
+    17920U,	// VFP_VMAXNMD
+    17920U,	// VFP_VMAXNMH
+    17920U,	// VFP_VMAXNMS
+    17920U,	// VFP_VMINNMD
+    17920U,	// VFP_VMINNMH
+    17920U,	// VFP_VMINNMS
+    163840U,	// VGETLNi32
+    163840U,	// VGETLNs16
+    163840U,	// VGETLNs8
+    163840U,	// VGETLNu16
+    163840U,	// VGETLNu8
+    0U,	// VHADDsv16i8
+    0U,	// VHADDsv2i32
+    0U,	// VHADDsv4i16
+    0U,	// VHADDsv4i32
+    0U,	// VHADDsv8i16
+    0U,	// VHADDsv8i8
+    0U,	// VHADDuv16i8
+    0U,	// VHADDuv2i32
+    0U,	// VHADDuv4i16
+    0U,	// VHADDuv4i32
+    0U,	// VHADDuv8i16
+    0U,	// VHADDuv8i8
+    0U,	// VHSUBsv16i8
+    0U,	// VHSUBsv2i32
+    0U,	// VHSUBsv4i16
+    0U,	// VHSUBsv4i32
+    0U,	// VHSUBsv8i16
+    0U,	// VHSUBsv8i8
+    0U,	// VHSUBuv16i8
+    0U,	// VHSUBuv2i32
+    0U,	// VHSUBuv4i16
+    0U,	// VHSUBuv4i32
+    0U,	// VHSUBuv8i16
+    0U,	// VHSUBuv8i8
+    2U,	// VINSH
     0U,	// VJCVT
-    32U,	// VLD1DUPd16
-    44U,	// VLD1DUPd16wb_fixed
-    10292U,	// VLD1DUPd16wb_register
-    32U,	// VLD1DUPd32
-    44U,	// VLD1DUPd32wb_fixed
-    10292U,	// VLD1DUPd32wb_register
-    32U,	// VLD1DUPd8
-    44U,	// VLD1DUPd8wb_fixed
-    10292U,	// VLD1DUPd8wb_register
-    32U,	// VLD1DUPq16
-    44U,	// VLD1DUPq16wb_fixed
-    10292U,	// VLD1DUPq16wb_register
-    32U,	// VLD1DUPq32
-    44U,	// VLD1DUPq32wb_fixed
-    10292U,	// VLD1DUPq32wb_register
-    32U,	// VLD1DUPq8
-    44U,	// VLD1DUPq8wb_fixed
-    10292U,	// VLD1DUPq8wb_register
-    699628U,	// VLD1LNd16
-    732404U,	// VLD1LNd16_UPD
-    699628U,	// VLD1LNd32
-    732404U,	// VLD1LNd32_UPD
-    699628U,	// VLD1LNd8
-    732404U,	// VLD1LNd8_UPD
+    518U,	// VLD1DUPd16
+    678U,	// VLD1DUPd16wb_fixed
+    2179878U,	// VLD1DUPd16wb_register
+    518U,	// VLD1DUPd32
+    678U,	// VLD1DUPd32wb_fixed
+    2179878U,	// VLD1DUPd32wb_register
+    518U,	// VLD1DUPd8
+    678U,	// VLD1DUPd8wb_fixed
+    2179878U,	// VLD1DUPd8wb_register
+    518U,	// VLD1DUPq16
+    678U,	// VLD1DUPq16wb_fixed
+    2179878U,	// VLD1DUPq16wb_register
+    518U,	// VLD1DUPq32
+    678U,	// VLD1DUPq32wb_fixed
+    2179878U,	// VLD1DUPq32wb_register
+    518U,	// VLD1DUPq8
+    678U,	// VLD1DUPq8wb_fixed
+    2179878U,	// VLD1DUPq8wb_register
+    12342568U,	// VLD1LNd16
+    12866984U,	// VLD1LNd16_UPD
+    12342568U,	// VLD1LNd32
+    12866984U,	// VLD1LNd32_UPD
+    12342568U,	// VLD1LNd8
+    12866984U,	// VLD1LNd8_UPD
     0U,	// VLD1LNq16Pseudo
     0U,	// VLD1LNq16Pseudo_UPD
     0U,	// VLD1LNq32Pseudo
     0U,	// VLD1LNq32Pseudo_UPD
     0U,	// VLD1LNq8Pseudo
     0U,	// VLD1LNq8Pseudo_UPD
-    32U,	// VLD1d16
-    32U,	// VLD1d16Q
+    518U,	// VLD1d16
+    518U,	// VLD1d16Q
     0U,	// VLD1d16QPseudo
-    44U,	// VLD1d16Qwb_fixed
-    10292U,	// VLD1d16Qwb_register
-    32U,	// VLD1d16T
+    0U,	// VLD1d16QPseudoWB_fixed
+    0U,	// VLD1d16QPseudoWB_register
+    678U,	// VLD1d16Qwb_fixed
+    2179878U,	// VLD1d16Qwb_register
+    518U,	// VLD1d16T
     0U,	// VLD1d16TPseudo
-    44U,	// VLD1d16Twb_fixed
-    10292U,	// VLD1d16Twb_register
-    44U,	// VLD1d16wb_fixed
-    10292U,	// VLD1d16wb_register
-    32U,	// VLD1d32
-    32U,	// VLD1d32Q
+    0U,	// VLD1d16TPseudoWB_fixed
+    0U,	// VLD1d16TPseudoWB_register
+    678U,	// VLD1d16Twb_fixed
+    2179878U,	// VLD1d16Twb_register
+    678U,	// VLD1d16wb_fixed
+    2179878U,	// VLD1d16wb_register
+    518U,	// VLD1d32
+    518U,	// VLD1d32Q
     0U,	// VLD1d32QPseudo
-    44U,	// VLD1d32Qwb_fixed
-    10292U,	// VLD1d32Qwb_register
-    32U,	// VLD1d32T
+    0U,	// VLD1d32QPseudoWB_fixed
+    0U,	// VLD1d32QPseudoWB_register
+    678U,	// VLD1d32Qwb_fixed
+    2179878U,	// VLD1d32Qwb_register
+    518U,	// VLD1d32T
     0U,	// VLD1d32TPseudo
-    44U,	// VLD1d32Twb_fixed
-    10292U,	// VLD1d32Twb_register
-    44U,	// VLD1d32wb_fixed
-    10292U,	// VLD1d32wb_register
-    32U,	// VLD1d64
-    32U,	// VLD1d64Q
+    0U,	// VLD1d32TPseudoWB_fixed
+    0U,	// VLD1d32TPseudoWB_register
+    678U,	// VLD1d32Twb_fixed
+    2179878U,	// VLD1d32Twb_register
+    678U,	// VLD1d32wb_fixed
+    2179878U,	// VLD1d32wb_register
+    518U,	// VLD1d64
+    518U,	// VLD1d64Q
     0U,	// VLD1d64QPseudo
     0U,	// VLD1d64QPseudoWB_fixed
     0U,	// VLD1d64QPseudoWB_register
-    44U,	// VLD1d64Qwb_fixed
-    10292U,	// VLD1d64Qwb_register
-    32U,	// VLD1d64T
+    678U,	// VLD1d64Qwb_fixed
+    2179878U,	// VLD1d64Qwb_register
+    518U,	// VLD1d64T
     0U,	// VLD1d64TPseudo
     0U,	// VLD1d64TPseudoWB_fixed
     0U,	// VLD1d64TPseudoWB_register
-    44U,	// VLD1d64Twb_fixed
-    10292U,	// VLD1d64Twb_register
-    44U,	// VLD1d64wb_fixed
-    10292U,	// VLD1d64wb_register
-    32U,	// VLD1d8
-    32U,	// VLD1d8Q
+    678U,	// VLD1d64Twb_fixed
+    2179878U,	// VLD1d64Twb_register
+    678U,	// VLD1d64wb_fixed
+    2179878U,	// VLD1d64wb_register
+    518U,	// VLD1d8
+    518U,	// VLD1d8Q
     0U,	// VLD1d8QPseudo
-    44U,	// VLD1d8Qwb_fixed
-    10292U,	// VLD1d8Qwb_register
-    32U,	// VLD1d8T
+    0U,	// VLD1d8QPseudoWB_fixed
+    0U,	// VLD1d8QPseudoWB_register
+    678U,	// VLD1d8Qwb_fixed
+    2179878U,	// VLD1d8Qwb_register
+    518U,	// VLD1d8T
     0U,	// VLD1d8TPseudo
-    44U,	// VLD1d8Twb_fixed
-    10292U,	// VLD1d8Twb_register
-    44U,	// VLD1d8wb_fixed
-    10292U,	// VLD1d8wb_register
-    32U,	// VLD1q16
+    0U,	// VLD1d8TPseudoWB_fixed
+    0U,	// VLD1d8TPseudoWB_register
+    678U,	// VLD1d8Twb_fixed
+    2179878U,	// VLD1d8Twb_register
+    678U,	// VLD1d8wb_fixed
+    2179878U,	// VLD1d8wb_register
+    518U,	// VLD1q16
     0U,	// VLD1q16HighQPseudo
+    0U,	// VLD1q16HighQPseudo_UPD
     0U,	// VLD1q16HighTPseudo
+    0U,	// VLD1q16HighTPseudo_UPD
     0U,	// VLD1q16LowQPseudo_UPD
     0U,	// VLD1q16LowTPseudo_UPD
-    44U,	// VLD1q16wb_fixed
-    10292U,	// VLD1q16wb_register
-    32U,	// VLD1q32
+    678U,	// VLD1q16wb_fixed
+    2179878U,	// VLD1q16wb_register
+    518U,	// VLD1q32
     0U,	// VLD1q32HighQPseudo
+    0U,	// VLD1q32HighQPseudo_UPD
     0U,	// VLD1q32HighTPseudo
+    0U,	// VLD1q32HighTPseudo_UPD
     0U,	// VLD1q32LowQPseudo_UPD
     0U,	// VLD1q32LowTPseudo_UPD
-    44U,	// VLD1q32wb_fixed
-    10292U,	// VLD1q32wb_register
-    32U,	// VLD1q64
+    678U,	// VLD1q32wb_fixed
+    2179878U,	// VLD1q32wb_register
+    518U,	// VLD1q64
     0U,	// VLD1q64HighQPseudo
+    0U,	// VLD1q64HighQPseudo_UPD
     0U,	// VLD1q64HighTPseudo
+    0U,	// VLD1q64HighTPseudo_UPD
     0U,	// VLD1q64LowQPseudo_UPD
     0U,	// VLD1q64LowTPseudo_UPD
-    44U,	// VLD1q64wb_fixed
-    10292U,	// VLD1q64wb_register
-    32U,	// VLD1q8
+    678U,	// VLD1q64wb_fixed
+    2179878U,	// VLD1q64wb_register
+    518U,	// VLD1q8
     0U,	// VLD1q8HighQPseudo
+    0U,	// VLD1q8HighQPseudo_UPD
     0U,	// VLD1q8HighTPseudo
+    0U,	// VLD1q8HighTPseudo_UPD
     0U,	// VLD1q8LowQPseudo_UPD
     0U,	// VLD1q8LowTPseudo_UPD
-    44U,	// VLD1q8wb_fixed
-    10292U,	// VLD1q8wb_register
-    32U,	// VLD2DUPd16
-    44U,	// VLD2DUPd16wb_fixed
-    10292U,	// VLD2DUPd16wb_register
-    32U,	// VLD2DUPd16x2
-    44U,	// VLD2DUPd16x2wb_fixed
-    10292U,	// VLD2DUPd16x2wb_register
-    32U,	// VLD2DUPd32
-    44U,	// VLD2DUPd32wb_fixed
-    10292U,	// VLD2DUPd32wb_register
-    32U,	// VLD2DUPd32x2
-    44U,	// VLD2DUPd32x2wb_fixed
-    10292U,	// VLD2DUPd32x2wb_register
-    32U,	// VLD2DUPd8
-    44U,	// VLD2DUPd8wb_fixed
-    10292U,	// VLD2DUPd8wb_register
-    32U,	// VLD2DUPd8x2
-    44U,	// VLD2DUPd8x2wb_fixed
-    10292U,	// VLD2DUPd8x2wb_register
+    678U,	// VLD1q8wb_fixed
+    2179878U,	// VLD1q8wb_register
+    518U,	// VLD2DUPd16
+    678U,	// VLD2DUPd16wb_fixed
+    2179878U,	// VLD2DUPd16wb_register
+    518U,	// VLD2DUPd16x2
+    678U,	// VLD2DUPd16x2wb_fixed
+    2179878U,	// VLD2DUPd16x2wb_register
+    518U,	// VLD2DUPd32
+    678U,	// VLD2DUPd32wb_fixed
+    2179878U,	// VLD2DUPd32wb_register
+    518U,	// VLD2DUPd32x2
+    678U,	// VLD2DUPd32x2wb_fixed
+    2179878U,	// VLD2DUPd32x2wb_register
+    518U,	// VLD2DUPd8
+    678U,	// VLD2DUPd8wb_fixed
+    2179878U,	// VLD2DUPd8wb_register
+    518U,	// VLD2DUPd8x2
+    678U,	// VLD2DUPd8x2wb_fixed
+    2179878U,	// VLD2DUPd8x2wb_register
     0U,	// VLD2DUPq16EvenPseudo
     0U,	// VLD2DUPq16OddPseudo
+    0U,	// VLD2DUPq16OddPseudoWB_fixed
+    0U,	// VLD2DUPq16OddPseudoWB_register
     0U,	// VLD2DUPq32EvenPseudo
     0U,	// VLD2DUPq32OddPseudo
+    0U,	// VLD2DUPq32OddPseudoWB_fixed
+    0U,	// VLD2DUPq32OddPseudoWB_register
     0U,	// VLD2DUPq8EvenPseudo
     0U,	// VLD2DUPq8OddPseudo
-    766196U,	// VLD2LNd16
+    0U,	// VLD2DUPq8OddPseudoWB_fixed
+    0U,	// VLD2DUPq8OddPseudoWB_register
+    13407656U,	// VLD2LNd16
     0U,	// VLD2LNd16Pseudo
     0U,	// VLD2LNd16Pseudo_UPD
-    799996U,	// VLD2LNd16_UPD
-    766196U,	// VLD2LNd32
+    13948456U,	// VLD2LNd16_UPD
+    13407656U,	// VLD2LNd32
     0U,	// VLD2LNd32Pseudo
     0U,	// VLD2LNd32Pseudo_UPD
-    799996U,	// VLD2LNd32_UPD
-    766196U,	// VLD2LNd8
+    13948456U,	// VLD2LNd32_UPD
+    13407656U,	// VLD2LNd8
     0U,	// VLD2LNd8Pseudo
     0U,	// VLD2LNd8Pseudo_UPD
-    799996U,	// VLD2LNd8_UPD
-    766196U,	// VLD2LNq16
+    13948456U,	// VLD2LNd8_UPD
+    13407656U,	// VLD2LNq16
     0U,	// VLD2LNq16Pseudo
     0U,	// VLD2LNq16Pseudo_UPD
-    799996U,	// VLD2LNq16_UPD
-    766196U,	// VLD2LNq32
+    13948456U,	// VLD2LNq16_UPD
+    13407656U,	// VLD2LNq32
     0U,	// VLD2LNq32Pseudo
     0U,	// VLD2LNq32Pseudo_UPD
-    799996U,	// VLD2LNq32_UPD
-    32U,	// VLD2b16
-    44U,	// VLD2b16wb_fixed
-    10292U,	// VLD2b16wb_register
-    32U,	// VLD2b32
-    44U,	// VLD2b32wb_fixed
-    10292U,	// VLD2b32wb_register
-    32U,	// VLD2b8
-    44U,	// VLD2b8wb_fixed
-    10292U,	// VLD2b8wb_register
-    32U,	// VLD2d16
-    44U,	// VLD2d16wb_fixed
-    10292U,	// VLD2d16wb_register
-    32U,	// VLD2d32
-    44U,	// VLD2d32wb_fixed
-    10292U,	// VLD2d32wb_register
-    32U,	// VLD2d8
-    44U,	// VLD2d8wb_fixed
-    10292U,	// VLD2d8wb_register
-    32U,	// VLD2q16
+    13948456U,	// VLD2LNq32_UPD
+    518U,	// VLD2b16
+    678U,	// VLD2b16wb_fixed
+    2179878U,	// VLD2b16wb_register
+    518U,	// VLD2b32
+    678U,	// VLD2b32wb_fixed
+    2179878U,	// VLD2b32wb_register
+    518U,	// VLD2b8
+    678U,	// VLD2b8wb_fixed
+    2179878U,	// VLD2b8wb_register
+    518U,	// VLD2d16
+    678U,	// VLD2d16wb_fixed
+    2179878U,	// VLD2d16wb_register
+    518U,	// VLD2d32
+    678U,	// VLD2d32wb_fixed
+    2179878U,	// VLD2d32wb_register
+    518U,	// VLD2d8
+    678U,	// VLD2d8wb_fixed
+    2179878U,	// VLD2d8wb_register
+    518U,	// VLD2q16
     0U,	// VLD2q16Pseudo
     0U,	// VLD2q16PseudoWB_fixed
     0U,	// VLD2q16PseudoWB_register
-    44U,	// VLD2q16wb_fixed
-    10292U,	// VLD2q16wb_register
-    32U,	// VLD2q32
+    678U,	// VLD2q16wb_fixed
+    2179878U,	// VLD2q16wb_register
+    518U,	// VLD2q32
     0U,	// VLD2q32Pseudo
     0U,	// VLD2q32PseudoWB_fixed
     0U,	// VLD2q32PseudoWB_register
-    44U,	// VLD2q32wb_fixed
-    10292U,	// VLD2q32wb_register
-    32U,	// VLD2q8
+    678U,	// VLD2q32wb_fixed
+    2179878U,	// VLD2q32wb_register
+    518U,	// VLD2q8
     0U,	// VLD2q8Pseudo
     0U,	// VLD2q8PseudoWB_fixed
     0U,	// VLD2q8PseudoWB_register
-    44U,	// VLD2q8wb_fixed
-    10292U,	// VLD2q8wb_register
-    14596U,	// VLD3DUPd16
+    678U,	// VLD2q8wb_fixed
+    2179878U,	// VLD2q8wb_register
+    333482U,	// VLD3DUPd16
     0U,	// VLD3DUPd16Pseudo
     0U,	// VLD3DUPd16Pseudo_UPD
-    834820U,	// VLD3DUPd16_UPD
-    14596U,	// VLD3DUPd32
+    14505642U,	// VLD3DUPd16_UPD
+    333482U,	// VLD3DUPd32
     0U,	// VLD3DUPd32Pseudo
     0U,	// VLD3DUPd32Pseudo_UPD
-    834820U,	// VLD3DUPd32_UPD
-    14596U,	// VLD3DUPd8
+    14505642U,	// VLD3DUPd32_UPD
+    333482U,	// VLD3DUPd8
     0U,	// VLD3DUPd8Pseudo
     0U,	// VLD3DUPd8Pseudo_UPD
-    834820U,	// VLD3DUPd8_UPD
-    14596U,	// VLD3DUPq16
+    14505642U,	// VLD3DUPd8_UPD
+    333482U,	// VLD3DUPq16
     0U,	// VLD3DUPq16EvenPseudo
     0U,	// VLD3DUPq16OddPseudo
-    834820U,	// VLD3DUPq16_UPD
-    14596U,	// VLD3DUPq32
+    0U,	// VLD3DUPq16OddPseudo_UPD
+    14505642U,	// VLD3DUPq16_UPD
+    333482U,	// VLD3DUPq32
     0U,	// VLD3DUPq32EvenPseudo
     0U,	// VLD3DUPq32OddPseudo
-    834820U,	// VLD3DUPq32_UPD
-    14596U,	// VLD3DUPq8
+    0U,	// VLD3DUPq32OddPseudo_UPD
+    14505642U,	// VLD3DUPq32_UPD
+    333482U,	// VLD3DUPq8
     0U,	// VLD3DUPq8EvenPseudo
     0U,	// VLD3DUPq8OddPseudo
-    834820U,	// VLD3DUPq8_UPD
-    865532U,	// VLD3LNd16
+    0U,	// VLD3DUPq8OddPseudo_UPD
+    14505642U,	// VLD3DUPq8_UPD
+    14997032U,	// VLD3LNd16
     0U,	// VLD3LNd16Pseudo
     0U,	// VLD3LNd16Pseudo_UPD
-    896268U,	// VLD3LNd16_UPD
-    865532U,	// VLD3LNd32
+    15488808U,	// VLD3LNd16_UPD
+    14997032U,	// VLD3LNd32
     0U,	// VLD3LNd32Pseudo
     0U,	// VLD3LNd32Pseudo_UPD
-    896268U,	// VLD3LNd32_UPD
-    865532U,	// VLD3LNd8
+    15488808U,	// VLD3LNd32_UPD
+    14997032U,	// VLD3LNd8
     0U,	// VLD3LNd8Pseudo
     0U,	// VLD3LNd8Pseudo_UPD
-    896268U,	// VLD3LNd8_UPD
-    865532U,	// VLD3LNq16
+    15488808U,	// VLD3LNd8_UPD
+    14997032U,	// VLD3LNq16
     0U,	// VLD3LNq16Pseudo
     0U,	// VLD3LNq16Pseudo_UPD
-    896268U,	// VLD3LNq16_UPD
-    865532U,	// VLD3LNq32
+    15488808U,	// VLD3LNq16_UPD
+    14997032U,	// VLD3LNq32
     0U,	// VLD3LNq32Pseudo
     0U,	// VLD3LNq32Pseudo_UPD
-    896268U,	// VLD3LNq32_UPD
-    119537664U,	// VLD3d16
+    15488808U,	// VLD3LNq32_UPD
+    369098752U,	// VLD3d16
     0U,	// VLD3d16Pseudo
     0U,	// VLD3d16Pseudo_UPD
-    153092096U,	// VLD3d16_UPD
-    119537664U,	// VLD3d32
+    369098752U,	// VLD3d16_UPD
+    369098752U,	// VLD3d32
     0U,	// VLD3d32Pseudo
     0U,	// VLD3d32Pseudo_UPD
-    153092096U,	// VLD3d32_UPD
-    119537664U,	// VLD3d8
+    369098752U,	// VLD3d32_UPD
+    369098752U,	// VLD3d8
     0U,	// VLD3d8Pseudo
     0U,	// VLD3d8Pseudo_UPD
-    153092096U,	// VLD3d8_UPD
-    119537664U,	// VLD3q16
+    369098752U,	// VLD3d8_UPD
+    369098752U,	// VLD3q16
     0U,	// VLD3q16Pseudo_UPD
-    153092096U,	// VLD3q16_UPD
+    369098752U,	// VLD3q16_UPD
     0U,	// VLD3q16oddPseudo
     0U,	// VLD3q16oddPseudo_UPD
-    119537664U,	// VLD3q32
+    369098752U,	// VLD3q32
     0U,	// VLD3q32Pseudo_UPD
-    153092096U,	// VLD3q32_UPD
+    369098752U,	// VLD3q32_UPD
     0U,	// VLD3q32oddPseudo
     0U,	// VLD3q32oddPseudo_UPD
-    119537664U,	// VLD3q8
+    369098752U,	// VLD3q8
     0U,	// VLD3q8Pseudo_UPD
-    153092096U,	// VLD3q8_UPD
+    369098752U,	// VLD3q8_UPD
     0U,	// VLD3q8oddPseudo
     0U,	// VLD3q8oddPseudo_UPD
-    81172U,	// VLD4DUPd16
+    2447274U,	// VLD4DUPd16
     0U,	// VLD4DUPd16Pseudo
     0U,	// VLD4DUPd16Pseudo_UPD
-    16660U,	// VLD4DUPd16_UPD
-    81172U,	// VLD4DUPd32
+    366506U,	// VLD4DUPd16_UPD
+    2447274U,	// VLD4DUPd32
     0U,	// VLD4DUPd32Pseudo
     0U,	// VLD4DUPd32Pseudo_UPD
-    16660U,	// VLD4DUPd32_UPD
-    81172U,	// VLD4DUPd8
+    366506U,	// VLD4DUPd32_UPD
+    2447274U,	// VLD4DUPd8
     0U,	// VLD4DUPd8Pseudo
     0U,	// VLD4DUPd8Pseudo_UPD
-    16660U,	// VLD4DUPd8_UPD
-    81172U,	// VLD4DUPq16
+    366506U,	// VLD4DUPd8_UPD
+    2447274U,	// VLD4DUPq16
     0U,	// VLD4DUPq16EvenPseudo
     0U,	// VLD4DUPq16OddPseudo
-    16660U,	// VLD4DUPq16_UPD
-    81172U,	// VLD4DUPq32
+    0U,	// VLD4DUPq16OddPseudo_UPD
+    366506U,	// VLD4DUPq16_UPD
+    2447274U,	// VLD4DUPq32
     0U,	// VLD4DUPq32EvenPseudo
     0U,	// VLD4DUPq32OddPseudo
-    16660U,	// VLD4DUPq32_UPD
-    81172U,	// VLD4DUPq8
+    0U,	// VLD4DUPq32OddPseudo_UPD
+    366506U,	// VLD4DUPq32_UPD
+    2447274U,	// VLD4DUPq8
     0U,	// VLD4DUPq8EvenPseudo
     0U,	// VLD4DUPq8OddPseudo
-    16660U,	// VLD4DUPq8_UPD
-    189346060U,	// VLD4LNd16
+    0U,	// VLD4DUPq8OddPseudo_UPD
+    366506U,	// VLD4DUPq8_UPD
+    406624040U,	// VLD4LNd16
     0U,	// VLD4LNd16Pseudo
     0U,	// VLD4LNd16Pseudo_UPD
-    284U,	// VLD4LNd16_UPD
-    189346060U,	// VLD4LNd32
+    6184U,	// VLD4LNd16_UPD
+    406624040U,	// VLD4LNd32
     0U,	// VLD4LNd32Pseudo
     0U,	// VLD4LNd32Pseudo_UPD
-    284U,	// VLD4LNd32_UPD
-    189346060U,	// VLD4LNd8
+    6184U,	// VLD4LNd32_UPD
+    406624040U,	// VLD4LNd8
     0U,	// VLD4LNd8Pseudo
     0U,	// VLD4LNd8Pseudo_UPD
-    284U,	// VLD4LNd8_UPD
-    189346060U,	// VLD4LNq16
+    6184U,	// VLD4LNd8_UPD
+    406624040U,	// VLD4LNq16
     0U,	// VLD4LNq16Pseudo
     0U,	// VLD4LNq16Pseudo_UPD
-    284U,	// VLD4LNq16_UPD
-    189346060U,	// VLD4LNq32
+    6184U,	// VLD4LNq16_UPD
+    406624040U,	// VLD4LNq32
     0U,	// VLD4LNq32Pseudo
     0U,	// VLD4LNq32Pseudo_UPD
-    284U,	// VLD4LNq32_UPD
-    572522496U,	// VLD4d16
+    6184U,	// VLD4LNq32_UPD
+    33554432U,	// VLD4d16
     0U,	// VLD4d16Pseudo
     0U,	// VLD4d16Pseudo_UPD
-    1646264320U,	// VLD4d16_UPD
-    572522496U,	// VLD4d32
+    33554432U,	// VLD4d16_UPD
+    33554432U,	// VLD4d32
     0U,	// VLD4d32Pseudo
     0U,	// VLD4d32Pseudo_UPD
-    1646264320U,	// VLD4d32_UPD
-    572522496U,	// VLD4d8
+    33554432U,	// VLD4d32_UPD
+    33554432U,	// VLD4d8
     0U,	// VLD4d8Pseudo
     0U,	// VLD4d8Pseudo_UPD
-    1646264320U,	// VLD4d8_UPD
-    572522496U,	// VLD4q16
+    33554432U,	// VLD4d8_UPD
+    33554432U,	// VLD4q16
     0U,	// VLD4q16Pseudo_UPD
-    1646264320U,	// VLD4q16_UPD
+    33554432U,	// VLD4q16_UPD
     0U,	// VLD4q16oddPseudo
     0U,	// VLD4q16oddPseudo_UPD
-    572522496U,	// VLD4q32
+    33554432U,	// VLD4q32
     0U,	// VLD4q32Pseudo_UPD
-    1646264320U,	// VLD4q32_UPD
+    33554432U,	// VLD4q32_UPD
     0U,	// VLD4q32oddPseudo
     0U,	// VLD4q32oddPseudo_UPD
-    572522496U,	// VLD4q8
+    33554432U,	// VLD4q8
     0U,	// VLD4q8Pseudo_UPD
-    1646264320U,	// VLD4q8_UPD
+    33554432U,	// VLD4q8_UPD
     0U,	// VLD4q8oddPseudo
     0U,	// VLD4q8oddPseudo_UPD
-    33U,	// VLDMDDB_UPD
-    1136U,	// VLDMDIA
-    33U,	// VLDMDIA_UPD
+    530U,	// VLDMDDB_UPD
+    18560U,	// VLDMDIA
+    530U,	// VLDMDIA_UPD
     0U,	// VLDMQIA
-    33U,	// VLDMSDB_UPD
-    1136U,	// VLDMSIA
-    33U,	// VLDMSIA_UPD
-    288U,	// VLDRD
-    296U,	// VLDRH
-    288U,	// VLDRS
-    0U,	// VLLDM
-    0U,	// VLSTM
-    1112U,	// VMAXNMD
-    1112U,	// VMAXNMH
-    1112U,	// VMAXNMNDf
-    1112U,	// VMAXNMNDh
-    1112U,	// VMAXNMNQf
-    1112U,	// VMAXNMNQh
-    1112U,	// VMAXNMS
-    70705U,	// VMAXfd
-    70705U,	// VMAXfq
-    70705U,	// VMAXhd
-    70705U,	// VMAXhq
-    1112U,	// VMAXsv16i8
-    1112U,	// VMAXsv2i32
-    1112U,	// VMAXsv4i16
-    1112U,	// VMAXsv4i32
-    1112U,	// VMAXsv8i16
-    1112U,	// VMAXsv8i8
-    1112U,	// VMAXuv16i8
-    1112U,	// VMAXuv2i32
-    1112U,	// VMAXuv4i16
-    1112U,	// VMAXuv4i32
-    1112U,	// VMAXuv8i16
-    1112U,	// VMAXuv8i8
-    1112U,	// VMINNMD
-    1112U,	// VMINNMH
-    1112U,	// VMINNMNDf
-    1112U,	// VMINNMNDh
-    1112U,	// VMINNMNQf
-    1112U,	// VMINNMNQh
-    1112U,	// VMINNMS
-    70705U,	// VMINfd
-    70705U,	// VMINfq
-    70705U,	// VMINhd
-    70705U,	// VMINhq
-    1112U,	// VMINsv16i8
-    1112U,	// VMINsv2i32
-    1112U,	// VMINsv4i16
-    1112U,	// VMINsv4i32
-    1112U,	// VMINsv8i16
-    1112U,	// VMINsv8i8
-    1112U,	// VMINuv16i8
-    1112U,	// VMINuv2i32
-    1112U,	// VMINuv4i16
-    1112U,	// VMINuv4i32
-    1112U,	// VMINuv8i16
-    1112U,	// VMINuv8i8
-    68659U,	// VMLAD
-    68659U,	// VMLAH
-    73752U,	// VMLALslsv2i32
-    73752U,	// VMLALslsv4i16
-    73752U,	// VMLALsluv2i32
-    73752U,	// VMLALsluv4i16
-    1048U,	// VMLALsv2i64
-    1048U,	// VMLALsv4i32
-    1048U,	// VMLALsv8i16
-    1048U,	// VMLALuv2i64
-    1048U,	// VMLALuv4i32
-    1048U,	// VMLALuv8i16
-    68659U,	// VMLAS
-    68659U,	// VMLAfd
-    68659U,	// VMLAfq
-    68659U,	// VMLAhd
-    68659U,	// VMLAhq
-    920627U,	// VMLAslfd
-    920627U,	// VMLAslfq
-    920627U,	// VMLAslhd
-    920627U,	// VMLAslhq
-    73752U,	// VMLAslv2i32
-    73752U,	// VMLAslv4i16
-    73752U,	// VMLAslv4i32
-    73752U,	// VMLAslv8i16
-    1048U,	// VMLAv16i8
-    1048U,	// VMLAv2i32
-    1048U,	// VMLAv4i16
-    1048U,	// VMLAv4i32
-    1048U,	// VMLAv8i16
-    1048U,	// VMLAv8i8
-    68659U,	// VMLSD
-    68659U,	// VMLSH
-    73752U,	// VMLSLslsv2i32
-    73752U,	// VMLSLslsv4i16
-    73752U,	// VMLSLsluv2i32
-    73752U,	// VMLSLsluv4i16
-    1048U,	// VMLSLsv2i64
-    1048U,	// VMLSLsv4i32
-    1048U,	// VMLSLsv8i16
-    1048U,	// VMLSLuv2i64
-    1048U,	// VMLSLuv4i32
-    1048U,	// VMLSLuv8i16
-    68659U,	// VMLSS
-    68659U,	// VMLSfd
-    68659U,	// VMLSfq
-    68659U,	// VMLShd
-    68659U,	// VMLShq
-    920627U,	// VMLSslfd
-    920627U,	// VMLSslfq
-    920627U,	// VMLSslhd
-    920627U,	// VMLSslhq
-    73752U,	// VMLSslv2i32
-    73752U,	// VMLSslv4i16
-    73752U,	// VMLSslv4i32
-    73752U,	// VMLSslv8i16
-    1048U,	// VMLSv16i8
-    1048U,	// VMLSv2i32
-    1048U,	// VMLSv4i16
-    1048U,	// VMLSv4i32
-    1048U,	// VMLSv8i16
-    1048U,	// VMLSv8i8
-    33U,	// VMOVD
+    530U,	// VLDMSDB_UPD
+    18560U,	// VLDMSIA
+    530U,	// VLDMSIA_UPD
+    6272U,	// VLDRD
+    6400U,	// VLDRH
+    6272U,	// VLDRS
+    0U,	// VLDR_FPCXTNS_off
+    44U,	// VLDR_FPCXTNS_post
+    0U,	// VLDR_FPCXTNS_pre
+    0U,	// VLDR_FPCXTS_off
+    44U,	// VLDR_FPCXTS_post
+    0U,	// VLDR_FPCXTS_pre
+    0U,	// VLDR_FPSCR_NZCVQC_off
+    44U,	// VLDR_FPSCR_NZCVQC_post
+    0U,	// VLDR_FPSCR_NZCVQC_pre
+    0U,	// VLDR_FPSCR_off
+    44U,	// VLDR_FPSCR_post
+    0U,	// VLDR_FPSCR_pre
+    0U,	// VLDR_P0_off
+    46U,	// VLDR_P0_post
+    0U,	// VLDR_P0_pre
+    0U,	// VLDR_VPR_off
+    44U,	// VLDR_VPR_post
+    0U,	// VLDR_VPR_pre
+    2U,	// VLLDM
+    2U,	// VLSTM
+    0U,	// VMAXfd
+    0U,	// VMAXfq
+    0U,	// VMAXhd
+    0U,	// VMAXhq
+    0U,	// VMAXsv16i8
+    0U,	// VMAXsv2i32
+    0U,	// VMAXsv4i16
+    0U,	// VMAXsv4i32
+    0U,	// VMAXsv8i16
+    0U,	// VMAXsv8i8
+    0U,	// VMAXuv16i8
+    0U,	// VMAXuv2i32
+    0U,	// VMAXuv4i16
+    0U,	// VMAXuv4i32
+    0U,	// VMAXuv8i16
+    0U,	// VMAXuv8i8
+    0U,	// VMINfd
+    0U,	// VMINfq
+    0U,	// VMINhd
+    0U,	// VMINhq
+    0U,	// VMINsv16i8
+    0U,	// VMINsv2i32
+    0U,	// VMINsv4i16
+    0U,	// VMINsv4i32
+    0U,	// VMINsv8i16
+    0U,	// VMINsv8i8
+    0U,	// VMINuv16i8
+    0U,	// VMINuv2i32
+    0U,	// VMINuv4i16
+    0U,	// VMINuv4i32
+    0U,	// VMINuv8i16
+    0U,	// VMINuv8i8
+    49944U,	// VMLAD
+    3671552U,	// VMLAH
+    439879168U,	// VMLALslsv2i32
+    439879168U,	// VMLALslsv4i16
+    439879168U,	// VMLALsluv2i32
+    439879168U,	// VMLALsluv4i16
+    3671552U,	// VMLALsv2i64
+    3671552U,	// VMLALsv4i32
+    3671552U,	// VMLALsv8i16
+    3671552U,	// VMLALuv2i64
+    3671552U,	// VMLALuv4i32
+    3671552U,	// VMLALuv8i16
+    3671552U,	// VMLAS
+    3671552U,	// VMLAfd
+    3671552U,	// VMLAfq
+    3671552U,	// VMLAhd
+    3671552U,	// VMLAhq
+    439879168U,	// VMLAslfd
+    439879168U,	// VMLAslfq
+    439879168U,	// VMLAslhd
+    439879168U,	// VMLAslhq
+    439879168U,	// VMLAslv2i32
+    439879168U,	// VMLAslv4i16
+    439879168U,	// VMLAslv4i32
+    439879168U,	// VMLAslv8i16
+    3671552U,	// VMLAv16i8
+    3671552U,	// VMLAv2i32
+    3671552U,	// VMLAv4i16
+    3671552U,	// VMLAv4i32
+    3671552U,	// VMLAv8i16
+    3671552U,	// VMLAv8i8
+    49944U,	// VMLSD
+    3671552U,	// VMLSH
+    439879168U,	// VMLSLslsv2i32
+    439879168U,	// VMLSLslsv4i16
+    439879168U,	// VMLSLsluv2i32
+    439879168U,	// VMLSLsluv4i16
+    3671552U,	// VMLSLsv2i64
+    3671552U,	// VMLSLsv4i32
+    3671552U,	// VMLSLsv8i16
+    3671552U,	// VMLSLuv2i64
+    3671552U,	// VMLSLuv4i32
+    3671552U,	// VMLSLuv8i16
+    3671552U,	// VMLSS
+    3671552U,	// VMLSfd
+    3671552U,	// VMLSfq
+    3671552U,	// VMLShd
+    3671552U,	// VMLShq
+    439879168U,	// VMLSslfd
+    439879168U,	// VMLSslfq
+    439879168U,	// VMLSslhd
+    439879168U,	// VMLSslhq
+    439879168U,	// VMLSslv2i32
+    439879168U,	// VMLSslv4i16
+    439879168U,	// VMLSslv4i32
+    439879168U,	// VMLSslv8i16
+    3671552U,	// VMLSv16i8
+    3671552U,	// VMLSv2i32
+    3671552U,	// VMLSv4i16
+    3671552U,	// VMLSv4i32
+    3671552U,	// VMLSv8i16
+    3671552U,	// VMLSv8i8
+    16768U,	// VMMLA
+    526U,	// VMOVD
     0U,	// VMOVDRR
-    0U,	// VMOVH
-    33U,	// VMOVHR
-    0U,	// VMOVLsv2i64
-    0U,	// VMOVLsv4i32
-    0U,	// VMOVLsv8i16
-    0U,	// VMOVLuv2i64
-    0U,	// VMOVLuv4i32
-    0U,	// VMOVLuv8i16
-    0U,	// VMOVNv2i32
-    0U,	// VMOVNv4i16
-    0U,	// VMOVNv8i8
-    33U,	// VMOVRH
+    2U,	// VMOVH
+    16384U,	// VMOVHR
+    16384U,	// VMOVLsv2i64
+    16384U,	// VMOVLsv4i32
+    16384U,	// VMOVLsv8i16
+    16384U,	// VMOVLuv2i64
+    16384U,	// VMOVLuv4i32
+    16384U,	// VMOVLuv8i16
+    2U,	// VMOVNv2i32
+    16384U,	// VMOVNv4i16
+    16384U,	// VMOVNv8i8
+    16384U,	// VMOVRH
     0U,	// VMOVRRD
-    35651584U,	// VMOVRRS
-    1024U,	// VMOVRS
-    33U,	// VMOVS
-    1024U,	// VMOVSR
-    35651584U,	// VMOVSRR
-    0U,	// VMOVv16i8
+    33554432U,	// VMOVRRS
+    16384U,	// VMOVRS
+    16384U,	// VMOVS
+    16384U,	// VMOVSR
+    33554432U,	// VMOVSRR
+    4864U,	// VMOVv16i8
     0U,	// VMOVv1i64
-    1U,	// VMOVv2f32
-    0U,	// VMOVv2i32
+    2048U,	// VMOVv2f32
+    4864U,	// VMOVv2i32
     0U,	// VMOVv2i64
-    1U,	// VMOVv4f32
-    0U,	// VMOVv4i16
-    0U,	// VMOVv4i32
-    0U,	// VMOVv8i16
-    0U,	// VMOVv8i8
-    4U,	// VMRS
-    5U,	// VMRS_FPEXC
-    5U,	// VMRS_FPINST
-    5U,	// VMRS_FPINST2
-    5U,	// VMRS_FPSID
-    6U,	// VMRS_MVFR0
-    6U,	// VMRS_MVFR1
-    6U,	// VMRS_MVFR2
-    0U,	// VMSR
+    2048U,	// VMOVv4f32
+    4864U,	// VMOVv4i16
+    4864U,	// VMOVv4i32
+    4864U,	// VMOVv8i16
+    4864U,	// VMOVv8i8
+    48U,	// VMRS
+    50U,	// VMRS_FPCXTNS
+    52U,	// VMRS_FPCXTS
+    54U,	// VMRS_FPEXC
+    56U,	// VMRS_FPINST
+    58U,	// VMRS_FPINST2
+    60U,	// VMRS_FPSCR_NZCVQC
+    62U,	// VMRS_FPSID
+    64U,	// VMRS_MVFR0
+    66U,	// VMRS_MVFR1
+    68U,	// VMRS_MVFR2
+    70U,	// VMRS_P0
+    72U,	// VMRS_VPR
+    2U,	// VMSR
+    2U,	// VMSR_FPCXTNS
+    2U,	// VMSR_FPCXTS
     0U,	// VMSR_FPEXC
     0U,	// VMSR_FPINST
     0U,	// VMSR_FPINST2
+    2U,	// VMSR_FPSCR_NZCVQC
     0U,	// VMSR_FPSID
-    70705U,	// VMULD
-    70705U,	// VMULH
-    1112U,	// VMULLp64
+    2U,	// VMSR_P0
+    2U,	// VMSR_VPR
+    2212622U,	// VMULD
+    0U,	// VMULH
+    17920U,	// VMULLp64
     0U,	// VMULLp8
-    17496U,	// VMULLslsv2i32
-    17496U,	// VMULLslsv4i16
-    17496U,	// VMULLsluv2i32
-    17496U,	// VMULLsluv4i16
-    1112U,	// VMULLsv2i64
-    1112U,	// VMULLsv4i32
-    1112U,	// VMULLsv8i16
-    1112U,	// VMULLuv2i64
-    1112U,	// VMULLuv4i32
-    1112U,	// VMULLuv8i16
-    70705U,	// VMULS
-    70705U,	// VMULfd
-    70705U,	// VMULfq
-    70705U,	// VMULhd
-    70705U,	// VMULhq
+    167772160U,	// VMULLslsv2i32
+    167772160U,	// VMULLslsv4i16
+    167772160U,	// VMULLsluv2i32
+    167772160U,	// VMULLsluv4i16
+    0U,	// VMULLsv2i64
+    0U,	// VMULLsv4i32
+    0U,	// VMULLsv8i16
+    0U,	// VMULLuv2i64
+    0U,	// VMULLuv4i32
+    0U,	// VMULLuv8i16
+    0U,	// VMULS
+    0U,	// VMULfd
+    0U,	// VMULfq
+    0U,	// VMULhd
+    0U,	// VMULhq
     0U,	// VMULpd
     0U,	// VMULpq
-    955441U,	// VMULslfd
-    955441U,	// VMULslfq
-    955441U,	// VMULslhd
-    955441U,	// VMULslhq
-    17496U,	// VMULslv2i32
-    17496U,	// VMULslv4i16
-    17496U,	// VMULslv4i32
-    17496U,	// VMULslv8i16
-    1112U,	// VMULv16i8
-    1112U,	// VMULv2i32
-    1112U,	// VMULv4i16
-    1112U,	// VMULv4i32
-    1112U,	// VMULv8i16
-    1112U,	// VMULv8i8
-    1024U,	// VMVNd
-    1024U,	// VMVNq
-    0U,	// VMVNv2i32
-    0U,	// VMVNv4i16
-    0U,	// VMVNv4i32
-    0U,	// VMVNv8i16
-    33U,	// VNEGD
-    33U,	// VNEGH
-    33U,	// VNEGS
-    33U,	// VNEGf32q
-    33U,	// VNEGfd
-    33U,	// VNEGhd
-    33U,	// VNEGhq
-    0U,	// VNEGs16d
-    0U,	// VNEGs16q
-    0U,	// VNEGs32d
-    0U,	// VNEGs32q
-    0U,	// VNEGs8d
-    0U,	// VNEGs8q
-    68659U,	// VNMLAD
-    68659U,	// VNMLAH
-    68659U,	// VNMLAS
-    68659U,	// VNMLSD
-    68659U,	// VNMLSH
-    68659U,	// VNMLSS
-    70705U,	// VNMULD
-    70705U,	// VNMULH
-    70705U,	// VNMULS
+    167772160U,	// VMULslfd
+    167772160U,	// VMULslfq
+    167772160U,	// VMULslhd
+    167772160U,	// VMULslhq
+    167772160U,	// VMULslv2i32
+    167772160U,	// VMULslv4i16
+    167772160U,	// VMULslv4i32
+    167772160U,	// VMULslv8i16
+    0U,	// VMULv16i8
+    0U,	// VMULv2i32
+    0U,	// VMULv4i16
+    0U,	// VMULv4i32
+    0U,	// VMULv8i16
+    0U,	// VMULv8i8
+    16384U,	// VMVNd
+    16384U,	// VMVNq
+    4864U,	// VMVNv2i32
+    4864U,	// VMVNv4i16
+    4864U,	// VMVNv4i32
+    4864U,	// VMVNv8i16
+    526U,	// VNEGD
+    16384U,	// VNEGH
+    16384U,	// VNEGS
+    16384U,	// VNEGf32q
+    16384U,	// VNEGfd
+    16384U,	// VNEGhd
+    16384U,	// VNEGhq
+    16384U,	// VNEGs16d
+    16384U,	// VNEGs16q
+    16384U,	// VNEGs32d
+    16384U,	// VNEGs32q
+    16384U,	// VNEGs8d
+    16384U,	// VNEGs8q
+    49944U,	// VNMLAD
+    3671552U,	// VNMLAH
+    3671552U,	// VNMLAS
+    49944U,	// VNMLSD
+    3671552U,	// VNMLSH
+    3671552U,	// VNMLSS
+    2212622U,	// VNMULD
+    0U,	// VNMULH
+    0U,	// VNMULS
     0U,	// VORNd
     0U,	// VORNq
     0U,	// VORRd
-    0U,	// VORRiv2i32
-    0U,	// VORRiv4i16
-    0U,	// VORRiv4i32
-    0U,	// VORRiv8i16
+    4864U,	// VORRiv2i32
+    4864U,	// VORRiv4i16
+    4864U,	// VORRiv4i32
+    4864U,	// VORRiv8i16
     0U,	// VORRq
-    0U,	// VPADALsv16i8
-    0U,	// VPADALsv2i32
-    0U,	// VPADALsv4i16
-    0U,	// VPADALsv4i32
-    0U,	// VPADALsv8i16
-    0U,	// VPADALsv8i8
-    0U,	// VPADALuv16i8
-    0U,	// VPADALuv2i32
-    0U,	// VPADALuv4i16
-    0U,	// VPADALuv4i32
-    0U,	// VPADALuv8i16
-    0U,	// VPADALuv8i8
-    0U,	// VPADDLsv16i8
-    0U,	// VPADDLsv2i32
-    0U,	// VPADDLsv4i16
-    0U,	// VPADDLsv4i32
-    0U,	// VPADDLsv8i16
-    0U,	// VPADDLsv8i8
-    0U,	// VPADDLuv16i8
-    0U,	// VPADDLuv2i32
-    0U,	// VPADDLuv4i16
-    0U,	// VPADDLuv4i32
-    0U,	// VPADDLuv8i16
-    0U,	// VPADDLuv8i8
-    70705U,	// VPADDf
-    70705U,	// VPADDh
-    1112U,	// VPADDi16
-    1112U,	// VPADDi32
-    1112U,	// VPADDi8
-    70705U,	// VPMAXf
-    70705U,	// VPMAXh
-    1112U,	// VPMAXs16
-    1112U,	// VPMAXs32
-    1112U,	// VPMAXs8
-    1112U,	// VPMAXu16
-    1112U,	// VPMAXu32
-    1112U,	// VPMAXu8
-    70705U,	// VPMINf
-    70705U,	// VPMINh
-    1112U,	// VPMINs16
-    1112U,	// VPMINs32
-    1112U,	// VPMINs8
-    1112U,	// VPMINu16
-    1112U,	// VPMINu32
-    1112U,	// VPMINu8
-    0U,	// VQABSv16i8
-    0U,	// VQABSv2i32
-    0U,	// VQABSv4i16
-    0U,	// VQABSv4i32
-    0U,	// VQABSv8i16
-    0U,	// VQABSv8i8
-    1112U,	// VQADDsv16i8
-    1112U,	// VQADDsv1i64
-    1112U,	// VQADDsv2i32
-    1112U,	// VQADDsv2i64
-    1112U,	// VQADDsv4i16
-    1112U,	// VQADDsv4i32
-    1112U,	// VQADDsv8i16
-    1112U,	// VQADDsv8i8
-    1112U,	// VQADDuv16i8
-    1112U,	// VQADDuv1i64
-    1112U,	// VQADDuv2i32
-    1112U,	// VQADDuv2i64
-    1112U,	// VQADDuv4i16
-    1112U,	// VQADDuv4i32
-    1112U,	// VQADDuv8i16
-    1112U,	// VQADDuv8i8
-    73752U,	// VQDMLALslv2i32
-    73752U,	// VQDMLALslv4i16
-    1048U,	// VQDMLALv2i64
-    1048U,	// VQDMLALv4i32
-    73752U,	// VQDMLSLslv2i32
-    73752U,	// VQDMLSLslv4i16
-    1048U,	// VQDMLSLv2i64
-    1048U,	// VQDMLSLv4i32
-    17496U,	// VQDMULHslv2i32
-    17496U,	// VQDMULHslv4i16
-    17496U,	// VQDMULHslv4i32
-    17496U,	// VQDMULHslv8i16
-    1112U,	// VQDMULHv2i32
-    1112U,	// VQDMULHv4i16
-    1112U,	// VQDMULHv4i32
-    1112U,	// VQDMULHv8i16
-    17496U,	// VQDMULLslv2i32
-    17496U,	// VQDMULLslv4i16
-    1112U,	// VQDMULLv2i64
-    1112U,	// VQDMULLv4i32
-    0U,	// VQMOVNsuv2i32
-    0U,	// VQMOVNsuv4i16
-    0U,	// VQMOVNsuv8i8
-    0U,	// VQMOVNsv2i32
-    0U,	// VQMOVNsv4i16
-    0U,	// VQMOVNsv8i8
-    0U,	// VQMOVNuv2i32
-    0U,	// VQMOVNuv4i16
-    0U,	// VQMOVNuv8i8
-    0U,	// VQNEGv16i8
-    0U,	// VQNEGv2i32
-    0U,	// VQNEGv4i16
-    0U,	// VQNEGv4i32
-    0U,	// VQNEGv8i16
-    0U,	// VQNEGv8i8
-    73752U,	// VQRDMLAHslv2i32
-    73752U,	// VQRDMLAHslv4i16
-    73752U,	// VQRDMLAHslv4i32
-    73752U,	// VQRDMLAHslv8i16
-    1048U,	// VQRDMLAHv2i32
-    1048U,	// VQRDMLAHv4i16
-    1048U,	// VQRDMLAHv4i32
-    1048U,	// VQRDMLAHv8i16
-    73752U,	// VQRDMLSHslv2i32
-    73752U,	// VQRDMLSHslv4i16
-    73752U,	// VQRDMLSHslv4i32
-    73752U,	// VQRDMLSHslv8i16
-    1048U,	// VQRDMLSHv2i32
-    1048U,	// VQRDMLSHv4i16
-    1048U,	// VQRDMLSHv4i32
-    1048U,	// VQRDMLSHv8i16
-    17496U,	// VQRDMULHslv2i32
-    17496U,	// VQRDMULHslv4i16
-    17496U,	// VQRDMULHslv4i32
-    17496U,	// VQRDMULHslv8i16
-    1112U,	// VQRDMULHv2i32
-    1112U,	// VQRDMULHv4i16
-    1112U,	// VQRDMULHv4i32
-    1112U,	// VQRDMULHv8i16
-    1112U,	// VQRSHLsv16i8
-    1112U,	// VQRSHLsv1i64
-    1112U,	// VQRSHLsv2i32
-    1112U,	// VQRSHLsv2i64
-    1112U,	// VQRSHLsv4i16
-    1112U,	// VQRSHLsv4i32
-    1112U,	// VQRSHLsv8i16
-    1112U,	// VQRSHLsv8i8
-    1112U,	// VQRSHLuv16i8
-    1112U,	// VQRSHLuv1i64
-    1112U,	// VQRSHLuv2i32
-    1112U,	// VQRSHLuv2i64
-    1112U,	// VQRSHLuv4i16
-    1112U,	// VQRSHLuv4i32
-    1112U,	// VQRSHLuv8i16
-    1112U,	// VQRSHLuv8i8
-    1112U,	// VQRSHRNsv2i32
-    1112U,	// VQRSHRNsv4i16
-    1112U,	// VQRSHRNsv8i8
-    1112U,	// VQRSHRNuv2i32
-    1112U,	// VQRSHRNuv4i16
-    1112U,	// VQRSHRNuv8i8
-    1112U,	// VQRSHRUNv2i32
-    1112U,	// VQRSHRUNv4i16
-    1112U,	// VQRSHRUNv8i8
-    1112U,	// VQSHLsiv16i8
-    1112U,	// VQSHLsiv1i64
-    1112U,	// VQSHLsiv2i32
-    1112U,	// VQSHLsiv2i64
-    1112U,	// VQSHLsiv4i16
-    1112U,	// VQSHLsiv4i32
-    1112U,	// VQSHLsiv8i16
-    1112U,	// VQSHLsiv8i8
-    1112U,	// VQSHLsuv16i8
-    1112U,	// VQSHLsuv1i64
-    1112U,	// VQSHLsuv2i32
-    1112U,	// VQSHLsuv2i64
-    1112U,	// VQSHLsuv4i16
-    1112U,	// VQSHLsuv4i32
-    1112U,	// VQSHLsuv8i16
-    1112U,	// VQSHLsuv8i8
-    1112U,	// VQSHLsv16i8
-    1112U,	// VQSHLsv1i64
-    1112U,	// VQSHLsv2i32
-    1112U,	// VQSHLsv2i64
-    1112U,	// VQSHLsv4i16
-    1112U,	// VQSHLsv4i32
-    1112U,	// VQSHLsv8i16
-    1112U,	// VQSHLsv8i8
-    1112U,	// VQSHLuiv16i8
-    1112U,	// VQSHLuiv1i64
-    1112U,	// VQSHLuiv2i32
-    1112U,	// VQSHLuiv2i64
-    1112U,	// VQSHLuiv4i16
-    1112U,	// VQSHLuiv4i32
-    1112U,	// VQSHLuiv8i16
-    1112U,	// VQSHLuiv8i8
-    1112U,	// VQSHLuv16i8
-    1112U,	// VQSHLuv1i64
-    1112U,	// VQSHLuv2i32
-    1112U,	// VQSHLuv2i64
-    1112U,	// VQSHLuv4i16
-    1112U,	// VQSHLuv4i32
-    1112U,	// VQSHLuv8i16
-    1112U,	// VQSHLuv8i8
-    1112U,	// VQSHRNsv2i32
-    1112U,	// VQSHRNsv4i16
-    1112U,	// VQSHRNsv8i8
-    1112U,	// VQSHRNuv2i32
-    1112U,	// VQSHRNuv4i16
-    1112U,	// VQSHRNuv8i8
-    1112U,	// VQSHRUNv2i32
-    1112U,	// VQSHRUNv4i16
-    1112U,	// VQSHRUNv8i8
-    1112U,	// VQSUBsv16i8
-    1112U,	// VQSUBsv1i64
-    1112U,	// VQSUBsv2i32
-    1112U,	// VQSUBsv2i64
-    1112U,	// VQSUBsv4i16
-    1112U,	// VQSUBsv4i32
-    1112U,	// VQSUBsv8i16
-    1112U,	// VQSUBsv8i8
-    1112U,	// VQSUBuv16i8
-    1112U,	// VQSUBuv1i64
-    1112U,	// VQSUBuv2i32
-    1112U,	// VQSUBuv2i64
-    1112U,	// VQSUBuv4i16
-    1112U,	// VQSUBuv4i32
-    1112U,	// VQSUBuv8i16
-    1112U,	// VQSUBuv8i8
-    1112U,	// VRADDHNv2i32
-    1112U,	// VRADDHNv4i16
-    1112U,	// VRADDHNv8i8
-    0U,	// VRECPEd
-    33U,	// VRECPEfd
-    33U,	// VRECPEfq
-    33U,	// VRECPEhd
-    33U,	// VRECPEhq
-    0U,	// VRECPEq
-    70705U,	// VRECPSfd
-    70705U,	// VRECPSfq
-    70705U,	// VRECPShd
-    70705U,	// VRECPShq
-    1024U,	// VREV16d8
-    1024U,	// VREV16q8
-    1024U,	// VREV32d16
-    1024U,	// VREV32d8
-    1024U,	// VREV32q16
-    1024U,	// VREV32q8
-    1024U,	// VREV64d16
-    1024U,	// VREV64d32
-    1024U,	// VREV64d8
-    1024U,	// VREV64q16
-    1024U,	// VREV64q32
-    1024U,	// VREV64q8
-    1112U,	// VRHADDsv16i8
-    1112U,	// VRHADDsv2i32
-    1112U,	// VRHADDsv4i16
-    1112U,	// VRHADDsv4i32
-    1112U,	// VRHADDsv8i16
-    1112U,	// VRHADDsv8i8
-    1112U,	// VRHADDuv16i8
-    1112U,	// VRHADDuv2i32
-    1112U,	// VRHADDuv4i16
-    1112U,	// VRHADDuv4i32
-    1112U,	// VRHADDuv8i16
-    1112U,	// VRHADDuv8i8
-    0U,	// VRINTAD
-    0U,	// VRINTAH
-    0U,	// VRINTANDf
-    0U,	// VRINTANDh
-    0U,	// VRINTANQf
-    0U,	// VRINTANQh
-    0U,	// VRINTAS
-    0U,	// VRINTMD
-    0U,	// VRINTMH
-    0U,	// VRINTMNDf
-    0U,	// VRINTMNDh
-    0U,	// VRINTMNQf
-    0U,	// VRINTMNQh
-    0U,	// VRINTMS
-    0U,	// VRINTND
-    0U,	// VRINTNH
-    0U,	// VRINTNNDf
-    0U,	// VRINTNNDh
-    0U,	// VRINTNNQf
-    0U,	// VRINTNNQh
-    0U,	// VRINTNS
-    0U,	// VRINTPD
-    0U,	// VRINTPH
-    0U,	// VRINTPNDf
-    0U,	// VRINTPNDh
-    0U,	// VRINTPNQf
-    0U,	// VRINTPNQh
-    0U,	// VRINTPS
-    33U,	// VRINTRD
-    33U,	// VRINTRH
-    33U,	// VRINTRS
-    33U,	// VRINTXD
-    33U,	// VRINTXH
-    0U,	// VRINTXNDf
-    0U,	// VRINTXNDh
-    0U,	// VRINTXNQf
-    0U,	// VRINTXNQh
-    33U,	// VRINTXS
-    33U,	// VRINTZD
-    33U,	// VRINTZH
-    0U,	// VRINTZNDf
-    0U,	// VRINTZNDh
-    0U,	// VRINTZNQf
-    0U,	// VRINTZNQh
-    33U,	// VRINTZS
-    1112U,	// VRSHLsv16i8
-    1112U,	// VRSHLsv1i64
-    1112U,	// VRSHLsv2i32
-    1112U,	// VRSHLsv2i64
-    1112U,	// VRSHLsv4i16
-    1112U,	// VRSHLsv4i32
-    1112U,	// VRSHLsv8i16
-    1112U,	// VRSHLsv8i8
-    1112U,	// VRSHLuv16i8
-    1112U,	// VRSHLuv1i64
-    1112U,	// VRSHLuv2i32
-    1112U,	// VRSHLuv2i64
-    1112U,	// VRSHLuv4i16
-    1112U,	// VRSHLuv4i32
-    1112U,	// VRSHLuv8i16
-    1112U,	// VRSHLuv8i8
-    1112U,	// VRSHRNv2i32
-    1112U,	// VRSHRNv4i16
-    1112U,	// VRSHRNv8i8
-    1112U,	// VRSHRsv16i8
-    1112U,	// VRSHRsv1i64
-    1112U,	// VRSHRsv2i32
-    1112U,	// VRSHRsv2i64
-    1112U,	// VRSHRsv4i16
-    1112U,	// VRSHRsv4i32
-    1112U,	// VRSHRsv8i16
-    1112U,	// VRSHRsv8i8
-    1112U,	// VRSHRuv16i8
-    1112U,	// VRSHRuv1i64
-    1112U,	// VRSHRuv2i32
-    1112U,	// VRSHRuv2i64
-    1112U,	// VRSHRuv4i16
-    1112U,	// VRSHRuv4i32
-    1112U,	// VRSHRuv8i16
-    1112U,	// VRSHRuv8i8
-    0U,	// VRSQRTEd
-    33U,	// VRSQRTEfd
-    33U,	// VRSQRTEfq
-    33U,	// VRSQRTEhd
-    33U,	// VRSQRTEhq
-    0U,	// VRSQRTEq
-    70705U,	// VRSQRTSfd
-    70705U,	// VRSQRTSfq
-    70705U,	// VRSQRTShd
-    70705U,	// VRSQRTShq
-    1048U,	// VRSRAsv16i8
-    1048U,	// VRSRAsv1i64
-    1048U,	// VRSRAsv2i32
-    1048U,	// VRSRAsv2i64
-    1048U,	// VRSRAsv4i16
-    1048U,	// VRSRAsv4i32
-    1048U,	// VRSRAsv8i16
-    1048U,	// VRSRAsv8i8
-    1048U,	// VRSRAuv16i8
-    1048U,	// VRSRAuv1i64
-    1048U,	// VRSRAuv2i32
-    1048U,	// VRSRAuv2i64
-    1048U,	// VRSRAuv4i16
-    1048U,	// VRSRAuv4i32
-    1048U,	// VRSRAuv8i16
-    1048U,	// VRSRAuv8i8
-    1112U,	// VRSUBHNv2i32
-    1112U,	// VRSUBHNv4i16
-    1112U,	// VRSUBHNv8i8
-    0U,	// VSDOTD
-    0U,	// VSDOTDI
-    0U,	// VSDOTQ
-    0U,	// VSDOTQI
-    1112U,	// VSELEQD
-    1112U,	// VSELEQH
-    1112U,	// VSELEQS
-    1112U,	// VSELGED
-    1112U,	// VSELGEH
-    1112U,	// VSELGES
-    1112U,	// VSELGTD
-    1112U,	// VSELGTH
-    1112U,	// VSELGTS
-    1112U,	// VSELVSD
-    1112U,	// VSELVSH
-    1112U,	// VSELVSS
-    6U,	// VSETLNi16
-    6U,	// VSETLNi32
-    6U,	// VSETLNi8
-    1112U,	// VSHLLi16
-    1112U,	// VSHLLi32
-    1112U,	// VSHLLi8
-    1112U,	// VSHLLsv2i64
-    1112U,	// VSHLLsv4i32
-    1112U,	// VSHLLsv8i16
-    1112U,	// VSHLLuv2i64
-    1112U,	// VSHLLuv4i32
-    1112U,	// VSHLLuv8i16
-    1112U,	// VSHLiv16i8
-    1112U,	// VSHLiv1i64
-    1112U,	// VSHLiv2i32
-    1112U,	// VSHLiv2i64
-    1112U,	// VSHLiv4i16
-    1112U,	// VSHLiv4i32
-    1112U,	// VSHLiv8i16
-    1112U,	// VSHLiv8i8
-    1112U,	// VSHLsv16i8
-    1112U,	// VSHLsv1i64
-    1112U,	// VSHLsv2i32
-    1112U,	// VSHLsv2i64
-    1112U,	// VSHLsv4i16
-    1112U,	// VSHLsv4i32
-    1112U,	// VSHLsv8i16
-    1112U,	// VSHLsv8i8
-    1112U,	// VSHLuv16i8
-    1112U,	// VSHLuv1i64
-    1112U,	// VSHLuv2i32
-    1112U,	// VSHLuv2i64
-    1112U,	// VSHLuv4i16
-    1112U,	// VSHLuv4i32
-    1112U,	// VSHLuv8i16
-    1112U,	// VSHLuv8i8
-    1112U,	// VSHRNv2i32
-    1112U,	// VSHRNv4i16
-    1112U,	// VSHRNv8i8
-    1112U,	// VSHRsv16i8
-    1112U,	// VSHRsv1i64
-    1112U,	// VSHRsv2i32
-    1112U,	// VSHRsv2i64
-    1112U,	// VSHRsv4i16
-    1112U,	// VSHRsv4i32
-    1112U,	// VSHRsv8i16
-    1112U,	// VSHRsv8i8
-    1112U,	// VSHRuv16i8
-    1112U,	// VSHRuv1i64
-    1112U,	// VSHRuv2i32
-    1112U,	// VSHRuv2i64
-    1112U,	// VSHRuv4i16
-    1112U,	// VSHRuv4i32
-    1112U,	// VSHRuv8i16
-    1112U,	// VSHRuv8i8
+    17920U,	// VPADALsv16i8
+    17920U,	// VPADALsv2i32
+    17920U,	// VPADALsv4i16
+    17920U,	// VPADALsv4i32
+    17920U,	// VPADALsv8i16
+    17920U,	// VPADALsv8i8
+    17920U,	// VPADALuv16i8
+    17920U,	// VPADALuv2i32
+    17920U,	// VPADALuv4i16
+    17920U,	// VPADALuv4i32
+    17920U,	// VPADALuv8i16
+    17920U,	// VPADALuv8i8
+    16384U,	// VPADDLsv16i8
+    16384U,	// VPADDLsv2i32
+    16384U,	// VPADDLsv4i16
+    16384U,	// VPADDLsv4i32
+    16384U,	// VPADDLsv8i16
+    16384U,	// VPADDLsv8i8
+    16384U,	// VPADDLuv16i8
+    16384U,	// VPADDLuv2i32
+    16384U,	// VPADDLuv4i16
+    16384U,	// VPADDLuv4i32
+    16384U,	// VPADDLuv8i16
+    16384U,	// VPADDLuv8i8
+    0U,	// VPADDf
+    0U,	// VPADDh
+    0U,	// VPADDi16
+    0U,	// VPADDi32
+    0U,	// VPADDi8
+    0U,	// VPMAXf
+    0U,	// VPMAXh
+    0U,	// VPMAXs16
+    0U,	// VPMAXs32
+    0U,	// VPMAXs8
+    0U,	// VPMAXu16
+    0U,	// VPMAXu32
+    0U,	// VPMAXu8
+    0U,	// VPMINf
+    0U,	// VPMINh
+    0U,	// VPMINs16
+    0U,	// VPMINs32
+    0U,	// VPMINs8
+    0U,	// VPMINu16
+    0U,	// VPMINu32
+    0U,	// VPMINu8
+    16384U,	// VQABSv16i8
+    16384U,	// VQABSv2i32
+    16384U,	// VQABSv4i16
+    16384U,	// VQABSv4i32
+    16384U,	// VQABSv8i16
+    16384U,	// VQABSv8i8
+    0U,	// VQADDsv16i8
+    17920U,	// VQADDsv1i64
+    0U,	// VQADDsv2i32
+    17920U,	// VQADDsv2i64
+    0U,	// VQADDsv4i16
+    0U,	// VQADDsv4i32
+    0U,	// VQADDsv8i16
+    0U,	// VQADDsv8i8
+    0U,	// VQADDuv16i8
+    0U,	// VQADDuv1i64
+    0U,	// VQADDuv2i32
+    0U,	// VQADDuv2i64
+    0U,	// VQADDuv4i16
+    0U,	// VQADDuv4i32
+    0U,	// VQADDuv8i16
+    0U,	// VQADDuv8i8
+    439879168U,	// VQDMLALslv2i32
+    439879168U,	// VQDMLALslv4i16
+    3671552U,	// VQDMLALv2i64
+    3671552U,	// VQDMLALv4i32
+    439879168U,	// VQDMLSLslv2i32
+    439879168U,	// VQDMLSLslv4i16
+    3671552U,	// VQDMLSLv2i64
+    3671552U,	// VQDMLSLv4i32
+    167772160U,	// VQDMULHslv2i32
+    167772160U,	// VQDMULHslv4i16
+    167772160U,	// VQDMULHslv4i32
+    167772160U,	// VQDMULHslv8i16
+    0U,	// VQDMULHv2i32
+    0U,	// VQDMULHv4i16
+    0U,	// VQDMULHv4i32
+    0U,	// VQDMULHv8i16
+    167772160U,	// VQDMULLslv2i32
+    167772160U,	// VQDMULLslv4i16
+    0U,	// VQDMULLv2i64
+    0U,	// VQDMULLv4i32
+    2U,	// VQMOVNsuv2i32
+    16384U,	// VQMOVNsuv4i16
+    16384U,	// VQMOVNsuv8i8
+    2U,	// VQMOVNsv2i32
+    16384U,	// VQMOVNsv4i16
+    16384U,	// VQMOVNsv8i8
+    16384U,	// VQMOVNuv2i32
+    16384U,	// VQMOVNuv4i16
+    16384U,	// VQMOVNuv8i8
+    16384U,	// VQNEGv16i8
+    16384U,	// VQNEGv2i32
+    16384U,	// VQNEGv4i16
+    16384U,	// VQNEGv4i32
+    16384U,	// VQNEGv8i16
+    16384U,	// VQNEGv8i8
+    439879168U,	// VQRDMLAHslv2i32
+    439879168U,	// VQRDMLAHslv4i16
+    439879168U,	// VQRDMLAHslv4i32
+    439879168U,	// VQRDMLAHslv8i16
+    3671552U,	// VQRDMLAHv2i32
+    3671552U,	// VQRDMLAHv4i16
+    3671552U,	// VQRDMLAHv4i32
+    3671552U,	// VQRDMLAHv8i16
+    439879168U,	// VQRDMLSHslv2i32
+    439879168U,	// VQRDMLSHslv4i16
+    439879168U,	// VQRDMLSHslv4i32
+    439879168U,	// VQRDMLSHslv8i16
+    3671552U,	// VQRDMLSHv2i32
+    3671552U,	// VQRDMLSHv4i16
+    3671552U,	// VQRDMLSHv4i32
+    3671552U,	// VQRDMLSHv8i16
+    167772160U,	// VQRDMULHslv2i32
+    167772160U,	// VQRDMULHslv4i16
+    167772160U,	// VQRDMULHslv4i32
+    167772160U,	// VQRDMULHslv8i16
+    0U,	// VQRDMULHv2i32
+    0U,	// VQRDMULHv4i16
+    0U,	// VQRDMULHv4i32
+    0U,	// VQRDMULHv8i16
+    0U,	// VQRSHLsv16i8
+    17920U,	// VQRSHLsv1i64
+    0U,	// VQRSHLsv2i32
+    17920U,	// VQRSHLsv2i64
+    0U,	// VQRSHLsv4i16
+    0U,	// VQRSHLsv4i32
+    0U,	// VQRSHLsv8i16
+    0U,	// VQRSHLsv8i8
+    0U,	// VQRSHLuv16i8
+    0U,	// VQRSHLuv1i64
+    0U,	// VQRSHLuv2i32
+    0U,	// VQRSHLuv2i64
+    0U,	// VQRSHLuv4i16
+    0U,	// VQRSHLuv4i32
+    0U,	// VQRSHLuv8i16
+    0U,	// VQRSHLuv8i8
+    17920U,	// VQRSHRNsv2i32
+    0U,	// VQRSHRNsv4i16
+    0U,	// VQRSHRNsv8i8
+    0U,	// VQRSHRNuv2i32
+    0U,	// VQRSHRNuv4i16
+    0U,	// VQRSHRNuv8i8
+    17920U,	// VQRSHRUNv2i32
+    0U,	// VQRSHRUNv4i16
+    0U,	// VQRSHRUNv8i8
+    0U,	// VQSHLsiv16i8
+    17920U,	// VQSHLsiv1i64
+    0U,	// VQSHLsiv2i32
+    17920U,	// VQSHLsiv2i64
+    0U,	// VQSHLsiv4i16
+    0U,	// VQSHLsiv4i32
+    0U,	// VQSHLsiv8i16
+    0U,	// VQSHLsiv8i8
+    0U,	// VQSHLsuv16i8
+    17920U,	// VQSHLsuv1i64
+    0U,	// VQSHLsuv2i32
+    17920U,	// VQSHLsuv2i64
+    0U,	// VQSHLsuv4i16
+    0U,	// VQSHLsuv4i32
+    0U,	// VQSHLsuv8i16
+    0U,	// VQSHLsuv8i8
+    0U,	// VQSHLsv16i8
+    17920U,	// VQSHLsv1i64
+    0U,	// VQSHLsv2i32
+    17920U,	// VQSHLsv2i64
+    0U,	// VQSHLsv4i16
+    0U,	// VQSHLsv4i32
+    0U,	// VQSHLsv8i16
+    0U,	// VQSHLsv8i8
+    0U,	// VQSHLuiv16i8
+    0U,	// VQSHLuiv1i64
+    0U,	// VQSHLuiv2i32
+    0U,	// VQSHLuiv2i64
+    0U,	// VQSHLuiv4i16
+    0U,	// VQSHLuiv4i32
+    0U,	// VQSHLuiv8i16
+    0U,	// VQSHLuiv8i8
+    0U,	// VQSHLuv16i8
+    0U,	// VQSHLuv1i64
+    0U,	// VQSHLuv2i32
+    0U,	// VQSHLuv2i64
+    0U,	// VQSHLuv4i16
+    0U,	// VQSHLuv4i32
+    0U,	// VQSHLuv8i16
+    0U,	// VQSHLuv8i8
+    17920U,	// VQSHRNsv2i32
+    0U,	// VQSHRNsv4i16
+    0U,	// VQSHRNsv8i8
+    0U,	// VQSHRNuv2i32
+    0U,	// VQSHRNuv4i16
+    0U,	// VQSHRNuv8i8
+    17920U,	// VQSHRUNv2i32
+    0U,	// VQSHRUNv4i16
+    0U,	// VQSHRUNv8i8
+    0U,	// VQSUBsv16i8
+    17920U,	// VQSUBsv1i64
+    0U,	// VQSUBsv2i32
+    17920U,	// VQSUBsv2i64
+    0U,	// VQSUBsv4i16
+    0U,	// VQSUBsv4i32
+    0U,	// VQSUBsv8i16
+    0U,	// VQSUBsv8i8
+    0U,	// VQSUBuv16i8
+    0U,	// VQSUBuv1i64
+    0U,	// VQSUBuv2i32
+    0U,	// VQSUBuv2i64
+    0U,	// VQSUBuv4i16
+    0U,	// VQSUBuv4i32
+    0U,	// VQSUBuv8i16
+    0U,	// VQSUBuv8i8
+    17920U,	// VRADDHNv2i32
+    0U,	// VRADDHNv4i16
+    0U,	// VRADDHNv8i8
+    16384U,	// VRECPEd
+    16384U,	// VRECPEfd
+    16384U,	// VRECPEfq
+    16384U,	// VRECPEhd
+    16384U,	// VRECPEhq
+    16384U,	// VRECPEq
+    0U,	// VRECPSfd
+    0U,	// VRECPSfq
+    0U,	// VRECPShd
+    0U,	// VRECPShq
+    16384U,	// VREV16d8
+    16384U,	// VREV16q8
+    16384U,	// VREV32d16
+    16384U,	// VREV32d8
+    16384U,	// VREV32q16
+    16384U,	// VREV32q8
+    16384U,	// VREV64d16
+    16384U,	// VREV64d32
+    16384U,	// VREV64d8
+    16384U,	// VREV64q16
+    16384U,	// VREV64q32
+    16384U,	// VREV64q8
+    0U,	// VRHADDsv16i8
+    0U,	// VRHADDsv2i32
+    0U,	// VRHADDsv4i16
+    0U,	// VRHADDsv4i32
+    0U,	// VRHADDsv8i16
+    0U,	// VRHADDsv8i8
+    0U,	// VRHADDuv16i8
+    0U,	// VRHADDuv2i32
+    0U,	// VRHADDuv4i16
+    0U,	// VRHADDuv4i32
+    0U,	// VRHADDuv8i16
+    0U,	// VRHADDuv8i8
+    2U,	// VRINTAD
+    2U,	// VRINTAH
+    2U,	// VRINTANDf
+    2U,	// VRINTANDh
+    2U,	// VRINTANQf
+    2U,	// VRINTANQh
+    2U,	// VRINTAS
+    2U,	// VRINTMD
+    2U,	// VRINTMH
+    2U,	// VRINTMNDf
+    2U,	// VRINTMNDh
+    2U,	// VRINTMNQf
+    2U,	// VRINTMNQh
+    2U,	// VRINTMS
+    2U,	// VRINTND
+    2U,	// VRINTNH
+    2U,	// VRINTNNDf
+    2U,	// VRINTNNDh
+    2U,	// VRINTNNQf
+    2U,	// VRINTNNQh
+    2U,	// VRINTNS
+    2U,	// VRINTPD
+    2U,	// VRINTPH
+    2U,	// VRINTPNDf
+    2U,	// VRINTPNDh
+    2U,	// VRINTPNQf
+    2U,	// VRINTPNQh
+    2U,	// VRINTPS
+    526U,	// VRINTRD
+    16384U,	// VRINTRH
+    16384U,	// VRINTRS
+    526U,	// VRINTXD
+    16384U,	// VRINTXH
+    2U,	// VRINTXNDf
+    2U,	// VRINTXNDh
+    2U,	// VRINTXNQf
+    2U,	// VRINTXNQh
+    16384U,	// VRINTXS
+    526U,	// VRINTZD
+    16384U,	// VRINTZH
+    2U,	// VRINTZNDf
+    2U,	// VRINTZNDh
+    2U,	// VRINTZNQf
+    2U,	// VRINTZNQh
+    16384U,	// VRINTZS
+    0U,	// VRSHLsv16i8
+    17920U,	// VRSHLsv1i64
+    0U,	// VRSHLsv2i32
+    17920U,	// VRSHLsv2i64
+    0U,	// VRSHLsv4i16
+    0U,	// VRSHLsv4i32
+    0U,	// VRSHLsv8i16
+    0U,	// VRSHLsv8i8
+    0U,	// VRSHLuv16i8
+    0U,	// VRSHLuv1i64
+    0U,	// VRSHLuv2i32
+    0U,	// VRSHLuv2i64
+    0U,	// VRSHLuv4i16
+    0U,	// VRSHLuv4i32
+    0U,	// VRSHLuv8i16
+    0U,	// VRSHLuv8i8
+    17920U,	// VRSHRNv2i32
+    0U,	// VRSHRNv4i16
+    0U,	// VRSHRNv8i8
+    0U,	// VRSHRsv16i8
+    17920U,	// VRSHRsv1i64
+    0U,	// VRSHRsv2i32
+    17920U,	// VRSHRsv2i64
+    0U,	// VRSHRsv4i16
+    0U,	// VRSHRsv4i32
+    0U,	// VRSHRsv8i16
+    0U,	// VRSHRsv8i8
+    0U,	// VRSHRuv16i8
+    0U,	// VRSHRuv1i64
+    0U,	// VRSHRuv2i32
+    0U,	// VRSHRuv2i64
+    0U,	// VRSHRuv4i16
+    0U,	// VRSHRuv4i32
+    0U,	// VRSHRuv8i16
+    0U,	// VRSHRuv8i8
+    16384U,	// VRSQRTEd
+    16384U,	// VRSQRTEfd
+    16384U,	// VRSQRTEfq
+    16384U,	// VRSQRTEhd
+    16384U,	// VRSQRTEhq
+    16384U,	// VRSQRTEq
+    0U,	// VRSQRTSfd
+    0U,	// VRSQRTSfq
+    0U,	// VRSQRTShd
+    0U,	// VRSQRTShq
+    3671552U,	// VRSRAsv16i8
+    16768U,	// VRSRAsv1i64
+    3671552U,	// VRSRAsv2i32
+    16768U,	// VRSRAsv2i64
+    3671552U,	// VRSRAsv4i16
+    3671552U,	// VRSRAsv4i32
+    3671552U,	// VRSRAsv8i16
+    3671552U,	// VRSRAsv8i8
+    3671552U,	// VRSRAuv16i8
+    3671552U,	// VRSRAuv1i64
+    3671552U,	// VRSRAuv2i32
+    3671552U,	// VRSRAuv2i64
+    3671552U,	// VRSRAuv4i16
+    3671552U,	// VRSRAuv4i32
+    3671552U,	// VRSRAuv8i16
+    3671552U,	// VRSRAuv8i8
+    17920U,	// VRSUBHNv2i32
+    0U,	// VRSUBHNv4i16
+    0U,	// VRSUBHNv8i8
+    0U,	// VSCCLRMD
+    0U,	// VSCCLRMS
+    16768U,	// VSDOTD
+    2163072U,	// VSDOTDI
+    16768U,	// VSDOTQ
+    2163072U,	// VSDOTQI
+    17920U,	// VSELEQD
+    17920U,	// VSELEQH
+    17920U,	// VSELEQS
+    17920U,	// VSELGED
+    17920U,	// VSELGEH
+    17920U,	// VSELGES
+    17920U,	// VSELGTD
+    17920U,	// VSELGTH
+    17920U,	// VSELGTS
+    17920U,	// VSELVSD
+    17920U,	// VSELVSH
+    17920U,	// VSELVSS
+    34U,	// VSETLNi16
+    34U,	// VSETLNi32
+    34U,	// VSETLNi8
+    0U,	// VSHLLi16
+    0U,	// VSHLLi32
+    0U,	// VSHLLi8
+    0U,	// VSHLLsv2i64
+    0U,	// VSHLLsv4i32
+    0U,	// VSHLLsv8i16
+    0U,	// VSHLLuv2i64
+    0U,	// VSHLLuv4i32
+    0U,	// VSHLLuv8i16
+    0U,	// VSHLiv16i8
+    17920U,	// VSHLiv1i64
+    0U,	// VSHLiv2i32
+    17920U,	// VSHLiv2i64
+    0U,	// VSHLiv4i16
+    0U,	// VSHLiv4i32
+    0U,	// VSHLiv8i16
+    0U,	// VSHLiv8i8
+    0U,	// VSHLsv16i8
+    17920U,	// VSHLsv1i64
+    0U,	// VSHLsv2i32
+    17920U,	// VSHLsv2i64
+    0U,	// VSHLsv4i16
+    0U,	// VSHLsv4i32
+    0U,	// VSHLsv8i16
+    0U,	// VSHLsv8i8
+    0U,	// VSHLuv16i8
+    0U,	// VSHLuv1i64
+    0U,	// VSHLuv2i32
+    0U,	// VSHLuv2i64
+    0U,	// VSHLuv4i16
+    0U,	// VSHLuv4i32
+    0U,	// VSHLuv8i16
+    0U,	// VSHLuv8i8
+    17920U,	// VSHRNv2i32
+    0U,	// VSHRNv4i16
+    0U,	// VSHRNv8i8
+    0U,	// VSHRsv16i8
+    17920U,	// VSHRsv1i64
+    0U,	// VSHRsv2i32
+    17920U,	// VSHRsv2i64
+    0U,	// VSHRsv4i16
+    0U,	// VSHRsv4i32
+    0U,	// VSHRsv8i16
+    0U,	// VSHRsv8i8
+    0U,	// VSHRuv16i8
+    0U,	// VSHRuv1i64
+    0U,	// VSHRuv2i32
+    0U,	// VSHRuv2i64
+    0U,	// VSHRuv4i16
+    0U,	// VSHRuv4i32
+    0U,	// VSHRuv8i16
+    0U,	// VSHRuv8i8
     0U,	// VSHTOD
-    7U,	// VSHTOH
+    74U,	// VSHTOH
     0U,	// VSHTOS
     0U,	// VSITOD
     0U,	// VSITOH
     0U,	// VSITOS
-    589912U,	// VSLIv16i8
-    589912U,	// VSLIv1i64
-    589912U,	// VSLIv2i32
-    589912U,	// VSLIv2i64
-    589912U,	// VSLIv4i16
-    589912U,	// VSLIv4i32
-    589912U,	// VSLIv8i16
-    589912U,	// VSLIv8i8
-    7U,	// VSLTOD
-    7U,	// VSLTOH
-    7U,	// VSLTOS
-    33U,	// VSQRTD
-    33U,	// VSQRTH
-    33U,	// VSQRTS
-    1048U,	// VSRAsv16i8
-    1048U,	// VSRAsv1i64
-    1048U,	// VSRAsv2i32
-    1048U,	// VSRAsv2i64
-    1048U,	// VSRAsv4i16
-    1048U,	// VSRAsv4i32
-    1048U,	// VSRAsv8i16
-    1048U,	// VSRAsv8i8
-    1048U,	// VSRAuv16i8
-    1048U,	// VSRAuv1i64
-    1048U,	// VSRAuv2i32
-    1048U,	// VSRAuv2i64
-    1048U,	// VSRAuv4i16
-    1048U,	// VSRAuv4i32
-    1048U,	// VSRAuv8i16
-    1048U,	// VSRAuv8i8
-    589912U,	// VSRIv16i8
-    589912U,	// VSRIv1i64
-    589912U,	// VSRIv2i32
-    589912U,	// VSRIv2i64
-    589912U,	// VSRIv4i16
-    589912U,	// VSRIv4i32
-    589912U,	// VSRIv8i16
-    589912U,	// VSRIv8i8
-    308U,	// VST1LNd16
-    23768380U,	// VST1LNd16_UPD
-    308U,	// VST1LNd32
-    23768380U,	// VST1LNd32_UPD
-    308U,	// VST1LNd8
-    23768380U,	// VST1LNd8_UPD
+    3671552U,	// VSLIv16i8
+    3671552U,	// VSLIv1i64
+    3671552U,	// VSLIv2i32
+    3671552U,	// VSLIv2i64
+    3671552U,	// VSLIv4i16
+    3671552U,	// VSLIv4i32
+    3671552U,	// VSLIv8i16
+    3671552U,	// VSLIv8i8
+    76U,	// VSLTOD
+    76U,	// VSLTOH
+    76U,	// VSLTOS
+    16768U,	// VSMMLA
+    526U,	// VSQRTD
+    16384U,	// VSQRTH
+    16384U,	// VSQRTS
+    3671552U,	// VSRAsv16i8
+    16768U,	// VSRAsv1i64
+    3671552U,	// VSRAsv2i32
+    16768U,	// VSRAsv2i64
+    3671552U,	// VSRAsv4i16
+    3671552U,	// VSRAsv4i32
+    3671552U,	// VSRAsv8i16
+    3671552U,	// VSRAsv8i8
+    3671552U,	// VSRAuv16i8
+    3671552U,	// VSRAuv1i64
+    3671552U,	// VSRAuv2i32
+    3671552U,	// VSRAuv2i64
+    3671552U,	// VSRAuv4i16
+    3671552U,	// VSRAuv4i32
+    3671552U,	// VSRAuv8i16
+    3671552U,	// VSRAuv8i8
+    3671552U,	// VSRIv16i8
+    3671552U,	// VSRIv1i64
+    3671552U,	// VSRIv2i32
+    3671552U,	// VSRIv2i64
+    3671552U,	// VSRIv4i16
+    3671552U,	// VSRIv4i32
+    3671552U,	// VSRIv8i16
+    3671552U,	// VSRIv8i8
+    6568U,	// VST1LNd16
+    482105896U,	// VST1LNd16_UPD
+    6568U,	// VST1LNd32
+    482105896U,	// VST1LNd32_UPD
+    6568U,	// VST1LNd8
+    482105896U,	// VST1LNd8_UPD
     0U,	// VST1LNq16Pseudo
     0U,	// VST1LNq16Pseudo_UPD
     0U,	// VST1LNq32Pseudo
@@ -6149,10 +8720,14 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VST1d16
     0U,	// VST1d16Q
     0U,	// VST1d16QPseudo
+    0U,	// VST1d16QPseudoWB_fixed
+    0U,	// VST1d16QPseudoWB_register
     0U,	// VST1d16Qwb_fixed
     0U,	// VST1d16Qwb_register
     0U,	// VST1d16T
     0U,	// VST1d16TPseudo
+    0U,	// VST1d16TPseudoWB_fixed
+    0U,	// VST1d16TPseudoWB_register
     0U,	// VST1d16Twb_fixed
     0U,	// VST1d16Twb_register
     0U,	// VST1d16wb_fixed
@@ -6160,10 +8735,14 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VST1d32
     0U,	// VST1d32Q
     0U,	// VST1d32QPseudo
+    0U,	// VST1d32QPseudoWB_fixed
+    0U,	// VST1d32QPseudoWB_register
     0U,	// VST1d32Qwb_fixed
     0U,	// VST1d32Qwb_register
     0U,	// VST1d32T
     0U,	// VST1d32TPseudo
+    0U,	// VST1d32TPseudoWB_fixed
+    0U,	// VST1d32TPseudoWB_register
     0U,	// VST1d32Twb_fixed
     0U,	// VST1d32Twb_register
     0U,	// VST1d32wb_fixed
@@ -6186,62 +8765,74 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VST1d8
     0U,	// VST1d8Q
     0U,	// VST1d8QPseudo
+    0U,	// VST1d8QPseudoWB_fixed
+    0U,	// VST1d8QPseudoWB_register
     0U,	// VST1d8Qwb_fixed
     0U,	// VST1d8Qwb_register
     0U,	// VST1d8T
     0U,	// VST1d8TPseudo
+    0U,	// VST1d8TPseudoWB_fixed
+    0U,	// VST1d8TPseudoWB_register
     0U,	// VST1d8Twb_fixed
     0U,	// VST1d8Twb_register
     0U,	// VST1d8wb_fixed
     0U,	// VST1d8wb_register
     0U,	// VST1q16
     0U,	// VST1q16HighQPseudo
+    0U,	// VST1q16HighQPseudo_UPD
     0U,	// VST1q16HighTPseudo
+    0U,	// VST1q16HighTPseudo_UPD
     0U,	// VST1q16LowQPseudo_UPD
     0U,	// VST1q16LowTPseudo_UPD
     0U,	// VST1q16wb_fixed
     0U,	// VST1q16wb_register
     0U,	// VST1q32
     0U,	// VST1q32HighQPseudo
+    0U,	// VST1q32HighQPseudo_UPD
     0U,	// VST1q32HighTPseudo
+    0U,	// VST1q32HighTPseudo_UPD
     0U,	// VST1q32LowQPseudo_UPD
     0U,	// VST1q32LowTPseudo_UPD
     0U,	// VST1q32wb_fixed
     0U,	// VST1q32wb_register
     0U,	// VST1q64
     0U,	// VST1q64HighQPseudo
+    0U,	// VST1q64HighQPseudo_UPD
     0U,	// VST1q64HighTPseudo
+    0U,	// VST1q64HighTPseudo_UPD
     0U,	// VST1q64LowQPseudo_UPD
     0U,	// VST1q64LowTPseudo_UPD
     0U,	// VST1q64wb_fixed
     0U,	// VST1q64wb_register
     0U,	// VST1q8
     0U,	// VST1q8HighQPseudo
+    0U,	// VST1q8HighQPseudo_UPD
     0U,	// VST1q8HighTPseudo
+    0U,	// VST1q8HighTPseudo_UPD
     0U,	// VST1q8LowQPseudo_UPD
     0U,	// VST1q8LowTPseudo_UPD
     0U,	// VST1q8wb_fixed
     0U,	// VST1q8wb_register
-    222900460U,	// VST2LNd16
+    406623528U,	// VST2LNd16
     0U,	// VST2LNd16Pseudo
     0U,	// VST2LNd16Pseudo_UPD
-    995572U,	// VST2LNd16_UPD
-    222900460U,	// VST2LNd32
+    407147944U,	// VST2LNd16_UPD
+    406623528U,	// VST2LNd32
     0U,	// VST2LNd32Pseudo
     0U,	// VST2LNd32Pseudo_UPD
-    995572U,	// VST2LNd32_UPD
-    222900460U,	// VST2LNd8
+    407147944U,	// VST2LNd32_UPD
+    406623528U,	// VST2LNd8
     0U,	// VST2LNd8Pseudo
     0U,	// VST2LNd8Pseudo_UPD
-    995572U,	// VST2LNd8_UPD
-    222900460U,	// VST2LNq16
+    407147944U,	// VST2LNd8_UPD
+    406623528U,	// VST2LNq16
     0U,	// VST2LNq16Pseudo
     0U,	// VST2LNq16Pseudo_UPD
-    995572U,	// VST2LNq16_UPD
-    222900460U,	// VST2LNq32
+    407147944U,	// VST2LNq16_UPD
+    406623528U,	// VST2LNq32
     0U,	// VST2LNq32Pseudo
     0U,	// VST2LNq32Pseudo_UPD
-    995572U,	// VST2LNq32_UPD
+    407147944U,	// VST2LNq32_UPD
     0U,	// VST2b16
     0U,	// VST2b16wb_fixed
     0U,	// VST2b16wb_register
@@ -6278,156 +8869,176 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VST2q8PseudoWB_register
     0U,	// VST2q8wb_fixed
     0U,	// VST2q8wb_register
-    256454972U,	// VST3LNd16
+    406624808U,	// VST3LNd16
     0U,	// VST3LNd16Pseudo
     0U,	// VST3LNd16Pseudo_UPD
-    324U,	// VST3LNd16_UPD
-    256454972U,	// VST3LNd32
+    6824U,	// VST3LNd16_UPD
+    406624808U,	// VST3LNd32
     0U,	// VST3LNd32Pseudo
     0U,	// VST3LNd32Pseudo_UPD
-    324U,	// VST3LNd32_UPD
-    256454972U,	// VST3LNd8
+    6824U,	// VST3LNd32_UPD
+    406624808U,	// VST3LNd8
     0U,	// VST3LNd8Pseudo
     0U,	// VST3LNd8Pseudo_UPD
-    324U,	// VST3LNd8_UPD
-    256454972U,	// VST3LNq16
+    6824U,	// VST3LNd8_UPD
+    406624808U,	// VST3LNq16
     0U,	// VST3LNq16Pseudo
     0U,	// VST3LNq16Pseudo_UPD
-    324U,	// VST3LNq16_UPD
-    256454972U,	// VST3LNq32
+    6824U,	// VST3LNq16_UPD
+    406624808U,	// VST3LNq32
     0U,	// VST3LNq32Pseudo
     0U,	// VST3LNq32Pseudo_UPD
-    324U,	// VST3LNq32_UPD
-    287342616U,	// VST3d16
+    6824U,	// VST3LNq32_UPD
+    369623424U,	// VST3d16
     0U,	// VST3d16Pseudo
     0U,	// VST3d16Pseudo_UPD
-    18760U,	// VST3d16_UPD
-    287342616U,	// VST3d32
+    383744U,	// VST3d16_UPD
+    369623424U,	// VST3d32
     0U,	// VST3d32Pseudo
     0U,	// VST3d32Pseudo_UPD
-    18760U,	// VST3d32_UPD
-    287342616U,	// VST3d8
+    383744U,	// VST3d32_UPD
+    369623424U,	// VST3d8
     0U,	// VST3d8Pseudo
     0U,	// VST3d8Pseudo_UPD
-    18760U,	// VST3d8_UPD
-    287342616U,	// VST3q16
+    383744U,	// VST3d8_UPD
+    369623424U,	// VST3q16
     0U,	// VST3q16Pseudo_UPD
-    18760U,	// VST3q16_UPD
+    383744U,	// VST3q16_UPD
     0U,	// VST3q16oddPseudo
     0U,	// VST3q16oddPseudo_UPD
-    287342616U,	// VST3q32
+    369623424U,	// VST3q32
     0U,	// VST3q32Pseudo_UPD
-    18760U,	// VST3q32_UPD
+    383744U,	// VST3q32_UPD
     0U,	// VST3q32oddPseudo
     0U,	// VST3q32oddPseudo_UPD
-    287342616U,	// VST3q8
+    369623424U,	// VST3q8
     0U,	// VST3q8Pseudo_UPD
-    18760U,	// VST3q8_UPD
+    383744U,	// VST3q8_UPD
     0U,	// VST3q8oddPseudo
     0U,	// VST3q8oddPseudo_UPD
-    323563764U,	// VST4LNd16
+    406623656U,	// VST4LNd16
     0U,	// VST4LNd16Pseudo
     0U,	// VST4LNd16Pseudo_UPD
-    19708U,	// VST4LNd16_UPD
-    323563764U,	// VST4LNd32
+    398888U,	// VST4LNd16_UPD
+    406623656U,	// VST4LNd32
     0U,	// VST4LNd32Pseudo
     0U,	// VST4LNd32Pseudo_UPD
-    19708U,	// VST4LNd32_UPD
-    323563764U,	// VST4LNd8
+    398888U,	// VST4LNd32_UPD
+    406623656U,	// VST4LNd8
     0U,	// VST4LNd8Pseudo
     0U,	// VST4LNd8Pseudo_UPD
-    19708U,	// VST4LNd8_UPD
-    323563764U,	// VST4LNq16
+    398888U,	// VST4LNd8_UPD
+    406623656U,	// VST4LNq16
     0U,	// VST4LNq16Pseudo
     0U,	// VST4LNq16Pseudo_UPD
-    19708U,	// VST4LNq16_UPD
-    323563764U,	// VST4LNq32
+    398888U,	// VST4LNq16_UPD
+    406623656U,	// VST4LNq32
     0U,	// VST4LNq32Pseudo
     0U,	// VST4LNq32Pseudo_UPD
-    19708U,	// VST4LNq32_UPD
-    337674264U,	// VST4d16
+    398888U,	// VST4LNq32_UPD
+    34079104U,	// VST4d16
     0U,	// VST4d16Pseudo
     0U,	// VST4d16Pseudo_UPD
-    1016136U,	// VST4d16_UPD
-    337674264U,	// VST4d32
+    15735552U,	// VST4d16_UPD
+    34079104U,	// VST4d32
     0U,	// VST4d32Pseudo
     0U,	// VST4d32Pseudo_UPD
-    1016136U,	// VST4d32_UPD
-    337674264U,	// VST4d8
+    15735552U,	// VST4d32_UPD
+    34079104U,	// VST4d8
     0U,	// VST4d8Pseudo
     0U,	// VST4d8Pseudo_UPD
-    1016136U,	// VST4d8_UPD
-    337674264U,	// VST4q16
+    15735552U,	// VST4d8_UPD
+    34079104U,	// VST4q16
     0U,	// VST4q16Pseudo_UPD
-    1016136U,	// VST4q16_UPD
+    15735552U,	// VST4q16_UPD
     0U,	// VST4q16oddPseudo
     0U,	// VST4q16oddPseudo_UPD
-    337674264U,	// VST4q32
+    34079104U,	// VST4q32
     0U,	// VST4q32Pseudo_UPD
-    1016136U,	// VST4q32_UPD
+    15735552U,	// VST4q32_UPD
     0U,	// VST4q32oddPseudo
     0U,	// VST4q32oddPseudo_UPD
-    337674264U,	// VST4q8
+    34079104U,	// VST4q8
     0U,	// VST4q8Pseudo_UPD
-    1016136U,	// VST4q8_UPD
+    15735552U,	// VST4q8_UPD
     0U,	// VST4q8oddPseudo
     0U,	// VST4q8oddPseudo_UPD
-    33U,	// VSTMDDB_UPD
-    1136U,	// VSTMDIA
-    33U,	// VSTMDIA_UPD
+    530U,	// VSTMDDB_UPD
+    18560U,	// VSTMDIA
+    530U,	// VSTMDIA_UPD
     0U,	// VSTMQIA
-    33U,	// VSTMSDB_UPD
-    1136U,	// VSTMSIA
-    33U,	// VSTMSIA_UPD
-    288U,	// VSTRD
-    296U,	// VSTRH
-    288U,	// VSTRS
-    70705U,	// VSUBD
-    70705U,	// VSUBH
-    1112U,	// VSUBHNv2i32
-    1112U,	// VSUBHNv4i16
-    1112U,	// VSUBHNv8i8
-    1112U,	// VSUBLsv2i64
-    1112U,	// VSUBLsv4i32
-    1112U,	// VSUBLsv8i16
-    1112U,	// VSUBLuv2i64
-    1112U,	// VSUBLuv4i32
-    1112U,	// VSUBLuv8i16
-    70705U,	// VSUBS
-    1112U,	// VSUBWsv2i64
-    1112U,	// VSUBWsv4i32
-    1112U,	// VSUBWsv8i16
-    1112U,	// VSUBWuv2i64
-    1112U,	// VSUBWuv4i32
-    1112U,	// VSUBWuv8i16
-    70705U,	// VSUBfd
-    70705U,	// VSUBfq
-    70705U,	// VSUBhd
-    70705U,	// VSUBhq
-    1112U,	// VSUBv16i8
-    1112U,	// VSUBv1i64
-    1112U,	// VSUBv2i32
-    1112U,	// VSUBv2i64
-    1112U,	// VSUBv4i16
-    1112U,	// VSUBv4i32
-    1112U,	// VSUBv8i16
-    1112U,	// VSUBv8i8
-    1024U,	// VSWPd
-    1024U,	// VSWPq
-    336U,	// VTBL1
-    344U,	// VTBL2
-    352U,	// VTBL3
+    530U,	// VSTMSDB_UPD
+    18560U,	// VSTMSIA
+    530U,	// VSTMSIA_UPD
+    6272U,	// VSTRD
+    6400U,	// VSTRH
+    6272U,	// VSTRS
+    0U,	// VSTR_FPCXTNS_off
+    44U,	// VSTR_FPCXTNS_post
+    0U,	// VSTR_FPCXTNS_pre
+    0U,	// VSTR_FPCXTS_off
+    44U,	// VSTR_FPCXTS_post
+    0U,	// VSTR_FPCXTS_pre
+    0U,	// VSTR_FPSCR_NZCVQC_off
+    44U,	// VSTR_FPSCR_NZCVQC_post
+    0U,	// VSTR_FPSCR_NZCVQC_pre
+    0U,	// VSTR_FPSCR_off
+    44U,	// VSTR_FPSCR_post
+    0U,	// VSTR_FPSCR_pre
+    0U,	// VSTR_P0_off
+    46U,	// VSTR_P0_post
+    0U,	// VSTR_P0_pre
+    0U,	// VSTR_VPR_off
+    44U,	// VSTR_VPR_post
+    0U,	// VSTR_VPR_pre
+    2212622U,	// VSUBD
+    0U,	// VSUBH
+    17920U,	// VSUBHNv2i32
+    0U,	// VSUBHNv4i16
+    0U,	// VSUBHNv8i8
+    0U,	// VSUBLsv2i64
+    0U,	// VSUBLsv4i32
+    0U,	// VSUBLsv8i16
+    0U,	// VSUBLuv2i64
+    0U,	// VSUBLuv4i32
+    0U,	// VSUBLuv8i16
+    0U,	// VSUBS
+    0U,	// VSUBWsv2i64
+    0U,	// VSUBWsv4i32
+    0U,	// VSUBWsv8i16
+    0U,	// VSUBWuv2i64
+    0U,	// VSUBWuv4i32
+    0U,	// VSUBWuv8i16
+    0U,	// VSUBfd
+    0U,	// VSUBfq
+    0U,	// VSUBhd
+    0U,	// VSUBhq
+    0U,	// VSUBv16i8
+    17920U,	// VSUBv1i64
+    0U,	// VSUBv2i32
+    17920U,	// VSUBv2i64
+    0U,	// VSUBv4i16
+    0U,	// VSUBv4i32
+    0U,	// VSUBv8i16
+    0U,	// VSUBv8i8
+    2163072U,	// VSUDOTDI
+    2163072U,	// VSUDOTQI
+    16384U,	// VSWPd
+    16384U,	// VSWPq
+    7040U,	// VTBL1
+    7168U,	// VTBL2
+    7296U,	// VTBL3
     0U,	// VTBL3Pseudo
-    360U,	// VTBL4
+    7424U,	// VTBL4
     0U,	// VTBL4Pseudo
-    368U,	// VTBX1
-    376U,	// VTBX2
-    384U,	// VTBX3
+    7552U,	// VTBX1
+    7680U,	// VTBX2
+    7808U,	// VTBX3
     0U,	// VTBX3Pseudo
-    392U,	// VTBX4
+    7936U,	// VTBX4
     0U,	// VTBX4Pseudo
     0U,	// VTOSHD
-    7U,	// VTOSHH
+    74U,	// VTOSHH
     0U,	// VTOSHS
     0U,	// VTOSIRD
     0U,	// VTOSIRH
@@ -6435,11 +9046,11 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VTOSIZD
     0U,	// VTOSIZH
     0U,	// VTOSIZS
-    7U,	// VTOSLD
-    7U,	// VTOSLH
-    7U,	// VTOSLS
+    76U,	// VTOSLD
+    76U,	// VTOSLH
+    76U,	// VTOSLS
     0U,	// VTOUHD
-    7U,	// VTOUHH
+    74U,	// VTOUHH
     0U,	// VTOUHS
     0U,	// VTOUIRD
     0U,	// VTOUIRH
@@ -6447,234 +9058,262 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// VTOUIZD
     0U,	// VTOUIZH
     0U,	// VTOUIZS
-    7U,	// VTOULD
-    7U,	// VTOULH
-    7U,	// VTOULS
-    1024U,	// VTRNd16
-    1024U,	// VTRNd32
-    1024U,	// VTRNd8
-    1024U,	// VTRNq16
-    1024U,	// VTRNq32
-    1024U,	// VTRNq8
+    76U,	// VTOULD
+    76U,	// VTOULH
+    76U,	// VTOULS
+    16384U,	// VTRNd16
+    16384U,	// VTRNd32
+    16384U,	// VTRNd8
+    16384U,	// VTRNq16
+    16384U,	// VTRNq32
+    16384U,	// VTRNq8
     0U,	// VTSTv16i8
     0U,	// VTSTv2i32
     0U,	// VTSTv4i16
     0U,	// VTSTv4i32
     0U,	// VTSTv8i16
     0U,	// VTSTv8i8
-    0U,	// VUDOTD
-    0U,	// VUDOTDI
-    0U,	// VUDOTQ
-    0U,	// VUDOTQI
+    16768U,	// VUDOTD
+    2163072U,	// VUDOTDI
+    16768U,	// VUDOTQ
+    2163072U,	// VUDOTQI
     0U,	// VUHTOD
-    7U,	// VUHTOH
+    74U,	// VUHTOH
     0U,	// VUHTOS
     0U,	// VUITOD
     0U,	// VUITOH
     0U,	// VUITOS
-    7U,	// VULTOD
-    7U,	// VULTOH
-    7U,	// VULTOS
-    1024U,	// VUZPd16
-    1024U,	// VUZPd8
-    1024U,	// VUZPq16
-    1024U,	// VUZPq32
-    1024U,	// VUZPq8
-    1024U,	// VZIPd16
-    1024U,	// VZIPd8
-    1024U,	// VZIPq16
-    1024U,	// VZIPq32
-    1024U,	// VZIPq8
-    20592U,	// sysLDMDA
-    401U,	// sysLDMDA_UPD
-    20592U,	// sysLDMDB
-    401U,	// sysLDMDB_UPD
-    20592U,	// sysLDMIA
-    401U,	// sysLDMIA_UPD
-    20592U,	// sysLDMIB
-    401U,	// sysLDMIB_UPD
-    20592U,	// sysSTMDA
-    401U,	// sysSTMDA_UPD
-    20592U,	// sysSTMDB
-    401U,	// sysSTMDB_UPD
-    20592U,	// sysSTMIA
-    401U,	// sysSTMIA_UPD
-    20592U,	// sysSTMIB
-    401U,	// sysSTMIB_UPD
+    76U,	// VULTOD
+    76U,	// VULTOH
+    76U,	// VULTOS
+    16768U,	// VUMMLA
+    16768U,	// VUSDOTD
+    2163072U,	// VUSDOTDI
+    16768U,	// VUSDOTQ
+    2163072U,	// VUSDOTQI
+    16768U,	// VUSMMLA
+    16384U,	// VUZPd16
+    16384U,	// VUZPd8
+    16384U,	// VUZPq16
+    16384U,	// VUZPq32
+    16384U,	// VUZPq8
+    16384U,	// VZIPd16
+    16384U,	// VZIPd8
+    16384U,	// VZIPq16
+    16384U,	// VZIPq32
+    16384U,	// VZIPq8
+    411776U,	// sysLDMDA
+    8082U,	// sysLDMDA_UPD
+    411776U,	// sysLDMDB
+    8082U,	// sysLDMDB_UPD
+    411776U,	// sysLDMIA
+    8082U,	// sysLDMIA_UPD
+    411776U,	// sysLDMIB
+    8082U,	// sysLDMIB_UPD
+    411776U,	// sysSTMDA
+    8082U,	// sysSTMDA_UPD
+    411776U,	// sysSTMDB
+    8082U,	// sysSTMDB_UPD
+    411776U,	// sysSTMIA
+    8082U,	// sysSTMIA_UPD
+    411776U,	// sysSTMIB
+    8082U,	// sysSTMIB_UPD
     0U,	// t2ADCri
     0U,	// t2ADCrr
-    1048576U,	// t2ADCrs
+    16252928U,	// t2ADCrs
     0U,	// t2ADDri
     0U,	// t2ADDri12
     0U,	// t2ADDrr
-    1048576U,	// t2ADDrs
-    72U,	// t2ADR
+    16252928U,	// t2ADDrs
+    0U,	// t2ADDspImm
+    0U,	// t2ADDspImm12
+    1280U,	// t2ADR
     0U,	// t2ANDri
     0U,	// t2ANDrr
-    1048576U,	// t2ANDrs
-    1081344U,	// t2ASRri
+    16252928U,	// t2ANDrs
+    16777216U,	// t2ASRri
     0U,	// t2ASRrr
-    0U,	// t2B
-    80U,	// t2BFC
-    163928U,	// t2BFI
+    0U,	// t2AUT
+    524672U,	// t2AUTG
+    2U,	// t2B
+    1408U,	// t2BFC
+    2622976U,	// t2BFI
+    8192U,	// t2BFLi
+    16384U,	// t2BFLr
+    8192U,	// t2BFi
+    17306496U,	// t2BFic
+    16384U,	// t2BFr
     0U,	// t2BICri
     0U,	// t2BICrr
-    1048576U,	// t2BICrs
-    0U,	// t2BXJ
-    0U,	// t2Bcc
-    4145U,	// t2CDP
-    4145U,	// t2CDP2
+    16252928U,	// t2BICrs
+    0U,	// t2BTI
+    524672U,	// t2BXAUT
+    2U,	// t2BXJ
+    2U,	// t2Bcc
+    99086U,	// t2CDP
+    99086U,	// t2CDP2
     0U,	// t2CLREX
-    1024U,	// t2CLZ
-    1024U,	// t2CMNri
-    1024U,	// t2CMNzrr
-    56U,	// t2CMNzrs
-    1024U,	// t2CMPri
-    1024U,	// t2CMPrr
-    56U,	// t2CMPrs
+    0U,	// t2CLRM
+    16384U,	// t2CLZ
+    16384U,	// t2CMNri
+    16384U,	// t2CMNzrr
+    1024U,	// t2CMNzrs
+    16384U,	// t2CMPri
+    16384U,	// t2CMPrr
+    1024U,	// t2CMPrs
     0U,	// t2CPS1p
-    0U,	// t2CPS2p
-    1112U,	// t2CPS3p
-    1112U,	// t2CRC32B
-    1112U,	// t2CRC32CB
-    1112U,	// t2CRC32CH
-    1112U,	// t2CRC32CW
-    1112U,	// t2CRC32H
-    1112U,	// t2CRC32W
-    0U,	// t2DBG
+    2U,	// t2CPS2p
+    17920U,	// t2CPS3p
+    17920U,	// t2CRC32B
+    17920U,	// t2CRC32CB
+    17920U,	// t2CRC32CH
+    17920U,	// t2CRC32CW
+    17920U,	// t2CRC32H
+    17920U,	// t2CRC32W
+    17303040U,	// t2CSEL
+    17303040U,	// t2CSINC
+    17303040U,	// t2CSINV
+    17303040U,	// t2CSNEG
+    2U,	// t2DBG
     0U,	// t2DCPS1
     0U,	// t2DCPS2
     0U,	// t2DCPS3
+    2U,	// t2DLS
     0U,	// t2DMB
     0U,	// t2DSB
     0U,	// t2EORri
     0U,	// t2EORrr
-    1048576U,	// t2EORrs
-    0U,	// t2HINT
+    16252928U,	// t2EORrs
+    2U,	// t2HINT
     0U,	// t2HVC
     0U,	// t2ISB
     0U,	// t2IT
     0U,	// t2Int_eh_sjlj_setjmp
     0U,	// t2Int_eh_sjlj_setjmp_nofp
-    8U,	// t2LDA
-    8U,	// t2LDAB
-    8U,	// t2LDAEX
-    8U,	// t2LDAEXB
-    557056U,	// t2LDAEXD
-    8U,	// t2LDAEXH
-    8U,	// t2LDAH
-    122U,	// t2LDC2L_OFFSET
-    196738U,	// t2LDC2L_OPTION
-    229506U,	// t2LDC2L_POST
-    138U,	// t2LDC2L_PRE
-    122U,	// t2LDC2_OFFSET
-    196738U,	// t2LDC2_OPTION
-    229506U,	// t2LDC2_POST
-    138U,	// t2LDC2_PRE
-    122U,	// t2LDCL_OFFSET
-    196738U,	// t2LDCL_OPTION
-    229506U,	// t2LDCL_POST
-    138U,	// t2LDCL_PRE
-    122U,	// t2LDC_OFFSET
-    196738U,	// t2LDC_OPTION
-    229506U,	// t2LDC_POST
-    138U,	// t2LDC_PRE
-    1136U,	// t2LDMDB
-    33U,	// t2LDMDB_UPD
-    1136U,	// t2LDMIA
-    33U,	// t2LDMIA_UPD
-    408U,	// t2LDRBT
-    21632U,	// t2LDRB_POST
-    416U,	// t2LDRB_PRE
-    160U,	// t2LDRBi12
-    408U,	// t2LDRBi8
-    424U,	// t2LDRBpci
-    432U,	// t2LDRBs
-    25493504U,	// t2LDRD_POST
-    1114112U,	// t2LDRD_PRE
-    1146880U,	// t2LDRDi8
-    440U,	// t2LDREX
-    8U,	// t2LDREXB
-    557056U,	// t2LDREXD
-    8U,	// t2LDREXH
-    408U,	// t2LDRHT
-    21632U,	// t2LDRH_POST
-    416U,	// t2LDRH_PRE
-    160U,	// t2LDRHi12
-    408U,	// t2LDRHi8
-    424U,	// t2LDRHpci
-    432U,	// t2LDRHs
-    408U,	// t2LDRSBT
-    21632U,	// t2LDRSB_POST
-    416U,	// t2LDRSB_PRE
-    160U,	// t2LDRSBi12
-    408U,	// t2LDRSBi8
-    424U,	// t2LDRSBpci
-    432U,	// t2LDRSBs
-    408U,	// t2LDRSHT
-    21632U,	// t2LDRSH_POST
-    416U,	// t2LDRSH_PRE
-    160U,	// t2LDRSHi12
-    408U,	// t2LDRSHi8
-    424U,	// t2LDRSHpci
-    432U,	// t2LDRSHs
-    408U,	// t2LDRT
-    21632U,	// t2LDR_POST
-    416U,	// t2LDR_PRE
-    160U,	// t2LDRi12
-    408U,	// t2LDRi8
-    424U,	// t2LDRpci
-    432U,	// t2LDRs
+    128U,	// t2LDA
+    128U,	// t2LDAB
+    128U,	// t2LDAEX
+    128U,	// t2LDAEXB
+    10485760U,	// t2LDAEXD
+    128U,	// t2LDAEXH
+    128U,	// t2LDAH
+    2580U,	// t2LDC2L_OFFSET
+    4721300U,	// t2LDC2L_OPTION
+    5245588U,	// t2LDC2L_POST
+    22U,	// t2LDC2L_PRE
+    2580U,	// t2LDC2_OFFSET
+    4721300U,	// t2LDC2_OPTION
+    5245588U,	// t2LDC2_POST
+    22U,	// t2LDC2_PRE
+    2580U,	// t2LDCL_OFFSET
+    4721300U,	// t2LDCL_OPTION
+    5245588U,	// t2LDCL_POST
+    22U,	// t2LDCL_PRE
+    2580U,	// t2LDC_OFFSET
+    4721300U,	// t2LDC_OPTION
+    5245588U,	// t2LDC_POST
+    22U,	// t2LDC_PRE
+    18560U,	// t2LDMDB
+    530U,	// t2LDMDB_UPD
+    18560U,	// t2LDMIA
+    530U,	// t2LDMIA_UPD
+    3968U,	// t2LDRBT
+    150144U,	// t2LDRB_POST
+    4352U,	// t2LDRB_PRE
+    3072U,	// t2LDRBi12
+    3968U,	// t2LDRBi8
+    8320U,	// t2LDRBpci
+    8448U,	// t2LDRBs
+    510132224U,	// t2LDRD_POST
+    17825792U,	// t2LDRD_PRE
+    18350080U,	// t2LDRDi8
+    8576U,	// t2LDREX
+    128U,	// t2LDREXB
+    10485760U,	// t2LDREXD
+    128U,	// t2LDREXH
+    3968U,	// t2LDRHT
+    150144U,	// t2LDRH_POST
+    4352U,	// t2LDRH_PRE
+    3072U,	// t2LDRHi12
+    3968U,	// t2LDRHi8
+    8320U,	// t2LDRHpci
+    8448U,	// t2LDRHs
+    3968U,	// t2LDRSBT
+    150144U,	// t2LDRSB_POST
+    4352U,	// t2LDRSB_PRE
+    3072U,	// t2LDRSBi12
+    3968U,	// t2LDRSBi8
+    8320U,	// t2LDRSBpci
+    8448U,	// t2LDRSBs
+    3968U,	// t2LDRSHT
+    150144U,	// t2LDRSH_POST
+    4352U,	// t2LDRSH_PRE
+    3072U,	// t2LDRSHi12
+    3968U,	// t2LDRSHi8
+    8320U,	// t2LDRSHpci
+    8448U,	// t2LDRSHs
+    3968U,	// t2LDRT
+    150144U,	// t2LDR_POST
+    4352U,	// t2LDR_PRE
+    3072U,	// t2LDRi12
+    3968U,	// t2LDRi8
+    8320U,	// t2LDRpci
+    8448U,	// t2LDRs
+    0U,	// t2LE
+    0U,	// t2LEUpdate
     0U,	// t2LSLri
     0U,	// t2LSLrr
-    1081344U,	// t2LSRri
+    16777216U,	// t2LSRri
     0U,	// t2LSRrr
-    4690993U,	// t2MCR
-    4690993U,	// t2MCR2
-    6788145U,	// t2MCRR
-    6788145U,	// t2MCRR2
-    35651584U,	// t2MLA
-    35651584U,	// t2MLS
-    1112U,	// t2MOVTi16
-    1024U,	// t2MOVi
-    1024U,	// t2MOVi16
-    1024U,	// t2MOVr
-    22528U,	// t2MOVsra_flag
-    22528U,	// t2MOVsrl_flag
-    0U,	// t2MRC
-    0U,	// t2MRC2
+    103924494U,	// t2MCR
+    103924494U,	// t2MCR2
+    137478926U,	// t2MCRR
+    137478926U,	// t2MCRR2
+    33554432U,	// t2MLA
+    33554432U,	// t2MLS
+    17920U,	// t2MOVTi16
+    16384U,	// t2MOVi
+    16384U,	// t2MOVi16
+    16384U,	// t2MOVr
+    425984U,	// t2MOVsra_flag
+    425984U,	// t2MOVsrl_flag
+    131864U,	// t2MRC
+    131864U,	// t2MRC2
     0U,	// t2MRRC
     0U,	// t2MRRC2
-    2U,	// t2MRS_AR
-    448U,	// t2MRS_M
-    200U,	// t2MRSbanked
-    2U,	// t2MRSsys_AR
-    33U,	// t2MSR_AR
-    33U,	// t2MSR_M
+    26U,	// t2MRS_AR
+    8704U,	// t2MRS_M
+    3712U,	// t2MRSbanked
+    28U,	// t2MRSsys_AR
+    526U,	// t2MSR_AR
+    526U,	// t2MSR_M
     0U,	// t2MSRbanked
     0U,	// t2MUL
-    1024U,	// t2MVNi
-    1024U,	// t2MVNr
-    56U,	// t2MVNs
+    16384U,	// t2MVNi
+    16384U,	// t2MVNr
+    1024U,	// t2MVNs
     0U,	// t2ORNri
     0U,	// t2ORNrr
-    1048576U,	// t2ORNrs
+    16252928U,	// t2ORNrs
     0U,	// t2ORRri
     0U,	// t2ORRrr
-    1048576U,	// t2ORRrs
-    8388608U,	// t2PKHBT
-    10485760U,	// t2PKHTB
+    16252928U,	// t2ORRrs
+    0U,	// t2PAC
+    0U,	// t2PACBTI
+    524672U,	// t2PACG
+    201326592U,	// t2PKHBT
+    234881024U,	// t2PKHTB
     0U,	// t2PLDWi12
     0U,	// t2PLDWi8
-    0U,	// t2PLDWs
+    1U,	// t2PLDWs
     0U,	// t2PLDi12
     0U,	// t2PLDi8
-    0U,	// t2PLDpci
-    0U,	// t2PLDs
+    1U,	// t2PLDpci
+    1U,	// t2PLDs
     0U,	// t2PLIi12
     0U,	// t2PLIi8
-    0U,	// t2PLIpci
-    0U,	// t2PLIs
+    1U,	// t2PLIpci
+    1U,	// t2PLIs
     0U,	// t2QADD
     0U,	// t2QADD16
     0U,	// t2QADD8
@@ -6685,27 +9324,28 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2QSUB
     0U,	// t2QSUB16
     0U,	// t2QSUB8
-    1024U,	// t2RBIT
-    1024U,	// t2REV
-    1024U,	// t2REV16
-    1024U,	// t2REVSH
-    0U,	// t2RFEDB
-    0U,	// t2RFEDBW
-    0U,	// t2RFEIA
-    0U,	// t2RFEIAW
+    16384U,	// t2RBIT
+    16384U,	// t2REV
+    16384U,	// t2REV16
+    16384U,	// t2REVSH
+    2U,	// t2RFEDB
+    4U,	// t2RFEDBW
+    2U,	// t2RFEIA
+    4U,	// t2RFEIAW
     0U,	// t2RORri
     0U,	// t2RORrr
-    1024U,	// t2RRX
+    16384U,	// t2RRX
     0U,	// t2RSBri
     0U,	// t2RSBrr
-    1048576U,	// t2RSBrs
+    16252928U,	// t2RSBrs
     0U,	// t2SADD16
     0U,	// t2SADD8
     0U,	// t2SASX
+    0U,	// t2SB
     0U,	// t2SBCri
     0U,	// t2SBCrr
-    1048576U,	// t2SBCrs
-    69206016U,	// t2SBFX
+    16252928U,	// t2SBCrs
+    33554432U,	// t2SBFX
     0U,	// t2SDIV
     0U,	// t2SEL
     0U,	// t2SETPAN
@@ -6716,37 +9356,37 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2SHSAX
     0U,	// t2SHSUB16
     0U,	// t2SHSUB8
-    0U,	// t2SMC
-    35651584U,	// t2SMLABB
-    35651584U,	// t2SMLABT
-    35651584U,	// t2SMLAD
-    35651584U,	// t2SMLADX
-    35651584U,	// t2SMLAL
-    35651584U,	// t2SMLALBB
-    35651584U,	// t2SMLALBT
-    35651584U,	// t2SMLALD
-    35651584U,	// t2SMLALDX
-    35651584U,	// t2SMLALTB
-    35651584U,	// t2SMLALTT
-    35651584U,	// t2SMLATB
-    35651584U,	// t2SMLATT
-    35651584U,	// t2SMLAWB
-    35651584U,	// t2SMLAWT
-    35651584U,	// t2SMLSD
-    35651584U,	// t2SMLSDX
-    35651584U,	// t2SMLSLD
-    35651584U,	// t2SMLSLDX
-    35651584U,	// t2SMMLA
-    35651584U,	// t2SMMLAR
-    35651584U,	// t2SMMLS
-    35651584U,	// t2SMMLSR
+    2U,	// t2SMC
+    33554432U,	// t2SMLABB
+    33554432U,	// t2SMLABT
+    33554432U,	// t2SMLAD
+    33554432U,	// t2SMLADX
+    33554432U,	// t2SMLAL
+    33554432U,	// t2SMLALBB
+    33554432U,	// t2SMLALBT
+    33554432U,	// t2SMLALD
+    33554432U,	// t2SMLALDX
+    33554432U,	// t2SMLALTB
+    33554432U,	// t2SMLALTT
+    33554432U,	// t2SMLATB
+    33554432U,	// t2SMLATT
+    33554432U,	// t2SMLAWB
+    33554432U,	// t2SMLAWT
+    33554432U,	// t2SMLSD
+    33554432U,	// t2SMLSDX
+    33554432U,	// t2SMLSLD
+    33554432U,	// t2SMLSLDX
+    33554432U,	// t2SMMLA
+    33554432U,	// t2SMMLAR
+    33554432U,	// t2SMMLS
+    33554432U,	// t2SMMLSR
     0U,	// t2SMMUL
     0U,	// t2SMMULR
     0U,	// t2SMUAD
     0U,	// t2SMUADX
     0U,	// t2SMULBB
     0U,	// t2SMULBT
-    35651584U,	// t2SMULL
+    33554432U,	// t2SMULL
     0U,	// t2SMULTB
     0U,	// t2SMULTT
     0U,	// t2SMULWB
@@ -6757,91 +9397,93 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2SRSDB_UPD
     0U,	// t2SRSIA
     0U,	// t2SRSIA_UPD
-    6352U,	// t2SSAT
-    1232U,	// t2SSAT16
+    218112U,	// t2SSAT
+    21504U,	// t2SSAT16
     0U,	// t2SSAX
     0U,	// t2SSUB16
     0U,	// t2SSUB8
-    122U,	// t2STC2L_OFFSET
-    196738U,	// t2STC2L_OPTION
-    229506U,	// t2STC2L_POST
-    138U,	// t2STC2L_PRE
-    122U,	// t2STC2_OFFSET
-    196738U,	// t2STC2_OPTION
-    229506U,	// t2STC2_POST
-    138U,	// t2STC2_PRE
-    122U,	// t2STCL_OFFSET
-    196738U,	// t2STCL_OPTION
-    229506U,	// t2STCL_POST
-    138U,	// t2STCL_PRE
-    122U,	// t2STC_OFFSET
-    196738U,	// t2STC_OPTION
-    229506U,	// t2STC_POST
-    138U,	// t2STC_PRE
-    8U,	// t2STL
-    8U,	// t2STLB
-    557056U,	// t2STLEX
-    557056U,	// t2STLEXB
-    371195904U,	// t2STLEXD
-    557056U,	// t2STLEXH
-    8U,	// t2STLH
-    1136U,	// t2STMDB
-    33U,	// t2STMDB_UPD
-    1136U,	// t2STMIA
-    33U,	// t2STMIA_UPD
-    408U,	// t2STRBT
-    21632U,	// t2STRB_POST
-    416U,	// t2STRB_PRE
-    160U,	// t2STRBi12
-    408U,	// t2STRBi8
-    432U,	// t2STRBs
-    25493592U,	// t2STRD_POST
-    1114200U,	// t2STRD_PRE
-    1146880U,	// t2STRDi8
-    1179648U,	// t2STREX
-    557056U,	// t2STREXB
-    371195904U,	// t2STREXD
-    557056U,	// t2STREXH
-    408U,	// t2STRHT
-    21632U,	// t2STRH_POST
-    416U,	// t2STRH_PRE
-    160U,	// t2STRHi12
-    408U,	// t2STRHi8
-    432U,	// t2STRHs
-    408U,	// t2STRT
-    21632U,	// t2STR_POST
-    416U,	// t2STR_PRE
-    160U,	// t2STRi12
-    408U,	// t2STRi8
-    432U,	// t2STRs
+    2580U,	// t2STC2L_OFFSET
+    4721300U,	// t2STC2L_OPTION
+    5245588U,	// t2STC2L_POST
+    22U,	// t2STC2L_PRE
+    2580U,	// t2STC2_OFFSET
+    4721300U,	// t2STC2_OPTION
+    5245588U,	// t2STC2_POST
+    22U,	// t2STC2_PRE
+    2580U,	// t2STCL_OFFSET
+    4721300U,	// t2STCL_OPTION
+    5245588U,	// t2STCL_POST
+    22U,	// t2STCL_PRE
+    2580U,	// t2STC_OFFSET
+    4721300U,	// t2STC_OPTION
+    5245588U,	// t2STC_POST
+    22U,	// t2STC_PRE
+    128U,	// t2STL
+    128U,	// t2STLB
+    10485760U,	// t2STLEX
+    10485760U,	// t2STLEXB
+    33554432U,	// t2STLEXD
+    10485760U,	// t2STLEXH
+    128U,	// t2STLH
+    18560U,	// t2STMDB
+    530U,	// t2STMDB_UPD
+    18560U,	// t2STMIA
+    530U,	// t2STMIA_UPD
+    3968U,	// t2STRBT
+    150144U,	// t2STRB_POST
+    4352U,	// t2STRB_PRE
+    3072U,	// t2STRBi12
+    3968U,	// t2STRBi8
+    8448U,	// t2STRBs
+    510133760U,	// t2STRD_POST
+    17827328U,	// t2STRD_PRE
+    18350080U,	// t2STRDi8
+    18874368U,	// t2STREX
+    10485760U,	// t2STREXB
+    33554432U,	// t2STREXD
+    10485760U,	// t2STREXH
+    3968U,	// t2STRHT
+    150144U,	// t2STRH_POST
+    4352U,	// t2STRH_PRE
+    3072U,	// t2STRHi12
+    3968U,	// t2STRHi8
+    8448U,	// t2STRHs
+    3968U,	// t2STRT
+    150144U,	// t2STR_POST
+    4352U,	// t2STR_PRE
+    3072U,	// t2STRi12
+    3968U,	// t2STRi8
+    8448U,	// t2STRs
     0U,	// t2SUBS_PC_LR
     0U,	// t2SUBri
     0U,	// t2SUBri12
     0U,	// t2SUBrr
-    1048576U,	// t2SUBrs
-    12582912U,	// t2SXTAB
-    12582912U,	// t2SXTAB16
-    12582912U,	// t2SXTAH
-    7168U,	// t2SXTB
-    7168U,	// t2SXTB16
-    7168U,	// t2SXTH
-    0U,	// t2TBB
-    0U,	// t2TBH
-    1024U,	// t2TEQri
-    1024U,	// t2TEQrr
-    56U,	// t2TEQrs
-    0U,	// t2TSB
-    1024U,	// t2TSTri
-    1024U,	// t2TSTrr
-    56U,	// t2TSTrs
-    1024U,	// t2TT
-    1024U,	// t2TTA
-    1024U,	// t2TTAT
-    1024U,	// t2TTT
+    16252928U,	// t2SUBrs
+    0U,	// t2SUBspImm
+    0U,	// t2SUBspImm12
+    268435456U,	// t2SXTAB
+    268435456U,	// t2SXTAB16
+    268435456U,	// t2SXTAH
+    229376U,	// t2SXTB
+    229376U,	// t2SXTB16
+    229376U,	// t2SXTH
+    1U,	// t2TBB
+    1U,	// t2TBH
+    16384U,	// t2TEQri
+    16384U,	// t2TEQrr
+    1024U,	// t2TEQrs
+    1U,	// t2TSB
+    16384U,	// t2TSTri
+    16384U,	// t2TSTrr
+    1024U,	// t2TSTrs
+    16384U,	// t2TT
+    16384U,	// t2TTA
+    16384U,	// t2TTAT
+    16384U,	// t2TTT
     0U,	// t2UADD16
     0U,	// t2UADD8
     0U,	// t2UASX
-    69206016U,	// t2UBFX
+    33554432U,	// t2UBFX
     0U,	// t2UDF
     0U,	// t2UDIV
     0U,	// t2UHADD16
@@ -6850,9 +9492,9 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2UHSAX
     0U,	// t2UHSUB16
     0U,	// t2UHSUB8
-    35651584U,	// t2UMAAL
-    35651584U,	// t2UMLAL
-    35651584U,	// t2UMULL
+    33554432U,	// t2UMAAL
+    33554432U,	// t2UMLAL
+    33554432U,	// t2UMULL
     0U,	// t2UQADD16
     0U,	// t2UQADD8
     0U,	// t2UQASX
@@ -6860,126 +9502,140 @@ static void printInstruction(MCInst *MI, SStream *O)
     0U,	// t2UQSUB16
     0U,	// t2UQSUB8
     0U,	// t2USAD8
-    35651584U,	// t2USADA8
-    14680064U,	// t2USAT
+    33554432U,	// t2USADA8
+    301989888U,	// t2USAT
     0U,	// t2USAT16
     0U,	// t2USAX
     0U,	// t2USUB16
     0U,	// t2USUB8
-    12582912U,	// t2UXTAB
-    12582912U,	// t2UXTAB16
-    12582912U,	// t2UXTAH
-    7168U,	// t2UXTB
-    7168U,	// t2UXTB16
-    7168U,	// t2UXTH
-    0U,	// tADC
-    1112U,	// tADDhirr
-    1048U,	// tADDi3
-    0U,	// tADDi8
+    268435456U,	// t2UXTAB
+    268435456U,	// t2UXTAB16
+    268435456U,	// t2UXTAH
+    229376U,	// t2UXTB
+    229376U,	// t2UXTB16
+    229376U,	// t2UXTH
+    21376U,	// t2WLS
+    2U,	// tADC
+    17920U,	// tADDhirr
+    16768U,	// tADDi3
+    2U,	// tADDi8
     0U,	// tADDrSP
-    1212416U,	// tADDrSPi
-    1048U,	// tADDrr
-    456U,	// tADDspi
-    1112U,	// tADDspr
-    464U,	// tADR
-    0U,	// tAND
-    472U,	// tASRri
-    0U,	// tASRrr
-    0U,	// tB
-    0U,	// tBIC
+    19398656U,	// tADDrSPi
+    16768U,	// tADDrr
+    8832U,	// tADDspi
+    17920U,	// tADDspr
+    8960U,	// tADR
+    2U,	// tAND
+    9088U,	// tASRri
+    2U,	// tASRrr
+    2U,	// tB
+    2U,	// tBIC
     0U,	// tBKPT
     0U,	// tBL
-    0U,	// tBLXNSr
+    2U,	// tBLXNSr
     0U,	// tBLXi
-    0U,	// tBLXr
-    0U,	// tBX
-    0U,	// tBXNS
-    0U,	// tBcc
-    0U,	// tCBNZ
-    0U,	// tCBZ
-    1024U,	// tCMNz
-    1024U,	// tCMPhir
-    1024U,	// tCMPi8
-    1024U,	// tCMPr
-    0U,	// tCPS
-    0U,	// tEOR
-    0U,	// tHINT
+    2U,	// tBLXr
+    2U,	// tBX
+    2U,	// tBXNS
+    2U,	// tBcc
+    2U,	// tCBNZ
+    2U,	// tCBZ
+    16384U,	// tCMNz
+    16384U,	// tCMPhir
+    16384U,	// tCMPi8
+    16384U,	// tCMPr
+    2U,	// tCPS
+    2U,	// tEOR
+    2U,	// tHINT
     0U,	// tHLT
     0U,	// tInt_WIN_eh_sjlj_longjmp
     0U,	// tInt_eh_sjlj_longjmp
     0U,	// tInt_eh_sjlj_setjmp
-    1136U,	// tLDMIA
-    480U,	// tLDRBi
-    488U,	// tLDRBr
-    496U,	// tLDRHi
-    488U,	// tLDRHr
-    488U,	// tLDRSB
-    488U,	// tLDRSH
-    504U,	// tLDRi
-    424U,	// tLDRpci
-    488U,	// tLDRr
-    512U,	// tLDRspi
-    1048U,	// tLSLri
-    0U,	// tLSLrr
-    472U,	// tLSRri
-    0U,	// tLSRrr
-    0U,	// tMOVSr
+    18560U,	// tLDMIA
+    9216U,	// tLDRBi
+    9344U,	// tLDRBr
+    9472U,	// tLDRHi
+    9344U,	// tLDRHr
+    9344U,	// tLDRSB
+    9344U,	// tLDRSH
+    9600U,	// tLDRi
+    8320U,	// tLDRpci
+    9344U,	// tLDRr
+    9728U,	// tLDRspi
+    16768U,	// tLSLri
+    2U,	// tLSLrr
+    9088U,	// tLSRri
+    2U,	// tLSRrr
+    2U,	// tMOVSr
     0U,	// tMOVi8
-    1024U,	// tMOVr
-    1048U,	// tMUL
+    16384U,	// tMOVr
+    16768U,	// tMUL
     0U,	// tMVN
-    0U,	// tORR
+    2U,	// tORR
     0U,	// tPICADD
     0U,	// tPOP
     0U,	// tPUSH
-    1024U,	// tREV
-    1024U,	// tREV16
-    1024U,	// tREVSH
-    0U,	// tROR
+    16384U,	// tREV
+    16384U,	// tREV16
+    16384U,	// tREVSH
+    2U,	// tROR
     0U,	// tRSB
-    0U,	// tSBC
+    2U,	// tSBC
     0U,	// tSETEND
-    33U,	// tSTMIA_UPD
-    480U,	// tSTRBi
-    488U,	// tSTRBr
-    496U,	// tSTRHi
-    488U,	// tSTRHr
-    504U,	// tSTRi
-    488U,	// tSTRr
-    512U,	// tSTRspi
-    1048U,	// tSUBi3
-    0U,	// tSUBi8
-    1048U,	// tSUBrr
-    456U,	// tSUBspi
-    0U,	// tSVC
-    1024U,	// tSXTB
-    1024U,	// tSXTH
+    530U,	// tSTMIA_UPD
+    9216U,	// tSTRBi
+    9344U,	// tSTRBr
+    9472U,	// tSTRHi
+    9344U,	// tSTRHr
+    9600U,	// tSTRi
+    9344U,	// tSTRr
+    9728U,	// tSTRspi
+    16768U,	// tSUBi3
+    2U,	// tSUBi8
+    16768U,	// tSUBrr
+    8832U,	// tSUBspi
+    2U,	// tSVC
+    16384U,	// tSXTB
+    16384U,	// tSXTH
     0U,	// tTRAP
-    1024U,	// tTST
+    16384U,	// tTST
     0U,	// tUDF
-    1024U,	// tUXTB
-    1024U,	// tUXTH
+    16384U,	// tUXTB
+    16384U,	// tUXTH
     0U,	// t__brkdiv0
   };
 
-  unsigned int opcode = MCInst_getOpcode(MI);
-  // printf("opcode = %u\n", opcode);
-
   // Emit the opcode for the instruction.
   uint64_t Bits = 0;
-  Bits |= (uint64_t)OpInfo0[opcode] << 0;
-  Bits |= (uint64_t)OpInfo1[opcode] << 32;
+  Bits |= (uint64_t)OpInfo0[MCInst_getOpcode(MI)] << 0;
+  Bits |= (uint64_t)OpInfo1[MCInst_getOpcode(MI)] << 32;
+  MnemonicBitsInfo MBI = {
 #ifndef CAPSTONE_DIET
-  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
-#endif
+    AsmStrs+(Bits & 8191)-1,
+#else
+    NULL,
+#endif // CAPSTONE_DIET
+    Bits
+  };
+  return MBI;
+}
 
+/// printInstruction - This method is automatically generated by tablegen
+/// from the instruction set description.
+void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
+  SStream_concat0(O, "");
+  MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
 
-  // Fragment 0 encoded into 5 bits for 32 unique commands.
-  // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 12) & 31));
-  switch ((Bits >> 12) & 31) {
-  default: // unreachable
+  SStream_concat0(O, MnemonicInfo.first);
+
+  uint64_t Bits = MnemonicInfo.second;
+  assert(Bits != 0 && "Cannot print this instruction.");
+
+  // Fragment 0 encoded into 6 bits for 43 unique commands.
+  switch ((Bits >> 13) & 63) {
+  default: assert(0 && "Invalid command number.");
   case 0:
-    // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL...
+    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
     return;
     break;
   case 1:
@@ -6992,7 +9648,7 @@ static void printInstruction(MCInst *MI, SStream *O)
     printThumbITMask(MI, 1, O);
     break;
   case 3:
-    // LDRBT_POST, LDRConstPool, LDRT_POST, STRBT_POST, STRT_POST, t2LDRBpcre...
+    // LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRB...
     printPredicateOperand(MI, 2, O);
     break;
   case 4:
@@ -7030,56 +9686,70 @@ static void printInstruction(MCInst *MI, SStream *O)
     return;
     break;
   case 10:
-    // AESD, AESE, AESIMC, AESMC, BKPT, BL, BLX, BLXi, BX, CPS1p, CRC32B, CRC...
+    // AESD, AESE, AESIMC, AESMC, BKPT, BLX, BX, CPS1p, CRC32B, CRC32CB, CRC3...
     printOperand(MI, 0, O);
     break;
   case 11:
+    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDOTS_VDOTQ, MV...
+    printOperand(MI, 1, O);
+    break;
+  case 12:
+    // BL, BLXi, t2BFic, t2LE
+    printOperandAddr(MI, Address, 0, O);
+    break;
+  case 13:
     // BLX_pred, BL_pred, BXJ, BX_pred, Bcc, DBG, FLDMXIA, FSTMXIA, HINT, LDM...
     printPredicateOperand(MI, 1, O);
     break;
-  case 12:
-    // BX_RET, ERET, FMSTAT, MOVPCLR, t2CLREX, t2DCPS1, t2DCPS2, t2DCPS3, t2S...
+  case 14:
+    // BX_RET, ERET, FMSTAT, MOVPCLR, MVE_LCTP, VSCCLRMD, VSCCLRMS, t2AUTG, t...
     printPredicateOperand(MI, 0, O);
     break;
-  case 13:
-    // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, SMLALBB, SMLALBT, SMLALD, SMLALDX,...
+  case 15:
+    // CDE_CX1, CDE_CX1D, CDE_CX2, CDE_CX2D, CDE_CX3, CDE_CX3D, CDE_VCX1A_fpd...
+    printPImmediate(MI, 1, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 16:
+    // CDE_CX3A, CDE_CX3DA, CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, ...
     printPredicateOperand(MI, 6, O);
     break;
-  case 14:
-    // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, ...
+  case 17:
+    // CDE_VCX1A_vec, CDE_VCX2_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, ...
+    printVPTPredicateOperand(MI, 4, O);
+    break;
+  case 18:
+    // CDE_VCX1_vec, MVE_VABDf16, MVE_VABDf32, MVE_VABDs16, MVE_VABDs32, MVE_...
+    printVPTPredicateOperand(MI, 3, O);
+    break;
+  case 19:
+    // CDE_VCX2A_vec, CDE_VCX3_vec, MVE_VADC, MVE_VADDLVs32acc, MVE_VADDLVu32...
+    printVPTPredicateOperand(MI, 5, O);
+    break;
+  case 20:
+    // CDE_VCX3A_vec, MVE_VMLALDAVas16, MVE_VMLALDAVas32, MVE_VMLALDAVau16, M...
+    printVPTPredicateOperand(MI, 6, O);
+    break;
+  case 21:
+    // CDP2, LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2_OFFSET, LDC2_OPTION...
     printPImmediate(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 15:
+  case 22:
     // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS
     printCPSIMod(MI, 0, O);
     break;
-  case 16:
+  case 23:
     // DMB, DSB
     printMemBOption(MI, 0, O);
     return;
     break;
-  case 17:
+  case 24:
     // ISB
     printInstSyncBOption(MI, 0, O);
     return;
     break;
-  case 18:
-    // MRC2
-    printPImmediate(MI, 1, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 2, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printCImmediate(MI, 3, O);
-    SStream_concat0(O, ", ");
-    printCImmediate(MI, 4, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 5, O);
-    return;
-    break;
-  case 19:
+  case 25:
     // MRRC2
     printPImmediate(MI, 2, O);
     SStream_concat0(O, ", ");
@@ -7092,22 +9762,56 @@ static void printInstruction(MCInst *MI, SStream *O)
     printCImmediate(MI, 4, O);
     return;
     break;
-  case 20:
-    // PLDWi12, PLDi12, PLIi12
-    printAddrModeImm12Operand(MI, 0, O, false);
+  case 26:
+    // MVE_VABSf16, MVE_VABSf32, MVE_VABSs16, MVE_VABSs32, MVE_VABSs8, MVE_VA...
+    printVPTPredicateOperand(MI, 2, O);
+    break;
+  case 27:
+    // MVE_VLD20_16, MVE_VLD20_16_wb, MVE_VLD20_32, MVE_VLD20_32_wb, MVE_VLD2...
+    printMVEVectorList_2(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 28:
+    // MVE_VLD40_16, MVE_VLD40_16_wb, MVE_VLD40_32, MVE_VLD40_32_wb, MVE_VLD4...
+    printMVEVectorList_4(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 29:
+    // MVE_VPST, MVE_VPTv16i8, MVE_VPTv16i8r, MVE_VPTv16s8, MVE_VPTv16s8r, MV...
+    printVPTMask(MI, 0, O);
+    break;
+  case 30:
+    // MVE_VST20_16_wb, MVE_VST20_32_wb, MVE_VST20_8_wb, MVE_VST21_16_wb, MVE...
+    printMVEVectorList_2(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printAddrMode7Operand(MI, 2, O);
+    SStream_concat1(O, '!');
     return;
     break;
-  case 21:
+  case 31:
+    // MVE_VST40_16_wb, MVE_VST40_32_wb, MVE_VST40_8_wb, MVE_VST41_16_wb, MVE...
+    printMVEVectorList_4(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printAddrMode7Operand(MI, 2, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 32:
+    // PLDWi12, PLDi12, PLIi12
+    printAddrModeImm12Operand_0(MI, 0, O);
+    return;
+    break;
+  case 33:
     // PLDWrs, PLDrs, PLIrs
     printAddrMode2Operand(MI, 0, O);
     return;
     break;
-  case 22:
+  case 34:
     // SETEND, tSETEND
     printSetendOperand(MI, 0, O);
     return;
     break;
-  case 23:
+  case 35:
     // SMLAL, UMLAL
     printSBitModifierOperand(MI, 8, O);
     printPredicateOperand(MI, 6, O);
@@ -7121,387 +9825,285 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 3, O);
     return;
     break;
-  case 24:
+  case 36:
     // TSB
     printTraceSyncBOption(MI, 0, O);
     return;
     break;
-  case 25:
+  case 37:
     // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2...
     printPredicateOperand(MI, 7, O);
     break;
-  case 26:
+  case 38:
     // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
     printPredicateOperand(MI, 9, O);
     break;
-  case 27:
+  case 39:
     // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U...
     printPredicateOperand(MI, 11, O);
     break;
-  case 28:
+  case 40:
     // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
     printPredicateOperand(MI, 8, O);
     break;
-  case 29:
+  case 41:
     // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U...
     printPredicateOperand(MI, 13, O);
     break;
-  case 30:
-    // VSDOTD, VSDOTDI, VSDOTQ, VSDOTQI, VUDOTD, VUDOTDI, VUDOTQ, VUDOTQI
-    printOperand(MI, 1, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 2, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 3, O);
-    break;
-  case 31:
+  case 42:
     // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
     printSBitModifierOperand(MI, 1, O);
     break;
   }
 
 
-  // Fragment 1 encoded into 7 bits for 75 unique commands.
-  // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 17) & 127));
-  switch ((Bits >> 17) & 127) {
-  default: // unreachable
+  // Fragment 1 encoded into 7 bits for 89 unique commands.
+  switch ((Bits >> 19) & 127) {
+  default: assert(0 && "Invalid command number.");
   case 0:
-    // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LS...
-    SStream_concat0(O, " ");
+    // ASRi, ASRr, ITasm, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHT...
+    SStream_concat1(O, ' ');
     break;
   case 1:
     // VLD1LNdAsm_16, VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_register_Asm_16, VLD2...
     SStream_concat0(O, ".16\t");
-    ARM_addVectorDataSize(MI, 16);
     break;
   case 2:
     // VLD1LNdAsm_32, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_register_Asm_32, VLD2...
     SStream_concat0(O, ".32\t");
-    ARM_addVectorDataSize(MI, 32);
     break;
   case 3:
     // VLD1LNdAsm_8, VLD1LNdWB_fixed_Asm_8, VLD1LNdWB_register_Asm_8, VLD2LNd...
     SStream_concat0(O, ".8\t");
-    ARM_addVectorDataSize(MI, 8);
     break;
   case 4:
+    // t2LDR_POST_imm, t2LDR_PRE_imm, t2STR_POST_imm, t2STR_PRE_imm
+    SStream_concat0(O, ".w ");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 5:
     // ADCri, ADCrr, ADCrsi, ADDri, ADDrr, ADDrsi, ADR, ANDri, ANDrr, ANDrsi,...
     SStream_concat0(O, "\t");
     break;
-  case 5:
-    // AESD, AESE, AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, ...
+  case 6:
+    // AESD, AESE, AESIMC, AESMC, BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS...
     SStream_concat0(O, ", ");
     break;
-  case 6:
+  case 7:
+    // BF16_VCVT, BF16_VCVTB, BF16_VCVTT
+    SStream_concat0(O, ".bf16.f32\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 8:
     // BKPT, BL, BLX, BLXi, BX, CPS1p, ERET, HLT, HVC, RFEDA, RFEDB, RFEIA, R...
     return;
     break;
-  case 7:
+  case 9:
     // BX_RET
     SStream_concat0(O, "\tlr");
-    ARM_addReg(MI, ARM_REG_LR);
     return;
     break;
-  case 8:
+  case 10:
+    // CDE_CX1, CDE_CX2, CDE_CX3, CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX1_fp...
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 11:
+    // CDE_CX1D, CDE_CX2D, CDE_CX3D
+    printGPRPairOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    break;
+  case 12:
     // CDP2, MCR2, MCRR2
     printOperand(MI, 1, O);
     SStream_concat0(O, ", ");
     break;
-  case 9:
+  case 13:
     // FCONSTD, VABSD, VADDD, VCMPD, VCMPED, VCMPEZD, VCMPZD, VDIVD, VFMAD, V...
     SStream_concat0(O, ".f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64);
     printOperand(MI, 0, O);
     break;
-  case 10:
-    // FCONSTH, VABDhd, VABDhq, VABSH, VABShd, VABShq, VACGEhd, VACGEhq, VACG...
+  case 14:
+    // FCONSTH, MVE_VABDf16, MVE_VABSf16, MVE_VADD_qr_f16, MVE_VADDf16, MVE_V...
     SStream_concat0(O, ".f16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F16);
-    printOperand(MI, 0, O);
     break;
-  case 11:
-    // FCONSTS, VABDfd, VABDfq, VABSS, VABSfd, VABSfq, VACGEfd, VACGEfq, VACG...
+  case 15:
+    // FCONSTS, MVE_VABDf32, MVE_VABSf32, MVE_VADD_qr_f32, MVE_VADDf32, MVE_V...
     SStream_concat0(O, ".f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32);
-    printOperand(MI, 0, O);
     break;
-  case 12:
+  case 16:
     // FMSTAT
-    SStream_concat0(O, "\tapsr_nzcv, fpscr");
-    ARM_addReg(MI, ARM_REG_APSR_NZCV);
-    ARM_addReg(MI, ARM_REG_FPSCR);
+    SStream_concat0(O, "\tAPSR_nzcv, fpscr");
     return;
     break;
-  case 13:
-    // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2L_PRE, LDC2_OFFSET, LDC2_O...
+  case 17:
+    // LDC2L_OFFSET, LDC2L_OPTION, LDC2L_POST, LDC2_OFFSET, LDC2_OPTION, LDC2...
     printCImmediate(MI, 1, O);
     SStream_concat0(O, ", ");
     break;
-  case 14:
-    // MOVPCLR
-    SStream_concat0(O, "\tpc, lr");
-    ARM_addReg(MI, ARM_REG_PC);
-    ARM_addReg(MI, ARM_REG_LR);
-    return;
-    break;
-  case 15:
-    // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD
-    SStream_concat0(O, "!");
-    return;
-    break;
-  case 16:
-    // VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
-    SStream_concat0(O, ".s32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    break;
-  case 17:
-    // VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
-    SStream_concat0(O, ".s16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S16);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    break;
   case 18:
-    // VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
-    SStream_concat0(O, ".s8\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S8);
-    printOperand(MI, 0, O);
+    // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE
+    printCImmediate(MI, 2, O);
     SStream_concat0(O, ", ");
+    printAddrMode5Operand_1(MI, 3, O);
+    SStream_concat1(O, '!');
+    return;
     break;
   case 19:
-    // VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
-    SStream_concat0(O, ".u32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
+    // MOVPCLR
+    SStream_concat0(O, "\tpc, lr");
+    return;
     break;
   case 20:
-    // VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
-    SStream_concat0(O, ".u16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U16);
+    // MRC2
+    printOperand(MI, 2, O);
+    SStream_concat0(O, ", ");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
+    printCImmediate(MI, 3, O);
+    SStream_concat0(O, ", ");
+    printCImmediate(MI, 4, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 5, O);
+    return;
     break;
   case 21:
-    // VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
-    SStream_concat0(O, ".u8\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U8);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
+    // MVE_VABAVs16, MVE_VABDs16, MVE_VABSs16, MVE_VADDVs16acc, MVE_VADDVs16n...
+    SStream_concat0(O, ".s16\t");
     break;
   case 22:
-    // VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
-    SStream_concat0(O, ".i64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_I64);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
+    // MVE_VABAVs32, MVE_VABDs32, MVE_VABSs32, MVE_VADDLVs32acc, MVE_VADDLVs3...
+    SStream_concat0(O, ".s32\t");
     break;
   case 23:
-    // VADDHNv4i16, VADDv2i32, VADDv4i32, VBICiv2i32, VBICiv4i32, VCEQv2i32, ...
-    SStream_concat0(O, ".i32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_I32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
+    // MVE_VABAVs8, MVE_VABDs8, MVE_VABSs8, MVE_VADDVs8acc, MVE_VADDVs8no_acc...
+    SStream_concat0(O, ".s8\t");
     break;
   case 24:
-    // VADDHNv8i8, VADDv4i16, VADDv8i16, VBICiv4i16, VBICiv8i16, VCEQv4i16, V...
-    SStream_concat0(O, ".i16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_I16);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
+    // MVE_VABAVu16, MVE_VABDu16, MVE_VADDVu16acc, MVE_VADDVu16no_acc, MVE_VC...
+    SStream_concat0(O, ".u16\t");
     break;
   case 25:
-    // VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv...
-    SStream_concat0(O, ".i8\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_I8);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
+    // MVE_VABAVu32, MVE_VABDu32, MVE_VADDLVu32acc, MVE_VADDLVu32no_acc, MVE_...
+    SStream_concat0(O, ".u32\t");
     break;
   case 26:
-    // VCVTBDH, VCVTTDH
-    SStream_concat0(O, ".f16.f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F64);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    return;
+    // MVE_VABAVu8, MVE_VABDu8, MVE_VADDVu8acc, MVE_VADDVu8no_acc, MVE_VCMPu8...
+    SStream_concat0(O, ".u8\t");
     break;
   case 27:
-    // VCVTBHD, VCVTTHD
-    SStream_concat0(O, ".f64.f16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F16);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    return;
+    // MVE_VADC, MVE_VADCI, MVE_VADD_qr_i32, MVE_VADDi32, MVE_VBICimmi32, MVE...
+    SStream_concat0(O, ".i32\t");
     break;
   case 28:
-    // VCVTBHS, VCVTTHS, VCVTh2f
-    SStream_concat0(O, ".f32.f16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F16);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    return;
+    // MVE_VADD_qr_i16, MVE_VADDi16, MVE_VBICimmi16, MVE_VCADDi16, MVE_VCLZs1...
+    SStream_concat0(O, ".i16\t");
     break;
   case 29:
-    // VCVTBSH, VCVTTSH, VCVTf2h
-    SStream_concat0(O, ".f16.f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F16F32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    return;
+    // MVE_VADD_qr_i8, MVE_VADDi8, MVE_VCADDi8, MVE_VCLZs8, MVE_VCMPi8, MVE_V...
+    SStream_concat0(O, ".i8\t");
     break;
   case 30:
-    // VCVTDS
-    SStream_concat0(O, ".f64.f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64F32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    return;
+    // MVE_VCTP64, MVE_VSTRD64_qi, MVE_VSTRD64_qi_pre, MVE_VSTRD64_rq, MVE_VS...
+    SStream_concat0(O, ".64\t");
     break;
   case 31:
-    // VCVTSD
-    SStream_concat0(O, ".f32.f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32F64);
+    // MVE_VCVTf16f32bh, MVE_VCVTf16f32th, VCVTBSH, VCVTTSH, VCVTf2h
+    SStream_concat0(O, ".f16.f32\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    return;
     break;
   case 32:
-    // VCVTf2sd, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSIZS, VTOSLS
-    SStream_concat0(O, ".s32.f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    break;
-  case 33:
-    // VCVTf2ud, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUIZS, VTOULS
-    SStream_concat0(O, ".u32.f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    break;
-  case 34:
-    // VCVTh2sd, VCVTh2sq, VCVTh2xsd, VCVTh2xsq, VTOSHH
-    SStream_concat0(O, ".s16.f16\t");
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    break;
-  case 35:
-    // VCVTh2ud, VCVTh2uq, VCVTh2xud, VCVTh2xuq, VTOUHH
-    SStream_concat0(O, ".u16.f16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F16);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    break;
-  case 36:
-    // VCVTs2fd, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
-    SStream_concat0(O, ".f32.s32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S32);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    break;
-  case 37:
-    // VCVTs2hd, VCVTs2hq, VCVTxs2hd, VCVTxs2hq, VSHTOH
+    // MVE_VCVTf16s16_fix, MVE_VCVTf16s16n, VCVTs2hd, VCVTs2hq, VCVTxs2hd, VC...
     SStream_concat0(O, ".f16.s16\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 38:
-    // VCVTu2fd, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
+  case 33:
+    // MVE_VCVTf16u16_fix, MVE_VCVTf16u16n, VCVTu2hd, VCVTu2hq, VCVTxu2hd, VC...
+    SStream_concat0(O, ".f16.u16\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    break;
+  case 34:
+    // MVE_VCVTf32f16bh, MVE_VCVTf32f16th, VCVTBHS, VCVTTHS, VCVTh2f
+    SStream_concat0(O, ".f32.f16\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 35:
+    // MVE_VCVTf32s32_fix, MVE_VCVTf32s32n, VCVTs2fd, VCVTs2fq, VCVTxs2fd, VC...
+    SStream_concat0(O, ".f32.s32\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    break;
+  case 36:
+    // MVE_VCVTf32u32_fix, MVE_VCVTf32u32n, VCVTu2fd, VCVTu2fq, VCVTxu2fd, VC...
     SStream_concat0(O, ".f32.u32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U32);
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    break;
+  case 37:
+    // MVE_VCVTs16f16_fix, MVE_VCVTs16f16a, MVE_VCVTs16f16m, MVE_VCVTs16f16n,...
+    SStream_concat0(O, ".s16.f16\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    break;
+  case 38:
+    // MVE_VCVTs32f32_fix, MVE_VCVTs32f32a, MVE_VCVTs32f32m, MVE_VCVTs32f32n,...
+    SStream_concat0(O, ".s32.f32\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
   case 39:
-    // VCVTu2hd, VCVTu2hq, VCVTxu2hd, VCVTxu2hq, VUHTOH
-    SStream_concat0(O, ".f16.u16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U16);
+    // MVE_VCVTu16f16_fix, MVE_VCVTu16f16a, MVE_VCVTu16f16m, MVE_VCVTu16f16n,...
+    SStream_concat0(O, ".u16.f16\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
   case 40:
-    // VEXTq64, VLD1d64, VLD1d64Q, VLD1d64Qwb_fixed, VLD1d64Qwb_register, VLD...
-    SStream_concat0(O, ".64\t");
-    ARM_addVectorDataSize(MI, 64);
-    break;
-  case 41:
-    // VJCVT, VTOSIRD, VTOSIZD, VTOSLD
-    SStream_concat0(O, ".s32.f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S32F64);
+    // MVE_VCVTu32f32_fix, MVE_VCVTu32f32a, MVE_VCVTu32f32m, MVE_VCVTu32f32n,...
+    SStream_concat0(O, ".u32.f32\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
+  case 41:
+    // MVE_VLD20_16, MVE_VLD20_32, MVE_VLD20_8, MVE_VLD21_16, MVE_VLD21_32, M...
+    printAddrMode7Operand(MI, 2, O);
+    return;
+    break;
   case 42:
-    // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq...
-    SStream_concat0(O, ".16\t{");
-    ARM_addVectorDataSize(MI, 16);
+    // MVE_VLD20_16_wb, MVE_VLD20_32_wb, MVE_VLD20_8_wb, MVE_VLD21_16_wb, MVE...
+    printAddrMode7Operand(MI, 3, O);
+    SStream_concat1(O, '!');
+    return;
     break;
   case 43:
-    // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq...
-    SStream_concat0(O, ".32\t{");
-    ARM_addVectorDataSize(MI, 32);
+    // MVE_VLDRDU64_qi, MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq, MVE_VLDRDU64_rq...
+    SStream_concat0(O, ".u64\t");
     break;
   case 44:
-    // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U...
-    SStream_concat0(O, ".8\t{");
-    ARM_addVectorDataSize(MI, 8);
+    // MVE_VMOVimmi64, VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i...
+    SStream_concat0(O, ".i64\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
     break;
   case 45:
-    // VMSR
-    SStream_concat0(O, "\tfpscr, ");
-    ARM_addReg(MI, ARM_REG_FPSCR);
-    printOperand(MI, 0, O);
-    return;
-    break;
-  case 46:
-    // VMSR_FPEXC
-    SStream_concat0(O, "\tfpexc, ");
-    ARM_addReg(MI, ARM_REG_FPEXC);
-    printOperand(MI, 0, O);
-    return;
-    break;
-  case 47:
-    // VMSR_FPINST
-    SStream_concat0(O, "\tfpinst, ");
-    ARM_addReg(MI, ARM_REG_FPINST);
-    printOperand(MI, 0, O);
-    return;
-    break;
-  case 48:
-    // VMSR_FPINST2
-    SStream_concat0(O, "\tfpinst2, ");
-    ARM_addReg(MI, ARM_REG_FPINST2);
-    printOperand(MI, 0, O);
-    return;
-    break;
-  case 49:
-    // VMSR_FPSID
-    SStream_concat0(O, "\tfpsid, ");
-    ARM_addReg(MI, ARM_REG_FPSID);
-    printOperand(MI, 0, O);
-    return;
-    break;
-  case 50:
-    // VMULLp8, VMULpd, VMULpq
-    SStream_concat0(O, ".p8\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_P8);
+    // MVE_VMULLBp16, MVE_VMULLTp16
+    SStream_concat0(O, ".p16\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7509,40 +10111,134 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 2, O);
     return;
     break;
-  case 51:
-    // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
-    SStream_concat0(O, ".s64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S64);
+  case 46:
+    // MVE_VMULLBp8, MVE_VMULLTp8, VMULLp8, VMULpd, VMULpq
+    SStream_concat0(O, ".p8\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    return;
+    break;
+  case 47:
+    // MVE_VST20_16, MVE_VST20_32, MVE_VST20_8, MVE_VST21_16, MVE_VST21_32, M...
+    printAddrMode7Operand(MI, 1, O);
+    return;
+    break;
+  case 48:
+    // RFEDA_UPD, RFEDB_UPD, RFEIA_UPD, RFEIB_UPD
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 49:
+    // VCVTBDH, VCVTTDH
+    SStream_concat0(O, ".f16.f64\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    return;
+    break;
+  case 50:
+    // VCVTBHD, VCVTTHD
+    SStream_concat0(O, ".f64.f16\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
+    break;
+  case 51:
+    // VCVTDS
+    SStream_concat0(O, ".f64.f32\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
     break;
   case 52:
-    // VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
-    SStream_concat0(O, ".u64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U64);
+    // VCVTSD
+    SStream_concat0(O, ".f32.f64\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    return;
     break;
   case 53:
-    // VSDOTDI, VSDOTQI, VUDOTDI, VUDOTQI
-    printVectorIndex(MI, 4, O);
-    return;
+    // VJCVT, VTOSIRD, VTOSIZD, VTOSLD
+    SStream_concat0(O, ".s32.f64\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
     break;
   case 54:
-    // VSHTOD
-    SStream_concat0(O, ".f64.s16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S16);
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 1, O);
-    SStream_concat0(O, ", ");
-    printFBits16(MI, 2, O);
-    return;
+    // VLD1LNd16, VLD1LNd16_UPD, VLD2LNd16, VLD2LNd16_UPD, VLD2LNq16, VLD2LNq...
+    SStream_concat0(O, ".16\t{");
     break;
   case 55:
-    // VSHTOS
-    SStream_concat0(O, ".f32.s16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32S16);
+    // VLD1LNd32, VLD1LNd32_UPD, VLD2LNd32, VLD2LNd32_UPD, VLD2LNq32, VLD2LNq...
+    SStream_concat0(O, ".32\t{");
+    break;
+  case 56:
+    // VLD1LNd8, VLD1LNd8_UPD, VLD2LNd8, VLD2LNd8_UPD, VLD3DUPd8, VLD3DUPd8_U...
+    SStream_concat0(O, ".8\t{");
+    break;
+  case 57:
+    // VLDR_FPCXTNS_off, VLDR_FPCXTNS_post, VLDR_FPCXTNS_pre, VMSR_FPCXTNS, V...
+    SStream_concat0(O, "\tfpcxtns, ");
+    break;
+  case 58:
+    // VLDR_FPCXTS_off, VLDR_FPCXTS_post, VLDR_FPCXTS_pre, VMSR_FPCXTS, VSTR_...
+    SStream_concat0(O, "\tfpcxts, ");
+    break;
+  case 59:
+    // VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_NZCVQC_post, VLDR_FPSCR_NZCVQC_pre, ...
+    SStream_concat0(O, "\tfpscr_nzcvqc, ");
+    break;
+  case 60:
+    // VLDR_FPSCR_off, VLDR_FPSCR_post, VLDR_FPSCR_pre, VMSR, VSTR_FPSCR_off,...
+    SStream_concat0(O, "\tfpscr, ");
+    break;
+  case 61:
+    // VLDR_P0_off, VLDR_P0_post, VLDR_P0_pre, VMSR_P0, VSTR_P0_off, VSTR_P0_...
+    SStream_concat0(O, "\tp0, ");
+    break;
+  case 62:
+    // VLDR_VPR_off, VLDR_VPR_post, VLDR_VPR_pre, VMSR_VPR, VSTR_VPR_off, VST...
+    SStream_concat0(O, "\tvpr, ");
+    break;
+  case 63:
+    // VMSR_FPEXC
+    SStream_concat0(O, "\tfpexc, ");
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 64:
+    // VMSR_FPINST
+    SStream_concat0(O, "\tfpinst, ");
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 65:
+    // VMSR_FPINST2
+    SStream_concat0(O, "\tfpinst2, ");
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 66:
+    // VMSR_FPSID
+    SStream_concat0(O, "\tfpsid, ");
+    printOperand(MI, 0, O);
+    return;
+    break;
+  case 67:
+    // VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
+    SStream_concat0(O, ".s64\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 68:
+    // VSHTOD
+    SStream_concat0(O, ".f64.s16\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7550,25 +10246,33 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 56:
+  case 69:
+    // VSHTOS
+    SStream_concat0(O, ".f32.s16\t");
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printFBits16(MI, 2, O);
+    return;
+    break;
+  case 70:
     // VSITOD, VSLTOD
     SStream_concat0(O, ".f64.s32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64S32);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 57:
+  case 71:
     // VSITOH, VSLTOH
     SStream_concat0(O, ".f16.s32\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 58:
+  case 72:
     // VTOSHD
     SStream_concat0(O, ".s16.f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F64);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7576,10 +10280,9 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 59:
+  case 73:
     // VTOSHS
     SStream_concat0(O, ".s16.f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_S16F32);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7587,17 +10290,16 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 60:
+  case 74:
     // VTOSIRH, VTOSIZH, VTOSLH
     SStream_concat0(O, ".s32.f16\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 61:
+  case 75:
     // VTOUHD
     SStream_concat0(O, ".u16.f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F64);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7605,10 +10307,9 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 62:
+  case 76:
     // VTOUHS
     SStream_concat0(O, ".u16.f32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U16F32);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7616,26 +10317,23 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 63:
+  case 77:
     // VTOUIRD, VTOUIZD, VTOULD
     SStream_concat0(O, ".u32.f64\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F64);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 64:
+  case 78:
     // VTOUIRH, VTOUIZH, VTOULH
     SStream_concat0(O, ".u32.f16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_U32F16);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 65:
+  case 79:
     // VUHTOD
     SStream_concat0(O, ".f64.u16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U16);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7643,10 +10341,9 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 66:
+  case 80:
     // VUHTOS
     SStream_concat0(O, ".f32.u16\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F32U16);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
@@ -7654,54 +10351,50 @@ static void printInstruction(MCInst *MI, SStream *O)
     printFBits16(MI, 2, O);
     return;
     break;
-  case 67:
+  case 81:
     // VUITOD, VULTOD
     SStream_concat0(O, ".f64.u32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F64U32);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 68:
+  case 82:
     // VUITOH, VULTOH
     SStream_concat0(O, ".f16.u32\t");
-    ARM_addVectorDataType(MI, ARM_VECTORDATA_F16U32);
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     break;
-  case 69:
-    // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADR, t2ANDrr, t2ANDrs, ...
+  case 83:
+    // t2ADCrr, t2ADCrs, t2ADDri, t2ADDrr, t2ADDrs, t2ADDspImm, t2ADR, t2ANDr...
     SStream_concat0(O, ".w\t");
     break;
-  case 70:
+  case 84:
     // t2SRSDB, t2SRSIA
     SStream_concat0(O, "\tsp, ");
-    ARM_addReg(MI, ARM_REG_SP);
     printOperand(MI, 0, O);
     return;
     break;
-  case 71:
+  case 85:
     // t2SRSDB_UPD, t2SRSIA_UPD
     SStream_concat0(O, "\tsp!, ");
-    ARM_addReg(MI, ARM_REG_SP);
     printOperand(MI, 0, O);
     return;
     break;
-  case 72:
+  case 86:
     // t2SUBS_PC_LR
     SStream_concat0(O, "\tpc, lr, ");
     printOperand(MI, 0, O);
     return;
     break;
-  case 73:
+  case 87:
     // tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
     printPredicateOperand(MI, 4, O);
     SStream_concat0(O, "\t");
     printOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 74:
+  case 88:
     // tMOVi8, tMVN, tRSB
     printPredicateOperand(MI, 3, O);
     SStream_concat0(O, "\t");
@@ -7712,12 +10405,11 @@ static void printInstruction(MCInst *MI, SStream *O)
   }
 
 
-  // Fragment 2 encoded into 6 bits for 60 unique commands.
-  // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 24) & 63));
-  switch ((Bits >> 24) & 63) {
-  default: // unreachable
+  // Fragment 2 encoded into 7 bits for 69 unique commands.
+  switch ((Bits >> 26) & 127) {
+  default: assert(0 && "Invalid command number.");
   case 0:
-    // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR...
+    // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR...
     printOperand(MI, 0, O);
     break;
   case 1:
@@ -7772,19 +10464,50 @@ static void printInstruction(MCInst *MI, SStream *O)
     printAddrMode6Operand(MI, 1, O);
     break;
   case 10:
-    // AESD, AESE, MCR2, MCRR2, SHA1C, SHA1M, SHA1P, SHA1SU0, SHA1SU1, SHA256...
-    printOperand(MI, 2, O);
+    // t2LDR_POST_imm, t2STR_POST_imm, VLDR_FPCXTNS_post, VLDR_FPCXTS_post, V...
+    printAddrMode7Operand(MI, 1, O);
     break;
   case 11:
-    // AESIMC, AESMC, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, FLDM...
-    printOperand(MI, 1, O);
+    // t2LDR_PRE_imm, t2STR_PRE_imm
+    printT2AddrModeImm8Operand_1(MI, 1, O);
+    SStream_concat1(O, '!');
+    return;
     break;
   case 12:
-    // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OP...
+    // AESD, AESE, BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, BF16VDOTS_VDOTD, BF16VDO...
+    printOperand(MI, 2, O);
+    break;
+  case 13:
+    // AESIMC, AESMC, BF16_VCVT, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, C...
+    printOperand(MI, 1, O);
+    break;
+  case 14:
+    // BL_pred, Bcc, t2B, t2BFLi, t2BFLr, t2BFi, t2BFr, t2Bcc, tB, tBcc
+    printOperandAddr(MI, Address, 0, O);
+    break;
+  case 15:
+    // CDE_CX1A, CDE_CX1DA, CDE_CX2A, CDE_CX2DA, CDE_CX3A, CDE_CX3DA, CDE_VCX...
+    printPImmediate(MI, 1, O);
+    SStream_concat0(O, ", ");
+    break;
+  case 16:
+    // CDE_CX1D, MVE_LCTP, MVE_VCVTf16s16n, MVE_VCVTf16u16n, MVE_VCVTf32s32n,...
+    return;
+    break;
+  case 17:
+    // CDE_CX2D, CDE_CX3D, FCONSTD, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, M...
+    SStream_concat0(O, ", ");
+    break;
+  case 18:
+    // CDE_VCX1A_fpdp, CDE_VCX1A_fpsp, CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VC...
+    printOperand(MI, 3, O);
+    break;
+  case 19:
+    // CDP, LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDC_OFFSET, LDC_OPTION, LDC_...
     printPImmediate(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 13:
+  case 20:
     // CDP2
     printCImmediate(MI, 2, O);
     SStream_concat0(O, ", ");
@@ -7795,53 +10518,27 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 5, O);
     return;
     break;
-  case 14:
+  case 21:
     // CPS2p, CPS3p, t2CPS2p, t2CPS3p, tCPS
     printCPSIFlag(MI, 1, O);
     break;
-  case 15:
-    // FCONSTD, FCONSTH, FCONSTS, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABS...
-    SStream_concat0(O, ", ");
-    break;
-  case 16:
+  case 22:
     // LDAEXD, LDREXD
     printGPRPairOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printAddrMode7Operand(MI, 1, O);
     return;
     break;
-  case 17:
+  case 23:
     // LDC2L_OFFSET, LDC2_OFFSET, STC2L_OFFSET, STC2_OFFSET
-    printAddrMode5Operand(MI, 2, O, false);
+    printAddrMode5Operand_0(MI, 2, O);
     return;
     break;
-  case 18:
+  case 24:
     // LDC2L_OPTION, LDC2L_POST, LDC2_OPTION, LDC2_POST, STC2L_OPTION, STC2L_...
     printAddrMode7Operand(MI, 2, O);
-    SStream_concat0(O, ", ");
     break;
-  case 19:
-    // LDC2L_PRE, LDC2_PRE, STC2L_PRE, STC2_PRE
-    printAddrMode5Operand(MI, 2, O, true);
-    SStream_concat0(O, "!");
-    return;
-    break;
-  case 20:
-    // MRC, t2MRC, t2MRC2
-    printPImmediate(MI, 1, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 2, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 0, O);
-    SStream_concat0(O, ", ");
-    printCImmediate(MI, 3, O);
-    SStream_concat0(O, ", ");
-    printCImmediate(MI, 4, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 5, O);
-    return;
-    break;
-  case 21:
+  case 25:
     // MRRC, t2MRRC, t2MRRC2
     printPImmediate(MI, 2, O);
     SStream_concat0(O, ", ");
@@ -7854,90 +10551,126 @@ static void printInstruction(MCInst *MI, SStream *O)
     printCImmediate(MI, 4, O);
     return;
     break;
-  case 22:
+  case 26:
     // MSR, MSRi, t2MSR_AR, t2MSR_M
     printMSRMaskOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 23:
+  case 27:
     // MSRbanked, t2MSRbanked
     printBankedRegOperand(MI, 0, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 1, O);
     return;
     break;
-  case 24:
-    // VBICiv2i32, VBICiv4i16, VBICiv4i32, VBICiv8i16, VMOVv16i8, VMOVv1i64, ...
-    printNEONModImmOperand(MI, 1, O);
+  case 28:
+    // MVE_LETP, t2LEUpdate, tBL, tBLXi
+    printOperandAddr(MI, Address, 2, O);
     return;
     break;
-  case 25:
-    // VCMPEZD, VCMPEZH, VCMPEZS, VCMPZD, VCMPZH, VCMPZS, tRSB
+  case 29:
+    // MVE_VCMPf16, MVE_VCMPf16r, MVE_VCMPf32, MVE_VCMPf32r, MVE_VCMPi16, MVE...
+    printMandatoryRestrictedPredicateOperand(MI, 3, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    return;
+    break;
+  case 30:
+    // MVE_VMOVimmi64, VMOVv1i64, VMOVv2i64
+    printVMOVModImmOperand(MI, 1, O);
+    return;
+    break;
+  case 31:
+    // VCMPEZD, VCMPZD, tRSB
     SStream_concat0(O, ", #0");
-    op_addImm(MI, 0);
     return;
     break;
-  case 26:
-    // VCVTf2sd, VCVTf2sq, VCVTf2ud, VCVTf2uq, VCVTh2sd, VCVTh2sq, VCVTh2ud, ...
-    return;
-    break;
-  case 27:
+  case 32:
     // VLD1DUPd16, VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32, VLD...
     printVectorListOneAllLanes(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 28:
+  case 33:
     // VLD1DUPq16, VLD1DUPq16wb_fixed, VLD1DUPq16wb_register, VLD1DUPq32, VLD...
     printVectorListTwoAllLanes(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 29:
+  case 34:
     // VLD1d16, VLD1d16wb_fixed, VLD1d16wb_register, VLD1d32, VLD1d32wb_fixed...
     printVectorListOne(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 30:
+  case 35:
     // VLD1q16, VLD1q16wb_fixed, VLD1q16wb_register, VLD1q32, VLD1q32wb_fixed...
     printVectorListTwo(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 31:
+  case 36:
     // VLD2DUPd16x2, VLD2DUPd16x2wb_fixed, VLD2DUPd16x2wb_register, VLD2DUPd3...
     printVectorListTwoSpacedAllLanes(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 32:
+  case 37:
     // VLD2b16, VLD2b16wb_fixed, VLD2b16wb_register, VLD2b32, VLD2b32wb_fixed...
     printVectorListTwoSpaced(MI, 0, O);
     SStream_concat0(O, ", ");
     break;
-  case 33:
+  case 38:
+    // VLDR_FPCXTNS_off, VLDR_FPCXTS_off, VLDR_FPSCR_NZCVQC_off, VLDR_FPSCR_o...
+    printT2AddrModeImm8s4Operand_0(MI, 0, O);
+    return;
+    break;
+  case 39:
+    // VLDR_FPCXTNS_pre, VLDR_FPCXTS_pre, VLDR_FPSCR_NZCVQC_pre, VLDR_FPSCR_p...
+    printT2AddrModeImm8s4Operand_1(MI, 1, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 40:
+    // VLDR_P0_off, VSTR_P0_off
+    printT2AddrModeImm8s4Operand_0(MI, 1, O);
+    return;
+    break;
+  case 41:
+    // VLDR_P0_pre, VSTR_P0_pre
+    printT2AddrModeImm8s4Operand_1(MI, 2, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 42:
+    // VSCCLRMD, VSCCLRMS, t2CLRM, tPOP, tPUSH
+    printRegisterList(MI, 2, O);
+    return;
+    break;
+  case 43:
     // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST2LNd16_UPD, VST2LNd32_U...
     printOperand(MI, 4, O);
     break;
-  case 34:
+  case 44:
     // VST1d16, VST1d32, VST1d64, VST1d8
     printVectorListOne(MI, 2, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 0, O);
     return;
     break;
-  case 35:
+  case 45:
     // VST1d16Q, VST1d32Q, VST1d64Q, VST1d8Q, VST2q16, VST2q32, VST2q8
     printVectorListFour(MI, 2, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 0, O);
     return;
     break;
-  case 36:
+  case 46:
     // VST1d16Qwb_fixed, VST1d32Qwb_fixed, VST1d64Qwb_fixed, VST1d8Qwb_fixed,...
     printVectorListFour(MI, 3, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 1, O);
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
-  case 37:
+  case 47:
     // VST1d16Qwb_register, VST1d32Qwb_register, VST1d64Qwb_register, VST1d8Q...
     printVectorListFour(MI, 4, O);
     SStream_concat0(O, ", ");
@@ -7946,22 +10679,22 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 3, O);
     return;
     break;
-  case 38:
+  case 48:
     // VST1d16T, VST1d32T, VST1d64T, VST1d8T
     printVectorListThree(MI, 2, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 0, O);
     return;
     break;
-  case 39:
+  case 49:
     // VST1d16Twb_fixed, VST1d32Twb_fixed, VST1d64Twb_fixed, VST1d8Twb_fixed
     printVectorListThree(MI, 3, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 1, O);
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
-  case 40:
+  case 50:
     // VST1d16Twb_register, VST1d32Twb_register, VST1d64Twb_register, VST1d8T...
     printVectorListThree(MI, 4, O);
     SStream_concat0(O, ", ");
@@ -7970,15 +10703,15 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 3, O);
     return;
     break;
-  case 41:
+  case 51:
     // VST1d16wb_fixed, VST1d32wb_fixed, VST1d64wb_fixed, VST1d8wb_fixed
     printVectorListOne(MI, 3, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 1, O);
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
-  case 42:
+  case 52:
     // VST1d16wb_register, VST1d32wb_register, VST1d64wb_register, VST1d8wb_r...
     printVectorListOne(MI, 4, O);
     SStream_concat0(O, ", ");
@@ -7987,22 +10720,22 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 3, O);
     return;
     break;
-  case 43:
+  case 53:
     // VST1q16, VST1q32, VST1q64, VST1q8, VST2d16, VST2d32, VST2d8
     printVectorListTwo(MI, 2, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 0, O);
     return;
     break;
-  case 44:
+  case 54:
     // VST1q16wb_fixed, VST1q32wb_fixed, VST1q64wb_fixed, VST1q8wb_fixed, VST...
     printVectorListTwo(MI, 3, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 1, O);
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
-  case 45:
+  case 55:
     // VST1q16wb_register, VST1q32wb_register, VST1q64wb_register, VST1q8wb_r...
     printVectorListTwo(MI, 4, O);
     SStream_concat0(O, ", ");
@@ -8011,22 +10744,22 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 3, O);
     return;
     break;
-  case 46:
+  case 56:
     // VST2b16, VST2b32, VST2b8
     printVectorListTwoSpaced(MI, 2, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 0, O);
     return;
     break;
-  case 47:
+  case 57:
     // VST2b16wb_fixed, VST2b32wb_fixed, VST2b8wb_fixed
     printVectorListTwoSpaced(MI, 3, O);
     SStream_concat0(O, ", ");
     printAddrMode6Operand(MI, 1, O);
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
-  case 48:
+  case 58:
     // VST2b16wb_register, VST2b32wb_register, VST2b8wb_register
     printVectorListTwoSpaced(MI, 4, O);
     SStream_concat0(O, ", ");
@@ -8035,70 +10768,63 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 3, O);
     return;
     break;
-  case 49:
+  case 59:
+    // t2BFic, tCBNZ, tCBZ
+    printOperandAddr(MI, Address, 1, O);
+    break;
+  case 60:
     // t2DMB, t2DSB
     printMemBOption(MI, 0, O);
     return;
     break;
-  case 50:
+  case 61:
     // t2ISB
     printInstSyncBOption(MI, 0, O);
     return;
     break;
-  case 51:
+  case 62:
     // t2PLDWi12, t2PLDi12, t2PLIi12
-    printAddrModeImm12Operand(MI, 0, O, false);
+    printAddrModeImm12Operand_0(MI, 0, O);
     return;
     break;
-  case 52:
+  case 63:
     // t2PLDWi8, t2PLDi8, t2PLIi8
-    printT2AddrModeImm8Operand(MI, 0, O, false);
+    printT2AddrModeImm8Operand_0(MI, 0, O);
     return;
     break;
-  case 53:
+  case 64:
     // t2PLDWs, t2PLDs, t2PLIs
     printT2AddrModeSoRegOperand(MI, 0, O);
     return;
     break;
-  case 54:
+  case 65:
     // t2PLDpci, t2PLIpci
     printThumbLdrLabelOperand(MI, 0, O);
     return;
     break;
-  case 55:
+  case 66:
     // t2TBB
     printAddrModeTBB(MI, 0, O);
     return;
     break;
-  case 56:
+  case 67:
     // t2TBH
     printAddrModeTBH(MI, 0, O);
     return;
     break;
-  case 57:
+  case 68:
     // t2TSB
     printTraceSyncBOption(MI, 0, O);
     return;
     break;
-  case 58:
-    // tADC, tADDi8, tAND, tASRrr, tBIC, tEOR, tLSLrr, tLSRrr, tORR, tROR, tS...
-    printOperand(MI, 3, O);
-    return;
-    break;
-  case 59:
-    // tPOP, tPUSH
-    printRegisterList(MI, 2, O);
-    return;
-    break;
   }
 
 
-  // Fragment 3 encoded into 5 bits for 30 unique commands.
-  // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 30) & 31));
-  switch ((Bits >> 30) & 31) {
-  default: // unreachable
+  // Fragment 3 encoded into 6 bits for 39 unique commands.
+  switch ((Bits >> 33) & 63) {
+  default: assert(0 && "Invalid command number.");
   case 0:
-    // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRT_POST, LSLi, LSLr, LSRi, LSR...
+    // ASRi, ASRr, LDRBT_POST, LDRConstPool, LDRHTii, LDRSBTii, LDRSHTii, LDR...
     SStream_concat0(O, ", ");
     break;
   case 1:
@@ -8107,7 +10833,7 @@ static void printInstruction(MCInst *MI, SStream *O)
     break;
   case 2:
     // VLD3DUPdWB_fixed_Asm_16, VLD3DUPdWB_fixed_Asm_32, VLD3DUPdWB_fixed_Asm...
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
   case 3:
@@ -8115,143 +10841,186 @@ static void printInstruction(MCInst *MI, SStream *O)
     printAddrMode6Operand(MI, 1, O);
     break;
   case 4:
-    // CDP, MCR, MCRR, MSR, VABDfd, VABDfq, VABDhd, VABDhq, VABSD, VABSH, VAB...
-    printOperand(MI, 1, O);
+    // CDE_CX1A, CDE_CX2A, CDE_CX3A, CDE_VCX1A_vec, CDE_VCX1_vec, CDE_VCX2A_v...
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
     break;
   case 5:
-    // FCONSTD, FCONSTH, FCONSTS, VMOVv2f32, VMOVv4f32
+    // CDE_CX1DA, CDE_CX2DA, CDE_CX3DA
+    printGPRPairOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 3, O);
+    break;
+  case 6:
+    // CDE_CX2D, CDE_CX3D
+    printOperand(MI, 3, O);
+    break;
+  case 7:
+    // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,...
+    printOperand(MI, 1, O);
+    break;
+  case 8:
+    // FCONSTD
     printFPImmOperand(MI, 1, O);
     return;
     break;
-  case 6:
+  case 9:
     // FLDMXDB_UPD, FLDMXIA_UPD, FSTMXDB_UPD, FSTMXIA_UPD, LDMDA_UPD, LDMDB_U...
     SStream_concat0(O, "!, ");
     printRegisterList(MI, 4, O);
     break;
-  case 7:
-    // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION
-    printCoprocOptionImm(MI, 3, O);
-    return;
-    break;
-  case 8:
-    // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST
-    printPostIdxImm8s4Operand(MI, 3, O);
-    return;
-    break;
-  case 9:
-    // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDCL_PRE, LDC_OFFSET, LDC_OPTION,...
+  case 10:
+    // LDCL_OFFSET, LDCL_OPTION, LDCL_POST, LDC_OFFSET, LDC_OPTION, LDC_POST,...
     printCImmediate(MI, 1, O);
     SStream_concat0(O, ", ");
     break;
-  case 10:
-    // MRS, t2MRS_AR
-    SStream_concat0(O, ", apsr");
-    ARM_addReg(MI, ARM_REG_APSR);
-    return;
-    break;
   case 11:
-    // MRSsys, t2MRSsys_AR
-    SStream_concat0(O, ", spsr");
-    ARM_addReg(MI, ARM_REG_SPSR);
+    // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_...
+    printCImmediate(MI, 2, O);
+    SStream_concat0(O, ", ");
+    printAddrMode5Operand_1(MI, 3, O);
+    SStream_concat1(O, '!');
     return;
     break;
   case 12:
+    // MRC, MVE_VCVTf16s16_fix, MVE_VCVTf16u16_fix, MVE_VCVTf32s32_fix, MVE_V...
+    printOperand(MI, 2, O);
+    break;
+  case 13:
+    // MRS, t2MRS_AR
+    SStream_concat0(O, ", apsr");
+    return;
+    break;
+  case 14:
+    // MRSsys, t2MRSsys_AR
+    SStream_concat0(O, ", spsr");
+    return;
+    break;
+  case 15:
     // MSRi
     printModImmOperand(MI, 1, O);
     return;
     break;
-  case 13:
-    // VCEQzv16i8, VCEQzv2i32, VCEQzv4i16, VCEQzv4i32, VCEQzv8i16, VCEQzv8i8,...
-    SStream_concat0(O, ", #0");
-    op_addImm(MI, 0);
-    return;
-    break;
-  case 14:
-    // VCVTf2xsd, VCVTf2xsq, VCVTf2xud, VCVTf2xuq, VCVTh2xsd, VCVTh2xsq, VCVT...
-    printOperand(MI, 2, O);
-    break;
-  case 15:
-    // VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8
-    printVectorIndex(MI, 2, O);
-    return;
-    break;
   case 16:
+    // MVE_VMOV_q_rr
+    printVectorIndex(MI, 4, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 1, O);
+    printVectorIndex(MI, 5, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 3, O);
+    return;
+    break;
+  case 17:
+    // MVE_VMOV_to_lane_16, MVE_VMOV_to_lane_32, MVE_VMOV_to_lane_8, VSETLNi1...
+    printVectorIndex(MI, 3, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    return;
+    break;
+  case 18:
+    // VCMPEZH, VCMPEZS, VCMPZH, VCMPZS
+    SStream_concat0(O, ", #0");
+    return;
+    break;
+  case 19:
     // VLD1DUPd16wb_fixed, VLD1DUPd16wb_register, VLD1DUPd32wb_fixed, VLD1DUP...
     printAddrMode6Operand(MI, 2, O);
     break;
-  case 17:
+  case 20:
     // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8...
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     break;
-  case 18:
+  case 21:
     // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD...
     SStream_concat0(O, "[], ");
     printOperand(MI, 1, O);
     SStream_concat0(O, "[], ");
     printOperand(MI, 2, O);
     break;
-  case 19:
-    // VMRS
-    SStream_concat0(O, ", fpscr");
-    ARM_addReg(MI, ARM_REG_FPSCR);
-    return;
-    break;
-  case 20:
-    // VMRS_FPEXC
-    SStream_concat0(O, ", fpexc");
-    ARM_addReg(MI, ARM_REG_FPEXC);
-    return;
-    break;
-  case 21:
-    // VMRS_FPINST
-    SStream_concat0(O, ", fpinst");
-    ARM_addReg(MI, ARM_REG_FPINST);
-    return;
-    break;
   case 22:
-    // VMRS_FPINST2
-    SStream_concat0(O, ", fpinst2");
-    ARM_addReg(MI, ARM_REG_FPINST2);
+    // VLDR_FPCXTNS_post, VLDR_FPCXTS_post, VLDR_FPSCR_NZCVQC_post, VLDR_FPSC...
+    printT2AddrModeImm8s4OffsetOperand(MI, 2, O);
     return;
     break;
   case 23:
-    // VMRS_FPSID
-    SStream_concat0(O, ", fpsid");
-    ARM_addReg(MI, ARM_REG_FPSID);
+    // VLDR_P0_post, VSTR_P0_post
+    printT2AddrModeImm8s4OffsetOperand(MI, 3, O);
     return;
     break;
   case 24:
-    // VMRS_MVFR0
-    SStream_concat0(O, ", mvfr0");
-    ARM_addReg(MI, ARM_REG_MVFR0);
+    // VMRS
+    SStream_concat0(O, ", fpscr");
     return;
     break;
   case 25:
-    // VMRS_MVFR1
-    SStream_concat0(O, ", mvfr1");
-    ARM_addReg(MI, ARM_REG_MVFR1);
+    // VMRS_FPCXTNS
+    SStream_concat0(O, ", fpcxtns");
     return;
     break;
   case 26:
-    // VMRS_MVFR2
-    SStream_concat0(O, ", mvfr2");
-    ARM_addReg(MI, ARM_REG_MVFR2);
+    // VMRS_FPCXTS
+    SStream_concat0(O, ", fpcxts");
     return;
     break;
   case 27:
-    // VSETLNi16, VSETLNi32, VSETLNi8
-    printVectorIndex(MI, 3, O);
-    SStream_concat0(O, ", ");
-    printOperand(MI, 2, O);
+    // VMRS_FPEXC
+    SStream_concat0(O, ", fpexc");
     return;
     break;
   case 28:
+    // VMRS_FPINST
+    SStream_concat0(O, ", fpinst");
+    return;
+    break;
+  case 29:
+    // VMRS_FPINST2
+    SStream_concat0(O, ", fpinst2");
+    return;
+    break;
+  case 30:
+    // VMRS_FPSCR_NZCVQC
+    SStream_concat0(O, ", fpscr_nzcvqc");
+    return;
+    break;
+  case 31:
+    // VMRS_FPSID
+    SStream_concat0(O, ", fpsid");
+    return;
+    break;
+  case 32:
+    // VMRS_MVFR0
+    SStream_concat0(O, ", mvfr0");
+    return;
+    break;
+  case 33:
+    // VMRS_MVFR1
+    SStream_concat0(O, ", mvfr1");
+    return;
+    break;
+  case 34:
+    // VMRS_MVFR2
+    SStream_concat0(O, ", mvfr2");
+    return;
+    break;
+  case 35:
+    // VMRS_P0
+    SStream_concat0(O, ", p0");
+    return;
+    break;
+  case 36:
+    // VMRS_VPR
+    SStream_concat0(O, ", vpr");
+    return;
+    break;
+  case 37:
     // VSHTOH, VTOSHH, VTOUHH, VUHTOH
     printFBits16(MI, 2, O);
     return;
     break;
-  case 29:
+  case 38:
     // VSLTOD, VSLTOH, VSLTOS, VTOSLD, VTOSLH, VTOSLS, VTOULD, VTOULH, VTOULS...
     printFBits32(MI, 2, O);
     return;
@@ -8259,16 +11028,15 @@ static void printInstruction(MCInst *MI, SStream *O)
   }
 
 
-  // Fragment 4 encoded into 7 bits for 65 unique commands.
-  // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 35) & 127));
-  switch ((Bits >> 35) & 127) {
-  default: // unreachable
+  // Fragment 4 encoded into 7 bits for 77 unique commands.
+  switch ((Bits >> 39) & 127) {
+  default: assert(0 && "Invalid command number.");
   case 0:
     // ASRi, ASRr, LDRConstPool, LSLi, LSLr, LSRi, LSRr, RORi, RORr, RRXi, t2...
     printOperand(MI, 1, O);
     break;
   case 1:
-    // LDRBT_POST, LDRT_POST, STRBT_POST, STRT_POST, LDA, LDAB, LDAEX, LDAEXB...
+    // LDRBT_POST, LDRHTii, LDRSBTii, LDRSHTii, LDRT_POST, STRBT_POST, STRT_P...
     printAddrMode7Operand(MI, 1, O);
     return;
     break;
@@ -8286,7 +11054,7 @@ static void printInstruction(MCInst *MI, SStream *O)
     break;
   case 5:
     // VLD3dWB_fixed_Asm_16, VLD3dWB_fixed_Asm_32, VLD3dWB_fixed_Asm_8, VLD4d...
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
   case 6:
@@ -8294,92 +11062,110 @@ static void printInstruction(MCInst *MI, SStream *O)
     SStream_concat0(O, ", ");
     break;
   case 7:
+    // t2LDR_POST_imm, t2STR_POST_imm
+    printT2AddrModeImm8OffsetOperand(MI, 2, O);
+    return;
+    break;
+  case 8:
     // t2MOVSsi, t2MOVsi, t2CMNzrs, t2CMPrs, t2MVNs, t2TEQrs, t2TSTrs
     printT2SOOperand(MI, 1, O);
     return;
     break;
-  case 8:
+  case 9:
     // t2MOVSsr, t2MOVsr, CMNzrsr, CMPrsr, MOVsr, MVNsr, TEQrsr, TSTrsr
     printSORegRegOperand(MI, 1, O);
     return;
     break;
-  case 9:
+  case 10:
     // ADR, t2ADR
-    printAdrLabelOperand(MI, 1, O, 0);
+    printAdrLabelOperand_0(MI, 1, O);
     return;
     break;
-  case 10:
+  case 11:
     // BFC, t2BFC
     printBitfieldInvMaskImmOperand(MI, 2, O);
     return;
     break;
-  case 11:
-    // BFI, CPS3p, CRC32B, CRC32CB, CRC32CH, CRC32CW, CRC32H, CRC32W, MOVTi16...
+  case 12:
+    // BFI, CDE_VCX1_vec, CDE_VCX2_vec, CDE_VCX3_vec, CPS3p, CRC32B, CRC32CB,...
     printOperand(MI, 2, O);
     break;
-  case 12:
+  case 13:
+    // CDE_VCX2A_fpdp, CDE_VCX2A_fpsp, CDE_VCX3A_fpdp, CDE_VCX3A_fpsp
+    printOperand(MI, 4, O);
+    break;
+  case 14:
     // CMNri, CMPri, MOVi, MVNi, TEQri, TSTri
     printModImmOperand(MI, 1, O);
     return;
     break;
-  case 13:
+  case 15:
     // CMNzrsi, CMPrsi, MOVsi, MVNsi, TEQrsi, TSTrsi
     printSORegImmOperand(MI, 1, O);
     return;
     break;
-  case 14:
+  case 16:
+    // FCONSTH, FCONSTS, MVE_VMOVimmf32, VMOVv2f32, VMOVv4f32
+    printFPImmOperand(MI, 1, O);
+    return;
+    break;
+  case 17:
     // FLDMXIA, FSTMXIA, LDMDA, LDMDB, LDMIA, LDMIB, STMDA, STMDB, STMIA, STM...
     printRegisterList(MI, 3, O);
     break;
-  case 15:
-    // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD...
-    printAddrMode5Operand(MI, 2, O, false);
-    return;
-    break;
-  case 16:
-    // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO...
-    printAddrMode7Operand(MI, 2, O);
-    break;
-  case 17:
-    // LDCL_PRE, LDC_PRE, STCL_PRE, STC_PRE, t2LDC2L_PRE, t2LDC2_PRE, t2LDCL_...
-    printAddrMode5Operand(MI, 2, O, true);
-    SStream_concat0(O, "!");
-    return;
-    break;
   case 18:
-    // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM
-    printAddrModeImm12Operand(MI, 2, O, true);
-    SStream_concat0(O, "!");
+    // LDC2L_OPTION, LDC2_OPTION, STC2L_OPTION, STC2_OPTION
+    printCoprocOptionImm(MI, 3, O);
     return;
     break;
   case 19:
-    // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG
-    printAddrMode2Operand(MI, 2, O);
-    SStream_concat0(O, "!");
+    // LDC2L_POST, LDC2_POST, STC2L_POST, STC2_POST
+    printPostIdxImm8s4Operand(MI, 3, O);
     return;
     break;
   case 20:
-    // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB...
-    printAddrModeImm12Operand(MI, 1, O, false);
+    // LDCL_OFFSET, LDC_OFFSET, STCL_OFFSET, STC_OFFSET, t2LDC2L_OFFSET, t2LD...
+    printAddrMode5Operand_0(MI, 2, O);
     return;
     break;
   case 21:
+    // LDCL_OPTION, LDCL_POST, LDC_OPTION, LDC_POST, LDRBT_POST_IMM, LDRBT_PO...
+    printAddrMode7Operand(MI, 2, O);
+    break;
+  case 22:
+    // LDRB_PRE_IMM, LDR_PRE_IMM, STRB_PRE_IMM, STR_PRE_IMM
+    printAddrModeImm12Operand_1(MI, 2, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 23:
+    // LDRB_PRE_REG, LDR_PRE_REG, STRB_PRE_REG, STR_PRE_REG
+    printAddrMode2Operand(MI, 2, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 24:
+    // LDRBi12, LDRcp, LDRi12, STRBi12, STRi12, t2LDRBi12, t2LDRHi12, t2LDRSB...
+    printAddrModeImm12Operand_0(MI, 1, O);
+    return;
+    break;
+  case 25:
     // LDRBrs, LDRrs, STRBrs, STRrs
     printAddrMode2Operand(MI, 1, O);
     return;
     break;
-  case 22:
+  case 26:
     // LDRH, LDRSB, LDRSH, STRH
-    printAddrMode3Operand(MI, 1, O, false);
+    printAddrMode3Operand_0(MI, 1, O);
     return;
     break;
-  case 23:
+  case 27:
     // LDRH_PRE, LDRSB_PRE, LDRSH_PRE, STRH_PRE
-    printAddrMode3Operand(MI, 2, O, true);
-    SStream_concat0(O, "!");
+    printAddrMode3Operand_1(MI, 2, O);
+    SStream_concat1(O, '!');
     return;
     break;
-  case 24:
+  case 28:
     // MCR2
     printCImmediate(MI, 3, O);
     SStream_concat0(O, ", ");
@@ -8388,275 +11174,295 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 5, O);
     return;
     break;
-  case 25:
+  case 29:
     // MRSbanked, t2MRSbanked
     printBankedRegOperand(MI, 1, O);
     return;
     break;
-  case 26:
+  case 30:
+    // MVE_VBICimmi16, MVE_VBICimmi32, MVE_VORRimmi16, MVE_VORRimmi32
+    printVMOVModImmOperand(MI, 2, O);
+    return;
+    break;
+  case 31:
+    // MVE_VLDRBS16, MVE_VLDRBS32, MVE_VLDRBU16, MVE_VLDRBU32, MVE_VLDRBU8, M...
+    printT2AddrModeImm8Operand_0(MI, 1, O);
+    return;
+    break;
+  case 32:
+    // MVE_VLDRBS16_pre, MVE_VLDRBS32_pre, MVE_VLDRBU16_pre, MVE_VLDRBU32_pre...
+    printT2AddrModeImm8Operand_0(MI, 2, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 33:
+    // MVE_VLDRBS16_rq, MVE_VLDRBS32_rq, MVE_VLDRBU16_rq, MVE_VLDRBU32_rq, MV...
+    printMveAddrModeRQOperand_0(MI, 1, O);
+    return;
+    break;
+  case 34:
+    // MVE_VLDRBU8_pre, MVE_VLDRHU16_pre, MVE_VLDRWU32_pre, MVE_VSTRBU8_pre, ...
+    printT2AddrModeImm8Operand_1(MI, 2, O);
+    SStream_concat1(O, '!');
+    return;
+    break;
+  case 35:
+    // MVE_VLDRDU64_rq, MVE_VSTRD64_rq
+    printMveAddrModeRQOperand_3(MI, 1, O);
+    return;
+    break;
+  case 36:
+    // MVE_VLDRHS32_rq, MVE_VLDRHU16_rq, MVE_VLDRHU32_rq, MVE_VSTRH16_rq, MVE...
+    printMveAddrModeRQOperand_1(MI, 1, O);
+    return;
+    break;
+  case 37:
+    // MVE_VLDRWU32_rq, MVE_VSTRW32_rq
+    printMveAddrModeRQOperand_2(MI, 1, O);
+    return;
+    break;
+  case 38:
+    // MVE_VMOVimmi16, MVE_VMOVimmi32, MVE_VMOVimmi8, MVE_VMVNimmi16, MVE_VMV...
+    printVMOVModImmOperand(MI, 1, O);
+    return;
+    break;
+  case 39:
+    // MVE_WLSTP_16, MVE_WLSTP_32, MVE_WLSTP_64, MVE_WLSTP_8, t2BFic, t2WLS
+    printOperandAddr(MI, Address, 2, O);
+    break;
+  case 40:
     // SSAT, SSAT16, t2SSAT, t2SSAT16
     printImmPlusOneOperand(MI, 1, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 2, O);
     break;
-  case 27:
+  case 41:
     // STLEXD, STREXD
     printGPRPairOperand(MI, 1, O);
     SStream_concat0(O, ", ");
     printAddrMode7Operand(MI, 2, O);
     return;
     break;
-  case 28:
-    // VCEQzv2f32, VCEQzv4f16, VCEQzv4f32, VCEQzv8f16, VCGEzv2f32, VCGEzv4f16...
-    SStream_concat0(O, ", #0");
-    op_addImm(MI, 0);
-    return;
-    break;
-  case 29:
+  case 42:
     // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST2LNd16, VST2LNd32, VST2LNd8, VST2LN...
     printNoHashImmediate(MI, 4, O);
     break;
-  case 30:
+  case 43:
     // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD, VLD2LNd16, VLD2LNd32, VLD2...
     printNoHashImmediate(MI, 6, O);
     break;
-  case 31:
+  case 44:
     // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
     printNoHashImmediate(MI, 8, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     break;
-  case 32:
+  case 45:
     // VLD3DUPd16, VLD3DUPd16_UPD, VLD3DUPd32, VLD3DUPd32_UPD, VLD3DUPd8, VLD...
     SStream_concat0(O, "[]}, ");
     break;
-  case 33:
+  case 46:
     // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U...
     printNoHashImmediate(MI, 10, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 1, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 10, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 2, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 10, O);
     break;
-  case 34:
+  case 47:
     // VLD4DUPd16, VLD4DUPd16_UPD, VLD4DUPd32, VLD4DUPd32_UPD, VLD4DUPd8, VLD...
     SStream_concat0(O, "[], ");
     printOperand(MI, 3, O);
     SStream_concat0(O, "[]}, ");
     break;
-  case 35:
+  case 48:
     // VLD4LNd16_UPD, VLD4LNd32_UPD, VLD4LNd8_UPD, VLD4LNq16_UPD, VLD4LNq32_U...
     printNoHashImmediate(MI, 12, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 1, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 12, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 2, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 12, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 3, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 12, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 5, O);
     printAddrMode6OffsetOperand(MI, 7, O);
     return;
     break;
-  case 36:
+  case 49:
     // VLDRD, VLDRS, VSTRD, VSTRS
-    printAddrMode5Operand(MI, 1, O, false);
+    printAddrMode5Operand_0(MI, 1, O);
     return;
     break;
-  case 37:
+  case 50:
     // VLDRH, VSTRH
-    printAddrMode5FP16Operand(MI, 1, O, false);
+    printAddrMode5FP16Operand_0(MI, 1, O);
     return;
     break;
-  case 38:
+  case 51:
     // VST1LNd16, VST1LNd32, VST1LNd8
     printNoHashImmediate(MI, 3, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 0, O);
     return;
     break;
-  case 39:
+  case 52:
     // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD, VST3LNd16, VST3LNd32, VST3...
     printNoHashImmediate(MI, 5, O);
     break;
-  case 40:
+  case 53:
     // VST3LNd16_UPD, VST3LNd32_UPD, VST3LNd8_UPD, VST3LNq16_UPD, VST3LNq32_U...
     printNoHashImmediate(MI, 7, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 5, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 7, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 6, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 7, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 1, O);
     printAddrMode6OffsetOperand(MI, 3, O);
     return;
     break;
-  case 41:
+  case 54:
     // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8...
     printOperand(MI, 5, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 6, O);
     break;
-  case 42:
+  case 55:
     // VTBL1
     printVectorListOne(MI, 1, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 2, O);
     return;
     break;
-  case 43:
+  case 56:
     // VTBL2
     printVectorListTwo(MI, 1, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 2, O);
     return;
     break;
-  case 44:
+  case 57:
     // VTBL3
     printVectorListThree(MI, 1, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 2, O);
     return;
     break;
-  case 45:
+  case 58:
     // VTBL4
     printVectorListFour(MI, 1, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 2, O);
     return;
     break;
-  case 46:
+  case 59:
     // VTBX1
     printVectorListOne(MI, 2, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 3, O);
     return;
     break;
-  case 47:
+  case 60:
     // VTBX2
     printVectorListTwo(MI, 2, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 3, O);
     return;
     break;
-  case 48:
+  case 61:
     // VTBX3
     printVectorListThree(MI, 2, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 3, O);
     return;
     break;
-  case 49:
+  case 62:
     // VTBX4
     printVectorListFour(MI, 2, O);
     SStream_concat0(O, ", ");
     printOperand(MI, 3, O);
     return;
     break;
-  case 50:
+  case 63:
     // sysLDMDA_UPD, sysLDMDB_UPD, sysLDMIA_UPD, sysLDMIB_UPD, sysSTMDA_UPD, ...
     SStream_concat0(O, " ^");
-    ARM_addUserMode(MI);
     return;
     break;
-  case 51:
-    // t2LDRBT, t2LDRBi8, t2LDRHT, t2LDRHi8, t2LDRSBT, t2LDRSBi8, t2LDRSHT, t...
-    printT2AddrModeImm8Operand(MI, 1, O, false);
+  case 64:
+    // t2BFLi, t2BFi
+    printOperandAddr(MI, Address, 1, O);
     return;
     break;
-  case 52:
-    // t2LDRB_PRE, t2LDRH_PRE, t2LDRSB_PRE, t2LDRSH_PRE, t2LDR_PRE, t2STRB_PR...
-    printT2AddrModeImm8Operand(MI, 2, O, true);
-    SStream_concat0(O, "!");
-    return;
-    break;
-  case 53:
+  case 65:
     // t2LDRBpci, t2LDRHpci, t2LDRSBpci, t2LDRSHpci, t2LDRpci, tLDRpci
     printThumbLdrLabelOperand(MI, 1, O);
     return;
     break;
-  case 54:
+  case 66:
     // t2LDRBs, t2LDRHs, t2LDRSBs, t2LDRSHs, t2LDRs, t2STRBs, t2STRHs, t2STRs
     printT2AddrModeSoRegOperand(MI, 1, O);
     return;
     break;
-  case 55:
+  case 67:
     // t2LDREX
     printT2AddrModeImm0_1020s4Operand(MI, 1, O);
     return;
     break;
-  case 56:
+  case 68:
     // t2MRS_M
     printMSRMaskOperand(MI, 1, O);
     return;
     break;
-  case 57:
+  case 69:
     // tADDspi, tSUBspi
     printThumbS4ImmOperand(MI, 2, O);
     return;
     break;
-  case 58:
+  case 70:
     // tADR
-    printAdrLabelOperand(MI, 1, O, 2);
+    printAdrLabelOperandAddr_2(MI, Address, 1, O);
     return;
     break;
-  case 59:
+  case 71:
     // tASRri, tLSRri
     printThumbSRImm(MI, 3, O);
     return;
     break;
-  case 60:
+  case 72:
     // tLDRBi, tSTRBi
     printThumbAddrModeImm5S1Operand(MI, 1, O);
     return;
     break;
-  case 61:
+  case 73:
     // tLDRBr, tLDRHr, tLDRSB, tLDRSH, tLDRr, tSTRBr, tSTRHr, tSTRr
     printThumbAddrModeRROperand(MI, 1, O);
     return;
     break;
-  case 62:
+  case 74:
     // tLDRHi, tSTRHi
     printThumbAddrModeImm5S2Operand(MI, 1, O);
     return;
     break;
-  case 63:
+  case 75:
     // tLDRi, tSTRi
     printThumbAddrModeImm5S4Operand(MI, 1, O);
     return;
     break;
-  case 64:
+  case 76:
     // tLDRspi, tSTRspi
     printThumbAddrModeSPOperand(MI, 1, O);
     return;
@@ -8664,10 +11470,9 @@ static void printInstruction(MCInst *MI, SStream *O)
   }
 
 
-  // Fragment 5 encoded into 5 bits for 23 unique commands.
-  // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 42) & 31));
-  switch ((Bits >> 42) & 31) {
-  default: // unreachable
+  // Fragment 5 encoded into 5 bits for 27 unique commands.
+  switch ((Bits >> 46) & 31) {
+  default: assert(0 && "Invalid command number.");
   case 0:
     // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm...
     SStream_concat0(O, ", ");
@@ -8678,14 +11483,23 @@ static void printInstruction(MCInst *MI, SStream *O)
     break;
   case 2:
     // VLD1LNdWB_fixed_Asm_16, VLD1LNdWB_fixed_Asm_32, VLD1LNdWB_fixed_Asm_8,...
-    SStream_concat0(O, "!");
+    SStream_concat1(O, '!');
     return;
     break;
   case 3:
     // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm...
     printOperand(MI, 3, O);
+    return;
     break;
   case 4:
+    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, VBF16MALBQI, VBF16MALTQI, VCMLAv2f32...
+    printVectorIndex(MI, 4, O);
+    break;
+  case 5:
+    // CDE_CX2DA, CDE_CX3D, CDE_CX3DA, VLD1DUPd16wb_register, VLD1DUPd32wb_re...
+    printOperand(MI, 4, O);
+    break;
+  case 6:
     // CDP, t2CDP, t2CDP2
     printCImmediate(MI, 2, O);
     SStream_concat0(O, ", ");
@@ -8696,126 +11510,131 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 5, O);
     return;
     break;
-  case 5:
-    // MCR, MCRR, VABDfd, VABDfq, VABDhd, VABDhq, VACGEfd, VACGEfq, VACGEhd, ...
+  case 7:
+    // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ...
     printOperand(MI, 2, O);
     break;
-  case 6:
+  case 8:
+    // MRC, t2MRC, t2MRC2
+    printOperand(MI, 0, O);
+    SStream_concat0(O, ", ");
+    printCImmediate(MI, 3, O);
+    SStream_concat0(O, ", ");
+    printCImmediate(MI, 4, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 5, O);
+    return;
+    break;
+  case 9:
+    // MVE_VLDRBS16_post, MVE_VLDRBS32_post, MVE_VLDRBU16_post, MVE_VLDRBU32_...
+    printT2AddrModeImm8OffsetOperand(MI, 3, O);
+    return;
+    break;
+  case 10:
+    // MVE_VMOV_from_lane_32, MVE_VMOV_from_lane_s16, MVE_VMOV_from_lane_s8, ...
+    printVectorIndex(MI, 2, O);
+    return;
+    break;
+  case 11:
+    // MVE_VSHLL_lws16bh, MVE_VSHLL_lws16th, MVE_VSHLL_lwu16bh, MVE_VSHLL_lwu...
+    SStream_concat0(O, ", #16");
+    return;
+    break;
+  case 12:
+    // MVE_VSHLL_lws8bh, MVE_VSHLL_lws8th, MVE_VSHLL_lwu8bh, MVE_VSHLL_lwu8th
+    SStream_concat0(O, ", #8");
+    return;
+    break;
+  case 13:
     // SSAT, t2SSAT
     printShiftImmOperand(MI, 3, O);
     return;
     break;
-  case 7:
+  case 14:
     // SXTB, SXTB16, SXTH, UXTB, UXTB16, UXTH, t2SXTB, t2SXTB16, t2SXTH, t2UX...
     printRotImmOperand(MI, 2, O);
     return;
     break;
-  case 8:
-    // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16...
-    printVectorIndex(MI, 4, O);
-    break;
-  case 9:
-    // VDUPLN16d, VDUPLN16q, VDUPLN32d, VDUPLN32q, VDUPLN8d, VDUPLN8q, VGETLN...
-    printVectorIndex(MI, 2, O);
+  case 15:
+    // VCEQzv16i8, VCEQzv2f32, VCEQzv2i32, VCEQzv4f16, VCEQzv4f32, VCEQzv4i16...
+    SStream_concat0(O, ", #0");
     return;
     break;
-  case 10:
-    // VLD1DUPd16wb_register, VLD1DUPd32wb_register, VLD1DUPd8wb_register, VL...
-    printOperand(MI, 4, O);
+  case 16:
+    // VFMALDI, VFMALQI, VFMSLDI, VFMSLQI
+    printVectorIndex(MI, 3, O);
     return;
     break;
-  case 11:
+  case 17:
     // VLD1LNd16, VLD1LNd16_UPD, VLD1LNd32, VLD1LNd32_UPD, VLD1LNd8, VLD1LNd8...
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     break;
-  case 12:
+  case 18:
     // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32, VLD4LNd16, VLD4L...
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     break;
-  case 13:
+  case 19:
     // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
     printOperand(MI, 1, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 8, O);
     break;
-  case 14:
+  case 20:
     // VLD3DUPd16, VLD3DUPd32, VLD3DUPd8, VLD3DUPq16, VLD3DUPq32, VLD3DUPq8
     printAddrMode6Operand(MI, 3, O);
     return;
     break;
-  case 15:
+  case 21:
     // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
     printAddrMode6Operand(MI, 4, O);
     break;
-  case 16:
+  case 22:
     // VLD4DUPd16_UPD, VLD4DUPd32_UPD, VLD4DUPd8_UPD, VLD4DUPq16_UPD, VLD4DUP...
     printAddrMode6Operand(MI, 5, O);
     printAddrMode6OffsetOperand(MI, 7, O);
     return;
     break;
-  case 17:
-    // VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4i16, VMULslv2i3...
-    printVectorIndex(MI, 3, O);
-    return;
-    break;
-  case 18:
+  case 23:
     // VST3d16_UPD, VST3d32_UPD, VST3d8_UPD, VST3q16_UPD, VST3q32_UPD, VST3q8...
     SStream_concat0(O, "}, ");
     printAddrMode6Operand(MI, 1, O);
     printAddrMode6OffsetOperand(MI, 3, O);
     return;
     break;
-  case 19:
+  case 24:
     // VST4LNd16_UPD, VST4LNd32_UPD, VST4LNd8_UPD, VST4LNq16_UPD, VST4LNq32_U...
     printOperand(MI, 5, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 8, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 6, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 8, O);
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 7, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 8, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 1, O);
     printAddrMode6OffsetOperand(MI, 3, O);
     return;
     break;
-  case 20:
+  case 25:
     // sysLDMDA, sysLDMDB, sysLDMIA, sysLDMIB, sysSTMDA, sysSTMDB, sysSTMIA, ...
     SStream_concat0(O, " ^");
-    ARM_addUserMode(MI);
     return;
     break;
-  case 21:
-    // t2LDRB_POST, t2LDRH_POST, t2LDRSB_POST, t2LDRSH_POST, t2LDR_POST, t2ST...
-    printT2AddrModeImm8OffsetOperand(MI, 3, O);
-    return;
-    break;
-  case 22:
+  case 26:
     // t2MOVsra_flag, t2MOVsrl_flag
     SStream_concat0(O, ", #1");
-    op_addImm(MI, 1);
     return;
     break;
   }
 
 
   // Fragment 6 encoded into 6 bits for 38 unique commands.
-  // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 47) & 63));
-  switch ((Bits >> 47) & 63) {
-  default: // unreachable
+  switch ((Bits >> 51) & 63) {
+  default: assert(0 && "Invalid command number.");
   case 0:
     // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, ADCrr, ADDrr, ANDrr, B...
     printOperand(MI, 2, O);
@@ -8825,173 +11644,156 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 4, O);
     break;
   case 2:
-    // VLD3dWB_register_Asm_16, VLD3dWB_register_Asm_32, VLD3dWB_register_Asm...
-    return;
-    break;
-  case 3:
     // ADCri, ADDri, ANDri, BICri, EORri, ORRri, RSBri, RSCri, SBCri, SUBri
     printModImmOperand(MI, 2, O);
     return;
     break;
-  case 4:
+  case 3:
     // ADCrsi, ADDrsi, ANDrsi, BICrsi, EORrsi, ORRrsi, RSBrsi, RSCrsi, SBCrsi...
     printSORegImmOperand(MI, 2, O);
     return;
     break;
+  case 4:
+    // BF16VDOTI_VDOTD, BF16VDOTI_VDOTQ, CDE_CX2DA, CDE_CX3D, VADDD, VBF16MAL...
+    return;
+    break;
   case 5:
     // BFI, t2BFI
     printBitfieldInvMaskImmOperand(MI, 3, O);
     return;
     break;
   case 6:
+    // CDE_CX3DA, MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f...
+    SStream_concat0(O, ", ");
+    break;
+  case 7:
+    // CDE_VCX2_vec, CDE_VCX3_vec, MVE_VABAVs16, MVE_VABAVs32, MVE_VABAVs8, M...
+    printOperand(MI, 3, O);
+    break;
+  case 8:
+    // CDE_VCX3A_fpdp, CDE_VCX3A_fpsp, VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8...
+    printOperand(MI, 5, O);
+    break;
+  case 9:
     // LDCL_OPTION, LDC_OPTION, STCL_OPTION, STC_OPTION, t2LDC2L_OPTION, t2LD...
     printCoprocOptionImm(MI, 3, O);
     return;
     break;
-  case 7:
+  case 10:
     // LDCL_POST, LDC_POST, STCL_POST, STC_POST, t2LDC2L_POST, t2LDC2_POST, t...
     printPostIdxImm8s4Operand(MI, 3, O);
     return;
     break;
-  case 8:
+  case 11:
     // LDRBT_POST_IMM, LDRBT_POST_REG, LDRB_POST_IMM, LDRB_POST_REG, LDRT_POS...
     printAddrMode2OffsetOperand(MI, 3, O);
     return;
     break;
-  case 9:
+  case 12:
     // LDRD, STRD
-    printAddrMode3Operand(MI, 2, O, false);
+    printAddrMode3Operand_0(MI, 2, O);
     return;
     break;
-  case 10:
+  case 13:
     // LDRD_POST, STRD_POST, t2LDRD_POST, t2STRD_POST
     printAddrMode7Operand(MI, 3, O);
     break;
-  case 11:
+  case 14:
     // LDRD_PRE, STRD_PRE
-    printAddrMode3Operand(MI, 3, O, true);
-    SStream_concat0(O, "!");
+    printAddrMode3Operand_1(MI, 3, O);
+    SStream_concat1(O, '!');
     return;
     break;
-  case 12:
+  case 15:
     // LDRHTi, LDRSBTi, LDRSHTi, STRHTi
     printPostIdxImm8Operand(MI, 3, O);
     return;
     break;
-  case 13:
+  case 16:
     // LDRHTr, LDRSBTr, LDRSHTr, STRHTr
     printPostIdxRegOperand(MI, 3, O);
     return;
     break;
-  case 14:
+  case 17:
     // LDRH_POST, LDRSB_POST, LDRSH_POST, STRH_POST
     printAddrMode3OffsetOperand(MI, 3, O);
     return;
     break;
-  case 15:
-    // MCR, MCRR, VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed,...
-    SStream_concat0(O, ", ");
-    break;
-  case 16:
+  case 18:
     // MCRR2
     printCImmediate(MI, 4, O);
     return;
     break;
-  case 17:
+  case 19:
+    // MVE_SQRSHRL, MVE_UQRSHLL
+    printMveSaturateOp(MI, 5, O);
+    SStream_concat0(O, ", ");
+    printOperand(MI, 4, O);
+    return;
+    break;
+  case 20:
     // STLEX, STLEXB, STLEXH, STREX, STREXB, STREXH, SWP, SWPB, t2LDAEXD, t2L...
     printAddrMode7Operand(MI, 2, O);
     return;
     break;
-  case 18:
-    // VBIFd, VBIFq, VBITd, VBITq, VBSLd, VBSLq, VLD4LNd16, VLD4LNd32, VLD4LN...
-    printOperand(MI, 3, O);
-    break;
-  case 19:
-    // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16
-    printComplexRotationOp(MI, 3, O, 180, 90);
-    return;
-    break;
-  case 20:
-    // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16
-    printComplexRotationOp(MI, 4, O, 90, 0);
-    return;
-    break;
   case 21:
+    // VCADDv2f32, VCADDv4f16, VCADDv4f32, VCADDv8f16
+    printComplexRotationOp_180_90(MI, 3, O);
+    return;
+    break;
+  case 22:
+    // VCMLAv2f32, VCMLAv4f16, VCMLAv4f32, VCMLAv8f16
+    printComplexRotationOp_90_0(MI, 4, O);
+    return;
+    break;
+  case 23:
     // VLD1LNd16, VLD1LNd32, VLD1LNd8, VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8...
     printAddrMode6Operand(MI, 1, O);
     break;
-  case 22:
+  case 24:
     // VLD1LNd16_UPD, VLD1LNd32_UPD, VLD1LNd8_UPD
     printAddrMode6Operand(MI, 2, O);
     printAddrMode6OffsetOperand(MI, 4, O);
     return;
     break;
-  case 23:
+  case 25:
     // VLD2LNd16, VLD2LNd32, VLD2LNd8, VLD2LNq16, VLD2LNq32
     printOperand(MI, 1, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 6, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 2, O);
     return;
     break;
-  case 24:
+  case 26:
     // VLD2LNd16_UPD, VLD2LNd32_UPD, VLD2LNd8_UPD, VLD2LNq16_UPD, VLD2LNq32_U...
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 3, O);
     printAddrMode6OffsetOperand(MI, 5, O);
     return;
     break;
-  case 25:
+  case 27:
     // VLD3DUPd16_UPD, VLD3DUPd32_UPD, VLD3DUPd8_UPD, VLD3DUPq16_UPD, VLD3DUP...
     printAddrMode6OffsetOperand(MI, 6, O);
     return;
     break;
-  case 26:
+  case 28:
     // VLD3LNd16, VLD3LNd32, VLD3LNd8, VLD3LNq16, VLD3LNq32
     SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
     printOperand(MI, 2, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     printNoHashImmediate(MI, 8, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 3, O);
     return;
     break;
-  case 27:
+  case 29:
     // VLD3LNd16_UPD, VLD3LNd32_UPD, VLD3LNd8_UPD, VLD3LNq16_UPD, VLD3LNq32_U...
     printAddrMode6Operand(MI, 4, O);
     printAddrMode6OffsetOperand(MI, 6, O);
     return;
     break;
-  case 28:
-    // VMLAslfd, VMLAslfq, VMLAslhd, VMLAslhq, VMLSslfd, VMLSslfq, VMLSslhd, ...
-    printVectorIndex(MI, 4, O);
-    return;
-    break;
-  case 29:
-    // VMULslfd, VMULslfq, VMULslhd, VMULslhq
-    printVectorIndex(MI, 3, O);
-    return;
-    break;
   case 30:
-    // VST2LNd16_UPD, VST2LNd32_UPD, VST2LNd8_UPD, VST2LNq16_UPD, VST2LNq32_U...
-    printOperand(MI, 5, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
-    printNoHashImmediate(MI, 6, O);
-    SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
-    printAddrMode6Operand(MI, 1, O);
-    printAddrMode6OffsetOperand(MI, 3, O);
-    return;
-    break;
-  case 31:
     // VST4d16_UPD, VST4d32_UPD, VST4d8_UPD, VST4q16_UPD, VST4q32_UPD, VST4q8...
     printOperand(MI, 7, O);
     SStream_concat0(O, "}, ");
@@ -8999,25 +11801,30 @@ static void printInstruction(MCInst *MI, SStream *O)
     printAddrMode6OffsetOperand(MI, 3, O);
     return;
     break;
-  case 32:
+  case 31:
     // t2ADCrs, t2ADDrs, t2ANDrs, t2BICrs, t2EORrs, t2ORNrs, t2ORRrs, t2RSBrs...
     printT2SOOperand(MI, 2, O);
     return;
     break;
-  case 33:
+  case 32:
     // t2ASRri, t2LSRri
     printThumbSRImm(MI, 2, O);
     return;
     break;
+  case 33:
+    // t2BFic, t2CSEL, t2CSINC, t2CSINV, t2CSNEG
+    printMandatoryPredicateOperand(MI, 3, O);
+    return;
+    break;
   case 34:
     // t2LDRD_PRE, t2STRD_PRE
-    printT2AddrModeImm8s4Operand(MI, 3, O, true);
-    SStream_concat0(O, "!");
+    printT2AddrModeImm8s4Operand_1(MI, 3, O);
+    SStream_concat1(O, '!');
     return;
     break;
   case 35:
     // t2LDRDi8, t2STRDi8
-    printT2AddrModeImm8s4Operand(MI, 2, O, false);
+    printT2AddrModeImm8s4Operand_0(MI, 2, O);
     return;
     break;
   case 36:
@@ -9033,19 +11840,23 @@ static void printInstruction(MCInst *MI, SStream *O)
   }
 
 
-  // Fragment 7 encoded into 4 bits for 13 unique commands.
-  // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 53) & 15));
-  switch ((Bits >> 53) & 15) {
-  default: // unreachable
+  // Fragment 7 encoded into 4 bits for 16 unique commands.
+  switch ((Bits >> 57) & 15) {
+  default: assert(0 && "Invalid command number.");
   case 0:
     // ASRi, ASRr, LSLi, LSLr, LSRi, LSRr, RORi, RORr, VLD1LNdWB_register_Asm...
     return;
     break;
   case 1:
-    // LDRD_POST, MLA, MLS, SBFX, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SML...
+    // CDE_CX3A, CDE_VCX3A_vec, CDE_VCX3_vec, LDRD_POST, MLA, MLS, MVE_VCADDf...
     SStream_concat0(O, ", ");
     break;
   case 2:
+    // CDE_CX3DA
+    printOperand(MI, 5, O);
+    return;
+    break;
+  case 3:
     // MCR, t2MCR, t2MCR2
     printCImmediate(MI, 3, O);
     SStream_concat0(O, ", ");
@@ -9054,492 +11865,1429 @@ static void printInstruction(MCInst *MI, SStream *O)
     printOperand(MI, 5, O);
     return;
     break;
-  case 3:
+  case 4:
     // MCRR, t2MCRR, t2MCRR2
     printOperand(MI, 3, O);
     SStream_concat0(O, ", ");
     printCImmediate(MI, 4, O);
     return;
     break;
-  case 4:
+  case 5:
+    // MVE_VMOV_rr_q, VMULLslsv2i32, VMULLslsv4i16, VMULLsluv2i32, VMULLsluv4...
+    printVectorIndex(MI, 3, O);
+    break;
+  case 6:
     // PKHBT, t2PKHBT
     printPKHLSLShiftImm(MI, 3, O);
     return;
     break;
-  case 5:
+  case 7:
     // PKHTB, t2PKHTB
     printPKHASRShiftImm(MI, 3, O);
     return;
     break;
-  case 6:
+  case 8:
     // SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, UXTAH, t2SXTAB, t2SXTAB16, t2SX...
     printRotImmOperand(MI, 3, O);
     return;
     break;
-  case 7:
+  case 9:
     // USAT, t2USAT
     printShiftImmOperand(MI, 3, O);
     return;
     break;
-  case 8:
+  case 10:
     // VCMLAv2f32_indexed, VCMLAv4f16_indexed, VCMLAv4f32_indexed, VCMLAv8f16...
-    printComplexRotationOp(MI, 5, O, 90, 0);
+    printComplexRotationOp_90_0(MI, 5, O);
     return;
     break;
-  case 9:
+  case 11:
     // VLD3d16, VLD3d16_UPD, VLD3d32, VLD3d32_UPD, VLD3d8, VLD3d8_UPD, VLD3q1...
     SStream_concat0(O, "}, ");
     break;
-  case 10:
+  case 12:
     // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32, VST2LNd16, VST2L...
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
+    SStream_concat1(O, '[');
     break;
-  case 11:
+  case 13:
+    // VMLALslsv2i32, VMLALslsv4i16, VMLALsluv2i32, VMLALsluv4i16, VMLAslfd, ...
+    printVectorIndex(MI, 4, O);
+    return;
+    break;
+  case 14:
     // VST1LNd16_UPD, VST1LNd32_UPD, VST1LNd8_UPD
     printAddrMode6OffsetOperand(MI, 3, O);
     return;
     break;
-  case 12:
+  case 15:
     // t2LDRD_POST, t2STRD_POST
     printT2AddrModeImm8s4OffsetOperand(MI, 4, O);
     return;
     break;
   }
 
-
-  // Fragment 8 encoded into 4 bits for 12 unique commands.
-  // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 57) & 15));
-  switch ((Bits >> 57) & 15) {
-  default: // unreachable
-  case 0:
-    // LDRD_POST, STRD_POST
-    printAddrMode3OffsetOperand(MI, 4, O);
+  switch (MCInst_getOpcode(MI)) {
+  default: assert(0 && "Unexpected opcode.");
+  case ARM_CDE_CX3A:
+  case ARM_CDE_VCX3A_vec:
+  case ARM_CDE_VCX3_vec:
+  case ARM_LDRD_POST:
+  case ARM_MLA:
+  case ARM_MLS:
+  case ARM_MVE_VCADDf16:
+  case ARM_MVE_VCADDf32:
+  case ARM_MVE_VCADDi16:
+  case ARM_MVE_VCADDi32:
+  case ARM_MVE_VCADDi8:
+  case ARM_MVE_VCMLAf16:
+  case ARM_MVE_VCMLAf32:
+  case ARM_MVE_VCMULf16:
+  case ARM_MVE_VCMULf32:
+  case ARM_MVE_VDWDUPu16:
+  case ARM_MVE_VDWDUPu32:
+  case ARM_MVE_VDWDUPu8:
+  case ARM_MVE_VHCADDs16:
+  case ARM_MVE_VHCADDs32:
+  case ARM_MVE_VHCADDs8:
+  case ARM_MVE_VIWDUPu16:
+  case ARM_MVE_VIWDUPu32:
+  case ARM_MVE_VIWDUPu8:
+  case ARM_MVE_VMLALDAVas16:
+  case ARM_MVE_VMLALDAVas32:
+  case ARM_MVE_VMLALDAVau16:
+  case ARM_MVE_VMLALDAVau32:
+  case ARM_MVE_VMLALDAVaxs16:
+  case ARM_MVE_VMLALDAVaxs32:
+  case ARM_MVE_VMLALDAVs16:
+  case ARM_MVE_VMLALDAVs32:
+  case ARM_MVE_VMLALDAVu16:
+  case ARM_MVE_VMLALDAVu32:
+  case ARM_MVE_VMLALDAVxs16:
+  case ARM_MVE_VMLALDAVxs32:
+  case ARM_MVE_VMLSLDAVas16:
+  case ARM_MVE_VMLSLDAVas32:
+  case ARM_MVE_VMLSLDAVaxs16:
+  case ARM_MVE_VMLSLDAVaxs32:
+  case ARM_MVE_VMLSLDAVs16:
+  case ARM_MVE_VMLSLDAVs32:
+  case ARM_MVE_VMLSLDAVxs16:
+  case ARM_MVE_VMLSLDAVxs32:
+  case ARM_MVE_VRMLALDAVHas32:
+  case ARM_MVE_VRMLALDAVHau32:
+  case ARM_MVE_VRMLALDAVHaxs32:
+  case ARM_MVE_VRMLALDAVHs32:
+  case ARM_MVE_VRMLALDAVHu32:
+  case ARM_MVE_VRMLALDAVHxs32:
+  case ARM_MVE_VRMLSLDAVHas32:
+  case ARM_MVE_VRMLSLDAVHaxs32:
+  case ARM_MVE_VRMLSLDAVHs32:
+  case ARM_MVE_VRMLSLDAVHxs32:
+  case ARM_SBFX:
+  case ARM_SMLABB:
+  case ARM_SMLABT:
+  case ARM_SMLAD:
+  case ARM_SMLADX:
+  case ARM_SMLALBB:
+  case ARM_SMLALBT:
+  case ARM_SMLALD:
+  case ARM_SMLALDX:
+  case ARM_SMLALTB:
+  case ARM_SMLALTT:
+  case ARM_SMLATB:
+  case ARM_SMLATT:
+  case ARM_SMLAWB:
+  case ARM_SMLAWT:
+  case ARM_SMLSD:
+  case ARM_SMLSDX:
+  case ARM_SMLSLD:
+  case ARM_SMLSLDX:
+  case ARM_SMMLA:
+  case ARM_SMMLAR:
+  case ARM_SMMLS:
+  case ARM_SMMLSR:
+  case ARM_SMULL:
+  case ARM_STRD_POST:
+  case ARM_UBFX:
+  case ARM_UMAAL:
+  case ARM_UMULL:
+  case ARM_USADA8:
+  case ARM_VEXTd16:
+  case ARM_VEXTd32:
+  case ARM_VEXTd8:
+  case ARM_VEXTq16:
+  case ARM_VEXTq32:
+  case ARM_VEXTq64:
+  case ARM_VEXTq8:
+  case ARM_VLD3d16:
+  case ARM_VLD3d32:
+  case ARM_VLD3d8:
+  case ARM_VLD3q16:
+  case ARM_VLD3q32:
+  case ARM_VLD3q8:
+  case ARM_VMOVRRS:
+  case ARM_VMOVSRR:
+  case ARM_VST3d16:
+  case ARM_VST3d32:
+  case ARM_VST3d8:
+  case ARM_VST3q16:
+  case ARM_VST3q32:
+  case ARM_VST3q8:
+  case ARM_t2MLA:
+  case ARM_t2MLS:
+  case ARM_t2SBFX:
+  case ARM_t2SMLABB:
+  case ARM_t2SMLABT:
+  case ARM_t2SMLAD:
+  case ARM_t2SMLADX:
+  case ARM_t2SMLAL:
+  case ARM_t2SMLALBB:
+  case ARM_t2SMLALBT:
+  case ARM_t2SMLALD:
+  case ARM_t2SMLALDX:
+  case ARM_t2SMLALTB:
+  case ARM_t2SMLALTT:
+  case ARM_t2SMLATB:
+  case ARM_t2SMLATT:
+  case ARM_t2SMLAWB:
+  case ARM_t2SMLAWT:
+  case ARM_t2SMLSD:
+  case ARM_t2SMLSDX:
+  case ARM_t2SMLSLD:
+  case ARM_t2SMLSLDX:
+  case ARM_t2SMMLA:
+  case ARM_t2SMMLAR:
+  case ARM_t2SMMLS:
+  case ARM_t2SMMLSR:
+  case ARM_t2SMULL:
+  case ARM_t2STLEXD:
+  case ARM_t2STREXD:
+  case ARM_t2UBFX:
+  case ARM_t2UMAAL:
+  case ARM_t2UMLAL:
+  case ARM_t2UMULL:
+  case ARM_t2USADA8:
+    switch (MCInst_getOpcode(MI)) {
+    default: assert(0 && "Unexpected opcode.");
+    case ARM_CDE_CX3A:
+    case ARM_CDE_VCX3A_vec:
+    case ARM_MVE_VMLALDAVas16:
+    case ARM_MVE_VMLALDAVas32:
+    case ARM_MVE_VMLALDAVau16:
+    case ARM_MVE_VMLALDAVau32:
+    case ARM_MVE_VMLALDAVaxs16:
+    case ARM_MVE_VMLALDAVaxs32:
+    case ARM_MVE_VMLSLDAVas16:
+    case ARM_MVE_VMLSLDAVas32:
+    case ARM_MVE_VMLSLDAVaxs16:
+    case ARM_MVE_VMLSLDAVaxs32:
+    case ARM_MVE_VRMLALDAVHas32:
+    case ARM_MVE_VRMLALDAVHau32:
+    case ARM_MVE_VRMLALDAVHaxs32:
+    case ARM_MVE_VRMLSLDAVHas32:
+    case ARM_MVE_VRMLSLDAVHaxs32:
+      printOperand(MI, 5, O);
+      break;
+    case ARM_CDE_VCX3_vec:
+    case ARM_MVE_VDWDUPu16:
+    case ARM_MVE_VDWDUPu32:
+    case ARM_MVE_VDWDUPu8:
+    case ARM_MVE_VIWDUPu16:
+    case ARM_MVE_VIWDUPu32:
+    case ARM_MVE_VIWDUPu8:
+      printOperand(MI, 4, O);
+      break;
+    case ARM_LDRD_POST:
+    case ARM_STRD_POST:
+      printAddrMode3OffsetOperand(MI, 4, O);
+      break;
+    case ARM_MLA:
+    case ARM_MLS:
+    case ARM_MVE_VMLALDAVs16:
+    case ARM_MVE_VMLALDAVs32:
+    case ARM_MVE_VMLALDAVu16:
+    case ARM_MVE_VMLALDAVu32:
+    case ARM_MVE_VMLALDAVxs16:
+    case ARM_MVE_VMLALDAVxs32:
+    case ARM_MVE_VMLSLDAVs16:
+    case ARM_MVE_VMLSLDAVs32:
+    case ARM_MVE_VMLSLDAVxs16:
+    case ARM_MVE_VMLSLDAVxs32:
+    case ARM_MVE_VRMLALDAVHs32:
+    case ARM_MVE_VRMLALDAVHu32:
+    case ARM_MVE_VRMLALDAVHxs32:
+    case ARM_MVE_VRMLSLDAVHs32:
+    case ARM_MVE_VRMLSLDAVHxs32:
+    case ARM_SMLABB:
+    case ARM_SMLABT:
+    case ARM_SMLAD:
+    case ARM_SMLADX:
+    case ARM_SMLALBB:
+    case ARM_SMLALBT:
+    case ARM_SMLALD:
+    case ARM_SMLALDX:
+    case ARM_SMLALTB:
+    case ARM_SMLALTT:
+    case ARM_SMLATB:
+    case ARM_SMLATT:
+    case ARM_SMLAWB:
+    case ARM_SMLAWT:
+    case ARM_SMLSD:
+    case ARM_SMLSDX:
+    case ARM_SMLSLD:
+    case ARM_SMLSLDX:
+    case ARM_SMMLA:
+    case ARM_SMMLAR:
+    case ARM_SMMLS:
+    case ARM_SMMLSR:
+    case ARM_SMULL:
+    case ARM_UMAAL:
+    case ARM_UMULL:
+    case ARM_USADA8:
+    case ARM_VEXTd16:
+    case ARM_VEXTd32:
+    case ARM_VEXTd8:
+    case ARM_VEXTq16:
+    case ARM_VEXTq32:
+    case ARM_VEXTq64:
+    case ARM_VEXTq8:
+    case ARM_VMOVRRS:
+    case ARM_VMOVSRR:
+    case ARM_t2MLA:
+    case ARM_t2MLS:
+    case ARM_t2SMLABB:
+    case ARM_t2SMLABT:
+    case ARM_t2SMLAD:
+    case ARM_t2SMLADX:
+    case ARM_t2SMLAL:
+    case ARM_t2SMLALBB:
+    case ARM_t2SMLALBT:
+    case ARM_t2SMLALD:
+    case ARM_t2SMLALDX:
+    case ARM_t2SMLALTB:
+    case ARM_t2SMLALTT:
+    case ARM_t2SMLATB:
+    case ARM_t2SMLATT:
+    case ARM_t2SMLAWB:
+    case ARM_t2SMLAWT:
+    case ARM_t2SMLSD:
+    case ARM_t2SMLSDX:
+    case ARM_t2SMLSLD:
+    case ARM_t2SMLSLDX:
+    case ARM_t2SMMLA:
+    case ARM_t2SMMLAR:
+    case ARM_t2SMMLS:
+    case ARM_t2SMMLSR:
+    case ARM_t2SMULL:
+    case ARM_t2UMAAL:
+    case ARM_t2UMLAL:
+    case ARM_t2UMULL:
+    case ARM_t2USADA8:
+      printOperand(MI, 3, O);
+      break;
+    case ARM_MVE_VCADDf16:
+    case ARM_MVE_VCADDf32:
+    case ARM_MVE_VCADDi16:
+    case ARM_MVE_VCADDi32:
+    case ARM_MVE_VCADDi8:
+    case ARM_MVE_VHCADDs16:
+    case ARM_MVE_VHCADDs32:
+    case ARM_MVE_VHCADDs8:
+      printComplexRotationOp_180_90(MI, 3, O);
+      break;
+    case ARM_MVE_VCMLAf16:
+    case ARM_MVE_VCMLAf32:
+      printComplexRotationOp_90_0(MI, 4, O);
+      break;
+    case ARM_MVE_VCMULf16:
+    case ARM_MVE_VCMULf32:
+      printComplexRotationOp_90_0(MI, 3, O);
+      break;
+    case ARM_SBFX:
+    case ARM_UBFX:
+    case ARM_t2SBFX:
+    case ARM_t2UBFX:
+      printImmPlusOneOperand(MI, 3, O);
+      break;
+    case ARM_VLD3d16:
+    case ARM_VLD3d32:
+    case ARM_VLD3d8:
+    case ARM_VLD3q16:
+    case ARM_VLD3q32:
+    case ARM_VLD3q8:
+      printAddrMode6Operand(MI, 3, O);
+      break;
+    case ARM_VST3d16:
+    case ARM_VST3d32:
+    case ARM_VST3d8:
+    case ARM_VST3q16:
+    case ARM_VST3q32:
+    case ARM_VST3q8:
+      printAddrMode6Operand(MI, 0, O);
+      break;
+    case ARM_t2STLEXD:
+    case ARM_t2STREXD:
+      printAddrMode7Operand(MI, 3, O);
+      break;
+    }
     return;
     break;
-  case 1:
-    // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML...
-    printOperand(MI, 3, O);
-    break;
-  case 2:
-    // SBFX, UBFX, t2SBFX, t2UBFX
-    printImmPlusOneOperand(MI, 3, O);
+  case ARM_MVE_VMOV_rr_q:
+    SStream_concat0(O, ", ");
+    printOperand(MI, 2, O);
+    printVectorIndex(MI, 4, O);
     return;
     break;
-  case 3:
-    // VLD3d16, VLD3d32, VLD3d8, VLD3q16, VLD3q32, VLD3q8
-    printAddrMode6Operand(MI, 3, O);
-    return;
-    break;
-  case 4:
-    // VLD3d16_UPD, VLD3d32_UPD, VLD3d8_UPD, VLD3q16_UPD, VLD3q32_UPD, VLD3q8...
+  case ARM_VLD3d16_UPD:
+  case ARM_VLD3d32_UPD:
+  case ARM_VLD3d8_UPD:
+  case ARM_VLD3q16_UPD:
+  case ARM_VLD3q32_UPD:
+  case ARM_VLD3q8_UPD:
     printAddrMode6Operand(MI, 4, O);
     printAddrMode6OffsetOperand(MI, 6, O);
     return;
     break;
-  case 5:
-    // VLD4LNd16, VLD4LNd32, VLD4LNd8, VLD4LNq16, VLD4LNq32
+  case ARM_VLD4LNd16:
+  case ARM_VLD4LNd32:
+  case ARM_VLD4LNd8:
+  case ARM_VLD4LNq16:
+  case ARM_VLD4LNq32:
     printNoHashImmediate(MI, 10, O);
     SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
     printAddrMode6Operand(MI, 4, O);
     return;
     break;
-  case 6:
-    // VST2LNd16, VST2LNd32, VST2LNd8, VST2LNq16, VST2LNq32
-    printNoHashImmediate(MI, 4, O);
-    SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
-    printAddrMode6Operand(MI, 0, O);
-    return;
-    break;
-  case 7:
-    // VST3LNd16, VST3LNd32, VST3LNd8, VST3LNq16, VST3LNq32
-    printNoHashImmediate(MI, 5, O);
-    SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
-    printOperand(MI, 4, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
-    printNoHashImmediate(MI, 5, O);
-    SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
-    printAddrMode6Operand(MI, 0, O);
-    return;
-    break;
-  case 8:
-    // VST3d16, VST3d32, VST3d8, VST3q16, VST3q32, VST3q8
-    printAddrMode6Operand(MI, 0, O);
-    return;
-    break;
-  case 9:
-    // VST4LNd16, VST4LNd32, VST4LNd8, VST4LNq16, VST4LNq32
-    printNoHashImmediate(MI, 6, O);
-    SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
-    printOperand(MI, 4, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
-    printNoHashImmediate(MI, 6, O);
-    SStream_concat0(O, "], ");
-    set_mem_access(MI, false);
-    printOperand(MI, 5, O);
-    SStream_concat0(O, "[");
-    set_mem_access(MI, true);
-    printNoHashImmediate(MI, 6, O);
-    SStream_concat0(O, "]}, ");
-    set_mem_access(MI, false);
-    printAddrMode6Operand(MI, 0, O);
-    return;
-    break;
-  case 10:
-    // VST4d16, VST4d32, VST4d8, VST4q16, VST4q32, VST4q8
-    printOperand(MI, 5, O);
+  case ARM_VLD4d16:
+  case ARM_VLD4d32:
+  case ARM_VLD4d8:
+  case ARM_VLD4q16:
+  case ARM_VLD4q32:
+  case ARM_VLD4q8:
+    printOperand(MI, 3, O);
     SStream_concat0(O, "}, ");
-    printAddrMode6Operand(MI, 0, O);
+    printAddrMode6Operand(MI, 4, O);
     return;
     break;
-  case 11:
-    // t2STLEXD, t2STREXD
-    printAddrMode7Operand(MI, 3, O);
-    return;
-    break;
-  }
-
-
-  // Fragment 9 encoded into 1 bits for 2 unique commands.
-  // printf("Fragment 9: %"PRIu64"\n", ((Bits >> 61) & 1));
-  if ((Bits >> 61) & 1) {
-    // VLD4d16, VLD4d16_UPD, VLD4d32, VLD4d32_UPD, VLD4d8, VLD4d8_UPD, VLD4q1...
+  case ARM_VLD4d16_UPD:
+  case ARM_VLD4d32_UPD:
+  case ARM_VLD4d8_UPD:
+  case ARM_VLD4q16_UPD:
+  case ARM_VLD4q32_UPD:
+  case ARM_VLD4q8_UPD:
+    printOperand(MI, 3, O);
     SStream_concat0(O, "}, ");
-  } else {
-    // MLA, MLS, SMLABB, SMLABT, SMLAD, SMLADX, SMLALBB, SMLALBT, SMLALD, SML...
-    return;
-  }
-
-
-  // Fragment 10 encoded into 1 bits for 2 unique commands.
-  // printf("Fragment 10: %"PRIu64"\n", ((Bits >> 62) & 1));
-  if ((Bits >> 62) & 1) {
-    // VLD4d16_UPD, VLD4d32_UPD, VLD4d8_UPD, VLD4q16_UPD, VLD4q32_UPD, VLD4q8...
     printAddrMode6Operand(MI, 5, O);
     printAddrMode6OffsetOperand(MI, 7, O);
     return;
-  } else {
-    // VLD4d16, VLD4d32, VLD4d8, VLD4q16, VLD4q32, VLD4q8
-    printAddrMode6Operand(MI, 4, O);
+    break;
+  case ARM_VMULLslsv2i32:
+  case ARM_VMULLslsv4i16:
+  case ARM_VMULLsluv2i32:
+  case ARM_VMULLsluv4i16:
+  case ARM_VMULslfd:
+  case ARM_VMULslfq:
+  case ARM_VMULslhd:
+  case ARM_VMULslhq:
+  case ARM_VMULslv2i32:
+  case ARM_VMULslv4i16:
+  case ARM_VMULslv4i32:
+  case ARM_VMULslv8i16:
+  case ARM_VQDMULHslv2i32:
+  case ARM_VQDMULHslv4i16:
+  case ARM_VQDMULHslv4i32:
+  case ARM_VQDMULHslv8i16:
+  case ARM_VQDMULLslv2i32:
+  case ARM_VQDMULLslv4i16:
+  case ARM_VQRDMULHslv2i32:
+  case ARM_VQRDMULHslv4i16:
+  case ARM_VQRDMULHslv4i32:
+  case ARM_VQRDMULHslv8i16:
     return;
+    break;
+  case ARM_VST2LNd16:
+  case ARM_VST2LNd32:
+  case ARM_VST2LNd8:
+  case ARM_VST2LNq16:
+  case ARM_VST2LNq32:
+    printNoHashImmediate(MI, 4, O);
+    SStream_concat0(O, "]}, ");
+    printAddrMode6Operand(MI, 0, O);
+    return;
+    break;
+  case ARM_VST2LNd16_UPD:
+  case ARM_VST2LNd32_UPD:
+  case ARM_VST2LNd8_UPD:
+  case ARM_VST2LNq16_UPD:
+  case ARM_VST2LNq32_UPD:
+    printNoHashImmediate(MI, 6, O);
+    SStream_concat0(O, "]}, ");
+    printAddrMode6Operand(MI, 1, O);
+    printAddrMode6OffsetOperand(MI, 3, O);
+    return;
+    break;
+  case ARM_VST3LNd16:
+  case ARM_VST3LNd32:
+  case ARM_VST3LNd8:
+  case ARM_VST3LNq16:
+  case ARM_VST3LNq32:
+    printNoHashImmediate(MI, 5, O);
+    SStream_concat0(O, "], ");
+    printOperand(MI, 4, O);
+    SStream_concat1(O, '[');
+    printNoHashImmediate(MI, 5, O);
+    SStream_concat0(O, "]}, ");
+    printAddrMode6Operand(MI, 0, O);
+    return;
+    break;
+  case ARM_VST4LNd16:
+  case ARM_VST4LNd32:
+  case ARM_VST4LNd8:
+  case ARM_VST4LNq16:
+  case ARM_VST4LNq32:
+    printNoHashImmediate(MI, 6, O);
+    SStream_concat0(O, "], ");
+    printOperand(MI, 4, O);
+    SStream_concat1(O, '[');
+    printNoHashImmediate(MI, 6, O);
+    SStream_concat0(O, "], ");
+    printOperand(MI, 5, O);
+    SStream_concat1(O, '[');
+    printNoHashImmediate(MI, 6, O);
+    SStream_concat0(O, "]}, ");
+    printAddrMode6Operand(MI, 0, O);
+    return;
+    break;
+  case ARM_VST4d16:
+  case ARM_VST4d32:
+  case ARM_VST4d8:
+  case ARM_VST4q16:
+  case ARM_VST4q32:
+  case ARM_VST4q8:
+    printOperand(MI, 5, O);
+    SStream_concat0(O, "}, ");
+    printAddrMode6Operand(MI, 0, O);
+    return;
+    break;
   }
-
 }
 
 
+/// getRegisterName - This method is automatically generated by tblgen
+/// from the register set description.  This returns the assembler name
+/// for the specified register.
+const char *
+getRegisterName(unsigned RegNo, unsigned AltIdx) {
+#ifndef CAPSTONE_DIET
+  assert(RegNo && RegNo < 296 && "Invalid register number!");
 
+  static const char AsmStrsNoRegAltName[] = {
+  /* 0 */ "D4_D6_D8_D10\0"
+  /* 13 */ "D7_D8_D9_D10\0"
+  /* 26 */ "Q7_Q8_Q9_Q10\0"
+  /* 39 */ "d10\0"
+  /* 43 */ "q10\0"
+  /* 47 */ "r10\0"
+  /* 51 */ "s10\0"
+  /* 55 */ "D14_D16_D18_D20\0"
+  /* 71 */ "D17_D18_D19_D20\0"
+  /* 87 */ "d20\0"
+  /* 91 */ "s20\0"
+  /* 95 */ "D24_D26_D28_D30\0"
+  /* 111 */ "D27_D28_D29_D30\0"
+  /* 127 */ "d30\0"
+  /* 131 */ "s30\0"
+  /* 135 */ "d0\0"
+  /* 138 */ "p0\0"
+  /* 141 */ "q0\0"
+  /* 144 */ "mvfr0\0"
+  /* 150 */ "s0\0"
+  /* 153 */ "D9_D10_D11\0"
+  /* 164 */ "D5_D7_D9_D11\0"
+  /* 177 */ "Q8_Q9_Q10_Q11\0"
+  /* 191 */ "R10_R11\0"
+  /* 199 */ "d11\0"
+  /* 203 */ "q11\0"
+  /* 207 */ "r11\0"
+  /* 211 */ "s11\0"
+  /* 215 */ "D19_D20_D21\0"
+  /* 227 */ "D15_D17_D19_D21\0"
+  /* 243 */ "d21\0"
+  /* 247 */ "s21\0"
+  /* 251 */ "D29_D30_D31\0"
+  /* 263 */ "D25_D27_D29_D31\0"
+  /* 279 */ "d31\0"
+  /* 283 */ "s31\0"
+  /* 287 */ "Q0_Q1\0"
+  /* 293 */ "R0_R1\0"
+  /* 299 */ "d1\0"
+  /* 302 */ "q1\0"
+  /* 305 */ "mvfr1\0"
+  /* 311 */ "s1\0"
+  /* 314 */ "D6_D8_D10_D12\0"
+  /* 328 */ "D9_D10_D11_D12\0"
+  /* 343 */ "Q9_Q10_Q11_Q12\0"
+  /* 358 */ "d12\0"
+  /* 362 */ "q12\0"
+  /* 366 */ "r12\0"
+  /* 370 */ "s12\0"
+  /* 374 */ "D16_D18_D20_D22\0"
+  /* 390 */ "D19_D20_D21_D22\0"
+  /* 406 */ "d22\0"
+  /* 410 */ "s22\0"
+  /* 414 */ "D0_D2\0"
+  /* 420 */ "D0_D1_D2\0"
+  /* 429 */ "Q1_Q2\0"
+  /* 435 */ "d2\0"
+  /* 438 */ "q2\0"
+  /* 441 */ "mvfr2\0"
+  /* 447 */ "s2\0"
+  /* 450 */ "fpinst2\0"
+  /* 458 */ "D7_D9_D11_D13\0"
+  /* 472 */ "D11_D12_D13\0"
+  /* 484 */ "Q10_Q11_Q12_Q13\0"
+  /* 500 */ "d13\0"
+  /* 504 */ "q13\0"
+  /* 508 */ "s13\0"
+  /* 512 */ "D17_D19_D21_D23\0"
+  /* 528 */ "D21_D22_D23\0"
+  /* 540 */ "d23\0"
+  /* 544 */ "s23\0"
+  /* 548 */ "D1_D3\0"
+  /* 554 */ "D1_D2_D3\0"
+  /* 563 */ "Q0_Q1_Q2_Q3\0"
+  /* 575 */ "R2_R3\0"
+  /* 581 */ "d3\0"
+  /* 584 */ "q3\0"
+  /* 587 */ "r3\0"
+  /* 590 */ "s3\0"
+  /* 593 */ "D8_D10_D12_D14\0"
+  /* 608 */ "D11_D12_D13_D14\0"
+  /* 624 */ "Q11_Q12_Q13_Q14\0"
+  /* 640 */ "d14\0"
+  /* 644 */ "q14\0"
+  /* 648 */ "s14\0"
+  /* 652 */ "D18_D20_D22_D24\0"
+  /* 668 */ "D21_D22_D23_D24\0"
+  /* 684 */ "d24\0"
+  /* 688 */ "s24\0"
+  /* 692 */ "D0_D2_D4\0"
+  /* 701 */ "D1_D2_D3_D4\0"
+  /* 713 */ "Q1_Q2_Q3_Q4\0"
+  /* 725 */ "d4\0"
+  /* 728 */ "q4\0"
+  /* 731 */ "r4\0"
+  /* 734 */ "s4\0"
+  /* 737 */ "D9_D11_D13_D15\0"
+  /* 752 */ "D13_D14_D15\0"
+  /* 764 */ "Q12_Q13_Q14_Q15\0"
+  /* 780 */ "d15\0"
+  /* 784 */ "q15\0"
+  /* 788 */ "s15\0"
+  /* 792 */ "D19_D21_D23_D25\0"
+  /* 808 */ "D23_D24_D25\0"
+  /* 820 */ "d25\0"
+  /* 824 */ "s25\0"
+  /* 828 */ "D1_D3_D5\0"
+  /* 837 */ "D3_D4_D5\0"
+  /* 846 */ "Q2_Q3_Q4_Q5\0"
+  /* 858 */ "R4_R5\0"
+  /* 864 */ "d5\0"
+  /* 867 */ "q5\0"
+  /* 870 */ "r5\0"
+  /* 873 */ "s5\0"
+  /* 876 */ "D10_D12_D14_D16\0"
+  /* 892 */ "D13_D14_D15_D16\0"
+  /* 908 */ "d16\0"
+  /* 912 */ "s16\0"
+  /* 916 */ "D20_D22_D24_D26\0"
+  /* 932 */ "D23_D24_D25_D26\0"
+  /* 948 */ "d26\0"
+  /* 952 */ "s26\0"
+  /* 956 */ "D0_D2_D4_D6\0"
+  /* 968 */ "D3_D4_D5_D6\0"
+  /* 980 */ "Q3_Q4_Q5_Q6\0"
+  /* 992 */ "d6\0"
+  /* 995 */ "q6\0"
+  /* 998 */ "r6\0"
+  /* 1001 */ "s6\0"
+  /* 1004 */ "D11_D13_D15_D17\0"
+  /* 1020 */ "D15_D16_D17\0"
+  /* 1032 */ "d17\0"
+  /* 1036 */ "s17\0"
+  /* 1040 */ "D21_D23_D25_D27\0"
+  /* 1056 */ "D25_D26_D27\0"
+  /* 1068 */ "d27\0"
+  /* 1072 */ "s27\0"
+  /* 1076 */ "D1_D3_D5_D7\0"
+  /* 1088 */ "D5_D6_D7\0"
+  /* 1097 */ "Q4_Q5_Q6_Q7\0"
+  /* 1109 */ "R6_R7\0"
+  /* 1115 */ "d7\0"
+  /* 1118 */ "q7\0"
+  /* 1121 */ "r7\0"
+  /* 1124 */ "s7\0"
+  /* 1127 */ "D12_D14_D16_D18\0"
+  /* 1143 */ "D15_D16_D17_D18\0"
+  /* 1159 */ "d18\0"
+  /* 1163 */ "s18\0"
+  /* 1167 */ "D22_D24_D26_D28\0"
+  /* 1183 */ "D25_D26_D27_D28\0"
+  /* 1199 */ "d28\0"
+  /* 1203 */ "s28\0"
+  /* 1207 */ "D2_D4_D6_D8\0"
+  /* 1219 */ "D5_D6_D7_D8\0"
+  /* 1231 */ "Q5_Q6_Q7_Q8\0"
+  /* 1243 */ "d8\0"
+  /* 1246 */ "q8\0"
+  /* 1249 */ "r8\0"
+  /* 1252 */ "s8\0"
+  /* 1255 */ "D13_D15_D17_D19\0"
+  /* 1271 */ "D17_D18_D19\0"
+  /* 1283 */ "d19\0"
+  /* 1287 */ "s19\0"
+  /* 1291 */ "D23_D25_D27_D29\0"
+  /* 1307 */ "D27_D28_D29\0"
+  /* 1319 */ "d29\0"
+  /* 1323 */ "s29\0"
+  /* 1327 */ "D3_D5_D7_D9\0"
+  /* 1339 */ "D7_D8_D9\0"
+  /* 1348 */ "Q6_Q7_Q8_Q9\0"
+  /* 1360 */ "R8_R9\0"
+  /* 1366 */ "d9\0"
+  /* 1369 */ "q9\0"
+  /* 1372 */ "r9\0"
+  /* 1375 */ "s9\0"
+  /* 1378 */ "R12_SP\0"
+  /* 1385 */ "pc\0"
+  /* 1388 */ "fpscr_nzcvqc\0"
+  /* 1401 */ "fpexc\0"
+  /* 1407 */ "fpsid\0"
+  /* 1413 */ "ra_auth_code\0"
+  /* 1426 */ "itstate\0"
+  /* 1434 */ "sp\0"
+  /* 1437 */ "fpscr\0"
+  /* 1443 */ "lr\0"
+  /* 1446 */ "vpr\0"
+  /* 1450 */ "apsr\0"
+  /* 1455 */ "cpsr\0"
+  /* 1460 */ "spsr\0"
+  /* 1465 */ "zr\0"
+  /* 1468 */ "fpcxtns\0"
+  /* 1476 */ "fpcxts\0"
+  /* 1483 */ "fpinst\0"
+  /* 1490 */ "fpscr_nzcv\0"
+  /* 1501 */ "apsr_nzcv\0"
+};
+  static const uint16_t RegAsmOffsetNoRegAltName[] = {
+    1450, 1501, 1455, 1468, 1476, 1401, 1483, 1437, 1490, 1388, 1407, 1426, 1443, 1385, 
+    1413, 1434, 1460, 1446, 1465, 135, 299, 435, 581, 725, 864, 992, 1115, 1243, 
+    1366, 39, 199, 358, 500, 640, 780, 908, 1032, 1159, 1283, 87, 243, 406, 
+    540, 684, 820, 948, 1068, 1199, 1319, 127, 279, 450, 144, 305, 441, 138, 
+    141, 302, 438, 584, 728, 867, 995, 1118, 1246, 1369, 43, 203, 362, 504, 
+    644, 784, 147, 308, 444, 587, 731, 870, 998, 1121, 1249, 1372, 47, 207, 
+    366, 150, 311, 447, 590, 734, 873, 1001, 1124, 1252, 1375, 51, 211, 370, 
+    508, 648, 788, 912, 1036, 1163, 1287, 91, 247, 410, 544, 688, 824, 952, 
+    1072, 1203, 1323, 131, 283, 414, 548, 695, 831, 962, 1082, 1213, 1333, 6, 
+    170, 320, 464, 600, 744, 884, 1012, 1135, 1263, 63, 235, 382, 520, 660, 
+    800, 924, 1048, 1175, 1299, 103, 271, 287, 429, 569, 719, 852, 986, 1103, 
+    1237, 1354, 32, 183, 350, 492, 632, 772, 563, 713, 846, 980, 1097, 1231, 
+    1348, 26, 177, 343, 484, 624, 764, 293, 575, 858, 1109, 1360, 191, 1378, 
+    420, 554, 704, 837, 971, 1088, 1222, 1339, 16, 153, 331, 472, 612, 752, 
+    896, 1020, 1147, 1271, 75, 215, 394, 528, 672, 808, 936, 1056, 1187, 1307, 
+    115, 251, 692, 828, 959, 1079, 1210, 1330, 3, 167, 317, 461, 596, 740, 
+    880, 1008, 1131, 1259, 59, 231, 378, 516, 656, 796, 920, 1044, 1171, 1295, 
+    99, 267, 956, 1076, 1207, 1327, 0, 164, 314, 458, 593, 737, 876, 1004, 
+    1127, 1255, 55, 227, 374, 512, 652, 792, 916, 1040, 1167, 1291, 95, 263, 
+    423, 707, 974, 1225, 19, 335, 616, 900, 1151, 79, 398, 676, 940, 1191, 
+    119, 701, 968, 1219, 13, 328, 608, 892, 1143, 71, 390, 668, 932, 1183, 
+    111, 
+  };
+
+  static const char AsmStrsRegNamesRaw[] = {
+  /* 0 */ "r13\0"
+  /* 4 */ "r14\0"
+  /* 8 */ "r15\0"
+};
+  static const uint8_t RegAsmOffsetRegNamesRaw[] = {
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 4, 8, 
+    3, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
+    3, 
+  };
+
+  switch(AltIdx) {
+  default: assert(0 && "Invalid register alt name index!");
+  case ARM_NoRegAltName:
+    assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
+           "Invalid alt name index for register!");
+    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
+  case ARM_RegNamesRaw:
+    if (!*(AsmStrsRegNamesRaw+RegAsmOffsetRegNamesRaw[RegNo-1]))
+      return getRegisterName(RegNo, ARM_NoRegAltName);
+    return AsmStrsRegNamesRaw+RegAsmOffsetRegNamesRaw[RegNo-1];
+  }
+#else
+  return NULL;
+#endif // CAPSTONE_DIET
+}
 #ifdef PRINT_ALIAS_INSTR
 #undef PRINT_ALIAS_INSTR
 
-static bool printAliasInstr(MCInst *MI, SStream *OS)
-{
-  unsigned int I = 0, OpIdx, PrintMethodIdx;
-  char *tmpString;
-  const char *AsmString;
-  switch (MCInst_getOpcode(MI)) {
-  default: return false;
-  case ARM_DSB:
-    if (MCInst_getNumOperands(MI) == 1 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) {
-      // (DSB 12)
-      AsmString = "dfb";
-      break;
-    }
-    return false;
-  case ARM_HINT:
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) {
-      // (HINT 0, pred:$p)
-      AsmString = "nop$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) {
-      // (HINT 1, pred:$p)
-      AsmString = "yield$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) {
-      // (HINT 2, pred:$p)
-      AsmString = "wfe$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) {
-      // (HINT 3, pred:$p)
-      AsmString = "wfi$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) {
-      // (HINT 4, pred:$p)
-      AsmString = "sev$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) {
-      // (HINT 5, pred:$p)
-      AsmString = "sevl$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) {
-      // (HINT 16, pred:$p)
-      AsmString = "esb$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 &&
-        !ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps)) {
-      // (HINT 20, pred:$p)
-      AsmString = "csdb$\xFF\x02\x01";
-      break;
-    }
-    return false;
-  case ARM_t2DSB:
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 12 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDFB)) {
-      // (t2DSB 12, pred:$p)
-      AsmString = "dfb$\xFF\x02\x01";
-      break;
-    }
-    return false;
-  case ARM_t2HINT:
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) {
-      // (t2HINT 0, pred:$p)
-      AsmString = "nop$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) {
-      // (t2HINT 1, pred:$p)
-      AsmString = "yield$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) {
-      // (t2HINT 2, pred:$p)
-      AsmString = "wfe$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) {
-      // (t2HINT 3, pred:$p)
-      AsmString = "wfi$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) {
-      // (t2HINT 4, pred:$p)
-      AsmString = "sev$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) {
-      // (t2HINT 5, pred:$p)
-      AsmString = "sevl$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureRAS)) {
-      // (t2HINT 16, pred:$p)
-      AsmString = "esb$\xFF\x02\x01.w";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2)) {
-      // (t2HINT 20, pred:$p)
-      AsmString = "csdb$\xFF\x02\x01";
-      break;
-    }
-    return false;
-  case ARM_t2SUBS_PC_LR:
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization)) {
-      // (t2SUBS_PC_LR 0, pred:$p)
-      AsmString = "eret$\xFF\x02\x01";
-      break;
-    }
-    return false;
-  case ARM_tHINT:
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 0 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) {
-      // (tHINT 0, pred:$p)
-      AsmString = "nop$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 1 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) {
-      // (tHINT 1, pred:$p)
-      AsmString = "yield$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 2 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) {
-      // (tHINT 2, pred:$p)
-      AsmString = "wfe$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 3 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) {
-      // (tHINT 3, pred:$p)
-      AsmString = "wfi$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 4 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps)) {
-      // (tHINT 4, pred:$p)
-      AsmString = "sev$\xFF\x02\x01";
-      break;
-    }
-    if (MCInst_getNumOperands(MI) == 3 &&
-        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
-        MCOperand_getImm(MCInst_getOperand(MI, 0)) == 5 &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) &&
-        ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)) {
-      // (tHINT 5, pred:$p)
-      AsmString = "sevl$\xFF\x02\x01";
-      break;
-    }
-    return false;
-  }
+static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
+#ifndef CAPSTONE_DIET
+  static const PatternsForOpcode OpToPatterns[] = {
+    {ARM_DSB, 0, 3 },
+    {ARM_HINT, 3, 9 },
+    {ARM_MVE_VMLADAVas16, 12, 1 },
+    {ARM_MVE_VMLADAVas32, 13, 1 },
+    {ARM_MVE_VMLADAVas8, 14, 1 },
+    {ARM_MVE_VMLADAVau16, 15, 1 },
+    {ARM_MVE_VMLADAVau32, 16, 1 },
+    {ARM_MVE_VMLADAVau8, 17, 1 },
+    {ARM_MVE_VMLADAVs16, 18, 1 },
+    {ARM_MVE_VMLADAVs32, 19, 1 },
+    {ARM_MVE_VMLADAVs8, 20, 1 },
+    {ARM_MVE_VMLADAVu16, 21, 1 },
+    {ARM_MVE_VMLADAVu32, 22, 1 },
+    {ARM_MVE_VMLADAVu8, 23, 1 },
+    {ARM_MVE_VMLALDAVas16, 24, 1 },
+    {ARM_MVE_VMLALDAVas32, 25, 1 },
+    {ARM_MVE_VMLALDAVau16, 26, 1 },
+    {ARM_MVE_VMLALDAVau32, 27, 1 },
+    {ARM_MVE_VMLALDAVs16, 28, 1 },
+    {ARM_MVE_VMLALDAVs32, 29, 1 },
+    {ARM_MVE_VMLALDAVu16, 30, 1 },
+    {ARM_MVE_VMLALDAVu32, 31, 1 },
+    {ARM_MVE_VORR, 32, 1 },
+    {ARM_MVE_VRMLALDAVHas32, 33, 1 },
+    {ARM_MVE_VRMLALDAVHau32, 34, 1 },
+    {ARM_MVE_VRMLALDAVHs32, 35, 1 },
+    {ARM_MVE_VRMLALDAVHu32, 36, 1 },
+    {ARM_t2CSINC, 37, 2 },
+    {ARM_t2CSINV, 39, 2 },
+    {ARM_t2CSNEG, 41, 1 },
+    {ARM_t2DSB, 42, 3 },
+    {ARM_t2HINT, 45, 13 },
+    {ARM_t2SUBS_PC_LR, 58, 1 },
+    {ARM_tHINT, 59, 6 },
+  {0},  };
 
+  static const AliasPattern Patterns[] = {
+    // ARM_DSB - 0
+    {0, 0, 1, 3 },
+    {5, 3, 1, 3 },
+    {11, 6, 1, 3 },
+    // ARM_HINT - 3
+    {15, 9, 3, 3 },
+    {23, 12, 3, 3 },
+    {33, 15, 3, 3 },
+    {41, 18, 3, 3 },
+    {49, 21, 3, 3 },
+    {57, 24, 3, 3 },
+    {66, 27, 3, 3 },
+    {74, 30, 3, 3 },
+    {83, 33, 3, 4 },
+    // ARM_MVE_VMLADAVas16 - 12
+    {94, 37, 7, 6 },
+    // ARM_MVE_VMLADAVas32 - 13
+    {120, 43, 7, 6 },
+    // ARM_MVE_VMLADAVas8 - 14
+    {146, 49, 7, 6 },
+    // ARM_MVE_VMLADAVau16 - 15
+    {171, 55, 7, 6 },
+    // ARM_MVE_VMLADAVau32 - 16
+    {197, 61, 7, 6 },
+    // ARM_MVE_VMLADAVau8 - 17
+    {223, 67, 7, 6 },
+    // ARM_MVE_VMLADAVs16 - 18
+    {248, 73, 6, 5 },
+    // ARM_MVE_VMLADAVs32 - 19
+    {273, 78, 6, 5 },
+    // ARM_MVE_VMLADAVs8 - 20
+    {298, 83, 6, 5 },
+    // ARM_MVE_VMLADAVu16 - 21
+    {322, 88, 6, 5 },
+    // ARM_MVE_VMLADAVu32 - 22
+    {347, 93, 6, 5 },
+    // ARM_MVE_VMLADAVu8 - 23
+    {372, 98, 6, 5 },
+    // ARM_MVE_VMLALDAVas16 - 24
+    {396, 103, 9, 8 },
+    // ARM_MVE_VMLALDAVas32 - 25
+    {427, 111, 9, 8 },
+    // ARM_MVE_VMLALDAVau16 - 26
+    {458, 119, 9, 8 },
+    // ARM_MVE_VMLALDAVau32 - 27
+    {489, 127, 9, 8 },
+    // ARM_MVE_VMLALDAVs16 - 28
+    {520, 135, 7, 6 },
+    // ARM_MVE_VMLALDAVs32 - 29
+    {550, 141, 7, 6 },
+    // ARM_MVE_VMLALDAVu16 - 30
+    {580, 147, 7, 6 },
+    // ARM_MVE_VMLALDAVu32 - 31
+    {610, 153, 7, 6 },
+    // ARM_MVE_VORR - 32
+    {640, 159, 7, 5 },
+    // ARM_MVE_VRMLALDAVHas32 - 33
+    {656, 164, 9, 8 },
+    // ARM_MVE_VRMLALDAVHau32 - 34
+    {689, 172, 9, 8 },
+    // ARM_MVE_VRMLALDAVHs32 - 35
+    {722, 180, 7, 6 },
+    // ARM_MVE_VRMLALDAVHu32 - 36
+    {754, 186, 7, 6 },
+    // ARM_t2CSINC - 37
+    {786, 192, 4, 4 },
+    {800, 196, 4, 4 },
+    // ARM_t2CSINV - 39
+    {818, 200, 4, 4 },
+    {833, 204, 4, 4 },
+    // ARM_t2CSNEG - 41
+    {851, 208, 4, 4 },
+    // ARM_t2DSB - 42
+    {0, 212, 3, 6 },
+    {5, 218, 3, 6 },
+    {869, 224, 3, 2 },
+    // ARM_t2HINT - 45
+    {877, 226, 3, 3 },
+    {887, 229, 3, 3 },
+    {899, 232, 3, 3 },
+    {909, 235, 3, 3 },
+    {919, 238, 3, 3 },
+    {929, 241, 3, 4 },
+    {940, 245, 3, 4 },
+    {74, 249, 3, 3 },
+    {950, 252, 3, 3 },
+    {971, 255, 3, 3 },
+    {979, 258, 3, 3 },
+    {997, 261, 3, 3 },
+    {83, 264, 3, 5 },
+    // ARM_t2SUBS_PC_LR - 58
+    {1015, 269, 3, 4 },
+    // ARM_tHINT - 59
+    {15, 273, 3, 3 },
+    {23, 276, 3, 3 },
+    {33, 279, 3, 3 },
+    {41, 282, 3, 3 },
+    {49, 285, 3, 3 },
+    {57, 288, 3, 4 },
+  {0},  };
 
-  tmpString = cs_strdup(AsmString);
+  static const AliasPatternCond Conds[] = {
+    // (DSB 0) - 0
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureDB},
+    // (DSB 4) - 3
+    {AliasPatternCond_K_Imm, (uint32_t)4},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureDB},
+    // (DSB 12) - 6
+    {AliasPatternCond_K_Imm, (uint32_t)12},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureDFB},
+    // (HINT 0, pred:$p) - 9
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
+    // (HINT 1, pred:$p) - 12
+    {AliasPatternCond_K_Imm, (uint32_t)1},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
+    // (HINT 2, pred:$p) - 15
+    {AliasPatternCond_K_Imm, (uint32_t)2},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
+    // (HINT 3, pred:$p) - 18
+    {AliasPatternCond_K_Imm, (uint32_t)3},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
+    // (HINT 4, pred:$p) - 21
+    {AliasPatternCond_K_Imm, (uint32_t)4},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
+    // (HINT 5, pred:$p) - 24
+    {AliasPatternCond_K_Imm, (uint32_t)5},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
+    // (HINT 16, pred:$p) - 27
+    {AliasPatternCond_K_Imm, (uint32_t)16},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureRAS},
+    // (HINT 20, pred:$p) - 30
+    {AliasPatternCond_K_Imm, (uint32_t)20},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6KOps},
+    // (HINT 22, pred:$p) - 33
+    {AliasPatternCond_K_Imm, (uint32_t)22},
+    {AliasPatternCond_K_NegFeature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
+    {AliasPatternCond_K_Feature, ARM_FeatureCLRBHB},
+    // (MVE_VMLADAVas16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 37
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVas32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 43
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVas8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 49
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVau16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 55
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVau32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 61
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVau8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 67
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVs16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 73
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVs32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 78
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVs8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 83
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVu16 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 88
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVu32 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 93
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLADAVu8 tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 98
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVas16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 103
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVas32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 111
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVau16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 119
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVau32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 127
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVs16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 135
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVs32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 141
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVu16 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 147
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VMLALDAVu32 tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 153
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp) - 159
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_TiedReg, 1},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VRMLALDAVHas32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 164
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VRMLALDAVHau32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 172
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_Ignore, 0},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VRMLALDAVHs32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 180
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (MVE_VRMLALDAVHu32 tGPREven:$RdaLo, tGPROdd:$RdaHi, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp) - 186
+    {AliasPatternCond_K_RegClass, ARM_tGPREvenRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_tGPROddRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_MQPRRegClassID},
+    {AliasPatternCond_K_Feature, ARM_HasMVEIntegerOps},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    // (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 192
+    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
+    {AliasPatternCond_K_Reg, ARM_ZR},
+    {AliasPatternCond_K_Reg, ARM_ZR},
+    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
+    // (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 196
+    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID},
+    {AliasPatternCond_K_TiedReg, 1},
+    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
+    // (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond) - 200
+    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
+    {AliasPatternCond_K_Reg, ARM_ZR},
+    {AliasPatternCond_K_Reg, ARM_ZR},
+    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
+    // (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 204
+    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID},
+    {AliasPatternCond_K_TiedReg, 1},
+    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
+    // (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond) - 208
+    {AliasPatternCond_K_RegClass, ARM_rGPRRegClassID},
+    {AliasPatternCond_K_RegClass, ARM_GPRwithZRnospRegClassID},
+    {AliasPatternCond_K_TiedReg, 1},
+    {AliasPatternCond_K_Feature, ARM_HasV8_1MMainlineOps},
+    // (t2DSB 0, 14, 0) - 212
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_Imm, (uint32_t)14},
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_Feature, ARM_FeatureDB},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2DSB 4, 14, 0) - 218
+    {AliasPatternCond_K_Imm, (uint32_t)4},
+    {AliasPatternCond_K_Imm, (uint32_t)14},
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_Feature, ARM_FeatureDB},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2DSB 12, pred:$p) - 224
+    {AliasPatternCond_K_Imm, (uint32_t)12},
+    {AliasPatternCond_K_Feature, ARM_FeatureDFB},
+    // (t2HINT 0, pred:$p) - 226
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 1, pred:$p) - 229
+    {AliasPatternCond_K_Imm, (uint32_t)1},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 2, pred:$p) - 232
+    {AliasPatternCond_K_Imm, (uint32_t)2},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 3, pred:$p) - 235
+    {AliasPatternCond_K_Imm, (uint32_t)3},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 4, pred:$p) - 238
+    {AliasPatternCond_K_Imm, (uint32_t)4},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 5, pred:$p) - 241
+    {AliasPatternCond_K_Imm, (uint32_t)5},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
+    // (t2HINT 16, pred:$p) - 245
+    {AliasPatternCond_K_Imm, (uint32_t)16},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    {AliasPatternCond_K_Feature, ARM_FeatureRAS},
+    // (t2HINT 20, pred:$p) - 249
+    {AliasPatternCond_K_Imm, (uint32_t)20},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 13, pred:$p) - 252
+    {AliasPatternCond_K_Imm, (uint32_t)13},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 15, pred:$p) - 255
+    {AliasPatternCond_K_Imm, (uint32_t)15},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 29, pred:$p) - 258
+    {AliasPatternCond_K_Imm, (uint32_t)29},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 45, pred:$p) - 261
+    {AliasPatternCond_K_Imm, (uint32_t)45},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    // (t2HINT 22, pred:$p) - 264
+    {AliasPatternCond_K_Imm, (uint32_t)22},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
+    {AliasPatternCond_K_Feature, ARM_FeatureCLRBHB},
+    // (t2SUBS_PC_LR 0, pred:$p) - 269
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    {AliasPatternCond_K_Feature, ARM_FeatureVirtualization},
+    // (tHINT 0, pred:$p) - 273
+    {AliasPatternCond_K_Imm, (uint32_t)0},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
+    // (tHINT 1, pred:$p) - 276
+    {AliasPatternCond_K_Imm, (uint32_t)1},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
+    // (tHINT 2, pred:$p) - 279
+    {AliasPatternCond_K_Imm, (uint32_t)2},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
+    // (tHINT 3, pred:$p) - 282
+    {AliasPatternCond_K_Imm, (uint32_t)3},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
+    // (tHINT 4, pred:$p) - 285
+    {AliasPatternCond_K_Imm, (uint32_t)4},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_HasV6MOps},
+    // (tHINT 5, pred:$p) - 288
+    {AliasPatternCond_K_Imm, (uint32_t)5},
+    {AliasPatternCond_K_Feature, ARM_ModeThumb},
+    {AliasPatternCond_K_Feature, ARM_FeatureThumb2},
+    {AliasPatternCond_K_Feature, ARM_HasV8Ops},
+  {0},  };
 
+  static const char AsmStrings[] =
+    /* 0 */ "ssbb\0"
+    /* 5 */ "pssbb\0"
+    /* 11 */ "dfb\0"
+    /* 15 */ "nop$\xFF\x02\x01\0"
+    /* 23 */ "yield$\xFF\x02\x01\0"
+    /* 33 */ "wfe$\xFF\x02\x01\0"
+    /* 41 */ "wfi$\xFF\x02\x01\0"
+    /* 49 */ "sev$\xFF\x02\x01\0"
+    /* 57 */ "sevl$\xFF\x02\x01\0"
+    /* 66 */ "esb$\xFF\x02\x01\0"
+    /* 74 */ "csdb$\xFF\x02\x01\0"
+    /* 83 */ "clrbhb$\xFF\x02\x01\0"
+    /* 94 */ "vmlava$\xFF\x05\x02.s16	$\x01, $\x03, $\x04\0"
+    /* 120 */ "vmlava$\xFF\x05\x02.s32	$\x01, $\x03, $\x04\0"
+    /* 146 */ "vmlava$\xFF\x05\x02.s8	$\x01, $\x03, $\x04\0"
+    /* 171 */ "vmlava$\xFF\x05\x02.u16	$\x01, $\x03, $\x04\0"
+    /* 197 */ "vmlava$\xFF\x05\x02.u32	$\x01, $\x03, $\x04\0"
+    /* 223 */ "vmlava$\xFF\x05\x02.u8	$\x01, $\x03, $\x04\0"
+    /* 248 */ "vmlav$\xFF\x04\x02.s16	$\x01, $\x02, $\x03\0"
+    /* 273 */ "vmlav$\xFF\x04\x02.s32	$\x01, $\x02, $\x03\0"
+    /* 298 */ "vmlav$\xFF\x04\x02.s8	$\x01, $\x02, $\x03\0"
+    /* 322 */ "vmlav$\xFF\x04\x02.u16	$\x01, $\x02, $\x03\0"
+    /* 347 */ "vmlav$\xFF\x04\x02.u32	$\x01, $\x02, $\x03\0"
+    /* 372 */ "vmlav$\xFF\x04\x02.u8	$\x01, $\x02, $\x03\0"
+    /* 396 */ "vmlalva$\xFF\x07\x02.s16	$\x01, $\x02, $\x05, $\x06\0"
+    /* 427 */ "vmlalva$\xFF\x07\x02.s32	$\x01, $\x02, $\x05, $\x06\0"
+    /* 458 */ "vmlalva$\xFF\x07\x02.u16	$\x01, $\x02, $\x05, $\x06\0"
+    /* 489 */ "vmlalva$\xFF\x07\x02.u32	$\x01, $\x02, $\x05, $\x06\0"
+    /* 520 */ "vmlalv$\xFF\x05\x02.s16	$\x01, $\x02, $\x03, $\x04\0"
+    /* 550 */ "vmlalv$\xFF\x05\x02.s32	$\x01, $\x02, $\x03, $\x04\0"
+    /* 580 */ "vmlalv$\xFF\x05\x02.u16	$\x01, $\x02, $\x03, $\x04\0"
+    /* 610 */ "vmlalv$\xFF\x05\x02.u32	$\x01, $\x02, $\x03, $\x04\0"
+    /* 640 */ "vmov$\xFF\x04\x02	$\x01, $\x02\0"
+    /* 656 */ "vrmlalvha$\xFF\x07\x02.s32	$\x01, $\x02, $\x05, $\x06\0"
+    /* 689 */ "vrmlalvha$\xFF\x07\x02.u32	$\x01, $\x02, $\x05, $\x06\0"
+    /* 722 */ "vrmlalvh$\xFF\x05\x02.s32	$\x01, $\x02, $\x03, $\x04\0"
+    /* 754 */ "vrmlalvh$\xFF\x05\x02.u32	$\x01, $\x02, $\x03, $\x04\0"
+    /* 786 */ "cset	$\x01, $\xFF\x04\x03\0"
+    /* 800 */ "cinc	$\x01, $\x02, $\xFF\x04\x03\0"
+    /* 818 */ "csetm	$\x01, $\xFF\x04\x03\0"
+    /* 833 */ "cinv	$\x01, $\x02, $\xFF\x04\x03\0"
+    /* 851 */ "cneg	$\x01, $\x02, $\xFF\x04\x03\0"
+    /* 869 */ "dfb$\xFF\x02\x01\0"
+    /* 877 */ "nop$\xFF\x02\x01.w\0"
+    /* 887 */ "yield$\xFF\x02\x01.w\0"
+    /* 899 */ "wfe$\xFF\x02\x01.w\0"
+    /* 909 */ "wfi$\xFF\x02\x01.w\0"
+    /* 919 */ "sev$\xFF\x02\x01.w\0"
+    /* 929 */ "sevl$\xFF\x02\x01.w\0"
+    /* 940 */ "esb$\xFF\x02\x01.w\0"
+    /* 950 */ "pacbti$\xFF\x02\x01 r12,lr,sp\0"
+    /* 971 */ "bti$\xFF\x02\x01\0"
+    /* 979 */ "pac$\xFF\x02\x01 r12,lr,sp\0"
+    /* 997 */ "aut$\xFF\x02\x01 r12,lr,sp\0"
+    /* 1015 */ "eret$\xFF\x02\x01\0"
+  ;
+
+#ifndef NDEBUG
+  //static struct SortCheck {
+  //  SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
+  //    assert(std::is_sorted(
+  //               OpToPatterns.begin(), OpToPatterns.end(),
+  //               [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
+  //                 return L.Opcode < R.Opcode;
+  //               }) &&
+  //           "tablegen failed to sort opcode patterns");
+  //  }
+  //} sortCheckVar(OpToPatterns);
+#endif
+
+  AliasMatchingData M = {
+    OpToPatterns,
+    Patterns,
+    Conds,
+    AsmStrings,
+    NULL,
+  };
+  const char *AsmString = matchAliasPatterns(MI, &M);
+  if (!AsmString) return false;
+
+  unsigned I = 0;
   while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
          AsmString[I] != '$' && AsmString[I] != '\0')
     ++I;
-
-  tmpString[I] = 0;
-  SStream_concat0(OS, tmpString);
-  cs_mem_free(tmpString);
-
+  char *substr = malloc(I+1);
+  memcpy(substr, AsmString, I);
+  substr[I] = '\0';
+  SStream_concat0(OS, substr);
+  free(substr);
   if (AsmString[I] != '\0') {
     if (AsmString[I] == ' ' || AsmString[I] == '\t') {
-      SStream_concat0(OS, " ");
       ++I;
     }
-
     do {
       if (AsmString[I] == '$') {
         ++I;
         if (AsmString[I] == (char)0xff) {
           ++I;
-          OpIdx = AsmString[I++] - 1;
-          PrintMethodIdx = AsmString[I++] - 1;
-          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
+          int OpIdx = AsmString[I++] - 1;
+          int PrintMethodIdx = AsmString[I++] - 1;
+          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
         } else
-            printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS);
+          printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
       } else {
-        if (AsmString[I] == '[') {
-          set_mem_access(MI, true);
-        } else if (AsmString[I] == ']') {
-          set_mem_access(MI, false);
-        }
         SStream_concat1(OS, AsmString[I++]);
       }
     } while (AsmString[I] != '\0');
   }
 
   return true;
+#else
+  return false;
+#endif // CAPSTONE_DIET
 }
-        
-static void printCustomAliasOperand(
-         MCInst *MI, unsigned OpIdx,
+
+void printCustomAliasOperand(
+         MCInst *MI, uint64_t Address, unsigned OpIdx,
          unsigned PrintMethodIdx,
-         SStream *OS)
-{
+         SStream *OS) {
+#ifndef CAPSTONE_DIET
   switch (PrintMethodIdx) {
   default:
+    assert(0 && "Unknown PrintMethod kind");
     break;
   case 0:
     printPredicateOperand(MI, OpIdx, OS);
     break;
+  case 1:
+    printVPTPredicateOperand(MI, OpIdx, OS);
+    break;
+  case 2:
+    printMandatoryInvertedPredicateOperand(MI, OpIdx, OS);
+    break;
   }
+#endif // CAPSTONE_DIET
 }
 
 #endif // PRINT_ALIAS_INSTR
diff --git a/arch/ARM/ARMGenCSFeatureName.inc b/arch/ARM/ARMGenCSFeatureName.inc
new file mode 100644
index 000000000..cb1646f4c
--- /dev/null
+++ b/arch/ARM/ARMGenCSFeatureName.inc
@@ -0,0 +1,70 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ ARM_FEATURE_IsARM, "IsARM" },
+{ ARM_FEATURE_HasV5T, "HasV5T" },
+{ ARM_FEATURE_HasV4T, "HasV4T" },
+{ ARM_FEATURE_HasVFP2, "HasVFP2" },
+{ ARM_FEATURE_HasV5TE, "HasV5TE" },
+{ ARM_FEATURE_HasV6T2, "HasV6T2" },
+{ ARM_FEATURE_HasMVEInt, "HasMVEInt" },
+{ ARM_FEATURE_HasNEON, "HasNEON" },
+{ ARM_FEATURE_HasFPRegs64, "HasFPRegs64" },
+{ ARM_FEATURE_HasFPRegs, "HasFPRegs" },
+{ ARM_FEATURE_IsThumb2, "IsThumb2" },
+{ ARM_FEATURE_HasV8_1MMainline, "HasV8_1MMainline" },
+{ ARM_FEATURE_HasLOB, "HasLOB" },
+{ ARM_FEATURE_IsThumb, "IsThumb" },
+{ ARM_FEATURE_HasV8MBaseline, "HasV8MBaseline" },
+{ ARM_FEATURE_Has8MSecExt, "Has8MSecExt" },
+{ ARM_FEATURE_HasV8, "HasV8" },
+{ ARM_FEATURE_HasAES, "HasAES" },
+{ ARM_FEATURE_HasBF16, "HasBF16" },
+{ ARM_FEATURE_HasCDE, "HasCDE" },
+{ ARM_FEATURE_PreV8, "PreV8" },
+{ ARM_FEATURE_HasV6K, "HasV6K" },
+{ ARM_FEATURE_HasCRC, "HasCRC" },
+{ ARM_FEATURE_HasV7, "HasV7" },
+{ ARM_FEATURE_HasDB, "HasDB" },
+{ ARM_FEATURE_HasVirtualization, "HasVirtualization" },
+{ ARM_FEATURE_HasVFP3, "HasVFP3" },
+{ ARM_FEATURE_HasDPVFP, "HasDPVFP" },
+{ ARM_FEATURE_HasFullFP16, "HasFullFP16" },
+{ ARM_FEATURE_HasV6, "HasV6" },
+{ ARM_FEATURE_HasAcquireRelease, "HasAcquireRelease" },
+{ ARM_FEATURE_HasV7Clrex, "HasV7Clrex" },
+{ ARM_FEATURE_HasMVEFloat, "HasMVEFloat" },
+{ ARM_FEATURE_HasFPRegsV8_1M, "HasFPRegsV8_1M" },
+{ ARM_FEATURE_HasMP, "HasMP" },
+{ ARM_FEATURE_HasSB, "HasSB" },
+{ ARM_FEATURE_HasDivideInARM, "HasDivideInARM" },
+{ ARM_FEATURE_HasV8_1a, "HasV8_1a" },
+{ ARM_FEATURE_HasSHA2, "HasSHA2" },
+{ ARM_FEATURE_HasTrustZone, "HasTrustZone" },
+{ ARM_FEATURE_UseNaClTrap, "UseNaClTrap" },
+{ ARM_FEATURE_HasV8_4a, "HasV8_4a" },
+{ ARM_FEATURE_HasV8_3a, "HasV8_3a" },
+{ ARM_FEATURE_HasFPARMv8, "HasFPARMv8" },
+{ ARM_FEATURE_HasFP16, "HasFP16" },
+{ ARM_FEATURE_HasVFP4, "HasVFP4" },
+{ ARM_FEATURE_HasFP16FML, "HasFP16FML" },
+{ ARM_FEATURE_HasFPRegs16, "HasFPRegs16" },
+{ ARM_FEATURE_HasV8MMainline, "HasV8MMainline" },
+{ ARM_FEATURE_HasDotProd, "HasDotProd" },
+{ ARM_FEATURE_HasMatMulInt8, "HasMatMulInt8" },
+{ ARM_FEATURE_IsMClass, "IsMClass" },
+{ ARM_FEATURE_HasPACBTI, "HasPACBTI" },
+{ ARM_FEATURE_IsNotMClass, "IsNotMClass" },
+{ ARM_FEATURE_HasDSP, "HasDSP" },
+{ ARM_FEATURE_HasDivideInThumb, "HasDivideInThumb" },
+{ ARM_FEATURE_HasV6M, "HasV6M" },
diff --git a/arch/ARM/ARMGenCSMappingInsn.inc b/arch/ARM/ARMGenCSMappingInsn.inc
new file mode 100644
index 000000000..200b51ca4
--- /dev/null
+++ b/arch/ARM/ARMGenCSMappingInsn.inc
@@ -0,0 +1,30995 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{
+  /* PHINODE */
+  ARM_PHI /* 0 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_INLINEASM /* 1 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_INLINEASM_BR /* 2 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_CFI_INSTRUCTION /* 3 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_EH_LABEL /* 4 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_GC_LABEL /* 5 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ANNOTATION_LABEL /* 6 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_KILL /* 7 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_EXTRACT_SUBREG /* 8 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_INSERT_SUBREG /* 9 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_IMPLICIT_DEF /* 10 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SUBREG_TO_REG /* 11 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_COPY_TO_REGCLASS /* 12 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* DBG_VALUE */
+  ARM_DBG_VALUE /* 13 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* DBG_VALUE_LIST */
+  ARM_DBG_VALUE_LIST /* 14 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* DBG_INSTR_REF */
+  ARM_DBG_INSTR_REF /* 15 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* DBG_PHI */
+  ARM_DBG_PHI /* 16 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* DBG_LABEL */
+  ARM_DBG_LABEL /* 17 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_REG_SEQUENCE /* 18 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_COPY /* 19 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* BUNDLE */
+  ARM_BUNDLE /* 20 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* LIFETIME_START */
+  ARM_LIFETIME_START /* 21 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* LIFETIME_END */
+  ARM_LIFETIME_END /* 22 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* PSEUDO_PROBE */
+  ARM_PSEUDO_PROBE /* 23 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ARITH_FENCE /* 24 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STACKMAP /* 25 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # FEntry call */
+  ARM_FENTRY_CALL /* 26 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PATCHPOINT /* 27 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LOAD_STACK_GUARD /* 28 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PREALLOCATED_SETUP /* 29 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PREALLOCATED_ARG /* 30 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STATEPOINT /* 31 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LOCAL_ESCAPE /* 32 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_FAULTING_OP /* 33 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PATCHABLE_OP /* 34 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # XRay Function Enter. */
+  ARM_PATCHABLE_FUNCTION_ENTER /* 35 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # XRay Function Patchable RET. */
+  ARM_PATCHABLE_RET /* 36 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # XRay Function Exit. */
+  ARM_PATCHABLE_FUNCTION_EXIT /* 37 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # XRay Tail Call Exit. */
+  ARM_PATCHABLE_TAIL_CALL /* 38 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # XRay Custom Event Log. */
+  ARM_PATCHABLE_EVENT_CALL /* 39 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* # XRay Typed Event Log. */
+  ARM_PATCHABLE_TYPED_EVENT_CALL /* 40 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ICALL_BRANCH_FUNNEL /* 41 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MEMBARRIER /* 42 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ASSERT_SEXT /* 43 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ASSERT_ZEXT /* 44 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ASSERT_ALIGN /* 45 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ADD /* 46 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SUB /* 47 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_MUL /* 48 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SDIV /* 49 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UDIV /* 50 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SREM /* 51 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UREM /* 52 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SDIVREM /* 53 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UDIVREM /* 54 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_AND /* 55 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_OR /* 56 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_XOR /* 57 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_IMPLICIT_DEF /* 58 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_PHI /* 59 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FRAME_INDEX /* 60 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_GLOBAL_VALUE /* 61 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_EXTRACT /* 62 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UNMERGE_VALUES /* 63 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INSERT /* 64 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_MERGE_VALUES /* 65 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BUILD_VECTOR /* 66 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BUILD_VECTOR_TRUNC /* 67 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CONCAT_VECTORS /* 68 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_PTRTOINT /* 69 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTTOPTR /* 70 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BITCAST /* 71 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FREEZE /* 72 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC_FPTRUNC_ROUND /* 73 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC_TRUNC /* 74 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC_ROUND /* 75 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC_LRINT /* 76 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC_ROUNDEVEN /* 77 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_READCYCLECOUNTER /* 78 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_LOAD /* 79 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SEXTLOAD /* 80 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ZEXTLOAD /* 81 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INDEXED_LOAD /* 82 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INDEXED_SEXTLOAD /* 83 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INDEXED_ZEXTLOAD /* 84 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STORE /* 85 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INDEXED_STORE /* 86 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS /* 87 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMIC_CMPXCHG /* 88 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_XCHG /* 89 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_ADD /* 90 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_SUB /* 91 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_AND /* 92 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_NAND /* 93 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_OR /* 94 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_XOR /* 95 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_MAX /* 96 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_MIN /* 97 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_UMAX /* 98 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_UMIN /* 99 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_FADD /* 100 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_FSUB /* 101 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_FMAX /* 102 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_FMIN /* 103 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_UINC_WRAP /* 104 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ATOMICRMW_UDEC_WRAP /* 105 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FENCE /* 106 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BRCOND /* 107 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BRINDIRECT /* 108 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INVOKE_REGION_START /* 109 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC /* 110 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INTRINSIC_W_SIDE_EFFECTS /* 111 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ANYEXT /* 112 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_TRUNC /* 113 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CONSTANT /* 114 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FCONSTANT /* 115 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VASTART /* 116 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VAARG /* 117 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SEXT /* 118 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SEXT_INREG /* 119 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ZEXT /* 120 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SHL /* 121 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_LSHR /* 122 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ASHR /* 123 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FSHL /* 124 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FSHR /* 125 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ROTR /* 126 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ROTL /* 127 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ICMP /* 128 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FCMP /* 129 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SELECT /* 130 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UADDO /* 131 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UADDE /* 132 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_USUBO /* 133 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_USUBE /* 134 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SADDO /* 135 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SADDE /* 136 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SSUBO /* 137 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SSUBE /* 138 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UMULO /* 139 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SMULO /* 140 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UMULH /* 141 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SMULH /* 142 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UADDSAT /* 143 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SADDSAT /* 144 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_USUBSAT /* 145 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SSUBSAT /* 146 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_USHLSAT /* 147 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SSHLSAT /* 148 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SMULFIX /* 149 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UMULFIX /* 150 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SMULFIXSAT /* 151 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UMULFIXSAT /* 152 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SDIVFIX /* 153 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UDIVFIX /* 154 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SDIVFIXSAT /* 155 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UDIVFIXSAT /* 156 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FADD /* 157 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FSUB /* 158 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMUL /* 159 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMA /* 160 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMAD /* 161 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FDIV /* 162 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FREM /* 163 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FPOW /* 164 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FPOWI /* 165 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FEXP /* 166 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FEXP2 /* 167 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FLOG /* 168 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FLOG2 /* 169 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FLOG10 /* 170 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FNEG /* 171 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FPEXT /* 172 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FPTRUNC /* 173 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FPTOSI /* 174 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FPTOUI /* 175 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SITOFP /* 176 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UITOFP /* 177 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FABS /* 178 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FCOPYSIGN /* 179 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_IS_FPCLASS /* 180 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FCANONICALIZE /* 181 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMINNUM /* 182 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMAXNUM /* 183 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMINNUM_IEEE /* 184 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMAXNUM_IEEE /* 185 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMINIMUM /* 186 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FMAXIMUM /* 187 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_PTR_ADD /* 188 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_PTRMASK /* 189 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SMIN /* 190 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SMAX /* 191 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UMIN /* 192 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UMAX /* 193 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ABS /* 194 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_LROUND /* 195 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_LLROUND /* 196 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BR /* 197 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BRJT /* 198 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_INSERT_VECTOR_ELT /* 199 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_EXTRACT_VECTOR_ELT /* 200 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SHUFFLE_VECTOR /* 201 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CTTZ /* 202 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CTTZ_ZERO_UNDEF /* 203 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CTLZ /* 204 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CTLZ_ZERO_UNDEF /* 205 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_CTPOP /* 206 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BSWAP /* 207 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BITREVERSE /* 208 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FCEIL /* 209 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FCOS /* 210 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FSIN /* 211 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FSQRT /* 212 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FFLOOR /* 213 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FRINT /* 214 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_FNEARBYINT /* 215 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_ADDRSPACE_CAST /* 216 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BLOCK_ADDR /* 217 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_JUMP_TABLE /* 218 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_DYN_STACKALLOC /* 219 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FADD /* 220 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FSUB /* 221 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FMUL /* 222 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FDIV /* 223 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FREM /* 224 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FMA /* 225 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_STRICT_FSQRT /* 226 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_READ_REGISTER /* 227 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_WRITE_REGISTER /* 228 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_MEMCPY /* 229 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_MEMCPY_INLINE /* 230 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_MEMMOVE /* 231 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_MEMSET /* 232 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_BZERO /* 233 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_SEQ_FADD /* 234 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_SEQ_FMUL /* 235 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_FADD /* 236 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_FMUL /* 237 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_FMAX /* 238 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_FMIN /* 239 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_ADD /* 240 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_MUL /* 241 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_AND /* 242 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_OR /* 243 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_XOR /* 244 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_SMAX /* 245 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_SMIN /* 246 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_UMAX /* 247 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_VECREDUCE_UMIN /* 248 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_SBFX /* 249 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_G_UBFX /* 250 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ABS /* 251 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ADDSri /* 252 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ADDSrr /* 253 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ADDSrsi /* 254 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ADDSrsr /* 255 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ADJCALLSTACKDOWN /* 256 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_ADJCALLSTACKUP /* 257 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* asr${s}${p} $Rd, $Rm, $imm */
+  ARM_ASRi /* 258 */, ARM_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* asr${s}${p} $Rd, $Rn, $Rm */
+  ARM_ASRr /* 259 */, ARM_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_B /* 260 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BCCZi64 /* 261 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BCCi64 /* 262 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BLX_noip /* 263 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BLX_pred_noip /* 264 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BL_PUSHLR /* 265 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BMOVPCB_CALL /* 266 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BMOVPCRX_CALL /* 267 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BR_JTadd /* 268 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BR_JTm_i12 /* 269 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BR_JTm_rs /* 270 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BR_JTr /* 271 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_BX_CALL /* 272 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_CMP_SWAP_16 /* 273 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_CMP_SWAP_32 /* 274 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_CMP_SWAP_64 /* 275 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_CMP_SWAP_8 /* 276 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_CONSTPOOL_ENTRY /* 277 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_COPY_STRUCT_BYVAL_I32 /* 278 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* it$mask $cc */
+  ARM_ITasm /* 279 */, ARM_INS_IT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_Int_eh_sjlj_dispatchsetup /* 280 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_Int_eh_sjlj_longjmp /* 281 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_Int_eh_sjlj_setjmp /* 282 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_Int_eh_sjlj_setjmp_nofp /* 283 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_Int_eh_sjlj_setup_dispatch /* 284 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_JUMPTABLE_ADDRS /* 285 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_JUMPTABLE_INSTS /* 286 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_JUMPTABLE_TBB /* 287 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_JUMPTABLE_TBH /* 288 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LDMIA_RET /* 289 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrbt${q} $Rt, $addr */
+  ARM_LDRBT_POST /* 290 */, ARM_INS_LDRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${q} $Rt, $immediate */
+  ARM_LDRConstPool /* 291 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrht${p} $Rt, $addr */
+  ARM_LDRHTii /* 292 */, ARM_INS_LDRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LDRLIT_ga_abs /* 293 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LDRLIT_ga_pcrel /* 294 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LDRLIT_ga_pcrel_ldr /* 295 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsbt${p} $Rt, $addr */
+  ARM_LDRSBTii /* 296 */, ARM_INS_LDRSBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsht${p} $Rt, $addr */
+  ARM_LDRSHTii /* 297 */, ARM_INS_LDRSHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrt${q} $Rt, $addr */
+  ARM_LDRT_POST /* 298 */, ARM_INS_LDRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LEApcrel /* 299 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LEApcrelJT /* 300 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_LOADDUAL /* 301 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* lsl${s}${p} $Rd, $Rm, $imm */
+  ARM_LSLi /* 302 */, ARM_INS_LSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsl${s}${p} $Rd, $Rn, $Rm */
+  ARM_LSLr /* 303 */, ARM_INS_LSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsr${s}${p} $Rd, $Rm, $imm */
+  ARM_LSRi /* 304 */, ARM_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsr${s}${p} $Rd, $Rn, $Rm */
+  ARM_LSRr /* 305 */, ARM_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MEMCPY /* 306 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MLAv5 /* 307 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVCCi /* 308 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVCCi16 /* 309 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVCCi32imm /* 310 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVCCr /* 311 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVCCsi /* 312 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVCCsr /* 313 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVPCRX /* 314 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVTi16_ga_pcrel /* 315 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOV_ga_pcrel /* 316 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOV_ga_pcrel_ldr /* 317 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVi16_ga_pcrel /* 318 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVi32imm /* 319 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVsra_flag /* 320 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MOVsrl_flag /* 321 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MQPRCopy /* 322 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MQQPRLoad /* 323 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MQQPRStore /* 324 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MQQQQPRLoad /* 325 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MQQQQPRStore /* 326 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MULv5 /* 327 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MVE_MEMCPYLOOPINST /* 328 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MVE_MEMSETLOOPINST /* 329 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_MVNCCi /* 330 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICADD /* 331 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICLDR /* 332 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICLDRB /* 333 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICLDRH /* 334 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICLDRSB /* 335 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICLDRSH /* 336 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICSTR /* 337 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICSTRB /* 338 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_PICSTRH /* 339 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ror${s}${p} $Rd, $Rm, $imm */
+  ARM_RORi /* 340 */, ARM_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ror${s}${p} $Rd, $Rn, $Rm */
+  ARM_RORr /* 341 */, ARM_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_RRX /* 342 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* rrx${s}${p} $Rd, $Rm */
+  ARM_RRXi /* 343 */, ARM_INS_RRX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_RSBSri /* 344 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_RSBSrsi /* 345 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_RSBSrsr /* 346 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_EpilogEnd /* 347 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_EpilogStart /* 348 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_Nop /* 349 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_Nop_Ret /* 350 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_PrologEnd /* 351 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_SaveFRegs /* 352 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_SaveLR /* 353 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_SaveRegs /* 354 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_SaveRegs_Ret /* 355 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_SaveSP /* 356 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SEH_StackAlloc /* 357 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SMLALv5 /* 358 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SMULLv5 /* 359 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SPACE /* 360 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STOREDUAL /* 361 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* strbt${q} $Rt, $addr */
+  ARM_STRBT_POST /* 362 */, ARM_INS_STRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STRBi_preidx /* 363 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STRBr_preidx /* 364 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STRH_preidx /* 365 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* strt${q} $Rt, $addr */
+  ARM_STRT_POST /* 366 */, ARM_INS_STRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STRi_preidx /* 367 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_STRr_preidx /* 368 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SUBS_PC_LR /* 369 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SUBSri /* 370 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SUBSrr /* 371 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SUBSrsi /* 372 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SUBSrsr /* 373 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SpeculationBarrierISBDSBEndBB /* 374 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_SpeculationBarrierSBEndBB /* 375 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_TAILJMPd /* 376 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_TAILJMPr /* 377 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_TAILJMPr4 /* 378 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_TCRETURNdi /* 379 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_TCRETURNri /* 380 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_TPsoft /* 381 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_UMLALv5 /* 382 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_UMULLv5 /* 383 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$list, $addr */
+  ARM_VLD1LNdAsm_16 /* 384 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$list, $addr */
+  ARM_VLD1LNdAsm_32 /* 385 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$list, $addr */
+  ARM_VLD1LNdAsm_8 /* 386 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$list, $addr! */
+  ARM_VLD1LNdWB_fixed_Asm_16 /* 387 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$list, $addr! */
+  ARM_VLD1LNdWB_fixed_Asm_32 /* 388 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$list, $addr! */
+  ARM_VLD1LNdWB_fixed_Asm_8 /* 389 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$list, $addr, $Rm */
+  ARM_VLD1LNdWB_register_Asm_16 /* 390 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$list, $addr, $Rm */
+  ARM_VLD1LNdWB_register_Asm_32 /* 391 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$list, $addr, $Rm */
+  ARM_VLD1LNdWB_register_Asm_8 /* 392 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$list, $addr */
+  ARM_VLD2LNdAsm_16 /* 393 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$list, $addr */
+  ARM_VLD2LNdAsm_32 /* 394 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$list, $addr */
+  ARM_VLD2LNdAsm_8 /* 395 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$list, $addr! */
+  ARM_VLD2LNdWB_fixed_Asm_16 /* 396 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$list, $addr! */
+  ARM_VLD2LNdWB_fixed_Asm_32 /* 397 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$list, $addr! */
+  ARM_VLD2LNdWB_fixed_Asm_8 /* 398 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$list, $addr, $Rm */
+  ARM_VLD2LNdWB_register_Asm_16 /* 399 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$list, $addr, $Rm */
+  ARM_VLD2LNdWB_register_Asm_32 /* 400 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$list, $addr, $Rm */
+  ARM_VLD2LNdWB_register_Asm_8 /* 401 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$list, $addr */
+  ARM_VLD2LNqAsm_16 /* 402 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$list, $addr */
+  ARM_VLD2LNqAsm_32 /* 403 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$list, $addr! */
+  ARM_VLD2LNqWB_fixed_Asm_16 /* 404 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$list, $addr! */
+  ARM_VLD2LNqWB_fixed_Asm_32 /* 405 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$list, $addr, $Rm */
+  ARM_VLD2LNqWB_register_Asm_16 /* 406 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$list, $addr, $Rm */
+  ARM_VLD2LNqWB_register_Asm_32 /* 407 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr */
+  ARM_VLD3DUPdAsm_16 /* 408 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr */
+  ARM_VLD3DUPdAsm_32 /* 409 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr */
+  ARM_VLD3DUPdAsm_8 /* 410 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr! */
+  ARM_VLD3DUPdWB_fixed_Asm_16 /* 411 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr! */
+  ARM_VLD3DUPdWB_fixed_Asm_32 /* 412 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr! */
+  ARM_VLD3DUPdWB_fixed_Asm_8 /* 413 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr, $Rm */
+  ARM_VLD3DUPdWB_register_Asm_16 /* 414 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr, $Rm */
+  ARM_VLD3DUPdWB_register_Asm_32 /* 415 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr, $Rm */
+  ARM_VLD3DUPdWB_register_Asm_8 /* 416 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr */
+  ARM_VLD3DUPqAsm_16 /* 417 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr */
+  ARM_VLD3DUPqAsm_32 /* 418 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr */
+  ARM_VLD3DUPqAsm_8 /* 419 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr! */
+  ARM_VLD3DUPqWB_fixed_Asm_16 /* 420 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr! */
+  ARM_VLD3DUPqWB_fixed_Asm_32 /* 421 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr! */
+  ARM_VLD3DUPqWB_fixed_Asm_8 /* 422 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr, $Rm */
+  ARM_VLD3DUPqWB_register_Asm_16 /* 423 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr, $Rm */
+  ARM_VLD3DUPqWB_register_Asm_32 /* 424 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr, $Rm */
+  ARM_VLD3DUPqWB_register_Asm_8 /* 425 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr */
+  ARM_VLD3LNdAsm_16 /* 426 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr */
+  ARM_VLD3LNdAsm_32 /* 427 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr */
+  ARM_VLD3LNdAsm_8 /* 428 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr! */
+  ARM_VLD3LNdWB_fixed_Asm_16 /* 429 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr! */
+  ARM_VLD3LNdWB_fixed_Asm_32 /* 430 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr! */
+  ARM_VLD3LNdWB_fixed_Asm_8 /* 431 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr, $Rm */
+  ARM_VLD3LNdWB_register_Asm_16 /* 432 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr, $Rm */
+  ARM_VLD3LNdWB_register_Asm_32 /* 433 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr, $Rm */
+  ARM_VLD3LNdWB_register_Asm_8 /* 434 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr */
+  ARM_VLD3LNqAsm_16 /* 435 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr */
+  ARM_VLD3LNqAsm_32 /* 436 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr! */
+  ARM_VLD3LNqWB_fixed_Asm_16 /* 437 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr! */
+  ARM_VLD3LNqWB_fixed_Asm_32 /* 438 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr, $Rm */
+  ARM_VLD3LNqWB_register_Asm_16 /* 439 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr, $Rm */
+  ARM_VLD3LNqWB_register_Asm_32 /* 440 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr */
+  ARM_VLD3dAsm_16 /* 441 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr */
+  ARM_VLD3dAsm_32 /* 442 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr */
+  ARM_VLD3dAsm_8 /* 443 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr! */
+  ARM_VLD3dWB_fixed_Asm_16 /* 444 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr! */
+  ARM_VLD3dWB_fixed_Asm_32 /* 445 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr! */
+  ARM_VLD3dWB_fixed_Asm_8 /* 446 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr, $Rm */
+  ARM_VLD3dWB_register_Asm_16 /* 447 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr, $Rm */
+  ARM_VLD3dWB_register_Asm_32 /* 448 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr, $Rm */
+  ARM_VLD3dWB_register_Asm_8 /* 449 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr */
+  ARM_VLD3qAsm_16 /* 450 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr */
+  ARM_VLD3qAsm_32 /* 451 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr */
+  ARM_VLD3qAsm_8 /* 452 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr! */
+  ARM_VLD3qWB_fixed_Asm_16 /* 453 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr! */
+  ARM_VLD3qWB_fixed_Asm_32 /* 454 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr! */
+  ARM_VLD3qWB_fixed_Asm_8 /* 455 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	$list, $addr, $Rm */
+  ARM_VLD3qWB_register_Asm_16 /* 456 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	$list, $addr, $Rm */
+  ARM_VLD3qWB_register_Asm_32 /* 457 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	$list, $addr, $Rm */
+  ARM_VLD3qWB_register_Asm_8 /* 458 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr */
+  ARM_VLD4DUPdAsm_16 /* 459 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr */
+  ARM_VLD4DUPdAsm_32 /* 460 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr */
+  ARM_VLD4DUPdAsm_8 /* 461 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr! */
+  ARM_VLD4DUPdWB_fixed_Asm_16 /* 462 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr! */
+  ARM_VLD4DUPdWB_fixed_Asm_32 /* 463 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr! */
+  ARM_VLD4DUPdWB_fixed_Asm_8 /* 464 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr, $Rm */
+  ARM_VLD4DUPdWB_register_Asm_16 /* 465 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr, $Rm */
+  ARM_VLD4DUPdWB_register_Asm_32 /* 466 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr, $Rm */
+  ARM_VLD4DUPdWB_register_Asm_8 /* 467 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr */
+  ARM_VLD4DUPqAsm_16 /* 468 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr */
+  ARM_VLD4DUPqAsm_32 /* 469 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr */
+  ARM_VLD4DUPqAsm_8 /* 470 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr! */
+  ARM_VLD4DUPqWB_fixed_Asm_16 /* 471 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr! */
+  ARM_VLD4DUPqWB_fixed_Asm_32 /* 472 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr! */
+  ARM_VLD4DUPqWB_fixed_Asm_8 /* 473 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr, $Rm */
+  ARM_VLD4DUPqWB_register_Asm_16 /* 474 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr, $Rm */
+  ARM_VLD4DUPqWB_register_Asm_32 /* 475 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr, $Rm */
+  ARM_VLD4DUPqWB_register_Asm_8 /* 476 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr */
+  ARM_VLD4LNdAsm_16 /* 477 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr */
+  ARM_VLD4LNdAsm_32 /* 478 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr */
+  ARM_VLD4LNdAsm_8 /* 479 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr! */
+  ARM_VLD4LNdWB_fixed_Asm_16 /* 480 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr! */
+  ARM_VLD4LNdWB_fixed_Asm_32 /* 481 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr! */
+  ARM_VLD4LNdWB_fixed_Asm_8 /* 482 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr, $Rm */
+  ARM_VLD4LNdWB_register_Asm_16 /* 483 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr, $Rm */
+  ARM_VLD4LNdWB_register_Asm_32 /* 484 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr, $Rm */
+  ARM_VLD4LNdWB_register_Asm_8 /* 485 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr */
+  ARM_VLD4LNqAsm_16 /* 486 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr */
+  ARM_VLD4LNqAsm_32 /* 487 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr! */
+  ARM_VLD4LNqWB_fixed_Asm_16 /* 488 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr! */
+  ARM_VLD4LNqWB_fixed_Asm_32 /* 489 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr, $Rm */
+  ARM_VLD4LNqWB_register_Asm_16 /* 490 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr, $Rm */
+  ARM_VLD4LNqWB_register_Asm_32 /* 491 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr */
+  ARM_VLD4dAsm_16 /* 492 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr */
+  ARM_VLD4dAsm_32 /* 493 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr */
+  ARM_VLD4dAsm_8 /* 494 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr! */
+  ARM_VLD4dWB_fixed_Asm_16 /* 495 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr! */
+  ARM_VLD4dWB_fixed_Asm_32 /* 496 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr! */
+  ARM_VLD4dWB_fixed_Asm_8 /* 497 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr, $Rm */
+  ARM_VLD4dWB_register_Asm_16 /* 498 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr, $Rm */
+  ARM_VLD4dWB_register_Asm_32 /* 499 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr, $Rm */
+  ARM_VLD4dWB_register_Asm_8 /* 500 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr */
+  ARM_VLD4qAsm_16 /* 501 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr */
+  ARM_VLD4qAsm_32 /* 502 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr */
+  ARM_VLD4qAsm_8 /* 503 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr! */
+  ARM_VLD4qWB_fixed_Asm_16 /* 504 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr! */
+  ARM_VLD4qWB_fixed_Asm_32 /* 505 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr! */
+  ARM_VLD4qWB_fixed_Asm_8 /* 506 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	$list, $addr, $Rm */
+  ARM_VLD4qWB_register_Asm_16 /* 507 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	$list, $addr, $Rm */
+  ARM_VLD4qWB_register_Asm_32 /* 508 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	$list, $addr, $Rm */
+  ARM_VLD4qWB_register_Asm_8 /* 509 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VMOVD0 /* 510 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VMOVDcc /* 511 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VMOVHcc /* 512 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VMOVQ0 /* 513 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VMOVScc /* 514 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$list, $addr */
+  ARM_VST1LNdAsm_16 /* 515 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$list, $addr */
+  ARM_VST1LNdAsm_32 /* 516 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$list, $addr */
+  ARM_VST1LNdAsm_8 /* 517 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$list, $addr! */
+  ARM_VST1LNdWB_fixed_Asm_16 /* 518 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$list, $addr! */
+  ARM_VST1LNdWB_fixed_Asm_32 /* 519 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$list, $addr! */
+  ARM_VST1LNdWB_fixed_Asm_8 /* 520 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$list, $addr, $Rm */
+  ARM_VST1LNdWB_register_Asm_16 /* 521 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$list, $addr, $Rm */
+  ARM_VST1LNdWB_register_Asm_32 /* 522 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$list, $addr, $Rm */
+  ARM_VST1LNdWB_register_Asm_8 /* 523 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$list, $addr */
+  ARM_VST2LNdAsm_16 /* 524 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$list, $addr */
+  ARM_VST2LNdAsm_32 /* 525 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$list, $addr */
+  ARM_VST2LNdAsm_8 /* 526 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$list, $addr! */
+  ARM_VST2LNdWB_fixed_Asm_16 /* 527 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$list, $addr! */
+  ARM_VST2LNdWB_fixed_Asm_32 /* 528 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$list, $addr! */
+  ARM_VST2LNdWB_fixed_Asm_8 /* 529 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$list, $addr, $Rm */
+  ARM_VST2LNdWB_register_Asm_16 /* 530 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$list, $addr, $Rm */
+  ARM_VST2LNdWB_register_Asm_32 /* 531 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$list, $addr, $Rm */
+  ARM_VST2LNdWB_register_Asm_8 /* 532 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$list, $addr */
+  ARM_VST2LNqAsm_16 /* 533 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$list, $addr */
+  ARM_VST2LNqAsm_32 /* 534 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$list, $addr! */
+  ARM_VST2LNqWB_fixed_Asm_16 /* 535 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$list, $addr! */
+  ARM_VST2LNqWB_fixed_Asm_32 /* 536 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$list, $addr, $Rm */
+  ARM_VST2LNqWB_register_Asm_16 /* 537 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$list, $addr, $Rm */
+  ARM_VST2LNqWB_register_Asm_32 /* 538 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr */
+  ARM_VST3LNdAsm_16 /* 539 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr */
+  ARM_VST3LNdAsm_32 /* 540 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr */
+  ARM_VST3LNdAsm_8 /* 541 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr! */
+  ARM_VST3LNdWB_fixed_Asm_16 /* 542 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr! */
+  ARM_VST3LNdWB_fixed_Asm_32 /* 543 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr! */
+  ARM_VST3LNdWB_fixed_Asm_8 /* 544 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr, $Rm */
+  ARM_VST3LNdWB_register_Asm_16 /* 545 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr, $Rm */
+  ARM_VST3LNdWB_register_Asm_32 /* 546 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr, $Rm */
+  ARM_VST3LNdWB_register_Asm_8 /* 547 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr */
+  ARM_VST3LNqAsm_16 /* 548 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr */
+  ARM_VST3LNqAsm_32 /* 549 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr! */
+  ARM_VST3LNqWB_fixed_Asm_16 /* 550 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr! */
+  ARM_VST3LNqWB_fixed_Asm_32 /* 551 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr, $Rm */
+  ARM_VST3LNqWB_register_Asm_16 /* 552 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr, $Rm */
+  ARM_VST3LNqWB_register_Asm_32 /* 553 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr */
+  ARM_VST3dAsm_16 /* 554 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr */
+  ARM_VST3dAsm_32 /* 555 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr */
+  ARM_VST3dAsm_8 /* 556 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr! */
+  ARM_VST3dWB_fixed_Asm_16 /* 557 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr! */
+  ARM_VST3dWB_fixed_Asm_32 /* 558 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr! */
+  ARM_VST3dWB_fixed_Asm_8 /* 559 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr, $Rm */
+  ARM_VST3dWB_register_Asm_16 /* 560 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr, $Rm */
+  ARM_VST3dWB_register_Asm_32 /* 561 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr, $Rm */
+  ARM_VST3dWB_register_Asm_8 /* 562 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr */
+  ARM_VST3qAsm_16 /* 563 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr */
+  ARM_VST3qAsm_32 /* 564 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr */
+  ARM_VST3qAsm_8 /* 565 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr! */
+  ARM_VST3qWB_fixed_Asm_16 /* 566 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr! */
+  ARM_VST3qWB_fixed_Asm_32 /* 567 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr! */
+  ARM_VST3qWB_fixed_Asm_8 /* 568 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	$list, $addr, $Rm */
+  ARM_VST3qWB_register_Asm_16 /* 569 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	$list, $addr, $Rm */
+  ARM_VST3qWB_register_Asm_32 /* 570 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	$list, $addr, $Rm */
+  ARM_VST3qWB_register_Asm_8 /* 571 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr */
+  ARM_VST4LNdAsm_16 /* 572 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr */
+  ARM_VST4LNdAsm_32 /* 573 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr */
+  ARM_VST4LNdAsm_8 /* 574 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr! */
+  ARM_VST4LNdWB_fixed_Asm_16 /* 575 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr! */
+  ARM_VST4LNdWB_fixed_Asm_32 /* 576 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr! */
+  ARM_VST4LNdWB_fixed_Asm_8 /* 577 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr, $Rm */
+  ARM_VST4LNdWB_register_Asm_16 /* 578 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr, $Rm */
+  ARM_VST4LNdWB_register_Asm_32 /* 579 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr, $Rm */
+  ARM_VST4LNdWB_register_Asm_8 /* 580 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr */
+  ARM_VST4LNqAsm_16 /* 581 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr */
+  ARM_VST4LNqAsm_32 /* 582 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr! */
+  ARM_VST4LNqWB_fixed_Asm_16 /* 583 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr! */
+  ARM_VST4LNqWB_fixed_Asm_32 /* 584 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr, $Rm */
+  ARM_VST4LNqWB_register_Asm_16 /* 585 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr, $Rm */
+  ARM_VST4LNqWB_register_Asm_32 /* 586 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr */
+  ARM_VST4dAsm_16 /* 587 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr */
+  ARM_VST4dAsm_32 /* 588 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr */
+  ARM_VST4dAsm_8 /* 589 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr! */
+  ARM_VST4dWB_fixed_Asm_16 /* 590 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr! */
+  ARM_VST4dWB_fixed_Asm_32 /* 591 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr! */
+  ARM_VST4dWB_fixed_Asm_8 /* 592 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr, $Rm */
+  ARM_VST4dWB_register_Asm_16 /* 593 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr, $Rm */
+  ARM_VST4dWB_register_Asm_32 /* 594 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr, $Rm */
+  ARM_VST4dWB_register_Asm_8 /* 595 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr */
+  ARM_VST4qAsm_16 /* 596 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr */
+  ARM_VST4qAsm_32 /* 597 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr */
+  ARM_VST4qAsm_8 /* 598 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr! */
+  ARM_VST4qWB_fixed_Asm_16 /* 599 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr! */
+  ARM_VST4qWB_fixed_Asm_32 /* 600 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr! */
+  ARM_VST4qWB_fixed_Asm_8 /* 601 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	$list, $addr, $Rm */
+  ARM_VST4qWB_register_Asm_16 /* 602 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	$list, $addr, $Rm */
+  ARM_VST4qWB_register_Asm_32 /* 603 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	$list, $addr, $Rm */
+  ARM_VST4qWB_register_Asm_8 /* 604 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_WIN__CHKSTK /* 605 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_WIN__DBZCHK /* 606 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2ABS /* 607 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2ADDSri /* 608 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2ADDSrr /* 609 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2ADDSrs /* 610 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2BF_LabelPseudo /* 611 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2BR_JT /* 612 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2CALL_BTI /* 613 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2DoLoopStart /* 614 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2DoLoopStartTP /* 615 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LDMIA_RET /* 616 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p} $Rt, $addr */
+  ARM_t2LDRBpcrel /* 617 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p} $Rt, $immediate */
+  ARM_t2LDRConstPool /* 618 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p} $Rt, $addr */
+  ARM_t2LDRHpcrel /* 619 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LDRLIT_ga_pcrel /* 620 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p} $Rt, $addr */
+  ARM_t2LDRSBpcrel /* 621 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p} $Rt, $addr */
+  ARM_t2LDRSHpcrel /* 622 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}.w $Rt, $Rn, $imm */
+  ARM_t2LDR_POST_imm /* 623 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}.w $Rt, $addr! */
+  ARM_t2LDR_PRE_imm /* 624 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LDRpci_pic /* 625 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p} $Rt, $addr */
+  ARM_t2LDRpcrel /* 626 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LEApcrel /* 627 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LEApcrelJT /* 628 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LoopDec /* 629 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LoopEnd /* 630 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2LoopEndDec /* 631 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCCasr /* 632 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCCi /* 633 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCCi16 /* 634 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCCi32imm /* 635 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCClsl /* 636 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCClsr /* 637 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCCr /* 638 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVCCror /* 639 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* movs${p} $Rd, $shift */
+  ARM_t2MOVSsi /* 640 */, ARM_INS_MOVS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* movs${p} $Rd, $shift */
+  ARM_t2MOVSsr /* 641 */, ARM_INS_MOVS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVTi16_ga_pcrel /* 642 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOV_ga_pcrel /* 643 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVi16_ga_pcrel /* 644 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MOVi32imm /* 645 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${p} $Rd, $shift */
+  ARM_t2MOVsi /* 646 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${p} $Rd, $shift */
+  ARM_t2MOVsr /* 647 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2MVNCCi /* 648 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2RSBSri /* 649 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2RSBSrs /* 650 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2STRB_preidx /* 651 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2STRH_preidx /* 652 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}.w $Rt, $Rn, $imm */
+  ARM_t2STR_POST_imm /* 653 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}.w $Rt, $addr! */
+  ARM_t2STR_PRE_imm /* 654 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2STR_preidx /* 655 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2SUBSri /* 656 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2SUBSrr /* 657 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2SUBSrs /* 658 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2SpeculationBarrierISBDSBEndBB /* 659 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2SpeculationBarrierSBEndBB /* 660 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2TBB_JT /* 661 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2TBH_JT /* 662 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2WhileLoopSetup /* 663 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2WhileLoopStart /* 664 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2WhileLoopStartLR /* 665 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2WhileLoopStartTP /* 666 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADCS /* 667 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADDSi3 /* 668 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADDSi8 /* 669 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADDSrr /* 670 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADDframe /* 671 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADJCALLSTACKDOWN /* 672 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tADJCALLSTACKUP /* 673 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBLXNS_CALL /* 674 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBLXr_noip /* 675 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBL_PUSHLR /* 676 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBRIND /* 677 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBR_JTr /* 678 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBXNS_RET /* 679 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBX_CALL /* 680 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBX_RET /* 681 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBX_RET_vararg /* 682 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tBfar /* 683 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tCMP_SWAP_16 /* 684 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tCMP_SWAP_32 /* 685 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tCMP_SWAP_8 /* 686 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLDMIA_UPD /* 687 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p} $Rt, $immediate */
+  ARM_tLDRConstPool /* 688 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLDRLIT_ga_abs /* 689 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLDRLIT_ga_pcrel /* 690 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLDR_postidx /* 691 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLDRpci_pic /* 692 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLEApcrel /* 693 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLEApcrelJT /* 694 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tLSLSri /* 695 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tMOVCCr_pseudo /* 696 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tPOP_RET /* 697 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tRSBS /* 698 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tSBCS /* 699 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tSUBSi3 /* 700 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tSUBSi8 /* 701 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tSUBSrr /* 702 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tTAILJMPd /* 703 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tTAILJMPdND /* 704 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tTAILJMPr /* 705 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tTBB_JT /* 706 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tTBH_JT /* 707 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tTPsoft /* 708 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}	$Rd, $Rn, $imm */
+  ARM_ADCri /* 709 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}	$Rd, $Rn, $Rm */
+  ARM_ADCrr /* 710 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}	$Rd, $Rn, $shift */
+  ARM_ADCrsi /* 711 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}	$Rd, $Rn, $shift */
+  ARM_ADCrsr /* 712 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rd, $Rn, $imm */
+  ARM_ADDri /* 713 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rd, $Rn, $Rm */
+  ARM_ADDrr /* 714 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rd, $Rn, $shift */
+  ARM_ADDrsi /* 715 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rd, $Rn, $shift */
+  ARM_ADDrsr /* 716 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* adr${p}	$Rd, $label */
+  ARM_ADR /* 717 */, ARM_INS_ADR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* aesd.8	$Vd, $Vm */
+  ARM_AESD /* 718 */, ARM_INS_AESD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0
+  #endif
+},
+{
+  /* aese.8	$Vd, $Vm */
+  ARM_AESE /* 719 */, ARM_INS_AESE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0
+  #endif
+},
+{
+  /* aesimc.8	$Vd, $Vm */
+  ARM_AESIMC /* 720 */, ARM_INS_AESIMC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0
+  #endif
+},
+{
+  /* aesmc.8	$Vd, $Vm */
+  ARM_AESMC /* 721 */, ARM_INS_AESMC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}	$Rd, $Rn, $imm */
+  ARM_ANDri /* 722 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}	$Rd, $Rn, $Rm */
+  ARM_ANDrr /* 723 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}	$Rd, $Rn, $shift */
+  ARM_ANDrsi /* 724 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}	$Rd, $Rn, $shift */
+  ARM_ANDrsr /* 725 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdot.bf16	$Vd, $Vn, $Vm$lane */
+  ARM_BF16VDOTI_VDOTD /* 726 */, ARM_INS_VDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdot.bf16	$Vd, $Vn, $Vm$lane */
+  ARM_BF16VDOTI_VDOTQ /* 727 */, ARM_INS_VDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdot.bf16	$Vd, $Vn, $Vm */
+  ARM_BF16VDOTS_VDOTD /* 728 */, ARM_INS_VDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdot.bf16	$Vd, $Vn, $Vm */
+  ARM_BF16VDOTS_VDOTQ /* 729 */, ARM_INS_VDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.bf16.f32	$Vd, $Vm */
+  ARM_BF16_VCVT /* 730 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${p}.bf16.f32	$Sd, $Sm */
+  ARM_BF16_VCVTB /* 731 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${p}.bf16.f32	$Sd, $Sm */
+  ARM_BF16_VCVTT /* 732 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, 0 }, 0, 0
+  #endif
+},
+{
+  /* bfc${p}	$Rd, $imm */
+  ARM_BFC /* 733 */, ARM_INS_BFC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bfi${p}	$Rd, $Rn, $imm */
+  ARM_BFI /* 734 */, ARM_INS_BFI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}	$Rd, $Rn, $imm */
+  ARM_BICri /* 735 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}	$Rd, $Rn, $Rm */
+  ARM_BICrr /* 736 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}	$Rd, $Rn, $shift */
+  ARM_BICrsi /* 737 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}	$Rd, $Rn, $shift */
+  ARM_BICrsr /* 738 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* bkpt	$val */
+  ARM_BKPT /* 739 */, ARM_INS_BKPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* bl	$func */
+  ARM_BL /* 740 */, ARM_INS_BL,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* blx	$func */
+  ARM_BLX /* 741 */, ARM_INS_BLX,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0
+  #endif
+},
+{
+  /* blx${p}	$func */
+  ARM_BLX_pred /* 742 */, ARM_INS_BLX,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0
+  #endif
+},
+{
+  /* blx	$target */
+  ARM_BLXi /* 743 */, ARM_INS_BLX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0
+  #endif
+},
+{
+  /* bl${p}	$func */
+  ARM_BL_pred /* 744 */, ARM_INS_BL,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* bx	$dst */
+  ARM_BX /* 745 */, ARM_INS_BX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsARM, ARM_FEATURE_HasV4T, 0 }, 1, 1
+  #endif
+},
+{
+  /* bxj${p}	$func */
+  ARM_BXJ /* 746 */, ARM_INS_BXJ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsARM, 0 }, 1, 1
+  #endif
+},
+{
+  /* bx${p}	lr */
+  ARM_BX_RET /* 747 */, ARM_INS_BX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV4T, 0 }, 0, 0
+  #endif
+},
+{
+  /* bx${p}	$dst */
+  ARM_BX_pred /* 748 */, ARM_INS_BX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsARM, ARM_FEATURE_HasV4T, 0 }, 1, 1
+  #endif
+},
+{
+  /* b${p}	$target */
+  ARM_Bcc /* 749 */, ARM_INS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsARM, 0 }, 1, 0
+  #endif
+},
+{
+  /* cx1	$coproc, $Rd, $imm */
+  ARM_CDE_CX1 /* 750 */, ARM_INS_CX1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx1a${p}	$coproc, $Rd, $imm */
+  ARM_CDE_CX1A /* 751 */, ARM_INS_CX1A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx1d	$coproc, $Rd, $imm */
+  ARM_CDE_CX1D /* 752 */, ARM_INS_CX1D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx1da${p}	$coproc, $Rd, $imm */
+  ARM_CDE_CX1DA /* 753 */, ARM_INS_CX1DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx2	$coproc, $Rd, $Rn, $imm */
+  ARM_CDE_CX2 /* 754 */, ARM_INS_CX2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx2a${p}	$coproc, $Rd, $Rn, $imm */
+  ARM_CDE_CX2A /* 755 */, ARM_INS_CX2A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx2d	$coproc, $Rd, $Rn, $imm */
+  ARM_CDE_CX2D /* 756 */, ARM_INS_CX2D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx2da${p}	$coproc, $Rd, $Rn, $imm */
+  ARM_CDE_CX2DA /* 757 */, ARM_INS_CX2DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx3	$coproc, $Rd, $Rn, $Rm, $imm */
+  ARM_CDE_CX3 /* 758 */, ARM_INS_CX3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx3a${p}	$coproc, $Rd, $Rn, $Rm, $imm */
+  ARM_CDE_CX3A /* 759 */, ARM_INS_CX3A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx3d	$coproc, $Rd, $Rn, $Rm, $imm */
+  ARM_CDE_CX3D /* 760 */, ARM_INS_CX3D,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* cx3da${p}	$coproc, $Rd, $Rn, $Rm, $imm */
+  ARM_CDE_CX3DA /* 761 */, ARM_INS_CX3DA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx1a	$coproc, $Vd, $imm */
+  ARM_CDE_VCX1A_fpdp /* 762 */, ARM_INS_VCX1A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx1a	$coproc, $Vd, $imm */
+  ARM_CDE_VCX1A_fpsp /* 763 */, ARM_INS_VCX1A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx1a${vp}	$coproc, $Qd, $imm */
+  ARM_CDE_VCX1A_vec /* 764 */, ARM_INS_VCX1A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx1	$coproc, $Vd, $imm */
+  ARM_CDE_VCX1_fpdp /* 765 */, ARM_INS_VCX1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx1	$coproc, $Vd, $imm */
+  ARM_CDE_VCX1_fpsp /* 766 */, ARM_INS_VCX1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx1${vp}	$coproc, $Qd, $imm */
+  ARM_CDE_VCX1_vec /* 767 */, ARM_INS_VCX1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx2a	$coproc, $Vd, $Vm, $imm */
+  ARM_CDE_VCX2A_fpdp /* 768 */, ARM_INS_VCX2A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx2a	$coproc, $Vd, $Vm, $imm */
+  ARM_CDE_VCX2A_fpsp /* 769 */, ARM_INS_VCX2A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx2a${vp}	$coproc, $Qd, $Qm, $imm */
+  ARM_CDE_VCX2A_vec /* 770 */, ARM_INS_VCX2A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx2	$coproc, $Vd, $Vm, $imm */
+  ARM_CDE_VCX2_fpdp /* 771 */, ARM_INS_VCX2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx2	$coproc, $Vd, $Vm, $imm */
+  ARM_CDE_VCX2_fpsp /* 772 */, ARM_INS_VCX2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx2${vp}	$coproc, $Qd, $Qm, $imm */
+  ARM_CDE_VCX2_vec /* 773 */, ARM_INS_VCX2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx3a	$coproc, $Vd, $Vn, $Vm, $imm */
+  ARM_CDE_VCX3A_fpdp /* 774 */, ARM_INS_VCX3A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx3a	$coproc, $Vd, $Vn, $Vm, $imm */
+  ARM_CDE_VCX3A_fpsp /* 775 */, ARM_INS_VCX3A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx3a${vp}	$coproc, $Qd, $Qn, $Qm, $imm */
+  ARM_CDE_VCX3A_vec /* 776 */, ARM_INS_VCX3A,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx3	$coproc, $Vd, $Vn, $Vm, $imm */
+  ARM_CDE_VCX3_fpdp /* 777 */, ARM_INS_VCX3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx3	$coproc, $Vd, $Vn, $Vm, $imm */
+  ARM_CDE_VCX3_fpsp /* 778 */, ARM_INS_VCX3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcx3${vp}	$coproc, $Qd, $Qn, $Qm, $imm */
+  ARM_CDE_VCX3_vec /* 779 */, ARM_INS_VCX3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasCDE, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* cdp${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+  ARM_CDP /* 780 */, ARM_INS_CDP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* cdp2	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+  ARM_CDP2 /* 781 */, ARM_INS_CDP2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* clrex */
+  ARM_CLREX /* 782 */, ARM_INS_CLREX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6K, 0 }, 0, 0
+  #endif
+},
+{
+  /* clz${p}	$Rd, $Rm */
+  ARM_CLZ /* 783 */, ARM_INS_CLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5T, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}	$Rn, $imm */
+  ARM_CMNri /* 784 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}	$Rn, $Rm */
+  ARM_CMNzrr /* 785 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}	$Rn, $shift */
+  ARM_CMNzrsi /* 786 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}	$Rn, $shift */
+  ARM_CMNzrsr /* 787 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $imm */
+  ARM_CMPri /* 788 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $Rm */
+  ARM_CMPrr /* 789 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $shift */
+  ARM_CMPrsi /* 790 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $shift */
+  ARM_CMPrsr /* 791 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps	$mode */
+  ARM_CPS1p /* 792 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps$imod	$iflags */
+  ARM_CPS2p /* 793 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps$imod	$iflags, $mode */
+  ARM_CPS3p /* 794 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32b	$Rd, $Rn, $Rm */
+  ARM_CRC32B /* 795 */, ARM_INS_CRC32B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32cb	$Rd, $Rn, $Rm */
+  ARM_CRC32CB /* 796 */, ARM_INS_CRC32CB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32ch	$Rd, $Rn, $Rm */
+  ARM_CRC32CH /* 797 */, ARM_INS_CRC32CH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32cw	$Rd, $Rn, $Rm */
+  ARM_CRC32CW /* 798 */, ARM_INS_CRC32CW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32h	$Rd, $Rn, $Rm */
+  ARM_CRC32H /* 799 */, ARM_INS_CRC32H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32w	$Rd, $Rn, $Rm */
+  ARM_CRC32W /* 800 */, ARM_INS_CRC32W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* dbg${p}	$opt */
+  ARM_DBG /* 801 */, ARM_INS_DBG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* dmb	$opt */
+  ARM_DMB /* 802 */, ARM_INS_DMB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDB, 0 }, 0, 0
+  #endif
+},
+{
+  /* dsb	$opt */
+  ARM_DSB /* 803 */, ARM_INS_DSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDB, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}	$Rd, $Rn, $imm */
+  ARM_EORri /* 804 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}	$Rd, $Rn, $Rm */
+  ARM_EORrr /* 805 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}	$Rd, $Rn, $shift */
+  ARM_EORrsi /* 806 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}	$Rd, $Rn, $shift */
+  ARM_EORrsr /* 807 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* eret${p} */
+  ARM_ERET /* 808 */, ARM_INS_ERET,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_PC, 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f64	$Dd, $imm */
+  ARM_FCONSTD /* 809 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP3, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f16	$Sd, $imm */
+  ARM_FCONSTH /* 810 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f32	$Sd, $imm */
+  ARM_FCONSTS /* 811 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP3, 0 }, 0, 0
+  #endif
+},
+{
+  /* fldmdbx${p}	$Rn!, $regs */
+  ARM_FLDMXDB_UPD /* 812 */, ARM_INS_FLDMDBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* fldmiax${p}	$Rn, $regs */
+  ARM_FLDMXIA /* 813 */, ARM_INS_FLDMIAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* fldmiax${p}	$Rn!, $regs */
+  ARM_FLDMXIA_UPD /* 814 */, ARM_INS_FLDMIAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	APSR_nzcv, fpscr */
+  ARM_FMSTAT /* 815 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR_NZCV, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* fstmdbx${p}	$Rn!, $regs */
+  ARM_FSTMXDB_UPD /* 816 */, ARM_INS_FSTMDBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* fstmiax${p}	$Rn, $regs */
+  ARM_FSTMXIA /* 817 */, ARM_INS_FSTMIAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* fstmiax${p}	$Rn!, $regs */
+  ARM_FSTMXIA_UPD /* 818 */, ARM_INS_FSTMIAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* hint${p}	$imm */
+  ARM_HINT /* 819 */, ARM_INS_HINT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* hlt	$val */
+  ARM_HLT /* 820 */, ARM_INS_HLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* hvc	$imm */
+  ARM_HVC /* 821 */, ARM_INS_HVC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* isb	$opt */
+  ARM_ISB /* 822 */, ARM_INS_ISB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDB, 0 }, 0, 0
+  #endif
+},
+{
+  /* lda${p}	$Rt, $addr */
+  ARM_LDA /* 823 */, ARM_INS_LDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldab${p}	$Rt, $addr */
+  ARM_LDAB /* 824 */, ARM_INS_LDAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaex${p}	$Rt, $addr */
+  ARM_LDAEX /* 825 */, ARM_INS_LDAEX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaexb${p}	$Rt, $addr */
+  ARM_LDAEXB /* 826 */, ARM_INS_LDAEXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaexd${p}	$Rt, $addr */
+  ARM_LDAEXD /* 827 */, ARM_INS_LDAEXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaexh${p}	$Rt, $addr */
+  ARM_LDAEXH /* 828 */, ARM_INS_LDAEXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldah${p}	$Rt, $addr */
+  ARM_LDAH /* 829 */, ARM_INS_LDAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l	$cop, $CRd, $addr */
+  ARM_LDC2L_OFFSET /* 830 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l	$cop, $CRd, $addr, $option */
+  ARM_LDC2L_OPTION /* 831 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l	$cop, $CRd, $addr, $offset */
+  ARM_LDC2L_POST /* 832 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l	$cop, $CRd, $addr! */
+  ARM_LDC2L_PRE /* 833 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2	$cop, $CRd, $addr */
+  ARM_LDC2_OFFSET /* 834 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2	$cop, $CRd, $addr, $option */
+  ARM_LDC2_OPTION /* 835 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2	$cop, $CRd, $addr, $offset */
+  ARM_LDC2_POST /* 836 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2	$cop, $CRd, $addr! */
+  ARM_LDC2_PRE /* 837 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr */
+  ARM_LDCL_OFFSET /* 838 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr, $option */
+  ARM_LDCL_OPTION /* 839 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr, $offset */
+  ARM_LDCL_POST /* 840 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr! */
+  ARM_LDCL_PRE /* 841 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr */
+  ARM_LDC_OFFSET /* 842 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr, $option */
+  ARM_LDC_OPTION /* 843 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr, $offset */
+  ARM_LDC_POST /* 844 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr! */
+  ARM_LDC_PRE /* 845 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmda${p}	$Rn, $regs */
+  ARM_LDMDA /* 846 */, ARM_INS_LDMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmda${p}	$Rn!, $regs */
+  ARM_LDMDA_UPD /* 847 */, ARM_INS_LDMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmdb${p}	$Rn, $regs */
+  ARM_LDMDB /* 848 */, ARM_INS_LDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmdb${p}	$Rn!, $regs */
+  ARM_LDMDB_UPD /* 849 */, ARM_INS_LDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}	$Rn, $regs */
+  ARM_LDMIA /* 850 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}	$Rn!, $regs */
+  ARM_LDMIA_UPD /* 851 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmib${p}	$Rn, $regs */
+  ARM_LDMIB /* 852 */, ARM_INS_LDMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmib${p}	$Rn!, $regs */
+  ARM_LDMIB_UPD /* 853 */, ARM_INS_LDMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrbt${p}	$Rt, $addr, $offset */
+  ARM_LDRBT_POST_IMM /* 854 */, ARM_INS_LDRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrbt${p}	$Rt, $addr, $offset */
+  ARM_LDRBT_POST_REG /* 855 */, ARM_INS_LDRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr, $offset */
+  ARM_LDRB_POST_IMM /* 856 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr, $offset */
+  ARM_LDRB_POST_REG /* 857 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr! */
+  ARM_LDRB_PRE_IMM /* 858 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr! */
+  ARM_LDRB_PRE_REG /* 859 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr */
+  ARM_LDRBi12 /* 860 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $shift */
+  ARM_LDRBrs /* 861 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrd${p}	$Rt, $Rt2, $addr */
+  ARM_LDRD /* 862 */, ARM_INS_LDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrd${p}	$Rt, $Rt2, $addr, $offset */
+  ARM_LDRD_POST /* 863 */, ARM_INS_LDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrd${p}	$Rt, $Rt2, $addr! */
+  ARM_LDRD_PRE /* 864 */, ARM_INS_LDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrex${p}	$Rt, $addr */
+  ARM_LDREX /* 865 */, ARM_INS_LDREX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrexb${p}	$Rt, $addr */
+  ARM_LDREXB /* 866 */, ARM_INS_LDREXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrexd${p}	$Rt, $addr */
+  ARM_LDREXD /* 867 */, ARM_INS_LDREXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrexh${p}	$Rt, $addr */
+  ARM_LDREXH /* 868 */, ARM_INS_LDREXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr */
+  ARM_LDRH /* 869 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrht${p}	$Rt, $addr, $offset */
+  ARM_LDRHTi /* 870 */, ARM_INS_LDRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrht${p}	$Rt, $addr, $Rm */
+  ARM_LDRHTr /* 871 */, ARM_INS_LDRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr, $offset */
+  ARM_LDRH_POST /* 872 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr! */
+  ARM_LDRH_PRE /* 873 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $addr */
+  ARM_LDRSB /* 874 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsbt${p}	$Rt, $addr, $offset */
+  ARM_LDRSBTi /* 875 */, ARM_INS_LDRSBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsbt${p}	$Rt, $addr, $Rm */
+  ARM_LDRSBTr /* 876 */, ARM_INS_LDRSBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $addr, $offset */
+  ARM_LDRSB_POST /* 877 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $addr! */
+  ARM_LDRSB_PRE /* 878 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $addr */
+  ARM_LDRSH /* 879 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsht${p}	$Rt, $addr, $offset */
+  ARM_LDRSHTi /* 880 */, ARM_INS_LDRSHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsht${p}	$Rt, $addr, $Rm */
+  ARM_LDRSHTr /* 881 */, ARM_INS_LDRSHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $addr, $offset */
+  ARM_LDRSH_POST /* 882 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $addr! */
+  ARM_LDRSH_PRE /* 883 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrt${p}	$Rt, $addr, $offset */
+  ARM_LDRT_POST_IMM /* 884 */, ARM_INS_LDRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrt${p}	$Rt, $addr, $offset */
+  ARM_LDRT_POST_REG /* 885 */, ARM_INS_LDRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr, $offset */
+  ARM_LDR_POST_IMM /* 886 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr, $offset */
+  ARM_LDR_POST_REG /* 887 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr! */
+  ARM_LDR_PRE_IMM /* 888 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr! */
+  ARM_LDR_PRE_REG /* 889 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_LDRcp /* 890 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_LDRi12 /* 891 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $shift */
+  ARM_LDRrs /* 892 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcr${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_MCR /* 893 */, ARM_INS_MCR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcr2	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_MCR2 /* 894 */, ARM_INS_MCR2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcrr${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_MCRR /* 895 */, ARM_INS_MCRR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcrr2	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_MCRR2 /* 896 */, ARM_INS_MCRR2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mla${s}${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_MLA /* 897 */, ARM_INS_MLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* mls${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_MLS /* 898 */, ARM_INS_MLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${p}	pc, lr */
+  ARM_MOVPCLR /* 899 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* movt${p}	$Rd, $imm */
+  ARM_MOVTi16 /* 900 */, ARM_INS_MOVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}	$Rd, $imm */
+  ARM_MOVi /* 901 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* movw${p}	$Rd, $imm */
+  ARM_MOVi16 /* 902 */, ARM_INS_MOVW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}	$Rd, $Rm */
+  ARM_MOVr /* 903 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}	$Rd, $Rm */
+  ARM_MOVr_TC /* 904 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}	$Rd, $src */
+  ARM_MOVsi /* 905 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}	$Rd, $src */
+  ARM_MOVsr /* 906 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrc${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_MRC /* 907 */, ARM_INS_MRC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrc2	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_MRC2 /* 908 */, ARM_INS_MRC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrrc${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_MRRC /* 909 */, ARM_INS_MRRC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrrc2	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_MRRC2 /* 910 */, ARM_INS_MRRC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, apsr */
+  ARM_MRS /* 911 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, $banked */
+  ARM_MRSbanked /* 912 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, spsr */
+  ARM_MRSsys /* 913 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* msr${p}	$mask, $Rn */
+  ARM_MSR /* 914 */, ARM_INS_MSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* msr${p}	$banked, $Rn */
+  ARM_MSRbanked /* 915 */, ARM_INS_MSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* msr${p}	$mask, $imm */
+  ARM_MSRi /* 916 */, ARM_INS_MSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mul${s}${p}	$Rd, $Rn, $Rm */
+  ARM_MUL /* 917 */, ARM_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* asrl${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_ASRLi /* 918 */, ARM_INS_ASRL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* asrl${p}	$RdaLo, $RdaHi, $Rm */
+  ARM_MVE_ASRLr /* 919 */, ARM_INS_ASRL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* dlstp.16	$LR, $Rn */
+  ARM_MVE_DLSTP_16 /* 920 */, ARM_INS_DLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* dlstp.32	$LR, $Rn */
+  ARM_MVE_DLSTP_32 /* 921 */, ARM_INS_DLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* dlstp.64	$LR, $Rn */
+  ARM_MVE_DLSTP_64 /* 922 */, ARM_INS_DLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* dlstp.8	$LR, $Rn */
+  ARM_MVE_DLSTP_8 /* 923 */, ARM_INS_DLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* lctp${p}	 */
+  ARM_MVE_LCTP /* 924 */, ARM_INS_LCTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* letp	$LRin, $label */
+  ARM_MVE_LETP /* 925 */, ARM_INS_LETP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0
+  #endif
+},
+{
+  /* lsll${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_LSLLi /* 926 */, ARM_INS_LSLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsll${p}	$RdaLo, $RdaHi, $Rm */
+  ARM_MVE_LSLLr /* 927 */, ARM_INS_LSLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsrl${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_LSRL /* 928 */, ARM_INS_LSRL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* sqrshr${p}	$RdaSrc, $Rm */
+  ARM_MVE_SQRSHR /* 929 */, ARM_INS_SQRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* sqrshrl${p}	$RdaLo, $RdaHi, $sat, $Rm */
+  ARM_MVE_SQRSHRL /* 930 */, ARM_INS_SQRSHRL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* sqshl${p}	$RdaSrc, $imm */
+  ARM_MVE_SQSHL /* 931 */, ARM_INS_SQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* sqshll${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_SQSHLL /* 932 */, ARM_INS_SQSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* srshr${p}	$RdaSrc, $imm */
+  ARM_MVE_SRSHR /* 933 */, ARM_INS_SRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* srshrl${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_SRSHRL /* 934 */, ARM_INS_SRSHRL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqrshl${p}	$RdaSrc, $Rm */
+  ARM_MVE_UQRSHL /* 935 */, ARM_INS_UQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqrshll${p}	$RdaLo, $RdaHi, $sat, $Rm */
+  ARM_MVE_UQRSHLL /* 936 */, ARM_INS_UQRSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqshl${p}	$RdaSrc, $imm */
+  ARM_MVE_UQSHL /* 937 */, ARM_INS_UQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqshll${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_UQSHLL /* 938 */, ARM_INS_UQSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* urshr${p}	$RdaSrc, $imm */
+  ARM_MVE_URSHR /* 939 */, ARM_INS_URSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* urshrl${p}	$RdaLo, $RdaHi, $imm */
+  ARM_MVE_URSHRL /* 940 */, ARM_INS_URSHRL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabav${vp}.s16	$Rda, $Qn, $Qm */
+  ARM_MVE_VABAVs16 /* 941 */, ARM_INS_VABAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabav${vp}.s32	$Rda, $Qn, $Qm */
+  ARM_MVE_VABAVs32 /* 942 */, ARM_INS_VABAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabav${vp}.s8	$Rda, $Qn, $Qm */
+  ARM_MVE_VABAVs8 /* 943 */, ARM_INS_VABAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabav${vp}.u16	$Rda, $Qn, $Qm */
+  ARM_MVE_VABAVu16 /* 944 */, ARM_INS_VABAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabav${vp}.u32	$Rda, $Qn, $Qm */
+  ARM_MVE_VABAVu32 /* 945 */, ARM_INS_VABAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabav${vp}.u8	$Rda, $Qn, $Qm */
+  ARM_MVE_VABAVu8 /* 946 */, ARM_INS_VABAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDf16 /* 947 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDf32 /* 948 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDs16 /* 949 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDs32 /* 950 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDs8 /* 951 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDu16 /* 952 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDu32 /* 953 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VABDu8 /* 954 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VABSf16 /* 955 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VABSf32 /* 956 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VABSs16 /* 957 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VABSs32 /* 958 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VABSs8 /* 959 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadc${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VADC /* 960 */, ARM_INS_VADC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadci${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VADCI /* 961 */, ARM_INS_VADCI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddlva${vp}.s32	$RdaLo, $RdaHi, $Qm */
+  ARM_MVE_VADDLVs32acc /* 962 */, ARM_INS_VADDLVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddlv${vp}.s32	$RdaLo, $RdaHi, $Qm */
+  ARM_MVE_VADDLVs32no_acc /* 963 */, ARM_INS_VADDLV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddlva${vp}.u32	$RdaLo, $RdaHi, $Qm */
+  ARM_MVE_VADDLVu32acc /* 964 */, ARM_INS_VADDLVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddlv${vp}.u32	$RdaLo, $RdaHi, $Qm */
+  ARM_MVE_VADDLVu32no_acc /* 965 */, ARM_INS_VADDLV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddva${vp}.s16	$Rda, $Qm */
+  ARM_MVE_VADDVs16acc /* 966 */, ARM_INS_VADDVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddv${vp}.s16	$Rda, $Qm */
+  ARM_MVE_VADDVs16no_acc /* 967 */, ARM_INS_VADDV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddva${vp}.s32	$Rda, $Qm */
+  ARM_MVE_VADDVs32acc /* 968 */, ARM_INS_VADDVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddv${vp}.s32	$Rda, $Qm */
+  ARM_MVE_VADDVs32no_acc /* 969 */, ARM_INS_VADDV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddva${vp}.s8	$Rda, $Qm */
+  ARM_MVE_VADDVs8acc /* 970 */, ARM_INS_VADDVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddv${vp}.s8	$Rda, $Qm */
+  ARM_MVE_VADDVs8no_acc /* 971 */, ARM_INS_VADDV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddva${vp}.u16	$Rda, $Qm */
+  ARM_MVE_VADDVu16acc /* 972 */, ARM_INS_VADDVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddv${vp}.u16	$Rda, $Qm */
+  ARM_MVE_VADDVu16no_acc /* 973 */, ARM_INS_VADDV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddva${vp}.u32	$Rda, $Qm */
+  ARM_MVE_VADDVu32acc /* 974 */, ARM_INS_VADDVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddv${vp}.u32	$Rda, $Qm */
+  ARM_MVE_VADDVu32no_acc /* 975 */, ARM_INS_VADDV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddva${vp}.u8	$Rda, $Qm */
+  ARM_MVE_VADDVu8acc /* 976 */, ARM_INS_VADDVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddv${vp}.u8	$Rda, $Qm */
+  ARM_MVE_VADDVu8no_acc /* 977 */, ARM_INS_VADDV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.f16	$Qd, $Qn, $Rm */
+  ARM_MVE_VADD_qr_f16 /* 978 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.f32	$Qd, $Qn, $Rm */
+  ARM_MVE_VADD_qr_f32 /* 979 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.i16	$Qd, $Qn, $Rm */
+  ARM_MVE_VADD_qr_i16 /* 980 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.i32	$Qd, $Qn, $Rm */
+  ARM_MVE_VADD_qr_i32 /* 981 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.i8	$Qd, $Qn, $Rm */
+  ARM_MVE_VADD_qr_i8 /* 982 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VADDf16 /* 983 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VADDf32 /* 984 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.i16	$Qd, $Qn, $Qm */
+  ARM_MVE_VADDi16 /* 985 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VADDi32 /* 986 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${vp}.i8	$Qd, $Qn, $Qm */
+  ARM_MVE_VADDi8 /* 987 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vand${vp}	$Qd, $Qn, $Qm */
+  ARM_MVE_VAND /* 988 */, ARM_INS_VAND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${vp}	$Qd, $Qn, $Qm */
+  ARM_MVE_VBIC /* 989 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${vp}.i16	$Qd, $imm */
+  ARM_MVE_VBICimmi16 /* 990 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${vp}.i32	$Qd, $imm */
+  ARM_MVE_VBICimmi32 /* 991 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbrsr${vp}.16	$Qd, $Qn, $Rm */
+  ARM_MVE_VBRSR16 /* 992 */, ARM_INS_VBRSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbrsr${vp}.32	$Qd, $Qn, $Rm */
+  ARM_MVE_VBRSR32 /* 993 */, ARM_INS_VBRSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbrsr${vp}.8	$Qd, $Qn, $Rm */
+  ARM_MVE_VBRSR8 /* 994 */, ARM_INS_VBRSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd${vp}.f16	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCADDf16 /* 995 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd${vp}.f32	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCADDf32 /* 996 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd${vp}.i16	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCADDi16 /* 997 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd${vp}.i32	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCADDi32 /* 998 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd${vp}.i8	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCADDi8 /* 999 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VCLSs16 /* 1000 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VCLSs32 /* 1001 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VCLSs8 /* 1002 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${vp}.i16	$Qd, $Qm */
+  ARM_MVE_VCLZs16 /* 1003 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${vp}.i32	$Qd, $Qm */
+  ARM_MVE_VCLZs32 /* 1004 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${vp}.i8	$Qd, $Qm */
+  ARM_MVE_VCLZs8 /* 1005 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla${vp}.f16	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCMLAf16 /* 1006 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla${vp}.f32	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCMLAf32 /* 1007 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.f16	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPf16 /* 1008 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.f16	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPf16r /* 1009 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.f32	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPf32 /* 1010 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.f32	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPf32r /* 1011 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.i16	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPi16 /* 1012 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.i16	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPi16r /* 1013 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.i32	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPi32 /* 1014 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.i32	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPi32r /* 1015 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.i8	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPi8 /* 1016 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.i8	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPi8r /* 1017 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.s16	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPs16 /* 1018 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.s16	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPs16r /* 1019 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.s32	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPs32 /* 1020 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.s32	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPs32r /* 1021 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.s8	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPs8 /* 1022 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.s8	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPs8r /* 1023 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.u16	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPu16 /* 1024 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.u16	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPu16r /* 1025 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.u32	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPu32 /* 1026 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.u32	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPu32r /* 1027 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.u8	$fc, $Qn, $Qm */
+  ARM_MVE_VCMPu8 /* 1028 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${vp}.u8	$fc, $Qn, $Rm */
+  ARM_MVE_VCMPu8r /* 1029 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmul${vp}.f16	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCMULf16 /* 1030 */, ARM_INS_VCMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmul${vp}.f32	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VCMULf32 /* 1031 */, ARM_INS_VCMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vctp${vp}.16	$Rn */
+  ARM_MVE_VCTP16 /* 1032 */, ARM_INS_VCTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vctp${vp}.32	$Rn */
+  ARM_MVE_VCTP32 /* 1033 */, ARM_INS_VCTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vctp${vp}.64	$Rn */
+  ARM_MVE_VCTP64 /* 1034 */, ARM_INS_VCTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vctp${vp}.8	$Rn */
+  ARM_MVE_VCTP8 /* 1035 */, ARM_INS_VCTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${vp}.f16.f32	$Qd, $Qm */
+  ARM_MVE_VCVTf16f32bh /* 1036 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${vp}.f16.f32	$Qd, $Qm */
+  ARM_MVE_VCVTf16f32th /* 1037 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f16.s16	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTf16s16_fix /* 1038 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f16.s16	$Qd, $Qm */
+  ARM_MVE_VCVTf16s16n /* 1039 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f16.u16	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTf16u16_fix /* 1040 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f16.u16	$Qd, $Qm */
+  ARM_MVE_VCVTf16u16n /* 1041 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${vp}.f32.f16	$Qd, $Qm */
+  ARM_MVE_VCVTf32f16bh /* 1042 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${vp}.f32.f16	$Qd, $Qm */
+  ARM_MVE_VCVTf32f16th /* 1043 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f32.s32	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTf32s32_fix /* 1044 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f32.s32	$Qd, $Qm */
+  ARM_MVE_VCVTf32s32n /* 1045 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f32.u32	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTf32u32_fix /* 1046 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.f32.u32	$Qd, $Qm */
+  ARM_MVE_VCVTf32u32n /* 1047 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.s16.f16	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTs16f16_fix /* 1048 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta${vp}.s16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTs16f16a /* 1049 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm${vp}.s16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTs16f16m /* 1050 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn${vp}.s16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTs16f16n /* 1051 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp${vp}.s16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTs16f16p /* 1052 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.s16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTs16f16z /* 1053 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.s32.f32	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTs32f32_fix /* 1054 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta${vp}.s32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTs32f32a /* 1055 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm${vp}.s32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTs32f32m /* 1056 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn${vp}.s32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTs32f32n /* 1057 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp${vp}.s32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTs32f32p /* 1058 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.s32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTs32f32z /* 1059 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.u16.f16	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTu16f16_fix /* 1060 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta${vp}.u16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTu16f16a /* 1061 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm${vp}.u16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTu16f16m /* 1062 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn${vp}.u16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTu16f16n /* 1063 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp${vp}.u16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTu16f16p /* 1064 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.u16.f16	$Qd, $Qm */
+  ARM_MVE_VCVTu16f16z /* 1065 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.u32.f32	$Qd, $Qm, $imm6 */
+  ARM_MVE_VCVTu32f32_fix /* 1066 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta${vp}.u32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTu32f32a /* 1067 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm${vp}.u32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTu32f32m /* 1068 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn${vp}.u32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTu32f32n /* 1069 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp${vp}.u32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTu32f32p /* 1070 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${vp}.u32.f32	$Qd, $Qm */
+  ARM_MVE_VCVTu32f32z /* 1071 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vddup${vp}.u16	$Qd, $Rn, $imm */
+  ARM_MVE_VDDUPu16 /* 1072 */, ARM_INS_VDDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vddup${vp}.u32	$Qd, $Rn, $imm */
+  ARM_MVE_VDDUPu32 /* 1073 */, ARM_INS_VDDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vddup${vp}.u8	$Qd, $Rn, $imm */
+  ARM_MVE_VDDUPu8 /* 1074 */, ARM_INS_VDDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${vp}.16	$Qd, $Rt */
+  ARM_MVE_VDUP16 /* 1075 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${vp}.32	$Qd, $Rt */
+  ARM_MVE_VDUP32 /* 1076 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${vp}.8	$Qd, $Rt */
+  ARM_MVE_VDUP8 /* 1077 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdwdup${vp}.u16	$Qd, $Rn, $Rm, $imm */
+  ARM_MVE_VDWDUPu16 /* 1078 */, ARM_INS_VDWDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdwdup${vp}.u32	$Qd, $Rn, $Rm, $imm */
+  ARM_MVE_VDWDUPu32 /* 1079 */, ARM_INS_VDWDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdwdup${vp}.u8	$Qd, $Rn, $Rm, $imm */
+  ARM_MVE_VDWDUPu8 /* 1080 */, ARM_INS_VDWDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* veor${vp}	$Qd, $Qn, $Qm */
+  ARM_MVE_VEOR /* 1081 */, ARM_INS_VEOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmas${vp}.f16	$Qd, $Qn, $Rm */
+  ARM_MVE_VFMA_qr_Sf16 /* 1082 */, ARM_INS_VFMAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmas${vp}.f32	$Qd, $Qn, $Rm */
+  ARM_MVE_VFMA_qr_Sf32 /* 1083 */, ARM_INS_VFMAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${vp}.f16	$Qd, $Qn, $Rm */
+  ARM_MVE_VFMA_qr_f16 /* 1084 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${vp}.f32	$Qd, $Qn, $Rm */
+  ARM_MVE_VFMA_qr_f32 /* 1085 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VFMAf16 /* 1086 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VFMAf32 /* 1087 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VFMSf16 /* 1088 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VFMSf32 /* 1089 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VHADD_qr_s16 /* 1090 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VHADD_qr_s32 /* 1091 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VHADD_qr_s8 /* 1092 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.u16	$Qd, $Qn, $Rm */
+  ARM_MVE_VHADD_qr_u16 /* 1093 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.u32	$Qd, $Qn, $Rm */
+  ARM_MVE_VHADD_qr_u32 /* 1094 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.u8	$Qd, $Qn, $Rm */
+  ARM_MVE_VHADD_qr_u8 /* 1095 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VHADDs16 /* 1096 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VHADDs32 /* 1097 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VHADDs8 /* 1098 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VHADDu16 /* 1099 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VHADDu32 /* 1100 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VHADDu8 /* 1101 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhcadd${vp}.s16	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VHCADDs16 /* 1102 */, ARM_INS_VHCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhcadd${vp}.s32	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VHCADDs32 /* 1103 */, ARM_INS_VHCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhcadd${vp}.s8	$Qd, $Qn, $Qm, $rot */
+  ARM_MVE_VHCADDs8 /* 1104 */, ARM_INS_VHCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VHSUB_qr_s16 /* 1105 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VHSUB_qr_s32 /* 1106 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VHSUB_qr_s8 /* 1107 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.u16	$Qd, $Qn, $Rm */
+  ARM_MVE_VHSUB_qr_u16 /* 1108 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.u32	$Qd, $Qn, $Rm */
+  ARM_MVE_VHSUB_qr_u32 /* 1109 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.u8	$Qd, $Qn, $Rm */
+  ARM_MVE_VHSUB_qr_u8 /* 1110 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VHSUBs16 /* 1111 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VHSUBs32 /* 1112 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VHSUBs8 /* 1113 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VHSUBu16 /* 1114 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VHSUBu32 /* 1115 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VHSUBu8 /* 1116 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vidup${vp}.u16	$Qd, $Rn, $imm */
+  ARM_MVE_VIDUPu16 /* 1117 */, ARM_INS_VIDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vidup${vp}.u32	$Qd, $Rn, $imm */
+  ARM_MVE_VIDUPu32 /* 1118 */, ARM_INS_VIDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vidup${vp}.u8	$Qd, $Rn, $imm */
+  ARM_MVE_VIDUPu8 /* 1119 */, ARM_INS_VIDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* viwdup${vp}.u16	$Qd, $Rn, $Rm, $imm */
+  ARM_MVE_VIWDUPu16 /* 1120 */, ARM_INS_VIWDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* viwdup${vp}.u32	$Qd, $Rn, $Rm, $imm */
+  ARM_MVE_VIWDUPu32 /* 1121 */, ARM_INS_VIWDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* viwdup${vp}.u8	$Qd, $Rn, $Rm, $imm */
+  ARM_MVE_VIWDUPu8 /* 1122 */, ARM_INS_VIWDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld20.16	$VQd, $Rn */
+  ARM_MVE_VLD20_16 /* 1123 */, ARM_INS_VLD20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld20.16	$VQd, $Rn! */
+  ARM_MVE_VLD20_16_wb /* 1124 */, ARM_INS_VLD20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld20.32	$VQd, $Rn */
+  ARM_MVE_VLD20_32 /* 1125 */, ARM_INS_VLD20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld20.32	$VQd, $Rn! */
+  ARM_MVE_VLD20_32_wb /* 1126 */, ARM_INS_VLD20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld20.8	$VQd, $Rn */
+  ARM_MVE_VLD20_8 /* 1127 */, ARM_INS_VLD20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld20.8	$VQd, $Rn! */
+  ARM_MVE_VLD20_8_wb /* 1128 */, ARM_INS_VLD20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld21.16	$VQd, $Rn */
+  ARM_MVE_VLD21_16 /* 1129 */, ARM_INS_VLD21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld21.16	$VQd, $Rn! */
+  ARM_MVE_VLD21_16_wb /* 1130 */, ARM_INS_VLD21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld21.32	$VQd, $Rn */
+  ARM_MVE_VLD21_32 /* 1131 */, ARM_INS_VLD21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld21.32	$VQd, $Rn! */
+  ARM_MVE_VLD21_32_wb /* 1132 */, ARM_INS_VLD21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld21.8	$VQd, $Rn */
+  ARM_MVE_VLD21_8 /* 1133 */, ARM_INS_VLD21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld21.8	$VQd, $Rn! */
+  ARM_MVE_VLD21_8_wb /* 1134 */, ARM_INS_VLD21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld40.16	$VQd, $Rn */
+  ARM_MVE_VLD40_16 /* 1135 */, ARM_INS_VLD40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld40.16	$VQd, $Rn! */
+  ARM_MVE_VLD40_16_wb /* 1136 */, ARM_INS_VLD40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld40.32	$VQd, $Rn */
+  ARM_MVE_VLD40_32 /* 1137 */, ARM_INS_VLD40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld40.32	$VQd, $Rn! */
+  ARM_MVE_VLD40_32_wb /* 1138 */, ARM_INS_VLD40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld40.8	$VQd, $Rn */
+  ARM_MVE_VLD40_8 /* 1139 */, ARM_INS_VLD40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld40.8	$VQd, $Rn! */
+  ARM_MVE_VLD40_8_wb /* 1140 */, ARM_INS_VLD40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld41.16	$VQd, $Rn */
+  ARM_MVE_VLD41_16 /* 1141 */, ARM_INS_VLD41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld41.16	$VQd, $Rn! */
+  ARM_MVE_VLD41_16_wb /* 1142 */, ARM_INS_VLD41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld41.32	$VQd, $Rn */
+  ARM_MVE_VLD41_32 /* 1143 */, ARM_INS_VLD41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld41.32	$VQd, $Rn! */
+  ARM_MVE_VLD41_32_wb /* 1144 */, ARM_INS_VLD41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld41.8	$VQd, $Rn */
+  ARM_MVE_VLD41_8 /* 1145 */, ARM_INS_VLD41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld41.8	$VQd, $Rn! */
+  ARM_MVE_VLD41_8_wb /* 1146 */, ARM_INS_VLD41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld42.16	$VQd, $Rn */
+  ARM_MVE_VLD42_16 /* 1147 */, ARM_INS_VLD42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld42.16	$VQd, $Rn! */
+  ARM_MVE_VLD42_16_wb /* 1148 */, ARM_INS_VLD42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld42.32	$VQd, $Rn */
+  ARM_MVE_VLD42_32 /* 1149 */, ARM_INS_VLD42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld42.32	$VQd, $Rn! */
+  ARM_MVE_VLD42_32_wb /* 1150 */, ARM_INS_VLD42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld42.8	$VQd, $Rn */
+  ARM_MVE_VLD42_8 /* 1151 */, ARM_INS_VLD42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld42.8	$VQd, $Rn! */
+  ARM_MVE_VLD42_8_wb /* 1152 */, ARM_INS_VLD42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld43.16	$VQd, $Rn */
+  ARM_MVE_VLD43_16 /* 1153 */, ARM_INS_VLD43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld43.16	$VQd, $Rn! */
+  ARM_MVE_VLD43_16_wb /* 1154 */, ARM_INS_VLD43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld43.32	$VQd, $Rn */
+  ARM_MVE_VLD43_32 /* 1155 */, ARM_INS_VLD43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld43.32	$VQd, $Rn! */
+  ARM_MVE_VLD43_32_wb /* 1156 */, ARM_INS_VLD43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld43.8	$VQd, $Rn */
+  ARM_MVE_VLD43_8 /* 1157 */, ARM_INS_VLD43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld43.8	$VQd, $Rn! */
+  ARM_MVE_VLD43_8_wb /* 1158 */, ARM_INS_VLD43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s16	$Qd, $addr */
+  ARM_MVE_VLDRBS16 /* 1159 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s16	$Qd, $Rn$addr */
+  ARM_MVE_VLDRBS16_post /* 1160 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s16	$Qd, $addr! */
+  ARM_MVE_VLDRBS16_pre /* 1161 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s16	$Qd, $addr */
+  ARM_MVE_VLDRBS16_rq /* 1162 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s32	$Qd, $addr */
+  ARM_MVE_VLDRBS32 /* 1163 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s32	$Qd, $Rn$addr */
+  ARM_MVE_VLDRBS32_post /* 1164 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s32	$Qd, $addr! */
+  ARM_MVE_VLDRBS32_pre /* 1165 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.s32	$Qd, $addr */
+  ARM_MVE_VLDRBS32_rq /* 1166 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u16	$Qd, $addr */
+  ARM_MVE_VLDRBU16 /* 1167 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u16	$Qd, $Rn$addr */
+  ARM_MVE_VLDRBU16_post /* 1168 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u16	$Qd, $addr! */
+  ARM_MVE_VLDRBU16_pre /* 1169 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u16	$Qd, $addr */
+  ARM_MVE_VLDRBU16_rq /* 1170 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRBU32 /* 1171 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u32	$Qd, $Rn$addr */
+  ARM_MVE_VLDRBU32_post /* 1172 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u32	$Qd, $addr! */
+  ARM_MVE_VLDRBU32_pre /* 1173 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRBU32_rq /* 1174 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u8	$Qd, $addr */
+  ARM_MVE_VLDRBU8 /* 1175 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u8	$Qd, $Rn$addr */
+  ARM_MVE_VLDRBU8_post /* 1176 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u8	$Qd, $addr! */
+  ARM_MVE_VLDRBU8_pre /* 1177 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrb${vp}.u8	$Qd, $addr */
+  ARM_MVE_VLDRBU8_rq /* 1178 */, ARM_INS_VLDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrd${vp}.u64	$Qd, $addr */
+  ARM_MVE_VLDRDU64_qi /* 1179 */, ARM_INS_VLDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrd${vp}.u64	$Qd, $addr! */
+  ARM_MVE_VLDRDU64_qi_pre /* 1180 */, ARM_INS_VLDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrd${vp}.u64	$Qd, $addr */
+  ARM_MVE_VLDRDU64_rq /* 1181 */, ARM_INS_VLDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrd${vp}.u64	$Qd, $addr */
+  ARM_MVE_VLDRDU64_rq_u /* 1182 */, ARM_INS_VLDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.s32	$Qd, $addr */
+  ARM_MVE_VLDRHS32 /* 1183 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.s32	$Qd, $Rn$addr */
+  ARM_MVE_VLDRHS32_post /* 1184 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.s32	$Qd, $addr! */
+  ARM_MVE_VLDRHS32_pre /* 1185 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.s32	$Qd, $addr */
+  ARM_MVE_VLDRHS32_rq /* 1186 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.s32	$Qd, $addr */
+  ARM_MVE_VLDRHS32_rq_u /* 1187 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u16	$Qd, $addr */
+  ARM_MVE_VLDRHU16 /* 1188 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u16	$Qd, $Rn$addr */
+  ARM_MVE_VLDRHU16_post /* 1189 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u16	$Qd, $addr! */
+  ARM_MVE_VLDRHU16_pre /* 1190 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u16	$Qd, $addr */
+  ARM_MVE_VLDRHU16_rq /* 1191 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u16	$Qd, $addr */
+  ARM_MVE_VLDRHU16_rq_u /* 1192 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRHU32 /* 1193 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u32	$Qd, $Rn$addr */
+  ARM_MVE_VLDRHU32_post /* 1194 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u32	$Qd, $addr! */
+  ARM_MVE_VLDRHU32_pre /* 1195 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRHU32_rq /* 1196 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrh${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRHU32_rq_u /* 1197 */, ARM_INS_VLDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRWU32 /* 1198 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $Rn$addr */
+  ARM_MVE_VLDRWU32_post /* 1199 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $addr! */
+  ARM_MVE_VLDRWU32_pre /* 1200 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRWU32_qi /* 1201 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $addr! */
+  ARM_MVE_VLDRWU32_qi_pre /* 1202 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRWU32_rq /* 1203 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldrw${vp}.u32	$Qd, $addr */
+  ARM_MVE_VLDRWU32_rq_u /* 1204 */, ARM_INS_VLDRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxav${vp}.s16	$RdaSrc, $Qm */
+  ARM_MVE_VMAXAVs16 /* 1205 */, ARM_INS_VMAXAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxav${vp}.s32	$RdaSrc, $Qm */
+  ARM_MVE_VMAXAVs32 /* 1206 */, ARM_INS_VMAXAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxav${vp}.s8	$RdaSrc, $Qm */
+  ARM_MVE_VMAXAVs8 /* 1207 */, ARM_INS_VMAXAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxa${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VMAXAs16 /* 1208 */, ARM_INS_VMAXA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxa${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VMAXAs32 /* 1209 */, ARM_INS_VMAXA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxa${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VMAXAs8 /* 1210 */, ARM_INS_VMAXA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnmav${vp}.f16	$RdaSrc, $Qm */
+  ARM_MVE_VMAXNMAVf16 /* 1211 */, ARM_INS_VMAXNMAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnmav${vp}.f32	$RdaSrc, $Qm */
+  ARM_MVE_VMAXNMAVf32 /* 1212 */, ARM_INS_VMAXNMAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnma${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VMAXNMAf16 /* 1213 */, ARM_INS_VMAXNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnma${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VMAXNMAf32 /* 1214 */, ARM_INS_VMAXNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnmv${vp}.f16	$RdaSrc, $Qm */
+  ARM_MVE_VMAXNMVf16 /* 1215 */, ARM_INS_VMAXNMV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnmv${vp}.f32	$RdaSrc, $Qm */
+  ARM_MVE_VMAXNMVf32 /* 1216 */, ARM_INS_VMAXNMV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXNMf16 /* 1217 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXNMf32 /* 1218 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxv${vp}.s16	$RdaSrc, $Qm */
+  ARM_MVE_VMAXVs16 /* 1219 */, ARM_INS_VMAXV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxv${vp}.s32	$RdaSrc, $Qm */
+  ARM_MVE_VMAXVs32 /* 1220 */, ARM_INS_VMAXV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxv${vp}.s8	$RdaSrc, $Qm */
+  ARM_MVE_VMAXVs8 /* 1221 */, ARM_INS_VMAXV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxv${vp}.u16	$RdaSrc, $Qm */
+  ARM_MVE_VMAXVu16 /* 1222 */, ARM_INS_VMAXV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxv${vp}.u32	$RdaSrc, $Qm */
+  ARM_MVE_VMAXVu32 /* 1223 */, ARM_INS_VMAXV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxv${vp}.u8	$RdaSrc, $Qm */
+  ARM_MVE_VMAXVu8 /* 1224 */, ARM_INS_VMAXV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXs16 /* 1225 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXs32 /* 1226 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXs8 /* 1227 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXu16 /* 1228 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXu32 /* 1229 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMAXu8 /* 1230 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminav${vp}.s16	$RdaSrc, $Qm */
+  ARM_MVE_VMINAVs16 /* 1231 */, ARM_INS_VMINAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminav${vp}.s32	$RdaSrc, $Qm */
+  ARM_MVE_VMINAVs32 /* 1232 */, ARM_INS_VMINAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminav${vp}.s8	$RdaSrc, $Qm */
+  ARM_MVE_VMINAVs8 /* 1233 */, ARM_INS_VMINAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmina${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VMINAs16 /* 1234 */, ARM_INS_VMINA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmina${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VMINAs32 /* 1235 */, ARM_INS_VMINA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmina${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VMINAs8 /* 1236 */, ARM_INS_VMINA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnmav${vp}.f16	$RdaSrc, $Qm */
+  ARM_MVE_VMINNMAVf16 /* 1237 */, ARM_INS_VMINNMAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnmav${vp}.f32	$RdaSrc, $Qm */
+  ARM_MVE_VMINNMAVf32 /* 1238 */, ARM_INS_VMINNMAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnma${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VMINNMAf16 /* 1239 */, ARM_INS_VMINNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnma${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VMINNMAf32 /* 1240 */, ARM_INS_VMINNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnmv${vp}.f16	$RdaSrc, $Qm */
+  ARM_MVE_VMINNMVf16 /* 1241 */, ARM_INS_VMINNMV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnmv${vp}.f32	$RdaSrc, $Qm */
+  ARM_MVE_VMINNMVf32 /* 1242 */, ARM_INS_VMINNMV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINNMf16 /* 1243 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINNMf32 /* 1244 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminv${vp}.s16	$RdaSrc, $Qm */
+  ARM_MVE_VMINVs16 /* 1245 */, ARM_INS_VMINV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminv${vp}.s32	$RdaSrc, $Qm */
+  ARM_MVE_VMINVs32 /* 1246 */, ARM_INS_VMINV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminv${vp}.s8	$RdaSrc, $Qm */
+  ARM_MVE_VMINVs8 /* 1247 */, ARM_INS_VMINV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminv${vp}.u16	$RdaSrc, $Qm */
+  ARM_MVE_VMINVu16 /* 1248 */, ARM_INS_VMINV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminv${vp}.u32	$RdaSrc, $Qm */
+  ARM_MVE_VMINVu32 /* 1249 */, ARM_INS_VMINV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminv${vp}.u8	$RdaSrc, $Qm */
+  ARM_MVE_VMINVu8 /* 1250 */, ARM_INS_VMINV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINs16 /* 1251 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINs32 /* 1252 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINs8 /* 1253 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINu16 /* 1254 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINu32 /* 1255 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMINu8 /* 1256 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladava${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVas16 /* 1257 */, ARM_INS_VMLADAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladava${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVas32 /* 1258 */, ARM_INS_VMLADAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladava${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVas8 /* 1259 */, ARM_INS_VMLADAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladava${vp}.u16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVau16 /* 1260 */, ARM_INS_VMLADAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladava${vp}.u32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVau32 /* 1261 */, ARM_INS_VMLADAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladava${vp}.u8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVau8 /* 1262 */, ARM_INS_VMLADAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladavax${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVaxs16 /* 1263 */, ARM_INS_VMLADAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladavax${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVaxs32 /* 1264 */, ARM_INS_VMLADAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladavax${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVaxs8 /* 1265 */, ARM_INS_VMLADAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladav${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVs16 /* 1266 */, ARM_INS_VMLADAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladav${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVs32 /* 1267 */, ARM_INS_VMLADAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladav${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVs8 /* 1268 */, ARM_INS_VMLADAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladav${vp}.u16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVu16 /* 1269 */, ARM_INS_VMLADAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladav${vp}.u32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVu32 /* 1270 */, ARM_INS_VMLADAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladav${vp}.u8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVu8 /* 1271 */, ARM_INS_VMLADAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladavx${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVxs16 /* 1272 */, ARM_INS_VMLADAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladavx${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVxs32 /* 1273 */, ARM_INS_VMLADAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmladavx${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLADAVxs8 /* 1274 */, ARM_INS_VMLADAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldava${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVas16 /* 1275 */, ARM_INS_VMLALDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldava${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVas32 /* 1276 */, ARM_INS_VMLALDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldava${vp}.u16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVau16 /* 1277 */, ARM_INS_VMLALDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldava${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVau32 /* 1278 */, ARM_INS_VMLALDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldavax${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVaxs16 /* 1279 */, ARM_INS_VMLALDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldavax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVaxs32 /* 1280 */, ARM_INS_VMLALDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldav${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVs16 /* 1281 */, ARM_INS_VMLALDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldav${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVs32 /* 1282 */, ARM_INS_VMLALDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldav${vp}.u16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVu16 /* 1283 */, ARM_INS_VMLALDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldav${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVu32 /* 1284 */, ARM_INS_VMLALDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldavx${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVxs16 /* 1285 */, ARM_INS_VMLALDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlaldavx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLALDAVxs32 /* 1286 */, ARM_INS_VMLALDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlas${vp}.i16	$Qd, $Qn, $Rm */
+  ARM_MVE_VMLAS_qr_i16 /* 1287 */, ARM_INS_VMLAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlas${vp}.i32	$Qd, $Qn, $Rm */
+  ARM_MVE_VMLAS_qr_i32 /* 1288 */, ARM_INS_VMLAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlas${vp}.i8	$Qd, $Qn, $Rm */
+  ARM_MVE_VMLAS_qr_i8 /* 1289 */, ARM_INS_VMLAS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${vp}.i16	$Qd, $Qn, $Rm */
+  ARM_MVE_VMLA_qr_i16 /* 1290 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${vp}.i32	$Qd, $Qn, $Rm */
+  ARM_MVE_VMLA_qr_i32 /* 1291 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${vp}.i8	$Qd, $Qn, $Rm */
+  ARM_MVE_VMLA_qr_i8 /* 1292 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdava${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVas16 /* 1293 */, ARM_INS_VMLSDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdava${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVas32 /* 1294 */, ARM_INS_VMLSDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdava${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVas8 /* 1295 */, ARM_INS_VMLSDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdavax${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVaxs16 /* 1296 */, ARM_INS_VMLSDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdavax${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVaxs32 /* 1297 */, ARM_INS_VMLSDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdavax${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVaxs8 /* 1298 */, ARM_INS_VMLSDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdav${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVs16 /* 1299 */, ARM_INS_VMLSDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdav${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVs32 /* 1300 */, ARM_INS_VMLSDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdav${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVs8 /* 1301 */, ARM_INS_VMLSDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdavx${vp}.s16	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVxs16 /* 1302 */, ARM_INS_VMLSDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdavx${vp}.s32	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVxs32 /* 1303 */, ARM_INS_VMLSDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsdavx${vp}.s8	$RdaDest, $Qn, $Qm */
+  ARM_MVE_VMLSDAVxs8 /* 1304 */, ARM_INS_VMLSDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldava${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVas16 /* 1305 */, ARM_INS_VMLSLDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldava${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVas32 /* 1306 */, ARM_INS_VMLSLDAVA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldavax${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVaxs16 /* 1307 */, ARM_INS_VMLSLDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldavax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVaxs32 /* 1308 */, ARM_INS_VMLSLDAVAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldav${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVs16 /* 1309 */, ARM_INS_VMLSLDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldav${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVs32 /* 1310 */, ARM_INS_VMLSLDAV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldavx${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVxs16 /* 1311 */, ARM_INS_VMLSLDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsldavx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VMLSLDAVxs32 /* 1312 */, ARM_INS_VMLSLDAVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlb${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VMOVLs16bh /* 1313 */, ARM_INS_VMOVLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlt${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VMOVLs16th /* 1314 */, ARM_INS_VMOVLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlb${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VMOVLs8bh /* 1315 */, ARM_INS_VMOVLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlt${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VMOVLs8th /* 1316 */, ARM_INS_VMOVLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlb${vp}.u16	$Qd, $Qm */
+  ARM_MVE_VMOVLu16bh /* 1317 */, ARM_INS_VMOVLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlt${vp}.u16	$Qd, $Qm */
+  ARM_MVE_VMOVLu16th /* 1318 */, ARM_INS_VMOVLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlb${vp}.u8	$Qd, $Qm */
+  ARM_MVE_VMOVLu8bh /* 1319 */, ARM_INS_VMOVLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovlt${vp}.u8	$Qd, $Qm */
+  ARM_MVE_VMOVLu8th /* 1320 */, ARM_INS_VMOVLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovnb${vp}.i16	$Qd, $Qm */
+  ARM_MVE_VMOVNi16bh /* 1321 */, ARM_INS_VMOVNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovnt${vp}.i16	$Qd, $Qm */
+  ARM_MVE_VMOVNi16th /* 1322 */, ARM_INS_VMOVNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovnb${vp}.i32	$Qd, $Qm */
+  ARM_MVE_VMOVNi32bh /* 1323 */, ARM_INS_VMOVNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovnt${vp}.i32	$Qd, $Qm */
+  ARM_MVE_VMOVNi32th /* 1324 */, ARM_INS_VMOVNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.32	$Rt, $Qd$Idx */
+  ARM_MVE_VMOV_from_lane_32 /* 1325 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegsV8_1M, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.s16	$Rt, $Qd$Idx */
+  ARM_MVE_VMOV_from_lane_s16 /* 1326 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.s8	$Rt, $Qd$Idx */
+  ARM_MVE_VMOV_from_lane_s8 /* 1327 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.u16	$Rt, $Qd$Idx */
+  ARM_MVE_VMOV_from_lane_u16 /* 1328 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.u8	$Rt, $Qd$Idx */
+  ARM_MVE_VMOV_from_lane_u8 /* 1329 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Qd$idx, $QdSrc$idx2, $Rt, $Rt2 */
+  ARM_MVE_VMOV_q_rr /* 1330 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Rt, $Rt2, $Qd$idx, $Qd$idx2 */
+  ARM_MVE_VMOV_rr_q /* 1331 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.16	$Qd$Idx, $Rt */
+  ARM_MVE_VMOV_to_lane_16 /* 1332 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.32	$Qd$Idx, $Rt */
+  ARM_MVE_VMOV_to_lane_32 /* 1333 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegsV8_1M, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.8	$Qd$Idx, $Rt */
+  ARM_MVE_VMOV_to_lane_8 /* 1334 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${vp}.f32	$Qd, $imm */
+  ARM_MVE_VMOVimmf32 /* 1335 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${vp}.i16	$Qd, $imm */
+  ARM_MVE_VMOVimmi16 /* 1336 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${vp}.i32	$Qd, $imm */
+  ARM_MVE_VMOVimmi32 /* 1337 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${vp}.i64	$Qd, $imm */
+  ARM_MVE_VMOVimmi64 /* 1338 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${vp}.i8	$Qd, $imm */
+  ARM_MVE_VMOVimmi8 /* 1339 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmulh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULHs16 /* 1340 */, ARM_INS_VMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmulh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULHs32 /* 1341 */, ARM_INS_VMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmulh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULHs8 /* 1342 */, ARM_INS_VMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmulh${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULHu16 /* 1343 */, ARM_INS_VMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmulh${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULHu32 /* 1344 */, ARM_INS_VMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmulh${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULHu8 /* 1345 */, ARM_INS_VMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.p16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBp16 /* 1346 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.p8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBp8 /* 1347 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBs16 /* 1348 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBs32 /* 1349 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBs8 /* 1350 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBu16 /* 1351 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBu32 /* 1352 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullb${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLBu8 /* 1353 */, ARM_INS_VMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.p16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTp16 /* 1354 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.p8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTp8 /* 1355 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTs16 /* 1356 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTs32 /* 1357 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTs8 /* 1358 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTu16 /* 1359 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTu32 /* 1360 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmullt${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULLTu8 /* 1361 */, ARM_INS_VMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.f16	$Qd, $Qn, $Rm */
+  ARM_MVE_VMUL_qr_f16 /* 1362 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.f32	$Qd, $Qn, $Rm */
+  ARM_MVE_VMUL_qr_f32 /* 1363 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.i16	$Qd, $Qn, $Rm */
+  ARM_MVE_VMUL_qr_i16 /* 1364 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.i32	$Qd, $Qn, $Rm */
+  ARM_MVE_VMUL_qr_i32 /* 1365 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.i8	$Qd, $Qn, $Rm */
+  ARM_MVE_VMUL_qr_i8 /* 1366 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULf16 /* 1367 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULf32 /* 1368 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.i16	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULi16 /* 1369 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULi32 /* 1370 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${vp}.i8	$Qd, $Qn, $Qm */
+  ARM_MVE_VMULi8 /* 1371 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${vp}	$Qd, $Qm */
+  ARM_MVE_VMVN /* 1372 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${vp}.i16	$Qd, $imm */
+  ARM_MVE_VMVNimmi16 /* 1373 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${vp}.i32	$Qd, $imm */
+  ARM_MVE_VMVNimmi32 /* 1374 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VNEGf16 /* 1375 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VNEGf32 /* 1376 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VNEGs16 /* 1377 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VNEGs32 /* 1378 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VNEGs8 /* 1379 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorn${vp}	$Qd, $Qn, $Qm */
+  ARM_MVE_VORN /* 1380 */, ARM_INS_VORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${vp}	$Qd, $Qn, $Qm */
+  ARM_MVE_VORR /* 1381 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${vp}.i16	$Qd, $imm */
+  ARM_MVE_VORRimmi16 /* 1382 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${vp}.i32	$Qd, $imm */
+  ARM_MVE_VORRimmi32 /* 1383 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpnot${vp}	 */
+  ARM_MVE_VPNOT /* 1384 */, ARM_INS_VPNOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpsel${vp}	$Qd, $Qn, $Qm */
+  ARM_MVE_VPSEL /* 1385 */, ARM_INS_VPSEL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpst${Mk}	 */
+  ARM_MVE_VPST /* 1386 */, ARM_INS_VPST,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.i8	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv16i8 /* 1387 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.i8	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv16i8r /* 1388 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.s8	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv16s8 /* 1389 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.s8	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv16s8r /* 1390 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.u8	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv16u8 /* 1391 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.u8	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv16u8r /* 1392 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.f32	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv4f32 /* 1393 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.f32	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv4f32r /* 1394 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.i32	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv4i32 /* 1395 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.i32	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv4i32r /* 1396 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.s32	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv4s32 /* 1397 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.s32	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv4s32r /* 1398 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.u32	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv4u32 /* 1399 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.u32	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv4u32r /* 1400 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.f16	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv8f16 /* 1401 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.f16	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv8f16r /* 1402 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.i16	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv8i16 /* 1403 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.i16	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv8i16r /* 1404 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.s16	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv8s16 /* 1405 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.s16	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv8s16r /* 1406 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.u16	$fc, $Qn, $Qm */
+  ARM_MVE_VPTv8u16 /* 1407 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpt${Mk}.u16	$fc, $Qn, $Rm */
+  ARM_MVE_VPTv8u16r /* 1408 */, ARM_INS_VPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VQABSs16 /* 1409 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VQABSs32 /* 1410 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VQABSs8 /* 1411 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQADD_qr_s16 /* 1412 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQADD_qr_s32 /* 1413 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQADD_qr_s8 /* 1414 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.u16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQADD_qr_u16 /* 1415 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.u32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQADD_qr_u32 /* 1416 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.u8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQADD_qr_u8 /* 1417 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQADDs16 /* 1418 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQADDs32 /* 1419 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQADDs8 /* 1420 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQADDu16 /* 1421 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQADDu32 /* 1422 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQADDu8 /* 1423 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmladhx${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLADHXs16 /* 1424 */, ARM_INS_VQDMLADHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmladhx${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLADHXs32 /* 1425 */, ARM_INS_VQDMLADHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmladhx${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLADHXs8 /* 1426 */, ARM_INS_VQDMLADHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmladh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLADHs16 /* 1427 */, ARM_INS_VQDMLADH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmladh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLADHs32 /* 1428 */, ARM_INS_VQDMLADH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmladh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLADHs8 /* 1429 */, ARM_INS_VQDMLADH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlah${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMLAH_qrs16 /* 1430 */, ARM_INS_VQDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlah${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMLAH_qrs32 /* 1431 */, ARM_INS_VQDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlah${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMLAH_qrs8 /* 1432 */, ARM_INS_VQDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlash${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMLASH_qrs16 /* 1433 */, ARM_INS_VQDMLASH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlash${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMLASH_qrs32 /* 1434 */, ARM_INS_VQDMLASH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlash${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMLASH_qrs8 /* 1435 */, ARM_INS_VQDMLASH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsdhx${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLSDHXs16 /* 1436 */, ARM_INS_VQDMLSDHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsdhx${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLSDHXs32 /* 1437 */, ARM_INS_VQDMLSDHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsdhx${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLSDHXs8 /* 1438 */, ARM_INS_VQDMLSDHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsdh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLSDHs16 /* 1439 */, ARM_INS_VQDMLSDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsdh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLSDHs32 /* 1440 */, ARM_INS_VQDMLSDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsdh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMLSDHs8 /* 1441 */, ARM_INS_VQDMLSDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULH_qr_s16 /* 1442 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULH_qr_s32 /* 1443 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULH_qr_s8 /* 1444 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULHi16 /* 1445 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULHi32 /* 1446 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULHi8 /* 1447 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullb${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULL_qr_s16bh /* 1448 */, ARM_INS_VQDMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullt${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULL_qr_s16th /* 1449 */, ARM_INS_VQDMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullb${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULL_qr_s32bh /* 1450 */, ARM_INS_VQDMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullt${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQDMULL_qr_s32th /* 1451 */, ARM_INS_VQDMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullb${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULLs16bh /* 1452 */, ARM_INS_VQDMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullt${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULLs16th /* 1453 */, ARM_INS_VQDMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullb${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULLs32bh /* 1454 */, ARM_INS_VQDMULLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmullt${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQDMULLs32th /* 1455 */, ARM_INS_VQDMULLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnb${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VQMOVNs16bh /* 1456 */, ARM_INS_VQMOVNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnt${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VQMOVNs16th /* 1457 */, ARM_INS_VQMOVNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnb${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VQMOVNs32bh /* 1458 */, ARM_INS_VQMOVNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnt${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VQMOVNs32th /* 1459 */, ARM_INS_VQMOVNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnb${vp}.u16	$Qd, $Qm */
+  ARM_MVE_VQMOVNu16bh /* 1460 */, ARM_INS_VQMOVNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnt${vp}.u16	$Qd, $Qm */
+  ARM_MVE_VQMOVNu16th /* 1461 */, ARM_INS_VQMOVNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnb${vp}.u32	$Qd, $Qm */
+  ARM_MVE_VQMOVNu32bh /* 1462 */, ARM_INS_VQMOVNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovnt${vp}.u32	$Qd, $Qm */
+  ARM_MVE_VQMOVNu32th /* 1463 */, ARM_INS_VQMOVNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovunb${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VQMOVUNs16bh /* 1464 */, ARM_INS_VQMOVUNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovunt${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VQMOVUNs16th /* 1465 */, ARM_INS_VQMOVUNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovunb${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VQMOVUNs32bh /* 1466 */, ARM_INS_VQMOVUNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovunt${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VQMOVUNs32th /* 1467 */, ARM_INS_VQMOVUNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${vp}.s16	$Qd, $Qm */
+  ARM_MVE_VQNEGs16 /* 1468 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${vp}.s32	$Qd, $Qm */
+  ARM_MVE_VQNEGs32 /* 1469 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${vp}.s8	$Qd, $Qm */
+  ARM_MVE_VQNEGs8 /* 1470 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmladhx${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLADHXs16 /* 1471 */, ARM_INS_VQRDMLADHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmladhx${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLADHXs32 /* 1472 */, ARM_INS_VQRDMLADHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmladhx${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLADHXs8 /* 1473 */, ARM_INS_VQRDMLADHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmladh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLADHs16 /* 1474 */, ARM_INS_VQRDMLADH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmladh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLADHs32 /* 1475 */, ARM_INS_VQRDMLADH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmladh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLADHs8 /* 1476 */, ARM_INS_VQRDMLADH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMLAH_qrs16 /* 1477 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMLAH_qrs32 /* 1478 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMLAH_qrs8 /* 1479 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlash${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMLASH_qrs16 /* 1480 */, ARM_INS_VQRDMLASH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlash${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMLASH_qrs32 /* 1481 */, ARM_INS_VQRDMLASH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlash${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMLASH_qrs8 /* 1482 */, ARM_INS_VQRDMLASH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsdhx${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLSDHXs16 /* 1483 */, ARM_INS_VQRDMLSDHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsdhx${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLSDHXs32 /* 1484 */, ARM_INS_VQRDMLSDHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsdhx${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLSDHXs8 /* 1485 */, ARM_INS_VQRDMLSDHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsdh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLSDHs16 /* 1486 */, ARM_INS_VQRDMLSDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsdh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLSDHs32 /* 1487 */, ARM_INS_VQRDMLSDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsdh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMLSDHs8 /* 1488 */, ARM_INS_VQRDMLSDH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMULH_qr_s16 /* 1489 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMULH_qr_s32 /* 1490 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQRDMULH_qr_s8 /* 1491 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMULHi16 /* 1492 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMULHi32 /* 1493 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQRDMULHi8 /* 1494 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.s16	$Qd, $Qm, $Qn */
+  ARM_MVE_VQRSHL_by_vecs16 /* 1495 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.s32	$Qd, $Qm, $Qn */
+  ARM_MVE_VQRSHL_by_vecs32 /* 1496 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.s8	$Qd, $Qm, $Qn */
+  ARM_MVE_VQRSHL_by_vecs8 /* 1497 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.u16	$Qd, $Qm, $Qn */
+  ARM_MVE_VQRSHL_by_vecu16 /* 1498 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.u32	$Qd, $Qm, $Qn */
+  ARM_MVE_VQRSHL_by_vecu32 /* 1499 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.u8	$Qd, $Qm, $Qn */
+  ARM_MVE_VQRSHL_by_vecu8 /* 1500 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.s16	$Qd, $Rm */
+  ARM_MVE_VQRSHL_qrs16 /* 1501 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.s32	$Qd, $Rm */
+  ARM_MVE_VQRSHL_qrs32 /* 1502 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.s8	$Qd, $Rm */
+  ARM_MVE_VQRSHL_qrs8 /* 1503 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.u16	$Qd, $Rm */
+  ARM_MVE_VQRSHL_qru16 /* 1504 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.u32	$Qd, $Rm */
+  ARM_MVE_VQRSHL_qru32 /* 1505 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${vp}.u8	$Qd, $Rm */
+  ARM_MVE_VQRSHL_qru8 /* 1506 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnb${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNbhs16 /* 1507 */, ARM_INS_VQRSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnb${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNbhs32 /* 1508 */, ARM_INS_VQRSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnb${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNbhu16 /* 1509 */, ARM_INS_VQRSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnb${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNbhu32 /* 1510 */, ARM_INS_VQRSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnt${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNths16 /* 1511 */, ARM_INS_VQRSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnt${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNths32 /* 1512 */, ARM_INS_VQRSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnt${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNthu16 /* 1513 */, ARM_INS_VQRSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrnt${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRNthu32 /* 1514 */, ARM_INS_VQRSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrunb${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRUNs16bh /* 1515 */, ARM_INS_VQRSHRUNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrunt${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRUNs16th /* 1516 */, ARM_INS_VQRSHRUNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrunb${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRUNs32bh /* 1517 */, ARM_INS_VQRSHRUNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrunt${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQRSHRUNs32th /* 1518 */, ARM_INS_VQRSHRUNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLU_imms16 /* 1519 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLU_imms32 /* 1520 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${vp}.s8	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLU_imms8 /* 1521 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s16	$Qd, $Qm, $Qn */
+  ARM_MVE_VQSHL_by_vecs16 /* 1522 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s32	$Qd, $Qm, $Qn */
+  ARM_MVE_VQSHL_by_vecs32 /* 1523 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s8	$Qd, $Qm, $Qn */
+  ARM_MVE_VQSHL_by_vecs8 /* 1524 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u16	$Qd, $Qm, $Qn */
+  ARM_MVE_VQSHL_by_vecu16 /* 1525 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u32	$Qd, $Qm, $Qn */
+  ARM_MVE_VQSHL_by_vecu32 /* 1526 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u8	$Qd, $Qm, $Qn */
+  ARM_MVE_VQSHL_by_vecu8 /* 1527 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s16	$Qd, $Rm */
+  ARM_MVE_VQSHL_qrs16 /* 1528 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s32	$Qd, $Rm */
+  ARM_MVE_VQSHL_qrs32 /* 1529 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s8	$Qd, $Rm */
+  ARM_MVE_VQSHL_qrs8 /* 1530 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u16	$Qd, $Rm */
+  ARM_MVE_VQSHL_qru16 /* 1531 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u32	$Qd, $Rm */
+  ARM_MVE_VQSHL_qru32 /* 1532 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u8	$Qd, $Rm */
+  ARM_MVE_VQSHL_qru8 /* 1533 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLimms16 /* 1534 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLimms32 /* 1535 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.s8	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLimms8 /* 1536 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLimmu16 /* 1537 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLimmu32 /* 1538 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${vp}.u8	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHLimmu8 /* 1539 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnb${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNbhs16 /* 1540 */, ARM_INS_VQSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnb${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNbhs32 /* 1541 */, ARM_INS_VQSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnb${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNbhu16 /* 1542 */, ARM_INS_VQSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnb${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNbhu32 /* 1543 */, ARM_INS_VQSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnt${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNths16 /* 1544 */, ARM_INS_VQSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnt${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNths32 /* 1545 */, ARM_INS_VQSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnt${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNthu16 /* 1546 */, ARM_INS_VQSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrnt${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRNthu32 /* 1547 */, ARM_INS_VQSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrunb${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRUNs16bh /* 1548 */, ARM_INS_VQSHRUNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrunt${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRUNs16th /* 1549 */, ARM_INS_VQSHRUNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrunb${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRUNs32bh /* 1550 */, ARM_INS_VQSHRUNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrunt${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VQSHRUNs32th /* 1551 */, ARM_INS_VQSHRUNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.s16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQSUB_qr_s16 /* 1552 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.s32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQSUB_qr_s32 /* 1553 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.s8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQSUB_qr_s8 /* 1554 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.u16	$Qd, $Qn, $Rm */
+  ARM_MVE_VQSUB_qr_u16 /* 1555 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.u32	$Qd, $Qn, $Rm */
+  ARM_MVE_VQSUB_qr_u32 /* 1556 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.u8	$Qd, $Qn, $Rm */
+  ARM_MVE_VQSUB_qr_u8 /* 1557 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQSUBs16 /* 1558 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQSUBs32 /* 1559 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQSUBs8 /* 1560 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VQSUBu16 /* 1561 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VQSUBu32 /* 1562 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VQSUBu8 /* 1563 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev16${vp}.8	$Qd, $Qm */
+  ARM_MVE_VREV16_8 /* 1564 */, ARM_INS_VREV16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev32${vp}.16	$Qd, $Qm */
+  ARM_MVE_VREV32_16 /* 1565 */, ARM_INS_VREV32,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev32${vp}.8	$Qd, $Qm */
+  ARM_MVE_VREV32_8 /* 1566 */, ARM_INS_VREV32,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${vp}.16	$Qd, $Qm */
+  ARM_MVE_VREV64_16 /* 1567 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${vp}.32	$Qd, $Qm */
+  ARM_MVE_VREV64_32 /* 1568 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${vp}.8	$Qd, $Qm */
+  ARM_MVE_VREV64_8 /* 1569 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VRHADDs16 /* 1570 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VRHADDs32 /* 1571 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VRHADDs8 /* 1572 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VRHADDu16 /* 1573 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VRHADDu32 /* 1574 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VRHADDu8 /* 1575 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VRINTf16A /* 1576 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VRINTf16M /* 1577 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VRINTf16N /* 1578 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VRINTf16P /* 1579 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VRINTf16X /* 1580 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz${vp}.f16	$Qd, $Qm */
+  ARM_MVE_VRINTf16Z /* 1581 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VRINTf32A /* 1582 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VRINTf32M /* 1583 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VRINTf32N /* 1584 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VRINTf32P /* 1585 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VRINTf32X /* 1586 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz${vp}.f32	$Qd, $Qm */
+  ARM_MVE_VRINTf32Z /* 1587 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlaldavha${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLALDAVHas32 /* 1588 */, ARM_INS_VRMLALDAVHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlaldavha${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLALDAVHau32 /* 1589 */, ARM_INS_VRMLALDAVHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlaldavhax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLALDAVHaxs32 /* 1590 */, ARM_INS_VRMLALDAVHAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlaldavh${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLALDAVHs32 /* 1591 */, ARM_INS_VRMLALDAVH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlaldavh${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLALDAVHu32 /* 1592 */, ARM_INS_VRMLALDAVH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlaldavhx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLALDAVHxs32 /* 1593 */, ARM_INS_VRMLALDAVHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlsldavha${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLSLDAVHas32 /* 1594 */, ARM_INS_VRMLSLDAVHA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlsldavhax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLSLDAVHaxs32 /* 1595 */, ARM_INS_VRMLSLDAVHAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlsldavh${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLSLDAVHs32 /* 1596 */, ARM_INS_VRMLSLDAVH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmlsldavhx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+  ARM_MVE_VRMLSLDAVHxs32 /* 1597 */, ARM_INS_VRMLSLDAVHX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmulh${vp}.s16	$Qd, $Qn, $Qm */
+  ARM_MVE_VRMULHs16 /* 1598 */, ARM_INS_VRMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmulh${vp}.s32	$Qd, $Qn, $Qm */
+  ARM_MVE_VRMULHs32 /* 1599 */, ARM_INS_VRMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmulh${vp}.s8	$Qd, $Qn, $Qm */
+  ARM_MVE_VRMULHs8 /* 1600 */, ARM_INS_VRMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmulh${vp}.u16	$Qd, $Qn, $Qm */
+  ARM_MVE_VRMULHu16 /* 1601 */, ARM_INS_VRMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmulh${vp}.u32	$Qd, $Qn, $Qm */
+  ARM_MVE_VRMULHu32 /* 1602 */, ARM_INS_VRMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrmulh${vp}.u8	$Qd, $Qn, $Qm */
+  ARM_MVE_VRMULHu8 /* 1603 */, ARM_INS_VRMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.s16	$Qd, $Qm, $Qn */
+  ARM_MVE_VRSHL_by_vecs16 /* 1604 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.s32	$Qd, $Qm, $Qn */
+  ARM_MVE_VRSHL_by_vecs32 /* 1605 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.s8	$Qd, $Qm, $Qn */
+  ARM_MVE_VRSHL_by_vecs8 /* 1606 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.u16	$Qd, $Qm, $Qn */
+  ARM_MVE_VRSHL_by_vecu16 /* 1607 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.u32	$Qd, $Qm, $Qn */
+  ARM_MVE_VRSHL_by_vecu32 /* 1608 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.u8	$Qd, $Qm, $Qn */
+  ARM_MVE_VRSHL_by_vecu8 /* 1609 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.s16	$Qd, $Rm */
+  ARM_MVE_VRSHL_qrs16 /* 1610 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.s32	$Qd, $Rm */
+  ARM_MVE_VRSHL_qrs32 /* 1611 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.s8	$Qd, $Rm */
+  ARM_MVE_VRSHL_qrs8 /* 1612 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.u16	$Qd, $Rm */
+  ARM_MVE_VRSHL_qru16 /* 1613 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.u32	$Qd, $Rm */
+  ARM_MVE_VRSHL_qru32 /* 1614 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${vp}.u8	$Qd, $Rm */
+  ARM_MVE_VRSHL_qru8 /* 1615 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrnb${vp}.i16	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHRNi16bh /* 1616 */, ARM_INS_VRSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrnt${vp}.i16	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHRNi16th /* 1617 */, ARM_INS_VRSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrnb${vp}.i32	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHRNi32bh /* 1618 */, ARM_INS_VRSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrnt${vp}.i32	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHRNi32th /* 1619 */, ARM_INS_VRSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHR_imms16 /* 1620 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHR_imms32 /* 1621 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${vp}.s8	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHR_imms8 /* 1622 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHR_immu16 /* 1623 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHR_immu32 /* 1624 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${vp}.u8	$Qd, $Qm, $imm */
+  ARM_MVE_VRSHR_immu8 /* 1625 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsbc${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VSBC /* 1626 */, ARM_INS_VSBC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsbci${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VSBCI /* 1627 */, ARM_INS_VSBCI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshlc${vp}	$QdSrc, $RdmSrc, $imm */
+  ARM_MVE_VSHLC /* 1628 */, ARM_INS_VSHLC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_imms16bh /* 1629 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_imms16th /* 1630 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.s8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_imms8bh /* 1631 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.s8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_imms8th /* 1632 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_immu16bh /* 1633 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_immu16th /* 1634 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.u8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_immu8bh /* 1635 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.u8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHLL_immu8th /* 1636 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.s16	$Qd, $Qm, #16 */
+  ARM_MVE_VSHLL_lws16bh /* 1637 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.s16	$Qd, $Qm, #16 */
+  ARM_MVE_VSHLL_lws16th /* 1638 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.s8	$Qd, $Qm, #8 */
+  ARM_MVE_VSHLL_lws8bh /* 1639 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.s8	$Qd, $Qm, #8 */
+  ARM_MVE_VSHLL_lws8th /* 1640 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.u16	$Qd, $Qm, #16 */
+  ARM_MVE_VSHLL_lwu16bh /* 1641 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.u16	$Qd, $Qm, #16 */
+  ARM_MVE_VSHLL_lwu16th /* 1642 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllb${vp}.u8	$Qd, $Qm, #8 */
+  ARM_MVE_VSHLL_lwu8bh /* 1643 */, ARM_INS_VSHLLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshllt${vp}.u8	$Qd, $Qm, #8 */
+  ARM_MVE_VSHLL_lwu8th /* 1644 */, ARM_INS_VSHLLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.s16	$Qd, $Qm, $Qn */
+  ARM_MVE_VSHL_by_vecs16 /* 1645 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.s32	$Qd, $Qm, $Qn */
+  ARM_MVE_VSHL_by_vecs32 /* 1646 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.s8	$Qd, $Qm, $Qn */
+  ARM_MVE_VSHL_by_vecs8 /* 1647 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.u16	$Qd, $Qm, $Qn */
+  ARM_MVE_VSHL_by_vecu16 /* 1648 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.u32	$Qd, $Qm, $Qn */
+  ARM_MVE_VSHL_by_vecu32 /* 1649 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.u8	$Qd, $Qm, $Qn */
+  ARM_MVE_VSHL_by_vecu8 /* 1650 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.i16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHL_immi16 /* 1651 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.i32	$Qd, $Qm, $imm */
+  ARM_MVE_VSHL_immi32 /* 1652 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.i8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHL_immi8 /* 1653 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.s16	$Qd, $Rm */
+  ARM_MVE_VSHL_qrs16 /* 1654 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.s32	$Qd, $Rm */
+  ARM_MVE_VSHL_qrs32 /* 1655 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.s8	$Qd, $Rm */
+  ARM_MVE_VSHL_qrs8 /* 1656 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.u16	$Qd, $Rm */
+  ARM_MVE_VSHL_qru16 /* 1657 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.u32	$Qd, $Rm */
+  ARM_MVE_VSHL_qru32 /* 1658 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${vp}.u8	$Qd, $Rm */
+  ARM_MVE_VSHL_qru8 /* 1659 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrnb${vp}.i16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHRNi16bh /* 1660 */, ARM_INS_VSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrnt${vp}.i16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHRNi16th /* 1661 */, ARM_INS_VSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrnb${vp}.i32	$Qd, $Qm, $imm */
+  ARM_MVE_VSHRNi32bh /* 1662 */, ARM_INS_VSHRNB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrnt${vp}.i32	$Qd, $Qm, $imm */
+  ARM_MVE_VSHRNi32th /* 1663 */, ARM_INS_VSHRNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${vp}.s16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHR_imms16 /* 1664 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${vp}.s32	$Qd, $Qm, $imm */
+  ARM_MVE_VSHR_imms32 /* 1665 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${vp}.s8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHR_imms8 /* 1666 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${vp}.u16	$Qd, $Qm, $imm */
+  ARM_MVE_VSHR_immu16 /* 1667 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${vp}.u32	$Qd, $Qm, $imm */
+  ARM_MVE_VSHR_immu32 /* 1668 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${vp}.u8	$Qd, $Qm, $imm */
+  ARM_MVE_VSHR_immu8 /* 1669 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${vp}.16	$Qd, $Qm, $imm */
+  ARM_MVE_VSLIimm16 /* 1670 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${vp}.32	$Qd, $Qm, $imm */
+  ARM_MVE_VSLIimm32 /* 1671 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${vp}.8	$Qd, $Qm, $imm */
+  ARM_MVE_VSLIimm8 /* 1672 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${vp}.16	$Qd, $Qm, $imm */
+  ARM_MVE_VSRIimm16 /* 1673 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${vp}.32	$Qd, $Qm, $imm */
+  ARM_MVE_VSRIimm32 /* 1674 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${vp}.8	$Qd, $Qm, $imm */
+  ARM_MVE_VSRIimm8 /* 1675 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst20.16	$VQd, $Rn */
+  ARM_MVE_VST20_16 /* 1676 */, ARM_INS_VST20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst20.16	$VQd, $Rn! */
+  ARM_MVE_VST20_16_wb /* 1677 */, ARM_INS_VST20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst20.32	$VQd, $Rn */
+  ARM_MVE_VST20_32 /* 1678 */, ARM_INS_VST20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst20.32	$VQd, $Rn! */
+  ARM_MVE_VST20_32_wb /* 1679 */, ARM_INS_VST20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst20.8	$VQd, $Rn */
+  ARM_MVE_VST20_8 /* 1680 */, ARM_INS_VST20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst20.8	$VQd, $Rn! */
+  ARM_MVE_VST20_8_wb /* 1681 */, ARM_INS_VST20,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst21.16	$VQd, $Rn */
+  ARM_MVE_VST21_16 /* 1682 */, ARM_INS_VST21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst21.16	$VQd, $Rn! */
+  ARM_MVE_VST21_16_wb /* 1683 */, ARM_INS_VST21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst21.32	$VQd, $Rn */
+  ARM_MVE_VST21_32 /* 1684 */, ARM_INS_VST21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst21.32	$VQd, $Rn! */
+  ARM_MVE_VST21_32_wb /* 1685 */, ARM_INS_VST21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst21.8	$VQd, $Rn */
+  ARM_MVE_VST21_8 /* 1686 */, ARM_INS_VST21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst21.8	$VQd, $Rn! */
+  ARM_MVE_VST21_8_wb /* 1687 */, ARM_INS_VST21,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst40.16	$VQd, $Rn */
+  ARM_MVE_VST40_16 /* 1688 */, ARM_INS_VST40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst40.16	$VQd, $Rn! */
+  ARM_MVE_VST40_16_wb /* 1689 */, ARM_INS_VST40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst40.32	$VQd, $Rn */
+  ARM_MVE_VST40_32 /* 1690 */, ARM_INS_VST40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst40.32	$VQd, $Rn! */
+  ARM_MVE_VST40_32_wb /* 1691 */, ARM_INS_VST40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst40.8	$VQd, $Rn */
+  ARM_MVE_VST40_8 /* 1692 */, ARM_INS_VST40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst40.8	$VQd, $Rn! */
+  ARM_MVE_VST40_8_wb /* 1693 */, ARM_INS_VST40,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst41.16	$VQd, $Rn */
+  ARM_MVE_VST41_16 /* 1694 */, ARM_INS_VST41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst41.16	$VQd, $Rn! */
+  ARM_MVE_VST41_16_wb /* 1695 */, ARM_INS_VST41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst41.32	$VQd, $Rn */
+  ARM_MVE_VST41_32 /* 1696 */, ARM_INS_VST41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst41.32	$VQd, $Rn! */
+  ARM_MVE_VST41_32_wb /* 1697 */, ARM_INS_VST41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst41.8	$VQd, $Rn */
+  ARM_MVE_VST41_8 /* 1698 */, ARM_INS_VST41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst41.8	$VQd, $Rn! */
+  ARM_MVE_VST41_8_wb /* 1699 */, ARM_INS_VST41,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst42.16	$VQd, $Rn */
+  ARM_MVE_VST42_16 /* 1700 */, ARM_INS_VST42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst42.16	$VQd, $Rn! */
+  ARM_MVE_VST42_16_wb /* 1701 */, ARM_INS_VST42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst42.32	$VQd, $Rn */
+  ARM_MVE_VST42_32 /* 1702 */, ARM_INS_VST42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst42.32	$VQd, $Rn! */
+  ARM_MVE_VST42_32_wb /* 1703 */, ARM_INS_VST42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst42.8	$VQd, $Rn */
+  ARM_MVE_VST42_8 /* 1704 */, ARM_INS_VST42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst42.8	$VQd, $Rn! */
+  ARM_MVE_VST42_8_wb /* 1705 */, ARM_INS_VST42,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst43.16	$VQd, $Rn */
+  ARM_MVE_VST43_16 /* 1706 */, ARM_INS_VST43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst43.16	$VQd, $Rn! */
+  ARM_MVE_VST43_16_wb /* 1707 */, ARM_INS_VST43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst43.32	$VQd, $Rn */
+  ARM_MVE_VST43_32 /* 1708 */, ARM_INS_VST43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst43.32	$VQd, $Rn! */
+  ARM_MVE_VST43_32_wb /* 1709 */, ARM_INS_VST43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst43.8	$VQd, $Rn */
+  ARM_MVE_VST43_8 /* 1710 */, ARM_INS_VST43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst43.8	$VQd, $Rn! */
+  ARM_MVE_VST43_8_wb /* 1711 */, ARM_INS_VST43,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.16	$Qd, $addr */
+  ARM_MVE_VSTRB16 /* 1712 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.16	$Qd, $Rn$addr */
+  ARM_MVE_VSTRB16_post /* 1713 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.16	$Qd, $addr! */
+  ARM_MVE_VSTRB16_pre /* 1714 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.16	$Qd, $addr */
+  ARM_MVE_VSTRB16_rq /* 1715 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRB32 /* 1716 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.32	$Qd, $Rn$addr */
+  ARM_MVE_VSTRB32_post /* 1717 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.32	$Qd, $addr! */
+  ARM_MVE_VSTRB32_pre /* 1718 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRB32_rq /* 1719 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.8	$Qd, $addr */
+  ARM_MVE_VSTRB8_rq /* 1720 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.8	$Qd, $addr */
+  ARM_MVE_VSTRBU8 /* 1721 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.8	$Qd, $Rn$addr */
+  ARM_MVE_VSTRBU8_post /* 1722 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrb${vp}.8	$Qd, $addr! */
+  ARM_MVE_VSTRBU8_pre /* 1723 */, ARM_INS_VSTRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrd${vp}.64	$Qd, $addr */
+  ARM_MVE_VSTRD64_qi /* 1724 */, ARM_INS_VSTRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrd${vp}.64	$Qd, $addr! */
+  ARM_MVE_VSTRD64_qi_pre /* 1725 */, ARM_INS_VSTRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrd${vp}.64	$Qd, $addr */
+  ARM_MVE_VSTRD64_rq /* 1726 */, ARM_INS_VSTRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrd${vp}.64	$Qd, $addr */
+  ARM_MVE_VSTRD64_rq_u /* 1727 */, ARM_INS_VSTRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.16	$Qd, $addr */
+  ARM_MVE_VSTRH16_rq /* 1728 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.16	$Qd, $addr */
+  ARM_MVE_VSTRH16_rq_u /* 1729 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRH32 /* 1730 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.32	$Qd, $Rn$addr */
+  ARM_MVE_VSTRH32_post /* 1731 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.32	$Qd, $addr! */
+  ARM_MVE_VSTRH32_pre /* 1732 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRH32_rq /* 1733 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRH32_rq_u /* 1734 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.16	$Qd, $addr */
+  ARM_MVE_VSTRHU16 /* 1735 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.16	$Qd, $Rn$addr */
+  ARM_MVE_VSTRHU16_post /* 1736 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrh${vp}.16	$Qd, $addr! */
+  ARM_MVE_VSTRHU16_pre /* 1737 */, ARM_INS_VSTRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRW32_qi /* 1738 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $addr! */
+  ARM_MVE_VSTRW32_qi_pre /* 1739 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRW32_rq /* 1740 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRW32_rq_u /* 1741 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $addr */
+  ARM_MVE_VSTRWU32 /* 1742 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $Rn$addr */
+  ARM_MVE_VSTRWU32_post /* 1743 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstrw${vp}.32	$Qd, $addr! */
+  ARM_MVE_VSTRWU32_pre /* 1744 */, ARM_INS_VSTRW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.f16	$Qd, $Qn, $Rm */
+  ARM_MVE_VSUB_qr_f16 /* 1745 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.f32	$Qd, $Qn, $Rm */
+  ARM_MVE_VSUB_qr_f32 /* 1746 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.i16	$Qd, $Qn, $Rm */
+  ARM_MVE_VSUB_qr_i16 /* 1747 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.i32	$Qd, $Qn, $Rm */
+  ARM_MVE_VSUB_qr_i32 /* 1748 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.i8	$Qd, $Qn, $Rm */
+  ARM_MVE_VSUB_qr_i8 /* 1749 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.f16	$Qd, $Qn, $Qm */
+  ARM_MVE_VSUBf16 /* 1750 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.f32	$Qd, $Qn, $Qm */
+  ARM_MVE_VSUBf32 /* 1751 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEFloat, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.i16	$Qd, $Qn, $Qm */
+  ARM_MVE_VSUBi16 /* 1752 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.i32	$Qd, $Qn, $Qm */
+  ARM_MVE_VSUBi32 /* 1753 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${vp}.i8	$Qd, $Qn, $Qm */
+  ARM_MVE_VSUBi8 /* 1754 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* wlstp.16	$LR, $Rn, $label */
+  ARM_MVE_WLSTP_16 /* 1755 */, ARM_INS_WLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0
+  #endif
+},
+{
+  /* wlstp.32	$LR, $Rn, $label */
+  ARM_MVE_WLSTP_32 /* 1756 */, ARM_INS_WLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0
+  #endif
+},
+{
+  /* wlstp.64	$LR, $Rn, $label */
+  ARM_MVE_WLSTP_64 /* 1757 */, ARM_INS_WLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0
+  #endif
+},
+{
+  /* wlstp.8	$LR, $Rn, $label */
+  ARM_MVE_WLSTP_8 /* 1758 */, ARM_INS_WLSTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_HasMVEInt, 0 }, 1, 0
+  #endif
+},
+{
+  /* mvn${s}${p}	$Rd, $imm */
+  ARM_MVNi /* 1759 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}	$Rd, $Rm */
+  ARM_MVNr /* 1760 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}	$Rd, $shift */
+  ARM_MVNsi /* 1761 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}	$Rd, $shift */
+  ARM_MVNsr /* 1762 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f32	$Vd, $Vn, $Vm */
+  ARM_NEON_VMAXNMNDf /* 1763 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f16	$Vd, $Vn, $Vm */
+  ARM_NEON_VMAXNMNDh /* 1764 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f32	$Vd, $Vn, $Vm */
+  ARM_NEON_VMAXNMNQf /* 1765 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f16	$Vd, $Vn, $Vm */
+  ARM_NEON_VMAXNMNQh /* 1766 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f32	$Vd, $Vn, $Vm */
+  ARM_NEON_VMINNMNDf /* 1767 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f16	$Vd, $Vn, $Vm */
+  ARM_NEON_VMINNMNDh /* 1768 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f32	$Vd, $Vn, $Vm */
+  ARM_NEON_VMINNMNQf /* 1769 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f16	$Vd, $Vn, $Vm */
+  ARM_NEON_VMINNMNQh /* 1770 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}	$Rd, $Rn, $imm */
+  ARM_ORRri /* 1771 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}	$Rd, $Rn, $Rm */
+  ARM_ORRrr /* 1772 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}	$Rd, $Rn, $shift */
+  ARM_ORRrsi /* 1773 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}	$Rd, $Rn, $shift */
+  ARM_ORRrsr /* 1774 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* pkhbt${p}	$Rd, $Rn, $Rm$sh */
+  ARM_PKHBT /* 1775 */, ARM_INS_PKHBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* pkhtb${p}	$Rd, $Rn, $Rm$sh */
+  ARM_PKHTB /* 1776 */, ARM_INS_PKHTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* pldw	$addr */
+  ARM_PLDWi12 /* 1777 */, ARM_INS_PLDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0
+  #endif
+},
+{
+  /* pldw	$shift */
+  ARM_PLDWrs /* 1778 */, ARM_INS_PLDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0
+  #endif
+},
+{
+  /* pld	$addr */
+  ARM_PLDi12 /* 1779 */, ARM_INS_PLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* pld	$shift */
+  ARM_PLDrs /* 1780 */, ARM_INS_PLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* pli	$addr */
+  ARM_PLIi12 /* 1781 */, ARM_INS_PLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* pli	$shift */
+  ARM_PLIrs /* 1782 */, ARM_INS_PLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* qadd${p}	$Rd, $Rm, $Rn */
+  ARM_QADD /* 1783 */, ARM_INS_QADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qadd16${p}	$Rd, $Rn, $Rm */
+  ARM_QADD16 /* 1784 */, ARM_INS_QADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qadd8${p}	$Rd, $Rn, $Rm */
+  ARM_QADD8 /* 1785 */, ARM_INS_QADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qasx${p}	$Rd, $Rn, $Rm */
+  ARM_QASX /* 1786 */, ARM_INS_QASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qdadd${p}	$Rd, $Rm, $Rn */
+  ARM_QDADD /* 1787 */, ARM_INS_QDADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qdsub${p}	$Rd, $Rm, $Rn */
+  ARM_QDSUB /* 1788 */, ARM_INS_QDSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsax${p}	$Rd, $Rn, $Rm */
+  ARM_QSAX /* 1789 */, ARM_INS_QSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsub${p}	$Rd, $Rm, $Rn */
+  ARM_QSUB /* 1790 */, ARM_INS_QSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsub16${p}	$Rd, $Rn, $Rm */
+  ARM_QSUB16 /* 1791 */, ARM_INS_QSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsub8${p}	$Rd, $Rn, $Rm */
+  ARM_QSUB8 /* 1792 */, ARM_INS_QSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rbit${p}	$Rd, $Rm */
+  ARM_RBIT /* 1793 */, ARM_INS_RBIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rev${p}	$Rd, $Rm */
+  ARM_REV /* 1794 */, ARM_INS_REV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* rev16${p}	$Rd, $Rm */
+  ARM_REV16 /* 1795 */, ARM_INS_REV16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* revsh${p}	$Rd, $Rm */
+  ARM_REVSH /* 1796 */, ARM_INS_REVSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeda	$Rn */
+  ARM_RFEDA /* 1797 */, ARM_INS_RFEDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeda	$Rn! */
+  ARM_RFEDA_UPD /* 1798 */, ARM_INS_RFEDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfedb	$Rn */
+  ARM_RFEDB /* 1799 */, ARM_INS_RFEDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfedb	$Rn! */
+  ARM_RFEDB_UPD /* 1800 */, ARM_INS_RFEDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeia	$Rn */
+  ARM_RFEIA /* 1801 */, ARM_INS_RFEIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeia	$Rn! */
+  ARM_RFEIA_UPD /* 1802 */, ARM_INS_RFEIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeib	$Rn */
+  ARM_RFEIB /* 1803 */, ARM_INS_RFEIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeib	$Rn! */
+  ARM_RFEIB_UPD /* 1804 */, ARM_INS_RFEIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, $imm */
+  ARM_RSBri /* 1805 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, $Rm */
+  ARM_RSBrr /* 1806 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, $shift */
+  ARM_RSBrsi /* 1807 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, $shift */
+  ARM_RSBrsr /* 1808 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsc${s}${p}	$Rd, $Rn, $imm */
+  ARM_RSCri /* 1809 */, ARM_INS_RSC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsc${s}${p}	$Rd, $Rn, $Rm */
+  ARM_RSCrr /* 1810 */, ARM_INS_RSC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsc${s}${p}	$Rd, $Rn, $shift */
+  ARM_RSCrsi /* 1811 */, ARM_INS_RSC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsc${s}${p}	$Rd, $Rn, $shift */
+  ARM_RSCrsr /* 1812 */, ARM_INS_RSC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sadd16${p}	$Rd, $Rn, $Rm */
+  ARM_SADD16 /* 1813 */, ARM_INS_SADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sadd8${p}	$Rd, $Rn, $Rm */
+  ARM_SADD8 /* 1814 */, ARM_INS_SADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sasx${p}	$Rd, $Rn, $Rm */
+  ARM_SASX /* 1815 */, ARM_INS_SASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sb */
+  ARM_SB /* 1816 */, ARM_INS_SB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasSB, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}	$Rd, $Rn, $imm */
+  ARM_SBCri /* 1817 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}	$Rd, $Rn, $Rm */
+  ARM_SBCrr /* 1818 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}	$Rd, $Rn, $shift */
+  ARM_SBCrsi /* 1819 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}	$Rd, $Rn, $shift */
+  ARM_SBCrsr /* 1820 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbfx${p}	$Rd, $Rn, $lsb, $width */
+  ARM_SBFX /* 1821 */, ARM_INS_SBFX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sdiv${p}	$Rd, $Rn, $Rm */
+  ARM_SDIV /* 1822 */, ARM_INS_SDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDivideInARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sel${p}	$Rd, $Rn, $Rm */
+  ARM_SEL /* 1823 */, ARM_INS_SEL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* setend	$end */
+  ARM_SETEND /* 1824 */, ARM_INS_SETEND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* setpan	$imm */
+  ARM_SETPAN /* 1825 */, ARM_INS_SETPAN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha1c.32	$Vd, $Vn, $Vm */
+  ARM_SHA1C /* 1826 */, ARM_INS_SHA1C,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha1h.32	$Vd, $Vm */
+  ARM_SHA1H /* 1827 */, ARM_INS_SHA1H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha1m.32	$Vd, $Vn, $Vm */
+  ARM_SHA1M /* 1828 */, ARM_INS_SHA1M,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha1p.32	$Vd, $Vn, $Vm */
+  ARM_SHA1P /* 1829 */, ARM_INS_SHA1P,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha1su0.32	$Vd, $Vn, $Vm */
+  ARM_SHA1SU0 /* 1830 */, ARM_INS_SHA1SU0,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha1su1.32	$Vd, $Vm */
+  ARM_SHA1SU1 /* 1831 */, ARM_INS_SHA1SU1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha256h.32	$Vd, $Vn, $Vm */
+  ARM_SHA256H /* 1832 */, ARM_INS_SHA256H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha256h2.32	$Vd, $Vn, $Vm */
+  ARM_SHA256H2 /* 1833 */, ARM_INS_SHA256H2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha256su0.32	$Vd, $Vm */
+  ARM_SHA256SU0 /* 1834 */, ARM_INS_SHA256SU0,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sha256su1.32	$Vd, $Vn, $Vm */
+  ARM_SHA256SU1 /* 1835 */, ARM_INS_SHA256SU1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasSHA2, 0 }, 0, 0
+  #endif
+},
+{
+  /* shadd16${p}	$Rd, $Rn, $Rm */
+  ARM_SHADD16 /* 1836 */, ARM_INS_SHADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* shadd8${p}	$Rd, $Rn, $Rm */
+  ARM_SHADD8 /* 1837 */, ARM_INS_SHADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* shasx${p}	$Rd, $Rn, $Rm */
+  ARM_SHASX /* 1838 */, ARM_INS_SHASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* shsax${p}	$Rd, $Rn, $Rm */
+  ARM_SHSAX /* 1839 */, ARM_INS_SHSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* shsub16${p}	$Rd, $Rn, $Rm */
+  ARM_SHSUB16 /* 1840 */, ARM_INS_SHSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* shsub8${p}	$Rd, $Rn, $Rm */
+  ARM_SHSUB8 /* 1841 */, ARM_INS_SHSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* smc${p}	$opt */
+  ARM_SMC /* 1842 */, ARM_INS_SMC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasTrustZone, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlabb${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLABB /* 1843 */, ARM_INS_SMLABB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlabt${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLABT /* 1844 */, ARM_INS_SMLABT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlad${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLAD /* 1845 */, ARM_INS_SMLAD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smladx${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLADX /* 1846 */, ARM_INS_SMLADX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlal${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLAL /* 1847 */, ARM_INS_SMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlalbb${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLALBB /* 1848 */, ARM_INS_SMLALBB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlalbt${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLALBT /* 1849 */, ARM_INS_SMLALBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlald${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLALD /* 1850 */, ARM_INS_SMLALD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlaldx${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLALDX /* 1851 */, ARM_INS_SMLALDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlaltb${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLALTB /* 1852 */, ARM_INS_SMLALTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlaltt${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLALTT /* 1853 */, ARM_INS_SMLALTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlatb${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLATB /* 1854 */, ARM_INS_SMLATB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlatt${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLATT /* 1855 */, ARM_INS_SMLATT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlawb${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLAWB /* 1856 */, ARM_INS_SMLAWB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlawt${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLAWT /* 1857 */, ARM_INS_SMLAWT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsd${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLSD /* 1858 */, ARM_INS_SMLSD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsdx${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMLSDX /* 1859 */, ARM_INS_SMLSDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsld${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLSLD /* 1860 */, ARM_INS_SMLSLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsldx${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMLSLDX /* 1861 */, ARM_INS_SMLSLDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmla${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMMLA /* 1862 */, ARM_INS_SMMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmlar${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMMLAR /* 1863 */, ARM_INS_SMMLAR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmls${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMMLS /* 1864 */, ARM_INS_SMMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmlsr${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_SMMLSR /* 1865 */, ARM_INS_SMMLSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmul${p}	$Rd, $Rn, $Rm */
+  ARM_SMMUL /* 1866 */, ARM_INS_SMMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmulr${p}	$Rd, $Rn, $Rm */
+  ARM_SMMULR /* 1867 */, ARM_INS_SMMULR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smuad${p}	$Rd, $Rn, $Rm */
+  ARM_SMUAD /* 1868 */, ARM_INS_SMUAD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smuadx${p}	$Rd, $Rn, $Rm */
+  ARM_SMUADX /* 1869 */, ARM_INS_SMUADX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulbb${p}	$Rd, $Rn, $Rm */
+  ARM_SMULBB /* 1870 */, ARM_INS_SMULBB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulbt${p}	$Rd, $Rn, $Rm */
+  ARM_SMULBT /* 1871 */, ARM_INS_SMULBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smull${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_SMULL /* 1872 */, ARM_INS_SMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smultb${p}	$Rd, $Rn, $Rm */
+  ARM_SMULTB /* 1873 */, ARM_INS_SMULTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smultt${p}	$Rd, $Rn, $Rm */
+  ARM_SMULTT /* 1874 */, ARM_INS_SMULTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulwb${p}	$Rd, $Rn, $Rm */
+  ARM_SMULWB /* 1875 */, ARM_INS_SMULWB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulwt${p}	$Rd, $Rn, $Rm */
+  ARM_SMULWT /* 1876 */, ARM_INS_SMULWT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* smusd${p}	$Rd, $Rn, $Rm */
+  ARM_SMUSD /* 1877 */, ARM_INS_SMUSD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* smusdx${p}	$Rd, $Rn, $Rm */
+  ARM_SMUSDX /* 1878 */, ARM_INS_SMUSDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsda	sp, $mode */
+  ARM_SRSDA /* 1879 */, ARM_INS_SRSDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsda	sp!, $mode */
+  ARM_SRSDA_UPD /* 1880 */, ARM_INS_SRSDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsdb	sp, $mode */
+  ARM_SRSDB /* 1881 */, ARM_INS_SRSDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsdb	sp!, $mode */
+  ARM_SRSDB_UPD /* 1882 */, ARM_INS_SRSDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsia	sp, $mode */
+  ARM_SRSIA /* 1883 */, ARM_INS_SRSIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsia	sp!, $mode */
+  ARM_SRSIA_UPD /* 1884 */, ARM_INS_SRSIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsib	sp, $mode */
+  ARM_SRSIB /* 1885 */, ARM_INS_SRSIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsib	sp!, $mode */
+  ARM_SRSIB_UPD /* 1886 */, ARM_INS_SRSIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssat${p}	$Rd, $sat_imm, $Rn$sh */
+  ARM_SSAT /* 1887 */, ARM_INS_SSAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssat16${p}	$Rd, $sat_imm, $Rn */
+  ARM_SSAT16 /* 1888 */, ARM_INS_SSAT16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssax${p}	$Rd, $Rn, $Rm */
+  ARM_SSAX /* 1889 */, ARM_INS_SSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssub16${p}	$Rd, $Rn, $Rm */
+  ARM_SSUB16 /* 1890 */, ARM_INS_SSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssub8${p}	$Rd, $Rn, $Rm */
+  ARM_SSUB8 /* 1891 */, ARM_INS_SSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l	$cop, $CRd, $addr */
+  ARM_STC2L_OFFSET /* 1892 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l	$cop, $CRd, $addr, $option */
+  ARM_STC2L_OPTION /* 1893 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l	$cop, $CRd, $addr, $offset */
+  ARM_STC2L_POST /* 1894 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l	$cop, $CRd, $addr! */
+  ARM_STC2L_PRE /* 1895 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2	$cop, $CRd, $addr */
+  ARM_STC2_OFFSET /* 1896 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2	$cop, $CRd, $addr, $option */
+  ARM_STC2_OPTION /* 1897 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2	$cop, $CRd, $addr, $offset */
+  ARM_STC2_POST /* 1898 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2	$cop, $CRd, $addr! */
+  ARM_STC2_PRE /* 1899 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr */
+  ARM_STCL_OFFSET /* 1900 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr, $option */
+  ARM_STCL_OPTION /* 1901 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr, $offset */
+  ARM_STCL_POST /* 1902 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr! */
+  ARM_STCL_PRE /* 1903 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr */
+  ARM_STC_OFFSET /* 1904 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr, $option */
+  ARM_STC_OPTION /* 1905 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr, $offset */
+  ARM_STC_POST /* 1906 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr! */
+  ARM_STC_PRE /* 1907 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stl${p}	$Rt, $addr */
+  ARM_STL /* 1908 */, ARM_INS_STL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlb${p}	$Rt, $addr */
+  ARM_STLB /* 1909 */, ARM_INS_STLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlex${p}	$Rd, $Rt, $addr */
+  ARM_STLEX /* 1910 */, ARM_INS_STLEX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlexb${p}	$Rd, $Rt, $addr */
+  ARM_STLEXB /* 1911 */, ARM_INS_STLEXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlexd${p}	$Rd, $Rt, $addr */
+  ARM_STLEXD /* 1912 */, ARM_INS_STLEXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlexh${p}	$Rd, $Rt, $addr */
+  ARM_STLEXH /* 1913 */, ARM_INS_STLEXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlh${p}	$Rt, $addr */
+  ARM_STLH /* 1914 */, ARM_INS_STLH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmda${p}	$Rn, $regs */
+  ARM_STMDA /* 1915 */, ARM_INS_STMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmda${p}	$Rn!, $regs */
+  ARM_STMDA_UPD /* 1916 */, ARM_INS_STMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmdb${p}	$Rn, $regs */
+  ARM_STMDB /* 1917 */, ARM_INS_STMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmdb${p}	$Rn!, $regs */
+  ARM_STMDB_UPD /* 1918 */, ARM_INS_STMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}	$Rn, $regs */
+  ARM_STMIA /* 1919 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}	$Rn!, $regs */
+  ARM_STMIA_UPD /* 1920 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmib${p}	$Rn, $regs */
+  ARM_STMIB /* 1921 */, ARM_INS_STMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmib${p}	$Rn!, $regs */
+  ARM_STMIB_UPD /* 1922 */, ARM_INS_STMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strbt${p}	$Rt, $addr, $offset */
+  ARM_STRBT_POST_IMM /* 1923 */, ARM_INS_STRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strbt${p}	$Rt, $addr, $offset */
+  ARM_STRBT_POST_REG /* 1924 */, ARM_INS_STRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr, $offset */
+  ARM_STRB_POST_IMM /* 1925 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr, $offset */
+  ARM_STRB_POST_REG /* 1926 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr! */
+  ARM_STRB_PRE_IMM /* 1927 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr! */
+  ARM_STRB_PRE_REG /* 1928 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr */
+  ARM_STRBi12 /* 1929 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $shift */
+  ARM_STRBrs /* 1930 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strd${p}	$Rt, $Rt2, $addr */
+  ARM_STRD /* 1931 */, ARM_INS_STRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV5TE, 0 }, 0, 0
+  #endif
+},
+{
+  /* strd${p}	$Rt, $Rt2, $addr, $offset */
+  ARM_STRD_POST /* 1932 */, ARM_INS_STRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strd${p}	$Rt, $Rt2, $addr! */
+  ARM_STRD_PRE /* 1933 */, ARM_INS_STRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strex${p}	$Rd, $Rt, $addr */
+  ARM_STREX /* 1934 */, ARM_INS_STREX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strexb${p}	$Rd, $Rt, $addr */
+  ARM_STREXB /* 1935 */, ARM_INS_STREXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strexd${p}	$Rd, $Rt, $addr */
+  ARM_STREXD /* 1936 */, ARM_INS_STREXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strexh${p}	$Rd, $Rt, $addr */
+  ARM_STREXH /* 1937 */, ARM_INS_STREXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr */
+  ARM_STRH /* 1938 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strht${p}	$Rt, $addr, $offset */
+  ARM_STRHTi /* 1939 */, ARM_INS_STRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strht${p}	$Rt, $addr, $Rm */
+  ARM_STRHTr /* 1940 */, ARM_INS_STRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr, $offset */
+  ARM_STRH_POST /* 1941 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr! */
+  ARM_STRH_PRE /* 1942 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strt${p}	$Rt, $addr, $offset */
+  ARM_STRT_POST_IMM /* 1943 */, ARM_INS_STRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* strt${p}	$Rt, $addr, $offset */
+  ARM_STRT_POST_REG /* 1944 */, ARM_INS_STRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr, $offset */
+  ARM_STR_POST_IMM /* 1945 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr, $offset */
+  ARM_STR_POST_REG /* 1946 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr! */
+  ARM_STR_PRE_IMM /* 1947 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr! */
+  ARM_STR_PRE_REG /* 1948 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr */
+  ARM_STRi12 /* 1949 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $shift */
+  ARM_STRrs /* 1950 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rd, $Rn, $imm */
+  ARM_SUBri /* 1951 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rd, $Rn, $Rm */
+  ARM_SUBrr /* 1952 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rd, $Rn, $shift */
+  ARM_SUBrsi /* 1953 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rd, $Rn, $shift */
+  ARM_SUBrsr /* 1954 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* svc${p}	$svc */
+  ARM_SVC /* 1955 */, ARM_INS_SVC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* swp${p}	$Rt, $Rt2, $addr */
+  ARM_SWP /* 1956 */, ARM_INS_SWP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* swpb${p}	$Rt, $Rt2, $addr */
+  ARM_SWPB /* 1957 */, ARM_INS_SWPB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtab${p}	$Rd, $Rn, $Rm$rot */
+  ARM_SXTAB /* 1958 */, ARM_INS_SXTAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtab16${p}	$Rd, $Rn, $Rm$rot */
+  ARM_SXTAB16 /* 1959 */, ARM_INS_SXTAB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtah${p}	$Rd, $Rn, $Rm$rot */
+  ARM_SXTAH /* 1960 */, ARM_INS_SXTAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtb${p}	$Rd, $Rm$rot */
+  ARM_SXTB /* 1961 */, ARM_INS_SXTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtb16${p}	$Rd, $Rm$rot */
+  ARM_SXTB16 /* 1962 */, ARM_INS_SXTB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxth${p}	$Rd, $Rm$rot */
+  ARM_SXTH /* 1963 */, ARM_INS_SXTH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* teq${p}	$Rn, $imm */
+  ARM_TEQri /* 1964 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* teq${p}	$Rn, $Rm */
+  ARM_TEQrr /* 1965 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* teq${p}	$Rn, $shift */
+  ARM_TEQrsi /* 1966 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* teq${p}	$Rn, $shift */
+  ARM_TEQrsr /* 1967 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* trap */
+  ARM_TRAP /* 1968 */, ARM_INS_TRAP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* trap */
+  ARM_TRAPNaCl /* 1969 */, ARM_INS_TRAP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_UseNaClTrap, 0 }, 0, 0
+  #endif
+},
+{
+  /* tsb	$opt */
+  ARM_TSB /* 1970 */, ARM_INS_TSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV8_4a, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}	$Rn, $imm */
+  ARM_TSTri /* 1971 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}	$Rn, $Rm */
+  ARM_TSTrr /* 1972 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}	$Rn, $shift */
+  ARM_TSTrsi /* 1973 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}	$Rn, $shift */
+  ARM_TSTrsr /* 1974 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uadd16${p}	$Rd, $Rn, $Rm */
+  ARM_UADD16 /* 1975 */, ARM_INS_UADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uadd8${p}	$Rd, $Rn, $Rm */
+  ARM_UADD8 /* 1976 */, ARM_INS_UADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uasx${p}	$Rd, $Rn, $Rm */
+  ARM_UASX /* 1977 */, ARM_INS_UASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ubfx${p}	$Rd, $Rn, $lsb, $width */
+  ARM_UBFX /* 1978 */, ARM_INS_UBFX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6T2, 0 }, 0, 0
+  #endif
+},
+{
+  /* udf	$imm16 */
+  ARM_UDF /* 1979 */, ARM_INS_UDF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* udiv${p}	$Rd, $Rn, $Rm */
+  ARM_UDIV /* 1980 */, ARM_INS_UDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasDivideInARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhadd16${p}	$Rd, $Rn, $Rm */
+  ARM_UHADD16 /* 1981 */, ARM_INS_UHADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhadd8${p}	$Rd, $Rn, $Rm */
+  ARM_UHADD8 /* 1982 */, ARM_INS_UHADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhasx${p}	$Rd, $Rn, $Rm */
+  ARM_UHASX /* 1983 */, ARM_INS_UHASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhsax${p}	$Rd, $Rn, $Rm */
+  ARM_UHSAX /* 1984 */, ARM_INS_UHSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhsub16${p}	$Rd, $Rn, $Rm */
+  ARM_UHSUB16 /* 1985 */, ARM_INS_UHSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhsub8${p}	$Rd, $Rn, $Rm */
+  ARM_UHSUB8 /* 1986 */, ARM_INS_UHSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* umaal${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_UMAAL /* 1987 */, ARM_INS_UMAAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* umlal${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_UMLAL /* 1988 */, ARM_INS_UMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* umull${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_UMULL /* 1989 */, ARM_INS_UMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqadd16${p}	$Rd, $Rn, $Rm */
+  ARM_UQADD16 /* 1990 */, ARM_INS_UQADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqadd8${p}	$Rd, $Rn, $Rm */
+  ARM_UQADD8 /* 1991 */, ARM_INS_UQADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqasx${p}	$Rd, $Rn, $Rm */
+  ARM_UQASX /* 1992 */, ARM_INS_UQASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqsax${p}	$Rd, $Rn, $Rm */
+  ARM_UQSAX /* 1993 */, ARM_INS_UQSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqsub16${p}	$Rd, $Rn, $Rm */
+  ARM_UQSUB16 /* 1994 */, ARM_INS_UQSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqsub8${p}	$Rd, $Rn, $Rm */
+  ARM_UQSUB8 /* 1995 */, ARM_INS_UQSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* usad8${p}	$Rd, $Rn, $Rm */
+  ARM_USAD8 /* 1996 */, ARM_INS_USAD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* usada8${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_USADA8 /* 1997 */, ARM_INS_USADA8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* usat${p}	$Rd, $sat_imm, $Rn$sh */
+  ARM_USAT /* 1998 */, ARM_INS_USAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* usat16${p}	$Rd, $sat_imm, $Rn */
+  ARM_USAT16 /* 1999 */, ARM_INS_USAT16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* usax${p}	$Rd, $Rn, $Rm */
+  ARM_USAX /* 2000 */, ARM_INS_USAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* usub16${p}	$Rd, $Rn, $Rm */
+  ARM_USUB16 /* 2001 */, ARM_INS_USUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* usub8${p}	$Rd, $Rn, $Rm */
+  ARM_USUB8 /* 2002 */, ARM_INS_USUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtab${p}	$Rd, $Rn, $Rm$rot */
+  ARM_UXTAB /* 2003 */, ARM_INS_UXTAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtab16${p}	$Rd, $Rn, $Rm$rot */
+  ARM_UXTAB16 /* 2004 */, ARM_INS_UXTAB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtah${p}	$Rd, $Rn, $Rm$rot */
+  ARM_UXTAH /* 2005 */, ARM_INS_UXTAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtb${p}	$Rd, $Rm$rot */
+  ARM_UXTB /* 2006 */, ARM_INS_UXTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtb16${p}	$Rd, $Rm$rot */
+  ARM_UXTB16 /* 2007 */, ARM_INS_UXTB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxth${p}	$Rd, $Rm$rot */
+  ARM_UXTH /* 2008 */, ARM_INS_UXTH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabal${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VABALsv2i64 /* 2009 */, ARM_INS_VABAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabal${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VABALsv4i32 /* 2010 */, ARM_INS_VABAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabal${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VABALsv8i16 /* 2011 */, ARM_INS_VABAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabal${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VABALuv2i64 /* 2012 */, ARM_INS_VABAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabal${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VABALuv4i32 /* 2013 */, ARM_INS_VABAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabal${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VABALuv8i16 /* 2014 */, ARM_INS_VABAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VABAsv16i8 /* 2015 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VABAsv2i32 /* 2016 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VABAsv4i16 /* 2017 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VABAsv4i32 /* 2018 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VABAsv8i16 /* 2019 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VABAsv8i8 /* 2020 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VABAuv16i8 /* 2021 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VABAuv2i32 /* 2022 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VABAuv4i16 /* 2023 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VABAuv4i32 /* 2024 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VABAuv8i16 /* 2025 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaba${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VABAuv8i8 /* 2026 */, ARM_INS_VABA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabdl${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VABDLsv2i64 /* 2027 */, ARM_INS_VABDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabdl${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VABDLsv4i32 /* 2028 */, ARM_INS_VABDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabdl${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VABDLsv8i16 /* 2029 */, ARM_INS_VABDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabdl${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VABDLuv2i64 /* 2030 */, ARM_INS_VABDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabdl${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VABDLuv4i32 /* 2031 */, ARM_INS_VABDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabdl${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VABDLuv8i16 /* 2032 */, ARM_INS_VABDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VABDfd /* 2033 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VABDfq /* 2034 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VABDhd /* 2035 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VABDhq /* 2036 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VABDsv16i8 /* 2037 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VABDsv2i32 /* 2038 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VABDsv4i16 /* 2039 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VABDsv4i32 /* 2040 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VABDsv8i16 /* 2041 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VABDsv8i8 /* 2042 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VABDuv16i8 /* 2043 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VABDuv2i32 /* 2044 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VABDuv4i16 /* 2045 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VABDuv4i32 /* 2046 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VABDuv8i16 /* 2047 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VABDuv8i8 /* 2048 */, ARM_INS_VABD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f64	$Dd, $Dm */
+  ARM_VABSD /* 2049 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f16	$Sd, $Sm */
+  ARM_VABSH /* 2050 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f32	$Sd, $Sm */
+  ARM_VABSS /* 2051 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f32	$Vd, $Vm */
+  ARM_VABSfd /* 2052 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f32	$Vd, $Vm */
+  ARM_VABSfq /* 2053 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f16	$Vd, $Vm */
+  ARM_VABShd /* 2054 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.f16	$Vd, $Vm */
+  ARM_VABShq /* 2055 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.s8	$Vd, $Vm */
+  ARM_VABSv16i8 /* 2056 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.s32	$Vd, $Vm */
+  ARM_VABSv2i32 /* 2057 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.s16	$Vd, $Vm */
+  ARM_VABSv4i16 /* 2058 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.s32	$Vd, $Vm */
+  ARM_VABSv4i32 /* 2059 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.s16	$Vd, $Vm */
+  ARM_VABSv8i16 /* 2060 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vabs${p}.s8	$Vd, $Vm */
+  ARM_VABSv8i8 /* 2061 */, ARM_INS_VABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacge${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VACGEfd /* 2062 */, ARM_INS_VACGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacge${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VACGEfq /* 2063 */, ARM_INS_VACGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacge${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VACGEhd /* 2064 */, ARM_INS_VACGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacge${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VACGEhq /* 2065 */, ARM_INS_VACGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacgt${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VACGTfd /* 2066 */, ARM_INS_VACGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacgt${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VACGTfq /* 2067 */, ARM_INS_VACGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacgt${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VACGThd /* 2068 */, ARM_INS_VACGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vacgt${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VACGThq /* 2069 */, ARM_INS_VACGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VADDD /* 2070 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VADDH /* 2071 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddhn${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VADDHNv2i32 /* 2072 */, ARM_INS_VADDHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddhn${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VADDHNv4i16 /* 2073 */, ARM_INS_VADDHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddhn${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VADDHNv8i8 /* 2074 */, ARM_INS_VADDHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddl${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VADDLsv2i64 /* 2075 */, ARM_INS_VADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddl${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VADDLsv4i32 /* 2076 */, ARM_INS_VADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddl${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VADDLsv8i16 /* 2077 */, ARM_INS_VADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddl${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VADDLuv2i64 /* 2078 */, ARM_INS_VADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddl${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VADDLuv4i32 /* 2079 */, ARM_INS_VADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddl${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VADDLuv8i16 /* 2080 */, ARM_INS_VADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VADDS /* 2081 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddw${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VADDWsv2i64 /* 2082 */, ARM_INS_VADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddw${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VADDWsv4i32 /* 2083 */, ARM_INS_VADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddw${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VADDWsv8i16 /* 2084 */, ARM_INS_VADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddw${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VADDWuv2i64 /* 2085 */, ARM_INS_VADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddw${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VADDWuv4i32 /* 2086 */, ARM_INS_VADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vaddw${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VADDWuv8i16 /* 2087 */, ARM_INS_VADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VADDfd /* 2088 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VADDfq /* 2089 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VADDhd /* 2090 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VADDhq /* 2091 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VADDv16i8 /* 2092 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VADDv1i64 /* 2093 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VADDv2i32 /* 2094 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VADDv2i64 /* 2095 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VADDv4i16 /* 2096 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VADDv4i32 /* 2097 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VADDv8i16 /* 2098 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vadd${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VADDv8i8 /* 2099 */, ARM_INS_VADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vand${p}	$Vd, $Vn, $Vm */
+  ARM_VANDd /* 2100 */, ARM_INS_VAND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vand${p}	$Vd, $Vn, $Vm */
+  ARM_VANDq /* 2101 */, ARM_INS_VAND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmab.bf16	$Vd, $Vn, $Vm */
+  ARM_VBF16MALBQ /* 2102 */, ARM_INS_VFMAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmab.bf16	$Vd, $Vn, $Vm$idx */
+  ARM_VBF16MALBQI /* 2103 */, ARM_INS_VFMAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmat.bf16	$Vd, $Vn, $Vm */
+  ARM_VBF16MALTQ /* 2104 */, ARM_INS_VFMAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmat.bf16	$Vd, $Vn, $Vm$idx */
+  ARM_VBF16MALTQI /* 2105 */, ARM_INS_VFMAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${p}	$Vd, $Vn, $Vm */
+  ARM_VBICd /* 2106 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${p}.i32	$Vd, $SIMM */
+  ARM_VBICiv2i32 /* 2107 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${p}.i16	$Vd, $SIMM */
+  ARM_VBICiv4i16 /* 2108 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${p}.i32	$Vd, $SIMM */
+  ARM_VBICiv4i32 /* 2109 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${p}.i16	$Vd, $SIMM */
+  ARM_VBICiv8i16 /* 2110 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbic${p}	$Vd, $Vn, $Vm */
+  ARM_VBICq /* 2111 */, ARM_INS_VBIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbif${p}	$Vd, $Vn, $Vm */
+  ARM_VBIFd /* 2112 */, ARM_INS_VBIF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbif${p}	$Vd, $Vn, $Vm */
+  ARM_VBIFq /* 2113 */, ARM_INS_VBIF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbit${p}	$Vd, $Vn, $Vm */
+  ARM_VBITd /* 2114 */, ARM_INS_VBIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbit${p}	$Vd, $Vn, $Vm */
+  ARM_VBITq /* 2115 */, ARM_INS_VBIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbsl${p}	$Vd, $Vn, $Vm */
+  ARM_VBSLd /* 2116 */, ARM_INS_VBSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vbsl${p}	$Vd, $Vn, $Vm */
+  ARM_VBSLq /* 2117 */, ARM_INS_VBSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VBSPd /* 2118 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VBSPq /* 2119 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd.f32	$Vd, $Vn, $Vm, $rot */
+  ARM_VCADDv2f32 /* 2120 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd.f16	$Vd, $Vn, $Vm, $rot */
+  ARM_VCADDv4f16 /* 2121 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd.f32	$Vd, $Vn, $Vm, $rot */
+  ARM_VCADDv4f32 /* 2122 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcadd.f16	$Vd, $Vn, $Vm, $rot */
+  ARM_VCADDv8f16 /* 2123 */, ARM_INS_VCADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VCEQfd /* 2124 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VCEQfq /* 2125 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VCEQhd /* 2126 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VCEQhq /* 2127 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VCEQv16i8 /* 2128 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VCEQv2i32 /* 2129 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VCEQv4i16 /* 2130 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VCEQv4i32 /* 2131 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VCEQv8i16 /* 2132 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VCEQv8i8 /* 2133 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i8	$Vd, $Vm, #0 */
+  ARM_VCEQzv16i8 /* 2134 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCEQzv2f32 /* 2135 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i32	$Vd, $Vm, #0 */
+  ARM_VCEQzv2i32 /* 2136 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCEQzv4f16 /* 2137 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCEQzv4f32 /* 2138 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i16	$Vd, $Vm, #0 */
+  ARM_VCEQzv4i16 /* 2139 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i32	$Vd, $Vm, #0 */
+  ARM_VCEQzv4i32 /* 2140 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCEQzv8f16 /* 2141 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i16	$Vd, $Vm, #0 */
+  ARM_VCEQzv8i16 /* 2142 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vceq${p}.i8	$Vd, $Vm, #0 */
+  ARM_VCEQzv8i8 /* 2143 */, ARM_INS_VCEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VCGEfd /* 2144 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VCGEfq /* 2145 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VCGEhd /* 2146 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VCGEhq /* 2147 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VCGEsv16i8 /* 2148 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VCGEsv2i32 /* 2149 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VCGEsv4i16 /* 2150 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VCGEsv4i32 /* 2151 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VCGEsv8i16 /* 2152 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VCGEsv8i8 /* 2153 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VCGEuv16i8 /* 2154 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VCGEuv2i32 /* 2155 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VCGEuv4i16 /* 2156 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VCGEuv4i32 /* 2157 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VCGEuv8i16 /* 2158 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VCGEuv8i8 /* 2159 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCGEzv16i8 /* 2160 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCGEzv2f32 /* 2161 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCGEzv2i32 /* 2162 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCGEzv4f16 /* 2163 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCGEzv4f32 /* 2164 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCGEzv4i16 /* 2165 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCGEzv4i32 /* 2166 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCGEzv8f16 /* 2167 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCGEzv8i16 /* 2168 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcge${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCGEzv8i8 /* 2169 */, ARM_INS_VCGE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VCGTfd /* 2170 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VCGTfq /* 2171 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VCGThd /* 2172 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VCGThq /* 2173 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VCGTsv16i8 /* 2174 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VCGTsv2i32 /* 2175 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VCGTsv4i16 /* 2176 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VCGTsv4i32 /* 2177 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VCGTsv8i16 /* 2178 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VCGTsv8i8 /* 2179 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VCGTuv16i8 /* 2180 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VCGTuv2i32 /* 2181 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VCGTuv4i16 /* 2182 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VCGTuv4i32 /* 2183 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VCGTuv8i16 /* 2184 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VCGTuv8i8 /* 2185 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCGTzv16i8 /* 2186 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCGTzv2f32 /* 2187 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCGTzv2i32 /* 2188 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCGTzv4f16 /* 2189 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCGTzv4f32 /* 2190 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCGTzv4i16 /* 2191 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCGTzv4i32 /* 2192 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCGTzv8f16 /* 2193 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCGTzv8i16 /* 2194 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcgt${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCGTzv8i8 /* 2195 */, ARM_INS_VCGT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCLEzv16i8 /* 2196 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCLEzv2f32 /* 2197 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCLEzv2i32 /* 2198 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCLEzv4f16 /* 2199 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCLEzv4f32 /* 2200 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCLEzv4i16 /* 2201 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCLEzv4i32 /* 2202 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCLEzv8f16 /* 2203 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCLEzv8i16 /* 2204 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcle${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCLEzv8i8 /* 2205 */, ARM_INS_VCLE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${p}.s8	$Vd, $Vm */
+  ARM_VCLSv16i8 /* 2206 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${p}.s32	$Vd, $Vm */
+  ARM_VCLSv2i32 /* 2207 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${p}.s16	$Vd, $Vm */
+  ARM_VCLSv4i16 /* 2208 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${p}.s32	$Vd, $Vm */
+  ARM_VCLSv4i32 /* 2209 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${p}.s16	$Vd, $Vm */
+  ARM_VCLSv8i16 /* 2210 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcls${p}.s8	$Vd, $Vm */
+  ARM_VCLSv8i8 /* 2211 */, ARM_INS_VCLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCLTzv16i8 /* 2212 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCLTzv2f32 /* 2213 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCLTzv2i32 /* 2214 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCLTzv4f16 /* 2215 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.f32	$Vd, $Vm, #0 */
+  ARM_VCLTzv4f32 /* 2216 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCLTzv4i16 /* 2217 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.s32	$Vd, $Vm, #0 */
+  ARM_VCLTzv4i32 /* 2218 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.f16	$Vd, $Vm, #0 */
+  ARM_VCLTzv8f16 /* 2219 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.s16	$Vd, $Vm, #0 */
+  ARM_VCLTzv8i16 /* 2220 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclt${p}.s8	$Vd, $Vm, #0 */
+  ARM_VCLTzv8i8 /* 2221 */, ARM_INS_VCLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${p}.i8	$Vd, $Vm */
+  ARM_VCLZv16i8 /* 2222 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${p}.i32	$Vd, $Vm */
+  ARM_VCLZv2i32 /* 2223 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${p}.i16	$Vd, $Vm */
+  ARM_VCLZv4i16 /* 2224 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${p}.i32	$Vd, $Vm */
+  ARM_VCLZv4i32 /* 2225 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${p}.i16	$Vd, $Vm */
+  ARM_VCLZv8i16 /* 2226 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vclz${p}.i8	$Vd, $Vm */
+  ARM_VCLZv8i8 /* 2227 */, ARM_INS_VCLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f32	$Vd, $Vn, $Vm, $rot */
+  ARM_VCMLAv2f32 /* 2228 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f32	$Vd, $Vn, $Vm$lane, $rot */
+  ARM_VCMLAv2f32_indexed /* 2229 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f16	$Vd, $Vn, $Vm, $rot */
+  ARM_VCMLAv4f16 /* 2230 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f16	$Vd, $Vn, $Vm$lane, $rot */
+  ARM_VCMLAv4f16_indexed /* 2231 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f32	$Vd, $Vn, $Vm, $rot */
+  ARM_VCMLAv4f32 /* 2232 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f32	$Vd, $Vn, $Vm$lane, $rot */
+  ARM_VCMLAv4f32_indexed /* 2233 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f16	$Vd, $Vn, $Vm, $rot */
+  ARM_VCMLAv8f16 /* 2234 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmla.f16	$Vd, $Vn, $Vm$lane, $rot */
+  ARM_VCMLAv8f16_indexed /* 2235 */, ARM_INS_VCMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_3a, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${p}.f64	$Dd, $Dm */
+  ARM_VCMPD /* 2236 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmpe${p}.f64	$Dd, $Dm */
+  ARM_VCMPED /* 2237 */, ARM_INS_VCMPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmpe${p}.f16	$Sd, $Sm */
+  ARM_VCMPEH /* 2238 */, ARM_INS_VCMPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmpe${p}.f32	$Sd, $Sm */
+  ARM_VCMPES /* 2239 */, ARM_INS_VCMPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmpe${p}.f64	$Dd, #0 */
+  ARM_VCMPEZD /* 2240 */, ARM_INS_VCMPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmpe${p}.f16	$Sd, #0 */
+  ARM_VCMPEZH /* 2241 */, ARM_INS_VCMPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmpe${p}.f32	$Sd, #0 */
+  ARM_VCMPEZS /* 2242 */, ARM_INS_VCMPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${p}.f16	$Sd, $Sm */
+  ARM_VCMPH /* 2243 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${p}.f32	$Sd, $Sm */
+  ARM_VCMPS /* 2244 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${p}.f64	$Dd, #0 */
+  ARM_VCMPZD /* 2245 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${p}.f16	$Sd, #0 */
+  ARM_VCMPZH /* 2246 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcmp${p}.f32	$Sd, #0 */
+  ARM_VCMPZS /* 2247 */, ARM_INS_VCMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcnt${p}.8	$Vd, $Vm */
+  ARM_VCNTd /* 2248 */, ARM_INS_VCNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcnt${p}.8	$Vd, $Vm */
+  ARM_VCNTq /* 2249 */, ARM_INS_VCNT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s32.f32	$Vd, $Vm */
+  ARM_VCVTANSDf /* 2250 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s16.f16	$Vd, $Vm */
+  ARM_VCVTANSDh /* 2251 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s32.f32	$Vd, $Vm */
+  ARM_VCVTANSQf /* 2252 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s16.f16	$Vd, $Vm */
+  ARM_VCVTANSQh /* 2253 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u32.f32	$Vd, $Vm */
+  ARM_VCVTANUDf /* 2254 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u16.f16	$Vd, $Vm */
+  ARM_VCVTANUDh /* 2255 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u32.f32	$Vd, $Vm */
+  ARM_VCVTANUQf /* 2256 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u16.f16	$Vd, $Vm */
+  ARM_VCVTANUQh /* 2257 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s32.f64	$Sd, $Dm */
+  ARM_VCVTASD /* 2258 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s32.f16	$Sd, $Sm */
+  ARM_VCVTASH /* 2259 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.s32.f32	$Sd, $Sm */
+  ARM_VCVTASS /* 2260 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u32.f64	$Sd, $Dm */
+  ARM_VCVTAUD /* 2261 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u32.f16	$Sd, $Sm */
+  ARM_VCVTAUH /* 2262 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvta.u32.f32	$Sd, $Sm */
+  ARM_VCVTAUS /* 2263 */, ARM_INS_VCVTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${p}.f16.f64	$Sd, $Dm */
+  ARM_VCVTBDH /* 2264 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${p}.f64.f16	$Dd, $Sm */
+  ARM_VCVTBHD /* 2265 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${p}.f32.f16	$Sd, $Sm */
+  ARM_VCVTBHS /* 2266 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtb${p}.f16.f32	$Sd, $Sm */
+  ARM_VCVTBSH /* 2267 */, ARM_INS_VCVTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.f32	$Dd, $Sm */
+  ARM_VCVTDS /* 2268 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s32.f32	$Vd, $Vm */
+  ARM_VCVTMNSDf /* 2269 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s16.f16	$Vd, $Vm */
+  ARM_VCVTMNSDh /* 2270 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s32.f32	$Vd, $Vm */
+  ARM_VCVTMNSQf /* 2271 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s16.f16	$Vd, $Vm */
+  ARM_VCVTMNSQh /* 2272 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u32.f32	$Vd, $Vm */
+  ARM_VCVTMNUDf /* 2273 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u16.f16	$Vd, $Vm */
+  ARM_VCVTMNUDh /* 2274 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u32.f32	$Vd, $Vm */
+  ARM_VCVTMNUQf /* 2275 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u16.f16	$Vd, $Vm */
+  ARM_VCVTMNUQh /* 2276 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s32.f64	$Sd, $Dm */
+  ARM_VCVTMSD /* 2277 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s32.f16	$Sd, $Sm */
+  ARM_VCVTMSH /* 2278 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.s32.f32	$Sd, $Sm */
+  ARM_VCVTMSS /* 2279 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u32.f64	$Sd, $Dm */
+  ARM_VCVTMUD /* 2280 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u32.f16	$Sd, $Sm */
+  ARM_VCVTMUH /* 2281 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtm.u32.f32	$Sd, $Sm */
+  ARM_VCVTMUS /* 2282 */, ARM_INS_VCVTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s32.f32	$Vd, $Vm */
+  ARM_VCVTNNSDf /* 2283 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s16.f16	$Vd, $Vm */
+  ARM_VCVTNNSDh /* 2284 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s32.f32	$Vd, $Vm */
+  ARM_VCVTNNSQf /* 2285 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s16.f16	$Vd, $Vm */
+  ARM_VCVTNNSQh /* 2286 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u32.f32	$Vd, $Vm */
+  ARM_VCVTNNUDf /* 2287 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u16.f16	$Vd, $Vm */
+  ARM_VCVTNNUDh /* 2288 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u32.f32	$Vd, $Vm */
+  ARM_VCVTNNUQf /* 2289 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u16.f16	$Vd, $Vm */
+  ARM_VCVTNNUQh /* 2290 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s32.f64	$Sd, $Dm */
+  ARM_VCVTNSD /* 2291 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s32.f16	$Sd, $Sm */
+  ARM_VCVTNSH /* 2292 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.s32.f32	$Sd, $Sm */
+  ARM_VCVTNSS /* 2293 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u32.f64	$Sd, $Dm */
+  ARM_VCVTNUD /* 2294 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u32.f16	$Sd, $Sm */
+  ARM_VCVTNUH /* 2295 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtn.u32.f32	$Sd, $Sm */
+  ARM_VCVTNUS /* 2296 */, ARM_INS_VCVTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s32.f32	$Vd, $Vm */
+  ARM_VCVTPNSDf /* 2297 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s16.f16	$Vd, $Vm */
+  ARM_VCVTPNSDh /* 2298 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s32.f32	$Vd, $Vm */
+  ARM_VCVTPNSQf /* 2299 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s16.f16	$Vd, $Vm */
+  ARM_VCVTPNSQh /* 2300 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u32.f32	$Vd, $Vm */
+  ARM_VCVTPNUDf /* 2301 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u16.f16	$Vd, $Vm */
+  ARM_VCVTPNUDh /* 2302 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u32.f32	$Vd, $Vm */
+  ARM_VCVTPNUQf /* 2303 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u16.f16	$Vd, $Vm */
+  ARM_VCVTPNUQh /* 2304 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s32.f64	$Sd, $Dm */
+  ARM_VCVTPSD /* 2305 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s32.f16	$Sd, $Sm */
+  ARM_VCVTPSH /* 2306 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.s32.f32	$Sd, $Sm */
+  ARM_VCVTPSS /* 2307 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u32.f64	$Sd, $Dm */
+  ARM_VCVTPUD /* 2308 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u32.f16	$Sd, $Sm */
+  ARM_VCVTPUH /* 2309 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtp.u32.f32	$Sd, $Sm */
+  ARM_VCVTPUS /* 2310 */, ARM_INS_VCVTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.f64	$Sd, $Dm */
+  ARM_VCVTSD /* 2311 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${p}.f16.f64	$Sd, $Dm */
+  ARM_VCVTTDH /* 2312 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${p}.f64.f16	$Dd, $Sm */
+  ARM_VCVTTHD /* 2313 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${p}.f32.f16	$Sd, $Sm */
+  ARM_VCVTTHS /* 2314 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtt${p}.f16.f32	$Sd, $Sm */
+  ARM_VCVTTSH /* 2315 */, ARM_INS_VCVTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.f32	$Vd, $Vm */
+  ARM_VCVTf2h /* 2316 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f32	$Vd, $Vm */
+  ARM_VCVTf2sd /* 2317 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f32	$Vd, $Vm */
+  ARM_VCVTf2sq /* 2318 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f32	$Vd, $Vm */
+  ARM_VCVTf2ud /* 2319 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f32	$Vd, $Vm */
+  ARM_VCVTf2uq /* 2320 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f32	$Vd, $Vm, $SIMM */
+  ARM_VCVTf2xsd /* 2321 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f32	$Vd, $Vm, $SIMM */
+  ARM_VCVTf2xsq /* 2322 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f32	$Vd, $Vm, $SIMM */
+  ARM_VCVTf2xud /* 2323 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f32	$Vd, $Vm, $SIMM */
+  ARM_VCVTf2xuq /* 2324 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.f16	$Vd, $Vm */
+  ARM_VCVTh2f /* 2325 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f16	$Vd, $Vm */
+  ARM_VCVTh2sd /* 2326 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f16	$Vd, $Vm */
+  ARM_VCVTh2sq /* 2327 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f16	$Vd, $Vm */
+  ARM_VCVTh2ud /* 2328 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f16	$Vd, $Vm */
+  ARM_VCVTh2uq /* 2329 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f16	$Vd, $Vm, $SIMM */
+  ARM_VCVTh2xsd /* 2330 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f16	$Vd, $Vm, $SIMM */
+  ARM_VCVTh2xsq /* 2331 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f16	$Vd, $Vm, $SIMM */
+  ARM_VCVTh2xud /* 2332 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f16	$Vd, $Vm, $SIMM */
+  ARM_VCVTh2xuq /* 2333 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s32	$Vd, $Vm */
+  ARM_VCVTs2fd /* 2334 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s32	$Vd, $Vm */
+  ARM_VCVTs2fq /* 2335 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s16	$Vd, $Vm */
+  ARM_VCVTs2hd /* 2336 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s16	$Vd, $Vm */
+  ARM_VCVTs2hq /* 2337 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u32	$Vd, $Vm */
+  ARM_VCVTu2fd /* 2338 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u32	$Vd, $Vm */
+  ARM_VCVTu2fq /* 2339 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u16	$Vd, $Vm */
+  ARM_VCVTu2hd /* 2340 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u16	$Vd, $Vm */
+  ARM_VCVTu2hq /* 2341 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s32	$Vd, $Vm, $SIMM */
+  ARM_VCVTxs2fd /* 2342 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s32	$Vd, $Vm, $SIMM */
+  ARM_VCVTxs2fq /* 2343 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s16	$Vd, $Vm, $SIMM */
+  ARM_VCVTxs2hd /* 2344 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s16	$Vd, $Vm, $SIMM */
+  ARM_VCVTxs2hq /* 2345 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u32	$Vd, $Vm, $SIMM */
+  ARM_VCVTxu2fd /* 2346 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u32	$Vd, $Vm, $SIMM */
+  ARM_VCVTxu2fq /* 2347 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u16	$Vd, $Vm, $SIMM */
+  ARM_VCVTxu2hd /* 2348 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u16	$Vd, $Vm, $SIMM */
+  ARM_VCVTxu2hq /* 2349 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdiv${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VDIVD /* 2350 */, ARM_INS_VDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdiv${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VDIVH /* 2351 */, ARM_INS_VDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdiv${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VDIVS /* 2352 */, ARM_INS_VDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.16	$V, $R */
+  ARM_VDUP16d /* 2353 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.16	$V, $R */
+  ARM_VDUP16q /* 2354 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.32	$V, $R */
+  ARM_VDUP32d /* 2355 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.32	$V, $R */
+  ARM_VDUP32q /* 2356 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.8	$V, $R */
+  ARM_VDUP8d /* 2357 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.8	$V, $R */
+  ARM_VDUP8q /* 2358 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.16	$Vd, $Vm$lane */
+  ARM_VDUPLN16d /* 2359 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.16	$Vd, $Vm$lane */
+  ARM_VDUPLN16q /* 2360 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.32	$Vd, $Vm$lane */
+  ARM_VDUPLN32d /* 2361 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.32	$Vd, $Vm$lane */
+  ARM_VDUPLN32q /* 2362 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.8	$Vd, $Vm$lane */
+  ARM_VDUPLN8d /* 2363 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vdup${p}.8	$Vd, $Vm$lane */
+  ARM_VDUPLN8q /* 2364 */, ARM_INS_VDUP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* veor${p}	$Vd, $Vn, $Vm */
+  ARM_VEORd /* 2365 */, ARM_INS_VEOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* veor${p}	$Vd, $Vn, $Vm */
+  ARM_VEORq /* 2366 */, ARM_INS_VEOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.16	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTd16 /* 2367 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.32	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTd32 /* 2368 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.8	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTd8 /* 2369 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.16	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTq16 /* 2370 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.32	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTq32 /* 2371 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.64	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTq64 /* 2372 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vext${p}.8	$Vd, $Vn, $Vm, $index */
+  ARM_VEXTq8 /* 2373 */, ARM_INS_VEXT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VFMAD /* 2374 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VFMAH /* 2375 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmal.f16	$Vd, $Vn, $Vm */
+  ARM_VFMALD /* 2376 */, ARM_INS_VFMAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmal.f16	$Vd, $Vn, $Vm$idx */
+  ARM_VFMALDI /* 2377 */, ARM_INS_VFMAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmal.f16	$Vd, $Vn, $Vm */
+  ARM_VFMALQ /* 2378 */, ARM_INS_VFMAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmal.f16	$Vd, $Vn, $Vm$idx */
+  ARM_VFMALQI /* 2379 */, ARM_INS_VFMAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VFMAS /* 2380 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VFMAfd /* 2381 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VFMAfq /* 2382 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VFMAhd /* 2383 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfma${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VFMAhq /* 2384 */, ARM_INS_VFMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VFMSD /* 2385 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VFMSH /* 2386 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmsl.f16	$Vd, $Vn, $Vm */
+  ARM_VFMSLD /* 2387 */, ARM_INS_VFMSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmsl.f16	$Vd, $Vn, $Vm$idx */
+  ARM_VFMSLDI /* 2388 */, ARM_INS_VFMSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmsl.f16	$Vd, $Vn, $Vm */
+  ARM_VFMSLQ /* 2389 */, ARM_INS_VFMSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfmsl.f16	$Vd, $Vn, $Vm$idx */
+  ARM_VFMSLQI /* 2390 */, ARM_INS_VFMSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFP16FML, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VFMSS /* 2391 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VFMSfd /* 2392 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VFMSfq /* 2393 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VFMShd /* 2394 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfms${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VFMShq /* 2395 */, ARM_INS_VFMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfnma${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VFNMAD /* 2396 */, ARM_INS_VFNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfnma${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VFNMAH /* 2397 */, ARM_INS_VFNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfnma${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VFNMAS /* 2398 */, ARM_INS_VFNMA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfnms${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VFNMSD /* 2399 */, ARM_INS_VFNMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfnms${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VFNMSH /* 2400 */, ARM_INS_VFNMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vfnms${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VFNMSS /* 2401 */, ARM_INS_VFNMS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP4, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f64	$Dd, $Dn, $Dm */
+  ARM_VFP_VMAXNMD /* 2402 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f16	$Sd, $Sn, $Sm */
+  ARM_VFP_VMAXNMH /* 2403 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmaxnm.f32	$Sd, $Sn, $Sm */
+  ARM_VFP_VMAXNMS /* 2404 */, ARM_INS_VMAXNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f64	$Dd, $Dn, $Dm */
+  ARM_VFP_VMINNMD /* 2405 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f16	$Sd, $Sn, $Sm */
+  ARM_VFP_VMINNMH /* 2406 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vminnm.f32	$Sd, $Sn, $Sm */
+  ARM_VFP_VMINNMS /* 2407 */, ARM_INS_VMINNM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.32	$R, $V$lane */
+  ARM_VGETLNi32 /* 2408 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.s16	$R, $V$lane */
+  ARM_VGETLNs16 /* 2409 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.s8	$R, $V$lane */
+  ARM_VGETLNs8 /* 2410 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.u16	$R, $V$lane */
+  ARM_VGETLNu16 /* 2411 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.u8	$R, $V$lane */
+  ARM_VGETLNu8 /* 2412 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VHADDsv16i8 /* 2413 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VHADDsv2i32 /* 2414 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VHADDsv4i16 /* 2415 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VHADDsv4i32 /* 2416 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VHADDsv8i16 /* 2417 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VHADDsv8i8 /* 2418 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VHADDuv16i8 /* 2419 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VHADDuv2i32 /* 2420 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VHADDuv4i16 /* 2421 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VHADDuv4i32 /* 2422 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VHADDuv8i16 /* 2423 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhadd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VHADDuv8i8 /* 2424 */, ARM_INS_VHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VHSUBsv16i8 /* 2425 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VHSUBsv2i32 /* 2426 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VHSUBsv4i16 /* 2427 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VHSUBsv4i32 /* 2428 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VHSUBsv8i16 /* 2429 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VHSUBsv8i8 /* 2430 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VHSUBuv16i8 /* 2431 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VHSUBuv2i32 /* 2432 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VHSUBuv4i16 /* 2433 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VHSUBuv4i32 /* 2434 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VHSUBuv8i16 /* 2435 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vhsub${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VHSUBuv8i8 /* 2436 */, ARM_INS_VHSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vins.f16	$Sd, $Sm */
+  ARM_VINSH /* 2437 */, ARM_INS_VINS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vjcvt${p}.s32.f64	$Sd, $Dm */
+  ARM_VJCVT /* 2438 */, ARM_INS_VJCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasV8_3a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn */
+  ARM_VLD1DUPd16 /* 2439 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn! */
+  ARM_VLD1DUPd16wb_fixed /* 2440 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD1DUPd16wb_register /* 2441 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn */
+  ARM_VLD1DUPd32 /* 2442 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn! */
+  ARM_VLD1DUPd32wb_fixed /* 2443 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD1DUPd32wb_register /* 2444 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn */
+  ARM_VLD1DUPd8 /* 2445 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn! */
+  ARM_VLD1DUPd8wb_fixed /* 2446 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD1DUPd8wb_register /* 2447 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn */
+  ARM_VLD1DUPq16 /* 2448 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn! */
+  ARM_VLD1DUPq16wb_fixed /* 2449 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD1DUPq16wb_register /* 2450 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn */
+  ARM_VLD1DUPq32 /* 2451 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn! */
+  ARM_VLD1DUPq32wb_fixed /* 2452 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD1DUPq32wb_register /* 2453 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn */
+  ARM_VLD1DUPq8 /* 2454 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn! */
+  ARM_VLD1DUPq8wb_fixed /* 2455 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD1DUPq8wb_register /* 2456 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	\{$Vd[$lane]\}, $Rn */
+  ARM_VLD1LNd16 /* 2457 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	\{$Vd[$lane]\}, $Rn$Rm */
+  ARM_VLD1LNd16_UPD /* 2458 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	\{$Vd[$lane]\}, $Rn */
+  ARM_VLD1LNd32 /* 2459 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	\{$Vd[$lane]\}, $Rn$Rm */
+  ARM_VLD1LNd32_UPD /* 2460 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	\{$Vd[$lane]\}, $Rn */
+  ARM_VLD1LNd8 /* 2461 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	\{$Vd[$lane]\}, $Rn$Rm */
+  ARM_VLD1LNd8_UPD /* 2462 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1LNq16Pseudo /* 2463 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1LNq16Pseudo_UPD /* 2464 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1LNq32Pseudo /* 2465 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1LNq32Pseudo_UPD /* 2466 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1LNq8Pseudo /* 2467 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1LNq8Pseudo_UPD /* 2468 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn */
+  ARM_VLD1d16 /* 2469 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn */
+  ARM_VLD1d16Q /* 2470 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d16QPseudo /* 2471 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d16QPseudoWB_fixed /* 2472 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d16QPseudoWB_register /* 2473 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn! */
+  ARM_VLD1d16Qwb_fixed /* 2474 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD1d16Qwb_register /* 2475 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn */
+  ARM_VLD1d16T /* 2476 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d16TPseudo /* 2477 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d16TPseudoWB_fixed /* 2478 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d16TPseudoWB_register /* 2479 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn! */
+  ARM_VLD1d16Twb_fixed /* 2480 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD1d16Twb_register /* 2481 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn! */
+  ARM_VLD1d16wb_fixed /* 2482 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD1d16wb_register /* 2483 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn */
+  ARM_VLD1d32 /* 2484 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn */
+  ARM_VLD1d32Q /* 2485 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d32QPseudo /* 2486 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d32QPseudoWB_fixed /* 2487 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d32QPseudoWB_register /* 2488 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn! */
+  ARM_VLD1d32Qwb_fixed /* 2489 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD1d32Qwb_register /* 2490 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn */
+  ARM_VLD1d32T /* 2491 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d32TPseudo /* 2492 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d32TPseudoWB_fixed /* 2493 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d32TPseudoWB_register /* 2494 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn! */
+  ARM_VLD1d32Twb_fixed /* 2495 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD1d32Twb_register /* 2496 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn! */
+  ARM_VLD1d32wb_fixed /* 2497 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD1d32wb_register /* 2498 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn */
+  ARM_VLD1d64 /* 2499 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn */
+  ARM_VLD1d64Q /* 2500 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d64QPseudo /* 2501 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d64QPseudoWB_fixed /* 2502 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d64QPseudoWB_register /* 2503 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn! */
+  ARM_VLD1d64Qwb_fixed /* 2504 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VLD1d64Qwb_register /* 2505 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn */
+  ARM_VLD1d64T /* 2506 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d64TPseudo /* 2507 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d64TPseudoWB_fixed /* 2508 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d64TPseudoWB_register /* 2509 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn! */
+  ARM_VLD1d64Twb_fixed /* 2510 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VLD1d64Twb_register /* 2511 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn! */
+  ARM_VLD1d64wb_fixed /* 2512 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VLD1d64wb_register /* 2513 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn */
+  ARM_VLD1d8 /* 2514 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn */
+  ARM_VLD1d8Q /* 2515 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d8QPseudo /* 2516 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d8QPseudoWB_fixed /* 2517 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d8QPseudoWB_register /* 2518 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn! */
+  ARM_VLD1d8Qwb_fixed /* 2519 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD1d8Qwb_register /* 2520 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn */
+  ARM_VLD1d8T /* 2521 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d8TPseudo /* 2522 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d8TPseudoWB_fixed /* 2523 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1d8TPseudoWB_register /* 2524 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn! */
+  ARM_VLD1d8Twb_fixed /* 2525 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD1d8Twb_register /* 2526 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn! */
+  ARM_VLD1d8wb_fixed /* 2527 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD1d8wb_register /* 2528 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn */
+  ARM_VLD1q16 /* 2529 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q16HighQPseudo /* 2530 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q16HighQPseudo_UPD /* 2531 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q16HighTPseudo /* 2532 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q16HighTPseudo_UPD /* 2533 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q16LowQPseudo_UPD /* 2534 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q16LowTPseudo_UPD /* 2535 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn! */
+  ARM_VLD1q16wb_fixed /* 2536 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD1q16wb_register /* 2537 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn */
+  ARM_VLD1q32 /* 2538 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q32HighQPseudo /* 2539 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q32HighQPseudo_UPD /* 2540 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q32HighTPseudo /* 2541 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q32HighTPseudo_UPD /* 2542 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q32LowQPseudo_UPD /* 2543 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q32LowTPseudo_UPD /* 2544 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn! */
+  ARM_VLD1q32wb_fixed /* 2545 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD1q32wb_register /* 2546 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn */
+  ARM_VLD1q64 /* 2547 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q64HighQPseudo /* 2548 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q64HighQPseudo_UPD /* 2549 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q64HighTPseudo /* 2550 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q64HighTPseudo_UPD /* 2551 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q64LowQPseudo_UPD /* 2552 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q64LowTPseudo_UPD /* 2553 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn! */
+  ARM_VLD1q64wb_fixed /* 2554 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VLD1q64wb_register /* 2555 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn */
+  ARM_VLD1q8 /* 2556 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q8HighQPseudo /* 2557 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q8HighQPseudo_UPD /* 2558 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q8HighTPseudo /* 2559 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q8HighTPseudo_UPD /* 2560 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q8LowQPseudo_UPD /* 2561 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD1q8LowTPseudo_UPD /* 2562 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn! */
+  ARM_VLD1q8wb_fixed /* 2563 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD1q8wb_register /* 2564 */, ARM_INS_VLD1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn */
+  ARM_VLD2DUPd16 /* 2565 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn! */
+  ARM_VLD2DUPd16wb_fixed /* 2566 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD2DUPd16wb_register /* 2567 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn */
+  ARM_VLD2DUPd16x2 /* 2568 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn! */
+  ARM_VLD2DUPd16x2wb_fixed /* 2569 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD2DUPd16x2wb_register /* 2570 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn */
+  ARM_VLD2DUPd32 /* 2571 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn! */
+  ARM_VLD2DUPd32wb_fixed /* 2572 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD2DUPd32wb_register /* 2573 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn */
+  ARM_VLD2DUPd32x2 /* 2574 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn! */
+  ARM_VLD2DUPd32x2wb_fixed /* 2575 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD2DUPd32x2wb_register /* 2576 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn */
+  ARM_VLD2DUPd8 /* 2577 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn! */
+  ARM_VLD2DUPd8wb_fixed /* 2578 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD2DUPd8wb_register /* 2579 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn */
+  ARM_VLD2DUPd8x2 /* 2580 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn! */
+  ARM_VLD2DUPd8x2wb_fixed /* 2581 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD2DUPd8x2wb_register /* 2582 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq16EvenPseudo /* 2583 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq16OddPseudo /* 2584 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq16OddPseudoWB_fixed /* 2585 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq16OddPseudoWB_register /* 2586 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq32EvenPseudo /* 2587 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq32OddPseudo /* 2588 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq32OddPseudoWB_fixed /* 2589 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq32OddPseudoWB_register /* 2590 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq8EvenPseudo /* 2591 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq8OddPseudo /* 2592 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq8OddPseudoWB_fixed /* 2593 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2DUPq8OddPseudoWB_register /* 2594 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+  ARM_VLD2LNd16 /* 2595 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNd16Pseudo /* 2596 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNd16Pseudo_UPD /* 2597 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+  ARM_VLD2LNd16_UPD /* 2598 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+  ARM_VLD2LNd32 /* 2599 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNd32Pseudo /* 2600 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNd32Pseudo_UPD /* 2601 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+  ARM_VLD2LNd32_UPD /* 2602 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+  ARM_VLD2LNd8 /* 2603 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNd8Pseudo /* 2604 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNd8Pseudo_UPD /* 2605 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+  ARM_VLD2LNd8_UPD /* 2606 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+  ARM_VLD2LNq16 /* 2607 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNq16Pseudo /* 2608 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNq16Pseudo_UPD /* 2609 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+  ARM_VLD2LNq16_UPD /* 2610 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+  ARM_VLD2LNq32 /* 2611 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNq32Pseudo /* 2612 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2LNq32Pseudo_UPD /* 2613 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+  ARM_VLD2LNq32_UPD /* 2614 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn */
+  ARM_VLD2b16 /* 2615 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn! */
+  ARM_VLD2b16wb_fixed /* 2616 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD2b16wb_register /* 2617 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn */
+  ARM_VLD2b32 /* 2618 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn! */
+  ARM_VLD2b32wb_fixed /* 2619 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD2b32wb_register /* 2620 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn */
+  ARM_VLD2b8 /* 2621 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn! */
+  ARM_VLD2b8wb_fixed /* 2622 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD2b8wb_register /* 2623 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn */
+  ARM_VLD2d16 /* 2624 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn! */
+  ARM_VLD2d16wb_fixed /* 2625 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD2d16wb_register /* 2626 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn */
+  ARM_VLD2d32 /* 2627 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn! */
+  ARM_VLD2d32wb_fixed /* 2628 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD2d32wb_register /* 2629 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn */
+  ARM_VLD2d8 /* 2630 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn! */
+  ARM_VLD2d8wb_fixed /* 2631 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD2d8wb_register /* 2632 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn */
+  ARM_VLD2q16 /* 2633 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q16Pseudo /* 2634 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q16PseudoWB_fixed /* 2635 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q16PseudoWB_register /* 2636 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn! */
+  ARM_VLD2q16wb_fixed /* 2637 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VLD2q16wb_register /* 2638 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn */
+  ARM_VLD2q32 /* 2639 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q32Pseudo /* 2640 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q32PseudoWB_fixed /* 2641 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q32PseudoWB_register /* 2642 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn! */
+  ARM_VLD2q32wb_fixed /* 2643 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VLD2q32wb_register /* 2644 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn */
+  ARM_VLD2q8 /* 2645 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q8Pseudo /* 2646 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q8PseudoWB_fixed /* 2647 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD2q8PseudoWB_register /* 2648 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn! */
+  ARM_VLD2q8wb_fixed /* 2649 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VLD2q8wb_register /* 2650 */, ARM_INS_VLD2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+  ARM_VLD3DUPd16 /* 2651 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPd16Pseudo /* 2652 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPd16Pseudo_UPD /* 2653 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+  ARM_VLD3DUPd16_UPD /* 2654 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+  ARM_VLD3DUPd32 /* 2655 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPd32Pseudo /* 2656 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPd32Pseudo_UPD /* 2657 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+  ARM_VLD3DUPd32_UPD /* 2658 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+  ARM_VLD3DUPd8 /* 2659 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPd8Pseudo /* 2660 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPd8Pseudo_UPD /* 2661 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+  ARM_VLD3DUPd8_UPD /* 2662 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+  ARM_VLD3DUPq16 /* 2663 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq16EvenPseudo /* 2664 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq16OddPseudo /* 2665 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq16OddPseudo_UPD /* 2666 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+  ARM_VLD3DUPq16_UPD /* 2667 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+  ARM_VLD3DUPq32 /* 2668 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq32EvenPseudo /* 2669 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq32OddPseudo /* 2670 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq32OddPseudo_UPD /* 2671 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+  ARM_VLD3DUPq32_UPD /* 2672 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+  ARM_VLD3DUPq8 /* 2673 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq8EvenPseudo /* 2674 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq8OddPseudo /* 2675 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3DUPq8OddPseudo_UPD /* 2676 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+  ARM_VLD3DUPq8_UPD /* 2677 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+  ARM_VLD3LNd16 /* 2678 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNd16Pseudo /* 2679 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNd16Pseudo_UPD /* 2680 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+  ARM_VLD3LNd16_UPD /* 2681 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+  ARM_VLD3LNd32 /* 2682 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNd32Pseudo /* 2683 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNd32Pseudo_UPD /* 2684 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+  ARM_VLD3LNd32_UPD /* 2685 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+  ARM_VLD3LNd8 /* 2686 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNd8Pseudo /* 2687 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNd8Pseudo_UPD /* 2688 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+  ARM_VLD3LNd8_UPD /* 2689 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+  ARM_VLD3LNq16 /* 2690 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNq16Pseudo /* 2691 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNq16Pseudo_UPD /* 2692 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+  ARM_VLD3LNq16_UPD /* 2693 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+  ARM_VLD3LNq32 /* 2694 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNq32Pseudo /* 2695 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3LNq32Pseudo_UPD /* 2696 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+  ARM_VLD3LNq32_UPD /* 2697 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn */
+  ARM_VLD3d16 /* 2698 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3d16Pseudo /* 2699 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3d16Pseudo_UPD /* 2700 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+  ARM_VLD3d16_UPD /* 2701 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn */
+  ARM_VLD3d32 /* 2702 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3d32Pseudo /* 2703 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3d32Pseudo_UPD /* 2704 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+  ARM_VLD3d32_UPD /* 2705 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn */
+  ARM_VLD3d8 /* 2706 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3d8Pseudo /* 2707 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3d8Pseudo_UPD /* 2708 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+  ARM_VLD3d8_UPD /* 2709 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn */
+  ARM_VLD3q16 /* 2710 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q16Pseudo_UPD /* 2711 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+  ARM_VLD3q16_UPD /* 2712 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q16oddPseudo /* 2713 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q16oddPseudo_UPD /* 2714 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn */
+  ARM_VLD3q32 /* 2715 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q32Pseudo_UPD /* 2716 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+  ARM_VLD3q32_UPD /* 2717 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q32oddPseudo /* 2718 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q32oddPseudo_UPD /* 2719 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn */
+  ARM_VLD3q8 /* 2720 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q8Pseudo_UPD /* 2721 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+  ARM_VLD3q8_UPD /* 2722 */, ARM_INS_VLD3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q8oddPseudo /* 2723 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD3q8oddPseudo_UPD /* 2724 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+  ARM_VLD4DUPd16 /* 2725 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPd16Pseudo /* 2726 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPd16Pseudo_UPD /* 2727 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+  ARM_VLD4DUPd16_UPD /* 2728 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+  ARM_VLD4DUPd32 /* 2729 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPd32Pseudo /* 2730 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPd32Pseudo_UPD /* 2731 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+  ARM_VLD4DUPd32_UPD /* 2732 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+  ARM_VLD4DUPd8 /* 2733 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPd8Pseudo /* 2734 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPd8Pseudo_UPD /* 2735 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+  ARM_VLD4DUPd8_UPD /* 2736 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+  ARM_VLD4DUPq16 /* 2737 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq16EvenPseudo /* 2738 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq16OddPseudo /* 2739 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq16OddPseudo_UPD /* 2740 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+  ARM_VLD4DUPq16_UPD /* 2741 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+  ARM_VLD4DUPq32 /* 2742 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq32EvenPseudo /* 2743 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq32OddPseudo /* 2744 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq32OddPseudo_UPD /* 2745 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+  ARM_VLD4DUPq32_UPD /* 2746 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+  ARM_VLD4DUPq8 /* 2747 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq8EvenPseudo /* 2748 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq8OddPseudo /* 2749 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4DUPq8OddPseudo_UPD /* 2750 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+  ARM_VLD4DUPq8_UPD /* 2751 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+  ARM_VLD4LNd16 /* 2752 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNd16Pseudo /* 2753 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNd16Pseudo_UPD /* 2754 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+  ARM_VLD4LNd16_UPD /* 2755 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+  ARM_VLD4LNd32 /* 2756 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNd32Pseudo /* 2757 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNd32Pseudo_UPD /* 2758 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+  ARM_VLD4LNd32_UPD /* 2759 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+  ARM_VLD4LNd8 /* 2760 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNd8Pseudo /* 2761 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNd8Pseudo_UPD /* 2762 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+  ARM_VLD4LNd8_UPD /* 2763 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+  ARM_VLD4LNq16 /* 2764 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNq16Pseudo /* 2765 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNq16Pseudo_UPD /* 2766 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+  ARM_VLD4LNq16_UPD /* 2767 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+  ARM_VLD4LNq32 /* 2768 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNq32Pseudo /* 2769 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4LNq32Pseudo_UPD /* 2770 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+  ARM_VLD4LNq32_UPD /* 2771 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+  ARM_VLD4d16 /* 2772 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4d16Pseudo /* 2773 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4d16Pseudo_UPD /* 2774 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+  ARM_VLD4d16_UPD /* 2775 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+  ARM_VLD4d32 /* 2776 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4d32Pseudo /* 2777 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4d32Pseudo_UPD /* 2778 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+  ARM_VLD4d32_UPD /* 2779 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+  ARM_VLD4d8 /* 2780 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4d8Pseudo /* 2781 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4d8Pseudo_UPD /* 2782 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+  ARM_VLD4d8_UPD /* 2783 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+  ARM_VLD4q16 /* 2784 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q16Pseudo_UPD /* 2785 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+  ARM_VLD4q16_UPD /* 2786 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q16oddPseudo /* 2787 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q16oddPseudo_UPD /* 2788 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+  ARM_VLD4q32 /* 2789 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q32Pseudo_UPD /* 2790 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+  ARM_VLD4q32_UPD /* 2791 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q32oddPseudo /* 2792 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q32oddPseudo_UPD /* 2793 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+  ARM_VLD4q8 /* 2794 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q8Pseudo_UPD /* 2795 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+  ARM_VLD4q8_UPD /* 2796 */, ARM_INS_VLD4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q8oddPseudo /* 2797 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLD4q8oddPseudo_UPD /* 2798 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vldmdb${p}	$Rn!, $regs */
+  ARM_VLDMDDB_UPD /* 2799 */, ARM_INS_VLDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldmia${p}	$Rn, $regs */
+  ARM_VLDMDIA /* 2800 */, ARM_INS_VLDMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldmia${p}	$Rn!, $regs */
+  ARM_VLDMDIA_UPD /* 2801 */, ARM_INS_VLDMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VLDMQIA /* 2802 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vldmdb${p}	$Rn!, $regs */
+  ARM_VLDMSDB_UPD /* 2803 */, ARM_INS_VLDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldmia${p}	$Rn, $regs */
+  ARM_VLDMSIA /* 2804 */, ARM_INS_VLDMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldmia${p}	$Rn!, $regs */
+  ARM_VLDMSIA_UPD /* 2805 */, ARM_INS_VLDMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	$Dd, $addr */
+  ARM_VLDRD /* 2806 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}.16	$Sd, $addr */
+  ARM_VLDRH /* 2807 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	$Sd, $addr */
+  ARM_VLDRS /* 2808 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpcxtns, $addr */
+  ARM_VLDR_FPCXTNS_off /* 2809 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpcxtns, $Rn$addr */
+  ARM_VLDR_FPCXTNS_post /* 2810 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpcxtns, $addr! */
+  ARM_VLDR_FPCXTNS_pre /* 2811 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpcxts, $addr */
+  ARM_VLDR_FPCXTS_off /* 2812 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpcxts, $Rn$addr */
+  ARM_VLDR_FPCXTS_post /* 2813 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpcxts, $addr! */
+  ARM_VLDR_FPCXTS_pre /* 2814 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpscr_nzcvqc, $addr */
+  ARM_VLDR_FPSCR_NZCVQC_off /* 2815 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpscr_nzcvqc, $Rn$addr */
+  ARM_VLDR_FPSCR_NZCVQC_post /* 2816 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpscr_nzcvqc, $addr! */
+  ARM_VLDR_FPSCR_NZCVQC_pre /* 2817 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpscr, $addr */
+  ARM_VLDR_FPSCR_off /* 2818 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpscr, $Rn$addr */
+  ARM_VLDR_FPSCR_post /* 2819 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	fpscr, $addr! */
+  ARM_VLDR_FPSCR_pre /* 2820 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	p0, $addr */
+  ARM_VLDR_P0_off /* 2821 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	p0, $Rn$addr */
+  ARM_VLDR_P0_post /* 2822 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	p0, $addr! */
+  ARM_VLDR_P0_pre /* 2823 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	vpr, $addr */
+  ARM_VLDR_VPR_off /* 2824 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	vpr, $Rn$addr */
+  ARM_VLDR_VPR_post /* 2825 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vldr${p}	vpr, $addr! */
+  ARM_VLDR_VPR_pre /* 2826 */, ARM_INS_VLDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vlldm${p}	$Rn */
+  ARM_VLLDM /* 2827 */, ARM_INS_VLLDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_Q0, ARM_REG_Q1, ARM_REG_Q2, ARM_REG_Q3, ARM_REG_Q4, ARM_REG_Q5, ARM_REG_Q6, ARM_REG_Q7, ARM_REG_VPR, ARM_REG_FPSCR, ARM_REG_FPSCR_NZCV, 0 }, { ARM_FEATURE_HasV8MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vlstm${p}	$Rn */
+  ARM_VLSTM /* 2828 */, ARM_INS_VLSTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMAXfd /* 2829 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMAXfq /* 2830 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMAXhd /* 2831 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMAXhq /* 2832 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMAXsv16i8 /* 2833 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMAXsv2i32 /* 2834 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMAXsv4i16 /* 2835 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMAXsv4i32 /* 2836 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMAXsv8i16 /* 2837 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMAXsv8i8 /* 2838 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMAXuv16i8 /* 2839 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMAXuv2i32 /* 2840 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMAXuv4i16 /* 2841 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMAXuv4i32 /* 2842 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMAXuv8i16 /* 2843 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmax${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMAXuv8i8 /* 2844 */, ARM_INS_VMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMINfd /* 2845 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMINfq /* 2846 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMINhd /* 2847 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMINhq /* 2848 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMINsv16i8 /* 2849 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMINsv2i32 /* 2850 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMINsv4i16 /* 2851 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMINsv4i32 /* 2852 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMINsv8i16 /* 2853 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMINsv8i8 /* 2854 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMINuv16i8 /* 2855 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMINuv2i32 /* 2856 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMINuv4i16 /* 2857 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMINuv4i32 /* 2858 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMINuv8i16 /* 2859 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmin${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMINuv8i8 /* 2860 */, ARM_INS_VMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VMLAD /* 2861 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VMLAH /* 2862 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLALslsv2i32 /* 2863 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLALslsv4i16 /* 2864 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.u32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLALsluv2i32 /* 2865 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.u16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLALsluv4i16 /* 2866 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMLALsv2i64 /* 2867 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMLALsv4i32 /* 2868 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMLALsv8i16 /* 2869 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMLALuv2i64 /* 2870 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMLALuv4i32 /* 2871 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlal${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMLALuv8i16 /* 2872 */, ARM_INS_VMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VMLAS /* 2873 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMLAfd /* 2874 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMLAfq /* 2875 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMLAhd /* 2876 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMLAhq /* 2877 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslfd /* 2878 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslfq /* 2879 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslhd /* 2880 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.f16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslhq /* 2881 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslv2i32 /* 2882 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslv4i16 /* 2883 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslv4i32 /* 2884 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLAslv8i16 /* 2885 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VMLAv16i8 /* 2886 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VMLAv2i32 /* 2887 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VMLAv4i16 /* 2888 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VMLAv4i32 /* 2889 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VMLAv8i16 /* 2890 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmla${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VMLAv8i8 /* 2891 */, ARM_INS_VMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VMLSD /* 2892 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VMLSH /* 2893 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSLslsv2i32 /* 2894 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSLslsv4i16 /* 2895 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.u32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSLsluv2i32 /* 2896 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.u16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSLsluv4i16 /* 2897 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMLSLsv2i64 /* 2898 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMLSLsv4i32 /* 2899 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMLSLsv8i16 /* 2900 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMLSLuv2i64 /* 2901 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMLSLuv4i32 /* 2902 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmlsl${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMLSLuv8i16 /* 2903 */, ARM_INS_VMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VMLSS /* 2904 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMLSfd /* 2905 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMLSfq /* 2906 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMLShd /* 2907 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMLShq /* 2908 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslfd /* 2909 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslfq /* 2910 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslhd /* 2911 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.f16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslhq /* 2912 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslv2i32 /* 2913 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslv4i16 /* 2914 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i32	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslv4i32 /* 2915 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i16	$Vd, $Vn, $Vm$lane */
+  ARM_VMLSslv8i16 /* 2916 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VMLSv16i8 /* 2917 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VMLSv2i32 /* 2918 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VMLSv4i16 /* 2919 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VMLSv4i32 /* 2920 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VMLSv8i16 /* 2921 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmls${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VMLSv8i8 /* 2922 */, ARM_INS_VMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmmla.bf16	$Vd, $Vn, $Vm */
+  ARM_VMMLA /* 2923 */, ARM_INS_VMMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasBF16, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f64	$Dd, $Dm */
+  ARM_VMOVD /* 2924 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs64, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Dm, $Rt, $Rt2 */
+  ARM_VMOVDRR /* 2925 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovx.f16	$Sd, $Sm */
+  ARM_VMOVH /* 2926 */, ARM_INS_VMOVX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f16	$Sn, $Rt */
+  ARM_VMOVHR /* 2927 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovl${p}.s32	$Vd, $Vm */
+  ARM_VMOVLsv2i64 /* 2928 */, ARM_INS_VMOVL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovl${p}.s16	$Vd, $Vm */
+  ARM_VMOVLsv4i32 /* 2929 */, ARM_INS_VMOVL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovl${p}.s8	$Vd, $Vm */
+  ARM_VMOVLsv8i16 /* 2930 */, ARM_INS_VMOVL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovl${p}.u32	$Vd, $Vm */
+  ARM_VMOVLuv2i64 /* 2931 */, ARM_INS_VMOVL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovl${p}.u16	$Vd, $Vm */
+  ARM_VMOVLuv4i32 /* 2932 */, ARM_INS_VMOVL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovl${p}.u8	$Vd, $Vm */
+  ARM_VMOVLuv8i16 /* 2933 */, ARM_INS_VMOVL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovn${p}.i64	$Vd, $Vm */
+  ARM_VMOVNv2i32 /* 2934 */, ARM_INS_VMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovn${p}.i32	$Vd, $Vm */
+  ARM_VMOVNv4i16 /* 2935 */, ARM_INS_VMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmovn${p}.i16	$Vd, $Vm */
+  ARM_VMOVNv8i8 /* 2936 */, ARM_INS_VMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f16	$Rt, $Sn */
+  ARM_VMOVRH /* 2937 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Rt, $Rt2, $Dm */
+  ARM_VMOVRRD /* 2938 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Rt, $Rt2, $src1, $src2 */
+  ARM_VMOVRRS /* 2939 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Rt, $Sn */
+  ARM_VMOVRS /* 2940 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f32	$Sd, $Sm */
+  ARM_VMOVS /* 2941 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$Sn, $Rt */
+  ARM_VMOVSR /* 2942 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}	$dst1, $dst2, $src1, $src2 */
+  ARM_VMOVSRR /* 2943 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i8	$Vd, $SIMM */
+  ARM_VMOVv16i8 /* 2944 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i64	$Vd, $SIMM */
+  ARM_VMOVv1i64 /* 2945 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f32	$Vd, $SIMM */
+  ARM_VMOVv2f32 /* 2946 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i32	$Vd, $SIMM */
+  ARM_VMOVv2i32 /* 2947 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i64	$Vd, $SIMM */
+  ARM_VMOVv2i64 /* 2948 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.f32	$Vd, $SIMM */
+  ARM_VMOVv4f32 /* 2949 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i16	$Vd, $SIMM */
+  ARM_VMOVv4i16 /* 2950 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i32	$Vd, $SIMM */
+  ARM_VMOVv4i32 /* 2951 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i16	$Vd, $SIMM */
+  ARM_VMOVv8i16 /* 2952 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.i8	$Vd, $SIMM */
+  ARM_VMOVv8i8 /* 2953 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpscr */
+  ARM_VMRS /* 2954 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpcxtns */
+  ARM_VMRS_FPCXTNS /* 2955 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpcxts */
+  ARM_VMRS_FPCXTS /* 2956 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpexc */
+  ARM_VMRS_FPEXC /* 2957 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpinst */
+  ARM_VMRS_FPINST /* 2958 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpinst2 */
+  ARM_VMRS_FPINST2 /* 2959 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpscr_nzcvqc */
+  ARM_VMRS_FPSCR_NZCVQC /* 2960 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, fpsid */
+  ARM_VMRS_FPSID /* 2961 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, mvfr0 */
+  ARM_VMRS_MVFR0 /* 2962 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, mvfr1 */
+  ARM_VMRS_MVFR1 /* 2963 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, mvfr2 */
+  ARM_VMRS_MVFR2 /* 2964 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, p0 */
+  ARM_VMRS_P0 /* 2965 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmrs${p}	$Rt, vpr */
+  ARM_VMRS_VPR /* 2966 */, ARM_INS_VMRS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpscr, $Rt */
+  ARM_VMSR /* 2967 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpcxtns, $Rt */
+  ARM_VMSR_FPCXTNS /* 2968 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpcxts, $Rt */
+  ARM_VMSR_FPCXTS /* 2969 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpexc, $Rt */
+  ARM_VMSR_FPEXC /* 2970 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpinst, $Rt */
+  ARM_VMSR_FPINST /* 2971 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpinst2, $Rt */
+  ARM_VMSR_FPINST2 /* 2972 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpscr_nzcvqc, $Rt */
+  ARM_VMSR_FPSCR_NZCVQC /* 2973 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	fpsid, $Rt */
+  ARM_VMSR_FPSID /* 2974 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	p0, $Rt */
+  ARM_VMSR_P0 /* 2975 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmsr${p}	vpr, $Rt */
+  ARM_VMSR_VPR /* 2976 */, ARM_INS_VMSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_VPR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VMULD /* 2977 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VMULH /* 2978 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull.p64	$Vd, $Vn, $Vm */
+  ARM_VMULLp64 /* 2979 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasAES, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.p8	$Vd, $Vn, $Vm */
+  ARM_VMULLp8 /* 2980 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VMULLslsv2i32 /* 2981 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VMULLslsv4i16 /* 2982 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.u32	$Vd, $Vn, $Vm$lane */
+  ARM_VMULLsluv2i32 /* 2983 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.u16	$Vd, $Vn, $Vm$lane */
+  ARM_VMULLsluv4i16 /* 2984 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VMULLsv2i64 /* 2985 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VMULLsv4i32 /* 2986 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VMULLsv8i16 /* 2987 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VMULLuv2i64 /* 2988 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VMULLuv4i32 /* 2989 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmull${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VMULLuv8i16 /* 2990 */, ARM_INS_VMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VMULS /* 2991 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMULfd /* 2992 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VMULfq /* 2993 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMULhd /* 2994 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VMULhq /* 2995 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.p8	$Vd, $Vn, $Vm */
+  ARM_VMULpd /* 2996 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.p8	$Vd, $Vn, $Vm */
+  ARM_VMULpq /* 2997 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f32	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslfd /* 2998 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f32	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslfq /* 2999 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f16	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslhd /* 3000 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.f16	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslhq /* 3001 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i32	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslv2i32 /* 3002 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i16	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslv4i16 /* 3003 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i32	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslv4i32 /* 3004 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i16	$Vd, $Vn, $Vm$lane */
+  ARM_VMULslv8i16 /* 3005 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VMULv16i8 /* 3006 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VMULv2i32 /* 3007 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VMULv4i16 /* 3008 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VMULv4i32 /* 3009 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VMULv8i16 /* 3010 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmul${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VMULv8i8 /* 3011 */, ARM_INS_VMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${p}	$Vd, $Vm */
+  ARM_VMVNd /* 3012 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${p}	$Vd, $Vm */
+  ARM_VMVNq /* 3013 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${p}.i32	$Vd, $SIMM */
+  ARM_VMVNv2i32 /* 3014 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${p}.i16	$Vd, $SIMM */
+  ARM_VMVNv4i16 /* 3015 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${p}.i32	$Vd, $SIMM */
+  ARM_VMVNv4i32 /* 3016 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmvn${p}.i16	$Vd, $SIMM */
+  ARM_VMVNv8i16 /* 3017 */, ARM_INS_VMVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f64	$Dd, $Dm */
+  ARM_VNEGD /* 3018 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f16	$Sd, $Sm */
+  ARM_VNEGH /* 3019 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f32	$Sd, $Sm */
+  ARM_VNEGS /* 3020 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f32	$Vd, $Vm */
+  ARM_VNEGf32q /* 3021 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f32	$Vd, $Vm */
+  ARM_VNEGfd /* 3022 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f16	$Vd, $Vm */
+  ARM_VNEGhd /* 3023 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.f16	$Vd, $Vm */
+  ARM_VNEGhq /* 3024 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.s16	$Vd, $Vm */
+  ARM_VNEGs16d /* 3025 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.s16	$Vd, $Vm */
+  ARM_VNEGs16q /* 3026 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.s32	$Vd, $Vm */
+  ARM_VNEGs32d /* 3027 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.s32	$Vd, $Vm */
+  ARM_VNEGs32q /* 3028 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.s8	$Vd, $Vm */
+  ARM_VNEGs8d /* 3029 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vneg${p}.s8	$Vd, $Vm */
+  ARM_VNEGs8q /* 3030 */, ARM_INS_VNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmla${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VNMLAD /* 3031 */, ARM_INS_VNMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmla${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VNMLAH /* 3032 */, ARM_INS_VNMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmla${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VNMLAS /* 3033 */, ARM_INS_VNMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmls${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VNMLSD /* 3034 */, ARM_INS_VNMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmls${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VNMLSH /* 3035 */, ARM_INS_VNMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmls${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VNMLSS /* 3036 */, ARM_INS_VNMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmul${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VNMULD /* 3037 */, ARM_INS_VNMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmul${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VNMULH /* 3038 */, ARM_INS_VNMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vnmul${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VNMULS /* 3039 */, ARM_INS_VNMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorn${p}	$Vd, $Vn, $Vm */
+  ARM_VORNd /* 3040 */, ARM_INS_VORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorn${p}	$Vd, $Vn, $Vm */
+  ARM_VORNq /* 3041 */, ARM_INS_VORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${p}	$Vd, $Vn, $Vm */
+  ARM_VORRd /* 3042 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${p}.i32	$Vd, $SIMM */
+  ARM_VORRiv2i32 /* 3043 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${p}.i16	$Vd, $SIMM */
+  ARM_VORRiv4i16 /* 3044 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${p}.i32	$Vd, $SIMM */
+  ARM_VORRiv4i32 /* 3045 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${p}.i16	$Vd, $SIMM */
+  ARM_VORRiv8i16 /* 3046 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vorr${p}	$Vd, $Vn, $Vm */
+  ARM_VORRq /* 3047 */, ARM_INS_VORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.s8	$Vd, $Vm */
+  ARM_VPADALsv16i8 /* 3048 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.s32	$Vd, $Vm */
+  ARM_VPADALsv2i32 /* 3049 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.s16	$Vd, $Vm */
+  ARM_VPADALsv4i16 /* 3050 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.s32	$Vd, $Vm */
+  ARM_VPADALsv4i32 /* 3051 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.s16	$Vd, $Vm */
+  ARM_VPADALsv8i16 /* 3052 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.s8	$Vd, $Vm */
+  ARM_VPADALsv8i8 /* 3053 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.u8	$Vd, $Vm */
+  ARM_VPADALuv16i8 /* 3054 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.u32	$Vd, $Vm */
+  ARM_VPADALuv2i32 /* 3055 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.u16	$Vd, $Vm */
+  ARM_VPADALuv4i16 /* 3056 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.u32	$Vd, $Vm */
+  ARM_VPADALuv4i32 /* 3057 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.u16	$Vd, $Vm */
+  ARM_VPADALuv8i16 /* 3058 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadal${p}.u8	$Vd, $Vm */
+  ARM_VPADALuv8i8 /* 3059 */, ARM_INS_VPADAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.s8	$Vd, $Vm */
+  ARM_VPADDLsv16i8 /* 3060 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.s32	$Vd, $Vm */
+  ARM_VPADDLsv2i32 /* 3061 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.s16	$Vd, $Vm */
+  ARM_VPADDLsv4i16 /* 3062 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.s32	$Vd, $Vm */
+  ARM_VPADDLsv4i32 /* 3063 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.s16	$Vd, $Vm */
+  ARM_VPADDLsv8i16 /* 3064 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.s8	$Vd, $Vm */
+  ARM_VPADDLsv8i8 /* 3065 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.u8	$Vd, $Vm */
+  ARM_VPADDLuv16i8 /* 3066 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.u32	$Vd, $Vm */
+  ARM_VPADDLuv2i32 /* 3067 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.u16	$Vd, $Vm */
+  ARM_VPADDLuv4i16 /* 3068 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.u32	$Vd, $Vm */
+  ARM_VPADDLuv4i32 /* 3069 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.u16	$Vd, $Vm */
+  ARM_VPADDLuv8i16 /* 3070 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpaddl${p}.u8	$Vd, $Vm */
+  ARM_VPADDLuv8i8 /* 3071 */, ARM_INS_VPADDL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadd${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VPADDf /* 3072 */, ARM_INS_VPADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadd${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VPADDh /* 3073 */, ARM_INS_VPADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadd${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VPADDi16 /* 3074 */, ARM_INS_VPADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadd${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VPADDi32 /* 3075 */, ARM_INS_VPADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpadd${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VPADDi8 /* 3076 */, ARM_INS_VPADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VPMAXf /* 3077 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VPMAXh /* 3078 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VPMAXs16 /* 3079 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VPMAXs32 /* 3080 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VPMAXs8 /* 3081 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VPMAXu16 /* 3082 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VPMAXu32 /* 3083 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmax${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VPMAXu8 /* 3084 */, ARM_INS_VPMAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VPMINf /* 3085 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VPMINh /* 3086 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VPMINs16 /* 3087 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VPMINs32 /* 3088 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VPMINs8 /* 3089 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VPMINu16 /* 3090 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VPMINu32 /* 3091 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vpmin${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VPMINu8 /* 3092 */, ARM_INS_VPMIN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${p}.s8	$Vd, $Vm */
+  ARM_VQABSv16i8 /* 3093 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${p}.s32	$Vd, $Vm */
+  ARM_VQABSv2i32 /* 3094 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${p}.s16	$Vd, $Vm */
+  ARM_VQABSv4i16 /* 3095 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${p}.s32	$Vd, $Vm */
+  ARM_VQABSv4i32 /* 3096 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${p}.s16	$Vd, $Vm */
+  ARM_VQABSv8i16 /* 3097 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqabs${p}.s8	$Vd, $Vm */
+  ARM_VQABSv8i8 /* 3098 */, ARM_INS_VQABS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VQADDsv16i8 /* 3099 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s64	$Vd, $Vn, $Vm */
+  ARM_VQADDsv1i64 /* 3100 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQADDsv2i32 /* 3101 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s64	$Vd, $Vn, $Vm */
+  ARM_VQADDsv2i64 /* 3102 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQADDsv4i16 /* 3103 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQADDsv4i32 /* 3104 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQADDsv8i16 /* 3105 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VQADDsv8i8 /* 3106 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VQADDuv16i8 /* 3107 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u64	$Vd, $Vn, $Vm */
+  ARM_VQADDuv1i64 /* 3108 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VQADDuv2i32 /* 3109 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u64	$Vd, $Vn, $Vm */
+  ARM_VQADDuv2i64 /* 3110 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VQADDuv4i16 /* 3111 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VQADDuv4i32 /* 3112 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VQADDuv8i16 /* 3113 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqadd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VQADDuv8i8 /* 3114 */, ARM_INS_VQADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlal${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMLALslv2i32 /* 3115 */, ARM_INS_VQDMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlal${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMLALslv4i16 /* 3116 */, ARM_INS_VQDMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlal${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQDMLALv2i64 /* 3117 */, ARM_INS_VQDMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlal${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQDMLALv4i32 /* 3118 */, ARM_INS_VQDMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsl${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMLSLslv2i32 /* 3119 */, ARM_INS_VQDMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsl${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMLSLslv4i16 /* 3120 */, ARM_INS_VQDMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsl${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQDMLSLv2i64 /* 3121 */, ARM_INS_VQDMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmlsl${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQDMLSLv4i32 /* 3122 */, ARM_INS_VQDMLSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMULHslv2i32 /* 3123 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMULHslv4i16 /* 3124 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMULHslv4i32 /* 3125 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMULHslv8i16 /* 3126 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQDMULHv2i32 /* 3127 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQDMULHv4i16 /* 3128 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQDMULHv4i32 /* 3129 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmulh${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQDMULHv8i16 /* 3130 */, ARM_INS_VQDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmull${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMULLslv2i32 /* 3131 */, ARM_INS_VQDMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmull${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQDMULLslv4i16 /* 3132 */, ARM_INS_VQDMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmull${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQDMULLv2i64 /* 3133 */, ARM_INS_VQDMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqdmull${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQDMULLv4i32 /* 3134 */, ARM_INS_VQDMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovun${p}.s64	$Vd, $Vm */
+  ARM_VQMOVNsuv2i32 /* 3135 */, ARM_INS_VQMOVUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovun${p}.s32	$Vd, $Vm */
+  ARM_VQMOVNsuv4i16 /* 3136 */, ARM_INS_VQMOVUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovun${p}.s16	$Vd, $Vm */
+  ARM_VQMOVNsuv8i8 /* 3137 */, ARM_INS_VQMOVUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovn${p}.s64	$Vd, $Vm */
+  ARM_VQMOVNsv2i32 /* 3138 */, ARM_INS_VQMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovn${p}.s32	$Vd, $Vm */
+  ARM_VQMOVNsv4i16 /* 3139 */, ARM_INS_VQMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovn${p}.s16	$Vd, $Vm */
+  ARM_VQMOVNsv8i8 /* 3140 */, ARM_INS_VQMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovn${p}.u64	$Vd, $Vm */
+  ARM_VQMOVNuv2i32 /* 3141 */, ARM_INS_VQMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovn${p}.u32	$Vd, $Vm */
+  ARM_VQMOVNuv4i16 /* 3142 */, ARM_INS_VQMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqmovn${p}.u16	$Vd, $Vm */
+  ARM_VQMOVNuv8i8 /* 3143 */, ARM_INS_VQMOVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${p}.s8	$Vd, $Vm */
+  ARM_VQNEGv16i8 /* 3144 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${p}.s32	$Vd, $Vm */
+  ARM_VQNEGv2i32 /* 3145 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${p}.s16	$Vd, $Vm */
+  ARM_VQNEGv4i16 /* 3146 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${p}.s32	$Vd, $Vm */
+  ARM_VQNEGv4i32 /* 3147 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${p}.s16	$Vd, $Vm */
+  ARM_VQNEGv8i16 /* 3148 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqneg${p}.s8	$Vd, $Vm */
+  ARM_VQNEGv8i8 /* 3149 */, ARM_INS_VQNEG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLAHslv2i32 /* 3150 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLAHslv4i16 /* 3151 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLAHslv4i32 /* 3152 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLAHslv8i16 /* 3153 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQRDMLAHv2i32 /* 3154 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQRDMLAHv4i16 /* 3155 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQRDMLAHv4i32 /* 3156 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlah${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQRDMLAHv8i16 /* 3157 */, ARM_INS_VQRDMLAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLSHslv2i32 /* 3158 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLSHslv4i16 /* 3159 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLSHslv4i32 /* 3160 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMLSHslv8i16 /* 3161 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQRDMLSHv2i32 /* 3162 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQRDMLSHv4i16 /* 3163 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQRDMLSHv4i32 /* 3164 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmlsh${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQRDMLSHv8i16 /* 3165 */, ARM_INS_VQRDMLSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMULHslv2i32 /* 3166 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMULHslv4i16 /* 3167 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMULHslv4i32 /* 3168 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+  ARM_VQRDMULHslv8i16 /* 3169 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQRDMULHv2i32 /* 3170 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQRDMULHv4i16 /* 3171 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQRDMULHv4i32 /* 3172 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrdmulh${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQRDMULHv8i16 /* 3173 */, ARM_INS_VQRDMULH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv16i8 /* 3174 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv1i64 /* 3175 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv2i32 /* 3176 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv2i64 /* 3177 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv4i16 /* 3178 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv4i32 /* 3179 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv8i16 /* 3180 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VQRSHLsv8i8 /* 3181 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv16i8 /* 3182 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv1i64 /* 3183 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv2i32 /* 3184 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv2i64 /* 3185 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv4i16 /* 3186 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv4i32 /* 3187 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv8i16 /* 3188 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VQRSHLuv8i8 /* 3189 */, ARM_INS_VQRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrn${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRNsv2i32 /* 3190 */, ARM_INS_VQRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrn${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRNsv4i16 /* 3191 */, ARM_INS_VQRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrn${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRNsv8i8 /* 3192 */, ARM_INS_VQRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrn${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRNuv2i32 /* 3193 */, ARM_INS_VQRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrn${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRNuv4i16 /* 3194 */, ARM_INS_VQRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrn${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRNuv8i8 /* 3195 */, ARM_INS_VQRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrun${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRUNv2i32 /* 3196 */, ARM_INS_VQRSHRUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrun${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRUNv4i16 /* 3197 */, ARM_INS_VQRSHRUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqrshrun${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQRSHRUNv8i8 /* 3198 */, ARM_INS_VQRSHRUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv16i8 /* 3199 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv1i64 /* 3200 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv2i32 /* 3201 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv2i64 /* 3202 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv4i16 /* 3203 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv4i32 /* 3204 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv8i16 /* 3205 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsiv8i8 /* 3206 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv16i8 /* 3207 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv1i64 /* 3208 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv2i32 /* 3209 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv2i64 /* 3210 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv4i16 /* 3211 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv4i32 /* 3212 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv8i16 /* 3213 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshlu${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VQSHLsuv8i8 /* 3214 */, ARM_INS_VQSHLU,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv16i8 /* 3215 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv1i64 /* 3216 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv2i32 /* 3217 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv2i64 /* 3218 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv4i16 /* 3219 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv4i32 /* 3220 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv8i16 /* 3221 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VQSHLsv8i8 /* 3222 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv16i8 /* 3223 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv1i64 /* 3224 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv2i32 /* 3225 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv2i64 /* 3226 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv4i16 /* 3227 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv4i32 /* 3228 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv8i16 /* 3229 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VQSHLuiv8i8 /* 3230 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv16i8 /* 3231 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv1i64 /* 3232 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv2i32 /* 3233 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv2i64 /* 3234 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv4i16 /* 3235 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv4i32 /* 3236 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv8i16 /* 3237 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VQSHLuv8i8 /* 3238 */, ARM_INS_VQSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrn${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQSHRNsv2i32 /* 3239 */, ARM_INS_VQSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrn${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQSHRNsv4i16 /* 3240 */, ARM_INS_VQSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrn${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQSHRNsv8i8 /* 3241 */, ARM_INS_VQSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrn${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VQSHRNuv2i32 /* 3242 */, ARM_INS_VQSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrn${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VQSHRNuv4i16 /* 3243 */, ARM_INS_VQSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrn${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VQSHRNuv8i8 /* 3244 */, ARM_INS_VQSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrun${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VQSHRUNv2i32 /* 3245 */, ARM_INS_VQSHRUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrun${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VQSHRUNv4i16 /* 3246 */, ARM_INS_VQSHRUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqshrun${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VQSHRUNv8i8 /* 3247 */, ARM_INS_VQSHRUN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv16i8 /* 3248 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s64	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv1i64 /* 3249 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv2i32 /* 3250 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s64	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv2i64 /* 3251 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv4i16 /* 3252 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv4i32 /* 3253 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv8i16 /* 3254 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VQSUBsv8i8 /* 3255 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv16i8 /* 3256 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u64	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv1i64 /* 3257 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv2i32 /* 3258 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u64	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv2i64 /* 3259 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv4i16 /* 3260 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv4i32 /* 3261 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv8i16 /* 3262 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vqsub${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VQSUBuv8i8 /* 3263 */, ARM_INS_VQSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vraddhn${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VRADDHNv2i32 /* 3264 */, ARM_INS_VRADDHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vraddhn${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VRADDHNv4i16 /* 3265 */, ARM_INS_VRADDHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vraddhn${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VRADDHNv8i8 /* 3266 */, ARM_INS_VRADDHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecpe${p}.u32	$Vd, $Vm */
+  ARM_VRECPEd /* 3267 */, ARM_INS_VRECPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecpe${p}.f32	$Vd, $Vm */
+  ARM_VRECPEfd /* 3268 */, ARM_INS_VRECPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecpe${p}.f32	$Vd, $Vm */
+  ARM_VRECPEfq /* 3269 */, ARM_INS_VRECPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecpe${p}.f16	$Vd, $Vm */
+  ARM_VRECPEhd /* 3270 */, ARM_INS_VRECPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecpe${p}.f16	$Vd, $Vm */
+  ARM_VRECPEhq /* 3271 */, ARM_INS_VRECPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecpe${p}.u32	$Vd, $Vm */
+  ARM_VRECPEq /* 3272 */, ARM_INS_VRECPE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecps${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VRECPSfd /* 3273 */, ARM_INS_VRECPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecps${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VRECPSfq /* 3274 */, ARM_INS_VRECPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecps${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VRECPShd /* 3275 */, ARM_INS_VRECPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrecps${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VRECPShq /* 3276 */, ARM_INS_VRECPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev16${p}.8	$Vd, $Vm */
+  ARM_VREV16d8 /* 3277 */, ARM_INS_VREV16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev16${p}.8	$Vd, $Vm */
+  ARM_VREV16q8 /* 3278 */, ARM_INS_VREV16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev32${p}.16	$Vd, $Vm */
+  ARM_VREV32d16 /* 3279 */, ARM_INS_VREV32,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev32${p}.8	$Vd, $Vm */
+  ARM_VREV32d8 /* 3280 */, ARM_INS_VREV32,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev32${p}.16	$Vd, $Vm */
+  ARM_VREV32q16 /* 3281 */, ARM_INS_VREV32,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev32${p}.8	$Vd, $Vm */
+  ARM_VREV32q8 /* 3282 */, ARM_INS_VREV32,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${p}.16	$Vd, $Vm */
+  ARM_VREV64d16 /* 3283 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${p}.32	$Vd, $Vm */
+  ARM_VREV64d32 /* 3284 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${p}.8	$Vd, $Vm */
+  ARM_VREV64d8 /* 3285 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${p}.16	$Vd, $Vm */
+  ARM_VREV64q16 /* 3286 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${p}.32	$Vd, $Vm */
+  ARM_VREV64q32 /* 3287 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrev64${p}.8	$Vd, $Vm */
+  ARM_VREV64q8 /* 3288 */, ARM_INS_VREV64,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VRHADDsv16i8 /* 3289 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VRHADDsv2i32 /* 3290 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VRHADDsv4i16 /* 3291 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VRHADDsv4i32 /* 3292 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VRHADDsv8i16 /* 3293 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VRHADDsv8i8 /* 3294 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VRHADDuv16i8 /* 3295 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VRHADDuv2i32 /* 3296 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VRHADDuv4i16 /* 3297 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VRHADDuv4i32 /* 3298 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VRHADDuv8i16 /* 3299 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrhadd${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VRHADDuv8i8 /* 3300 */, ARM_INS_VRHADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f64	$Dd, $Dm */
+  ARM_VRINTAD /* 3301 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f16	$Sd, $Sm */
+  ARM_VRINTAH /* 3302 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f32	$Vd, $Vm */
+  ARM_VRINTANDf /* 3303 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f16	$Vd, $Vm */
+  ARM_VRINTANDh /* 3304 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f32	$Vd, $Vm */
+  ARM_VRINTANQf /* 3305 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f16	$Vd, $Vm */
+  ARM_VRINTANQh /* 3306 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrinta.f32	$Sd, $Sm */
+  ARM_VRINTAS /* 3307 */, ARM_INS_VRINTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f64	$Dd, $Dm */
+  ARM_VRINTMD /* 3308 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f16	$Sd, $Sm */
+  ARM_VRINTMH /* 3309 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f32	$Vd, $Vm */
+  ARM_VRINTMNDf /* 3310 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f16	$Vd, $Vm */
+  ARM_VRINTMNDh /* 3311 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f32	$Vd, $Vm */
+  ARM_VRINTMNQf /* 3312 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f16	$Vd, $Vm */
+  ARM_VRINTMNQh /* 3313 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintm.f32	$Sd, $Sm */
+  ARM_VRINTMS /* 3314 */, ARM_INS_VRINTM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f64	$Dd, $Dm */
+  ARM_VRINTND /* 3315 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f16	$Sd, $Sm */
+  ARM_VRINTNH /* 3316 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f32	$Vd, $Vm */
+  ARM_VRINTNNDf /* 3317 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f16	$Vd, $Vm */
+  ARM_VRINTNNDh /* 3318 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f32	$Vd, $Vm */
+  ARM_VRINTNNQf /* 3319 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f16	$Vd, $Vm */
+  ARM_VRINTNNQh /* 3320 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintn.f32	$Sd, $Sm */
+  ARM_VRINTNS /* 3321 */, ARM_INS_VRINTN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f64	$Dd, $Dm */
+  ARM_VRINTPD /* 3322 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f16	$Sd, $Sm */
+  ARM_VRINTPH /* 3323 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f32	$Vd, $Vm */
+  ARM_VRINTPNDf /* 3324 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f16	$Vd, $Vm */
+  ARM_VRINTPNDh /* 3325 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f32	$Vd, $Vm */
+  ARM_VRINTPNQf /* 3326 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f16	$Vd, $Vm */
+  ARM_VRINTPNQh /* 3327 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintp.f32	$Sd, $Sm */
+  ARM_VRINTPS /* 3328 */, ARM_INS_VRINTP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintr${p}.f64	$Dd, $Dm */
+  ARM_VRINTRD /* 3329 */, ARM_INS_VRINTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintr${p}.f16	$Sd, $Sm */
+  ARM_VRINTRH /* 3330 */, ARM_INS_VRINTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintr${p}.f32	$Sd, $Sm */
+  ARM_VRINTRS /* 3331 */, ARM_INS_VRINTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx${p}.f64	$Dd, $Dm */
+  ARM_VRINTXD /* 3332 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx${p}.f16	$Sd, $Sm */
+  ARM_VRINTXH /* 3333 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx.f32	$Vd, $Vm */
+  ARM_VRINTXNDf /* 3334 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx.f16	$Vd, $Vm */
+  ARM_VRINTXNDh /* 3335 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx.f32	$Vd, $Vm */
+  ARM_VRINTXNQf /* 3336 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx.f16	$Vd, $Vm */
+  ARM_VRINTXNQh /* 3337 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintx${p}.f32	$Sd, $Sm */
+  ARM_VRINTXS /* 3338 */, ARM_INS_VRINTX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz${p}.f64	$Dd, $Dm */
+  ARM_VRINTZD /* 3339 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz${p}.f16	$Sd, $Sm */
+  ARM_VRINTZH /* 3340 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz.f32	$Vd, $Vm */
+  ARM_VRINTZNDf /* 3341 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz.f16	$Vd, $Vm */
+  ARM_VRINTZNDh /* 3342 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz.f32	$Vd, $Vm */
+  ARM_VRINTZNQf /* 3343 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz.f16	$Vd, $Vm */
+  ARM_VRINTZNQh /* 3344 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8, ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrintz${p}.f32	$Sd, $Sm */
+  ARM_VRINTZS /* 3345 */, ARM_INS_VRINTZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv16i8 /* 3346 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv1i64 /* 3347 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv2i32 /* 3348 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv2i64 /* 3349 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv4i16 /* 3350 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv4i32 /* 3351 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv8i16 /* 3352 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VRSHLsv8i8 /* 3353 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv16i8 /* 3354 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv1i64 /* 3355 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv2i32 /* 3356 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv2i64 /* 3357 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv4i16 /* 3358 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv4i32 /* 3359 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv8i16 /* 3360 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VRSHLuv8i8 /* 3361 */, ARM_INS_VRSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrn${p}.i64	$Vd, $Vm, $SIMM */
+  ARM_VRSHRNv2i32 /* 3362 */, ARM_INS_VRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrn${p}.i32	$Vd, $Vm, $SIMM */
+  ARM_VRSHRNv4i16 /* 3363 */, ARM_INS_VRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshrn${p}.i16	$Vd, $Vm, $SIMM */
+  ARM_VRSHRNv8i8 /* 3364 */, ARM_INS_VRSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv16i8 /* 3365 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv1i64 /* 3366 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv2i32 /* 3367 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv2i64 /* 3368 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv4i16 /* 3369 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv4i32 /* 3370 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv8i16 /* 3371 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VRSHRsv8i8 /* 3372 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv16i8 /* 3373 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv1i64 /* 3374 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv2i32 /* 3375 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv2i64 /* 3376 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv4i16 /* 3377 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv4i32 /* 3378 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv8i16 /* 3379 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrshr${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VRSHRuv8i8 /* 3380 */, ARM_INS_VRSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrte${p}.u32	$Vd, $Vm */
+  ARM_VRSQRTEd /* 3381 */, ARM_INS_VRSQRTE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrte${p}.f32	$Vd, $Vm */
+  ARM_VRSQRTEfd /* 3382 */, ARM_INS_VRSQRTE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrte${p}.f32	$Vd, $Vm */
+  ARM_VRSQRTEfq /* 3383 */, ARM_INS_VRSQRTE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrte${p}.f16	$Vd, $Vm */
+  ARM_VRSQRTEhd /* 3384 */, ARM_INS_VRSQRTE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrte${p}.f16	$Vd, $Vm */
+  ARM_VRSQRTEhq /* 3385 */, ARM_INS_VRSQRTE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrte${p}.u32	$Vd, $Vm */
+  ARM_VRSQRTEq /* 3386 */, ARM_INS_VRSQRTE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrts${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VRSQRTSfd /* 3387 */, ARM_INS_VRSQRTS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrts${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VRSQRTSfq /* 3388 */, ARM_INS_VRSQRTS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrts${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VRSQRTShd /* 3389 */, ARM_INS_VRSQRTS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsqrts${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VRSQRTShq /* 3390 */, ARM_INS_VRSQRTS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv16i8 /* 3391 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv1i64 /* 3392 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv2i32 /* 3393 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv2i64 /* 3394 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv4i16 /* 3395 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv4i32 /* 3396 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv8i16 /* 3397 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VRSRAsv8i8 /* 3398 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv16i8 /* 3399 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv1i64 /* 3400 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv2i32 /* 3401 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv2i64 /* 3402 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv4i16 /* 3403 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv4i32 /* 3404 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv8i16 /* 3405 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsra${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VRSRAuv8i8 /* 3406 */, ARM_INS_VRSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsubhn${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VRSUBHNv2i32 /* 3407 */, ARM_INS_VRSUBHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsubhn${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VRSUBHNv4i16 /* 3408 */, ARM_INS_VRSUBHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vrsubhn${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VRSUBHNv8i8 /* 3409 */, ARM_INS_VRSUBHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vscclrm{$p}	$regs */
+  ARM_VSCCLRMD /* 3410 */, ARM_INS_VSCCLRM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vscclrm{$p}	$regs */
+  ARM_VSCCLRMS /* 3411 */, ARM_INS_VSCCLRM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsdot.s8	$Vd, $Vn, $Vm */
+  ARM_VSDOTD /* 3412 */, ARM_INS_VSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsdot.s8	$Vd, $Vn, $Vm$lane */
+  ARM_VSDOTDI /* 3413 */, ARM_INS_VSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsdot.s8	$Vd, $Vn, $Vm */
+  ARM_VSDOTQ /* 3414 */, ARM_INS_VSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsdot.s8	$Vd, $Vn, $Vm$lane */
+  ARM_VSDOTQI /* 3415 */, ARM_INS_VSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vseleq.f64	$Dd, $Dn, $Dm */
+  ARM_VSELEQD /* 3416 */, ARM_INS_VSELEQ,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vseleq.f16	$Sd, $Sn, $Sm */
+  ARM_VSELEQH /* 3417 */, ARM_INS_VSELEQ,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vseleq.f32	$Sd, $Sn, $Sm */
+  ARM_VSELEQS /* 3418 */, ARM_INS_VSELEQ,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselge.f64	$Dd, $Dn, $Dm */
+  ARM_VSELGED /* 3419 */, ARM_INS_VSELGE,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselge.f16	$Sd, $Sn, $Sm */
+  ARM_VSELGEH /* 3420 */, ARM_INS_VSELGE,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselge.f32	$Sd, $Sn, $Sm */
+  ARM_VSELGES /* 3421 */, ARM_INS_VSELGE,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselgt.f64	$Dd, $Dn, $Dm */
+  ARM_VSELGTD /* 3422 */, ARM_INS_VSELGT,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselgt.f16	$Sd, $Sn, $Sm */
+  ARM_VSELGTH /* 3423 */, ARM_INS_VSELGT,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselgt.f32	$Sd, $Sn, $Sm */
+  ARM_VSELGTS /* 3424 */, ARM_INS_VSELGT,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselvs.f64	$Dd, $Dn, $Dm */
+  ARM_VSELVSD /* 3425 */, ARM_INS_VSELVS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselvs.f16	$Sd, $Sn, $Sm */
+  ARM_VSELVSH /* 3426 */, ARM_INS_VSELVS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vselvs.f32	$Sd, $Sn, $Sm */
+  ARM_VSELVSS /* 3427 */, ARM_INS_VSELVS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasFPARMv8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.16	$V$lane, $R */
+  ARM_VSETLNi16 /* 3428 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.32	$V$lane, $R */
+  ARM_VSETLNi32 /* 3429 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vmov${p}.8	$V$lane, $R */
+  ARM_VSETLNi8 /* 3430 */, ARM_INS_VMOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.i16	$Vd, $Vm, $SIMM */
+  ARM_VSHLLi16 /* 3431 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.i32	$Vd, $Vm, $SIMM */
+  ARM_VSHLLi32 /* 3432 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.i8	$Vd, $Vm, $SIMM */
+  ARM_VSHLLi8 /* 3433 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VSHLLsv2i64 /* 3434 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VSHLLsv4i32 /* 3435 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VSHLLsv8i16 /* 3436 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VSHLLuv2i64 /* 3437 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VSHLLuv4i32 /* 3438 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshll${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VSHLLuv8i16 /* 3439 */, ARM_INS_VSHLL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i8	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv16i8 /* 3440 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i64	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv1i64 /* 3441 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i32	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv2i32 /* 3442 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i64	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv2i64 /* 3443 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i16	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv4i16 /* 3444 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i32	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv4i32 /* 3445 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i16	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv8i16 /* 3446 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.i8	$Vd, $Vm, $SIMM */
+  ARM_VSHLiv8i8 /* 3447 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VSHLsv16i8 /* 3448 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VSHLsv1i64 /* 3449 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VSHLsv2i32 /* 3450 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s64	$Vd, $Vm, $Vn */
+  ARM_VSHLsv2i64 /* 3451 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VSHLsv4i16 /* 3452 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s32	$Vd, $Vm, $Vn */
+  ARM_VSHLsv4i32 /* 3453 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s16	$Vd, $Vm, $Vn */
+  ARM_VSHLsv8i16 /* 3454 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.s8	$Vd, $Vm, $Vn */
+  ARM_VSHLsv8i8 /* 3455 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VSHLuv16i8 /* 3456 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VSHLuv1i64 /* 3457 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VSHLuv2i32 /* 3458 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u64	$Vd, $Vm, $Vn */
+  ARM_VSHLuv2i64 /* 3459 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VSHLuv4i16 /* 3460 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u32	$Vd, $Vm, $Vn */
+  ARM_VSHLuv4i32 /* 3461 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u16	$Vd, $Vm, $Vn */
+  ARM_VSHLuv8i16 /* 3462 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshl${p}.u8	$Vd, $Vm, $Vn */
+  ARM_VSHLuv8i8 /* 3463 */, ARM_INS_VSHL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrn${p}.i64	$Vd, $Vm, $SIMM */
+  ARM_VSHRNv2i32 /* 3464 */, ARM_INS_VSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrn${p}.i32	$Vd, $Vm, $SIMM */
+  ARM_VSHRNv4i16 /* 3465 */, ARM_INS_VSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshrn${p}.i16	$Vd, $Vm, $SIMM */
+  ARM_VSHRNv8i8 /* 3466 */, ARM_INS_VSHRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv16i8 /* 3467 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv1i64 /* 3468 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv2i32 /* 3469 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv2i64 /* 3470 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv4i16 /* 3471 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv4i32 /* 3472 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv8i16 /* 3473 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VSHRsv8i8 /* 3474 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv16i8 /* 3475 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv1i64 /* 3476 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv2i32 /* 3477 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv2i64 /* 3478 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv4i16 /* 3479 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv4i32 /* 3480 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv8i16 /* 3481 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vshr${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VSHRuv8i8 /* 3482 */, ARM_INS_VSHR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.s16	$dst, $a, $fbits */
+  ARM_VSHTOD /* 3483 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s16	$dst, $a, $fbits */
+  ARM_VSHTOH /* 3484 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s16	$dst, $a, $fbits */
+  ARM_VSHTOS /* 3485 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.s32	$Dd, $Sm */
+  ARM_VSITOD /* 3486 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s32	$Sd, $Sm */
+  ARM_VSITOH /* 3487 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s32	$Sd, $Sm */
+  ARM_VSITOS /* 3488 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.8	$Vd, $Vm, $SIMM */
+  ARM_VSLIv16i8 /* 3489 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.64	$Vd, $Vm, $SIMM */
+  ARM_VSLIv1i64 /* 3490 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.32	$Vd, $Vm, $SIMM */
+  ARM_VSLIv2i32 /* 3491 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.64	$Vd, $Vm, $SIMM */
+  ARM_VSLIv2i64 /* 3492 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.16	$Vd, $Vm, $SIMM */
+  ARM_VSLIv4i16 /* 3493 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.32	$Vd, $Vm, $SIMM */
+  ARM_VSLIv4i32 /* 3494 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.16	$Vd, $Vm, $SIMM */
+  ARM_VSLIv8i16 /* 3495 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsli${p}.8	$Vd, $Vm, $SIMM */
+  ARM_VSLIv8i8 /* 3496 */, ARM_INS_VSLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.s32	$dst, $a, $fbits */
+  ARM_VSLTOD /* 3497 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.s32	$dst, $a, $fbits */
+  ARM_VSLTOH /* 3498 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.s32	$dst, $a, $fbits */
+  ARM_VSLTOS /* 3499 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsmmla.s8	$Vd, $Vn, $Vm */
+  ARM_VSMMLA /* 3500 */, ARM_INS_VSMMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsqrt${p}.f64	$Dd, $Dm */
+  ARM_VSQRTD /* 3501 */, ARM_INS_VSQRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsqrt${p}.f16	$Sd, $Sm */
+  ARM_VSQRTH /* 3502 */, ARM_INS_VSQRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsqrt${p}.f32	$Sd, $Sm */
+  ARM_VSQRTS /* 3503 */, ARM_INS_VSQRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv16i8 /* 3504 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv1i64 /* 3505 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv2i32 /* 3506 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s64	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv2i64 /* 3507 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv4i16 /* 3508 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s32	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv4i32 /* 3509 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s16	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv8i16 /* 3510 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.s8	$Vd, $Vm, $SIMM */
+  ARM_VSRAsv8i8 /* 3511 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv16i8 /* 3512 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv1i64 /* 3513 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv2i32 /* 3514 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u64	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv2i64 /* 3515 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv4i16 /* 3516 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u32	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv4i32 /* 3517 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u16	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv8i16 /* 3518 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsra${p}.u8	$Vd, $Vm, $SIMM */
+  ARM_VSRAuv8i8 /* 3519 */, ARM_INS_VSRA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.8	$Vd, $Vm, $SIMM */
+  ARM_VSRIv16i8 /* 3520 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.64	$Vd, $Vm, $SIMM */
+  ARM_VSRIv1i64 /* 3521 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.32	$Vd, $Vm, $SIMM */
+  ARM_VSRIv2i32 /* 3522 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.64	$Vd, $Vm, $SIMM */
+  ARM_VSRIv2i64 /* 3523 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.16	$Vd, $Vm, $SIMM */
+  ARM_VSRIv4i16 /* 3524 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.32	$Vd, $Vm, $SIMM */
+  ARM_VSRIv4i32 /* 3525 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.16	$Vd, $Vm, $SIMM */
+  ARM_VSRIv8i16 /* 3526 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsri${p}.8	$Vd, $Vm, $SIMM */
+  ARM_VSRIv8i8 /* 3527 */, ARM_INS_VSRI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	\{$Vd[$lane]\}, $Rn */
+  ARM_VST1LNd16 /* 3528 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	\{$Vd[$lane]\}, $Rn$Rm */
+  ARM_VST1LNd16_UPD /* 3529 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	\{$Vd[$lane]\}, $Rn */
+  ARM_VST1LNd32 /* 3530 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	\{$Vd[$lane]\}, $Rn$Rm */
+  ARM_VST1LNd32_UPD /* 3531 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	\{$Vd[$lane]\}, $Rn */
+  ARM_VST1LNd8 /* 3532 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	\{$Vd[$lane]\}, $Rn$Rm */
+  ARM_VST1LNd8_UPD /* 3533 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1LNq16Pseudo /* 3534 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1LNq16Pseudo_UPD /* 3535 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1LNq32Pseudo /* 3536 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1LNq32Pseudo_UPD /* 3537 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1LNq8Pseudo /* 3538 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1LNq8Pseudo_UPD /* 3539 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn */
+  ARM_VST1d16 /* 3540 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn */
+  ARM_VST1d16Q /* 3541 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d16QPseudo /* 3542 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d16QPseudoWB_fixed /* 3543 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d16QPseudoWB_register /* 3544 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn! */
+  ARM_VST1d16Qwb_fixed /* 3545 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST1d16Qwb_register /* 3546 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn */
+  ARM_VST1d16T /* 3547 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d16TPseudo /* 3548 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d16TPseudoWB_fixed /* 3549 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d16TPseudoWB_register /* 3550 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn! */
+  ARM_VST1d16Twb_fixed /* 3551 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST1d16Twb_register /* 3552 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn! */
+  ARM_VST1d16wb_fixed /* 3553 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST1d16wb_register /* 3554 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn */
+  ARM_VST1d32 /* 3555 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn */
+  ARM_VST1d32Q /* 3556 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d32QPseudo /* 3557 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d32QPseudoWB_fixed /* 3558 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d32QPseudoWB_register /* 3559 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn! */
+  ARM_VST1d32Qwb_fixed /* 3560 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST1d32Qwb_register /* 3561 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn */
+  ARM_VST1d32T /* 3562 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d32TPseudo /* 3563 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d32TPseudoWB_fixed /* 3564 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d32TPseudoWB_register /* 3565 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn! */
+  ARM_VST1d32Twb_fixed /* 3566 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST1d32Twb_register /* 3567 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn! */
+  ARM_VST1d32wb_fixed /* 3568 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST1d32wb_register /* 3569 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn */
+  ARM_VST1d64 /* 3570 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn */
+  ARM_VST1d64Q /* 3571 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d64QPseudo /* 3572 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d64QPseudoWB_fixed /* 3573 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d64QPseudoWB_register /* 3574 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn! */
+  ARM_VST1d64Qwb_fixed /* 3575 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VST1d64Qwb_register /* 3576 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn */
+  ARM_VST1d64T /* 3577 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d64TPseudo /* 3578 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d64TPseudoWB_fixed /* 3579 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d64TPseudoWB_register /* 3580 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn! */
+  ARM_VST1d64Twb_fixed /* 3581 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VST1d64Twb_register /* 3582 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn! */
+  ARM_VST1d64wb_fixed /* 3583 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VST1d64wb_register /* 3584 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn */
+  ARM_VST1d8 /* 3585 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn */
+  ARM_VST1d8Q /* 3586 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d8QPseudo /* 3587 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d8QPseudoWB_fixed /* 3588 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d8QPseudoWB_register /* 3589 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn! */
+  ARM_VST1d8Qwb_fixed /* 3590 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST1d8Qwb_register /* 3591 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn */
+  ARM_VST1d8T /* 3592 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d8TPseudo /* 3593 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d8TPseudoWB_fixed /* 3594 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1d8TPseudoWB_register /* 3595 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn! */
+  ARM_VST1d8Twb_fixed /* 3596 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST1d8Twb_register /* 3597 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn! */
+  ARM_VST1d8wb_fixed /* 3598 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST1d8wb_register /* 3599 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn */
+  ARM_VST1q16 /* 3600 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q16HighQPseudo /* 3601 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q16HighQPseudo_UPD /* 3602 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q16HighTPseudo /* 3603 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q16HighTPseudo_UPD /* 3604 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q16LowQPseudo_UPD /* 3605 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q16LowTPseudo_UPD /* 3606 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn! */
+  ARM_VST1q16wb_fixed /* 3607 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST1q16wb_register /* 3608 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn */
+  ARM_VST1q32 /* 3609 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q32HighQPseudo /* 3610 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q32HighQPseudo_UPD /* 3611 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q32HighTPseudo /* 3612 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q32HighTPseudo_UPD /* 3613 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q32LowQPseudo_UPD /* 3614 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q32LowTPseudo_UPD /* 3615 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn! */
+  ARM_VST1q32wb_fixed /* 3616 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST1q32wb_register /* 3617 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn */
+  ARM_VST1q64 /* 3618 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q64HighQPseudo /* 3619 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q64HighQPseudo_UPD /* 3620 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q64HighTPseudo /* 3621 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q64HighTPseudo_UPD /* 3622 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q64LowQPseudo_UPD /* 3623 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q64LowTPseudo_UPD /* 3624 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn! */
+  ARM_VST1q64wb_fixed /* 3625 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.64	$Vd, $Rn, $Rm */
+  ARM_VST1q64wb_register /* 3626 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn */
+  ARM_VST1q8 /* 3627 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q8HighQPseudo /* 3628 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q8HighQPseudo_UPD /* 3629 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q8HighTPseudo /* 3630 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q8HighTPseudo_UPD /* 3631 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q8LowQPseudo_UPD /* 3632 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST1q8LowTPseudo_UPD /* 3633 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn! */
+  ARM_VST1q8wb_fixed /* 3634 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst1${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST1q8wb_register /* 3635 */, ARM_INS_VST1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+  ARM_VST2LNd16 /* 3636 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNd16Pseudo /* 3637 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNd16Pseudo_UPD /* 3638 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+  ARM_VST2LNd16_UPD /* 3639 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+  ARM_VST2LNd32 /* 3640 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNd32Pseudo /* 3641 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNd32Pseudo_UPD /* 3642 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+  ARM_VST2LNd32_UPD /* 3643 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+  ARM_VST2LNd8 /* 3644 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNd8Pseudo /* 3645 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNd8Pseudo_UPD /* 3646 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+  ARM_VST2LNd8_UPD /* 3647 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+  ARM_VST2LNq16 /* 3648 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNq16Pseudo /* 3649 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNq16Pseudo_UPD /* 3650 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+  ARM_VST2LNq16_UPD /* 3651 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+  ARM_VST2LNq32 /* 3652 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNq32Pseudo /* 3653 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2LNq32Pseudo_UPD /* 3654 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+  ARM_VST2LNq32_UPD /* 3655 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn */
+  ARM_VST2b16 /* 3656 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn! */
+  ARM_VST2b16wb_fixed /* 3657 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST2b16wb_register /* 3658 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn */
+  ARM_VST2b32 /* 3659 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn! */
+  ARM_VST2b32wb_fixed /* 3660 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST2b32wb_register /* 3661 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn */
+  ARM_VST2b8 /* 3662 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn! */
+  ARM_VST2b8wb_fixed /* 3663 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST2b8wb_register /* 3664 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn */
+  ARM_VST2d16 /* 3665 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn! */
+  ARM_VST2d16wb_fixed /* 3666 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST2d16wb_register /* 3667 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn */
+  ARM_VST2d32 /* 3668 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn! */
+  ARM_VST2d32wb_fixed /* 3669 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST2d32wb_register /* 3670 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn */
+  ARM_VST2d8 /* 3671 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn! */
+  ARM_VST2d8wb_fixed /* 3672 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST2d8wb_register /* 3673 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn */
+  ARM_VST2q16 /* 3674 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q16Pseudo /* 3675 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q16PseudoWB_fixed /* 3676 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q16PseudoWB_register /* 3677 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn! */
+  ARM_VST2q16wb_fixed /* 3678 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.16	$Vd, $Rn, $Rm */
+  ARM_VST2q16wb_register /* 3679 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn */
+  ARM_VST2q32 /* 3680 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q32Pseudo /* 3681 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q32PseudoWB_fixed /* 3682 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q32PseudoWB_register /* 3683 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn! */
+  ARM_VST2q32wb_fixed /* 3684 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.32	$Vd, $Rn, $Rm */
+  ARM_VST2q32wb_register /* 3685 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn */
+  ARM_VST2q8 /* 3686 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q8Pseudo /* 3687 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q8PseudoWB_fixed /* 3688 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST2q8PseudoWB_register /* 3689 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn! */
+  ARM_VST2q8wb_fixed /* 3690 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst2${p}.8	$Vd, $Rn, $Rm */
+  ARM_VST2q8wb_register /* 3691 */, ARM_INS_VST2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+  ARM_VST3LNd16 /* 3692 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNd16Pseudo /* 3693 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNd16Pseudo_UPD /* 3694 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+  ARM_VST3LNd16_UPD /* 3695 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+  ARM_VST3LNd32 /* 3696 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNd32Pseudo /* 3697 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNd32Pseudo_UPD /* 3698 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+  ARM_VST3LNd32_UPD /* 3699 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+  ARM_VST3LNd8 /* 3700 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNd8Pseudo /* 3701 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNd8Pseudo_UPD /* 3702 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+  ARM_VST3LNd8_UPD /* 3703 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+  ARM_VST3LNq16 /* 3704 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNq16Pseudo /* 3705 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNq16Pseudo_UPD /* 3706 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+  ARM_VST3LNq16_UPD /* 3707 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+  ARM_VST3LNq32 /* 3708 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNq32Pseudo /* 3709 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3LNq32Pseudo_UPD /* 3710 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+  ARM_VST3LNq32_UPD /* 3711 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn */
+  ARM_VST3d16 /* 3712 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3d16Pseudo /* 3713 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3d16Pseudo_UPD /* 3714 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn$Rm */
+  ARM_VST3d16_UPD /* 3715 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn */
+  ARM_VST3d32 /* 3716 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3d32Pseudo /* 3717 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3d32Pseudo_UPD /* 3718 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn$Rm */
+  ARM_VST3d32_UPD /* 3719 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn */
+  ARM_VST3d8 /* 3720 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3d8Pseudo /* 3721 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3d8Pseudo_UPD /* 3722 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn$Rm */
+  ARM_VST3d8_UPD /* 3723 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn */
+  ARM_VST3q16 /* 3724 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q16Pseudo_UPD /* 3725 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn$Rm */
+  ARM_VST3q16_UPD /* 3726 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q16oddPseudo /* 3727 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q16oddPseudo_UPD /* 3728 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn */
+  ARM_VST3q32 /* 3729 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q32Pseudo_UPD /* 3730 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn$Rm */
+  ARM_VST3q32_UPD /* 3731 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q32oddPseudo /* 3732 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q32oddPseudo_UPD /* 3733 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn */
+  ARM_VST3q8 /* 3734 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q8Pseudo_UPD /* 3735 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn$Rm */
+  ARM_VST3q8_UPD /* 3736 */, ARM_INS_VST3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q8oddPseudo /* 3737 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST3q8oddPseudo_UPD /* 3738 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+  ARM_VST4LNd16 /* 3739 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNd16Pseudo /* 3740 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNd16Pseudo_UPD /* 3741 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+  ARM_VST4LNd16_UPD /* 3742 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+  ARM_VST4LNd32 /* 3743 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNd32Pseudo /* 3744 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNd32Pseudo_UPD /* 3745 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+  ARM_VST4LNd32_UPD /* 3746 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+  ARM_VST4LNd8 /* 3747 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNd8Pseudo /* 3748 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNd8Pseudo_UPD /* 3749 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+  ARM_VST4LNd8_UPD /* 3750 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+  ARM_VST4LNq16 /* 3751 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNq16Pseudo /* 3752 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNq16Pseudo_UPD /* 3753 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+  ARM_VST4LNq16_UPD /* 3754 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+  ARM_VST4LNq32 /* 3755 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNq32Pseudo /* 3756 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4LNq32Pseudo_UPD /* 3757 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+  ARM_VST4LNq32_UPD /* 3758 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn */
+  ARM_VST4d16 /* 3759 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4d16Pseudo /* 3760 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4d16Pseudo_UPD /* 3761 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+  ARM_VST4d16_UPD /* 3762 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn */
+  ARM_VST4d32 /* 3763 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4d32Pseudo /* 3764 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4d32Pseudo_UPD /* 3765 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+  ARM_VST4d32_UPD /* 3766 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn */
+  ARM_VST4d8 /* 3767 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4d8Pseudo /* 3768 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4d8Pseudo_UPD /* 3769 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+  ARM_VST4d8_UPD /* 3770 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn */
+  ARM_VST4q16 /* 3771 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q16Pseudo_UPD /* 3772 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+  ARM_VST4q16_UPD /* 3773 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q16oddPseudo /* 3774 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q16oddPseudo_UPD /* 3775 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn */
+  ARM_VST4q32 /* 3776 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q32Pseudo_UPD /* 3777 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+  ARM_VST4q32_UPD /* 3778 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q32oddPseudo /* 3779 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q32oddPseudo_UPD /* 3780 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn */
+  ARM_VST4q8 /* 3781 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q8Pseudo_UPD /* 3782 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+  ARM_VST4q8_UPD /* 3783 */, ARM_INS_VST4,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q8oddPseudo /* 3784 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VST4q8oddPseudo_UPD /* 3785 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vstmdb${p}	$Rn!, $regs */
+  ARM_VSTMDDB_UPD /* 3786 */, ARM_INS_VSTMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstmia${p}	$Rn, $regs */
+  ARM_VSTMDIA /* 3787 */, ARM_INS_VSTMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstmia${p}	$Rn!, $regs */
+  ARM_VSTMDIA_UPD /* 3788 */, ARM_INS_VSTMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VSTMQIA /* 3789 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vstmdb${p}	$Rn!, $regs */
+  ARM_VSTMSDB_UPD /* 3790 */, ARM_INS_VSTMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstmia${p}	$Rn, $regs */
+  ARM_VSTMSIA /* 3791 */, ARM_INS_VSTMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstmia${p}	$Rn!, $regs */
+  ARM_VSTMSIA_UPD /* 3792 */, ARM_INS_VSTMIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	$Dd, $addr */
+  ARM_VSTRD /* 3793 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}.16	$Sd, $addr */
+  ARM_VSTRH /* 3794 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	$Sd, $addr */
+  ARM_VSTRS /* 3795 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFPRegs, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpcxtns, $addr */
+  ARM_VSTR_FPCXTNS_off /* 3796 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpcxtns, $Rn$addr */
+  ARM_VSTR_FPCXTNS_post /* 3797 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpcxtns, $addr! */
+  ARM_VSTR_FPCXTNS_pre /* 3798 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpcxts, $addr */
+  ARM_VSTR_FPCXTS_off /* 3799 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpcxts, $Rn$addr */
+  ARM_VSTR_FPCXTS_post /* 3800 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpcxts, $addr! */
+  ARM_VSTR_FPCXTS_pre /* 3801 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpscr_nzcvqc, $addr */
+  ARM_VSTR_FPSCR_NZCVQC_off /* 3802 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpscr_nzcvqc, $Rn$addr */
+  ARM_VSTR_FPSCR_NZCVQC_post /* 3803 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpscr_nzcvqc, $addr! */
+  ARM_VSTR_FPSCR_NZCVQC_pre /* 3804 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpscr, $addr */
+  ARM_VSTR_FPSCR_off /* 3805 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpscr, $Rn$addr */
+  ARM_VSTR_FPSCR_post /* 3806 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	fpscr, $addr! */
+  ARM_VSTR_FPSCR_pre /* 3807 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_FPSCR, 0 }, { ARM_FEATURE_HasFPRegs, ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	p0, $addr */
+  ARM_VSTR_P0_off /* 3808 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	p0, $Rn$addr */
+  ARM_VSTR_P0_post /* 3809 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	p0, $addr! */
+  ARM_VSTR_P0_pre /* 3810 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	vpr, $addr */
+  ARM_VSTR_VPR_off /* 3811 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	vpr, $Rn$addr */
+  ARM_VSTR_VPR_post /* 3812 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vstr${p}	vpr, $addr! */
+  ARM_VSTR_VPR_pre /* 3813 */, ARM_INS_VSTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_VPR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasMVEInt, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f64	$Dd, $Dn, $Dm */
+  ARM_VSUBD /* 3814 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f16	$Sd, $Sn, $Sm */
+  ARM_VSUBH /* 3815 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubhn${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VSUBHNv2i32 /* 3816 */, ARM_INS_VSUBHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubhn${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VSUBHNv4i16 /* 3817 */, ARM_INS_VSUBHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubhn${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VSUBHNv8i8 /* 3818 */, ARM_INS_VSUBHN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubl${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VSUBLsv2i64 /* 3819 */, ARM_INS_VSUBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubl${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VSUBLsv4i32 /* 3820 */, ARM_INS_VSUBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubl${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VSUBLsv8i16 /* 3821 */, ARM_INS_VSUBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubl${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VSUBLuv2i64 /* 3822 */, ARM_INS_VSUBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubl${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VSUBLuv4i32 /* 3823 */, ARM_INS_VSUBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubl${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VSUBLuv8i16 /* 3824 */, ARM_INS_VSUBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f32	$Sd, $Sn, $Sm */
+  ARM_VSUBS /* 3825 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubw${p}.s32	$Vd, $Vn, $Vm */
+  ARM_VSUBWsv2i64 /* 3826 */, ARM_INS_VSUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubw${p}.s16	$Vd, $Vn, $Vm */
+  ARM_VSUBWsv4i32 /* 3827 */, ARM_INS_VSUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubw${p}.s8	$Vd, $Vn, $Vm */
+  ARM_VSUBWsv8i16 /* 3828 */, ARM_INS_VSUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubw${p}.u32	$Vd, $Vn, $Vm */
+  ARM_VSUBWuv2i64 /* 3829 */, ARM_INS_VSUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubw${p}.u16	$Vd, $Vn, $Vm */
+  ARM_VSUBWuv4i32 /* 3830 */, ARM_INS_VSUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsubw${p}.u8	$Vd, $Vn, $Vm */
+  ARM_VSUBWuv8i16 /* 3831 */, ARM_INS_VSUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VSUBfd /* 3832 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f32	$Vd, $Vn, $Vm */
+  ARM_VSUBfq /* 3833 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VSUBhd /* 3834 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.f16	$Vd, $Vn, $Vm */
+  ARM_VSUBhq /* 3835 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VSUBv16i8 /* 3836 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VSUBv1i64 /* 3837 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VSUBv2i32 /* 3838 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i64	$Vd, $Vn, $Vm */
+  ARM_VSUBv2i64 /* 3839 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VSUBv4i16 /* 3840 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i32	$Vd, $Vn, $Vm */
+  ARM_VSUBv4i32 /* 3841 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i16	$Vd, $Vn, $Vm */
+  ARM_VSUBv8i16 /* 3842 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsub${p}.i8	$Vd, $Vn, $Vm */
+  ARM_VSUBv8i8 /* 3843 */, ARM_INS_VSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsudot.u8	$Vd, $Vn, $Vm$lane */
+  ARM_VSUDOTDI /* 3844 */, ARM_INS_VSUDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vsudot.u8	$Vd, $Vn, $Vm$lane */
+  ARM_VSUDOTQI /* 3845 */, ARM_INS_VSUDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vswp${p}	$Vd, $Vm */
+  ARM_VSWPd /* 3846 */, ARM_INS_VSWP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vswp${p}	$Vd, $Vm */
+  ARM_VSWPq /* 3847 */, ARM_INS_VSWP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbl${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBL1 /* 3848 */, ARM_INS_VTBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbl${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBL2 /* 3849 */, ARM_INS_VTBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbl${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBL3 /* 3850 */, ARM_INS_VTBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VTBL3Pseudo /* 3851 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbl${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBL4 /* 3852 */, ARM_INS_VTBL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VTBL4Pseudo /* 3853 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbx${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBX1 /* 3854 */, ARM_INS_VTBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbx${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBX2 /* 3855 */, ARM_INS_VTBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbx${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBX3 /* 3856 */, ARM_INS_VTBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VTBX3Pseudo /* 3857 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vtbx${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTBX4 /* 3858 */, ARM_INS_VTBX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_VTBX4Pseudo /* 3859 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f64	$dst, $a, $fbits */
+  ARM_VTOSHD /* 3860 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f16	$dst, $a, $fbits */
+  ARM_VTOSHH /* 3861 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s16.f32	$dst, $a, $fbits */
+  ARM_VTOSHS /* 3862 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtr${p}.s32.f64	$Sd, $Dm */
+  ARM_VTOSIRD /* 3863 */, ARM_INS_VCVTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtr${p}.s32.f16	$Sd, $Sm */
+  ARM_VTOSIRH /* 3864 */, ARM_INS_VCVTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtr${p}.s32.f32	$Sd, $Sm */
+  ARM_VTOSIRS /* 3865 */, ARM_INS_VCVTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f64	$Sd, $Dm */
+  ARM_VTOSIZD /* 3866 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f16	$Sd, $Sm */
+  ARM_VTOSIZH /* 3867 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f32	$Sd, $Sm */
+  ARM_VTOSIZS /* 3868 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f64	$dst, $a, $fbits */
+  ARM_VTOSLD /* 3869 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f16	$dst, $a, $fbits */
+  ARM_VTOSLH /* 3870 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.s32.f32	$dst, $a, $fbits */
+  ARM_VTOSLS /* 3871 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f64	$dst, $a, $fbits */
+  ARM_VTOUHD /* 3872 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f16	$dst, $a, $fbits */
+  ARM_VTOUHH /* 3873 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u16.f32	$dst, $a, $fbits */
+  ARM_VTOUHS /* 3874 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtr${p}.u32.f64	$Sd, $Dm */
+  ARM_VTOUIRD /* 3875 */, ARM_INS_VCVTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtr${p}.u32.f16	$Sd, $Sm */
+  ARM_VTOUIRH /* 3876 */, ARM_INS_VCVTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvtr${p}.u32.f32	$Sd, $Sm */
+  ARM_VTOUIRS /* 3877 */, ARM_INS_VCVTR,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_FPSCR, 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f64	$Sd, $Dm */
+  ARM_VTOUIZD /* 3878 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f16	$Sd, $Sm */
+  ARM_VTOUIZH /* 3879 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f32	$Sd, $Sm */
+  ARM_VTOUIZS /* 3880 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f64	$dst, $a, $fbits */
+  ARM_VTOULD /* 3881 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f16	$dst, $a, $fbits */
+  ARM_VTOULH /* 3882 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.u32.f32	$dst, $a, $fbits */
+  ARM_VTOULS /* 3883 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtrn${p}.16	$Vd, $Vm */
+  ARM_VTRNd16 /* 3884 */, ARM_INS_VTRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtrn${p}.32	$Vd, $Vm */
+  ARM_VTRNd32 /* 3885 */, ARM_INS_VTRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtrn${p}.8	$Vd, $Vm */
+  ARM_VTRNd8 /* 3886 */, ARM_INS_VTRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtrn${p}.16	$Vd, $Vm */
+  ARM_VTRNq16 /* 3887 */, ARM_INS_VTRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtrn${p}.32	$Vd, $Vm */
+  ARM_VTRNq32 /* 3888 */, ARM_INS_VTRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtrn${p}.8	$Vd, $Vm */
+  ARM_VTRNq8 /* 3889 */, ARM_INS_VTRN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtst${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTSTv16i8 /* 3890 */, ARM_INS_VTST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtst${p}.32	$Vd, $Vn, $Vm */
+  ARM_VTSTv2i32 /* 3891 */, ARM_INS_VTST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtst${p}.16	$Vd, $Vn, $Vm */
+  ARM_VTSTv4i16 /* 3892 */, ARM_INS_VTST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtst${p}.32	$Vd, $Vn, $Vm */
+  ARM_VTSTv4i32 /* 3893 */, ARM_INS_VTST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtst${p}.16	$Vd, $Vn, $Vm */
+  ARM_VTSTv8i16 /* 3894 */, ARM_INS_VTST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vtst${p}.8	$Vd, $Vn, $Vm */
+  ARM_VTSTv8i8 /* 3895 */, ARM_INS_VTST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vudot.u8	$Vd, $Vn, $Vm */
+  ARM_VUDOTD /* 3896 */, ARM_INS_VUDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vudot.u8	$Vd, $Vn, $Vm$lane */
+  ARM_VUDOTDI /* 3897 */, ARM_INS_VUDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vudot.u8	$Vd, $Vn, $Vm */
+  ARM_VUDOTQ /* 3898 */, ARM_INS_VUDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vudot.u8	$Vd, $Vn, $Vm$lane */
+  ARM_VUDOTQI /* 3899 */, ARM_INS_VUDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDotProd, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.u16	$dst, $a, $fbits */
+  ARM_VUHTOD /* 3900 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u16	$dst, $a, $fbits */
+  ARM_VUHTOH /* 3901 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u16	$dst, $a, $fbits */
+  ARM_VUHTOS /* 3902 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.u32	$Dd, $Sm */
+  ARM_VUITOD /* 3903 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u32	$Sd, $Sm */
+  ARM_VUITOH /* 3904 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u32	$Sd, $Sm */
+  ARM_VUITOS /* 3905 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f64.u32	$dst, $a, $fbits */
+  ARM_VULTOD /* 3906 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, ARM_FEATURE_HasDPVFP, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f16.u32	$dst, $a, $fbits */
+  ARM_VULTOH /* 3907 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasFullFP16, 0 }, 0, 0
+  #endif
+},
+{
+  /* vcvt${p}.f32.u32	$dst, $a, $fbits */
+  ARM_VULTOS /* 3908 */, ARM_INS_VCVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasVFP2, 0 }, 0, 0
+  #endif
+},
+{
+  /* vummla.u8	$Vd, $Vn, $Vm */
+  ARM_VUMMLA /* 3909 */, ARM_INS_VUMMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vusdot.s8	$Vd, $Vn, $Vm */
+  ARM_VUSDOTD /* 3910 */, ARM_INS_VUSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vusdot.s8	$Vd, $Vn, $Vm$lane */
+  ARM_VUSDOTDI /* 3911 */, ARM_INS_VUSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vusdot.s8	$Vd, $Vn, $Vm */
+  ARM_VUSDOTQ /* 3912 */, ARM_INS_VUSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vusdot.s8	$Vd, $Vn, $Vm$lane */
+  ARM_VUSDOTQI /* 3913 */, ARM_INS_VUSDOT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vusmmla.s8	$Vd, $Vn, $Vm */
+  ARM_VUSMMLA /* 3914 */, ARM_INS_VUSMMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasMatMulInt8, 0 }, 0, 0
+  #endif
+},
+{
+  /* vuzp${p}.16	$Vd, $Vm */
+  ARM_VUZPd16 /* 3915 */, ARM_INS_VUZP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vuzp${p}.8	$Vd, $Vm */
+  ARM_VUZPd8 /* 3916 */, ARM_INS_VUZP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vuzp${p}.16	$Vd, $Vm */
+  ARM_VUZPq16 /* 3917 */, ARM_INS_VUZP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vuzp${p}.32	$Vd, $Vm */
+  ARM_VUZPq32 /* 3918 */, ARM_INS_VUZP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vuzp${p}.8	$Vd, $Vm */
+  ARM_VUZPq8 /* 3919 */, ARM_INS_VUZP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vzip${p}.16	$Vd, $Vm */
+  ARM_VZIPd16 /* 3920 */, ARM_INS_VZIP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vzip${p}.8	$Vd, $Vm */
+  ARM_VZIPd8 /* 3921 */, ARM_INS_VZIP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vzip${p}.16	$Vd, $Vm */
+  ARM_VZIPq16 /* 3922 */, ARM_INS_VZIP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vzip${p}.32	$Vd, $Vm */
+  ARM_VZIPq32 /* 3923 */, ARM_INS_VZIP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* vzip${p}.8	$Vd, $Vm */
+  ARM_VZIPq8 /* 3924 */, ARM_INS_VZIP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasNEON, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmda${p}	$Rn, $regs ^ */
+  ARM_sysLDMDA /* 3925 */, ARM_INS_LDMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmda${p}	$Rn!, $regs ^ */
+  ARM_sysLDMDA_UPD /* 3926 */, ARM_INS_LDMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmdb${p}	$Rn, $regs ^ */
+  ARM_sysLDMDB /* 3927 */, ARM_INS_LDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmdb${p}	$Rn!, $regs ^ */
+  ARM_sysLDMDB_UPD /* 3928 */, ARM_INS_LDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}	$Rn, $regs ^ */
+  ARM_sysLDMIA /* 3929 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}	$Rn!, $regs ^ */
+  ARM_sysLDMIA_UPD /* 3930 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmib${p}	$Rn, $regs ^ */
+  ARM_sysLDMIB /* 3931 */, ARM_INS_LDMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmib${p}	$Rn!, $regs ^ */
+  ARM_sysLDMIB_UPD /* 3932 */, ARM_INS_LDMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmda${p}	$Rn, $regs ^ */
+  ARM_sysSTMDA /* 3933 */, ARM_INS_STMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmda${p}	$Rn!, $regs ^ */
+  ARM_sysSTMDA_UPD /* 3934 */, ARM_INS_STMDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmdb${p}	$Rn, $regs ^ */
+  ARM_sysSTMDB /* 3935 */, ARM_INS_STMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmdb${p}	$Rn!, $regs ^ */
+  ARM_sysSTMDB_UPD /* 3936 */, ARM_INS_STMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}	$Rn, $regs ^ */
+  ARM_sysSTMIA /* 3937 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}	$Rn!, $regs ^ */
+  ARM_sysSTMIA_UPD /* 3938 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmib${p}	$Rn, $regs ^ */
+  ARM_sysSTMIB /* 3939 */, ARM_INS_STMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmib${p}	$Rn!, $regs ^ */
+  ARM_sysSTMIB_UPD /* 3940 */, ARM_INS_STMIB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsARM, 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2ADCri /* 3941 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2ADCrr /* 3942 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* adc${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2ADCrs /* 3943 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}.w	$Rd, $Rn, $imm */
+  ARM_t2ADDri /* 3944 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* addw${p}	$Rd, $Rn, $imm */
+  ARM_t2ADDri12 /* 3945 */, ARM_INS_ADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2ADDrr /* 3946 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2ADDrs /* 3947 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}.w	$Rd, $Rn, $imm */
+  ARM_t2ADDspImm /* 3948 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* addw${p}	$Rd, $Rn, $imm */
+  ARM_t2ADDspImm12 /* 3949 */, ARM_INS_ADDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* adr{$p}.w	$Rd, $addr */
+  ARM_t2ADR /* 3950 */, ARM_INS_ADR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2ANDri /* 3951 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2ANDrr /* 3952 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2ANDrs /* 3953 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* asr${s}${p}.w	$Rd, $Rm, $imm */
+  ARM_t2ASRri /* 3954 */, ARM_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* asr${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2ASRrr /* 3955 */, ARM_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* aut	r12, lr, sp */
+  ARM_t2AUT /* 3956 */, ARM_INS_AUT,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_R12, ARM_REG_LR, ARM_REG_SP, 0 }, { 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* autg${p}	$Ra, $Rn, $Rm */
+  ARM_t2AUTG /* 3957 */, ARM_INS_AUTG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasPACBTI, 0 }, 0, 0
+  #endif
+},
+{
+  /* b${p}.w	$target */
+  ARM_t2B /* 3958 */, ARM_INS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 1, 0
+  #endif
+},
+{
+  /* bfc${p}	$Rd, $imm */
+  ARM_t2BFC /* 3959 */, ARM_INS_BFC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bfi${p}	$Rd, $Rn, $imm */
+  ARM_t2BFI /* 3960 */, ARM_INS_BFI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bfl${p}	$b_label, $label */
+  ARM_t2BFLi /* 3961 */, ARM_INS_BFL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0
+  #endif
+},
+{
+  /* bflx${p}	$b_label, $Rn */
+  ARM_t2BFLr /* 3962 */, ARM_INS_BFLX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0
+  #endif
+},
+{
+  /* bf${p}	$b_label, $label */
+  ARM_t2BFi /* 3963 */, ARM_INS_BF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0
+  #endif
+},
+{
+  /* bfcsel	$b_label, $label, $ba_label, $bcond */
+  ARM_t2BFic /* 3964 */, ARM_INS_BFCSEL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0
+  #endif
+},
+{
+  /* bfx${p}	$b_label, $Rn */
+  ARM_t2BFr /* 3965 */, ARM_INS_BFX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2BICri /* 3966 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2BICrr /* 3967 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bic${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2BICrs /* 3968 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* bti	 */
+  ARM_t2BTI /* 3969 */, ARM_INS_BTI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* bxaut${p}	$Ra, $Rn, $Rm */
+  ARM_t2BXAUT /* 3970 */, ARM_INS_BXAUT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasPACBTI, 0 }, 1, 1
+  #endif
+},
+{
+  /* bxj${p}	$func */
+  ARM_t2BXJ /* 3971 */, ARM_INS_BXJ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 1, 1
+  #endif
+},
+{
+  /* b${p}.w	$target */
+  ARM_t2Bcc /* 3972 */, ARM_INS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, 0 }, 1, 0
+  #endif
+},
+{
+  /* cdp${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+  ARM_t2CDP /* 3973 */, ARM_INS_CDP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* cdp2${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+  ARM_t2CDP2 /* 3974 */, ARM_INS_CDP2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* clrex${p} */
+  ARM_t2CLREX /* 3975 */, ARM_INS_CLREX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* clrm${p}	$regs */
+  ARM_t2CLRM /* 3976 */, ARM_INS_CLRM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* clz${p}	$Rd, $Rm */
+  ARM_t2CLZ /* 3977 */, ARM_INS_CLZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}.w	$Rn, $imm */
+  ARM_t2CMNri /* 3978 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}.w	$Rn, $Rm */
+  ARM_t2CMNzrr /* 3979 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmn${p}.w	$Rn, $ShiftedRm */
+  ARM_t2CMNzrs /* 3980 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}.w	$Rn, $imm */
+  ARM_t2CMPri /* 3981 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}.w	$Rn, $Rm */
+  ARM_t2CMPrr /* 3982 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}.w	$Rn, $ShiftedRm */
+  ARM_t2CMPrs /* 3983 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps	$mode */
+  ARM_t2CPS1p /* 3984 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps$imod.w	$iflags */
+  ARM_t2CPS2p /* 3985 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps$imod	$iflags, $mode */
+  ARM_t2CPS3p /* 3986 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32b	$Rd, $Rn, $Rm */
+  ARM_t2CRC32B /* 3987 */, ARM_INS_CRC32B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32cb	$Rd, $Rn, $Rm */
+  ARM_t2CRC32CB /* 3988 */, ARM_INS_CRC32CB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32ch	$Rd, $Rn, $Rm */
+  ARM_t2CRC32CH /* 3989 */, ARM_INS_CRC32CH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32cw	$Rd, $Rn, $Rm */
+  ARM_t2CRC32CW /* 3990 */, ARM_INS_CRC32CW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32h	$Rd, $Rn, $Rm */
+  ARM_t2CRC32H /* 3991 */, ARM_INS_CRC32H,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* crc32w	$Rd, $Rn, $Rm */
+  ARM_t2CRC32W /* 3992 */, ARM_INS_CRC32W,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasCRC, 0 }, 0, 0
+  #endif
+},
+{
+  /* csel	$Rd, $Rn, $Rm, $fcond */
+  ARM_t2CSEL /* 3993 */, ARM_INS_CSEL,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* csinc	$Rd, $Rn, $Rm, $fcond */
+  ARM_t2CSINC /* 3994 */, ARM_INS_CSINC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* csinv	$Rd, $Rn, $Rm, $fcond */
+  ARM_t2CSINV /* 3995 */, ARM_INS_CSINV,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* csneg	$Rd, $Rn, $Rm, $fcond */
+  ARM_t2CSNEG /* 3996 */, ARM_INS_CSNEG,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_HasV8_1MMainline, 0 }, 0, 0
+  #endif
+},
+{
+  /* dbg${p}	$opt */
+  ARM_t2DBG /* 3997 */, ARM_INS_DBG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* dcps1${p} */
+  ARM_t2DCPS1 /* 3998 */, ARM_INS_DCPS1,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* dcps2${p} */
+  ARM_t2DCPS2 /* 3999 */, ARM_INS_DCPS2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* dcps3${p} */
+  ARM_t2DCPS3 /* 4000 */, ARM_INS_DCPS3,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* dls	$LR, $Rn */
+  ARM_t2DLS /* 4001 */, ARM_INS_DLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 0, 0
+  #endif
+},
+{
+  /* dmb${p}	$opt */
+  ARM_t2DMB /* 4002 */, ARM_INS_DMB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasDB, 0 }, 0, 0
+  #endif
+},
+{
+  /* dsb${p}	$opt */
+  ARM_t2DSB /* 4003 */, ARM_INS_DSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasDB, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2EORri /* 4004 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2EORrr /* 4005 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2EORrs /* 4006 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* hint${p}.w	$imm */
+  ARM_t2HINT /* 4007 */, ARM_INS_HINT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* hvc.w	$imm16 */
+  ARM_t2HVC /* 4008 */, ARM_INS_HVC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* isb${p}	$opt */
+  ARM_t2ISB /* 4009 */, ARM_INS_ISB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasDB, 0 }, 0, 0
+  #endif
+},
+{
+  /* it$mask	$cc */
+  ARM_t2IT /* 4010 */, ARM_INS_IT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_ITSTATE, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2Int_eh_sjlj_setjmp /* 4011 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_t2Int_eh_sjlj_setjmp_nofp /* 4012 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* lda${p}	$Rt, $addr */
+  ARM_t2LDA /* 4013 */, ARM_INS_LDA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldab${p}	$Rt, $addr */
+  ARM_t2LDAB /* 4014 */, ARM_INS_LDAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaex${p}	$Rt, $addr */
+  ARM_t2LDAEX /* 4015 */, ARM_INS_LDAEX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaexb${p}	$Rt, $addr */
+  ARM_t2LDAEXB /* 4016 */, ARM_INS_LDAEXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaexd${p}	$Rt, $Rt2, $addr */
+  ARM_t2LDAEXD /* 4017 */, ARM_INS_LDAEXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldaexh${p}	$Rt, $addr */
+  ARM_t2LDAEXH /* 4018 */, ARM_INS_LDAEXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldah${p}	$Rt, $addr */
+  ARM_t2LDAH /* 4019 */, ARM_INS_LDAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l${p}	$cop, $CRd, $addr */
+  ARM_t2LDC2L_OFFSET /* 4020 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l${p}	$cop, $CRd, $addr, $option */
+  ARM_t2LDC2L_OPTION /* 4021 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2LDC2L_POST /* 4022 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2l${p}	$cop, $CRd, $addr! */
+  ARM_t2LDC2L_PRE /* 4023 */, ARM_INS_LDC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2${p}	$cop, $CRd, $addr */
+  ARM_t2LDC2_OFFSET /* 4024 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2${p}	$cop, $CRd, $addr, $option */
+  ARM_t2LDC2_OPTION /* 4025 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2LDC2_POST /* 4026 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc2${p}	$cop, $CRd, $addr! */
+  ARM_t2LDC2_PRE /* 4027 */, ARM_INS_LDC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr */
+  ARM_t2LDCL_OFFSET /* 4028 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr, $option */
+  ARM_t2LDCL_OPTION /* 4029 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2LDCL_POST /* 4030 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldcl${p}	$cop, $CRd, $addr! */
+  ARM_t2LDCL_PRE /* 4031 */, ARM_INS_LDCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr */
+  ARM_t2LDC_OFFSET /* 4032 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr, $option */
+  ARM_t2LDC_OPTION /* 4033 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2LDC_POST /* 4034 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldc${p}	$cop, $CRd, $addr! */
+  ARM_t2LDC_PRE /* 4035 */, ARM_INS_LDC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmdb${p}	$Rn, $regs */
+  ARM_t2LDMDB /* 4036 */, ARM_INS_LDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldmdb${p}	$Rn!, $regs */
+  ARM_t2LDMDB_UPD /* 4037 */, ARM_INS_LDMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}.w	$Rn, $regs */
+  ARM_t2LDMIA /* 4038 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}.w	$Rn!, $regs */
+  ARM_t2LDMIA_UPD /* 4039 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrbt${p}	$Rt, $addr */
+  ARM_t2LDRBT /* 4040 */, ARM_INS_LDRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $Rn$offset */
+  ARM_t2LDRB_POST /* 4041 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr! */
+  ARM_t2LDRB_PRE /* 4042 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}.w	$Rt, $addr */
+  ARM_t2LDRBi12 /* 4043 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr */
+  ARM_t2LDRBi8 /* 4044 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}.w	$Rt, $addr */
+  ARM_t2LDRBpci /* 4045 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}.w	$Rt, $addr */
+  ARM_t2LDRBs /* 4046 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrd${p}	$Rt, $Rt2, $addr$imm */
+  ARM_t2LDRD_POST /* 4047 */, ARM_INS_LDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrd${p}	$Rt, $Rt2, $addr! */
+  ARM_t2LDRD_PRE /* 4048 */, ARM_INS_LDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrd${p}	$Rt, $Rt2, $addr */
+  ARM_t2LDRDi8 /* 4049 */, ARM_INS_LDRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrex${p}	$Rt, $addr */
+  ARM_t2LDREX /* 4050 */, ARM_INS_LDREX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrexb${p}	$Rt, $addr */
+  ARM_t2LDREXB /* 4051 */, ARM_INS_LDREXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrexd${p}	$Rt, $Rt2, $addr */
+  ARM_t2LDREXD /* 4052 */, ARM_INS_LDREXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrexh${p}	$Rt, $addr */
+  ARM_t2LDREXH /* 4053 */, ARM_INS_LDREXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrht${p}	$Rt, $addr */
+  ARM_t2LDRHT /* 4054 */, ARM_INS_LDRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $Rn$offset */
+  ARM_t2LDRH_POST /* 4055 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr! */
+  ARM_t2LDRH_PRE /* 4056 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}.w	$Rt, $addr */
+  ARM_t2LDRHi12 /* 4057 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr */
+  ARM_t2LDRHi8 /* 4058 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}.w	$Rt, $addr */
+  ARM_t2LDRHpci /* 4059 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}.w	$Rt, $addr */
+  ARM_t2LDRHs /* 4060 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsbt${p}	$Rt, $addr */
+  ARM_t2LDRSBT /* 4061 */, ARM_INS_LDRSBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $Rn$offset */
+  ARM_t2LDRSB_POST /* 4062 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $addr! */
+  ARM_t2LDRSB_PRE /* 4063 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}.w	$Rt, $addr */
+  ARM_t2LDRSBi12 /* 4064 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $addr */
+  ARM_t2LDRSBi8 /* 4065 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}.w	$Rt, $addr */
+  ARM_t2LDRSBpci /* 4066 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}.w	$Rt, $addr */
+  ARM_t2LDRSBs /* 4067 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsht${p}	$Rt, $addr */
+  ARM_t2LDRSHT /* 4068 */, ARM_INS_LDRSHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $Rn$offset */
+  ARM_t2LDRSH_POST /* 4069 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $addr! */
+  ARM_t2LDRSH_PRE /* 4070 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}.w	$Rt, $addr */
+  ARM_t2LDRSHi12 /* 4071 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $addr */
+  ARM_t2LDRSHi8 /* 4072 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}.w	$Rt, $addr */
+  ARM_t2LDRSHpci /* 4073 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}.w	$Rt, $addr */
+  ARM_t2LDRSHs /* 4074 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrt${p}	$Rt, $addr */
+  ARM_t2LDRT /* 4075 */, ARM_INS_LDRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $Rn$offset */
+  ARM_t2LDR_POST /* 4076 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr! */
+  ARM_t2LDR_PRE /* 4077 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}.w	$Rt, $addr */
+  ARM_t2LDRi12 /* 4078 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_t2LDRi8 /* 4079 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}.w	$Rt, $addr */
+  ARM_t2LDRpci /* 4080 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}.w	$Rt, $addr */
+  ARM_t2LDRs /* 4081 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* le	$label */
+  ARM_t2LE /* 4082 */, ARM_INS_LE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 1, 0
+  #endif
+},
+{
+  /* le	$LRin, $label */
+  ARM_t2LEUpdate /* 4083 */, ARM_INS_LE,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 1, 0
+  #endif
+},
+{
+  /* lsl${s}${p}.w	$Rd, $Rm, $imm */
+  ARM_t2LSLri /* 4084 */, ARM_INS_LSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsl${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2LSLrr /* 4085 */, ARM_INS_LSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsr${s}${p}.w	$Rd, $Rm, $imm */
+  ARM_t2LSRri /* 4086 */, ARM_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsr${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2LSRrr /* 4087 */, ARM_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcr${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_t2MCR /* 4088 */, ARM_INS_MCR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcr2${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_t2MCR2 /* 4089 */, ARM_INS_MCR2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcrr${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_t2MCRR /* 4090 */, ARM_INS_MCRR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mcrr2${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_t2MCRR2 /* 4091 */, ARM_INS_MCRR2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mla${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2MLA /* 4092 */, ARM_INS_MLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mls${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2MLS /* 4093 */, ARM_INS_MLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* movt${p}	$Rd, $imm */
+  ARM_t2MOVTi16 /* 4094 */, ARM_INS_MOVT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}.w	$Rd, $imm */
+  ARM_t2MOVi /* 4095 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* movw${p}	$Rd, $imm */
+  ARM_t2MOVi16 /* 4096 */, ARM_INS_MOVW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}.w	$Rd, $Rm */
+  ARM_t2MOVr /* 4097 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* asrs${p}.w	$Rd, $Rm, #1 */
+  ARM_t2MOVsra_flag /* 4098 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* lsrs${p}.w	$Rd, $Rm, #1 */
+  ARM_t2MOVsrl_flag /* 4099 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* mrc${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_t2MRC /* 4100 */, ARM_INS_MRC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrc2${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+  ARM_t2MRC2 /* 4101 */, ARM_INS_MRC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrrc${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_t2MRRC /* 4102 */, ARM_INS_MRRC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrrc2${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+  ARM_t2MRRC2 /* 4103 */, ARM_INS_MRRC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_PreV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, apsr */
+  ARM_t2MRS_AR /* 4104 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, $SYSm */
+  ARM_t2MRS_M /* 4105 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_IsMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, $banked */
+  ARM_t2MRSbanked /* 4106 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* mrs${p}	$Rd, spsr */
+  ARM_t2MRSsys_AR /* 4107 */, ARM_INS_MRS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* msr${p}	$mask, $Rn */
+  ARM_t2MSR_AR /* 4108 */, ARM_INS_MSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* msr${p}	$SYSm, $Rn */
+  ARM_t2MSR_M /* 4109 */, ARM_INS_MSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_IsMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* msr${p}	$banked, $Rn */
+  ARM_t2MSRbanked /* 4110 */, ARM_INS_MSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasVirtualization, 0 }, 0, 0
+  #endif
+},
+{
+  /* mul${p}	$Rd, $Rn, $Rm */
+  ARM_t2MUL /* 4111 */, ARM_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}	$Rd, $imm */
+  ARM_t2MVNi /* 4112 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}.w	$Rd, $Rm */
+  ARM_t2MVNr /* 4113 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}.w	$Rd, $ShiftedRm */
+  ARM_t2MVNs /* 4114 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* orn${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2ORNri /* 4115 */, ARM_INS_ORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* orn${s}${p}	$Rd, $Rn, $Rm */
+  ARM_t2ORNrr /* 4116 */, ARM_INS_ORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* orn${s}${p}	$Rd, $Rn, $ShiftedRm */
+  ARM_t2ORNrs /* 4117 */, ARM_INS_ORN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2ORRri /* 4118 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2ORRrr /* 4119 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2ORRrs /* 4120 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pac	r12, lr, sp */
+  ARM_t2PAC /* 4121 */, ARM_INS_PAC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_LR, ARM_REG_SP, 0 }, { ARM_REG_R12, 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* pacbti	r12, lr, sp */
+  ARM_t2PACBTI /* 4122 */, ARM_INS_PACBTI,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_LR, ARM_REG_SP, 0 }, { ARM_REG_R12, 0 }, { ARM_FEATURE_HasV7, ARM_FEATURE_IsMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* pacg${p}	$Rd, $Rn, $Rm */
+  ARM_t2PACG /* 4123 */, ARM_INS_PACG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasPACBTI, 0 }, 0, 0
+  #endif
+},
+{
+  /* pkhbt${p}	$Rd, $Rn, $Rm$sh */
+  ARM_t2PKHBT /* 4124 */, ARM_INS_PKHBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pkhtb${p}	$Rd, $Rn, $Rm$sh */
+  ARM_t2PKHTB /* 4125 */, ARM_INS_PKHTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pldw${p}	$addr */
+  ARM_t2PLDWi12 /* 4126 */, ARM_INS_PLDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0
+  #endif
+},
+{
+  /* pldw${p}	$addr */
+  ARM_t2PLDWi8 /* 4127 */, ARM_INS_PLDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0
+  #endif
+},
+{
+  /* pldw${p}	$addr */
+  ARM_t2PLDWs /* 4128 */, ARM_INS_PLDW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, ARM_FEATURE_HasMP, 0 }, 0, 0
+  #endif
+},
+{
+  /* pld${p}	$addr */
+  ARM_t2PLDi12 /* 4129 */, ARM_INS_PLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pld${p}	$addr */
+  ARM_t2PLDi8 /* 4130 */, ARM_INS_PLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pld${p}	$addr */
+  ARM_t2PLDpci /* 4131 */, ARM_INS_PLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pld${p}	$addr */
+  ARM_t2PLDs /* 4132 */, ARM_INS_PLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* pli${p}	$addr */
+  ARM_t2PLIi12 /* 4133 */, ARM_INS_PLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* pli${p}	$addr */
+  ARM_t2PLIi8 /* 4134 */, ARM_INS_PLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* pli${p}	$addr */
+  ARM_t2PLIpci /* 4135 */, ARM_INS_PLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* pli${p}	$addr */
+  ARM_t2PLIs /* 4136 */, ARM_INS_PLI,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV7, 0 }, 0, 0
+  #endif
+},
+{
+  /* qadd${p}	$Rd, $Rm, $Rn */
+  ARM_t2QADD /* 4137 */, ARM_INS_QADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qadd16${p}	$Rd, $Rn, $Rm */
+  ARM_t2QADD16 /* 4138 */, ARM_INS_QADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qadd8${p}	$Rd, $Rn, $Rm */
+  ARM_t2QADD8 /* 4139 */, ARM_INS_QADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qasx${p}	$Rd, $Rn, $Rm */
+  ARM_t2QASX /* 4140 */, ARM_INS_QASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qdadd${p}	$Rd, $Rm, $Rn */
+  ARM_t2QDADD /* 4141 */, ARM_INS_QDADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qdsub${p}	$Rd, $Rm, $Rn */
+  ARM_t2QDSUB /* 4142 */, ARM_INS_QDSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsax${p}	$Rd, $Rn, $Rm */
+  ARM_t2QSAX /* 4143 */, ARM_INS_QSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsub${p}	$Rd, $Rm, $Rn */
+  ARM_t2QSUB /* 4144 */, ARM_INS_QSUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsub16${p}	$Rd, $Rn, $Rm */
+  ARM_t2QSUB16 /* 4145 */, ARM_INS_QSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* qsub8${p}	$Rd, $Rn, $Rm */
+  ARM_t2QSUB8 /* 4146 */, ARM_INS_QSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* rbit${p}	$Rd, $Rm */
+  ARM_t2RBIT /* 4147 */, ARM_INS_RBIT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rev${p}.w	$Rd, $Rm */
+  ARM_t2REV /* 4148 */, ARM_INS_REV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rev16${p}.w	$Rd, $Rm */
+  ARM_t2REV16 /* 4149 */, ARM_INS_REV16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* revsh${p}.w	$Rd, $Rm */
+  ARM_t2REVSH /* 4150 */, ARM_INS_REVSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfedb${p}	$Rn */
+  ARM_t2RFEDB /* 4151 */, ARM_INS_RFEDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_PC, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfedb${p}	$Rn! */
+  ARM_t2RFEDBW /* 4152 */, ARM_INS_RFEDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_PC, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeia${p}	$Rn */
+  ARM_t2RFEIA /* 4153 */, ARM_INS_RFEIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_PC, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* rfeia${p}	$Rn! */
+  ARM_t2RFEIAW /* 4154 */, ARM_INS_RFEIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_PC, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* ror${s}${p}.w	$Rd, $Rm, $imm */
+  ARM_t2RORri /* 4155 */, ARM_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ror${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2RORrr /* 4156 */, ARM_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rrx${s}${p}	$Rd, $Rm */
+  ARM_t2RRX /* 4157 */, ARM_INS_RRX,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}.w	$Rd, $Rn, $imm */
+  ARM_t2RSBri /* 4158 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, $Rm */
+  ARM_t2RSBrr /* 4159 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, $ShiftedRm */
+  ARM_t2RSBrs /* 4160 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sadd16${p}	$Rd, $Rn, $Rm */
+  ARM_t2SADD16 /* 4161 */, ARM_INS_SADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* sadd8${p}	$Rd, $Rn, $Rm */
+  ARM_t2SADD8 /* 4162 */, ARM_INS_SADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* sasx${p}	$Rd, $Rn, $Rm */
+  ARM_t2SASX /* 4163 */, ARM_INS_SASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* sb */
+  ARM_t2SB /* 4164 */, ARM_INS_SB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasSB, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}	$Rd, $Rn, $imm */
+  ARM_t2SBCri /* 4165 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2SBCrr /* 4166 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2SBCrs /* 4167 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbfx${p}	$Rd, $Rn, $lsb, $msb */
+  ARM_t2SBFX /* 4168 */, ARM_INS_SBFX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sdiv${p}	$Rd, $Rn, $Rm */
+  ARM_t2SDIV /* 4169 */, ARM_INS_SDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* sel${p}	$Rd, $Rn, $Rm */
+  ARM_t2SEL /* 4170 */, ARM_INS_SEL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* setpan	$imm */
+  ARM_t2SETPAN /* 4171 */, ARM_INS_SETPAN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8, ARM_FEATURE_HasV8_1a, 0 }, 0, 0
+  #endif
+},
+{
+  /* sg${p} */
+  ARM_t2SG /* 4172 */, ARM_INS_SG,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* shadd16${p}	$Rd, $Rn, $Rm */
+  ARM_t2SHADD16 /* 4173 */, ARM_INS_SHADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* shadd8${p}	$Rd, $Rn, $Rm */
+  ARM_t2SHADD8 /* 4174 */, ARM_INS_SHADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* shasx${p}	$Rd, $Rn, $Rm */
+  ARM_t2SHASX /* 4175 */, ARM_INS_SHASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* shsax${p}	$Rd, $Rn, $Rm */
+  ARM_t2SHSAX /* 4176 */, ARM_INS_SHSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* shsub16${p}	$Rd, $Rn, $Rm */
+  ARM_t2SHSUB16 /* 4177 */, ARM_INS_SHSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* shsub8${p}	$Rd, $Rn, $Rm */
+  ARM_t2SHSUB8 /* 4178 */, ARM_INS_SHSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smc${p}	$opt */
+  ARM_t2SMC /* 4179 */, ARM_INS_SMC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasTrustZone, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlabb${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLABB /* 4180 */, ARM_INS_SMLABB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlabt${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLABT /* 4181 */, ARM_INS_SMLABT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlad${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLAD /* 4182 */, ARM_INS_SMLAD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smladx${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLADX /* 4183 */, ARM_INS_SMLADX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlal${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2SMLAL /* 4184 */, ARM_INS_SMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlalbb${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2SMLALBB /* 4185 */, ARM_INS_SMLALBB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlalbt${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2SMLALBT /* 4186 */, ARM_INS_SMLALBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlald${p}	$Ra, $Rd, $Rn, $Rm */
+  ARM_t2SMLALD /* 4187 */, ARM_INS_SMLALD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlaldx${p}	$Ra, $Rd, $Rn, $Rm */
+  ARM_t2SMLALDX /* 4188 */, ARM_INS_SMLALDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlaltb${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2SMLALTB /* 4189 */, ARM_INS_SMLALTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlaltt${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2SMLALTT /* 4190 */, ARM_INS_SMLALTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlatb${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLATB /* 4191 */, ARM_INS_SMLATB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlatt${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLATT /* 4192 */, ARM_INS_SMLATT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlawb${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLAWB /* 4193 */, ARM_INS_SMLAWB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlawt${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLAWT /* 4194 */, ARM_INS_SMLAWT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsd${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLSD /* 4195 */, ARM_INS_SMLSD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsdx${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMLSDX /* 4196 */, ARM_INS_SMLSDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsld${p}	$Ra, $Rd, $Rn, $Rm */
+  ARM_t2SMLSLD /* 4197 */, ARM_INS_SMLSLD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smlsldx${p}	$Ra, $Rd, $Rn, $Rm */
+  ARM_t2SMLSLDX /* 4198 */, ARM_INS_SMLSLDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmla${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMMLA /* 4199 */, ARM_INS_SMMLA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmlar${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMMLAR /* 4200 */, ARM_INS_SMMLAR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmls${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMMLS /* 4201 */, ARM_INS_SMMLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmlsr${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2SMMLSR /* 4202 */, ARM_INS_SMMLSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmul${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMMUL /* 4203 */, ARM_INS_SMMUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smmulr${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMMULR /* 4204 */, ARM_INS_SMMULR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smuad${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMUAD /* 4205 */, ARM_INS_SMUAD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smuadx${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMUADX /* 4206 */, ARM_INS_SMUADX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulbb${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMULBB /* 4207 */, ARM_INS_SMULBB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulbt${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMULBT /* 4208 */, ARM_INS_SMULBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smull${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2SMULL /* 4209 */, ARM_INS_SMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* smultb${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMULTB /* 4210 */, ARM_INS_SMULTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smultt${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMULTT /* 4211 */, ARM_INS_SMULTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulwb${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMULWB /* 4212 */, ARM_INS_SMULWB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smulwt${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMULWT /* 4213 */, ARM_INS_SMULWT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smusd${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMUSD /* 4214 */, ARM_INS_SMUSD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* smusdx${p}	$Rd, $Rn, $Rm */
+  ARM_t2SMUSDX /* 4215 */, ARM_INS_SMUSDX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsdb${p}	sp, $mode */
+  ARM_t2SRSDB /* 4216 */, ARM_INS_SRSDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsdb${p}	sp!, $mode */
+  ARM_t2SRSDB_UPD /* 4217 */, ARM_INS_SRSDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsia${p}	sp, $mode */
+  ARM_t2SRSIA /* 4218 */, ARM_INS_SRSIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* srsia${p}	sp!, $mode */
+  ARM_t2SRSIA_UPD /* 4219 */, ARM_INS_SRSIA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssat${p}	$Rd, $sat_imm, $Rn$sh */
+  ARM_t2SSAT /* 4220 */, ARM_INS_SSAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssat16${p}	$Rd, $sat_imm, $Rn */
+  ARM_t2SSAT16 /* 4221 */, ARM_INS_SSAT16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssax${p}	$Rd, $Rn, $Rm */
+  ARM_t2SSAX /* 4222 */, ARM_INS_SSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssub16${p}	$Rd, $Rn, $Rm */
+  ARM_t2SSUB16 /* 4223 */, ARM_INS_SSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* ssub8${p}	$Rd, $Rn, $Rm */
+  ARM_t2SSUB8 /* 4224 */, ARM_INS_SSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l${p}	$cop, $CRd, $addr */
+  ARM_t2STC2L_OFFSET /* 4225 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l${p}	$cop, $CRd, $addr, $option */
+  ARM_t2STC2L_OPTION /* 4226 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2STC2L_POST /* 4227 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2l${p}	$cop, $CRd, $addr! */
+  ARM_t2STC2L_PRE /* 4228 */, ARM_INS_STC2L,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2${p}	$cop, $CRd, $addr */
+  ARM_t2STC2_OFFSET /* 4229 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2${p}	$cop, $CRd, $addr, $option */
+  ARM_t2STC2_OPTION /* 4230 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2STC2_POST /* 4231 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc2${p}	$cop, $CRd, $addr! */
+  ARM_t2STC2_PRE /* 4232 */, ARM_INS_STC2,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_PreV8, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr */
+  ARM_t2STCL_OFFSET /* 4233 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr, $option */
+  ARM_t2STCL_OPTION /* 4234 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2STCL_POST /* 4235 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stcl${p}	$cop, $CRd, $addr! */
+  ARM_t2STCL_PRE /* 4236 */, ARM_INS_STCL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr */
+  ARM_t2STC_OFFSET /* 4237 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr, $option */
+  ARM_t2STC_OPTION /* 4238 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr, $offset */
+  ARM_t2STC_POST /* 4239 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stc${p}	$cop, $CRd, $addr! */
+  ARM_t2STC_PRE /* 4240 */, ARM_INS_STC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stl${p}	$Rt, $addr */
+  ARM_t2STL /* 4241 */, ARM_INS_STL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlb${p}	$Rt, $addr */
+  ARM_t2STLB /* 4242 */, ARM_INS_STLB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlex${p}	$Rd, $Rt, $addr */
+  ARM_t2STLEX /* 4243 */, ARM_INS_STLEX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlexb${p}	$Rd, $Rt, $addr */
+  ARM_t2STLEXB /* 4244 */, ARM_INS_STLEXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlexd${p}	$Rd, $Rt, $Rt2, $addr */
+  ARM_t2STLEXD /* 4245 */, ARM_INS_STLEXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlexh${p}	$Rd, $Rt, $addr */
+  ARM_t2STLEXH /* 4246 */, ARM_INS_STLEXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, ARM_FEATURE_HasV7Clrex, 0 }, 0, 0
+  #endif
+},
+{
+  /* stlh${p}	$Rt, $addr */
+  ARM_t2STLH /* 4247 */, ARM_INS_STLH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasAcquireRelease, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmdb${p}	$Rn, $regs */
+  ARM_t2STMDB /* 4248 */, ARM_INS_STMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stmdb${p}	$Rn!, $regs */
+  ARM_t2STMDB_UPD /* 4249 */, ARM_INS_STMDB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}.w	$Rn, $regs */
+  ARM_t2STMIA /* 4250 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}.w	$Rn!, $regs */
+  ARM_t2STMIA_UPD /* 4251 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strbt${p}	$Rt, $addr */
+  ARM_t2STRBT /* 4252 */, ARM_INS_STRBT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $Rn$offset */
+  ARM_t2STRB_POST /* 4253 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr! */
+  ARM_t2STRB_PRE /* 4254 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}.w	$Rt, $addr */
+  ARM_t2STRBi12 /* 4255 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr */
+  ARM_t2STRBi8 /* 4256 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}.w	$Rt, $addr */
+  ARM_t2STRBs /* 4257 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strd${p}	$Rt, $Rt2, $addr$imm */
+  ARM_t2STRD_POST /* 4258 */, ARM_INS_STRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strd${p}	$Rt, $Rt2, $addr! */
+  ARM_t2STRD_PRE /* 4259 */, ARM_INS_STRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strd${p}	$Rt, $Rt2, $addr */
+  ARM_t2STRDi8 /* 4260 */, ARM_INS_STRD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strex${p}	$Rd, $Rt, $addr */
+  ARM_t2STREX /* 4261 */, ARM_INS_STREX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* strexb${p}	$Rd, $Rt, $addr */
+  ARM_t2STREXB /* 4262 */, ARM_INS_STREXB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* strexd${p}	$Rd, $Rt, $Rt2, $addr */
+  ARM_t2STREXD /* 4263 */, ARM_INS_STREXD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* strexh${p}	$Rd, $Rt, $addr */
+  ARM_t2STREXH /* 4264 */, ARM_INS_STREXH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* strht${p}	$Rt, $addr */
+  ARM_t2STRHT /* 4265 */, ARM_INS_STRHT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $Rn$offset */
+  ARM_t2STRH_POST /* 4266 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr! */
+  ARM_t2STRH_PRE /* 4267 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}.w	$Rt, $addr */
+  ARM_t2STRHi12 /* 4268 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr */
+  ARM_t2STRHi8 /* 4269 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}.w	$Rt, $addr */
+  ARM_t2STRHs /* 4270 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* strt${p}	$Rt, $addr */
+  ARM_t2STRT /* 4271 */, ARM_INS_STRT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $Rn$offset */
+  ARM_t2STR_POST /* 4272 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr! */
+  ARM_t2STR_PRE /* 4273 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}.w	$Rt, $addr */
+  ARM_t2STRi12 /* 4274 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr */
+  ARM_t2STRi8 /* 4275 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}.w	$Rt, $addr */
+  ARM_t2STRs /* 4276 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* subs${p}	pc, lr, $imm */
+  ARM_t2SUBS_PC_LR /* 4277 */, ARM_INS_SUBS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_PC, 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}.w	$Rd, $Rn, $imm */
+  ARM_t2SUBri /* 4278 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* subw${p}	$Rd, $Rn, $imm */
+  ARM_t2SUBri12 /* 4279 */, ARM_INS_SUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}.w	$Rd, $Rn, $Rm */
+  ARM_t2SUBrr /* 4280 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+  ARM_t2SUBrs /* 4281 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}.w	$Rd, $Rn, $imm */
+  ARM_t2SUBspImm /* 4282 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* subw${p}	$Rd, $Rn, $imm */
+  ARM_t2SUBspImm12 /* 4283 */, ARM_INS_SUBW,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtab${p}	$Rd, $Rn, $Rm$rot */
+  ARM_t2SXTAB /* 4284 */, ARM_INS_SXTAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtab16${p}	$Rd, $Rn, $Rm$rot */
+  ARM_t2SXTAB16 /* 4285 */, ARM_INS_SXTAB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtah${p}	$Rd, $Rn, $Rm$rot */
+  ARM_t2SXTAH /* 4286 */, ARM_INS_SXTAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtb${p}.w	$Rd, $Rm$rot */
+  ARM_t2SXTB /* 4287 */, ARM_INS_SXTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtb16${p}	$Rd, $Rm$rot */
+  ARM_t2SXTB16 /* 4288 */, ARM_INS_SXTB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxth${p}.w	$Rd, $Rm$rot */
+  ARM_t2SXTH /* 4289 */, ARM_INS_SXTH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* tbb${p}	$addr */
+  ARM_t2TBB /* 4290 */, ARM_INS_TBB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, 0 }, 1, 1
+  #endif
+},
+{
+  /* tbh${p}	$addr */
+  ARM_t2TBH /* 4291 */, ARM_INS_TBH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb2, 0 }, 1, 1
+  #endif
+},
+{
+  /* teq${p}.w	$Rn, $imm */
+  ARM_t2TEQri /* 4292 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* teq${p}.w	$Rn, $Rm */
+  ARM_t2TEQrr /* 4293 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* teq${p}.w	$Rn, $ShiftedRm */
+  ARM_t2TEQrs /* 4294 */, ARM_INS_TEQ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* tsb${p}	$opt */
+  ARM_t2TSB /* 4295 */, ARM_INS_TSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8_4a, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}.w	$Rn, $imm */
+  ARM_t2TSTri /* 4296 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}.w	$Rn, $Rm */
+  ARM_t2TSTrr /* 4297 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}.w	$Rn, $ShiftedRm */
+  ARM_t2TSTrs /* 4298 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* tt${p}	$Rt, $Rn */
+  ARM_t2TT /* 4299 */, ARM_INS_TT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* tta${p}	$Rt, $Rn */
+  ARM_t2TTA /* 4300 */, ARM_INS_TTA,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* ttat${p}	$Rt, $Rn */
+  ARM_t2TTAT /* 4301 */, ARM_INS_TTAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* ttt${p}	$Rt, $Rn */
+  ARM_t2TTT /* 4302 */, ARM_INS_TTT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* uadd16${p}	$Rd, $Rn, $Rm */
+  ARM_t2UADD16 /* 4303 */, ARM_INS_UADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uadd8${p}	$Rd, $Rn, $Rm */
+  ARM_t2UADD8 /* 4304 */, ARM_INS_UADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uasx${p}	$Rd, $Rn, $Rm */
+  ARM_t2UASX /* 4305 */, ARM_INS_UASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* ubfx${p}	$Rd, $Rn, $lsb, $msb */
+  ARM_t2UBFX /* 4306 */, ARM_INS_UBFX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* udf.w	$imm16 */
+  ARM_t2UDF /* 4307 */, ARM_INS_UDF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* udiv${p}	$Rd, $Rn, $Rm */
+  ARM_t2UDIV /* 4308 */, ARM_INS_UDIV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDivideInThumb, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhadd16${p}	$Rd, $Rn, $Rm */
+  ARM_t2UHADD16 /* 4309 */, ARM_INS_UHADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhadd8${p}	$Rd, $Rn, $Rm */
+  ARM_t2UHADD8 /* 4310 */, ARM_INS_UHADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhasx${p}	$Rd, $Rn, $Rm */
+  ARM_t2UHASX /* 4311 */, ARM_INS_UHASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhsax${p}	$Rd, $Rn, $Rm */
+  ARM_t2UHSAX /* 4312 */, ARM_INS_UHSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhsub16${p}	$Rd, $Rn, $Rm */
+  ARM_t2UHSUB16 /* 4313 */, ARM_INS_UHSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uhsub8${p}	$Rd, $Rn, $Rm */
+  ARM_t2UHSUB8 /* 4314 */, ARM_INS_UHSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* umaal${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2UMAAL /* 4315 */, ARM_INS_UMAAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* umlal${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2UMLAL /* 4316 */, ARM_INS_UMLAL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* umull${p}	$RdLo, $RdHi, $Rn, $Rm */
+  ARM_t2UMULL /* 4317 */, ARM_INS_UMULL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqadd16${p}	$Rd, $Rn, $Rm */
+  ARM_t2UQADD16 /* 4318 */, ARM_INS_UQADD16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqadd8${p}	$Rd, $Rn, $Rm */
+  ARM_t2UQADD8 /* 4319 */, ARM_INS_UQADD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqasx${p}	$Rd, $Rn, $Rm */
+  ARM_t2UQASX /* 4320 */, ARM_INS_UQASX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqsax${p}	$Rd, $Rn, $Rm */
+  ARM_t2UQSAX /* 4321 */, ARM_INS_UQSAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqsub16${p}	$Rd, $Rn, $Rm */
+  ARM_t2UQSUB16 /* 4322 */, ARM_INS_UQSUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uqsub8${p}	$Rd, $Rn, $Rm */
+  ARM_t2UQSUB8 /* 4323 */, ARM_INS_UQSUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* usad8${p}	$Rd, $Rn, $Rm */
+  ARM_t2USAD8 /* 4324 */, ARM_INS_USAD8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* usada8${p}	$Rd, $Rn, $Rm, $Ra */
+  ARM_t2USADA8 /* 4325 */, ARM_INS_USADA8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* usat${p}	$Rd, $sat_imm, $Rn$sh */
+  ARM_t2USAT /* 4326 */, ARM_INS_USAT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* usat16${p}	$Rd, $sat_imm, $Rn */
+  ARM_t2USAT16 /* 4327 */, ARM_INS_USAT16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* usax${p}	$Rd, $Rn, $Rm */
+  ARM_t2USAX /* 4328 */, ARM_INS_USAX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* usub16${p}	$Rd, $Rn, $Rm */
+  ARM_t2USUB16 /* 4329 */, ARM_INS_USUB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* usub8${p}	$Rd, $Rn, $Rm */
+  ARM_t2USUB8 /* 4330 */, ARM_INS_USUB8,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, ARM_FEATURE_HasDSP, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtab${p}	$Rd, $Rn, $Rm$rot */
+  ARM_t2UXTAB /* 4331 */, ARM_INS_UXTAB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtab16${p}	$Rd, $Rn, $Rm$rot */
+  ARM_t2UXTAB16 /* 4332 */, ARM_INS_UXTAB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtah${p}	$Rd, $Rn, $Rm$rot */
+  ARM_t2UXTAH /* 4333 */, ARM_INS_UXTAH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtb${p}.w	$Rd, $Rm$rot */
+  ARM_t2UXTB /* 4334 */, ARM_INS_UXTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtb16${p}	$Rd, $Rm$rot */
+  ARM_t2UXTB16 /* 4335 */, ARM_INS_UXTB16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_HasDSP, ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxth${p}.w	$Rd, $Rm$rot */
+  ARM_t2UXTH /* 4336 */, ARM_INS_UXTH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb2, 0 }, 0, 0
+  #endif
+},
+{
+  /* wls	$LR, $Rn, $label */
+  ARM_t2WLS /* 4337 */, ARM_INS_WLS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb2, ARM_FEATURE_HasV8_1MMainline, ARM_FEATURE_HasLOB, 0 }, 1, 0
+  #endif
+},
+{
+  /* adc${s}${p}	$Rdn, $Rm */
+  ARM_tADC /* 4338 */, ARM_INS_ADC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${p}	$Rdn, $Rm */
+  ARM_tADDhirr /* 4339 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rd, $Rm, $imm3 */
+  ARM_tADDi3 /* 4340 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rdn, $imm8 */
+  ARM_tADDi8 /* 4341 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${p}	$Rdn, $sp, $Rn */
+  ARM_tADDrSP /* 4342 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${p}	$dst, $sp, $imm */
+  ARM_tADDrSPi /* 4343 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${s}${p}	$Rd, $Rn, $Rm */
+  ARM_tADDrr /* 4344 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${p}	$Rdn, $imm */
+  ARM_tADDspi /* 4345 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* add${p}	$Rdn, $Rm */
+  ARM_tADDspr /* 4346 */, ARM_INS_ADD,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* adr{$p}	$Rd, $addr */
+  ARM_tADR /* 4347 */, ARM_INS_ADR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* and${s}${p}	$Rdn, $Rm */
+  ARM_tAND /* 4348 */, ARM_INS_AND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* asr${s}${p}	$Rd, $Rm, $imm5 */
+  ARM_tASRri /* 4349 */, ARM_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* asr${s}${p}	$Rdn, $Rm */
+  ARM_tASRrr /* 4350 */, ARM_INS_ASR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* b${p}	$target */
+  ARM_tB /* 4351 */, ARM_INS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, 0 }, 1, 0
+  #endif
+},
+{
+  /* bic${s}${p}	$Rdn, $Rm */
+  ARM_tBIC /* 4352 */, ARM_INS_BIC,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* bkpt	$val */
+  ARM_tBKPT /* 4353 */, ARM_INS_BKPT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* bl${p}	$func */
+  ARM_tBL /* 4354 */, ARM_INS_BL,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* blxns${p}	$func */
+  ARM_tBLXNSr /* 4355 */, ARM_INS_BLXNS,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 0, 0
+  #endif
+},
+{
+  /* blx${p}	$func */
+  ARM_tBLXi /* 4356 */, ARM_INS_BLX,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV5T, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* blx${p}	$func */
+  ARM_tBLXr /* 4357 */, ARM_INS_BLX,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV5T, 0 }, 0, 0
+  #endif
+},
+{
+  /* bx${p}	$Rm */
+  ARM_tBX /* 4358 */, ARM_INS_BX,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb, 0 }, 1, 1
+  #endif
+},
+{
+  /* bxns${p}	$Rm */
+  ARM_tBXNS /* 4359 */, ARM_INS_BXNS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_FEATURE_IsThumb, ARM_FEATURE_Has8MSecExt, 0 }, 1, 1
+  #endif
+},
+{
+  /* b${p}	$target */
+  ARM_tBcc /* 4360 */, ARM_INS_B,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, 0 }, 1, 0
+  #endif
+},
+{
+  /* cbnz	$Rn, $target */
+  ARM_tCBNZ /* 4361 */, ARM_INS_CBNZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 1, 0
+  #endif
+},
+{
+  /* cbz	$Rn, $target */
+  ARM_tCBZ /* 4362 */, ARM_INS_CBZ,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_GRP_JUMP, ARM_GRP_BRANCH_RELATIVE, ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8MBaseline, 0 }, 1, 0
+  #endif
+},
+{
+  /* cmn${p}	$Rn, $Rm */
+  ARM_tCMNz /* 4363 */, ARM_INS_CMN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $Rm */
+  ARM_tCMPhir /* 4364 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $imm8 */
+  ARM_tCMPi8 /* 4365 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* cmp${p}	$Rn, $Rm */
+  ARM_tCMPr /* 4366 */, ARM_INS_CMP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* cps$imod $iflags */
+  ARM_tCPS /* 4367 */, ARM_INS_CPS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* eor${s}${p}	$Rdn, $Rm */
+  ARM_tEOR /* 4368 */, ARM_INS_EOR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* hint${p}	$imm */
+  ARM_tHINT /* 4369 */, ARM_INS_HINT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6M, 0 }, 0, 0
+  #endif
+},
+{
+  /* hlt	$val */
+  ARM_tHLT /* 4370 */, ARM_INS_HLT,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV8, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tInt_WIN_eh_sjlj_longjmp /* 4371 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tInt_eh_sjlj_longjmp /* 4372 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tInt_eh_sjlj_setjmp /* 4373 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* ldm${p}	$Rn, $regs */
+  ARM_tLDMIA /* 4374 */, ARM_INS_LDM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr */
+  ARM_tLDRBi /* 4375 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrb${p}	$Rt, $addr */
+  ARM_tLDRBr /* 4376 */, ARM_INS_LDRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr */
+  ARM_tLDRHi /* 4377 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrh${p}	$Rt, $addr */
+  ARM_tLDRHr /* 4378 */, ARM_INS_LDRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsb${p}	$Rt, $addr */
+  ARM_tLDRSB /* 4379 */, ARM_INS_LDRSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldrsh${p}	$Rt, $addr */
+  ARM_tLDRSH /* 4380 */, ARM_INS_LDRSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_tLDRi /* 4381 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_tLDRpci /* 4382 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_tLDRr /* 4383 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* ldr${p}	$Rt, $addr */
+  ARM_tLDRspi /* 4384 */, ARM_INS_LDR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsl${s}${p}	$Rd, $Rm, $imm5 */
+  ARM_tLSLri /* 4385 */, ARM_INS_LSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsl${s}${p}	$Rdn, $Rm */
+  ARM_tLSLrr /* 4386 */, ARM_INS_LSL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsr${s}${p}	$Rd, $Rm, $imm5 */
+  ARM_tLSRri /* 4387 */, ARM_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* lsr${s}${p}	$Rdn, $Rm */
+  ARM_tLSRrr /* 4388 */, ARM_INS_LSR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* movs	$Rd, $Rm */
+  ARM_tMOVSr /* 4389 */, ARM_INS_MOVS,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${s}${p}	$Rd, $imm8 */
+  ARM_tMOVi8 /* 4390 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* mov${p}	$Rd, $Rm */
+  ARM_tMOVr /* 4391 */, ARM_INS_MOV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* mul${s}${p}	$Rd, $Rn, $Rm */
+  ARM_tMUL /* 4392 */, ARM_INS_MUL,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* mvn${s}${p}	$Rd, $Rn */
+  ARM_tMVN /* 4393 */, ARM_INS_MVN,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* orr${s}${p}	$Rdn, $Rm */
+  ARM_tORR /* 4394 */, ARM_INS_ORR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* <No AsmString> */
+  ARM_tPICADD /* 4395 */, ARM_INS_INVALID,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { 0 }, 0, 0
+  #endif
+},
+{
+  /* pop${p}	$regs */
+  ARM_tPOP /* 4396 */, ARM_INS_POP,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* push${p}	$regs */
+  ARM_tPUSH /* 4397 */, ARM_INS_PUSH,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { ARM_REG_SP, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* rev${p}	$Rd, $Rm */
+  ARM_tREV /* 4398 */, ARM_INS_REV,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* rev16${p}	$Rd, $Rm */
+  ARM_tREV16 /* 4399 */, ARM_INS_REV16,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* revsh${p}	$Rd, $Rm */
+  ARM_tREVSH /* 4400 */, ARM_INS_REVSH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* ror${s}${p}	$Rdn, $Rm */
+  ARM_tROR /* 4401 */, ARM_INS_ROR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* rsb${s}${p}	$Rd, $Rn, #0 */
+  ARM_tRSB /* 4402 */, ARM_INS_RSB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* sbc${s}${p}	$Rdn, $Rm */
+  ARM_tSBC /* 4403 */, ARM_INS_SBC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_CPSR, 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* setend	$end */
+  ARM_tSETEND /* 4404 */, ARM_INS_SETEND,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_IsNotMClass, 0 }, 0, 0
+  #endif
+},
+{
+  /* stm${p}	$Rn!, $regs */
+  ARM_tSTMIA_UPD /* 4405 */, ARM_INS_STM,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr */
+  ARM_tSTRBi /* 4406 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* strb${p}	$Rt, $addr */
+  ARM_tSTRBr /* 4407 */, ARM_INS_STRB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr */
+  ARM_tSTRHi /* 4408 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* strh${p}	$Rt, $addr */
+  ARM_tSTRHr /* 4409 */, ARM_INS_STRH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr */
+  ARM_tSTRi /* 4410 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr */
+  ARM_tSTRr /* 4411 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* str${p}	$Rt, $addr */
+  ARM_tSTRspi /* 4412 */, ARM_INS_STR,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rd, $Rm, $imm3 */
+  ARM_tSUBi3 /* 4413 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rdn, $imm8 */
+  ARM_tSUBi8 /* 4414 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${s}${p}	$Rd, $Rn, $Rm */
+  ARM_tSUBrr /* 4415 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* sub${p}	$Rdn, $imm */
+  ARM_tSUBspi /* 4416 */, ARM_INS_SUB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* svc${p}	$imm */
+  ARM_tSVC /* 4417 */, ARM_INS_SVC,
+  #ifndef CAPSTONE_DIET
+    { ARM_REG_SP, 0 }, { 0 }, { ARM_GRP_CALL, ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxtb${p}	$Rd, $Rm */
+  ARM_tSXTB /* 4418 */, ARM_INS_SXTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* sxth${p}	$Rd, $Rm */
+  ARM_tSXTH /* 4419 */, ARM_INS_SXTH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* trap */
+  ARM_tTRAP /* 4420 */, ARM_INS_TRAP,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* tst${p}	$Rn, $Rm */
+  ARM_tTST /* 4421 */, ARM_INS_TST,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { ARM_REG_CPSR, 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* udf	$imm8 */
+  ARM_tUDF /* 4422 */, ARM_INS_UDF,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxtb${p}	$Rd, $Rm */
+  ARM_tUXTB /* 4423 */, ARM_INS_UXTB,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* uxth${p}	$Rd, $Rm */
+  ARM_tUXTH /* 4424 */, ARM_INS_UXTH,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, ARM_FEATURE_HasV6, 0 }, 0, 0
+  #endif
+},
+{
+  /* __brkdiv0 */
+  ARM_t__brkdiv0 /* 4425 */, ARM_INS___BRKDIV0,
+  #ifndef CAPSTONE_DIET
+    { 0 }, { 0 }, { ARM_FEATURE_IsThumb, 0 }, 0, 0
+  #endif
+},
diff --git a/arch/ARM/ARMGenCSMappingInsnName.inc b/arch/ARM/ARMGenCSMappingInsnName.inc
new file mode 100644
index 000000000..abed4f5b8
--- /dev/null
+++ b/arch/ARM/ARMGenCSMappingInsnName.inc
@@ -0,0 +1,650 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // ARM_INS_INVALID
+  "asr", // ARM_INS_ASR
+  "it", // ARM_INS_IT
+  "ldrbt", // ARM_INS_LDRBT
+  "ldr", // ARM_INS_LDR
+  "ldrht", // ARM_INS_LDRHT
+  "ldrsbt", // ARM_INS_LDRSBT
+  "ldrsht", // ARM_INS_LDRSHT
+  "ldrt", // ARM_INS_LDRT
+  "lsl", // ARM_INS_LSL
+  "lsr", // ARM_INS_LSR
+  "ror", // ARM_INS_ROR
+  "rrx", // ARM_INS_RRX
+  "strbt", // ARM_INS_STRBT
+  "strt", // ARM_INS_STRT
+  "vld1", // ARM_INS_VLD1
+  "vld2", // ARM_INS_VLD2
+  "vld3", // ARM_INS_VLD3
+  "vld4", // ARM_INS_VLD4
+  "vst1", // ARM_INS_VST1
+  "vst2", // ARM_INS_VST2
+  "vst3", // ARM_INS_VST3
+  "vst4", // ARM_INS_VST4
+  "ldrb", // ARM_INS_LDRB
+  "ldrh", // ARM_INS_LDRH
+  "ldrsb", // ARM_INS_LDRSB
+  "ldrsh", // ARM_INS_LDRSH
+  "movs", // ARM_INS_MOVS
+  "mov", // ARM_INS_MOV
+  "str", // ARM_INS_STR
+  "adc", // ARM_INS_ADC
+  "add", // ARM_INS_ADD
+  "adr", // ARM_INS_ADR
+  "aesd", // ARM_INS_AESD
+  "aese", // ARM_INS_AESE
+  "aesimc", // ARM_INS_AESIMC
+  "aesmc", // ARM_INS_AESMC
+  "and", // ARM_INS_AND
+  "vdot", // ARM_INS_VDOT
+  "vcvt", // ARM_INS_VCVT
+  "vcvtb", // ARM_INS_VCVTB
+  "vcvtt", // ARM_INS_VCVTT
+  "bfc", // ARM_INS_BFC
+  "bfi", // ARM_INS_BFI
+  "bic", // ARM_INS_BIC
+  "bkpt", // ARM_INS_BKPT
+  "bl", // ARM_INS_BL
+  "blx", // ARM_INS_BLX
+  "bx", // ARM_INS_BX
+  "bxj", // ARM_INS_BXJ
+  "b", // ARM_INS_B
+  "cx1", // ARM_INS_CX1
+  "cx1a", // ARM_INS_CX1A
+  "cx1d", // ARM_INS_CX1D
+  "cx1da", // ARM_INS_CX1DA
+  "cx2", // ARM_INS_CX2
+  "cx2a", // ARM_INS_CX2A
+  "cx2d", // ARM_INS_CX2D
+  "cx2da", // ARM_INS_CX2DA
+  "cx3", // ARM_INS_CX3
+  "cx3a", // ARM_INS_CX3A
+  "cx3d", // ARM_INS_CX3D
+  "cx3da", // ARM_INS_CX3DA
+  "vcx1a", // ARM_INS_VCX1A
+  "vcx1", // ARM_INS_VCX1
+  "vcx2a", // ARM_INS_VCX2A
+  "vcx2", // ARM_INS_VCX2
+  "vcx3a", // ARM_INS_VCX3A
+  "vcx3", // ARM_INS_VCX3
+  "cdp", // ARM_INS_CDP
+  "cdp2", // ARM_INS_CDP2
+  "clrex", // ARM_INS_CLREX
+  "clz", // ARM_INS_CLZ
+  "cmn", // ARM_INS_CMN
+  "cmp", // ARM_INS_CMP
+  "cps", // ARM_INS_CPS
+  "crc32b", // ARM_INS_CRC32B
+  "crc32cb", // ARM_INS_CRC32CB
+  "crc32ch", // ARM_INS_CRC32CH
+  "crc32cw", // ARM_INS_CRC32CW
+  "crc32h", // ARM_INS_CRC32H
+  "crc32w", // ARM_INS_CRC32W
+  "dbg", // ARM_INS_DBG
+  "dmb", // ARM_INS_DMB
+  "dsb", // ARM_INS_DSB
+  "eor", // ARM_INS_EOR
+  "eret", // ARM_INS_ERET
+  "vmov", // ARM_INS_VMOV
+  "fldmdbx", // ARM_INS_FLDMDBX
+  "fldmiax", // ARM_INS_FLDMIAX
+  "vmrs", // ARM_INS_VMRS
+  "fstmdbx", // ARM_INS_FSTMDBX
+  "fstmiax", // ARM_INS_FSTMIAX
+  "hint", // ARM_INS_HINT
+  "hlt", // ARM_INS_HLT
+  "hvc", // ARM_INS_HVC
+  "isb", // ARM_INS_ISB
+  "lda", // ARM_INS_LDA
+  "ldab", // ARM_INS_LDAB
+  "ldaex", // ARM_INS_LDAEX
+  "ldaexb", // ARM_INS_LDAEXB
+  "ldaexd", // ARM_INS_LDAEXD
+  "ldaexh", // ARM_INS_LDAEXH
+  "ldah", // ARM_INS_LDAH
+  "ldc2l", // ARM_INS_LDC2L
+  "ldc2", // ARM_INS_LDC2
+  "ldcl", // ARM_INS_LDCL
+  "ldc", // ARM_INS_LDC
+  "ldmda", // ARM_INS_LDMDA
+  "ldmdb", // ARM_INS_LDMDB
+  "ldm", // ARM_INS_LDM
+  "ldmib", // ARM_INS_LDMIB
+  "ldrd", // ARM_INS_LDRD
+  "ldrex", // ARM_INS_LDREX
+  "ldrexb", // ARM_INS_LDREXB
+  "ldrexd", // ARM_INS_LDREXD
+  "ldrexh", // ARM_INS_LDREXH
+  "mcr", // ARM_INS_MCR
+  "mcr2", // ARM_INS_MCR2
+  "mcrr", // ARM_INS_MCRR
+  "mcrr2", // ARM_INS_MCRR2
+  "mla", // ARM_INS_MLA
+  "mls", // ARM_INS_MLS
+  "movt", // ARM_INS_MOVT
+  "movw", // ARM_INS_MOVW
+  "mrc", // ARM_INS_MRC
+  "mrc2", // ARM_INS_MRC2
+  "mrrc", // ARM_INS_MRRC
+  "mrrc2", // ARM_INS_MRRC2
+  "mrs", // ARM_INS_MRS
+  "msr", // ARM_INS_MSR
+  "mul", // ARM_INS_MUL
+  "asrl", // ARM_INS_ASRL
+  "dlstp", // ARM_INS_DLSTP
+  "lctp", // ARM_INS_LCTP
+  "letp", // ARM_INS_LETP
+  "lsll", // ARM_INS_LSLL
+  "lsrl", // ARM_INS_LSRL
+  "sqrshr", // ARM_INS_SQRSHR
+  "sqrshrl", // ARM_INS_SQRSHRL
+  "sqshl", // ARM_INS_SQSHL
+  "sqshll", // ARM_INS_SQSHLL
+  "srshr", // ARM_INS_SRSHR
+  "srshrl", // ARM_INS_SRSHRL
+  "uqrshl", // ARM_INS_UQRSHL
+  "uqrshll", // ARM_INS_UQRSHLL
+  "uqshl", // ARM_INS_UQSHL
+  "uqshll", // ARM_INS_UQSHLL
+  "urshr", // ARM_INS_URSHR
+  "urshrl", // ARM_INS_URSHRL
+  "vabav", // ARM_INS_VABAV
+  "vabd", // ARM_INS_VABD
+  "vabs", // ARM_INS_VABS
+  "vadc", // ARM_INS_VADC
+  "vadci", // ARM_INS_VADCI
+  "vaddlva", // ARM_INS_VADDLVA
+  "vaddlv", // ARM_INS_VADDLV
+  "vaddva", // ARM_INS_VADDVA
+  "vaddv", // ARM_INS_VADDV
+  "vadd", // ARM_INS_VADD
+  "vand", // ARM_INS_VAND
+  "vbic", // ARM_INS_VBIC
+  "vbrsr", // ARM_INS_VBRSR
+  "vcadd", // ARM_INS_VCADD
+  "vcls", // ARM_INS_VCLS
+  "vclz", // ARM_INS_VCLZ
+  "vcmla", // ARM_INS_VCMLA
+  "vcmp", // ARM_INS_VCMP
+  "vcmul", // ARM_INS_VCMUL
+  "vctp", // ARM_INS_VCTP
+  "vcvta", // ARM_INS_VCVTA
+  "vcvtm", // ARM_INS_VCVTM
+  "vcvtn", // ARM_INS_VCVTN
+  "vcvtp", // ARM_INS_VCVTP
+  "vddup", // ARM_INS_VDDUP
+  "vdup", // ARM_INS_VDUP
+  "vdwdup", // ARM_INS_VDWDUP
+  "veor", // ARM_INS_VEOR
+  "vfmas", // ARM_INS_VFMAS
+  "vfma", // ARM_INS_VFMA
+  "vfms", // ARM_INS_VFMS
+  "vhadd", // ARM_INS_VHADD
+  "vhcadd", // ARM_INS_VHCADD
+  "vhsub", // ARM_INS_VHSUB
+  "vidup", // ARM_INS_VIDUP
+  "viwdup", // ARM_INS_VIWDUP
+  "vld20", // ARM_INS_VLD20
+  "vld21", // ARM_INS_VLD21
+  "vld40", // ARM_INS_VLD40
+  "vld41", // ARM_INS_VLD41
+  "vld42", // ARM_INS_VLD42
+  "vld43", // ARM_INS_VLD43
+  "vldrb", // ARM_INS_VLDRB
+  "vldrd", // ARM_INS_VLDRD
+  "vldrh", // ARM_INS_VLDRH
+  "vldrw", // ARM_INS_VLDRW
+  "vmaxav", // ARM_INS_VMAXAV
+  "vmaxa", // ARM_INS_VMAXA
+  "vmaxnmav", // ARM_INS_VMAXNMAV
+  "vmaxnma", // ARM_INS_VMAXNMA
+  "vmaxnmv", // ARM_INS_VMAXNMV
+  "vmaxnm", // ARM_INS_VMAXNM
+  "vmaxv", // ARM_INS_VMAXV
+  "vmax", // ARM_INS_VMAX
+  "vminav", // ARM_INS_VMINAV
+  "vmina", // ARM_INS_VMINA
+  "vminnmav", // ARM_INS_VMINNMAV
+  "vminnma", // ARM_INS_VMINNMA
+  "vminnmv", // ARM_INS_VMINNMV
+  "vminnm", // ARM_INS_VMINNM
+  "vminv", // ARM_INS_VMINV
+  "vmin", // ARM_INS_VMIN
+  "vmladava", // ARM_INS_VMLADAVA
+  "vmladavax", // ARM_INS_VMLADAVAX
+  "vmladav", // ARM_INS_VMLADAV
+  "vmladavx", // ARM_INS_VMLADAVX
+  "vmlaldava", // ARM_INS_VMLALDAVA
+  "vmlaldavax", // ARM_INS_VMLALDAVAX
+  "vmlaldav", // ARM_INS_VMLALDAV
+  "vmlaldavx", // ARM_INS_VMLALDAVX
+  "vmlas", // ARM_INS_VMLAS
+  "vmla", // ARM_INS_VMLA
+  "vmlsdava", // ARM_INS_VMLSDAVA
+  "vmlsdavax", // ARM_INS_VMLSDAVAX
+  "vmlsdav", // ARM_INS_VMLSDAV
+  "vmlsdavx", // ARM_INS_VMLSDAVX
+  "vmlsldava", // ARM_INS_VMLSLDAVA
+  "vmlsldavax", // ARM_INS_VMLSLDAVAX
+  "vmlsldav", // ARM_INS_VMLSLDAV
+  "vmlsldavx", // ARM_INS_VMLSLDAVX
+  "vmovlb", // ARM_INS_VMOVLB
+  "vmovlt", // ARM_INS_VMOVLT
+  "vmovnb", // ARM_INS_VMOVNB
+  "vmovnt", // ARM_INS_VMOVNT
+  "vmulh", // ARM_INS_VMULH
+  "vmullb", // ARM_INS_VMULLB
+  "vmullt", // ARM_INS_VMULLT
+  "vmul", // ARM_INS_VMUL
+  "vmvn", // ARM_INS_VMVN
+  "vneg", // ARM_INS_VNEG
+  "vorn", // ARM_INS_VORN
+  "vorr", // ARM_INS_VORR
+  "vpnot", // ARM_INS_VPNOT
+  "vpsel", // ARM_INS_VPSEL
+  "vpst", // ARM_INS_VPST
+  "vpt", // ARM_INS_VPT
+  "vqabs", // ARM_INS_VQABS
+  "vqadd", // ARM_INS_VQADD
+  "vqdmladhx", // ARM_INS_VQDMLADHX
+  "vqdmladh", // ARM_INS_VQDMLADH
+  "vqdmlah", // ARM_INS_VQDMLAH
+  "vqdmlash", // ARM_INS_VQDMLASH
+  "vqdmlsdhx", // ARM_INS_VQDMLSDHX
+  "vqdmlsdh", // ARM_INS_VQDMLSDH
+  "vqdmulh", // ARM_INS_VQDMULH
+  "vqdmullb", // ARM_INS_VQDMULLB
+  "vqdmullt", // ARM_INS_VQDMULLT
+  "vqmovnb", // ARM_INS_VQMOVNB
+  "vqmovnt", // ARM_INS_VQMOVNT
+  "vqmovunb", // ARM_INS_VQMOVUNB
+  "vqmovunt", // ARM_INS_VQMOVUNT
+  "vqneg", // ARM_INS_VQNEG
+  "vqrdmladhx", // ARM_INS_VQRDMLADHX
+  "vqrdmladh", // ARM_INS_VQRDMLADH
+  "vqrdmlah", // ARM_INS_VQRDMLAH
+  "vqrdmlash", // ARM_INS_VQRDMLASH
+  "vqrdmlsdhx", // ARM_INS_VQRDMLSDHX
+  "vqrdmlsdh", // ARM_INS_VQRDMLSDH
+  "vqrdmulh", // ARM_INS_VQRDMULH
+  "vqrshl", // ARM_INS_VQRSHL
+  "vqrshrnb", // ARM_INS_VQRSHRNB
+  "vqrshrnt", // ARM_INS_VQRSHRNT
+  "vqrshrunb", // ARM_INS_VQRSHRUNB
+  "vqrshrunt", // ARM_INS_VQRSHRUNT
+  "vqshlu", // ARM_INS_VQSHLU
+  "vqshl", // ARM_INS_VQSHL
+  "vqshrnb", // ARM_INS_VQSHRNB
+  "vqshrnt", // ARM_INS_VQSHRNT
+  "vqshrunb", // ARM_INS_VQSHRUNB
+  "vqshrunt", // ARM_INS_VQSHRUNT
+  "vqsub", // ARM_INS_VQSUB
+  "vrev16", // ARM_INS_VREV16
+  "vrev32", // ARM_INS_VREV32
+  "vrev64", // ARM_INS_VREV64
+  "vrhadd", // ARM_INS_VRHADD
+  "vrinta", // ARM_INS_VRINTA
+  "vrintm", // ARM_INS_VRINTM
+  "vrintn", // ARM_INS_VRINTN
+  "vrintp", // ARM_INS_VRINTP
+  "vrintx", // ARM_INS_VRINTX
+  "vrintz", // ARM_INS_VRINTZ
+  "vrmlaldavha", // ARM_INS_VRMLALDAVHA
+  "vrmlaldavhax", // ARM_INS_VRMLALDAVHAX
+  "vrmlaldavh", // ARM_INS_VRMLALDAVH
+  "vrmlaldavhx", // ARM_INS_VRMLALDAVHX
+  "vrmlsldavha", // ARM_INS_VRMLSLDAVHA
+  "vrmlsldavhax", // ARM_INS_VRMLSLDAVHAX
+  "vrmlsldavh", // ARM_INS_VRMLSLDAVH
+  "vrmlsldavhx", // ARM_INS_VRMLSLDAVHX
+  "vrmulh", // ARM_INS_VRMULH
+  "vrshl", // ARM_INS_VRSHL
+  "vrshrnb", // ARM_INS_VRSHRNB
+  "vrshrnt", // ARM_INS_VRSHRNT
+  "vrshr", // ARM_INS_VRSHR
+  "vsbc", // ARM_INS_VSBC
+  "vsbci", // ARM_INS_VSBCI
+  "vshlc", // ARM_INS_VSHLC
+  "vshllb", // ARM_INS_VSHLLB
+  "vshllt", // ARM_INS_VSHLLT
+  "vshl", // ARM_INS_VSHL
+  "vshrnb", // ARM_INS_VSHRNB
+  "vshrnt", // ARM_INS_VSHRNT
+  "vshr", // ARM_INS_VSHR
+  "vsli", // ARM_INS_VSLI
+  "vsri", // ARM_INS_VSRI
+  "vst20", // ARM_INS_VST20
+  "vst21", // ARM_INS_VST21
+  "vst40", // ARM_INS_VST40
+  "vst41", // ARM_INS_VST41
+  "vst42", // ARM_INS_VST42
+  "vst43", // ARM_INS_VST43
+  "vstrb", // ARM_INS_VSTRB
+  "vstrd", // ARM_INS_VSTRD
+  "vstrh", // ARM_INS_VSTRH
+  "vstrw", // ARM_INS_VSTRW
+  "vsub", // ARM_INS_VSUB
+  "wlstp", // ARM_INS_WLSTP
+  "mvn", // ARM_INS_MVN
+  "orr", // ARM_INS_ORR
+  "pkhbt", // ARM_INS_PKHBT
+  "pkhtb", // ARM_INS_PKHTB
+  "pldw", // ARM_INS_PLDW
+  "pld", // ARM_INS_PLD
+  "pli", // ARM_INS_PLI
+  "qadd", // ARM_INS_QADD
+  "qadd16", // ARM_INS_QADD16
+  "qadd8", // ARM_INS_QADD8
+  "qasx", // ARM_INS_QASX
+  "qdadd", // ARM_INS_QDADD
+  "qdsub", // ARM_INS_QDSUB
+  "qsax", // ARM_INS_QSAX
+  "qsub", // ARM_INS_QSUB
+  "qsub16", // ARM_INS_QSUB16
+  "qsub8", // ARM_INS_QSUB8
+  "rbit", // ARM_INS_RBIT
+  "rev", // ARM_INS_REV
+  "rev16", // ARM_INS_REV16
+  "revsh", // ARM_INS_REVSH
+  "rfeda", // ARM_INS_RFEDA
+  "rfedb", // ARM_INS_RFEDB
+  "rfeia", // ARM_INS_RFEIA
+  "rfeib", // ARM_INS_RFEIB
+  "rsb", // ARM_INS_RSB
+  "rsc", // ARM_INS_RSC
+  "sadd16", // ARM_INS_SADD16
+  "sadd8", // ARM_INS_SADD8
+  "sasx", // ARM_INS_SASX
+  "sb", // ARM_INS_SB
+  "sbc", // ARM_INS_SBC
+  "sbfx", // ARM_INS_SBFX
+  "sdiv", // ARM_INS_SDIV
+  "sel", // ARM_INS_SEL
+  "setend", // ARM_INS_SETEND
+  "setpan", // ARM_INS_SETPAN
+  "sha1c", // ARM_INS_SHA1C
+  "sha1h", // ARM_INS_SHA1H
+  "sha1m", // ARM_INS_SHA1M
+  "sha1p", // ARM_INS_SHA1P
+  "sha1su0", // ARM_INS_SHA1SU0
+  "sha1su1", // ARM_INS_SHA1SU1
+  "sha256h", // ARM_INS_SHA256H
+  "sha256h2", // ARM_INS_SHA256H2
+  "sha256su0", // ARM_INS_SHA256SU0
+  "sha256su1", // ARM_INS_SHA256SU1
+  "shadd16", // ARM_INS_SHADD16
+  "shadd8", // ARM_INS_SHADD8
+  "shasx", // ARM_INS_SHASX
+  "shsax", // ARM_INS_SHSAX
+  "shsub16", // ARM_INS_SHSUB16
+  "shsub8", // ARM_INS_SHSUB8
+  "smc", // ARM_INS_SMC
+  "smlabb", // ARM_INS_SMLABB
+  "smlabt", // ARM_INS_SMLABT
+  "smlad", // ARM_INS_SMLAD
+  "smladx", // ARM_INS_SMLADX
+  "smlal", // ARM_INS_SMLAL
+  "smlalbb", // ARM_INS_SMLALBB
+  "smlalbt", // ARM_INS_SMLALBT
+  "smlald", // ARM_INS_SMLALD
+  "smlaldx", // ARM_INS_SMLALDX
+  "smlaltb", // ARM_INS_SMLALTB
+  "smlaltt", // ARM_INS_SMLALTT
+  "smlatb", // ARM_INS_SMLATB
+  "smlatt", // ARM_INS_SMLATT
+  "smlawb", // ARM_INS_SMLAWB
+  "smlawt", // ARM_INS_SMLAWT
+  "smlsd", // ARM_INS_SMLSD
+  "smlsdx", // ARM_INS_SMLSDX
+  "smlsld", // ARM_INS_SMLSLD
+  "smlsldx", // ARM_INS_SMLSLDX
+  "smmla", // ARM_INS_SMMLA
+  "smmlar", // ARM_INS_SMMLAR
+  "smmls", // ARM_INS_SMMLS
+  "smmlsr", // ARM_INS_SMMLSR
+  "smmul", // ARM_INS_SMMUL
+  "smmulr", // ARM_INS_SMMULR
+  "smuad", // ARM_INS_SMUAD
+  "smuadx", // ARM_INS_SMUADX
+  "smulbb", // ARM_INS_SMULBB
+  "smulbt", // ARM_INS_SMULBT
+  "smull", // ARM_INS_SMULL
+  "smultb", // ARM_INS_SMULTB
+  "smultt", // ARM_INS_SMULTT
+  "smulwb", // ARM_INS_SMULWB
+  "smulwt", // ARM_INS_SMULWT
+  "smusd", // ARM_INS_SMUSD
+  "smusdx", // ARM_INS_SMUSDX
+  "srsda", // ARM_INS_SRSDA
+  "srsdb", // ARM_INS_SRSDB
+  "srsia", // ARM_INS_SRSIA
+  "srsib", // ARM_INS_SRSIB
+  "ssat", // ARM_INS_SSAT
+  "ssat16", // ARM_INS_SSAT16
+  "ssax", // ARM_INS_SSAX
+  "ssub16", // ARM_INS_SSUB16
+  "ssub8", // ARM_INS_SSUB8
+  "stc2l", // ARM_INS_STC2L
+  "stc2", // ARM_INS_STC2
+  "stcl", // ARM_INS_STCL
+  "stc", // ARM_INS_STC
+  "stl", // ARM_INS_STL
+  "stlb", // ARM_INS_STLB
+  "stlex", // ARM_INS_STLEX
+  "stlexb", // ARM_INS_STLEXB
+  "stlexd", // ARM_INS_STLEXD
+  "stlexh", // ARM_INS_STLEXH
+  "stlh", // ARM_INS_STLH
+  "stmda", // ARM_INS_STMDA
+  "stmdb", // ARM_INS_STMDB
+  "stm", // ARM_INS_STM
+  "stmib", // ARM_INS_STMIB
+  "strb", // ARM_INS_STRB
+  "strd", // ARM_INS_STRD
+  "strex", // ARM_INS_STREX
+  "strexb", // ARM_INS_STREXB
+  "strexd", // ARM_INS_STREXD
+  "strexh", // ARM_INS_STREXH
+  "strh", // ARM_INS_STRH
+  "strht", // ARM_INS_STRHT
+  "sub", // ARM_INS_SUB
+  "svc", // ARM_INS_SVC
+  "swp", // ARM_INS_SWP
+  "swpb", // ARM_INS_SWPB
+  "sxtab", // ARM_INS_SXTAB
+  "sxtab16", // ARM_INS_SXTAB16
+  "sxtah", // ARM_INS_SXTAH
+  "sxtb", // ARM_INS_SXTB
+  "sxtb16", // ARM_INS_SXTB16
+  "sxth", // ARM_INS_SXTH
+  "teq", // ARM_INS_TEQ
+  "trap", // ARM_INS_TRAP
+  "tsb", // ARM_INS_TSB
+  "tst", // ARM_INS_TST
+  "uadd16", // ARM_INS_UADD16
+  "uadd8", // ARM_INS_UADD8
+  "uasx", // ARM_INS_UASX
+  "ubfx", // ARM_INS_UBFX
+  "udf", // ARM_INS_UDF
+  "udiv", // ARM_INS_UDIV
+  "uhadd16", // ARM_INS_UHADD16
+  "uhadd8", // ARM_INS_UHADD8
+  "uhasx", // ARM_INS_UHASX
+  "uhsax", // ARM_INS_UHSAX
+  "uhsub16", // ARM_INS_UHSUB16
+  "uhsub8", // ARM_INS_UHSUB8
+  "umaal", // ARM_INS_UMAAL
+  "umlal", // ARM_INS_UMLAL
+  "umull", // ARM_INS_UMULL
+  "uqadd16", // ARM_INS_UQADD16
+  "uqadd8", // ARM_INS_UQADD8
+  "uqasx", // ARM_INS_UQASX
+  "uqsax", // ARM_INS_UQSAX
+  "uqsub16", // ARM_INS_UQSUB16
+  "uqsub8", // ARM_INS_UQSUB8
+  "usad8", // ARM_INS_USAD8
+  "usada8", // ARM_INS_USADA8
+  "usat", // ARM_INS_USAT
+  "usat16", // ARM_INS_USAT16
+  "usax", // ARM_INS_USAX
+  "usub16", // ARM_INS_USUB16
+  "usub8", // ARM_INS_USUB8
+  "uxtab", // ARM_INS_UXTAB
+  "uxtab16", // ARM_INS_UXTAB16
+  "uxtah", // ARM_INS_UXTAH
+  "uxtb", // ARM_INS_UXTB
+  "uxtb16", // ARM_INS_UXTB16
+  "uxth", // ARM_INS_UXTH
+  "vabal", // ARM_INS_VABAL
+  "vaba", // ARM_INS_VABA
+  "vabdl", // ARM_INS_VABDL
+  "vacge", // ARM_INS_VACGE
+  "vacgt", // ARM_INS_VACGT
+  "vaddhn", // ARM_INS_VADDHN
+  "vaddl", // ARM_INS_VADDL
+  "vaddw", // ARM_INS_VADDW
+  "vfmab", // ARM_INS_VFMAB
+  "vfmat", // ARM_INS_VFMAT
+  "vbif", // ARM_INS_VBIF
+  "vbit", // ARM_INS_VBIT
+  "vbsl", // ARM_INS_VBSL
+  "vceq", // ARM_INS_VCEQ
+  "vcge", // ARM_INS_VCGE
+  "vcgt", // ARM_INS_VCGT
+  "vcle", // ARM_INS_VCLE
+  "vclt", // ARM_INS_VCLT
+  "vcmpe", // ARM_INS_VCMPE
+  "vcnt", // ARM_INS_VCNT
+  "vdiv", // ARM_INS_VDIV
+  "vext", // ARM_INS_VEXT
+  "vfmal", // ARM_INS_VFMAL
+  "vfmsl", // ARM_INS_VFMSL
+  "vfnma", // ARM_INS_VFNMA
+  "vfnms", // ARM_INS_VFNMS
+  "vins", // ARM_INS_VINS
+  "vjcvt", // ARM_INS_VJCVT
+  "vldmdb", // ARM_INS_VLDMDB
+  "vldmia", // ARM_INS_VLDMIA
+  "vldr", // ARM_INS_VLDR
+  "vlldm", // ARM_INS_VLLDM
+  "vlstm", // ARM_INS_VLSTM
+  "vmlal", // ARM_INS_VMLAL
+  "vmls", // ARM_INS_VMLS
+  "vmlsl", // ARM_INS_VMLSL
+  "vmmla", // ARM_INS_VMMLA
+  "vmovx", // ARM_INS_VMOVX
+  "vmovl", // ARM_INS_VMOVL
+  "vmovn", // ARM_INS_VMOVN
+  "vmsr", // ARM_INS_VMSR
+  "vmull", // ARM_INS_VMULL
+  "vnmla", // ARM_INS_VNMLA
+  "vnmls", // ARM_INS_VNMLS
+  "vnmul", // ARM_INS_VNMUL
+  "vpadal", // ARM_INS_VPADAL
+  "vpaddl", // ARM_INS_VPADDL
+  "vpadd", // ARM_INS_VPADD
+  "vpmax", // ARM_INS_VPMAX
+  "vpmin", // ARM_INS_VPMIN
+  "vqdmlal", // ARM_INS_VQDMLAL
+  "vqdmlsl", // ARM_INS_VQDMLSL
+  "vqdmull", // ARM_INS_VQDMULL
+  "vqmovun", // ARM_INS_VQMOVUN
+  "vqmovn", // ARM_INS_VQMOVN
+  "vqrdmlsh", // ARM_INS_VQRDMLSH
+  "vqrshrn", // ARM_INS_VQRSHRN
+  "vqrshrun", // ARM_INS_VQRSHRUN
+  "vqshrn", // ARM_INS_VQSHRN
+  "vqshrun", // ARM_INS_VQSHRUN
+  "vraddhn", // ARM_INS_VRADDHN
+  "vrecpe", // ARM_INS_VRECPE
+  "vrecps", // ARM_INS_VRECPS
+  "vrintr", // ARM_INS_VRINTR
+  "vrshrn", // ARM_INS_VRSHRN
+  "vrsqrte", // ARM_INS_VRSQRTE
+  "vrsqrts", // ARM_INS_VRSQRTS
+  "vrsra", // ARM_INS_VRSRA
+  "vrsubhn", // ARM_INS_VRSUBHN
+  "vscclrm", // ARM_INS_VSCCLRM
+  "vsdot", // ARM_INS_VSDOT
+  "vseleq", // ARM_INS_VSELEQ
+  "vselge", // ARM_INS_VSELGE
+  "vselgt", // ARM_INS_VSELGT
+  "vselvs", // ARM_INS_VSELVS
+  "vshll", // ARM_INS_VSHLL
+  "vshrn", // ARM_INS_VSHRN
+  "vsmmla", // ARM_INS_VSMMLA
+  "vsqrt", // ARM_INS_VSQRT
+  "vsra", // ARM_INS_VSRA
+  "vstmdb", // ARM_INS_VSTMDB
+  "vstmia", // ARM_INS_VSTMIA
+  "vstr", // ARM_INS_VSTR
+  "vsubhn", // ARM_INS_VSUBHN
+  "vsubl", // ARM_INS_VSUBL
+  "vsubw", // ARM_INS_VSUBW
+  "vsudot", // ARM_INS_VSUDOT
+  "vswp", // ARM_INS_VSWP
+  "vtbl", // ARM_INS_VTBL
+  "vtbx", // ARM_INS_VTBX
+  "vcvtr", // ARM_INS_VCVTR
+  "vtrn", // ARM_INS_VTRN
+  "vtst", // ARM_INS_VTST
+  "vudot", // ARM_INS_VUDOT
+  "vummla", // ARM_INS_VUMMLA
+  "vusdot", // ARM_INS_VUSDOT
+  "vusmmla", // ARM_INS_VUSMMLA
+  "vuzp", // ARM_INS_VUZP
+  "vzip", // ARM_INS_VZIP
+  "addw", // ARM_INS_ADDW
+  "aut", // ARM_INS_AUT
+  "autg", // ARM_INS_AUTG
+  "bfl", // ARM_INS_BFL
+  "bflx", // ARM_INS_BFLX
+  "bf", // ARM_INS_BF
+  "bfcsel", // ARM_INS_BFCSEL
+  "bfx", // ARM_INS_BFX
+  "bti", // ARM_INS_BTI
+  "bxaut", // ARM_INS_BXAUT
+  "clrm", // ARM_INS_CLRM
+  "csel", // ARM_INS_CSEL
+  "csinc", // ARM_INS_CSINC
+  "csinv", // ARM_INS_CSINV
+  "csneg", // ARM_INS_CSNEG
+  "dcps1", // ARM_INS_DCPS1
+  "dcps2", // ARM_INS_DCPS2
+  "dcps3", // ARM_INS_DCPS3
+  "dls", // ARM_INS_DLS
+  "le", // ARM_INS_LE
+  "orn", // ARM_INS_ORN
+  "pac", // ARM_INS_PAC
+  "pacbti", // ARM_INS_PACBTI
+  "pacg", // ARM_INS_PACG
+  "sg", // ARM_INS_SG
+  "subs", // ARM_INS_SUBS
+  "subw", // ARM_INS_SUBW
+  "tbb", // ARM_INS_TBB
+  "tbh", // ARM_INS_TBH
+  "tt", // ARM_INS_TT
+  "tta", // ARM_INS_TTA
+  "ttat", // ARM_INS_TTAT
+  "ttt", // ARM_INS_TTT
+  "wls", // ARM_INS_WLS
+  "blxns", // ARM_INS_BLXNS
+  "bxns", // ARM_INS_BXNS
+  "cbnz", // ARM_INS_CBNZ
+  "cbz", // ARM_INS_CBZ
+  "pop", // ARM_INS_POP
+  "push", // ARM_INS_PUSH
+  "__brkdiv0", // ARM_INS___BRKDIV0
diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
new file mode 100644
index 000000000..512160716
--- /dev/null
+++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
@@ -0,0 +1,36917 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{{{ /* ARM_PHI (0) - ARM_INS_INVALID - PHINODE */
+ 0
+}}},
+{{{ /* ARM_INLINEASM (1) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_INLINEASM_BR (2) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_CFI_INSTRUCTION (3) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_EH_LABEL (4) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_GC_LABEL (5) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ANNOTATION_LABEL (6) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_KILL (7) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_EXTRACT_SUBREG (8) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_INSERT_SUBREG (9) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_IMPLICIT_DEF (10) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SUBREG_TO_REG (11) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_COPY_TO_REGCLASS (12) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_DBG_VALUE (13) - ARM_INS_INVALID - DBG_VALUE */
+ 0
+}}},
+{{{ /* ARM_DBG_VALUE_LIST (14) - ARM_INS_INVALID - DBG_VALUE_LIST */
+ 0
+}}},
+{{{ /* ARM_DBG_INSTR_REF (15) - ARM_INS_INVALID - DBG_INSTR_REF */
+ 0
+}}},
+{{{ /* ARM_DBG_PHI (16) - ARM_INS_INVALID - DBG_PHI */
+ 0
+}}},
+{{{ /* ARM_DBG_LABEL (17) - ARM_INS_INVALID - DBG_LABEL */
+ 0
+}}},
+{{{ /* ARM_REG_SEQUENCE (18) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_COPY (19) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BUNDLE (20) - ARM_INS_INVALID - BUNDLE */
+ 0
+}}},
+{{{ /* ARM_LIFETIME_START (21) - ARM_INS_INVALID - LIFETIME_START */
+ 0
+}}},
+{{{ /* ARM_LIFETIME_END (22) - ARM_INS_INVALID - LIFETIME_END */
+ 0
+}}},
+{{{ /* ARM_PSEUDO_PROBE (23) - ARM_INS_INVALID - PSEUDO_PROBE */
+ 0
+}}},
+{{{ /* ARM_ARITH_FENCE (24) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_STACKMAP (25) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_FENTRY_CALL (26) - ARM_INS_INVALID - # FEntry call */
+ 0
+}}},
+{{{ /* ARM_PATCHPOINT (27) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LOAD_STACK_GUARD (28) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PREALLOCATED_SETUP (29) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PREALLOCATED_ARG (30) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_STATEPOINT (31) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LOCAL_ESCAPE (32) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_FAULTING_OP (33) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_OP (34) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_FUNCTION_ENTER (35) - ARM_INS_INVALID - # XRay Function Enter. */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_RET (36) - ARM_INS_INVALID - # XRay Function Patchable RET. */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_FUNCTION_EXIT (37) - ARM_INS_INVALID - # XRay Function Exit. */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_TAIL_CALL (38) - ARM_INS_INVALID - # XRay Tail Call Exit. */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_EVENT_CALL (39) - ARM_INS_INVALID - # XRay Custom Event Log. */
+ 0
+}}},
+{{{ /* ARM_PATCHABLE_TYPED_EVENT_CALL (40) - ARM_INS_INVALID - # XRay Typed Event Log. */
+ 0
+}}},
+{{{ /* ARM_ICALL_BRANCH_FUNNEL (41) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MEMBARRIER (42) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ASSERT_SEXT (43) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ASSERT_ZEXT (44) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ASSERT_ALIGN (45) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ADD (46) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SUB (47) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_MUL (48) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SDIV (49) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UDIV (50) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SREM (51) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UREM (52) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SDIVREM (53) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UDIVREM (54) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_AND (55) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_OR (56) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_XOR (57) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_IMPLICIT_DEF (58) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_PHI (59) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FRAME_INDEX (60) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_GLOBAL_VALUE (61) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_EXTRACT (62) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UNMERGE_VALUES (63) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INSERT (64) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_MERGE_VALUES (65) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BUILD_VECTOR (66) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BUILD_VECTOR_TRUNC (67) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CONCAT_VECTORS (68) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_PTRTOINT (69) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTTOPTR (70) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BITCAST (71) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FREEZE (72) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC_FPTRUNC_ROUND (73) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC_TRUNC (74) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC_ROUND (75) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC_LRINT (76) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC_ROUNDEVEN (77) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_READCYCLECOUNTER (78) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_LOAD (79) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SEXTLOAD (80) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ZEXTLOAD (81) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INDEXED_LOAD (82) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INDEXED_SEXTLOAD (83) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INDEXED_ZEXTLOAD (84) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STORE (85) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INDEXED_STORE (86) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS (87) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMIC_CMPXCHG (88) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_XCHG (89) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_ADD (90) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_SUB (91) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_AND (92) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_NAND (93) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_OR (94) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_XOR (95) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_MAX (96) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_MIN (97) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_UMAX (98) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_UMIN (99) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_FADD (100) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_FSUB (101) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_FMAX (102) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_FMIN (103) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_UINC_WRAP (104) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ATOMICRMW_UDEC_WRAP (105) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FENCE (106) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BRCOND (107) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BRINDIRECT (108) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INVOKE_REGION_START (109) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC (110) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INTRINSIC_W_SIDE_EFFECTS (111) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ANYEXT (112) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_TRUNC (113) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CONSTANT (114) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FCONSTANT (115) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VASTART (116) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VAARG (117) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SEXT (118) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SEXT_INREG (119) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ZEXT (120) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SHL (121) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_LSHR (122) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ASHR (123) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FSHL (124) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FSHR (125) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ROTR (126) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ROTL (127) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ICMP (128) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FCMP (129) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SELECT (130) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UADDO (131) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UADDE (132) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_USUBO (133) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_USUBE (134) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SADDO (135) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SADDE (136) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SSUBO (137) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SSUBE (138) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UMULO (139) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SMULO (140) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UMULH (141) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SMULH (142) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UADDSAT (143) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SADDSAT (144) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_USUBSAT (145) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SSUBSAT (146) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_USHLSAT (147) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SSHLSAT (148) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SMULFIX (149) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UMULFIX (150) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SMULFIXSAT (151) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UMULFIXSAT (152) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SDIVFIX (153) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UDIVFIX (154) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SDIVFIXSAT (155) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UDIVFIXSAT (156) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FADD (157) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FSUB (158) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMUL (159) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMA (160) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMAD (161) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FDIV (162) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FREM (163) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FPOW (164) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FPOWI (165) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FEXP (166) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FEXP2 (167) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FLOG (168) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FLOG2 (169) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FLOG10 (170) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FNEG (171) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FPEXT (172) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FPTRUNC (173) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FPTOSI (174) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FPTOUI (175) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SITOFP (176) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UITOFP (177) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FABS (178) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FCOPYSIGN (179) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_IS_FPCLASS (180) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FCANONICALIZE (181) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMINNUM (182) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMAXNUM (183) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMINNUM_IEEE (184) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMAXNUM_IEEE (185) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMINIMUM (186) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FMAXIMUM (187) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_PTR_ADD (188) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_PTRMASK (189) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SMIN (190) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SMAX (191) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UMIN (192) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UMAX (193) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ABS (194) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_LROUND (195) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_LLROUND (196) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BR (197) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BRJT (198) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_INSERT_VECTOR_ELT (199) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_EXTRACT_VECTOR_ELT (200) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SHUFFLE_VECTOR (201) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CTTZ (202) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CTTZ_ZERO_UNDEF (203) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CTLZ (204) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CTLZ_ZERO_UNDEF (205) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_CTPOP (206) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BSWAP (207) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BITREVERSE (208) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FCEIL (209) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FCOS (210) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FSIN (211) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FSQRT (212) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FFLOOR (213) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FRINT (214) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_FNEARBYINT (215) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_ADDRSPACE_CAST (216) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BLOCK_ADDR (217) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_JUMP_TABLE (218) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_DYN_STACKALLOC (219) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FADD (220) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FSUB (221) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FMUL (222) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FDIV (223) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FREM (224) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FMA (225) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_STRICT_FSQRT (226) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_READ_REGISTER (227) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_WRITE_REGISTER (228) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_MEMCPY (229) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_MEMCPY_INLINE (230) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_MEMMOVE (231) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_MEMSET (232) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_BZERO (233) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_SEQ_FADD (234) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_SEQ_FMUL (235) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_FADD (236) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_FMUL (237) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_FMAX (238) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_FMIN (239) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_ADD (240) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_MUL (241) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_AND (242) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_OR (243) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_XOR (244) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_SMAX (245) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_SMIN (246) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_UMAX (247) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_VECREDUCE_UMIN (248) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_SBFX (249) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_G_UBFX (250) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ABS (251) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ADDSri (252) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ADDSrr (253) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ADDSrsi (254) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ADDSrsr (255) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ADJCALLSTACKDOWN (256) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_ADJCALLSTACKUP (257) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_ASRi (258) - ARM_INS_ASR - asr${s}${p} $Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ASRr (259) - ARM_INS_ASR - asr${s}${p} $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{{{ /* ARM_B (260) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BCCZi64 (261) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BCCi64 (262) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BLX_noip (263) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BLX_pred_noip (264) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BL_PUSHLR (265) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BMOVPCB_CALL (266) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BMOVPCRX_CALL (267) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BR_JTadd (268) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BR_JTm_i12 (269) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BR_JTm_rs (270) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BR_JTr (271) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_BX_CALL (272) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_CMP_SWAP_16 (273) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_CMP_SWAP_32 (274) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_CMP_SWAP_64 (275) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_CMP_SWAP_8 (276) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_CONSTPOOL_ENTRY (277) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_COPY_STRUCT_BYVAL_I32 (278) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_ITasm (279) - ARM_INS_IT - it$mask $cc */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */
+  { 0 }
+}},
+{{{ /* ARM_Int_eh_sjlj_dispatchsetup (280) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_Int_eh_sjlj_longjmp (281) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_Int_eh_sjlj_setjmp (282) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_Int_eh_sjlj_setjmp_nofp (283) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_Int_eh_sjlj_setup_dispatch (284) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_JUMPTABLE_ADDRS (285) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_JUMPTABLE_INSTS (286) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_JUMPTABLE_TBB (287) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_JUMPTABLE_TBH (288) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LDMIA_RET (289) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_LDRBT_POST (290) - ARM_INS_LDRBT - ldrbt${q} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRConstPool (291) - ARM_INS_LDR - ldr${q} $Rt, $immediate */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* immediate */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRHTii (292) - ARM_INS_LDRHT - ldrht${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_LDRLIT_ga_abs (293) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LDRLIT_ga_pcrel (294) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LDRLIT_ga_pcrel_ldr (295) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_LDRSBTii (296) - ARM_INS_LDRSBT - ldrsbt${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSHTii (297) - ARM_INS_LDRSHT - ldrsht${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRT_POST (298) - ARM_INS_LDRT - ldrt${q} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_LEApcrel (299) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LEApcrelJT (300) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_LOADDUAL (301) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_LSLi (302) - ARM_INS_LSL - lsl${s}${p} $Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_LSLr (303) - ARM_INS_LSL - lsl${s}${p} $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_LSRi (304) - ARM_INS_LSR - lsr${s}${p} $Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_LSRr (305) - ARM_INS_LSR - lsr${s}${p} $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{{{ /* ARM_MEMCPY (306) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MLAv5 (307) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVCCi (308) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVCCi16 (309) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVCCi32imm (310) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVCCr (311) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVCCsi (312) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVCCsr (313) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVPCRX (314) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVTi16_ga_pcrel (315) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOV_ga_pcrel (316) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOV_ga_pcrel_ldr (317) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVi16_ga_pcrel (318) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVi32imm (319) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVsra_flag (320) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MOVsrl_flag (321) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MQPRCopy (322) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MQQPRLoad (323) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MQQPRStore (324) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MQQQQPRLoad (325) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MQQQQPRStore (326) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MULv5 (327) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MVE_MEMCPYLOOPINST (328) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MVE_MEMSETLOOPINST (329) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_MVNCCi (330) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICADD (331) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICLDR (332) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICLDRB (333) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICLDRH (334) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICLDRSB (335) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICLDRSH (336) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICSTR (337) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICSTRB (338) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_PICSTRH (339) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_RORi (340) - ARM_INS_ROR - ror${s}${p} $Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RORr (341) - ARM_INS_ROR - ror${s}${p} $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{{{ /* ARM_RRX (342) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_RRXi (343) - ARM_INS_RRX - rrx${s}${p} $Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{{{ /* ARM_RSBSri (344) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_RSBSrsi (345) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_RSBSrsr (346) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_EpilogEnd (347) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_EpilogStart (348) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_Nop (349) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_Nop_Ret (350) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_PrologEnd (351) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_SaveFRegs (352) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_SaveLR (353) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_SaveRegs (354) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_SaveRegs_Ret (355) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_SaveSP (356) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SEH_StackAlloc (357) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SMLALv5 (358) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SMULLv5 (359) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SPACE (360) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_STOREDUAL (361) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_STRBT_POST (362) - ARM_INS_STRBT - strbt${q} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_STRBi_preidx (363) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_STRBr_preidx (364) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_STRH_preidx (365) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_STRT_POST (366) - ARM_INS_STRT - strt${q} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* q - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_STRi_preidx (367) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_STRr_preidx (368) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SUBS_PC_LR (369) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SUBSri (370) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SUBSrr (371) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SUBSrsi (372) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SUBSrsr (373) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SpeculationBarrierISBDSBEndBB (374) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_SpeculationBarrierSBEndBB (375) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_TAILJMPd (376) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_TAILJMPr (377) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_TAILJMPr4 (378) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_TCRETURNdi (379) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_TCRETURNri (380) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_TPsoft (381) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_UMLALv5 (382) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_UMULLv5 (383) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1LNdAsm_16 (384) - ARM_INS_VLD1 - vld1${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdAsm_32 (385) - ARM_INS_VLD1 - vld1${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdAsm_8 (386) - ARM_INS_VLD1 - vld1${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdWB_fixed_Asm_16 (387) - ARM_INS_VLD1 - vld1${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdWB_fixed_Asm_32 (388) - ARM_INS_VLD1 - vld1${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdWB_fixed_Asm_8 (389) - ARM_INS_VLD1 - vld1${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdWB_register_Asm_16 (390) - ARM_INS_VLD1 - vld1${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdWB_register_Asm_32 (391) - ARM_INS_VLD1 - vld1${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNdWB_register_Asm_8 (392) - ARM_INS_VLD1 - vld1${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdAsm_16 (393) - ARM_INS_VLD2 - vld2${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdAsm_32 (394) - ARM_INS_VLD2 - vld2${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdAsm_8 (395) - ARM_INS_VLD2 - vld2${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdWB_fixed_Asm_16 (396) - ARM_INS_VLD2 - vld2${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdWB_fixed_Asm_32 (397) - ARM_INS_VLD2 - vld2${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdWB_fixed_Asm_8 (398) - ARM_INS_VLD2 - vld2${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdWB_register_Asm_16 (399) - ARM_INS_VLD2 - vld2${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdWB_register_Asm_32 (400) - ARM_INS_VLD2 - vld2${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNdWB_register_Asm_8 (401) - ARM_INS_VLD2 - vld2${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNqAsm_16 (402) - ARM_INS_VLD2 - vld2${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNqAsm_32 (403) - ARM_INS_VLD2 - vld2${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNqWB_fixed_Asm_16 (404) - ARM_INS_VLD2 - vld2${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNqWB_fixed_Asm_32 (405) - ARM_INS_VLD2 - vld2${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNqWB_register_Asm_16 (406) - ARM_INS_VLD2 - vld2${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNqWB_register_Asm_32 (407) - ARM_INS_VLD2 - vld2${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdAsm_16 (408) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdAsm_32 (409) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdAsm_8 (410) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdWB_fixed_Asm_16 (411) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdWB_fixed_Asm_32 (412) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdWB_fixed_Asm_8 (413) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdWB_register_Asm_16 (414) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdWB_register_Asm_32 (415) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPdWB_register_Asm_8 (416) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqAsm_16 (417) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqAsm_32 (418) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqAsm_8 (419) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqWB_fixed_Asm_16 (420) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqWB_fixed_Asm_32 (421) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqWB_fixed_Asm_8 (422) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqWB_register_Asm_16 (423) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqWB_register_Asm_32 (424) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPqWB_register_Asm_8 (425) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdAsm_16 (426) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdAsm_32 (427) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdAsm_8 (428) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdWB_fixed_Asm_16 (429) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdWB_fixed_Asm_32 (430) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdWB_fixed_Asm_8 (431) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdWB_register_Asm_16 (432) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdWB_register_Asm_32 (433) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNdWB_register_Asm_8 (434) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNqAsm_16 (435) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNqAsm_32 (436) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNqWB_fixed_Asm_16 (437) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNqWB_fixed_Asm_32 (438) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNqWB_register_Asm_16 (439) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNqWB_register_Asm_32 (440) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dAsm_16 (441) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dAsm_32 (442) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dAsm_8 (443) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dWB_fixed_Asm_16 (444) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dWB_fixed_Asm_32 (445) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dWB_fixed_Asm_8 (446) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dWB_register_Asm_16 (447) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dWB_register_Asm_32 (448) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3dWB_register_Asm_8 (449) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qAsm_16 (450) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qAsm_32 (451) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qAsm_8 (452) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qWB_fixed_Asm_16 (453) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qWB_fixed_Asm_32 (454) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qWB_fixed_Asm_8 (455) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qWB_register_Asm_16 (456) - ARM_INS_VLD3 - vld3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qWB_register_Asm_32 (457) - ARM_INS_VLD3 - vld3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3qWB_register_Asm_8 (458) - ARM_INS_VLD3 - vld3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdAsm_16 (459) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdAsm_32 (460) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdAsm_8 (461) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdWB_fixed_Asm_16 (462) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdWB_fixed_Asm_32 (463) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdWB_fixed_Asm_8 (464) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdWB_register_Asm_16 (465) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdWB_register_Asm_32 (466) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPdWB_register_Asm_8 (467) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqAsm_16 (468) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqAsm_32 (469) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqAsm_8 (470) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqWB_fixed_Asm_16 (471) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqWB_fixed_Asm_32 (472) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqWB_fixed_Asm_8 (473) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqWB_register_Asm_16 (474) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqWB_register_Asm_32 (475) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPqWB_register_Asm_8 (476) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdAsm_16 (477) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdAsm_32 (478) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdAsm_8 (479) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdWB_fixed_Asm_16 (480) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdWB_fixed_Asm_32 (481) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdWB_fixed_Asm_8 (482) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdWB_register_Asm_16 (483) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdWB_register_Asm_32 (484) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNdWB_register_Asm_8 (485) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNqAsm_16 (486) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNqAsm_32 (487) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNqWB_fixed_Asm_16 (488) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNqWB_fixed_Asm_32 (489) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNqWB_register_Asm_16 (490) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNqWB_register_Asm_32 (491) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dAsm_16 (492) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dAsm_32 (493) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dAsm_8 (494) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dWB_fixed_Asm_16 (495) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dWB_fixed_Asm_32 (496) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dWB_fixed_Asm_8 (497) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dWB_register_Asm_16 (498) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dWB_register_Asm_32 (499) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4dWB_register_Asm_8 (500) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qAsm_16 (501) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qAsm_32 (502) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qAsm_8 (503) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qWB_fixed_Asm_16 (504) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qWB_fixed_Asm_32 (505) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qWB_fixed_Asm_8 (506) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qWB_register_Asm_16 (507) - ARM_INS_VLD4 - vld4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qWB_register_Asm_32 (508) - ARM_INS_VLD4 - vld4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4qWB_register_Asm_8 (509) - ARM_INS_VLD4 - vld4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VMOVD0 (510) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VMOVDcc (511) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VMOVHcc (512) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VMOVQ0 (513) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VMOVScc (514) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1LNdAsm_16 (515) - ARM_INS_VST1 - vst1${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdAsm_32 (516) - ARM_INS_VST1 - vst1${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdAsm_8 (517) - ARM_INS_VST1 - vst1${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdWB_fixed_Asm_16 (518) - ARM_INS_VST1 - vst1${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdWB_fixed_Asm_32 (519) - ARM_INS_VST1 - vst1${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdWB_fixed_Asm_8 (520) - ARM_INS_VST1 - vst1${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdWB_register_Asm_16 (521) - ARM_INS_VST1 - vst1${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdWB_register_Asm_32 (522) - ARM_INS_VST1 - vst1${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNdWB_register_Asm_8 (523) - ARM_INS_VST1 - vst1${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdAsm_16 (524) - ARM_INS_VST2 - vst2${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdAsm_32 (525) - ARM_INS_VST2 - vst2${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdAsm_8 (526) - ARM_INS_VST2 - vst2${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdWB_fixed_Asm_16 (527) - ARM_INS_VST2 - vst2${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdWB_fixed_Asm_32 (528) - ARM_INS_VST2 - vst2${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdWB_fixed_Asm_8 (529) - ARM_INS_VST2 - vst2${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdWB_register_Asm_16 (530) - ARM_INS_VST2 - vst2${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdWB_register_Asm_32 (531) - ARM_INS_VST2 - vst2${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNdWB_register_Asm_8 (532) - ARM_INS_VST2 - vst2${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNqAsm_16 (533) - ARM_INS_VST2 - vst2${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNqAsm_32 (534) - ARM_INS_VST2 - vst2${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNqWB_fixed_Asm_16 (535) - ARM_INS_VST2 - vst2${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNqWB_fixed_Asm_32 (536) - ARM_INS_VST2 - vst2${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNqWB_register_Asm_16 (537) - ARM_INS_VST2 - vst2${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNqWB_register_Asm_32 (538) - ARM_INS_VST2 - vst2${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdAsm_16 (539) - ARM_INS_VST3 - vst3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdAsm_32 (540) - ARM_INS_VST3 - vst3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdAsm_8 (541) - ARM_INS_VST3 - vst3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdWB_fixed_Asm_16 (542) - ARM_INS_VST3 - vst3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdWB_fixed_Asm_32 (543) - ARM_INS_VST3 - vst3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdWB_fixed_Asm_8 (544) - ARM_INS_VST3 - vst3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdWB_register_Asm_16 (545) - ARM_INS_VST3 - vst3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdWB_register_Asm_32 (546) - ARM_INS_VST3 - vst3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNdWB_register_Asm_8 (547) - ARM_INS_VST3 - vst3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNqAsm_16 (548) - ARM_INS_VST3 - vst3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNqAsm_32 (549) - ARM_INS_VST3 - vst3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNqWB_fixed_Asm_16 (550) - ARM_INS_VST3 - vst3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNqWB_fixed_Asm_32 (551) - ARM_INS_VST3 - vst3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNqWB_register_Asm_16 (552) - ARM_INS_VST3 - vst3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNqWB_register_Asm_32 (553) - ARM_INS_VST3 - vst3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dAsm_16 (554) - ARM_INS_VST3 - vst3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dAsm_32 (555) - ARM_INS_VST3 - vst3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dAsm_8 (556) - ARM_INS_VST3 - vst3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dWB_fixed_Asm_16 (557) - ARM_INS_VST3 - vst3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dWB_fixed_Asm_32 (558) - ARM_INS_VST3 - vst3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dWB_fixed_Asm_8 (559) - ARM_INS_VST3 - vst3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dWB_register_Asm_16 (560) - ARM_INS_VST3 - vst3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dWB_register_Asm_32 (561) - ARM_INS_VST3 - vst3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3dWB_register_Asm_8 (562) - ARM_INS_VST3 - vst3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qAsm_16 (563) - ARM_INS_VST3 - vst3${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qAsm_32 (564) - ARM_INS_VST3 - vst3${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qAsm_8 (565) - ARM_INS_VST3 - vst3${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qWB_fixed_Asm_16 (566) - ARM_INS_VST3 - vst3${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qWB_fixed_Asm_32 (567) - ARM_INS_VST3 - vst3${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qWB_fixed_Asm_8 (568) - ARM_INS_VST3 - vst3${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qWB_register_Asm_16 (569) - ARM_INS_VST3 - vst3${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qWB_register_Asm_32 (570) - ARM_INS_VST3 - vst3${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3qWB_register_Asm_8 (571) - ARM_INS_VST3 - vst3${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdAsm_16 (572) - ARM_INS_VST4 - vst4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdAsm_32 (573) - ARM_INS_VST4 - vst4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdAsm_8 (574) - ARM_INS_VST4 - vst4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdWB_fixed_Asm_16 (575) - ARM_INS_VST4 - vst4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdWB_fixed_Asm_32 (576) - ARM_INS_VST4 - vst4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdWB_fixed_Asm_8 (577) - ARM_INS_VST4 - vst4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdWB_register_Asm_16 (578) - ARM_INS_VST4 - vst4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdWB_register_Asm_32 (579) - ARM_INS_VST4 - vst4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNdWB_register_Asm_8 (580) - ARM_INS_VST4 - vst4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNqAsm_16 (581) - ARM_INS_VST4 - vst4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNqAsm_32 (582) - ARM_INS_VST4 - vst4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNqWB_fixed_Asm_16 (583) - ARM_INS_VST4 - vst4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNqWB_fixed_Asm_32 (584) - ARM_INS_VST4 - vst4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNqWB_register_Asm_16 (585) - ARM_INS_VST4 - vst4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNqWB_register_Asm_32 (586) - ARM_INS_VST4 - vst4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list - DPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* list - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dAsm_16 (587) - ARM_INS_VST4 - vst4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dAsm_32 (588) - ARM_INS_VST4 - vst4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dAsm_8 (589) - ARM_INS_VST4 - vst4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dWB_fixed_Asm_16 (590) - ARM_INS_VST4 - vst4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dWB_fixed_Asm_32 (591) - ARM_INS_VST4 - vst4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dWB_fixed_Asm_8 (592) - ARM_INS_VST4 - vst4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dWB_register_Asm_16 (593) - ARM_INS_VST4 - vst4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dWB_register_Asm_32 (594) - ARM_INS_VST4 - vst4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4dWB_register_Asm_8 (595) - ARM_INS_VST4 - vst4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qAsm_16 (596) - ARM_INS_VST4 - vst4${p}.16	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qAsm_32 (597) - ARM_INS_VST4 - vst4${p}.32	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qAsm_8 (598) - ARM_INS_VST4 - vst4${p}.8	$list, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qWB_fixed_Asm_16 (599) - ARM_INS_VST4 - vst4${p}.16	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qWB_fixed_Asm_32 (600) - ARM_INS_VST4 - vst4${p}.32	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qWB_fixed_Asm_8 (601) - ARM_INS_VST4 - vst4${p}.8	$list, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qWB_register_Asm_16 (602) - ARM_INS_VST4 - vst4${p}.16	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qWB_register_Asm_32 (603) - ARM_INS_VST4 - vst4${p}.32	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4qWB_register_Asm_8 (604) - ARM_INS_VST4 - vst4${p}.8	$list, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* list */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_WIN__CHKSTK (605) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_WIN__DBZCHK (606) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2ABS (607) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2ADDSri (608) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2ADDSrr (609) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2ADDSrs (610) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2BF_LabelPseudo (611) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2BR_JT (612) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2CALL_BTI (613) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2DoLoopStart (614) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2DoLoopStartTP (615) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2LDMIA_RET (616) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2LDRBpcrel (617) - ARM_INS_LDRB - ldrb${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRConstPool (618) - ARM_INS_LDR - ldr${p} $Rt, $immediate */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* immediate */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRHpcrel (619) - ARM_INS_LDRH - ldrh${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_t2LDRLIT_ga_pcrel (620) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2LDRSBpcrel (621) - ARM_INS_LDRSB - ldrsb${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSHpcrel (622) - ARM_INS_LDRSH - ldrsh${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDR_POST_imm (623) - ARM_INS_LDR - ldr${p}.w $Rt, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDR_PRE_imm (624) - ARM_INS_LDR - ldr${p}.w $Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_t2LDRpci_pic (625) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2LDRpcrel (626) - ARM_INS_LDR - ldr${p} $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_t2LEApcrel (627) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2LEApcrelJT (628) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2LoopDec (629) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2LoopEnd (630) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2LoopEndDec (631) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCCasr (632) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCCi (633) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCCi16 (634) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCCi32imm (635) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCClsl (636) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCClsr (637) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCCr (638) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVCCror (639) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2MOVSsi (640) - ARM_INS_MOVS - movs${p} $Rd, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MOVSsr (641) - ARM_INS_MOVS - movs${p} $Rd, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_t2MOVTi16_ga_pcrel (642) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOV_ga_pcrel (643) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVi16_ga_pcrel (644) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2MOVi32imm (645) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2MOVsi (646) - ARM_INS_MOV - mov${p} $Rd, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MOVsr (647) - ARM_INS_MOV - mov${p} $Rd, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_t2MVNCCi (648) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2RSBSri (649) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2RSBSrs (650) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2STRB_preidx (651) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2STRH_preidx (652) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2STR_POST_imm (653) - ARM_INS_STR - str${p}.w $Rt, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STR_PRE_imm (654) - ARM_INS_STR - str${p}.w $Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_t2STR_preidx (655) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2SUBSri (656) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2SUBSrr (657) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2SUBSrs (658) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2SpeculationBarrierISBDSBEndBB (659) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2SpeculationBarrierSBEndBB (660) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2TBB_JT (661) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2TBH_JT (662) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2WhileLoopSetup (663) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2WhileLoopStart (664) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2WhileLoopStartLR (665) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2WhileLoopStartTP (666) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADCS (667) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADDSi3 (668) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADDSi8 (669) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADDSrr (670) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADDframe (671) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADJCALLSTACKDOWN (672) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tADJCALLSTACKUP (673) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBLXNS_CALL (674) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBLXr_noip (675) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBL_PUSHLR (676) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBRIND (677) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBR_JTr (678) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBXNS_RET (679) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBX_CALL (680) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBX_RET (681) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBX_RET_vararg (682) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tBfar (683) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tCMP_SWAP_16 (684) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tCMP_SWAP_32 (685) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tCMP_SWAP_8 (686) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLDMIA_UPD (687) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_tLDRConstPool (688) - ARM_INS_LDR - ldr${p} $Rt, $immediate */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* immediate */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_tLDRLIT_ga_abs (689) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLDRLIT_ga_pcrel (690) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLDR_postidx (691) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLDRpci_pic (692) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLEApcrel (693) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLEApcrelJT (694) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tLSLSri (695) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tMOVCCr_pseudo (696) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tPOP_RET (697) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tRSBS (698) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tSBCS (699) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tSUBSi3 (700) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tSUBSi8 (701) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tSUBSrr (702) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tTAILJMPd (703) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tTAILJMPdND (704) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tTAILJMPr (705) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tTBB_JT (706) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tTBH_JT (707) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tTPsoft (708) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_ADCri (709) - ARM_INS_ADC - adc${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADCrr (710) - ARM_INS_ADC - adc${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADCrsi (711) - ARM_INS_ADC - adc${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADCrsr (712) - ARM_INS_ADC - adc${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADDri (713) - ARM_INS_ADD - add${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADDrr (714) - ARM_INS_ADD - add${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADDrsi (715) - ARM_INS_ADD - add${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADDrsr (716) - ARM_INS_ADD - add${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ADR (717) - ARM_INS_ADR - adr${p}	$Rd, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_AESD (718) - ARM_INS_AESD - aesd.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_AESE (719) - ARM_INS_AESE - aese.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_AESIMC (720) - ARM_INS_AESIMC - aesimc.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_AESMC (721) - ARM_INS_AESMC - aesmc.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_ANDri (722) - ARM_INS_AND - and${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ANDrr (723) - ARM_INS_AND - and${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ANDrsi (724) - ARM_INS_AND - and${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ANDrsr (725) - ARM_INS_AND - and${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_BF16VDOTI_VDOTD (726) - ARM_INS_VDOT - vdot.bf16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_BF16VDOTI_VDOTQ (727) - ARM_INS_VDOT - vdot.bf16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_BF16VDOTS_VDOTD (728) - ARM_INS_VDOT - vdot.bf16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_BF16VDOTS_VDOTQ (729) - ARM_INS_VDOT - vdot.bf16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_BF16_VCVT (730) - ARM_INS_VCVT - vcvt${p}.bf16.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BF16_VCVTB (731) - ARM_INS_VCVTB - vcvtb${p}.bf16.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BF16_VCVTT (732) - ARM_INS_VCVTT - vcvtt${p}.bf16.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BFC (733) - ARM_INS_BFC - bfc${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BFI (734) - ARM_INS_BFI - bfi${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BICri (735) - ARM_INS_BIC - bic${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_BICrr (736) - ARM_INS_BIC - bic${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_BICrsi (737) - ARM_INS_BIC - bic${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_BICrsr (738) - ARM_INS_BIC - bic${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_BKPT (739) - ARM_INS_BKPT - bkpt	$val */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */
+  { 0 }
+}},
+{ /* ARM_BL (740) - ARM_INS_BL - bl	$func */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { 0 }
+}},
+{ /* ARM_BLX (741) - ARM_INS_BLX - blx	$func */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { 0 }
+}},
+{ /* ARM_BLX_pred (742) - ARM_INS_BLX - blx${p}	$func */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BLXi (743) - ARM_INS_BLX - blx	$target */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* target */
+  { 0 }
+}},
+{ /* ARM_BL_pred (744) - ARM_INS_BL - bl${p}	$func */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BX (745) - ARM_INS_BX - bx	$dst */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { 0 }
+}},
+{ /* ARM_BXJ (746) - ARM_INS_BXJ - bxj${p}	$func */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BX_RET (747) - ARM_INS_BX - bx${p}	lr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_BX_pred (748) - ARM_INS_BX - bx${p}	$dst */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_Bcc (749) - ARM_INS_B - b${p}	$target */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX1 (750) - ARM_INS_CX1 - cx1	$coproc, $Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX1A (751) - ARM_INS_CX1A - cx1a${p}	$coproc, $Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX1D (752) - ARM_INS_CX1D - cx1d	$coproc, $Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX1DA (753) - ARM_INS_CX1DA - cx1da${p}	$coproc, $Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX2 (754) - ARM_INS_CX2 - cx2	$coproc, $Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX2A (755) - ARM_INS_CX2A - cx2a${p}	$coproc, $Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX2D (756) - ARM_INS_CX2D - cx2d	$coproc, $Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX2DA (757) - ARM_INS_CX2DA - cx2da${p}	$coproc, $Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX3 (758) - ARM_INS_CX3 - cx3	$coproc, $Rd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX3A (759) - ARM_INS_CX3A - cx3a${p}	$coproc, $Rd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX3D (760) - ARM_INS_CX3D - cx3d	$coproc, $Rd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_CX3DA (761) - ARM_INS_CX3DA - cx3da${p}	$coproc, $Rd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX1A_fpdp (762) - ARM_INS_VCX1A - vcx1a	$coproc, $Vd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX1A_fpsp (763) - ARM_INS_VCX1A - vcx1a	$coproc, $Vd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX1A_vec (764) - ARM_INS_VCX1A - vcx1a${vp}	$coproc, $Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX1_fpdp (765) - ARM_INS_VCX1 - vcx1	$coproc, $Vd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX1_fpsp (766) - ARM_INS_VCX1 - vcx1	$coproc, $Vd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX1_vec (767) - ARM_INS_VCX1 - vcx1${vp}	$coproc, $Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX2A_fpdp (768) - ARM_INS_VCX2A - vcx2a	$coproc, $Vd, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX2A_fpsp (769) - ARM_INS_VCX2A - vcx2a	$coproc, $Vd, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX2A_vec (770) - ARM_INS_VCX2A - vcx2a${vp}	$coproc, $Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX2_fpdp (771) - ARM_INS_VCX2 - vcx2	$coproc, $Vd, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX2_fpsp (772) - ARM_INS_VCX2 - vcx2	$coproc, $Vd, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX2_vec (773) - ARM_INS_VCX2 - vcx2${vp}	$coproc, $Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX3A_fpdp (774) - ARM_INS_VCX3A - vcx3a	$coproc, $Vd, $Vn, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX3A_fpsp (775) - ARM_INS_VCX3A - vcx3a	$coproc, $Vd, $Vn, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX3A_vec (776) - ARM_INS_VCX3A - vcx3a${vp}	$coproc, $Qd, $Qn, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX3_fpdp (777) - ARM_INS_VCX3 - vcx3	$coproc, $Vd, $Vn, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX3_fpsp (778) - ARM_INS_VCX3 - vcx3	$coproc, $Vd, $Vn, $Vm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_CDE_VCX3_vec (779) - ARM_INS_VCX3 - vcx3${vp}	$coproc, $Qd, $Qn, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* coproc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_CDP (780) - ARM_INS_CDP - cdp${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CDP2 (781) - ARM_INS_CDP2 - cdp2	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { 0 }
+}},
+{ /* ARM_CLREX (782) - ARM_INS_CLREX - clrex */
+{
+  { 0 }
+}},
+{ /* ARM_CLZ (783) - ARM_INS_CLZ - clz${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMNri (784) - ARM_INS_CMN - cmn${p}	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMNzrr (785) - ARM_INS_CMN - cmn${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMNzrsi (786) - ARM_INS_CMN - cmn${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMNzrsr (787) - ARM_INS_CMN - cmn${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMPri (788) - ARM_INS_CMP - cmp${p}	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMPrr (789) - ARM_INS_CMP - cmp${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMPrsi (790) - ARM_INS_CMP - cmp${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CMPrsr (791) - ARM_INS_CMP - cmp${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_CPS1p (792) - ARM_INS_CPS - cps	$mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_CPS2p (793) - ARM_INS_CPS - cps$imod	$iflags */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */
+  { 0 }
+}},
+{ /* ARM_CPS3p (794) - ARM_INS_CPS - cps$imod	$iflags, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_CRC32B (795) - ARM_INS_CRC32B - crc32b	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_CRC32CB (796) - ARM_INS_CRC32CB - crc32cb	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_CRC32CH (797) - ARM_INS_CRC32CH - crc32ch	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_CRC32CW (798) - ARM_INS_CRC32CW - crc32cw	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_CRC32H (799) - ARM_INS_CRC32H - crc32h	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_CRC32W (800) - ARM_INS_CRC32W - crc32w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_DBG (801) - ARM_INS_DBG - dbg${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_DMB (802) - ARM_INS_DMB - dmb	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { 0 }
+}},
+{ /* ARM_DSB (803) - ARM_INS_DSB - dsb	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { 0 }
+}},
+{ /* ARM_EORri (804) - ARM_INS_EOR - eor${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_EORrr (805) - ARM_INS_EOR - eor${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_EORrsi (806) - ARM_INS_EOR - eor${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_EORrsr (807) - ARM_INS_EOR - eor${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ERET (808) - ARM_INS_ERET - eret${p} */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_FCONSTD (809) - ARM_INS_VMOV - vmov${p}.f64	$Dd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_FP, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_FCONSTH (810) - ARM_INS_VMOV - vmov${p}.f16	$Sd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_FP, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_FCONSTS (811) - ARM_INS_VMOV - vmov${p}.f32	$Sd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_FP, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_FLDMXDB_UPD (812) - ARM_INS_FLDMDBX - fldmdbx${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_FLDMXIA (813) - ARM_INS_FLDMIAX - fldmiax${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_FLDMXIA_UPD (814) - ARM_INS_FLDMIAX - fldmiax${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_FMSTAT (815) - ARM_INS_VMRS - vmrs${p}	APSR_nzcv, fpscr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_FSTMXDB_UPD (816) - ARM_INS_FSTMDBX - fstmdbx${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_FSTMXIA (817) - ARM_INS_FSTMIAX - fstmiax${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_FSTMXIA_UPD (818) - ARM_INS_FSTMIAX - fstmiax${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_HINT (819) - ARM_INS_HINT - hint${p}	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_HLT (820) - ARM_INS_HLT - hlt	$val */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */
+  { 0 }
+}},
+{ /* ARM_HVC (821) - ARM_INS_HVC - hvc	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_ISB (822) - ARM_INS_ISB - isb	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { 0 }
+}},
+{ /* ARM_LDA (823) - ARM_INS_LDA - lda${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDAB (824) - ARM_INS_LDAB - ldab${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDAEX (825) - ARM_INS_LDAEX - ldaex${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDAEXB (826) - ARM_INS_LDAEXB - ldaexb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDAEXD (827) - ARM_INS_LDAEXD - ldaexd${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDAEXH (828) - ARM_INS_LDAEXH - ldaexh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDAH (829) - ARM_INS_LDAH - ldah${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC2L_OFFSET (830) - ARM_INS_LDC2L - ldc2l	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC2L_OPTION (831) - ARM_INS_LDC2L - ldc2l	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { 0 }
+}},
+{ /* ARM_LDC2L_POST (832) - ARM_INS_LDC2L - ldc2l	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC2L_PRE (833) - ARM_INS_LDC2L - ldc2l	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC2_OFFSET (834) - ARM_INS_LDC2 - ldc2	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC2_OPTION (835) - ARM_INS_LDC2 - ldc2	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { 0 }
+}},
+{ /* ARM_LDC2_POST (836) - ARM_INS_LDC2 - ldc2	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC2_PRE (837) - ARM_INS_LDC2 - ldc2	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDCL_OFFSET (838) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDCL_OPTION (839) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDCL_POST (840) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDCL_PRE (841) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC_OFFSET (842) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC_OPTION (843) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC_POST (844) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDC_PRE (845) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDMDA (846) - ARM_INS_LDMDA - ldmda${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMDA_UPD (847) - ARM_INS_LDMDA - ldmda${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMDB (848) - ARM_INS_LDMDB - ldmdb${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMDB_UPD (849) - ARM_INS_LDMDB - ldmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMIA (850) - ARM_INS_LDM - ldm${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMIA_UPD (851) - ARM_INS_LDM - ldm${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMIB (852) - ARM_INS_LDMIB - ldmib${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDMIB_UPD (853) - ARM_INS_LDMIB - ldmib${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_LDRBT_POST_IMM (854) - ARM_INS_LDRBT - ldrbt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRBT_POST_REG (855) - ARM_INS_LDRBT - ldrbt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRB_POST_IMM (856) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRB_POST_REG (857) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRB_PRE_IMM (858) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRB_PRE_REG (859) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRBi12 (860) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRBrs (861) - ARM_INS_LDRB - ldrb${p}	$Rt, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRD (862) - ARM_INS_LDRD - ldrd${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRD_POST (863) - ARM_INS_LDRD - ldrd${p}	$Rt, $Rt2, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRD_PRE (864) - ARM_INS_LDRD - ldrd${p}	$Rt, $Rt2, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDREX (865) - ARM_INS_LDREX - ldrex${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDREXB (866) - ARM_INS_LDREXB - ldrexb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDREXD (867) - ARM_INS_LDREXD - ldrexd${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDREXH (868) - ARM_INS_LDREXH - ldrexh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRH (869) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRHTi (870) - ARM_INS_LDRHT - ldrht${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRHTr (871) - ARM_INS_LDRHT - ldrht${p}	$Rt, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRH_POST (872) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRH_PRE (873) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSB (874) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSBTi (875) - ARM_INS_LDRSBT - ldrsbt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSBTr (876) - ARM_INS_LDRSBT - ldrsbt${p}	$Rt, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSB_POST (877) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSB_PRE (878) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSH (879) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSHTi (880) - ARM_INS_LDRSHT - ldrsht${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSHTr (881) - ARM_INS_LDRSHT - ldrsht${p}	$Rt, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSH_POST (882) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRSH_PRE (883) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRT_POST_IMM (884) - ARM_INS_LDRT - ldrt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRT_POST_REG (885) - ARM_INS_LDRT - ldrt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDR_POST_IMM (886) - ARM_INS_LDR - ldr${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDR_POST_REG (887) - ARM_INS_LDR - ldr${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDR_PRE_IMM (888) - ARM_INS_LDR - ldr${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDR_PRE_REG (889) - ARM_INS_LDR - ldr${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_LDRcp (890) - ARM_INS_INVALID - ldr${p}	$Rt, $addr */
+ 0
+}}},
+{ /* ARM_LDRi12 (891) - ARM_INS_LDR - ldr${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_LDRrs (892) - ARM_INS_LDR - ldr${p}	$Rt, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MCR (893) - ARM_INS_MCR - mcr${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MCR2 (894) - ARM_INS_MCR2 - mcr2	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { 0 }
+}},
+{ /* ARM_MCRR (895) - ARM_INS_MCRR - mcrr${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MCRR2 (896) - ARM_INS_MCRR2 - mcrr2	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { 0 }
+}},
+{ /* ARM_MLA (897) - ARM_INS_MLA - mla${s}${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MLS (898) - ARM_INS_MLS - mls${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MOVPCLR (899) - ARM_INS_MOV - mov${p}	pc, lr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MOVTi16 (900) - ARM_INS_MOVT - movt${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MOVi (901) - ARM_INS_MOV - mov${s}${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MOVi16 (902) - ARM_INS_MOVW - movw${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MOVr (903) - ARM_INS_MOV - mov${s}${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MOVr_TC (904) - ARM_INS_MOV - mov${s}${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MOVsi (905) - ARM_INS_MOV - mov${s}${p}	$Rd, $src */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MOVsr (906) - ARM_INS_MOV - mov${s}${p}	$Rd, $src */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MRC (907) - ARM_INS_MRC - mrc${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MRC2 (908) - ARM_INS_MRC2 - mrc2	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { 0 }
+}},
+{ /* ARM_MRRC (909) - ARM_INS_MRRC - mrrc${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MRRC2 (910) - ARM_INS_MRRC2 - mrrc2	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { 0 }
+}},
+{ /* ARM_MRS (911) - ARM_INS_MRS - mrs${p}	$Rd, apsr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MRSbanked (912) - ARM_INS_MRS - mrs${p}	$Rd, $banked */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MRSsys (913) - ARM_INS_MRS - mrs${p}	$Rd, spsr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MSR (914) - ARM_INS_MSR - msr${p}	$mask, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MSRbanked (915) - ARM_INS_MSR - msr${p}	$banked, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MSRi (916) - ARM_INS_MSR - msr${p}	$mask, $imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MUL (917) - ARM_INS_MUL - mul${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MVE_ASRLi (918) - ARM_INS_ASRL - asrl${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_ASRLr (919) - ARM_INS_ASRL - asrl${p}	$RdaLo, $RdaHi, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_DLSTP_16 (920) - ARM_INS_DLSTP - dlstp.16	$LR, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_MVE_DLSTP_32 (921) - ARM_INS_DLSTP - dlstp.32	$LR, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_MVE_DLSTP_64 (922) - ARM_INS_DLSTP - dlstp.64	$LR, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_MVE_DLSTP_8 (923) - ARM_INS_DLSTP - dlstp.8	$LR, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_MVE_LCTP (924) - ARM_INS_LCTP - lctp${p}	 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_LETP (925) - ARM_INS_LETP - letp	$LRin, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRin */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_MVE_LSLLi (926) - ARM_INS_LSLL - lsll${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_LSLLr (927) - ARM_INS_LSLL - lsll${p}	$RdaLo, $RdaHi, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_LSRL (928) - ARM_INS_LSRL - lsrl${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_SQRSHR (929) - ARM_INS_SQRSHR - sqrshr${p}	$RdaSrc, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_SQRSHRL (930) - ARM_INS_SQRSHRL - sqrshrl${p}	$RdaLo, $RdaHi, $sat, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_SQSHL (931) - ARM_INS_SQSHL - sqshl${p}	$RdaSrc, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_SQSHLL (932) - ARM_INS_SQSHLL - sqshll${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_SRSHR (933) - ARM_INS_SRSHR - srshr${p}	$RdaSrc, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_SRSHRL (934) - ARM_INS_SRSHRL - srshrl${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_UQRSHL (935) - ARM_INS_UQRSHL - uqrshl${p}	$RdaSrc, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_UQRSHLL (936) - ARM_INS_UQRSHLL - uqrshll${p}	$RdaLo, $RdaHi, $sat, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_UQSHL (937) - ARM_INS_UQSHL - uqshl${p}	$RdaSrc, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_UQSHLL (938) - ARM_INS_UQSHLL - uqshll${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_URSHR (939) - ARM_INS_URSHR - urshr${p}	$RdaSrc, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_URSHRL (940) - ARM_INS_URSHRL - urshrl${p}	$RdaLo, $RdaHi, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VABAVs16 (941) - ARM_INS_VABAV - vabav${vp}.s16	$Rda, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VABAVs32 (942) - ARM_INS_VABAV - vabav${vp}.s32	$Rda, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VABAVs8 (943) - ARM_INS_VABAV - vabav${vp}.s8	$Rda, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VABAVu16 (944) - ARM_INS_VABAV - vabav${vp}.u16	$Rda, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VABAVu32 (945) - ARM_INS_VABAV - vabav${vp}.u32	$Rda, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VABAVu8 (946) - ARM_INS_VABAV - vabav${vp}.u8	$Rda, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDf16 (947) - ARM_INS_VABD - vabd${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDf32 (948) - ARM_INS_VABD - vabd${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDs16 (949) - ARM_INS_VABD - vabd${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDs32 (950) - ARM_INS_VABD - vabd${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDs8 (951) - ARM_INS_VABD - vabd${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDu16 (952) - ARM_INS_VABD - vabd${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDu32 (953) - ARM_INS_VABD - vabd${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABDu8 (954) - ARM_INS_VABD - vabd${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABSf16 (955) - ARM_INS_VABS - vabs${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABSf32 (956) - ARM_INS_VABS - vabs${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABSs16 (957) - ARM_INS_VABS - vabs${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABSs32 (958) - ARM_INS_VABS - vabs${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VABSs8 (959) - ARM_INS_VABS - vabs${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADC (960) - ARM_INS_VADC - vadc${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryin */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADCI (961) - ARM_INS_VADCI - vadci${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDLVs32acc (962) - ARM_INS_VADDLVA - vaddlva${vp}.s32	$RdaLo, $RdaHi, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDLVs32no_acc (963) - ARM_INS_VADDLV - vaddlv${vp}.s32	$RdaLo, $RdaHi, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDLVu32acc (964) - ARM_INS_VADDLVA - vaddlva${vp}.u32	$RdaLo, $RdaHi, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDLVu32no_acc (965) - ARM_INS_VADDLV - vaddlv${vp}.u32	$RdaLo, $RdaHi, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVs16acc (966) - ARM_INS_VADDVA - vaddva${vp}.s16	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVs16no_acc (967) - ARM_INS_VADDV - vaddv${vp}.s16	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVs32acc (968) - ARM_INS_VADDVA - vaddva${vp}.s32	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVs32no_acc (969) - ARM_INS_VADDV - vaddv${vp}.s32	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVs8acc (970) - ARM_INS_VADDVA - vaddva${vp}.s8	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVs8no_acc (971) - ARM_INS_VADDV - vaddv${vp}.s8	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVu16acc (972) - ARM_INS_VADDVA - vaddva${vp}.u16	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVu16no_acc (973) - ARM_INS_VADDV - vaddv${vp}.u16	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVu32acc (974) - ARM_INS_VADDVA - vaddva${vp}.u32	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVu32no_acc (975) - ARM_INS_VADDV - vaddv${vp}.u32	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVu8acc (976) - ARM_INS_VADDVA - vaddva${vp}.u8	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDVu8no_acc (977) - ARM_INS_VADDV - vaddv${vp}.u8	$Rda, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VADD_qr_f16 (978) - ARM_INS_VADD - vadd${vp}.f16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADD_qr_f32 (979) - ARM_INS_VADD - vadd${vp}.f32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADD_qr_i16 (980) - ARM_INS_VADD - vadd${vp}.i16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADD_qr_i32 (981) - ARM_INS_VADD - vadd${vp}.i32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADD_qr_i8 (982) - ARM_INS_VADD - vadd${vp}.i8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDf16 (983) - ARM_INS_VADD - vadd${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDf32 (984) - ARM_INS_VADD - vadd${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDi16 (985) - ARM_INS_VADD - vadd${vp}.i16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDi32 (986) - ARM_INS_VADD - vadd${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VADDi8 (987) - ARM_INS_VADD - vadd${vp}.i8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VAND (988) - ARM_INS_VAND - vand${vp}	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VBIC (989) - ARM_INS_VBIC - vbic${vp}	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VBICimmi16 (990) - ARM_INS_VBIC - vbic${vp}.i16	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VBICimmi32 (991) - ARM_INS_VBIC - vbic${vp}.i32	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VBRSR16 (992) - ARM_INS_VBRSR - vbrsr${vp}.16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VBRSR32 (993) - ARM_INS_VBRSR - vbrsr${vp}.32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VBRSR8 (994) - ARM_INS_VBRSR - vbrsr${vp}.8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCADDf16 (995) - ARM_INS_VCADD - vcadd${vp}.f16	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCADDf32 (996) - ARM_INS_VCADD - vcadd${vp}.f32	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCADDi16 (997) - ARM_INS_VCADD - vcadd${vp}.i16	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCADDi32 (998) - ARM_INS_VCADD - vcadd${vp}.i32	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCADDi8 (999) - ARM_INS_VCADD - vcadd${vp}.i8	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCLSs16 (1000) - ARM_INS_VCLS - vcls${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCLSs32 (1001) - ARM_INS_VCLS - vcls${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCLSs8 (1002) - ARM_INS_VCLS - vcls${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCLZs16 (1003) - ARM_INS_VCLZ - vclz${vp}.i16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCLZs32 (1004) - ARM_INS_VCLZ - vclz${vp}.i32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCLZs8 (1005) - ARM_INS_VCLZ - vclz${vp}.i8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMLAf16 (1006) - ARM_INS_VCMLA - vcmla${vp}.f16	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMLAf32 (1007) - ARM_INS_VCMLA - vcmla${vp}.f32	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPf16 (1008) - ARM_INS_VCMP - vcmp${vp}.f16	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPf16r (1009) - ARM_INS_VCMP - vcmp${vp}.f16	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPf32 (1010) - ARM_INS_VCMP - vcmp${vp}.f32	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPf32r (1011) - ARM_INS_VCMP - vcmp${vp}.f32	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPi16 (1012) - ARM_INS_VCMP - vcmp${vp}.i16	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPi16r (1013) - ARM_INS_VCMP - vcmp${vp}.i16	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPi32 (1014) - ARM_INS_VCMP - vcmp${vp}.i32	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPi32r (1015) - ARM_INS_VCMP - vcmp${vp}.i32	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPi8 (1016) - ARM_INS_VCMP - vcmp${vp}.i8	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPi8r (1017) - ARM_INS_VCMP - vcmp${vp}.i8	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPs16 (1018) - ARM_INS_VCMP - vcmp${vp}.s16	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPs16r (1019) - ARM_INS_VCMP - vcmp${vp}.s16	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPs32 (1020) - ARM_INS_VCMP - vcmp${vp}.s32	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPs32r (1021) - ARM_INS_VCMP - vcmp${vp}.s32	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPs8 (1022) - ARM_INS_VCMP - vcmp${vp}.s8	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPs8r (1023) - ARM_INS_VCMP - vcmp${vp}.s8	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPu16 (1024) - ARM_INS_VCMP - vcmp${vp}.u16	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPu16r (1025) - ARM_INS_VCMP - vcmp${vp}.u16	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPu32 (1026) - ARM_INS_VCMP - vcmp${vp}.u32	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPu32r (1027) - ARM_INS_VCMP - vcmp${vp}.u32	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPu8 (1028) - ARM_INS_VCMP - vcmp${vp}.u8	$fc, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMPu8r (1029) - ARM_INS_VCMP - vcmp${vp}.u8	$fc, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMULf16 (1030) - ARM_INS_VCMUL - vcmul${vp}.f16	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCMULf32 (1031) - ARM_INS_VCMUL - vcmul${vp}.f32	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCTP16 (1032) - ARM_INS_VCTP - vctp${vp}.16	$Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCTP32 (1033) - ARM_INS_VCTP - vctp${vp}.32	$Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCTP64 (1034) - ARM_INS_VCTP - vctp${vp}.64	$Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCTP8 (1035) - ARM_INS_VCTP - vctp${vp}.8	$Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf16f32bh (1036) - ARM_INS_VCVTB - vcvtb${vp}.f16.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf16f32th (1037) - ARM_INS_VCVTT - vcvtt${vp}.f16.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf16s16_fix (1038) - ARM_INS_VCVT - vcvt${vp}.f16.s16	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf16s16n (1039) - ARM_INS_VCVT - vcvt${vp}.f16.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf16u16_fix (1040) - ARM_INS_VCVT - vcvt${vp}.f16.u16	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf16u16n (1041) - ARM_INS_VCVT - vcvt${vp}.f16.u16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf32f16bh (1042) - ARM_INS_VCVTB - vcvtb${vp}.f32.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf32f16th (1043) - ARM_INS_VCVTT - vcvtt${vp}.f32.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf32s32_fix (1044) - ARM_INS_VCVT - vcvt${vp}.f32.s32	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf32s32n (1045) - ARM_INS_VCVT - vcvt${vp}.f32.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf32u32_fix (1046) - ARM_INS_VCVT - vcvt${vp}.f32.u32	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTf32u32n (1047) - ARM_INS_VCVT - vcvt${vp}.f32.u32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs16f16_fix (1048) - ARM_INS_VCVT - vcvt${vp}.s16.f16	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs16f16a (1049) - ARM_INS_VCVTA - vcvta${vp}.s16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs16f16m (1050) - ARM_INS_VCVTM - vcvtm${vp}.s16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs16f16n (1051) - ARM_INS_VCVTN - vcvtn${vp}.s16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs16f16p (1052) - ARM_INS_VCVTP - vcvtp${vp}.s16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs16f16z (1053) - ARM_INS_VCVT - vcvt${vp}.s16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs32f32_fix (1054) - ARM_INS_VCVT - vcvt${vp}.s32.f32	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs32f32a (1055) - ARM_INS_VCVTA - vcvta${vp}.s32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs32f32m (1056) - ARM_INS_VCVTM - vcvtm${vp}.s32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs32f32n (1057) - ARM_INS_VCVTN - vcvtn${vp}.s32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs32f32p (1058) - ARM_INS_VCVTP - vcvtp${vp}.s32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTs32f32z (1059) - ARM_INS_VCVT - vcvt${vp}.s32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu16f16_fix (1060) - ARM_INS_VCVT - vcvt${vp}.u16.f16	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu16f16a (1061) - ARM_INS_VCVTA - vcvta${vp}.u16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu16f16m (1062) - ARM_INS_VCVTM - vcvtm${vp}.u16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu16f16n (1063) - ARM_INS_VCVTN - vcvtn${vp}.u16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu16f16p (1064) - ARM_INS_VCVTP - vcvtp${vp}.u16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu16f16z (1065) - ARM_INS_VCVT - vcvt${vp}.u16.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu32f32_fix (1066) - ARM_INS_VCVT - vcvt${vp}.u32.f32	$Qd, $Qm, $imm6 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm6 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu32f32a (1067) - ARM_INS_VCVTA - vcvta${vp}.u32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu32f32m (1068) - ARM_INS_VCVTM - vcvtm${vp}.u32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu32f32n (1069) - ARM_INS_VCVTN - vcvtn${vp}.u32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu32f32p (1070) - ARM_INS_VCVTP - vcvtp${vp}.u32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VCVTu32f32z (1071) - ARM_INS_VCVT - vcvt${vp}.u32.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDDUPu16 (1072) - ARM_INS_VDDUP - vddup${vp}.u16	$Qd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDDUPu32 (1073) - ARM_INS_VDDUP - vddup${vp}.u32	$Qd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDDUPu8 (1074) - ARM_INS_VDDUP - vddup${vp}.u8	$Qd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDUP16 (1075) - ARM_INS_VDUP - vdup${vp}.16	$Qd, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDUP32 (1076) - ARM_INS_VDUP - vdup${vp}.32	$Qd, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDUP8 (1077) - ARM_INS_VDUP - vdup${vp}.8	$Qd, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDWDUPu16 (1078) - ARM_INS_VDWDUP - vdwdup${vp}.u16	$Qd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDWDUPu32 (1079) - ARM_INS_VDWDUP - vdwdup${vp}.u32	$Qd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VDWDUPu8 (1080) - ARM_INS_VDWDUP - vdwdup${vp}.u8	$Qd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VEOR (1081) - ARM_INS_VEOR - veor${vp}	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMA_qr_Sf16 (1082) - ARM_INS_VFMAS - vfmas${vp}.f16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMA_qr_Sf32 (1083) - ARM_INS_VFMAS - vfmas${vp}.f32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMA_qr_f16 (1084) - ARM_INS_VFMA - vfma${vp}.f16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMA_qr_f32 (1085) - ARM_INS_VFMA - vfma${vp}.f32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMAf16 (1086) - ARM_INS_VFMA - vfma${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMAf32 (1087) - ARM_INS_VFMA - vfma${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMSf16 (1088) - ARM_INS_VFMS - vfms${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VFMSf32 (1089) - ARM_INS_VFMS - vfms${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADD_qr_s16 (1090) - ARM_INS_VHADD - vhadd${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADD_qr_s32 (1091) - ARM_INS_VHADD - vhadd${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADD_qr_s8 (1092) - ARM_INS_VHADD - vhadd${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADD_qr_u16 (1093) - ARM_INS_VHADD - vhadd${vp}.u16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADD_qr_u32 (1094) - ARM_INS_VHADD - vhadd${vp}.u32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADD_qr_u8 (1095) - ARM_INS_VHADD - vhadd${vp}.u8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADDs16 (1096) - ARM_INS_VHADD - vhadd${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADDs32 (1097) - ARM_INS_VHADD - vhadd${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADDs8 (1098) - ARM_INS_VHADD - vhadd${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADDu16 (1099) - ARM_INS_VHADD - vhadd${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADDu32 (1100) - ARM_INS_VHADD - vhadd${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHADDu8 (1101) - ARM_INS_VHADD - vhadd${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHCADDs16 (1102) - ARM_INS_VHCADD - vhcadd${vp}.s16	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHCADDs32 (1103) - ARM_INS_VHCADD - vhcadd${vp}.s32	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHCADDs8 (1104) - ARM_INS_VHCADD - vhcadd${vp}.s8	$Qd, $Qn, $Qm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUB_qr_s16 (1105) - ARM_INS_VHSUB - vhsub${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUB_qr_s32 (1106) - ARM_INS_VHSUB - vhsub${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUB_qr_s8 (1107) - ARM_INS_VHSUB - vhsub${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUB_qr_u16 (1108) - ARM_INS_VHSUB - vhsub${vp}.u16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUB_qr_u32 (1109) - ARM_INS_VHSUB - vhsub${vp}.u32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUB_qr_u8 (1110) - ARM_INS_VHSUB - vhsub${vp}.u8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUBs16 (1111) - ARM_INS_VHSUB - vhsub${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUBs32 (1112) - ARM_INS_VHSUB - vhsub${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUBs8 (1113) - ARM_INS_VHSUB - vhsub${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUBu16 (1114) - ARM_INS_VHSUB - vhsub${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUBu32 (1115) - ARM_INS_VHSUB - vhsub${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VHSUBu8 (1116) - ARM_INS_VHSUB - vhsub${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VIDUPu16 (1117) - ARM_INS_VIDUP - vidup${vp}.u16	$Qd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VIDUPu32 (1118) - ARM_INS_VIDUP - vidup${vp}.u32	$Qd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VIDUPu8 (1119) - ARM_INS_VIDUP - vidup${vp}.u8	$Qd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VIWDUPu16 (1120) - ARM_INS_VIWDUP - viwdup${vp}.u16	$Qd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VIWDUPu32 (1121) - ARM_INS_VIWDUP - viwdup${vp}.u32	$Qd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VIWDUPu8 (1122) - ARM_INS_VIWDUP - viwdup${vp}.u8	$Qd, $Rn, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD20_16 (1123) - ARM_INS_VLD20 - vld20.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD20_16_wb (1124) - ARM_INS_VLD20 - vld20.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD20_32 (1125) - ARM_INS_VLD20 - vld20.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD20_32_wb (1126) - ARM_INS_VLD20 - vld20.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD20_8 (1127) - ARM_INS_VLD20 - vld20.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD20_8_wb (1128) - ARM_INS_VLD20 - vld20.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD21_16 (1129) - ARM_INS_VLD21 - vld21.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD21_16_wb (1130) - ARM_INS_VLD21 - vld21.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD21_32 (1131) - ARM_INS_VLD21 - vld21.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD21_32_wb (1132) - ARM_INS_VLD21 - vld21.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD21_8 (1133) - ARM_INS_VLD21 - vld21.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD21_8_wb (1134) - ARM_INS_VLD21 - vld21.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD40_16 (1135) - ARM_INS_VLD40 - vld40.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD40_16_wb (1136) - ARM_INS_VLD40 - vld40.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD40_32 (1137) - ARM_INS_VLD40 - vld40.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD40_32_wb (1138) - ARM_INS_VLD40 - vld40.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD40_8 (1139) - ARM_INS_VLD40 - vld40.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD40_8_wb (1140) - ARM_INS_VLD40 - vld40.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD41_16 (1141) - ARM_INS_VLD41 - vld41.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD41_16_wb (1142) - ARM_INS_VLD41 - vld41.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD41_32 (1143) - ARM_INS_VLD41 - vld41.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD41_32_wb (1144) - ARM_INS_VLD41 - vld41.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD41_8 (1145) - ARM_INS_VLD41 - vld41.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD41_8_wb (1146) - ARM_INS_VLD41 - vld41.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD42_16 (1147) - ARM_INS_VLD42 - vld42.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD42_16_wb (1148) - ARM_INS_VLD42 - vld42.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD42_32 (1149) - ARM_INS_VLD42 - vld42.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD42_32_wb (1150) - ARM_INS_VLD42 - vld42.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD42_8 (1151) - ARM_INS_VLD42 - vld42.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD42_8_wb (1152) - ARM_INS_VLD42 - vld42.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD43_16 (1153) - ARM_INS_VLD43 - vld43.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD43_16_wb (1154) - ARM_INS_VLD43 - vld43.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD43_32 (1155) - ARM_INS_VLD43 - vld43.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD43_32_wb (1156) - ARM_INS_VLD43 - vld43.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD43_8 (1157) - ARM_INS_VLD43 - vld43.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VLD43_8_wb (1158) - ARM_INS_VLD43 - vld43.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQdSrc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS16 (1159) - ARM_INS_VLDRB - vldrb${vp}.s16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS16_post (1160) - ARM_INS_VLDRB - vldrb${vp}.s16	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS16_pre (1161) - ARM_INS_VLDRB - vldrb${vp}.s16	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS16_rq (1162) - ARM_INS_VLDRB - vldrb${vp}.s16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS32 (1163) - ARM_INS_VLDRB - vldrb${vp}.s32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS32_post (1164) - ARM_INS_VLDRB - vldrb${vp}.s32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS32_pre (1165) - ARM_INS_VLDRB - vldrb${vp}.s32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBS32_rq (1166) - ARM_INS_VLDRB - vldrb${vp}.s32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU16 (1167) - ARM_INS_VLDRB - vldrb${vp}.u16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU16_post (1168) - ARM_INS_VLDRB - vldrb${vp}.u16	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU16_pre (1169) - ARM_INS_VLDRB - vldrb${vp}.u16	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU16_rq (1170) - ARM_INS_VLDRB - vldrb${vp}.u16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU32 (1171) - ARM_INS_VLDRB - vldrb${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU32_post (1172) - ARM_INS_VLDRB - vldrb${vp}.u32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU32_pre (1173) - ARM_INS_VLDRB - vldrb${vp}.u32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU32_rq (1174) - ARM_INS_VLDRB - vldrb${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU8 (1175) - ARM_INS_VLDRB - vldrb${vp}.u8	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU8_post (1176) - ARM_INS_VLDRB - vldrb${vp}.u8	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU8_pre (1177) - ARM_INS_VLDRB - vldrb${vp}.u8	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRBU8_rq (1178) - ARM_INS_VLDRB - vldrb${vp}.u8	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRDU64_qi (1179) - ARM_INS_VLDRD - vldrd${vp}.u64	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRDU64_qi_pre (1180) - ARM_INS_VLDRD - vldrd${vp}.u64	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRDU64_rq (1181) - ARM_INS_VLDRD - vldrd${vp}.u64	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRDU64_rq_u (1182) - ARM_INS_VLDRD - vldrd${vp}.u64	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHS32 (1183) - ARM_INS_VLDRH - vldrh${vp}.s32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHS32_post (1184) - ARM_INS_VLDRH - vldrh${vp}.s32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHS32_pre (1185) - ARM_INS_VLDRH - vldrh${vp}.s32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHS32_rq (1186) - ARM_INS_VLDRH - vldrh${vp}.s32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHS32_rq_u (1187) - ARM_INS_VLDRH - vldrh${vp}.s32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU16 (1188) - ARM_INS_VLDRH - vldrh${vp}.u16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU16_post (1189) - ARM_INS_VLDRH - vldrh${vp}.u16	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU16_pre (1190) - ARM_INS_VLDRH - vldrh${vp}.u16	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU16_rq (1191) - ARM_INS_VLDRH - vldrh${vp}.u16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU16_rq_u (1192) - ARM_INS_VLDRH - vldrh${vp}.u16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU32 (1193) - ARM_INS_VLDRH - vldrh${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU32_post (1194) - ARM_INS_VLDRH - vldrh${vp}.u32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU32_pre (1195) - ARM_INS_VLDRH - vldrh${vp}.u32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU32_rq (1196) - ARM_INS_VLDRH - vldrh${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRHU32_rq_u (1197) - ARM_INS_VLDRH - vldrh${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32 (1198) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32_post (1199) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32_pre (1200) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32_qi (1201) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32_qi_pre (1202) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32_rq (1203) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VLDRWU32_rq_u (1204) - ARM_INS_VLDRW - vldrw${vp}.u32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXAVs16 (1205) - ARM_INS_VMAXAV - vmaxav${vp}.s16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXAVs32 (1206) - ARM_INS_VMAXAV - vmaxav${vp}.s32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXAVs8 (1207) - ARM_INS_VMAXAV - vmaxav${vp}.s8	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXAs16 (1208) - ARM_INS_VMAXA - vmaxa${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXAs32 (1209) - ARM_INS_VMAXA - vmaxa${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXAs8 (1210) - ARM_INS_VMAXA - vmaxa${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMAVf16 (1211) - ARM_INS_VMAXNMAV - vmaxnmav${vp}.f16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMAVf32 (1212) - ARM_INS_VMAXNMAV - vmaxnmav${vp}.f32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMAf16 (1213) - ARM_INS_VMAXNMA - vmaxnma${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMAf32 (1214) - ARM_INS_VMAXNMA - vmaxnma${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMVf16 (1215) - ARM_INS_VMAXNMV - vmaxnmv${vp}.f16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMVf32 (1216) - ARM_INS_VMAXNMV - vmaxnmv${vp}.f32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMf16 (1217) - ARM_INS_VMAXNM - vmaxnm${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXNMf32 (1218) - ARM_INS_VMAXNM - vmaxnm${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXVs16 (1219) - ARM_INS_VMAXV - vmaxv${vp}.s16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXVs32 (1220) - ARM_INS_VMAXV - vmaxv${vp}.s32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXVs8 (1221) - ARM_INS_VMAXV - vmaxv${vp}.s8	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXVu16 (1222) - ARM_INS_VMAXV - vmaxv${vp}.u16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXVu32 (1223) - ARM_INS_VMAXV - vmaxv${vp}.u32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXVu8 (1224) - ARM_INS_VMAXV - vmaxv${vp}.u8	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXs16 (1225) - ARM_INS_VMAX - vmax${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXs32 (1226) - ARM_INS_VMAX - vmax${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXs8 (1227) - ARM_INS_VMAX - vmax${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXu16 (1228) - ARM_INS_VMAX - vmax${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXu32 (1229) - ARM_INS_VMAX - vmax${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMAXu8 (1230) - ARM_INS_VMAX - vmax${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINAVs16 (1231) - ARM_INS_VMINAV - vminav${vp}.s16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINAVs32 (1232) - ARM_INS_VMINAV - vminav${vp}.s32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINAVs8 (1233) - ARM_INS_VMINAV - vminav${vp}.s8	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINAs16 (1234) - ARM_INS_VMINA - vmina${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINAs32 (1235) - ARM_INS_VMINA - vmina${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINAs8 (1236) - ARM_INS_VMINA - vmina${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMAVf16 (1237) - ARM_INS_VMINNMAV - vminnmav${vp}.f16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMAVf32 (1238) - ARM_INS_VMINNMAV - vminnmav${vp}.f32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMAf16 (1239) - ARM_INS_VMINNMA - vminnma${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMAf32 (1240) - ARM_INS_VMINNMA - vminnma${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMVf16 (1241) - ARM_INS_VMINNMV - vminnmv${vp}.f16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMVf32 (1242) - ARM_INS_VMINNMV - vminnmv${vp}.f32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMf16 (1243) - ARM_INS_VMINNM - vminnm${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINNMf32 (1244) - ARM_INS_VMINNM - vminnm${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINVs16 (1245) - ARM_INS_VMINV - vminv${vp}.s16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINVs32 (1246) - ARM_INS_VMINV - vminv${vp}.s32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINVs8 (1247) - ARM_INS_VMINV - vminv${vp}.s8	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINVu16 (1248) - ARM_INS_VMINV - vminv${vp}.u16	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINVu32 (1249) - ARM_INS_VMINV - vminv${vp}.u32	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINVu8 (1250) - ARM_INS_VMINV - vminv${vp}.u8	$RdaSrc, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINs16 (1251) - ARM_INS_VMIN - vmin${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINs32 (1252) - ARM_INS_VMIN - vmin${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINs8 (1253) - ARM_INS_VMIN - vmin${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINu16 (1254) - ARM_INS_VMIN - vmin${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINu32 (1255) - ARM_INS_VMIN - vmin${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMINu8 (1256) - ARM_INS_VMIN - vmin${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVas16 (1257) - ARM_INS_VMLADAVA - vmladava${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVas32 (1258) - ARM_INS_VMLADAVA - vmladava${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVas8 (1259) - ARM_INS_VMLADAVA - vmladava${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVau16 (1260) - ARM_INS_VMLADAVA - vmladava${vp}.u16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVau32 (1261) - ARM_INS_VMLADAVA - vmladava${vp}.u32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVau8 (1262) - ARM_INS_VMLADAVA - vmladava${vp}.u8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVaxs16 (1263) - ARM_INS_VMLADAVAX - vmladavax${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVaxs32 (1264) - ARM_INS_VMLADAVAX - vmladavax${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVaxs8 (1265) - ARM_INS_VMLADAVAX - vmladavax${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVs16 (1266) - ARM_INS_VMLADAV - vmladav${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVs32 (1267) - ARM_INS_VMLADAV - vmladav${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVs8 (1268) - ARM_INS_VMLADAV - vmladav${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVu16 (1269) - ARM_INS_VMLADAV - vmladav${vp}.u16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVu32 (1270) - ARM_INS_VMLADAV - vmladav${vp}.u32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVu8 (1271) - ARM_INS_VMLADAV - vmladav${vp}.u8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVxs16 (1272) - ARM_INS_VMLADAVX - vmladavx${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVxs32 (1273) - ARM_INS_VMLADAVX - vmladavx${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLADAVxs8 (1274) - ARM_INS_VMLADAVX - vmladavx${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVas16 (1275) - ARM_INS_VMLALDAVA - vmlaldava${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVas32 (1276) - ARM_INS_VMLALDAVA - vmlaldava${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVau16 (1277) - ARM_INS_VMLALDAVA - vmlaldava${vp}.u16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVau32 (1278) - ARM_INS_VMLALDAVA - vmlaldava${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVaxs16 (1279) - ARM_INS_VMLALDAVAX - vmlaldavax${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVaxs32 (1280) - ARM_INS_VMLALDAVAX - vmlaldavax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVs16 (1281) - ARM_INS_VMLALDAV - vmlaldav${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVs32 (1282) - ARM_INS_VMLALDAV - vmlaldav${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVu16 (1283) - ARM_INS_VMLALDAV - vmlaldav${vp}.u16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVu32 (1284) - ARM_INS_VMLALDAV - vmlaldav${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVxs16 (1285) - ARM_INS_VMLALDAVX - vmlaldavx${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLALDAVxs32 (1286) - ARM_INS_VMLALDAVX - vmlaldavx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLAS_qr_i16 (1287) - ARM_INS_VMLAS - vmlas${vp}.i16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLAS_qr_i32 (1288) - ARM_INS_VMLAS - vmlas${vp}.i32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLAS_qr_i8 (1289) - ARM_INS_VMLAS - vmlas${vp}.i8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLA_qr_i16 (1290) - ARM_INS_VMLA - vmla${vp}.i16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLA_qr_i32 (1291) - ARM_INS_VMLA - vmla${vp}.i32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLA_qr_i8 (1292) - ARM_INS_VMLA - vmla${vp}.i8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVas16 (1293) - ARM_INS_VMLSDAVA - vmlsdava${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVas32 (1294) - ARM_INS_VMLSDAVA - vmlsdava${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVas8 (1295) - ARM_INS_VMLSDAVA - vmlsdava${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVaxs16 (1296) - ARM_INS_VMLSDAVAX - vmlsdavax${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVaxs32 (1297) - ARM_INS_VMLSDAVAX - vmlsdavax${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVaxs8 (1298) - ARM_INS_VMLSDAVAX - vmlsdavax${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVs16 (1299) - ARM_INS_VMLSDAV - vmlsdav${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVs32 (1300) - ARM_INS_VMLSDAV - vmlsdav${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVs8 (1301) - ARM_INS_VMLSDAV - vmlsdav${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVxs16 (1302) - ARM_INS_VMLSDAVX - vmlsdavx${vp}.s16	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVxs32 (1303) - ARM_INS_VMLSDAVX - vmlsdavx${vp}.s32	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSDAVxs8 (1304) - ARM_INS_VMLSDAVX - vmlsdavx${vp}.s8	$RdaDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVas16 (1305) - ARM_INS_VMLSLDAVA - vmlsldava${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVas32 (1306) - ARM_INS_VMLSLDAVA - vmlsldava${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVaxs16 (1307) - ARM_INS_VMLSLDAVAX - vmlsldavax${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVaxs32 (1308) - ARM_INS_VMLSLDAVAX - vmlsldavax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVs16 (1309) - ARM_INS_VMLSLDAV - vmlsldav${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVs32 (1310) - ARM_INS_VMLSLDAV - vmlsldav${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVxs16 (1311) - ARM_INS_VMLSLDAVX - vmlsldavx${vp}.s16	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMLSLDAVxs32 (1312) - ARM_INS_VMLSLDAVX - vmlsldavx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLs16bh (1313) - ARM_INS_VMOVLB - vmovlb${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLs16th (1314) - ARM_INS_VMOVLT - vmovlt${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLs8bh (1315) - ARM_INS_VMOVLB - vmovlb${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLs8th (1316) - ARM_INS_VMOVLT - vmovlt${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLu16bh (1317) - ARM_INS_VMOVLB - vmovlb${vp}.u16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLu16th (1318) - ARM_INS_VMOVLT - vmovlt${vp}.u16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLu8bh (1319) - ARM_INS_VMOVLB - vmovlb${vp}.u8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVLu8th (1320) - ARM_INS_VMOVLT - vmovlt${vp}.u8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVNi16bh (1321) - ARM_INS_VMOVNB - vmovnb${vp}.i16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVNi16th (1322) - ARM_INS_VMOVNT - vmovnt${vp}.i16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVNi32bh (1323) - ARM_INS_VMOVNB - vmovnb${vp}.i32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVNi32th (1324) - ARM_INS_VMOVNT - vmovnt${vp}.i32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_from_lane_32 (1325) - ARM_INS_VMOV - vmov${p}.32	$Rt, $Qd$Idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_from_lane_s16 (1326) - ARM_INS_VMOV - vmov${p}.s16	$Rt, $Qd$Idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_from_lane_s8 (1327) - ARM_INS_VMOV - vmov${p}.s8	$Rt, $Qd$Idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_from_lane_u16 (1328) - ARM_INS_VMOV - vmov${p}.u16	$Rt, $Qd$Idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_from_lane_u8 (1329) - ARM_INS_VMOV - vmov${p}.u8	$Rt, $Qd$Idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_q_rr (1330) - ARM_INS_VMOV - vmov${p}	$Qd$idx, $QdSrc$idx2, $Rt, $Rt2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx2 - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_rr_q (1331) - ARM_INS_VMOV - vmov${p}	$Rt, $Rt2, $Qd$idx, $Qd$idx2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx2 - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_to_lane_16 (1332) - ARM_INS_VMOV - vmov${p}.16	$Qd$Idx, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_to_lane_32 (1333) - ARM_INS_VMOV - vmov${p}.32	$Qd$Idx, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOV_to_lane_8 (1334) - ARM_INS_VMOV - vmov${p}.8	$Qd$Idx, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Idx - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVimmf32 (1335) - ARM_INS_VMOV - vmov${vp}.f32	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVimmi16 (1336) - ARM_INS_VMOV - vmov${vp}.i16	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVimmi32 (1337) - ARM_INS_VMOV - vmov${vp}.i32	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVimmi64 (1338) - ARM_INS_VMOV - vmov${vp}.i64	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMOVimmi8 (1339) - ARM_INS_VMOV - vmov${vp}.i8	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULHs16 (1340) - ARM_INS_VMULH - vmulh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULHs32 (1341) - ARM_INS_VMULH - vmulh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULHs8 (1342) - ARM_INS_VMULH - vmulh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULHu16 (1343) - ARM_INS_VMULH - vmulh${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULHu32 (1344) - ARM_INS_VMULH - vmulh${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULHu8 (1345) - ARM_INS_VMULH - vmulh${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBp16 (1346) - ARM_INS_VMULLB - vmullb${vp}.p16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBp8 (1347) - ARM_INS_VMULLB - vmullb${vp}.p8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBs16 (1348) - ARM_INS_VMULLB - vmullb${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBs32 (1349) - ARM_INS_VMULLB - vmullb${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBs8 (1350) - ARM_INS_VMULLB - vmullb${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBu16 (1351) - ARM_INS_VMULLB - vmullb${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBu32 (1352) - ARM_INS_VMULLB - vmullb${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLBu8 (1353) - ARM_INS_VMULLB - vmullb${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTp16 (1354) - ARM_INS_VMULLT - vmullt${vp}.p16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTp8 (1355) - ARM_INS_VMULLT - vmullt${vp}.p8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTs16 (1356) - ARM_INS_VMULLT - vmullt${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTs32 (1357) - ARM_INS_VMULLT - vmullt${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTs8 (1358) - ARM_INS_VMULLT - vmullt${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTu16 (1359) - ARM_INS_VMULLT - vmullt${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTu32 (1360) - ARM_INS_VMULLT - vmullt${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULLTu8 (1361) - ARM_INS_VMULLT - vmullt${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMUL_qr_f16 (1362) - ARM_INS_VMUL - vmul${vp}.f16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMUL_qr_f32 (1363) - ARM_INS_VMUL - vmul${vp}.f32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMUL_qr_i16 (1364) - ARM_INS_VMUL - vmul${vp}.i16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMUL_qr_i32 (1365) - ARM_INS_VMUL - vmul${vp}.i32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMUL_qr_i8 (1366) - ARM_INS_VMUL - vmul${vp}.i8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULf16 (1367) - ARM_INS_VMUL - vmul${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULf32 (1368) - ARM_INS_VMUL - vmul${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULi16 (1369) - ARM_INS_VMUL - vmul${vp}.i16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULi32 (1370) - ARM_INS_VMUL - vmul${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMULi8 (1371) - ARM_INS_VMUL - vmul${vp}.i8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMVN (1372) - ARM_INS_VMVN - vmvn${vp}	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMVNimmi16 (1373) - ARM_INS_VMVN - vmvn${vp}.i16	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VMVNimmi32 (1374) - ARM_INS_VMVN - vmvn${vp}.i32	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VNEGf16 (1375) - ARM_INS_VNEG - vneg${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VNEGf32 (1376) - ARM_INS_VNEG - vneg${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VNEGs16 (1377) - ARM_INS_VNEG - vneg${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VNEGs32 (1378) - ARM_INS_VNEG - vneg${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VNEGs8 (1379) - ARM_INS_VNEG - vneg${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VORN (1380) - ARM_INS_VORN - vorn${vp}	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VORR (1381) - ARM_INS_VORR - vorr${vp}	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VORRimmi16 (1382) - ARM_INS_VORR - vorr${vp}.i16	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VORRimmi32 (1383) - ARM_INS_VORR - vorr${vp}.i32	$Qd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VPNOT (1384) - ARM_INS_VPNOT - vpnot${vp}	 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0_in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VPSEL (1385) - ARM_INS_VPSEL - vpsel${vp}	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VPST (1386) - ARM_INS_VPST - vpst${Mk}	 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv16i8 (1387) - ARM_INS_VPT - vpt${Mk}.i8	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv16i8r (1388) - ARM_INS_VPT - vpt${Mk}.i8	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv16s8 (1389) - ARM_INS_VPT - vpt${Mk}.s8	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv16s8r (1390) - ARM_INS_VPT - vpt${Mk}.s8	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv16u8 (1391) - ARM_INS_VPT - vpt${Mk}.u8	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv16u8r (1392) - ARM_INS_VPT - vpt${Mk}.u8	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4f32 (1393) - ARM_INS_VPT - vpt${Mk}.f32	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4f32r (1394) - ARM_INS_VPT - vpt${Mk}.f32	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4i32 (1395) - ARM_INS_VPT - vpt${Mk}.i32	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4i32r (1396) - ARM_INS_VPT - vpt${Mk}.i32	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4s32 (1397) - ARM_INS_VPT - vpt${Mk}.s32	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4s32r (1398) - ARM_INS_VPT - vpt${Mk}.s32	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4u32 (1399) - ARM_INS_VPT - vpt${Mk}.u32	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv4u32r (1400) - ARM_INS_VPT - vpt${Mk}.u32	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8f16 (1401) - ARM_INS_VPT - vpt${Mk}.f16	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8f16r (1402) - ARM_INS_VPT - vpt${Mk}.f16	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8i16 (1403) - ARM_INS_VPT - vpt${Mk}.i16	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8i16r (1404) - ARM_INS_VPT - vpt${Mk}.i16	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8s16 (1405) - ARM_INS_VPT - vpt${Mk}.s16	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8s16r (1406) - ARM_INS_VPT - vpt${Mk}.s16	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8u16 (1407) - ARM_INS_VPT - vpt${Mk}.u16	$fc, $Qn, $Qm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VPTv8u16r (1408) - ARM_INS_VPT - vpt${Mk}.u16	$fc, $Qn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Mk */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fc */
+  { 0 }
+}},
+{ /* ARM_MVE_VQABSs16 (1409) - ARM_INS_VQABS - vqabs${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQABSs32 (1410) - ARM_INS_VQABS - vqabs${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQABSs8 (1411) - ARM_INS_VQABS - vqabs${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADD_qr_s16 (1412) - ARM_INS_VQADD - vqadd${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADD_qr_s32 (1413) - ARM_INS_VQADD - vqadd${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADD_qr_s8 (1414) - ARM_INS_VQADD - vqadd${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADD_qr_u16 (1415) - ARM_INS_VQADD - vqadd${vp}.u16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADD_qr_u32 (1416) - ARM_INS_VQADD - vqadd${vp}.u32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADD_qr_u8 (1417) - ARM_INS_VQADD - vqadd${vp}.u8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADDs16 (1418) - ARM_INS_VQADD - vqadd${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADDs32 (1419) - ARM_INS_VQADD - vqadd${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADDs8 (1420) - ARM_INS_VQADD - vqadd${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADDu16 (1421) - ARM_INS_VQADD - vqadd${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADDu32 (1422) - ARM_INS_VQADD - vqadd${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQADDu8 (1423) - ARM_INS_VQADD - vqadd${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLADHXs16 (1424) - ARM_INS_VQDMLADHX - vqdmladhx${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLADHXs32 (1425) - ARM_INS_VQDMLADHX - vqdmladhx${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLADHXs8 (1426) - ARM_INS_VQDMLADHX - vqdmladhx${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLADHs16 (1427) - ARM_INS_VQDMLADH - vqdmladh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLADHs32 (1428) - ARM_INS_VQDMLADH - vqdmladh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLADHs8 (1429) - ARM_INS_VQDMLADH - vqdmladh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLAH_qrs16 (1430) - ARM_INS_VQDMLAH - vqdmlah${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLAH_qrs32 (1431) - ARM_INS_VQDMLAH - vqdmlah${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLAH_qrs8 (1432) - ARM_INS_VQDMLAH - vqdmlah${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLASH_qrs16 (1433) - ARM_INS_VQDMLASH - vqdmlash${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLASH_qrs32 (1434) - ARM_INS_VQDMLASH - vqdmlash${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLASH_qrs8 (1435) - ARM_INS_VQDMLASH - vqdmlash${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLSDHXs16 (1436) - ARM_INS_VQDMLSDHX - vqdmlsdhx${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLSDHXs32 (1437) - ARM_INS_VQDMLSDHX - vqdmlsdhx${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLSDHXs8 (1438) - ARM_INS_VQDMLSDHX - vqdmlsdhx${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLSDHs16 (1439) - ARM_INS_VQDMLSDH - vqdmlsdh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLSDHs32 (1440) - ARM_INS_VQDMLSDH - vqdmlsdh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMLSDHs8 (1441) - ARM_INS_VQDMLSDH - vqdmlsdh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULH_qr_s16 (1442) - ARM_INS_VQDMULH - vqdmulh${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULH_qr_s32 (1443) - ARM_INS_VQDMULH - vqdmulh${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULH_qr_s8 (1444) - ARM_INS_VQDMULH - vqdmulh${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULHi16 (1445) - ARM_INS_VQDMULH - vqdmulh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULHi32 (1446) - ARM_INS_VQDMULH - vqdmulh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULHi8 (1447) - ARM_INS_VQDMULH - vqdmulh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULL_qr_s16bh (1448) - ARM_INS_VQDMULLB - vqdmullb${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULL_qr_s16th (1449) - ARM_INS_VQDMULLT - vqdmullt${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULL_qr_s32bh (1450) - ARM_INS_VQDMULLB - vqdmullb${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULL_qr_s32th (1451) - ARM_INS_VQDMULLT - vqdmullt${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULLs16bh (1452) - ARM_INS_VQDMULLB - vqdmullb${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULLs16th (1453) - ARM_INS_VQDMULLT - vqdmullt${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULLs32bh (1454) - ARM_INS_VQDMULLB - vqdmullb${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQDMULLs32th (1455) - ARM_INS_VQDMULLT - vqdmullt${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNs16bh (1456) - ARM_INS_VQMOVNB - vqmovnb${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNs16th (1457) - ARM_INS_VQMOVNT - vqmovnt${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNs32bh (1458) - ARM_INS_VQMOVNB - vqmovnb${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNs32th (1459) - ARM_INS_VQMOVNT - vqmovnt${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNu16bh (1460) - ARM_INS_VQMOVNB - vqmovnb${vp}.u16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNu16th (1461) - ARM_INS_VQMOVNT - vqmovnt${vp}.u16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNu32bh (1462) - ARM_INS_VQMOVNB - vqmovnb${vp}.u32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVNu32th (1463) - ARM_INS_VQMOVNT - vqmovnt${vp}.u32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVUNs16bh (1464) - ARM_INS_VQMOVUNB - vqmovunb${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVUNs16th (1465) - ARM_INS_VQMOVUNT - vqmovunt${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVUNs32bh (1466) - ARM_INS_VQMOVUNB - vqmovunb${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQMOVUNs32th (1467) - ARM_INS_VQMOVUNT - vqmovunt${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQNEGs16 (1468) - ARM_INS_VQNEG - vqneg${vp}.s16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQNEGs32 (1469) - ARM_INS_VQNEG - vqneg${vp}.s32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQNEGs8 (1470) - ARM_INS_VQNEG - vqneg${vp}.s8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLADHXs16 (1471) - ARM_INS_VQRDMLADHX - vqrdmladhx${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLADHXs32 (1472) - ARM_INS_VQRDMLADHX - vqrdmladhx${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLADHXs8 (1473) - ARM_INS_VQRDMLADHX - vqrdmladhx${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLADHs16 (1474) - ARM_INS_VQRDMLADH - vqrdmladh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLADHs32 (1475) - ARM_INS_VQRDMLADH - vqrdmladh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLADHs8 (1476) - ARM_INS_VQRDMLADH - vqrdmladh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLAH_qrs16 (1477) - ARM_INS_VQRDMLAH - vqrdmlah${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLAH_qrs32 (1478) - ARM_INS_VQRDMLAH - vqrdmlah${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLAH_qrs8 (1479) - ARM_INS_VQRDMLAH - vqrdmlah${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLASH_qrs16 (1480) - ARM_INS_VQRDMLASH - vqrdmlash${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLASH_qrs32 (1481) - ARM_INS_VQRDMLASH - vqrdmlash${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLASH_qrs8 (1482) - ARM_INS_VQRDMLASH - vqrdmlash${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLSDHXs16 (1483) - ARM_INS_VQRDMLSDHX - vqrdmlsdhx${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLSDHXs32 (1484) - ARM_INS_VQRDMLSDHX - vqrdmlsdhx${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLSDHXs8 (1485) - ARM_INS_VQRDMLSDHX - vqrdmlsdhx${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLSDHs16 (1486) - ARM_INS_VQRDMLSDH - vqrdmlsdh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLSDHs32 (1487) - ARM_INS_VQRDMLSDH - vqrdmlsdh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMLSDHs8 (1488) - ARM_INS_VQRDMLSDH - vqrdmlsdh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMULH_qr_s16 (1489) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMULH_qr_s32 (1490) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMULH_qr_s8 (1491) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMULHi16 (1492) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMULHi32 (1493) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRDMULHi8 (1494) - ARM_INS_VQRDMULH - vqrdmulh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_by_vecs16 (1495) - ARM_INS_VQRSHL - vqrshl${vp}.s16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_by_vecs32 (1496) - ARM_INS_VQRSHL - vqrshl${vp}.s32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_by_vecs8 (1497) - ARM_INS_VQRSHL - vqrshl${vp}.s8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_by_vecu16 (1498) - ARM_INS_VQRSHL - vqrshl${vp}.u16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_by_vecu32 (1499) - ARM_INS_VQRSHL - vqrshl${vp}.u32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_by_vecu8 (1500) - ARM_INS_VQRSHL - vqrshl${vp}.u8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_qrs16 (1501) - ARM_INS_VQRSHL - vqrshl${vp}.s16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_qrs32 (1502) - ARM_INS_VQRSHL - vqrshl${vp}.s32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_qrs8 (1503) - ARM_INS_VQRSHL - vqrshl${vp}.s8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_qru16 (1504) - ARM_INS_VQRSHL - vqrshl${vp}.u16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_qru32 (1505) - ARM_INS_VQRSHL - vqrshl${vp}.u32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHL_qru8 (1506) - ARM_INS_VQRSHL - vqrshl${vp}.u8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNbhs16 (1507) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNbhs32 (1508) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNbhu16 (1509) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNbhu32 (1510) - ARM_INS_VQRSHRNB - vqrshrnb${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNths16 (1511) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNths32 (1512) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNthu16 (1513) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRNthu32 (1514) - ARM_INS_VQRSHRNT - vqrshrnt${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRUNs16bh (1515) - ARM_INS_VQRSHRUNB - vqrshrunb${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRUNs16th (1516) - ARM_INS_VQRSHRUNT - vqrshrunt${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRUNs32bh (1517) - ARM_INS_VQRSHRUNB - vqrshrunb${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQRSHRUNs32th (1518) - ARM_INS_VQRSHRUNT - vqrshrunt${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLU_imms16 (1519) - ARM_INS_VQSHLU - vqshlu${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLU_imms32 (1520) - ARM_INS_VQSHLU - vqshlu${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLU_imms8 (1521) - ARM_INS_VQSHLU - vqshlu${vp}.s8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_by_vecs16 (1522) - ARM_INS_VQSHL - vqshl${vp}.s16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_by_vecs32 (1523) - ARM_INS_VQSHL - vqshl${vp}.s32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_by_vecs8 (1524) - ARM_INS_VQSHL - vqshl${vp}.s8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_by_vecu16 (1525) - ARM_INS_VQSHL - vqshl${vp}.u16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_by_vecu32 (1526) - ARM_INS_VQSHL - vqshl${vp}.u32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_by_vecu8 (1527) - ARM_INS_VQSHL - vqshl${vp}.u8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_qrs16 (1528) - ARM_INS_VQSHL - vqshl${vp}.s16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_qrs32 (1529) - ARM_INS_VQSHL - vqshl${vp}.s32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_qrs8 (1530) - ARM_INS_VQSHL - vqshl${vp}.s8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_qru16 (1531) - ARM_INS_VQSHL - vqshl${vp}.u16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_qru32 (1532) - ARM_INS_VQSHL - vqshl${vp}.u32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHL_qru8 (1533) - ARM_INS_VQSHL - vqshl${vp}.u8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLimms16 (1534) - ARM_INS_VQSHL - vqshl${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLimms32 (1535) - ARM_INS_VQSHL - vqshl${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLimms8 (1536) - ARM_INS_VQSHL - vqshl${vp}.s8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLimmu16 (1537) - ARM_INS_VQSHL - vqshl${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLimmu32 (1538) - ARM_INS_VQSHL - vqshl${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHLimmu8 (1539) - ARM_INS_VQSHL - vqshl${vp}.u8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNbhs16 (1540) - ARM_INS_VQSHRNB - vqshrnb${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNbhs32 (1541) - ARM_INS_VQSHRNB - vqshrnb${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNbhu16 (1542) - ARM_INS_VQSHRNB - vqshrnb${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNbhu32 (1543) - ARM_INS_VQSHRNB - vqshrnb${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNths16 (1544) - ARM_INS_VQSHRNT - vqshrnt${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNths32 (1545) - ARM_INS_VQSHRNT - vqshrnt${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNthu16 (1546) - ARM_INS_VQSHRNT - vqshrnt${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRNthu32 (1547) - ARM_INS_VQSHRNT - vqshrnt${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRUNs16bh (1548) - ARM_INS_VQSHRUNB - vqshrunb${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRUNs16th (1549) - ARM_INS_VQSHRUNT - vqshrunt${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRUNs32bh (1550) - ARM_INS_VQSHRUNB - vqshrunb${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSHRUNs32th (1551) - ARM_INS_VQSHRUNT - vqshrunt${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUB_qr_s16 (1552) - ARM_INS_VQSUB - vqsub${vp}.s16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUB_qr_s32 (1553) - ARM_INS_VQSUB - vqsub${vp}.s32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUB_qr_s8 (1554) - ARM_INS_VQSUB - vqsub${vp}.s8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUB_qr_u16 (1555) - ARM_INS_VQSUB - vqsub${vp}.u16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUB_qr_u32 (1556) - ARM_INS_VQSUB - vqsub${vp}.u32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUB_qr_u8 (1557) - ARM_INS_VQSUB - vqsub${vp}.u8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUBs16 (1558) - ARM_INS_VQSUB - vqsub${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUBs32 (1559) - ARM_INS_VQSUB - vqsub${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUBs8 (1560) - ARM_INS_VQSUB - vqsub${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUBu16 (1561) - ARM_INS_VQSUB - vqsub${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUBu32 (1562) - ARM_INS_VQSUB - vqsub${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VQSUBu8 (1563) - ARM_INS_VQSUB - vqsub${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VREV16_8 (1564) - ARM_INS_VREV16 - vrev16${vp}.8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VREV32_16 (1565) - ARM_INS_VREV32 - vrev32${vp}.16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VREV32_8 (1566) - ARM_INS_VREV32 - vrev32${vp}.8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VREV64_16 (1567) - ARM_INS_VREV64 - vrev64${vp}.16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VREV64_32 (1568) - ARM_INS_VREV64 - vrev64${vp}.32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VREV64_8 (1569) - ARM_INS_VREV64 - vrev64${vp}.8	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRHADDs16 (1570) - ARM_INS_VRHADD - vrhadd${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRHADDs32 (1571) - ARM_INS_VRHADD - vrhadd${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRHADDs8 (1572) - ARM_INS_VRHADD - vrhadd${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRHADDu16 (1573) - ARM_INS_VRHADD - vrhadd${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRHADDu32 (1574) - ARM_INS_VRHADD - vrhadd${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRHADDu8 (1575) - ARM_INS_VRHADD - vrhadd${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf16A (1576) - ARM_INS_VRINTA - vrinta${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf16M (1577) - ARM_INS_VRINTM - vrintm${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf16N (1578) - ARM_INS_VRINTN - vrintn${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf16P (1579) - ARM_INS_VRINTP - vrintp${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf16X (1580) - ARM_INS_VRINTX - vrintx${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf16Z (1581) - ARM_INS_VRINTZ - vrintz${vp}.f16	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf32A (1582) - ARM_INS_VRINTA - vrinta${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf32M (1583) - ARM_INS_VRINTM - vrintm${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf32N (1584) - ARM_INS_VRINTN - vrintn${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf32P (1585) - ARM_INS_VRINTP - vrintp${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf32X (1586) - ARM_INS_VRINTX - vrintx${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRINTf32Z (1587) - ARM_INS_VRINTZ - vrintz${vp}.f32	$Qd, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLALDAVHas32 (1588) - ARM_INS_VRMLALDAVHA - vrmlaldavha${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLALDAVHau32 (1589) - ARM_INS_VRMLALDAVHA - vrmlaldavha${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLALDAVHaxs32 (1590) - ARM_INS_VRMLALDAVHAX - vrmlaldavhax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLALDAVHs32 (1591) - ARM_INS_VRMLALDAVH - vrmlaldavh${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLALDAVHu32 (1592) - ARM_INS_VRMLALDAVH - vrmlaldavh${vp}.u32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLALDAVHxs32 (1593) - ARM_INS_VRMLALDAVHX - vrmlaldavhx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLSLDAVHas32 (1594) - ARM_INS_VRMLSLDAVHA - vrmlsldavha${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLSLDAVHaxs32 (1595) - ARM_INS_VRMLSLDAVHAX - vrmlsldavhax${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLSLDAVHs32 (1596) - ARM_INS_VRMLSLDAVH - vrmlsldavh${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMLSLDAVHxs32 (1597) - ARM_INS_VRMLSLDAVHX - vrmlsldavhx${vp}.s32	$RdaLoDest, $RdaHiDest, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaLoDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdaHiDest */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMULHs16 (1598) - ARM_INS_VRMULH - vrmulh${vp}.s16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMULHs32 (1599) - ARM_INS_VRMULH - vrmulh${vp}.s32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMULHs8 (1600) - ARM_INS_VRMULH - vrmulh${vp}.s8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMULHu16 (1601) - ARM_INS_VRMULH - vrmulh${vp}.u16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMULHu32 (1602) - ARM_INS_VRMULH - vrmulh${vp}.u32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRMULHu8 (1603) - ARM_INS_VRMULH - vrmulh${vp}.u8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_by_vecs16 (1604) - ARM_INS_VRSHL - vrshl${vp}.s16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_by_vecs32 (1605) - ARM_INS_VRSHL - vrshl${vp}.s32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_by_vecs8 (1606) - ARM_INS_VRSHL - vrshl${vp}.s8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_by_vecu16 (1607) - ARM_INS_VRSHL - vrshl${vp}.u16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_by_vecu32 (1608) - ARM_INS_VRSHL - vrshl${vp}.u32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_by_vecu8 (1609) - ARM_INS_VRSHL - vrshl${vp}.u8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_qrs16 (1610) - ARM_INS_VRSHL - vrshl${vp}.s16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_qrs32 (1611) - ARM_INS_VRSHL - vrshl${vp}.s32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_qrs8 (1612) - ARM_INS_VRSHL - vrshl${vp}.s8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_qru16 (1613) - ARM_INS_VRSHL - vrshl${vp}.u16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_qru32 (1614) - ARM_INS_VRSHL - vrshl${vp}.u32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHL_qru8 (1615) - ARM_INS_VRSHL - vrshl${vp}.u8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHRNi16bh (1616) - ARM_INS_VRSHRNB - vrshrnb${vp}.i16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHRNi16th (1617) - ARM_INS_VRSHRNT - vrshrnt${vp}.i16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHRNi32bh (1618) - ARM_INS_VRSHRNB - vrshrnb${vp}.i32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHRNi32th (1619) - ARM_INS_VRSHRNT - vrshrnt${vp}.i32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHR_imms16 (1620) - ARM_INS_VRSHR - vrshr${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHR_imms32 (1621) - ARM_INS_VRSHR - vrshr${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHR_imms8 (1622) - ARM_INS_VRSHR - vrshr${vp}.s8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHR_immu16 (1623) - ARM_INS_VRSHR - vrshr${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHR_immu32 (1624) - ARM_INS_VRSHR - vrshr${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VRSHR_immu8 (1625) - ARM_INS_VRSHR - vrshr${vp}.u8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSBC (1626) - ARM_INS_VSBC - vsbc${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryin */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSBCI (1627) - ARM_INS_VSBCI - vsbci${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* carryout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLC (1628) - ARM_INS_VSHLC - vshlc${vp}	$QdSrc, $RdmSrc, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdmDest */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdmSrc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_imms16bh (1629) - ARM_INS_VSHLLB - vshllb${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_imms16th (1630) - ARM_INS_VSHLLT - vshllt${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_imms8bh (1631) - ARM_INS_VSHLLB - vshllb${vp}.s8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_imms8th (1632) - ARM_INS_VSHLLT - vshllt${vp}.s8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_immu16bh (1633) - ARM_INS_VSHLLB - vshllb${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_immu16th (1634) - ARM_INS_VSHLLT - vshllt${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_immu8bh (1635) - ARM_INS_VSHLLB - vshllb${vp}.u8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_immu8th (1636) - ARM_INS_VSHLLT - vshllt${vp}.u8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lws16bh (1637) - ARM_INS_VSHLLB - vshllb${vp}.s16	$Qd, $Qm, #16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lws16th (1638) - ARM_INS_VSHLLT - vshllt${vp}.s16	$Qd, $Qm, #16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lws8bh (1639) - ARM_INS_VSHLLB - vshllb${vp}.s8	$Qd, $Qm, #8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lws8th (1640) - ARM_INS_VSHLLT - vshllt${vp}.s8	$Qd, $Qm, #8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lwu16bh (1641) - ARM_INS_VSHLLB - vshllb${vp}.u16	$Qd, $Qm, #16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lwu16th (1642) - ARM_INS_VSHLLT - vshllt${vp}.u16	$Qd, $Qm, #16 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lwu8bh (1643) - ARM_INS_VSHLLB - vshllb${vp}.u8	$Qd, $Qm, #8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHLL_lwu8th (1644) - ARM_INS_VSHLLT - vshllt${vp}.u8	$Qd, $Qm, #8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_by_vecs16 (1645) - ARM_INS_VSHL - vshl${vp}.s16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_by_vecs32 (1646) - ARM_INS_VSHL - vshl${vp}.s32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_by_vecs8 (1647) - ARM_INS_VSHL - vshl${vp}.s8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_by_vecu16 (1648) - ARM_INS_VSHL - vshl${vp}.u16	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_by_vecu32 (1649) - ARM_INS_VSHL - vshl${vp}.u32	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_by_vecu8 (1650) - ARM_INS_VSHL - vshl${vp}.u8	$Qd, $Qm, $Qn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_immi16 (1651) - ARM_INS_VSHL - vshl${vp}.i16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_immi32 (1652) - ARM_INS_VSHL - vshl${vp}.i32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_immi8 (1653) - ARM_INS_VSHL - vshl${vp}.i8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_qrs16 (1654) - ARM_INS_VSHL - vshl${vp}.s16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_qrs32 (1655) - ARM_INS_VSHL - vshl${vp}.s32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_qrs8 (1656) - ARM_INS_VSHL - vshl${vp}.s8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_qru16 (1657) - ARM_INS_VSHL - vshl${vp}.u16	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_qru32 (1658) - ARM_INS_VSHL - vshl${vp}.u32	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHL_qru8 (1659) - ARM_INS_VSHL - vshl${vp}.u8	$Qd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHRNi16bh (1660) - ARM_INS_VSHRNB - vshrnb${vp}.i16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHRNi16th (1661) - ARM_INS_VSHRNT - vshrnt${vp}.i16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHRNi32bh (1662) - ARM_INS_VSHRNB - vshrnb${vp}.i32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHRNi32th (1663) - ARM_INS_VSHRNT - vshrnt${vp}.i32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* QdSrc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHR_imms16 (1664) - ARM_INS_VSHR - vshr${vp}.s16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHR_imms32 (1665) - ARM_INS_VSHR - vshr${vp}.s32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHR_imms8 (1666) - ARM_INS_VSHR - vshr${vp}.s8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHR_immu16 (1667) - ARM_INS_VSHR - vshr${vp}.u16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHR_immu32 (1668) - ARM_INS_VSHR - vshr${vp}.u32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSHR_immu8 (1669) - ARM_INS_VSHR - vshr${vp}.u8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSLIimm16 (1670) - ARM_INS_VSLI - vsli${vp}.16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSLIimm32 (1671) - ARM_INS_VSLI - vsli${vp}.32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSLIimm8 (1672) - ARM_INS_VSLI - vsli${vp}.8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSRIimm16 (1673) - ARM_INS_VSRI - vsri${vp}.16	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSRIimm32 (1674) - ARM_INS_VSRI - vsri${vp}.32	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSRIimm8 (1675) - ARM_INS_VSRI - vsri${vp}.8	$Qd, $Qm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd_src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VST20_16 (1676) - ARM_INS_VST20 - vst20.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST20_16_wb (1677) - ARM_INS_VST20 - vst20.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST20_32 (1678) - ARM_INS_VST20 - vst20.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST20_32_wb (1679) - ARM_INS_VST20 - vst20.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST20_8 (1680) - ARM_INS_VST20 - vst20.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST20_8_wb (1681) - ARM_INS_VST20 - vst20.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST21_16 (1682) - ARM_INS_VST21 - vst21.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST21_16_wb (1683) - ARM_INS_VST21 - vst21.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST21_32 (1684) - ARM_INS_VST21 - vst21.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST21_32_wb (1685) - ARM_INS_VST21 - vst21.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST21_8 (1686) - ARM_INS_VST21 - vst21.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST21_8_wb (1687) - ARM_INS_VST21 - vst21.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v4i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST40_16 (1688) - ARM_INS_VST40 - vst40.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST40_16_wb (1689) - ARM_INS_VST40 - vst40.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST40_32 (1690) - ARM_INS_VST40 - vst40.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST40_32_wb (1691) - ARM_INS_VST40 - vst40.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST40_8 (1692) - ARM_INS_VST40 - vst40.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST40_8_wb (1693) - ARM_INS_VST40 - vst40.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST41_16 (1694) - ARM_INS_VST41 - vst41.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST41_16_wb (1695) - ARM_INS_VST41 - vst41.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST41_32 (1696) - ARM_INS_VST41 - vst41.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST41_32_wb (1697) - ARM_INS_VST41 - vst41.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST41_8 (1698) - ARM_INS_VST41 - vst41.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST41_8_wb (1699) - ARM_INS_VST41 - vst41.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST42_16 (1700) - ARM_INS_VST42 - vst42.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST42_16_wb (1701) - ARM_INS_VST42 - vst42.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST42_32 (1702) - ARM_INS_VST42 - vst42.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST42_32_wb (1703) - ARM_INS_VST42 - vst42.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST42_8 (1704) - ARM_INS_VST42 - vst42.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST42_8_wb (1705) - ARM_INS_VST42 - vst42.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST43_16 (1706) - ARM_INS_VST43 - vst43.16	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST43_16_wb (1707) - ARM_INS_VST43 - vst43.16	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST43_32 (1708) - ARM_INS_VST43 - vst43.32	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST43_32_wb (1709) - ARM_INS_VST43 - vst43.32	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VST43_8 (1710) - ARM_INS_VST43 - vst43.8	$VQd, $Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { 0 }
+}},
+{ /* ARM_MVE_VST43_8_wb (1711) - ARM_INS_VST43 - vst43.8	$VQd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v8i64, CS_DATA_TYPE_LAST } }, /* VQd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB16 (1712) - ARM_INS_VSTRB - vstrb${vp}.16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB16_post (1713) - ARM_INS_VSTRB - vstrb${vp}.16	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB16_pre (1714) - ARM_INS_VSTRB - vstrb${vp}.16	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB16_rq (1715) - ARM_INS_VSTRB - vstrb${vp}.16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB32 (1716) - ARM_INS_VSTRB - vstrb${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB32_post (1717) - ARM_INS_VSTRB - vstrb${vp}.32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB32_pre (1718) - ARM_INS_VSTRB - vstrb${vp}.32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB32_rq (1719) - ARM_INS_VSTRB - vstrb${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRB8_rq (1720) - ARM_INS_VSTRB - vstrb${vp}.8	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRBU8 (1721) - ARM_INS_VSTRB - vstrb${vp}.8	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRBU8_post (1722) - ARM_INS_VSTRB - vstrb${vp}.8	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRBU8_pre (1723) - ARM_INS_VSTRB - vstrb${vp}.8	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRD64_qi (1724) - ARM_INS_VSTRD - vstrd${vp}.64	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRD64_qi_pre (1725) - ARM_INS_VSTRD - vstrd${vp}.64	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRD64_rq (1726) - ARM_INS_VSTRD - vstrd${vp}.64	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRD64_rq_u (1727) - ARM_INS_VSTRD - vstrd${vp}.64	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH16_rq (1728) - ARM_INS_VSTRH - vstrh${vp}.16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH16_rq_u (1729) - ARM_INS_VSTRH - vstrh${vp}.16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH32 (1730) - ARM_INS_VSTRH - vstrh${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH32_post (1731) - ARM_INS_VSTRH - vstrh${vp}.32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH32_pre (1732) - ARM_INS_VSTRH - vstrh${vp}.32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH32_rq (1733) - ARM_INS_VSTRH - vstrh${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRH32_rq_u (1734) - ARM_INS_VSTRH - vstrh${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRHU16 (1735) - ARM_INS_VSTRH - vstrh${vp}.16	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRHU16_post (1736) - ARM_INS_VSTRH - vstrh${vp}.16	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRHU16_pre (1737) - ARM_INS_VSTRH - vstrh${vp}.16	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRW32_qi (1738) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRW32_qi_pre (1739) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRW32_rq (1740) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRW32_rq_u (1741) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* addr - MQPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRWU32 (1742) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRWU32_post (1743) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSTRWU32_pre (1744) - ARM_INS_VSTRW - vstrw${vp}.32	$Qd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUB_qr_f16 (1745) - ARM_INS_VSUB - vsub${vp}.f16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUB_qr_f32 (1746) - ARM_INS_VSUB - vsub${vp}.f32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUB_qr_i16 (1747) - ARM_INS_VSUB - vsub${vp}.i16	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUB_qr_i32 (1748) - ARM_INS_VSUB - vsub${vp}.i32	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUB_qr_i8 (1749) - ARM_INS_VSUB - vsub${vp}.i8	$Qd, $Qn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUBf16 (1750) - ARM_INS_VSUB - vsub${vp}.f16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUBf32 (1751) - ARM_INS_VSUB - vsub${vp}.f32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUBi16 (1752) - ARM_INS_VSUB - vsub${vp}.i16	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUBi32 (1753) - ARM_INS_VSUB - vsub${vp}.i32	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_VSUBi8 (1754) - ARM_INS_VSUB - vsub${vp}.i8	$Qd, $Qn, $Qm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* Qm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* vp - VCCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* vp - GPRlr */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_LAST } }, /* vp - MQPR */
+  { 0 }
+}},
+{ /* ARM_MVE_WLSTP_16 (1755) - ARM_INS_WLSTP - wlstp.16	$LR, $Rn, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_MVE_WLSTP_32 (1756) - ARM_INS_WLSTP - wlstp.32	$LR, $Rn, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_MVE_WLSTP_64 (1757) - ARM_INS_WLSTP - wlstp.64	$LR, $Rn, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_MVE_WLSTP_8 (1758) - ARM_INS_WLSTP - wlstp.8	$LR, $Rn, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_MVNi (1759) - ARM_INS_MVN - mvn${s}${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MVNr (1760) - ARM_INS_MVN - mvn${s}${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MVNsi (1761) - ARM_INS_MVN - mvn${s}${p}	$Rd, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_MVNsr (1762) - ARM_INS_MVN - mvn${s}${p}	$Rd, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_NEON_VMAXNMNDf (1763) - ARM_INS_VMAXNM - vmaxnm.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMAXNMNDh (1764) - ARM_INS_VMAXNM - vmaxnm.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMAXNMNQf (1765) - ARM_INS_VMAXNM - vmaxnm.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMAXNMNQh (1766) - ARM_INS_VMAXNM - vmaxnm.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMINNMNDf (1767) - ARM_INS_VMINNM - vminnm.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMINNMNDh (1768) - ARM_INS_VMINNM - vminnm.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMINNMNQf (1769) - ARM_INS_VMINNM - vminnm.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_NEON_VMINNMNQh (1770) - ARM_INS_VMINNM - vminnm.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_ORRri (1771) - ARM_INS_ORR - orr${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ORRrr (1772) - ARM_INS_ORR - orr${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ORRrsi (1773) - ARM_INS_ORR - orr${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_ORRrsr (1774) - ARM_INS_ORR - orr${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_PKHBT (1775) - ARM_INS_PKHBT - pkhbt${p}	$Rd, $Rn, $Rm$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_PKHTB (1776) - ARM_INS_PKHTB - pkhtb${p}	$Rd, $Rn, $Rm$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_PLDWi12 (1777) - ARM_INS_PLDW - pldw	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_PLDWrs (1778) - ARM_INS_PLDW - pldw	$shift */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { 0 }
+}},
+{ /* ARM_PLDi12 (1779) - ARM_INS_PLD - pld	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_PLDrs (1780) - ARM_INS_PLD - pld	$shift */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { 0 }
+}},
+{ /* ARM_PLIi12 (1781) - ARM_INS_PLI - pli	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_PLIrs (1782) - ARM_INS_PLI - pli	$shift */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { 0 }
+}},
+{ /* ARM_QADD (1783) - ARM_INS_QADD - qadd${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QADD16 (1784) - ARM_INS_QADD16 - qadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QADD8 (1785) - ARM_INS_QADD8 - qadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QASX (1786) - ARM_INS_QASX - qasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QDADD (1787) - ARM_INS_QDADD - qdadd${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QDSUB (1788) - ARM_INS_QDSUB - qdsub${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QSAX (1789) - ARM_INS_QSAX - qsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QSUB (1790) - ARM_INS_QSUB - qsub${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QSUB16 (1791) - ARM_INS_QSUB16 - qsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_QSUB8 (1792) - ARM_INS_QSUB8 - qsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_RBIT (1793) - ARM_INS_RBIT - rbit${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_REV (1794) - ARM_INS_REV - rev${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_REV16 (1795) - ARM_INS_REV16 - rev16${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_REVSH (1796) - ARM_INS_REVSH - revsh${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_RFEDA (1797) - ARM_INS_RFEDA - rfeda	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEDA_UPD (1798) - ARM_INS_RFEDA - rfeda	$Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEDB (1799) - ARM_INS_RFEDB - rfedb	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEDB_UPD (1800) - ARM_INS_RFEDB - rfedb	$Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEIA (1801) - ARM_INS_RFEIA - rfeia	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEIA_UPD (1802) - ARM_INS_RFEIA - rfeia	$Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEIB (1803) - ARM_INS_RFEIB - rfeib	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RFEIB_UPD (1804) - ARM_INS_RFEIB - rfeib	$Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_RSBri (1805) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSBrr (1806) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSBrsi (1807) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSBrsr (1808) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSCri (1809) - ARM_INS_RSC - rsc${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSCrr (1810) - ARM_INS_RSC - rsc${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSCrsi (1811) - ARM_INS_RSC - rsc${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_RSCrsr (1812) - ARM_INS_RSC - rsc${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SADD16 (1813) - ARM_INS_SADD16 - sadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SADD8 (1814) - ARM_INS_SADD8 - sadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SASX (1815) - ARM_INS_SASX - sasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SB (1816) - ARM_INS_SB - sb */
+{
+  { 0 }
+}},
+{ /* ARM_SBCri (1817) - ARM_INS_SBC - sbc${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SBCrr (1818) - ARM_INS_SBC - sbc${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SBCrsi (1819) - ARM_INS_SBC - sbc${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SBCrsr (1820) - ARM_INS_SBC - sbc${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SBFX (1821) - ARM_INS_SBFX - sbfx${p}	$Rd, $Rn, $lsb, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SDIV (1822) - ARM_INS_SDIV - sdiv${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SEL (1823) - ARM_INS_SEL - sel${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SETEND (1824) - ARM_INS_SETEND - setend	$end */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* end */
+  { 0 }
+}},
+{ /* ARM_SETPAN (1825) - ARM_INS_SETPAN - setpan	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_SHA1C (1826) - ARM_INS_SHA1C - sha1c.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA1H (1827) - ARM_INS_SHA1H - sha1h.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA1M (1828) - ARM_INS_SHA1M - sha1m.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA1P (1829) - ARM_INS_SHA1P - sha1p.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA1SU0 (1830) - ARM_INS_SHA1SU0 - sha1su0.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA1SU1 (1831) - ARM_INS_SHA1SU1 - sha1su1.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA256H (1832) - ARM_INS_SHA256H - sha256h.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA256H2 (1833) - ARM_INS_SHA256H2 - sha256h2.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA256SU0 (1834) - ARM_INS_SHA256SU0 - sha256su0.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHA256SU1 (1835) - ARM_INS_SHA256SU1 - sha256su1.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_SHADD16 (1836) - ARM_INS_SHADD16 - shadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SHADD8 (1837) - ARM_INS_SHADD8 - shadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SHASX (1838) - ARM_INS_SHASX - shasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SHSAX (1839) - ARM_INS_SHSAX - shsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SHSUB16 (1840) - ARM_INS_SHSUB16 - shsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SHSUB8 (1841) - ARM_INS_SHSUB8 - shsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMC (1842) - ARM_INS_SMC - smc${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLABB (1843) - ARM_INS_SMLABB - smlabb${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLABT (1844) - ARM_INS_SMLABT - smlabt${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLAD (1845) - ARM_INS_SMLAD - smlad${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLADX (1846) - ARM_INS_SMLADX - smladx${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLAL (1847) - ARM_INS_SMLAL - smlal${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SMLALBB (1848) - ARM_INS_SMLALBB - smlalbb${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLALBT (1849) - ARM_INS_SMLALBT - smlalbt${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLALD (1850) - ARM_INS_SMLALD - smlald${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLALDX (1851) - ARM_INS_SMLALDX - smlaldx${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLALTB (1852) - ARM_INS_SMLALTB - smlaltb${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLALTT (1853) - ARM_INS_SMLALTT - smlaltt${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLATB (1854) - ARM_INS_SMLATB - smlatb${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLATT (1855) - ARM_INS_SMLATT - smlatt${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLAWB (1856) - ARM_INS_SMLAWB - smlawb${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLAWT (1857) - ARM_INS_SMLAWT - smlawt${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLSD (1858) - ARM_INS_SMLSD - smlsd${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLSDX (1859) - ARM_INS_SMLSDX - smlsdx${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLSLD (1860) - ARM_INS_SMLSLD - smlsld${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMLSLDX (1861) - ARM_INS_SMLSLDX - smlsldx${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMMLA (1862) - ARM_INS_SMMLA - smmla${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMMLAR (1863) - ARM_INS_SMMLAR - smmlar${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMMLS (1864) - ARM_INS_SMMLS - smmls${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMMLSR (1865) - ARM_INS_SMMLSR - smmlsr${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMMUL (1866) - ARM_INS_SMMUL - smmul${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMMULR (1867) - ARM_INS_SMMULR - smmulr${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMUAD (1868) - ARM_INS_SMUAD - smuad${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMUADX (1869) - ARM_INS_SMUADX - smuadx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMULBB (1870) - ARM_INS_SMULBB - smulbb${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMULBT (1871) - ARM_INS_SMULBT - smulbt${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMULL (1872) - ARM_INS_SMULL - smull${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SMULTB (1873) - ARM_INS_SMULTB - smultb${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMULTT (1874) - ARM_INS_SMULTT - smultt${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMULWB (1875) - ARM_INS_SMULWB - smulwb${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMULWT (1876) - ARM_INS_SMULWT - smulwt${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMUSD (1877) - ARM_INS_SMUSD - smusd${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SMUSDX (1878) - ARM_INS_SMUSDX - smusdx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SRSDA (1879) - ARM_INS_SRSDA - srsda	sp, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSDA_UPD (1880) - ARM_INS_SRSDA - srsda	sp!, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSDB (1881) - ARM_INS_SRSDB - srsdb	sp, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSDB_UPD (1882) - ARM_INS_SRSDB - srsdb	sp!, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSIA (1883) - ARM_INS_SRSIA - srsia	sp, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSIA_UPD (1884) - ARM_INS_SRSIA - srsia	sp!, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSIB (1885) - ARM_INS_SRSIB - srsib	sp, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SRSIB_UPD (1886) - ARM_INS_SRSIB - srsib	sp!, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_SSAT (1887) - ARM_INS_SSAT - ssat${p}	$Rd, $sat_imm, $Rn$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SSAT16 (1888) - ARM_INS_SSAT16 - ssat16${p}	$Rd, $sat_imm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SSAX (1889) - ARM_INS_SSAX - ssax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SSUB16 (1890) - ARM_INS_SSUB16 - ssub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SSUB8 (1891) - ARM_INS_SSUB8 - ssub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC2L_OFFSET (1892) - ARM_INS_STC2L - stc2l	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC2L_OPTION (1893) - ARM_INS_STC2L - stc2l	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { 0 }
+}},
+{ /* ARM_STC2L_POST (1894) - ARM_INS_STC2L - stc2l	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC2L_PRE (1895) - ARM_INS_STC2L - stc2l	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC2_OFFSET (1896) - ARM_INS_STC2 - stc2	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC2_OPTION (1897) - ARM_INS_STC2 - stc2	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { 0 }
+}},
+{ /* ARM_STC2_POST (1898) - ARM_INS_STC2 - stc2	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC2_PRE (1899) - ARM_INS_STC2 - stc2	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { 0 }
+}},
+{ /* ARM_STCL_OFFSET (1900) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STCL_OPTION (1901) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STCL_POST (1902) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STCL_PRE (1903) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC_OFFSET (1904) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC_OPTION (1905) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC_POST (1906) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STC_PRE (1907) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STL (1908) - ARM_INS_STL - stl${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STLB (1909) - ARM_INS_STLB - stlb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STLEX (1910) - ARM_INS_STLEX - stlex${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STLEXB (1911) - ARM_INS_STLEXB - stlexb${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STLEXD (1912) - ARM_INS_STLEXD - stlexd${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STLEXH (1913) - ARM_INS_STLEXH - stlexh${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STLH (1914) - ARM_INS_STLH - stlh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STMDA (1915) - ARM_INS_STMDA - stmda${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMDA_UPD (1916) - ARM_INS_STMDA - stmda${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMDB (1917) - ARM_INS_STMDB - stmdb${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMDB_UPD (1918) - ARM_INS_STMDB - stmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMIA (1919) - ARM_INS_STM - stm${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMIA_UPD (1920) - ARM_INS_STM - stm${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMIB (1921) - ARM_INS_STMIB - stmib${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STMIB_UPD (1922) - ARM_INS_STMIB - stmib${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_STRBT_POST_IMM (1923) - ARM_INS_STRBT - strbt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRBT_POST_REG (1924) - ARM_INS_STRBT - strbt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRB_POST_IMM (1925) - ARM_INS_STRB - strb${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRB_POST_REG (1926) - ARM_INS_STRB - strb${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRB_PRE_IMM (1927) - ARM_INS_STRB - strb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRB_PRE_REG (1928) - ARM_INS_STRB - strb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRBi12 (1929) - ARM_INS_STRB - strb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRBrs (1930) - ARM_INS_STRB - strb${p}	$Rt, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRD (1931) - ARM_INS_STRD - strd${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRD_POST (1932) - ARM_INS_STRD - strd${p}	$Rt, $Rt2, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRD_PRE (1933) - ARM_INS_STRD - strd${p}	$Rt, $Rt2, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STREX (1934) - ARM_INS_STREX - strex${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STREXB (1935) - ARM_INS_STREXB - strexb${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STREXD (1936) - ARM_INS_STREXD - strexd${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_Untyped, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STREXH (1937) - ARM_INS_STREXH - strexh${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRH (1938) - ARM_INS_STRH - strh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRHTi (1939) - ARM_INS_STRHT - strht${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRHTr (1940) - ARM_INS_STRHT - strht${p}	$Rt, $addr, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* base_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRH_POST (1941) - ARM_INS_STRH - strh${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRH_PRE (1942) - ARM_INS_STRH - strh${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRT_POST_IMM (1943) - ARM_INS_STRT - strt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRT_POST_REG (1944) - ARM_INS_STRT - strt${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STR_POST_IMM (1945) - ARM_INS_STR - str${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STR_POST_REG (1946) - ARM_INS_STR - str${p}	$Rt, $addr, $offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STR_PRE_IMM (1947) - ARM_INS_STR - str${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STR_PRE_REG (1948) - ARM_INS_STR - str${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRi12 (1949) - ARM_INS_STR - str${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_STRrs (1950) - ARM_INS_STR - str${p}	$Rt, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SUBri (1951) - ARM_INS_SUB - sub${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SUBrr (1952) - ARM_INS_SUB - sub${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SUBrsi (1953) - ARM_INS_SUB - sub${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SUBrsr (1954) - ARM_INS_SUB - sub${s}${p}	$Rd, $Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_SVC (1955) - ARM_INS_SVC - svc${p}	$svc */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* svc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SWP (1956) - ARM_INS_SWP - swp${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SWPB (1957) - ARM_INS_SWPB - swpb${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SXTAB (1958) - ARM_INS_SXTAB - sxtab${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SXTAB16 (1959) - ARM_INS_SXTAB16 - sxtab16${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SXTAH (1960) - ARM_INS_SXTAH - sxtah${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SXTB (1961) - ARM_INS_SXTB - sxtb${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SXTB16 (1962) - ARM_INS_SXTB16 - sxtb16${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_SXTH (1963) - ARM_INS_SXTH - sxth${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TEQri (1964) - ARM_INS_TEQ - teq${p}	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TEQrr (1965) - ARM_INS_TEQ - teq${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TEQrsi (1966) - ARM_INS_TEQ - teq${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TEQrsr (1967) - ARM_INS_TEQ - teq${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TRAP (1968) - ARM_INS_TRAP - trap */
+{
+  { 0 }
+}},
+{ /* ARM_TRAPNaCl (1969) - ARM_INS_TRAP - trap */
+{
+  { 0 }
+}},
+{ /* ARM_TSB (1970) - ARM_INS_TSB - tsb	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { 0 }
+}},
+{ /* ARM_TSTri (1971) - ARM_INS_TST - tst${p}	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TSTrr (1972) - ARM_INS_TST - tst${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TSTrsi (1973) - ARM_INS_TST - tst${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_TSTrsr (1974) - ARM_INS_TST - tst${p}	$Rn, $shift */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - GPRnopc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* shift - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UADD16 (1975) - ARM_INS_UADD16 - uadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UADD8 (1976) - ARM_INS_UADD8 - uadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UASX (1977) - ARM_INS_UASX - uasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UBFX (1978) - ARM_INS_UBFX - ubfx${p}	$Rd, $Rn, $lsb, $width */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* width */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UDF (1979) - ARM_INS_UDF - udf	$imm16 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */
+  { 0 }
+}},
+{ /* ARM_UDIV (1980) - ARM_INS_UDIV - udiv${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UHADD16 (1981) - ARM_INS_UHADD16 - uhadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UHADD8 (1982) - ARM_INS_UHADD8 - uhadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UHASX (1983) - ARM_INS_UHASX - uhasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UHSAX (1984) - ARM_INS_UHSAX - uhsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UHSUB16 (1985) - ARM_INS_UHSUB16 - uhsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UHSUB8 (1986) - ARM_INS_UHSUB8 - uhsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UMAAL (1987) - ARM_INS_UMAAL - umaal${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UMLAL (1988) - ARM_INS_UMLAL - umlal${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_UMULL (1989) - ARM_INS_UMULL - umull${s}${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_UQADD16 (1990) - ARM_INS_UQADD16 - uqadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UQADD8 (1991) - ARM_INS_UQADD8 - uqadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UQASX (1992) - ARM_INS_UQASX - uqasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UQSAX (1993) - ARM_INS_UQSAX - uqsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UQSUB16 (1994) - ARM_INS_UQSUB16 - uqsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UQSUB8 (1995) - ARM_INS_UQSUB8 - uqsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USAD8 (1996) - ARM_INS_USAD8 - usad8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USADA8 (1997) - ARM_INS_USADA8 - usada8${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USAT (1998) - ARM_INS_USAT - usat${p}	$Rd, $sat_imm, $Rn$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USAT16 (1999) - ARM_INS_USAT16 - usat16${p}	$Rd, $sat_imm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USAX (2000) - ARM_INS_USAX - usax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USUB16 (2001) - ARM_INS_USUB16 - usub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_USUB8 (2002) - ARM_INS_USUB8 - usub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UXTAB (2003) - ARM_INS_UXTAB - uxtab${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UXTAB16 (2004) - ARM_INS_UXTAB16 - uxtab16${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UXTAH (2005) - ARM_INS_UXTAH - uxtah${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UXTB (2006) - ARM_INS_UXTB - uxtb${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UXTB16 (2007) - ARM_INS_UXTB16 - uxtb16${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_UXTH (2008) - ARM_INS_UXTH - uxth${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABALsv2i64 (2009) - ARM_INS_VABAL - vabal${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABALsv4i32 (2010) - ARM_INS_VABAL - vabal${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABALsv8i16 (2011) - ARM_INS_VABAL - vabal${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABALuv2i64 (2012) - ARM_INS_VABAL - vabal${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABALuv4i32 (2013) - ARM_INS_VABAL - vabal${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABALuv8i16 (2014) - ARM_INS_VABAL - vabal${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAsv16i8 (2015) - ARM_INS_VABA - vaba${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAsv2i32 (2016) - ARM_INS_VABA - vaba${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAsv4i16 (2017) - ARM_INS_VABA - vaba${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAsv4i32 (2018) - ARM_INS_VABA - vaba${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAsv8i16 (2019) - ARM_INS_VABA - vaba${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAsv8i8 (2020) - ARM_INS_VABA - vaba${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAuv16i8 (2021) - ARM_INS_VABA - vaba${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAuv2i32 (2022) - ARM_INS_VABA - vaba${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAuv4i16 (2023) - ARM_INS_VABA - vaba${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAuv4i32 (2024) - ARM_INS_VABA - vaba${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAuv8i16 (2025) - ARM_INS_VABA - vaba${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABAuv8i8 (2026) - ARM_INS_VABA - vaba${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDLsv2i64 (2027) - ARM_INS_VABDL - vabdl${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDLsv4i32 (2028) - ARM_INS_VABDL - vabdl${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDLsv8i16 (2029) - ARM_INS_VABDL - vabdl${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDLuv2i64 (2030) - ARM_INS_VABDL - vabdl${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDLuv4i32 (2031) - ARM_INS_VABDL - vabdl${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDLuv8i16 (2032) - ARM_INS_VABDL - vabdl${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDfd (2033) - ARM_INS_VABD - vabd${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDfq (2034) - ARM_INS_VABD - vabd${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDhd (2035) - ARM_INS_VABD - vabd${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDhq (2036) - ARM_INS_VABD - vabd${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDsv16i8 (2037) - ARM_INS_VABD - vabd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDsv2i32 (2038) - ARM_INS_VABD - vabd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDsv4i16 (2039) - ARM_INS_VABD - vabd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDsv4i32 (2040) - ARM_INS_VABD - vabd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDsv8i16 (2041) - ARM_INS_VABD - vabd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDsv8i8 (2042) - ARM_INS_VABD - vabd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDuv16i8 (2043) - ARM_INS_VABD - vabd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDuv2i32 (2044) - ARM_INS_VABD - vabd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDuv4i16 (2045) - ARM_INS_VABD - vabd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDuv4i32 (2046) - ARM_INS_VABD - vabd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDuv8i16 (2047) - ARM_INS_VABD - vabd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABDuv8i8 (2048) - ARM_INS_VABD - vabd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSD (2049) - ARM_INS_VABS - vabs${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSH (2050) - ARM_INS_VABS - vabs${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSS (2051) - ARM_INS_VABS - vabs${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSfd (2052) - ARM_INS_VABS - vabs${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSfq (2053) - ARM_INS_VABS - vabs${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABShd (2054) - ARM_INS_VABS - vabs${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABShq (2055) - ARM_INS_VABS - vabs${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSv16i8 (2056) - ARM_INS_VABS - vabs${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSv2i32 (2057) - ARM_INS_VABS - vabs${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSv4i16 (2058) - ARM_INS_VABS - vabs${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSv4i32 (2059) - ARM_INS_VABS - vabs${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSv8i16 (2060) - ARM_INS_VABS - vabs${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VABSv8i8 (2061) - ARM_INS_VABS - vabs${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGEfd (2062) - ARM_INS_VACGE - vacge${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGEfq (2063) - ARM_INS_VACGE - vacge${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGEhd (2064) - ARM_INS_VACGE - vacge${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGEhq (2065) - ARM_INS_VACGE - vacge${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGTfd (2066) - ARM_INS_VACGT - vacgt${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGTfq (2067) - ARM_INS_VACGT - vacgt${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGThd (2068) - ARM_INS_VACGT - vacgt${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VACGThq (2069) - ARM_INS_VACGT - vacgt${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDD (2070) - ARM_INS_VADD - vadd${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDH (2071) - ARM_INS_VADD - vadd${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDHNv2i32 (2072) - ARM_INS_VADDHN - vaddhn${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDHNv4i16 (2073) - ARM_INS_VADDHN - vaddhn${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDHNv8i8 (2074) - ARM_INS_VADDHN - vaddhn${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDLsv2i64 (2075) - ARM_INS_VADDL - vaddl${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDLsv4i32 (2076) - ARM_INS_VADDL - vaddl${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDLsv8i16 (2077) - ARM_INS_VADDL - vaddl${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDLuv2i64 (2078) - ARM_INS_VADDL - vaddl${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDLuv4i32 (2079) - ARM_INS_VADDL - vaddl${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDLuv8i16 (2080) - ARM_INS_VADDL - vaddl${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDS (2081) - ARM_INS_VADD - vadd${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDWsv2i64 (2082) - ARM_INS_VADDW - vaddw${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDWsv4i32 (2083) - ARM_INS_VADDW - vaddw${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDWsv8i16 (2084) - ARM_INS_VADDW - vaddw${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDWuv2i64 (2085) - ARM_INS_VADDW - vaddw${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDWuv4i32 (2086) - ARM_INS_VADDW - vaddw${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDWuv8i16 (2087) - ARM_INS_VADDW - vaddw${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDfd (2088) - ARM_INS_VADD - vadd${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDfq (2089) - ARM_INS_VADD - vadd${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDhd (2090) - ARM_INS_VADD - vadd${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDhq (2091) - ARM_INS_VADD - vadd${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv16i8 (2092) - ARM_INS_VADD - vadd${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv1i64 (2093) - ARM_INS_VADD - vadd${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv2i32 (2094) - ARM_INS_VADD - vadd${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv2i64 (2095) - ARM_INS_VADD - vadd${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv4i16 (2096) - ARM_INS_VADD - vadd${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv4i32 (2097) - ARM_INS_VADD - vadd${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv8i16 (2098) - ARM_INS_VADD - vadd${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VADDv8i8 (2099) - ARM_INS_VADD - vadd${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VANDd (2100) - ARM_INS_VAND - vand${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VANDq (2101) - ARM_INS_VAND - vand${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBF16MALBQ (2102) - ARM_INS_VFMAB - vfmab.bf16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VBF16MALBQI (2103) - ARM_INS_VFMAB - vfmab.bf16	$Vd, $Vn, $Vm$idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBF16MALTQ (2104) - ARM_INS_VFMAT - vfmat.bf16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VBF16MALTQI (2105) - ARM_INS_VFMAT - vfmat.bf16	$Vd, $Vn, $Vm$idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBICd (2106) - ARM_INS_VBIC - vbic${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBICiv2i32 (2107) - ARM_INS_VBIC - vbic${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBICiv4i16 (2108) - ARM_INS_VBIC - vbic${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBICiv4i32 (2109) - ARM_INS_VBIC - vbic${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBICiv8i16 (2110) - ARM_INS_VBIC - vbic${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBICq (2111) - ARM_INS_VBIC - vbic${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBIFd (2112) - ARM_INS_VBIF - vbif${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBIFq (2113) - ARM_INS_VBIF - vbif${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBITd (2114) - ARM_INS_VBIT - vbit${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBITq (2115) - ARM_INS_VBIT - vbit${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBSLd (2116) - ARM_INS_VBSL - vbsl${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VBSLq (2117) - ARM_INS_VBSL - vbsl${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VBSPd (2118) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VBSPq (2119) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VCADDv2f32 (2120) - ARM_INS_VCADD - vcadd.f32	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCADDv4f16 (2121) - ARM_INS_VCADD - vcadd.f16	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCADDv4f32 (2122) - ARM_INS_VCADD - vcadd.f32	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCADDv8f16 (2123) - ARM_INS_VCADD - vcadd.f16	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCEQfd (2124) - ARM_INS_VCEQ - vceq${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQfq (2125) - ARM_INS_VCEQ - vceq${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQhd (2126) - ARM_INS_VCEQ - vceq${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQhq (2127) - ARM_INS_VCEQ - vceq${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQv16i8 (2128) - ARM_INS_VCEQ - vceq${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQv2i32 (2129) - ARM_INS_VCEQ - vceq${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQv4i16 (2130) - ARM_INS_VCEQ - vceq${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQv4i32 (2131) - ARM_INS_VCEQ - vceq${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQv8i16 (2132) - ARM_INS_VCEQ - vceq${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQv8i8 (2133) - ARM_INS_VCEQ - vceq${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv16i8 (2134) - ARM_INS_VCEQ - vceq${p}.i8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv2f32 (2135) - ARM_INS_VCEQ - vceq${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv2i32 (2136) - ARM_INS_VCEQ - vceq${p}.i32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv4f16 (2137) - ARM_INS_VCEQ - vceq${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv4f32 (2138) - ARM_INS_VCEQ - vceq${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv4i16 (2139) - ARM_INS_VCEQ - vceq${p}.i16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv4i32 (2140) - ARM_INS_VCEQ - vceq${p}.i32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv8f16 (2141) - ARM_INS_VCEQ - vceq${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv8i16 (2142) - ARM_INS_VCEQ - vceq${p}.i16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCEQzv8i8 (2143) - ARM_INS_VCEQ - vceq${p}.i8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEfd (2144) - ARM_INS_VCGE - vcge${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEfq (2145) - ARM_INS_VCGE - vcge${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEhd (2146) - ARM_INS_VCGE - vcge${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEhq (2147) - ARM_INS_VCGE - vcge${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEsv16i8 (2148) - ARM_INS_VCGE - vcge${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEsv2i32 (2149) - ARM_INS_VCGE - vcge${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEsv4i16 (2150) - ARM_INS_VCGE - vcge${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEsv4i32 (2151) - ARM_INS_VCGE - vcge${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEsv8i16 (2152) - ARM_INS_VCGE - vcge${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEsv8i8 (2153) - ARM_INS_VCGE - vcge${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEuv16i8 (2154) - ARM_INS_VCGE - vcge${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEuv2i32 (2155) - ARM_INS_VCGE - vcge${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEuv4i16 (2156) - ARM_INS_VCGE - vcge${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEuv4i32 (2157) - ARM_INS_VCGE - vcge${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEuv8i16 (2158) - ARM_INS_VCGE - vcge${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEuv8i8 (2159) - ARM_INS_VCGE - vcge${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv16i8 (2160) - ARM_INS_VCGE - vcge${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv2f32 (2161) - ARM_INS_VCGE - vcge${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv2i32 (2162) - ARM_INS_VCGE - vcge${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv4f16 (2163) - ARM_INS_VCGE - vcge${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv4f32 (2164) - ARM_INS_VCGE - vcge${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv4i16 (2165) - ARM_INS_VCGE - vcge${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv4i32 (2166) - ARM_INS_VCGE - vcge${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv8f16 (2167) - ARM_INS_VCGE - vcge${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv8i16 (2168) - ARM_INS_VCGE - vcge${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGEzv8i8 (2169) - ARM_INS_VCGE - vcge${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTfd (2170) - ARM_INS_VCGT - vcgt${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTfq (2171) - ARM_INS_VCGT - vcgt${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGThd (2172) - ARM_INS_VCGT - vcgt${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGThq (2173) - ARM_INS_VCGT - vcgt${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTsv16i8 (2174) - ARM_INS_VCGT - vcgt${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTsv2i32 (2175) - ARM_INS_VCGT - vcgt${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTsv4i16 (2176) - ARM_INS_VCGT - vcgt${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTsv4i32 (2177) - ARM_INS_VCGT - vcgt${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTsv8i16 (2178) - ARM_INS_VCGT - vcgt${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTsv8i8 (2179) - ARM_INS_VCGT - vcgt${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTuv16i8 (2180) - ARM_INS_VCGT - vcgt${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTuv2i32 (2181) - ARM_INS_VCGT - vcgt${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTuv4i16 (2182) - ARM_INS_VCGT - vcgt${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTuv4i32 (2183) - ARM_INS_VCGT - vcgt${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTuv8i16 (2184) - ARM_INS_VCGT - vcgt${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTuv8i8 (2185) - ARM_INS_VCGT - vcgt${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv16i8 (2186) - ARM_INS_VCGT - vcgt${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv2f32 (2187) - ARM_INS_VCGT - vcgt${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv2i32 (2188) - ARM_INS_VCGT - vcgt${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv4f16 (2189) - ARM_INS_VCGT - vcgt${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv4f32 (2190) - ARM_INS_VCGT - vcgt${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv4i16 (2191) - ARM_INS_VCGT - vcgt${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv4i32 (2192) - ARM_INS_VCGT - vcgt${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv8f16 (2193) - ARM_INS_VCGT - vcgt${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv8i16 (2194) - ARM_INS_VCGT - vcgt${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCGTzv8i8 (2195) - ARM_INS_VCGT - vcgt${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv16i8 (2196) - ARM_INS_VCLE - vcle${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv2f32 (2197) - ARM_INS_VCLE - vcle${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv2i32 (2198) - ARM_INS_VCLE - vcle${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv4f16 (2199) - ARM_INS_VCLE - vcle${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv4f32 (2200) - ARM_INS_VCLE - vcle${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv4i16 (2201) - ARM_INS_VCLE - vcle${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv4i32 (2202) - ARM_INS_VCLE - vcle${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv8f16 (2203) - ARM_INS_VCLE - vcle${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv8i16 (2204) - ARM_INS_VCLE - vcle${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLEzv8i8 (2205) - ARM_INS_VCLE - vcle${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLSv16i8 (2206) - ARM_INS_VCLS - vcls${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLSv2i32 (2207) - ARM_INS_VCLS - vcls${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLSv4i16 (2208) - ARM_INS_VCLS - vcls${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLSv4i32 (2209) - ARM_INS_VCLS - vcls${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLSv8i16 (2210) - ARM_INS_VCLS - vcls${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLSv8i8 (2211) - ARM_INS_VCLS - vcls${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv16i8 (2212) - ARM_INS_VCLT - vclt${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv2f32 (2213) - ARM_INS_VCLT - vclt${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv2i32 (2214) - ARM_INS_VCLT - vclt${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv4f16 (2215) - ARM_INS_VCLT - vclt${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv4f32 (2216) - ARM_INS_VCLT - vclt${p}.f32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv4i16 (2217) - ARM_INS_VCLT - vclt${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv4i32 (2218) - ARM_INS_VCLT - vclt${p}.s32	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv8f16 (2219) - ARM_INS_VCLT - vclt${p}.f16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv8i16 (2220) - ARM_INS_VCLT - vclt${p}.s16	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLTzv8i8 (2221) - ARM_INS_VCLT - vclt${p}.s8	$Vd, $Vm, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLZv16i8 (2222) - ARM_INS_VCLZ - vclz${p}.i8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLZv2i32 (2223) - ARM_INS_VCLZ - vclz${p}.i32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLZv4i16 (2224) - ARM_INS_VCLZ - vclz${p}.i16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLZv4i32 (2225) - ARM_INS_VCLZ - vclz${p}.i32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLZv8i16 (2226) - ARM_INS_VCLZ - vclz${p}.i16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCLZv8i8 (2227) - ARM_INS_VCLZ - vclz${p}.i8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMLAv2f32 (2228) - ARM_INS_VCMLA - vcmla.f32	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv2f32_indexed (2229) - ARM_INS_VCMLA - vcmla.f32	$Vd, $Vn, $Vm$lane, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv4f16 (2230) - ARM_INS_VCMLA - vcmla.f16	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv4f16_indexed (2231) - ARM_INS_VCMLA - vcmla.f16	$Vd, $Vn, $Vm$lane, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv4f32 (2232) - ARM_INS_VCMLA - vcmla.f32	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv4f32_indexed (2233) - ARM_INS_VCMLA - vcmla.f32	$Vd, $Vn, $Vm$lane, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv8f16 (2234) - ARM_INS_VCMLA - vcmla.f16	$Vd, $Vn, $Vm, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMLAv8f16_indexed (2235) - ARM_INS_VCMLA - vcmla.f16	$Vd, $Vn, $Vm$lane, $rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { 0 }
+}},
+{ /* ARM_VCMPD (2236) - ARM_INS_VCMP - vcmp${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPED (2237) - ARM_INS_VCMPE - vcmpe${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPEH (2238) - ARM_INS_VCMPE - vcmpe${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPES (2239) - ARM_INS_VCMPE - vcmpe${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPEZD (2240) - ARM_INS_VCMPE - vcmpe${p}.f64	$Dd, #0 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPEZH (2241) - ARM_INS_VCMPE - vcmpe${p}.f16	$Sd, #0 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPEZS (2242) - ARM_INS_VCMPE - vcmpe${p}.f32	$Sd, #0 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPH (2243) - ARM_INS_VCMP - vcmp${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPS (2244) - ARM_INS_VCMP - vcmp${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPZD (2245) - ARM_INS_VCMP - vcmp${p}.f64	$Dd, #0 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPZH (2246) - ARM_INS_VCMP - vcmp${p}.f16	$Sd, #0 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCMPZS (2247) - ARM_INS_VCMP - vcmp${p}.f32	$Sd, #0 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCNTd (2248) - ARM_INS_VCNT - vcnt${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCNTq (2249) - ARM_INS_VCNT - vcnt${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTANSDf (2250) - ARM_INS_VCVTA - vcvta.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANSDh (2251) - ARM_INS_VCVTA - vcvta.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANSQf (2252) - ARM_INS_VCVTA - vcvta.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANSQh (2253) - ARM_INS_VCVTA - vcvta.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANUDf (2254) - ARM_INS_VCVTA - vcvta.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANUDh (2255) - ARM_INS_VCVTA - vcvta.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANUQf (2256) - ARM_INS_VCVTA - vcvta.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTANUQh (2257) - ARM_INS_VCVTA - vcvta.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTASD (2258) - ARM_INS_VCVTA - vcvta.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTASH (2259) - ARM_INS_VCVTA - vcvta.s32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTASS (2260) - ARM_INS_VCVTA - vcvta.s32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTAUD (2261) - ARM_INS_VCVTA - vcvta.u32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTAUH (2262) - ARM_INS_VCVTA - vcvta.u32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTAUS (2263) - ARM_INS_VCVTA - vcvta.u32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTBDH (2264) - ARM_INS_VCVTB - vcvtb${p}.f16.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTBHD (2265) - ARM_INS_VCVTB - vcvtb${p}.f64.f16	$Dd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTBHS (2266) - ARM_INS_VCVTB - vcvtb${p}.f32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTBSH (2267) - ARM_INS_VCVTB - vcvtb${p}.f16.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTDS (2268) - ARM_INS_VCVT - vcvt${p}.f64.f32	$Dd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNSDf (2269) - ARM_INS_VCVTM - vcvtm.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNSDh (2270) - ARM_INS_VCVTM - vcvtm.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNSQf (2271) - ARM_INS_VCVTM - vcvtm.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNSQh (2272) - ARM_INS_VCVTM - vcvtm.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNUDf (2273) - ARM_INS_VCVTM - vcvtm.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNUDh (2274) - ARM_INS_VCVTM - vcvtm.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNUQf (2275) - ARM_INS_VCVTM - vcvtm.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMNUQh (2276) - ARM_INS_VCVTM - vcvtm.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTMSD (2277) - ARM_INS_VCVTM - vcvtm.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTMSH (2278) - ARM_INS_VCVTM - vcvtm.s32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTMSS (2279) - ARM_INS_VCVTM - vcvtm.s32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTMUD (2280) - ARM_INS_VCVTM - vcvtm.u32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTMUH (2281) - ARM_INS_VCVTM - vcvtm.u32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTMUS (2282) - ARM_INS_VCVTM - vcvtm.u32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNSDf (2283) - ARM_INS_VCVTN - vcvtn.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNSDh (2284) - ARM_INS_VCVTN - vcvtn.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNSQf (2285) - ARM_INS_VCVTN - vcvtn.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNSQh (2286) - ARM_INS_VCVTN - vcvtn.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNUDf (2287) - ARM_INS_VCVTN - vcvtn.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNUDh (2288) - ARM_INS_VCVTN - vcvtn.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNUQf (2289) - ARM_INS_VCVTN - vcvtn.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNNUQh (2290) - ARM_INS_VCVTN - vcvtn.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTNSD (2291) - ARM_INS_VCVTN - vcvtn.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTNSH (2292) - ARM_INS_VCVTN - vcvtn.s32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTNSS (2293) - ARM_INS_VCVTN - vcvtn.s32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTNUD (2294) - ARM_INS_VCVTN - vcvtn.u32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTNUH (2295) - ARM_INS_VCVTN - vcvtn.u32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTNUS (2296) - ARM_INS_VCVTN - vcvtn.u32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNSDf (2297) - ARM_INS_VCVTP - vcvtp.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNSDh (2298) - ARM_INS_VCVTP - vcvtp.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNSQf (2299) - ARM_INS_VCVTP - vcvtp.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNSQh (2300) - ARM_INS_VCVTP - vcvtp.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNUDf (2301) - ARM_INS_VCVTP - vcvtp.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNUDh (2302) - ARM_INS_VCVTP - vcvtp.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNUQf (2303) - ARM_INS_VCVTP - vcvtp.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPNUQh (2304) - ARM_INS_VCVTP - vcvtp.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VCVTPSD (2305) - ARM_INS_VCVTP - vcvtp.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTPSH (2306) - ARM_INS_VCVTP - vcvtp.s32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTPSS (2307) - ARM_INS_VCVTP - vcvtp.s32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTPUD (2308) - ARM_INS_VCVTP - vcvtp.u32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VCVTPUH (2309) - ARM_INS_VCVTP - vcvtp.u32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTPUS (2310) - ARM_INS_VCVTP - vcvtp.u32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VCVTSD (2311) - ARM_INS_VCVT - vcvt${p}.f32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTTDH (2312) - ARM_INS_VCVTT - vcvtt${p}.f16.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTTHD (2313) - ARM_INS_VCVTT - vcvtt${p}.f64.f16	$Dd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTTHS (2314) - ARM_INS_VCVTT - vcvtt${p}.f32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTTSH (2315) - ARM_INS_VCVTT - vcvtt${p}.f16.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2h (2316) - ARM_INS_VCVT - vcvt${p}.f16.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2sd (2317) - ARM_INS_VCVT - vcvt${p}.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2sq (2318) - ARM_INS_VCVT - vcvt${p}.s32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2ud (2319) - ARM_INS_VCVT - vcvt${p}.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2uq (2320) - ARM_INS_VCVT - vcvt${p}.u32.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2xsd (2321) - ARM_INS_VCVT - vcvt${p}.s32.f32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2xsq (2322) - ARM_INS_VCVT - vcvt${p}.s32.f32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2xud (2323) - ARM_INS_VCVT - vcvt${p}.u32.f32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTf2xuq (2324) - ARM_INS_VCVT - vcvt${p}.u32.f32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2f (2325) - ARM_INS_VCVT - vcvt${p}.f32.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2sd (2326) - ARM_INS_VCVT - vcvt${p}.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2sq (2327) - ARM_INS_VCVT - vcvt${p}.s16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2ud (2328) - ARM_INS_VCVT - vcvt${p}.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2uq (2329) - ARM_INS_VCVT - vcvt${p}.u16.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2xsd (2330) - ARM_INS_VCVT - vcvt${p}.s16.f16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2xsq (2331) - ARM_INS_VCVT - vcvt${p}.s16.f16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2xud (2332) - ARM_INS_VCVT - vcvt${p}.u16.f16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTh2xuq (2333) - ARM_INS_VCVT - vcvt${p}.u16.f16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTs2fd (2334) - ARM_INS_VCVT - vcvt${p}.f32.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTs2fq (2335) - ARM_INS_VCVT - vcvt${p}.f32.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTs2hd (2336) - ARM_INS_VCVT - vcvt${p}.f16.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTs2hq (2337) - ARM_INS_VCVT - vcvt${p}.f16.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTu2fd (2338) - ARM_INS_VCVT - vcvt${p}.f32.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTu2fq (2339) - ARM_INS_VCVT - vcvt${p}.f32.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTu2hd (2340) - ARM_INS_VCVT - vcvt${p}.f16.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTu2hq (2341) - ARM_INS_VCVT - vcvt${p}.f16.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxs2fd (2342) - ARM_INS_VCVT - vcvt${p}.f32.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxs2fq (2343) - ARM_INS_VCVT - vcvt${p}.f32.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxs2hd (2344) - ARM_INS_VCVT - vcvt${p}.f16.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxs2hq (2345) - ARM_INS_VCVT - vcvt${p}.f16.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxu2fd (2346) - ARM_INS_VCVT - vcvt${p}.f32.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxu2fq (2347) - ARM_INS_VCVT - vcvt${p}.f32.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxu2hd (2348) - ARM_INS_VCVT - vcvt${p}.f16.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VCVTxu2hq (2349) - ARM_INS_VCVT - vcvt${p}.f16.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDIVD (2350) - ARM_INS_VDIV - vdiv${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDIVH (2351) - ARM_INS_VDIV - vdiv${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDIVS (2352) - ARM_INS_VDIV - vdiv${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUP16d (2353) - ARM_INS_VDUP - vdup${p}.16	$V, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUP16q (2354) - ARM_INS_VDUP - vdup${p}.16	$V, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUP32d (2355) - ARM_INS_VDUP - vdup${p}.32	$V, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUP32q (2356) - ARM_INS_VDUP - vdup${p}.32	$V, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUP8d (2357) - ARM_INS_VDUP - vdup${p}.8	$V, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUP8q (2358) - ARM_INS_VDUP - vdup${p}.8	$V, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUPLN16d (2359) - ARM_INS_VDUP - vdup${p}.16	$Vd, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUPLN16q (2360) - ARM_INS_VDUP - vdup${p}.16	$Vd, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUPLN32d (2361) - ARM_INS_VDUP - vdup${p}.32	$Vd, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUPLN32q (2362) - ARM_INS_VDUP - vdup${p}.32	$Vd, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUPLN8d (2363) - ARM_INS_VDUP - vdup${p}.8	$Vd, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VDUPLN8q (2364) - ARM_INS_VDUP - vdup${p}.8	$Vd, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEORd (2365) - ARM_INS_VEOR - veor${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEORq (2366) - ARM_INS_VEOR - veor${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTd16 (2367) - ARM_INS_VEXT - vext${p}.16	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTd32 (2368) - ARM_INS_VEXT - vext${p}.32	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTd8 (2369) - ARM_INS_VEXT - vext${p}.8	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTq16 (2370) - ARM_INS_VEXT - vext${p}.16	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTq32 (2371) - ARM_INS_VEXT - vext${p}.32	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTq64 (2372) - ARM_INS_VEXT - vext${p}.64	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VEXTq8 (2373) - ARM_INS_VEXT - vext${p}.8	$Vd, $Vn, $Vm, $index */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* index */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAD (2374) - ARM_INS_VFMA - vfma${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAH (2375) - ARM_INS_VFMA - vfma${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMALD (2376) - ARM_INS_VFMAL - vfmal.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VFMALDI (2377) - ARM_INS_VFMAL - vfmal.f16	$Vd, $Vn, $Vm$idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMALQ (2378) - ARM_INS_VFMAL - vfmal.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VFMALQI (2379) - ARM_INS_VFMAL - vfmal.f16	$Vd, $Vn, $Vm$idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAS (2380) - ARM_INS_VFMA - vfma${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAfd (2381) - ARM_INS_VFMA - vfma${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAfq (2382) - ARM_INS_VFMA - vfma${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAhd (2383) - ARM_INS_VFMA - vfma${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMAhq (2384) - ARM_INS_VFMA - vfma${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSD (2385) - ARM_INS_VFMS - vfms${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSH (2386) - ARM_INS_VFMS - vfms${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSLD (2387) - ARM_INS_VFMSL - vfmsl.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VFMSLDI (2388) - ARM_INS_VFMSL - vfmsl.f16	$Vd, $Vn, $Vm$idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSLQ (2389) - ARM_INS_VFMSL - vfmsl.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VFMSLQI (2390) - ARM_INS_VFMSL - vfmsl.f16	$Vd, $Vn, $Vm$idx */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* idx - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSS (2391) - ARM_INS_VFMS - vfms${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSfd (2392) - ARM_INS_VFMS - vfms${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMSfq (2393) - ARM_INS_VFMS - vfms${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMShd (2394) - ARM_INS_VFMS - vfms${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFMShq (2395) - ARM_INS_VFMS - vfms${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFNMAD (2396) - ARM_INS_VFNMA - vfnma${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFNMAH (2397) - ARM_INS_VFNMA - vfnma${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFNMAS (2398) - ARM_INS_VFNMA - vfnma${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFNMSD (2399) - ARM_INS_VFNMS - vfnms${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFNMSH (2400) - ARM_INS_VFNMS - vfnms${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFNMSS (2401) - ARM_INS_VFNMS - vfnms${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VFP_VMAXNMD (2402) - ARM_INS_VMAXNM - vmaxnm.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VFP_VMAXNMH (2403) - ARM_INS_VMAXNM - vmaxnm.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VFP_VMAXNMS (2404) - ARM_INS_VMAXNM - vmaxnm.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VFP_VMINNMD (2405) - ARM_INS_VMINNM - vminnm.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VFP_VMINNMH (2406) - ARM_INS_VMINNM - vminnm.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VFP_VMINNMS (2407) - ARM_INS_VMINNM - vminnm.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VGETLNi32 (2408) - ARM_INS_VMOV - vmov${p}.32	$R, $V$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VGETLNs16 (2409) - ARM_INS_VMOV - vmov${p}.s16	$R, $V$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VGETLNs8 (2410) - ARM_INS_VMOV - vmov${p}.s8	$R, $V$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VGETLNu16 (2411) - ARM_INS_VMOV - vmov${p}.u16	$R, $V$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VGETLNu8 (2412) - ARM_INS_VMOV - vmov${p}.u8	$R, $V$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDsv16i8 (2413) - ARM_INS_VHADD - vhadd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDsv2i32 (2414) - ARM_INS_VHADD - vhadd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDsv4i16 (2415) - ARM_INS_VHADD - vhadd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDsv4i32 (2416) - ARM_INS_VHADD - vhadd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDsv8i16 (2417) - ARM_INS_VHADD - vhadd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDsv8i8 (2418) - ARM_INS_VHADD - vhadd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDuv16i8 (2419) - ARM_INS_VHADD - vhadd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDuv2i32 (2420) - ARM_INS_VHADD - vhadd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDuv4i16 (2421) - ARM_INS_VHADD - vhadd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDuv4i32 (2422) - ARM_INS_VHADD - vhadd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDuv8i16 (2423) - ARM_INS_VHADD - vhadd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHADDuv8i8 (2424) - ARM_INS_VHADD - vhadd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBsv16i8 (2425) - ARM_INS_VHSUB - vhsub${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBsv2i32 (2426) - ARM_INS_VHSUB - vhsub${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBsv4i16 (2427) - ARM_INS_VHSUB - vhsub${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBsv4i32 (2428) - ARM_INS_VHSUB - vhsub${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBsv8i16 (2429) - ARM_INS_VHSUB - vhsub${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBsv8i8 (2430) - ARM_INS_VHSUB - vhsub${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBuv16i8 (2431) - ARM_INS_VHSUB - vhsub${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBuv2i32 (2432) - ARM_INS_VHSUB - vhsub${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBuv4i16 (2433) - ARM_INS_VHSUB - vhsub${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBuv4i32 (2434) - ARM_INS_VHSUB - vhsub${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBuv8i16 (2435) - ARM_INS_VHSUB - vhsub${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VHSUBuv8i8 (2436) - ARM_INS_VHSUB - vhsub${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VINSH (2437) - ARM_INS_VINS - vins.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sda */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VJCVT (2438) - ARM_INS_VJCVT - vjcvt${p}.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd16 (2439) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd16wb_fixed (2440) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd16wb_register (2441) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd32 (2442) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd32wb_fixed (2443) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd32wb_register (2444) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd8 (2445) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd8wb_fixed (2446) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPd8wb_register (2447) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq16 (2448) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq16wb_fixed (2449) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq16wb_register (2450) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq32 (2451) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq32wb_fixed (2452) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq32wb_register (2453) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq8 (2454) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq8wb_fixed (2455) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1DUPq8wb_register (2456) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNd16 (2457) - ARM_INS_VLD1 - vld1${p}.16	\{$Vd[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNd16_UPD (2458) - ARM_INS_VLD1 - vld1${p}.16	\{$Vd[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNd32 (2459) - ARM_INS_VLD1 - vld1${p}.32	\{$Vd[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNd32_UPD (2460) - ARM_INS_VLD1 - vld1${p}.32	\{$Vd[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNd8 (2461) - ARM_INS_VLD1 - vld1${p}.8	\{$Vd[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1LNd8_UPD (2462) - ARM_INS_VLD1 - vld1${p}.8	\{$Vd[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1LNq16Pseudo (2463) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1LNq16Pseudo_UPD (2464) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1LNq32Pseudo (2465) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1LNq32Pseudo_UPD (2466) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1LNq8Pseudo (2467) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1LNq8Pseudo_UPD (2468) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d16 (2469) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d16Q (2470) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d16QPseudo (2471) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d16QPseudoWB_fixed (2472) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d16QPseudoWB_register (2473) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d16Qwb_fixed (2474) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d16Qwb_register (2475) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d16T (2476) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d16TPseudo (2477) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d16TPseudoWB_fixed (2478) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d16TPseudoWB_register (2479) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d16Twb_fixed (2480) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d16Twb_register (2481) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d16wb_fixed (2482) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d16wb_register (2483) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32 (2484) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32Q (2485) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d32QPseudo (2486) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d32QPseudoWB_fixed (2487) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d32QPseudoWB_register (2488) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d32Qwb_fixed (2489) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32Qwb_register (2490) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32T (2491) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d32TPseudo (2492) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d32TPseudoWB_fixed (2493) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d32TPseudoWB_register (2494) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d32Twb_fixed (2495) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32Twb_register (2496) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32wb_fixed (2497) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d32wb_register (2498) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64 (2499) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64Q (2500) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d64QPseudo (2501) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d64QPseudoWB_fixed (2502) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d64QPseudoWB_register (2503) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d64Qwb_fixed (2504) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64Qwb_register (2505) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64T (2506) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d64TPseudo (2507) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d64TPseudoWB_fixed (2508) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d64TPseudoWB_register (2509) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d64Twb_fixed (2510) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64Twb_register (2511) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64wb_fixed (2512) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d64wb_register (2513) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8 (2514) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8Q (2515) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d8QPseudo (2516) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d8QPseudoWB_fixed (2517) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d8QPseudoWB_register (2518) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d8Qwb_fixed (2519) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8Qwb_register (2520) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8T (2521) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1d8TPseudo (2522) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d8TPseudoWB_fixed (2523) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1d8TPseudoWB_register (2524) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1d8Twb_fixed (2525) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8Twb_register (2526) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8wb_fixed (2527) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1d8wb_register (2528) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q16 (2529) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1q16HighQPseudo (2530) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q16HighQPseudo_UPD (2531) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q16HighTPseudo (2532) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q16HighTPseudo_UPD (2533) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q16LowQPseudo_UPD (2534) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q16LowTPseudo_UPD (2535) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1q16wb_fixed (2536) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q16wb_register (2537) - ARM_INS_VLD1 - vld1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q32 (2538) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1q32HighQPseudo (2539) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q32HighQPseudo_UPD (2540) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q32HighTPseudo (2541) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q32HighTPseudo_UPD (2542) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q32LowQPseudo_UPD (2543) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q32LowTPseudo_UPD (2544) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1q32wb_fixed (2545) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q32wb_register (2546) - ARM_INS_VLD1 - vld1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q64 (2547) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1q64HighQPseudo (2548) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q64HighQPseudo_UPD (2549) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q64HighTPseudo (2550) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q64HighTPseudo_UPD (2551) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q64LowQPseudo_UPD (2552) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q64LowTPseudo_UPD (2553) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1q64wb_fixed (2554) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q64wb_register (2555) - ARM_INS_VLD1 - vld1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q8 (2556) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD1q8HighQPseudo (2557) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q8HighQPseudo_UPD (2558) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q8HighTPseudo (2559) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q8HighTPseudo_UPD (2560) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q8LowQPseudo_UPD (2561) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD1q8LowTPseudo_UPD (2562) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD1q8wb_fixed (2563) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD1q8wb_register (2564) - ARM_INS_VLD1 - vld1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd16 (2565) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd16wb_fixed (2566) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd16wb_register (2567) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd16x2 (2568) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd16x2wb_fixed (2569) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd16x2wb_register (2570) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd32 (2571) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd32wb_fixed (2572) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd32wb_register (2573) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd32x2 (2574) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd32x2wb_fixed (2575) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd32x2wb_register (2576) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd8 (2577) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd8wb_fixed (2578) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd8wb_register (2579) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd8x2 (2580) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd8x2wb_fixed (2581) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2DUPd8x2wb_register (2582) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v2i64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2DUPq16EvenPseudo (2583) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq16OddPseudo (2584) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq16OddPseudoWB_fixed (2585) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq16OddPseudoWB_register (2586) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq32EvenPseudo (2587) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq32OddPseudo (2588) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq32OddPseudoWB_fixed (2589) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq32OddPseudoWB_register (2590) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq8EvenPseudo (2591) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq8OddPseudo (2592) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq8OddPseudoWB_fixed (2593) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2DUPq8OddPseudoWB_register (2594) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2LNd16 (2595) - ARM_INS_VLD2 - vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2LNd16Pseudo (2596) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2LNd16Pseudo_UPD (2597) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2LNd16_UPD (2598) - ARM_INS_VLD2 - vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNd32 (2599) - ARM_INS_VLD2 - vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2LNd32Pseudo (2600) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2LNd32Pseudo_UPD (2601) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2LNd32_UPD (2602) - ARM_INS_VLD2 - vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNd8 (2603) - ARM_INS_VLD2 - vld2${p}.8	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2LNd8Pseudo (2604) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2LNd8Pseudo_UPD (2605) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2LNd8_UPD (2606) - ARM_INS_VLD2 - vld2${p}.8	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNq16 (2607) - ARM_INS_VLD2 - vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2LNq16Pseudo (2608) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2LNq16Pseudo_UPD (2609) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2LNq16_UPD (2610) - ARM_INS_VLD2 - vld2${p}.16	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2LNq32 (2611) - ARM_INS_VLD2 - vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2LNq32Pseudo (2612) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2LNq32Pseudo_UPD (2613) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2LNq32_UPD (2614) - ARM_INS_VLD2 - vld2${p}.32	\{$Vd[$lane], $dst2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b16 (2615) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b16wb_fixed (2616) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b16wb_register (2617) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b32 (2618) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b32wb_fixed (2619) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b32wb_register (2620) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b8 (2621) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b8wb_fixed (2622) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2b8wb_register (2623) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d16 (2624) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d16wb_fixed (2625) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d16wb_register (2626) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d32 (2627) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d32wb_fixed (2628) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d32wb_register (2629) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d8 (2630) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d8wb_fixed (2631) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2d8wb_register (2632) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2q16 (2633) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2q16Pseudo (2634) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2q16PseudoWB_fixed (2635) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2q16PseudoWB_register (2636) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2q16wb_fixed (2637) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2q16wb_register (2638) - ARM_INS_VLD2 - vld2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2q32 (2639) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2q32Pseudo (2640) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2q32PseudoWB_fixed (2641) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2q32PseudoWB_register (2642) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2q32wb_fixed (2643) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2q32wb_register (2644) - ARM_INS_VLD2 - vld2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2q8 (2645) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD2q8Pseudo (2646) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2q8PseudoWB_fixed (2647) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD2q8PseudoWB_register (2648) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD2q8wb_fixed (2649) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD2q8wb_register (2650) - ARM_INS_VLD2 - vld2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPd16 (2651) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3DUPd16Pseudo (2652) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPd16Pseudo_UPD (2653) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3DUPd16_UPD (2654) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPd32 (2655) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3DUPd32Pseudo (2656) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPd32Pseudo_UPD (2657) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3DUPd32_UPD (2658) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPd8 (2659) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3DUPd8Pseudo (2660) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPd8Pseudo_UPD (2661) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3DUPd8_UPD (2662) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPq16 (2663) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3DUPq16EvenPseudo (2664) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPq16OddPseudo (2665) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPq16OddPseudo_UPD (2666) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3DUPq16_UPD (2667) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPq32 (2668) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3DUPq32EvenPseudo (2669) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPq32OddPseudo (2670) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPq32OddPseudo_UPD (2671) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3DUPq32_UPD (2672) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3DUPq8 (2673) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3DUPq8EvenPseudo (2674) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPq8OddPseudo (2675) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3DUPq8OddPseudo_UPD (2676) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3DUPq8_UPD (2677) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd[], $dst2[], $dst3[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNd16 (2678) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3LNd16Pseudo (2679) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3LNd16Pseudo_UPD (2680) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3LNd16_UPD (2681) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNd32 (2682) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3LNd32Pseudo (2683) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3LNd32Pseudo_UPD (2684) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3LNd32_UPD (2685) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNd8 (2686) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3LNd8Pseudo (2687) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3LNd8Pseudo_UPD (2688) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3LNd8_UPD (2689) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNq16 (2690) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3LNq16Pseudo (2691) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3LNq16Pseudo_UPD (2692) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3LNq16_UPD (2693) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3LNq32 (2694) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3LNq32Pseudo (2695) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3LNq32Pseudo_UPD (2696) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3LNq32_UPD (2697) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3d16 (2698) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3d16Pseudo (2699) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3d16Pseudo_UPD (2700) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3d16_UPD (2701) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3d32 (2702) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3d32Pseudo (2703) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3d32Pseudo_UPD (2704) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3d32_UPD (2705) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3d8 (2706) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3d8Pseudo (2707) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3d8Pseudo_UPD (2708) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3d8_UPD (2709) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD3q16 (2710) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3q16Pseudo_UPD (2711) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3q16_UPD (2712) - ARM_INS_VLD3 - vld3${p}.16	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3q16oddPseudo (2713) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3q16oddPseudo_UPD (2714) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3q32 (2715) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3q32Pseudo_UPD (2716) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3q32_UPD (2717) - ARM_INS_VLD3 - vld3${p}.32	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3q32oddPseudo (2718) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3q32oddPseudo_UPD (2719) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3q8 (2720) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3q8Pseudo_UPD (2721) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD3q8_UPD (2722) - ARM_INS_VLD3 - vld3${p}.8	\{$Vd, $dst2, $dst3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD3q8oddPseudo (2723) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD3q8oddPseudo_UPD (2724) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPd16 (2725) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4DUPd16Pseudo (2726) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPd16Pseudo_UPD (2727) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPd16_UPD (2728) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPd32 (2729) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4DUPd32Pseudo (2730) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPd32Pseudo_UPD (2731) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPd32_UPD (2732) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPd8 (2733) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4DUPd8Pseudo (2734) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPd8Pseudo_UPD (2735) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPd8_UPD (2736) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPq16 (2737) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4DUPq16EvenPseudo (2738) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPq16OddPseudo (2739) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPq16OddPseudo_UPD (2740) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPq16_UPD (2741) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPq32 (2742) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4DUPq32EvenPseudo (2743) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPq32OddPseudo (2744) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPq32OddPseudo_UPD (2745) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPq32_UPD (2746) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4DUPq8 (2747) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4DUPq8EvenPseudo (2748) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPq8OddPseudo (2749) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4DUPq8OddPseudo_UPD (2750) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4DUPq8_UPD (2751) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd[], $dst2[], $dst3[], $dst4[]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNd16 (2752) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4LNd16Pseudo (2753) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4LNd16Pseudo_UPD (2754) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4LNd16_UPD (2755) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNd32 (2756) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4LNd32Pseudo (2757) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4LNd32Pseudo_UPD (2758) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4LNd32_UPD (2759) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNd8 (2760) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4LNd8Pseudo (2761) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4LNd8Pseudo_UPD (2762) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4LNd8_UPD (2763) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNq16 (2764) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4LNq16Pseudo (2765) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4LNq16Pseudo_UPD (2766) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4LNq16_UPD (2767) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4LNq32 (2768) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4LNq32Pseudo (2769) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4LNq32Pseudo_UPD (2770) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4LNq32_UPD (2771) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4d16 (2772) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4d16Pseudo (2773) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4d16Pseudo_UPD (2774) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4d16_UPD (2775) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4d32 (2776) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4d32Pseudo (2777) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4d32Pseudo_UPD (2778) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4d32_UPD (2779) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4d8 (2780) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4d8Pseudo (2781) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4d8Pseudo_UPD (2782) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4d8_UPD (2783) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLD4q16 (2784) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4q16Pseudo_UPD (2785) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4q16_UPD (2786) - ARM_INS_VLD4 - vld4${p}.16	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4q16oddPseudo (2787) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4q16oddPseudo_UPD (2788) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4q32 (2789) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4q32Pseudo_UPD (2790) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4q32_UPD (2791) - ARM_INS_VLD4 - vld4${p}.32	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4q32oddPseudo (2792) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4q32oddPseudo_UPD (2793) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4q8 (2794) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4q8Pseudo_UPD (2795) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLD4q8_UPD (2796) - ARM_INS_VLD4 - vld4${p}.8	\{$Vd, $dst2, $dst3, $dst4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst3 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst4 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VLD4q8oddPseudo (2797) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VLD4q8oddPseudo_UPD (2798) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLDMDDB_UPD (2799) - ARM_INS_VLDMDB - vldmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VLDMDIA (2800) - ARM_INS_VLDMIA - vldmia${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VLDMDIA_UPD (2801) - ARM_INS_VLDMIA - vldmia${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{{{ /* ARM_VLDMQIA (2802) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VLDMSDB_UPD (2803) - ARM_INS_VLDMDB - vldmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VLDMSIA (2804) - ARM_INS_VLDMIA - vldmia${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VLDMSIA_UPD (2805) - ARM_INS_VLDMIA - vldmia${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VLDRD (2806) - ARM_INS_VLDR - vldr${p}	$Dd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDRH (2807) - ARM_INS_VLDR - vldr${p}.16	$Sd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDRS (2808) - ARM_INS_VLDR - vldr${p}	$Sd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPCXTNS_off (2809) - ARM_INS_VLDR - vldr${p}	fpcxtns, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPCXTNS_post (2810) - ARM_INS_VLDR - vldr${p}	fpcxtns, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPCXTNS_pre (2811) - ARM_INS_VLDR - vldr${p}	fpcxtns, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPCXTS_off (2812) - ARM_INS_VLDR - vldr${p}	fpcxts, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPCXTS_post (2813) - ARM_INS_VLDR - vldr${p}	fpcxts, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPCXTS_pre (2814) - ARM_INS_VLDR - vldr${p}	fpcxts, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPSCR_NZCVQC_off (2815) - ARM_INS_VLDR - vldr${p}	fpscr_nzcvqc, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPSCR_NZCVQC_post (2816) - ARM_INS_VLDR - vldr${p}	fpscr_nzcvqc, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPSCR_NZCVQC_pre (2817) - ARM_INS_VLDR - vldr${p}	fpscr_nzcvqc, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPSCR_off (2818) - ARM_INS_VLDR - vldr${p}	fpscr, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPSCR_post (2819) - ARM_INS_VLDR - vldr${p}	fpscr, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_FPSCR_pre (2820) - ARM_INS_VLDR - vldr${p}	fpscr, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_P0_off (2821) - ARM_INS_VLDR - vldr${p}	p0, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_P0_post (2822) - ARM_INS_VLDR - vldr${p}	p0, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_P0_pre (2823) - ARM_INS_VLDR - vldr${p}	p0, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_VPR_off (2824) - ARM_INS_VLDR - vldr${p}	vpr, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_VPR_post (2825) - ARM_INS_VLDR - vldr${p}	vpr, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLDR_VPR_pre (2826) - ARM_INS_VLDR - vldr${p}	vpr, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLLDM (2827) - ARM_INS_VLLDM - vlldm${p}	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VLSTM (2828) - ARM_INS_VLSTM - vlstm${p}	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXfd (2829) - ARM_INS_VMAX - vmax${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXfq (2830) - ARM_INS_VMAX - vmax${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXhd (2831) - ARM_INS_VMAX - vmax${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXhq (2832) - ARM_INS_VMAX - vmax${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXsv16i8 (2833) - ARM_INS_VMAX - vmax${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXsv2i32 (2834) - ARM_INS_VMAX - vmax${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXsv4i16 (2835) - ARM_INS_VMAX - vmax${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXsv4i32 (2836) - ARM_INS_VMAX - vmax${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXsv8i16 (2837) - ARM_INS_VMAX - vmax${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXsv8i8 (2838) - ARM_INS_VMAX - vmax${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXuv16i8 (2839) - ARM_INS_VMAX - vmax${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXuv2i32 (2840) - ARM_INS_VMAX - vmax${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXuv4i16 (2841) - ARM_INS_VMAX - vmax${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXuv4i32 (2842) - ARM_INS_VMAX - vmax${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXuv8i16 (2843) - ARM_INS_VMAX - vmax${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMAXuv8i8 (2844) - ARM_INS_VMAX - vmax${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINfd (2845) - ARM_INS_VMIN - vmin${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINfq (2846) - ARM_INS_VMIN - vmin${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINhd (2847) - ARM_INS_VMIN - vmin${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINhq (2848) - ARM_INS_VMIN - vmin${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINsv16i8 (2849) - ARM_INS_VMIN - vmin${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINsv2i32 (2850) - ARM_INS_VMIN - vmin${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINsv4i16 (2851) - ARM_INS_VMIN - vmin${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINsv4i32 (2852) - ARM_INS_VMIN - vmin${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINsv8i16 (2853) - ARM_INS_VMIN - vmin${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINsv8i8 (2854) - ARM_INS_VMIN - vmin${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINuv16i8 (2855) - ARM_INS_VMIN - vmin${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINuv2i32 (2856) - ARM_INS_VMIN - vmin${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINuv4i16 (2857) - ARM_INS_VMIN - vmin${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINuv4i32 (2858) - ARM_INS_VMIN - vmin${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINuv8i16 (2859) - ARM_INS_VMIN - vmin${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMINuv8i8 (2860) - ARM_INS_VMIN - vmin${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAD (2861) - ARM_INS_VMLA - vmla${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAH (2862) - ARM_INS_VMLA - vmla${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALslsv2i32 (2863) - ARM_INS_VMLAL - vmlal${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALslsv4i16 (2864) - ARM_INS_VMLAL - vmlal${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALsluv2i32 (2865) - ARM_INS_VMLAL - vmlal${p}.u32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALsluv4i16 (2866) - ARM_INS_VMLAL - vmlal${p}.u16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALsv2i64 (2867) - ARM_INS_VMLAL - vmlal${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALsv4i32 (2868) - ARM_INS_VMLAL - vmlal${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALsv8i16 (2869) - ARM_INS_VMLAL - vmlal${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALuv2i64 (2870) - ARM_INS_VMLAL - vmlal${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALuv4i32 (2871) - ARM_INS_VMLAL - vmlal${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLALuv8i16 (2872) - ARM_INS_VMLAL - vmlal${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAS (2873) - ARM_INS_VMLA - vmla${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAfd (2874) - ARM_INS_VMLA - vmla${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAfq (2875) - ARM_INS_VMLA - vmla${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAhd (2876) - ARM_INS_VMLA - vmla${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAhq (2877) - ARM_INS_VMLA - vmla${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslfd (2878) - ARM_INS_VMLA - vmla${p}.f32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslfq (2879) - ARM_INS_VMLA - vmla${p}.f32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslhd (2880) - ARM_INS_VMLA - vmla${p}.f16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslhq (2881) - ARM_INS_VMLA - vmla${p}.f16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslv2i32 (2882) - ARM_INS_VMLA - vmla${p}.i32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslv4i16 (2883) - ARM_INS_VMLA - vmla${p}.i16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslv4i32 (2884) - ARM_INS_VMLA - vmla${p}.i32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAslv8i16 (2885) - ARM_INS_VMLA - vmla${p}.i16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAv16i8 (2886) - ARM_INS_VMLA - vmla${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAv2i32 (2887) - ARM_INS_VMLA - vmla${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAv4i16 (2888) - ARM_INS_VMLA - vmla${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAv4i32 (2889) - ARM_INS_VMLA - vmla${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAv8i16 (2890) - ARM_INS_VMLA - vmla${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLAv8i8 (2891) - ARM_INS_VMLA - vmla${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSD (2892) - ARM_INS_VMLS - vmls${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSH (2893) - ARM_INS_VMLS - vmls${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLslsv2i32 (2894) - ARM_INS_VMLSL - vmlsl${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLslsv4i16 (2895) - ARM_INS_VMLSL - vmlsl${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLsluv2i32 (2896) - ARM_INS_VMLSL - vmlsl${p}.u32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLsluv4i16 (2897) - ARM_INS_VMLSL - vmlsl${p}.u16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLsv2i64 (2898) - ARM_INS_VMLSL - vmlsl${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLsv4i32 (2899) - ARM_INS_VMLSL - vmlsl${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLsv8i16 (2900) - ARM_INS_VMLSL - vmlsl${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLuv2i64 (2901) - ARM_INS_VMLSL - vmlsl${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLuv4i32 (2902) - ARM_INS_VMLSL - vmlsl${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSLuv8i16 (2903) - ARM_INS_VMLSL - vmlsl${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSS (2904) - ARM_INS_VMLS - vmls${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSfd (2905) - ARM_INS_VMLS - vmls${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSfq (2906) - ARM_INS_VMLS - vmls${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLShd (2907) - ARM_INS_VMLS - vmls${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLShq (2908) - ARM_INS_VMLS - vmls${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslfd (2909) - ARM_INS_VMLS - vmls${p}.f32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslfq (2910) - ARM_INS_VMLS - vmls${p}.f32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslhd (2911) - ARM_INS_VMLS - vmls${p}.f16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslhq (2912) - ARM_INS_VMLS - vmls${p}.f16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslv2i32 (2913) - ARM_INS_VMLS - vmls${p}.i32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslv4i16 (2914) - ARM_INS_VMLS - vmls${p}.i16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslv4i32 (2915) - ARM_INS_VMLS - vmls${p}.i32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSslv8i16 (2916) - ARM_INS_VMLS - vmls${p}.i16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSv16i8 (2917) - ARM_INS_VMLS - vmls${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSv2i32 (2918) - ARM_INS_VMLS - vmls${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSv4i16 (2919) - ARM_INS_VMLS - vmls${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSv4i32 (2920) - ARM_INS_VMLS - vmls${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSv8i16 (2921) - ARM_INS_VMLS - vmls${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMLSv8i8 (2922) - ARM_INS_VMLS - vmls${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMMLA (2923) - ARM_INS_VMMLA - vmmla.bf16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VMOVD (2924) - ARM_INS_VMOV - vmov${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVDRR (2925) - ARM_INS_VMOV - vmov${p}	$Dm, $Rt, $Rt2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVH (2926) - ARM_INS_VMOVX - vmovx.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VMOVHR (2927) - ARM_INS_VMOV - vmov${p}.f16	$Sn, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVLsv2i64 (2928) - ARM_INS_VMOVL - vmovl${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVLsv4i32 (2929) - ARM_INS_VMOVL - vmovl${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVLsv8i16 (2930) - ARM_INS_VMOVL - vmovl${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVLuv2i64 (2931) - ARM_INS_VMOVL - vmovl${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVLuv4i32 (2932) - ARM_INS_VMOVL - vmovl${p}.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVLuv8i16 (2933) - ARM_INS_VMOVL - vmovl${p}.u8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVNv2i32 (2934) - ARM_INS_VMOVN - vmovn${p}.i64	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVNv4i16 (2935) - ARM_INS_VMOVN - vmovn${p}.i32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVNv8i8 (2936) - ARM_INS_VMOVN - vmovn${p}.i16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVRH (2937) - ARM_INS_VMOV - vmov${p}.f16	$Rt, $Sn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVRRD (2938) - ARM_INS_VMOV - vmov${p}	$Rt, $Rt2, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVRRS (2939) - ARM_INS_VMOV - vmov${p}	$Rt, $Rt2, $src1, $src2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVRS (2940) - ARM_INS_VMOV - vmov${p}	$Rt, $Sn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVS (2941) - ARM_INS_VMOV - vmov${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVSR (2942) - ARM_INS_VMOV - vmov${p}	$Sn, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVSRR (2943) - ARM_INS_VMOV - vmov${p}	$dst1, $dst2, $src1, $src2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst1 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv16i8 (2944) - ARM_INS_VMOV - vmov${p}.i8	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv1i64 (2945) - ARM_INS_VMOV - vmov${p}.i64	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv2f32 (2946) - ARM_INS_VMOV - vmov${p}.f32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv2i32 (2947) - ARM_INS_VMOV - vmov${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv2i64 (2948) - ARM_INS_VMOV - vmov${p}.i64	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv4f32 (2949) - ARM_INS_VMOV - vmov${p}.f32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv4i16 (2950) - ARM_INS_VMOV - vmov${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv4i32 (2951) - ARM_INS_VMOV - vmov${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv8i16 (2952) - ARM_INS_VMOV - vmov${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMOVv8i8 (2953) - ARM_INS_VMOV - vmov${p}.i8	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS (2954) - ARM_INS_VMRS - vmrs${p}	$Rt, fpscr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPCXTNS (2955) - ARM_INS_VMRS - vmrs${p}	$Rt, fpcxtns */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPCXTS (2956) - ARM_INS_VMRS - vmrs${p}	$Rt, fpcxts */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPEXC (2957) - ARM_INS_VMRS - vmrs${p}	$Rt, fpexc */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPINST (2958) - ARM_INS_VMRS - vmrs${p}	$Rt, fpinst */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPINST2 (2959) - ARM_INS_VMRS - vmrs${p}	$Rt, fpinst2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPSCR_NZCVQC (2960) - ARM_INS_VMRS - vmrs${p}	$Rt, fpscr_nzcvqc */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fpscr_in */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_FPSID (2961) - ARM_INS_VMRS - vmrs${p}	$Rt, fpsid */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_MVFR0 (2962) - ARM_INS_VMRS - vmrs${p}	$Rt, mvfr0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_MVFR1 (2963) - ARM_INS_VMRS - vmrs${p}	$Rt, mvfr1 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_MVFR2 (2964) - ARM_INS_VMRS - vmrs${p}	$Rt, mvfr2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_P0 (2965) - ARM_INS_VMRS - vmrs${p}	$Rt, p0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* cond */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMRS_VPR (2966) - ARM_INS_VMRS - vmrs${p}	$Rt, vpr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR (2967) - ARM_INS_VMSR - vmsr${p}	fpscr, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPCXTNS (2968) - ARM_INS_VMSR - vmsr${p}	fpcxtns, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPCXTS (2969) - ARM_INS_VMSR - vmsr${p}	fpcxts, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPEXC (2970) - ARM_INS_VMSR - vmsr${p}	fpexc, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPINST (2971) - ARM_INS_VMSR - vmsr${p}	fpinst, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPINST2 (2972) - ARM_INS_VMSR - vmsr${p}	fpinst2, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPSCR_NZCVQC (2973) - ARM_INS_VMSR - vmsr${p}	fpscr_nzcvqc, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fpscr_out */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_FPSID (2974) - ARM_INS_VMSR - vmsr${p}	fpsid, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_P0 (2975) - ARM_INS_VMSR - vmsr${p}	p0, $Rt */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* cond */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMSR_VPR (2976) - ARM_INS_VMSR - vmsr${p}	vpr, $Rt */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULD (2977) - ARM_INS_VMUL - vmul${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULH (2978) - ARM_INS_VMUL - vmul${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLp64 (2979) - ARM_INS_VMULL - vmull.p64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VMULLp8 (2980) - ARM_INS_VMULL - vmull${p}.p8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLslsv2i32 (2981) - ARM_INS_VMULL - vmull${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLslsv4i16 (2982) - ARM_INS_VMULL - vmull${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLsluv2i32 (2983) - ARM_INS_VMULL - vmull${p}.u32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLsluv4i16 (2984) - ARM_INS_VMULL - vmull${p}.u16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLsv2i64 (2985) - ARM_INS_VMULL - vmull${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLsv4i32 (2986) - ARM_INS_VMULL - vmull${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLsv8i16 (2987) - ARM_INS_VMULL - vmull${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLuv2i64 (2988) - ARM_INS_VMULL - vmull${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLuv4i32 (2989) - ARM_INS_VMULL - vmull${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULLuv8i16 (2990) - ARM_INS_VMULL - vmull${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULS (2991) - ARM_INS_VMUL - vmul${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULfd (2992) - ARM_INS_VMUL - vmul${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULfq (2993) - ARM_INS_VMUL - vmul${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULhd (2994) - ARM_INS_VMUL - vmul${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULhq (2995) - ARM_INS_VMUL - vmul${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULpd (2996) - ARM_INS_VMUL - vmul${p}.p8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULpq (2997) - ARM_INS_VMUL - vmul${p}.p8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslfd (2998) - ARM_INS_VMUL - vmul${p}.f32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslfq (2999) - ARM_INS_VMUL - vmul${p}.f32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslhd (3000) - ARM_INS_VMUL - vmul${p}.f16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslhq (3001) - ARM_INS_VMUL - vmul${p}.f16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslv2i32 (3002) - ARM_INS_VMUL - vmul${p}.i32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslv4i16 (3003) - ARM_INS_VMUL - vmul${p}.i16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslv4i32 (3004) - ARM_INS_VMUL - vmul${p}.i32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULslv8i16 (3005) - ARM_INS_VMUL - vmul${p}.i16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULv16i8 (3006) - ARM_INS_VMUL - vmul${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULv2i32 (3007) - ARM_INS_VMUL - vmul${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULv4i16 (3008) - ARM_INS_VMUL - vmul${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULv4i32 (3009) - ARM_INS_VMUL - vmul${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULv8i16 (3010) - ARM_INS_VMUL - vmul${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMULv8i8 (3011) - ARM_INS_VMUL - vmul${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMVNd (3012) - ARM_INS_VMVN - vmvn${p}	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMVNq (3013) - ARM_INS_VMVN - vmvn${p}	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMVNv2i32 (3014) - ARM_INS_VMVN - vmvn${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMVNv4i16 (3015) - ARM_INS_VMVN - vmvn${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMVNv4i32 (3016) - ARM_INS_VMVN - vmvn${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VMVNv8i16 (3017) - ARM_INS_VMVN - vmvn${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGD (3018) - ARM_INS_VNEG - vneg${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGH (3019) - ARM_INS_VNEG - vneg${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGS (3020) - ARM_INS_VNEG - vneg${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGf32q (3021) - ARM_INS_VNEG - vneg${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGfd (3022) - ARM_INS_VNEG - vneg${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGhd (3023) - ARM_INS_VNEG - vneg${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGhq (3024) - ARM_INS_VNEG - vneg${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGs16d (3025) - ARM_INS_VNEG - vneg${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGs16q (3026) - ARM_INS_VNEG - vneg${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGs32d (3027) - ARM_INS_VNEG - vneg${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGs32q (3028) - ARM_INS_VNEG - vneg${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGs8d (3029) - ARM_INS_VNEG - vneg${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNEGs8q (3030) - ARM_INS_VNEG - vneg${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMLAD (3031) - ARM_INS_VNMLA - vnmla${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMLAH (3032) - ARM_INS_VNMLA - vnmla${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMLAS (3033) - ARM_INS_VNMLA - vnmla${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMLSD (3034) - ARM_INS_VNMLS - vnmls${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Ddin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMLSH (3035) - ARM_INS_VNMLS - vnmls${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMLSS (3036) - ARM_INS_VNMLS - vnmls${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sdin */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMULD (3037) - ARM_INS_VNMUL - vnmul${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMULH (3038) - ARM_INS_VNMUL - vnmul${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VNMULS (3039) - ARM_INS_VNMUL - vnmul${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORNd (3040) - ARM_INS_VORN - vorn${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORNq (3041) - ARM_INS_VORN - vorn${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORRd (3042) - ARM_INS_VORR - vorr${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORRiv2i32 (3043) - ARM_INS_VORR - vorr${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORRiv4i16 (3044) - ARM_INS_VORR - vorr${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORRiv4i32 (3045) - ARM_INS_VORR - vorr${p}.i32	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORRiv8i16 (3046) - ARM_INS_VORR - vorr${p}.i16	$Vd, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VORRq (3047) - ARM_INS_VORR - vorr${p}	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALsv16i8 (3048) - ARM_INS_VPADAL - vpadal${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALsv2i32 (3049) - ARM_INS_VPADAL - vpadal${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALsv4i16 (3050) - ARM_INS_VPADAL - vpadal${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALsv4i32 (3051) - ARM_INS_VPADAL - vpadal${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALsv8i16 (3052) - ARM_INS_VPADAL - vpadal${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALsv8i8 (3053) - ARM_INS_VPADAL - vpadal${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALuv16i8 (3054) - ARM_INS_VPADAL - vpadal${p}.u8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALuv2i32 (3055) - ARM_INS_VPADAL - vpadal${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALuv4i16 (3056) - ARM_INS_VPADAL - vpadal${p}.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALuv4i32 (3057) - ARM_INS_VPADAL - vpadal${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALuv8i16 (3058) - ARM_INS_VPADAL - vpadal${p}.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADALuv8i8 (3059) - ARM_INS_VPADAL - vpadal${p}.u8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLsv16i8 (3060) - ARM_INS_VPADDL - vpaddl${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLsv2i32 (3061) - ARM_INS_VPADDL - vpaddl${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLsv4i16 (3062) - ARM_INS_VPADDL - vpaddl${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLsv4i32 (3063) - ARM_INS_VPADDL - vpaddl${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLsv8i16 (3064) - ARM_INS_VPADDL - vpaddl${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLsv8i8 (3065) - ARM_INS_VPADDL - vpaddl${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLuv16i8 (3066) - ARM_INS_VPADDL - vpaddl${p}.u8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLuv2i32 (3067) - ARM_INS_VPADDL - vpaddl${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLuv4i16 (3068) - ARM_INS_VPADDL - vpaddl${p}.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLuv4i32 (3069) - ARM_INS_VPADDL - vpaddl${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLuv8i16 (3070) - ARM_INS_VPADDL - vpaddl${p}.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDLuv8i8 (3071) - ARM_INS_VPADDL - vpaddl${p}.u8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDf (3072) - ARM_INS_VPADD - vpadd${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDh (3073) - ARM_INS_VPADD - vpadd${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDi16 (3074) - ARM_INS_VPADD - vpadd${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDi32 (3075) - ARM_INS_VPADD - vpadd${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPADDi8 (3076) - ARM_INS_VPADD - vpadd${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXf (3077) - ARM_INS_VPMAX - vpmax${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXh (3078) - ARM_INS_VPMAX - vpmax${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXs16 (3079) - ARM_INS_VPMAX - vpmax${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXs32 (3080) - ARM_INS_VPMAX - vpmax${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXs8 (3081) - ARM_INS_VPMAX - vpmax${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXu16 (3082) - ARM_INS_VPMAX - vpmax${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXu32 (3083) - ARM_INS_VPMAX - vpmax${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMAXu8 (3084) - ARM_INS_VPMAX - vpmax${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINf (3085) - ARM_INS_VPMIN - vpmin${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINh (3086) - ARM_INS_VPMIN - vpmin${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINs16 (3087) - ARM_INS_VPMIN - vpmin${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINs32 (3088) - ARM_INS_VPMIN - vpmin${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINs8 (3089) - ARM_INS_VPMIN - vpmin${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINu16 (3090) - ARM_INS_VPMIN - vpmin${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINu32 (3091) - ARM_INS_VPMIN - vpmin${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VPMINu8 (3092) - ARM_INS_VPMIN - vpmin${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQABSv16i8 (3093) - ARM_INS_VQABS - vqabs${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQABSv2i32 (3094) - ARM_INS_VQABS - vqabs${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQABSv4i16 (3095) - ARM_INS_VQABS - vqabs${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQABSv4i32 (3096) - ARM_INS_VQABS - vqabs${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQABSv8i16 (3097) - ARM_INS_VQABS - vqabs${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQABSv8i8 (3098) - ARM_INS_VQABS - vqabs${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv16i8 (3099) - ARM_INS_VQADD - vqadd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv1i64 (3100) - ARM_INS_VQADD - vqadd${p}.s64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv2i32 (3101) - ARM_INS_VQADD - vqadd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv2i64 (3102) - ARM_INS_VQADD - vqadd${p}.s64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv4i16 (3103) - ARM_INS_VQADD - vqadd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv4i32 (3104) - ARM_INS_VQADD - vqadd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv8i16 (3105) - ARM_INS_VQADD - vqadd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDsv8i8 (3106) - ARM_INS_VQADD - vqadd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv16i8 (3107) - ARM_INS_VQADD - vqadd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv1i64 (3108) - ARM_INS_VQADD - vqadd${p}.u64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv2i32 (3109) - ARM_INS_VQADD - vqadd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv2i64 (3110) - ARM_INS_VQADD - vqadd${p}.u64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv4i16 (3111) - ARM_INS_VQADD - vqadd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv4i32 (3112) - ARM_INS_VQADD - vqadd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv8i16 (3113) - ARM_INS_VQADD - vqadd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQADDuv8i8 (3114) - ARM_INS_VQADD - vqadd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLALslv2i32 (3115) - ARM_INS_VQDMLAL - vqdmlal${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLALslv4i16 (3116) - ARM_INS_VQDMLAL - vqdmlal${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLALv2i64 (3117) - ARM_INS_VQDMLAL - vqdmlal${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLALv4i32 (3118) - ARM_INS_VQDMLAL - vqdmlal${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLSLslv2i32 (3119) - ARM_INS_VQDMLSL - vqdmlsl${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLSLslv4i16 (3120) - ARM_INS_VQDMLSL - vqdmlsl${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLSLv2i64 (3121) - ARM_INS_VQDMLSL - vqdmlsl${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMLSLv4i32 (3122) - ARM_INS_VQDMLSL - vqdmlsl${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHslv2i32 (3123) - ARM_INS_VQDMULH - vqdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHslv4i16 (3124) - ARM_INS_VQDMULH - vqdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHslv4i32 (3125) - ARM_INS_VQDMULH - vqdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHslv8i16 (3126) - ARM_INS_VQDMULH - vqdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHv2i32 (3127) - ARM_INS_VQDMULH - vqdmulh${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHv4i16 (3128) - ARM_INS_VQDMULH - vqdmulh${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHv4i32 (3129) - ARM_INS_VQDMULH - vqdmulh${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULHv8i16 (3130) - ARM_INS_VQDMULH - vqdmulh${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULLslv2i32 (3131) - ARM_INS_VQDMULL - vqdmull${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULLslv4i16 (3132) - ARM_INS_VQDMULL - vqdmull${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULLv2i64 (3133) - ARM_INS_VQDMULL - vqdmull${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQDMULLv4i32 (3134) - ARM_INS_VQDMULL - vqdmull${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNsuv2i32 (3135) - ARM_INS_VQMOVUN - vqmovun${p}.s64	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNsuv4i16 (3136) - ARM_INS_VQMOVUN - vqmovun${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNsuv8i8 (3137) - ARM_INS_VQMOVUN - vqmovun${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNsv2i32 (3138) - ARM_INS_VQMOVN - vqmovn${p}.s64	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNsv4i16 (3139) - ARM_INS_VQMOVN - vqmovn${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNsv8i8 (3140) - ARM_INS_VQMOVN - vqmovn${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNuv2i32 (3141) - ARM_INS_VQMOVN - vqmovn${p}.u64	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNuv4i16 (3142) - ARM_INS_VQMOVN - vqmovn${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQMOVNuv8i8 (3143) - ARM_INS_VQMOVN - vqmovn${p}.u16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQNEGv16i8 (3144) - ARM_INS_VQNEG - vqneg${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQNEGv2i32 (3145) - ARM_INS_VQNEG - vqneg${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQNEGv4i16 (3146) - ARM_INS_VQNEG - vqneg${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQNEGv4i32 (3147) - ARM_INS_VQNEG - vqneg${p}.s32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQNEGv8i16 (3148) - ARM_INS_VQNEG - vqneg${p}.s16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQNEGv8i8 (3149) - ARM_INS_VQNEG - vqneg${p}.s8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHslv2i32 (3150) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHslv4i16 (3151) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHslv4i32 (3152) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHslv8i16 (3153) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHv2i32 (3154) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHv4i16 (3155) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHv4i32 (3156) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLAHv8i16 (3157) - ARM_INS_VQRDMLAH - vqrdmlah${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHslv2i32 (3158) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHslv4i16 (3159) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHslv4i32 (3160) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHslv8i16 (3161) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHv2i32 (3162) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHv4i16 (3163) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHv4i32 (3164) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMLSHv8i16 (3165) - ARM_INS_VQRDMLSH - vqrdmlsh${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHslv2i32 (3166) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHslv4i16 (3167) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHslv4i32 (3168) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHslv8i16 (3169) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHv2i32 (3170) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHv4i16 (3171) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHv4i32 (3172) - ARM_INS_VQRDMULH - vqrdmulh${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRDMULHv8i16 (3173) - ARM_INS_VQRDMULH - vqrdmulh${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv16i8 (3174) - ARM_INS_VQRSHL - vqrshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv1i64 (3175) - ARM_INS_VQRSHL - vqrshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv2i32 (3176) - ARM_INS_VQRSHL - vqrshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv2i64 (3177) - ARM_INS_VQRSHL - vqrshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv4i16 (3178) - ARM_INS_VQRSHL - vqrshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv4i32 (3179) - ARM_INS_VQRSHL - vqrshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv8i16 (3180) - ARM_INS_VQRSHL - vqrshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLsv8i8 (3181) - ARM_INS_VQRSHL - vqrshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv16i8 (3182) - ARM_INS_VQRSHL - vqrshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv1i64 (3183) - ARM_INS_VQRSHL - vqrshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv2i32 (3184) - ARM_INS_VQRSHL - vqrshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv2i64 (3185) - ARM_INS_VQRSHL - vqrshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv4i16 (3186) - ARM_INS_VQRSHL - vqrshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv4i32 (3187) - ARM_INS_VQRSHL - vqrshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv8i16 (3188) - ARM_INS_VQRSHL - vqrshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHLuv8i8 (3189) - ARM_INS_VQRSHL - vqrshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRNsv2i32 (3190) - ARM_INS_VQRSHRN - vqrshrn${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRNsv4i16 (3191) - ARM_INS_VQRSHRN - vqrshrn${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRNsv8i8 (3192) - ARM_INS_VQRSHRN - vqrshrn${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRNuv2i32 (3193) - ARM_INS_VQRSHRN - vqrshrn${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRNuv4i16 (3194) - ARM_INS_VQRSHRN - vqrshrn${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRNuv8i8 (3195) - ARM_INS_VQRSHRN - vqrshrn${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRUNv2i32 (3196) - ARM_INS_VQRSHRUN - vqrshrun${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRUNv4i16 (3197) - ARM_INS_VQRSHRUN - vqrshrun${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQRSHRUNv8i8 (3198) - ARM_INS_VQRSHRUN - vqrshrun${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv16i8 (3199) - ARM_INS_VQSHL - vqshl${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv1i64 (3200) - ARM_INS_VQSHL - vqshl${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv2i32 (3201) - ARM_INS_VQSHL - vqshl${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv2i64 (3202) - ARM_INS_VQSHL - vqshl${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv4i16 (3203) - ARM_INS_VQSHL - vqshl${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv4i32 (3204) - ARM_INS_VQSHL - vqshl${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv8i16 (3205) - ARM_INS_VQSHL - vqshl${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsiv8i8 (3206) - ARM_INS_VQSHL - vqshl${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv16i8 (3207) - ARM_INS_VQSHLU - vqshlu${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv1i64 (3208) - ARM_INS_VQSHLU - vqshlu${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv2i32 (3209) - ARM_INS_VQSHLU - vqshlu${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv2i64 (3210) - ARM_INS_VQSHLU - vqshlu${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv4i16 (3211) - ARM_INS_VQSHLU - vqshlu${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv4i32 (3212) - ARM_INS_VQSHLU - vqshlu${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv8i16 (3213) - ARM_INS_VQSHLU - vqshlu${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsuv8i8 (3214) - ARM_INS_VQSHLU - vqshlu${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv16i8 (3215) - ARM_INS_VQSHL - vqshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv1i64 (3216) - ARM_INS_VQSHL - vqshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv2i32 (3217) - ARM_INS_VQSHL - vqshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv2i64 (3218) - ARM_INS_VQSHL - vqshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv4i16 (3219) - ARM_INS_VQSHL - vqshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv4i32 (3220) - ARM_INS_VQSHL - vqshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv8i16 (3221) - ARM_INS_VQSHL - vqshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLsv8i8 (3222) - ARM_INS_VQSHL - vqshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv16i8 (3223) - ARM_INS_VQSHL - vqshl${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv1i64 (3224) - ARM_INS_VQSHL - vqshl${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv2i32 (3225) - ARM_INS_VQSHL - vqshl${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv2i64 (3226) - ARM_INS_VQSHL - vqshl${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv4i16 (3227) - ARM_INS_VQSHL - vqshl${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv4i32 (3228) - ARM_INS_VQSHL - vqshl${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv8i16 (3229) - ARM_INS_VQSHL - vqshl${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuiv8i8 (3230) - ARM_INS_VQSHL - vqshl${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv16i8 (3231) - ARM_INS_VQSHL - vqshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv1i64 (3232) - ARM_INS_VQSHL - vqshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv2i32 (3233) - ARM_INS_VQSHL - vqshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv2i64 (3234) - ARM_INS_VQSHL - vqshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv4i16 (3235) - ARM_INS_VQSHL - vqshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv4i32 (3236) - ARM_INS_VQSHL - vqshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv8i16 (3237) - ARM_INS_VQSHL - vqshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHLuv8i8 (3238) - ARM_INS_VQSHL - vqshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRNsv2i32 (3239) - ARM_INS_VQSHRN - vqshrn${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRNsv4i16 (3240) - ARM_INS_VQSHRN - vqshrn${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRNsv8i8 (3241) - ARM_INS_VQSHRN - vqshrn${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRNuv2i32 (3242) - ARM_INS_VQSHRN - vqshrn${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRNuv4i16 (3243) - ARM_INS_VQSHRN - vqshrn${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRNuv8i8 (3244) - ARM_INS_VQSHRN - vqshrn${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRUNv2i32 (3245) - ARM_INS_VQSHRUN - vqshrun${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRUNv4i16 (3246) - ARM_INS_VQSHRUN - vqshrun${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSHRUNv8i8 (3247) - ARM_INS_VQSHRUN - vqshrun${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv16i8 (3248) - ARM_INS_VQSUB - vqsub${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv1i64 (3249) - ARM_INS_VQSUB - vqsub${p}.s64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv2i32 (3250) - ARM_INS_VQSUB - vqsub${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv2i64 (3251) - ARM_INS_VQSUB - vqsub${p}.s64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv4i16 (3252) - ARM_INS_VQSUB - vqsub${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv4i32 (3253) - ARM_INS_VQSUB - vqsub${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv8i16 (3254) - ARM_INS_VQSUB - vqsub${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBsv8i8 (3255) - ARM_INS_VQSUB - vqsub${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv16i8 (3256) - ARM_INS_VQSUB - vqsub${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv1i64 (3257) - ARM_INS_VQSUB - vqsub${p}.u64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv2i32 (3258) - ARM_INS_VQSUB - vqsub${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv2i64 (3259) - ARM_INS_VQSUB - vqsub${p}.u64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv4i16 (3260) - ARM_INS_VQSUB - vqsub${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv4i32 (3261) - ARM_INS_VQSUB - vqsub${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv8i16 (3262) - ARM_INS_VQSUB - vqsub${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VQSUBuv8i8 (3263) - ARM_INS_VQSUB - vqsub${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRADDHNv2i32 (3264) - ARM_INS_VRADDHN - vraddhn${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRADDHNv4i16 (3265) - ARM_INS_VRADDHN - vraddhn${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRADDHNv8i8 (3266) - ARM_INS_VRADDHN - vraddhn${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPEd (3267) - ARM_INS_VRECPE - vrecpe${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPEfd (3268) - ARM_INS_VRECPE - vrecpe${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPEfq (3269) - ARM_INS_VRECPE - vrecpe${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPEhd (3270) - ARM_INS_VRECPE - vrecpe${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPEhq (3271) - ARM_INS_VRECPE - vrecpe${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPEq (3272) - ARM_INS_VRECPE - vrecpe${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPSfd (3273) - ARM_INS_VRECPS - vrecps${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPSfq (3274) - ARM_INS_VRECPS - vrecps${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPShd (3275) - ARM_INS_VRECPS - vrecps${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRECPShq (3276) - ARM_INS_VRECPS - vrecps${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV16d8 (3277) - ARM_INS_VREV16 - vrev16${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV16q8 (3278) - ARM_INS_VREV16 - vrev16${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV32d16 (3279) - ARM_INS_VREV32 - vrev32${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV32d8 (3280) - ARM_INS_VREV32 - vrev32${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV32q16 (3281) - ARM_INS_VREV32 - vrev32${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV32q8 (3282) - ARM_INS_VREV32 - vrev32${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV64d16 (3283) - ARM_INS_VREV64 - vrev64${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV64d32 (3284) - ARM_INS_VREV64 - vrev64${p}.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV64d8 (3285) - ARM_INS_VREV64 - vrev64${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV64q16 (3286) - ARM_INS_VREV64 - vrev64${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV64q32 (3287) - ARM_INS_VREV64 - vrev64${p}.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VREV64q8 (3288) - ARM_INS_VREV64 - vrev64${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDsv16i8 (3289) - ARM_INS_VRHADD - vrhadd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDsv2i32 (3290) - ARM_INS_VRHADD - vrhadd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDsv4i16 (3291) - ARM_INS_VRHADD - vrhadd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDsv4i32 (3292) - ARM_INS_VRHADD - vrhadd${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDsv8i16 (3293) - ARM_INS_VRHADD - vrhadd${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDsv8i8 (3294) - ARM_INS_VRHADD - vrhadd${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDuv16i8 (3295) - ARM_INS_VRHADD - vrhadd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDuv2i32 (3296) - ARM_INS_VRHADD - vrhadd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDuv4i16 (3297) - ARM_INS_VRHADD - vrhadd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDuv4i32 (3298) - ARM_INS_VRHADD - vrhadd${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDuv8i16 (3299) - ARM_INS_VRHADD - vrhadd${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRHADDuv8i8 (3300) - ARM_INS_VRHADD - vrhadd${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTAD (3301) - ARM_INS_VRINTA - vrinta.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VRINTAH (3302) - ARM_INS_VRINTA - vrinta.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTANDf (3303) - ARM_INS_VRINTA - vrinta.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTANDh (3304) - ARM_INS_VRINTA - vrinta.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTANQf (3305) - ARM_INS_VRINTA - vrinta.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTANQh (3306) - ARM_INS_VRINTA - vrinta.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTAS (3307) - ARM_INS_VRINTA - vrinta.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTMD (3308) - ARM_INS_VRINTM - vrintm.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VRINTMH (3309) - ARM_INS_VRINTM - vrintm.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTMNDf (3310) - ARM_INS_VRINTM - vrintm.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTMNDh (3311) - ARM_INS_VRINTM - vrintm.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTMNQf (3312) - ARM_INS_VRINTM - vrintm.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTMNQh (3313) - ARM_INS_VRINTM - vrintm.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTMS (3314) - ARM_INS_VRINTM - vrintm.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTND (3315) - ARM_INS_VRINTN - vrintn.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VRINTNH (3316) - ARM_INS_VRINTN - vrintn.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTNNDf (3317) - ARM_INS_VRINTN - vrintn.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTNNDh (3318) - ARM_INS_VRINTN - vrintn.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTNNQf (3319) - ARM_INS_VRINTN - vrintn.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTNNQh (3320) - ARM_INS_VRINTN - vrintn.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTNS (3321) - ARM_INS_VRINTN - vrintn.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTPD (3322) - ARM_INS_VRINTP - vrintp.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VRINTPH (3323) - ARM_INS_VRINTP - vrintp.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTPNDf (3324) - ARM_INS_VRINTP - vrintp.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTPNDh (3325) - ARM_INS_VRINTP - vrintp.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTPNQf (3326) - ARM_INS_VRINTP - vrintp.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTPNQh (3327) - ARM_INS_VRINTP - vrintp.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTPS (3328) - ARM_INS_VRINTP - vrintp.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VRINTRD (3329) - ARM_INS_VRINTR - vrintr${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTRH (3330) - ARM_INS_VRINTR - vrintr${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTRS (3331) - ARM_INS_VRINTR - vrintr${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTXD (3332) - ARM_INS_VRINTX - vrintx${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTXH (3333) - ARM_INS_VRINTX - vrintx${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTXNDf (3334) - ARM_INS_VRINTX - vrintx.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTXNDh (3335) - ARM_INS_VRINTX - vrintx.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTXNQf (3336) - ARM_INS_VRINTX - vrintx.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTXNQh (3337) - ARM_INS_VRINTX - vrintx.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTXS (3338) - ARM_INS_VRINTX - vrintx${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTZD (3339) - ARM_INS_VRINTZ - vrintz${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTZH (3340) - ARM_INS_VRINTZ - vrintz${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRINTZNDf (3341) - ARM_INS_VRINTZ - vrintz.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTZNDh (3342) - ARM_INS_VRINTZ - vrintz.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTZNQf (3343) - ARM_INS_VRINTZ - vrintz.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTZNQh (3344) - ARM_INS_VRINTZ - vrintz.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VRINTZS (3345) - ARM_INS_VRINTZ - vrintz${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv16i8 (3346) - ARM_INS_VRSHL - vrshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv1i64 (3347) - ARM_INS_VRSHL - vrshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv2i32 (3348) - ARM_INS_VRSHL - vrshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv2i64 (3349) - ARM_INS_VRSHL - vrshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv4i16 (3350) - ARM_INS_VRSHL - vrshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv4i32 (3351) - ARM_INS_VRSHL - vrshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv8i16 (3352) - ARM_INS_VRSHL - vrshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLsv8i8 (3353) - ARM_INS_VRSHL - vrshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv16i8 (3354) - ARM_INS_VRSHL - vrshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv1i64 (3355) - ARM_INS_VRSHL - vrshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv2i32 (3356) - ARM_INS_VRSHL - vrshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv2i64 (3357) - ARM_INS_VRSHL - vrshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv4i16 (3358) - ARM_INS_VRSHL - vrshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv4i32 (3359) - ARM_INS_VRSHL - vrshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv8i16 (3360) - ARM_INS_VRSHL - vrshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHLuv8i8 (3361) - ARM_INS_VRSHL - vrshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRNv2i32 (3362) - ARM_INS_VRSHRN - vrshrn${p}.i64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRNv4i16 (3363) - ARM_INS_VRSHRN - vrshrn${p}.i32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRNv8i8 (3364) - ARM_INS_VRSHRN - vrshrn${p}.i16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv16i8 (3365) - ARM_INS_VRSHR - vrshr${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv1i64 (3366) - ARM_INS_VRSHR - vrshr${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv2i32 (3367) - ARM_INS_VRSHR - vrshr${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv2i64 (3368) - ARM_INS_VRSHR - vrshr${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv4i16 (3369) - ARM_INS_VRSHR - vrshr${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv4i32 (3370) - ARM_INS_VRSHR - vrshr${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv8i16 (3371) - ARM_INS_VRSHR - vrshr${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRsv8i8 (3372) - ARM_INS_VRSHR - vrshr${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv16i8 (3373) - ARM_INS_VRSHR - vrshr${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv1i64 (3374) - ARM_INS_VRSHR - vrshr${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv2i32 (3375) - ARM_INS_VRSHR - vrshr${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv2i64 (3376) - ARM_INS_VRSHR - vrshr${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv4i16 (3377) - ARM_INS_VRSHR - vrshr${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv4i32 (3378) - ARM_INS_VRSHR - vrshr${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv8i16 (3379) - ARM_INS_VRSHR - vrshr${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSHRuv8i8 (3380) - ARM_INS_VRSHR - vrshr${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTEd (3381) - ARM_INS_VRSQRTE - vrsqrte${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTEfd (3382) - ARM_INS_VRSQRTE - vrsqrte${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTEfq (3383) - ARM_INS_VRSQRTE - vrsqrte${p}.f32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTEhd (3384) - ARM_INS_VRSQRTE - vrsqrte${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTEhq (3385) - ARM_INS_VRSQRTE - vrsqrte${p}.f16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTEq (3386) - ARM_INS_VRSQRTE - vrsqrte${p}.u32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTSfd (3387) - ARM_INS_VRSQRTS - vrsqrts${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTSfq (3388) - ARM_INS_VRSQRTS - vrsqrts${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTShd (3389) - ARM_INS_VRSQRTS - vrsqrts${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSQRTShq (3390) - ARM_INS_VRSQRTS - vrsqrts${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv16i8 (3391) - ARM_INS_VRSRA - vrsra${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv1i64 (3392) - ARM_INS_VRSRA - vrsra${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv2i32 (3393) - ARM_INS_VRSRA - vrsra${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv2i64 (3394) - ARM_INS_VRSRA - vrsra${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv4i16 (3395) - ARM_INS_VRSRA - vrsra${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv4i32 (3396) - ARM_INS_VRSRA - vrsra${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv8i16 (3397) - ARM_INS_VRSRA - vrsra${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAsv8i8 (3398) - ARM_INS_VRSRA - vrsra${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv16i8 (3399) - ARM_INS_VRSRA - vrsra${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv1i64 (3400) - ARM_INS_VRSRA - vrsra${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv2i32 (3401) - ARM_INS_VRSRA - vrsra${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv2i64 (3402) - ARM_INS_VRSRA - vrsra${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv4i16 (3403) - ARM_INS_VRSRA - vrsra${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv4i32 (3404) - ARM_INS_VRSRA - vrsra${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv8i16 (3405) - ARM_INS_VRSRA - vrsra${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSRAuv8i8 (3406) - ARM_INS_VRSRA - vrsra${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSUBHNv2i32 (3407) - ARM_INS_VRSUBHN - vrsubhn${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSUBHNv4i16 (3408) - ARM_INS_VRSUBHN - vrsubhn${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VRSUBHNv8i8 (3409) - ARM_INS_VRSUBHN - vrsubhn${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSCCLRMD (3410) - ARM_INS_VSCCLRM - vscclrm{$p}	$regs */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSCCLRMS (3411) - ARM_INS_VSCCLRM - vscclrm{$p}	$regs */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSDOTD (3412) - ARM_INS_VSDOT - vsdot.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VSDOTDI (3413) - ARM_INS_VSDOT - vsdot.s8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSDOTQ (3414) - ARM_INS_VSDOT - vsdot.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VSDOTQI (3415) - ARM_INS_VSDOT - vsdot.s8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSELEQD (3416) - ARM_INS_VSELEQ - vseleq.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VSELEQH (3417) - ARM_INS_VSELEQ - vseleq.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELEQS (3418) - ARM_INS_VSELEQ - vseleq.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELGED (3419) - ARM_INS_VSELGE - vselge.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VSELGEH (3420) - ARM_INS_VSELGE - vselge.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELGES (3421) - ARM_INS_VSELGE - vselge.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELGTD (3422) - ARM_INS_VSELGT - vselgt.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VSELGTH (3423) - ARM_INS_VSELGT - vselgt.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELGTS (3424) - ARM_INS_VSELGT - vselgt.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELVSD (3425) - ARM_INS_VSELVS - vselvs.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { 0 }
+}},
+{ /* ARM_VSELVSH (3426) - ARM_INS_VSELVS - vselvs.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSELVSS (3427) - ARM_INS_VSELVS - vselvs.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { 0 }
+}},
+{ /* ARM_VSETLNi16 (3428) - ARM_INS_VMOV - vmov${p}.16	$V$lane, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSETLNi32 (3429) - ARM_INS_VMOV - vmov${p}.32	$V$lane, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSETLNi8 (3430) - ARM_INS_VMOV - vmov${p}.8	$V$lane, $R */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* V */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* R */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLi16 (3431) - ARM_INS_VSHLL - vshll${p}.i16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLi32 (3432) - ARM_INS_VSHLL - vshll${p}.i32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLi8 (3433) - ARM_INS_VSHLL - vshll${p}.i8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLsv2i64 (3434) - ARM_INS_VSHLL - vshll${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLsv4i32 (3435) - ARM_INS_VSHLL - vshll${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLsv8i16 (3436) - ARM_INS_VSHLL - vshll${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLuv2i64 (3437) - ARM_INS_VSHLL - vshll${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLuv4i32 (3438) - ARM_INS_VSHLL - vshll${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLLuv8i16 (3439) - ARM_INS_VSHLL - vshll${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv16i8 (3440) - ARM_INS_VSHL - vshl${p}.i8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv1i64 (3441) - ARM_INS_VSHL - vshl${p}.i64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv2i32 (3442) - ARM_INS_VSHL - vshl${p}.i32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv2i64 (3443) - ARM_INS_VSHL - vshl${p}.i64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv4i16 (3444) - ARM_INS_VSHL - vshl${p}.i16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv4i32 (3445) - ARM_INS_VSHL - vshl${p}.i32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv8i16 (3446) - ARM_INS_VSHL - vshl${p}.i16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLiv8i8 (3447) - ARM_INS_VSHL - vshl${p}.i8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv16i8 (3448) - ARM_INS_VSHL - vshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv1i64 (3449) - ARM_INS_VSHL - vshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv2i32 (3450) - ARM_INS_VSHL - vshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv2i64 (3451) - ARM_INS_VSHL - vshl${p}.s64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv4i16 (3452) - ARM_INS_VSHL - vshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv4i32 (3453) - ARM_INS_VSHL - vshl${p}.s32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv8i16 (3454) - ARM_INS_VSHL - vshl${p}.s16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLsv8i8 (3455) - ARM_INS_VSHL - vshl${p}.s8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv16i8 (3456) - ARM_INS_VSHL - vshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv1i64 (3457) - ARM_INS_VSHL - vshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv2i32 (3458) - ARM_INS_VSHL - vshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv2i64 (3459) - ARM_INS_VSHL - vshl${p}.u64	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv4i16 (3460) - ARM_INS_VSHL - vshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv4i32 (3461) - ARM_INS_VSHL - vshl${p}.u32	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv8i16 (3462) - ARM_INS_VSHL - vshl${p}.u16	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHLuv8i8 (3463) - ARM_INS_VSHL - vshl${p}.u8	$Vd, $Vm, $Vn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRNv2i32 (3464) - ARM_INS_VSHRN - vshrn${p}.i64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRNv4i16 (3465) - ARM_INS_VSHRN - vshrn${p}.i32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRNv8i8 (3466) - ARM_INS_VSHRN - vshrn${p}.i16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv16i8 (3467) - ARM_INS_VSHR - vshr${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv1i64 (3468) - ARM_INS_VSHR - vshr${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv2i32 (3469) - ARM_INS_VSHR - vshr${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv2i64 (3470) - ARM_INS_VSHR - vshr${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv4i16 (3471) - ARM_INS_VSHR - vshr${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv4i32 (3472) - ARM_INS_VSHR - vshr${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv8i16 (3473) - ARM_INS_VSHR - vshr${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRsv8i8 (3474) - ARM_INS_VSHR - vshr${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv16i8 (3475) - ARM_INS_VSHR - vshr${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv1i64 (3476) - ARM_INS_VSHR - vshr${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv2i32 (3477) - ARM_INS_VSHR - vshr${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv2i64 (3478) - ARM_INS_VSHR - vshr${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv4i16 (3479) - ARM_INS_VSHR - vshr${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv4i32 (3480) - ARM_INS_VSHR - vshr${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv8i16 (3481) - ARM_INS_VSHR - vshr${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHRuv8i8 (3482) - ARM_INS_VSHR - vshr${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHTOD (3483) - ARM_INS_VCVT - vcvt${p}.f64.s16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHTOH (3484) - ARM_INS_VCVT - vcvt${p}.f16.s16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSHTOS (3485) - ARM_INS_VCVT - vcvt${p}.f32.s16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSITOD (3486) - ARM_INS_VCVT - vcvt${p}.f64.s32	$Dd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSITOH (3487) - ARM_INS_VCVT - vcvt${p}.f16.s32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSITOS (3488) - ARM_INS_VCVT - vcvt${p}.f32.s32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv16i8 (3489) - ARM_INS_VSLI - vsli${p}.8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv1i64 (3490) - ARM_INS_VSLI - vsli${p}.64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv2i32 (3491) - ARM_INS_VSLI - vsli${p}.32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv2i64 (3492) - ARM_INS_VSLI - vsli${p}.64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv4i16 (3493) - ARM_INS_VSLI - vsli${p}.16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv4i32 (3494) - ARM_INS_VSLI - vsli${p}.32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv8i16 (3495) - ARM_INS_VSLI - vsli${p}.16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLIv8i8 (3496) - ARM_INS_VSLI - vsli${p}.8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLTOD (3497) - ARM_INS_VCVT - vcvt${p}.f64.s32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLTOH (3498) - ARM_INS_VCVT - vcvt${p}.f16.s32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSLTOS (3499) - ARM_INS_VCVT - vcvt${p}.f32.s32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSMMLA (3500) - ARM_INS_VSMMLA - vsmmla.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VSQRTD (3501) - ARM_INS_VSQRT - vsqrt${p}.f64	$Dd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSQRTH (3502) - ARM_INS_VSQRT - vsqrt${p}.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSQRTS (3503) - ARM_INS_VSQRT - vsqrt${p}.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv16i8 (3504) - ARM_INS_VSRA - vsra${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv1i64 (3505) - ARM_INS_VSRA - vsra${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv2i32 (3506) - ARM_INS_VSRA - vsra${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv2i64 (3507) - ARM_INS_VSRA - vsra${p}.s64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv4i16 (3508) - ARM_INS_VSRA - vsra${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv4i32 (3509) - ARM_INS_VSRA - vsra${p}.s32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv8i16 (3510) - ARM_INS_VSRA - vsra${p}.s16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAsv8i8 (3511) - ARM_INS_VSRA - vsra${p}.s8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv16i8 (3512) - ARM_INS_VSRA - vsra${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv1i64 (3513) - ARM_INS_VSRA - vsra${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv2i32 (3514) - ARM_INS_VSRA - vsra${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv2i64 (3515) - ARM_INS_VSRA - vsra${p}.u64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv4i16 (3516) - ARM_INS_VSRA - vsra${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv4i32 (3517) - ARM_INS_VSRA - vsra${p}.u32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv8i16 (3518) - ARM_INS_VSRA - vsra${p}.u16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRAuv8i8 (3519) - ARM_INS_VSRA - vsra${p}.u8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv16i8 (3520) - ARM_INS_VSRI - vsri${p}.8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv1i64 (3521) - ARM_INS_VSRI - vsri${p}.64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv2i32 (3522) - ARM_INS_VSRI - vsri${p}.32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv2i64 (3523) - ARM_INS_VSRI - vsri${p}.64	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv4i16 (3524) - ARM_INS_VSRI - vsri${p}.16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv4i32 (3525) - ARM_INS_VSRI - vsri${p}.32	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv8i16 (3526) - ARM_INS_VSRI - vsri${p}.16	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSRIv8i8 (3527) - ARM_INS_VSRI - vsri${p}.8	$Vd, $Vm, $SIMM */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SIMM */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNd16 (3528) - ARM_INS_VST1 - vst1${p}.16	\{$Vd[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNd16_UPD (3529) - ARM_INS_VST1 - vst1${p}.16	\{$Vd[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNd32 (3530) - ARM_INS_VST1 - vst1${p}.32	\{$Vd[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNd32_UPD (3531) - ARM_INS_VST1 - vst1${p}.32	\{$Vd[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNd8 (3532) - ARM_INS_VST1 - vst1${p}.8	\{$Vd[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1LNd8_UPD (3533) - ARM_INS_VST1 - vst1${p}.8	\{$Vd[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1LNq16Pseudo (3534) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1LNq16Pseudo_UPD (3535) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1LNq32Pseudo (3536) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1LNq32Pseudo_UPD (3537) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1LNq8Pseudo (3538) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1LNq8Pseudo_UPD (3539) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d16 (3540) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d16Q (3541) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d16QPseudo (3542) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d16QPseudoWB_fixed (3543) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d16QPseudoWB_register (3544) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d16Qwb_fixed (3545) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d16Qwb_register (3546) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d16T (3547) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d16TPseudo (3548) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d16TPseudoWB_fixed (3549) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d16TPseudoWB_register (3550) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d16Twb_fixed (3551) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d16Twb_register (3552) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d16wb_fixed (3553) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d16wb_register (3554) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32 (3555) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32Q (3556) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d32QPseudo (3557) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d32QPseudoWB_fixed (3558) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d32QPseudoWB_register (3559) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d32Qwb_fixed (3560) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32Qwb_register (3561) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32T (3562) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d32TPseudo (3563) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d32TPseudoWB_fixed (3564) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d32TPseudoWB_register (3565) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d32Twb_fixed (3566) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32Twb_register (3567) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32wb_fixed (3568) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d32wb_register (3569) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64 (3570) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64Q (3571) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d64QPseudo (3572) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d64QPseudoWB_fixed (3573) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d64QPseudoWB_register (3574) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d64Qwb_fixed (3575) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64Qwb_register (3576) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64T (3577) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d64TPseudo (3578) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d64TPseudoWB_fixed (3579) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d64TPseudoWB_register (3580) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d64Twb_fixed (3581) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64Twb_register (3582) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64wb_fixed (3583) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d64wb_register (3584) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8 (3585) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8Q (3586) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d8QPseudo (3587) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d8QPseudoWB_fixed (3588) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d8QPseudoWB_register (3589) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d8Qwb_fixed (3590) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8Qwb_register (3591) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8T (3592) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1d8TPseudo (3593) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d8TPseudoWB_fixed (3594) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1d8TPseudoWB_register (3595) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1d8Twb_fixed (3596) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8Twb_register (3597) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8wb_fixed (3598) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1d8wb_register (3599) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q16 (3600) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1q16HighQPseudo (3601) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q16HighQPseudo_UPD (3602) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q16HighTPseudo (3603) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q16HighTPseudo_UPD (3604) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q16LowQPseudo_UPD (3605) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q16LowTPseudo_UPD (3606) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1q16wb_fixed (3607) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q16wb_register (3608) - ARM_INS_VST1 - vst1${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q32 (3609) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1q32HighQPseudo (3610) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q32HighQPseudo_UPD (3611) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q32HighTPseudo (3612) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q32HighTPseudo_UPD (3613) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q32LowQPseudo_UPD (3614) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q32LowTPseudo_UPD (3615) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1q32wb_fixed (3616) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q32wb_register (3617) - ARM_INS_VST1 - vst1${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q64 (3618) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1q64HighQPseudo (3619) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q64HighQPseudo_UPD (3620) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q64HighTPseudo (3621) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q64HighTPseudo_UPD (3622) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q64LowQPseudo_UPD (3623) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q64LowTPseudo_UPD (3624) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1q64wb_fixed (3625) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q64wb_register (3626) - ARM_INS_VST1 - vst1${p}.64	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q8 (3627) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST1q8HighQPseudo (3628) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q8HighQPseudo_UPD (3629) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q8HighTPseudo (3630) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q8HighTPseudo_UPD (3631) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q8LowQPseudo_UPD (3632) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST1q8LowTPseudo_UPD (3633) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST1q8wb_fixed (3634) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST1q8wb_register (3635) - ARM_INS_VST1 - vst1${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNd16 (3636) - ARM_INS_VST2 - vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2LNd16Pseudo (3637) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2LNd16Pseudo_UPD (3638) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2LNd16_UPD (3639) - ARM_INS_VST2 - vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNd32 (3640) - ARM_INS_VST2 - vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2LNd32Pseudo (3641) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2LNd32Pseudo_UPD (3642) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2LNd32_UPD (3643) - ARM_INS_VST2 - vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNd8 (3644) - ARM_INS_VST2 - vst2${p}.8	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2LNd8Pseudo (3645) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2LNd8Pseudo_UPD (3646) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2LNd8_UPD (3647) - ARM_INS_VST2 - vst2${p}.8	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNq16 (3648) - ARM_INS_VST2 - vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2LNq16Pseudo (3649) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2LNq16Pseudo_UPD (3650) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2LNq16_UPD (3651) - ARM_INS_VST2 - vst2${p}.16	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2LNq32 (3652) - ARM_INS_VST2 - vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2LNq32Pseudo (3653) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2LNq32Pseudo_UPD (3654) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2LNq32_UPD (3655) - ARM_INS_VST2 - vst2${p}.32	\{$Vd[$lane], $src2[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b16 (3656) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b16wb_fixed (3657) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b16wb_register (3658) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b32 (3659) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b32wb_fixed (3660) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b32wb_register (3661) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b8 (3662) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b8wb_fixed (3663) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2b8wb_register (3664) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d16 (3665) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d16wb_fixed (3666) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d16wb_register (3667) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d32 (3668) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d32wb_fixed (3669) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d32wb_register (3670) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d8 (3671) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d8wb_fixed (3672) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2d8wb_register (3673) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2q16 (3674) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2q16Pseudo (3675) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2q16PseudoWB_fixed (3676) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2q16PseudoWB_register (3677) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2q16wb_fixed (3678) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2q16wb_register (3679) - ARM_INS_VST2 - vst2${p}.16	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2q32 (3680) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2q32Pseudo (3681) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2q32PseudoWB_fixed (3682) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2q32PseudoWB_register (3683) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2q32wb_fixed (3684) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2q32wb_register (3685) - ARM_INS_VST2 - vst2${p}.32	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2q8 (3686) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST2q8Pseudo (3687) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2q8PseudoWB_fixed (3688) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST2q8PseudoWB_register (3689) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST2q8wb_fixed (3690) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST2q8wb_register (3691) - ARM_INS_VST2 - vst2${p}.8	$Vd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNd16 (3692) - ARM_INS_VST3 - vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3LNd16Pseudo (3693) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3LNd16Pseudo_UPD (3694) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3LNd16_UPD (3695) - ARM_INS_VST3 - vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNd32 (3696) - ARM_INS_VST3 - vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3LNd32Pseudo (3697) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3LNd32Pseudo_UPD (3698) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3LNd32_UPD (3699) - ARM_INS_VST3 - vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNd8 (3700) - ARM_INS_VST3 - vst3${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3LNd8Pseudo (3701) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3LNd8Pseudo_UPD (3702) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3LNd8_UPD (3703) - ARM_INS_VST3 - vst3${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNq16 (3704) - ARM_INS_VST3 - vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3LNq16Pseudo (3705) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3LNq16Pseudo_UPD (3706) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3LNq16_UPD (3707) - ARM_INS_VST3 - vst3${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3LNq32 (3708) - ARM_INS_VST3 - vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3LNq32Pseudo (3709) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3LNq32Pseudo_UPD (3710) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3LNq32_UPD (3711) - ARM_INS_VST3 - vst3${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3d16 (3712) - ARM_INS_VST3 - vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3d16Pseudo (3713) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3d16Pseudo_UPD (3714) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3d16_UPD (3715) - ARM_INS_VST3 - vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3d32 (3716) - ARM_INS_VST3 - vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3d32Pseudo (3717) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3d32Pseudo_UPD (3718) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3d32_UPD (3719) - ARM_INS_VST3 - vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3d8 (3720) - ARM_INS_VST3 - vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3d8Pseudo (3721) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3d8Pseudo_UPD (3722) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3d8_UPD (3723) - ARM_INS_VST3 - vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST3q16 (3724) - ARM_INS_VST3 - vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3q16Pseudo_UPD (3725) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3q16_UPD (3726) - ARM_INS_VST3 - vst3${p}.16	\{$Vd, $src2, $src3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3q16oddPseudo (3727) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3q16oddPseudo_UPD (3728) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3q32 (3729) - ARM_INS_VST3 - vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3q32Pseudo_UPD (3730) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3q32_UPD (3731) - ARM_INS_VST3 - vst3${p}.32	\{$Vd, $src2, $src3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3q32oddPseudo (3732) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3q32oddPseudo_UPD (3733) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3q8 (3734) - ARM_INS_VST3 - vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3q8Pseudo_UPD (3735) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST3q8_UPD (3736) - ARM_INS_VST3 - vst3${p}.8	\{$Vd, $src2, $src3\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST3q8oddPseudo (3737) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST3q8oddPseudo_UPD (3738) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4LNd16 (3739) - ARM_INS_VST4 - vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4LNd16Pseudo (3740) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4LNd16Pseudo_UPD (3741) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4LNd16_UPD (3742) - ARM_INS_VST4 - vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNd32 (3743) - ARM_INS_VST4 - vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4LNd32Pseudo (3744) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4LNd32Pseudo_UPD (3745) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4LNd32_UPD (3746) - ARM_INS_VST4 - vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNd8 (3747) - ARM_INS_VST4 - vst4${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4LNd8Pseudo (3748) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4LNd8Pseudo_UPD (3749) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4LNd8_UPD (3750) - ARM_INS_VST4 - vst4${p}.8	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNq16 (3751) - ARM_INS_VST4 - vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4LNq16Pseudo (3752) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4LNq16Pseudo_UPD (3753) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4LNq16_UPD (3754) - ARM_INS_VST4 - vst4${p}.16	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4LNq32 (3755) - ARM_INS_VST4 - vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4LNq32Pseudo (3756) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4LNq32Pseudo_UPD (3757) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4LNq32_UPD (3758) - ARM_INS_VST4 - vst4${p}.32	\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4d16 (3759) - ARM_INS_VST4 - vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4d16Pseudo (3760) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4d16Pseudo_UPD (3761) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4d16_UPD (3762) - ARM_INS_VST4 - vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4d32 (3763) - ARM_INS_VST4 - vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4d32Pseudo (3764) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4d32Pseudo_UPD (3765) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4d32_UPD (3766) - ARM_INS_VST4 - vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4d8 (3767) - ARM_INS_VST4 - vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4d8Pseudo (3768) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4d8Pseudo_UPD (3769) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4d8_UPD (3770) - ARM_INS_VST4 - vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VST4q16 (3771) - ARM_INS_VST4 - vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4q16Pseudo_UPD (3772) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4q16_UPD (3773) - ARM_INS_VST4 - vst4${p}.16	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4q16oddPseudo (3774) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4q16oddPseudo_UPD (3775) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4q32 (3776) - ARM_INS_VST4 - vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4q32Pseudo_UPD (3777) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4q32_UPD (3778) - ARM_INS_VST4 - vst4${p}.32	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4q32oddPseudo (3779) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4q32oddPseudo_UPD (3780) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4q8 (3781) - ARM_INS_VST4 - vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4q8Pseudo_UPD (3782) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VST4q8_UPD (3783) - ARM_INS_VST4 - vst4${p}.8	\{$Vd, $src2, $src3, $src4\}, $Rn$Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - i32imm */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm - GPR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src3 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src4 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VST4q8oddPseudo (3784) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_VST4q8oddPseudo_UPD (3785) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VSTMDDB_UPD (3786) - ARM_INS_VSTMDB - vstmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSTMDIA (3787) - ARM_INS_VSTMIA - vstmia${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSTMDIA_UPD (3788) - ARM_INS_VSTMIA - vstmia${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{{{ /* ARM_VSTMQIA (3789) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VSTMSDB_UPD (3790) - ARM_INS_VSTMDB - vstmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSTMSIA (3791) - ARM_INS_VSTMIA - vstmia${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSTMSIA_UPD (3792) - ARM_INS_VSTMIA - vstmia${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_VSTRD (3793) - ARM_INS_VSTR - vstr${p}	$Dd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTRH (3794) - ARM_INS_VSTR - vstr${p}.16	$Sd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTRS (3795) - ARM_INS_VSTR - vstr${p}	$Sd, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPCXTNS_off (3796) - ARM_INS_VSTR - vstr${p}	fpcxtns, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPCXTNS_post (3797) - ARM_INS_VSTR - vstr${p}	fpcxtns, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPCXTNS_pre (3798) - ARM_INS_VSTR - vstr${p}	fpcxtns, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPCXTS_off (3799) - ARM_INS_VSTR - vstr${p}	fpcxts, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPCXTS_post (3800) - ARM_INS_VSTR - vstr${p}	fpcxts, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPCXTS_pre (3801) - ARM_INS_VSTR - vstr${p}	fpcxts, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPSCR_NZCVQC_off (3802) - ARM_INS_VSTR - vstr${p}	fpscr_nzcvqc, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPSCR_NZCVQC_post (3803) - ARM_INS_VSTR - vstr${p}	fpscr_nzcvqc, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPSCR_NZCVQC_pre (3804) - ARM_INS_VSTR - vstr${p}	fpscr_nzcvqc, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPSCR_off (3805) - ARM_INS_VSTR - vstr${p}	fpscr, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPSCR_post (3806) - ARM_INS_VSTR - vstr${p}	fpscr, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_FPSCR_pre (3807) - ARM_INS_VSTR - vstr${p}	fpscr, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_P0_off (3808) - ARM_INS_VSTR - vstr${p}	p0, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_P0_post (3809) - ARM_INS_VSTR - vstr${p}	p0, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_P0_pre (3810) - ARM_INS_VSTR - vstr${p}	p0, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_v16i1, CS_DATA_TYPE_v8i1, CS_DATA_TYPE_v4i1, CS_DATA_TYPE_v2i1, CS_DATA_TYPE_LAST } }, /* P0 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_VPR_off (3811) - ARM_INS_VSTR - vstr${p}	vpr, $addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_VPR_post (3812) - ARM_INS_VSTR - vstr${p}	vpr, $Rn$addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSTR_VPR_pre (3813) - ARM_INS_VSTR - vstr${p}	vpr, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBD (3814) - ARM_INS_VSUB - vsub${p}.f64	$Dd, $Dn, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBH (3815) - ARM_INS_VSUB - vsub${p}.f16	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBHNv2i32 (3816) - ARM_INS_VSUBHN - vsubhn${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBHNv4i16 (3817) - ARM_INS_VSUBHN - vsubhn${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBHNv8i8 (3818) - ARM_INS_VSUBHN - vsubhn${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBLsv2i64 (3819) - ARM_INS_VSUBL - vsubl${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBLsv4i32 (3820) - ARM_INS_VSUBL - vsubl${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBLsv8i16 (3821) - ARM_INS_VSUBL - vsubl${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBLuv2i64 (3822) - ARM_INS_VSUBL - vsubl${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBLuv4i32 (3823) - ARM_INS_VSUBL - vsubl${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBLuv8i16 (3824) - ARM_INS_VSUBL - vsubl${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBS (3825) - ARM_INS_VSUB - vsub${p}.f32	$Sd, $Sn, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBWsv2i64 (3826) - ARM_INS_VSUBW - vsubw${p}.s32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBWsv4i32 (3827) - ARM_INS_VSUBW - vsubw${p}.s16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBWsv8i16 (3828) - ARM_INS_VSUBW - vsubw${p}.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBWuv2i64 (3829) - ARM_INS_VSUBW - vsubw${p}.u32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBWuv4i32 (3830) - ARM_INS_VSUBW - vsubw${p}.u16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBWuv8i16 (3831) - ARM_INS_VSUBW - vsubw${p}.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBfd (3832) - ARM_INS_VSUB - vsub${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBfq (3833) - ARM_INS_VSUB - vsub${p}.f32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBhd (3834) - ARM_INS_VSUB - vsub${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBhq (3835) - ARM_INS_VSUB - vsub${p}.f16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv16i8 (3836) - ARM_INS_VSUB - vsub${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv1i64 (3837) - ARM_INS_VSUB - vsub${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv2i32 (3838) - ARM_INS_VSUB - vsub${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv2i64 (3839) - ARM_INS_VSUB - vsub${p}.i64	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv4i16 (3840) - ARM_INS_VSUB - vsub${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv4i32 (3841) - ARM_INS_VSUB - vsub${p}.i32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv8i16 (3842) - ARM_INS_VSUB - vsub${p}.i16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUBv8i8 (3843) - ARM_INS_VSUB - vsub${p}.i8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUDOTDI (3844) - ARM_INS_VSUDOT - vsudot.u8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSUDOTQI (3845) - ARM_INS_VSUDOT - vsudot.u8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSWPd (3846) - ARM_INS_VSWP - vswp${p}	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* in1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* in2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VSWPq (3847) - ARM_INS_VSWP - vswp${p}	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* in1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* in2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTBL1 (3848) - ARM_INS_VTBL - vtbl${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTBL2 (3849) - ARM_INS_VTBL - vtbl${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTBL3 (3850) - ARM_INS_VTBL - vtbl${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VTBL3Pseudo (3851) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VTBL4 (3852) - ARM_INS_VTBL - vtbl${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VTBL4Pseudo (3853) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VTBX1 (3854) - ARM_INS_VTBX - vtbx${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* orig */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTBX2 (3855) - ARM_INS_VTBX - vtbx${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* orig */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTBX3 (3856) - ARM_INS_VTBX - vtbx${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* orig */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VTBX3Pseudo (3857) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VTBX4 (3858) - ARM_INS_VTBX - vtbx${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* orig */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_VTBX4Pseudo (3859) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_VTOSHD (3860) - ARM_INS_VCVT - vcvt${p}.s16.f64	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSHH (3861) - ARM_INS_VCVT - vcvt${p}.s16.f16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSHS (3862) - ARM_INS_VCVT - vcvt${p}.s16.f32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSIRD (3863) - ARM_INS_VCVTR - vcvtr${p}.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSIRH (3864) - ARM_INS_VCVTR - vcvtr${p}.s32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSIRS (3865) - ARM_INS_VCVTR - vcvtr${p}.s32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSIZD (3866) - ARM_INS_VCVT - vcvt${p}.s32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSIZH (3867) - ARM_INS_VCVT - vcvt${p}.s32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSIZS (3868) - ARM_INS_VCVT - vcvt${p}.s32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSLD (3869) - ARM_INS_VCVT - vcvt${p}.s32.f64	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSLH (3870) - ARM_INS_VCVT - vcvt${p}.s32.f16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOSLS (3871) - ARM_INS_VCVT - vcvt${p}.s32.f32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUHD (3872) - ARM_INS_VCVT - vcvt${p}.u16.f64	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUHH (3873) - ARM_INS_VCVT - vcvt${p}.u16.f16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUHS (3874) - ARM_INS_VCVT - vcvt${p}.u16.f32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUIRD (3875) - ARM_INS_VCVTR - vcvtr${p}.u32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUIRH (3876) - ARM_INS_VCVTR - vcvtr${p}.u32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUIRS (3877) - ARM_INS_VCVTR - vcvtr${p}.u32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUIZD (3878) - ARM_INS_VCVT - vcvt${p}.u32.f64	$Sd, $Dm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUIZH (3879) - ARM_INS_VCVT - vcvt${p}.u32.f16	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOUIZS (3880) - ARM_INS_VCVT - vcvt${p}.u32.f32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOULD (3881) - ARM_INS_VCVT - vcvt${p}.u32.f64	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOULH (3882) - ARM_INS_VCVT - vcvt${p}.u32.f16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTOULS (3883) - ARM_INS_VCVT - vcvt${p}.u32.f32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTRNd16 (3884) - ARM_INS_VTRN - vtrn${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTRNd32 (3885) - ARM_INS_VTRN - vtrn${p}.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTRNd8 (3886) - ARM_INS_VTRN - vtrn${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTRNq16 (3887) - ARM_INS_VTRN - vtrn${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTRNq32 (3888) - ARM_INS_VTRN - vtrn${p}.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTRNq8 (3889) - ARM_INS_VTRN - vtrn${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTSTv16i8 (3890) - ARM_INS_VTST - vtst${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTSTv2i32 (3891) - ARM_INS_VTST - vtst${p}.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTSTv4i16 (3892) - ARM_INS_VTST - vtst${p}.16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTSTv4i32 (3893) - ARM_INS_VTST - vtst${p}.32	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTSTv8i16 (3894) - ARM_INS_VTST - vtst${p}.16	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VTSTv8i8 (3895) - ARM_INS_VTST - vtst${p}.8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUDOTD (3896) - ARM_INS_VUDOT - vudot.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VUDOTDI (3897) - ARM_INS_VUDOT - vudot.u8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUDOTQ (3898) - ARM_INS_VUDOT - vudot.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VUDOTQI (3899) - ARM_INS_VUDOT - vudot.u8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUHTOD (3900) - ARM_INS_VCVT - vcvt${p}.f64.u16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUHTOH (3901) - ARM_INS_VCVT - vcvt${p}.f16.u16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUHTOS (3902) - ARM_INS_VCVT - vcvt${p}.f32.u16	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUITOD (3903) - ARM_INS_VCVT - vcvt${p}.f64.u32	$Dd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Dd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUITOH (3904) - ARM_INS_VCVT - vcvt${p}.f16.u32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f16, CS_DATA_TYPE_bf16, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUITOS (3905) - ARM_INS_VCVT - vcvt${p}.f32.u32	$Sd, $Sm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* Sm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VULTOD (3906) - ARM_INS_VCVT - vcvt${p}.f64.u32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VULTOH (3907) - ARM_INS_VCVT - vcvt${p}.f16.u32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VULTOS (3908) - ARM_INS_VCVT - vcvt${p}.f32.u32	$dst, $a, $fbits */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST } }, /* a */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fbits */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUMMLA (3909) - ARM_INS_VUMMLA - vummla.u8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VUSDOTD (3910) - ARM_INS_VUSDOT - vusdot.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VUSDOTDI (3911) - ARM_INS_VUSDOT - vusdot.s8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUSDOTQ (3912) - ARM_INS_VUSDOT - vusdot.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VUSDOTQI (3913) - ARM_INS_VUSDOT - vusdot.s8	$Vd, $Vn, $Vm$lane */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lane - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUSMMLA (3914) - ARM_INS_VUSMMLA - vusmmla.s8	$Vd, $Vn, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { 0 }
+}},
+{ /* ARM_VUZPd16 (3915) - ARM_INS_VUZP - vuzp${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUZPd8 (3916) - ARM_INS_VUZP - vuzp${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUZPq16 (3917) - ARM_INS_VUZP - vuzp${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUZPq32 (3918) - ARM_INS_VUZP - vuzp${p}.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VUZPq8 (3919) - ARM_INS_VUZP - vuzp${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VZIPd16 (3920) - ARM_INS_VZIP - vzip${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VZIPd8 (3921) - ARM_INS_VZIP - vzip${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_v8i8, CS_DATA_TYPE_v4i16, CS_DATA_TYPE_v2i32, CS_DATA_TYPE_v1i64, CS_DATA_TYPE_v2f32, CS_DATA_TYPE_v4f16, CS_DATA_TYPE_v4bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VZIPq16 (3922) - ARM_INS_VZIP - vzip${p}.16	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VZIPq32 (3923) - ARM_INS_VZIP - vzip${p}.32	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_VZIPq8 (3924) - ARM_INS_VZIP - vzip${p}.8	$Vd, $Vm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* Vm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_v16i8, CS_DATA_TYPE_v8i16, CS_DATA_TYPE_v4i32, CS_DATA_TYPE_v2i64, CS_DATA_TYPE_v4f32, CS_DATA_TYPE_v2f64, CS_DATA_TYPE_v8f16, CS_DATA_TYPE_v8bf16, CS_DATA_TYPE_LAST } }, /* src2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_sysLDMDA (3925) - ARM_INS_LDMDA - ldmda${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMDA_UPD (3926) - ARM_INS_LDMDA - ldmda${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMDB (3927) - ARM_INS_LDMDB - ldmdb${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMDB_UPD (3928) - ARM_INS_LDMDB - ldmdb${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMIA (3929) - ARM_INS_LDM - ldm${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMIA_UPD (3930) - ARM_INS_LDM - ldm${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMIB (3931) - ARM_INS_LDMIB - ldmib${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysLDMIB_UPD (3932) - ARM_INS_LDMIB - ldmib${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMDA (3933) - ARM_INS_STMDA - stmda${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMDA_UPD (3934) - ARM_INS_STMDA - stmda${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMDB (3935) - ARM_INS_STMDB - stmdb${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMDB_UPD (3936) - ARM_INS_STMDB - stmdb${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMIA (3937) - ARM_INS_STM - stm${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMIA_UPD (3938) - ARM_INS_STM - stm${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMIB (3939) - ARM_INS_STMIB - stmib${p}	$Rn, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_sysSTMIB_UPD (3940) - ARM_INS_STMIB - stmib${p}	$Rn!, $regs ^ */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2ADCri (3941) - ARM_INS_ADC - adc${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADCrr (3942) - ARM_INS_ADC - adc${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADCrs (3943) - ARM_INS_ADC - adc${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADDri (3944) - ARM_INS_ADD - add${s}${p}.w	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADDri12 (3945) - ARM_INS_ADDW - addw${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2ADDrr (3946) - ARM_INS_ADD - add${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADDrs (3947) - ARM_INS_ADD - add${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADDspImm (3948) - ARM_INS_ADD - add${s}${p}.w	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ADDspImm12 (3949) - ARM_INS_ADDW - addw${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2ADR (3950) - ARM_INS_ADR - adr{$p}.w	$Rd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2ANDri (3951) - ARM_INS_AND - and${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ANDrr (3952) - ARM_INS_AND - and${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ANDrs (3953) - ARM_INS_AND - and${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ASRri (3954) - ARM_INS_ASR - asr${s}${p}.w	$Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ASRrr (3955) - ARM_INS_ASR - asr${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2AUT (3956) - ARM_INS_AUT - aut	r12, lr, sp */
+{
+  { 0 }
+}},
+{ /* ARM_t2AUTG (3957) - ARM_INS_AUTG - autg${p}	$Ra, $Rn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2B (3958) - ARM_INS_B - b${p}.w	$target */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BFC (3959) - ARM_INS_BFC - bfc${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BFI (3960) - ARM_INS_BFI - bfi${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BFLi (3961) - ARM_INS_BFL - bfl${p}	$b_label, $label */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BFLr (3962) - ARM_INS_BFLX - bflx${p}	$b_label, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BFi (3963) - ARM_INS_BF - bf${p}	$b_label, $label */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BFic (3964) - ARM_INS_BFCSEL - bfcsel	$b_label, $label, $ba_label, $bcond */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* ba_label */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* bcond */
+  { 0 }
+}},
+{ /* ARM_t2BFr (3965) - ARM_INS_BFX - bfx${p}	$b_label, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* b_label */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2BICri (3966) - ARM_INS_BIC - bic${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2BICrr (3967) - ARM_INS_BIC - bic${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2BICrs (3968) - ARM_INS_BIC - bic${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2BTI (3969) - ARM_INS_BTI - bti	 */
+{
+  { 0 }
+}},
+{ /* ARM_t2BXAUT (3970) - ARM_INS_BXAUT - bxaut${p}	$Ra, $Rn, $Rm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2BXJ (3971) - ARM_INS_BXJ - bxj${p}	$func */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2Bcc (3972) - ARM_INS_B - b${p}.w	$target */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CDP (3973) - ARM_INS_CDP - cdp${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CDP2 (3974) - ARM_INS_CDP2 - cdp2${p}	$cop, $opc1, $CRd, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CLREX (3975) - ARM_INS_CLREX - clrex${p} */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CLRM (3976) - ARM_INS_CLRM - clrm${p}	$regs */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2CLZ (3977) - ARM_INS_CLZ - clz${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CMNri (3978) - ARM_INS_CMN - cmn${p}.w	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CMNzrr (3979) - ARM_INS_CMN - cmn${p}.w	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CMNzrs (3980) - ARM_INS_CMN - cmn${p}.w	$Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CMPri (3981) - ARM_INS_CMP - cmp${p}.w	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CMPrr (3982) - ARM_INS_CMP - cmp${p}.w	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CMPrs (3983) - ARM_INS_CMP - cmp${p}.w	$Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2CPS1p (3984) - ARM_INS_CPS - cps	$mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_t2CPS2p (3985) - ARM_INS_CPS - cps$imod.w	$iflags */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */
+  { 0 }
+}},
+{ /* ARM_t2CPS3p (3986) - ARM_INS_CPS - cps$imod	$iflags, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { 0 }
+}},
+{ /* ARM_t2CRC32B (3987) - ARM_INS_CRC32B - crc32b	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2CRC32CB (3988) - ARM_INS_CRC32CB - crc32cb	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2CRC32CH (3989) - ARM_INS_CRC32CH - crc32ch	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2CRC32CW (3990) - ARM_INS_CRC32CW - crc32cw	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2CRC32H (3991) - ARM_INS_CRC32H - crc32h	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2CRC32W (3992) - ARM_INS_CRC32W - crc32w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2CSEL (3993) - ARM_INS_CSEL - csel	$Rd, $Rn, $Rm, $fcond */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */
+  { 0 }
+}},
+{ /* ARM_t2CSINC (3994) - ARM_INS_CSINC - csinc	$Rd, $Rn, $Rm, $fcond */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */
+  { 0 }
+}},
+{ /* ARM_t2CSINV (3995) - ARM_INS_CSINV - csinv	$Rd, $Rn, $Rm, $fcond */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */
+  { 0 }
+}},
+{ /* ARM_t2CSNEG (3996) - ARM_INS_CSNEG - csneg	$Rd, $Rn, $Rm, $fcond */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* fcond */
+  { 0 }
+}},
+{ /* ARM_t2DBG (3997) - ARM_INS_DBG - dbg${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2DCPS1 (3998) - ARM_INS_DCPS1 - dcps1${p} */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2DCPS2 (3999) - ARM_INS_DCPS2 - dcps2${p} */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2DCPS3 (4000) - ARM_INS_DCPS3 - dcps3${p} */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2DLS (4001) - ARM_INS_DLS - dls	$LR, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { 0 }
+}},
+{ /* ARM_t2DMB (4002) - ARM_INS_DMB - dmb${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2DSB (4003) - ARM_INS_DSB - dsb${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2EORri (4004) - ARM_INS_EOR - eor${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2EORrr (4005) - ARM_INS_EOR - eor${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2EORrs (4006) - ARM_INS_EOR - eor${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2HINT (4007) - ARM_INS_HINT - hint${p}.w	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2HVC (4008) - ARM_INS_HVC - hvc.w	$imm16 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */
+  { 0 }
+}},
+{ /* ARM_t2ISB (4009) - ARM_INS_ISB - isb${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2IT (4010) - ARM_INS_IT - it$mask	$cc */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cc */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */
+  { 0 }
+}},
+{{{ /* ARM_t2Int_eh_sjlj_setjmp (4011) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_t2Int_eh_sjlj_setjmp_nofp (4012) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_t2LDA (4013) - ARM_INS_LDA - lda${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDAB (4014) - ARM_INS_LDAB - ldab${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDAEX (4015) - ARM_INS_LDAEX - ldaex${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDAEXB (4016) - ARM_INS_LDAEXB - ldaexb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDAEXD (4017) - ARM_INS_LDAEXD - ldaexd${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDAEXH (4018) - ARM_INS_LDAEXH - ldaexh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDAH (4019) - ARM_INS_LDAH - ldah${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2L_OFFSET (4020) - ARM_INS_LDC2L - ldc2l${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2L_OPTION (4021) - ARM_INS_LDC2L - ldc2l${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2L_POST (4022) - ARM_INS_LDC2L - ldc2l${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2L_PRE (4023) - ARM_INS_LDC2L - ldc2l${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2_OFFSET (4024) - ARM_INS_LDC2 - ldc2${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2_OPTION (4025) - ARM_INS_LDC2 - ldc2${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2_POST (4026) - ARM_INS_LDC2 - ldc2${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC2_PRE (4027) - ARM_INS_LDC2 - ldc2${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDCL_OFFSET (4028) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDCL_OPTION (4029) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDCL_POST (4030) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDCL_PRE (4031) - ARM_INS_LDCL - ldcl${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC_OFFSET (4032) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC_OPTION (4033) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC_POST (4034) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDC_PRE (4035) - ARM_INS_LDC - ldc${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDMDB (4036) - ARM_INS_LDMDB - ldmdb${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2LDMDB_UPD (4037) - ARM_INS_LDMDB - ldmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2LDMIA (4038) - ARM_INS_LDM - ldm${p}.w	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2LDMIA_UPD (4039) - ARM_INS_LDM - ldm${p}.w	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2LDRBT (4040) - ARM_INS_LDRBT - ldrbt${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRB_POST (4041) - ARM_INS_LDRB - ldrb${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRB_PRE (4042) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRBi12 (4043) - ARM_INS_LDRB - ldrb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRBi8 (4044) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRBpci (4045) - ARM_INS_LDRB - ldrb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRBs (4046) - ARM_INS_LDRB - ldrb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRD_POST (4047) - ARM_INS_LDRD - ldrd${p}	$Rt, $Rt2, $addr$imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRD_PRE (4048) - ARM_INS_LDRD - ldrd${p}	$Rt, $Rt2, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRDi8 (4049) - ARM_INS_LDRD - ldrd${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDREX (4050) - ARM_INS_LDREX - ldrex${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDREXB (4051) - ARM_INS_LDREXB - ldrexb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDREXD (4052) - ARM_INS_LDREXD - ldrexd${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDREXH (4053) - ARM_INS_LDREXH - ldrexh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRHT (4054) - ARM_INS_LDRHT - ldrht${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRH_POST (4055) - ARM_INS_LDRH - ldrh${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRH_PRE (4056) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRHi12 (4057) - ARM_INS_LDRH - ldrh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRHi8 (4058) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRHpci (4059) - ARM_INS_LDRH - ldrh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRHs (4060) - ARM_INS_LDRH - ldrh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSBT (4061) - ARM_INS_LDRSBT - ldrsbt${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSB_POST (4062) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSB_PRE (4063) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSBi12 (4064) - ARM_INS_LDRSB - ldrsb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSBi8 (4065) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSBpci (4066) - ARM_INS_LDRSB - ldrsb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSBs (4067) - ARM_INS_LDRSB - ldrsb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSHT (4068) - ARM_INS_LDRSHT - ldrsht${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSH_POST (4069) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSH_PRE (4070) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSHi12 (4071) - ARM_INS_LDRSH - ldrsh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSHi8 (4072) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSHpci (4073) - ARM_INS_LDRSH - ldrsh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRSHs (4074) - ARM_INS_LDRSH - ldrsh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRT (4075) - ARM_INS_LDRT - ldrt${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDR_POST (4076) - ARM_INS_LDR - ldr${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDR_PRE (4077) - ARM_INS_LDR - ldr${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRi12 (4078) - ARM_INS_LDR - ldr${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRi8 (4079) - ARM_INS_LDR - ldr${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRpci (4080) - ARM_INS_LDR - ldr${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LDRs (4081) - ARM_INS_LDR - ldr${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_INVALID, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2LE (4082) - ARM_INS_LE - le	$label */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_t2LEUpdate (4083) - ARM_INS_LE - le	$LRin, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRout */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LRin */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_t2LSLri (4084) - ARM_INS_LSL - lsl${s}${p}.w	$Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2LSLrr (4085) - ARM_INS_LSL - lsl${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2LSRri (4086) - ARM_INS_LSR - lsr${s}${p}.w	$Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2LSRrr (4087) - ARM_INS_LSR - lsr${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2MCR (4088) - ARM_INS_MCR - mcr${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MCR2 (4089) - ARM_INS_MCR2 - mcr2${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MCRR (4090) - ARM_INS_MCRR - mcrr${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MCRR2 (4091) - ARM_INS_MCRR2 - mcrr2${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MLA (4092) - ARM_INS_MLA - mla${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MLS (4093) - ARM_INS_MLS - mls${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MOVTi16 (4094) - ARM_INS_MOVT - movt${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* src */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MOVi (4095) - ARM_INS_MOV - mov${s}${p}.w	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2MOVi16 (4096) - ARM_INS_MOVW - movw${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MOVr (4097) - ARM_INS_MOV - mov${s}${p}.w	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{{{ /* ARM_t2MOVsra_flag (4098) - ARM_INS_INVALID - asrs${p}.w	$Rd, $Rm, #1 */
+ 0
+}}},
+{{{ /* ARM_t2MOVsrl_flag (4099) - ARM_INS_INVALID - lsrs${p}.w	$Rd, $Rm, #1 */
+ 0
+}}},
+{ /* ARM_t2MRC (4100) - ARM_INS_MRC - mrc${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRC2 (4101) - ARM_INS_MRC2 - mrc2${p}	$cop, $opc1, $Rt, $CRn, $CRm, $opc2 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRRC (4102) - ARM_INS_MRRC - mrrc${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRRC2 (4103) - ARM_INS_MRRC2 - mrrc2${p}	$cop, $opc1, $Rt, $Rt2, $CRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opc1 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRS_AR (4104) - ARM_INS_MRS - mrs${p}	$Rd, apsr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRS_M (4105) - ARM_INS_MRS - mrs${p}	$Rd, $SYSm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SYSm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRSbanked (4106) - ARM_INS_MRS - mrs${p}	$Rd, $banked */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MRSsys_AR (4107) - ARM_INS_MRS - mrs${p}	$Rd, spsr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MSR_AR (4108) - ARM_INS_MSR - msr${p}	$mask, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mask */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MSR_M (4109) - ARM_INS_MSR - msr${p}	$SYSm, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* SYSm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MSRbanked (4110) - ARM_INS_MSR - msr${p}	$banked, $Rn */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* banked */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MUL (4111) - ARM_INS_MUL - mul${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2MVNi (4112) - ARM_INS_MVN - mvn${s}${p}	$Rd, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2MVNr (4113) - ARM_INS_MVN - mvn${s}${p}.w	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2MVNs (4114) - ARM_INS_MVN - mvn${s}${p}.w	$Rd, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ORNri (4115) - ARM_INS_ORN - orn${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ORNrr (4116) - ARM_INS_ORN - orn${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ORNrs (4117) - ARM_INS_ORN - orn${s}${p}	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ORRri (4118) - ARM_INS_ORR - orr${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ORRrr (4119) - ARM_INS_ORR - orr${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2ORRrs (4120) - ARM_INS_ORR - orr${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2PAC (4121) - ARM_INS_PAC - pac	r12, lr, sp */
+{
+  { 0 }
+}},
+{ /* ARM_t2PACBTI (4122) - ARM_INS_PACBTI - pacbti	r12, lr, sp */
+{
+  { 0 }
+}},
+{ /* ARM_t2PACG (4123) - ARM_INS_PACG - pacg${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_t2PKHBT (4124) - ARM_INS_PKHBT - pkhbt${p}	$Rd, $Rn, $Rm$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PKHTB (4125) - ARM_INS_PKHTB - pkhtb${p}	$Rd, $Rn, $Rm$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDWi12 (4126) - ARM_INS_PLDW - pldw${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDWi8 (4127) - ARM_INS_PLDW - pldw${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDWs (4128) - ARM_INS_PLDW - pldw${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDi12 (4129) - ARM_INS_PLD - pld${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDi8 (4130) - ARM_INS_PLD - pld${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDpci (4131) - ARM_INS_PLD - pld${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLDs (4132) - ARM_INS_PLD - pld${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLIi12 (4133) - ARM_INS_PLI - pli${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLIi8 (4134) - ARM_INS_PLI - pli${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLIpci (4135) - ARM_INS_PLI - pli${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2PLIs (4136) - ARM_INS_PLI - pli${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QADD (4137) - ARM_INS_QADD - qadd${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QADD16 (4138) - ARM_INS_QADD16 - qadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QADD8 (4139) - ARM_INS_QADD8 - qadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QASX (4140) - ARM_INS_QASX - qasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QDADD (4141) - ARM_INS_QDADD - qdadd${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QDSUB (4142) - ARM_INS_QDSUB - qdsub${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QSAX (4143) - ARM_INS_QSAX - qsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QSUB (4144) - ARM_INS_QSUB - qsub${p}	$Rd, $Rm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QSUB16 (4145) - ARM_INS_QSUB16 - qsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2QSUB8 (4146) - ARM_INS_QSUB8 - qsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2RBIT (4147) - ARM_INS_RBIT - rbit${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2REV (4148) - ARM_INS_REV - rev${p}.w	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2REV16 (4149) - ARM_INS_REV16 - rev16${p}.w	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2REVSH (4150) - ARM_INS_REVSH - revsh${p}.w	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2RFEDB (4151) - ARM_INS_RFEDB - rfedb${p}	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2RFEDBW (4152) - ARM_INS_RFEDB - rfedb${p}	$Rn! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2RFEIA (4153) - ARM_INS_RFEIA - rfeia${p}	$Rn */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2RFEIAW (4154) - ARM_INS_RFEIA - rfeia${p}	$Rn! */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2RORri (4155) - ARM_INS_ROR - ror${s}${p}.w	$Rd, $Rm, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2RORrr (4156) - ARM_INS_ROR - ror${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2RRX (4157) - ARM_INS_RRX - rrx${s}${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2RSBri (4158) - ARM_INS_RSB - rsb${s}${p}.w	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2RSBrr (4159) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2RSBrs (4160) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SADD16 (4161) - ARM_INS_SADD16 - sadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SADD8 (4162) - ARM_INS_SADD8 - sadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SASX (4163) - ARM_INS_SASX - sasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SB (4164) - ARM_INS_SB - sb */
+{
+  { 0 }
+}},
+{ /* ARM_t2SBCri (4165) - ARM_INS_SBC - sbc${s}${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SBCrr (4166) - ARM_INS_SBC - sbc${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SBCrs (4167) - ARM_INS_SBC - sbc${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SBFX (4168) - ARM_INS_SBFX - sbfx${p}	$Rd, $Rn, $lsb, $msb */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* msb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SDIV (4169) - ARM_INS_SDIV - sdiv${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SEL (4170) - ARM_INS_SEL - sel${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SETPAN (4171) - ARM_INS_SETPAN - setpan	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { 0 }
+}},
+{ /* ARM_t2SG (4172) - ARM_INS_SG - sg${p} */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SHADD16 (4173) - ARM_INS_SHADD16 - shadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SHADD8 (4174) - ARM_INS_SHADD8 - shadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SHASX (4175) - ARM_INS_SHASX - shasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SHSAX (4176) - ARM_INS_SHSAX - shsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SHSUB16 (4177) - ARM_INS_SHSUB16 - shsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SHSUB8 (4178) - ARM_INS_SHSUB8 - shsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMC (4179) - ARM_INS_SMC - smc${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLABB (4180) - ARM_INS_SMLABB - smlabb${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLABT (4181) - ARM_INS_SMLABT - smlabt${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLAD (4182) - ARM_INS_SMLAD - smlad${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLADX (4183) - ARM_INS_SMLADX - smladx${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLAL (4184) - ARM_INS_SMLAL - smlal${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLALBB (4185) - ARM_INS_SMLALBB - smlalbb${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLALBT (4186) - ARM_INS_SMLALBT - smlalbt${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLALD (4187) - ARM_INS_SMLALD - smlald${p}	$Ra, $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLALDX (4188) - ARM_INS_SMLALDX - smlaldx${p}	$Ra, $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLALTB (4189) - ARM_INS_SMLALTB - smlaltb${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLALTT (4190) - ARM_INS_SMLALTT - smlaltt${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLATB (4191) - ARM_INS_SMLATB - smlatb${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLATT (4192) - ARM_INS_SMLATT - smlatt${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLAWB (4193) - ARM_INS_SMLAWB - smlawb${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLAWT (4194) - ARM_INS_SMLAWT - smlawt${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLSD (4195) - ARM_INS_SMLSD - smlsd${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLSDX (4196) - ARM_INS_SMLSDX - smlsdx${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLSLD (4197) - ARM_INS_SMLSLD - smlsld${p}	$Ra, $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMLSLDX (4198) - ARM_INS_SMLSLDX - smlsldx${p}	$Ra, $Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMMLA (4199) - ARM_INS_SMMLA - smmla${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMMLAR (4200) - ARM_INS_SMMLAR - smmlar${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMMLS (4201) - ARM_INS_SMMLS - smmls${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMMLSR (4202) - ARM_INS_SMMLSR - smmlsr${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMMUL (4203) - ARM_INS_SMMUL - smmul${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMMULR (4204) - ARM_INS_SMMULR - smmulr${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMUAD (4205) - ARM_INS_SMUAD - smuad${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMUADX (4206) - ARM_INS_SMUADX - smuadx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULBB (4207) - ARM_INS_SMULBB - smulbb${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULBT (4208) - ARM_INS_SMULBT - smulbt${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULL (4209) - ARM_INS_SMULL - smull${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULTB (4210) - ARM_INS_SMULTB - smultb${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULTT (4211) - ARM_INS_SMULTT - smultt${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULWB (4212) - ARM_INS_SMULWB - smulwb${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMULWT (4213) - ARM_INS_SMULWT - smulwt${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMUSD (4214) - ARM_INS_SMUSD - smusd${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SMUSDX (4215) - ARM_INS_SMUSDX - smusdx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SRSDB (4216) - ARM_INS_SRSDB - srsdb${p}	sp, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SRSDB_UPD (4217) - ARM_INS_SRSDB - srsdb${p}	sp!, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SRSIA (4218) - ARM_INS_SRSIA - srsia${p}	sp, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SRSIA_UPD (4219) - ARM_INS_SRSIA - srsia${p}	sp!, $mode */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* mode */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SSAT (4220) - ARM_INS_SSAT - ssat${p}	$Rd, $sat_imm, $Rn$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SSAT16 (4221) - ARM_INS_SSAT16 - ssat16${p}	$Rd, $sat_imm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SSAX (4222) - ARM_INS_SSAX - ssax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SSUB16 (4223) - ARM_INS_SSUB16 - ssub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SSUB8 (4224) - ARM_INS_SSUB8 - ssub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2L_OFFSET (4225) - ARM_INS_STC2L - stc2l${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2L_OPTION (4226) - ARM_INS_STC2L - stc2l${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2L_POST (4227) - ARM_INS_STC2L - stc2l${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2L_PRE (4228) - ARM_INS_STC2L - stc2l${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2_OFFSET (4229) - ARM_INS_STC2 - stc2${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2_OPTION (4230) - ARM_INS_STC2 - stc2${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2_POST (4231) - ARM_INS_STC2 - stc2${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC2_PRE (4232) - ARM_INS_STC2 - stc2${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STCL_OFFSET (4233) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STCL_OPTION (4234) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STCL_POST (4235) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STCL_PRE (4236) - ARM_INS_STCL - stcl${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC_OFFSET (4237) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC_OPTION (4238) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr, $option */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* option */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC_POST (4239) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr, $offset */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STC_PRE (4240) - ARM_INS_STC - stc${p}	$cop, $CRd, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* cop */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* CRd */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STL (4241) - ARM_INS_STL - stl${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STLB (4242) - ARM_INS_STLB - stlb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STLEX (4243) - ARM_INS_STLEX - stlex${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STLEXB (4244) - ARM_INS_STLEXB - stlexb${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STLEXD (4245) - ARM_INS_STLEXD - stlexd${p}	$Rd, $Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STLEXH (4246) - ARM_INS_STLEXH - stlexh${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STLH (4247) - ARM_INS_STLH - stlh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STMDB (4248) - ARM_INS_STMDB - stmdb${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2STMDB_UPD (4249) - ARM_INS_STMDB - stmdb${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2STMIA (4250) - ARM_INS_STM - stm${p}.w	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2STMIA_UPD (4251) - ARM_INS_STM - stm${p}.w	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_t2STRBT (4252) - ARM_INS_STRBT - strbt${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRB_POST (4253) - ARM_INS_STRB - strb${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRB_PRE (4254) - ARM_INS_STRB - strb${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRBi12 (4255) - ARM_INS_STRB - strb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRBi8 (4256) - ARM_INS_STRB - strb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRBs (4257) - ARM_INS_STRB - strb${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRD_POST (4258) - ARM_INS_STRD - strd${p}	$Rt, $Rt2, $addr$imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRD_PRE (4259) - ARM_INS_STRD - strd${p}	$Rt, $Rt2, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRDi8 (4260) - ARM_INS_STRD - strd${p}	$Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STREX (4261) - ARM_INS_STREX - strex${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STREXB (4262) - ARM_INS_STREXB - strexb${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STREXD (4263) - ARM_INS_STREXD - strexd${p}	$Rd, $Rt, $Rt2, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt2 */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STREXH (4264) - ARM_INS_STREXH - strexh${p}	$Rd, $Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRHT (4265) - ARM_INS_STRHT - strht${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRH_POST (4266) - ARM_INS_STRH - strh${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRH_PRE (4267) - ARM_INS_STRH - strh${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRHi12 (4268) - ARM_INS_STRH - strh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRHi8 (4269) - ARM_INS_STRH - strh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRHs (4270) - ARM_INS_STRH - strh${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRT (4271) - ARM_INS_STRT - strt${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STR_POST (4272) - ARM_INS_STR - str${p}	$Rt, $Rn$offset */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* offset */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STR_PRE (4273) - ARM_INS_STR - str${p}	$Rt, $addr! */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn_wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRi12 (4274) - ARM_INS_STR - str${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRi8 (4275) - ARM_INS_STR - str${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2STRs (4276) - ARM_INS_STR - str${p}.w	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPRnopc */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SUBS_PC_LR (4277) - ARM_INS_SUBS - subs${p}	pc, lr, $imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SUBri (4278) - ARM_INS_SUB - sub${s}${p}.w	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SUBri12 (4279) - ARM_INS_SUBW - subw${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SUBrr (4280) - ARM_INS_SUB - sub${s}${p}.w	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SUBrs (4281) - ARM_INS_SUB - sub${s}${p}.w	$Rd, $Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SUBspImm (4282) - ARM_INS_SUB - sub${s}${p}.w	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { 0 }
+}},
+{ /* ARM_t2SUBspImm12 (4283) - ARM_INS_SUBW - subw${p}	$Rd, $Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SXTAB (4284) - ARM_INS_SXTAB - sxtab${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SXTAB16 (4285) - ARM_INS_SXTAB16 - sxtab16${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SXTAH (4286) - ARM_INS_SXTAH - sxtah${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SXTB (4287) - ARM_INS_SXTB - sxtb${p}.w	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SXTB16 (4288) - ARM_INS_SXTB16 - sxtb16${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2SXTH (4289) - ARM_INS_SXTH - sxth${p}.w	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TBB (4290) - ARM_INS_TBB - tbb${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TBH (4291) - ARM_INS_TBH - tbh${p}	$addr */
+{
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TEQri (4292) - ARM_INS_TEQ - teq${p}.w	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TEQrr (4293) - ARM_INS_TEQ - teq${p}.w	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TEQrs (4294) - ARM_INS_TEQ - teq${p}.w	$Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TSB (4295) - ARM_INS_TSB - tsb${p}	$opt */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* opt */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TSTri (4296) - ARM_INS_TST - tst${p}.w	$Rn, $imm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TSTrr (4297) - ARM_INS_TST - tst${p}.w	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TSTrs (4298) - ARM_INS_TST - tst${p}.w	$Rn, $ShiftedRm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - rGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* ShiftedRm - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TT (4299) - ARM_INS_TT - tt${p}	$Rt, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TTA (4300) - ARM_INS_TTA - tta${p}	$Rt, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TTAT (4301) - ARM_INS_TTAT - ttat${p}	$Rt, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2TTT (4302) - ARM_INS_TTT - ttt${p}	$Rt, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UADD16 (4303) - ARM_INS_UADD16 - uadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UADD8 (4304) - ARM_INS_UADD8 - uadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UASX (4305) - ARM_INS_UASX - uasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UBFX (4306) - ARM_INS_UBFX - ubfx${p}	$Rd, $Rn, $lsb, $msb */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* lsb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* msb */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UDF (4307) - ARM_INS_UDF - udf.w	$imm16 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm16 */
+  { 0 }
+}},
+{ /* ARM_t2UDIV (4308) - ARM_INS_UDIV - udiv${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UHADD16 (4309) - ARM_INS_UHADD16 - uhadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UHADD8 (4310) - ARM_INS_UHADD8 - uhadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UHASX (4311) - ARM_INS_UHASX - uhasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UHSAX (4312) - ARM_INS_UHSAX - uhsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UHSUB16 (4313) - ARM_INS_UHSUB16 - uhsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UHSUB8 (4314) - ARM_INS_UHSUB8 - uhsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UMAAL (4315) - ARM_INS_UMAAL - umaal${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UMLAL (4316) - ARM_INS_UMLAL - umlal${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RLo */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RHi */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UMULL (4317) - ARM_INS_UMULL - umull${p}	$RdLo, $RdHi, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdLo */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* RdHi */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UQADD16 (4318) - ARM_INS_UQADD16 - uqadd16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UQADD8 (4319) - ARM_INS_UQADD8 - uqadd8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UQASX (4320) - ARM_INS_UQASX - uqasx${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UQSAX (4321) - ARM_INS_UQSAX - uqsax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UQSUB16 (4322) - ARM_INS_UQSUB16 - uqsub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UQSUB8 (4323) - ARM_INS_UQSUB8 - uqsub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USAD8 (4324) - ARM_INS_USAD8 - usad8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USADA8 (4325) - ARM_INS_USADA8 - usada8${p}	$Rd, $Rn, $Rm, $Ra */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Ra */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USAT (4326) - ARM_INS_USAT - usat${p}	$Rd, $sat_imm, $Rn$sh */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sh */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USAT16 (4327) - ARM_INS_USAT16 - usat16${p}	$Rd, $sat_imm, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sat_imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USAX (4328) - ARM_INS_USAX - usax${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USUB16 (4329) - ARM_INS_USUB16 - usub16${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2USUB8 (4330) - ARM_INS_USUB8 - usub8${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UXTAB (4331) - ARM_INS_UXTAB - uxtab${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UXTAB16 (4332) - ARM_INS_UXTAB16 - uxtab16${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UXTAH (4333) - ARM_INS_UXTAH - uxtah${p}	$Rd, $Rn, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UXTB (4334) - ARM_INS_UXTB - uxtb${p}.w	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UXTB16 (4335) - ARM_INS_UXTB16 - uxtb16${p}	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2UXTH (4336) - ARM_INS_UXTH - uxth${p}.w	$Rd, $Rm$rot */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* rot */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t2WLS (4337) - ARM_INS_WLS - wls	$LR, $Rn, $label */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* LR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* label */
+  { 0 }
+}},
+{ /* ARM_tADC (4338) - ARM_INS_ADC - adc${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDhirr (4339) - ARM_INS_ADD - add${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDi3 (4340) - ARM_INS_ADD - add${s}${p}	$Rd, $Rm, $imm3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDi8 (4341) - ARM_INS_ADD - add${s}${p}	$Rdn, $imm8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDrSP (4342) - ARM_INS_ADD - add${p}	$Rdn, $sp, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sp */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDrSPi (4343) - ARM_INS_ADD - add${p}	$dst, $sp, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* dst */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* sp */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDrr (4344) - ARM_INS_ADD - add${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDspi (4345) - ARM_INS_ADD - add${p}	$Rdn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADDspr (4346) - ARM_INS_ADD - add${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tADR (4347) - ARM_INS_ADR - adr{$p}	$Rd, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tAND (4348) - ARM_INS_AND - and${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tASRri (4349) - ARM_INS_ASR - asr${s}${p}	$Rd, $Rm, $imm5 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm5 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tASRrr (4350) - ARM_INS_ASR - asr${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tB (4351) - ARM_INS_B - b${p}	$target */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tBIC (4352) - ARM_INS_BIC - bic${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tBKPT (4353) - ARM_INS_BKPT - bkpt	$val */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */
+  { 0 }
+}},
+{ /* ARM_tBL (4354) - ARM_INS_BL - bl${p}	$func */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { 0 }
+}},
+{ /* ARM_tBLXNSr (4355) - ARM_INS_BLXNS - blxns${p}	$func */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { 0 }
+}},
+{ /* ARM_tBLXi (4356) - ARM_INS_BLX - blx${p}	$func */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { 0 }
+}},
+{ /* ARM_tBLXr (4357) - ARM_INS_BLX - blx${p}	$func */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* func */
+  { 0 }
+}},
+{ /* ARM_tBX (4358) - ARM_INS_BX - bx${p}	$Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tBXNS (4359) - ARM_INS_BXNS - bxns${p}	$Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tBcc (4360) - ARM_INS_B - b${p}	$target */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tCBNZ (4361) - ARM_INS_CBNZ - cbnz	$Rn, $target */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { 0 }
+}},
+{ /* ARM_tCBZ (4362) - ARM_INS_CBZ - cbz	$Rn, $target */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_Other, CS_DATA_TYPE_LAST } }, /* target */
+  { 0 }
+}},
+{ /* ARM_tCMNz (4363) - ARM_INS_CMN - cmn${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tCMPhir (4364) - ARM_INS_CMP - cmp${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tCMPi8 (4365) - ARM_INS_CMP - cmp${p}	$Rn, $imm8 */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tCMPr (4366) - ARM_INS_CMP - cmp${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tCPS (4367) - ARM_INS_CPS - cps$imod $iflags */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imod */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* iflags */
+  { 0 }
+}},
+{ /* ARM_tEOR (4368) - ARM_INS_EOR - eor${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tHINT (4369) - ARM_INS_HINT - hint${p}	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tHLT (4370) - ARM_INS_HLT - hlt	$val */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* val */
+  { 0 }
+}},
+{{{ /* ARM_tInt_WIN_eh_sjlj_longjmp (4371) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tInt_eh_sjlj_longjmp (4372) - ARM_INS_INVALID -  */
+ 0
+}}},
+{{{ /* ARM_tInt_eh_sjlj_setjmp (4373) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_tLDMIA (4374) - ARM_INS_LDM - ldm${p}	$Rn, $regs */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_tLDRBi (4375) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRBr (4376) - ARM_INS_LDRB - ldrb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRHi (4377) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRHr (4378) - ARM_INS_LDRH - ldrh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRSB (4379) - ARM_INS_LDRSB - ldrsb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRSH (4380) - ARM_INS_LDRSH - ldrsh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRi (4381) - ARM_INS_LDR - ldr${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRpci (4382) - ARM_INS_LDR - ldr${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRr (4383) - ARM_INS_LDR - ldr${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLDRspi (4384) - ARM_INS_LDR - ldr${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLSLri (4385) - ARM_INS_LSL - lsl${s}${p}	$Rd, $Rm, $imm5 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm5 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLSLrr (4386) - ARM_INS_LSL - lsl${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLSRri (4387) - ARM_INS_LSR - lsr${s}${p}	$Rd, $Rm, $imm5 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm5 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tLSRrr (4388) - ARM_INS_LSR - lsr${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tMOVSr (4389) - ARM_INS_MOVS - movs	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { 0 }
+}},
+{ /* ARM_tMOVi8 (4390) - ARM_INS_MOV - mov${s}${p}	$Rd, $imm8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tMOVr (4391) - ARM_INS_MOV - mov${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tMUL (4392) - ARM_INS_MUL - mul${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tMVN (4393) - ARM_INS_MVN - mvn${s}${p}	$Rd, $Rn */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tORR (4394) - ARM_INS_ORR - orr${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{{{ /* ARM_tPICADD (4395) - ARM_INS_INVALID -  */
+ 0
+}}},
+{ /* ARM_tPOP (4396) - ARM_INS_POP - pop${p}	$regs */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_tPUSH (4397) - ARM_INS_PUSH - push${p}	$regs */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_tREV (4398) - ARM_INS_REV - rev${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tREV16 (4399) - ARM_INS_REV16 - rev16${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tREVSH (4400) - ARM_INS_REVSH - revsh${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tROR (4401) - ARM_INS_ROR - ror${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tRSB (4402) - ARM_INS_RSB - rsb${s}${p}	$Rd, $Rn, #0 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSBC (4403) - ARM_INS_SBC - sbc${s}${p}	$Rdn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSETEND (4404) - ARM_INS_SETEND - setend	$end */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* end */
+  { 0 }
+}},
+{ /* ARM_tSTMIA_UPD (4405) - ARM_INS_STM - stm${p}	$Rn!, $regs */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* wb */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+  { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+  { 0 }
+}},
+{ /* ARM_tSTRBi (4406) - ARM_INS_STRB - strb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSTRBr (4407) - ARM_INS_STRB - strb${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSTRHi (4408) - ARM_INS_STRH - strh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSTRHr (4409) - ARM_INS_STRH - strh${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSTRi (4410) - ARM_INS_STR - str${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSTRr (4411) - ARM_INS_STR - str${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_READ | CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - tGPR */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSTRspi (4412) - ARM_INS_STR - str${p}	$Rt, $addr */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rt */
+  { CS_OP_MEM | CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - GPR */
+  { CS_OP_MEM | CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* addr - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSUBi3 (4413) - ARM_INS_SUB - sub${s}${p}	$Rd, $Rm, $imm3 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm3 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSUBi8 (4414) - ARM_INS_SUB - sub${s}${p}	$Rdn, $imm8 */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSUBrr (4415) - ARM_INS_SUB - sub${s}${p}	$Rd, $Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* s - CCR */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSUBspi (4416) - ARM_INS_SUB - sub${p}	$Rdn, $imm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rdn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSVC (4417) - ARM_INS_SVC - svc${p}	$imm */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSXTB (4418) - ARM_INS_SXTB - sxtb${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tSXTH (4419) - ARM_INS_SXTH - sxth${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tTRAP (4420) - ARM_INS_TRAP - trap */
+{
+  { 0 }
+}},
+{ /* ARM_tTST (4421) - ARM_INS_TST - tst${p}	$Rn, $Rm */
+{
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tUDF (4422) - ARM_INS_UDF - udf	$imm8 */
+{
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* imm8 */
+  { 0 }
+}},
+{ /* ARM_tUXTB (4423) - ARM_INS_UXTB - uxtb${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_tUXTH (4424) - ARM_INS_UXTH - uxth${p}	$Rd, $Rm */
+{
+  { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rd */
+  { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+  { 0 }
+}},
+{ /* ARM_t__brkdiv0 (4425) - ARM_INS___BRKDIV0 - __brkdiv0 */
+{
+  { 0 }
+}},
diff --git a/arch/ARM/ARMGenCSOpGroup.inc b/arch/ARM/ARMGenCSOpGroup.inc
new file mode 100644
index 000000000..494c410a0
--- /dev/null
+++ b/arch/ARM/ARMGenCSOpGroup.inc
@@ -0,0 +1,115 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARM_OP_GROUP_RegImmShift = 0,
+  ARM_OP_GROUP_LdStmModeOperand = 1,
+  ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 2,
+  ARM_OP_GROUP_Operand = 3,
+  ARM_OP_GROUP_ModImmOperand = 4,
+  ARM_OP_GROUP_PredicateOperand = 5,
+  ARM_OP_GROUP_SORegImmOperand = 6,
+  ARM_OP_GROUP_SORegRegOperand = 7,
+  ARM_OP_GROUP_SBitModifierOperand = 8,
+  ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
+  ARM_OP_GROUP_AddrMode2Operand = 10,
+  ARM_OP_GROUP_CPInstOperand = 11,
+  ARM_OP_GROUP_MandatoryPredicateOperand = 12,
+  ARM_OP_GROUP_ThumbITMask = 13,
+  ARM_OP_GROUP_RegisterList = 14,
+  ARM_OP_GROUP_AddrMode7Operand = 15,
+  ARM_OP_GROUP_GPRPairOperand = 16,
+  ARM_OP_GROUP_AddrMode3Operand_0 = 17,
+  ARM_OP_GROUP_PCLabel = 18,
+  ARM_OP_GROUP_AddrModePCOperand = 19,
+  ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
+  ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
+  ARM_OP_GROUP_AddrMode6Operand = 22,
+  ARM_OP_GROUP_VectorListThreeAllLanes = 23,
+  ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24,
+  ARM_OP_GROUP_VectorListThree = 25,
+  ARM_OP_GROUP_VectorListThreeSpaced = 26,
+  ARM_OP_GROUP_VectorListFourAllLanes = 27,
+  ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
+  ARM_OP_GROUP_VectorListFour = 29,
+  ARM_OP_GROUP_VectorListFourSpaced = 30,
+  ARM_OP_GROUP_T2SOOperand = 31,
+  ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 32,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 33,
+  ARM_OP_GROUP_AdrLabelOperand_0 = 34,
+  ARM_OP_GROUP_VectorIndex = 35,
+  ARM_OP_GROUP_BitfieldInvMaskImmOperand = 36,
+  ARM_OP_GROUP_PImmediate = 37,
+  ARM_OP_GROUP_VPTPredicateOperand = 38,
+  ARM_OP_GROUP_CImmediate = 39,
+  ARM_OP_GROUP_CPSIMod = 40,
+  ARM_OP_GROUP_CPSIFlag = 41,
+  ARM_OP_GROUP_MemBOption = 42,
+  ARM_OP_GROUP_FPImmOperand = 43,
+  ARM_OP_GROUP_InstSyncBOption = 44,
+  ARM_OP_GROUP_AddrMode5Operand_0 = 45,
+  ARM_OP_GROUP_CoprocOptionImm = 46,
+  ARM_OP_GROUP_PostIdxImm8s4Operand = 47,
+  ARM_OP_GROUP_AddrMode5Operand_1 = 48,
+  ARM_OP_GROUP_AddrModeImm12Operand_1 = 49,
+  ARM_OP_GROUP_AddrMode3Operand_1 = 50,
+  ARM_OP_GROUP_PostIdxImm8Operand = 51,
+  ARM_OP_GROUP_PostIdxRegOperand = 52,
+  ARM_OP_GROUP_BankedRegOperand = 53,
+  ARM_OP_GROUP_MSRMaskOperand = 54,
+  ARM_OP_GROUP_MveSaturateOp = 55,
+  ARM_OP_GROUP_VMOVModImmOperand = 56,
+  ARM_OP_GROUP_ComplexRotationOp_180_90 = 57,
+  ARM_OP_GROUP_ComplexRotationOp_90_0 = 58,
+  ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 59,
+  ARM_OP_GROUP_MVEVectorList_2 = 60,
+  ARM_OP_GROUP_MVEVectorList_4 = 61,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 62,
+  ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
+  ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
+  ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
+  ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66,
+  ARM_OP_GROUP_VPTMask = 67,
+  ARM_OP_GROUP_PKHLSLShiftImm = 68,
+  ARM_OP_GROUP_PKHASRShiftImm = 69,
+  ARM_OP_GROUP_ImmPlusOneOperand = 70,
+  ARM_OP_GROUP_SetendOperand = 71,
+  ARM_OP_GROUP_ShiftImmOperand = 72,
+  ARM_OP_GROUP_RotImmOperand = 73,
+  ARM_OP_GROUP_TraceSyncBOption = 74,
+  ARM_OP_GROUP_VectorListOneAllLanes = 75,
+  ARM_OP_GROUP_VectorListTwoAllLanes = 76,
+  ARM_OP_GROUP_NoHashImmediate = 77,
+  ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
+  ARM_OP_GROUP_VectorListOne = 79,
+  ARM_OP_GROUP_VectorListTwo = 80,
+  ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
+  ARM_OP_GROUP_VectorListTwoSpaced = 82,
+  ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
+  ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86,
+  ARM_OP_GROUP_FBits16 = 87,
+  ARM_OP_GROUP_FBits32 = 88,
+  ARM_OP_GROUP_ThumbSRImm = 89,
+  ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
+  ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
+  ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
+  ARM_OP_GROUP_AddrModeTBB = 93,
+  ARM_OP_GROUP_AddrModeTBH = 94,
+  ARM_OP_GROUP_ThumbS4ImmOperand = 95,
+  ARM_OP_GROUP_AdrLabelOperand_2 = 96,
+  ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
+  ARM_OP_GROUP_ThumbAddrModeRROperand = 98,
+  ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99,
+  ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100,
+  ARM_OP_GROUP_ThumbAddrModeSPOperand = 101,
diff --git a/arch/ARM/ARMGenDisassemblerTables.inc b/arch/ARM/ARMGenDisassemblerTables.inc
index 385a7d555..cbde13e5e 100644
--- a/arch/ARM/ARMGenDisassemblerTables.inc
+++ b/arch/ARM/ARMGenDisassemblerTables.inc
@@ -1,17 +1,20 @@
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-/* Automatically generated file, do not edit! */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
 
 #include "../../MCInst.h"
 #include "../../LEB128.h"
 
-
 // Helper function for extracting fields from encoded instructions.
-
-//#if defined(_MSC_VER) && !defined(__clang__)
-//__declspec(noinline)
-//#endif
-
 #define FieldFromInstruction(fname, InsnType) \
 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
 { \
@@ -36,86 +39,86 @@ static const uint8_t DecoderTableARM32[] = {
 /* 35 */      MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 65
 /* 40 */      MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 56
 /* 45 */      MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 56
-/* 52 */      MCD_OPC_Decode, 159, 4, 0, // Opcode: ANDrr
-/* 56 */      MCD_OPC_CheckPredicate, 0, 92, 32, 0, // Skip to: 8345
-/* 61 */      MCD_OPC_Decode, 160, 4, 1, // Opcode: ANDrsi
+/* 52 */      MCD_OPC_Decode, 211, 5, 0, // Opcode: ANDrr
+/* 56 */      MCD_OPC_CheckPredicate, 0, 128, 32, 0, // Skip to: 8381
+/* 61 */      MCD_OPC_Decode, 212, 5, 1, // Opcode: ANDrsi
 /* 65 */      MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 95
 /* 70 */      MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 86
 /* 75 */      MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 86
-/* 82 */      MCD_OPC_Decode, 245, 6, 0, // Opcode: SUBrr
-/* 86 */      MCD_OPC_CheckPredicate, 0, 62, 32, 0, // Skip to: 8345
-/* 91 */      MCD_OPC_Decode, 246, 6, 1, // Opcode: SUBrsi
+/* 82 */      MCD_OPC_Decode, 160, 15, 0, // Opcode: SUBrr
+/* 86 */      MCD_OPC_CheckPredicate, 0, 98, 32, 0, // Skip to: 8381
+/* 91 */      MCD_OPC_Decode, 161, 15, 1, // Opcode: SUBrsi
 /* 95 */      MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 125
 /* 100 */     MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 116
 /* 105 */     MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 116
-/* 112 */     MCD_OPC_Decode, 150, 4, 0, // Opcode: ADDrr
-/* 116 */     MCD_OPC_CheckPredicate, 0, 32, 32, 0, // Skip to: 8345
-/* 121 */     MCD_OPC_Decode, 151, 4, 1, // Opcode: ADDrsi
-/* 125 */     MCD_OPC_FilterValue, 3, 23, 32, 0, // Skip to: 8345
+/* 112 */     MCD_OPC_Decode, 202, 5, 0, // Opcode: ADDrr
+/* 116 */     MCD_OPC_CheckPredicate, 0, 68, 32, 0, // Skip to: 8381
+/* 121 */     MCD_OPC_Decode, 203, 5, 1, // Opcode: ADDrsi
+/* 125 */     MCD_OPC_FilterValue, 3, 59, 32, 0, // Skip to: 8381
 /* 130 */     MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 146
 /* 135 */     MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 146
-/* 142 */     MCD_OPC_Decode, 239, 5, 0, // Opcode: SBCrr
-/* 146 */     MCD_OPC_CheckPredicate, 0, 2, 32, 0, // Skip to: 8345
-/* 151 */     MCD_OPC_Decode, 240, 5, 1, // Opcode: SBCrsi
-/* 155 */     MCD_OPC_FilterValue, 1, 249, 31, 0, // Skip to: 8345
+/* 142 */     MCD_OPC_Decode, 154, 14, 0, // Opcode: SBCrr
+/* 146 */     MCD_OPC_CheckPredicate, 0, 38, 32, 0, // Skip to: 8381
+/* 151 */     MCD_OPC_Decode, 155, 14, 1, // Opcode: SBCrsi
+/* 155 */     MCD_OPC_FilterValue, 1, 29, 32, 0, // Skip to: 8381
 /* 160 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 163 */     MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 227
 /* 168 */     MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
 /* 171 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 185
-/* 176 */     MCD_OPC_CheckPredicate, 0, 228, 31, 0, // Skip to: 8345
-/* 181 */     MCD_OPC_Decode, 161, 4, 2, // Opcode: ANDrsr
+/* 176 */     MCD_OPC_CheckPredicate, 0, 8, 32, 0, // Skip to: 8381
+/* 181 */     MCD_OPC_Decode, 213, 5, 2, // Opcode: ANDrsr
 /* 185 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 199
-/* 190 */     MCD_OPC_CheckPredicate, 0, 214, 31, 0, // Skip to: 8345
-/* 195 */     MCD_OPC_Decode, 247, 6, 2, // Opcode: SUBrsr
+/* 190 */     MCD_OPC_CheckPredicate, 0, 250, 31, 0, // Skip to: 8381
+/* 195 */     MCD_OPC_Decode, 162, 15, 2, // Opcode: SUBrsr
 /* 199 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 213
-/* 204 */     MCD_OPC_CheckPredicate, 0, 200, 31, 0, // Skip to: 8345
-/* 209 */     MCD_OPC_Decode, 152, 4, 2, // Opcode: ADDrsr
-/* 213 */     MCD_OPC_FilterValue, 3, 191, 31, 0, // Skip to: 8345
-/* 218 */     MCD_OPC_CheckPredicate, 0, 186, 31, 0, // Skip to: 8345
-/* 223 */     MCD_OPC_Decode, 241, 5, 3, // Opcode: SBCrsr
-/* 227 */     MCD_OPC_FilterValue, 1, 177, 31, 0, // Skip to: 8345
+/* 204 */     MCD_OPC_CheckPredicate, 0, 236, 31, 0, // Skip to: 8381
+/* 209 */     MCD_OPC_Decode, 204, 5, 2, // Opcode: ADDrsr
+/* 213 */     MCD_OPC_FilterValue, 3, 227, 31, 0, // Skip to: 8381
+/* 218 */     MCD_OPC_CheckPredicate, 0, 222, 31, 0, // Skip to: 8381
+/* 223 */     MCD_OPC_Decode, 156, 14, 3, // Opcode: SBCrsr
+/* 227 */     MCD_OPC_FilterValue, 1, 213, 31, 0, // Skip to: 8381
 /* 232 */     MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
 /* 235 */     MCD_OPC_FilterValue, 0, 71, 0, 0, // Skip to: 311
 /* 240 */     MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
 /* 243 */     MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 262
-/* 248 */     MCD_OPC_CheckPredicate, 1, 156, 31, 0, // Skip to: 8345
+/* 248 */     MCD_OPC_CheckPredicate, 1, 192, 31, 0, // Skip to: 8381
 /* 253 */     MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 258 */     MCD_OPC_Decode, 188, 5, 4, // Opcode: MUL
+/* 258 */     MCD_OPC_Decode, 149, 7, 4, // Opcode: MUL
 /* 262 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 283
-/* 267 */     MCD_OPC_CheckPredicate, 1, 137, 31, 0, // Skip to: 8345
-/* 272 */     MCD_OPC_CheckField, 20, 1, 0, 130, 31, 0, // Skip to: 8345
-/* 279 */     MCD_OPC_Decode, 152, 7, 5, // Opcode: UMAAL
+/* 267 */     MCD_OPC_CheckPredicate, 1, 173, 31, 0, // Skip to: 8381
+/* 272 */     MCD_OPC_CheckField, 20, 1, 0, 166, 31, 0, // Skip to: 8381
+/* 279 */     MCD_OPC_Decode, 195, 15, 5, // Opcode: UMAAL
 /* 283 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 297
-/* 288 */     MCD_OPC_CheckPredicate, 1, 116, 31, 0, // Skip to: 8345
-/* 293 */     MCD_OPC_Decode, 154, 7, 6, // Opcode: UMULL
-/* 297 */     MCD_OPC_FilterValue, 3, 107, 31, 0, // Skip to: 8345
-/* 302 */     MCD_OPC_CheckPredicate, 1, 102, 31, 0, // Skip to: 8345
-/* 307 */     MCD_OPC_Decode, 165, 6, 6, // Opcode: SMULL
+/* 288 */     MCD_OPC_CheckPredicate, 1, 152, 31, 0, // Skip to: 8381
+/* 293 */     MCD_OPC_Decode, 197, 15, 6, // Opcode: UMULL
+/* 297 */     MCD_OPC_FilterValue, 3, 143, 31, 0, // Skip to: 8381
+/* 302 */     MCD_OPC_CheckPredicate, 1, 138, 31, 0, // Skip to: 8381
+/* 307 */     MCD_OPC_Decode, 208, 14, 6, // Opcode: SMULL
 /* 311 */     MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 347
 /* 316 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 319 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 333
-/* 324 */     MCD_OPC_CheckPredicate, 0, 80, 31, 0, // Skip to: 8345
-/* 329 */     MCD_OPC_Decode, 234, 6, 7, // Opcode: STRH_POST
-/* 333 */     MCD_OPC_FilterValue, 1, 71, 31, 0, // Skip to: 8345
-/* 338 */     MCD_OPC_CheckPredicate, 0, 66, 31, 0, // Skip to: 8345
-/* 343 */     MCD_OPC_Decode, 143, 5, 7, // Opcode: LDRH_POST
+/* 324 */     MCD_OPC_CheckPredicate, 0, 116, 31, 0, // Skip to: 8381
+/* 329 */     MCD_OPC_Decode, 149, 15, 7, // Opcode: STRH_POST
+/* 333 */     MCD_OPC_FilterValue, 1, 107, 31, 0, // Skip to: 8381
+/* 338 */     MCD_OPC_CheckPredicate, 0, 102, 31, 0, // Skip to: 8381
+/* 343 */     MCD_OPC_Decode, 232, 6, 7, // Opcode: LDRH_POST
 /* 347 */     MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 383
 /* 352 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 355 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 369
-/* 360 */     MCD_OPC_CheckPredicate, 0, 44, 31, 0, // Skip to: 8345
-/* 365 */     MCD_OPC_Decode, 134, 5, 7, // Opcode: LDRD_POST
-/* 369 */     MCD_OPC_FilterValue, 1, 35, 31, 0, // Skip to: 8345
-/* 374 */     MCD_OPC_CheckPredicate, 0, 30, 31, 0, // Skip to: 8345
-/* 379 */     MCD_OPC_Decode, 148, 5, 7, // Opcode: LDRSB_POST
-/* 383 */     MCD_OPC_FilterValue, 3, 21, 31, 0, // Skip to: 8345
+/* 360 */     MCD_OPC_CheckPredicate, 0, 80, 31, 0, // Skip to: 8381
+/* 365 */     MCD_OPC_Decode, 223, 6, 7, // Opcode: LDRD_POST
+/* 369 */     MCD_OPC_FilterValue, 1, 71, 31, 0, // Skip to: 8381
+/* 374 */     MCD_OPC_CheckPredicate, 0, 66, 31, 0, // Skip to: 8381
+/* 379 */     MCD_OPC_Decode, 237, 6, 7, // Opcode: LDRSB_POST
+/* 383 */     MCD_OPC_FilterValue, 3, 57, 31, 0, // Skip to: 8381
 /* 388 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 391 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 405
-/* 396 */     MCD_OPC_CheckPredicate, 0, 8, 31, 0, // Skip to: 8345
-/* 401 */     MCD_OPC_Decode, 225, 6, 7, // Opcode: STRD_POST
-/* 405 */     MCD_OPC_FilterValue, 1, 255, 30, 0, // Skip to: 8345
-/* 410 */     MCD_OPC_CheckPredicate, 0, 250, 30, 0, // Skip to: 8345
-/* 415 */     MCD_OPC_Decode, 153, 5, 7, // Opcode: LDRSH_POST
-/* 419 */     MCD_OPC_FilterValue, 1, 241, 30, 0, // Skip to: 8345
+/* 396 */     MCD_OPC_CheckPredicate, 0, 44, 31, 0, // Skip to: 8381
+/* 401 */     MCD_OPC_Decode, 140, 15, 7, // Opcode: STRD_POST
+/* 405 */     MCD_OPC_FilterValue, 1, 35, 31, 0, // Skip to: 8381
+/* 410 */     MCD_OPC_CheckPredicate, 0, 30, 31, 0, // Skip to: 8381
+/* 415 */     MCD_OPC_Decode, 242, 6, 7, // Opcode: LDRSH_POST
+/* 419 */     MCD_OPC_FilterValue, 1, 21, 31, 0, // Skip to: 8381
 /* 424 */     MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
 /* 427 */     MCD_OPC_FilterValue, 0, 6, 2, 0, // Skip to: 950
 /* 432 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
@@ -130,35 +133,35 @@ static const uint8_t DecoderTableARM32[] = {
 /* 469 */     MCD_OPC_CheckField, 6, 2, 1, 164, 0, 0, // Skip to: 640
 /* 476 */     MCD_OPC_CheckField, 4, 1, 0, 157, 0, 0, // Skip to: 640
 /* 483 */     MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0,
-/* 487 */     MCD_OPC_Decode, 194, 4, 8, // Opcode: CRC32B
+/* 487 */     MCD_OPC_Decode, 155, 6, 8, // Opcode: CRC32B
 /* 491 */     MCD_OPC_FilterValue, 1, 144, 0, 0, // Skip to: 640
 /* 496 */     MCD_OPC_CheckPredicate, 2, 139, 0, 0, // Skip to: 640
 /* 501 */     MCD_OPC_CheckField, 6, 2, 1, 132, 0, 0, // Skip to: 640
 /* 508 */     MCD_OPC_CheckField, 4, 1, 0, 125, 0, 0, // Skip to: 640
 /* 515 */     MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0,
-/* 519 */     MCD_OPC_Decode, 195, 4, 8, // Opcode: CRC32CB
+/* 519 */     MCD_OPC_Decode, 156, 6, 8, // Opcode: CRC32CB
 /* 523 */     MCD_OPC_FilterValue, 15, 112, 0, 0, // Skip to: 640
 /* 528 */     MCD_OPC_ExtractField, 10, 8,  // Inst{17-10} ...
 /* 531 */     MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 559
 /* 536 */     MCD_OPC_CheckPredicate, 0, 99, 0, 0, // Skip to: 640
 /* 541 */     MCD_OPC_CheckField, 9, 1, 0, 92, 0, 0, // Skip to: 640
 /* 548 */     MCD_OPC_CheckField, 0, 5, 0, 85, 0, 0, // Skip to: 640
-/* 555 */     MCD_OPC_Decode, 192, 4, 9, // Opcode: CPS2p
+/* 555 */     MCD_OPC_Decode, 153, 6, 9, // Opcode: CPS2p
 /* 559 */     MCD_OPC_FilterValue, 64, 30, 0, 0, // Skip to: 594
 /* 564 */     MCD_OPC_CheckPredicate, 0, 71, 0, 0, // Skip to: 640
 /* 569 */     MCD_OPC_CheckField, 18, 2, 0, 64, 0, 0, // Skip to: 640
 /* 576 */     MCD_OPC_CheckField, 6, 3, 0, 57, 0, 0, // Skip to: 640
 /* 583 */     MCD_OPC_CheckField, 0, 5, 0, 50, 0, 0, // Skip to: 640
-/* 590 */     MCD_OPC_Decode, 245, 5, 10, // Opcode: SETEND
+/* 590 */     MCD_OPC_Decode, 160, 14, 10, // Opcode: SETEND
 /* 594 */     MCD_OPC_FilterValue, 128, 1, 40, 0, 0, // Skip to: 640
 /* 600 */     MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 603 */     MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 640
 /* 608 */     MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 631
 /* 613 */     MCD_OPC_CheckField, 18, 2, 0, 11, 0, 0, // Skip to: 631
 /* 620 */     MCD_OPC_CheckField, 6, 3, 0, 4, 0, 0, // Skip to: 631
-/* 627 */     MCD_OPC_Decode, 191, 4, 9, // Opcode: CPS1p
+/* 627 */     MCD_OPC_Decode, 152, 6, 9, // Opcode: CPS1p
 /* 631 */     MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 640
-/* 636 */     MCD_OPC_Decode, 193, 4, 9, // Opcode: CPS3p
+/* 636 */     MCD_OPC_Decode, 154, 6, 9, // Opcode: CPS3p
 /* 640 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 643 */     MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 684
 /* 648 */     MCD_OPC_CheckPredicate, 0, 88, 4, 0, // Skip to: 1765
@@ -166,60 +169,60 @@ static const uint8_t DecoderTableARM32[] = {
 /* 660 */     MCD_OPC_CheckField, 9, 1, 0, 74, 4, 0, // Skip to: 1765
 /* 667 */     MCD_OPC_CheckField, 4, 1, 0, 67, 4, 0, // Skip to: 1765
 /* 674 */     MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 56 /* 0xe0000 */,
-/* 680 */     MCD_OPC_Decode, 182, 5, 11, // Opcode: MRS
+/* 680 */     MCD_OPC_Decode, 143, 7, 11, // Opcode: MRS
 /* 684 */     MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 709
 /* 689 */     MCD_OPC_CheckPredicate, 0, 47, 4, 0, // Skip to: 1765
 /* 694 */     MCD_OPC_CheckField, 4, 1, 1, 40, 4, 0, // Skip to: 1765
 /* 701 */     MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 705 */     MCD_OPC_Decode, 205, 5, 12, // Opcode: QADD
+/* 705 */     MCD_OPC_Decode, 247, 13, 12, // Opcode: QADD
 /* 709 */     MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 749
 /* 714 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 717 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 731
 /* 722 */     MCD_OPC_CheckPredicate, 3, 14, 4, 0, // Skip to: 1765
-/* 727 */     MCD_OPC_Decode, 136, 6, 13, // Opcode: SMLABB
+/* 727 */     MCD_OPC_Decode, 179, 14, 13, // Opcode: SMLABB
 /* 731 */     MCD_OPC_FilterValue, 1, 5, 4, 0, // Skip to: 1765
 /* 736 */     MCD_OPC_CheckPredicate, 4, 0, 4, 0, // Skip to: 1765
 /* 741 */     MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 745 */     MCD_OPC_Decode, 249, 6, 14, // Opcode: SWP
+/* 745 */     MCD_OPC_Decode, 164, 15, 14, // Opcode: SWP
 /* 749 */     MCD_OPC_FilterValue, 3, 243, 3, 0, // Skip to: 1765
 /* 754 */     MCD_OPC_CheckPredicate, 3, 238, 3, 0, // Skip to: 1765
 /* 759 */     MCD_OPC_CheckField, 4, 1, 0, 231, 3, 0, // Skip to: 1765
-/* 766 */     MCD_OPC_Decode, 137, 6, 13, // Opcode: SMLABT
+/* 766 */     MCD_OPC_Decode, 180, 14, 13, // Opcode: SMLABT
 /* 770 */     MCD_OPC_FilterValue, 1, 222, 3, 0, // Skip to: 1765
 /* 775 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 778 */     MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 806
 /* 783 */     MCD_OPC_CheckPredicate, 5, 209, 3, 0, // Skip to: 1765
 /* 788 */     MCD_OPC_CheckField, 28, 4, 14, 202, 3, 0, // Skip to: 1765
 /* 795 */     MCD_OPC_CheckField, 4, 1, 1, 195, 3, 0, // Skip to: 1765
-/* 802 */     MCD_OPC_Decode, 219, 4, 15, // Opcode: HLT
+/* 802 */     MCD_OPC_Decode, 180, 6, 15, // Opcode: HLT
 /* 806 */     MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 827
 /* 811 */     MCD_OPC_CheckPredicate, 3, 181, 3, 0, // Skip to: 1765
 /* 816 */     MCD_OPC_CheckField, 4, 1, 0, 174, 3, 0, // Skip to: 1765
-/* 823 */     MCD_OPC_Decode, 147, 6, 13, // Opcode: SMLATB
+/* 823 */     MCD_OPC_Decode, 190, 14, 13, // Opcode: SMLATB
 /* 827 */     MCD_OPC_FilterValue, 3, 165, 3, 0, // Skip to: 1765
 /* 832 */     MCD_OPC_CheckPredicate, 3, 160, 3, 0, // Skip to: 1765
 /* 837 */     MCD_OPC_CheckField, 4, 1, 0, 153, 3, 0, // Skip to: 1765
-/* 844 */     MCD_OPC_Decode, 148, 6, 13, // Opcode: SMLATT
+/* 844 */     MCD_OPC_Decode, 191, 14, 13, // Opcode: SMLATT
 /* 848 */     MCD_OPC_FilterValue, 1, 144, 3, 0, // Skip to: 1765
 /* 853 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 856 */     MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 924
 /* 861 */     MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 882
 /* 866 */     MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 882
 /* 873 */     MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 878 */     MCD_OPC_Decode, 137, 7, 16, // Opcode: TSTrr
+/* 878 */     MCD_OPC_Decode, 180, 15, 16, // Opcode: TSTrr
 /* 882 */     MCD_OPC_CheckPredicate, 6, 23, 0, 0, // Skip to: 910
 /* 887 */     MCD_OPC_CheckField, 28, 4, 15, 16, 0, 0, // Skip to: 910
 /* 894 */     MCD_OPC_CheckField, 5, 3, 0, 9, 0, 0, // Skip to: 910
 /* 901 */     MCD_OPC_SoftFail, 143, 250, 63 /* 0xffd0f */, 0,
-/* 906 */     MCD_OPC_Decode, 246, 5, 10, // Opcode: SETPAN
+/* 906 */     MCD_OPC_Decode, 161, 14, 10, // Opcode: SETPAN
 /* 910 */     MCD_OPC_CheckPredicate, 0, 82, 3, 0, // Skip to: 1765
 /* 915 */     MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 920 */     MCD_OPC_Decode, 138, 7, 17, // Opcode: TSTrsi
+/* 920 */     MCD_OPC_Decode, 181, 15, 17, // Opcode: TSTrsi
 /* 924 */     MCD_OPC_FilterValue, 1, 68, 3, 0, // Skip to: 1765
 /* 929 */     MCD_OPC_CheckPredicate, 0, 63, 3, 0, // Skip to: 1765
 /* 934 */     MCD_OPC_CheckField, 7, 1, 0, 56, 3, 0, // Skip to: 1765
 /* 941 */     MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 946 */     MCD_OPC_Decode, 139, 7, 18, // Opcode: TSTrsr
+/* 946 */     MCD_OPC_Decode, 182, 15, 18, // Opcode: TSTrsr
 /* 950 */     MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 1273
 /* 955 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 958 */     MCD_OPC_FilterValue, 0, 192, 0, 0, // Skip to: 1155
@@ -230,39 +233,39 @@ static const uint8_t DecoderTableARM32[] = {
 /* 979 */     MCD_OPC_CheckPredicate, 0, 13, 3, 0, // Skip to: 1765
 /* 984 */     MCD_OPC_CheckField, 9, 1, 0, 6, 3, 0, // Skip to: 1765
 /* 991 */     MCD_OPC_SoftFail, 143, 26 /* 0xd0f */, 128, 128, 60 /* 0xf0000 */,
-/* 997 */     MCD_OPC_Decode, 184, 5, 11, // Opcode: MRSsys
+/* 997 */     MCD_OPC_Decode, 145, 7, 11, // Opcode: MRSsys
 /* 1001 */    MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 1059
 /* 1006 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 1009 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 1034
 /* 1014 */    MCD_OPC_CheckPredicate, 2, 234, 2, 0, // Skip to: 1765
 /* 1019 */    MCD_OPC_CheckField, 28, 4, 14, 227, 2, 0, // Skip to: 1765
 /* 1026 */    MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0,
-/* 1030 */    MCD_OPC_Decode, 199, 4, 8, // Opcode: CRC32W
+/* 1030 */    MCD_OPC_Decode, 160, 6, 8, // Opcode: CRC32W
 /* 1034 */    MCD_OPC_FilterValue, 1, 214, 2, 0, // Skip to: 1765
 /* 1039 */    MCD_OPC_CheckPredicate, 2, 209, 2, 0, // Skip to: 1765
 /* 1044 */    MCD_OPC_CheckField, 28, 4, 14, 202, 2, 0, // Skip to: 1765
 /* 1051 */    MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0,
-/* 1055 */    MCD_OPC_Decode, 197, 4, 8, // Opcode: CRC32CW
+/* 1055 */    MCD_OPC_Decode, 158, 6, 8, // Opcode: CRC32CW
 /* 1059 */    MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 1073
 /* 1064 */    MCD_OPC_CheckPredicate, 3, 184, 2, 0, // Skip to: 1765
-/* 1069 */    MCD_OPC_Decode, 141, 6, 19, // Opcode: SMLALBB
+/* 1069 */    MCD_OPC_Decode, 184, 14, 19, // Opcode: SMLALBB
 /* 1073 */    MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 1087
 /* 1078 */    MCD_OPC_CheckPredicate, 3, 170, 2, 0, // Skip to: 1765
-/* 1083 */    MCD_OPC_Decode, 145, 6, 19, // Opcode: SMLALTB
+/* 1083 */    MCD_OPC_Decode, 188, 14, 19, // Opcode: SMLALTB
 /* 1087 */    MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 1101
 /* 1092 */    MCD_OPC_CheckPredicate, 3, 156, 2, 0, // Skip to: 1765
-/* 1097 */    MCD_OPC_Decode, 142, 6, 19, // Opcode: SMLALBT
+/* 1097 */    MCD_OPC_Decode, 185, 14, 19, // Opcode: SMLALBT
 /* 1101 */    MCD_OPC_FilterValue, 7, 147, 2, 0, // Skip to: 1765
 /* 1106 */    MCD_OPC_CheckPredicate, 3, 142, 2, 0, // Skip to: 1765
-/* 1111 */    MCD_OPC_Decode, 146, 6, 19, // Opcode: SMLALTT
+/* 1111 */    MCD_OPC_Decode, 189, 14, 19, // Opcode: SMLALTT
 /* 1115 */    MCD_OPC_FilterValue, 1, 133, 2, 0, // Skip to: 1765
 /* 1120 */    MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 1141
 /* 1125 */    MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 1141
 /* 1132 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 1137 */    MCD_OPC_Decode, 188, 4, 20, // Opcode: CMPrr
+/* 1137 */    MCD_OPC_Decode, 149, 6, 20, // Opcode: CMPrr
 /* 1141 */    MCD_OPC_CheckPredicate, 0, 107, 2, 0, // Skip to: 1765
 /* 1146 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 1151 */    MCD_OPC_Decode, 189, 4, 17, // Opcode: CMPrsi
+/* 1151 */    MCD_OPC_Decode, 150, 6, 17, // Opcode: CMPrsi
 /* 1155 */    MCD_OPC_FilterValue, 1, 93, 2, 0, // Skip to: 1765
 /* 1160 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 1163 */    MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 1241
@@ -272,34 +275,34 @@ static const uint8_t DecoderTableARM32[] = {
 /* 1179 */    MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 1197
 /* 1184 */    MCD_OPC_CheckPredicate, 0, 64, 2, 0, // Skip to: 1765
 /* 1189 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 1193 */    MCD_OPC_Decode, 209, 5, 21, // Opcode: QDADD
+/* 1193 */    MCD_OPC_Decode, 251, 13, 21, // Opcode: QDADD
 /* 1197 */    MCD_OPC_FilterValue, 3, 51, 2, 0, // Skip to: 1765
 /* 1202 */    MCD_OPC_CheckPredicate, 7, 46, 2, 0, // Skip to: 1765
 /* 1207 */    MCD_OPC_SoftFail, 128, 128, 128, 128, 1 /* 0x10000000 */, 128, 128, 128, 128, 14 /* 0xffffffffe0000000 */,
-/* 1218 */    MCD_OPC_Decode, 220, 4, 15, // Opcode: HVC
+/* 1218 */    MCD_OPC_Decode, 181, 6, 15, // Opcode: HVC
 /* 1222 */    MCD_OPC_FilterValue, 1, 26, 2, 0, // Skip to: 1765
 /* 1227 */    MCD_OPC_CheckPredicate, 0, 21, 2, 0, // Skip to: 1765
 /* 1232 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 1237 */    MCD_OPC_Decode, 190, 4, 18, // Opcode: CMPrsr
+/* 1237 */    MCD_OPC_Decode, 151, 6, 18, // Opcode: CMPrsr
 /* 1241 */    MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 1765
 /* 1246 */    MCD_OPC_CheckPredicate, 4, 2, 2, 0, // Skip to: 1765
 /* 1251 */    MCD_OPC_CheckField, 20, 1, 0, 251, 1, 0, // Skip to: 1765
 /* 1258 */    MCD_OPC_CheckField, 5, 2, 0, 244, 1, 0, // Skip to: 1765
 /* 1265 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 1269 */    MCD_OPC_Decode, 250, 6, 14, // Opcode: SWPB
+/* 1269 */    MCD_OPC_Decode, 165, 15, 14, // Opcode: SWPB
 /* 1273 */    MCD_OPC_FilterValue, 2, 241, 0, 0, // Skip to: 1519
 /* 1278 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 1281 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1311
 /* 1286 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1302
 /* 1291 */    MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1302
-/* 1298 */    MCD_OPC_Decode, 194, 5, 0, // Opcode: ORRrr
+/* 1298 */    MCD_OPC_Decode, 236, 13, 0, // Opcode: ORRrr
 /* 1302 */    MCD_OPC_CheckPredicate, 0, 202, 1, 0, // Skip to: 1765
-/* 1307 */    MCD_OPC_Decode, 195, 5, 1, // Opcode: ORRrsi
+/* 1307 */    MCD_OPC_Decode, 237, 13, 1, // Opcode: ORRrsi
 /* 1311 */    MCD_OPC_FilterValue, 1, 193, 1, 0, // Skip to: 1765
 /* 1316 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 1319 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1333
 /* 1324 */    MCD_OPC_CheckPredicate, 0, 180, 1, 0, // Skip to: 1765
-/* 1329 */    MCD_OPC_Decode, 196, 5, 2, // Opcode: ORRrsr
+/* 1329 */    MCD_OPC_Decode, 238, 13, 2, // Opcode: ORRrsr
 /* 1333 */    MCD_OPC_FilterValue, 1, 171, 1, 0, // Skip to: 1765
 /* 1338 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
 /* 1341 */    MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1405
@@ -308,47 +311,47 @@ static const uint8_t DecoderTableARM32[] = {
 /* 1354 */    MCD_OPC_CheckPredicate, 8, 150, 1, 0, // Skip to: 1765
 /* 1359 */    MCD_OPC_CheckField, 12, 4, 15, 143, 1, 0, // Skip to: 1765
 /* 1366 */    MCD_OPC_CheckField, 5, 2, 0, 136, 1, 0, // Skip to: 1765
-/* 1373 */    MCD_OPC_Decode, 201, 6, 22, // Opcode: STL
+/* 1373 */    MCD_OPC_Decode, 244, 14, 22, // Opcode: STL
 /* 1377 */    MCD_OPC_FilterValue, 1, 127, 1, 0, // Skip to: 1765
 /* 1382 */    MCD_OPC_CheckPredicate, 8, 122, 1, 0, // Skip to: 1765
 /* 1387 */    MCD_OPC_CheckField, 5, 2, 0, 115, 1, 0, // Skip to: 1765
 /* 1394 */    MCD_OPC_CheckField, 0, 4, 15, 108, 1, 0, // Skip to: 1765
-/* 1401 */    MCD_OPC_Decode, 222, 4, 23, // Opcode: LDA
+/* 1401 */    MCD_OPC_Decode, 183, 6, 23, // Opcode: LDA
 /* 1405 */    MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1462
 /* 1410 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1413 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1434
 /* 1418 */    MCD_OPC_CheckPredicate, 9, 86, 1, 0, // Skip to: 1765
 /* 1423 */    MCD_OPC_CheckField, 5, 2, 0, 79, 1, 0, // Skip to: 1765
-/* 1430 */    MCD_OPC_Decode, 203, 6, 24, // Opcode: STLEX
+/* 1430 */    MCD_OPC_Decode, 246, 14, 24, // Opcode: STLEX
 /* 1434 */    MCD_OPC_FilterValue, 1, 70, 1, 0, // Skip to: 1765
 /* 1439 */    MCD_OPC_CheckPredicate, 9, 65, 1, 0, // Skip to: 1765
 /* 1444 */    MCD_OPC_CheckField, 5, 2, 0, 58, 1, 0, // Skip to: 1765
 /* 1451 */    MCD_OPC_CheckField, 0, 4, 15, 51, 1, 0, // Skip to: 1765
-/* 1458 */    MCD_OPC_Decode, 224, 4, 23, // Opcode: LDAEX
+/* 1458 */    MCD_OPC_Decode, 185, 6, 23, // Opcode: LDAEX
 /* 1462 */    MCD_OPC_FilterValue, 15, 42, 1, 0, // Skip to: 1765
 /* 1467 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1470 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1491
 /* 1475 */    MCD_OPC_CheckPredicate, 0, 29, 1, 0, // Skip to: 1765
 /* 1480 */    MCD_OPC_CheckField, 5, 2, 0, 22, 1, 0, // Skip to: 1765
-/* 1487 */    MCD_OPC_Decode, 227, 6, 24, // Opcode: STREX
+/* 1487 */    MCD_OPC_Decode, 142, 15, 24, // Opcode: STREX
 /* 1491 */    MCD_OPC_FilterValue, 1, 13, 1, 0, // Skip to: 1765
 /* 1496 */    MCD_OPC_CheckPredicate, 0, 8, 1, 0, // Skip to: 1765
 /* 1501 */    MCD_OPC_CheckField, 5, 2, 0, 1, 1, 0, // Skip to: 1765
 /* 1508 */    MCD_OPC_CheckField, 0, 4, 15, 250, 0, 0, // Skip to: 1765
-/* 1515 */    MCD_OPC_Decode, 136, 5, 23, // Opcode: LDREX
+/* 1515 */    MCD_OPC_Decode, 225, 6, 23, // Opcode: LDREX
 /* 1519 */    MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1765
 /* 1524 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 1527 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1557
 /* 1532 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1548
 /* 1537 */    MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1548
-/* 1544 */    MCD_OPC_Decode, 165, 4, 0, // Opcode: BICrr
+/* 1544 */    MCD_OPC_Decode, 224, 5, 0, // Opcode: BICrr
 /* 1548 */    MCD_OPC_CheckPredicate, 0, 212, 0, 0, // Skip to: 1765
-/* 1553 */    MCD_OPC_Decode, 166, 4, 1, // Opcode: BICrsi
+/* 1553 */    MCD_OPC_Decode, 225, 5, 1, // Opcode: BICrsi
 /* 1557 */    MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 1765
 /* 1562 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 1565 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1579
 /* 1570 */    MCD_OPC_CheckPredicate, 0, 190, 0, 0, // Skip to: 1765
-/* 1575 */    MCD_OPC_Decode, 167, 4, 2, // Opcode: BICrsr
+/* 1575 */    MCD_OPC_Decode, 226, 5, 2, // Opcode: BICrsr
 /* 1579 */    MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1765
 /* 1584 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
 /* 1587 */    MCD_OPC_FilterValue, 12, 59, 0, 0, // Skip to: 1651
@@ -357,67 +360,67 @@ static const uint8_t DecoderTableARM32[] = {
 /* 1600 */    MCD_OPC_CheckPredicate, 8, 160, 0, 0, // Skip to: 1765
 /* 1605 */    MCD_OPC_CheckField, 12, 4, 15, 153, 0, 0, // Skip to: 1765
 /* 1612 */    MCD_OPC_CheckField, 5, 2, 0, 146, 0, 0, // Skip to: 1765
-/* 1619 */    MCD_OPC_Decode, 202, 6, 22, // Opcode: STLB
+/* 1619 */    MCD_OPC_Decode, 245, 14, 22, // Opcode: STLB
 /* 1623 */    MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 1765
 /* 1628 */    MCD_OPC_CheckPredicate, 8, 132, 0, 0, // Skip to: 1765
 /* 1633 */    MCD_OPC_CheckField, 5, 2, 0, 125, 0, 0, // Skip to: 1765
 /* 1640 */    MCD_OPC_CheckField, 0, 4, 15, 118, 0, 0, // Skip to: 1765
-/* 1647 */    MCD_OPC_Decode, 223, 4, 23, // Opcode: LDAB
+/* 1647 */    MCD_OPC_Decode, 184, 6, 23, // Opcode: LDAB
 /* 1651 */    MCD_OPC_FilterValue, 14, 52, 0, 0, // Skip to: 1708
 /* 1656 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1659 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1680
 /* 1664 */    MCD_OPC_CheckPredicate, 9, 96, 0, 0, // Skip to: 1765
 /* 1669 */    MCD_OPC_CheckField, 5, 2, 0, 89, 0, 0, // Skip to: 1765
-/* 1676 */    MCD_OPC_Decode, 204, 6, 24, // Opcode: STLEXB
+/* 1676 */    MCD_OPC_Decode, 247, 14, 24, // Opcode: STLEXB
 /* 1680 */    MCD_OPC_FilterValue, 1, 80, 0, 0, // Skip to: 1765
 /* 1685 */    MCD_OPC_CheckPredicate, 9, 75, 0, 0, // Skip to: 1765
 /* 1690 */    MCD_OPC_CheckField, 5, 2, 0, 68, 0, 0, // Skip to: 1765
 /* 1697 */    MCD_OPC_CheckField, 0, 4, 15, 61, 0, 0, // Skip to: 1765
-/* 1704 */    MCD_OPC_Decode, 225, 4, 23, // Opcode: LDAEXB
+/* 1704 */    MCD_OPC_Decode, 186, 6, 23, // Opcode: LDAEXB
 /* 1708 */    MCD_OPC_FilterValue, 15, 52, 0, 0, // Skip to: 1765
 /* 1713 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1716 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1737
 /* 1721 */    MCD_OPC_CheckPredicate, 0, 39, 0, 0, // Skip to: 1765
 /* 1726 */    MCD_OPC_CheckField, 5, 2, 0, 32, 0, 0, // Skip to: 1765
-/* 1733 */    MCD_OPC_Decode, 228, 6, 24, // Opcode: STREXB
+/* 1733 */    MCD_OPC_Decode, 143, 15, 24, // Opcode: STREXB
 /* 1737 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 1765
 /* 1742 */    MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 1765
 /* 1747 */    MCD_OPC_CheckField, 5, 2, 0, 11, 0, 0, // Skip to: 1765
 /* 1754 */    MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 1765
-/* 1761 */    MCD_OPC_Decode, 137, 5, 23, // Opcode: LDREXB
+/* 1761 */    MCD_OPC_Decode, 226, 6, 23, // Opcode: LDREXB
 /* 1765 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
 /* 1768 */    MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 1810
-/* 1773 */    MCD_OPC_CheckPredicate, 7, 167, 25, 0, // Skip to: 8345
-/* 1778 */    MCD_OPC_CheckField, 23, 1, 0, 160, 25, 0, // Skip to: 8345
-/* 1785 */    MCD_OPC_CheckField, 20, 1, 0, 153, 25, 0, // Skip to: 8345
-/* 1792 */    MCD_OPC_CheckField, 9, 3, 1, 146, 25, 0, // Skip to: 8345
-/* 1799 */    MCD_OPC_CheckField, 0, 4, 0, 139, 25, 0, // Skip to: 8345
-/* 1806 */    MCD_OPC_Decode, 183, 5, 25, // Opcode: MRSbanked
+/* 1773 */    MCD_OPC_CheckPredicate, 7, 203, 25, 0, // Skip to: 8381
+/* 1778 */    MCD_OPC_CheckField, 23, 1, 0, 196, 25, 0, // Skip to: 8381
+/* 1785 */    MCD_OPC_CheckField, 20, 1, 0, 189, 25, 0, // Skip to: 8381
+/* 1792 */    MCD_OPC_CheckField, 9, 3, 1, 182, 25, 0, // Skip to: 8381
+/* 1799 */    MCD_OPC_CheckField, 0, 4, 0, 175, 25, 0, // Skip to: 8381
+/* 1806 */    MCD_OPC_Decode, 144, 7, 25, // Opcode: MRSbanked
 /* 1810 */    MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 1846
 /* 1815 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1818 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1832
-/* 1823 */    MCD_OPC_CheckPredicate, 0, 117, 25, 0, // Skip to: 8345
-/* 1828 */    MCD_OPC_Decode, 231, 6, 7, // Opcode: STRH
-/* 1832 */    MCD_OPC_FilterValue, 1, 108, 25, 0, // Skip to: 8345
-/* 1837 */    MCD_OPC_CheckPredicate, 0, 103, 25, 0, // Skip to: 8345
-/* 1842 */    MCD_OPC_Decode, 140, 5, 7, // Opcode: LDRH
+/* 1823 */    MCD_OPC_CheckPredicate, 0, 153, 25, 0, // Skip to: 8381
+/* 1828 */    MCD_OPC_Decode, 146, 15, 7, // Opcode: STRH
+/* 1832 */    MCD_OPC_FilterValue, 1, 144, 25, 0, // Skip to: 8381
+/* 1837 */    MCD_OPC_CheckPredicate, 0, 139, 25, 0, // Skip to: 8381
+/* 1842 */    MCD_OPC_Decode, 229, 6, 7, // Opcode: LDRH
 /* 1846 */    MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 1882
 /* 1851 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1854 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1868
-/* 1859 */    MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 8345
-/* 1864 */    MCD_OPC_Decode, 133, 5, 7, // Opcode: LDRD
-/* 1868 */    MCD_OPC_FilterValue, 1, 72, 25, 0, // Skip to: 8345
-/* 1873 */    MCD_OPC_CheckPredicate, 0, 67, 25, 0, // Skip to: 8345
-/* 1878 */    MCD_OPC_Decode, 145, 5, 7, // Opcode: LDRSB
-/* 1882 */    MCD_OPC_FilterValue, 15, 58, 25, 0, // Skip to: 8345
+/* 1859 */    MCD_OPC_CheckPredicate, 3, 117, 25, 0, // Skip to: 8381
+/* 1864 */    MCD_OPC_Decode, 222, 6, 7, // Opcode: LDRD
+/* 1868 */    MCD_OPC_FilterValue, 1, 108, 25, 0, // Skip to: 8381
+/* 1873 */    MCD_OPC_CheckPredicate, 0, 103, 25, 0, // Skip to: 8381
+/* 1878 */    MCD_OPC_Decode, 234, 6, 7, // Opcode: LDRSB
+/* 1882 */    MCD_OPC_FilterValue, 15, 94, 25, 0, // Skip to: 8381
 /* 1887 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 1890 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1904
-/* 1895 */    MCD_OPC_CheckPredicate, 3, 45, 25, 0, // Skip to: 8345
-/* 1900 */    MCD_OPC_Decode, 224, 6, 7, // Opcode: STRD
-/* 1904 */    MCD_OPC_FilterValue, 1, 36, 25, 0, // Skip to: 8345
-/* 1909 */    MCD_OPC_CheckPredicate, 0, 31, 25, 0, // Skip to: 8345
-/* 1914 */    MCD_OPC_Decode, 150, 5, 7, // Opcode: LDRSH
-/* 1918 */    MCD_OPC_FilterValue, 1, 22, 25, 0, // Skip to: 8345
+/* 1895 */    MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 8381
+/* 1900 */    MCD_OPC_Decode, 139, 15, 7, // Opcode: STRD
+/* 1904 */    MCD_OPC_FilterValue, 1, 72, 25, 0, // Skip to: 8381
+/* 1909 */    MCD_OPC_CheckPredicate, 0, 67, 25, 0, // Skip to: 8381
+/* 1914 */    MCD_OPC_Decode, 239, 6, 7, // Opcode: LDRSH
+/* 1918 */    MCD_OPC_FilterValue, 1, 58, 25, 0, // Skip to: 8381
 /* 1923 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 1926 */    MCD_OPC_FilterValue, 0, 180, 2, 0, // Skip to: 2623
 /* 1931 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
@@ -426,29 +429,29 @@ static const uint8_t DecoderTableARM32[] = {
 /* 1942 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1972
 /* 1947 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1963
 /* 1952 */    MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1963
-/* 1959 */    MCD_OPC_Decode, 204, 4, 0, // Opcode: EORrr
-/* 1963 */    MCD_OPC_CheckPredicate, 0, 233, 24, 0, // Skip to: 8345
-/* 1968 */    MCD_OPC_Decode, 205, 4, 1, // Opcode: EORrsi
-/* 1972 */    MCD_OPC_FilterValue, 1, 224, 24, 0, // Skip to: 8345
+/* 1959 */    MCD_OPC_Decode, 165, 6, 0, // Opcode: EORrr
+/* 1963 */    MCD_OPC_CheckPredicate, 0, 13, 25, 0, // Skip to: 8381
+/* 1968 */    MCD_OPC_Decode, 166, 6, 1, // Opcode: EORrsi
+/* 1972 */    MCD_OPC_FilterValue, 1, 4, 25, 0, // Skip to: 8381
 /* 1977 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 1993
 /* 1982 */    MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 1993
-/* 1989 */    MCD_OPC_Decode, 228, 5, 0, // Opcode: RSBrr
-/* 1993 */    MCD_OPC_CheckPredicate, 0, 203, 24, 0, // Skip to: 8345
-/* 1998 */    MCD_OPC_Decode, 229, 5, 1, // Opcode: RSBrsi
+/* 1989 */    MCD_OPC_Decode, 142, 14, 0, // Opcode: RSBrr
+/* 1993 */    MCD_OPC_CheckPredicate, 0, 239, 24, 0, // Skip to: 8381
+/* 1998 */    MCD_OPC_Decode, 143, 14, 1, // Opcode: RSBrsi
 /* 2002 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 2070
 /* 2007 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2010 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2040
 /* 2015 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2031
 /* 2020 */    MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2031
-/* 2027 */    MCD_OPC_Decode, 146, 4, 0, // Opcode: ADCrr
-/* 2031 */    MCD_OPC_CheckPredicate, 0, 165, 24, 0, // Skip to: 8345
-/* 2036 */    MCD_OPC_Decode, 147, 4, 1, // Opcode: ADCrsi
-/* 2040 */    MCD_OPC_FilterValue, 1, 156, 24, 0, // Skip to: 8345
+/* 2027 */    MCD_OPC_Decode, 198, 5, 0, // Opcode: ADCrr
+/* 2031 */    MCD_OPC_CheckPredicate, 0, 201, 24, 0, // Skip to: 8381
+/* 2036 */    MCD_OPC_Decode, 199, 5, 1, // Opcode: ADCrsi
+/* 2040 */    MCD_OPC_FilterValue, 1, 192, 24, 0, // Skip to: 8381
 /* 2045 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2061
 /* 2050 */    MCD_OPC_CheckField, 5, 7, 0, 4, 0, 0, // Skip to: 2061
-/* 2057 */    MCD_OPC_Decode, 232, 5, 0, // Opcode: RSCrr
-/* 2061 */    MCD_OPC_CheckPredicate, 0, 135, 24, 0, // Skip to: 8345
-/* 2066 */    MCD_OPC_Decode, 233, 5, 1, // Opcode: RSCrsi
+/* 2057 */    MCD_OPC_Decode, 146, 14, 0, // Opcode: RSCrr
+/* 2061 */    MCD_OPC_CheckPredicate, 0, 171, 24, 0, // Skip to: 8381
+/* 2066 */    MCD_OPC_Decode, 147, 14, 1, // Opcode: RSCrsi
 /* 2070 */    MCD_OPC_FilterValue, 2, 166, 1, 0, // Skip to: 2497
 /* 2075 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 2078 */    MCD_OPC_FilterValue, 0, 70, 1, 0, // Skip to: 2409
@@ -456,259 +459,259 @@ static const uint8_t DecoderTableARM32[] = {
 /* 2086 */    MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 2129
 /* 2091 */    MCD_OPC_ExtractField, 9, 7,  // Inst{15-9} ...
 /* 2094 */    MCD_OPC_FilterValue, 120, 16, 0, 0, // Skip to: 2115
-/* 2099 */    MCD_OPC_CheckPredicate, 0, 97, 24, 0, // Skip to: 8345
-/* 2104 */    MCD_OPC_CheckField, 8, 1, 0, 90, 24, 0, // Skip to: 8345
-/* 2111 */    MCD_OPC_Decode, 185, 5, 26, // Opcode: MSR
-/* 2115 */    MCD_OPC_FilterValue, 121, 81, 24, 0, // Skip to: 8345
-/* 2120 */    MCD_OPC_CheckPredicate, 7, 76, 24, 0, // Skip to: 8345
-/* 2125 */    MCD_OPC_Decode, 186, 5, 27, // Opcode: MSRbanked
+/* 2099 */    MCD_OPC_CheckPredicate, 0, 133, 24, 0, // Skip to: 8381
+/* 2104 */    MCD_OPC_CheckField, 8, 1, 0, 126, 24, 0, // Skip to: 8381
+/* 2111 */    MCD_OPC_Decode, 146, 7, 26, // Opcode: MSR
+/* 2115 */    MCD_OPC_FilterValue, 121, 117, 24, 0, // Skip to: 8381
+/* 2120 */    MCD_OPC_CheckPredicate, 7, 112, 24, 0, // Skip to: 8381
+/* 2125 */    MCD_OPC_Decode, 147, 7, 27, // Opcode: MSRbanked
 /* 2129 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2158
-/* 2134 */    MCD_OPC_CheckPredicate, 0, 62, 24, 0, // Skip to: 8345
-/* 2139 */    MCD_OPC_CheckField, 22, 1, 0, 55, 24, 0, // Skip to: 8345
-/* 2146 */    MCD_OPC_CheckField, 8, 12, 255, 31, 47, 24, 0, // Skip to: 8345
-/* 2154 */    MCD_OPC_Decode, 175, 4, 28, // Opcode: BXJ
+/* 2134 */    MCD_OPC_CheckPredicate, 0, 98, 24, 0, // Skip to: 8381
+/* 2139 */    MCD_OPC_CheckField, 22, 1, 0, 91, 24, 0, // Skip to: 8381
+/* 2146 */    MCD_OPC_CheckField, 8, 12, 255, 31, 83, 24, 0, // Skip to: 8381
+/* 2154 */    MCD_OPC_Decode, 234, 5, 28, // Opcode: BXJ
 /* 2158 */    MCD_OPC_FilterValue, 2, 67, 0, 0, // Skip to: 2230
 /* 2163 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 2166 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2198
-/* 2171 */    MCD_OPC_CheckPredicate, 2, 25, 24, 0, // Skip to: 8345
-/* 2176 */    MCD_OPC_CheckField, 28, 4, 14, 18, 24, 0, // Skip to: 8345
-/* 2183 */    MCD_OPC_CheckField, 22, 1, 0, 11, 24, 0, // Skip to: 8345
+/* 2171 */    MCD_OPC_CheckPredicate, 2, 61, 24, 0, // Skip to: 8381
+/* 2176 */    MCD_OPC_CheckField, 28, 4, 14, 54, 24, 0, // Skip to: 8381
+/* 2183 */    MCD_OPC_CheckField, 22, 1, 0, 47, 24, 0, // Skip to: 8381
 /* 2190 */    MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0,
-/* 2194 */    MCD_OPC_Decode, 198, 4, 8, // Opcode: CRC32H
-/* 2198 */    MCD_OPC_FilterValue, 1, 254, 23, 0, // Skip to: 8345
-/* 2203 */    MCD_OPC_CheckPredicate, 2, 249, 23, 0, // Skip to: 8345
-/* 2208 */    MCD_OPC_CheckField, 28, 4, 14, 242, 23, 0, // Skip to: 8345
-/* 2215 */    MCD_OPC_CheckField, 22, 1, 0, 235, 23, 0, // Skip to: 8345
+/* 2194 */    MCD_OPC_Decode, 159, 6, 8, // Opcode: CRC32H
+/* 2198 */    MCD_OPC_FilterValue, 1, 34, 24, 0, // Skip to: 8381
+/* 2203 */    MCD_OPC_CheckPredicate, 2, 29, 24, 0, // Skip to: 8381
+/* 2208 */    MCD_OPC_CheckField, 28, 4, 14, 22, 24, 0, // Skip to: 8381
+/* 2215 */    MCD_OPC_CheckField, 22, 1, 0, 15, 24, 0, // Skip to: 8381
 /* 2222 */    MCD_OPC_SoftFail, 128, 26 /* 0xd00 */, 0,
-/* 2226 */    MCD_OPC_Decode, 196, 4, 8, // Opcode: CRC32CH
+/* 2226 */    MCD_OPC_Decode, 157, 6, 8, // Opcode: CRC32CH
 /* 2230 */    MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 2265
-/* 2235 */    MCD_OPC_CheckPredicate, 7, 217, 23, 0, // Skip to: 8345
-/* 2240 */    MCD_OPC_CheckField, 22, 1, 1, 210, 23, 0, // Skip to: 8345
-/* 2247 */    MCD_OPC_CheckField, 8, 12, 0, 203, 23, 0, // Skip to: 8345
-/* 2254 */    MCD_OPC_CheckField, 0, 4, 14, 196, 23, 0, // Skip to: 8345
-/* 2261 */    MCD_OPC_Decode, 207, 4, 29, // Opcode: ERET
+/* 2235 */    MCD_OPC_CheckPredicate, 7, 253, 23, 0, // Skip to: 8381
+/* 2240 */    MCD_OPC_CheckField, 22, 1, 1, 246, 23, 0, // Skip to: 8381
+/* 2247 */    MCD_OPC_CheckField, 8, 12, 0, 239, 23, 0, // Skip to: 8381
+/* 2254 */    MCD_OPC_CheckField, 0, 4, 14, 232, 23, 0, // Skip to: 8381
+/* 2261 */    MCD_OPC_Decode, 168, 6, 29, // Opcode: ERET
 /* 2265 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 2301
 /* 2270 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2273 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2287
-/* 2278 */    MCD_OPC_CheckPredicate, 3, 174, 23, 0, // Skip to: 8345
-/* 2283 */    MCD_OPC_Decode, 149, 6, 13, // Opcode: SMLAWB
-/* 2287 */    MCD_OPC_FilterValue, 1, 165, 23, 0, // Skip to: 8345
-/* 2292 */    MCD_OPC_CheckPredicate, 3, 160, 23, 0, // Skip to: 8345
-/* 2297 */    MCD_OPC_Decode, 163, 6, 30, // Opcode: SMULBB
+/* 2278 */    MCD_OPC_CheckPredicate, 3, 210, 23, 0, // Skip to: 8381
+/* 2283 */    MCD_OPC_Decode, 192, 14, 13, // Opcode: SMLAWB
+/* 2287 */    MCD_OPC_FilterValue, 1, 201, 23, 0, // Skip to: 8381
+/* 2292 */    MCD_OPC_CheckPredicate, 3, 196, 23, 0, // Skip to: 8381
+/* 2297 */    MCD_OPC_Decode, 206, 14, 30, // Opcode: SMULBB
 /* 2301 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 2337
 /* 2306 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2309 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2323
-/* 2314 */    MCD_OPC_CheckPredicate, 3, 138, 23, 0, // Skip to: 8345
-/* 2319 */    MCD_OPC_Decode, 168, 6, 30, // Opcode: SMULWB
-/* 2323 */    MCD_OPC_FilterValue, 1, 129, 23, 0, // Skip to: 8345
-/* 2328 */    MCD_OPC_CheckPredicate, 3, 124, 23, 0, // Skip to: 8345
-/* 2333 */    MCD_OPC_Decode, 166, 6, 30, // Opcode: SMULTB
+/* 2314 */    MCD_OPC_CheckPredicate, 3, 174, 23, 0, // Skip to: 8381
+/* 2319 */    MCD_OPC_Decode, 211, 14, 30, // Opcode: SMULWB
+/* 2323 */    MCD_OPC_FilterValue, 1, 165, 23, 0, // Skip to: 8381
+/* 2328 */    MCD_OPC_CheckPredicate, 3, 160, 23, 0, // Skip to: 8381
+/* 2333 */    MCD_OPC_Decode, 209, 14, 30, // Opcode: SMULTB
 /* 2337 */    MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2373
 /* 2342 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2345 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2359
-/* 2350 */    MCD_OPC_CheckPredicate, 3, 102, 23, 0, // Skip to: 8345
-/* 2355 */    MCD_OPC_Decode, 150, 6, 13, // Opcode: SMLAWT
-/* 2359 */    MCD_OPC_FilterValue, 1, 93, 23, 0, // Skip to: 8345
-/* 2364 */    MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 8345
-/* 2369 */    MCD_OPC_Decode, 164, 6, 30, // Opcode: SMULBT
-/* 2373 */    MCD_OPC_FilterValue, 7, 79, 23, 0, // Skip to: 8345
+/* 2350 */    MCD_OPC_CheckPredicate, 3, 138, 23, 0, // Skip to: 8381
+/* 2355 */    MCD_OPC_Decode, 193, 14, 13, // Opcode: SMLAWT
+/* 2359 */    MCD_OPC_FilterValue, 1, 129, 23, 0, // Skip to: 8381
+/* 2364 */    MCD_OPC_CheckPredicate, 3, 124, 23, 0, // Skip to: 8381
+/* 2369 */    MCD_OPC_Decode, 207, 14, 30, // Opcode: SMULBT
+/* 2373 */    MCD_OPC_FilterValue, 7, 115, 23, 0, // Skip to: 8381
 /* 2378 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2381 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2395
-/* 2386 */    MCD_OPC_CheckPredicate, 3, 66, 23, 0, // Skip to: 8345
-/* 2391 */    MCD_OPC_Decode, 169, 6, 30, // Opcode: SMULWT
-/* 2395 */    MCD_OPC_FilterValue, 1, 57, 23, 0, // Skip to: 8345
-/* 2400 */    MCD_OPC_CheckPredicate, 3, 52, 23, 0, // Skip to: 8345
-/* 2405 */    MCD_OPC_Decode, 167, 6, 30, // Opcode: SMULTT
-/* 2409 */    MCD_OPC_FilterValue, 1, 43, 23, 0, // Skip to: 8345
+/* 2386 */    MCD_OPC_CheckPredicate, 3, 102, 23, 0, // Skip to: 8381
+/* 2391 */    MCD_OPC_Decode, 212, 14, 30, // Opcode: SMULWT
+/* 2395 */    MCD_OPC_FilterValue, 1, 93, 23, 0, // Skip to: 8381
+/* 2400 */    MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 8381
+/* 2405 */    MCD_OPC_Decode, 210, 14, 30, // Opcode: SMULTT
+/* 2409 */    MCD_OPC_FilterValue, 1, 79, 23, 0, // Skip to: 8381
 /* 2414 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2417 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2457
 /* 2422 */    MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2443
 /* 2427 */    MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2443
 /* 2434 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 2439 */    MCD_OPC_Decode, 130, 7, 20, // Opcode: TEQrr
-/* 2443 */    MCD_OPC_CheckPredicate, 0, 9, 23, 0, // Skip to: 8345
+/* 2439 */    MCD_OPC_Decode, 173, 15, 20, // Opcode: TEQrr
+/* 2443 */    MCD_OPC_CheckPredicate, 0, 45, 23, 0, // Skip to: 8381
 /* 2448 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 2453 */    MCD_OPC_Decode, 131, 7, 17, // Opcode: TEQrsi
-/* 2457 */    MCD_OPC_FilterValue, 1, 251, 22, 0, // Skip to: 8345
+/* 2453 */    MCD_OPC_Decode, 174, 15, 17, // Opcode: TEQrsi
+/* 2457 */    MCD_OPC_FilterValue, 1, 31, 23, 0, // Skip to: 8381
 /* 2462 */    MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2483
 /* 2467 */    MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2483
 /* 2474 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 2479 */    MCD_OPC_Decode, 184, 4, 20, // Opcode: CMNzrr
-/* 2483 */    MCD_OPC_CheckPredicate, 0, 225, 22, 0, // Skip to: 8345
+/* 2479 */    MCD_OPC_Decode, 145, 6, 20, // Opcode: CMNzrr
+/* 2483 */    MCD_OPC_CheckPredicate, 0, 5, 23, 0, // Skip to: 8381
 /* 2488 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 2493 */    MCD_OPC_Decode, 185, 4, 17, // Opcode: CMNzrsi
-/* 2497 */    MCD_OPC_FilterValue, 3, 211, 22, 0, // Skip to: 8345
+/* 2493 */    MCD_OPC_Decode, 146, 6, 17, // Opcode: CMNzrsi
+/* 2497 */    MCD_OPC_FilterValue, 3, 247, 22, 0, // Skip to: 8381
 /* 2502 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 2505 */    MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 2583
 /* 2510 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 2534
 /* 2515 */    MCD_OPC_CheckField, 5, 16, 128, 15, 11, 0, 0, // Skip to: 2534
 /* 2523 */    MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2534
-/* 2530 */    MCD_OPC_Decode, 170, 5, 29, // Opcode: MOVPCLR
+/* 2530 */    MCD_OPC_Decode, 131, 7, 29, // Opcode: MOVPCLR
 /* 2534 */    MCD_OPC_ExtractField, 5, 7,  // Inst{11-5} ...
 /* 2537 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2567
 /* 2542 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 2558
 /* 2547 */    MCD_OPC_CheckField, 16, 4, 0, 4, 0, 0, // Skip to: 2558
-/* 2554 */    MCD_OPC_Decode, 174, 5, 31, // Opcode: MOVr
+/* 2554 */    MCD_OPC_Decode, 135, 7, 31, // Opcode: MOVr
 /* 2558 */    MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 2567
-/* 2563 */    MCD_OPC_Decode, 175, 5, 32, // Opcode: MOVr_TC
-/* 2567 */    MCD_OPC_CheckPredicate, 0, 141, 22, 0, // Skip to: 8345
-/* 2572 */    MCD_OPC_CheckField, 16, 4, 0, 134, 22, 0, // Skip to: 8345
-/* 2579 */    MCD_OPC_Decode, 176, 5, 33, // Opcode: MOVsi
-/* 2583 */    MCD_OPC_FilterValue, 1, 125, 22, 0, // Skip to: 8345
+/* 2563 */    MCD_OPC_Decode, 136, 7, 32, // Opcode: MOVr_TC
+/* 2567 */    MCD_OPC_CheckPredicate, 0, 177, 22, 0, // Skip to: 8381
+/* 2572 */    MCD_OPC_CheckField, 16, 4, 0, 170, 22, 0, // Skip to: 8381
+/* 2579 */    MCD_OPC_Decode, 137, 7, 33, // Opcode: MOVsi
+/* 2583 */    MCD_OPC_FilterValue, 1, 161, 22, 0, // Skip to: 8381
 /* 2588 */    MCD_OPC_CheckPredicate, 0, 16, 0, 0, // Skip to: 2609
 /* 2593 */    MCD_OPC_CheckField, 5, 7, 0, 9, 0, 0, // Skip to: 2609
 /* 2600 */    MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0,
-/* 2605 */    MCD_OPC_Decode, 190, 5, 31, // Opcode: MVNr
-/* 2609 */    MCD_OPC_CheckPredicate, 0, 99, 22, 0, // Skip to: 8345
+/* 2605 */    MCD_OPC_Decode, 224, 13, 31, // Opcode: MVNr
+/* 2609 */    MCD_OPC_CheckPredicate, 0, 135, 22, 0, // Skip to: 8381
 /* 2614 */    MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0,
-/* 2619 */    MCD_OPC_Decode, 191, 5, 33, // Opcode: MVNsi
-/* 2623 */    MCD_OPC_FilterValue, 1, 85, 22, 0, // Skip to: 8345
+/* 2619 */    MCD_OPC_Decode, 225, 13, 33, // Opcode: MVNsi
+/* 2623 */    MCD_OPC_FilterValue, 1, 121, 22, 0, // Skip to: 8381
 /* 2628 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 2631 */    MCD_OPC_FilterValue, 0, 113, 1, 0, // Skip to: 3005
 /* 2636 */    MCD_OPC_ExtractField, 22, 3,  // Inst{24-22} ...
 /* 2639 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2653
-/* 2644 */    MCD_OPC_CheckPredicate, 0, 64, 22, 0, // Skip to: 8345
-/* 2649 */    MCD_OPC_Decode, 206, 4, 2, // Opcode: EORrsr
+/* 2644 */    MCD_OPC_CheckPredicate, 0, 100, 22, 0, // Skip to: 8381
+/* 2649 */    MCD_OPC_Decode, 167, 6, 2, // Opcode: EORrsr
 /* 2653 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 2667
-/* 2658 */    MCD_OPC_CheckPredicate, 0, 50, 22, 0, // Skip to: 8345
-/* 2663 */    MCD_OPC_Decode, 230, 5, 2, // Opcode: RSBrsr
+/* 2658 */    MCD_OPC_CheckPredicate, 0, 86, 22, 0, // Skip to: 8381
+/* 2663 */    MCD_OPC_Decode, 144, 14, 2, // Opcode: RSBrsr
 /* 2667 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 2681
-/* 2672 */    MCD_OPC_CheckPredicate, 0, 36, 22, 0, // Skip to: 8345
-/* 2677 */    MCD_OPC_Decode, 148, 4, 3, // Opcode: ADCrsr
+/* 2672 */    MCD_OPC_CheckPredicate, 0, 72, 22, 0, // Skip to: 8381
+/* 2677 */    MCD_OPC_Decode, 200, 5, 3, // Opcode: ADCrsr
 /* 2681 */    MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 2695
-/* 2686 */    MCD_OPC_CheckPredicate, 0, 22, 22, 0, // Skip to: 8345
-/* 2691 */    MCD_OPC_Decode, 234, 5, 2, // Opcode: RSCrsr
+/* 2686 */    MCD_OPC_CheckPredicate, 0, 58, 22, 0, // Skip to: 8381
+/* 2691 */    MCD_OPC_Decode, 148, 14, 2, // Opcode: RSCrsr
 /* 2695 */    MCD_OPC_FilterValue, 4, 163, 0, 0, // Skip to: 2863
 /* 2700 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 2703 */    MCD_OPC_FilterValue, 0, 136, 0, 0, // Skip to: 2844
 /* 2708 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
 /* 2711 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2766
 /* 2716 */    MCD_OPC_ExtractField, 8, 12,  // Inst{19-8} ...
-/* 2719 */    MCD_OPC_FilterValue, 255, 31, 244, 21, 0, // Skip to: 8345
+/* 2719 */    MCD_OPC_FilterValue, 255, 31, 24, 22, 0, // Skip to: 8381
 /* 2725 */    MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2741
 /* 2730 */    MCD_OPC_CheckField, 0, 4, 14, 4, 0, 0, // Skip to: 2741
-/* 2737 */    MCD_OPC_Decode, 176, 4, 29, // Opcode: BX_RET
+/* 2737 */    MCD_OPC_Decode, 235, 5, 29, // Opcode: BX_RET
 /* 2741 */    MCD_OPC_CheckPredicate, 10, 11, 0, 0, // Skip to: 2757
 /* 2746 */    MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2757
-/* 2753 */    MCD_OPC_Decode, 174, 4, 34, // Opcode: BX
-/* 2757 */    MCD_OPC_CheckPredicate, 10, 207, 21, 0, // Skip to: 8345
-/* 2762 */    MCD_OPC_Decode, 177, 4, 28, // Opcode: BX_pred
+/* 2753 */    MCD_OPC_Decode, 233, 5, 34, // Opcode: BX
+/* 2757 */    MCD_OPC_CheckPredicate, 10, 243, 21, 0, // Skip to: 8381
+/* 2762 */    MCD_OPC_Decode, 236, 5, 28, // Opcode: BX_pred
 /* 2766 */    MCD_OPC_FilterValue, 1, 34, 0, 0, // Skip to: 2805
 /* 2771 */    MCD_OPC_ExtractField, 8, 12,  // Inst{19-8} ...
-/* 2774 */    MCD_OPC_FilterValue, 255, 31, 189, 21, 0, // Skip to: 8345
+/* 2774 */    MCD_OPC_FilterValue, 255, 31, 225, 21, 0, // Skip to: 8381
 /* 2780 */    MCD_OPC_CheckPredicate, 11, 11, 0, 0, // Skip to: 2796
 /* 2785 */    MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 2796
-/* 2792 */    MCD_OPC_Decode, 170, 4, 34, // Opcode: BLX
-/* 2796 */    MCD_OPC_CheckPredicate, 11, 168, 21, 0, // Skip to: 8345
-/* 2801 */    MCD_OPC_Decode, 171, 4, 28, // Opcode: BLX_pred
+/* 2792 */    MCD_OPC_Decode, 229, 5, 34, // Opcode: BLX
+/* 2796 */    MCD_OPC_CheckPredicate, 11, 204, 21, 0, // Skip to: 8381
+/* 2801 */    MCD_OPC_Decode, 230, 5, 28, // Opcode: BLX_pred
 /* 2805 */    MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2823
-/* 2810 */    MCD_OPC_CheckPredicate, 0, 154, 21, 0, // Skip to: 8345
+/* 2810 */    MCD_OPC_CheckPredicate, 0, 190, 21, 0, // Skip to: 8381
 /* 2815 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 2819 */    MCD_OPC_Decode, 212, 5, 21, // Opcode: QSUB
-/* 2823 */    MCD_OPC_FilterValue, 3, 141, 21, 0, // Skip to: 8345
-/* 2828 */    MCD_OPC_CheckPredicate, 0, 136, 21, 0, // Skip to: 8345
-/* 2833 */    MCD_OPC_CheckField, 28, 4, 14, 129, 21, 0, // Skip to: 8345
-/* 2840 */    MCD_OPC_Decode, 168, 4, 15, // Opcode: BKPT
-/* 2844 */    MCD_OPC_FilterValue, 1, 120, 21, 0, // Skip to: 8345
-/* 2849 */    MCD_OPC_CheckPredicate, 0, 115, 21, 0, // Skip to: 8345
+/* 2819 */    MCD_OPC_Decode, 254, 13, 21, // Opcode: QSUB
+/* 2823 */    MCD_OPC_FilterValue, 3, 177, 21, 0, // Skip to: 8381
+/* 2828 */    MCD_OPC_CheckPredicate, 0, 172, 21, 0, // Skip to: 8381
+/* 2833 */    MCD_OPC_CheckField, 28, 4, 14, 165, 21, 0, // Skip to: 8381
+/* 2840 */    MCD_OPC_Decode, 227, 5, 15, // Opcode: BKPT
+/* 2844 */    MCD_OPC_FilterValue, 1, 156, 21, 0, // Skip to: 8381
+/* 2849 */    MCD_OPC_CheckPredicate, 0, 151, 21, 0, // Skip to: 8381
 /* 2854 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 2859 */    MCD_OPC_Decode, 132, 7, 18, // Opcode: TEQrsr
+/* 2859 */    MCD_OPC_Decode, 175, 15, 18, // Opcode: TEQrsr
 /* 2863 */    MCD_OPC_FilterValue, 5, 97, 0, 0, // Skip to: 2965
 /* 2868 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 2871 */    MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 2946
 /* 2876 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
 /* 2879 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2907
-/* 2884 */    MCD_OPC_CheckPredicate, 11, 80, 21, 0, // Skip to: 8345
-/* 2889 */    MCD_OPC_CheckField, 16, 4, 15, 73, 21, 0, // Skip to: 8345
-/* 2896 */    MCD_OPC_CheckField, 8, 4, 15, 66, 21, 0, // Skip to: 8345
-/* 2903 */    MCD_OPC_Decode, 182, 4, 35, // Opcode: CLZ
+/* 2884 */    MCD_OPC_CheckPredicate, 11, 116, 21, 0, // Skip to: 8381
+/* 2889 */    MCD_OPC_CheckField, 16, 4, 15, 109, 21, 0, // Skip to: 8381
+/* 2896 */    MCD_OPC_CheckField, 8, 4, 15, 102, 21, 0, // Skip to: 8381
+/* 2903 */    MCD_OPC_Decode, 143, 6, 35, // Opcode: CLZ
 /* 2907 */    MCD_OPC_FilterValue, 2, 13, 0, 0, // Skip to: 2925
-/* 2912 */    MCD_OPC_CheckPredicate, 0, 52, 21, 0, // Skip to: 8345
+/* 2912 */    MCD_OPC_CheckPredicate, 0, 88, 21, 0, // Skip to: 8381
 /* 2917 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 2921 */    MCD_OPC_Decode, 210, 5, 21, // Opcode: QDSUB
-/* 2925 */    MCD_OPC_FilterValue, 3, 39, 21, 0, // Skip to: 8345
-/* 2930 */    MCD_OPC_CheckPredicate, 12, 34, 21, 0, // Skip to: 8345
-/* 2935 */    MCD_OPC_CheckField, 8, 12, 0, 27, 21, 0, // Skip to: 8345
-/* 2942 */    MCD_OPC_Decode, 135, 6, 36, // Opcode: SMC
-/* 2946 */    MCD_OPC_FilterValue, 1, 18, 21, 0, // Skip to: 8345
-/* 2951 */    MCD_OPC_CheckPredicate, 0, 13, 21, 0, // Skip to: 8345
+/* 2921 */    MCD_OPC_Decode, 252, 13, 21, // Opcode: QDSUB
+/* 2925 */    MCD_OPC_FilterValue, 3, 75, 21, 0, // Skip to: 8381
+/* 2930 */    MCD_OPC_CheckPredicate, 12, 70, 21, 0, // Skip to: 8381
+/* 2935 */    MCD_OPC_CheckField, 8, 12, 0, 63, 21, 0, // Skip to: 8381
+/* 2942 */    MCD_OPC_Decode, 178, 14, 36, // Opcode: SMC
+/* 2946 */    MCD_OPC_FilterValue, 1, 54, 21, 0, // Skip to: 8381
+/* 2951 */    MCD_OPC_CheckPredicate, 0, 49, 21, 0, // Skip to: 8381
 /* 2956 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 2961 */    MCD_OPC_Decode, 186, 4, 18, // Opcode: CMNzrsr
+/* 2961 */    MCD_OPC_Decode, 147, 6, 18, // Opcode: CMNzrsr
 /* 2965 */    MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 2986
-/* 2970 */    MCD_OPC_CheckPredicate, 0, 250, 20, 0, // Skip to: 8345
-/* 2975 */    MCD_OPC_CheckField, 16, 4, 0, 243, 20, 0, // Skip to: 8345
-/* 2982 */    MCD_OPC_Decode, 177, 5, 37, // Opcode: MOVsr
-/* 2986 */    MCD_OPC_FilterValue, 7, 234, 20, 0, // Skip to: 8345
-/* 2991 */    MCD_OPC_CheckPredicate, 0, 229, 20, 0, // Skip to: 8345
+/* 2970 */    MCD_OPC_CheckPredicate, 0, 30, 21, 0, // Skip to: 8381
+/* 2975 */    MCD_OPC_CheckField, 16, 4, 0, 23, 21, 0, // Skip to: 8381
+/* 2982 */    MCD_OPC_Decode, 138, 7, 37, // Opcode: MOVsr
+/* 2986 */    MCD_OPC_FilterValue, 7, 14, 21, 0, // Skip to: 8381
+/* 2991 */    MCD_OPC_CheckPredicate, 0, 9, 21, 0, // Skip to: 8381
 /* 2996 */    MCD_OPC_SoftFail, 128, 128, 60 /* 0xf0000 */, 0,
-/* 3001 */    MCD_OPC_Decode, 192, 5, 37, // Opcode: MVNsr
-/* 3005 */    MCD_OPC_FilterValue, 1, 215, 20, 0, // Skip to: 8345
+/* 3001 */    MCD_OPC_Decode, 226, 13, 37, // Opcode: MVNsr
+/* 3005 */    MCD_OPC_FilterValue, 1, 251, 20, 0, // Skip to: 8381
 /* 3010 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
 /* 3013 */    MCD_OPC_FilterValue, 0, 48, 1, 0, // Skip to: 3322
 /* 3018 */    MCD_OPC_ExtractField, 22, 3,  // Inst{24-22} ...
 /* 3021 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3035
-/* 3026 */    MCD_OPC_CheckPredicate, 1, 194, 20, 0, // Skip to: 8345
-/* 3031 */    MCD_OPC_Decode, 168, 5, 38, // Opcode: MLA
+/* 3026 */    MCD_OPC_CheckPredicate, 1, 230, 20, 0, // Skip to: 8381
+/* 3031 */    MCD_OPC_Decode, 129, 7, 38, // Opcode: MLA
 /* 3035 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3056
-/* 3040 */    MCD_OPC_CheckPredicate, 13, 180, 20, 0, // Skip to: 8345
-/* 3045 */    MCD_OPC_CheckField, 20, 1, 0, 173, 20, 0, // Skip to: 8345
-/* 3052 */    MCD_OPC_Decode, 169, 5, 39, // Opcode: MLS
+/* 3040 */    MCD_OPC_CheckPredicate, 13, 216, 20, 0, // Skip to: 8381
+/* 3045 */    MCD_OPC_CheckField, 20, 1, 0, 209, 20, 0, // Skip to: 8381
+/* 3052 */    MCD_OPC_Decode, 130, 7, 39, // Opcode: MLS
 /* 3056 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3070
-/* 3061 */    MCD_OPC_CheckPredicate, 1, 159, 20, 0, // Skip to: 8345
-/* 3066 */    MCD_OPC_Decode, 153, 7, 40, // Opcode: UMLAL
+/* 3061 */    MCD_OPC_CheckPredicate, 1, 195, 20, 0, // Skip to: 8381
+/* 3066 */    MCD_OPC_Decode, 196, 15, 40, // Opcode: UMLAL
 /* 3070 */    MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3084
-/* 3075 */    MCD_OPC_CheckPredicate, 1, 145, 20, 0, // Skip to: 8345
-/* 3080 */    MCD_OPC_Decode, 140, 6, 40, // Opcode: SMLAL
+/* 3075 */    MCD_OPC_CheckPredicate, 1, 181, 20, 0, // Skip to: 8381
+/* 3080 */    MCD_OPC_Decode, 183, 14, 40, // Opcode: SMLAL
 /* 3084 */    MCD_OPC_FilterValue, 6, 89, 0, 0, // Skip to: 3178
 /* 3089 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
 /* 3092 */    MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3135
 /* 3097 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3100 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3114
-/* 3105 */    MCD_OPC_CheckPredicate, 9, 115, 20, 0, // Skip to: 8345
-/* 3110 */    MCD_OPC_Decode, 205, 6, 41, // Opcode: STLEXD
-/* 3114 */    MCD_OPC_FilterValue, 1, 106, 20, 0, // Skip to: 8345
-/* 3119 */    MCD_OPC_CheckPredicate, 9, 101, 20, 0, // Skip to: 8345
-/* 3124 */    MCD_OPC_CheckField, 0, 4, 15, 94, 20, 0, // Skip to: 8345
-/* 3131 */    MCD_OPC_Decode, 226, 4, 42, // Opcode: LDAEXD
-/* 3135 */    MCD_OPC_FilterValue, 15, 85, 20, 0, // Skip to: 8345
+/* 3105 */    MCD_OPC_CheckPredicate, 9, 151, 20, 0, // Skip to: 8381
+/* 3110 */    MCD_OPC_Decode, 248, 14, 41, // Opcode: STLEXD
+/* 3114 */    MCD_OPC_FilterValue, 1, 142, 20, 0, // Skip to: 8381
+/* 3119 */    MCD_OPC_CheckPredicate, 9, 137, 20, 0, // Skip to: 8381
+/* 3124 */    MCD_OPC_CheckField, 0, 4, 15, 130, 20, 0, // Skip to: 8381
+/* 3131 */    MCD_OPC_Decode, 187, 6, 42, // Opcode: LDAEXD
+/* 3135 */    MCD_OPC_FilterValue, 15, 121, 20, 0, // Skip to: 8381
 /* 3140 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3143 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3157
-/* 3148 */    MCD_OPC_CheckPredicate, 0, 72, 20, 0, // Skip to: 8345
-/* 3153 */    MCD_OPC_Decode, 229, 6, 41, // Opcode: STREXD
-/* 3157 */    MCD_OPC_FilterValue, 1, 63, 20, 0, // Skip to: 8345
-/* 3162 */    MCD_OPC_CheckPredicate, 0, 58, 20, 0, // Skip to: 8345
-/* 3167 */    MCD_OPC_CheckField, 0, 4, 15, 51, 20, 0, // Skip to: 8345
-/* 3174 */    MCD_OPC_Decode, 138, 5, 42, // Opcode: LDREXD
-/* 3178 */    MCD_OPC_FilterValue, 7, 42, 20, 0, // Skip to: 8345
+/* 3148 */    MCD_OPC_CheckPredicate, 0, 108, 20, 0, // Skip to: 8381
+/* 3153 */    MCD_OPC_Decode, 144, 15, 41, // Opcode: STREXD
+/* 3157 */    MCD_OPC_FilterValue, 1, 99, 20, 0, // Skip to: 8381
+/* 3162 */    MCD_OPC_CheckPredicate, 0, 94, 20, 0, // Skip to: 8381
+/* 3167 */    MCD_OPC_CheckField, 0, 4, 15, 87, 20, 0, // Skip to: 8381
+/* 3174 */    MCD_OPC_Decode, 227, 6, 42, // Opcode: LDREXD
+/* 3178 */    MCD_OPC_FilterValue, 7, 78, 20, 0, // Skip to: 8381
 /* 3183 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
 /* 3186 */    MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 3236
 /* 3191 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3194 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3215
-/* 3199 */    MCD_OPC_CheckPredicate, 8, 21, 20, 0, // Skip to: 8345
-/* 3204 */    MCD_OPC_CheckField, 12, 4, 15, 14, 20, 0, // Skip to: 8345
-/* 3211 */    MCD_OPC_Decode, 207, 6, 22, // Opcode: STLH
-/* 3215 */    MCD_OPC_FilterValue, 1, 5, 20, 0, // Skip to: 8345
-/* 3220 */    MCD_OPC_CheckPredicate, 8, 0, 20, 0, // Skip to: 8345
-/* 3225 */    MCD_OPC_CheckField, 0, 4, 15, 249, 19, 0, // Skip to: 8345
-/* 3232 */    MCD_OPC_Decode, 228, 4, 23, // Opcode: LDAH
+/* 3199 */    MCD_OPC_CheckPredicate, 8, 57, 20, 0, // Skip to: 8381
+/* 3204 */    MCD_OPC_CheckField, 12, 4, 15, 50, 20, 0, // Skip to: 8381
+/* 3211 */    MCD_OPC_Decode, 250, 14, 22, // Opcode: STLH
+/* 3215 */    MCD_OPC_FilterValue, 1, 41, 20, 0, // Skip to: 8381
+/* 3220 */    MCD_OPC_CheckPredicate, 8, 36, 20, 0, // Skip to: 8381
+/* 3225 */    MCD_OPC_CheckField, 0, 4, 15, 29, 20, 0, // Skip to: 8381
+/* 3232 */    MCD_OPC_Decode, 189, 6, 23, // Opcode: LDAH
 /* 3236 */    MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 3279
 /* 3241 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3244 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3258
-/* 3249 */    MCD_OPC_CheckPredicate, 9, 227, 19, 0, // Skip to: 8345
-/* 3254 */    MCD_OPC_Decode, 206, 6, 24, // Opcode: STLEXH
-/* 3258 */    MCD_OPC_FilterValue, 1, 218, 19, 0, // Skip to: 8345
-/* 3263 */    MCD_OPC_CheckPredicate, 9, 213, 19, 0, // Skip to: 8345
-/* 3268 */    MCD_OPC_CheckField, 0, 4, 15, 206, 19, 0, // Skip to: 8345
-/* 3275 */    MCD_OPC_Decode, 227, 4, 23, // Opcode: LDAEXH
-/* 3279 */    MCD_OPC_FilterValue, 15, 197, 19, 0, // Skip to: 8345
+/* 3249 */    MCD_OPC_CheckPredicate, 9, 7, 20, 0, // Skip to: 8381
+/* 3254 */    MCD_OPC_Decode, 249, 14, 24, // Opcode: STLEXH
+/* 3258 */    MCD_OPC_FilterValue, 1, 254, 19, 0, // Skip to: 8381
+/* 3263 */    MCD_OPC_CheckPredicate, 9, 249, 19, 0, // Skip to: 8381
+/* 3268 */    MCD_OPC_CheckField, 0, 4, 15, 242, 19, 0, // Skip to: 8381
+/* 3275 */    MCD_OPC_Decode, 188, 6, 23, // Opcode: LDAEXH
+/* 3279 */    MCD_OPC_FilterValue, 15, 233, 19, 0, // Skip to: 8381
 /* 3284 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3287 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3301
-/* 3292 */    MCD_OPC_CheckPredicate, 0, 184, 19, 0, // Skip to: 8345
-/* 3297 */    MCD_OPC_Decode, 230, 6, 24, // Opcode: STREXH
-/* 3301 */    MCD_OPC_FilterValue, 1, 175, 19, 0, // Skip to: 8345
-/* 3306 */    MCD_OPC_CheckPredicate, 0, 170, 19, 0, // Skip to: 8345
-/* 3311 */    MCD_OPC_CheckField, 0, 4, 15, 163, 19, 0, // Skip to: 8345
-/* 3318 */    MCD_OPC_Decode, 139, 5, 23, // Opcode: LDREXH
+/* 3292 */    MCD_OPC_CheckPredicate, 0, 220, 19, 0, // Skip to: 8381
+/* 3297 */    MCD_OPC_Decode, 145, 15, 24, // Opcode: STREXH
+/* 3301 */    MCD_OPC_FilterValue, 1, 211, 19, 0, // Skip to: 8381
+/* 3306 */    MCD_OPC_CheckPredicate, 0, 206, 19, 0, // Skip to: 8381
+/* 3311 */    MCD_OPC_CheckField, 0, 4, 15, 199, 19, 0, // Skip to: 8381
+/* 3318 */    MCD_OPC_Decode, 228, 6, 23, // Opcode: LDREXH
 /* 3322 */    MCD_OPC_FilterValue, 1, 130, 0, 0, // Skip to: 3457
 /* 3327 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3330 */    MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3395
@@ -716,69 +719,69 @@ static const uint8_t DecoderTableARM32[] = {
 /* 3338 */    MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 3381
 /* 3343 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 3346 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3367
-/* 3351 */    MCD_OPC_CheckPredicate, 0, 125, 19, 0, // Skip to: 8345
-/* 3356 */    MCD_OPC_CheckField, 8, 4, 0, 118, 19, 0, // Skip to: 8345
-/* 3363 */    MCD_OPC_Decode, 233, 6, 43, // Opcode: STRHTr
-/* 3367 */    MCD_OPC_FilterValue, 1, 109, 19, 0, // Skip to: 8345
-/* 3372 */    MCD_OPC_CheckPredicate, 0, 104, 19, 0, // Skip to: 8345
-/* 3377 */    MCD_OPC_Decode, 232, 6, 44, // Opcode: STRHTi
-/* 3381 */    MCD_OPC_FilterValue, 1, 95, 19, 0, // Skip to: 8345
-/* 3386 */    MCD_OPC_CheckPredicate, 0, 90, 19, 0, // Skip to: 8345
-/* 3391 */    MCD_OPC_Decode, 235, 6, 7, // Opcode: STRH_PRE
-/* 3395 */    MCD_OPC_FilterValue, 1, 81, 19, 0, // Skip to: 8345
+/* 3351 */    MCD_OPC_CheckPredicate, 0, 161, 19, 0, // Skip to: 8381
+/* 3356 */    MCD_OPC_CheckField, 8, 4, 0, 154, 19, 0, // Skip to: 8381
+/* 3363 */    MCD_OPC_Decode, 148, 15, 43, // Opcode: STRHTr
+/* 3367 */    MCD_OPC_FilterValue, 1, 145, 19, 0, // Skip to: 8381
+/* 3372 */    MCD_OPC_CheckPredicate, 0, 140, 19, 0, // Skip to: 8381
+/* 3377 */    MCD_OPC_Decode, 147, 15, 44, // Opcode: STRHTi
+/* 3381 */    MCD_OPC_FilterValue, 1, 131, 19, 0, // Skip to: 8381
+/* 3386 */    MCD_OPC_CheckPredicate, 0, 126, 19, 0, // Skip to: 8381
+/* 3391 */    MCD_OPC_Decode, 150, 15, 7, // Opcode: STRH_PRE
+/* 3395 */    MCD_OPC_FilterValue, 1, 117, 19, 0, // Skip to: 8381
 /* 3400 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 3403 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3443
 /* 3408 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 3411 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3429
-/* 3416 */    MCD_OPC_CheckPredicate, 0, 60, 19, 0, // Skip to: 8345
+/* 3416 */    MCD_OPC_CheckPredicate, 0, 96, 19, 0, // Skip to: 8381
 /* 3421 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 3425 */    MCD_OPC_Decode, 142, 5, 45, // Opcode: LDRHTr
-/* 3429 */    MCD_OPC_FilterValue, 1, 47, 19, 0, // Skip to: 8345
-/* 3434 */    MCD_OPC_CheckPredicate, 0, 42, 19, 0, // Skip to: 8345
-/* 3439 */    MCD_OPC_Decode, 141, 5, 46, // Opcode: LDRHTi
-/* 3443 */    MCD_OPC_FilterValue, 1, 33, 19, 0, // Skip to: 8345
-/* 3448 */    MCD_OPC_CheckPredicate, 0, 28, 19, 0, // Skip to: 8345
-/* 3453 */    MCD_OPC_Decode, 144, 5, 7, // Opcode: LDRH_PRE
+/* 3425 */    MCD_OPC_Decode, 231, 6, 45, // Opcode: LDRHTr
+/* 3429 */    MCD_OPC_FilterValue, 1, 83, 19, 0, // Skip to: 8381
+/* 3434 */    MCD_OPC_CheckPredicate, 0, 78, 19, 0, // Skip to: 8381
+/* 3439 */    MCD_OPC_Decode, 230, 6, 46, // Opcode: LDRHTi
+/* 3443 */    MCD_OPC_FilterValue, 1, 69, 19, 0, // Skip to: 8381
+/* 3448 */    MCD_OPC_CheckPredicate, 0, 64, 19, 0, // Skip to: 8381
+/* 3453 */    MCD_OPC_Decode, 233, 6, 7, // Opcode: LDRH_PRE
 /* 3457 */    MCD_OPC_FilterValue, 2, 86, 0, 0, // Skip to: 3548
 /* 3462 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3465 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3486
-/* 3470 */    MCD_OPC_CheckPredicate, 0, 6, 19, 0, // Skip to: 8345
-/* 3475 */    MCD_OPC_CheckField, 24, 1, 1, 255, 18, 0, // Skip to: 8345
-/* 3482 */    MCD_OPC_Decode, 135, 5, 7, // Opcode: LDRD_PRE
-/* 3486 */    MCD_OPC_FilterValue, 1, 246, 18, 0, // Skip to: 8345
+/* 3470 */    MCD_OPC_CheckPredicate, 0, 42, 19, 0, // Skip to: 8381
+/* 3475 */    MCD_OPC_CheckField, 24, 1, 1, 35, 19, 0, // Skip to: 8381
+/* 3482 */    MCD_OPC_Decode, 224, 6, 7, // Opcode: LDRD_PRE
+/* 3486 */    MCD_OPC_FilterValue, 1, 26, 19, 0, // Skip to: 8381
 /* 3491 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 3494 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3534
 /* 3499 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 3502 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3520
-/* 3507 */    MCD_OPC_CheckPredicate, 0, 225, 18, 0, // Skip to: 8345
+/* 3507 */    MCD_OPC_CheckPredicate, 0, 5, 19, 0, // Skip to: 8381
 /* 3512 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 3516 */    MCD_OPC_Decode, 147, 5, 45, // Opcode: LDRSBTr
-/* 3520 */    MCD_OPC_FilterValue, 1, 212, 18, 0, // Skip to: 8345
-/* 3525 */    MCD_OPC_CheckPredicate, 0, 207, 18, 0, // Skip to: 8345
-/* 3530 */    MCD_OPC_Decode, 146, 5, 46, // Opcode: LDRSBTi
-/* 3534 */    MCD_OPC_FilterValue, 1, 198, 18, 0, // Skip to: 8345
-/* 3539 */    MCD_OPC_CheckPredicate, 0, 193, 18, 0, // Skip to: 8345
-/* 3544 */    MCD_OPC_Decode, 149, 5, 7, // Opcode: LDRSB_PRE
-/* 3548 */    MCD_OPC_FilterValue, 3, 184, 18, 0, // Skip to: 8345
+/* 3516 */    MCD_OPC_Decode, 236, 6, 45, // Opcode: LDRSBTr
+/* 3520 */    MCD_OPC_FilterValue, 1, 248, 18, 0, // Skip to: 8381
+/* 3525 */    MCD_OPC_CheckPredicate, 0, 243, 18, 0, // Skip to: 8381
+/* 3530 */    MCD_OPC_Decode, 235, 6, 46, // Opcode: LDRSBTi
+/* 3534 */    MCD_OPC_FilterValue, 1, 234, 18, 0, // Skip to: 8381
+/* 3539 */    MCD_OPC_CheckPredicate, 0, 229, 18, 0, // Skip to: 8381
+/* 3544 */    MCD_OPC_Decode, 238, 6, 7, // Opcode: LDRSB_PRE
+/* 3548 */    MCD_OPC_FilterValue, 3, 220, 18, 0, // Skip to: 8381
 /* 3553 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3556 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3577
-/* 3561 */    MCD_OPC_CheckPredicate, 0, 171, 18, 0, // Skip to: 8345
-/* 3566 */    MCD_OPC_CheckField, 24, 1, 1, 164, 18, 0, // Skip to: 8345
-/* 3573 */    MCD_OPC_Decode, 226, 6, 7, // Opcode: STRD_PRE
-/* 3577 */    MCD_OPC_FilterValue, 1, 155, 18, 0, // Skip to: 8345
+/* 3561 */    MCD_OPC_CheckPredicate, 0, 207, 18, 0, // Skip to: 8381
+/* 3566 */    MCD_OPC_CheckField, 24, 1, 1, 200, 18, 0, // Skip to: 8381
+/* 3573 */    MCD_OPC_Decode, 141, 15, 7, // Opcode: STRD_PRE
+/* 3577 */    MCD_OPC_FilterValue, 1, 191, 18, 0, // Skip to: 8381
 /* 3582 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 3585 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3625
 /* 3590 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 3593 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 3611
-/* 3598 */    MCD_OPC_CheckPredicate, 0, 134, 18, 0, // Skip to: 8345
+/* 3598 */    MCD_OPC_CheckPredicate, 0, 170, 18, 0, // Skip to: 8381
 /* 3603 */    MCD_OPC_SoftFail, 128, 30 /* 0xf00 */, 0,
-/* 3607 */    MCD_OPC_Decode, 152, 5, 45, // Opcode: LDRSHTr
-/* 3611 */    MCD_OPC_FilterValue, 1, 121, 18, 0, // Skip to: 8345
-/* 3616 */    MCD_OPC_CheckPredicate, 0, 116, 18, 0, // Skip to: 8345
-/* 3621 */    MCD_OPC_Decode, 151, 5, 46, // Opcode: LDRSHTi
-/* 3625 */    MCD_OPC_FilterValue, 1, 107, 18, 0, // Skip to: 8345
-/* 3630 */    MCD_OPC_CheckPredicate, 0, 102, 18, 0, // Skip to: 8345
-/* 3635 */    MCD_OPC_Decode, 154, 5, 7, // Opcode: LDRSH_PRE
+/* 3607 */    MCD_OPC_Decode, 241, 6, 45, // Opcode: LDRSHTr
+/* 3611 */    MCD_OPC_FilterValue, 1, 157, 18, 0, // Skip to: 8381
+/* 3616 */    MCD_OPC_CheckPredicate, 0, 152, 18, 0, // Skip to: 8381
+/* 3621 */    MCD_OPC_Decode, 240, 6, 46, // Opcode: LDRSHTi
+/* 3625 */    MCD_OPC_FilterValue, 1, 143, 18, 0, // Skip to: 8381
+/* 3630 */    MCD_OPC_CheckPredicate, 0, 138, 18, 0, // Skip to: 8381
+/* 3635 */    MCD_OPC_Decode, 243, 6, 7, // Opcode: LDRSH_PRE
 /* 3639 */    MCD_OPC_FilterValue, 1, 0, 2, 0, // Skip to: 4156
 /* 3644 */    MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
 /* 3647 */    MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 3853
@@ -787,976 +790,982 @@ static const uint8_t DecoderTableARM32[] = {
 /* 3660 */    MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
 /* 3663 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3677
 /* 3668 */    MCD_OPC_CheckPredicate, 0, 46, 0, 0, // Skip to: 3719
-/* 3673 */    MCD_OPC_Decode, 158, 4, 47, // Opcode: ANDri
+/* 3673 */    MCD_OPC_Decode, 210, 5, 47, // Opcode: ANDri
 /* 3677 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3691
 /* 3682 */    MCD_OPC_CheckPredicate, 0, 32, 0, 0, // Skip to: 3719
-/* 3687 */    MCD_OPC_Decode, 244, 6, 47, // Opcode: SUBri
+/* 3687 */    MCD_OPC_Decode, 159, 15, 47, // Opcode: SUBri
 /* 3691 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3705
 /* 3696 */    MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 3719
-/* 3701 */    MCD_OPC_Decode, 149, 4, 47, // Opcode: ADDri
+/* 3701 */    MCD_OPC_Decode, 201, 5, 47, // Opcode: ADDri
 /* 3705 */    MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3719
 /* 3710 */    MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 3719
-/* 3715 */    MCD_OPC_Decode, 238, 5, 47, // Opcode: SBCri
-/* 3719 */    MCD_OPC_CheckPredicate, 0, 13, 18, 0, // Skip to: 8345
-/* 3724 */    MCD_OPC_CheckField, 16, 5, 15, 6, 18, 0, // Skip to: 8345
-/* 3731 */    MCD_OPC_Decode, 153, 4, 48, // Opcode: ADR
-/* 3735 */    MCD_OPC_FilterValue, 1, 253, 17, 0, // Skip to: 8345
+/* 3715 */    MCD_OPC_Decode, 153, 14, 47, // Opcode: SBCri
+/* 3719 */    MCD_OPC_CheckPredicate, 0, 49, 18, 0, // Skip to: 8381
+/* 3724 */    MCD_OPC_CheckField, 16, 5, 15, 42, 18, 0, // Skip to: 8381
+/* 3731 */    MCD_OPC_Decode, 205, 5, 48, // Opcode: ADR
+/* 3735 */    MCD_OPC_FilterValue, 1, 33, 18, 0, // Skip to: 8381
 /* 3740 */    MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
 /* 3743 */    MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3784
 /* 3748 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3751 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3765
-/* 3756 */    MCD_OPC_CheckPredicate, 13, 232, 17, 0, // Skip to: 8345
-/* 3761 */    MCD_OPC_Decode, 173, 5, 49, // Opcode: MOVi16
-/* 3765 */    MCD_OPC_FilterValue, 1, 223, 17, 0, // Skip to: 8345
-/* 3770 */    MCD_OPC_CheckPredicate, 0, 218, 17, 0, // Skip to: 8345
+/* 3756 */    MCD_OPC_CheckPredicate, 13, 12, 18, 0, // Skip to: 8381
+/* 3761 */    MCD_OPC_Decode, 134, 7, 49, // Opcode: MOVi16
+/* 3765 */    MCD_OPC_FilterValue, 1, 3, 18, 0, // Skip to: 8381
+/* 3770 */    MCD_OPC_CheckPredicate, 0, 254, 17, 0, // Skip to: 8381
 /* 3775 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 3780 */    MCD_OPC_Decode, 136, 7, 50, // Opcode: TSTri
+/* 3780 */    MCD_OPC_Decode, 179, 15, 50, // Opcode: TSTri
 /* 3784 */    MCD_OPC_FilterValue, 1, 36, 0, 0, // Skip to: 3825
 /* 3789 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3792 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3806
-/* 3797 */    MCD_OPC_CheckPredicate, 13, 191, 17, 0, // Skip to: 8345
-/* 3802 */    MCD_OPC_Decode, 171, 5, 49, // Opcode: MOVTi16
-/* 3806 */    MCD_OPC_FilterValue, 1, 182, 17, 0, // Skip to: 8345
-/* 3811 */    MCD_OPC_CheckPredicate, 0, 177, 17, 0, // Skip to: 8345
+/* 3797 */    MCD_OPC_CheckPredicate, 13, 227, 17, 0, // Skip to: 8381
+/* 3802 */    MCD_OPC_Decode, 132, 7, 49, // Opcode: MOVTi16
+/* 3806 */    MCD_OPC_FilterValue, 1, 218, 17, 0, // Skip to: 8381
+/* 3811 */    MCD_OPC_CheckPredicate, 0, 213, 17, 0, // Skip to: 8381
 /* 3816 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 3821 */    MCD_OPC_Decode, 187, 4, 50, // Opcode: CMPri
+/* 3821 */    MCD_OPC_Decode, 148, 6, 50, // Opcode: CMPri
 /* 3825 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 3839
-/* 3830 */    MCD_OPC_CheckPredicate, 0, 158, 17, 0, // Skip to: 8345
-/* 3835 */    MCD_OPC_Decode, 193, 5, 47, // Opcode: ORRri
-/* 3839 */    MCD_OPC_FilterValue, 3, 149, 17, 0, // Skip to: 8345
-/* 3844 */    MCD_OPC_CheckPredicate, 0, 144, 17, 0, // Skip to: 8345
-/* 3849 */    MCD_OPC_Decode, 164, 4, 47, // Opcode: BICri
-/* 3853 */    MCD_OPC_FilterValue, 1, 135, 17, 0, // Skip to: 8345
+/* 3830 */    MCD_OPC_CheckPredicate, 0, 194, 17, 0, // Skip to: 8381
+/* 3835 */    MCD_OPC_Decode, 235, 13, 47, // Opcode: ORRri
+/* 3839 */    MCD_OPC_FilterValue, 3, 185, 17, 0, // Skip to: 8381
+/* 3844 */    MCD_OPC_CheckPredicate, 0, 180, 17, 0, // Skip to: 8381
+/* 3849 */    MCD_OPC_Decode, 223, 5, 47, // Opcode: BICri
+/* 3853 */    MCD_OPC_FilterValue, 1, 171, 17, 0, // Skip to: 8381
 /* 3858 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
 /* 3861 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3897
 /* 3866 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 3869 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3883
-/* 3874 */    MCD_OPC_CheckPredicate, 0, 114, 17, 0, // Skip to: 8345
-/* 3879 */    MCD_OPC_Decode, 203, 4, 47, // Opcode: EORri
-/* 3883 */    MCD_OPC_FilterValue, 1, 105, 17, 0, // Skip to: 8345
-/* 3888 */    MCD_OPC_CheckPredicate, 0, 100, 17, 0, // Skip to: 8345
-/* 3893 */    MCD_OPC_Decode, 227, 5, 47, // Opcode: RSBri
+/* 3874 */    MCD_OPC_CheckPredicate, 0, 150, 17, 0, // Skip to: 8381
+/* 3879 */    MCD_OPC_Decode, 164, 6, 47, // Opcode: EORri
+/* 3883 */    MCD_OPC_FilterValue, 1, 141, 17, 0, // Skip to: 8381
+/* 3888 */    MCD_OPC_CheckPredicate, 0, 136, 17, 0, // Skip to: 8381
+/* 3893 */    MCD_OPC_Decode, 141, 14, 47, // Opcode: RSBri
 /* 3897 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 3933
 /* 3902 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 3905 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3919
-/* 3910 */    MCD_OPC_CheckPredicate, 0, 78, 17, 0, // Skip to: 8345
-/* 3915 */    MCD_OPC_Decode, 145, 4, 47, // Opcode: ADCri
-/* 3919 */    MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8345
-/* 3924 */    MCD_OPC_CheckPredicate, 0, 64, 17, 0, // Skip to: 8345
-/* 3929 */    MCD_OPC_Decode, 231, 5, 47, // Opcode: RSCri
+/* 3910 */    MCD_OPC_CheckPredicate, 0, 114, 17, 0, // Skip to: 8381
+/* 3915 */    MCD_OPC_Decode, 197, 5, 47, // Opcode: ADCri
+/* 3919 */    MCD_OPC_FilterValue, 1, 105, 17, 0, // Skip to: 8381
+/* 3924 */    MCD_OPC_CheckPredicate, 0, 100, 17, 0, // Skip to: 8381
+/* 3929 */    MCD_OPC_Decode, 145, 14, 47, // Opcode: RSCri
 /* 3933 */    MCD_OPC_FilterValue, 2, 168, 0, 0, // Skip to: 4106
 /* 3938 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 3941 */    MCD_OPC_FilterValue, 0, 114, 0, 0, // Skip to: 4060
 /* 3946 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 3949 */    MCD_OPC_FilterValue, 15, 39, 17, 0, // Skip to: 8345
+/* 3949 */    MCD_OPC_FilterValue, 15, 75, 17, 0, // Skip to: 8381
 /* 3954 */    MCD_OPC_CheckPredicate, 14, 32, 0, 0, // Skip to: 3991
 /* 3959 */    MCD_OPC_CheckField, 28, 4, 14, 25, 0, 0, // Skip to: 3991
 /* 3966 */    MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 3991
 /* 3973 */    MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 3991
 /* 3980 */    MCD_OPC_CheckField, 0, 12, 18, 4, 0, 0, // Skip to: 3991
-/* 3987 */    MCD_OPC_Decode, 135, 7, 51, // Opcode: TSB
+/* 3987 */    MCD_OPC_Decode, 178, 15, 51, // Opcode: TSB
 /* 3991 */    MCD_OPC_CheckPredicate, 15, 25, 0, 0, // Skip to: 4021
 /* 3996 */    MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4021
 /* 4003 */    MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4021
 /* 4010 */    MCD_OPC_CheckField, 4, 8, 15, 4, 0, 0, // Skip to: 4021
-/* 4017 */    MCD_OPC_Decode, 200, 4, 36, // Opcode: DBG
+/* 4017 */    MCD_OPC_Decode, 161, 6, 36, // Opcode: DBG
 /* 4021 */    MCD_OPC_CheckPredicate, 1, 25, 0, 0, // Skip to: 4051
 /* 4026 */    MCD_OPC_CheckField, 22, 1, 0, 18, 0, 0, // Skip to: 4051
 /* 4033 */    MCD_OPC_CheckField, 16, 4, 0, 11, 0, 0, // Skip to: 4051
 /* 4040 */    MCD_OPC_CheckField, 8, 4, 0, 4, 0, 0, // Skip to: 4051
-/* 4047 */    MCD_OPC_Decode, 218, 4, 52, // Opcode: HINT
-/* 4051 */    MCD_OPC_CheckPredicate, 0, 193, 16, 0, // Skip to: 8345
-/* 4056 */    MCD_OPC_Decode, 187, 5, 53, // Opcode: MSRi
-/* 4060 */    MCD_OPC_FilterValue, 1, 184, 16, 0, // Skip to: 8345
+/* 4047 */    MCD_OPC_Decode, 179, 6, 52, // Opcode: HINT
+/* 4051 */    MCD_OPC_CheckPredicate, 0, 229, 16, 0, // Skip to: 8381
+/* 4056 */    MCD_OPC_Decode, 148, 7, 53, // Opcode: MSRi
+/* 4060 */    MCD_OPC_FilterValue, 1, 220, 16, 0, // Skip to: 8381
 /* 4065 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 4068 */    MCD_OPC_FilterValue, 0, 14, 0, 0, // Skip to: 4087
-/* 4073 */    MCD_OPC_CheckPredicate, 0, 171, 16, 0, // Skip to: 8345
+/* 4073 */    MCD_OPC_CheckPredicate, 0, 207, 16, 0, // Skip to: 8381
 /* 4078 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 4083 */    MCD_OPC_Decode, 129, 7, 50, // Opcode: TEQri
-/* 4087 */    MCD_OPC_FilterValue, 1, 157, 16, 0, // Skip to: 8345
-/* 4092 */    MCD_OPC_CheckPredicate, 0, 152, 16, 0, // Skip to: 8345
+/* 4083 */    MCD_OPC_Decode, 172, 15, 50, // Opcode: TEQri
+/* 4087 */    MCD_OPC_FilterValue, 1, 193, 16, 0, // Skip to: 8381
+/* 4092 */    MCD_OPC_CheckPredicate, 0, 188, 16, 0, // Skip to: 8381
 /* 4097 */    MCD_OPC_SoftFail, 128, 224, 3 /* 0xf000 */, 0,
-/* 4102 */    MCD_OPC_Decode, 183, 4, 50, // Opcode: CMNri
-/* 4106 */    MCD_OPC_FilterValue, 3, 138, 16, 0, // Skip to: 8345
+/* 4102 */    MCD_OPC_Decode, 144, 6, 50, // Opcode: CMNri
+/* 4106 */    MCD_OPC_FilterValue, 3, 174, 16, 0, // Skip to: 8381
 /* 4111 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
 /* 4114 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4135
-/* 4119 */    MCD_OPC_CheckPredicate, 0, 125, 16, 0, // Skip to: 8345
-/* 4124 */    MCD_OPC_CheckField, 16, 4, 0, 118, 16, 0, // Skip to: 8345
-/* 4131 */    MCD_OPC_Decode, 172, 5, 54, // Opcode: MOVi
-/* 4135 */    MCD_OPC_FilterValue, 1, 109, 16, 0, // Skip to: 8345
-/* 4140 */    MCD_OPC_CheckPredicate, 0, 104, 16, 0, // Skip to: 8345
-/* 4145 */    MCD_OPC_CheckField, 16, 4, 0, 97, 16, 0, // Skip to: 8345
-/* 4152 */    MCD_OPC_Decode, 189, 5, 54, // Opcode: MVNi
-/* 4156 */    MCD_OPC_FilterValue, 2, 229, 1, 0, // Skip to: 4646
+/* 4119 */    MCD_OPC_CheckPredicate, 0, 161, 16, 0, // Skip to: 8381
+/* 4124 */    MCD_OPC_CheckField, 16, 4, 0, 154, 16, 0, // Skip to: 8381
+/* 4131 */    MCD_OPC_Decode, 133, 7, 54, // Opcode: MOVi
+/* 4135 */    MCD_OPC_FilterValue, 1, 145, 16, 0, // Skip to: 8381
+/* 4140 */    MCD_OPC_CheckPredicate, 0, 140, 16, 0, // Skip to: 8381
+/* 4145 */    MCD_OPC_CheckField, 16, 4, 0, 133, 16, 0, // Skip to: 8381
+/* 4152 */    MCD_OPC_Decode, 223, 13, 54, // Opcode: MVNi
+/* 4156 */    MCD_OPC_FilterValue, 2, 9, 2, 0, // Skip to: 4682
 /* 4161 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
 /* 4164 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4200
 /* 4169 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4172 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4186
-/* 4177 */    MCD_OPC_CheckPredicate, 0, 67, 16, 0, // Skip to: 8345
-/* 4182 */    MCD_OPC_Decode, 238, 6, 55, // Opcode: STR_POST_IMM
-/* 4186 */    MCD_OPC_FilterValue, 1, 58, 16, 0, // Skip to: 8345
-/* 4191 */    MCD_OPC_CheckPredicate, 0, 53, 16, 0, // Skip to: 8345
-/* 4196 */    MCD_OPC_Decode, 242, 6, 56, // Opcode: STRi12
+/* 4177 */    MCD_OPC_CheckPredicate, 0, 103, 16, 0, // Skip to: 8381
+/* 4182 */    MCD_OPC_Decode, 153, 15, 55, // Opcode: STR_POST_IMM
+/* 4186 */    MCD_OPC_FilterValue, 1, 94, 16, 0, // Skip to: 8381
+/* 4191 */    MCD_OPC_CheckPredicate, 0, 89, 16, 0, // Skip to: 8381
+/* 4196 */    MCD_OPC_Decode, 157, 15, 56, // Opcode: STRi12
 /* 4200 */    MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 4259
 /* 4205 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4208 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4222
-/* 4213 */    MCD_OPC_CheckPredicate, 0, 31, 16, 0, // Skip to: 8345
-/* 4218 */    MCD_OPC_Decode, 157, 5, 55, // Opcode: LDR_POST_IMM
-/* 4222 */    MCD_OPC_FilterValue, 1, 22, 16, 0, // Skip to: 8345
+/* 4213 */    MCD_OPC_CheckPredicate, 0, 67, 16, 0, // Skip to: 8381
+/* 4218 */    MCD_OPC_Decode, 246, 6, 55, // Opcode: LDR_POST_IMM
+/* 4222 */    MCD_OPC_FilterValue, 1, 58, 16, 0, // Skip to: 8381
 /* 4227 */    MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4250
 /* 4232 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4250
 /* 4239 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4250
-/* 4246 */    MCD_OPC_Decode, 199, 5, 57, // Opcode: PLDWi12
-/* 4250 */    MCD_OPC_CheckPredicate, 0, 250, 15, 0, // Skip to: 8345
-/* 4255 */    MCD_OPC_Decode, 162, 5, 56, // Opcode: LDRi12
+/* 4246 */    MCD_OPC_Decode, 241, 13, 57, // Opcode: PLDWi12
+/* 4250 */    MCD_OPC_CheckPredicate, 0, 30, 16, 0, // Skip to: 8381
+/* 4255 */    MCD_OPC_Decode, 251, 6, 56, // Opcode: LDRi12
 /* 4259 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 4295
 /* 4264 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4267 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4281
-/* 4272 */    MCD_OPC_CheckPredicate, 0, 228, 15, 0, // Skip to: 8345
-/* 4277 */    MCD_OPC_Decode, 236, 6, 55, // Opcode: STRT_POST_IMM
-/* 4281 */    MCD_OPC_FilterValue, 1, 219, 15, 0, // Skip to: 8345
-/* 4286 */    MCD_OPC_CheckPredicate, 0, 214, 15, 0, // Skip to: 8345
-/* 4291 */    MCD_OPC_Decode, 240, 6, 58, // Opcode: STR_PRE_IMM
+/* 4272 */    MCD_OPC_CheckPredicate, 0, 8, 16, 0, // Skip to: 8381
+/* 4277 */    MCD_OPC_Decode, 151, 15, 55, // Opcode: STRT_POST_IMM
+/* 4281 */    MCD_OPC_FilterValue, 1, 255, 15, 0, // Skip to: 8381
+/* 4286 */    MCD_OPC_CheckPredicate, 0, 250, 15, 0, // Skip to: 8381
+/* 4291 */    MCD_OPC_Decode, 155, 15, 58, // Opcode: STR_PRE_IMM
 /* 4295 */    MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 4331
 /* 4300 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4303 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4317
-/* 4308 */    MCD_OPC_CheckPredicate, 0, 192, 15, 0, // Skip to: 8345
-/* 4313 */    MCD_OPC_Decode, 155, 5, 55, // Opcode: LDRT_POST_IMM
-/* 4317 */    MCD_OPC_FilterValue, 1, 183, 15, 0, // Skip to: 8345
-/* 4322 */    MCD_OPC_CheckPredicate, 0, 178, 15, 0, // Skip to: 8345
-/* 4327 */    MCD_OPC_Decode, 159, 5, 59, // Opcode: LDR_PRE_IMM
+/* 4308 */    MCD_OPC_CheckPredicate, 0, 228, 15, 0, // Skip to: 8381
+/* 4313 */    MCD_OPC_Decode, 244, 6, 55, // Opcode: LDRT_POST_IMM
+/* 4317 */    MCD_OPC_FilterValue, 1, 219, 15, 0, // Skip to: 8381
+/* 4322 */    MCD_OPC_CheckPredicate, 0, 214, 15, 0, // Skip to: 8381
+/* 4327 */    MCD_OPC_Decode, 248, 6, 59, // Opcode: LDR_PRE_IMM
 /* 4331 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 4367
 /* 4336 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4339 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4353
-/* 4344 */    MCD_OPC_CheckPredicate, 0, 156, 15, 0, // Skip to: 8345
-/* 4349 */    MCD_OPC_Decode, 218, 6, 55, // Opcode: STRB_POST_IMM
-/* 4353 */    MCD_OPC_FilterValue, 1, 147, 15, 0, // Skip to: 8345
-/* 4358 */    MCD_OPC_CheckPredicate, 0, 142, 15, 0, // Skip to: 8345
-/* 4363 */    MCD_OPC_Decode, 222, 6, 60, // Opcode: STRBi12
+/* 4344 */    MCD_OPC_CheckPredicate, 0, 192, 15, 0, // Skip to: 8381
+/* 4349 */    MCD_OPC_Decode, 133, 15, 55, // Opcode: STRB_POST_IMM
+/* 4353 */    MCD_OPC_FilterValue, 1, 183, 15, 0, // Skip to: 8381
+/* 4358 */    MCD_OPC_CheckPredicate, 0, 178, 15, 0, // Skip to: 8381
+/* 4363 */    MCD_OPC_Decode, 137, 15, 60, // Opcode: STRBi12
 /* 4367 */    MCD_OPC_FilterValue, 5, 77, 0, 0, // Skip to: 4449
 /* 4372 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4375 */    MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 4412
 /* 4380 */    MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 4403
 /* 4385 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4403
 /* 4392 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4403
-/* 4399 */    MCD_OPC_Decode, 203, 5, 57, // Opcode: PLIi12
-/* 4403 */    MCD_OPC_CheckPredicate, 0, 97, 15, 0, // Skip to: 8345
-/* 4408 */    MCD_OPC_Decode, 255, 4, 55, // Opcode: LDRB_POST_IMM
-/* 4412 */    MCD_OPC_FilterValue, 1, 88, 15, 0, // Skip to: 8345
+/* 4399 */    MCD_OPC_Decode, 245, 13, 57, // Opcode: PLIi12
+/* 4403 */    MCD_OPC_CheckPredicate, 0, 133, 15, 0, // Skip to: 8381
+/* 4408 */    MCD_OPC_Decode, 216, 6, 55, // Opcode: LDRB_POST_IMM
+/* 4412 */    MCD_OPC_FilterValue, 1, 124, 15, 0, // Skip to: 8381
 /* 4417 */    MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 4440
 /* 4422 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4440
 /* 4429 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4440
-/* 4436 */    MCD_OPC_Decode, 201, 5, 57, // Opcode: PLDi12
-/* 4440 */    MCD_OPC_CheckPredicate, 0, 60, 15, 0, // Skip to: 8345
-/* 4445 */    MCD_OPC_Decode, 131, 5, 60, // Opcode: LDRBi12
+/* 4436 */    MCD_OPC_Decode, 243, 13, 57, // Opcode: PLDi12
+/* 4440 */    MCD_OPC_CheckPredicate, 0, 96, 15, 0, // Skip to: 8381
+/* 4445 */    MCD_OPC_Decode, 220, 6, 60, // Opcode: LDRBi12
 /* 4449 */    MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4485
 /* 4454 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4457 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4471
-/* 4462 */    MCD_OPC_CheckPredicate, 0, 38, 15, 0, // Skip to: 8345
-/* 4467 */    MCD_OPC_Decode, 216, 6, 55, // Opcode: STRBT_POST_IMM
-/* 4471 */    MCD_OPC_FilterValue, 1, 29, 15, 0, // Skip to: 8345
-/* 4476 */    MCD_OPC_CheckPredicate, 0, 24, 15, 0, // Skip to: 8345
-/* 4481 */    MCD_OPC_Decode, 220, 6, 58, // Opcode: STRB_PRE_IMM
-/* 4485 */    MCD_OPC_FilterValue, 7, 15, 15, 0, // Skip to: 8345
+/* 4462 */    MCD_OPC_CheckPredicate, 0, 74, 15, 0, // Skip to: 8381
+/* 4467 */    MCD_OPC_Decode, 131, 15, 55, // Opcode: STRBT_POST_IMM
+/* 4471 */    MCD_OPC_FilterValue, 1, 65, 15, 0, // Skip to: 8381
+/* 4476 */    MCD_OPC_CheckPredicate, 0, 60, 15, 0, // Skip to: 8381
+/* 4481 */    MCD_OPC_Decode, 135, 15, 58, // Opcode: STRB_PRE_IMM
+/* 4485 */    MCD_OPC_FilterValue, 7, 51, 15, 0, // Skip to: 8381
 /* 4490 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4493 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4507
-/* 4498 */    MCD_OPC_CheckPredicate, 0, 2, 15, 0, // Skip to: 8345
-/* 4503 */    MCD_OPC_Decode, 253, 4, 55, // Opcode: LDRBT_POST_IMM
-/* 4507 */    MCD_OPC_FilterValue, 1, 249, 14, 0, // Skip to: 8345
+/* 4498 */    MCD_OPC_CheckPredicate, 0, 38, 15, 0, // Skip to: 8381
+/* 4503 */    MCD_OPC_Decode, 214, 6, 55, // Opcode: LDRBT_POST_IMM
+/* 4507 */    MCD_OPC_FilterValue, 1, 29, 15, 0, // Skip to: 8381
 /* 4512 */    MCD_OPC_CheckPredicate, 17, 27, 0, 0, // Skip to: 4544
 /* 4517 */    MCD_OPC_CheckField, 28, 4, 15, 20, 0, 0, // Skip to: 4544
 /* 4524 */    MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 4544
 /* 4531 */    MCD_OPC_CheckField, 0, 20, 159, 224, 63, 4, 0, 0, // Skip to: 4544
-/* 4540 */    MCD_OPC_Decode, 181, 4, 51, // Opcode: CLREX
+/* 4540 */    MCD_OPC_Decode, 142, 6, 61, // Opcode: CLREX
 /* 4544 */    MCD_OPC_ExtractField, 4, 16,  // Inst{19-4} ...
 /* 4547 */    MCD_OPC_FilterValue, 132, 254, 3, 23, 0, 0, // Skip to: 4577
 /* 4554 */    MCD_OPC_CheckPredicate, 18, 78, 0, 0, // Skip to: 4637
 /* 4559 */    MCD_OPC_CheckField, 28, 4, 15, 71, 0, 0, // Skip to: 4637
 /* 4566 */    MCD_OPC_CheckField, 23, 1, 0, 64, 0, 0, // Skip to: 4637
-/* 4573 */    MCD_OPC_Decode, 202, 4, 61, // Opcode: DSB
+/* 4573 */    MCD_OPC_Decode, 163, 6, 62, // Opcode: DSB
 /* 4577 */    MCD_OPC_FilterValue, 133, 254, 3, 23, 0, 0, // Skip to: 4607
 /* 4584 */    MCD_OPC_CheckPredicate, 18, 48, 0, 0, // Skip to: 4637
 /* 4589 */    MCD_OPC_CheckField, 28, 4, 15, 41, 0, 0, // Skip to: 4637
 /* 4596 */    MCD_OPC_CheckField, 23, 1, 0, 34, 0, 0, // Skip to: 4637
-/* 4603 */    MCD_OPC_Decode, 201, 4, 61, // Opcode: DMB
+/* 4603 */    MCD_OPC_Decode, 162, 6, 62, // Opcode: DMB
 /* 4607 */    MCD_OPC_FilterValue, 134, 254, 3, 23, 0, 0, // Skip to: 4637
 /* 4614 */    MCD_OPC_CheckPredicate, 18, 18, 0, 0, // Skip to: 4637
 /* 4619 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4637
 /* 4626 */    MCD_OPC_CheckField, 23, 1, 0, 4, 0, 0, // Skip to: 4637
-/* 4633 */    MCD_OPC_Decode, 221, 4, 62, // Opcode: ISB
-/* 4637 */    MCD_OPC_CheckPredicate, 0, 119, 14, 0, // Skip to: 8345
-/* 4642 */    MCD_OPC_Decode, 129, 5, 59, // Opcode: LDRB_PRE_IMM
-/* 4646 */    MCD_OPC_FilterValue, 3, 129, 10, 0, // Skip to: 7340
-/* 4651 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
-/* 4654 */    MCD_OPC_FilterValue, 0, 200, 2, 0, // Skip to: 5371
-/* 4659 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 4662 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 4765
-/* 4667 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4670 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4706
-/* 4675 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 4678 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4692
-/* 4683 */    MCD_OPC_CheckPredicate, 0, 73, 14, 0, // Skip to: 8345
-/* 4688 */    MCD_OPC_Decode, 239, 6, 55, // Opcode: STR_POST_REG
-/* 4692 */    MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 8345
-/* 4697 */    MCD_OPC_CheckPredicate, 0, 59, 14, 0, // Skip to: 8345
-/* 4702 */    MCD_OPC_Decode, 243, 6, 63, // Opcode: STRrs
-/* 4706 */    MCD_OPC_FilterValue, 1, 50, 14, 0, // Skip to: 8345
+/* 4633 */    MCD_OPC_Decode, 182, 6, 63, // Opcode: ISB
+/* 4637 */    MCD_OPC_CheckPredicate, 19, 31, 0, 0, // Skip to: 4673
+/* 4642 */    MCD_OPC_CheckField, 28, 4, 15, 24, 0, 0, // Skip to: 4673
+/* 4649 */    MCD_OPC_CheckField, 23, 1, 0, 17, 0, 0, // Skip to: 4673
+/* 4656 */    MCD_OPC_CheckField, 4, 4, 7, 10, 0, 0, // Skip to: 4673
+/* 4663 */    MCD_OPC_SoftFail, 143, 30 /* 0xf0f */, 128, 224, 63 /* 0xff000 */,
+/* 4669 */    MCD_OPC_Decode, 152, 14, 61, // Opcode: SB
+/* 4673 */    MCD_OPC_CheckPredicate, 0, 119, 14, 0, // Skip to: 8381
+/* 4678 */    MCD_OPC_Decode, 218, 6, 59, // Opcode: LDRB_PRE_IMM
+/* 4682 */    MCD_OPC_FilterValue, 3, 129, 10, 0, // Skip to: 7376
+/* 4687 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 4690 */    MCD_OPC_FilterValue, 0, 200, 2, 0, // Skip to: 5407
+/* 4695 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 4698 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 4801
+/* 4703 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 4706 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4742
 /* 4711 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 4714 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4728
-/* 4719 */    MCD_OPC_CheckPredicate, 0, 37, 14, 0, // Skip to: 8345
-/* 4724 */    MCD_OPC_Decode, 158, 5, 55, // Opcode: LDR_POST_REG
-/* 4728 */    MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 8345
-/* 4733 */    MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4756
-/* 4738 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4756
-/* 4745 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4756
-/* 4752 */    MCD_OPC_Decode, 200, 5, 64, // Opcode: PLDWrs
-/* 4756 */    MCD_OPC_CheckPredicate, 0, 0, 14, 0, // Skip to: 8345
-/* 4761 */    MCD_OPC_Decode, 163, 5, 63, // Opcode: LDRrs
-/* 4765 */    MCD_OPC_FilterValue, 1, 247, 13, 0, // Skip to: 8345
-/* 4770 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
-/* 4773 */    MCD_OPC_FilterValue, 0, 202, 0, 0, // Skip to: 4980
-/* 4778 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 4781 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 4839
-/* 4786 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 4789 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 4814
-/* 4794 */    MCD_OPC_CheckPredicate, 0, 218, 13, 0, // Skip to: 8345
-/* 4799 */    MCD_OPC_CheckField, 20, 1, 1, 211, 13, 0, // Skip to: 8345
-/* 4806 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 4810 */    MCD_OPC_Decode, 235, 5, 65, // Opcode: SADD16
-/* 4814 */    MCD_OPC_FilterValue, 1, 198, 13, 0, // Skip to: 8345
-/* 4819 */    MCD_OPC_CheckPredicate, 0, 193, 13, 0, // Skip to: 8345
-/* 4824 */    MCD_OPC_CheckField, 20, 1, 1, 186, 13, 0, // Skip to: 8345
-/* 4831 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 4835 */    MCD_OPC_Decode, 236, 5, 65, // Opcode: SADD8
-/* 4839 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4860
-/* 4844 */    MCD_OPC_CheckPredicate, 1, 168, 13, 0, // Skip to: 8345
-/* 4849 */    MCD_OPC_CheckField, 20, 1, 0, 161, 13, 0, // Skip to: 8345
-/* 4856 */    MCD_OPC_Decode, 197, 5, 66, // Opcode: PKHBT
-/* 4860 */    MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 4934
-/* 4865 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4868 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 4906
-/* 4873 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 4876 */    MCD_OPC_FilterValue, 0, 136, 13, 0, // Skip to: 8345
-/* 4881 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4897
-/* 4886 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4897
-/* 4893 */    MCD_OPC_Decode, 161, 6, 67, // Opcode: SMUAD
-/* 4897 */    MCD_OPC_CheckPredicate, 1, 115, 13, 0, // Skip to: 8345
-/* 4902 */    MCD_OPC_Decode, 138, 6, 68, // Opcode: SMLAD
-/* 4906 */    MCD_OPC_FilterValue, 1, 106, 13, 0, // Skip to: 8345
-/* 4911 */    MCD_OPC_CheckPredicate, 19, 101, 13, 0, // Skip to: 8345
-/* 4916 */    MCD_OPC_CheckField, 12, 4, 15, 94, 13, 0, // Skip to: 8345
-/* 4923 */    MCD_OPC_CheckField, 7, 1, 0, 87, 13, 0, // Skip to: 8345
-/* 4930 */    MCD_OPC_Decode, 243, 5, 30, // Opcode: SDIV
-/* 4934 */    MCD_OPC_FilterValue, 3, 78, 13, 0, // Skip to: 8345
-/* 4939 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 4942 */    MCD_OPC_FilterValue, 0, 70, 13, 0, // Skip to: 8345
-/* 4947 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4950 */    MCD_OPC_FilterValue, 0, 62, 13, 0, // Skip to: 8345
-/* 4955 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4971
-/* 4960 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4971
-/* 4967 */    MCD_OPC_Decode, 161, 7, 30, // Opcode: USAD8
-/* 4971 */    MCD_OPC_CheckPredicate, 1, 41, 13, 0, // Skip to: 8345
-/* 4976 */    MCD_OPC_Decode, 162, 7, 39, // Opcode: USADA8
-/* 4980 */    MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 5098
-/* 4985 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 4988 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5020
-/* 4993 */    MCD_OPC_CheckPredicate, 0, 19, 13, 0, // Skip to: 8345
-/* 4998 */    MCD_OPC_CheckField, 20, 1, 1, 12, 13, 0, // Skip to: 8345
-/* 5005 */    MCD_OPC_CheckField, 7, 1, 0, 5, 13, 0, // Skip to: 8345
-/* 5012 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5016 */    MCD_OPC_Decode, 237, 5, 65, // Opcode: SASX
-/* 5020 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5052
-/* 5025 */    MCD_OPC_CheckPredicate, 1, 243, 12, 0, // Skip to: 8345
-/* 5030 */    MCD_OPC_CheckField, 20, 1, 0, 236, 12, 0, // Skip to: 8345
-/* 5037 */    MCD_OPC_CheckField, 7, 1, 1, 229, 12, 0, // Skip to: 8345
-/* 5044 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5048 */    MCD_OPC_Decode, 244, 5, 69, // Opcode: SEL
-/* 5052 */    MCD_OPC_FilterValue, 2, 216, 12, 0, // Skip to: 8345
-/* 5057 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 5060 */    MCD_OPC_FilterValue, 0, 208, 12, 0, // Skip to: 8345
-/* 5065 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5068 */    MCD_OPC_FilterValue, 0, 200, 12, 0, // Skip to: 8345
-/* 5073 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5089
-/* 5078 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5089
-/* 5085 */    MCD_OPC_Decode, 162, 6, 67, // Opcode: SMUADX
-/* 5089 */    MCD_OPC_CheckPredicate, 1, 179, 12, 0, // Skip to: 8345
-/* 5094 */    MCD_OPC_Decode, 139, 6, 68, // Opcode: SMLADX
-/* 5098 */    MCD_OPC_FilterValue, 2, 102, 0, 0, // Skip to: 5205
-/* 5103 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 5106 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5138
-/* 5111 */    MCD_OPC_CheckPredicate, 0, 157, 12, 0, // Skip to: 8345
-/* 5116 */    MCD_OPC_CheckField, 20, 1, 1, 150, 12, 0, // Skip to: 8345
-/* 5123 */    MCD_OPC_CheckField, 7, 1, 0, 143, 12, 0, // Skip to: 8345
-/* 5130 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5134 */    MCD_OPC_Decode, 182, 6, 65, // Opcode: SSAX
-/* 5138 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5159
-/* 5143 */    MCD_OPC_CheckPredicate, 1, 125, 12, 0, // Skip to: 8345
-/* 5148 */    MCD_OPC_CheckField, 20, 1, 0, 118, 12, 0, // Skip to: 8345
-/* 5155 */    MCD_OPC_Decode, 198, 5, 66, // Opcode: PKHTB
-/* 5159 */    MCD_OPC_FilterValue, 2, 109, 12, 0, // Skip to: 8345
-/* 5164 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 5167 */    MCD_OPC_FilterValue, 0, 101, 12, 0, // Skip to: 8345
-/* 5172 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5175 */    MCD_OPC_FilterValue, 0, 93, 12, 0, // Skip to: 8345
-/* 5180 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5196
-/* 5185 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5196
-/* 5192 */    MCD_OPC_Decode, 170, 6, 67, // Opcode: SMUSD
-/* 5196 */    MCD_OPC_CheckPredicate, 1, 72, 12, 0, // Skip to: 8345
-/* 5201 */    MCD_OPC_Decode, 151, 6, 68, // Opcode: SMLSD
-/* 5205 */    MCD_OPC_FilterValue, 3, 63, 12, 0, // Skip to: 8345
-/* 5210 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 5213 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 5271
-/* 5218 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 5221 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 5246
-/* 5226 */    MCD_OPC_CheckPredicate, 0, 42, 12, 0, // Skip to: 8345
-/* 5231 */    MCD_OPC_CheckField, 20, 1, 1, 35, 12, 0, // Skip to: 8345
-/* 5238 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5242 */    MCD_OPC_Decode, 183, 6, 65, // Opcode: SSUB16
-/* 5246 */    MCD_OPC_FilterValue, 1, 22, 12, 0, // Skip to: 8345
-/* 5251 */    MCD_OPC_CheckPredicate, 0, 17, 12, 0, // Skip to: 8345
-/* 5256 */    MCD_OPC_CheckField, 20, 1, 1, 10, 12, 0, // Skip to: 8345
-/* 5263 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5267 */    MCD_OPC_Decode, 184, 6, 65, // Opcode: SSUB8
-/* 5271 */    MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 5325
-/* 5276 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 5279 */    MCD_OPC_FilterValue, 0, 245, 11, 0, // Skip to: 8345
-/* 5284 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5287 */    MCD_OPC_FilterValue, 0, 237, 11, 0, // Skip to: 8345
-/* 5292 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5312
-/* 5297 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5312
-/* 5304 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 5308 */    MCD_OPC_Decode, 255, 6, 70, // Opcode: SXTB16
-/* 5312 */    MCD_OPC_CheckPredicate, 1, 212, 11, 0, // Skip to: 8345
-/* 5317 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 5321 */    MCD_OPC_Decode, 252, 6, 71, // Opcode: SXTAB16
-/* 5325 */    MCD_OPC_FilterValue, 2, 199, 11, 0, // Skip to: 8345
-/* 5330 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 5333 */    MCD_OPC_FilterValue, 0, 191, 11, 0, // Skip to: 8345
-/* 5338 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5341 */    MCD_OPC_FilterValue, 0, 183, 11, 0, // Skip to: 8345
-/* 5346 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5362
-/* 5351 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5362
-/* 5358 */    MCD_OPC_Decode, 171, 6, 67, // Opcode: SMUSDX
-/* 5362 */    MCD_OPC_CheckPredicate, 1, 162, 11, 0, // Skip to: 8345
-/* 5367 */    MCD_OPC_Decode, 152, 6, 68, // Opcode: SMLSDX
-/* 5371 */    MCD_OPC_FilterValue, 1, 106, 2, 0, // Skip to: 5994
-/* 5376 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 5379 */    MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 5459
-/* 5384 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5387 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5423
-/* 5392 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 5395 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5409
-/* 5400 */    MCD_OPC_CheckPredicate, 0, 124, 11, 0, // Skip to: 8345
-/* 5405 */    MCD_OPC_Decode, 237, 6, 55, // Opcode: STRT_POST_REG
-/* 5409 */    MCD_OPC_FilterValue, 1, 115, 11, 0, // Skip to: 8345
-/* 5414 */    MCD_OPC_CheckPredicate, 0, 110, 11, 0, // Skip to: 8345
-/* 5419 */    MCD_OPC_Decode, 241, 6, 72, // Opcode: STR_PRE_REG
-/* 5423 */    MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 8345
+/* 4719 */    MCD_OPC_CheckPredicate, 0, 73, 14, 0, // Skip to: 8381
+/* 4724 */    MCD_OPC_Decode, 154, 15, 55, // Opcode: STR_POST_REG
+/* 4728 */    MCD_OPC_FilterValue, 1, 64, 14, 0, // Skip to: 8381
+/* 4733 */    MCD_OPC_CheckPredicate, 0, 59, 14, 0, // Skip to: 8381
+/* 4738 */    MCD_OPC_Decode, 158, 15, 64, // Opcode: STRrs
+/* 4742 */    MCD_OPC_FilterValue, 1, 50, 14, 0, // Skip to: 8381
+/* 4747 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 4750 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4764
+/* 4755 */    MCD_OPC_CheckPredicate, 0, 37, 14, 0, // Skip to: 8381
+/* 4760 */    MCD_OPC_Decode, 247, 6, 55, // Opcode: LDR_POST_REG
+/* 4764 */    MCD_OPC_FilterValue, 1, 28, 14, 0, // Skip to: 8381
+/* 4769 */    MCD_OPC_CheckPredicate, 16, 18, 0, 0, // Skip to: 4792
+/* 4774 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 4792
+/* 4781 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4792
+/* 4788 */    MCD_OPC_Decode, 242, 13, 65, // Opcode: PLDWrs
+/* 4792 */    MCD_OPC_CheckPredicate, 0, 0, 14, 0, // Skip to: 8381
+/* 4797 */    MCD_OPC_Decode, 252, 6, 64, // Opcode: LDRrs
+/* 4801 */    MCD_OPC_FilterValue, 1, 247, 13, 0, // Skip to: 8381
+/* 4806 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
+/* 4809 */    MCD_OPC_FilterValue, 0, 202, 0, 0, // Skip to: 5016
+/* 4814 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 4817 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 4875
+/* 4822 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4825 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 4850
+/* 4830 */    MCD_OPC_CheckPredicate, 0, 218, 13, 0, // Skip to: 8381
+/* 4835 */    MCD_OPC_CheckField, 20, 1, 1, 211, 13, 0, // Skip to: 8381
+/* 4842 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 4846 */    MCD_OPC_Decode, 149, 14, 66, // Opcode: SADD16
+/* 4850 */    MCD_OPC_FilterValue, 1, 198, 13, 0, // Skip to: 8381
+/* 4855 */    MCD_OPC_CheckPredicate, 0, 193, 13, 0, // Skip to: 8381
+/* 4860 */    MCD_OPC_CheckField, 20, 1, 1, 186, 13, 0, // Skip to: 8381
+/* 4867 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 4871 */    MCD_OPC_Decode, 150, 14, 66, // Opcode: SADD8
+/* 4875 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4896
+/* 4880 */    MCD_OPC_CheckPredicate, 1, 168, 13, 0, // Skip to: 8381
+/* 4885 */    MCD_OPC_CheckField, 20, 1, 0, 161, 13, 0, // Skip to: 8381
+/* 4892 */    MCD_OPC_Decode, 239, 13, 67, // Opcode: PKHBT
+/* 4896 */    MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 4970
+/* 4901 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 4904 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 4942
+/* 4909 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4912 */    MCD_OPC_FilterValue, 0, 136, 13, 0, // Skip to: 8381
+/* 4917 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 4933
+/* 4922 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 4933
+/* 4929 */    MCD_OPC_Decode, 204, 14, 68, // Opcode: SMUAD
+/* 4933 */    MCD_OPC_CheckPredicate, 1, 115, 13, 0, // Skip to: 8381
+/* 4938 */    MCD_OPC_Decode, 181, 14, 69, // Opcode: SMLAD
+/* 4942 */    MCD_OPC_FilterValue, 1, 106, 13, 0, // Skip to: 8381
+/* 4947 */    MCD_OPC_CheckPredicate, 20, 101, 13, 0, // Skip to: 8381
+/* 4952 */    MCD_OPC_CheckField, 12, 4, 15, 94, 13, 0, // Skip to: 8381
+/* 4959 */    MCD_OPC_CheckField, 7, 1, 0, 87, 13, 0, // Skip to: 8381
+/* 4966 */    MCD_OPC_Decode, 158, 14, 30, // Opcode: SDIV
+/* 4970 */    MCD_OPC_FilterValue, 3, 78, 13, 0, // Skip to: 8381
+/* 4975 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4978 */    MCD_OPC_FilterValue, 0, 70, 13, 0, // Skip to: 8381
+/* 4983 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 4986 */    MCD_OPC_FilterValue, 0, 62, 13, 0, // Skip to: 8381
+/* 4991 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5007
+/* 4996 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5007
+/* 5003 */    MCD_OPC_Decode, 204, 15, 30, // Opcode: USAD8
+/* 5007 */    MCD_OPC_CheckPredicate, 1, 41, 13, 0, // Skip to: 8381
+/* 5012 */    MCD_OPC_Decode, 205, 15, 39, // Opcode: USADA8
+/* 5016 */    MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 5134
+/* 5021 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 5024 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5056
+/* 5029 */    MCD_OPC_CheckPredicate, 0, 19, 13, 0, // Skip to: 8381
+/* 5034 */    MCD_OPC_CheckField, 20, 1, 1, 12, 13, 0, // Skip to: 8381
+/* 5041 */    MCD_OPC_CheckField, 7, 1, 0, 5, 13, 0, // Skip to: 8381
+/* 5048 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5052 */    MCD_OPC_Decode, 151, 14, 66, // Opcode: SASX
+/* 5056 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5088
+/* 5061 */    MCD_OPC_CheckPredicate, 1, 243, 12, 0, // Skip to: 8381
+/* 5066 */    MCD_OPC_CheckField, 20, 1, 0, 236, 12, 0, // Skip to: 8381
+/* 5073 */    MCD_OPC_CheckField, 7, 1, 1, 229, 12, 0, // Skip to: 8381
+/* 5080 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5084 */    MCD_OPC_Decode, 159, 14, 70, // Opcode: SEL
+/* 5088 */    MCD_OPC_FilterValue, 2, 216, 12, 0, // Skip to: 8381
+/* 5093 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5096 */    MCD_OPC_FilterValue, 0, 208, 12, 0, // Skip to: 8381
+/* 5101 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5104 */    MCD_OPC_FilterValue, 0, 200, 12, 0, // Skip to: 8381
+/* 5109 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5125
+/* 5114 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5125
+/* 5121 */    MCD_OPC_Decode, 205, 14, 68, // Opcode: SMUADX
+/* 5125 */    MCD_OPC_CheckPredicate, 1, 179, 12, 0, // Skip to: 8381
+/* 5130 */    MCD_OPC_Decode, 182, 14, 69, // Opcode: SMLADX
+/* 5134 */    MCD_OPC_FilterValue, 2, 102, 0, 0, // Skip to: 5241
+/* 5139 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 5142 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5174
+/* 5147 */    MCD_OPC_CheckPredicate, 0, 157, 12, 0, // Skip to: 8381
+/* 5152 */    MCD_OPC_CheckField, 20, 1, 1, 150, 12, 0, // Skip to: 8381
+/* 5159 */    MCD_OPC_CheckField, 7, 1, 0, 143, 12, 0, // Skip to: 8381
+/* 5166 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5170 */    MCD_OPC_Decode, 225, 14, 66, // Opcode: SSAX
+/* 5174 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5195
+/* 5179 */    MCD_OPC_CheckPredicate, 1, 125, 12, 0, // Skip to: 8381
+/* 5184 */    MCD_OPC_CheckField, 20, 1, 0, 118, 12, 0, // Skip to: 8381
+/* 5191 */    MCD_OPC_Decode, 240, 13, 67, // Opcode: PKHTB
+/* 5195 */    MCD_OPC_FilterValue, 2, 109, 12, 0, // Skip to: 8381
+/* 5200 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5203 */    MCD_OPC_FilterValue, 0, 101, 12, 0, // Skip to: 8381
+/* 5208 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5211 */    MCD_OPC_FilterValue, 0, 93, 12, 0, // Skip to: 8381
+/* 5216 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5232
+/* 5221 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5232
+/* 5228 */    MCD_OPC_Decode, 213, 14, 68, // Opcode: SMUSD
+/* 5232 */    MCD_OPC_CheckPredicate, 1, 72, 12, 0, // Skip to: 8381
+/* 5237 */    MCD_OPC_Decode, 194, 14, 69, // Opcode: SMLSD
+/* 5241 */    MCD_OPC_FilterValue, 3, 63, 12, 0, // Skip to: 8381
+/* 5246 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 5249 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 5307
+/* 5254 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5257 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 5282
+/* 5262 */    MCD_OPC_CheckPredicate, 0, 42, 12, 0, // Skip to: 8381
+/* 5267 */    MCD_OPC_CheckField, 20, 1, 1, 35, 12, 0, // Skip to: 8381
+/* 5274 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5278 */    MCD_OPC_Decode, 226, 14, 66, // Opcode: SSUB16
+/* 5282 */    MCD_OPC_FilterValue, 1, 22, 12, 0, // Skip to: 8381
+/* 5287 */    MCD_OPC_CheckPredicate, 0, 17, 12, 0, // Skip to: 8381
+/* 5292 */    MCD_OPC_CheckField, 20, 1, 1, 10, 12, 0, // Skip to: 8381
+/* 5299 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5303 */    MCD_OPC_Decode, 227, 14, 66, // Opcode: SSUB8
+/* 5307 */    MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 5361
+/* 5312 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5315 */    MCD_OPC_FilterValue, 0, 245, 11, 0, // Skip to: 8381
+/* 5320 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5323 */    MCD_OPC_FilterValue, 0, 237, 11, 0, // Skip to: 8381
+/* 5328 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5348
+/* 5333 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5348
+/* 5340 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 5344 */    MCD_OPC_Decode, 170, 15, 71, // Opcode: SXTB16
+/* 5348 */    MCD_OPC_CheckPredicate, 1, 212, 11, 0, // Skip to: 8381
+/* 5353 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 5357 */    MCD_OPC_Decode, 167, 15, 72, // Opcode: SXTAB16
+/* 5361 */    MCD_OPC_FilterValue, 2, 199, 11, 0, // Skip to: 8381
+/* 5366 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5369 */    MCD_OPC_FilterValue, 0, 191, 11, 0, // Skip to: 8381
+/* 5374 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5377 */    MCD_OPC_FilterValue, 0, 183, 11, 0, // Skip to: 8381
+/* 5382 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 5398
+/* 5387 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 5398
+/* 5394 */    MCD_OPC_Decode, 214, 14, 68, // Opcode: SMUSDX
+/* 5398 */    MCD_OPC_CheckPredicate, 1, 162, 11, 0, // Skip to: 8381
+/* 5403 */    MCD_OPC_Decode, 195, 14, 69, // Opcode: SMLSDX
+/* 5407 */    MCD_OPC_FilterValue, 1, 106, 2, 0, // Skip to: 6030
+/* 5412 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 5415 */    MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 5495
+/* 5420 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5423 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5459
 /* 5428 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 5431 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5445
-/* 5436 */    MCD_OPC_CheckPredicate, 0, 88, 11, 0, // Skip to: 8345
-/* 5441 */    MCD_OPC_Decode, 156, 5, 55, // Opcode: LDRT_POST_REG
-/* 5445 */    MCD_OPC_FilterValue, 1, 79, 11, 0, // Skip to: 8345
-/* 5450 */    MCD_OPC_CheckPredicate, 0, 74, 11, 0, // Skip to: 8345
-/* 5455 */    MCD_OPC_Decode, 160, 5, 73, // Opcode: LDR_PRE_REG
-/* 5459 */    MCD_OPC_FilterValue, 1, 65, 11, 0, // Skip to: 8345
-/* 5464 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 5467 */    MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 5739
-/* 5472 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
-/* 5475 */    MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5519
-/* 5480 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5483 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5501
-/* 5488 */    MCD_OPC_CheckPredicate, 0, 36, 11, 0, // Skip to: 8345
-/* 5493 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5497 */    MCD_OPC_Decode, 206, 5, 65, // Opcode: QADD16
-/* 5501 */    MCD_OPC_FilterValue, 1, 23, 11, 0, // Skip to: 8345
-/* 5506 */    MCD_OPC_CheckPredicate, 0, 18, 11, 0, // Skip to: 8345
-/* 5511 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5515 */    MCD_OPC_Decode, 129, 6, 65, // Opcode: SHADD16
-/* 5519 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5563
-/* 5524 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5527 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5545
-/* 5532 */    MCD_OPC_CheckPredicate, 0, 248, 10, 0, // Skip to: 8345
-/* 5537 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5541 */    MCD_OPC_Decode, 208, 5, 65, // Opcode: QASX
-/* 5545 */    MCD_OPC_FilterValue, 1, 235, 10, 0, // Skip to: 8345
-/* 5550 */    MCD_OPC_CheckPredicate, 0, 230, 10, 0, // Skip to: 8345
-/* 5555 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5559 */    MCD_OPC_Decode, 131, 6, 65, // Opcode: SHASX
-/* 5563 */    MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 5607
-/* 5568 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5571 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5589
-/* 5576 */    MCD_OPC_CheckPredicate, 0, 204, 10, 0, // Skip to: 8345
-/* 5581 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5585 */    MCD_OPC_Decode, 211, 5, 65, // Opcode: QSAX
-/* 5589 */    MCD_OPC_FilterValue, 1, 191, 10, 0, // Skip to: 8345
-/* 5594 */    MCD_OPC_CheckPredicate, 0, 186, 10, 0, // Skip to: 8345
-/* 5599 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5603 */    MCD_OPC_Decode, 132, 6, 65, // Opcode: SHSAX
-/* 5607 */    MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 5651
-/* 5612 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5615 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5633
-/* 5620 */    MCD_OPC_CheckPredicate, 0, 160, 10, 0, // Skip to: 8345
-/* 5625 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5629 */    MCD_OPC_Decode, 213, 5, 65, // Opcode: QSUB16
-/* 5633 */    MCD_OPC_FilterValue, 1, 147, 10, 0, // Skip to: 8345
-/* 5638 */    MCD_OPC_CheckPredicate, 0, 142, 10, 0, // Skip to: 8345
-/* 5643 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5647 */    MCD_OPC_Decode, 133, 6, 65, // Opcode: SHSUB16
-/* 5651 */    MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 5695
-/* 5656 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5659 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5677
-/* 5664 */    MCD_OPC_CheckPredicate, 0, 116, 10, 0, // Skip to: 8345
-/* 5669 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5673 */    MCD_OPC_Decode, 207, 5, 65, // Opcode: QADD8
-/* 5677 */    MCD_OPC_FilterValue, 1, 103, 10, 0, // Skip to: 8345
-/* 5682 */    MCD_OPC_CheckPredicate, 0, 98, 10, 0, // Skip to: 8345
-/* 5687 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5691 */    MCD_OPC_Decode, 130, 6, 65, // Opcode: SHADD8
-/* 5695 */    MCD_OPC_FilterValue, 7, 85, 10, 0, // Skip to: 8345
-/* 5700 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5703 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5721
-/* 5708 */    MCD_OPC_CheckPredicate, 0, 72, 10, 0, // Skip to: 8345
-/* 5713 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5717 */    MCD_OPC_Decode, 214, 5, 65, // Opcode: QSUB8
-/* 5721 */    MCD_OPC_FilterValue, 1, 59, 10, 0, // Skip to: 8345
-/* 5726 */    MCD_OPC_CheckPredicate, 0, 54, 10, 0, // Skip to: 8345
-/* 5731 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 5735 */    MCD_OPC_Decode, 134, 6, 65, // Opcode: SHSUB8
-/* 5739 */    MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 5938
-/* 5744 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 5747 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5761
-/* 5752 */    MCD_OPC_CheckPredicate, 1, 28, 10, 0, // Skip to: 8345
-/* 5757 */    MCD_OPC_Decode, 180, 6, 74, // Opcode: SSAT
-/* 5761 */    MCD_OPC_FilterValue, 1, 19, 10, 0, // Skip to: 8345
-/* 5766 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 5769 */    MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5826
-/* 5774 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5777 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5798
-/* 5782 */    MCD_OPC_CheckPredicate, 1, 254, 9, 0, // Skip to: 8345
-/* 5787 */    MCD_OPC_CheckField, 8, 4, 15, 247, 9, 0, // Skip to: 8345
-/* 5794 */    MCD_OPC_Decode, 181, 6, 75, // Opcode: SSAT16
-/* 5798 */    MCD_OPC_FilterValue, 1, 238, 9, 0, // Skip to: 8345
-/* 5803 */    MCD_OPC_CheckPredicate, 1, 233, 9, 0, // Skip to: 8345
-/* 5808 */    MCD_OPC_CheckField, 16, 4, 15, 226, 9, 0, // Skip to: 8345
-/* 5815 */    MCD_OPC_CheckField, 8, 4, 15, 219, 9, 0, // Skip to: 8345
-/* 5822 */    MCD_OPC_Decode, 216, 5, 35, // Opcode: REV
-/* 5826 */    MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 5910
-/* 5831 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5834 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5872
-/* 5839 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5859
-/* 5844 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5859
-/* 5851 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 5855 */    MCD_OPC_Decode, 254, 6, 70, // Opcode: SXTB
-/* 5859 */    MCD_OPC_CheckPredicate, 1, 177, 9, 0, // Skip to: 8345
-/* 5864 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 5868 */    MCD_OPC_Decode, 251, 6, 71, // Opcode: SXTAB
-/* 5872 */    MCD_OPC_FilterValue, 1, 164, 9, 0, // Skip to: 8345
-/* 5877 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5897
-/* 5882 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5897
-/* 5889 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 5893 */    MCD_OPC_Decode, 128, 7, 70, // Opcode: SXTH
-/* 5897 */    MCD_OPC_CheckPredicate, 1, 139, 9, 0, // Skip to: 8345
-/* 5902 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 5906 */    MCD_OPC_Decode, 253, 6, 71, // Opcode: SXTAH
-/* 5910 */    MCD_OPC_FilterValue, 2, 126, 9, 0, // Skip to: 8345
-/* 5915 */    MCD_OPC_CheckPredicate, 1, 121, 9, 0, // Skip to: 8345
-/* 5920 */    MCD_OPC_CheckField, 16, 5, 31, 114, 9, 0, // Skip to: 8345
-/* 5927 */    MCD_OPC_CheckField, 8, 4, 15, 107, 9, 0, // Skip to: 8345
-/* 5934 */    MCD_OPC_Decode, 217, 5, 35, // Opcode: REV16
-/* 5938 */    MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 5973
-/* 5943 */    MCD_OPC_CheckPredicate, 19, 93, 9, 0, // Skip to: 8345
-/* 5948 */    MCD_OPC_CheckField, 20, 1, 1, 86, 9, 0, // Skip to: 8345
-/* 5955 */    MCD_OPC_CheckField, 12, 4, 15, 79, 9, 0, // Skip to: 8345
-/* 5962 */    MCD_OPC_CheckField, 5, 3, 0, 72, 9, 0, // Skip to: 8345
-/* 5969 */    MCD_OPC_Decode, 145, 7, 30, // Opcode: UDIV
-/* 5973 */    MCD_OPC_FilterValue, 3, 63, 9, 0, // Skip to: 8345
-/* 5978 */    MCD_OPC_CheckPredicate, 13, 58, 9, 0, // Skip to: 8345
-/* 5983 */    MCD_OPC_CheckField, 5, 2, 2, 51, 9, 0, // Skip to: 8345
-/* 5990 */    MCD_OPC_Decode, 242, 5, 76, // Opcode: SBFX
-/* 5994 */    MCD_OPC_FilterValue, 2, 155, 2, 0, // Skip to: 6666
-/* 5999 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 6002 */    MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 6128
-/* 6007 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6010 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6046
-/* 6015 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 6018 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6032
-/* 6023 */    MCD_OPC_CheckPredicate, 0, 13, 9, 0, // Skip to: 8345
-/* 6028 */    MCD_OPC_Decode, 219, 6, 55, // Opcode: STRB_POST_REG
-/* 6032 */    MCD_OPC_FilterValue, 1, 4, 9, 0, // Skip to: 8345
-/* 6037 */    MCD_OPC_CheckPredicate, 0, 255, 8, 0, // Skip to: 8345
-/* 6042 */    MCD_OPC_Decode, 223, 6, 77, // Opcode: STRBrs
-/* 6046 */    MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 8345
+/* 5436 */    MCD_OPC_CheckPredicate, 0, 124, 11, 0, // Skip to: 8381
+/* 5441 */    MCD_OPC_Decode, 152, 15, 55, // Opcode: STRT_POST_REG
+/* 5445 */    MCD_OPC_FilterValue, 1, 115, 11, 0, // Skip to: 8381
+/* 5450 */    MCD_OPC_CheckPredicate, 0, 110, 11, 0, // Skip to: 8381
+/* 5455 */    MCD_OPC_Decode, 156, 15, 73, // Opcode: STR_PRE_REG
+/* 5459 */    MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 8381
+/* 5464 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 5467 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5481
+/* 5472 */    MCD_OPC_CheckPredicate, 0, 88, 11, 0, // Skip to: 8381
+/* 5477 */    MCD_OPC_Decode, 245, 6, 55, // Opcode: LDRT_POST_REG
+/* 5481 */    MCD_OPC_FilterValue, 1, 79, 11, 0, // Skip to: 8381
+/* 5486 */    MCD_OPC_CheckPredicate, 0, 74, 11, 0, // Skip to: 8381
+/* 5491 */    MCD_OPC_Decode, 249, 6, 74, // Opcode: LDR_PRE_REG
+/* 5495 */    MCD_OPC_FilterValue, 1, 65, 11, 0, // Skip to: 8381
+/* 5500 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 5503 */    MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 5775
+/* 5508 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
+/* 5511 */    MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 5555
+/* 5516 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5519 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5537
+/* 5524 */    MCD_OPC_CheckPredicate, 0, 36, 11, 0, // Skip to: 8381
+/* 5529 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5533 */    MCD_OPC_Decode, 248, 13, 66, // Opcode: QADD16
+/* 5537 */    MCD_OPC_FilterValue, 1, 23, 11, 0, // Skip to: 8381
+/* 5542 */    MCD_OPC_CheckPredicate, 0, 18, 11, 0, // Skip to: 8381
+/* 5547 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5551 */    MCD_OPC_Decode, 172, 14, 66, // Opcode: SHADD16
+/* 5555 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 5599
+/* 5560 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5563 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5581
+/* 5568 */    MCD_OPC_CheckPredicate, 0, 248, 10, 0, // Skip to: 8381
+/* 5573 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5577 */    MCD_OPC_Decode, 250, 13, 66, // Opcode: QASX
+/* 5581 */    MCD_OPC_FilterValue, 1, 235, 10, 0, // Skip to: 8381
+/* 5586 */    MCD_OPC_CheckPredicate, 0, 230, 10, 0, // Skip to: 8381
+/* 5591 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5595 */    MCD_OPC_Decode, 174, 14, 66, // Opcode: SHASX
+/* 5599 */    MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 5643
+/* 5604 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5607 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5625
+/* 5612 */    MCD_OPC_CheckPredicate, 0, 204, 10, 0, // Skip to: 8381
+/* 5617 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5621 */    MCD_OPC_Decode, 253, 13, 66, // Opcode: QSAX
+/* 5625 */    MCD_OPC_FilterValue, 1, 191, 10, 0, // Skip to: 8381
+/* 5630 */    MCD_OPC_CheckPredicate, 0, 186, 10, 0, // Skip to: 8381
+/* 5635 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5639 */    MCD_OPC_Decode, 175, 14, 66, // Opcode: SHSAX
+/* 5643 */    MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 5687
+/* 5648 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5651 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5669
+/* 5656 */    MCD_OPC_CheckPredicate, 0, 160, 10, 0, // Skip to: 8381
+/* 5661 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5665 */    MCD_OPC_Decode, 255, 13, 66, // Opcode: QSUB16
+/* 5669 */    MCD_OPC_FilterValue, 1, 147, 10, 0, // Skip to: 8381
+/* 5674 */    MCD_OPC_CheckPredicate, 0, 142, 10, 0, // Skip to: 8381
+/* 5679 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5683 */    MCD_OPC_Decode, 176, 14, 66, // Opcode: SHSUB16
+/* 5687 */    MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 5731
+/* 5692 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5695 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5713
+/* 5700 */    MCD_OPC_CheckPredicate, 0, 116, 10, 0, // Skip to: 8381
+/* 5705 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5709 */    MCD_OPC_Decode, 249, 13, 66, // Opcode: QADD8
+/* 5713 */    MCD_OPC_FilterValue, 1, 103, 10, 0, // Skip to: 8381
+/* 5718 */    MCD_OPC_CheckPredicate, 0, 98, 10, 0, // Skip to: 8381
+/* 5723 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5727 */    MCD_OPC_Decode, 173, 14, 66, // Opcode: SHADD8
+/* 5731 */    MCD_OPC_FilterValue, 7, 85, 10, 0, // Skip to: 8381
+/* 5736 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5739 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 5757
+/* 5744 */    MCD_OPC_CheckPredicate, 0, 72, 10, 0, // Skip to: 8381
+/* 5749 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5753 */    MCD_OPC_Decode, 128, 14, 66, // Opcode: QSUB8
+/* 5757 */    MCD_OPC_FilterValue, 1, 59, 10, 0, // Skip to: 8381
+/* 5762 */    MCD_OPC_CheckPredicate, 0, 54, 10, 0, // Skip to: 8381
+/* 5767 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 5771 */    MCD_OPC_Decode, 177, 14, 66, // Opcode: SHSUB8
+/* 5775 */    MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 5974
+/* 5780 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 5783 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5797
+/* 5788 */    MCD_OPC_CheckPredicate, 1, 28, 10, 0, // Skip to: 8381
+/* 5793 */    MCD_OPC_Decode, 223, 14, 75, // Opcode: SSAT
+/* 5797 */    MCD_OPC_FilterValue, 1, 19, 10, 0, // Skip to: 8381
+/* 5802 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 5805 */    MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5862
+/* 5810 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5813 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5834
+/* 5818 */    MCD_OPC_CheckPredicate, 1, 254, 9, 0, // Skip to: 8381
+/* 5823 */    MCD_OPC_CheckField, 8, 4, 15, 247, 9, 0, // Skip to: 8381
+/* 5830 */    MCD_OPC_Decode, 224, 14, 76, // Opcode: SSAT16
+/* 5834 */    MCD_OPC_FilterValue, 1, 238, 9, 0, // Skip to: 8381
+/* 5839 */    MCD_OPC_CheckPredicate, 1, 233, 9, 0, // Skip to: 8381
+/* 5844 */    MCD_OPC_CheckField, 16, 4, 15, 226, 9, 0, // Skip to: 8381
+/* 5851 */    MCD_OPC_CheckField, 8, 4, 15, 219, 9, 0, // Skip to: 8381
+/* 5858 */    MCD_OPC_Decode, 130, 14, 35, // Opcode: REV
+/* 5862 */    MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 5946
+/* 5867 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5870 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5908
+/* 5875 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5895
+/* 5880 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5895
+/* 5887 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 5891 */    MCD_OPC_Decode, 169, 15, 71, // Opcode: SXTB
+/* 5895 */    MCD_OPC_CheckPredicate, 1, 177, 9, 0, // Skip to: 8381
+/* 5900 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 5904 */    MCD_OPC_Decode, 166, 15, 72, // Opcode: SXTAB
+/* 5908 */    MCD_OPC_FilterValue, 1, 164, 9, 0, // Skip to: 8381
+/* 5913 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 5933
+/* 5918 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 5933
+/* 5925 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 5929 */    MCD_OPC_Decode, 171, 15, 71, // Opcode: SXTH
+/* 5933 */    MCD_OPC_CheckPredicate, 1, 139, 9, 0, // Skip to: 8381
+/* 5938 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 5942 */    MCD_OPC_Decode, 168, 15, 72, // Opcode: SXTAH
+/* 5946 */    MCD_OPC_FilterValue, 2, 126, 9, 0, // Skip to: 8381
+/* 5951 */    MCD_OPC_CheckPredicate, 1, 121, 9, 0, // Skip to: 8381
+/* 5956 */    MCD_OPC_CheckField, 16, 5, 31, 114, 9, 0, // Skip to: 8381
+/* 5963 */    MCD_OPC_CheckField, 8, 4, 15, 107, 9, 0, // Skip to: 8381
+/* 5970 */    MCD_OPC_Decode, 131, 14, 35, // Opcode: REV16
+/* 5974 */    MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6009
+/* 5979 */    MCD_OPC_CheckPredicate, 20, 93, 9, 0, // Skip to: 8381
+/* 5984 */    MCD_OPC_CheckField, 20, 1, 1, 86, 9, 0, // Skip to: 8381
+/* 5991 */    MCD_OPC_CheckField, 12, 4, 15, 79, 9, 0, // Skip to: 8381
+/* 5998 */    MCD_OPC_CheckField, 5, 3, 0, 72, 9, 0, // Skip to: 8381
+/* 6005 */    MCD_OPC_Decode, 188, 15, 30, // Opcode: UDIV
+/* 6009 */    MCD_OPC_FilterValue, 3, 63, 9, 0, // Skip to: 8381
+/* 6014 */    MCD_OPC_CheckPredicate, 13, 58, 9, 0, // Skip to: 8381
+/* 6019 */    MCD_OPC_CheckField, 5, 2, 2, 51, 9, 0, // Skip to: 8381
+/* 6026 */    MCD_OPC_Decode, 157, 14, 77, // Opcode: SBFX
+/* 6030 */    MCD_OPC_FilterValue, 2, 155, 2, 0, // Skip to: 6702
+/* 6035 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 6038 */    MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 6164
+/* 6043 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6046 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6082
 /* 6051 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 6054 */    MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 6091
-/* 6059 */    MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 6082
-/* 6064 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6082
-/* 6071 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6082
-/* 6078 */    MCD_OPC_Decode, 204, 5, 64, // Opcode: PLIrs
-/* 6082 */    MCD_OPC_CheckPredicate, 0, 210, 8, 0, // Skip to: 8345
-/* 6087 */    MCD_OPC_Decode, 128, 5, 55, // Opcode: LDRB_POST_REG
-/* 6091 */    MCD_OPC_FilterValue, 1, 201, 8, 0, // Skip to: 8345
-/* 6096 */    MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 6119
-/* 6101 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6119
-/* 6108 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6119
-/* 6115 */    MCD_OPC_Decode, 202, 5, 64, // Opcode: PLDrs
-/* 6119 */    MCD_OPC_CheckPredicate, 0, 173, 8, 0, // Skip to: 8345
-/* 6124 */    MCD_OPC_Decode, 132, 5, 77, // Opcode: LDRBrs
-/* 6128 */    MCD_OPC_FilterValue, 1, 164, 8, 0, // Skip to: 8345
-/* 6133 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
-/* 6136 */    MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6299
-/* 6141 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 6144 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6202
-/* 6149 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6152 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6177
-/* 6157 */    MCD_OPC_CheckPredicate, 0, 135, 8, 0, // Skip to: 8345
-/* 6162 */    MCD_OPC_CheckField, 20, 1, 1, 128, 8, 0, // Skip to: 8345
-/* 6169 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6173 */    MCD_OPC_Decode, 140, 7, 65, // Opcode: UADD16
-/* 6177 */    MCD_OPC_FilterValue, 1, 115, 8, 0, // Skip to: 8345
-/* 6182 */    MCD_OPC_CheckPredicate, 0, 110, 8, 0, // Skip to: 8345
-/* 6187 */    MCD_OPC_CheckField, 20, 1, 1, 103, 8, 0, // Skip to: 8345
-/* 6194 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6198 */    MCD_OPC_Decode, 141, 7, 65, // Opcode: UADD8
-/* 6202 */    MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 6269
-/* 6207 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6210 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6231
-/* 6215 */    MCD_OPC_CheckPredicate, 1, 77, 8, 0, // Skip to: 8345
-/* 6220 */    MCD_OPC_CheckField, 7, 1, 0, 70, 8, 0, // Skip to: 8345
-/* 6227 */    MCD_OPC_Decode, 143, 6, 19, // Opcode: SMLALD
-/* 6231 */    MCD_OPC_FilterValue, 1, 61, 8, 0, // Skip to: 8345
-/* 6236 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6239 */    MCD_OPC_FilterValue, 0, 53, 8, 0, // Skip to: 8345
-/* 6244 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6260
-/* 6249 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6260
-/* 6256 */    MCD_OPC_Decode, 159, 6, 30, // Opcode: SMMUL
-/* 6260 */    MCD_OPC_CheckPredicate, 1, 32, 8, 0, // Skip to: 8345
-/* 6265 */    MCD_OPC_Decode, 155, 6, 39, // Opcode: SMMLA
-/* 6269 */    MCD_OPC_FilterValue, 3, 23, 8, 0, // Skip to: 8345
-/* 6274 */    MCD_OPC_CheckPredicate, 13, 11, 0, 0, // Skip to: 6290
-/* 6279 */    MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 6290
-/* 6286 */    MCD_OPC_Decode, 162, 4, 78, // Opcode: BFC
-/* 6290 */    MCD_OPC_CheckPredicate, 13, 2, 8, 0, // Skip to: 8345
-/* 6295 */    MCD_OPC_Decode, 163, 4, 79, // Opcode: BFI
-/* 6299 */    MCD_OPC_FilterValue, 1, 102, 0, 0, // Skip to: 6406
-/* 6304 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6307 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6335
-/* 6312 */    MCD_OPC_CheckPredicate, 1, 236, 7, 0, // Skip to: 8345
-/* 6317 */    MCD_OPC_CheckField, 23, 2, 2, 229, 7, 0, // Skip to: 8345
-/* 6324 */    MCD_OPC_CheckField, 7, 1, 0, 222, 7, 0, // Skip to: 8345
-/* 6331 */    MCD_OPC_Decode, 144, 6, 19, // Opcode: SMLALDX
-/* 6335 */    MCD_OPC_FilterValue, 1, 213, 7, 0, // Skip to: 8345
-/* 6340 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 6343 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6368
-/* 6348 */    MCD_OPC_CheckPredicate, 0, 200, 7, 0, // Skip to: 8345
-/* 6353 */    MCD_OPC_CheckField, 7, 1, 0, 193, 7, 0, // Skip to: 8345
-/* 6360 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6364 */    MCD_OPC_Decode, 142, 7, 65, // Opcode: UASX
-/* 6368 */    MCD_OPC_FilterValue, 2, 180, 7, 0, // Skip to: 8345
-/* 6373 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6376 */    MCD_OPC_FilterValue, 0, 172, 7, 0, // Skip to: 8345
-/* 6381 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6397
-/* 6386 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6397
-/* 6393 */    MCD_OPC_Decode, 160, 6, 30, // Opcode: SMMULR
-/* 6397 */    MCD_OPC_CheckPredicate, 1, 151, 7, 0, // Skip to: 8345
-/* 6402 */    MCD_OPC_Decode, 156, 6, 39, // Opcode: SMMLAR
-/* 6406 */    MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6496
-/* 6411 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6414 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6468
-/* 6419 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6422 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6443
-/* 6427 */    MCD_OPC_CheckPredicate, 1, 121, 7, 0, // Skip to: 8345
-/* 6432 */    MCD_OPC_CheckField, 23, 2, 2, 114, 7, 0, // Skip to: 8345
-/* 6439 */    MCD_OPC_Decode, 153, 6, 19, // Opcode: SMLSLD
-/* 6443 */    MCD_OPC_FilterValue, 1, 105, 7, 0, // Skip to: 8345
-/* 6448 */    MCD_OPC_CheckPredicate, 0, 100, 7, 0, // Skip to: 8345
-/* 6453 */    MCD_OPC_CheckField, 23, 2, 0, 93, 7, 0, // Skip to: 8345
-/* 6460 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6464 */    MCD_OPC_Decode, 165, 7, 65, // Opcode: USAX
-/* 6468 */    MCD_OPC_FilterValue, 1, 80, 7, 0, // Skip to: 8345
-/* 6473 */    MCD_OPC_CheckPredicate, 1, 75, 7, 0, // Skip to: 8345
-/* 6478 */    MCD_OPC_CheckField, 23, 2, 2, 68, 7, 0, // Skip to: 8345
-/* 6485 */    MCD_OPC_CheckField, 20, 1, 1, 61, 7, 0, // Skip to: 8345
-/* 6492 */    MCD_OPC_Decode, 157, 6, 39, // Opcode: SMMLS
-/* 6496 */    MCD_OPC_FilterValue, 3, 52, 7, 0, // Skip to: 8345
-/* 6501 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 6504 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6562
-/* 6509 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6512 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6537
-/* 6517 */    MCD_OPC_CheckPredicate, 0, 31, 7, 0, // Skip to: 8345
-/* 6522 */    MCD_OPC_CheckField, 20, 1, 1, 24, 7, 0, // Skip to: 8345
-/* 6529 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6533 */    MCD_OPC_Decode, 166, 7, 65, // Opcode: USUB16
-/* 6537 */    MCD_OPC_FilterValue, 1, 11, 7, 0, // Skip to: 8345
-/* 6542 */    MCD_OPC_CheckPredicate, 0, 6, 7, 0, // Skip to: 8345
-/* 6547 */    MCD_OPC_CheckField, 20, 1, 1, 255, 6, 0, // Skip to: 8345
-/* 6554 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6558 */    MCD_OPC_Decode, 167, 7, 65, // Opcode: USUB8
-/* 6562 */    MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 6616
-/* 6567 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6570 */    MCD_OPC_FilterValue, 0, 234, 6, 0, // Skip to: 8345
-/* 6575 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6578 */    MCD_OPC_FilterValue, 0, 226, 6, 0, // Skip to: 8345
-/* 6583 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 6603
-/* 6588 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 6603
-/* 6595 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 6599 */    MCD_OPC_Decode, 172, 7, 70, // Opcode: UXTB16
-/* 6603 */    MCD_OPC_CheckPredicate, 1, 201, 6, 0, // Skip to: 8345
-/* 6608 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 6612 */    MCD_OPC_Decode, 169, 7, 71, // Opcode: UXTAB16
-/* 6616 */    MCD_OPC_FilterValue, 2, 188, 6, 0, // Skip to: 8345
-/* 6621 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6624 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6645
-/* 6629 */    MCD_OPC_CheckPredicate, 1, 175, 6, 0, // Skip to: 8345
-/* 6634 */    MCD_OPC_CheckField, 20, 1, 0, 168, 6, 0, // Skip to: 8345
-/* 6641 */    MCD_OPC_Decode, 154, 6, 19, // Opcode: SMLSLDX
-/* 6645 */    MCD_OPC_FilterValue, 1, 159, 6, 0, // Skip to: 8345
-/* 6650 */    MCD_OPC_CheckPredicate, 1, 154, 6, 0, // Skip to: 8345
-/* 6655 */    MCD_OPC_CheckField, 20, 1, 1, 147, 6, 0, // Skip to: 8345
-/* 6662 */    MCD_OPC_Decode, 158, 6, 39, // Opcode: SMMLSR
-/* 6666 */    MCD_OPC_FilterValue, 3, 138, 6, 0, // Skip to: 8345
-/* 6671 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 6674 */    MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 6754
-/* 6679 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6682 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6718
-/* 6687 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 6690 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6704
-/* 6695 */    MCD_OPC_CheckPredicate, 0, 109, 6, 0, // Skip to: 8345
-/* 6700 */    MCD_OPC_Decode, 217, 6, 55, // Opcode: STRBT_POST_REG
-/* 6704 */    MCD_OPC_FilterValue, 1, 100, 6, 0, // Skip to: 8345
-/* 6709 */    MCD_OPC_CheckPredicate, 0, 95, 6, 0, // Skip to: 8345
-/* 6714 */    MCD_OPC_Decode, 221, 6, 72, // Opcode: STRB_PRE_REG
-/* 6718 */    MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 8345
+/* 6054 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6068
+/* 6059 */    MCD_OPC_CheckPredicate, 0, 13, 9, 0, // Skip to: 8381
+/* 6064 */    MCD_OPC_Decode, 134, 15, 55, // Opcode: STRB_POST_REG
+/* 6068 */    MCD_OPC_FilterValue, 1, 4, 9, 0, // Skip to: 8381
+/* 6073 */    MCD_OPC_CheckPredicate, 0, 255, 8, 0, // Skip to: 8381
+/* 6078 */    MCD_OPC_Decode, 138, 15, 78, // Opcode: STRBrs
+/* 6082 */    MCD_OPC_FilterValue, 1, 246, 8, 0, // Skip to: 8381
+/* 6087 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 6090 */    MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 6127
+/* 6095 */    MCD_OPC_CheckPredicate, 15, 18, 0, 0, // Skip to: 6118
+/* 6100 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6118
+/* 6107 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6118
+/* 6114 */    MCD_OPC_Decode, 246, 13, 65, // Opcode: PLIrs
+/* 6118 */    MCD_OPC_CheckPredicate, 0, 210, 8, 0, // Skip to: 8381
+/* 6123 */    MCD_OPC_Decode, 217, 6, 55, // Opcode: LDRB_POST_REG
+/* 6127 */    MCD_OPC_FilterValue, 1, 201, 8, 0, // Skip to: 8381
+/* 6132 */    MCD_OPC_CheckPredicate, 0, 18, 0, 0, // Skip to: 6155
+/* 6137 */    MCD_OPC_CheckField, 28, 4, 15, 11, 0, 0, // Skip to: 6155
+/* 6144 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6155
+/* 6151 */    MCD_OPC_Decode, 244, 13, 65, // Opcode: PLDrs
+/* 6155 */    MCD_OPC_CheckPredicate, 0, 173, 8, 0, // Skip to: 8381
+/* 6160 */    MCD_OPC_Decode, 221, 6, 78, // Opcode: LDRBrs
+/* 6164 */    MCD_OPC_FilterValue, 1, 164, 8, 0, // Skip to: 8381
+/* 6169 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
+/* 6172 */    MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6335
+/* 6177 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 6180 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6238
+/* 6185 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6188 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6213
+/* 6193 */    MCD_OPC_CheckPredicate, 0, 135, 8, 0, // Skip to: 8381
+/* 6198 */    MCD_OPC_CheckField, 20, 1, 1, 128, 8, 0, // Skip to: 8381
+/* 6205 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6209 */    MCD_OPC_Decode, 183, 15, 66, // Opcode: UADD16
+/* 6213 */    MCD_OPC_FilterValue, 1, 115, 8, 0, // Skip to: 8381
+/* 6218 */    MCD_OPC_CheckPredicate, 0, 110, 8, 0, // Skip to: 8381
+/* 6223 */    MCD_OPC_CheckField, 20, 1, 1, 103, 8, 0, // Skip to: 8381
+/* 6230 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6234 */    MCD_OPC_Decode, 184, 15, 66, // Opcode: UADD8
+/* 6238 */    MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 6305
+/* 6243 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6246 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6267
+/* 6251 */    MCD_OPC_CheckPredicate, 1, 77, 8, 0, // Skip to: 8381
+/* 6256 */    MCD_OPC_CheckField, 7, 1, 0, 70, 8, 0, // Skip to: 8381
+/* 6263 */    MCD_OPC_Decode, 186, 14, 19, // Opcode: SMLALD
+/* 6267 */    MCD_OPC_FilterValue, 1, 61, 8, 0, // Skip to: 8381
+/* 6272 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6275 */    MCD_OPC_FilterValue, 0, 53, 8, 0, // Skip to: 8381
+/* 6280 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6296
+/* 6285 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6296
+/* 6292 */    MCD_OPC_Decode, 202, 14, 30, // Opcode: SMMUL
+/* 6296 */    MCD_OPC_CheckPredicate, 1, 32, 8, 0, // Skip to: 8381
+/* 6301 */    MCD_OPC_Decode, 198, 14, 39, // Opcode: SMMLA
+/* 6305 */    MCD_OPC_FilterValue, 3, 23, 8, 0, // Skip to: 8381
+/* 6310 */    MCD_OPC_CheckPredicate, 13, 11, 0, 0, // Skip to: 6326
+/* 6315 */    MCD_OPC_CheckField, 0, 4, 15, 4, 0, 0, // Skip to: 6326
+/* 6322 */    MCD_OPC_Decode, 221, 5, 79, // Opcode: BFC
+/* 6326 */    MCD_OPC_CheckPredicate, 13, 2, 8, 0, // Skip to: 8381
+/* 6331 */    MCD_OPC_Decode, 222, 5, 80, // Opcode: BFI
+/* 6335 */    MCD_OPC_FilterValue, 1, 102, 0, 0, // Skip to: 6442
+/* 6340 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6343 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6371
+/* 6348 */    MCD_OPC_CheckPredicate, 1, 236, 7, 0, // Skip to: 8381
+/* 6353 */    MCD_OPC_CheckField, 23, 2, 2, 229, 7, 0, // Skip to: 8381
+/* 6360 */    MCD_OPC_CheckField, 7, 1, 0, 222, 7, 0, // Skip to: 8381
+/* 6367 */    MCD_OPC_Decode, 187, 14, 19, // Opcode: SMLALDX
+/* 6371 */    MCD_OPC_FilterValue, 1, 213, 7, 0, // Skip to: 8381
+/* 6376 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 6379 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6404
+/* 6384 */    MCD_OPC_CheckPredicate, 0, 200, 7, 0, // Skip to: 8381
+/* 6389 */    MCD_OPC_CheckField, 7, 1, 0, 193, 7, 0, // Skip to: 8381
+/* 6396 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6400 */    MCD_OPC_Decode, 185, 15, 66, // Opcode: UASX
+/* 6404 */    MCD_OPC_FilterValue, 2, 180, 7, 0, // Skip to: 8381
+/* 6409 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6412 */    MCD_OPC_FilterValue, 0, 172, 7, 0, // Skip to: 8381
+/* 6417 */    MCD_OPC_CheckPredicate, 1, 11, 0, 0, // Skip to: 6433
+/* 6422 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 6433
+/* 6429 */    MCD_OPC_Decode, 203, 14, 30, // Opcode: SMMULR
+/* 6433 */    MCD_OPC_CheckPredicate, 1, 151, 7, 0, // Skip to: 8381
+/* 6438 */    MCD_OPC_Decode, 199, 14, 39, // Opcode: SMMLAR
+/* 6442 */    MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6532
+/* 6447 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6450 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6504
+/* 6455 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6458 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6479
+/* 6463 */    MCD_OPC_CheckPredicate, 1, 121, 7, 0, // Skip to: 8381
+/* 6468 */    MCD_OPC_CheckField, 23, 2, 2, 114, 7, 0, // Skip to: 8381
+/* 6475 */    MCD_OPC_Decode, 196, 14, 19, // Opcode: SMLSLD
+/* 6479 */    MCD_OPC_FilterValue, 1, 105, 7, 0, // Skip to: 8381
+/* 6484 */    MCD_OPC_CheckPredicate, 0, 100, 7, 0, // Skip to: 8381
+/* 6489 */    MCD_OPC_CheckField, 23, 2, 0, 93, 7, 0, // Skip to: 8381
+/* 6496 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6500 */    MCD_OPC_Decode, 208, 15, 66, // Opcode: USAX
+/* 6504 */    MCD_OPC_FilterValue, 1, 80, 7, 0, // Skip to: 8381
+/* 6509 */    MCD_OPC_CheckPredicate, 1, 75, 7, 0, // Skip to: 8381
+/* 6514 */    MCD_OPC_CheckField, 23, 2, 2, 68, 7, 0, // Skip to: 8381
+/* 6521 */    MCD_OPC_CheckField, 20, 1, 1, 61, 7, 0, // Skip to: 8381
+/* 6528 */    MCD_OPC_Decode, 200, 14, 39, // Opcode: SMMLS
+/* 6532 */    MCD_OPC_FilterValue, 3, 52, 7, 0, // Skip to: 8381
+/* 6537 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 6540 */    MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 6598
+/* 6545 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6548 */    MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 6573
+/* 6553 */    MCD_OPC_CheckPredicate, 0, 31, 7, 0, // Skip to: 8381
+/* 6558 */    MCD_OPC_CheckField, 20, 1, 1, 24, 7, 0, // Skip to: 8381
+/* 6565 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6569 */    MCD_OPC_Decode, 209, 15, 66, // Opcode: USUB16
+/* 6573 */    MCD_OPC_FilterValue, 1, 11, 7, 0, // Skip to: 8381
+/* 6578 */    MCD_OPC_CheckPredicate, 0, 6, 7, 0, // Skip to: 8381
+/* 6583 */    MCD_OPC_CheckField, 20, 1, 1, 255, 6, 0, // Skip to: 8381
+/* 6590 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6594 */    MCD_OPC_Decode, 210, 15, 66, // Opcode: USUB8
+/* 6598 */    MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 6652
+/* 6603 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6606 */    MCD_OPC_FilterValue, 0, 234, 6, 0, // Skip to: 8381
+/* 6611 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6614 */    MCD_OPC_FilterValue, 0, 226, 6, 0, // Skip to: 8381
+/* 6619 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 6639
+/* 6624 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 6639
+/* 6631 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 6635 */    MCD_OPC_Decode, 215, 15, 71, // Opcode: UXTB16
+/* 6639 */    MCD_OPC_CheckPredicate, 1, 201, 6, 0, // Skip to: 8381
+/* 6644 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 6648 */    MCD_OPC_Decode, 212, 15, 72, // Opcode: UXTAB16
+/* 6652 */    MCD_OPC_FilterValue, 2, 188, 6, 0, // Skip to: 8381
+/* 6657 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6660 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 6681
+/* 6665 */    MCD_OPC_CheckPredicate, 1, 175, 6, 0, // Skip to: 8381
+/* 6670 */    MCD_OPC_CheckField, 20, 1, 0, 168, 6, 0, // Skip to: 8381
+/* 6677 */    MCD_OPC_Decode, 197, 14, 19, // Opcode: SMLSLDX
+/* 6681 */    MCD_OPC_FilterValue, 1, 159, 6, 0, // Skip to: 8381
+/* 6686 */    MCD_OPC_CheckPredicate, 1, 154, 6, 0, // Skip to: 8381
+/* 6691 */    MCD_OPC_CheckField, 20, 1, 1, 147, 6, 0, // Skip to: 8381
+/* 6698 */    MCD_OPC_Decode, 201, 14, 39, // Opcode: SMMLSR
+/* 6702 */    MCD_OPC_FilterValue, 3, 138, 6, 0, // Skip to: 8381
+/* 6707 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 6710 */    MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 6790
+/* 6715 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6718 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 6754
 /* 6723 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 6726 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6740
-/* 6731 */    MCD_OPC_CheckPredicate, 0, 73, 6, 0, // Skip to: 8345
-/* 6736 */    MCD_OPC_Decode, 254, 4, 55, // Opcode: LDRBT_POST_REG
-/* 6740 */    MCD_OPC_FilterValue, 1, 64, 6, 0, // Skip to: 8345
-/* 6745 */    MCD_OPC_CheckPredicate, 0, 59, 6, 0, // Skip to: 8345
-/* 6750 */    MCD_OPC_Decode, 130, 5, 73, // Opcode: LDRB_PRE_REG
-/* 6754 */    MCD_OPC_FilterValue, 1, 50, 6, 0, // Skip to: 8345
-/* 6759 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 6762 */    MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 7034
-/* 6767 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
-/* 6770 */    MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 6814
-/* 6775 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6778 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6796
-/* 6783 */    MCD_OPC_CheckPredicate, 0, 21, 6, 0, // Skip to: 8345
-/* 6788 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6792 */    MCD_OPC_Decode, 155, 7, 65, // Opcode: UQADD16
-/* 6796 */    MCD_OPC_FilterValue, 1, 8, 6, 0, // Skip to: 8345
-/* 6801 */    MCD_OPC_CheckPredicate, 0, 3, 6, 0, // Skip to: 8345
-/* 6806 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6810 */    MCD_OPC_Decode, 146, 7, 65, // Opcode: UHADD16
-/* 6814 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 6858
-/* 6819 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6822 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6840
-/* 6827 */    MCD_OPC_CheckPredicate, 0, 233, 5, 0, // Skip to: 8345
-/* 6832 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6836 */    MCD_OPC_Decode, 157, 7, 65, // Opcode: UQASX
-/* 6840 */    MCD_OPC_FilterValue, 1, 220, 5, 0, // Skip to: 8345
-/* 6845 */    MCD_OPC_CheckPredicate, 0, 215, 5, 0, // Skip to: 8345
-/* 6850 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6854 */    MCD_OPC_Decode, 148, 7, 65, // Opcode: UHASX
-/* 6858 */    MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 6902
-/* 6863 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6866 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6884
-/* 6871 */    MCD_OPC_CheckPredicate, 0, 189, 5, 0, // Skip to: 8345
-/* 6876 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6880 */    MCD_OPC_Decode, 158, 7, 65, // Opcode: UQSAX
-/* 6884 */    MCD_OPC_FilterValue, 1, 176, 5, 0, // Skip to: 8345
-/* 6889 */    MCD_OPC_CheckPredicate, 0, 171, 5, 0, // Skip to: 8345
-/* 6894 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6898 */    MCD_OPC_Decode, 149, 7, 65, // Opcode: UHSAX
-/* 6902 */    MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 6946
-/* 6907 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6910 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6928
-/* 6915 */    MCD_OPC_CheckPredicate, 0, 145, 5, 0, // Skip to: 8345
-/* 6920 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6924 */    MCD_OPC_Decode, 159, 7, 65, // Opcode: UQSUB16
-/* 6928 */    MCD_OPC_FilterValue, 1, 132, 5, 0, // Skip to: 8345
-/* 6933 */    MCD_OPC_CheckPredicate, 0, 127, 5, 0, // Skip to: 8345
-/* 6938 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6942 */    MCD_OPC_Decode, 150, 7, 65, // Opcode: UHSUB16
-/* 6946 */    MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 6990
-/* 6951 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6954 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6972
-/* 6959 */    MCD_OPC_CheckPredicate, 0, 101, 5, 0, // Skip to: 8345
-/* 6964 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6968 */    MCD_OPC_Decode, 156, 7, 65, // Opcode: UQADD8
-/* 6972 */    MCD_OPC_FilterValue, 1, 88, 5, 0, // Skip to: 8345
-/* 6977 */    MCD_OPC_CheckPredicate, 0, 83, 5, 0, // Skip to: 8345
-/* 6982 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 6986 */    MCD_OPC_Decode, 147, 7, 65, // Opcode: UHADD8
-/* 6990 */    MCD_OPC_FilterValue, 7, 70, 5, 0, // Skip to: 8345
-/* 6995 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6998 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 7016
-/* 7003 */    MCD_OPC_CheckPredicate, 0, 57, 5, 0, // Skip to: 8345
-/* 7008 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 7012 */    MCD_OPC_Decode, 160, 7, 65, // Opcode: UQSUB8
-/* 7016 */    MCD_OPC_FilterValue, 1, 44, 5, 0, // Skip to: 8345
-/* 7021 */    MCD_OPC_CheckPredicate, 0, 39, 5, 0, // Skip to: 8345
-/* 7026 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
-/* 7030 */    MCD_OPC_Decode, 151, 7, 65, // Opcode: UHSUB8
-/* 7034 */    MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 7233
-/* 7039 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 7042 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7056
-/* 7047 */    MCD_OPC_CheckPredicate, 1, 13, 5, 0, // Skip to: 8345
-/* 7052 */    MCD_OPC_Decode, 163, 7, 74, // Opcode: USAT
-/* 7056 */    MCD_OPC_FilterValue, 1, 4, 5, 0, // Skip to: 8345
-/* 7061 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7064 */    MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 7121
-/* 7069 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7072 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7093
-/* 7077 */    MCD_OPC_CheckPredicate, 1, 239, 4, 0, // Skip to: 8345
-/* 7082 */    MCD_OPC_CheckField, 8, 4, 15, 232, 4, 0, // Skip to: 8345
-/* 7089 */    MCD_OPC_Decode, 164, 7, 75, // Opcode: USAT16
-/* 7093 */    MCD_OPC_FilterValue, 1, 223, 4, 0, // Skip to: 8345
-/* 7098 */    MCD_OPC_CheckPredicate, 13, 218, 4, 0, // Skip to: 8345
-/* 7103 */    MCD_OPC_CheckField, 16, 4, 15, 211, 4, 0, // Skip to: 8345
-/* 7110 */    MCD_OPC_CheckField, 8, 4, 15, 204, 4, 0, // Skip to: 8345
-/* 7117 */    MCD_OPC_Decode, 215, 5, 35, // Opcode: RBIT
-/* 7121 */    MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 7205
-/* 7126 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7129 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7167
-/* 7134 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7154
-/* 7139 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7154
-/* 7146 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 7150 */    MCD_OPC_Decode, 171, 7, 70, // Opcode: UXTB
-/* 7154 */    MCD_OPC_CheckPredicate, 1, 162, 4, 0, // Skip to: 8345
-/* 7159 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 7163 */    MCD_OPC_Decode, 168, 7, 71, // Opcode: UXTAB
-/* 7167 */    MCD_OPC_FilterValue, 1, 149, 4, 0, // Skip to: 8345
-/* 7172 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7192
-/* 7177 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7192
-/* 7184 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 7188 */    MCD_OPC_Decode, 173, 7, 70, // Opcode: UXTH
-/* 7192 */    MCD_OPC_CheckPredicate, 1, 124, 4, 0, // Skip to: 8345
-/* 7197 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
-/* 7201 */    MCD_OPC_Decode, 170, 7, 71, // Opcode: UXTAH
-/* 7205 */    MCD_OPC_FilterValue, 2, 111, 4, 0, // Skip to: 8345
-/* 7210 */    MCD_OPC_CheckPredicate, 1, 106, 4, 0, // Skip to: 8345
-/* 7215 */    MCD_OPC_CheckField, 16, 5, 31, 99, 4, 0, // Skip to: 8345
-/* 7222 */    MCD_OPC_CheckField, 8, 4, 15, 92, 4, 0, // Skip to: 8345
-/* 7229 */    MCD_OPC_Decode, 218, 5, 35, // Opcode: REVSH
-/* 7233 */    MCD_OPC_FilterValue, 3, 83, 4, 0, // Skip to: 8345
-/* 7238 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
-/* 7241 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7255
-/* 7246 */    MCD_OPC_CheckPredicate, 13, 70, 4, 0, // Skip to: 8345
-/* 7251 */    MCD_OPC_Decode, 143, 7, 76, // Opcode: UBFX
-/* 7255 */    MCD_OPC_FilterValue, 3, 61, 4, 0, // Skip to: 8345
-/* 7260 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 7263 */    MCD_OPC_FilterValue, 1, 53, 4, 0, // Skip to: 8345
-/* 7268 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7271 */    MCD_OPC_FilterValue, 1, 45, 4, 0, // Skip to: 8345
-/* 7276 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
-/* 7279 */    MCD_OPC_FilterValue, 14, 37, 4, 0, // Skip to: 8345
-/* 7284 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
-/* 7287 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7309
-/* 7292 */    MCD_OPC_CheckPredicate, 20, 34, 0, 0, // Skip to: 7331
-/* 7297 */    MCD_OPC_CheckField, 8, 12, 222, 29, 26, 0, 0, // Skip to: 7331
-/* 7305 */    MCD_OPC_Decode, 134, 7, 51, // Opcode: TRAPNaCl
-/* 7309 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7331
-/* 7314 */    MCD_OPC_CheckPredicate, 0, 12, 0, 0, // Skip to: 7331
-/* 7319 */    MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, 0, // Skip to: 7331
-/* 7327 */    MCD_OPC_Decode, 133, 7, 51, // Opcode: TRAP
-/* 7331 */    MCD_OPC_CheckPredicate, 0, 241, 3, 0, // Skip to: 8345
-/* 7336 */    MCD_OPC_Decode, 144, 7, 15, // Opcode: UDF
-/* 7340 */    MCD_OPC_FilterValue, 4, 75, 3, 0, // Skip to: 8188
-/* 7345 */    MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
-/* 7348 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7362
-/* 7353 */    MCD_OPC_CheckPredicate, 0, 219, 3, 0, // Skip to: 8345
-/* 7358 */    MCD_OPC_Decode, 208, 6, 80, // Opcode: STMDA
-/* 7362 */    MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 7400
-/* 7367 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7391
-/* 7372 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7391
-/* 7379 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7391
-/* 7387 */    MCD_OPC_Decode, 219, 5, 81, // Opcode: RFEDA
-/* 7391 */    MCD_OPC_CheckPredicate, 0, 181, 3, 0, // Skip to: 8345
-/* 7396 */    MCD_OPC_Decode, 245, 4, 80, // Opcode: LDMDA
-/* 7400 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7414
-/* 7405 */    MCD_OPC_CheckPredicate, 0, 167, 3, 0, // Skip to: 8345
-/* 7410 */    MCD_OPC_Decode, 209, 6, 82, // Opcode: STMDA_UPD
-/* 7414 */    MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 7452
-/* 7419 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7443
-/* 7424 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7443
-/* 7431 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7443
-/* 7439 */    MCD_OPC_Decode, 220, 5, 81, // Opcode: RFEDA_UPD
-/* 7443 */    MCD_OPC_CheckPredicate, 0, 129, 3, 0, // Skip to: 8345
-/* 7448 */    MCD_OPC_Decode, 246, 4, 82, // Opcode: LDMDA_UPD
-/* 7452 */    MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 7491
-/* 7457 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7482
-/* 7462 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7482
-/* 7469 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7482
-/* 7478 */    MCD_OPC_Decode, 172, 6, 83, // Opcode: SRSDA
-/* 7482 */    MCD_OPC_CheckPredicate, 0, 90, 3, 0, // Skip to: 8345
-/* 7487 */    MCD_OPC_Decode, 190, 21, 80, // Opcode: sysSTMDA
-/* 7491 */    MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 7505
-/* 7496 */    MCD_OPC_CheckPredicate, 0, 76, 3, 0, // Skip to: 8345
-/* 7501 */    MCD_OPC_Decode, 182, 21, 80, // Opcode: sysLDMDA
-/* 7505 */    MCD_OPC_FilterValue, 6, 34, 0, 0, // Skip to: 7544
-/* 7510 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7535
-/* 7515 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7535
-/* 7522 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7535
-/* 7531 */    MCD_OPC_Decode, 173, 6, 83, // Opcode: SRSDA_UPD
-/* 7535 */    MCD_OPC_CheckPredicate, 0, 37, 3, 0, // Skip to: 8345
-/* 7540 */    MCD_OPC_Decode, 191, 21, 82, // Opcode: sysSTMDA_UPD
-/* 7544 */    MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 7558
-/* 7549 */    MCD_OPC_CheckPredicate, 0, 23, 3, 0, // Skip to: 8345
-/* 7554 */    MCD_OPC_Decode, 183, 21, 82, // Opcode: sysLDMDA_UPD
-/* 7558 */    MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7572
-/* 7563 */    MCD_OPC_CheckPredicate, 0, 9, 3, 0, // Skip to: 8345
-/* 7568 */    MCD_OPC_Decode, 212, 6, 80, // Opcode: STMIA
-/* 7572 */    MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 7610
-/* 7577 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7601
-/* 7582 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7601
-/* 7589 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7601
-/* 7597 */    MCD_OPC_Decode, 223, 5, 81, // Opcode: RFEIA
-/* 7601 */    MCD_OPC_CheckPredicate, 0, 227, 2, 0, // Skip to: 8345
-/* 7606 */    MCD_OPC_Decode, 249, 4, 80, // Opcode: LDMIA
-/* 7610 */    MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7624
-/* 7615 */    MCD_OPC_CheckPredicate, 0, 213, 2, 0, // Skip to: 8345
-/* 7620 */    MCD_OPC_Decode, 213, 6, 82, // Opcode: STMIA_UPD
-/* 7624 */    MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 7662
-/* 7629 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7653
-/* 7634 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7653
-/* 7641 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7653
-/* 7649 */    MCD_OPC_Decode, 224, 5, 81, // Opcode: RFEIA_UPD
-/* 7653 */    MCD_OPC_CheckPredicate, 0, 175, 2, 0, // Skip to: 8345
-/* 7658 */    MCD_OPC_Decode, 250, 4, 82, // Opcode: LDMIA_UPD
-/* 7662 */    MCD_OPC_FilterValue, 12, 34, 0, 0, // Skip to: 7701
-/* 7667 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7692
-/* 7672 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7692
-/* 7679 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7692
-/* 7688 */    MCD_OPC_Decode, 176, 6, 83, // Opcode: SRSIA
-/* 7692 */    MCD_OPC_CheckPredicate, 0, 136, 2, 0, // Skip to: 8345
-/* 7697 */    MCD_OPC_Decode, 194, 21, 80, // Opcode: sysSTMIA
-/* 7701 */    MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 7715
-/* 7706 */    MCD_OPC_CheckPredicate, 0, 122, 2, 0, // Skip to: 8345
-/* 7711 */    MCD_OPC_Decode, 186, 21, 80, // Opcode: sysLDMIA
-/* 7715 */    MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 7754
-/* 7720 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7745
-/* 7725 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7745
-/* 7732 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7745
-/* 7741 */    MCD_OPC_Decode, 177, 6, 83, // Opcode: SRSIA_UPD
-/* 7745 */    MCD_OPC_CheckPredicate, 0, 83, 2, 0, // Skip to: 8345
-/* 7750 */    MCD_OPC_Decode, 195, 21, 82, // Opcode: sysSTMIA_UPD
-/* 7754 */    MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 7768
-/* 7759 */    MCD_OPC_CheckPredicate, 0, 69, 2, 0, // Skip to: 8345
-/* 7764 */    MCD_OPC_Decode, 187, 21, 82, // Opcode: sysLDMIA_UPD
-/* 7768 */    MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 7782
-/* 7773 */    MCD_OPC_CheckPredicate, 0, 55, 2, 0, // Skip to: 8345
-/* 7778 */    MCD_OPC_Decode, 210, 6, 80, // Opcode: STMDB
-/* 7782 */    MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 7820
-/* 7787 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7811
-/* 7792 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7811
-/* 7799 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7811
-/* 7807 */    MCD_OPC_Decode, 221, 5, 81, // Opcode: RFEDB
-/* 7811 */    MCD_OPC_CheckPredicate, 0, 17, 2, 0, // Skip to: 8345
-/* 7816 */    MCD_OPC_Decode, 247, 4, 80, // Opcode: LDMDB
-/* 7820 */    MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 7834
-/* 7825 */    MCD_OPC_CheckPredicate, 0, 3, 2, 0, // Skip to: 8345
-/* 7830 */    MCD_OPC_Decode, 211, 6, 82, // Opcode: STMDB_UPD
-/* 7834 */    MCD_OPC_FilterValue, 19, 33, 0, 0, // Skip to: 7872
-/* 7839 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7863
-/* 7844 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7863
-/* 7851 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7863
-/* 7859 */    MCD_OPC_Decode, 222, 5, 81, // Opcode: RFEDB_UPD
-/* 7863 */    MCD_OPC_CheckPredicate, 0, 221, 1, 0, // Skip to: 8345
-/* 7868 */    MCD_OPC_Decode, 248, 4, 82, // Opcode: LDMDB_UPD
-/* 7872 */    MCD_OPC_FilterValue, 20, 34, 0, 0, // Skip to: 7911
-/* 7877 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7902
-/* 7882 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7902
-/* 7889 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7902
-/* 7898 */    MCD_OPC_Decode, 174, 6, 83, // Opcode: SRSDB
-/* 7902 */    MCD_OPC_CheckPredicate, 0, 182, 1, 0, // Skip to: 8345
-/* 7907 */    MCD_OPC_Decode, 192, 21, 80, // Opcode: sysSTMDB
-/* 7911 */    MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 7925
-/* 7916 */    MCD_OPC_CheckPredicate, 0, 168, 1, 0, // Skip to: 8345
-/* 7921 */    MCD_OPC_Decode, 184, 21, 80, // Opcode: sysLDMDB
-/* 7925 */    MCD_OPC_FilterValue, 22, 34, 0, 0, // Skip to: 7964
-/* 7930 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7955
-/* 7935 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7955
-/* 7942 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7955
-/* 7951 */    MCD_OPC_Decode, 175, 6, 83, // Opcode: SRSDB_UPD
-/* 7955 */    MCD_OPC_CheckPredicate, 0, 129, 1, 0, // Skip to: 8345
-/* 7960 */    MCD_OPC_Decode, 193, 21, 82, // Opcode: sysSTMDB_UPD
-/* 7964 */    MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 7978
-/* 7969 */    MCD_OPC_CheckPredicate, 0, 115, 1, 0, // Skip to: 8345
-/* 7974 */    MCD_OPC_Decode, 185, 21, 82, // Opcode: sysLDMDB_UPD
-/* 7978 */    MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 7992
-/* 7983 */    MCD_OPC_CheckPredicate, 0, 101, 1, 0, // Skip to: 8345
-/* 7988 */    MCD_OPC_Decode, 214, 6, 80, // Opcode: STMIB
-/* 7992 */    MCD_OPC_FilterValue, 25, 33, 0, 0, // Skip to: 8030
-/* 7997 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8021
-/* 8002 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8021
-/* 8009 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8021
-/* 8017 */    MCD_OPC_Decode, 225, 5, 81, // Opcode: RFEIB
-/* 8021 */    MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 8345
-/* 8026 */    MCD_OPC_Decode, 251, 4, 80, // Opcode: LDMIB
-/* 8030 */    MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 8044
-/* 8035 */    MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 8345
-/* 8040 */    MCD_OPC_Decode, 215, 6, 82, // Opcode: STMIB_UPD
-/* 8044 */    MCD_OPC_FilterValue, 27, 33, 0, 0, // Skip to: 8082
-/* 8049 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8073
-/* 8054 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8073
-/* 8061 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8073
-/* 8069 */    MCD_OPC_Decode, 226, 5, 81, // Opcode: RFEIB_UPD
-/* 8073 */    MCD_OPC_CheckPredicate, 0, 11, 1, 0, // Skip to: 8345
-/* 8078 */    MCD_OPC_Decode, 252, 4, 82, // Opcode: LDMIB_UPD
-/* 8082 */    MCD_OPC_FilterValue, 28, 34, 0, 0, // Skip to: 8121
-/* 8087 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8112
-/* 8092 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8112
-/* 8099 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8112
-/* 8108 */    MCD_OPC_Decode, 178, 6, 83, // Opcode: SRSIB
-/* 8112 */    MCD_OPC_CheckPredicate, 0, 228, 0, 0, // Skip to: 8345
-/* 8117 */    MCD_OPC_Decode, 196, 21, 80, // Opcode: sysSTMIB
-/* 8121 */    MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 8135
-/* 8126 */    MCD_OPC_CheckPredicate, 0, 214, 0, 0, // Skip to: 8345
-/* 8131 */    MCD_OPC_Decode, 188, 21, 80, // Opcode: sysLDMIB
-/* 8135 */    MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 8174
-/* 8140 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8165
-/* 8145 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8165
-/* 8152 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8165
-/* 8161 */    MCD_OPC_Decode, 179, 6, 83, // Opcode: SRSIB_UPD
-/* 8165 */    MCD_OPC_CheckPredicate, 0, 175, 0, 0, // Skip to: 8345
-/* 8170 */    MCD_OPC_Decode, 197, 21, 82, // Opcode: sysSTMIB_UPD
-/* 8174 */    MCD_OPC_FilterValue, 31, 166, 0, 0, // Skip to: 8345
-/* 8179 */    MCD_OPC_CheckPredicate, 0, 161, 0, 0, // Skip to: 8345
-/* 8184 */    MCD_OPC_Decode, 189, 21, 82, // Opcode: sysLDMIB_UPD
-/* 8188 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8256
-/* 8193 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 8196 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8210
-/* 8201 */    MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 8240
-/* 8206 */    MCD_OPC_Decode, 178, 4, 84, // Opcode: Bcc
-/* 8210 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 8240
-/* 8215 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8231
-/* 8220 */    MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 8231
-/* 8227 */    MCD_OPC_Decode, 169, 4, 84, // Opcode: BL
-/* 8231 */    MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 8240
-/* 8236 */    MCD_OPC_Decode, 173, 4, 84, // Opcode: BL_pred
-/* 8240 */    MCD_OPC_CheckPredicate, 11, 100, 0, 0, // Skip to: 8345
-/* 8245 */    MCD_OPC_CheckField, 28, 4, 15, 93, 0, 0, // Skip to: 8345
-/* 8252 */    MCD_OPC_Decode, 172, 4, 85, // Opcode: BLXi
-/* 8256 */    MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 8324
-/* 8261 */    MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
-/* 8264 */    MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 8294
-/* 8269 */    MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8285
-/* 8274 */    MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8285
-/* 8281 */    MCD_OPC_Decode, 167, 5, 86, // Opcode: MCRR2
-/* 8285 */    MCD_OPC_CheckPredicate, 0, 55, 0, 0, // Skip to: 8345
-/* 8290 */    MCD_OPC_Decode, 166, 5, 87, // Opcode: MCRR
-/* 8294 */    MCD_OPC_FilterValue, 5, 46, 0, 0, // Skip to: 8345
-/* 8299 */    MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8315
-/* 8304 */    MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8315
-/* 8311 */    MCD_OPC_Decode, 181, 5, 86, // Opcode: MRRC2
-/* 8315 */    MCD_OPC_CheckPredicate, 0, 25, 0, 0, // Skip to: 8345
-/* 8320 */    MCD_OPC_Decode, 180, 5, 88, // Opcode: MRRC
-/* 8324 */    MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 8345
-/* 8329 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8345
-/* 8334 */    MCD_OPC_CheckField, 24, 1, 1, 4, 0, 0, // Skip to: 8345
-/* 8341 */    MCD_OPC_Decode, 248, 6, 89, // Opcode: SVC
-/* 8345 */    MCD_OPC_Fail,
+/* 6731 */    MCD_OPC_CheckPredicate, 0, 109, 6, 0, // Skip to: 8381
+/* 6736 */    MCD_OPC_Decode, 132, 15, 55, // Opcode: STRBT_POST_REG
+/* 6740 */    MCD_OPC_FilterValue, 1, 100, 6, 0, // Skip to: 8381
+/* 6745 */    MCD_OPC_CheckPredicate, 0, 95, 6, 0, // Skip to: 8381
+/* 6750 */    MCD_OPC_Decode, 136, 15, 73, // Opcode: STRB_PRE_REG
+/* 6754 */    MCD_OPC_FilterValue, 1, 86, 6, 0, // Skip to: 8381
+/* 6759 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 6762 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6776
+/* 6767 */    MCD_OPC_CheckPredicate, 0, 73, 6, 0, // Skip to: 8381
+/* 6772 */    MCD_OPC_Decode, 215, 6, 55, // Opcode: LDRBT_POST_REG
+/* 6776 */    MCD_OPC_FilterValue, 1, 64, 6, 0, // Skip to: 8381
+/* 6781 */    MCD_OPC_CheckPredicate, 0, 59, 6, 0, // Skip to: 8381
+/* 6786 */    MCD_OPC_Decode, 219, 6, 74, // Opcode: LDRB_PRE_REG
+/* 6790 */    MCD_OPC_FilterValue, 1, 50, 6, 0, // Skip to: 8381
+/* 6795 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 6798 */    MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 7070
+/* 6803 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
+/* 6806 */    MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 6850
+/* 6811 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6814 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6832
+/* 6819 */    MCD_OPC_CheckPredicate, 0, 21, 6, 0, // Skip to: 8381
+/* 6824 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6828 */    MCD_OPC_Decode, 198, 15, 66, // Opcode: UQADD16
+/* 6832 */    MCD_OPC_FilterValue, 1, 8, 6, 0, // Skip to: 8381
+/* 6837 */    MCD_OPC_CheckPredicate, 0, 3, 6, 0, // Skip to: 8381
+/* 6842 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6846 */    MCD_OPC_Decode, 189, 15, 66, // Opcode: UHADD16
+/* 6850 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 6894
+/* 6855 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6858 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6876
+/* 6863 */    MCD_OPC_CheckPredicate, 0, 233, 5, 0, // Skip to: 8381
+/* 6868 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6872 */    MCD_OPC_Decode, 200, 15, 66, // Opcode: UQASX
+/* 6876 */    MCD_OPC_FilterValue, 1, 220, 5, 0, // Skip to: 8381
+/* 6881 */    MCD_OPC_CheckPredicate, 0, 215, 5, 0, // Skip to: 8381
+/* 6886 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6890 */    MCD_OPC_Decode, 191, 15, 66, // Opcode: UHASX
+/* 6894 */    MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 6938
+/* 6899 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6902 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6920
+/* 6907 */    MCD_OPC_CheckPredicate, 0, 189, 5, 0, // Skip to: 8381
+/* 6912 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6916 */    MCD_OPC_Decode, 201, 15, 66, // Opcode: UQSAX
+/* 6920 */    MCD_OPC_FilterValue, 1, 176, 5, 0, // Skip to: 8381
+/* 6925 */    MCD_OPC_CheckPredicate, 0, 171, 5, 0, // Skip to: 8381
+/* 6930 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6934 */    MCD_OPC_Decode, 192, 15, 66, // Opcode: UHSAX
+/* 6938 */    MCD_OPC_FilterValue, 3, 39, 0, 0, // Skip to: 6982
+/* 6943 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6946 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 6964
+/* 6951 */    MCD_OPC_CheckPredicate, 0, 145, 5, 0, // Skip to: 8381
+/* 6956 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6960 */    MCD_OPC_Decode, 202, 15, 66, // Opcode: UQSUB16
+/* 6964 */    MCD_OPC_FilterValue, 1, 132, 5, 0, // Skip to: 8381
+/* 6969 */    MCD_OPC_CheckPredicate, 0, 127, 5, 0, // Skip to: 8381
+/* 6974 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 6978 */    MCD_OPC_Decode, 193, 15, 66, // Opcode: UHSUB16
+/* 6982 */    MCD_OPC_FilterValue, 4, 39, 0, 0, // Skip to: 7026
+/* 6987 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6990 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 7008
+/* 6995 */    MCD_OPC_CheckPredicate, 0, 101, 5, 0, // Skip to: 8381
+/* 7000 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 7004 */    MCD_OPC_Decode, 199, 15, 66, // Opcode: UQADD8
+/* 7008 */    MCD_OPC_FilterValue, 1, 88, 5, 0, // Skip to: 8381
+/* 7013 */    MCD_OPC_CheckPredicate, 0, 83, 5, 0, // Skip to: 8381
+/* 7018 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 7022 */    MCD_OPC_Decode, 190, 15, 66, // Opcode: UHADD8
+/* 7026 */    MCD_OPC_FilterValue, 7, 70, 5, 0, // Skip to: 8381
+/* 7031 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7034 */    MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 7052
+/* 7039 */    MCD_OPC_CheckPredicate, 0, 57, 5, 0, // Skip to: 8381
+/* 7044 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 7048 */    MCD_OPC_Decode, 203, 15, 66, // Opcode: UQSUB8
+/* 7052 */    MCD_OPC_FilterValue, 1, 44, 5, 0, // Skip to: 8381
+/* 7057 */    MCD_OPC_CheckPredicate, 0, 39, 5, 0, // Skip to: 8381
+/* 7062 */    MCD_OPC_SoftFail, 0, 128, 30 /* 0xf00 */,
+/* 7066 */    MCD_OPC_Decode, 194, 15, 66, // Opcode: UHSUB8
+/* 7070 */    MCD_OPC_FilterValue, 1, 194, 0, 0, // Skip to: 7269
+/* 7075 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 7078 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7092
+/* 7083 */    MCD_OPC_CheckPredicate, 1, 13, 5, 0, // Skip to: 8381
+/* 7088 */    MCD_OPC_Decode, 206, 15, 75, // Opcode: USAT
+/* 7092 */    MCD_OPC_FilterValue, 1, 4, 5, 0, // Skip to: 8381
+/* 7097 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7100 */    MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 7157
+/* 7105 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7108 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7129
+/* 7113 */    MCD_OPC_CheckPredicate, 1, 239, 4, 0, // Skip to: 8381
+/* 7118 */    MCD_OPC_CheckField, 8, 4, 15, 232, 4, 0, // Skip to: 8381
+/* 7125 */    MCD_OPC_Decode, 207, 15, 76, // Opcode: USAT16
+/* 7129 */    MCD_OPC_FilterValue, 1, 223, 4, 0, // Skip to: 8381
+/* 7134 */    MCD_OPC_CheckPredicate, 13, 218, 4, 0, // Skip to: 8381
+/* 7139 */    MCD_OPC_CheckField, 16, 4, 15, 211, 4, 0, // Skip to: 8381
+/* 7146 */    MCD_OPC_CheckField, 8, 4, 15, 204, 4, 0, // Skip to: 8381
+/* 7153 */    MCD_OPC_Decode, 129, 14, 35, // Opcode: RBIT
+/* 7157 */    MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 7241
+/* 7162 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7165 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7203
+/* 7170 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7190
+/* 7175 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7190
+/* 7182 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 7186 */    MCD_OPC_Decode, 214, 15, 71, // Opcode: UXTB
+/* 7190 */    MCD_OPC_CheckPredicate, 1, 162, 4, 0, // Skip to: 8381
+/* 7195 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 7199 */    MCD_OPC_Decode, 211, 15, 72, // Opcode: UXTAB
+/* 7203 */    MCD_OPC_FilterValue, 1, 149, 4, 0, // Skip to: 8381
+/* 7208 */    MCD_OPC_CheckPredicate, 1, 15, 0, 0, // Skip to: 7228
+/* 7213 */    MCD_OPC_CheckField, 16, 4, 15, 8, 0, 0, // Skip to: 7228
+/* 7220 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 7224 */    MCD_OPC_Decode, 216, 15, 71, // Opcode: UXTH
+/* 7228 */    MCD_OPC_CheckPredicate, 1, 124, 4, 0, // Skip to: 8381
+/* 7233 */    MCD_OPC_SoftFail, 128, 6 /* 0x300 */, 0,
+/* 7237 */    MCD_OPC_Decode, 213, 15, 72, // Opcode: UXTAH
+/* 7241 */    MCD_OPC_FilterValue, 2, 111, 4, 0, // Skip to: 8381
+/* 7246 */    MCD_OPC_CheckPredicate, 1, 106, 4, 0, // Skip to: 8381
+/* 7251 */    MCD_OPC_CheckField, 16, 5, 31, 99, 4, 0, // Skip to: 8381
+/* 7258 */    MCD_OPC_CheckField, 8, 4, 15, 92, 4, 0, // Skip to: 8381
+/* 7265 */    MCD_OPC_Decode, 132, 14, 35, // Opcode: REVSH
+/* 7269 */    MCD_OPC_FilterValue, 3, 83, 4, 0, // Skip to: 8381
+/* 7274 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
+/* 7277 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7291
+/* 7282 */    MCD_OPC_CheckPredicate, 13, 70, 4, 0, // Skip to: 8381
+/* 7287 */    MCD_OPC_Decode, 186, 15, 77, // Opcode: UBFX
+/* 7291 */    MCD_OPC_FilterValue, 3, 61, 4, 0, // Skip to: 8381
+/* 7296 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7299 */    MCD_OPC_FilterValue, 1, 53, 4, 0, // Skip to: 8381
+/* 7304 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7307 */    MCD_OPC_FilterValue, 1, 45, 4, 0, // Skip to: 8381
+/* 7312 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7315 */    MCD_OPC_FilterValue, 14, 37, 4, 0, // Skip to: 8381
+/* 7320 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
+/* 7323 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7345
+/* 7328 */    MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 7367
+/* 7333 */    MCD_OPC_CheckField, 8, 12, 222, 29, 26, 0, 0, // Skip to: 7367
+/* 7341 */    MCD_OPC_Decode, 177, 15, 61, // Opcode: TRAPNaCl
+/* 7345 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7367
+/* 7350 */    MCD_OPC_CheckPredicate, 0, 12, 0, 0, // Skip to: 7367
+/* 7355 */    MCD_OPC_CheckField, 8, 12, 222, 31, 4, 0, 0, // Skip to: 7367
+/* 7363 */    MCD_OPC_Decode, 176, 15, 61, // Opcode: TRAP
+/* 7367 */    MCD_OPC_CheckPredicate, 0, 241, 3, 0, // Skip to: 8381
+/* 7372 */    MCD_OPC_Decode, 187, 15, 15, // Opcode: UDF
+/* 7376 */    MCD_OPC_FilterValue, 4, 75, 3, 0, // Skip to: 8224
+/* 7381 */    MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 7384 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7398
+/* 7389 */    MCD_OPC_CheckPredicate, 0, 219, 3, 0, // Skip to: 8381
+/* 7394 */    MCD_OPC_Decode, 251, 14, 81, // Opcode: STMDA
+/* 7398 */    MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 7436
+/* 7403 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7427
+/* 7408 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7427
+/* 7415 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7427
+/* 7423 */    MCD_OPC_Decode, 133, 14, 82, // Opcode: RFEDA
+/* 7427 */    MCD_OPC_CheckPredicate, 0, 181, 3, 0, // Skip to: 8381
+/* 7432 */    MCD_OPC_Decode, 206, 6, 81, // Opcode: LDMDA
+/* 7436 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7450
+/* 7441 */    MCD_OPC_CheckPredicate, 0, 167, 3, 0, // Skip to: 8381
+/* 7446 */    MCD_OPC_Decode, 252, 14, 83, // Opcode: STMDA_UPD
+/* 7450 */    MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 7488
+/* 7455 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7479
+/* 7460 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7479
+/* 7467 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7479
+/* 7475 */    MCD_OPC_Decode, 134, 14, 84, // Opcode: RFEDA_UPD
+/* 7479 */    MCD_OPC_CheckPredicate, 0, 129, 3, 0, // Skip to: 8381
+/* 7484 */    MCD_OPC_Decode, 207, 6, 83, // Opcode: LDMDA_UPD
+/* 7488 */    MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 7527
+/* 7493 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7518
+/* 7498 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7518
+/* 7505 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7518
+/* 7514 */    MCD_OPC_Decode, 215, 14, 85, // Opcode: SRSDA
+/* 7518 */    MCD_OPC_CheckPredicate, 0, 90, 3, 0, // Skip to: 8381
+/* 7523 */    MCD_OPC_Decode, 221, 30, 81, // Opcode: sysSTMDA
+/* 7527 */    MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 7541
+/* 7532 */    MCD_OPC_CheckPredicate, 0, 76, 3, 0, // Skip to: 8381
+/* 7537 */    MCD_OPC_Decode, 213, 30, 81, // Opcode: sysLDMDA
+/* 7541 */    MCD_OPC_FilterValue, 6, 34, 0, 0, // Skip to: 7580
+/* 7546 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7571
+/* 7551 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7571
+/* 7558 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7571
+/* 7567 */    MCD_OPC_Decode, 216, 14, 85, // Opcode: SRSDA_UPD
+/* 7571 */    MCD_OPC_CheckPredicate, 0, 37, 3, 0, // Skip to: 8381
+/* 7576 */    MCD_OPC_Decode, 222, 30, 83, // Opcode: sysSTMDA_UPD
+/* 7580 */    MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 7594
+/* 7585 */    MCD_OPC_CheckPredicate, 0, 23, 3, 0, // Skip to: 8381
+/* 7590 */    MCD_OPC_Decode, 214, 30, 83, // Opcode: sysLDMDA_UPD
+/* 7594 */    MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7608
+/* 7599 */    MCD_OPC_CheckPredicate, 0, 9, 3, 0, // Skip to: 8381
+/* 7604 */    MCD_OPC_Decode, 255, 14, 81, // Opcode: STMIA
+/* 7608 */    MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 7646
+/* 7613 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7637
+/* 7618 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7637
+/* 7625 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7637
+/* 7633 */    MCD_OPC_Decode, 137, 14, 82, // Opcode: RFEIA
+/* 7637 */    MCD_OPC_CheckPredicate, 0, 227, 2, 0, // Skip to: 8381
+/* 7642 */    MCD_OPC_Decode, 210, 6, 81, // Opcode: LDMIA
+/* 7646 */    MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7660
+/* 7651 */    MCD_OPC_CheckPredicate, 0, 213, 2, 0, // Skip to: 8381
+/* 7656 */    MCD_OPC_Decode, 128, 15, 83, // Opcode: STMIA_UPD
+/* 7660 */    MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 7698
+/* 7665 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7689
+/* 7670 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7689
+/* 7677 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7689
+/* 7685 */    MCD_OPC_Decode, 138, 14, 84, // Opcode: RFEIA_UPD
+/* 7689 */    MCD_OPC_CheckPredicate, 0, 175, 2, 0, // Skip to: 8381
+/* 7694 */    MCD_OPC_Decode, 211, 6, 83, // Opcode: LDMIA_UPD
+/* 7698 */    MCD_OPC_FilterValue, 12, 34, 0, 0, // Skip to: 7737
+/* 7703 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7728
+/* 7708 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7728
+/* 7715 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7728
+/* 7724 */    MCD_OPC_Decode, 219, 14, 85, // Opcode: SRSIA
+/* 7728 */    MCD_OPC_CheckPredicate, 0, 136, 2, 0, // Skip to: 8381
+/* 7733 */    MCD_OPC_Decode, 225, 30, 81, // Opcode: sysSTMIA
+/* 7737 */    MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 7751
+/* 7742 */    MCD_OPC_CheckPredicate, 0, 122, 2, 0, // Skip to: 8381
+/* 7747 */    MCD_OPC_Decode, 217, 30, 81, // Opcode: sysLDMIA
+/* 7751 */    MCD_OPC_FilterValue, 14, 34, 0, 0, // Skip to: 7790
+/* 7756 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7781
+/* 7761 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7781
+/* 7768 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7781
+/* 7777 */    MCD_OPC_Decode, 220, 14, 85, // Opcode: SRSIA_UPD
+/* 7781 */    MCD_OPC_CheckPredicate, 0, 83, 2, 0, // Skip to: 8381
+/* 7786 */    MCD_OPC_Decode, 226, 30, 83, // Opcode: sysSTMIA_UPD
+/* 7790 */    MCD_OPC_FilterValue, 15, 9, 0, 0, // Skip to: 7804
+/* 7795 */    MCD_OPC_CheckPredicate, 0, 69, 2, 0, // Skip to: 8381
+/* 7800 */    MCD_OPC_Decode, 218, 30, 83, // Opcode: sysLDMIA_UPD
+/* 7804 */    MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 7818
+/* 7809 */    MCD_OPC_CheckPredicate, 0, 55, 2, 0, // Skip to: 8381
+/* 7814 */    MCD_OPC_Decode, 253, 14, 81, // Opcode: STMDB
+/* 7818 */    MCD_OPC_FilterValue, 17, 33, 0, 0, // Skip to: 7856
+/* 7823 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7847
+/* 7828 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7847
+/* 7835 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7847
+/* 7843 */    MCD_OPC_Decode, 135, 14, 82, // Opcode: RFEDB
+/* 7847 */    MCD_OPC_CheckPredicate, 0, 17, 2, 0, // Skip to: 8381
+/* 7852 */    MCD_OPC_Decode, 208, 6, 81, // Opcode: LDMDB
+/* 7856 */    MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 7870
+/* 7861 */    MCD_OPC_CheckPredicate, 0, 3, 2, 0, // Skip to: 8381
+/* 7866 */    MCD_OPC_Decode, 254, 14, 83, // Opcode: STMDB_UPD
+/* 7870 */    MCD_OPC_FilterValue, 19, 33, 0, 0, // Skip to: 7908
+/* 7875 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 7899
+/* 7880 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 7899
+/* 7887 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 7899
+/* 7895 */    MCD_OPC_Decode, 136, 14, 84, // Opcode: RFEDB_UPD
+/* 7899 */    MCD_OPC_CheckPredicate, 0, 221, 1, 0, // Skip to: 8381
+/* 7904 */    MCD_OPC_Decode, 209, 6, 83, // Opcode: LDMDB_UPD
+/* 7908 */    MCD_OPC_FilterValue, 20, 34, 0, 0, // Skip to: 7947
+/* 7913 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7938
+/* 7918 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7938
+/* 7925 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7938
+/* 7934 */    MCD_OPC_Decode, 217, 14, 85, // Opcode: SRSDB
+/* 7938 */    MCD_OPC_CheckPredicate, 0, 182, 1, 0, // Skip to: 8381
+/* 7943 */    MCD_OPC_Decode, 223, 30, 81, // Opcode: sysSTMDB
+/* 7947 */    MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 7961
+/* 7952 */    MCD_OPC_CheckPredicate, 0, 168, 1, 0, // Skip to: 8381
+/* 7957 */    MCD_OPC_Decode, 215, 30, 81, // Opcode: sysLDMDB
+/* 7961 */    MCD_OPC_FilterValue, 22, 34, 0, 0, // Skip to: 8000
+/* 7966 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 7991
+/* 7971 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 7991
+/* 7978 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 7991
+/* 7987 */    MCD_OPC_Decode, 218, 14, 85, // Opcode: SRSDB_UPD
+/* 7991 */    MCD_OPC_CheckPredicate, 0, 129, 1, 0, // Skip to: 8381
+/* 7996 */    MCD_OPC_Decode, 224, 30, 83, // Opcode: sysSTMDB_UPD
+/* 8000 */    MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 8014
+/* 8005 */    MCD_OPC_CheckPredicate, 0, 115, 1, 0, // Skip to: 8381
+/* 8010 */    MCD_OPC_Decode, 216, 30, 83, // Opcode: sysLDMDB_UPD
+/* 8014 */    MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 8028
+/* 8019 */    MCD_OPC_CheckPredicate, 0, 101, 1, 0, // Skip to: 8381
+/* 8024 */    MCD_OPC_Decode, 129, 15, 81, // Opcode: STMIB
+/* 8028 */    MCD_OPC_FilterValue, 25, 33, 0, 0, // Skip to: 8066
+/* 8033 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8057
+/* 8038 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8057
+/* 8045 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8057
+/* 8053 */    MCD_OPC_Decode, 139, 14, 82, // Opcode: RFEIB
+/* 8057 */    MCD_OPC_CheckPredicate, 0, 63, 1, 0, // Skip to: 8381
+/* 8062 */    MCD_OPC_Decode, 212, 6, 81, // Opcode: LDMIB
+/* 8066 */    MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 8080
+/* 8071 */    MCD_OPC_CheckPredicate, 0, 49, 1, 0, // Skip to: 8381
+/* 8076 */    MCD_OPC_Decode, 130, 15, 83, // Opcode: STMIB_UPD
+/* 8080 */    MCD_OPC_FilterValue, 27, 33, 0, 0, // Skip to: 8118
+/* 8085 */    MCD_OPC_CheckPredicate, 0, 19, 0, 0, // Skip to: 8109
+/* 8090 */    MCD_OPC_CheckField, 28, 4, 15, 12, 0, 0, // Skip to: 8109
+/* 8097 */    MCD_OPC_CheckField, 0, 16, 128, 20, 4, 0, 0, // Skip to: 8109
+/* 8105 */    MCD_OPC_Decode, 140, 14, 84, // Opcode: RFEIB_UPD
+/* 8109 */    MCD_OPC_CheckPredicate, 0, 11, 1, 0, // Skip to: 8381
+/* 8114 */    MCD_OPC_Decode, 213, 6, 83, // Opcode: LDMIB_UPD
+/* 8118 */    MCD_OPC_FilterValue, 28, 34, 0, 0, // Skip to: 8157
+/* 8123 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8148
+/* 8128 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8148
+/* 8135 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8148
+/* 8144 */    MCD_OPC_Decode, 221, 14, 85, // Opcode: SRSIB
+/* 8148 */    MCD_OPC_CheckPredicate, 0, 228, 0, 0, // Skip to: 8381
+/* 8153 */    MCD_OPC_Decode, 227, 30, 81, // Opcode: sysSTMIB
+/* 8157 */    MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 8171
+/* 8162 */    MCD_OPC_CheckPredicate, 0, 214, 0, 0, // Skip to: 8381
+/* 8167 */    MCD_OPC_Decode, 219, 30, 81, // Opcode: sysLDMIB
+/* 8171 */    MCD_OPC_FilterValue, 30, 34, 0, 0, // Skip to: 8210
+/* 8176 */    MCD_OPC_CheckPredicate, 0, 20, 0, 0, // Skip to: 8201
+/* 8181 */    MCD_OPC_CheckField, 28, 4, 15, 13, 0, 0, // Skip to: 8201
+/* 8188 */    MCD_OPC_CheckField, 5, 15, 168, 208, 1, 4, 0, 0, // Skip to: 8201
+/* 8197 */    MCD_OPC_Decode, 222, 14, 85, // Opcode: SRSIB_UPD
+/* 8201 */    MCD_OPC_CheckPredicate, 0, 175, 0, 0, // Skip to: 8381
+/* 8206 */    MCD_OPC_Decode, 228, 30, 83, // Opcode: sysSTMIB_UPD
+/* 8210 */    MCD_OPC_FilterValue, 31, 166, 0, 0, // Skip to: 8381
+/* 8215 */    MCD_OPC_CheckPredicate, 0, 161, 0, 0, // Skip to: 8381
+/* 8220 */    MCD_OPC_Decode, 220, 30, 83, // Opcode: sysLDMIB_UPD
+/* 8224 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8292
+/* 8229 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 8232 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8246
+/* 8237 */    MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 8276
+/* 8242 */    MCD_OPC_Decode, 237, 5, 86, // Opcode: Bcc
+/* 8246 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 8276
+/* 8251 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8267
+/* 8256 */    MCD_OPC_CheckField, 28, 4, 14, 4, 0, 0, // Skip to: 8267
+/* 8263 */    MCD_OPC_Decode, 228, 5, 86, // Opcode: BL
+/* 8267 */    MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 8276
+/* 8272 */    MCD_OPC_Decode, 232, 5, 86, // Opcode: BL_pred
+/* 8276 */    MCD_OPC_CheckPredicate, 11, 100, 0, 0, // Skip to: 8381
+/* 8281 */    MCD_OPC_CheckField, 28, 4, 15, 93, 0, 0, // Skip to: 8381
+/* 8288 */    MCD_OPC_Decode, 231, 5, 87, // Opcode: BLXi
+/* 8292 */    MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 8360
+/* 8297 */    MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 8300 */    MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 8330
+/* 8305 */    MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8321
+/* 8310 */    MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8321
+/* 8317 */    MCD_OPC_Decode, 128, 7, 88, // Opcode: MCRR2
+/* 8321 */    MCD_OPC_CheckPredicate, 0, 55, 0, 0, // Skip to: 8381
+/* 8326 */    MCD_OPC_Decode, 255, 6, 89, // Opcode: MCRR
+/* 8330 */    MCD_OPC_FilterValue, 5, 46, 0, 0, // Skip to: 8381
+/* 8335 */    MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 8351
+/* 8340 */    MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 8351
+/* 8347 */    MCD_OPC_Decode, 142, 7, 88, // Opcode: MRRC2
+/* 8351 */    MCD_OPC_CheckPredicate, 0, 25, 0, 0, // Skip to: 8381
+/* 8356 */    MCD_OPC_Decode, 141, 7, 90, // Opcode: MRRC
+/* 8360 */    MCD_OPC_FilterValue, 7, 16, 0, 0, // Skip to: 8381
+/* 8365 */    MCD_OPC_CheckPredicate, 0, 11, 0, 0, // Skip to: 8381
+/* 8370 */    MCD_OPC_CheckField, 24, 1, 1, 4, 0, 0, // Skip to: 8381
+/* 8377 */    MCD_OPC_Decode, 163, 15, 91, // Opcode: SVC
+/* 8381 */    MCD_OPC_Fail,
   0
 };
 
@@ -1769,4037 +1778,8921 @@ static const uint8_t DecoderTableCoProc32[] = {
 /* 19 */      MCD_OPC_FilterValue, 1, 101, 2, 0, // Skip to: 637
 /* 24 */      MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 40
 /* 29 */      MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 40
-/* 36 */      MCD_OPC_Decode, 190, 6, 90, // Opcode: STC2_OPTION
+/* 36 */      MCD_OPC_Decode, 233, 14, 92, // Opcode: STC2_OPTION
 /* 40 */      MCD_OPC_CheckPredicate, 0, 80, 2, 0, // Skip to: 637
-/* 45 */      MCD_OPC_Decode, 198, 6, 90, // Opcode: STC_OPTION
+/* 45 */      MCD_OPC_Decode, 241, 14, 92, // Opcode: STC_OPTION
 /* 49 */      MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 87
 /* 54 */      MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 57 */      MCD_OPC_FilterValue, 1, 63, 2, 0, // Skip to: 637
 /* 62 */      MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 78
 /* 67 */      MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 78
-/* 74 */      MCD_OPC_Decode, 234, 4, 90, // Opcode: LDC2_OPTION
+/* 74 */      MCD_OPC_Decode, 195, 6, 92, // Opcode: LDC2_OPTION
 /* 78 */      MCD_OPC_CheckPredicate, 0, 42, 2, 0, // Skip to: 637
-/* 83 */      MCD_OPC_Decode, 242, 4, 90, // Opcode: LDC_OPTION
+/* 83 */      MCD_OPC_Decode, 203, 6, 92, // Opcode: LDC_OPTION
 /* 87 */      MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 117
 /* 92 */      MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 108
 /* 97 */      MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 108
-/* 104 */     MCD_OPC_Decode, 191, 6, 90, // Opcode: STC2_POST
+/* 104 */     MCD_OPC_Decode, 234, 14, 92, // Opcode: STC2_POST
 /* 108 */     MCD_OPC_CheckPredicate, 0, 12, 2, 0, // Skip to: 637
-/* 113 */     MCD_OPC_Decode, 199, 6, 90, // Opcode: STC_POST
+/* 113 */     MCD_OPC_Decode, 242, 14, 92, // Opcode: STC_POST
 /* 117 */     MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 147
 /* 122 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 138
 /* 127 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 138
-/* 134 */     MCD_OPC_Decode, 235, 4, 90, // Opcode: LDC2_POST
+/* 134 */     MCD_OPC_Decode, 196, 6, 92, // Opcode: LDC2_POST
 /* 138 */     MCD_OPC_CheckPredicate, 0, 238, 1, 0, // Skip to: 637
-/* 143 */     MCD_OPC_Decode, 243, 4, 90, // Opcode: LDC_POST
+/* 143 */     MCD_OPC_Decode, 204, 6, 92, // Opcode: LDC_POST
 /* 147 */     MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 185
 /* 152 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 155 */     MCD_OPC_FilterValue, 1, 221, 1, 0, // Skip to: 637
 /* 160 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 176
 /* 165 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 176
-/* 172 */     MCD_OPC_Decode, 186, 6, 90, // Opcode: STC2L_OPTION
+/* 172 */     MCD_OPC_Decode, 229, 14, 92, // Opcode: STC2L_OPTION
 /* 176 */     MCD_OPC_CheckPredicate, 0, 200, 1, 0, // Skip to: 637
-/* 181 */     MCD_OPC_Decode, 194, 6, 90, // Opcode: STCL_OPTION
+/* 181 */     MCD_OPC_Decode, 237, 14, 92, // Opcode: STCL_OPTION
 /* 185 */     MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 223
 /* 190 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 193 */     MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 637
 /* 198 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 214
 /* 203 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 214
-/* 210 */     MCD_OPC_Decode, 230, 4, 90, // Opcode: LDC2L_OPTION
+/* 210 */     MCD_OPC_Decode, 191, 6, 92, // Opcode: LDC2L_OPTION
 /* 214 */     MCD_OPC_CheckPredicate, 0, 162, 1, 0, // Skip to: 637
-/* 219 */     MCD_OPC_Decode, 238, 4, 90, // Opcode: LDCL_OPTION
+/* 219 */     MCD_OPC_Decode, 199, 6, 92, // Opcode: LDCL_OPTION
 /* 223 */     MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 253
 /* 228 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 244
 /* 233 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 244
-/* 240 */     MCD_OPC_Decode, 187, 6, 90, // Opcode: STC2L_POST
+/* 240 */     MCD_OPC_Decode, 230, 14, 92, // Opcode: STC2L_POST
 /* 244 */     MCD_OPC_CheckPredicate, 0, 132, 1, 0, // Skip to: 637
-/* 249 */     MCD_OPC_Decode, 195, 6, 90, // Opcode: STCL_POST
+/* 249 */     MCD_OPC_Decode, 238, 14, 92, // Opcode: STCL_POST
 /* 253 */     MCD_OPC_FilterValue, 7, 123, 1, 0, // Skip to: 637
 /* 258 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 274
 /* 263 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 274
-/* 270 */     MCD_OPC_Decode, 231, 4, 90, // Opcode: LDC2L_POST
+/* 270 */     MCD_OPC_Decode, 192, 6, 92, // Opcode: LDC2L_POST
 /* 274 */     MCD_OPC_CheckPredicate, 0, 102, 1, 0, // Skip to: 637
-/* 279 */     MCD_OPC_Decode, 239, 4, 90, // Opcode: LDCL_POST
+/* 279 */     MCD_OPC_Decode, 200, 6, 92, // Opcode: LDCL_POST
 /* 283 */     MCD_OPC_FilterValue, 13, 243, 0, 0, // Skip to: 531
 /* 288 */     MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
 /* 291 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 321
 /* 296 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 312
 /* 301 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 312
-/* 308 */     MCD_OPC_Decode, 189, 6, 90, // Opcode: STC2_OFFSET
+/* 308 */     MCD_OPC_Decode, 232, 14, 92, // Opcode: STC2_OFFSET
 /* 312 */     MCD_OPC_CheckPredicate, 0, 64, 1, 0, // Skip to: 637
-/* 317 */     MCD_OPC_Decode, 197, 6, 90, // Opcode: STC_OFFSET
+/* 317 */     MCD_OPC_Decode, 240, 14, 92, // Opcode: STC_OFFSET
 /* 321 */     MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 351
 /* 326 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 342
 /* 331 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 342
-/* 338 */     MCD_OPC_Decode, 233, 4, 90, // Opcode: LDC2_OFFSET
+/* 338 */     MCD_OPC_Decode, 194, 6, 92, // Opcode: LDC2_OFFSET
 /* 342 */     MCD_OPC_CheckPredicate, 0, 34, 1, 0, // Skip to: 637
-/* 347 */     MCD_OPC_Decode, 241, 4, 90, // Opcode: LDC_OFFSET
+/* 347 */     MCD_OPC_Decode, 202, 6, 92, // Opcode: LDC_OFFSET
 /* 351 */     MCD_OPC_FilterValue, 2, 25, 0, 0, // Skip to: 381
 /* 356 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 372
 /* 361 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 372
-/* 368 */     MCD_OPC_Decode, 192, 6, 90, // Opcode: STC2_PRE
+/* 368 */     MCD_OPC_Decode, 235, 14, 92, // Opcode: STC2_PRE
 /* 372 */     MCD_OPC_CheckPredicate, 0, 4, 1, 0, // Skip to: 637
-/* 377 */     MCD_OPC_Decode, 200, 6, 90, // Opcode: STC_PRE
+/* 377 */     MCD_OPC_Decode, 243, 14, 92, // Opcode: STC_PRE
 /* 381 */     MCD_OPC_FilterValue, 3, 25, 0, 0, // Skip to: 411
 /* 386 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 402
 /* 391 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 402
-/* 398 */     MCD_OPC_Decode, 236, 4, 90, // Opcode: LDC2_PRE
+/* 398 */     MCD_OPC_Decode, 197, 6, 92, // Opcode: LDC2_PRE
 /* 402 */     MCD_OPC_CheckPredicate, 0, 230, 0, 0, // Skip to: 637
-/* 407 */     MCD_OPC_Decode, 244, 4, 90, // Opcode: LDC_PRE
+/* 407 */     MCD_OPC_Decode, 205, 6, 92, // Opcode: LDC_PRE
 /* 411 */     MCD_OPC_FilterValue, 4, 25, 0, 0, // Skip to: 441
 /* 416 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 432
 /* 421 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 432
-/* 428 */     MCD_OPC_Decode, 185, 6, 90, // Opcode: STC2L_OFFSET
+/* 428 */     MCD_OPC_Decode, 228, 14, 92, // Opcode: STC2L_OFFSET
 /* 432 */     MCD_OPC_CheckPredicate, 0, 200, 0, 0, // Skip to: 637
-/* 437 */     MCD_OPC_Decode, 193, 6, 90, // Opcode: STCL_OFFSET
+/* 437 */     MCD_OPC_Decode, 236, 14, 92, // Opcode: STCL_OFFSET
 /* 441 */     MCD_OPC_FilterValue, 5, 25, 0, 0, // Skip to: 471
 /* 446 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 462
 /* 451 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 462
-/* 458 */     MCD_OPC_Decode, 229, 4, 90, // Opcode: LDC2L_OFFSET
+/* 458 */     MCD_OPC_Decode, 190, 6, 92, // Opcode: LDC2L_OFFSET
 /* 462 */     MCD_OPC_CheckPredicate, 0, 170, 0, 0, // Skip to: 637
-/* 467 */     MCD_OPC_Decode, 237, 4, 90, // Opcode: LDCL_OFFSET
+/* 467 */     MCD_OPC_Decode, 198, 6, 92, // Opcode: LDCL_OFFSET
 /* 471 */     MCD_OPC_FilterValue, 6, 25, 0, 0, // Skip to: 501
 /* 476 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 492
 /* 481 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 492
-/* 488 */     MCD_OPC_Decode, 188, 6, 90, // Opcode: STC2L_PRE
+/* 488 */     MCD_OPC_Decode, 231, 14, 92, // Opcode: STC2L_PRE
 /* 492 */     MCD_OPC_CheckPredicate, 0, 140, 0, 0, // Skip to: 637
-/* 497 */     MCD_OPC_Decode, 196, 6, 90, // Opcode: STCL_PRE
+/* 497 */     MCD_OPC_Decode, 239, 14, 92, // Opcode: STCL_PRE
 /* 501 */     MCD_OPC_FilterValue, 7, 131, 0, 0, // Skip to: 637
 /* 506 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 522
 /* 511 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 522
-/* 518 */     MCD_OPC_Decode, 232, 4, 90, // Opcode: LDC2L_PRE
+/* 518 */     MCD_OPC_Decode, 193, 6, 92, // Opcode: LDC2L_PRE
 /* 522 */     MCD_OPC_CheckPredicate, 0, 110, 0, 0, // Skip to: 637
-/* 527 */     MCD_OPC_Decode, 240, 4, 90, // Opcode: LDCL_PRE
+/* 527 */     MCD_OPC_Decode, 201, 6, 92, // Opcode: LDCL_PRE
 /* 531 */     MCD_OPC_FilterValue, 14, 101, 0, 0, // Skip to: 637
 /* 536 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 539 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 569
 /* 544 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 560
 /* 549 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 560
-/* 556 */     MCD_OPC_Decode, 180, 4, 91, // Opcode: CDP2
+/* 556 */     MCD_OPC_Decode, 141, 6, 93, // Opcode: CDP2
 /* 560 */     MCD_OPC_CheckPredicate, 4, 72, 0, 0, // Skip to: 637
-/* 565 */     MCD_OPC_Decode, 179, 4, 92, // Opcode: CDP
+/* 565 */     MCD_OPC_Decode, 140, 6, 94, // Opcode: CDP
 /* 569 */     MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 637
 /* 574 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 577 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 607
 /* 582 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 598
 /* 587 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 598
-/* 594 */     MCD_OPC_Decode, 165, 5, 93, // Opcode: MCR2
+/* 594 */     MCD_OPC_Decode, 254, 6, 95, // Opcode: MCR2
 /* 598 */     MCD_OPC_CheckPredicate, 0, 34, 0, 0, // Skip to: 637
-/* 603 */     MCD_OPC_Decode, 164, 5, 94, // Opcode: MCR
+/* 603 */     MCD_OPC_Decode, 253, 6, 96, // Opcode: MCR
 /* 607 */     MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 637
 /* 612 */     MCD_OPC_CheckPredicate, 4, 11, 0, 0, // Skip to: 628
 /* 617 */     MCD_OPC_CheckField, 28, 4, 15, 4, 0, 0, // Skip to: 628
-/* 624 */     MCD_OPC_Decode, 179, 5, 95, // Opcode: MRC2
+/* 624 */     MCD_OPC_Decode, 140, 7, 97, // Opcode: MRC2
 /* 628 */     MCD_OPC_CheckPredicate, 0, 4, 0, 0, // Skip to: 637
-/* 633 */     MCD_OPC_Decode, 178, 5, 96, // Opcode: MRC
+/* 633 */     MCD_OPC_Decode, 139, 7, 98, // Opcode: MRC
 /* 637 */     MCD_OPC_Fail,
   0
 };
 
+static const uint8_t DecoderTableMVE32[] = {
+/* 0 */       MCD_OPC_ExtractField, 25, 3,  // Inst{27-25} ...
+/* 3 */       MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 139
+/* 8 */       MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 43
+/* 16 */      MCD_OPC_CheckPredicate, 22, 235, 98, 0, // Skip to: 25344
+/* 21 */      MCD_OPC_CheckField, 28, 4, 15, 228, 98, 0, // Skip to: 25344
+/* 28 */      MCD_OPC_CheckField, 11, 5, 29, 221, 98, 0, // Skip to: 25344
+/* 35 */      MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 1,
+/* 39 */      MCD_OPC_Decode, 139, 8, 99, // Opcode: MVE_VCTP8
+/* 43 */      MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 75
+/* 48 */      MCD_OPC_CheckPredicate, 22, 203, 98, 0, // Skip to: 25344
+/* 53 */      MCD_OPC_CheckField, 28, 4, 15, 196, 98, 0, // Skip to: 25344
+/* 60 */      MCD_OPC_CheckField, 11, 5, 29, 189, 98, 0, // Skip to: 25344
+/* 67 */      MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 1,
+/* 71 */      MCD_OPC_Decode, 136, 8, 99, // Opcode: MVE_VCTP16
+/* 75 */      MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 107
+/* 80 */      MCD_OPC_CheckPredicate, 22, 171, 98, 0, // Skip to: 25344
+/* 85 */      MCD_OPC_CheckField, 28, 4, 15, 164, 98, 0, // Skip to: 25344
+/* 92 */      MCD_OPC_CheckField, 11, 5, 29, 157, 98, 0, // Skip to: 25344
+/* 99 */      MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 1,
+/* 103 */     MCD_OPC_Decode, 137, 8, 99, // Opcode: MVE_VCTP32
+/* 107 */     MCD_OPC_FilterValue, 3, 144, 98, 0, // Skip to: 25344
+/* 112 */     MCD_OPC_CheckPredicate, 22, 139, 98, 0, // Skip to: 25344
+/* 117 */     MCD_OPC_CheckField, 28, 4, 15, 132, 98, 0, // Skip to: 25344
+/* 124 */     MCD_OPC_CheckField, 11, 5, 29, 125, 98, 0, // Skip to: 25344
+/* 131 */     MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 1,
+/* 135 */     MCD_OPC_Decode, 138, 8, 99, // Opcode: MVE_VCTP64
+/* 139 */     MCD_OPC_FilterValue, 5, 238, 1, 0, // Skip to: 638
+/* 144 */     MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 147 */     MCD_OPC_FilterValue, 13, 89, 0, 0, // Skip to: 241
+/* 152 */     MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 155 */     MCD_OPC_FilterValue, 5, 96, 98, 0, // Skip to: 25344
+/* 160 */     MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 163 */     MCD_OPC_FilterValue, 14, 88, 98, 0, // Skip to: 25344
+/* 168 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 171 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 192
+/* 176 */     MCD_OPC_CheckPredicate, 23, 39, 0, 0, // Skip to: 220
+/* 181 */     MCD_OPC_CheckField, 6, 3, 4, 32, 0, 0, // Skip to: 220
+/* 188 */     MCD_OPC_Decode, 159, 7, 100, // Opcode: MVE_LSLLr
+/* 192 */     MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 220
+/* 197 */     MCD_OPC_CheckPredicate, 23, 18, 0, 0, // Skip to: 220
+/* 202 */     MCD_OPC_CheckField, 8, 1, 1, 11, 0, 0, // Skip to: 220
+/* 209 */     MCD_OPC_CheckField, 6, 1, 0, 4, 0, 0, // Skip to: 220
+/* 216 */     MCD_OPC_Decode, 168, 7, 100, // Opcode: MVE_UQRSHLL
+/* 220 */     MCD_OPC_CheckPredicate, 23, 31, 98, 0, // Skip to: 25344
+/* 225 */     MCD_OPC_CheckField, 9, 3, 7, 24, 98, 0, // Skip to: 25344
+/* 232 */     MCD_OPC_SoftFail, 192, 1 /* 0xc0 */, 128, 2 /* 0x100 */,
+/* 237 */     MCD_OPC_Decode, 167, 7, 101, // Opcode: MVE_UQRSHL
+/* 241 */     MCD_OPC_FilterValue, 15, 73, 0, 0, // Skip to: 319
+/* 246 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 249 */     MCD_OPC_FilterValue, 1, 2, 98, 0, // Skip to: 25344
+/* 254 */     MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
+/* 257 */     MCD_OPC_FilterValue, 0, 250, 97, 0, // Skip to: 25344
+/* 262 */     MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 265 */     MCD_OPC_FilterValue, 5, 242, 97, 0, // Skip to: 25344
+/* 270 */     MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 273 */     MCD_OPC_FilterValue, 14, 234, 97, 0, // Skip to: 25344
+/* 278 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 294
+/* 283 */     MCD_OPC_CheckField, 9, 3, 7, 4, 0, 0, // Skip to: 294
+/* 290 */     MCD_OPC_Decode, 169, 7, 102, // Opcode: MVE_UQSHL
+/* 294 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 310
+/* 299 */     MCD_OPC_CheckField, 16, 1, 1, 4, 0, 0, // Skip to: 310
+/* 306 */     MCD_OPC_Decode, 170, 7, 103, // Opcode: MVE_UQSHLL
+/* 310 */     MCD_OPC_CheckPredicate, 23, 197, 97, 0, // Skip to: 25344
+/* 315 */     MCD_OPC_Decode, 158, 7, 103, // Opcode: MVE_LSLLi
+/* 319 */     MCD_OPC_FilterValue, 31, 73, 0, 0, // Skip to: 397
+/* 324 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 327 */     MCD_OPC_FilterValue, 1, 180, 97, 0, // Skip to: 25344
+/* 332 */     MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
+/* 335 */     MCD_OPC_FilterValue, 0, 172, 97, 0, // Skip to: 25344
+/* 340 */     MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 343 */     MCD_OPC_FilterValue, 5, 164, 97, 0, // Skip to: 25344
+/* 348 */     MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 351 */     MCD_OPC_FilterValue, 14, 156, 97, 0, // Skip to: 25344
+/* 356 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 372
+/* 361 */     MCD_OPC_CheckField, 9, 3, 7, 4, 0, 0, // Skip to: 372
+/* 368 */     MCD_OPC_Decode, 171, 7, 102, // Opcode: MVE_URSHR
+/* 372 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 388
+/* 377 */     MCD_OPC_CheckField, 16, 1, 1, 4, 0, 0, // Skip to: 388
+/* 384 */     MCD_OPC_Decode, 172, 7, 103, // Opcode: MVE_URSHRL
+/* 388 */     MCD_OPC_CheckPredicate, 23, 119, 97, 0, // Skip to: 25344
+/* 393 */     MCD_OPC_Decode, 160, 7, 103, // Opcode: MVE_LSRL
+/* 397 */     MCD_OPC_FilterValue, 45, 89, 0, 0, // Skip to: 491
+/* 402 */     MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 405 */     MCD_OPC_FilterValue, 5, 102, 97, 0, // Skip to: 25344
+/* 410 */     MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 413 */     MCD_OPC_FilterValue, 14, 94, 97, 0, // Skip to: 25344
+/* 418 */     MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 421 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 442
+/* 426 */     MCD_OPC_CheckPredicate, 23, 39, 0, 0, // Skip to: 470
+/* 431 */     MCD_OPC_CheckField, 6, 3, 4, 32, 0, 0, // Skip to: 470
+/* 438 */     MCD_OPC_Decode, 151, 7, 100, // Opcode: MVE_ASRLr
+/* 442 */     MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 470
+/* 447 */     MCD_OPC_CheckPredicate, 23, 18, 0, 0, // Skip to: 470
+/* 452 */     MCD_OPC_CheckField, 8, 1, 1, 11, 0, 0, // Skip to: 470
+/* 459 */     MCD_OPC_CheckField, 6, 1, 0, 4, 0, 0, // Skip to: 470
+/* 466 */     MCD_OPC_Decode, 162, 7, 100, // Opcode: MVE_SQRSHRL
+/* 470 */     MCD_OPC_CheckPredicate, 23, 37, 97, 0, // Skip to: 25344
+/* 475 */     MCD_OPC_CheckField, 9, 3, 7, 30, 97, 0, // Skip to: 25344
+/* 482 */     MCD_OPC_SoftFail, 192, 1 /* 0xc0 */, 128, 2 /* 0x100 */,
+/* 487 */     MCD_OPC_Decode, 161, 7, 101, // Opcode: MVE_SQRSHR
+/* 491 */     MCD_OPC_FilterValue, 47, 73, 0, 0, // Skip to: 569
+/* 496 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 499 */     MCD_OPC_FilterValue, 1, 8, 97, 0, // Skip to: 25344
+/* 504 */     MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
+/* 507 */     MCD_OPC_FilterValue, 0, 0, 97, 0, // Skip to: 25344
+/* 512 */     MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 515 */     MCD_OPC_FilterValue, 5, 248, 96, 0, // Skip to: 25344
+/* 520 */     MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 523 */     MCD_OPC_FilterValue, 14, 240, 96, 0, // Skip to: 25344
+/* 528 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 544
+/* 533 */     MCD_OPC_CheckField, 9, 3, 7, 4, 0, 0, // Skip to: 544
+/* 540 */     MCD_OPC_Decode, 165, 7, 102, // Opcode: MVE_SRSHR
+/* 544 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 560
+/* 549 */     MCD_OPC_CheckField, 16, 1, 1, 4, 0, 0, // Skip to: 560
+/* 556 */     MCD_OPC_Decode, 166, 7, 103, // Opcode: MVE_SRSHRL
+/* 560 */     MCD_OPC_CheckPredicate, 23, 203, 96, 0, // Skip to: 25344
+/* 565 */     MCD_OPC_Decode, 150, 7, 103, // Opcode: MVE_ASRLi
+/* 569 */     MCD_OPC_FilterValue, 63, 194, 96, 0, // Skip to: 25344
+/* 574 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 577 */     MCD_OPC_FilterValue, 1, 186, 96, 0, // Skip to: 25344
+/* 582 */     MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
+/* 585 */     MCD_OPC_FilterValue, 0, 178, 96, 0, // Skip to: 25344
+/* 590 */     MCD_OPC_ExtractField, 20, 5,  // Inst{24-20} ...
+/* 593 */     MCD_OPC_FilterValue, 5, 170, 96, 0, // Skip to: 25344
+/* 598 */     MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 601 */     MCD_OPC_FilterValue, 14, 162, 96, 0, // Skip to: 25344
+/* 606 */     MCD_OPC_CheckPredicate, 23, 11, 0, 0, // Skip to: 622
+/* 611 */     MCD_OPC_CheckField, 9, 3, 7, 4, 0, 0, // Skip to: 622
+/* 618 */     MCD_OPC_Decode, 163, 7, 102, // Opcode: MVE_SQSHL
+/* 622 */     MCD_OPC_CheckPredicate, 23, 141, 96, 0, // Skip to: 25344
+/* 627 */     MCD_OPC_CheckField, 16, 1, 1, 134, 96, 0, // Skip to: 25344
+/* 634 */     MCD_OPC_Decode, 164, 7, 103, // Opcode: MVE_SQSHLL
+/* 638 */     MCD_OPC_FilterValue, 6, 2, 19, 0, // Skip to: 5509
+/* 643 */     MCD_OPC_ExtractField, 8, 5,  // Inst{12-8} ...
+/* 646 */     MCD_OPC_FilterValue, 8, 213, 0, 0, // Skip to: 864
+/* 651 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 654 */     MCD_OPC_FilterValue, 0, 51, 0, 0, // Skip to: 710
+/* 659 */     MCD_OPC_CheckPredicate, 24, 104, 96, 0, // Skip to: 25344
+/* 664 */     MCD_OPC_CheckField, 28, 4, 15, 97, 96, 0, // Skip to: 25344
+/* 671 */     MCD_OPC_CheckField, 23, 1, 1, 90, 96, 0, // Skip to: 25344
+/* 678 */     MCD_OPC_CheckField, 16, 1, 0, 83, 96, 0, // Skip to: 25344
+/* 685 */     MCD_OPC_CheckField, 6, 1, 1, 76, 96, 0, // Skip to: 25344
+/* 692 */     MCD_OPC_CheckField, 4, 1, 0, 69, 96, 0, // Skip to: 25344
+/* 699 */     MCD_OPC_CheckField, 0, 1, 0, 62, 96, 0, // Skip to: 25344
+/* 706 */     MCD_OPC_Decode, 227, 7, 104, // Opcode: MVE_VCADDf16
+/* 710 */     MCD_OPC_FilterValue, 1, 51, 0, 0, // Skip to: 766
+/* 715 */     MCD_OPC_CheckPredicate, 24, 48, 96, 0, // Skip to: 25344
+/* 720 */     MCD_OPC_CheckField, 28, 4, 15, 41, 96, 0, // Skip to: 25344
+/* 727 */     MCD_OPC_CheckField, 23, 1, 1, 34, 96, 0, // Skip to: 25344
+/* 734 */     MCD_OPC_CheckField, 16, 1, 0, 27, 96, 0, // Skip to: 25344
+/* 741 */     MCD_OPC_CheckField, 6, 1, 1, 20, 96, 0, // Skip to: 25344
+/* 748 */     MCD_OPC_CheckField, 4, 1, 0, 13, 96, 0, // Skip to: 25344
+/* 755 */     MCD_OPC_CheckField, 0, 1, 0, 6, 96, 0, // Skip to: 25344
+/* 762 */     MCD_OPC_Decode, 228, 7, 104, // Opcode: MVE_VCADDf32
+/* 766 */     MCD_OPC_FilterValue, 2, 44, 0, 0, // Skip to: 815
+/* 771 */     MCD_OPC_CheckPredicate, 24, 248, 95, 0, // Skip to: 25344
+/* 776 */     MCD_OPC_CheckField, 28, 4, 15, 241, 95, 0, // Skip to: 25344
+/* 783 */     MCD_OPC_CheckField, 16, 1, 0, 234, 95, 0, // Skip to: 25344
+/* 790 */     MCD_OPC_CheckField, 6, 1, 1, 227, 95, 0, // Skip to: 25344
+/* 797 */     MCD_OPC_CheckField, 4, 1, 0, 220, 95, 0, // Skip to: 25344
+/* 804 */     MCD_OPC_CheckField, 0, 1, 0, 213, 95, 0, // Skip to: 25344
+/* 811 */     MCD_OPC_Decode, 238, 7, 105, // Opcode: MVE_VCMLAf16
+/* 815 */     MCD_OPC_FilterValue, 3, 204, 95, 0, // Skip to: 25344
+/* 820 */     MCD_OPC_CheckPredicate, 24, 199, 95, 0, // Skip to: 25344
+/* 825 */     MCD_OPC_CheckField, 28, 4, 15, 192, 95, 0, // Skip to: 25344
+/* 832 */     MCD_OPC_CheckField, 16, 1, 0, 185, 95, 0, // Skip to: 25344
+/* 839 */     MCD_OPC_CheckField, 6, 1, 1, 178, 95, 0, // Skip to: 25344
+/* 846 */     MCD_OPC_CheckField, 4, 1, 0, 171, 95, 0, // Skip to: 25344
+/* 853 */     MCD_OPC_CheckField, 0, 1, 0, 164, 95, 0, // Skip to: 25344
+/* 860 */     MCD_OPC_Decode, 239, 7, 105, // Opcode: MVE_VCMLAf32
+/* 864 */     MCD_OPC_FilterValue, 14, 135, 2, 0, // Skip to: 1516
+/* 869 */     MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
+/* 872 */     MCD_OPC_FilterValue, 0, 188, 0, 0, // Skip to: 1065
+/* 877 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 880 */     MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 922
+/* 885 */     MCD_OPC_CheckPredicate, 22, 134, 95, 0, // Skip to: 25344
+/* 890 */     MCD_OPC_CheckField, 28, 4, 14, 127, 95, 0, // Skip to: 25344
+/* 897 */     MCD_OPC_CheckField, 23, 2, 1, 120, 95, 0, // Skip to: 25344
+/* 904 */     MCD_OPC_CheckField, 4, 3, 0, 113, 95, 0, // Skip to: 25344
+/* 911 */     MCD_OPC_CheckField, 0, 1, 0, 106, 95, 0, // Skip to: 25344
+/* 918 */     MCD_OPC_Decode, 184, 13, 106, // Opcode: MVE_VSTRB8_rq
+/* 922 */     MCD_OPC_FilterValue, 1, 97, 95, 0, // Skip to: 25344
+/* 927 */     MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 930 */     MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 1037
+/* 935 */     MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 938 */     MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 1002
+/* 943 */     MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 946 */     MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 974
+/* 951 */     MCD_OPC_CheckPredicate, 22, 68, 95, 0, // Skip to: 25344
+/* 956 */     MCD_OPC_CheckField, 28, 4, 14, 61, 95, 0, // Skip to: 25344
+/* 963 */     MCD_OPC_CheckField, 23, 1, 1, 54, 95, 0, // Skip to: 25344
+/* 970 */     MCD_OPC_Decode, 179, 13, 106, // Opcode: MVE_VSTRB16_rq
+/* 974 */     MCD_OPC_FilterValue, 1, 45, 95, 0, // Skip to: 25344
+/* 979 */     MCD_OPC_CheckPredicate, 22, 40, 95, 0, // Skip to: 25344
+/* 984 */     MCD_OPC_CheckField, 28, 4, 14, 33, 95, 0, // Skip to: 25344
+/* 991 */     MCD_OPC_CheckField, 23, 1, 1, 26, 95, 0, // Skip to: 25344
+/* 998 */     MCD_OPC_Decode, 193, 13, 106, // Opcode: MVE_VSTRH16_rq_u
+/* 1002 */    MCD_OPC_FilterValue, 1, 17, 95, 0, // Skip to: 25344
+/* 1007 */    MCD_OPC_CheckPredicate, 22, 12, 95, 0, // Skip to: 25344
+/* 1012 */    MCD_OPC_CheckField, 28, 4, 14, 5, 95, 0, // Skip to: 25344
+/* 1019 */    MCD_OPC_CheckField, 23, 1, 1, 254, 94, 0, // Skip to: 25344
+/* 1026 */    MCD_OPC_CheckField, 4, 3, 1, 247, 94, 0, // Skip to: 25344
+/* 1033 */    MCD_OPC_Decode, 192, 13, 106, // Opcode: MVE_VSTRH16_rq
+/* 1037 */    MCD_OPC_FilterValue, 1, 238, 94, 0, // Skip to: 25344
+/* 1042 */    MCD_OPC_CheckPredicate, 22, 233, 94, 0, // Skip to: 25344
+/* 1047 */    MCD_OPC_CheckField, 28, 4, 14, 226, 94, 0, // Skip to: 25344
+/* 1054 */    MCD_OPC_CheckField, 19, 1, 0, 219, 94, 0, // Skip to: 25344
+/* 1061 */    MCD_OPC_Decode, 176, 13, 107, // Opcode: MVE_VSTRB16
+/* 1065 */    MCD_OPC_FilterValue, 1, 232, 0, 0, // Skip to: 1302
+/* 1070 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1073 */    MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 1115
+/* 1078 */    MCD_OPC_CheckPredicate, 22, 197, 94, 0, // Skip to: 25344
+/* 1083 */    MCD_OPC_CheckField, 28, 4, 15, 190, 94, 0, // Skip to: 25344
+/* 1090 */    MCD_OPC_CheckField, 23, 2, 1, 183, 94, 0, // Skip to: 25344
+/* 1097 */    MCD_OPC_CheckField, 4, 3, 0, 176, 94, 0, // Skip to: 25344
+/* 1104 */    MCD_OPC_CheckField, 0, 1, 0, 169, 94, 0, // Skip to: 25344
+/* 1111 */    MCD_OPC_Decode, 154, 9, 106, // Opcode: MVE_VLDRBU8_rq
+/* 1115 */    MCD_OPC_FilterValue, 1, 160, 94, 0, // Skip to: 25344
+/* 1120 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 1123 */    MCD_OPC_FilterValue, 0, 124, 0, 0, // Skip to: 1252
+/* 1128 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 1131 */    MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 1217
+/* 1136 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 1139 */    MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 1189
+/* 1144 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 1147 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 1168
+/* 1152 */    MCD_OPC_CheckPredicate, 22, 123, 94, 0, // Skip to: 25344
+/* 1157 */    MCD_OPC_CheckField, 23, 1, 1, 116, 94, 0, // Skip to: 25344
+/* 1164 */    MCD_OPC_Decode, 138, 9, 106, // Opcode: MVE_VLDRBS16_rq
+/* 1168 */    MCD_OPC_FilterValue, 15, 107, 94, 0, // Skip to: 25344
+/* 1173 */    MCD_OPC_CheckPredicate, 22, 102, 94, 0, // Skip to: 25344
+/* 1178 */    MCD_OPC_CheckField, 23, 1, 1, 95, 94, 0, // Skip to: 25344
+/* 1185 */    MCD_OPC_Decode, 146, 9, 106, // Opcode: MVE_VLDRBU16_rq
+/* 1189 */    MCD_OPC_FilterValue, 1, 86, 94, 0, // Skip to: 25344
+/* 1194 */    MCD_OPC_CheckPredicate, 22, 81, 94, 0, // Skip to: 25344
+/* 1199 */    MCD_OPC_CheckField, 28, 4, 15, 74, 94, 0, // Skip to: 25344
+/* 1206 */    MCD_OPC_CheckField, 23, 1, 1, 67, 94, 0, // Skip to: 25344
+/* 1213 */    MCD_OPC_Decode, 168, 9, 106, // Opcode: MVE_VLDRHU16_rq_u
+/* 1217 */    MCD_OPC_FilterValue, 1, 58, 94, 0, // Skip to: 25344
+/* 1222 */    MCD_OPC_CheckPredicate, 22, 53, 94, 0, // Skip to: 25344
+/* 1227 */    MCD_OPC_CheckField, 28, 4, 15, 46, 94, 0, // Skip to: 25344
+/* 1234 */    MCD_OPC_CheckField, 23, 1, 1, 39, 94, 0, // Skip to: 25344
+/* 1241 */    MCD_OPC_CheckField, 4, 3, 1, 32, 94, 0, // Skip to: 25344
+/* 1248 */    MCD_OPC_Decode, 167, 9, 106, // Opcode: MVE_VLDRHU16_rq
+/* 1252 */    MCD_OPC_FilterValue, 1, 23, 94, 0, // Skip to: 25344
+/* 1257 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 1260 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 1281
+/* 1265 */    MCD_OPC_CheckPredicate, 22, 10, 94, 0, // Skip to: 25344
+/* 1270 */    MCD_OPC_CheckField, 19, 1, 0, 3, 94, 0, // Skip to: 25344
+/* 1277 */    MCD_OPC_Decode, 135, 9, 107, // Opcode: MVE_VLDRBS16
+/* 1281 */    MCD_OPC_FilterValue, 15, 250, 93, 0, // Skip to: 25344
+/* 1286 */    MCD_OPC_CheckPredicate, 22, 245, 93, 0, // Skip to: 25344
+/* 1291 */    MCD_OPC_CheckField, 19, 1, 0, 238, 93, 0, // Skip to: 25344
+/* 1298 */    MCD_OPC_Decode, 143, 9, 107, // Opcode: MVE_VLDRBU16
+/* 1302 */    MCD_OPC_FilterValue, 2, 73, 0, 0, // Skip to: 1380
+/* 1307 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 1310 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 1345
+/* 1315 */    MCD_OPC_CheckPredicate, 22, 216, 93, 0, // Skip to: 25344
+/* 1320 */    MCD_OPC_CheckField, 28, 4, 14, 209, 93, 0, // Skip to: 25344
+/* 1327 */    MCD_OPC_CheckField, 19, 1, 0, 202, 93, 0, // Skip to: 25344
+/* 1334 */    MCD_OPC_CheckField, 7, 1, 1, 195, 93, 0, // Skip to: 25344
+/* 1341 */    MCD_OPC_Decode, 177, 13, 108, // Opcode: MVE_VSTRB16_post
+/* 1345 */    MCD_OPC_FilterValue, 1, 186, 93, 0, // Skip to: 25344
+/* 1350 */    MCD_OPC_CheckPredicate, 22, 181, 93, 0, // Skip to: 25344
+/* 1355 */    MCD_OPC_CheckField, 28, 4, 14, 174, 93, 0, // Skip to: 25344
+/* 1362 */    MCD_OPC_CheckField, 19, 1, 0, 167, 93, 0, // Skip to: 25344
+/* 1369 */    MCD_OPC_CheckField, 7, 1, 1, 160, 93, 0, // Skip to: 25344
+/* 1376 */    MCD_OPC_Decode, 178, 13, 109, // Opcode: MVE_VSTRB16_pre
+/* 1380 */    MCD_OPC_FilterValue, 3, 151, 93, 0, // Skip to: 25344
+/* 1385 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 1388 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 1452
+/* 1393 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 1396 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 1424
+/* 1401 */    MCD_OPC_CheckPredicate, 22, 130, 93, 0, // Skip to: 25344
+/* 1406 */    MCD_OPC_CheckField, 19, 1, 0, 123, 93, 0, // Skip to: 25344
+/* 1413 */    MCD_OPC_CheckField, 7, 1, 1, 116, 93, 0, // Skip to: 25344
+/* 1420 */    MCD_OPC_Decode, 136, 9, 108, // Opcode: MVE_VLDRBS16_post
+/* 1424 */    MCD_OPC_FilterValue, 15, 107, 93, 0, // Skip to: 25344
+/* 1429 */    MCD_OPC_CheckPredicate, 22, 102, 93, 0, // Skip to: 25344
+/* 1434 */    MCD_OPC_CheckField, 19, 1, 0, 95, 93, 0, // Skip to: 25344
+/* 1441 */    MCD_OPC_CheckField, 7, 1, 1, 88, 93, 0, // Skip to: 25344
+/* 1448 */    MCD_OPC_Decode, 144, 9, 108, // Opcode: MVE_VLDRBU16_post
+/* 1452 */    MCD_OPC_FilterValue, 1, 79, 93, 0, // Skip to: 25344
+/* 1457 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 1460 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 1488
+/* 1465 */    MCD_OPC_CheckPredicate, 22, 66, 93, 0, // Skip to: 25344
+/* 1470 */    MCD_OPC_CheckField, 19, 1, 0, 59, 93, 0, // Skip to: 25344
+/* 1477 */    MCD_OPC_CheckField, 7, 1, 1, 52, 93, 0, // Skip to: 25344
+/* 1484 */    MCD_OPC_Decode, 137, 9, 109, // Opcode: MVE_VLDRBS16_pre
+/* 1488 */    MCD_OPC_FilterValue, 15, 43, 93, 0, // Skip to: 25344
+/* 1493 */    MCD_OPC_CheckPredicate, 22, 38, 93, 0, // Skip to: 25344
+/* 1498 */    MCD_OPC_CheckField, 19, 1, 0, 31, 93, 0, // Skip to: 25344
+/* 1505 */    MCD_OPC_CheckField, 7, 1, 1, 24, 93, 0, // Skip to: 25344
+/* 1512 */    MCD_OPC_Decode, 145, 9, 109, // Opcode: MVE_VLDRBU16_pre
+/* 1516 */    MCD_OPC_FilterValue, 15, 44, 5, 0, // Skip to: 2845
+/* 1521 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 1524 */    MCD_OPC_FilterValue, 0, 119, 1, 0, // Skip to: 1904
+/* 1529 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1532 */    MCD_OPC_FilterValue, 0, 33, 1, 0, // Skip to: 1826
+/* 1537 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 1540 */    MCD_OPC_FilterValue, 0, 217, 0, 0, // Skip to: 1762
+/* 1545 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
+/* 1548 */    MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 1684
+/* 1553 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1556 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1577
+/* 1561 */    MCD_OPC_CheckPredicate, 23, 226, 92, 0, // Skip to: 25344
+/* 1566 */    MCD_OPC_CheckField, 28, 4, 14, 219, 92, 0, // Skip to: 25344
+/* 1573 */    MCD_OPC_Decode, 179, 10, 110, // Opcode: MVE_VMOV_rr_q
+/* 1577 */    MCD_OPC_FilterValue, 1, 210, 92, 0, // Skip to: 25344
+/* 1582 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 1585 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 1649
+/* 1590 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1593 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1621
+/* 1598 */    MCD_OPC_CheckPredicate, 22, 189, 92, 0, // Skip to: 25344
+/* 1603 */    MCD_OPC_CheckField, 28, 4, 14, 182, 92, 0, // Skip to: 25344
+/* 1610 */    MCD_OPC_CheckField, 22, 1, 0, 175, 92, 0, // Skip to: 25344
+/* 1617 */    MCD_OPC_Decode, 183, 13, 106, // Opcode: MVE_VSTRB32_rq
+/* 1621 */    MCD_OPC_FilterValue, 1, 166, 92, 0, // Skip to: 25344
+/* 1626 */    MCD_OPC_CheckPredicate, 22, 161, 92, 0, // Skip to: 25344
+/* 1631 */    MCD_OPC_CheckField, 28, 4, 14, 154, 92, 0, // Skip to: 25344
+/* 1638 */    MCD_OPC_CheckField, 22, 1, 0, 147, 92, 0, // Skip to: 25344
+/* 1645 */    MCD_OPC_Decode, 198, 13, 106, // Opcode: MVE_VSTRH32_rq_u
+/* 1649 */    MCD_OPC_FilterValue, 1, 138, 92, 0, // Skip to: 25344
+/* 1654 */    MCD_OPC_CheckPredicate, 22, 133, 92, 0, // Skip to: 25344
+/* 1659 */    MCD_OPC_CheckField, 28, 4, 14, 126, 92, 0, // Skip to: 25344
+/* 1666 */    MCD_OPC_CheckField, 22, 1, 0, 119, 92, 0, // Skip to: 25344
+/* 1673 */    MCD_OPC_CheckField, 4, 1, 1, 112, 92, 0, // Skip to: 25344
+/* 1680 */    MCD_OPC_Decode, 197, 13, 106, // Opcode: MVE_VSTRH32_rq
+/* 1684 */    MCD_OPC_FilterValue, 2, 103, 92, 0, // Skip to: 25344
+/* 1689 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 1692 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 1727
+/* 1697 */    MCD_OPC_CheckPredicate, 22, 90, 92, 0, // Skip to: 25344
+/* 1702 */    MCD_OPC_CheckField, 28, 4, 14, 83, 92, 0, // Skip to: 25344
+/* 1709 */    MCD_OPC_CheckField, 22, 2, 2, 76, 92, 0, // Skip to: 25344
+/* 1716 */    MCD_OPC_CheckField, 4, 1, 0, 69, 92, 0, // Skip to: 25344
+/* 1723 */    MCD_OPC_Decode, 205, 13, 106, // Opcode: MVE_VSTRW32_rq_u
+/* 1727 */    MCD_OPC_FilterValue, 1, 60, 92, 0, // Skip to: 25344
+/* 1732 */    MCD_OPC_CheckPredicate, 22, 55, 92, 0, // Skip to: 25344
+/* 1737 */    MCD_OPC_CheckField, 28, 4, 14, 48, 92, 0, // Skip to: 25344
+/* 1744 */    MCD_OPC_CheckField, 22, 2, 2, 41, 92, 0, // Skip to: 25344
+/* 1751 */    MCD_OPC_CheckField, 4, 1, 0, 34, 92, 0, // Skip to: 25344
+/* 1758 */    MCD_OPC_Decode, 204, 13, 106, // Opcode: MVE_VSTRW32_rq
+/* 1762 */    MCD_OPC_FilterValue, 1, 25, 92, 0, // Skip to: 25344
+/* 1767 */    MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 1770 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 1798
+/* 1775 */    MCD_OPC_CheckPredicate, 22, 12, 92, 0, // Skip to: 25344
+/* 1780 */    MCD_OPC_CheckField, 28, 4, 14, 5, 92, 0, // Skip to: 25344
+/* 1787 */    MCD_OPC_CheckField, 22, 1, 0, 254, 91, 0, // Skip to: 25344
+/* 1794 */    MCD_OPC_Decode, 180, 13, 107, // Opcode: MVE_VSTRB32
+/* 1798 */    MCD_OPC_FilterValue, 1, 245, 91, 0, // Skip to: 25344
+/* 1803 */    MCD_OPC_CheckPredicate, 22, 240, 91, 0, // Skip to: 25344
+/* 1808 */    MCD_OPC_CheckField, 28, 4, 14, 233, 91, 0, // Skip to: 25344
+/* 1815 */    MCD_OPC_CheckField, 22, 1, 0, 226, 91, 0, // Skip to: 25344
+/* 1822 */    MCD_OPC_Decode, 194, 13, 111, // Opcode: MVE_VSTRH32
+/* 1826 */    MCD_OPC_FilterValue, 1, 217, 91, 0, // Skip to: 25344
+/* 1831 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 1834 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 1869
+/* 1839 */    MCD_OPC_CheckPredicate, 22, 204, 91, 0, // Skip to: 25344
+/* 1844 */    MCD_OPC_CheckField, 28, 4, 14, 197, 91, 0, // Skip to: 25344
+/* 1851 */    MCD_OPC_CheckField, 22, 3, 2, 190, 91, 0, // Skip to: 25344
+/* 1858 */    MCD_OPC_CheckField, 4, 3, 5, 183, 91, 0, // Skip to: 25344
+/* 1865 */    MCD_OPC_Decode, 191, 13, 106, // Opcode: MVE_VSTRD64_rq_u
+/* 1869 */    MCD_OPC_FilterValue, 1, 174, 91, 0, // Skip to: 25344
+/* 1874 */    MCD_OPC_CheckPredicate, 22, 169, 91, 0, // Skip to: 25344
+/* 1879 */    MCD_OPC_CheckField, 28, 4, 14, 162, 91, 0, // Skip to: 25344
+/* 1886 */    MCD_OPC_CheckField, 22, 3, 2, 155, 91, 0, // Skip to: 25344
+/* 1893 */    MCD_OPC_CheckField, 4, 3, 5, 148, 91, 0, // Skip to: 25344
+/* 1900 */    MCD_OPC_Decode, 190, 13, 106, // Opcode: MVE_VSTRD64_rq
+/* 1904 */    MCD_OPC_FilterValue, 1, 236, 1, 0, // Skip to: 2401
+/* 1909 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1912 */    MCD_OPC_FilterValue, 0, 150, 1, 0, // Skip to: 2323
+/* 1917 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 1920 */    MCD_OPC_FilterValue, 0, 34, 1, 0, // Skip to: 2215
+/* 1925 */    MCD_OPC_ExtractField, 5, 2,  // Inst{6-5} ...
+/* 1928 */    MCD_OPC_FilterValue, 0, 204, 0, 0, // Skip to: 2137
+/* 1933 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1936 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1957
+/* 1941 */    MCD_OPC_CheckPredicate, 23, 102, 91, 0, // Skip to: 25344
+/* 1946 */    MCD_OPC_CheckField, 28, 4, 14, 95, 91, 0, // Skip to: 25344
+/* 1953 */    MCD_OPC_Decode, 178, 10, 112, // Opcode: MVE_VMOV_q_rr
+/* 1957 */    MCD_OPC_FilterValue, 1, 86, 91, 0, // Skip to: 25344
+/* 1962 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 1965 */    MCD_OPC_FilterValue, 0, 103, 0, 0, // Skip to: 2073
+/* 1970 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1973 */    MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2023
+/* 1978 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 1981 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2002
+/* 1986 */    MCD_OPC_CheckPredicate, 22, 57, 91, 0, // Skip to: 25344
+/* 1991 */    MCD_OPC_CheckField, 22, 1, 0, 50, 91, 0, // Skip to: 25344
+/* 1998 */    MCD_OPC_Decode, 142, 9, 106, // Opcode: MVE_VLDRBS32_rq
+/* 2002 */    MCD_OPC_FilterValue, 15, 41, 91, 0, // Skip to: 25344
+/* 2007 */    MCD_OPC_CheckPredicate, 22, 36, 91, 0, // Skip to: 25344
+/* 2012 */    MCD_OPC_CheckField, 22, 1, 0, 29, 91, 0, // Skip to: 25344
+/* 2019 */    MCD_OPC_Decode, 150, 9, 106, // Opcode: MVE_VLDRBU32_rq
+/* 2023 */    MCD_OPC_FilterValue, 1, 20, 91, 0, // Skip to: 25344
+/* 2028 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2031 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2052
+/* 2036 */    MCD_OPC_CheckPredicate, 22, 7, 91, 0, // Skip to: 25344
+/* 2041 */    MCD_OPC_CheckField, 22, 1, 0, 0, 91, 0, // Skip to: 25344
+/* 2048 */    MCD_OPC_Decode, 163, 9, 106, // Opcode: MVE_VLDRHS32_rq_u
+/* 2052 */    MCD_OPC_FilterValue, 15, 247, 90, 0, // Skip to: 25344
+/* 2057 */    MCD_OPC_CheckPredicate, 22, 242, 90, 0, // Skip to: 25344
+/* 2062 */    MCD_OPC_CheckField, 22, 1, 0, 235, 90, 0, // Skip to: 25344
+/* 2069 */    MCD_OPC_Decode, 173, 9, 106, // Opcode: MVE_VLDRHU32_rq_u
+/* 2073 */    MCD_OPC_FilterValue, 1, 226, 90, 0, // Skip to: 25344
+/* 2078 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2081 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 2109
+/* 2086 */    MCD_OPC_CheckPredicate, 22, 213, 90, 0, // Skip to: 25344
+/* 2091 */    MCD_OPC_CheckField, 22, 1, 0, 206, 90, 0, // Skip to: 25344
+/* 2098 */    MCD_OPC_CheckField, 4, 1, 1, 199, 90, 0, // Skip to: 25344
+/* 2105 */    MCD_OPC_Decode, 162, 9, 106, // Opcode: MVE_VLDRHS32_rq
+/* 2109 */    MCD_OPC_FilterValue, 15, 190, 90, 0, // Skip to: 25344
+/* 2114 */    MCD_OPC_CheckPredicate, 22, 185, 90, 0, // Skip to: 25344
+/* 2119 */    MCD_OPC_CheckField, 22, 1, 0, 178, 90, 0, // Skip to: 25344
+/* 2126 */    MCD_OPC_CheckField, 4, 1, 1, 171, 90, 0, // Skip to: 25344
+/* 2133 */    MCD_OPC_Decode, 172, 9, 106, // Opcode: MVE_VLDRHU32_rq
+/* 2137 */    MCD_OPC_FilterValue, 2, 162, 90, 0, // Skip to: 25344
+/* 2142 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 2145 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 2180
+/* 2150 */    MCD_OPC_CheckPredicate, 22, 149, 90, 0, // Skip to: 25344
+/* 2155 */    MCD_OPC_CheckField, 28, 4, 15, 142, 90, 0, // Skip to: 25344
+/* 2162 */    MCD_OPC_CheckField, 22, 2, 2, 135, 90, 0, // Skip to: 25344
+/* 2169 */    MCD_OPC_CheckField, 4, 1, 0, 128, 90, 0, // Skip to: 25344
+/* 2176 */    MCD_OPC_Decode, 180, 9, 106, // Opcode: MVE_VLDRWU32_rq_u
+/* 2180 */    MCD_OPC_FilterValue, 1, 119, 90, 0, // Skip to: 25344
+/* 2185 */    MCD_OPC_CheckPredicate, 22, 114, 90, 0, // Skip to: 25344
+/* 2190 */    MCD_OPC_CheckField, 28, 4, 15, 107, 90, 0, // Skip to: 25344
+/* 2197 */    MCD_OPC_CheckField, 22, 2, 2, 100, 90, 0, // Skip to: 25344
+/* 2204 */    MCD_OPC_CheckField, 4, 1, 0, 93, 90, 0, // Skip to: 25344
+/* 2211 */    MCD_OPC_Decode, 179, 9, 106, // Opcode: MVE_VLDRWU32_rq
+/* 2215 */    MCD_OPC_FilterValue, 1, 84, 90, 0, // Skip to: 25344
+/* 2220 */    MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 2223 */    MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 2273
+/* 2228 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2231 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2252
+/* 2236 */    MCD_OPC_CheckPredicate, 22, 63, 90, 0, // Skip to: 25344
+/* 2241 */    MCD_OPC_CheckField, 22, 1, 0, 56, 90, 0, // Skip to: 25344
+/* 2248 */    MCD_OPC_Decode, 139, 9, 107, // Opcode: MVE_VLDRBS32
+/* 2252 */    MCD_OPC_FilterValue, 15, 47, 90, 0, // Skip to: 25344
+/* 2257 */    MCD_OPC_CheckPredicate, 22, 42, 90, 0, // Skip to: 25344
+/* 2262 */    MCD_OPC_CheckField, 22, 1, 0, 35, 90, 0, // Skip to: 25344
+/* 2269 */    MCD_OPC_Decode, 147, 9, 107, // Opcode: MVE_VLDRBU32
+/* 2273 */    MCD_OPC_FilterValue, 1, 26, 90, 0, // Skip to: 25344
+/* 2278 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2281 */    MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 2302
+/* 2286 */    MCD_OPC_CheckPredicate, 22, 13, 90, 0, // Skip to: 25344
+/* 2291 */    MCD_OPC_CheckField, 22, 1, 0, 6, 90, 0, // Skip to: 25344
+/* 2298 */    MCD_OPC_Decode, 159, 9, 111, // Opcode: MVE_VLDRHS32
+/* 2302 */    MCD_OPC_FilterValue, 15, 253, 89, 0, // Skip to: 25344
+/* 2307 */    MCD_OPC_CheckPredicate, 22, 248, 89, 0, // Skip to: 25344
+/* 2312 */    MCD_OPC_CheckField, 22, 1, 0, 241, 89, 0, // Skip to: 25344
+/* 2319 */    MCD_OPC_Decode, 169, 9, 111, // Opcode: MVE_VLDRHU32
+/* 2323 */    MCD_OPC_FilterValue, 1, 232, 89, 0, // Skip to: 25344
+/* 2328 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 2331 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 2366
+/* 2336 */    MCD_OPC_CheckPredicate, 22, 219, 89, 0, // Skip to: 25344
+/* 2341 */    MCD_OPC_CheckField, 28, 4, 15, 212, 89, 0, // Skip to: 25344
+/* 2348 */    MCD_OPC_CheckField, 22, 3, 2, 205, 89, 0, // Skip to: 25344
+/* 2355 */    MCD_OPC_CheckField, 4, 3, 5, 198, 89, 0, // Skip to: 25344
+/* 2362 */    MCD_OPC_Decode, 158, 9, 106, // Opcode: MVE_VLDRDU64_rq_u
+/* 2366 */    MCD_OPC_FilterValue, 1, 189, 89, 0, // Skip to: 25344
+/* 2371 */    MCD_OPC_CheckPredicate, 22, 184, 89, 0, // Skip to: 25344
+/* 2376 */    MCD_OPC_CheckField, 28, 4, 15, 177, 89, 0, // Skip to: 25344
+/* 2383 */    MCD_OPC_CheckField, 22, 3, 2, 170, 89, 0, // Skip to: 25344
+/* 2390 */    MCD_OPC_CheckField, 4, 3, 5, 163, 89, 0, // Skip to: 25344
+/* 2397 */    MCD_OPC_Decode, 157, 9, 106, // Opcode: MVE_VLDRDU64_rq
+/* 2401 */    MCD_OPC_FilterValue, 2, 159, 0, 0, // Skip to: 2565
+/* 2406 */    MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 2409 */    MCD_OPC_FilterValue, 0, 73, 0, 0, // Skip to: 2487
+/* 2414 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 2417 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 2452
+/* 2422 */    MCD_OPC_CheckPredicate, 22, 133, 89, 0, // Skip to: 25344
+/* 2427 */    MCD_OPC_CheckField, 28, 4, 14, 126, 89, 0, // Skip to: 25344
+/* 2434 */    MCD_OPC_CheckField, 22, 1, 0, 119, 89, 0, // Skip to: 25344
+/* 2441 */    MCD_OPC_CheckField, 7, 1, 0, 112, 89, 0, // Skip to: 25344
+/* 2448 */    MCD_OPC_Decode, 181, 13, 108, // Opcode: MVE_VSTRB32_post
+/* 2452 */    MCD_OPC_FilterValue, 1, 103, 89, 0, // Skip to: 25344
+/* 2457 */    MCD_OPC_CheckPredicate, 22, 98, 89, 0, // Skip to: 25344
+/* 2462 */    MCD_OPC_CheckField, 28, 4, 14, 91, 89, 0, // Skip to: 25344
+/* 2469 */    MCD_OPC_CheckField, 22, 1, 0, 84, 89, 0, // Skip to: 25344
+/* 2476 */    MCD_OPC_CheckField, 7, 1, 0, 77, 89, 0, // Skip to: 25344
+/* 2483 */    MCD_OPC_Decode, 182, 13, 109, // Opcode: MVE_VSTRB32_pre
+/* 2487 */    MCD_OPC_FilterValue, 1, 68, 89, 0, // Skip to: 25344
+/* 2492 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 2495 */    MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 2530
+/* 2500 */    MCD_OPC_CheckPredicate, 22, 55, 89, 0, // Skip to: 25344
+/* 2505 */    MCD_OPC_CheckField, 28, 4, 14, 48, 89, 0, // Skip to: 25344
+/* 2512 */    MCD_OPC_CheckField, 22, 1, 0, 41, 89, 0, // Skip to: 25344
+/* 2519 */    MCD_OPC_CheckField, 7, 1, 0, 34, 89, 0, // Skip to: 25344
+/* 2526 */    MCD_OPC_Decode, 195, 13, 113, // Opcode: MVE_VSTRH32_post
+/* 2530 */    MCD_OPC_FilterValue, 1, 25, 89, 0, // Skip to: 25344
+/* 2535 */    MCD_OPC_CheckPredicate, 22, 20, 89, 0, // Skip to: 25344
+/* 2540 */    MCD_OPC_CheckField, 28, 4, 14, 13, 89, 0, // Skip to: 25344
+/* 2547 */    MCD_OPC_CheckField, 22, 1, 0, 6, 89, 0, // Skip to: 25344
+/* 2554 */    MCD_OPC_CheckField, 7, 1, 0, 255, 88, 0, // Skip to: 25344
+/* 2561 */    MCD_OPC_Decode, 196, 13, 114, // Opcode: MVE_VSTRH32_pre
+/* 2565 */    MCD_OPC_FilterValue, 3, 246, 88, 0, // Skip to: 25344
+/* 2570 */    MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 2573 */    MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 2709
+/* 2578 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 2581 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 2645
+/* 2586 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2589 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 2617
+/* 2594 */    MCD_OPC_CheckPredicate, 22, 217, 88, 0, // Skip to: 25344
+/* 2599 */    MCD_OPC_CheckField, 22, 1, 0, 210, 88, 0, // Skip to: 25344
+/* 2606 */    MCD_OPC_CheckField, 7, 1, 0, 203, 88, 0, // Skip to: 25344
+/* 2613 */    MCD_OPC_Decode, 140, 9, 108, // Opcode: MVE_VLDRBS32_post
+/* 2617 */    MCD_OPC_FilterValue, 15, 194, 88, 0, // Skip to: 25344
+/* 2622 */    MCD_OPC_CheckPredicate, 22, 189, 88, 0, // Skip to: 25344
+/* 2627 */    MCD_OPC_CheckField, 22, 1, 0, 182, 88, 0, // Skip to: 25344
+/* 2634 */    MCD_OPC_CheckField, 7, 1, 0, 175, 88, 0, // Skip to: 25344
+/* 2641 */    MCD_OPC_Decode, 148, 9, 108, // Opcode: MVE_VLDRBU32_post
+/* 2645 */    MCD_OPC_FilterValue, 1, 166, 88, 0, // Skip to: 25344
+/* 2650 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2653 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 2681
+/* 2658 */    MCD_OPC_CheckPredicate, 22, 153, 88, 0, // Skip to: 25344
+/* 2663 */    MCD_OPC_CheckField, 22, 1, 0, 146, 88, 0, // Skip to: 25344
+/* 2670 */    MCD_OPC_CheckField, 7, 1, 0, 139, 88, 0, // Skip to: 25344
+/* 2677 */    MCD_OPC_Decode, 141, 9, 109, // Opcode: MVE_VLDRBS32_pre
+/* 2681 */    MCD_OPC_FilterValue, 15, 130, 88, 0, // Skip to: 25344
+/* 2686 */    MCD_OPC_CheckPredicate, 22, 125, 88, 0, // Skip to: 25344
+/* 2691 */    MCD_OPC_CheckField, 22, 1, 0, 118, 88, 0, // Skip to: 25344
+/* 2698 */    MCD_OPC_CheckField, 7, 1, 0, 111, 88, 0, // Skip to: 25344
+/* 2705 */    MCD_OPC_Decode, 149, 9, 109, // Opcode: MVE_VLDRBU32_pre
+/* 2709 */    MCD_OPC_FilterValue, 1, 102, 88, 0, // Skip to: 25344
+/* 2714 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 2717 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 2781
+/* 2722 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2725 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 2753
+/* 2730 */    MCD_OPC_CheckPredicate, 22, 81, 88, 0, // Skip to: 25344
+/* 2735 */    MCD_OPC_CheckField, 22, 1, 0, 74, 88, 0, // Skip to: 25344
+/* 2742 */    MCD_OPC_CheckField, 7, 1, 0, 67, 88, 0, // Skip to: 25344
+/* 2749 */    MCD_OPC_Decode, 160, 9, 113, // Opcode: MVE_VLDRHS32_post
+/* 2753 */    MCD_OPC_FilterValue, 15, 58, 88, 0, // Skip to: 25344
+/* 2758 */    MCD_OPC_CheckPredicate, 22, 53, 88, 0, // Skip to: 25344
+/* 2763 */    MCD_OPC_CheckField, 22, 1, 0, 46, 88, 0, // Skip to: 25344
+/* 2770 */    MCD_OPC_CheckField, 7, 1, 0, 39, 88, 0, // Skip to: 25344
+/* 2777 */    MCD_OPC_Decode, 170, 9, 113, // Opcode: MVE_VLDRHU32_post
+/* 2781 */    MCD_OPC_FilterValue, 1, 30, 88, 0, // Skip to: 25344
+/* 2786 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 2789 */    MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 2817
+/* 2794 */    MCD_OPC_CheckPredicate, 22, 17, 88, 0, // Skip to: 25344
+/* 2799 */    MCD_OPC_CheckField, 22, 1, 0, 10, 88, 0, // Skip to: 25344
+/* 2806 */    MCD_OPC_CheckField, 7, 1, 0, 3, 88, 0, // Skip to: 25344
+/* 2813 */    MCD_OPC_Decode, 161, 9, 114, // Opcode: MVE_VLDRHS32_pre
+/* 2817 */    MCD_OPC_FilterValue, 15, 250, 87, 0, // Skip to: 25344
+/* 2822 */    MCD_OPC_CheckPredicate, 22, 245, 87, 0, // Skip to: 25344
+/* 2827 */    MCD_OPC_CheckField, 22, 1, 0, 238, 87, 0, // Skip to: 25344
+/* 2834 */    MCD_OPC_CheckField, 7, 1, 0, 231, 87, 0, // Skip to: 25344
+/* 2841 */    MCD_OPC_Decode, 171, 9, 114, // Opcode: MVE_VLDRHU32_pre
+/* 2845 */    MCD_OPC_FilterValue, 30, 161, 6, 0, // Skip to: 4547
+/* 2850 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
+/* 2853 */    MCD_OPC_FilterValue, 0, 179, 1, 0, // Skip to: 3293
+/* 2858 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2861 */    MCD_OPC_FilterValue, 0, 222, 0, 0, // Skip to: 3088
+/* 2866 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 2869 */    MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 3045
+/* 2874 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 2877 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 2905
+/* 2882 */    MCD_OPC_CheckPredicate, 22, 185, 87, 0, // Skip to: 25344
+/* 2887 */    MCD_OPC_CheckField, 28, 4, 15, 178, 87, 0, // Skip to: 25344
+/* 2894 */    MCD_OPC_CheckField, 23, 1, 1, 171, 87, 0, // Skip to: 25344
+/* 2901 */    MCD_OPC_Decode, 144, 13, 115, // Opcode: MVE_VST20_8
+/* 2905 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 2933
+/* 2910 */    MCD_OPC_CheckPredicate, 22, 157, 87, 0, // Skip to: 25344
+/* 2915 */    MCD_OPC_CheckField, 28, 4, 15, 150, 87, 0, // Skip to: 25344
+/* 2922 */    MCD_OPC_CheckField, 23, 1, 1, 143, 87, 0, // Skip to: 25344
+/* 2929 */    MCD_OPC_Decode, 156, 13, 116, // Opcode: MVE_VST40_8
+/* 2933 */    MCD_OPC_FilterValue, 32, 23, 0, 0, // Skip to: 2961
+/* 2938 */    MCD_OPC_CheckPredicate, 22, 129, 87, 0, // Skip to: 25344
+/* 2943 */    MCD_OPC_CheckField, 28, 4, 15, 122, 87, 0, // Skip to: 25344
+/* 2950 */    MCD_OPC_CheckField, 23, 1, 1, 115, 87, 0, // Skip to: 25344
+/* 2957 */    MCD_OPC_Decode, 150, 13, 115, // Opcode: MVE_VST21_8
+/* 2961 */    MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 2989
+/* 2966 */    MCD_OPC_CheckPredicate, 22, 101, 87, 0, // Skip to: 25344
+/* 2971 */    MCD_OPC_CheckField, 28, 4, 15, 94, 87, 0, // Skip to: 25344
+/* 2978 */    MCD_OPC_CheckField, 23, 1, 1, 87, 87, 0, // Skip to: 25344
+/* 2985 */    MCD_OPC_Decode, 162, 13, 116, // Opcode: MVE_VST41_8
+/* 2989 */    MCD_OPC_FilterValue, 65, 23, 0, 0, // Skip to: 3017
+/* 2994 */    MCD_OPC_CheckPredicate, 22, 73, 87, 0, // Skip to: 25344
+/* 2999 */    MCD_OPC_CheckField, 28, 4, 15, 66, 87, 0, // Skip to: 25344
+/* 3006 */    MCD_OPC_CheckField, 23, 1, 1, 59, 87, 0, // Skip to: 25344
+/* 3013 */    MCD_OPC_Decode, 168, 13, 116, // Opcode: MVE_VST42_8
+/* 3017 */    MCD_OPC_FilterValue, 97, 50, 87, 0, // Skip to: 25344
+/* 3022 */    MCD_OPC_CheckPredicate, 22, 45, 87, 0, // Skip to: 25344
+/* 3027 */    MCD_OPC_CheckField, 28, 4, 15, 38, 87, 0, // Skip to: 25344
+/* 3034 */    MCD_OPC_CheckField, 23, 1, 1, 31, 87, 0, // Skip to: 25344
+/* 3041 */    MCD_OPC_Decode, 174, 13, 116, // Opcode: MVE_VST43_8
+/* 3045 */    MCD_OPC_FilterValue, 1, 22, 87, 0, // Skip to: 25344
+/* 3050 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 3053 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 3067
+/* 3058 */    MCD_OPC_CheckPredicate, 22, 9, 87, 0, // Skip to: 25344
+/* 3063 */    MCD_OPC_Decode, 185, 13, 117, // Opcode: MVE_VSTRBU8
+/* 3067 */    MCD_OPC_FilterValue, 15, 0, 87, 0, // Skip to: 25344
+/* 3072 */    MCD_OPC_CheckPredicate, 22, 251, 86, 0, // Skip to: 25344
+/* 3077 */    MCD_OPC_CheckField, 16, 1, 0, 244, 86, 0, // Skip to: 25344
+/* 3084 */    MCD_OPC_Decode, 202, 13, 118, // Opcode: MVE_VSTRW32_qi
+/* 3088 */    MCD_OPC_FilterValue, 1, 235, 86, 0, // Skip to: 25344
+/* 3093 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 3096 */    MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 3272
+/* 3101 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 3104 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3132
+/* 3109 */    MCD_OPC_CheckPredicate, 22, 214, 86, 0, // Skip to: 25344
+/* 3114 */    MCD_OPC_CheckField, 28, 4, 15, 207, 86, 0, // Skip to: 25344
+/* 3121 */    MCD_OPC_CheckField, 23, 1, 1, 200, 86, 0, // Skip to: 25344
+/* 3128 */    MCD_OPC_Decode, 140, 13, 115, // Opcode: MVE_VST20_16
+/* 3132 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 3160
+/* 3137 */    MCD_OPC_CheckPredicate, 22, 186, 86, 0, // Skip to: 25344
+/* 3142 */    MCD_OPC_CheckField, 28, 4, 15, 179, 86, 0, // Skip to: 25344
+/* 3149 */    MCD_OPC_CheckField, 23, 1, 1, 172, 86, 0, // Skip to: 25344
+/* 3156 */    MCD_OPC_Decode, 152, 13, 116, // Opcode: MVE_VST40_16
+/* 3160 */    MCD_OPC_FilterValue, 32, 23, 0, 0, // Skip to: 3188
+/* 3165 */    MCD_OPC_CheckPredicate, 22, 158, 86, 0, // Skip to: 25344
+/* 3170 */    MCD_OPC_CheckField, 28, 4, 15, 151, 86, 0, // Skip to: 25344
+/* 3177 */    MCD_OPC_CheckField, 23, 1, 1, 144, 86, 0, // Skip to: 25344
+/* 3184 */    MCD_OPC_Decode, 146, 13, 115, // Opcode: MVE_VST21_16
+/* 3188 */    MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3216
+/* 3193 */    MCD_OPC_CheckPredicate, 22, 130, 86, 0, // Skip to: 25344
+/* 3198 */    MCD_OPC_CheckField, 28, 4, 15, 123, 86, 0, // Skip to: 25344
+/* 3205 */    MCD_OPC_CheckField, 23, 1, 1, 116, 86, 0, // Skip to: 25344
+/* 3212 */    MCD_OPC_Decode, 158, 13, 116, // Opcode: MVE_VST41_16
+/* 3216 */    MCD_OPC_FilterValue, 65, 23, 0, 0, // Skip to: 3244
+/* 3221 */    MCD_OPC_CheckPredicate, 22, 102, 86, 0, // Skip to: 25344
+/* 3226 */    MCD_OPC_CheckField, 28, 4, 15, 95, 86, 0, // Skip to: 25344
+/* 3233 */    MCD_OPC_CheckField, 23, 1, 1, 88, 86, 0, // Skip to: 25344
+/* 3240 */    MCD_OPC_Decode, 164, 13, 116, // Opcode: MVE_VST42_16
+/* 3244 */    MCD_OPC_FilterValue, 97, 79, 86, 0, // Skip to: 25344
+/* 3249 */    MCD_OPC_CheckPredicate, 22, 74, 86, 0, // Skip to: 25344
+/* 3254 */    MCD_OPC_CheckField, 28, 4, 15, 67, 86, 0, // Skip to: 25344
+/* 3261 */    MCD_OPC_CheckField, 23, 1, 1, 60, 86, 0, // Skip to: 25344
+/* 3268 */    MCD_OPC_Decode, 170, 13, 116, // Opcode: MVE_VST43_16
+/* 3272 */    MCD_OPC_FilterValue, 1, 51, 86, 0, // Skip to: 25344
+/* 3277 */    MCD_OPC_CheckPredicate, 22, 46, 86, 0, // Skip to: 25344
+/* 3282 */    MCD_OPC_CheckField, 28, 4, 14, 39, 86, 0, // Skip to: 25344
+/* 3289 */    MCD_OPC_Decode, 199, 13, 119, // Opcode: MVE_VSTRHU16
+/* 3293 */    MCD_OPC_FilterValue, 1, 179, 1, 0, // Skip to: 3733
+/* 3298 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3301 */    MCD_OPC_FilterValue, 0, 222, 0, 0, // Skip to: 3528
+/* 3306 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 3309 */    MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 3485
+/* 3314 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 3317 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3345
+/* 3322 */    MCD_OPC_CheckPredicate, 22, 1, 86, 0, // Skip to: 25344
+/* 3327 */    MCD_OPC_CheckField, 28, 4, 15, 250, 85, 0, // Skip to: 25344
+/* 3334 */    MCD_OPC_CheckField, 23, 1, 1, 243, 85, 0, // Skip to: 25344
+/* 3341 */    MCD_OPC_Decode, 231, 8, 120, // Opcode: MVE_VLD20_8
+/* 3345 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 3373
+/* 3350 */    MCD_OPC_CheckPredicate, 22, 229, 85, 0, // Skip to: 25344
+/* 3355 */    MCD_OPC_CheckField, 28, 4, 15, 222, 85, 0, // Skip to: 25344
+/* 3362 */    MCD_OPC_CheckField, 23, 1, 1, 215, 85, 0, // Skip to: 25344
+/* 3369 */    MCD_OPC_Decode, 243, 8, 121, // Opcode: MVE_VLD40_8
+/* 3373 */    MCD_OPC_FilterValue, 32, 23, 0, 0, // Skip to: 3401
+/* 3378 */    MCD_OPC_CheckPredicate, 22, 201, 85, 0, // Skip to: 25344
+/* 3383 */    MCD_OPC_CheckField, 28, 4, 15, 194, 85, 0, // Skip to: 25344
+/* 3390 */    MCD_OPC_CheckField, 23, 1, 1, 187, 85, 0, // Skip to: 25344
+/* 3397 */    MCD_OPC_Decode, 237, 8, 120, // Opcode: MVE_VLD21_8
+/* 3401 */    MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3429
+/* 3406 */    MCD_OPC_CheckPredicate, 22, 173, 85, 0, // Skip to: 25344
+/* 3411 */    MCD_OPC_CheckField, 28, 4, 15, 166, 85, 0, // Skip to: 25344
+/* 3418 */    MCD_OPC_CheckField, 23, 1, 1, 159, 85, 0, // Skip to: 25344
+/* 3425 */    MCD_OPC_Decode, 249, 8, 121, // Opcode: MVE_VLD41_8
+/* 3429 */    MCD_OPC_FilterValue, 65, 23, 0, 0, // Skip to: 3457
+/* 3434 */    MCD_OPC_CheckPredicate, 22, 145, 85, 0, // Skip to: 25344
+/* 3439 */    MCD_OPC_CheckField, 28, 4, 15, 138, 85, 0, // Skip to: 25344
+/* 3446 */    MCD_OPC_CheckField, 23, 1, 1, 131, 85, 0, // Skip to: 25344
+/* 3453 */    MCD_OPC_Decode, 255, 8, 121, // Opcode: MVE_VLD42_8
+/* 3457 */    MCD_OPC_FilterValue, 97, 122, 85, 0, // Skip to: 25344
+/* 3462 */    MCD_OPC_CheckPredicate, 22, 117, 85, 0, // Skip to: 25344
+/* 3467 */    MCD_OPC_CheckField, 28, 4, 15, 110, 85, 0, // Skip to: 25344
+/* 3474 */    MCD_OPC_CheckField, 23, 1, 1, 103, 85, 0, // Skip to: 25344
+/* 3481 */    MCD_OPC_Decode, 133, 9, 121, // Opcode: MVE_VLD43_8
+/* 3485 */    MCD_OPC_FilterValue, 1, 94, 85, 0, // Skip to: 25344
+/* 3490 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 3493 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 3507
+/* 3498 */    MCD_OPC_CheckPredicate, 22, 81, 85, 0, // Skip to: 25344
+/* 3503 */    MCD_OPC_Decode, 151, 9, 117, // Opcode: MVE_VLDRBU8
+/* 3507 */    MCD_OPC_FilterValue, 15, 72, 85, 0, // Skip to: 25344
+/* 3512 */    MCD_OPC_CheckPredicate, 22, 67, 85, 0, // Skip to: 25344
+/* 3517 */    MCD_OPC_CheckField, 16, 1, 0, 60, 85, 0, // Skip to: 25344
+/* 3524 */    MCD_OPC_Decode, 177, 9, 118, // Opcode: MVE_VLDRWU32_qi
+/* 3528 */    MCD_OPC_FilterValue, 1, 51, 85, 0, // Skip to: 25344
+/* 3533 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 3536 */    MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 3712
+/* 3541 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 3544 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 3572
+/* 3549 */    MCD_OPC_CheckPredicate, 22, 30, 85, 0, // Skip to: 25344
+/* 3554 */    MCD_OPC_CheckField, 28, 4, 15, 23, 85, 0, // Skip to: 25344
+/* 3561 */    MCD_OPC_CheckField, 23, 1, 1, 16, 85, 0, // Skip to: 25344
+/* 3568 */    MCD_OPC_Decode, 227, 8, 120, // Opcode: MVE_VLD20_16
+/* 3572 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 3600
+/* 3577 */    MCD_OPC_CheckPredicate, 22, 2, 85, 0, // Skip to: 25344
+/* 3582 */    MCD_OPC_CheckField, 28, 4, 15, 251, 84, 0, // Skip to: 25344
+/* 3589 */    MCD_OPC_CheckField, 23, 1, 1, 244, 84, 0, // Skip to: 25344
+/* 3596 */    MCD_OPC_Decode, 239, 8, 121, // Opcode: MVE_VLD40_16
+/* 3600 */    MCD_OPC_FilterValue, 32, 23, 0, 0, // Skip to: 3628
+/* 3605 */    MCD_OPC_CheckPredicate, 22, 230, 84, 0, // Skip to: 25344
+/* 3610 */    MCD_OPC_CheckField, 28, 4, 15, 223, 84, 0, // Skip to: 25344
+/* 3617 */    MCD_OPC_CheckField, 23, 1, 1, 216, 84, 0, // Skip to: 25344
+/* 3624 */    MCD_OPC_Decode, 233, 8, 120, // Opcode: MVE_VLD21_16
+/* 3628 */    MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 3656
+/* 3633 */    MCD_OPC_CheckPredicate, 22, 202, 84, 0, // Skip to: 25344
+/* 3638 */    MCD_OPC_CheckField, 28, 4, 15, 195, 84, 0, // Skip to: 25344
+/* 3645 */    MCD_OPC_CheckField, 23, 1, 1, 188, 84, 0, // Skip to: 25344
+/* 3652 */    MCD_OPC_Decode, 245, 8, 121, // Opcode: MVE_VLD41_16
+/* 3656 */    MCD_OPC_FilterValue, 65, 23, 0, 0, // Skip to: 3684
+/* 3661 */    MCD_OPC_CheckPredicate, 22, 174, 84, 0, // Skip to: 25344
+/* 3666 */    MCD_OPC_CheckField, 28, 4, 15, 167, 84, 0, // Skip to: 25344
+/* 3673 */    MCD_OPC_CheckField, 23, 1, 1, 160, 84, 0, // Skip to: 25344
+/* 3680 */    MCD_OPC_Decode, 251, 8, 121, // Opcode: MVE_VLD42_16
+/* 3684 */    MCD_OPC_FilterValue, 97, 151, 84, 0, // Skip to: 25344
+/* 3689 */    MCD_OPC_CheckPredicate, 22, 146, 84, 0, // Skip to: 25344
+/* 3694 */    MCD_OPC_CheckField, 28, 4, 15, 139, 84, 0, // Skip to: 25344
+/* 3701 */    MCD_OPC_CheckField, 23, 1, 1, 132, 84, 0, // Skip to: 25344
+/* 3708 */    MCD_OPC_Decode, 129, 9, 121, // Opcode: MVE_VLD43_16
+/* 3712 */    MCD_OPC_FilterValue, 1, 123, 84, 0, // Skip to: 25344
+/* 3717 */    MCD_OPC_CheckPredicate, 22, 118, 84, 0, // Skip to: 25344
+/* 3722 */    MCD_OPC_CheckField, 28, 4, 14, 111, 84, 0, // Skip to: 25344
+/* 3729 */    MCD_OPC_Decode, 164, 9, 119, // Opcode: MVE_VLDRHU16
+/* 3733 */    MCD_OPC_FilterValue, 2, 140, 1, 0, // Skip to: 4134
+/* 3738 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 3741 */    MCD_OPC_FilterValue, 0, 202, 0, 0, // Skip to: 3948
+/* 3746 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 3749 */    MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 3905
+/* 3754 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 3757 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 3771
+/* 3762 */    MCD_OPC_CheckPredicate, 22, 73, 84, 0, // Skip to: 25344
+/* 3767 */    MCD_OPC_Decode, 186, 13, 122, // Opcode: MVE_VSTRBU8_post
+/* 3771 */    MCD_OPC_FilterValue, 15, 64, 84, 0, // Skip to: 25344
+/* 3776 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 3779 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 3800
+/* 3784 */    MCD_OPC_CheckPredicate, 22, 51, 84, 0, // Skip to: 25344
+/* 3789 */    MCD_OPC_CheckField, 23, 1, 1, 44, 84, 0, // Skip to: 25344
+/* 3796 */    MCD_OPC_Decode, 145, 13, 123, // Opcode: MVE_VST20_8_wb
+/* 3800 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 3821
+/* 3805 */    MCD_OPC_CheckPredicate, 22, 30, 84, 0, // Skip to: 25344
+/* 3810 */    MCD_OPC_CheckField, 23, 1, 1, 23, 84, 0, // Skip to: 25344
+/* 3817 */    MCD_OPC_Decode, 157, 13, 124, // Opcode: MVE_VST40_8_wb
+/* 3821 */    MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 3842
+/* 3826 */    MCD_OPC_CheckPredicate, 22, 9, 84, 0, // Skip to: 25344
+/* 3831 */    MCD_OPC_CheckField, 23, 1, 1, 2, 84, 0, // Skip to: 25344
+/* 3838 */    MCD_OPC_Decode, 151, 13, 123, // Opcode: MVE_VST21_8_wb
+/* 3842 */    MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 3863
+/* 3847 */    MCD_OPC_CheckPredicate, 22, 244, 83, 0, // Skip to: 25344
+/* 3852 */    MCD_OPC_CheckField, 23, 1, 1, 237, 83, 0, // Skip to: 25344
+/* 3859 */    MCD_OPC_Decode, 163, 13, 124, // Opcode: MVE_VST41_8_wb
+/* 3863 */    MCD_OPC_FilterValue, 65, 16, 0, 0, // Skip to: 3884
+/* 3868 */    MCD_OPC_CheckPredicate, 22, 223, 83, 0, // Skip to: 25344
+/* 3873 */    MCD_OPC_CheckField, 23, 1, 1, 216, 83, 0, // Skip to: 25344
+/* 3880 */    MCD_OPC_Decode, 169, 13, 124, // Opcode: MVE_VST42_8_wb
+/* 3884 */    MCD_OPC_FilterValue, 97, 207, 83, 0, // Skip to: 25344
+/* 3889 */    MCD_OPC_CheckPredicate, 22, 202, 83, 0, // Skip to: 25344
+/* 3894 */    MCD_OPC_CheckField, 23, 1, 1, 195, 83, 0, // Skip to: 25344
+/* 3901 */    MCD_OPC_Decode, 175, 13, 124, // Opcode: MVE_VST43_8_wb
+/* 3905 */    MCD_OPC_FilterValue, 1, 186, 83, 0, // Skip to: 25344
+/* 3910 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 3913 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 3927
+/* 3918 */    MCD_OPC_CheckPredicate, 22, 173, 83, 0, // Skip to: 25344
+/* 3923 */    MCD_OPC_Decode, 187, 13, 125, // Opcode: MVE_VSTRBU8_pre
+/* 3927 */    MCD_OPC_FilterValue, 15, 164, 83, 0, // Skip to: 25344
+/* 3932 */    MCD_OPC_CheckPredicate, 22, 159, 83, 0, // Skip to: 25344
+/* 3937 */    MCD_OPC_CheckField, 16, 1, 0, 152, 83, 0, // Skip to: 25344
+/* 3944 */    MCD_OPC_Decode, 203, 13, 126, // Opcode: MVE_VSTRW32_qi_pre
+/* 3948 */    MCD_OPC_FilterValue, 1, 143, 83, 0, // Skip to: 25344
+/* 3953 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 3956 */    MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 4112
+/* 3961 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 3964 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 3978
+/* 3969 */    MCD_OPC_CheckPredicate, 22, 122, 83, 0, // Skip to: 25344
+/* 3974 */    MCD_OPC_Decode, 200, 13, 127, // Opcode: MVE_VSTRHU16_post
+/* 3978 */    MCD_OPC_FilterValue, 15, 113, 83, 0, // Skip to: 25344
+/* 3983 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 3986 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4007
+/* 3991 */    MCD_OPC_CheckPredicate, 22, 100, 83, 0, // Skip to: 25344
+/* 3996 */    MCD_OPC_CheckField, 23, 1, 1, 93, 83, 0, // Skip to: 25344
+/* 4003 */    MCD_OPC_Decode, 141, 13, 123, // Opcode: MVE_VST20_16_wb
+/* 4007 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 4028
+/* 4012 */    MCD_OPC_CheckPredicate, 22, 79, 83, 0, // Skip to: 25344
+/* 4017 */    MCD_OPC_CheckField, 23, 1, 1, 72, 83, 0, // Skip to: 25344
+/* 4024 */    MCD_OPC_Decode, 153, 13, 124, // Opcode: MVE_VST40_16_wb
+/* 4028 */    MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 4049
+/* 4033 */    MCD_OPC_CheckPredicate, 22, 58, 83, 0, // Skip to: 25344
+/* 4038 */    MCD_OPC_CheckField, 23, 1, 1, 51, 83, 0, // Skip to: 25344
+/* 4045 */    MCD_OPC_Decode, 147, 13, 123, // Opcode: MVE_VST21_16_wb
+/* 4049 */    MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 4070
+/* 4054 */    MCD_OPC_CheckPredicate, 22, 37, 83, 0, // Skip to: 25344
+/* 4059 */    MCD_OPC_CheckField, 23, 1, 1, 30, 83, 0, // Skip to: 25344
+/* 4066 */    MCD_OPC_Decode, 159, 13, 124, // Opcode: MVE_VST41_16_wb
+/* 4070 */    MCD_OPC_FilterValue, 65, 16, 0, 0, // Skip to: 4091
+/* 4075 */    MCD_OPC_CheckPredicate, 22, 16, 83, 0, // Skip to: 25344
+/* 4080 */    MCD_OPC_CheckField, 23, 1, 1, 9, 83, 0, // Skip to: 25344
+/* 4087 */    MCD_OPC_Decode, 165, 13, 124, // Opcode: MVE_VST42_16_wb
+/* 4091 */    MCD_OPC_FilterValue, 97, 0, 83, 0, // Skip to: 25344
+/* 4096 */    MCD_OPC_CheckPredicate, 22, 251, 82, 0, // Skip to: 25344
+/* 4101 */    MCD_OPC_CheckField, 23, 1, 1, 244, 82, 0, // Skip to: 25344
+/* 4108 */    MCD_OPC_Decode, 171, 13, 124, // Opcode: MVE_VST43_16_wb
+/* 4112 */    MCD_OPC_FilterValue, 1, 235, 82, 0, // Skip to: 25344
+/* 4117 */    MCD_OPC_CheckPredicate, 22, 230, 82, 0, // Skip to: 25344
+/* 4122 */    MCD_OPC_CheckField, 28, 4, 14, 223, 82, 0, // Skip to: 25344
+/* 4129 */    MCD_OPC_Decode, 201, 13, 128, 1, // Opcode: MVE_VSTRHU16_pre
+/* 4134 */    MCD_OPC_FilterValue, 3, 213, 82, 0, // Skip to: 25344
+/* 4139 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 4142 */    MCD_OPC_FilterValue, 0, 208, 0, 0, // Skip to: 4355
+/* 4147 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 4150 */    MCD_OPC_FilterValue, 0, 157, 0, 0, // Skip to: 4312
+/* 4155 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 4158 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4172
+/* 4163 */    MCD_OPC_CheckPredicate, 22, 184, 82, 0, // Skip to: 25344
+/* 4168 */    MCD_OPC_Decode, 152, 9, 122, // Opcode: MVE_VLDRBU8_post
+/* 4172 */    MCD_OPC_FilterValue, 15, 175, 82, 0, // Skip to: 25344
+/* 4177 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 4180 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4202
+/* 4185 */    MCD_OPC_CheckPredicate, 22, 162, 82, 0, // Skip to: 25344
+/* 4190 */    MCD_OPC_CheckField, 23, 1, 1, 155, 82, 0, // Skip to: 25344
+/* 4197 */    MCD_OPC_Decode, 232, 8, 129, 1, // Opcode: MVE_VLD20_8_wb
+/* 4202 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4224
+/* 4207 */    MCD_OPC_CheckPredicate, 22, 140, 82, 0, // Skip to: 25344
+/* 4212 */    MCD_OPC_CheckField, 23, 1, 1, 133, 82, 0, // Skip to: 25344
+/* 4219 */    MCD_OPC_Decode, 244, 8, 130, 1, // Opcode: MVE_VLD40_8_wb
+/* 4224 */    MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 4246
+/* 4229 */    MCD_OPC_CheckPredicate, 22, 118, 82, 0, // Skip to: 25344
+/* 4234 */    MCD_OPC_CheckField, 23, 1, 1, 111, 82, 0, // Skip to: 25344
+/* 4241 */    MCD_OPC_Decode, 238, 8, 129, 1, // Opcode: MVE_VLD21_8_wb
+/* 4246 */    MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 4268
+/* 4251 */    MCD_OPC_CheckPredicate, 22, 96, 82, 0, // Skip to: 25344
+/* 4256 */    MCD_OPC_CheckField, 23, 1, 1, 89, 82, 0, // Skip to: 25344
+/* 4263 */    MCD_OPC_Decode, 250, 8, 130, 1, // Opcode: MVE_VLD41_8_wb
+/* 4268 */    MCD_OPC_FilterValue, 65, 17, 0, 0, // Skip to: 4290
+/* 4273 */    MCD_OPC_CheckPredicate, 22, 74, 82, 0, // Skip to: 25344
+/* 4278 */    MCD_OPC_CheckField, 23, 1, 1, 67, 82, 0, // Skip to: 25344
+/* 4285 */    MCD_OPC_Decode, 128, 9, 130, 1, // Opcode: MVE_VLD42_8_wb
+/* 4290 */    MCD_OPC_FilterValue, 97, 57, 82, 0, // Skip to: 25344
+/* 4295 */    MCD_OPC_CheckPredicate, 22, 52, 82, 0, // Skip to: 25344
+/* 4300 */    MCD_OPC_CheckField, 23, 1, 1, 45, 82, 0, // Skip to: 25344
+/* 4307 */    MCD_OPC_Decode, 134, 9, 130, 1, // Opcode: MVE_VLD43_8_wb
+/* 4312 */    MCD_OPC_FilterValue, 1, 35, 82, 0, // Skip to: 25344
+/* 4317 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 4320 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4334
+/* 4325 */    MCD_OPC_CheckPredicate, 22, 22, 82, 0, // Skip to: 25344
+/* 4330 */    MCD_OPC_Decode, 153, 9, 125, // Opcode: MVE_VLDRBU8_pre
+/* 4334 */    MCD_OPC_FilterValue, 15, 13, 82, 0, // Skip to: 25344
+/* 4339 */    MCD_OPC_CheckPredicate, 22, 8, 82, 0, // Skip to: 25344
+/* 4344 */    MCD_OPC_CheckField, 16, 1, 0, 1, 82, 0, // Skip to: 25344
+/* 4351 */    MCD_OPC_Decode, 178, 9, 126, // Opcode: MVE_VLDRWU32_qi_pre
+/* 4355 */    MCD_OPC_FilterValue, 1, 248, 81, 0, // Skip to: 25344
+/* 4360 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 4363 */    MCD_OPC_FilterValue, 0, 157, 0, 0, // Skip to: 4525
+/* 4368 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 4371 */    MCD_OPC_FilterValue, 14, 9, 0, 0, // Skip to: 4385
+/* 4376 */    MCD_OPC_CheckPredicate, 22, 227, 81, 0, // Skip to: 25344
+/* 4381 */    MCD_OPC_Decode, 165, 9, 127, // Opcode: MVE_VLDRHU16_post
+/* 4385 */    MCD_OPC_FilterValue, 15, 218, 81, 0, // Skip to: 25344
+/* 4390 */    MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 4393 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4415
+/* 4398 */    MCD_OPC_CheckPredicate, 22, 205, 81, 0, // Skip to: 25344
+/* 4403 */    MCD_OPC_CheckField, 23, 1, 1, 198, 81, 0, // Skip to: 25344
+/* 4410 */    MCD_OPC_Decode, 228, 8, 129, 1, // Opcode: MVE_VLD20_16_wb
+/* 4415 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4437
+/* 4420 */    MCD_OPC_CheckPredicate, 22, 183, 81, 0, // Skip to: 25344
+/* 4425 */    MCD_OPC_CheckField, 23, 1, 1, 176, 81, 0, // Skip to: 25344
+/* 4432 */    MCD_OPC_Decode, 240, 8, 130, 1, // Opcode: MVE_VLD40_16_wb
+/* 4437 */    MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 4459
+/* 4442 */    MCD_OPC_CheckPredicate, 22, 161, 81, 0, // Skip to: 25344
+/* 4447 */    MCD_OPC_CheckField, 23, 1, 1, 154, 81, 0, // Skip to: 25344
+/* 4454 */    MCD_OPC_Decode, 234, 8, 129, 1, // Opcode: MVE_VLD21_16_wb
+/* 4459 */    MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 4481
+/* 4464 */    MCD_OPC_CheckPredicate, 22, 139, 81, 0, // Skip to: 25344
+/* 4469 */    MCD_OPC_CheckField, 23, 1, 1, 132, 81, 0, // Skip to: 25344
+/* 4476 */    MCD_OPC_Decode, 246, 8, 130, 1, // Opcode: MVE_VLD41_16_wb
+/* 4481 */    MCD_OPC_FilterValue, 65, 17, 0, 0, // Skip to: 4503
+/* 4486 */    MCD_OPC_CheckPredicate, 22, 117, 81, 0, // Skip to: 25344
+/* 4491 */    MCD_OPC_CheckField, 23, 1, 1, 110, 81, 0, // Skip to: 25344
+/* 4498 */    MCD_OPC_Decode, 252, 8, 130, 1, // Opcode: MVE_VLD42_16_wb
+/* 4503 */    MCD_OPC_FilterValue, 97, 100, 81, 0, // Skip to: 25344
+/* 4508 */    MCD_OPC_CheckPredicate, 22, 95, 81, 0, // Skip to: 25344
+/* 4513 */    MCD_OPC_CheckField, 23, 1, 1, 88, 81, 0, // Skip to: 25344
+/* 4520 */    MCD_OPC_Decode, 130, 9, 130, 1, // Opcode: MVE_VLD43_16_wb
+/* 4525 */    MCD_OPC_FilterValue, 1, 78, 81, 0, // Skip to: 25344
+/* 4530 */    MCD_OPC_CheckPredicate, 22, 73, 81, 0, // Skip to: 25344
+/* 4535 */    MCD_OPC_CheckField, 28, 4, 14, 66, 81, 0, // Skip to: 25344
+/* 4542 */    MCD_OPC_Decode, 166, 9, 128, 1, // Opcode: MVE_VLDRHU16_pre
+/* 4547 */    MCD_OPC_FilterValue, 31, 56, 81, 0, // Skip to: 25344
+/* 4552 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
+/* 4555 */    MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 4798
+/* 4560 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 4563 */    MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 4739
+/* 4568 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
+/* 4571 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 4599
+/* 4576 */    MCD_OPC_CheckPredicate, 22, 27, 81, 0, // Skip to: 25344
+/* 4581 */    MCD_OPC_CheckField, 28, 4, 15, 20, 81, 0, // Skip to: 25344
+/* 4588 */    MCD_OPC_CheckField, 23, 1, 1, 13, 81, 0, // Skip to: 25344
+/* 4595 */    MCD_OPC_Decode, 142, 13, 115, // Opcode: MVE_VST20_32
+/* 4599 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 4627
+/* 4604 */    MCD_OPC_CheckPredicate, 22, 255, 80, 0, // Skip to: 25344
+/* 4609 */    MCD_OPC_CheckField, 28, 4, 15, 248, 80, 0, // Skip to: 25344
+/* 4616 */    MCD_OPC_CheckField, 23, 1, 1, 241, 80, 0, // Skip to: 25344
+/* 4623 */    MCD_OPC_Decode, 154, 13, 116, // Opcode: MVE_VST40_32
+/* 4627 */    MCD_OPC_FilterValue, 32, 23, 0, 0, // Skip to: 4655
+/* 4632 */    MCD_OPC_CheckPredicate, 22, 227, 80, 0, // Skip to: 25344
+/* 4637 */    MCD_OPC_CheckField, 28, 4, 15, 220, 80, 0, // Skip to: 25344
+/* 4644 */    MCD_OPC_CheckField, 23, 1, 1, 213, 80, 0, // Skip to: 25344
+/* 4651 */    MCD_OPC_Decode, 148, 13, 115, // Opcode: MVE_VST21_32
+/* 4655 */    MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 4683
+/* 4660 */    MCD_OPC_CheckPredicate, 22, 199, 80, 0, // Skip to: 25344
+/* 4665 */    MCD_OPC_CheckField, 28, 4, 15, 192, 80, 0, // Skip to: 25344
+/* 4672 */    MCD_OPC_CheckField, 23, 1, 1, 185, 80, 0, // Skip to: 25344
+/* 4679 */    MCD_OPC_Decode, 160, 13, 116, // Opcode: MVE_VST41_32
+/* 4683 */    MCD_OPC_FilterValue, 65, 23, 0, 0, // Skip to: 4711
+/* 4688 */    MCD_OPC_CheckPredicate, 22, 171, 80, 0, // Skip to: 25344
+/* 4693 */    MCD_OPC_CheckField, 28, 4, 15, 164, 80, 0, // Skip to: 25344
+/* 4700 */    MCD_OPC_CheckField, 23, 1, 1, 157, 80, 0, // Skip to: 25344
+/* 4707 */    MCD_OPC_Decode, 166, 13, 116, // Opcode: MVE_VST42_32
+/* 4711 */    MCD_OPC_FilterValue, 97, 148, 80, 0, // Skip to: 25344
+/* 4716 */    MCD_OPC_CheckPredicate, 22, 143, 80, 0, // Skip to: 25344
+/* 4721 */    MCD_OPC_CheckField, 28, 4, 15, 136, 80, 0, // Skip to: 25344
+/* 4728 */    MCD_OPC_CheckField, 23, 1, 1, 129, 80, 0, // Skip to: 25344
+/* 4735 */    MCD_OPC_Decode, 172, 13, 116, // Opcode: MVE_VST43_32
+/* 4739 */    MCD_OPC_FilterValue, 1, 120, 80, 0, // Skip to: 25344
+/* 4744 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 4747 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4769
+/* 4752 */    MCD_OPC_CheckPredicate, 22, 107, 80, 0, // Skip to: 25344
+/* 4757 */    MCD_OPC_CheckField, 7, 1, 0, 100, 80, 0, // Skip to: 25344
+/* 4764 */    MCD_OPC_Decode, 206, 13, 131, 1, // Opcode: MVE_VSTRWU32
+/* 4769 */    MCD_OPC_FilterValue, 15, 90, 80, 0, // Skip to: 25344
+/* 4774 */    MCD_OPC_CheckPredicate, 22, 85, 80, 0, // Skip to: 25344
+/* 4779 */    MCD_OPC_CheckField, 16, 1, 0, 78, 80, 0, // Skip to: 25344
+/* 4786 */    MCD_OPC_CheckField, 7, 1, 0, 71, 80, 0, // Skip to: 25344
+/* 4793 */    MCD_OPC_Decode, 188, 13, 132, 1, // Opcode: MVE_VSTRD64_qi
+/* 4798 */    MCD_OPC_FilterValue, 1, 238, 0, 0, // Skip to: 5041
+/* 4803 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 4806 */    MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 4982
+/* 4811 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
+/* 4814 */    MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 4842
+/* 4819 */    MCD_OPC_CheckPredicate, 22, 40, 80, 0, // Skip to: 25344
+/* 4824 */    MCD_OPC_CheckField, 28, 4, 15, 33, 80, 0, // Skip to: 25344
+/* 4831 */    MCD_OPC_CheckField, 23, 1, 1, 26, 80, 0, // Skip to: 25344
+/* 4838 */    MCD_OPC_Decode, 229, 8, 120, // Opcode: MVE_VLD20_32
+/* 4842 */    MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 4870
+/* 4847 */    MCD_OPC_CheckPredicate, 22, 12, 80, 0, // Skip to: 25344
+/* 4852 */    MCD_OPC_CheckField, 28, 4, 15, 5, 80, 0, // Skip to: 25344
+/* 4859 */    MCD_OPC_CheckField, 23, 1, 1, 254, 79, 0, // Skip to: 25344
+/* 4866 */    MCD_OPC_Decode, 241, 8, 121, // Opcode: MVE_VLD40_32
+/* 4870 */    MCD_OPC_FilterValue, 32, 23, 0, 0, // Skip to: 4898
+/* 4875 */    MCD_OPC_CheckPredicate, 22, 240, 79, 0, // Skip to: 25344
+/* 4880 */    MCD_OPC_CheckField, 28, 4, 15, 233, 79, 0, // Skip to: 25344
+/* 4887 */    MCD_OPC_CheckField, 23, 1, 1, 226, 79, 0, // Skip to: 25344
+/* 4894 */    MCD_OPC_Decode, 235, 8, 120, // Opcode: MVE_VLD21_32
+/* 4898 */    MCD_OPC_FilterValue, 33, 23, 0, 0, // Skip to: 4926
+/* 4903 */    MCD_OPC_CheckPredicate, 22, 212, 79, 0, // Skip to: 25344
+/* 4908 */    MCD_OPC_CheckField, 28, 4, 15, 205, 79, 0, // Skip to: 25344
+/* 4915 */    MCD_OPC_CheckField, 23, 1, 1, 198, 79, 0, // Skip to: 25344
+/* 4922 */    MCD_OPC_Decode, 247, 8, 121, // Opcode: MVE_VLD41_32
+/* 4926 */    MCD_OPC_FilterValue, 65, 23, 0, 0, // Skip to: 4954
+/* 4931 */    MCD_OPC_CheckPredicate, 22, 184, 79, 0, // Skip to: 25344
+/* 4936 */    MCD_OPC_CheckField, 28, 4, 15, 177, 79, 0, // Skip to: 25344
+/* 4943 */    MCD_OPC_CheckField, 23, 1, 1, 170, 79, 0, // Skip to: 25344
+/* 4950 */    MCD_OPC_Decode, 253, 8, 121, // Opcode: MVE_VLD42_32
+/* 4954 */    MCD_OPC_FilterValue, 97, 161, 79, 0, // Skip to: 25344
+/* 4959 */    MCD_OPC_CheckPredicate, 22, 156, 79, 0, // Skip to: 25344
+/* 4964 */    MCD_OPC_CheckField, 28, 4, 15, 149, 79, 0, // Skip to: 25344
+/* 4971 */    MCD_OPC_CheckField, 23, 1, 1, 142, 79, 0, // Skip to: 25344
+/* 4978 */    MCD_OPC_Decode, 131, 9, 121, // Opcode: MVE_VLD43_32
+/* 4982 */    MCD_OPC_FilterValue, 1, 133, 79, 0, // Skip to: 25344
+/* 4987 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 4990 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5012
+/* 4995 */    MCD_OPC_CheckPredicate, 22, 120, 79, 0, // Skip to: 25344
+/* 5000 */    MCD_OPC_CheckField, 7, 1, 0, 113, 79, 0, // Skip to: 25344
+/* 5007 */    MCD_OPC_Decode, 174, 9, 131, 1, // Opcode: MVE_VLDRWU32
+/* 5012 */    MCD_OPC_FilterValue, 15, 103, 79, 0, // Skip to: 25344
+/* 5017 */    MCD_OPC_CheckPredicate, 22, 98, 79, 0, // Skip to: 25344
+/* 5022 */    MCD_OPC_CheckField, 16, 1, 0, 91, 79, 0, // Skip to: 25344
+/* 5029 */    MCD_OPC_CheckField, 7, 1, 0, 84, 79, 0, // Skip to: 25344
+/* 5036 */    MCD_OPC_Decode, 155, 9, 132, 1, // Opcode: MVE_VLDRDU64_qi
+/* 5041 */    MCD_OPC_FilterValue, 2, 226, 0, 0, // Skip to: 5272
+/* 5046 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 5049 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 5213
+/* 5054 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5057 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5079
+/* 5062 */    MCD_OPC_CheckPredicate, 22, 53, 79, 0, // Skip to: 25344
+/* 5067 */    MCD_OPC_CheckField, 7, 1, 0, 46, 79, 0, // Skip to: 25344
+/* 5074 */    MCD_OPC_Decode, 207, 13, 133, 1, // Opcode: MVE_VSTRWU32_post
+/* 5079 */    MCD_OPC_FilterValue, 15, 36, 79, 0, // Skip to: 25344
+/* 5084 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
+/* 5087 */    MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 5108
+/* 5092 */    MCD_OPC_CheckPredicate, 22, 23, 79, 0, // Skip to: 25344
+/* 5097 */    MCD_OPC_CheckField, 23, 1, 1, 16, 79, 0, // Skip to: 25344
+/* 5104 */    MCD_OPC_Decode, 143, 13, 123, // Opcode: MVE_VST20_32_wb
+/* 5108 */    MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 5129
+/* 5113 */    MCD_OPC_CheckPredicate, 22, 2, 79, 0, // Skip to: 25344
+/* 5118 */    MCD_OPC_CheckField, 23, 1, 1, 251, 78, 0, // Skip to: 25344
+/* 5125 */    MCD_OPC_Decode, 155, 13, 124, // Opcode: MVE_VST40_32_wb
+/* 5129 */    MCD_OPC_FilterValue, 32, 16, 0, 0, // Skip to: 5150
+/* 5134 */    MCD_OPC_CheckPredicate, 22, 237, 78, 0, // Skip to: 25344
+/* 5139 */    MCD_OPC_CheckField, 23, 1, 1, 230, 78, 0, // Skip to: 25344
+/* 5146 */    MCD_OPC_Decode, 149, 13, 123, // Opcode: MVE_VST21_32_wb
+/* 5150 */    MCD_OPC_FilterValue, 33, 16, 0, 0, // Skip to: 5171
+/* 5155 */    MCD_OPC_CheckPredicate, 22, 216, 78, 0, // Skip to: 25344
+/* 5160 */    MCD_OPC_CheckField, 23, 1, 1, 209, 78, 0, // Skip to: 25344
+/* 5167 */    MCD_OPC_Decode, 161, 13, 124, // Opcode: MVE_VST41_32_wb
+/* 5171 */    MCD_OPC_FilterValue, 65, 16, 0, 0, // Skip to: 5192
+/* 5176 */    MCD_OPC_CheckPredicate, 22, 195, 78, 0, // Skip to: 25344
+/* 5181 */    MCD_OPC_CheckField, 23, 1, 1, 188, 78, 0, // Skip to: 25344
+/* 5188 */    MCD_OPC_Decode, 167, 13, 124, // Opcode: MVE_VST42_32_wb
+/* 5192 */    MCD_OPC_FilterValue, 97, 179, 78, 0, // Skip to: 25344
+/* 5197 */    MCD_OPC_CheckPredicate, 22, 174, 78, 0, // Skip to: 25344
+/* 5202 */    MCD_OPC_CheckField, 23, 1, 1, 167, 78, 0, // Skip to: 25344
+/* 5209 */    MCD_OPC_Decode, 173, 13, 124, // Opcode: MVE_VST43_32_wb
+/* 5213 */    MCD_OPC_FilterValue, 1, 158, 78, 0, // Skip to: 25344
+/* 5218 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5221 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5243
+/* 5226 */    MCD_OPC_CheckPredicate, 22, 145, 78, 0, // Skip to: 25344
+/* 5231 */    MCD_OPC_CheckField, 7, 1, 0, 138, 78, 0, // Skip to: 25344
+/* 5238 */    MCD_OPC_Decode, 208, 13, 134, 1, // Opcode: MVE_VSTRWU32_pre
+/* 5243 */    MCD_OPC_FilterValue, 15, 128, 78, 0, // Skip to: 25344
+/* 5248 */    MCD_OPC_CheckPredicate, 22, 123, 78, 0, // Skip to: 25344
+/* 5253 */    MCD_OPC_CheckField, 16, 1, 0, 116, 78, 0, // Skip to: 25344
+/* 5260 */    MCD_OPC_CheckField, 7, 1, 0, 109, 78, 0, // Skip to: 25344
+/* 5267 */    MCD_OPC_Decode, 189, 13, 135, 1, // Opcode: MVE_VSTRD64_qi_pre
+/* 5272 */    MCD_OPC_FilterValue, 3, 99, 78, 0, // Skip to: 25344
+/* 5277 */    MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 5280 */    MCD_OPC_FilterValue, 0, 165, 0, 0, // Skip to: 5450
+/* 5285 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5288 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5310
+/* 5293 */    MCD_OPC_CheckPredicate, 22, 78, 78, 0, // Skip to: 25344
+/* 5298 */    MCD_OPC_CheckField, 7, 1, 0, 71, 78, 0, // Skip to: 25344
+/* 5305 */    MCD_OPC_Decode, 175, 9, 133, 1, // Opcode: MVE_VLDRWU32_post
+/* 5310 */    MCD_OPC_FilterValue, 15, 61, 78, 0, // Skip to: 25344
+/* 5315 */    MCD_OPC_ExtractField, 0, 8,  // Inst{7-0} ...
+/* 5318 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5340
+/* 5323 */    MCD_OPC_CheckPredicate, 22, 48, 78, 0, // Skip to: 25344
+/* 5328 */    MCD_OPC_CheckField, 23, 1, 1, 41, 78, 0, // Skip to: 25344
+/* 5335 */    MCD_OPC_Decode, 230, 8, 129, 1, // Opcode: MVE_VLD20_32_wb
+/* 5340 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 5362
+/* 5345 */    MCD_OPC_CheckPredicate, 22, 26, 78, 0, // Skip to: 25344
+/* 5350 */    MCD_OPC_CheckField, 23, 1, 1, 19, 78, 0, // Skip to: 25344
+/* 5357 */    MCD_OPC_Decode, 242, 8, 130, 1, // Opcode: MVE_VLD40_32_wb
+/* 5362 */    MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 5384
+/* 5367 */    MCD_OPC_CheckPredicate, 22, 4, 78, 0, // Skip to: 25344
+/* 5372 */    MCD_OPC_CheckField, 23, 1, 1, 253, 77, 0, // Skip to: 25344
+/* 5379 */    MCD_OPC_Decode, 236, 8, 129, 1, // Opcode: MVE_VLD21_32_wb
+/* 5384 */    MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 5406
+/* 5389 */    MCD_OPC_CheckPredicate, 22, 238, 77, 0, // Skip to: 25344
+/* 5394 */    MCD_OPC_CheckField, 23, 1, 1, 231, 77, 0, // Skip to: 25344
+/* 5401 */    MCD_OPC_Decode, 248, 8, 130, 1, // Opcode: MVE_VLD41_32_wb
+/* 5406 */    MCD_OPC_FilterValue, 65, 17, 0, 0, // Skip to: 5428
+/* 5411 */    MCD_OPC_CheckPredicate, 22, 216, 77, 0, // Skip to: 25344
+/* 5416 */    MCD_OPC_CheckField, 23, 1, 1, 209, 77, 0, // Skip to: 25344
+/* 5423 */    MCD_OPC_Decode, 254, 8, 130, 1, // Opcode: MVE_VLD42_32_wb
+/* 5428 */    MCD_OPC_FilterValue, 97, 199, 77, 0, // Skip to: 25344
+/* 5433 */    MCD_OPC_CheckPredicate, 22, 194, 77, 0, // Skip to: 25344
+/* 5438 */    MCD_OPC_CheckField, 23, 1, 1, 187, 77, 0, // Skip to: 25344
+/* 5445 */    MCD_OPC_Decode, 132, 9, 130, 1, // Opcode: MVE_VLD43_32_wb
+/* 5450 */    MCD_OPC_FilterValue, 1, 177, 77, 0, // Skip to: 25344
+/* 5455 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5458 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5480
+/* 5463 */    MCD_OPC_CheckPredicate, 22, 164, 77, 0, // Skip to: 25344
+/* 5468 */    MCD_OPC_CheckField, 7, 1, 0, 157, 77, 0, // Skip to: 25344
+/* 5475 */    MCD_OPC_Decode, 176, 9, 134, 1, // Opcode: MVE_VLDRWU32_pre
+/* 5480 */    MCD_OPC_FilterValue, 15, 147, 77, 0, // Skip to: 25344
+/* 5485 */    MCD_OPC_CheckPredicate, 22, 142, 77, 0, // Skip to: 25344
+/* 5490 */    MCD_OPC_CheckField, 16, 1, 0, 135, 77, 0, // Skip to: 25344
+/* 5497 */    MCD_OPC_CheckField, 7, 1, 0, 128, 77, 0, // Skip to: 25344
+/* 5504 */    MCD_OPC_Decode, 156, 9, 135, 1, // Opcode: MVE_VLDRDU64_qi_pre
+/* 5509 */    MCD_OPC_FilterValue, 7, 118, 77, 0, // Skip to: 25344
+/* 5514 */    MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 5517 */    MCD_OPC_FilterValue, 0, 179, 28, 0, // Skip to: 12869
+/* 5522 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 5525 */    MCD_OPC_FilterValue, 11, 195, 0, 0, // Skip to: 5725
+/* 5530 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5533 */    MCD_OPC_FilterValue, 0, 91, 0, 0, // Skip to: 5629
+/* 5538 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 5541 */    MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 5600
+/* 5546 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 5549 */    MCD_OPC_FilterValue, 16, 24, 0, 0, // Skip to: 5578
+/* 5554 */    MCD_OPC_CheckPredicate, 25, 73, 77, 0, // Skip to: 25344
+/* 5559 */    MCD_OPC_CheckField, 28, 4, 14, 66, 77, 0, // Skip to: 25344
+/* 5566 */    MCD_OPC_CheckField, 6, 1, 0, 59, 77, 0, // Skip to: 25344
+/* 5573 */    MCD_OPC_Decode, 181, 10, 136, 1, // Opcode: MVE_VMOV_to_lane_32
+/* 5578 */    MCD_OPC_FilterValue, 48, 49, 77, 0, // Skip to: 25344
+/* 5583 */    MCD_OPC_CheckPredicate, 23, 44, 77, 0, // Skip to: 25344
+/* 5588 */    MCD_OPC_CheckField, 28, 4, 14, 37, 77, 0, // Skip to: 25344
+/* 5595 */    MCD_OPC_Decode, 180, 10, 137, 1, // Opcode: MVE_VMOV_to_lane_16
+/* 5600 */    MCD_OPC_FilterValue, 1, 27, 77, 0, // Skip to: 25344
+/* 5605 */    MCD_OPC_CheckPredicate, 23, 22, 77, 0, // Skip to: 25344
+/* 5610 */    MCD_OPC_CheckField, 28, 4, 14, 15, 77, 0, // Skip to: 25344
+/* 5617 */    MCD_OPC_CheckField, 0, 5, 16, 8, 77, 0, // Skip to: 25344
+/* 5624 */    MCD_OPC_Decode, 182, 10, 138, 1, // Opcode: MVE_VMOV_to_lane_8
+/* 5629 */    MCD_OPC_FilterValue, 1, 254, 76, 0, // Skip to: 25344
+/* 5634 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 5637 */    MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 5696
+/* 5642 */    MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
+/* 5645 */    MCD_OPC_FilterValue, 16, 24, 0, 0, // Skip to: 5674
+/* 5650 */    MCD_OPC_CheckPredicate, 25, 233, 76, 0, // Skip to: 25344
+/* 5655 */    MCD_OPC_CheckField, 28, 4, 14, 226, 76, 0, // Skip to: 25344
+/* 5662 */    MCD_OPC_CheckField, 6, 1, 0, 219, 76, 0, // Skip to: 25344
+/* 5669 */    MCD_OPC_Decode, 173, 10, 139, 1, // Opcode: MVE_VMOV_from_lane_32
+/* 5674 */    MCD_OPC_FilterValue, 48, 209, 76, 0, // Skip to: 25344
+/* 5679 */    MCD_OPC_CheckPredicate, 23, 204, 76, 0, // Skip to: 25344
+/* 5684 */    MCD_OPC_CheckField, 28, 4, 14, 197, 76, 0, // Skip to: 25344
+/* 5691 */    MCD_OPC_Decode, 174, 10, 140, 1, // Opcode: MVE_VMOV_from_lane_s16
+/* 5696 */    MCD_OPC_FilterValue, 1, 187, 76, 0, // Skip to: 25344
+/* 5701 */    MCD_OPC_CheckPredicate, 23, 182, 76, 0, // Skip to: 25344
+/* 5706 */    MCD_OPC_CheckField, 28, 4, 14, 175, 76, 0, // Skip to: 25344
+/* 5713 */    MCD_OPC_CheckField, 0, 5, 16, 168, 76, 0, // Skip to: 25344
+/* 5720 */    MCD_OPC_Decode, 175, 10, 141, 1, // Opcode: MVE_VMOV_from_lane_s8
+/* 5725 */    MCD_OPC_FilterValue, 14, 175, 16, 0, // Skip to: 10001
+/* 5730 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 5733 */    MCD_OPC_FilterValue, 0, 227, 2, 0, // Skip to: 6477
+/* 5738 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5741 */    MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 6213
+/* 5746 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 5749 */    MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 5981
+/* 5754 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 5757 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 5869
+/* 5762 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 5765 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 5817
+/* 5770 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5773 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5795
+/* 5778 */    MCD_OPC_CheckPredicate, 22, 105, 76, 0, // Skip to: 25344
+/* 5783 */    MCD_OPC_CheckField, 4, 1, 0, 98, 76, 0, // Skip to: 25344
+/* 5790 */    MCD_OPC_Decode, 149, 11, 142, 1, // Opcode: MVE_VQDMLADHs8
+/* 5795 */    MCD_OPC_FilterValue, 15, 88, 76, 0, // Skip to: 25344
+/* 5800 */    MCD_OPC_CheckPredicate, 22, 83, 76, 0, // Skip to: 25344
+/* 5805 */    MCD_OPC_CheckField, 4, 1, 0, 76, 76, 0, // Skip to: 25344
+/* 5812 */    MCD_OPC_Decode, 161, 11, 142, 1, // Opcode: MVE_VQDMLSDHs8
+/* 5817 */    MCD_OPC_FilterValue, 1, 66, 76, 0, // Skip to: 25344
+/* 5822 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5825 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5847
+/* 5830 */    MCD_OPC_CheckPredicate, 22, 53, 76, 0, // Skip to: 25344
+/* 5835 */    MCD_OPC_CheckField, 4, 1, 0, 46, 76, 0, // Skip to: 25344
+/* 5842 */    MCD_OPC_Decode, 198, 10, 143, 1, // Opcode: MVE_VMULLBs8
+/* 5847 */    MCD_OPC_FilterValue, 15, 36, 76, 0, // Skip to: 25344
+/* 5852 */    MCD_OPC_CheckPredicate, 22, 31, 76, 0, // Skip to: 25344
+/* 5857 */    MCD_OPC_CheckField, 4, 1, 0, 24, 76, 0, // Skip to: 25344
+/* 5864 */    MCD_OPC_Decode, 201, 10, 143, 1, // Opcode: MVE_VMULLBu8
+/* 5869 */    MCD_OPC_FilterValue, 1, 14, 76, 0, // Skip to: 25344
+/* 5874 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 5877 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 5929
+/* 5882 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5885 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5907
+/* 5890 */    MCD_OPC_CheckPredicate, 22, 249, 75, 0, // Skip to: 25344
+/* 5895 */    MCD_OPC_CheckField, 4, 1, 0, 242, 75, 0, // Skip to: 25344
+/* 5902 */    MCD_OPC_Decode, 146, 11, 142, 1, // Opcode: MVE_VQDMLADHXs8
+/* 5907 */    MCD_OPC_FilterValue, 15, 232, 75, 0, // Skip to: 25344
+/* 5912 */    MCD_OPC_CheckPredicate, 22, 227, 75, 0, // Skip to: 25344
+/* 5917 */    MCD_OPC_CheckField, 4, 1, 0, 220, 75, 0, // Skip to: 25344
+/* 5924 */    MCD_OPC_Decode, 158, 11, 142, 1, // Opcode: MVE_VQDMLSDHXs8
+/* 5929 */    MCD_OPC_FilterValue, 1, 210, 75, 0, // Skip to: 25344
+/* 5934 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 5937 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 5959
+/* 5942 */    MCD_OPC_CheckPredicate, 22, 197, 75, 0, // Skip to: 25344
+/* 5947 */    MCD_OPC_CheckField, 4, 1, 0, 190, 75, 0, // Skip to: 25344
+/* 5954 */    MCD_OPC_Decode, 206, 10, 143, 1, // Opcode: MVE_VMULLTs8
+/* 5959 */    MCD_OPC_FilterValue, 15, 180, 75, 0, // Skip to: 25344
+/* 5964 */    MCD_OPC_CheckPredicate, 22, 175, 75, 0, // Skip to: 25344
+/* 5969 */    MCD_OPC_CheckField, 4, 1, 0, 168, 75, 0, // Skip to: 25344
+/* 5976 */    MCD_OPC_Decode, 209, 10, 143, 1, // Opcode: MVE_VMULLTu8
+/* 5981 */    MCD_OPC_FilterValue, 1, 158, 75, 0, // Skip to: 25344
+/* 5986 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 5989 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 6101
+/* 5994 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 5997 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6049
+/* 6002 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6005 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6027
+/* 6010 */    MCD_OPC_CheckPredicate, 22, 129, 75, 0, // Skip to: 25344
+/* 6015 */    MCD_OPC_CheckField, 4, 1, 0, 122, 75, 0, // Skip to: 25344
+/* 6022 */    MCD_OPC_Decode, 196, 11, 142, 1, // Opcode: MVE_VQRDMLADHs8
+/* 6027 */    MCD_OPC_FilterValue, 15, 112, 75, 0, // Skip to: 25344
+/* 6032 */    MCD_OPC_CheckPredicate, 22, 107, 75, 0, // Skip to: 25344
+/* 6037 */    MCD_OPC_CheckField, 4, 1, 0, 100, 75, 0, // Skip to: 25344
+/* 6044 */    MCD_OPC_Decode, 208, 11, 142, 1, // Opcode: MVE_VQRDMLSDHs8
+/* 6049 */    MCD_OPC_FilterValue, 1, 90, 75, 0, // Skip to: 25344
+/* 6054 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6057 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6079
+/* 6062 */    MCD_OPC_CheckPredicate, 22, 77, 75, 0, // Skip to: 25344
+/* 6067 */    MCD_OPC_CheckField, 4, 1, 0, 70, 75, 0, // Skip to: 25344
+/* 6074 */    MCD_OPC_Decode, 190, 10, 143, 1, // Opcode: MVE_VMULHs8
+/* 6079 */    MCD_OPC_FilterValue, 15, 60, 75, 0, // Skip to: 25344
+/* 6084 */    MCD_OPC_CheckPredicate, 22, 55, 75, 0, // Skip to: 25344
+/* 6089 */    MCD_OPC_CheckField, 4, 1, 0, 48, 75, 0, // Skip to: 25344
+/* 6096 */    MCD_OPC_Decode, 193, 10, 143, 1, // Opcode: MVE_VMULHu8
+/* 6101 */    MCD_OPC_FilterValue, 1, 38, 75, 0, // Skip to: 25344
+/* 6106 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6109 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6161
+/* 6114 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6117 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6139
+/* 6122 */    MCD_OPC_CheckPredicate, 22, 17, 75, 0, // Skip to: 25344
+/* 6127 */    MCD_OPC_CheckField, 4, 1, 0, 10, 75, 0, // Skip to: 25344
+/* 6134 */    MCD_OPC_Decode, 193, 11, 142, 1, // Opcode: MVE_VQRDMLADHXs8
+/* 6139 */    MCD_OPC_FilterValue, 15, 0, 75, 0, // Skip to: 25344
+/* 6144 */    MCD_OPC_CheckPredicate, 22, 251, 74, 0, // Skip to: 25344
+/* 6149 */    MCD_OPC_CheckField, 4, 1, 0, 244, 74, 0, // Skip to: 25344
+/* 6156 */    MCD_OPC_Decode, 205, 11, 142, 1, // Opcode: MVE_VQRDMLSDHXs8
+/* 6161 */    MCD_OPC_FilterValue, 1, 234, 74, 0, // Skip to: 25344
+/* 6166 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6169 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6191
+/* 6174 */    MCD_OPC_CheckPredicate, 22, 221, 74, 0, // Skip to: 25344
+/* 6179 */    MCD_OPC_CheckField, 4, 1, 0, 214, 74, 0, // Skip to: 25344
+/* 6186 */    MCD_OPC_Decode, 192, 12, 143, 1, // Opcode: MVE_VRMULHs8
+/* 6191 */    MCD_OPC_FilterValue, 15, 204, 74, 0, // Skip to: 25344
+/* 6196 */    MCD_OPC_CheckPredicate, 22, 199, 74, 0, // Skip to: 25344
+/* 6201 */    MCD_OPC_CheckField, 4, 1, 0, 192, 74, 0, // Skip to: 25344
+/* 6208 */    MCD_OPC_Decode, 195, 12, 143, 1, // Opcode: MVE_VRMULHu8
+/* 6213 */    MCD_OPC_FilterValue, 1, 182, 74, 0, // Skip to: 25344
+/* 6218 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 6221 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 6333
+/* 6226 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 6229 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6281
+/* 6234 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6237 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6259
+/* 6242 */    MCD_OPC_CheckPredicate, 22, 153, 74, 0, // Skip to: 25344
+/* 6247 */    MCD_OPC_CheckField, 28, 4, 14, 146, 74, 0, // Skip to: 25344
+/* 6254 */    MCD_OPC_Decode, 199, 11, 144, 1, // Opcode: MVE_VQRDMLAH_qrs8
+/* 6259 */    MCD_OPC_FilterValue, 1, 136, 74, 0, // Skip to: 25344
+/* 6264 */    MCD_OPC_CheckPredicate, 22, 131, 74, 0, // Skip to: 25344
+/* 6269 */    MCD_OPC_CheckField, 28, 4, 14, 124, 74, 0, // Skip to: 25344
+/* 6276 */    MCD_OPC_Decode, 140, 10, 144, 1, // Opcode: MVE_VMLA_qr_i8
+/* 6281 */    MCD_OPC_FilterValue, 1, 114, 74, 0, // Skip to: 25344
+/* 6286 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6289 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6311
+/* 6294 */    MCD_OPC_CheckPredicate, 22, 101, 74, 0, // Skip to: 25344
+/* 6299 */    MCD_OPC_CheckField, 28, 4, 14, 94, 74, 0, // Skip to: 25344
+/* 6306 */    MCD_OPC_Decode, 202, 11, 144, 1, // Opcode: MVE_VQRDMLASH_qrs8
+/* 6311 */    MCD_OPC_FilterValue, 1, 84, 74, 0, // Skip to: 25344
+/* 6316 */    MCD_OPC_CheckPredicate, 22, 79, 74, 0, // Skip to: 25344
+/* 6321 */    MCD_OPC_CheckField, 28, 4, 14, 72, 74, 0, // Skip to: 25344
+/* 6328 */    MCD_OPC_Decode, 137, 10, 144, 1, // Opcode: MVE_VMLAS_qr_i8
+/* 6333 */    MCD_OPC_FilterValue, 2, 62, 74, 0, // Skip to: 25344
+/* 6338 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 6341 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 6409
+/* 6346 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6349 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6371
+/* 6354 */    MCD_OPC_CheckPredicate, 22, 41, 74, 0, // Skip to: 25344
+/* 6359 */    MCD_OPC_CheckField, 28, 4, 14, 34, 74, 0, // Skip to: 25344
+/* 6366 */    MCD_OPC_Decode, 152, 11, 144, 1, // Opcode: MVE_VQDMLAH_qrs8
+/* 6371 */    MCD_OPC_FilterValue, 1, 24, 74, 0, // Skip to: 25344
+/* 6376 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6379 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 6394
+/* 6384 */    MCD_OPC_CheckPredicate, 22, 11, 74, 0, // Skip to: 25344
+/* 6389 */    MCD_OPC_Decode, 164, 11, 145, 1, // Opcode: MVE_VQDMULH_qr_s8
+/* 6394 */    MCD_OPC_FilterValue, 15, 1, 74, 0, // Skip to: 25344
+/* 6399 */    MCD_OPC_CheckPredicate, 22, 252, 73, 0, // Skip to: 25344
+/* 6404 */    MCD_OPC_Decode, 211, 11, 145, 1, // Opcode: MVE_VQRDMULH_qr_s8
+/* 6409 */    MCD_OPC_FilterValue, 1, 242, 73, 0, // Skip to: 25344
+/* 6414 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6417 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6439
+/* 6422 */    MCD_OPC_CheckPredicate, 22, 229, 73, 0, // Skip to: 25344
+/* 6427 */    MCD_OPC_CheckField, 28, 4, 14, 222, 73, 0, // Skip to: 25344
+/* 6434 */    MCD_OPC_Decode, 155, 11, 144, 1, // Opcode: MVE_VQDMLASH_qrs8
+/* 6439 */    MCD_OPC_FilterValue, 1, 212, 73, 0, // Skip to: 25344
+/* 6444 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6447 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 6462
+/* 6452 */    MCD_OPC_CheckPredicate, 22, 199, 73, 0, // Skip to: 25344
+/* 6457 */    MCD_OPC_Decode, 214, 10, 145, 1, // Opcode: MVE_VMUL_qr_i8
+/* 6462 */    MCD_OPC_FilterValue, 15, 189, 73, 0, // Skip to: 25344
+/* 6467 */    MCD_OPC_CheckPredicate, 22, 184, 73, 0, // Skip to: 25344
+/* 6472 */    MCD_OPC_Decode, 226, 7, 145, 1, // Opcode: MVE_VBRSR8
+/* 6477 */    MCD_OPC_FilterValue, 1, 227, 2, 0, // Skip to: 7221
+/* 6482 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6485 */    MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 6957
+/* 6490 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 6493 */    MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 6725
+/* 6498 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 6501 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 6613
+/* 6506 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6509 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6561
+/* 6514 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6517 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6539
+/* 6522 */    MCD_OPC_CheckPredicate, 22, 129, 73, 0, // Skip to: 25344
+/* 6527 */    MCD_OPC_CheckField, 4, 1, 0, 122, 73, 0, // Skip to: 25344
+/* 6534 */    MCD_OPC_Decode, 147, 11, 142, 1, // Opcode: MVE_VQDMLADHs16
+/* 6539 */    MCD_OPC_FilterValue, 15, 112, 73, 0, // Skip to: 25344
+/* 6544 */    MCD_OPC_CheckPredicate, 22, 107, 73, 0, // Skip to: 25344
+/* 6549 */    MCD_OPC_CheckField, 4, 1, 0, 100, 73, 0, // Skip to: 25344
+/* 6556 */    MCD_OPC_Decode, 159, 11, 142, 1, // Opcode: MVE_VQDMLSDHs16
+/* 6561 */    MCD_OPC_FilterValue, 1, 90, 73, 0, // Skip to: 25344
+/* 6566 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6569 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6591
+/* 6574 */    MCD_OPC_CheckPredicate, 22, 77, 73, 0, // Skip to: 25344
+/* 6579 */    MCD_OPC_CheckField, 4, 1, 0, 70, 73, 0, // Skip to: 25344
+/* 6586 */    MCD_OPC_Decode, 196, 10, 143, 1, // Opcode: MVE_VMULLBs16
+/* 6591 */    MCD_OPC_FilterValue, 15, 60, 73, 0, // Skip to: 25344
+/* 6596 */    MCD_OPC_CheckPredicate, 22, 55, 73, 0, // Skip to: 25344
+/* 6601 */    MCD_OPC_CheckField, 4, 1, 0, 48, 73, 0, // Skip to: 25344
+/* 6608 */    MCD_OPC_Decode, 199, 10, 143, 1, // Opcode: MVE_VMULLBu16
+/* 6613 */    MCD_OPC_FilterValue, 1, 38, 73, 0, // Skip to: 25344
+/* 6618 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6621 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6673
+/* 6626 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6629 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6651
+/* 6634 */    MCD_OPC_CheckPredicate, 22, 17, 73, 0, // Skip to: 25344
+/* 6639 */    MCD_OPC_CheckField, 4, 1, 0, 10, 73, 0, // Skip to: 25344
+/* 6646 */    MCD_OPC_Decode, 144, 11, 142, 1, // Opcode: MVE_VQDMLADHXs16
+/* 6651 */    MCD_OPC_FilterValue, 15, 0, 73, 0, // Skip to: 25344
+/* 6656 */    MCD_OPC_CheckPredicate, 22, 251, 72, 0, // Skip to: 25344
+/* 6661 */    MCD_OPC_CheckField, 4, 1, 0, 244, 72, 0, // Skip to: 25344
+/* 6668 */    MCD_OPC_Decode, 156, 11, 142, 1, // Opcode: MVE_VQDMLSDHXs16
+/* 6673 */    MCD_OPC_FilterValue, 1, 234, 72, 0, // Skip to: 25344
+/* 6678 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6681 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6703
+/* 6686 */    MCD_OPC_CheckPredicate, 22, 221, 72, 0, // Skip to: 25344
+/* 6691 */    MCD_OPC_CheckField, 4, 1, 0, 214, 72, 0, // Skip to: 25344
+/* 6698 */    MCD_OPC_Decode, 204, 10, 143, 1, // Opcode: MVE_VMULLTs16
+/* 6703 */    MCD_OPC_FilterValue, 15, 204, 72, 0, // Skip to: 25344
+/* 6708 */    MCD_OPC_CheckPredicate, 22, 199, 72, 0, // Skip to: 25344
+/* 6713 */    MCD_OPC_CheckField, 4, 1, 0, 192, 72, 0, // Skip to: 25344
+/* 6720 */    MCD_OPC_Decode, 207, 10, 143, 1, // Opcode: MVE_VMULLTu16
+/* 6725 */    MCD_OPC_FilterValue, 1, 182, 72, 0, // Skip to: 25344
+/* 6730 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 6733 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 6845
+/* 6738 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6741 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6793
+/* 6746 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6749 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6771
+/* 6754 */    MCD_OPC_CheckPredicate, 22, 153, 72, 0, // Skip to: 25344
+/* 6759 */    MCD_OPC_CheckField, 4, 1, 0, 146, 72, 0, // Skip to: 25344
+/* 6766 */    MCD_OPC_Decode, 194, 11, 142, 1, // Opcode: MVE_VQRDMLADHs16
+/* 6771 */    MCD_OPC_FilterValue, 15, 136, 72, 0, // Skip to: 25344
+/* 6776 */    MCD_OPC_CheckPredicate, 22, 131, 72, 0, // Skip to: 25344
+/* 6781 */    MCD_OPC_CheckField, 4, 1, 0, 124, 72, 0, // Skip to: 25344
+/* 6788 */    MCD_OPC_Decode, 206, 11, 142, 1, // Opcode: MVE_VQRDMLSDHs16
+/* 6793 */    MCD_OPC_FilterValue, 1, 114, 72, 0, // Skip to: 25344
+/* 6798 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6801 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6823
+/* 6806 */    MCD_OPC_CheckPredicate, 22, 101, 72, 0, // Skip to: 25344
+/* 6811 */    MCD_OPC_CheckField, 4, 1, 0, 94, 72, 0, // Skip to: 25344
+/* 6818 */    MCD_OPC_Decode, 188, 10, 143, 1, // Opcode: MVE_VMULHs16
+/* 6823 */    MCD_OPC_FilterValue, 15, 84, 72, 0, // Skip to: 25344
+/* 6828 */    MCD_OPC_CheckPredicate, 22, 79, 72, 0, // Skip to: 25344
+/* 6833 */    MCD_OPC_CheckField, 4, 1, 0, 72, 72, 0, // Skip to: 25344
+/* 6840 */    MCD_OPC_Decode, 191, 10, 143, 1, // Opcode: MVE_VMULHu16
+/* 6845 */    MCD_OPC_FilterValue, 1, 62, 72, 0, // Skip to: 25344
+/* 6850 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6853 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 6905
+/* 6858 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6861 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6883
+/* 6866 */    MCD_OPC_CheckPredicate, 22, 41, 72, 0, // Skip to: 25344
+/* 6871 */    MCD_OPC_CheckField, 4, 1, 0, 34, 72, 0, // Skip to: 25344
+/* 6878 */    MCD_OPC_Decode, 191, 11, 142, 1, // Opcode: MVE_VQRDMLADHXs16
+/* 6883 */    MCD_OPC_FilterValue, 15, 24, 72, 0, // Skip to: 25344
+/* 6888 */    MCD_OPC_CheckPredicate, 22, 19, 72, 0, // Skip to: 25344
+/* 6893 */    MCD_OPC_CheckField, 4, 1, 0, 12, 72, 0, // Skip to: 25344
+/* 6900 */    MCD_OPC_Decode, 203, 11, 142, 1, // Opcode: MVE_VQRDMLSDHXs16
+/* 6905 */    MCD_OPC_FilterValue, 1, 2, 72, 0, // Skip to: 25344
+/* 6910 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 6913 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 6935
+/* 6918 */    MCD_OPC_CheckPredicate, 22, 245, 71, 0, // Skip to: 25344
+/* 6923 */    MCD_OPC_CheckField, 4, 1, 0, 238, 71, 0, // Skip to: 25344
+/* 6930 */    MCD_OPC_Decode, 190, 12, 143, 1, // Opcode: MVE_VRMULHs16
+/* 6935 */    MCD_OPC_FilterValue, 15, 228, 71, 0, // Skip to: 25344
+/* 6940 */    MCD_OPC_CheckPredicate, 22, 223, 71, 0, // Skip to: 25344
+/* 6945 */    MCD_OPC_CheckField, 4, 1, 0, 216, 71, 0, // Skip to: 25344
+/* 6952 */    MCD_OPC_Decode, 193, 12, 143, 1, // Opcode: MVE_VRMULHu16
+/* 6957 */    MCD_OPC_FilterValue, 1, 206, 71, 0, // Skip to: 25344
+/* 6962 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 6965 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 7077
+/* 6970 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 6973 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 7025
+/* 6978 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 6981 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7003
+/* 6986 */    MCD_OPC_CheckPredicate, 22, 177, 71, 0, // Skip to: 25344
+/* 6991 */    MCD_OPC_CheckField, 28, 4, 14, 170, 71, 0, // Skip to: 25344
+/* 6998 */    MCD_OPC_Decode, 197, 11, 144, 1, // Opcode: MVE_VQRDMLAH_qrs16
+/* 7003 */    MCD_OPC_FilterValue, 1, 160, 71, 0, // Skip to: 25344
+/* 7008 */    MCD_OPC_CheckPredicate, 22, 155, 71, 0, // Skip to: 25344
+/* 7013 */    MCD_OPC_CheckField, 28, 4, 14, 148, 71, 0, // Skip to: 25344
+/* 7020 */    MCD_OPC_Decode, 138, 10, 144, 1, // Opcode: MVE_VMLA_qr_i16
+/* 7025 */    MCD_OPC_FilterValue, 1, 138, 71, 0, // Skip to: 25344
+/* 7030 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7033 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7055
+/* 7038 */    MCD_OPC_CheckPredicate, 22, 125, 71, 0, // Skip to: 25344
+/* 7043 */    MCD_OPC_CheckField, 28, 4, 14, 118, 71, 0, // Skip to: 25344
+/* 7050 */    MCD_OPC_Decode, 200, 11, 144, 1, // Opcode: MVE_VQRDMLASH_qrs16
+/* 7055 */    MCD_OPC_FilterValue, 1, 108, 71, 0, // Skip to: 25344
+/* 7060 */    MCD_OPC_CheckPredicate, 22, 103, 71, 0, // Skip to: 25344
+/* 7065 */    MCD_OPC_CheckField, 28, 4, 14, 96, 71, 0, // Skip to: 25344
+/* 7072 */    MCD_OPC_Decode, 135, 10, 144, 1, // Opcode: MVE_VMLAS_qr_i16
+/* 7077 */    MCD_OPC_FilterValue, 2, 86, 71, 0, // Skip to: 25344
+/* 7082 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 7085 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 7153
+/* 7090 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7093 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7115
+/* 7098 */    MCD_OPC_CheckPredicate, 22, 65, 71, 0, // Skip to: 25344
+/* 7103 */    MCD_OPC_CheckField, 28, 4, 14, 58, 71, 0, // Skip to: 25344
+/* 7110 */    MCD_OPC_Decode, 150, 11, 144, 1, // Opcode: MVE_VQDMLAH_qrs16
+/* 7115 */    MCD_OPC_FilterValue, 1, 48, 71, 0, // Skip to: 25344
+/* 7120 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7123 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7138
+/* 7128 */    MCD_OPC_CheckPredicate, 22, 35, 71, 0, // Skip to: 25344
+/* 7133 */    MCD_OPC_Decode, 162, 11, 145, 1, // Opcode: MVE_VQDMULH_qr_s16
+/* 7138 */    MCD_OPC_FilterValue, 15, 25, 71, 0, // Skip to: 25344
+/* 7143 */    MCD_OPC_CheckPredicate, 22, 20, 71, 0, // Skip to: 25344
+/* 7148 */    MCD_OPC_Decode, 209, 11, 145, 1, // Opcode: MVE_VQRDMULH_qr_s16
+/* 7153 */    MCD_OPC_FilterValue, 1, 10, 71, 0, // Skip to: 25344
+/* 7158 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7161 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7183
+/* 7166 */    MCD_OPC_CheckPredicate, 22, 253, 70, 0, // Skip to: 25344
+/* 7171 */    MCD_OPC_CheckField, 28, 4, 14, 246, 70, 0, // Skip to: 25344
+/* 7178 */    MCD_OPC_Decode, 153, 11, 144, 1, // Opcode: MVE_VQDMLASH_qrs16
+/* 7183 */    MCD_OPC_FilterValue, 1, 236, 70, 0, // Skip to: 25344
+/* 7188 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7191 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7206
+/* 7196 */    MCD_OPC_CheckPredicate, 22, 223, 70, 0, // Skip to: 25344
+/* 7201 */    MCD_OPC_Decode, 212, 10, 145, 1, // Opcode: MVE_VMUL_qr_i16
+/* 7206 */    MCD_OPC_FilterValue, 15, 213, 70, 0, // Skip to: 25344
+/* 7211 */    MCD_OPC_CheckPredicate, 22, 208, 70, 0, // Skip to: 25344
+/* 7216 */    MCD_OPC_Decode, 224, 7, 145, 1, // Opcode: MVE_VBRSR16
+/* 7221 */    MCD_OPC_FilterValue, 2, 227, 2, 0, // Skip to: 7965
+/* 7226 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 7229 */    MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 7701
+/* 7234 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 7237 */    MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 7469
+/* 7242 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 7245 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 7357
+/* 7250 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7253 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 7305
+/* 7258 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7261 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7283
+/* 7266 */    MCD_OPC_CheckPredicate, 22, 153, 70, 0, // Skip to: 25344
+/* 7271 */    MCD_OPC_CheckField, 4, 1, 0, 146, 70, 0, // Skip to: 25344
+/* 7278 */    MCD_OPC_Decode, 148, 11, 142, 1, // Opcode: MVE_VQDMLADHs32
+/* 7283 */    MCD_OPC_FilterValue, 15, 136, 70, 0, // Skip to: 25344
+/* 7288 */    MCD_OPC_CheckPredicate, 22, 131, 70, 0, // Skip to: 25344
+/* 7293 */    MCD_OPC_CheckField, 4, 1, 0, 124, 70, 0, // Skip to: 25344
+/* 7300 */    MCD_OPC_Decode, 160, 11, 142, 1, // Opcode: MVE_VQDMLSDHs32
+/* 7305 */    MCD_OPC_FilterValue, 1, 114, 70, 0, // Skip to: 25344
+/* 7310 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7313 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7335
+/* 7318 */    MCD_OPC_CheckPredicate, 22, 101, 70, 0, // Skip to: 25344
+/* 7323 */    MCD_OPC_CheckField, 4, 1, 0, 94, 70, 0, // Skip to: 25344
+/* 7330 */    MCD_OPC_Decode, 197, 10, 143, 1, // Opcode: MVE_VMULLBs32
+/* 7335 */    MCD_OPC_FilterValue, 15, 84, 70, 0, // Skip to: 25344
+/* 7340 */    MCD_OPC_CheckPredicate, 22, 79, 70, 0, // Skip to: 25344
+/* 7345 */    MCD_OPC_CheckField, 4, 1, 0, 72, 70, 0, // Skip to: 25344
+/* 7352 */    MCD_OPC_Decode, 200, 10, 143, 1, // Opcode: MVE_VMULLBu32
+/* 7357 */    MCD_OPC_FilterValue, 1, 62, 70, 0, // Skip to: 25344
+/* 7362 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7365 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 7417
+/* 7370 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7373 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7395
+/* 7378 */    MCD_OPC_CheckPredicate, 22, 41, 70, 0, // Skip to: 25344
+/* 7383 */    MCD_OPC_CheckField, 4, 1, 0, 34, 70, 0, // Skip to: 25344
+/* 7390 */    MCD_OPC_Decode, 145, 11, 142, 1, // Opcode: MVE_VQDMLADHXs32
+/* 7395 */    MCD_OPC_FilterValue, 15, 24, 70, 0, // Skip to: 25344
+/* 7400 */    MCD_OPC_CheckPredicate, 22, 19, 70, 0, // Skip to: 25344
+/* 7405 */    MCD_OPC_CheckField, 4, 1, 0, 12, 70, 0, // Skip to: 25344
+/* 7412 */    MCD_OPC_Decode, 157, 11, 142, 1, // Opcode: MVE_VQDMLSDHXs32
+/* 7417 */    MCD_OPC_FilterValue, 1, 2, 70, 0, // Skip to: 25344
+/* 7422 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7425 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7447
+/* 7430 */    MCD_OPC_CheckPredicate, 22, 245, 69, 0, // Skip to: 25344
+/* 7435 */    MCD_OPC_CheckField, 4, 1, 0, 238, 69, 0, // Skip to: 25344
+/* 7442 */    MCD_OPC_Decode, 205, 10, 143, 1, // Opcode: MVE_VMULLTs32
+/* 7447 */    MCD_OPC_FilterValue, 15, 228, 69, 0, // Skip to: 25344
+/* 7452 */    MCD_OPC_CheckPredicate, 22, 223, 69, 0, // Skip to: 25344
+/* 7457 */    MCD_OPC_CheckField, 4, 1, 0, 216, 69, 0, // Skip to: 25344
+/* 7464 */    MCD_OPC_Decode, 208, 10, 143, 1, // Opcode: MVE_VMULLTu32
+/* 7469 */    MCD_OPC_FilterValue, 1, 206, 69, 0, // Skip to: 25344
+/* 7474 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 7477 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 7589
+/* 7482 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7485 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 7537
+/* 7490 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7493 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7515
+/* 7498 */    MCD_OPC_CheckPredicate, 22, 177, 69, 0, // Skip to: 25344
+/* 7503 */    MCD_OPC_CheckField, 4, 1, 0, 170, 69, 0, // Skip to: 25344
+/* 7510 */    MCD_OPC_Decode, 195, 11, 142, 1, // Opcode: MVE_VQRDMLADHs32
+/* 7515 */    MCD_OPC_FilterValue, 15, 160, 69, 0, // Skip to: 25344
+/* 7520 */    MCD_OPC_CheckPredicate, 22, 155, 69, 0, // Skip to: 25344
+/* 7525 */    MCD_OPC_CheckField, 4, 1, 0, 148, 69, 0, // Skip to: 25344
+/* 7532 */    MCD_OPC_Decode, 207, 11, 142, 1, // Opcode: MVE_VQRDMLSDHs32
+/* 7537 */    MCD_OPC_FilterValue, 1, 138, 69, 0, // Skip to: 25344
+/* 7542 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7545 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7567
+/* 7550 */    MCD_OPC_CheckPredicate, 22, 125, 69, 0, // Skip to: 25344
+/* 7555 */    MCD_OPC_CheckField, 4, 1, 0, 118, 69, 0, // Skip to: 25344
+/* 7562 */    MCD_OPC_Decode, 189, 10, 143, 1, // Opcode: MVE_VMULHs32
+/* 7567 */    MCD_OPC_FilterValue, 15, 108, 69, 0, // Skip to: 25344
+/* 7572 */    MCD_OPC_CheckPredicate, 22, 103, 69, 0, // Skip to: 25344
+/* 7577 */    MCD_OPC_CheckField, 4, 1, 0, 96, 69, 0, // Skip to: 25344
+/* 7584 */    MCD_OPC_Decode, 192, 10, 143, 1, // Opcode: MVE_VMULHu32
+/* 7589 */    MCD_OPC_FilterValue, 1, 86, 69, 0, // Skip to: 25344
+/* 7594 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7597 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 7649
+/* 7602 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7605 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7627
+/* 7610 */    MCD_OPC_CheckPredicate, 22, 65, 69, 0, // Skip to: 25344
+/* 7615 */    MCD_OPC_CheckField, 4, 1, 0, 58, 69, 0, // Skip to: 25344
+/* 7622 */    MCD_OPC_Decode, 192, 11, 142, 1, // Opcode: MVE_VQRDMLADHXs32
+/* 7627 */    MCD_OPC_FilterValue, 15, 48, 69, 0, // Skip to: 25344
+/* 7632 */    MCD_OPC_CheckPredicate, 22, 43, 69, 0, // Skip to: 25344
+/* 7637 */    MCD_OPC_CheckField, 4, 1, 0, 36, 69, 0, // Skip to: 25344
+/* 7644 */    MCD_OPC_Decode, 204, 11, 142, 1, // Opcode: MVE_VQRDMLSDHXs32
+/* 7649 */    MCD_OPC_FilterValue, 1, 26, 69, 0, // Skip to: 25344
+/* 7654 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7657 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 7679
+/* 7662 */    MCD_OPC_CheckPredicate, 22, 13, 69, 0, // Skip to: 25344
+/* 7667 */    MCD_OPC_CheckField, 4, 1, 0, 6, 69, 0, // Skip to: 25344
+/* 7674 */    MCD_OPC_Decode, 191, 12, 143, 1, // Opcode: MVE_VRMULHs32
+/* 7679 */    MCD_OPC_FilterValue, 15, 252, 68, 0, // Skip to: 25344
+/* 7684 */    MCD_OPC_CheckPredicate, 22, 247, 68, 0, // Skip to: 25344
+/* 7689 */    MCD_OPC_CheckField, 4, 1, 0, 240, 68, 0, // Skip to: 25344
+/* 7696 */    MCD_OPC_Decode, 194, 12, 143, 1, // Opcode: MVE_VRMULHu32
+/* 7701 */    MCD_OPC_FilterValue, 1, 230, 68, 0, // Skip to: 25344
+/* 7706 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 7709 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 7821
+/* 7714 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 7717 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 7769
+/* 7722 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7725 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7747
+/* 7730 */    MCD_OPC_CheckPredicate, 22, 201, 68, 0, // Skip to: 25344
+/* 7735 */    MCD_OPC_CheckField, 28, 4, 14, 194, 68, 0, // Skip to: 25344
+/* 7742 */    MCD_OPC_Decode, 198, 11, 144, 1, // Opcode: MVE_VQRDMLAH_qrs32
+/* 7747 */    MCD_OPC_FilterValue, 1, 184, 68, 0, // Skip to: 25344
+/* 7752 */    MCD_OPC_CheckPredicate, 22, 179, 68, 0, // Skip to: 25344
+/* 7757 */    MCD_OPC_CheckField, 28, 4, 14, 172, 68, 0, // Skip to: 25344
+/* 7764 */    MCD_OPC_Decode, 139, 10, 144, 1, // Opcode: MVE_VMLA_qr_i32
+/* 7769 */    MCD_OPC_FilterValue, 1, 162, 68, 0, // Skip to: 25344
+/* 7774 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7777 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7799
+/* 7782 */    MCD_OPC_CheckPredicate, 22, 149, 68, 0, // Skip to: 25344
+/* 7787 */    MCD_OPC_CheckField, 28, 4, 14, 142, 68, 0, // Skip to: 25344
+/* 7794 */    MCD_OPC_Decode, 201, 11, 144, 1, // Opcode: MVE_VQRDMLASH_qrs32
+/* 7799 */    MCD_OPC_FilterValue, 1, 132, 68, 0, // Skip to: 25344
+/* 7804 */    MCD_OPC_CheckPredicate, 22, 127, 68, 0, // Skip to: 25344
+/* 7809 */    MCD_OPC_CheckField, 28, 4, 14, 120, 68, 0, // Skip to: 25344
+/* 7816 */    MCD_OPC_Decode, 136, 10, 144, 1, // Opcode: MVE_VMLAS_qr_i32
+/* 7821 */    MCD_OPC_FilterValue, 2, 110, 68, 0, // Skip to: 25344
+/* 7826 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 7829 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 7897
+/* 7834 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7837 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7859
+/* 7842 */    MCD_OPC_CheckPredicate, 22, 89, 68, 0, // Skip to: 25344
+/* 7847 */    MCD_OPC_CheckField, 28, 4, 14, 82, 68, 0, // Skip to: 25344
+/* 7854 */    MCD_OPC_Decode, 151, 11, 144, 1, // Opcode: MVE_VQDMLAH_qrs32
+/* 7859 */    MCD_OPC_FilterValue, 1, 72, 68, 0, // Skip to: 25344
+/* 7864 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7867 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7882
+/* 7872 */    MCD_OPC_CheckPredicate, 22, 59, 68, 0, // Skip to: 25344
+/* 7877 */    MCD_OPC_Decode, 163, 11, 145, 1, // Opcode: MVE_VQDMULH_qr_s32
+/* 7882 */    MCD_OPC_FilterValue, 15, 49, 68, 0, // Skip to: 25344
+/* 7887 */    MCD_OPC_CheckPredicate, 22, 44, 68, 0, // Skip to: 25344
+/* 7892 */    MCD_OPC_Decode, 210, 11, 145, 1, // Opcode: MVE_VQRDMULH_qr_s32
+/* 7897 */    MCD_OPC_FilterValue, 1, 34, 68, 0, // Skip to: 25344
+/* 7902 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7905 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7927
+/* 7910 */    MCD_OPC_CheckPredicate, 22, 21, 68, 0, // Skip to: 25344
+/* 7915 */    MCD_OPC_CheckField, 28, 4, 14, 14, 68, 0, // Skip to: 25344
+/* 7922 */    MCD_OPC_Decode, 154, 11, 144, 1, // Opcode: MVE_VQDMLASH_qrs32
+/* 7927 */    MCD_OPC_FilterValue, 1, 4, 68, 0, // Skip to: 25344
+/* 7932 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7935 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 7950
+/* 7940 */    MCD_OPC_CheckPredicate, 22, 247, 67, 0, // Skip to: 25344
+/* 7945 */    MCD_OPC_Decode, 213, 10, 145, 1, // Opcode: MVE_VMUL_qr_i32
+/* 7950 */    MCD_OPC_FilterValue, 15, 237, 67, 0, // Skip to: 25344
+/* 7955 */    MCD_OPC_CheckPredicate, 22, 232, 67, 0, // Skip to: 25344
+/* 7960 */    MCD_OPC_Decode, 225, 7, 145, 1, // Opcode: MVE_VBRSR32
+/* 7965 */    MCD_OPC_FilterValue, 3, 222, 67, 0, // Skip to: 25344
+/* 7970 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 7973 */    MCD_OPC_FilterValue, 0, 51, 5, 0, // Skip to: 9309
+/* 7978 */    MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 7981 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8033
+/* 7986 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 7989 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8011
+/* 7994 */    MCD_OPC_CheckPredicate, 24, 193, 67, 0, // Skip to: 25344
+/* 7999 */    MCD_OPC_CheckField, 4, 1, 0, 186, 67, 0, // Skip to: 25344
+/* 8006 */    MCD_OPC_Decode, 134, 8, 146, 1, // Opcode: MVE_VCMULf16
+/* 8011 */    MCD_OPC_FilterValue, 15, 176, 67, 0, // Skip to: 25344
+/* 8016 */    MCD_OPC_CheckPredicate, 24, 171, 67, 0, // Skip to: 25344
+/* 8021 */    MCD_OPC_CheckField, 4, 1, 0, 164, 67, 0, // Skip to: 25344
+/* 8028 */    MCD_OPC_Decode, 135, 8, 146, 1, // Opcode: MVE_VCMULf32
+/* 8033 */    MCD_OPC_FilterValue, 1, 154, 67, 0, // Skip to: 25344
+/* 8038 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 8041 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 8153
+/* 8046 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8049 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8101
+/* 8054 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8057 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8079
+/* 8062 */    MCD_OPC_CheckPredicate, 22, 125, 67, 0, // Skip to: 25344
+/* 8067 */    MCD_OPC_CheckField, 4, 1, 0, 118, 67, 0, // Skip to: 25344
+/* 8074 */    MCD_OPC_Decode, 195, 10, 143, 1, // Opcode: MVE_VMULLBp8
+/* 8079 */    MCD_OPC_FilterValue, 15, 108, 67, 0, // Skip to: 25344
+/* 8084 */    MCD_OPC_CheckPredicate, 22, 103, 67, 0, // Skip to: 25344
+/* 8089 */    MCD_OPC_CheckField, 4, 1, 0, 96, 67, 0, // Skip to: 25344
+/* 8096 */    MCD_OPC_Decode, 194, 10, 143, 1, // Opcode: MVE_VMULLBp16
+/* 8101 */    MCD_OPC_FilterValue, 1, 86, 67, 0, // Skip to: 25344
+/* 8106 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8109 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8131
+/* 8114 */    MCD_OPC_CheckPredicate, 22, 73, 67, 0, // Skip to: 25344
+/* 8119 */    MCD_OPC_CheckField, 4, 1, 0, 66, 67, 0, // Skip to: 25344
+/* 8126 */    MCD_OPC_Decode, 203, 10, 143, 1, // Opcode: MVE_VMULLTp8
+/* 8131 */    MCD_OPC_FilterValue, 15, 56, 67, 0, // Skip to: 25344
+/* 8136 */    MCD_OPC_CheckPredicate, 22, 51, 67, 0, // Skip to: 25344
+/* 8141 */    MCD_OPC_CheckField, 4, 1, 0, 44, 67, 0, // Skip to: 25344
+/* 8148 */    MCD_OPC_Decode, 202, 10, 143, 1, // Opcode: MVE_VMULLTp16
+/* 8153 */    MCD_OPC_FilterValue, 1, 34, 67, 0, // Skip to: 25344
+/* 8158 */    MCD_OPC_ExtractField, 17, 3,  // Inst{19-17} ...
+/* 8161 */    MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 8393
+/* 8166 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8169 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 8281
+/* 8174 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8177 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8229
+/* 8182 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8185 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8207
+/* 8190 */    MCD_OPC_CheckPredicate, 22, 253, 66, 0, // Skip to: 25344
+/* 8195 */    MCD_OPC_CheckField, 4, 1, 0, 246, 66, 0, // Skip to: 25344
+/* 8202 */    MCD_OPC_Decode, 231, 12, 147, 1, // Opcode: MVE_VSHLL_lws8bh
+/* 8207 */    MCD_OPC_FilterValue, 15, 236, 66, 0, // Skip to: 25344
+/* 8212 */    MCD_OPC_CheckPredicate, 22, 231, 66, 0, // Skip to: 25344
+/* 8217 */    MCD_OPC_CheckField, 4, 1, 0, 224, 66, 0, // Skip to: 25344
+/* 8224 */    MCD_OPC_Decode, 235, 12, 147, 1, // Opcode: MVE_VSHLL_lwu8bh
+/* 8229 */    MCD_OPC_FilterValue, 1, 214, 66, 0, // Skip to: 25344
+/* 8234 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8237 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8259
+/* 8242 */    MCD_OPC_CheckPredicate, 22, 201, 66, 0, // Skip to: 25344
+/* 8247 */    MCD_OPC_CheckField, 4, 1, 0, 194, 66, 0, // Skip to: 25344
+/* 8254 */    MCD_OPC_Decode, 232, 12, 147, 1, // Opcode: MVE_VSHLL_lws8th
+/* 8259 */    MCD_OPC_FilterValue, 15, 184, 66, 0, // Skip to: 25344
+/* 8264 */    MCD_OPC_CheckPredicate, 22, 179, 66, 0, // Skip to: 25344
+/* 8269 */    MCD_OPC_CheckField, 4, 1, 0, 172, 66, 0, // Skip to: 25344
+/* 8276 */    MCD_OPC_Decode, 236, 12, 147, 1, // Opcode: MVE_VSHLL_lwu8th
+/* 8281 */    MCD_OPC_FilterValue, 1, 162, 66, 0, // Skip to: 25344
+/* 8286 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8289 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8341
+/* 8294 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8297 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8319
+/* 8302 */    MCD_OPC_CheckPredicate, 22, 141, 66, 0, // Skip to: 25344
+/* 8307 */    MCD_OPC_CheckField, 4, 1, 0, 134, 66, 0, // Skip to: 25344
+/* 8314 */    MCD_OPC_Decode, 184, 11, 148, 1, // Opcode: MVE_VQMOVUNs16bh
+/* 8319 */    MCD_OPC_FilterValue, 15, 124, 66, 0, // Skip to: 25344
+/* 8324 */    MCD_OPC_CheckPredicate, 22, 119, 66, 0, // Skip to: 25344
+/* 8329 */    MCD_OPC_CheckField, 4, 1, 0, 112, 66, 0, // Skip to: 25344
+/* 8336 */    MCD_OPC_Decode, 169, 10, 148, 1, // Opcode: MVE_VMOVNi16bh
+/* 8341 */    MCD_OPC_FilterValue, 1, 102, 66, 0, // Skip to: 25344
+/* 8346 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8349 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8371
+/* 8354 */    MCD_OPC_CheckPredicate, 22, 89, 66, 0, // Skip to: 25344
+/* 8359 */    MCD_OPC_CheckField, 4, 1, 0, 82, 66, 0, // Skip to: 25344
+/* 8366 */    MCD_OPC_Decode, 185, 11, 148, 1, // Opcode: MVE_VQMOVUNs16th
+/* 8371 */    MCD_OPC_FilterValue, 15, 72, 66, 0, // Skip to: 25344
+/* 8376 */    MCD_OPC_CheckPredicate, 22, 67, 66, 0, // Skip to: 25344
+/* 8381 */    MCD_OPC_CheckField, 4, 1, 0, 60, 66, 0, // Skip to: 25344
+/* 8388 */    MCD_OPC_Decode, 170, 10, 148, 1, // Opcode: MVE_VMOVNi16th
+/* 8393 */    MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 8579
+/* 8398 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8401 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 8513
+/* 8406 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8409 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8461
+/* 8414 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8417 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8439
+/* 8422 */    MCD_OPC_CheckPredicate, 22, 21, 66, 0, // Skip to: 25344
+/* 8427 */    MCD_OPC_CheckField, 4, 1, 0, 14, 66, 0, // Skip to: 25344
+/* 8434 */    MCD_OPC_Decode, 176, 11, 148, 1, // Opcode: MVE_VQMOVNs16bh
+/* 8439 */    MCD_OPC_FilterValue, 15, 4, 66, 0, // Skip to: 25344
+/* 8444 */    MCD_OPC_CheckPredicate, 22, 255, 65, 0, // Skip to: 25344
+/* 8449 */    MCD_OPC_CheckField, 4, 1, 0, 248, 65, 0, // Skip to: 25344
+/* 8456 */    MCD_OPC_Decode, 180, 11, 148, 1, // Opcode: MVE_VQMOVNu16bh
+/* 8461 */    MCD_OPC_FilterValue, 1, 238, 65, 0, // Skip to: 25344
+/* 8466 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8469 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8491
+/* 8474 */    MCD_OPC_CheckPredicate, 22, 225, 65, 0, // Skip to: 25344
+/* 8479 */    MCD_OPC_CheckField, 4, 1, 0, 218, 65, 0, // Skip to: 25344
+/* 8486 */    MCD_OPC_Decode, 177, 11, 148, 1, // Opcode: MVE_VQMOVNs16th
+/* 8491 */    MCD_OPC_FilterValue, 15, 208, 65, 0, // Skip to: 25344
+/* 8496 */    MCD_OPC_CheckPredicate, 22, 203, 65, 0, // Skip to: 25344
+/* 8501 */    MCD_OPC_CheckField, 4, 1, 0, 196, 65, 0, // Skip to: 25344
+/* 8508 */    MCD_OPC_Decode, 181, 11, 148, 1, // Opcode: MVE_VQMOVNu16th
+/* 8513 */    MCD_OPC_FilterValue, 1, 186, 65, 0, // Skip to: 25344
+/* 8518 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8521 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 8550
+/* 8526 */    MCD_OPC_CheckPredicate, 22, 173, 65, 0, // Skip to: 25344
+/* 8531 */    MCD_OPC_CheckField, 28, 4, 14, 166, 65, 0, // Skip to: 25344
+/* 8538 */    MCD_OPC_CheckField, 4, 1, 0, 159, 65, 0, // Skip to: 25344
+/* 8545 */    MCD_OPC_Decode, 186, 9, 148, 1, // Opcode: MVE_VMAXAs8
+/* 8550 */    MCD_OPC_FilterValue, 1, 149, 65, 0, // Skip to: 25344
+/* 8555 */    MCD_OPC_CheckPredicate, 22, 144, 65, 0, // Skip to: 25344
+/* 8560 */    MCD_OPC_CheckField, 28, 4, 14, 137, 65, 0, // Skip to: 25344
+/* 8567 */    MCD_OPC_CheckField, 4, 1, 0, 130, 65, 0, // Skip to: 25344
+/* 8574 */    MCD_OPC_Decode, 212, 9, 148, 1, // Opcode: MVE_VMINAs8
+/* 8579 */    MCD_OPC_FilterValue, 2, 227, 0, 0, // Skip to: 8811
+/* 8584 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8587 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 8699
+/* 8592 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8595 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8647
+/* 8600 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8603 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8625
+/* 8608 */    MCD_OPC_CheckPredicate, 22, 91, 65, 0, // Skip to: 25344
+/* 8613 */    MCD_OPC_CheckField, 4, 1, 0, 84, 65, 0, // Skip to: 25344
+/* 8620 */    MCD_OPC_Decode, 229, 12, 147, 1, // Opcode: MVE_VSHLL_lws16bh
+/* 8625 */    MCD_OPC_FilterValue, 15, 74, 65, 0, // Skip to: 25344
+/* 8630 */    MCD_OPC_CheckPredicate, 22, 69, 65, 0, // Skip to: 25344
+/* 8635 */    MCD_OPC_CheckField, 4, 1, 0, 62, 65, 0, // Skip to: 25344
+/* 8642 */    MCD_OPC_Decode, 233, 12, 147, 1, // Opcode: MVE_VSHLL_lwu16bh
+/* 8647 */    MCD_OPC_FilterValue, 1, 52, 65, 0, // Skip to: 25344
+/* 8652 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8655 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8677
+/* 8660 */    MCD_OPC_CheckPredicate, 22, 39, 65, 0, // Skip to: 25344
+/* 8665 */    MCD_OPC_CheckField, 4, 1, 0, 32, 65, 0, // Skip to: 25344
+/* 8672 */    MCD_OPC_Decode, 230, 12, 147, 1, // Opcode: MVE_VSHLL_lws16th
+/* 8677 */    MCD_OPC_FilterValue, 15, 22, 65, 0, // Skip to: 25344
+/* 8682 */    MCD_OPC_CheckPredicate, 22, 17, 65, 0, // Skip to: 25344
+/* 8687 */    MCD_OPC_CheckField, 4, 1, 0, 10, 65, 0, // Skip to: 25344
+/* 8694 */    MCD_OPC_Decode, 234, 12, 147, 1, // Opcode: MVE_VSHLL_lwu16th
+/* 8699 */    MCD_OPC_FilterValue, 1, 0, 65, 0, // Skip to: 25344
+/* 8704 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8707 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8759
+/* 8712 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8715 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8737
+/* 8720 */    MCD_OPC_CheckPredicate, 22, 235, 64, 0, // Skip to: 25344
+/* 8725 */    MCD_OPC_CheckField, 4, 1, 0, 228, 64, 0, // Skip to: 25344
+/* 8732 */    MCD_OPC_Decode, 186, 11, 148, 1, // Opcode: MVE_VQMOVUNs32bh
+/* 8737 */    MCD_OPC_FilterValue, 15, 218, 64, 0, // Skip to: 25344
+/* 8742 */    MCD_OPC_CheckPredicate, 22, 213, 64, 0, // Skip to: 25344
+/* 8747 */    MCD_OPC_CheckField, 4, 1, 0, 206, 64, 0, // Skip to: 25344
+/* 8754 */    MCD_OPC_Decode, 171, 10, 148, 1, // Opcode: MVE_VMOVNi32bh
+/* 8759 */    MCD_OPC_FilterValue, 1, 196, 64, 0, // Skip to: 25344
+/* 8764 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8767 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8789
+/* 8772 */    MCD_OPC_CheckPredicate, 22, 183, 64, 0, // Skip to: 25344
+/* 8777 */    MCD_OPC_CheckField, 4, 1, 0, 176, 64, 0, // Skip to: 25344
+/* 8784 */    MCD_OPC_Decode, 187, 11, 148, 1, // Opcode: MVE_VQMOVUNs32th
+/* 8789 */    MCD_OPC_FilterValue, 15, 166, 64, 0, // Skip to: 25344
+/* 8794 */    MCD_OPC_CheckPredicate, 22, 161, 64, 0, // Skip to: 25344
+/* 8799 */    MCD_OPC_CheckField, 4, 1, 0, 154, 64, 0, // Skip to: 25344
+/* 8806 */    MCD_OPC_Decode, 172, 10, 148, 1, // Opcode: MVE_VMOVNi32th
+/* 8811 */    MCD_OPC_FilterValue, 3, 181, 0, 0, // Skip to: 8997
+/* 8816 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 8819 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 8931
+/* 8824 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8827 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 8879
+/* 8832 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8835 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8857
+/* 8840 */    MCD_OPC_CheckPredicate, 22, 115, 64, 0, // Skip to: 25344
+/* 8845 */    MCD_OPC_CheckField, 4, 1, 0, 108, 64, 0, // Skip to: 25344
+/* 8852 */    MCD_OPC_Decode, 178, 11, 148, 1, // Opcode: MVE_VQMOVNs32bh
+/* 8857 */    MCD_OPC_FilterValue, 15, 98, 64, 0, // Skip to: 25344
+/* 8862 */    MCD_OPC_CheckPredicate, 22, 93, 64, 0, // Skip to: 25344
+/* 8867 */    MCD_OPC_CheckField, 4, 1, 0, 86, 64, 0, // Skip to: 25344
+/* 8874 */    MCD_OPC_Decode, 182, 11, 148, 1, // Opcode: MVE_VQMOVNu32bh
+/* 8879 */    MCD_OPC_FilterValue, 1, 76, 64, 0, // Skip to: 25344
+/* 8884 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 8887 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 8909
+/* 8892 */    MCD_OPC_CheckPredicate, 22, 63, 64, 0, // Skip to: 25344
+/* 8897 */    MCD_OPC_CheckField, 4, 1, 0, 56, 64, 0, // Skip to: 25344
+/* 8904 */    MCD_OPC_Decode, 179, 11, 148, 1, // Opcode: MVE_VQMOVNs32th
+/* 8909 */    MCD_OPC_FilterValue, 15, 46, 64, 0, // Skip to: 25344
+/* 8914 */    MCD_OPC_CheckPredicate, 22, 41, 64, 0, // Skip to: 25344
+/* 8919 */    MCD_OPC_CheckField, 4, 1, 0, 34, 64, 0, // Skip to: 25344
+/* 8926 */    MCD_OPC_Decode, 183, 11, 148, 1, // Opcode: MVE_VQMOVNu32th
+/* 8931 */    MCD_OPC_FilterValue, 1, 24, 64, 0, // Skip to: 25344
+/* 8936 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 8939 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 8968
+/* 8944 */    MCD_OPC_CheckPredicate, 22, 11, 64, 0, // Skip to: 25344
+/* 8949 */    MCD_OPC_CheckField, 28, 4, 14, 4, 64, 0, // Skip to: 25344
+/* 8956 */    MCD_OPC_CheckField, 4, 1, 0, 253, 63, 0, // Skip to: 25344
+/* 8963 */    MCD_OPC_Decode, 184, 9, 148, 1, // Opcode: MVE_VMAXAs16
+/* 8968 */    MCD_OPC_FilterValue, 1, 243, 63, 0, // Skip to: 25344
+/* 8973 */    MCD_OPC_CheckPredicate, 22, 238, 63, 0, // Skip to: 25344
+/* 8978 */    MCD_OPC_CheckField, 28, 4, 14, 231, 63, 0, // Skip to: 25344
+/* 8985 */    MCD_OPC_CheckField, 4, 1, 0, 224, 63, 0, // Skip to: 25344
+/* 8992 */    MCD_OPC_Decode, 210, 9, 148, 1, // Opcode: MVE_VMINAs16
+/* 8997 */    MCD_OPC_FilterValue, 5, 75, 0, 0, // Skip to: 9077
+/* 9002 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 9005 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9041
+/* 9010 */    MCD_OPC_CheckPredicate, 22, 201, 63, 0, // Skip to: 25344
+/* 9015 */    MCD_OPC_CheckField, 28, 4, 14, 194, 63, 0, // Skip to: 25344
+/* 9022 */    MCD_OPC_CheckField, 7, 1, 1, 187, 63, 0, // Skip to: 25344
+/* 9029 */    MCD_OPC_CheckField, 4, 1, 0, 180, 63, 0, // Skip to: 25344
+/* 9036 */    MCD_OPC_Decode, 185, 9, 148, 1, // Opcode: MVE_VMAXAs32
+/* 9041 */    MCD_OPC_FilterValue, 1, 170, 63, 0, // Skip to: 25344
+/* 9046 */    MCD_OPC_CheckPredicate, 22, 165, 63, 0, // Skip to: 25344
+/* 9051 */    MCD_OPC_CheckField, 28, 4, 14, 158, 63, 0, // Skip to: 25344
+/* 9058 */    MCD_OPC_CheckField, 7, 1, 1, 151, 63, 0, // Skip to: 25344
+/* 9065 */    MCD_OPC_CheckField, 4, 1, 0, 144, 63, 0, // Skip to: 25344
+/* 9072 */    MCD_OPC_Decode, 211, 9, 148, 1, // Opcode: MVE_VMINAs32
+/* 9077 */    MCD_OPC_FilterValue, 7, 134, 63, 0, // Skip to: 25344
+/* 9082 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9085 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 9197
+/* 9090 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 9093 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 9145
+/* 9098 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9101 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9123
+/* 9106 */    MCD_OPC_CheckPredicate, 24, 105, 63, 0, // Skip to: 25344
+/* 9111 */    MCD_OPC_CheckField, 4, 1, 0, 98, 63, 0, // Skip to: 25344
+/* 9118 */    MCD_OPC_Decode, 140, 8, 148, 1, // Opcode: MVE_VCVTf16f32bh
+/* 9123 */    MCD_OPC_FilterValue, 15, 88, 63, 0, // Skip to: 25344
+/* 9128 */    MCD_OPC_CheckPredicate, 24, 83, 63, 0, // Skip to: 25344
+/* 9133 */    MCD_OPC_CheckField, 4, 1, 0, 76, 63, 0, // Skip to: 25344
+/* 9140 */    MCD_OPC_Decode, 146, 8, 147, 1, // Opcode: MVE_VCVTf32f16bh
+/* 9145 */    MCD_OPC_FilterValue, 1, 66, 63, 0, // Skip to: 25344
+/* 9150 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9153 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9175
+/* 9158 */    MCD_OPC_CheckPredicate, 24, 53, 63, 0, // Skip to: 25344
+/* 9163 */    MCD_OPC_CheckField, 4, 1, 0, 46, 63, 0, // Skip to: 25344
+/* 9170 */    MCD_OPC_Decode, 141, 8, 148, 1, // Opcode: MVE_VCVTf16f32th
+/* 9175 */    MCD_OPC_FilterValue, 15, 36, 63, 0, // Skip to: 25344
+/* 9180 */    MCD_OPC_CheckPredicate, 24, 31, 63, 0, // Skip to: 25344
+/* 9185 */    MCD_OPC_CheckField, 4, 1, 0, 24, 63, 0, // Skip to: 25344
+/* 9192 */    MCD_OPC_Decode, 147, 8, 147, 1, // Opcode: MVE_VCVTf32f16th
+/* 9197 */    MCD_OPC_FilterValue, 1, 14, 63, 0, // Skip to: 25344
+/* 9202 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 9205 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 9257
+/* 9210 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9213 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9235
+/* 9218 */    MCD_OPC_CheckPredicate, 24, 249, 62, 0, // Skip to: 25344
+/* 9223 */    MCD_OPC_CheckField, 4, 1, 0, 242, 62, 0, // Skip to: 25344
+/* 9230 */    MCD_OPC_Decode, 190, 9, 148, 1, // Opcode: MVE_VMAXNMAf32
+/* 9235 */    MCD_OPC_FilterValue, 15, 232, 62, 0, // Skip to: 25344
+/* 9240 */    MCD_OPC_CheckPredicate, 24, 227, 62, 0, // Skip to: 25344
+/* 9245 */    MCD_OPC_CheckField, 4, 1, 0, 220, 62, 0, // Skip to: 25344
+/* 9252 */    MCD_OPC_Decode, 189, 9, 148, 1, // Opcode: MVE_VMAXNMAf16
+/* 9257 */    MCD_OPC_FilterValue, 1, 210, 62, 0, // Skip to: 25344
+/* 9262 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9265 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9287
+/* 9270 */    MCD_OPC_CheckPredicate, 24, 197, 62, 0, // Skip to: 25344
+/* 9275 */    MCD_OPC_CheckField, 4, 1, 0, 190, 62, 0, // Skip to: 25344
+/* 9282 */    MCD_OPC_Decode, 216, 9, 148, 1, // Opcode: MVE_VMINNMAf32
+/* 9287 */    MCD_OPC_FilterValue, 15, 180, 62, 0, // Skip to: 25344
+/* 9292 */    MCD_OPC_CheckPredicate, 24, 175, 62, 0, // Skip to: 25344
+/* 9297 */    MCD_OPC_CheckField, 4, 1, 0, 168, 62, 0, // Skip to: 25344
+/* 9304 */    MCD_OPC_Decode, 215, 9, 148, 1, // Opcode: MVE_VMINNMAf16
+/* 9309 */    MCD_OPC_FilterValue, 1, 158, 62, 0, // Skip to: 25344
+/* 9314 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 9317 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 9429
+/* 9322 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 9325 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 9377
+/* 9330 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9333 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9355
+/* 9338 */    MCD_OPC_CheckPredicate, 24, 129, 62, 0, // Skip to: 25344
+/* 9343 */    MCD_OPC_CheckField, 16, 1, 1, 122, 62, 0, // Skip to: 25344
+/* 9350 */    MCD_OPC_Decode, 189, 8, 144, 1, // Opcode: MVE_VFMA_qr_f32
+/* 9355 */    MCD_OPC_FilterValue, 15, 112, 62, 0, // Skip to: 25344
+/* 9360 */    MCD_OPC_CheckPredicate, 24, 107, 62, 0, // Skip to: 25344
+/* 9365 */    MCD_OPC_CheckField, 16, 1, 1, 100, 62, 0, // Skip to: 25344
+/* 9372 */    MCD_OPC_Decode, 188, 8, 144, 1, // Opcode: MVE_VFMA_qr_f16
+/* 9377 */    MCD_OPC_FilterValue, 1, 90, 62, 0, // Skip to: 25344
+/* 9382 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9385 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9407
+/* 9390 */    MCD_OPC_CheckPredicate, 24, 77, 62, 0, // Skip to: 25344
+/* 9395 */    MCD_OPC_CheckField, 16, 1, 1, 70, 62, 0, // Skip to: 25344
+/* 9402 */    MCD_OPC_Decode, 187, 8, 144, 1, // Opcode: MVE_VFMA_qr_Sf32
+/* 9407 */    MCD_OPC_FilterValue, 15, 60, 62, 0, // Skip to: 25344
+/* 9412 */    MCD_OPC_CheckPredicate, 24, 55, 62, 0, // Skip to: 25344
+/* 9417 */    MCD_OPC_CheckField, 16, 1, 1, 48, 62, 0, // Skip to: 25344
+/* 9424 */    MCD_OPC_Decode, 186, 8, 144, 1, // Opcode: MVE_VFMA_qr_Sf16
+/* 9429 */    MCD_OPC_FilterValue, 2, 38, 62, 0, // Skip to: 25344
+/* 9434 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 9437 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 9489
+/* 9442 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9445 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 9467
+/* 9450 */    MCD_OPC_CheckPredicate, 24, 17, 62, 0, // Skip to: 25344
+/* 9455 */    MCD_OPC_CheckField, 16, 1, 1, 10, 62, 0, // Skip to: 25344
+/* 9462 */    MCD_OPC_Decode, 211, 10, 145, 1, // Opcode: MVE_VMUL_qr_f32
+/* 9467 */    MCD_OPC_FilterValue, 15, 0, 62, 0, // Skip to: 25344
+/* 9472 */    MCD_OPC_CheckPredicate, 24, 251, 61, 0, // Skip to: 25344
+/* 9477 */    MCD_OPC_CheckField, 16, 1, 1, 244, 61, 0, // Skip to: 25344
+/* 9484 */    MCD_OPC_Decode, 210, 10, 145, 1, // Opcode: MVE_VMUL_qr_f16
+/* 9489 */    MCD_OPC_FilterValue, 1, 234, 61, 0, // Skip to: 25344
+/* 9494 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 9497 */    MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 9581
+/* 9502 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9505 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 9543
+/* 9510 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9513 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9528
+/* 9518 */    MCD_OPC_CheckPredicate, 22, 205, 61, 0, // Skip to: 25344
+/* 9523 */    MCD_OPC_Decode, 248, 12, 149, 1, // Opcode: MVE_VSHL_qrs8
+/* 9528 */    MCD_OPC_FilterValue, 15, 195, 61, 0, // Skip to: 25344
+/* 9533 */    MCD_OPC_CheckPredicate, 22, 190, 61, 0, // Skip to: 25344
+/* 9538 */    MCD_OPC_Decode, 251, 12, 149, 1, // Opcode: MVE_VSHL_qru8
+/* 9543 */    MCD_OPC_FilterValue, 1, 180, 61, 0, // Skip to: 25344
+/* 9548 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9551 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9566
+/* 9556 */    MCD_OPC_CheckPredicate, 22, 167, 61, 0, // Skip to: 25344
+/* 9561 */    MCD_OPC_Decode, 250, 11, 149, 1, // Opcode: MVE_VQSHL_qrs8
+/* 9566 */    MCD_OPC_FilterValue, 15, 157, 61, 0, // Skip to: 25344
+/* 9571 */    MCD_OPC_CheckPredicate, 22, 152, 61, 0, // Skip to: 25344
+/* 9576 */    MCD_OPC_Decode, 253, 11, 149, 1, // Opcode: MVE_VQSHL_qru8
+/* 9581 */    MCD_OPC_FilterValue, 3, 79, 0, 0, // Skip to: 9665
+/* 9586 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9589 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 9627
+/* 9594 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9597 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9612
+/* 9602 */    MCD_OPC_CheckPredicate, 22, 121, 61, 0, // Skip to: 25344
+/* 9607 */    MCD_OPC_Decode, 204, 12, 149, 1, // Opcode: MVE_VRSHL_qrs8
+/* 9612 */    MCD_OPC_FilterValue, 15, 111, 61, 0, // Skip to: 25344
+/* 9617 */    MCD_OPC_CheckPredicate, 22, 106, 61, 0, // Skip to: 25344
+/* 9622 */    MCD_OPC_Decode, 207, 12, 149, 1, // Opcode: MVE_VRSHL_qru8
+/* 9627 */    MCD_OPC_FilterValue, 1, 96, 61, 0, // Skip to: 25344
+/* 9632 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9635 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9650
+/* 9640 */    MCD_OPC_CheckPredicate, 22, 83, 61, 0, // Skip to: 25344
+/* 9645 */    MCD_OPC_Decode, 223, 11, 149, 1, // Opcode: MVE_VQRSHL_qrs8
+/* 9650 */    MCD_OPC_FilterValue, 15, 73, 61, 0, // Skip to: 25344
+/* 9655 */    MCD_OPC_CheckPredicate, 22, 68, 61, 0, // Skip to: 25344
+/* 9660 */    MCD_OPC_Decode, 226, 11, 149, 1, // Opcode: MVE_VQRSHL_qru8
+/* 9665 */    MCD_OPC_FilterValue, 5, 79, 0, 0, // Skip to: 9749
+/* 9670 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9673 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 9711
+/* 9678 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9681 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9696
+/* 9686 */    MCD_OPC_CheckPredicate, 22, 37, 61, 0, // Skip to: 25344
+/* 9691 */    MCD_OPC_Decode, 246, 12, 149, 1, // Opcode: MVE_VSHL_qrs16
+/* 9696 */    MCD_OPC_FilterValue, 15, 27, 61, 0, // Skip to: 25344
+/* 9701 */    MCD_OPC_CheckPredicate, 22, 22, 61, 0, // Skip to: 25344
+/* 9706 */    MCD_OPC_Decode, 249, 12, 149, 1, // Opcode: MVE_VSHL_qru16
+/* 9711 */    MCD_OPC_FilterValue, 1, 12, 61, 0, // Skip to: 25344
+/* 9716 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9719 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9734
+/* 9724 */    MCD_OPC_CheckPredicate, 22, 255, 60, 0, // Skip to: 25344
+/* 9729 */    MCD_OPC_Decode, 248, 11, 149, 1, // Opcode: MVE_VQSHL_qrs16
+/* 9734 */    MCD_OPC_FilterValue, 15, 245, 60, 0, // Skip to: 25344
+/* 9739 */    MCD_OPC_CheckPredicate, 22, 240, 60, 0, // Skip to: 25344
+/* 9744 */    MCD_OPC_Decode, 251, 11, 149, 1, // Opcode: MVE_VQSHL_qru16
+/* 9749 */    MCD_OPC_FilterValue, 7, 79, 0, 0, // Skip to: 9833
+/* 9754 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9757 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 9795
+/* 9762 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9765 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9780
+/* 9770 */    MCD_OPC_CheckPredicate, 22, 209, 60, 0, // Skip to: 25344
+/* 9775 */    MCD_OPC_Decode, 202, 12, 149, 1, // Opcode: MVE_VRSHL_qrs16
+/* 9780 */    MCD_OPC_FilterValue, 15, 199, 60, 0, // Skip to: 25344
+/* 9785 */    MCD_OPC_CheckPredicate, 22, 194, 60, 0, // Skip to: 25344
+/* 9790 */    MCD_OPC_Decode, 205, 12, 149, 1, // Opcode: MVE_VRSHL_qru16
+/* 9795 */    MCD_OPC_FilterValue, 1, 184, 60, 0, // Skip to: 25344
+/* 9800 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9803 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9818
+/* 9808 */    MCD_OPC_CheckPredicate, 22, 171, 60, 0, // Skip to: 25344
+/* 9813 */    MCD_OPC_Decode, 221, 11, 149, 1, // Opcode: MVE_VQRSHL_qrs16
+/* 9818 */    MCD_OPC_FilterValue, 15, 161, 60, 0, // Skip to: 25344
+/* 9823 */    MCD_OPC_CheckPredicate, 22, 156, 60, 0, // Skip to: 25344
+/* 9828 */    MCD_OPC_Decode, 224, 11, 149, 1, // Opcode: MVE_VQRSHL_qru16
+/* 9833 */    MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 9917
+/* 9838 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9841 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 9879
+/* 9846 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9849 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9864
+/* 9854 */    MCD_OPC_CheckPredicate, 22, 125, 60, 0, // Skip to: 25344
+/* 9859 */    MCD_OPC_Decode, 247, 12, 149, 1, // Opcode: MVE_VSHL_qrs32
+/* 9864 */    MCD_OPC_FilterValue, 15, 115, 60, 0, // Skip to: 25344
+/* 9869 */    MCD_OPC_CheckPredicate, 22, 110, 60, 0, // Skip to: 25344
+/* 9874 */    MCD_OPC_Decode, 250, 12, 149, 1, // Opcode: MVE_VSHL_qru32
+/* 9879 */    MCD_OPC_FilterValue, 1, 100, 60, 0, // Skip to: 25344
+/* 9884 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9887 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9902
+/* 9892 */    MCD_OPC_CheckPredicate, 22, 87, 60, 0, // Skip to: 25344
+/* 9897 */    MCD_OPC_Decode, 249, 11, 149, 1, // Opcode: MVE_VQSHL_qrs32
+/* 9902 */    MCD_OPC_FilterValue, 15, 77, 60, 0, // Skip to: 25344
+/* 9907 */    MCD_OPC_CheckPredicate, 22, 72, 60, 0, // Skip to: 25344
+/* 9912 */    MCD_OPC_Decode, 252, 11, 149, 1, // Opcode: MVE_VQSHL_qru32
+/* 9917 */    MCD_OPC_FilterValue, 11, 62, 60, 0, // Skip to: 25344
+/* 9922 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 9925 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 9963
+/* 9930 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9933 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9948
+/* 9938 */    MCD_OPC_CheckPredicate, 22, 41, 60, 0, // Skip to: 25344
+/* 9943 */    MCD_OPC_Decode, 203, 12, 149, 1, // Opcode: MVE_VRSHL_qrs32
+/* 9948 */    MCD_OPC_FilterValue, 15, 31, 60, 0, // Skip to: 25344
+/* 9953 */    MCD_OPC_CheckPredicate, 22, 26, 60, 0, // Skip to: 25344
+/* 9958 */    MCD_OPC_Decode, 206, 12, 149, 1, // Opcode: MVE_VRSHL_qru32
+/* 9963 */    MCD_OPC_FilterValue, 1, 16, 60, 0, // Skip to: 25344
+/* 9968 */    MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 9971 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 9986
+/* 9976 */    MCD_OPC_CheckPredicate, 22, 3, 60, 0, // Skip to: 25344
+/* 9981 */    MCD_OPC_Decode, 222, 11, 149, 1, // Opcode: MVE_VQRSHL_qrs32
+/* 9986 */    MCD_OPC_FilterValue, 15, 249, 59, 0, // Skip to: 25344
+/* 9991 */    MCD_OPC_CheckPredicate, 22, 244, 59, 0, // Skip to: 25344
+/* 9996 */    MCD_OPC_Decode, 225, 11, 149, 1, // Opcode: MVE_VQRSHL_qru32
+/* 10001 */   MCD_OPC_FilterValue, 15, 234, 59, 0, // Skip to: 25344
+/* 10006 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 10009 */   MCD_OPC_FilterValue, 0, 197, 2, 0, // Skip to: 10723
+/* 10014 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10017 */   MCD_OPC_FilterValue, 0, 250, 0, 0, // Skip to: 10272
+/* 10022 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10025 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10091
+/* 10030 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10033 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10062
+/* 10038 */   MCD_OPC_CheckPredicate, 22, 197, 59, 0, // Skip to: 25344
+/* 10043 */   MCD_OPC_CheckField, 4, 1, 0, 190, 59, 0, // Skip to: 25344
+/* 10050 */   MCD_OPC_CheckField, 0, 1, 0, 183, 59, 0, // Skip to: 25344
+/* 10057 */   MCD_OPC_Decode, 208, 8, 150, 1, // Opcode: MVE_VHCADDs8
+/* 10062 */   MCD_OPC_FilterValue, 15, 173, 59, 0, // Skip to: 25344
+/* 10067 */   MCD_OPC_CheckPredicate, 22, 168, 59, 0, // Skip to: 25344
+/* 10072 */   MCD_OPC_CheckField, 4, 1, 0, 161, 59, 0, // Skip to: 25344
+/* 10079 */   MCD_OPC_CheckField, 0, 1, 0, 154, 59, 0, // Skip to: 25344
+/* 10086 */   MCD_OPC_Decode, 231, 7, 150, 1, // Opcode: MVE_VCADDi8
+/* 10091 */   MCD_OPC_FilterValue, 1, 144, 59, 0, // Skip to: 25344
+/* 10096 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 10099 */   MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 10217
+/* 10104 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 10107 */   MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 10162
+/* 10112 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10115 */   MCD_OPC_FilterValue, 0, 120, 59, 0, // Skip to: 25344
+/* 10120 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10123 */   MCD_OPC_FilterValue, 15, 112, 59, 0, // Skip to: 25344
+/* 10128 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10152
+/* 10133 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10152
+/* 10140 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10152
+/* 10147 */   MCD_OPC_Decode, 248, 7, 151, 1, // Opcode: MVE_VCMPi8
+/* 10152 */   MCD_OPC_CheckPredicate, 22, 83, 59, 0, // Skip to: 25344
+/* 10157 */   MCD_OPC_Decode, 235, 10, 152, 1, // Opcode: MVE_VPTv16i8
+/* 10162 */   MCD_OPC_FilterValue, 1, 73, 59, 0, // Skip to: 25344
+/* 10167 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10170 */   MCD_OPC_FilterValue, 0, 65, 59, 0, // Skip to: 25344
+/* 10175 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10178 */   MCD_OPC_FilterValue, 15, 57, 59, 0, // Skip to: 25344
+/* 10183 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10207
+/* 10188 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10207
+/* 10195 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10207
+/* 10202 */   MCD_OPC_Decode, 132, 8, 153, 1, // Opcode: MVE_VCMPu8
+/* 10207 */   MCD_OPC_CheckPredicate, 22, 28, 59, 0, // Skip to: 25344
+/* 10212 */   MCD_OPC_Decode, 239, 10, 154, 1, // Opcode: MVE_VPTv16u8
+/* 10217 */   MCD_OPC_FilterValue, 1, 18, 59, 0, // Skip to: 25344
+/* 10222 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10225 */   MCD_OPC_FilterValue, 0, 10, 59, 0, // Skip to: 25344
+/* 10230 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10233 */   MCD_OPC_FilterValue, 15, 2, 59, 0, // Skip to: 25344
+/* 10238 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10262
+/* 10243 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10262
+/* 10250 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10262
+/* 10257 */   MCD_OPC_Decode, 254, 7, 155, 1, // Opcode: MVE_VCMPs8
+/* 10262 */   MCD_OPC_CheckPredicate, 22, 229, 58, 0, // Skip to: 25344
+/* 10267 */   MCD_OPC_Decode, 237, 10, 156, 1, // Opcode: MVE_VPTv16s8
+/* 10272 */   MCD_OPC_FilterValue, 1, 219, 58, 0, // Skip to: 25344
+/* 10277 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 10280 */   MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 10521
+/* 10285 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 10288 */   MCD_OPC_FilterValue, 0, 103, 0, 0, // Skip to: 10396
+/* 10293 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10296 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10334
+/* 10301 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10304 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10319
+/* 10309 */   MCD_OPC_CheckPredicate, 22, 182, 58, 0, // Skip to: 25344
+/* 10314 */   MCD_OPC_Decode, 196, 8, 145, 1, // Opcode: MVE_VHADD_qr_s8
+/* 10319 */   MCD_OPC_FilterValue, 15, 172, 58, 0, // Skip to: 25344
+/* 10324 */   MCD_OPC_CheckPredicate, 22, 167, 58, 0, // Skip to: 25344
+/* 10329 */   MCD_OPC_Decode, 199, 8, 145, 1, // Opcode: MVE_VHADD_qr_u8
+/* 10334 */   MCD_OPC_FilterValue, 1, 157, 58, 0, // Skip to: 25344
+/* 10339 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10342 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10357
+/* 10347 */   MCD_OPC_CheckPredicate, 22, 144, 58, 0, // Skip to: 25344
+/* 10352 */   MCD_OPC_Decode, 214, 7, 145, 1, // Opcode: MVE_VADD_qr_i8
+/* 10357 */   MCD_OPC_FilterValue, 15, 134, 58, 0, // Skip to: 25344
+/* 10362 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10386
+/* 10367 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10386
+/* 10374 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10386
+/* 10381 */   MCD_OPC_Decode, 249, 7, 157, 1, // Opcode: MVE_VCMPi8r
+/* 10386 */   MCD_OPC_CheckPredicate, 22, 105, 58, 0, // Skip to: 25344
+/* 10391 */   MCD_OPC_Decode, 236, 10, 158, 1, // Opcode: MVE_VPTv16i8r
+/* 10396 */   MCD_OPC_FilterValue, 2, 95, 58, 0, // Skip to: 25344
+/* 10401 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10404 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10442
+/* 10409 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10412 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10427
+/* 10417 */   MCD_OPC_CheckPredicate, 22, 74, 58, 0, // Skip to: 25344
+/* 10422 */   MCD_OPC_Decode, 134, 11, 145, 1, // Opcode: MVE_VQADD_qr_s8
+/* 10427 */   MCD_OPC_FilterValue, 15, 64, 58, 0, // Skip to: 25344
+/* 10432 */   MCD_OPC_CheckPredicate, 22, 59, 58, 0, // Skip to: 25344
+/* 10437 */   MCD_OPC_Decode, 137, 11, 145, 1, // Opcode: MVE_VQADD_qr_u8
+/* 10442 */   MCD_OPC_FilterValue, 1, 49, 58, 0, // Skip to: 25344
+/* 10447 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10450 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 10482
+/* 10455 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 10472
+/* 10460 */   MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 10472
+/* 10467 */   MCD_OPC_Decode, 223, 8, 159, 1, // Opcode: MVE_VIDUPu8
+/* 10472 */   MCD_OPC_CheckPredicate, 22, 19, 58, 0, // Skip to: 25344
+/* 10477 */   MCD_OPC_Decode, 226, 8, 160, 1, // Opcode: MVE_VIWDUPu8
+/* 10482 */   MCD_OPC_FilterValue, 15, 9, 58, 0, // Skip to: 25344
+/* 10487 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10511
+/* 10492 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10511
+/* 10499 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10511
+/* 10506 */   MCD_OPC_Decode, 133, 8, 161, 1, // Opcode: MVE_VCMPu8r
+/* 10511 */   MCD_OPC_CheckPredicate, 22, 236, 57, 0, // Skip to: 25344
+/* 10516 */   MCD_OPC_Decode, 240, 10, 162, 1, // Opcode: MVE_VPTv16u8r
+/* 10521 */   MCD_OPC_FilterValue, 1, 226, 57, 0, // Skip to: 25344
+/* 10526 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10529 */   MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 10613
+/* 10534 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 10537 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10575
+/* 10542 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10545 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10560
+/* 10550 */   MCD_OPC_CheckPredicate, 22, 197, 57, 0, // Skip to: 25344
+/* 10555 */   MCD_OPC_Decode, 211, 8, 145, 1, // Opcode: MVE_VHSUB_qr_s8
+/* 10560 */   MCD_OPC_FilterValue, 15, 187, 57, 0, // Skip to: 25344
+/* 10565 */   MCD_OPC_CheckPredicate, 22, 182, 57, 0, // Skip to: 25344
+/* 10570 */   MCD_OPC_Decode, 214, 8, 145, 1, // Opcode: MVE_VHSUB_qr_u8
+/* 10575 */   MCD_OPC_FilterValue, 2, 172, 57, 0, // Skip to: 25344
+/* 10580 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10583 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 10598
+/* 10588 */   MCD_OPC_CheckPredicate, 22, 159, 57, 0, // Skip to: 25344
+/* 10593 */   MCD_OPC_Decode, 146, 12, 145, 1, // Opcode: MVE_VQSUB_qr_s8
+/* 10598 */   MCD_OPC_FilterValue, 15, 149, 57, 0, // Skip to: 25344
+/* 10603 */   MCD_OPC_CheckPredicate, 22, 144, 57, 0, // Skip to: 25344
+/* 10608 */   MCD_OPC_Decode, 149, 12, 145, 1, // Opcode: MVE_VQSUB_qr_u8
+/* 10613 */   MCD_OPC_FilterValue, 1, 134, 57, 0, // Skip to: 25344
+/* 10618 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10621 */   MCD_OPC_FilterValue, 14, 50, 0, 0, // Skip to: 10676
+/* 10626 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 10629 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10644
+/* 10634 */   MCD_OPC_CheckPredicate, 22, 113, 57, 0, // Skip to: 25344
+/* 10639 */   MCD_OPC_Decode, 213, 13, 145, 1, // Opcode: MVE_VSUB_qr_i8
+/* 10644 */   MCD_OPC_FilterValue, 2, 103, 57, 0, // Skip to: 25344
+/* 10649 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 10666
+/* 10654 */   MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 10666
+/* 10661 */   MCD_OPC_Decode, 178, 8, 159, 1, // Opcode: MVE_VDDUPu8
+/* 10666 */   MCD_OPC_CheckPredicate, 22, 81, 57, 0, // Skip to: 25344
+/* 10671 */   MCD_OPC_Decode, 184, 8, 160, 1, // Opcode: MVE_VDWDUPu8
+/* 10676 */   MCD_OPC_FilterValue, 15, 71, 57, 0, // Skip to: 25344
+/* 10681 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10684 */   MCD_OPC_FilterValue, 0, 63, 57, 0, // Skip to: 25344
+/* 10689 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10713
+/* 10694 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10713
+/* 10701 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10713
+/* 10708 */   MCD_OPC_Decode, 255, 7, 163, 1, // Opcode: MVE_VCMPs8r
+/* 10713 */   MCD_OPC_CheckPredicate, 22, 34, 57, 0, // Skip to: 25344
+/* 10718 */   MCD_OPC_Decode, 238, 10, 164, 1, // Opcode: MVE_VPTv16s8r
+/* 10723 */   MCD_OPC_FilterValue, 1, 197, 2, 0, // Skip to: 11437
+/* 10728 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10731 */   MCD_OPC_FilterValue, 0, 250, 0, 0, // Skip to: 10986
+/* 10736 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10739 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 10805
+/* 10744 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10747 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 10776
+/* 10752 */   MCD_OPC_CheckPredicate, 22, 251, 56, 0, // Skip to: 25344
+/* 10757 */   MCD_OPC_CheckField, 4, 1, 0, 244, 56, 0, // Skip to: 25344
+/* 10764 */   MCD_OPC_CheckField, 0, 1, 0, 237, 56, 0, // Skip to: 25344
+/* 10771 */   MCD_OPC_Decode, 206, 8, 150, 1, // Opcode: MVE_VHCADDs16
+/* 10776 */   MCD_OPC_FilterValue, 15, 227, 56, 0, // Skip to: 25344
+/* 10781 */   MCD_OPC_CheckPredicate, 22, 222, 56, 0, // Skip to: 25344
+/* 10786 */   MCD_OPC_CheckField, 4, 1, 0, 215, 56, 0, // Skip to: 25344
+/* 10793 */   MCD_OPC_CheckField, 0, 1, 0, 208, 56, 0, // Skip to: 25344
+/* 10800 */   MCD_OPC_Decode, 229, 7, 150, 1, // Opcode: MVE_VCADDi16
+/* 10805 */   MCD_OPC_FilterValue, 1, 198, 56, 0, // Skip to: 25344
+/* 10810 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 10813 */   MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 10931
+/* 10818 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 10821 */   MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 10876
+/* 10826 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10829 */   MCD_OPC_FilterValue, 0, 174, 56, 0, // Skip to: 25344
+/* 10834 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10837 */   MCD_OPC_FilterValue, 15, 166, 56, 0, // Skip to: 25344
+/* 10842 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10866
+/* 10847 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10866
+/* 10854 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10866
+/* 10861 */   MCD_OPC_Decode, 244, 7, 151, 1, // Opcode: MVE_VCMPi16
+/* 10866 */   MCD_OPC_CheckPredicate, 22, 137, 56, 0, // Skip to: 25344
+/* 10871 */   MCD_OPC_Decode, 251, 10, 152, 1, // Opcode: MVE_VPTv8i16
+/* 10876 */   MCD_OPC_FilterValue, 1, 127, 56, 0, // Skip to: 25344
+/* 10881 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10884 */   MCD_OPC_FilterValue, 0, 119, 56, 0, // Skip to: 25344
+/* 10889 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10892 */   MCD_OPC_FilterValue, 15, 111, 56, 0, // Skip to: 25344
+/* 10897 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10921
+/* 10902 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10921
+/* 10909 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10921
+/* 10916 */   MCD_OPC_Decode, 128, 8, 153, 1, // Opcode: MVE_VCMPu16
+/* 10921 */   MCD_OPC_CheckPredicate, 22, 82, 56, 0, // Skip to: 25344
+/* 10926 */   MCD_OPC_Decode, 255, 10, 154, 1, // Opcode: MVE_VPTv8u16
+/* 10931 */   MCD_OPC_FilterValue, 1, 72, 56, 0, // Skip to: 25344
+/* 10936 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 10939 */   MCD_OPC_FilterValue, 0, 64, 56, 0, // Skip to: 25344
+/* 10944 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 10947 */   MCD_OPC_FilterValue, 15, 56, 56, 0, // Skip to: 25344
+/* 10952 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 10976
+/* 10957 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 10976
+/* 10964 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 10976
+/* 10971 */   MCD_OPC_Decode, 250, 7, 155, 1, // Opcode: MVE_VCMPs16
+/* 10976 */   MCD_OPC_CheckPredicate, 22, 27, 56, 0, // Skip to: 25344
+/* 10981 */   MCD_OPC_Decode, 253, 10, 156, 1, // Opcode: MVE_VPTv8s16
+/* 10986 */   MCD_OPC_FilterValue, 1, 17, 56, 0, // Skip to: 25344
+/* 10991 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 10994 */   MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 11235
+/* 10999 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 11002 */   MCD_OPC_FilterValue, 0, 103, 0, 0, // Skip to: 11110
+/* 11007 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11010 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11048
+/* 11015 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11018 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11033
+/* 11023 */   MCD_OPC_CheckPredicate, 22, 236, 55, 0, // Skip to: 25344
+/* 11028 */   MCD_OPC_Decode, 194, 8, 145, 1, // Opcode: MVE_VHADD_qr_s16
+/* 11033 */   MCD_OPC_FilterValue, 15, 226, 55, 0, // Skip to: 25344
+/* 11038 */   MCD_OPC_CheckPredicate, 22, 221, 55, 0, // Skip to: 25344
+/* 11043 */   MCD_OPC_Decode, 197, 8, 145, 1, // Opcode: MVE_VHADD_qr_u16
+/* 11048 */   MCD_OPC_FilterValue, 1, 211, 55, 0, // Skip to: 25344
+/* 11053 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11056 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11071
+/* 11061 */   MCD_OPC_CheckPredicate, 22, 198, 55, 0, // Skip to: 25344
+/* 11066 */   MCD_OPC_Decode, 212, 7, 145, 1, // Opcode: MVE_VADD_qr_i16
+/* 11071 */   MCD_OPC_FilterValue, 15, 188, 55, 0, // Skip to: 25344
+/* 11076 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11100
+/* 11081 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11100
+/* 11088 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11100
+/* 11095 */   MCD_OPC_Decode, 245, 7, 157, 1, // Opcode: MVE_VCMPi16r
+/* 11100 */   MCD_OPC_CheckPredicate, 22, 159, 55, 0, // Skip to: 25344
+/* 11105 */   MCD_OPC_Decode, 252, 10, 158, 1, // Opcode: MVE_VPTv8i16r
+/* 11110 */   MCD_OPC_FilterValue, 2, 149, 55, 0, // Skip to: 25344
+/* 11115 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11118 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11156
+/* 11123 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11126 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11141
+/* 11131 */   MCD_OPC_CheckPredicate, 22, 128, 55, 0, // Skip to: 25344
+/* 11136 */   MCD_OPC_Decode, 132, 11, 145, 1, // Opcode: MVE_VQADD_qr_s16
+/* 11141 */   MCD_OPC_FilterValue, 15, 118, 55, 0, // Skip to: 25344
+/* 11146 */   MCD_OPC_CheckPredicate, 22, 113, 55, 0, // Skip to: 25344
+/* 11151 */   MCD_OPC_Decode, 135, 11, 145, 1, // Opcode: MVE_VQADD_qr_u16
+/* 11156 */   MCD_OPC_FilterValue, 1, 103, 55, 0, // Skip to: 25344
+/* 11161 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11164 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 11196
+/* 11169 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 11186
+/* 11174 */   MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 11186
+/* 11181 */   MCD_OPC_Decode, 221, 8, 159, 1, // Opcode: MVE_VIDUPu16
+/* 11186 */   MCD_OPC_CheckPredicate, 22, 73, 55, 0, // Skip to: 25344
+/* 11191 */   MCD_OPC_Decode, 224, 8, 160, 1, // Opcode: MVE_VIWDUPu16
+/* 11196 */   MCD_OPC_FilterValue, 15, 63, 55, 0, // Skip to: 25344
+/* 11201 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11225
+/* 11206 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11225
+/* 11213 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11225
+/* 11220 */   MCD_OPC_Decode, 129, 8, 161, 1, // Opcode: MVE_VCMPu16r
+/* 11225 */   MCD_OPC_CheckPredicate, 22, 34, 55, 0, // Skip to: 25344
+/* 11230 */   MCD_OPC_Decode, 128, 11, 162, 1, // Opcode: MVE_VPTv8u16r
+/* 11235 */   MCD_OPC_FilterValue, 1, 24, 55, 0, // Skip to: 25344
+/* 11240 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11243 */   MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 11327
+/* 11248 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 11251 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11289
+/* 11256 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11259 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11274
+/* 11264 */   MCD_OPC_CheckPredicate, 22, 251, 54, 0, // Skip to: 25344
+/* 11269 */   MCD_OPC_Decode, 209, 8, 145, 1, // Opcode: MVE_VHSUB_qr_s16
+/* 11274 */   MCD_OPC_FilterValue, 15, 241, 54, 0, // Skip to: 25344
+/* 11279 */   MCD_OPC_CheckPredicate, 22, 236, 54, 0, // Skip to: 25344
+/* 11284 */   MCD_OPC_Decode, 212, 8, 145, 1, // Opcode: MVE_VHSUB_qr_u16
+/* 11289 */   MCD_OPC_FilterValue, 2, 226, 54, 0, // Skip to: 25344
+/* 11294 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11297 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11312
+/* 11302 */   MCD_OPC_CheckPredicate, 22, 213, 54, 0, // Skip to: 25344
+/* 11307 */   MCD_OPC_Decode, 144, 12, 145, 1, // Opcode: MVE_VQSUB_qr_s16
+/* 11312 */   MCD_OPC_FilterValue, 15, 203, 54, 0, // Skip to: 25344
+/* 11317 */   MCD_OPC_CheckPredicate, 22, 198, 54, 0, // Skip to: 25344
+/* 11322 */   MCD_OPC_Decode, 147, 12, 145, 1, // Opcode: MVE_VQSUB_qr_u16
+/* 11327 */   MCD_OPC_FilterValue, 1, 188, 54, 0, // Skip to: 25344
+/* 11332 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11335 */   MCD_OPC_FilterValue, 14, 50, 0, 0, // Skip to: 11390
+/* 11340 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 11343 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 11358
+/* 11348 */   MCD_OPC_CheckPredicate, 22, 167, 54, 0, // Skip to: 25344
+/* 11353 */   MCD_OPC_Decode, 211, 13, 145, 1, // Opcode: MVE_VSUB_qr_i16
+/* 11358 */   MCD_OPC_FilterValue, 2, 157, 54, 0, // Skip to: 25344
+/* 11363 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 11380
+/* 11368 */   MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 11380
+/* 11375 */   MCD_OPC_Decode, 176, 8, 159, 1, // Opcode: MVE_VDDUPu16
+/* 11380 */   MCD_OPC_CheckPredicate, 22, 135, 54, 0, // Skip to: 25344
+/* 11385 */   MCD_OPC_Decode, 182, 8, 160, 1, // Opcode: MVE_VDWDUPu16
+/* 11390 */   MCD_OPC_FilterValue, 15, 125, 54, 0, // Skip to: 25344
+/* 11395 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 11398 */   MCD_OPC_FilterValue, 0, 117, 54, 0, // Skip to: 25344
+/* 11403 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11427
+/* 11408 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11427
+/* 11415 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11427
+/* 11422 */   MCD_OPC_Decode, 251, 7, 163, 1, // Opcode: MVE_VCMPs16r
+/* 11427 */   MCD_OPC_CheckPredicate, 22, 88, 54, 0, // Skip to: 25344
+/* 11432 */   MCD_OPC_Decode, 254, 10, 164, 1, // Opcode: MVE_VPTv8s16r
+/* 11437 */   MCD_OPC_FilterValue, 2, 197, 2, 0, // Skip to: 12151
+/* 11442 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 11445 */   MCD_OPC_FilterValue, 0, 250, 0, 0, // Skip to: 11700
+/* 11450 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11453 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 11519
+/* 11458 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11461 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 11490
+/* 11466 */   MCD_OPC_CheckPredicate, 22, 49, 54, 0, // Skip to: 25344
+/* 11471 */   MCD_OPC_CheckField, 4, 1, 0, 42, 54, 0, // Skip to: 25344
+/* 11478 */   MCD_OPC_CheckField, 0, 1, 0, 35, 54, 0, // Skip to: 25344
+/* 11485 */   MCD_OPC_Decode, 207, 8, 150, 1, // Opcode: MVE_VHCADDs32
+/* 11490 */   MCD_OPC_FilterValue, 15, 25, 54, 0, // Skip to: 25344
+/* 11495 */   MCD_OPC_CheckPredicate, 22, 20, 54, 0, // Skip to: 25344
+/* 11500 */   MCD_OPC_CheckField, 4, 1, 0, 13, 54, 0, // Skip to: 25344
+/* 11507 */   MCD_OPC_CheckField, 0, 1, 0, 6, 54, 0, // Skip to: 25344
+/* 11514 */   MCD_OPC_Decode, 230, 7, 150, 1, // Opcode: MVE_VCADDi32
+/* 11519 */   MCD_OPC_FilterValue, 1, 252, 53, 0, // Skip to: 25344
+/* 11524 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 11527 */   MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 11645
+/* 11532 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 11535 */   MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 11590
+/* 11540 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 11543 */   MCD_OPC_FilterValue, 0, 228, 53, 0, // Skip to: 25344
+/* 11548 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11551 */   MCD_OPC_FilterValue, 15, 220, 53, 0, // Skip to: 25344
+/* 11556 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11580
+/* 11561 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11580
+/* 11568 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11580
+/* 11575 */   MCD_OPC_Decode, 246, 7, 151, 1, // Opcode: MVE_VCMPi32
+/* 11580 */   MCD_OPC_CheckPredicate, 22, 191, 53, 0, // Skip to: 25344
+/* 11585 */   MCD_OPC_Decode, 243, 10, 152, 1, // Opcode: MVE_VPTv4i32
+/* 11590 */   MCD_OPC_FilterValue, 1, 181, 53, 0, // Skip to: 25344
+/* 11595 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 11598 */   MCD_OPC_FilterValue, 0, 173, 53, 0, // Skip to: 25344
+/* 11603 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11606 */   MCD_OPC_FilterValue, 15, 165, 53, 0, // Skip to: 25344
+/* 11611 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11635
+/* 11616 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11635
+/* 11623 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11635
+/* 11630 */   MCD_OPC_Decode, 130, 8, 153, 1, // Opcode: MVE_VCMPu32
+/* 11635 */   MCD_OPC_CheckPredicate, 22, 136, 53, 0, // Skip to: 25344
+/* 11640 */   MCD_OPC_Decode, 247, 10, 154, 1, // Opcode: MVE_VPTv4u32
+/* 11645 */   MCD_OPC_FilterValue, 1, 126, 53, 0, // Skip to: 25344
+/* 11650 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 11653 */   MCD_OPC_FilterValue, 0, 118, 53, 0, // Skip to: 25344
+/* 11658 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11661 */   MCD_OPC_FilterValue, 15, 110, 53, 0, // Skip to: 25344
+/* 11666 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11690
+/* 11671 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11690
+/* 11678 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11690
+/* 11685 */   MCD_OPC_Decode, 252, 7, 155, 1, // Opcode: MVE_VCMPs32
+/* 11690 */   MCD_OPC_CheckPredicate, 22, 81, 53, 0, // Skip to: 25344
+/* 11695 */   MCD_OPC_Decode, 245, 10, 156, 1, // Opcode: MVE_VPTv4s32
+/* 11700 */   MCD_OPC_FilterValue, 1, 71, 53, 0, // Skip to: 25344
+/* 11705 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 11708 */   MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 11949
+/* 11713 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 11716 */   MCD_OPC_FilterValue, 0, 103, 0, 0, // Skip to: 11824
+/* 11721 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11724 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11762
+/* 11729 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11732 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11747
+/* 11737 */   MCD_OPC_CheckPredicate, 22, 34, 53, 0, // Skip to: 25344
+/* 11742 */   MCD_OPC_Decode, 195, 8, 145, 1, // Opcode: MVE_VHADD_qr_s32
+/* 11747 */   MCD_OPC_FilterValue, 15, 24, 53, 0, // Skip to: 25344
+/* 11752 */   MCD_OPC_CheckPredicate, 22, 19, 53, 0, // Skip to: 25344
+/* 11757 */   MCD_OPC_Decode, 198, 8, 145, 1, // Opcode: MVE_VHADD_qr_u32
+/* 11762 */   MCD_OPC_FilterValue, 1, 9, 53, 0, // Skip to: 25344
+/* 11767 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11770 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11785
+/* 11775 */   MCD_OPC_CheckPredicate, 22, 252, 52, 0, // Skip to: 25344
+/* 11780 */   MCD_OPC_Decode, 213, 7, 145, 1, // Opcode: MVE_VADD_qr_i32
+/* 11785 */   MCD_OPC_FilterValue, 15, 242, 52, 0, // Skip to: 25344
+/* 11790 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11814
+/* 11795 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11814
+/* 11802 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11814
+/* 11809 */   MCD_OPC_Decode, 247, 7, 157, 1, // Opcode: MVE_VCMPi32r
+/* 11814 */   MCD_OPC_CheckPredicate, 22, 213, 52, 0, // Skip to: 25344
+/* 11819 */   MCD_OPC_Decode, 244, 10, 158, 1, // Opcode: MVE_VPTv4i32r
+/* 11824 */   MCD_OPC_FilterValue, 2, 203, 52, 0, // Skip to: 25344
+/* 11829 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11832 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11870
+/* 11837 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11840 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11855
+/* 11845 */   MCD_OPC_CheckPredicate, 22, 182, 52, 0, // Skip to: 25344
+/* 11850 */   MCD_OPC_Decode, 133, 11, 145, 1, // Opcode: MVE_VQADD_qr_s32
+/* 11855 */   MCD_OPC_FilterValue, 15, 172, 52, 0, // Skip to: 25344
+/* 11860 */   MCD_OPC_CheckPredicate, 22, 167, 52, 0, // Skip to: 25344
+/* 11865 */   MCD_OPC_Decode, 136, 11, 145, 1, // Opcode: MVE_VQADD_qr_u32
+/* 11870 */   MCD_OPC_FilterValue, 1, 157, 52, 0, // Skip to: 25344
+/* 11875 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11878 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 11910
+/* 11883 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 11900
+/* 11888 */   MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 11900
+/* 11895 */   MCD_OPC_Decode, 222, 8, 159, 1, // Opcode: MVE_VIDUPu32
+/* 11900 */   MCD_OPC_CheckPredicate, 22, 127, 52, 0, // Skip to: 25344
+/* 11905 */   MCD_OPC_Decode, 225, 8, 160, 1, // Opcode: MVE_VIWDUPu32
+/* 11910 */   MCD_OPC_FilterValue, 15, 117, 52, 0, // Skip to: 25344
+/* 11915 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 11939
+/* 11920 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 11939
+/* 11927 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 11939
+/* 11934 */   MCD_OPC_Decode, 131, 8, 161, 1, // Opcode: MVE_VCMPu32r
+/* 11939 */   MCD_OPC_CheckPredicate, 22, 88, 52, 0, // Skip to: 25344
+/* 11944 */   MCD_OPC_Decode, 248, 10, 162, 1, // Opcode: MVE_VPTv4u32r
+/* 11949 */   MCD_OPC_FilterValue, 1, 78, 52, 0, // Skip to: 25344
+/* 11954 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 11957 */   MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 12041
+/* 11962 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 11965 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12003
+/* 11970 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 11973 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 11988
+/* 11978 */   MCD_OPC_CheckPredicate, 22, 49, 52, 0, // Skip to: 25344
+/* 11983 */   MCD_OPC_Decode, 210, 8, 145, 1, // Opcode: MVE_VHSUB_qr_s32
+/* 11988 */   MCD_OPC_FilterValue, 15, 39, 52, 0, // Skip to: 25344
+/* 11993 */   MCD_OPC_CheckPredicate, 22, 34, 52, 0, // Skip to: 25344
+/* 11998 */   MCD_OPC_Decode, 213, 8, 145, 1, // Opcode: MVE_VHSUB_qr_u32
+/* 12003 */   MCD_OPC_FilterValue, 2, 24, 52, 0, // Skip to: 25344
+/* 12008 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12011 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12026
+/* 12016 */   MCD_OPC_CheckPredicate, 22, 11, 52, 0, // Skip to: 25344
+/* 12021 */   MCD_OPC_Decode, 145, 12, 145, 1, // Opcode: MVE_VQSUB_qr_s32
+/* 12026 */   MCD_OPC_FilterValue, 15, 1, 52, 0, // Skip to: 25344
+/* 12031 */   MCD_OPC_CheckPredicate, 22, 252, 51, 0, // Skip to: 25344
+/* 12036 */   MCD_OPC_Decode, 148, 12, 145, 1, // Opcode: MVE_VQSUB_qr_u32
+/* 12041 */   MCD_OPC_FilterValue, 1, 242, 51, 0, // Skip to: 25344
+/* 12046 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12049 */   MCD_OPC_FilterValue, 14, 50, 0, 0, // Skip to: 12104
+/* 12054 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 12057 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12072
+/* 12062 */   MCD_OPC_CheckPredicate, 22, 221, 51, 0, // Skip to: 25344
+/* 12067 */   MCD_OPC_Decode, 212, 13, 145, 1, // Opcode: MVE_VSUB_qr_i32
+/* 12072 */   MCD_OPC_FilterValue, 2, 211, 51, 0, // Skip to: 25344
+/* 12077 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 12094
+/* 12082 */   MCD_OPC_CheckField, 1, 3, 7, 5, 0, 0, // Skip to: 12094
+/* 12089 */   MCD_OPC_Decode, 177, 8, 159, 1, // Opcode: MVE_VDDUPu32
+/* 12094 */   MCD_OPC_CheckPredicate, 22, 189, 51, 0, // Skip to: 25344
+/* 12099 */   MCD_OPC_Decode, 183, 8, 160, 1, // Opcode: MVE_VDWDUPu32
+/* 12104 */   MCD_OPC_FilterValue, 15, 179, 51, 0, // Skip to: 25344
+/* 12109 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 12112 */   MCD_OPC_FilterValue, 0, 171, 51, 0, // Skip to: 25344
+/* 12117 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 12141
+/* 12122 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 12141
+/* 12129 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 12141
+/* 12136 */   MCD_OPC_Decode, 253, 7, 163, 1, // Opcode: MVE_VCMPs32r
+/* 12141 */   MCD_OPC_CheckPredicate, 22, 142, 51, 0, // Skip to: 25344
+/* 12146 */   MCD_OPC_Decode, 246, 10, 164, 1, // Opcode: MVE_VPTv4s32r
+/* 12151 */   MCD_OPC_FilterValue, 3, 132, 51, 0, // Skip to: 25344
+/* 12156 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 12159 */   MCD_OPC_FilterValue, 0, 105, 1, 0, // Skip to: 12525
+/* 12164 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 12167 */   MCD_OPC_FilterValue, 0, 227, 0, 0, // Skip to: 12399
+/* 12172 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 12175 */   MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 12287
+/* 12180 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 12183 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12235
+/* 12188 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12191 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 12213
+/* 12196 */   MCD_OPC_CheckPredicate, 22, 87, 51, 0, // Skip to: 25344
+/* 12201 */   MCD_OPC_CheckField, 4, 1, 0, 80, 51, 0, // Skip to: 25344
+/* 12208 */   MCD_OPC_Decode, 192, 7, 165, 1, // Opcode: MVE_VADC
+/* 12213 */   MCD_OPC_FilterValue, 15, 70, 51, 0, // Skip to: 25344
+/* 12218 */   MCD_OPC_CheckPredicate, 22, 65, 51, 0, // Skip to: 25344
+/* 12223 */   MCD_OPC_CheckField, 4, 1, 0, 58, 51, 0, // Skip to: 25344
+/* 12230 */   MCD_OPC_Decode, 218, 12, 165, 1, // Opcode: MVE_VSBC
+/* 12235 */   MCD_OPC_FilterValue, 1, 48, 51, 0, // Skip to: 25344
+/* 12240 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12243 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 12265
+/* 12248 */   MCD_OPC_CheckPredicate, 22, 35, 51, 0, // Skip to: 25344
+/* 12253 */   MCD_OPC_CheckField, 4, 1, 0, 28, 51, 0, // Skip to: 25344
+/* 12260 */   MCD_OPC_Decode, 193, 7, 165, 1, // Opcode: MVE_VADCI
+/* 12265 */   MCD_OPC_FilterValue, 15, 18, 51, 0, // Skip to: 25344
+/* 12270 */   MCD_OPC_CheckPredicate, 22, 13, 51, 0, // Skip to: 25344
+/* 12275 */   MCD_OPC_CheckField, 4, 1, 0, 6, 51, 0, // Skip to: 25344
+/* 12282 */   MCD_OPC_Decode, 219, 12, 165, 1, // Opcode: MVE_VSBCI
+/* 12287 */   MCD_OPC_FilterValue, 1, 252, 50, 0, // Skip to: 25344
+/* 12292 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 12295 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12347
+/* 12300 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12303 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 12325
+/* 12308 */   MCD_OPC_CheckPredicate, 22, 231, 50, 0, // Skip to: 25344
+/* 12313 */   MCD_OPC_CheckField, 4, 1, 0, 224, 50, 0, // Skip to: 25344
+/* 12320 */   MCD_OPC_Decode, 172, 11, 143, 1, // Opcode: MVE_VQDMULLs16bh
+/* 12325 */   MCD_OPC_FilterValue, 15, 214, 50, 0, // Skip to: 25344
+/* 12330 */   MCD_OPC_CheckPredicate, 22, 209, 50, 0, // Skip to: 25344
+/* 12335 */   MCD_OPC_CheckField, 4, 1, 0, 202, 50, 0, // Skip to: 25344
+/* 12342 */   MCD_OPC_Decode, 174, 11, 143, 1, // Opcode: MVE_VQDMULLs32bh
+/* 12347 */   MCD_OPC_FilterValue, 1, 192, 50, 0, // Skip to: 25344
+/* 12352 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12355 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 12377
+/* 12360 */   MCD_OPC_CheckPredicate, 22, 179, 50, 0, // Skip to: 25344
+/* 12365 */   MCD_OPC_CheckField, 4, 1, 0, 172, 50, 0, // Skip to: 25344
+/* 12372 */   MCD_OPC_Decode, 173, 11, 143, 1, // Opcode: MVE_VQDMULLs16th
+/* 12377 */   MCD_OPC_FilterValue, 15, 162, 50, 0, // Skip to: 25344
+/* 12382 */   MCD_OPC_CheckPredicate, 22, 157, 50, 0, // Skip to: 25344
+/* 12387 */   MCD_OPC_CheckField, 4, 1, 0, 150, 50, 0, // Skip to: 25344
+/* 12394 */   MCD_OPC_Decode, 175, 11, 143, 1, // Opcode: MVE_VQDMULLs32th
+/* 12399 */   MCD_OPC_FilterValue, 1, 140, 50, 0, // Skip to: 25344
+/* 12404 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12407 */   MCD_OPC_FilterValue, 14, 42, 0, 0, // Skip to: 12454
+/* 12412 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 12415 */   MCD_OPC_FilterValue, 0, 124, 50, 0, // Skip to: 25344
+/* 12420 */   MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 12444
+/* 12425 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 12444
+/* 12432 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 12444
+/* 12439 */   MCD_OPC_Decode, 242, 7, 166, 1, // Opcode: MVE_VCMPf32
+/* 12444 */   MCD_OPC_CheckPredicate, 24, 95, 50, 0, // Skip to: 25344
+/* 12449 */   MCD_OPC_Decode, 241, 10, 167, 1, // Opcode: MVE_VPTv4f32
+/* 12454 */   MCD_OPC_FilterValue, 15, 85, 50, 0, // Skip to: 25344
+/* 12459 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 12462 */   MCD_OPC_FilterValue, 0, 77, 50, 0, // Skip to: 25344
+/* 12467 */   MCD_OPC_CheckPredicate, 22, 19, 0, 0, // Skip to: 12491
+/* 12472 */   MCD_OPC_CheckField, 12, 1, 0, 12, 0, 0, // Skip to: 12491
+/* 12479 */   MCD_OPC_CheckField, 0, 1, 1, 5, 0, 0, // Skip to: 12491
+/* 12486 */   MCD_OPC_Decode, 233, 10, 168, 1, // Opcode: MVE_VPSEL
+/* 12491 */   MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 12515
+/* 12496 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 12515
+/* 12503 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 12515
+/* 12510 */   MCD_OPC_Decode, 240, 7, 166, 1, // Opcode: MVE_VCMPf16
+/* 12515 */   MCD_OPC_CheckPredicate, 24, 24, 50, 0, // Skip to: 25344
+/* 12520 */   MCD_OPC_Decode, 249, 10, 167, 1, // Opcode: MVE_VPTv8f16
+/* 12525 */   MCD_OPC_FilterValue, 1, 14, 50, 0, // Skip to: 25344
+/* 12530 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 12533 */   MCD_OPC_FilterValue, 0, 171, 0, 0, // Skip to: 12709
+/* 12538 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 12541 */   MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 12625
+/* 12546 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 12549 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12587
+/* 12554 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12557 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12572
+/* 12562 */   MCD_OPC_CheckPredicate, 24, 233, 49, 0, // Skip to: 25344
+/* 12567 */   MCD_OPC_Decode, 211, 7, 145, 1, // Opcode: MVE_VADD_qr_f32
+/* 12572 */   MCD_OPC_FilterValue, 15, 223, 49, 0, // Skip to: 25344
+/* 12577 */   MCD_OPC_CheckPredicate, 24, 218, 49, 0, // Skip to: 25344
+/* 12582 */   MCD_OPC_Decode, 210, 7, 145, 1, // Opcode: MVE_VADD_qr_f16
+/* 12587 */   MCD_OPC_FilterValue, 1, 208, 49, 0, // Skip to: 25344
+/* 12592 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12595 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12610
+/* 12600 */   MCD_OPC_CheckPredicate, 24, 195, 49, 0, // Skip to: 25344
+/* 12605 */   MCD_OPC_Decode, 210, 13, 145, 1, // Opcode: MVE_VSUB_qr_f32
+/* 12610 */   MCD_OPC_FilterValue, 15, 185, 49, 0, // Skip to: 25344
+/* 12615 */   MCD_OPC_CheckPredicate, 24, 180, 49, 0, // Skip to: 25344
+/* 12620 */   MCD_OPC_Decode, 209, 13, 145, 1, // Opcode: MVE_VSUB_qr_f16
+/* 12625 */   MCD_OPC_FilterValue, 2, 170, 49, 0, // Skip to: 25344
+/* 12630 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 12633 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12671
+/* 12638 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12641 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12656
+/* 12646 */   MCD_OPC_CheckPredicate, 22, 149, 49, 0, // Skip to: 25344
+/* 12651 */   MCD_OPC_Decode, 168, 11, 145, 1, // Opcode: MVE_VQDMULL_qr_s16bh
+/* 12656 */   MCD_OPC_FilterValue, 15, 139, 49, 0, // Skip to: 25344
+/* 12661 */   MCD_OPC_CheckPredicate, 22, 134, 49, 0, // Skip to: 25344
+/* 12666 */   MCD_OPC_Decode, 170, 11, 145, 1, // Opcode: MVE_VQDMULL_qr_s32bh
+/* 12671 */   MCD_OPC_FilterValue, 1, 124, 49, 0, // Skip to: 25344
+/* 12676 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12679 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 12694
+/* 12684 */   MCD_OPC_CheckPredicate, 22, 111, 49, 0, // Skip to: 25344
+/* 12689 */   MCD_OPC_Decode, 169, 11, 145, 1, // Opcode: MVE_VQDMULL_qr_s16th
+/* 12694 */   MCD_OPC_FilterValue, 15, 101, 49, 0, // Skip to: 25344
+/* 12699 */   MCD_OPC_CheckPredicate, 22, 96, 49, 0, // Skip to: 25344
+/* 12704 */   MCD_OPC_Decode, 171, 11, 145, 1, // Opcode: MVE_VQDMULL_qr_s32th
+/* 12709 */   MCD_OPC_FilterValue, 1, 86, 49, 0, // Skip to: 25344
+/* 12714 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 12717 */   MCD_OPC_FilterValue, 14, 42, 0, 0, // Skip to: 12764
+/* 12722 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 12725 */   MCD_OPC_FilterValue, 0, 70, 49, 0, // Skip to: 25344
+/* 12730 */   MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 12754
+/* 12735 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 12754
+/* 12742 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 12754
+/* 12749 */   MCD_OPC_Decode, 243, 7, 169, 1, // Opcode: MVE_VCMPf32r
+/* 12754 */   MCD_OPC_CheckPredicate, 24, 41, 49, 0, // Skip to: 25344
+/* 12759 */   MCD_OPC_Decode, 242, 10, 170, 1, // Opcode: MVE_VPTv4f32r
+/* 12764 */   MCD_OPC_FilterValue, 15, 31, 49, 0, // Skip to: 25344
+/* 12769 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 12772 */   MCD_OPC_FilterValue, 0, 23, 49, 0, // Skip to: 25344
+/* 12777 */   MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
+/* 12780 */   MCD_OPC_FilterValue, 13, 50, 0, 0, // Skip to: 12835
+/* 12785 */   MCD_OPC_CheckPredicate, 22, 24, 0, 0, // Skip to: 12814
+/* 12790 */   MCD_OPC_CheckField, 22, 1, 0, 17, 0, 0, // Skip to: 12814
+/* 12797 */   MCD_OPC_CheckField, 13, 3, 0, 10, 0, 0, // Skip to: 12814
+/* 12804 */   MCD_OPC_SoftFail, 160, 161, 56 /* 0xe10a0 */, 0,
+/* 12809 */   MCD_OPC_Decode, 232, 10, 171, 1, // Opcode: MVE_VPNOT
+/* 12814 */   MCD_OPC_CheckPredicate, 22, 16, 0, 0, // Skip to: 12835
+/* 12819 */   MCD_OPC_CheckField, 17, 3, 0, 9, 0, 0, // Skip to: 12835
+/* 12826 */   MCD_OPC_SoftFail, 160, 33 /* 0x10a0 */, 0,
+/* 12830 */   MCD_OPC_Decode, 234, 10, 172, 1, // Opcode: MVE_VPST
+/* 12835 */   MCD_OPC_CheckPredicate, 24, 19, 0, 0, // Skip to: 12859
+/* 12840 */   MCD_OPC_CheckField, 22, 1, 0, 12, 0, 0, // Skip to: 12859
+/* 12847 */   MCD_OPC_CheckField, 13, 3, 0, 5, 0, 0, // Skip to: 12859
+/* 12854 */   MCD_OPC_Decode, 241, 7, 169, 1, // Opcode: MVE_VCMPf16r
+/* 12859 */   MCD_OPC_CheckPredicate, 24, 192, 48, 0, // Skip to: 25344
+/* 12864 */   MCD_OPC_Decode, 250, 10, 170, 1, // Opcode: MVE_VPTv8f16r
+/* 12869 */   MCD_OPC_FilterValue, 1, 119, 16, 0, // Skip to: 17089
+/* 12874 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 12877 */   MCD_OPC_FilterValue, 11, 179, 0, 0, // Skip to: 13061
+/* 12882 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 12885 */   MCD_OPC_FilterValue, 0, 105, 0, 0, // Skip to: 12995
+/* 12890 */   MCD_OPC_ExtractField, 0, 7,  // Inst{6-0} ...
+/* 12893 */   MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 12959
+/* 12898 */   MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 12901 */   MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 12930
+/* 12906 */   MCD_OPC_CheckPredicate, 22, 145, 48, 0, // Skip to: 25344
+/* 12911 */   MCD_OPC_CheckField, 28, 4, 14, 138, 48, 0, // Skip to: 25344
+/* 12918 */   MCD_OPC_CheckField, 16, 1, 0, 131, 48, 0, // Skip to: 25344
+/* 12925 */   MCD_OPC_Decode, 180, 8, 173, 1, // Opcode: MVE_VDUP32
+/* 12930 */   MCD_OPC_FilterValue, 3, 121, 48, 0, // Skip to: 25344
+/* 12935 */   MCD_OPC_CheckPredicate, 22, 116, 48, 0, // Skip to: 25344
+/* 12940 */   MCD_OPC_CheckField, 28, 4, 14, 109, 48, 0, // Skip to: 25344
+/* 12947 */   MCD_OPC_CheckField, 16, 1, 0, 102, 48, 0, // Skip to: 25344
+/* 12954 */   MCD_OPC_Decode, 181, 8, 173, 1, // Opcode: MVE_VDUP8
+/* 12959 */   MCD_OPC_FilterValue, 48, 92, 48, 0, // Skip to: 25344
+/* 12964 */   MCD_OPC_CheckPredicate, 22, 87, 48, 0, // Skip to: 25344
+/* 12969 */   MCD_OPC_CheckField, 28, 4, 14, 80, 48, 0, // Skip to: 25344
+/* 12976 */   MCD_OPC_CheckField, 21, 2, 1, 73, 48, 0, // Skip to: 25344
+/* 12983 */   MCD_OPC_CheckField, 16, 1, 0, 66, 48, 0, // Skip to: 25344
+/* 12990 */   MCD_OPC_Decode, 179, 8, 173, 1, // Opcode: MVE_VDUP16
+/* 12995 */   MCD_OPC_FilterValue, 1, 56, 48, 0, // Skip to: 25344
+/* 13000 */   MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 13003 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13032
+/* 13008 */   MCD_OPC_CheckPredicate, 23, 43, 48, 0, // Skip to: 25344
+/* 13013 */   MCD_OPC_CheckField, 28, 4, 14, 36, 48, 0, // Skip to: 25344
+/* 13020 */   MCD_OPC_CheckField, 0, 6, 48, 29, 48, 0, // Skip to: 25344
+/* 13027 */   MCD_OPC_Decode, 176, 10, 140, 1, // Opcode: MVE_VMOV_from_lane_u16
+/* 13032 */   MCD_OPC_FilterValue, 1, 19, 48, 0, // Skip to: 25344
+/* 13037 */   MCD_OPC_CheckPredicate, 23, 14, 48, 0, // Skip to: 25344
+/* 13042 */   MCD_OPC_CheckField, 28, 4, 14, 7, 48, 0, // Skip to: 25344
+/* 13049 */   MCD_OPC_CheckField, 0, 5, 16, 0, 48, 0, // Skip to: 25344
+/* 13056 */   MCD_OPC_Decode, 177, 10, 141, 1, // Opcode: MVE_VMOV_from_lane_u8
+/* 13061 */   MCD_OPC_FilterValue, 14, 243, 3, 0, // Skip to: 14077
+/* 13066 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 13069 */   MCD_OPC_FilterValue, 0, 243, 1, 0, // Skip to: 13573
+/* 13074 */   MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 13077 */   MCD_OPC_FilterValue, 0, 243, 0, 0, // Skip to: 13325
+/* 13082 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 13085 */   MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 13237
+/* 13090 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13093 */   MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 13165
+/* 13098 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13101 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13133
+/* 13106 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13123
+/* 13111 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13123
+/* 13118 */   MCD_OPC_Decode, 242, 9, 174, 1, // Opcode: MVE_VMLADAVs16
+/* 13123 */   MCD_OPC_CheckPredicate, 22, 184, 47, 0, // Skip to: 25344
+/* 13128 */   MCD_OPC_Decode, 129, 10, 175, 1, // Opcode: MVE_VMLALDAVs16
+/* 13133 */   MCD_OPC_FilterValue, 15, 174, 47, 0, // Skip to: 25344
+/* 13138 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13155
+/* 13143 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13155
+/* 13150 */   MCD_OPC_Decode, 245, 9, 174, 1, // Opcode: MVE_VMLADAVu16
+/* 13155 */   MCD_OPC_CheckPredicate, 22, 152, 47, 0, // Skip to: 25344
+/* 13160 */   MCD_OPC_Decode, 131, 10, 175, 1, // Opcode: MVE_VMLALDAVu16
+/* 13165 */   MCD_OPC_FilterValue, 1, 142, 47, 0, // Skip to: 25344
+/* 13170 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13173 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13205
+/* 13178 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13195
+/* 13183 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13195
+/* 13190 */   MCD_OPC_Decode, 243, 9, 174, 1, // Opcode: MVE_VMLADAVs32
+/* 13195 */   MCD_OPC_CheckPredicate, 22, 112, 47, 0, // Skip to: 25344
+/* 13200 */   MCD_OPC_Decode, 130, 10, 175, 1, // Opcode: MVE_VMLALDAVs32
+/* 13205 */   MCD_OPC_FilterValue, 15, 102, 47, 0, // Skip to: 25344
+/* 13210 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13227
+/* 13215 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13227
+/* 13222 */   MCD_OPC_Decode, 246, 9, 174, 1, // Opcode: MVE_VMLADAVu32
+/* 13227 */   MCD_OPC_CheckPredicate, 22, 80, 47, 0, // Skip to: 25344
+/* 13232 */   MCD_OPC_Decode, 132, 10, 175, 1, // Opcode: MVE_VMLALDAVu32
+/* 13237 */   MCD_OPC_FilterValue, 1, 70, 47, 0, // Skip to: 25344
+/* 13242 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13245 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 13285
+/* 13250 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13253 */   MCD_OPC_FilterValue, 14, 54, 47, 0, // Skip to: 25344
+/* 13258 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13275
+/* 13263 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13275
+/* 13270 */   MCD_OPC_Decode, 248, 9, 174, 1, // Opcode: MVE_VMLADAVxs16
+/* 13275 */   MCD_OPC_CheckPredicate, 22, 32, 47, 0, // Skip to: 25344
+/* 13280 */   MCD_OPC_Decode, 133, 10, 175, 1, // Opcode: MVE_VMLALDAVxs16
+/* 13285 */   MCD_OPC_FilterValue, 1, 22, 47, 0, // Skip to: 25344
+/* 13290 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13293 */   MCD_OPC_FilterValue, 14, 14, 47, 0, // Skip to: 25344
+/* 13298 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13315
+/* 13303 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13315
+/* 13310 */   MCD_OPC_Decode, 249, 9, 174, 1, // Opcode: MVE_VMLADAVxs32
+/* 13315 */   MCD_OPC_CheckPredicate, 22, 248, 46, 0, // Skip to: 25344
+/* 13320 */   MCD_OPC_Decode, 134, 10, 175, 1, // Opcode: MVE_VMLALDAVxs32
+/* 13325 */   MCD_OPC_FilterValue, 2, 238, 46, 0, // Skip to: 25344
+/* 13330 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 13333 */   MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 13485
+/* 13338 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13341 */   MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 13413
+/* 13346 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13349 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13381
+/* 13354 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13371
+/* 13359 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13371
+/* 13366 */   MCD_OPC_Decode, 233, 9, 176, 1, // Opcode: MVE_VMLADAVas16
+/* 13371 */   MCD_OPC_CheckPredicate, 22, 192, 46, 0, // Skip to: 25344
+/* 13376 */   MCD_OPC_Decode, 251, 9, 177, 1, // Opcode: MVE_VMLALDAVas16
+/* 13381 */   MCD_OPC_FilterValue, 15, 182, 46, 0, // Skip to: 25344
+/* 13386 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13403
+/* 13391 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13403
+/* 13398 */   MCD_OPC_Decode, 236, 9, 176, 1, // Opcode: MVE_VMLADAVau16
+/* 13403 */   MCD_OPC_CheckPredicate, 22, 160, 46, 0, // Skip to: 25344
+/* 13408 */   MCD_OPC_Decode, 253, 9, 177, 1, // Opcode: MVE_VMLALDAVau16
+/* 13413 */   MCD_OPC_FilterValue, 1, 150, 46, 0, // Skip to: 25344
+/* 13418 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13421 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13453
+/* 13426 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13443
+/* 13431 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13443
+/* 13438 */   MCD_OPC_Decode, 234, 9, 176, 1, // Opcode: MVE_VMLADAVas32
+/* 13443 */   MCD_OPC_CheckPredicate, 22, 120, 46, 0, // Skip to: 25344
+/* 13448 */   MCD_OPC_Decode, 252, 9, 177, 1, // Opcode: MVE_VMLALDAVas32
+/* 13453 */   MCD_OPC_FilterValue, 15, 110, 46, 0, // Skip to: 25344
+/* 13458 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13475
+/* 13463 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13475
+/* 13470 */   MCD_OPC_Decode, 237, 9, 176, 1, // Opcode: MVE_VMLADAVau32
+/* 13475 */   MCD_OPC_CheckPredicate, 22, 88, 46, 0, // Skip to: 25344
+/* 13480 */   MCD_OPC_Decode, 254, 9, 177, 1, // Opcode: MVE_VMLALDAVau32
+/* 13485 */   MCD_OPC_FilterValue, 1, 78, 46, 0, // Skip to: 25344
+/* 13490 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13493 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 13533
+/* 13498 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13501 */   MCD_OPC_FilterValue, 14, 62, 46, 0, // Skip to: 25344
+/* 13506 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13523
+/* 13511 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13523
+/* 13518 */   MCD_OPC_Decode, 239, 9, 176, 1, // Opcode: MVE_VMLADAVaxs16
+/* 13523 */   MCD_OPC_CheckPredicate, 22, 40, 46, 0, // Skip to: 25344
+/* 13528 */   MCD_OPC_Decode, 255, 9, 177, 1, // Opcode: MVE_VMLALDAVaxs16
+/* 13533 */   MCD_OPC_FilterValue, 1, 30, 46, 0, // Skip to: 25344
+/* 13538 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13541 */   MCD_OPC_FilterValue, 14, 22, 46, 0, // Skip to: 25344
+/* 13546 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13563
+/* 13551 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13563
+/* 13558 */   MCD_OPC_Decode, 240, 9, 176, 1, // Opcode: MVE_VMLADAVaxs32
+/* 13563 */   MCD_OPC_CheckPredicate, 22, 0, 46, 0, // Skip to: 25344
+/* 13568 */   MCD_OPC_Decode, 128, 10, 177, 1, // Opcode: MVE_VMLALDAVaxs32
+/* 13573 */   MCD_OPC_FilterValue, 1, 246, 45, 0, // Skip to: 25344
+/* 13578 */   MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 13581 */   MCD_OPC_FilterValue, 0, 243, 0, 0, // Skip to: 13829
+/* 13586 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 13589 */   MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 13709
+/* 13594 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13597 */   MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 13669
+/* 13602 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13605 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13637
+/* 13610 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13627
+/* 13615 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13627
+/* 13622 */   MCD_OPC_Decode, 147, 10, 174, 1, // Opcode: MVE_VMLSDAVs16
+/* 13627 */   MCD_OPC_CheckPredicate, 22, 192, 45, 0, // Skip to: 25344
+/* 13632 */   MCD_OPC_Decode, 157, 10, 175, 1, // Opcode: MVE_VMLSLDAVs16
+/* 13637 */   MCD_OPC_FilterValue, 15, 182, 45, 0, // Skip to: 25344
+/* 13642 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13659
+/* 13647 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13659
+/* 13654 */   MCD_OPC_Decode, 149, 10, 174, 1, // Opcode: MVE_VMLSDAVs8
+/* 13659 */   MCD_OPC_CheckPredicate, 22, 160, 45, 0, // Skip to: 25344
+/* 13664 */   MCD_OPC_Decode, 188, 12, 175, 1, // Opcode: MVE_VRMLSLDAVHs32
+/* 13669 */   MCD_OPC_FilterValue, 1, 150, 45, 0, // Skip to: 25344
+/* 13674 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13677 */   MCD_OPC_FilterValue, 14, 142, 45, 0, // Skip to: 25344
+/* 13682 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13699
+/* 13687 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13699
+/* 13694 */   MCD_OPC_Decode, 148, 10, 174, 1, // Opcode: MVE_VMLSDAVs32
+/* 13699 */   MCD_OPC_CheckPredicate, 22, 120, 45, 0, // Skip to: 25344
+/* 13704 */   MCD_OPC_Decode, 158, 10, 175, 1, // Opcode: MVE_VMLSLDAVs32
+/* 13709 */   MCD_OPC_FilterValue, 1, 110, 45, 0, // Skip to: 25344
+/* 13714 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13717 */   MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 13789
+/* 13722 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13725 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13757
+/* 13730 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13747
+/* 13735 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13747
+/* 13742 */   MCD_OPC_Decode, 150, 10, 174, 1, // Opcode: MVE_VMLSDAVxs16
+/* 13747 */   MCD_OPC_CheckPredicate, 22, 72, 45, 0, // Skip to: 25344
+/* 13752 */   MCD_OPC_Decode, 159, 10, 175, 1, // Opcode: MVE_VMLSLDAVxs16
+/* 13757 */   MCD_OPC_FilterValue, 15, 62, 45, 0, // Skip to: 25344
+/* 13762 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13779
+/* 13767 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13779
+/* 13774 */   MCD_OPC_Decode, 152, 10, 174, 1, // Opcode: MVE_VMLSDAVxs8
+/* 13779 */   MCD_OPC_CheckPredicate, 22, 40, 45, 0, // Skip to: 25344
+/* 13784 */   MCD_OPC_Decode, 189, 12, 175, 1, // Opcode: MVE_VRMLSLDAVHxs32
+/* 13789 */   MCD_OPC_FilterValue, 1, 30, 45, 0, // Skip to: 25344
+/* 13794 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13797 */   MCD_OPC_FilterValue, 14, 22, 45, 0, // Skip to: 25344
+/* 13802 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13819
+/* 13807 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13819
+/* 13814 */   MCD_OPC_Decode, 151, 10, 174, 1, // Opcode: MVE_VMLSDAVxs32
+/* 13819 */   MCD_OPC_CheckPredicate, 22, 0, 45, 0, // Skip to: 25344
+/* 13824 */   MCD_OPC_Decode, 160, 10, 175, 1, // Opcode: MVE_VMLSLDAVxs32
+/* 13829 */   MCD_OPC_FilterValue, 2, 246, 44, 0, // Skip to: 25344
+/* 13834 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 13837 */   MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 13957
+/* 13842 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13845 */   MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 13917
+/* 13850 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13853 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 13885
+/* 13858 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13875
+/* 13863 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13875
+/* 13870 */   MCD_OPC_Decode, 141, 10, 176, 1, // Opcode: MVE_VMLSDAVas16
+/* 13875 */   MCD_OPC_CheckPredicate, 22, 200, 44, 0, // Skip to: 25344
+/* 13880 */   MCD_OPC_Decode, 153, 10, 177, 1, // Opcode: MVE_VMLSLDAVas16
+/* 13885 */   MCD_OPC_FilterValue, 15, 190, 44, 0, // Skip to: 25344
+/* 13890 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13907
+/* 13895 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13907
+/* 13902 */   MCD_OPC_Decode, 143, 10, 176, 1, // Opcode: MVE_VMLSDAVas8
+/* 13907 */   MCD_OPC_CheckPredicate, 22, 168, 44, 0, // Skip to: 25344
+/* 13912 */   MCD_OPC_Decode, 186, 12, 177, 1, // Opcode: MVE_VRMLSLDAVHas32
+/* 13917 */   MCD_OPC_FilterValue, 1, 158, 44, 0, // Skip to: 25344
+/* 13922 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13925 */   MCD_OPC_FilterValue, 14, 150, 44, 0, // Skip to: 25344
+/* 13930 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13947
+/* 13935 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13947
+/* 13942 */   MCD_OPC_Decode, 142, 10, 176, 1, // Opcode: MVE_VMLSDAVas32
+/* 13947 */   MCD_OPC_CheckPredicate, 22, 128, 44, 0, // Skip to: 25344
+/* 13952 */   MCD_OPC_Decode, 154, 10, 177, 1, // Opcode: MVE_VMLSLDAVas32
+/* 13957 */   MCD_OPC_FilterValue, 1, 118, 44, 0, // Skip to: 25344
+/* 13962 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 13965 */   MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 14037
+/* 13970 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 13973 */   MCD_OPC_FilterValue, 14, 27, 0, 0, // Skip to: 14005
+/* 13978 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 13995
+/* 13983 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 13995
+/* 13990 */   MCD_OPC_Decode, 144, 10, 176, 1, // Opcode: MVE_VMLSDAVaxs16
+/* 13995 */   MCD_OPC_CheckPredicate, 22, 80, 44, 0, // Skip to: 25344
+/* 14000 */   MCD_OPC_Decode, 155, 10, 177, 1, // Opcode: MVE_VMLSLDAVaxs16
+/* 14005 */   MCD_OPC_FilterValue, 15, 70, 44, 0, // Skip to: 25344
+/* 14010 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14027
+/* 14015 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14027
+/* 14022 */   MCD_OPC_Decode, 146, 10, 176, 1, // Opcode: MVE_VMLSDAVaxs8
+/* 14027 */   MCD_OPC_CheckPredicate, 22, 48, 44, 0, // Skip to: 25344
+/* 14032 */   MCD_OPC_Decode, 187, 12, 177, 1, // Opcode: MVE_VRMLSLDAVHaxs32
+/* 14037 */   MCD_OPC_FilterValue, 1, 38, 44, 0, // Skip to: 25344
+/* 14042 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14045 */   MCD_OPC_FilterValue, 14, 30, 44, 0, // Skip to: 25344
+/* 14050 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14067
+/* 14055 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14067
+/* 14062 */   MCD_OPC_Decode, 145, 10, 176, 1, // Opcode: MVE_VMLSDAVaxs32
+/* 14067 */   MCD_OPC_CheckPredicate, 22, 8, 44, 0, // Skip to: 25344
+/* 14072 */   MCD_OPC_Decode, 156, 10, 177, 1, // Opcode: MVE_VMLSLDAVaxs32
+/* 14077 */   MCD_OPC_FilterValue, 15, 254, 43, 0, // Skip to: 25344
+/* 14082 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 14085 */   MCD_OPC_FilterValue, 0, 154, 5, 0, // Skip to: 15524
+/* 14090 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 14093 */   MCD_OPC_FilterValue, 0, 196, 4, 0, // Skip to: 15318
+/* 14098 */   MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 14101 */   MCD_OPC_FilterValue, 0, 56, 3, 0, // Skip to: 14930
+/* 14106 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 14109 */   MCD_OPC_FilterValue, 0, 40, 2, 0, // Skip to: 14666
+/* 14114 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 14117 */   MCD_OPC_FilterValue, 0, 60, 1, 0, // Skip to: 14438
+/* 14122 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14125 */   MCD_OPC_FilterValue, 14, 190, 0, 0, // Skip to: 14320
+/* 14130 */   MCD_OPC_ExtractField, 17, 6,  // Inst{22-17} ...
+/* 14133 */   MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 14148
+/* 14138 */   MCD_OPC_CheckPredicate, 22, 110, 0, 0, // Skip to: 14253
+/* 14143 */   MCD_OPC_Decode, 183, 9, 178, 1, // Opcode: MVE_VMAXAVs8
+/* 14148 */   MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 14163
+/* 14153 */   MCD_OPC_CheckPredicate, 22, 95, 0, 0, // Skip to: 14253
+/* 14158 */   MCD_OPC_Decode, 197, 9, 178, 1, // Opcode: MVE_VMAXVs8
+/* 14163 */   MCD_OPC_FilterValue, 50, 10, 0, 0, // Skip to: 14178
+/* 14168 */   MCD_OPC_CheckPredicate, 22, 80, 0, 0, // Skip to: 14253
+/* 14173 */   MCD_OPC_Decode, 181, 9, 178, 1, // Opcode: MVE_VMAXAVs16
+/* 14178 */   MCD_OPC_FilterValue, 51, 10, 0, 0, // Skip to: 14193
+/* 14183 */   MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 14253
+/* 14188 */   MCD_OPC_Decode, 195, 9, 178, 1, // Opcode: MVE_VMAXVs16
+/* 14193 */   MCD_OPC_FilterValue, 52, 10, 0, 0, // Skip to: 14208
+/* 14198 */   MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 14253
+/* 14203 */   MCD_OPC_Decode, 182, 9, 178, 1, // Opcode: MVE_VMAXAVs32
+/* 14208 */   MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 14223
+/* 14213 */   MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 14253
+/* 14218 */   MCD_OPC_Decode, 196, 9, 178, 1, // Opcode: MVE_VMAXVs32
+/* 14223 */   MCD_OPC_FilterValue, 54, 10, 0, 0, // Skip to: 14238
+/* 14228 */   MCD_OPC_CheckPredicate, 24, 20, 0, 0, // Skip to: 14253
+/* 14233 */   MCD_OPC_Decode, 188, 9, 178, 1, // Opcode: MVE_VMAXNMAVf32
+/* 14238 */   MCD_OPC_FilterValue, 55, 10, 0, 0, // Skip to: 14253
+/* 14243 */   MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 14253
+/* 14248 */   MCD_OPC_Decode, 192, 9, 178, 1, // Opcode: MVE_VMAXNMVf32
+/* 14253 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 14256 */   MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 14288
+/* 14261 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14278
+/* 14266 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14278
+/* 14273 */   MCD_OPC_Decode, 244, 9, 174, 1, // Opcode: MVE_VMLADAVs8
+/* 14278 */   MCD_OPC_CheckPredicate, 22, 53, 43, 0, // Skip to: 25344
+/* 14283 */   MCD_OPC_Decode, 183, 12, 175, 1, // Opcode: MVE_VRMLALDAVHs32
+/* 14288 */   MCD_OPC_FilterValue, 1, 43, 43, 0, // Skip to: 25344
+/* 14293 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14310
+/* 14298 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14310
+/* 14305 */   MCD_OPC_Decode, 250, 9, 174, 1, // Opcode: MVE_VMLADAVxs8
+/* 14310 */   MCD_OPC_CheckPredicate, 22, 21, 43, 0, // Skip to: 25344
+/* 14315 */   MCD_OPC_Decode, 185, 12, 175, 1, // Opcode: MVE_VRMLALDAVHxs32
+/* 14320 */   MCD_OPC_FilterValue, 15, 11, 43, 0, // Skip to: 25344
+/* 14325 */   MCD_OPC_ExtractField, 17, 6,  // Inst{22-17} ...
+/* 14328 */   MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 14343
+/* 14333 */   MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 14403
+/* 14338 */   MCD_OPC_Decode, 200, 9, 178, 1, // Opcode: MVE_VMAXVu8
+/* 14343 */   MCD_OPC_FilterValue, 51, 10, 0, 0, // Skip to: 14358
+/* 14348 */   MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 14403
+/* 14353 */   MCD_OPC_Decode, 198, 9, 178, 1, // Opcode: MVE_VMAXVu16
+/* 14358 */   MCD_OPC_FilterValue, 53, 10, 0, 0, // Skip to: 14373
+/* 14363 */   MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 14403
+/* 14368 */   MCD_OPC_Decode, 199, 9, 178, 1, // Opcode: MVE_VMAXVu32
+/* 14373 */   MCD_OPC_FilterValue, 54, 10, 0, 0, // Skip to: 14388
+/* 14378 */   MCD_OPC_CheckPredicate, 24, 20, 0, 0, // Skip to: 14403
+/* 14383 */   MCD_OPC_Decode, 187, 9, 178, 1, // Opcode: MVE_VMAXNMAVf16
+/* 14388 */   MCD_OPC_FilterValue, 55, 10, 0, 0, // Skip to: 14403
+/* 14393 */   MCD_OPC_CheckPredicate, 24, 5, 0, 0, // Skip to: 14403
+/* 14398 */   MCD_OPC_Decode, 191, 9, 178, 1, // Opcode: MVE_VMAXNMVf16
+/* 14403 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 14406 */   MCD_OPC_FilterValue, 0, 181, 42, 0, // Skip to: 25344
+/* 14411 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14428
+/* 14416 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14428
+/* 14423 */   MCD_OPC_Decode, 247, 9, 174, 1, // Opcode: MVE_VMLADAVu8
+/* 14428 */   MCD_OPC_CheckPredicate, 22, 159, 42, 0, // Skip to: 25344
+/* 14433 */   MCD_OPC_Decode, 184, 12, 175, 1, // Opcode: MVE_VRMLALDAVHu32
+/* 14438 */   MCD_OPC_FilterValue, 1, 149, 42, 0, // Skip to: 25344
+/* 14443 */   MCD_OPC_ExtractField, 17, 3,  // Inst{19-17} ...
+/* 14446 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 14512
+/* 14451 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14454 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 14483
+/* 14459 */   MCD_OPC_CheckPredicate, 22, 128, 42, 0, // Skip to: 25344
+/* 14464 */   MCD_OPC_CheckField, 20, 3, 7, 121, 42, 0, // Skip to: 25344
+/* 14471 */   MCD_OPC_CheckField, 12, 1, 0, 114, 42, 0, // Skip to: 25344
+/* 14478 */   MCD_OPC_Decode, 203, 7, 179, 1, // Opcode: MVE_VADDVs8no_acc
+/* 14483 */   MCD_OPC_FilterValue, 15, 104, 42, 0, // Skip to: 25344
+/* 14488 */   MCD_OPC_CheckPredicate, 22, 99, 42, 0, // Skip to: 25344
+/* 14493 */   MCD_OPC_CheckField, 20, 3, 7, 92, 42, 0, // Skip to: 25344
+/* 14500 */   MCD_OPC_CheckField, 12, 1, 0, 85, 42, 0, // Skip to: 25344
+/* 14507 */   MCD_OPC_Decode, 209, 7, 179, 1, // Opcode: MVE_VADDVu8no_acc
+/* 14512 */   MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 14578
+/* 14517 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14520 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 14549
+/* 14525 */   MCD_OPC_CheckPredicate, 22, 62, 42, 0, // Skip to: 25344
+/* 14530 */   MCD_OPC_CheckField, 20, 3, 7, 55, 42, 0, // Skip to: 25344
+/* 14537 */   MCD_OPC_CheckField, 12, 1, 0, 48, 42, 0, // Skip to: 25344
+/* 14544 */   MCD_OPC_Decode, 199, 7, 179, 1, // Opcode: MVE_VADDVs16no_acc
+/* 14549 */   MCD_OPC_FilterValue, 15, 38, 42, 0, // Skip to: 25344
+/* 14554 */   MCD_OPC_CheckPredicate, 22, 33, 42, 0, // Skip to: 25344
+/* 14559 */   MCD_OPC_CheckField, 20, 3, 7, 26, 42, 0, // Skip to: 25344
+/* 14566 */   MCD_OPC_CheckField, 12, 1, 0, 19, 42, 0, // Skip to: 25344
+/* 14573 */   MCD_OPC_Decode, 205, 7, 179, 1, // Opcode: MVE_VADDVu16no_acc
+/* 14578 */   MCD_OPC_FilterValue, 4, 9, 42, 0, // Skip to: 25344
+/* 14583 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14586 */   MCD_OPC_FilterValue, 14, 35, 0, 0, // Skip to: 14626
+/* 14591 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 14594 */   MCD_OPC_FilterValue, 0, 249, 41, 0, // Skip to: 25344
+/* 14599 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14616
+/* 14604 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14616
+/* 14611 */   MCD_OPC_Decode, 201, 7, 179, 1, // Opcode: MVE_VADDVs32no_acc
+/* 14616 */   MCD_OPC_CheckPredicate, 22, 227, 41, 0, // Skip to: 25344
+/* 14621 */   MCD_OPC_Decode, 195, 7, 180, 1, // Opcode: MVE_VADDLVs32no_acc
+/* 14626 */   MCD_OPC_FilterValue, 15, 217, 41, 0, // Skip to: 25344
+/* 14631 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 14634 */   MCD_OPC_FilterValue, 0, 209, 41, 0, // Skip to: 25344
+/* 14639 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14656
+/* 14644 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14656
+/* 14651 */   MCD_OPC_Decode, 207, 7, 179, 1, // Opcode: MVE_VADDVu32no_acc
+/* 14656 */   MCD_OPC_CheckPredicate, 22, 187, 41, 0, // Skip to: 25344
+/* 14661 */   MCD_OPC_Decode, 197, 7, 180, 1, // Opcode: MVE_VADDLVu32no_acc
+/* 14666 */   MCD_OPC_FilterValue, 1, 177, 41, 0, // Skip to: 25344
+/* 14671 */   MCD_OPC_ExtractField, 16, 7,  // Inst{22-16} ...
+/* 14674 */   MCD_OPC_FilterValue, 96, 17, 0, 0, // Skip to: 14696
+/* 14679 */   MCD_OPC_CheckPredicate, 22, 164, 41, 0, // Skip to: 25344
+/* 14684 */   MCD_OPC_CheckField, 28, 4, 14, 157, 41, 0, // Skip to: 25344
+/* 14691 */   MCD_OPC_Decode, 209, 9, 178, 1, // Opcode: MVE_VMINAVs8
+/* 14696 */   MCD_OPC_FilterValue, 98, 33, 0, 0, // Skip to: 14734
+/* 14701 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14704 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14719
+/* 14709 */   MCD_OPC_CheckPredicate, 22, 134, 41, 0, // Skip to: 25344
+/* 14714 */   MCD_OPC_Decode, 223, 9, 178, 1, // Opcode: MVE_VMINVs8
+/* 14719 */   MCD_OPC_FilterValue, 15, 124, 41, 0, // Skip to: 25344
+/* 14724 */   MCD_OPC_CheckPredicate, 22, 119, 41, 0, // Skip to: 25344
+/* 14729 */   MCD_OPC_Decode, 226, 9, 178, 1, // Opcode: MVE_VMINVu8
+/* 14734 */   MCD_OPC_FilterValue, 100, 17, 0, 0, // Skip to: 14756
+/* 14739 */   MCD_OPC_CheckPredicate, 22, 104, 41, 0, // Skip to: 25344
+/* 14744 */   MCD_OPC_CheckField, 28, 4, 14, 97, 41, 0, // Skip to: 25344
+/* 14751 */   MCD_OPC_Decode, 207, 9, 178, 1, // Opcode: MVE_VMINAVs16
+/* 14756 */   MCD_OPC_FilterValue, 102, 33, 0, 0, // Skip to: 14794
+/* 14761 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14764 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14779
+/* 14769 */   MCD_OPC_CheckPredicate, 22, 74, 41, 0, // Skip to: 25344
+/* 14774 */   MCD_OPC_Decode, 221, 9, 178, 1, // Opcode: MVE_VMINVs16
+/* 14779 */   MCD_OPC_FilterValue, 15, 64, 41, 0, // Skip to: 25344
+/* 14784 */   MCD_OPC_CheckPredicate, 22, 59, 41, 0, // Skip to: 25344
+/* 14789 */   MCD_OPC_Decode, 224, 9, 178, 1, // Opcode: MVE_VMINVu16
+/* 14794 */   MCD_OPC_FilterValue, 104, 17, 0, 0, // Skip to: 14816
+/* 14799 */   MCD_OPC_CheckPredicate, 22, 44, 41, 0, // Skip to: 25344
+/* 14804 */   MCD_OPC_CheckField, 28, 4, 14, 37, 41, 0, // Skip to: 25344
+/* 14811 */   MCD_OPC_Decode, 208, 9, 178, 1, // Opcode: MVE_VMINAVs32
+/* 14816 */   MCD_OPC_FilterValue, 106, 33, 0, 0, // Skip to: 14854
+/* 14821 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14824 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14839
+/* 14829 */   MCD_OPC_CheckPredicate, 22, 14, 41, 0, // Skip to: 25344
+/* 14834 */   MCD_OPC_Decode, 222, 9, 178, 1, // Opcode: MVE_VMINVs32
+/* 14839 */   MCD_OPC_FilterValue, 15, 4, 41, 0, // Skip to: 25344
+/* 14844 */   MCD_OPC_CheckPredicate, 22, 255, 40, 0, // Skip to: 25344
+/* 14849 */   MCD_OPC_Decode, 225, 9, 178, 1, // Opcode: MVE_VMINVu32
+/* 14854 */   MCD_OPC_FilterValue, 108, 33, 0, 0, // Skip to: 14892
+/* 14859 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14862 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14877
+/* 14867 */   MCD_OPC_CheckPredicate, 24, 232, 40, 0, // Skip to: 25344
+/* 14872 */   MCD_OPC_Decode, 214, 9, 178, 1, // Opcode: MVE_VMINNMAVf32
+/* 14877 */   MCD_OPC_FilterValue, 15, 222, 40, 0, // Skip to: 25344
+/* 14882 */   MCD_OPC_CheckPredicate, 24, 217, 40, 0, // Skip to: 25344
+/* 14887 */   MCD_OPC_Decode, 213, 9, 178, 1, // Opcode: MVE_VMINNMAVf16
+/* 14892 */   MCD_OPC_FilterValue, 110, 207, 40, 0, // Skip to: 25344
+/* 14897 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14900 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 14915
+/* 14905 */   MCD_OPC_CheckPredicate, 24, 194, 40, 0, // Skip to: 25344
+/* 14910 */   MCD_OPC_Decode, 218, 9, 178, 1, // Opcode: MVE_VMINNMVf32
+/* 14915 */   MCD_OPC_FilterValue, 15, 184, 40, 0, // Skip to: 25344
+/* 14920 */   MCD_OPC_CheckPredicate, 24, 179, 40, 0, // Skip to: 25344
+/* 14925 */   MCD_OPC_Decode, 217, 9, 178, 1, // Opcode: MVE_VMINNMVf16
+/* 14930 */   MCD_OPC_FilterValue, 2, 169, 40, 0, // Skip to: 25344
+/* 14935 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 14938 */   MCD_OPC_FilterValue, 0, 63, 1, 0, // Skip to: 15262
+/* 14943 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 14946 */   MCD_OPC_FilterValue, 0, 83, 0, 0, // Skip to: 15034
+/* 14951 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 14954 */   MCD_OPC_FilterValue, 14, 35, 0, 0, // Skip to: 14994
+/* 14959 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 14962 */   MCD_OPC_FilterValue, 0, 137, 40, 0, // Skip to: 25344
+/* 14967 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 14984
+/* 14972 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 14984
+/* 14979 */   MCD_OPC_Decode, 235, 9, 176, 1, // Opcode: MVE_VMLADAVas8
+/* 14984 */   MCD_OPC_CheckPredicate, 22, 115, 40, 0, // Skip to: 25344
+/* 14989 */   MCD_OPC_Decode, 180, 12, 177, 1, // Opcode: MVE_VRMLALDAVHas32
+/* 14994 */   MCD_OPC_FilterValue, 15, 105, 40, 0, // Skip to: 25344
+/* 14999 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 15002 */   MCD_OPC_FilterValue, 0, 97, 40, 0, // Skip to: 25344
+/* 15007 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 15024
+/* 15012 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 15024
+/* 15019 */   MCD_OPC_Decode, 238, 9, 176, 1, // Opcode: MVE_VMLADAVau8
+/* 15024 */   MCD_OPC_CheckPredicate, 22, 75, 40, 0, // Skip to: 25344
+/* 15029 */   MCD_OPC_Decode, 181, 12, 177, 1, // Opcode: MVE_VRMLALDAVHau32
+/* 15034 */   MCD_OPC_FilterValue, 1, 65, 40, 0, // Skip to: 25344
+/* 15039 */   MCD_OPC_ExtractField, 17, 3,  // Inst{19-17} ...
+/* 15042 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 15108
+/* 15047 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15050 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15079
+/* 15055 */   MCD_OPC_CheckPredicate, 22, 44, 40, 0, // Skip to: 25344
+/* 15060 */   MCD_OPC_CheckField, 20, 3, 7, 37, 40, 0, // Skip to: 25344
+/* 15067 */   MCD_OPC_CheckField, 7, 1, 0, 30, 40, 0, // Skip to: 25344
+/* 15074 */   MCD_OPC_Decode, 202, 7, 181, 1, // Opcode: MVE_VADDVs8acc
+/* 15079 */   MCD_OPC_FilterValue, 15, 20, 40, 0, // Skip to: 25344
+/* 15084 */   MCD_OPC_CheckPredicate, 22, 15, 40, 0, // Skip to: 25344
+/* 15089 */   MCD_OPC_CheckField, 20, 3, 7, 8, 40, 0, // Skip to: 25344
+/* 15096 */   MCD_OPC_CheckField, 7, 1, 0, 1, 40, 0, // Skip to: 25344
+/* 15103 */   MCD_OPC_Decode, 208, 7, 181, 1, // Opcode: MVE_VADDVu8acc
+/* 15108 */   MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 15174
+/* 15113 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15116 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15145
+/* 15121 */   MCD_OPC_CheckPredicate, 22, 234, 39, 0, // Skip to: 25344
+/* 15126 */   MCD_OPC_CheckField, 20, 3, 7, 227, 39, 0, // Skip to: 25344
+/* 15133 */   MCD_OPC_CheckField, 7, 1, 0, 220, 39, 0, // Skip to: 25344
+/* 15140 */   MCD_OPC_Decode, 198, 7, 181, 1, // Opcode: MVE_VADDVs16acc
+/* 15145 */   MCD_OPC_FilterValue, 15, 210, 39, 0, // Skip to: 25344
+/* 15150 */   MCD_OPC_CheckPredicate, 22, 205, 39, 0, // Skip to: 25344
+/* 15155 */   MCD_OPC_CheckField, 20, 3, 7, 198, 39, 0, // Skip to: 25344
+/* 15162 */   MCD_OPC_CheckField, 7, 1, 0, 191, 39, 0, // Skip to: 25344
+/* 15169 */   MCD_OPC_Decode, 204, 7, 181, 1, // Opcode: MVE_VADDVu16acc
+/* 15174 */   MCD_OPC_FilterValue, 4, 181, 39, 0, // Skip to: 25344
+/* 15179 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15182 */   MCD_OPC_FilterValue, 14, 35, 0, 0, // Skip to: 15222
+/* 15187 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 15190 */   MCD_OPC_FilterValue, 0, 165, 39, 0, // Skip to: 25344
+/* 15195 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 15212
+/* 15200 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 15212
+/* 15207 */   MCD_OPC_Decode, 200, 7, 181, 1, // Opcode: MVE_VADDVs32acc
+/* 15212 */   MCD_OPC_CheckPredicate, 22, 143, 39, 0, // Skip to: 25344
+/* 15217 */   MCD_OPC_Decode, 194, 7, 182, 1, // Opcode: MVE_VADDLVs32acc
+/* 15222 */   MCD_OPC_FilterValue, 15, 133, 39, 0, // Skip to: 25344
+/* 15227 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 15230 */   MCD_OPC_FilterValue, 0, 125, 39, 0, // Skip to: 25344
+/* 15235 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 15252
+/* 15240 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 15252
+/* 15247 */   MCD_OPC_Decode, 206, 7, 181, 1, // Opcode: MVE_VADDVu32acc
+/* 15252 */   MCD_OPC_CheckPredicate, 22, 103, 39, 0, // Skip to: 25344
+/* 15257 */   MCD_OPC_Decode, 196, 7, 182, 1, // Opcode: MVE_VADDLVu32acc
+/* 15262 */   MCD_OPC_FilterValue, 1, 93, 39, 0, // Skip to: 25344
+/* 15267 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 15270 */   MCD_OPC_FilterValue, 0, 85, 39, 0, // Skip to: 25344
+/* 15275 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 15278 */   MCD_OPC_FilterValue, 0, 77, 39, 0, // Skip to: 25344
+/* 15283 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15286 */   MCD_OPC_FilterValue, 14, 69, 39, 0, // Skip to: 25344
+/* 15291 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 15308
+/* 15296 */   MCD_OPC_CheckField, 20, 3, 7, 5, 0, 0, // Skip to: 15308
+/* 15303 */   MCD_OPC_Decode, 241, 9, 176, 1, // Opcode: MVE_VMLADAVaxs8
+/* 15308 */   MCD_OPC_CheckPredicate, 22, 47, 39, 0, // Skip to: 25344
+/* 15313 */   MCD_OPC_Decode, 182, 12, 177, 1, // Opcode: MVE_VRMLALDAVHaxs32
+/* 15318 */   MCD_OPC_FilterValue, 1, 37, 39, 0, // Skip to: 25344
+/* 15323 */   MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
+/* 15326 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 15392
+/* 15331 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15334 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15363
+/* 15339 */   MCD_OPC_CheckPredicate, 22, 16, 39, 0, // Skip to: 25344
+/* 15344 */   MCD_OPC_CheckField, 16, 1, 0, 9, 39, 0, // Skip to: 25344
+/* 15351 */   MCD_OPC_CheckField, 4, 1, 0, 2, 39, 0, // Skip to: 25344
+/* 15358 */   MCD_OPC_Decode, 175, 7, 183, 1, // Opcode: MVE_VABAVs8
+/* 15363 */   MCD_OPC_FilterValue, 15, 248, 38, 0, // Skip to: 25344
+/* 15368 */   MCD_OPC_CheckPredicate, 22, 243, 38, 0, // Skip to: 25344
+/* 15373 */   MCD_OPC_CheckField, 16, 1, 0, 236, 38, 0, // Skip to: 25344
+/* 15380 */   MCD_OPC_CheckField, 4, 1, 0, 229, 38, 0, // Skip to: 25344
+/* 15387 */   MCD_OPC_Decode, 178, 7, 183, 1, // Opcode: MVE_VABAVu8
+/* 15392 */   MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 15458
+/* 15397 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15400 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15429
+/* 15405 */   MCD_OPC_CheckPredicate, 22, 206, 38, 0, // Skip to: 25344
+/* 15410 */   MCD_OPC_CheckField, 16, 1, 0, 199, 38, 0, // Skip to: 25344
+/* 15417 */   MCD_OPC_CheckField, 4, 1, 0, 192, 38, 0, // Skip to: 25344
+/* 15424 */   MCD_OPC_Decode, 173, 7, 183, 1, // Opcode: MVE_VABAVs16
+/* 15429 */   MCD_OPC_FilterValue, 15, 182, 38, 0, // Skip to: 25344
+/* 15434 */   MCD_OPC_CheckPredicate, 22, 177, 38, 0, // Skip to: 25344
+/* 15439 */   MCD_OPC_CheckField, 16, 1, 0, 170, 38, 0, // Skip to: 25344
+/* 15446 */   MCD_OPC_CheckField, 4, 1, 0, 163, 38, 0, // Skip to: 25344
+/* 15453 */   MCD_OPC_Decode, 176, 7, 183, 1, // Opcode: MVE_VABAVu16
+/* 15458 */   MCD_OPC_FilterValue, 2, 153, 38, 0, // Skip to: 25344
+/* 15463 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15466 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15495
+/* 15471 */   MCD_OPC_CheckPredicate, 22, 140, 38, 0, // Skip to: 25344
+/* 15476 */   MCD_OPC_CheckField, 16, 1, 0, 133, 38, 0, // Skip to: 25344
+/* 15483 */   MCD_OPC_CheckField, 4, 1, 0, 126, 38, 0, // Skip to: 25344
+/* 15490 */   MCD_OPC_Decode, 174, 7, 183, 1, // Opcode: MVE_VABAVs32
+/* 15495 */   MCD_OPC_FilterValue, 15, 116, 38, 0, // Skip to: 25344
+/* 15500 */   MCD_OPC_CheckPredicate, 22, 111, 38, 0, // Skip to: 25344
+/* 15505 */   MCD_OPC_CheckField, 16, 1, 0, 104, 38, 0, // Skip to: 25344
+/* 15512 */   MCD_OPC_CheckField, 4, 1, 0, 97, 38, 0, // Skip to: 25344
+/* 15519 */   MCD_OPC_Decode, 177, 7, 183, 1, // Opcode: MVE_VABAVu32
+/* 15524 */   MCD_OPC_FilterValue, 1, 87, 38, 0, // Skip to: 25344
+/* 15529 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 15532 */   MCD_OPC_FilterValue, 0, 219, 3, 0, // Skip to: 16524
+/* 15537 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 15540 */   MCD_OPC_FilterValue, 0, 27, 1, 0, // Skip to: 15828
+/* 15545 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 15548 */   MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 15688
+/* 15553 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 15556 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 15622
+/* 15561 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15564 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15593
+/* 15569 */   MCD_OPC_CheckPredicate, 22, 42, 38, 0, // Skip to: 25344
+/* 15574 */   MCD_OPC_CheckField, 19, 1, 1, 35, 38, 0, // Skip to: 25344
+/* 15581 */   MCD_OPC_CheckField, 4, 1, 0, 28, 38, 0, // Skip to: 25344
+/* 15588 */   MCD_OPC_Decode, 132, 12, 184, 1, // Opcode: MVE_VQSHRNbhs16
+/* 15593 */   MCD_OPC_FilterValue, 15, 18, 38, 0, // Skip to: 25344
+/* 15598 */   MCD_OPC_CheckPredicate, 22, 13, 38, 0, // Skip to: 25344
+/* 15603 */   MCD_OPC_CheckField, 19, 1, 1, 6, 38, 0, // Skip to: 25344
+/* 15610 */   MCD_OPC_CheckField, 4, 1, 0, 255, 37, 0, // Skip to: 25344
+/* 15617 */   MCD_OPC_Decode, 134, 12, 184, 1, // Opcode: MVE_VQSHRNbhu16
+/* 15622 */   MCD_OPC_FilterValue, 1, 245, 37, 0, // Skip to: 25344
+/* 15627 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15630 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15659
+/* 15635 */   MCD_OPC_CheckPredicate, 22, 232, 37, 0, // Skip to: 25344
+/* 15640 */   MCD_OPC_CheckField, 19, 1, 1, 225, 37, 0, // Skip to: 25344
+/* 15647 */   MCD_OPC_CheckField, 4, 1, 0, 218, 37, 0, // Skip to: 25344
+/* 15654 */   MCD_OPC_Decode, 136, 12, 184, 1, // Opcode: MVE_VQSHRNths16
+/* 15659 */   MCD_OPC_FilterValue, 15, 208, 37, 0, // Skip to: 25344
+/* 15664 */   MCD_OPC_CheckPredicate, 22, 203, 37, 0, // Skip to: 25344
+/* 15669 */   MCD_OPC_CheckField, 19, 1, 1, 196, 37, 0, // Skip to: 25344
+/* 15676 */   MCD_OPC_CheckField, 4, 1, 0, 189, 37, 0, // Skip to: 25344
+/* 15683 */   MCD_OPC_Decode, 138, 12, 184, 1, // Opcode: MVE_VQSHRNthu16
+/* 15688 */   MCD_OPC_FilterValue, 1, 179, 37, 0, // Skip to: 25344
+/* 15693 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 15696 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 15762
+/* 15701 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15704 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15733
+/* 15709 */   MCD_OPC_CheckPredicate, 22, 158, 37, 0, // Skip to: 25344
+/* 15714 */   MCD_OPC_CheckField, 19, 1, 1, 151, 37, 0, // Skip to: 25344
+/* 15721 */   MCD_OPC_CheckField, 4, 1, 0, 144, 37, 0, // Skip to: 25344
+/* 15728 */   MCD_OPC_Decode, 227, 11, 184, 1, // Opcode: MVE_VQRSHRNbhs16
+/* 15733 */   MCD_OPC_FilterValue, 15, 134, 37, 0, // Skip to: 25344
+/* 15738 */   MCD_OPC_CheckPredicate, 22, 129, 37, 0, // Skip to: 25344
+/* 15743 */   MCD_OPC_CheckField, 19, 1, 1, 122, 37, 0, // Skip to: 25344
+/* 15750 */   MCD_OPC_CheckField, 4, 1, 0, 115, 37, 0, // Skip to: 25344
+/* 15757 */   MCD_OPC_Decode, 229, 11, 184, 1, // Opcode: MVE_VQRSHRNbhu16
+/* 15762 */   MCD_OPC_FilterValue, 1, 105, 37, 0, // Skip to: 25344
+/* 15767 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15770 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 15799
+/* 15775 */   MCD_OPC_CheckPredicate, 22, 92, 37, 0, // Skip to: 25344
+/* 15780 */   MCD_OPC_CheckField, 19, 1, 1, 85, 37, 0, // Skip to: 25344
+/* 15787 */   MCD_OPC_CheckField, 4, 1, 0, 78, 37, 0, // Skip to: 25344
+/* 15794 */   MCD_OPC_Decode, 231, 11, 184, 1, // Opcode: MVE_VQRSHRNths16
+/* 15799 */   MCD_OPC_FilterValue, 15, 68, 37, 0, // Skip to: 25344
+/* 15804 */   MCD_OPC_CheckPredicate, 22, 63, 37, 0, // Skip to: 25344
+/* 15809 */   MCD_OPC_CheckField, 19, 1, 1, 56, 37, 0, // Skip to: 25344
+/* 15816 */   MCD_OPC_CheckField, 4, 1, 0, 49, 37, 0, // Skip to: 25344
+/* 15823 */   MCD_OPC_Decode, 233, 11, 184, 1, // Opcode: MVE_VQRSHRNthu16
+/* 15828 */   MCD_OPC_FilterValue, 1, 227, 0, 0, // Skip to: 16060
+/* 15833 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 15836 */   MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 15948
+/* 15841 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 15844 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 15896
+/* 15849 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15852 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 15874
+/* 15857 */   MCD_OPC_CheckPredicate, 22, 10, 37, 0, // Skip to: 25344
+/* 15862 */   MCD_OPC_CheckField, 4, 1, 0, 3, 37, 0, // Skip to: 25344
+/* 15869 */   MCD_OPC_Decode, 133, 12, 185, 1, // Opcode: MVE_VQSHRNbhs32
+/* 15874 */   MCD_OPC_FilterValue, 15, 249, 36, 0, // Skip to: 25344
+/* 15879 */   MCD_OPC_CheckPredicate, 22, 244, 36, 0, // Skip to: 25344
+/* 15884 */   MCD_OPC_CheckField, 4, 1, 0, 237, 36, 0, // Skip to: 25344
+/* 15891 */   MCD_OPC_Decode, 135, 12, 185, 1, // Opcode: MVE_VQSHRNbhu32
+/* 15896 */   MCD_OPC_FilterValue, 1, 227, 36, 0, // Skip to: 25344
+/* 15901 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15904 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 15926
+/* 15909 */   MCD_OPC_CheckPredicate, 22, 214, 36, 0, // Skip to: 25344
+/* 15914 */   MCD_OPC_CheckField, 4, 1, 0, 207, 36, 0, // Skip to: 25344
+/* 15921 */   MCD_OPC_Decode, 137, 12, 185, 1, // Opcode: MVE_VQSHRNths32
+/* 15926 */   MCD_OPC_FilterValue, 15, 197, 36, 0, // Skip to: 25344
+/* 15931 */   MCD_OPC_CheckPredicate, 22, 192, 36, 0, // Skip to: 25344
+/* 15936 */   MCD_OPC_CheckField, 4, 1, 0, 185, 36, 0, // Skip to: 25344
+/* 15943 */   MCD_OPC_Decode, 139, 12, 185, 1, // Opcode: MVE_VQSHRNthu32
+/* 15948 */   MCD_OPC_FilterValue, 1, 175, 36, 0, // Skip to: 25344
+/* 15953 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 15956 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16008
+/* 15961 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 15964 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 15986
+/* 15969 */   MCD_OPC_CheckPredicate, 22, 154, 36, 0, // Skip to: 25344
+/* 15974 */   MCD_OPC_CheckField, 4, 1, 0, 147, 36, 0, // Skip to: 25344
+/* 15981 */   MCD_OPC_Decode, 228, 11, 185, 1, // Opcode: MVE_VQRSHRNbhs32
+/* 15986 */   MCD_OPC_FilterValue, 15, 137, 36, 0, // Skip to: 25344
+/* 15991 */   MCD_OPC_CheckPredicate, 22, 132, 36, 0, // Skip to: 25344
+/* 15996 */   MCD_OPC_CheckField, 4, 1, 0, 125, 36, 0, // Skip to: 25344
+/* 16003 */   MCD_OPC_Decode, 230, 11, 185, 1, // Opcode: MVE_VQRSHRNbhu32
+/* 16008 */   MCD_OPC_FilterValue, 1, 115, 36, 0, // Skip to: 25344
+/* 16013 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16016 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16038
+/* 16021 */   MCD_OPC_CheckPredicate, 22, 102, 36, 0, // Skip to: 25344
+/* 16026 */   MCD_OPC_CheckField, 4, 1, 0, 95, 36, 0, // Skip to: 25344
+/* 16033 */   MCD_OPC_Decode, 232, 11, 185, 1, // Opcode: MVE_VQRSHRNths32
+/* 16038 */   MCD_OPC_FilterValue, 15, 85, 36, 0, // Skip to: 25344
+/* 16043 */   MCD_OPC_CheckPredicate, 22, 80, 36, 0, // Skip to: 25344
+/* 16048 */   MCD_OPC_CheckField, 4, 1, 0, 73, 36, 0, // Skip to: 25344
+/* 16055 */   MCD_OPC_Decode, 234, 11, 185, 1, // Opcode: MVE_VQRSHRNthu32
+/* 16060 */   MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 16308
+/* 16065 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 16068 */   MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 16188
+/* 16073 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16076 */   MCD_OPC_FilterValue, 14, 51, 0, 0, // Skip to: 16132
+/* 16081 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16084 */   MCD_OPC_FilterValue, 0, 39, 36, 0, // Skip to: 25344
+/* 16089 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16092 */   MCD_OPC_FilterValue, 0, 31, 36, 0, // Skip to: 25344
+/* 16097 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 16100 */   MCD_OPC_FilterValue, 1, 23, 36, 0, // Skip to: 25344
+/* 16105 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16122
+/* 16110 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 16122
+/* 16117 */   MCD_OPC_Decode, 163, 10, 147, 1, // Opcode: MVE_VMOVLs8bh
+/* 16122 */   MCD_OPC_CheckPredicate, 22, 1, 36, 0, // Skip to: 25344
+/* 16127 */   MCD_OPC_Decode, 223, 12, 186, 1, // Opcode: MVE_VSHLL_imms8bh
+/* 16132 */   MCD_OPC_FilterValue, 15, 247, 35, 0, // Skip to: 25344
+/* 16137 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16140 */   MCD_OPC_FilterValue, 0, 239, 35, 0, // Skip to: 25344
+/* 16145 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16148 */   MCD_OPC_FilterValue, 0, 231, 35, 0, // Skip to: 25344
+/* 16153 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 16156 */   MCD_OPC_FilterValue, 1, 223, 35, 0, // Skip to: 25344
+/* 16161 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16178
+/* 16166 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 16178
+/* 16173 */   MCD_OPC_Decode, 167, 10, 147, 1, // Opcode: MVE_VMOVLu8bh
+/* 16178 */   MCD_OPC_CheckPredicate, 22, 201, 35, 0, // Skip to: 25344
+/* 16183 */   MCD_OPC_Decode, 227, 12, 186, 1, // Opcode: MVE_VSHLL_immu8bh
+/* 16188 */   MCD_OPC_FilterValue, 1, 191, 35, 0, // Skip to: 25344
+/* 16193 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16196 */   MCD_OPC_FilterValue, 14, 51, 0, 0, // Skip to: 16252
+/* 16201 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16204 */   MCD_OPC_FilterValue, 0, 175, 35, 0, // Skip to: 25344
+/* 16209 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16212 */   MCD_OPC_FilterValue, 0, 167, 35, 0, // Skip to: 25344
+/* 16217 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 16220 */   MCD_OPC_FilterValue, 1, 159, 35, 0, // Skip to: 25344
+/* 16225 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16242
+/* 16230 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 16242
+/* 16237 */   MCD_OPC_Decode, 164, 10, 147, 1, // Opcode: MVE_VMOVLs8th
+/* 16242 */   MCD_OPC_CheckPredicate, 22, 137, 35, 0, // Skip to: 25344
+/* 16247 */   MCD_OPC_Decode, 224, 12, 186, 1, // Opcode: MVE_VSHLL_imms8th
+/* 16252 */   MCD_OPC_FilterValue, 15, 127, 35, 0, // Skip to: 25344
+/* 16257 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16260 */   MCD_OPC_FilterValue, 0, 119, 35, 0, // Skip to: 25344
+/* 16265 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16268 */   MCD_OPC_FilterValue, 0, 111, 35, 0, // Skip to: 25344
+/* 16273 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 16276 */   MCD_OPC_FilterValue, 1, 103, 35, 0, // Skip to: 25344
+/* 16281 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16298
+/* 16286 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 16298
+/* 16293 */   MCD_OPC_Decode, 168, 10, 147, 1, // Opcode: MVE_VMOVLu8th
+/* 16298 */   MCD_OPC_CheckPredicate, 22, 81, 35, 0, // Skip to: 25344
+/* 16303 */   MCD_OPC_Decode, 228, 12, 186, 1, // Opcode: MVE_VSHLL_immu8th
+/* 16308 */   MCD_OPC_FilterValue, 3, 71, 35, 0, // Skip to: 25344
+/* 16313 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 16316 */   MCD_OPC_FilterValue, 0, 99, 0, 0, // Skip to: 16420
+/* 16321 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16324 */   MCD_OPC_FilterValue, 14, 43, 0, 0, // Skip to: 16372
+/* 16329 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16332 */   MCD_OPC_FilterValue, 0, 47, 35, 0, // Skip to: 25344
+/* 16337 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16340 */   MCD_OPC_FilterValue, 0, 39, 35, 0, // Skip to: 25344
+/* 16345 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16362
+/* 16350 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 16362
+/* 16357 */   MCD_OPC_Decode, 161, 10, 147, 1, // Opcode: MVE_VMOVLs16bh
+/* 16362 */   MCD_OPC_CheckPredicate, 22, 17, 35, 0, // Skip to: 25344
+/* 16367 */   MCD_OPC_Decode, 221, 12, 187, 1, // Opcode: MVE_VSHLL_imms16bh
+/* 16372 */   MCD_OPC_FilterValue, 15, 7, 35, 0, // Skip to: 25344
+/* 16377 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16380 */   MCD_OPC_FilterValue, 0, 255, 34, 0, // Skip to: 25344
+/* 16385 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16388 */   MCD_OPC_FilterValue, 0, 247, 34, 0, // Skip to: 25344
+/* 16393 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16410
+/* 16398 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 16410
+/* 16405 */   MCD_OPC_Decode, 165, 10, 147, 1, // Opcode: MVE_VMOVLu16bh
+/* 16410 */   MCD_OPC_CheckPredicate, 22, 225, 34, 0, // Skip to: 25344
+/* 16415 */   MCD_OPC_Decode, 225, 12, 187, 1, // Opcode: MVE_VSHLL_immu16bh
+/* 16420 */   MCD_OPC_FilterValue, 1, 215, 34, 0, // Skip to: 25344
+/* 16425 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16428 */   MCD_OPC_FilterValue, 14, 43, 0, 0, // Skip to: 16476
+/* 16433 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16436 */   MCD_OPC_FilterValue, 0, 199, 34, 0, // Skip to: 25344
+/* 16441 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16444 */   MCD_OPC_FilterValue, 0, 191, 34, 0, // Skip to: 25344
+/* 16449 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16466
+/* 16454 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 16466
+/* 16461 */   MCD_OPC_Decode, 162, 10, 147, 1, // Opcode: MVE_VMOVLs16th
+/* 16466 */   MCD_OPC_CheckPredicate, 22, 169, 34, 0, // Skip to: 25344
+/* 16471 */   MCD_OPC_Decode, 222, 12, 187, 1, // Opcode: MVE_VSHLL_imms16th
+/* 16476 */   MCD_OPC_FilterValue, 15, 159, 34, 0, // Skip to: 25344
+/* 16481 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16484 */   MCD_OPC_FilterValue, 0, 151, 34, 0, // Skip to: 25344
+/* 16489 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 16492 */   MCD_OPC_FilterValue, 0, 143, 34, 0, // Skip to: 25344
+/* 16497 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 16514
+/* 16502 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 16514
+/* 16509 */   MCD_OPC_Decode, 166, 10, 147, 1, // Opcode: MVE_VMOVLu16th
+/* 16514 */   MCD_OPC_CheckPredicate, 22, 121, 34, 0, // Skip to: 25344
+/* 16519 */   MCD_OPC_Decode, 226, 12, 187, 1, // Opcode: MVE_VSHLL_immu16th
+/* 16524 */   MCD_OPC_FilterValue, 1, 111, 34, 0, // Skip to: 25344
+/* 16529 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 16532 */   MCD_OPC_FilterValue, 0, 36, 1, 0, // Skip to: 16829
+/* 16537 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 16540 */   MCD_OPC_FilterValue, 0, 255, 0, 0, // Skip to: 16800
+/* 16545 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16548 */   MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 16674
+/* 16553 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 16556 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 16622
+/* 16561 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16564 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 16593
+/* 16569 */   MCD_OPC_CheckPredicate, 22, 66, 34, 0, // Skip to: 25344
+/* 16574 */   MCD_OPC_CheckField, 19, 1, 1, 59, 34, 0, // Skip to: 25344
+/* 16581 */   MCD_OPC_CheckField, 4, 1, 0, 52, 34, 0, // Skip to: 25344
+/* 16588 */   MCD_OPC_Decode, 140, 12, 184, 1, // Opcode: MVE_VQSHRUNs16bh
+/* 16593 */   MCD_OPC_FilterValue, 15, 42, 34, 0, // Skip to: 25344
+/* 16598 */   MCD_OPC_CheckPredicate, 22, 37, 34, 0, // Skip to: 25344
+/* 16603 */   MCD_OPC_CheckField, 19, 1, 1, 30, 34, 0, // Skip to: 25344
+/* 16610 */   MCD_OPC_CheckField, 4, 1, 0, 23, 34, 0, // Skip to: 25344
+/* 16617 */   MCD_OPC_Decode, 235, 11, 184, 1, // Opcode: MVE_VQRSHRUNs16bh
+/* 16622 */   MCD_OPC_FilterValue, 1, 13, 34, 0, // Skip to: 25344
+/* 16627 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16630 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16652
+/* 16635 */   MCD_OPC_CheckPredicate, 22, 0, 34, 0, // Skip to: 25344
+/* 16640 */   MCD_OPC_CheckField, 4, 1, 0, 249, 33, 0, // Skip to: 25344
+/* 16647 */   MCD_OPC_Decode, 142, 12, 185, 1, // Opcode: MVE_VQSHRUNs32bh
+/* 16652 */   MCD_OPC_FilterValue, 15, 239, 33, 0, // Skip to: 25344
+/* 16657 */   MCD_OPC_CheckPredicate, 22, 234, 33, 0, // Skip to: 25344
+/* 16662 */   MCD_OPC_CheckField, 4, 1, 0, 227, 33, 0, // Skip to: 25344
+/* 16669 */   MCD_OPC_Decode, 237, 11, 185, 1, // Opcode: MVE_VQRSHRUNs32bh
+/* 16674 */   MCD_OPC_FilterValue, 1, 217, 33, 0, // Skip to: 25344
+/* 16679 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 16682 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 16748
+/* 16687 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16690 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 16719
+/* 16695 */   MCD_OPC_CheckPredicate, 22, 196, 33, 0, // Skip to: 25344
+/* 16700 */   MCD_OPC_CheckField, 19, 1, 1, 189, 33, 0, // Skip to: 25344
+/* 16707 */   MCD_OPC_CheckField, 4, 1, 0, 182, 33, 0, // Skip to: 25344
+/* 16714 */   MCD_OPC_Decode, 252, 12, 184, 1, // Opcode: MVE_VSHRNi16bh
+/* 16719 */   MCD_OPC_FilterValue, 15, 172, 33, 0, // Skip to: 25344
+/* 16724 */   MCD_OPC_CheckPredicate, 22, 167, 33, 0, // Skip to: 25344
+/* 16729 */   MCD_OPC_CheckField, 19, 1, 1, 160, 33, 0, // Skip to: 25344
+/* 16736 */   MCD_OPC_CheckField, 4, 1, 0, 153, 33, 0, // Skip to: 25344
+/* 16743 */   MCD_OPC_Decode, 208, 12, 184, 1, // Opcode: MVE_VRSHRNi16bh
+/* 16748 */   MCD_OPC_FilterValue, 1, 143, 33, 0, // Skip to: 25344
+/* 16753 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16756 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16778
+/* 16761 */   MCD_OPC_CheckPredicate, 22, 130, 33, 0, // Skip to: 25344
+/* 16766 */   MCD_OPC_CheckField, 4, 1, 0, 123, 33, 0, // Skip to: 25344
+/* 16773 */   MCD_OPC_Decode, 254, 12, 185, 1, // Opcode: MVE_VSHRNi32bh
+/* 16778 */   MCD_OPC_FilterValue, 15, 113, 33, 0, // Skip to: 25344
+/* 16783 */   MCD_OPC_CheckPredicate, 22, 108, 33, 0, // Skip to: 25344
+/* 16788 */   MCD_OPC_CheckField, 4, 1, 0, 101, 33, 0, // Skip to: 25344
+/* 16795 */   MCD_OPC_Decode, 210, 12, 185, 1, // Opcode: MVE_VRSHRNi32bh
+/* 16800 */   MCD_OPC_FilterValue, 1, 91, 33, 0, // Skip to: 25344
+/* 16805 */   MCD_OPC_CheckPredicate, 22, 86, 33, 0, // Skip to: 25344
+/* 16810 */   MCD_OPC_CheckField, 28, 4, 14, 79, 33, 0, // Skip to: 25344
+/* 16817 */   MCD_OPC_CheckField, 4, 2, 0, 72, 33, 0, // Skip to: 25344
+/* 16824 */   MCD_OPC_Decode, 220, 12, 188, 1, // Opcode: MVE_VSHLC
+/* 16829 */   MCD_OPC_FilterValue, 1, 62, 33, 0, // Skip to: 25344
+/* 16834 */   MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 16837 */   MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 16963
+/* 16842 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16845 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 16911
+/* 16850 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16853 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 16882
+/* 16858 */   MCD_OPC_CheckPredicate, 22, 33, 33, 0, // Skip to: 25344
+/* 16863 */   MCD_OPC_CheckField, 19, 1, 1, 26, 33, 0, // Skip to: 25344
+/* 16870 */   MCD_OPC_CheckField, 4, 1, 0, 19, 33, 0, // Skip to: 25344
+/* 16877 */   MCD_OPC_Decode, 141, 12, 184, 1, // Opcode: MVE_VQSHRUNs16th
+/* 16882 */   MCD_OPC_FilterValue, 15, 9, 33, 0, // Skip to: 25344
+/* 16887 */   MCD_OPC_CheckPredicate, 22, 4, 33, 0, // Skip to: 25344
+/* 16892 */   MCD_OPC_CheckField, 19, 1, 1, 253, 32, 0, // Skip to: 25344
+/* 16899 */   MCD_OPC_CheckField, 4, 1, 0, 246, 32, 0, // Skip to: 25344
+/* 16906 */   MCD_OPC_Decode, 236, 11, 184, 1, // Opcode: MVE_VQRSHRUNs16th
+/* 16911 */   MCD_OPC_FilterValue, 1, 236, 32, 0, // Skip to: 25344
+/* 16916 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16919 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 16941
+/* 16924 */   MCD_OPC_CheckPredicate, 22, 223, 32, 0, // Skip to: 25344
+/* 16929 */   MCD_OPC_CheckField, 4, 1, 0, 216, 32, 0, // Skip to: 25344
+/* 16936 */   MCD_OPC_Decode, 143, 12, 185, 1, // Opcode: MVE_VQSHRUNs32th
+/* 16941 */   MCD_OPC_FilterValue, 15, 206, 32, 0, // Skip to: 25344
+/* 16946 */   MCD_OPC_CheckPredicate, 22, 201, 32, 0, // Skip to: 25344
+/* 16951 */   MCD_OPC_CheckField, 4, 1, 0, 194, 32, 0, // Skip to: 25344
+/* 16958 */   MCD_OPC_Decode, 238, 11, 185, 1, // Opcode: MVE_VQRSHRUNs32th
+/* 16963 */   MCD_OPC_FilterValue, 1, 184, 32, 0, // Skip to: 25344
+/* 16968 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16971 */   MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 17037
+/* 16976 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 16979 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 17008
+/* 16984 */   MCD_OPC_CheckPredicate, 22, 163, 32, 0, // Skip to: 25344
+/* 16989 */   MCD_OPC_CheckField, 19, 1, 1, 156, 32, 0, // Skip to: 25344
+/* 16996 */   MCD_OPC_CheckField, 4, 1, 0, 149, 32, 0, // Skip to: 25344
+/* 17003 */   MCD_OPC_Decode, 253, 12, 184, 1, // Opcode: MVE_VSHRNi16th
+/* 17008 */   MCD_OPC_FilterValue, 15, 139, 32, 0, // Skip to: 25344
+/* 17013 */   MCD_OPC_CheckPredicate, 22, 134, 32, 0, // Skip to: 25344
+/* 17018 */   MCD_OPC_CheckField, 19, 1, 1, 127, 32, 0, // Skip to: 25344
+/* 17025 */   MCD_OPC_CheckField, 4, 1, 0, 120, 32, 0, // Skip to: 25344
+/* 17032 */   MCD_OPC_Decode, 209, 12, 184, 1, // Opcode: MVE_VRSHRNi16th
+/* 17037 */   MCD_OPC_FilterValue, 1, 110, 32, 0, // Skip to: 25344
+/* 17042 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17045 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 17067
+/* 17050 */   MCD_OPC_CheckPredicate, 22, 97, 32, 0, // Skip to: 25344
+/* 17055 */   MCD_OPC_CheckField, 4, 1, 0, 90, 32, 0, // Skip to: 25344
+/* 17062 */   MCD_OPC_Decode, 255, 12, 185, 1, // Opcode: MVE_VSHRNi32th
+/* 17067 */   MCD_OPC_FilterValue, 15, 80, 32, 0, // Skip to: 25344
+/* 17072 */   MCD_OPC_CheckPredicate, 22, 75, 32, 0, // Skip to: 25344
+/* 17077 */   MCD_OPC_CheckField, 4, 1, 0, 68, 32, 0, // Skip to: 25344
+/* 17084 */   MCD_OPC_Decode, 211, 12, 185, 1, // Opcode: MVE_VRSHRNi32th
+/* 17089 */   MCD_OPC_FilterValue, 2, 15, 19, 0, // Skip to: 21973
+/* 17094 */   MCD_OPC_ExtractField, 8, 5,  // Inst{12-8} ...
+/* 17097 */   MCD_OPC_FilterValue, 0, 251, 1, 0, // Skip to: 17609
+/* 17102 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 17105 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 17273
+/* 17110 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17113 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 17193
+/* 17118 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17121 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17157
+/* 17126 */   MCD_OPC_CheckPredicate, 22, 21, 32, 0, // Skip to: 25344
+/* 17131 */   MCD_OPC_CheckField, 16, 1, 0, 14, 32, 0, // Skip to: 25344
+/* 17138 */   MCD_OPC_CheckField, 6, 1, 1, 7, 32, 0, // Skip to: 25344
+/* 17145 */   MCD_OPC_CheckField, 0, 1, 0, 0, 32, 0, // Skip to: 25344
+/* 17152 */   MCD_OPC_Decode, 202, 8, 143, 1, // Opcode: MVE_VHADDs8
+/* 17157 */   MCD_OPC_FilterValue, 15, 246, 31, 0, // Skip to: 25344
+/* 17162 */   MCD_OPC_CheckPredicate, 22, 241, 31, 0, // Skip to: 25344
+/* 17167 */   MCD_OPC_CheckField, 16, 1, 0, 234, 31, 0, // Skip to: 25344
+/* 17174 */   MCD_OPC_CheckField, 6, 1, 1, 227, 31, 0, // Skip to: 25344
+/* 17181 */   MCD_OPC_CheckField, 0, 1, 0, 220, 31, 0, // Skip to: 25344
+/* 17188 */   MCD_OPC_Decode, 205, 8, 143, 1, // Opcode: MVE_VHADDu8
+/* 17193 */   MCD_OPC_FilterValue, 1, 210, 31, 0, // Skip to: 25344
+/* 17198 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17201 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17237
+/* 17206 */   MCD_OPC_CheckPredicate, 22, 197, 31, 0, // Skip to: 25344
+/* 17211 */   MCD_OPC_CheckField, 16, 1, 0, 190, 31, 0, // Skip to: 25344
+/* 17218 */   MCD_OPC_CheckField, 6, 1, 1, 183, 31, 0, // Skip to: 25344
+/* 17225 */   MCD_OPC_CheckField, 0, 1, 0, 176, 31, 0, // Skip to: 25344
+/* 17232 */   MCD_OPC_Decode, 140, 11, 143, 1, // Opcode: MVE_VQADDs8
+/* 17237 */   MCD_OPC_FilterValue, 15, 166, 31, 0, // Skip to: 25344
+/* 17242 */   MCD_OPC_CheckPredicate, 22, 161, 31, 0, // Skip to: 25344
+/* 17247 */   MCD_OPC_CheckField, 16, 1, 0, 154, 31, 0, // Skip to: 25344
+/* 17254 */   MCD_OPC_CheckField, 6, 1, 1, 147, 31, 0, // Skip to: 25344
+/* 17261 */   MCD_OPC_CheckField, 0, 1, 0, 140, 31, 0, // Skip to: 25344
+/* 17268 */   MCD_OPC_Decode, 143, 11, 143, 1, // Opcode: MVE_VQADDu8
+/* 17273 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 17441
+/* 17278 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17281 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 17361
+/* 17286 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17289 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17325
+/* 17294 */   MCD_OPC_CheckPredicate, 22, 109, 31, 0, // Skip to: 25344
+/* 17299 */   MCD_OPC_CheckField, 16, 1, 0, 102, 31, 0, // Skip to: 25344
+/* 17306 */   MCD_OPC_CheckField, 6, 1, 1, 95, 31, 0, // Skip to: 25344
+/* 17313 */   MCD_OPC_CheckField, 0, 1, 0, 88, 31, 0, // Skip to: 25344
+/* 17320 */   MCD_OPC_Decode, 200, 8, 143, 1, // Opcode: MVE_VHADDs16
+/* 17325 */   MCD_OPC_FilterValue, 15, 78, 31, 0, // Skip to: 25344
+/* 17330 */   MCD_OPC_CheckPredicate, 22, 73, 31, 0, // Skip to: 25344
+/* 17335 */   MCD_OPC_CheckField, 16, 1, 0, 66, 31, 0, // Skip to: 25344
+/* 17342 */   MCD_OPC_CheckField, 6, 1, 1, 59, 31, 0, // Skip to: 25344
+/* 17349 */   MCD_OPC_CheckField, 0, 1, 0, 52, 31, 0, // Skip to: 25344
+/* 17356 */   MCD_OPC_Decode, 203, 8, 143, 1, // Opcode: MVE_VHADDu16
+/* 17361 */   MCD_OPC_FilterValue, 1, 42, 31, 0, // Skip to: 25344
+/* 17366 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17369 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17405
+/* 17374 */   MCD_OPC_CheckPredicate, 22, 29, 31, 0, // Skip to: 25344
+/* 17379 */   MCD_OPC_CheckField, 16, 1, 0, 22, 31, 0, // Skip to: 25344
+/* 17386 */   MCD_OPC_CheckField, 6, 1, 1, 15, 31, 0, // Skip to: 25344
+/* 17393 */   MCD_OPC_CheckField, 0, 1, 0, 8, 31, 0, // Skip to: 25344
+/* 17400 */   MCD_OPC_Decode, 138, 11, 143, 1, // Opcode: MVE_VQADDs16
+/* 17405 */   MCD_OPC_FilterValue, 15, 254, 30, 0, // Skip to: 25344
+/* 17410 */   MCD_OPC_CheckPredicate, 22, 249, 30, 0, // Skip to: 25344
+/* 17415 */   MCD_OPC_CheckField, 16, 1, 0, 242, 30, 0, // Skip to: 25344
+/* 17422 */   MCD_OPC_CheckField, 6, 1, 1, 235, 30, 0, // Skip to: 25344
+/* 17429 */   MCD_OPC_CheckField, 0, 1, 0, 228, 30, 0, // Skip to: 25344
+/* 17436 */   MCD_OPC_Decode, 141, 11, 143, 1, // Opcode: MVE_VQADDu16
+/* 17441 */   MCD_OPC_FilterValue, 2, 218, 30, 0, // Skip to: 25344
+/* 17446 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17449 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 17529
+/* 17454 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17457 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17493
+/* 17462 */   MCD_OPC_CheckPredicate, 22, 197, 30, 0, // Skip to: 25344
+/* 17467 */   MCD_OPC_CheckField, 16, 1, 0, 190, 30, 0, // Skip to: 25344
+/* 17474 */   MCD_OPC_CheckField, 6, 1, 1, 183, 30, 0, // Skip to: 25344
+/* 17481 */   MCD_OPC_CheckField, 0, 1, 0, 176, 30, 0, // Skip to: 25344
+/* 17488 */   MCD_OPC_Decode, 201, 8, 143, 1, // Opcode: MVE_VHADDs32
+/* 17493 */   MCD_OPC_FilterValue, 15, 166, 30, 0, // Skip to: 25344
+/* 17498 */   MCD_OPC_CheckPredicate, 22, 161, 30, 0, // Skip to: 25344
+/* 17503 */   MCD_OPC_CheckField, 16, 1, 0, 154, 30, 0, // Skip to: 25344
+/* 17510 */   MCD_OPC_CheckField, 6, 1, 1, 147, 30, 0, // Skip to: 25344
+/* 17517 */   MCD_OPC_CheckField, 0, 1, 0, 140, 30, 0, // Skip to: 25344
+/* 17524 */   MCD_OPC_Decode, 204, 8, 143, 1, // Opcode: MVE_VHADDu32
+/* 17529 */   MCD_OPC_FilterValue, 1, 130, 30, 0, // Skip to: 25344
+/* 17534 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17537 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17573
+/* 17542 */   MCD_OPC_CheckPredicate, 22, 117, 30, 0, // Skip to: 25344
+/* 17547 */   MCD_OPC_CheckField, 16, 1, 0, 110, 30, 0, // Skip to: 25344
+/* 17554 */   MCD_OPC_CheckField, 6, 1, 1, 103, 30, 0, // Skip to: 25344
+/* 17561 */   MCD_OPC_CheckField, 0, 1, 0, 96, 30, 0, // Skip to: 25344
+/* 17568 */   MCD_OPC_Decode, 139, 11, 143, 1, // Opcode: MVE_VQADDs32
+/* 17573 */   MCD_OPC_FilterValue, 15, 86, 30, 0, // Skip to: 25344
+/* 17578 */   MCD_OPC_CheckPredicate, 22, 81, 30, 0, // Skip to: 25344
+/* 17583 */   MCD_OPC_CheckField, 16, 1, 0, 74, 30, 0, // Skip to: 25344
+/* 17590 */   MCD_OPC_CheckField, 6, 1, 1, 67, 30, 0, // Skip to: 25344
+/* 17597 */   MCD_OPC_CheckField, 0, 1, 0, 60, 30, 0, // Skip to: 25344
+/* 17604 */   MCD_OPC_Decode, 142, 11, 143, 1, // Opcode: MVE_VQADDu32
+/* 17609 */   MCD_OPC_FilterValue, 1, 227, 1, 0, // Skip to: 18097
+/* 17614 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 17617 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 17785
+/* 17622 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17625 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 17705
+/* 17630 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17633 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17669
+/* 17638 */   MCD_OPC_CheckPredicate, 22, 21, 30, 0, // Skip to: 25344
+/* 17643 */   MCD_OPC_CheckField, 16, 1, 0, 14, 30, 0, // Skip to: 25344
+/* 17650 */   MCD_OPC_CheckField, 6, 1, 1, 7, 30, 0, // Skip to: 25344
+/* 17657 */   MCD_OPC_CheckField, 0, 1, 0, 0, 30, 0, // Skip to: 25344
+/* 17664 */   MCD_OPC_Decode, 164, 12, 143, 1, // Opcode: MVE_VRHADDs8
+/* 17669 */   MCD_OPC_FilterValue, 15, 246, 29, 0, // Skip to: 25344
+/* 17674 */   MCD_OPC_CheckPredicate, 22, 241, 29, 0, // Skip to: 25344
+/* 17679 */   MCD_OPC_CheckField, 16, 1, 0, 234, 29, 0, // Skip to: 25344
+/* 17686 */   MCD_OPC_CheckField, 6, 1, 1, 227, 29, 0, // Skip to: 25344
+/* 17693 */   MCD_OPC_CheckField, 0, 1, 0, 220, 29, 0, // Skip to: 25344
+/* 17700 */   MCD_OPC_Decode, 167, 12, 143, 1, // Opcode: MVE_VRHADDu8
+/* 17705 */   MCD_OPC_FilterValue, 1, 210, 29, 0, // Skip to: 25344
+/* 17710 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17713 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17749
+/* 17718 */   MCD_OPC_CheckPredicate, 22, 197, 29, 0, // Skip to: 25344
+/* 17723 */   MCD_OPC_CheckField, 16, 1, 0, 190, 29, 0, // Skip to: 25344
+/* 17730 */   MCD_OPC_CheckField, 6, 1, 1, 183, 29, 0, // Skip to: 25344
+/* 17737 */   MCD_OPC_CheckField, 0, 1, 0, 176, 29, 0, // Skip to: 25344
+/* 17744 */   MCD_OPC_Decode, 220, 7, 143, 1, // Opcode: MVE_VAND
+/* 17749 */   MCD_OPC_FilterValue, 15, 166, 29, 0, // Skip to: 25344
+/* 17754 */   MCD_OPC_CheckPredicate, 22, 161, 29, 0, // Skip to: 25344
+/* 17759 */   MCD_OPC_CheckField, 16, 1, 0, 154, 29, 0, // Skip to: 25344
+/* 17766 */   MCD_OPC_CheckField, 6, 1, 1, 147, 29, 0, // Skip to: 25344
+/* 17773 */   MCD_OPC_CheckField, 0, 1, 0, 140, 29, 0, // Skip to: 25344
+/* 17780 */   MCD_OPC_Decode, 185, 8, 143, 1, // Opcode: MVE_VEOR
+/* 17785 */   MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 17916
+/* 17790 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17793 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 17873
+/* 17798 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17801 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17837
+/* 17806 */   MCD_OPC_CheckPredicate, 22, 109, 29, 0, // Skip to: 25344
+/* 17811 */   MCD_OPC_CheckField, 16, 1, 0, 102, 29, 0, // Skip to: 25344
+/* 17818 */   MCD_OPC_CheckField, 6, 1, 1, 95, 29, 0, // Skip to: 25344
+/* 17825 */   MCD_OPC_CheckField, 0, 1, 0, 88, 29, 0, // Skip to: 25344
+/* 17832 */   MCD_OPC_Decode, 162, 12, 143, 1, // Opcode: MVE_VRHADDs16
+/* 17837 */   MCD_OPC_FilterValue, 15, 78, 29, 0, // Skip to: 25344
+/* 17842 */   MCD_OPC_CheckPredicate, 22, 73, 29, 0, // Skip to: 25344
+/* 17847 */   MCD_OPC_CheckField, 16, 1, 0, 66, 29, 0, // Skip to: 25344
+/* 17854 */   MCD_OPC_CheckField, 6, 1, 1, 59, 29, 0, // Skip to: 25344
+/* 17861 */   MCD_OPC_CheckField, 0, 1, 0, 52, 29, 0, // Skip to: 25344
+/* 17868 */   MCD_OPC_Decode, 165, 12, 143, 1, // Opcode: MVE_VRHADDu16
+/* 17873 */   MCD_OPC_FilterValue, 1, 42, 29, 0, // Skip to: 25344
+/* 17878 */   MCD_OPC_CheckPredicate, 22, 37, 29, 0, // Skip to: 25344
+/* 17883 */   MCD_OPC_CheckField, 28, 4, 14, 30, 29, 0, // Skip to: 25344
+/* 17890 */   MCD_OPC_CheckField, 16, 1, 0, 23, 29, 0, // Skip to: 25344
+/* 17897 */   MCD_OPC_CheckField, 6, 1, 1, 16, 29, 0, // Skip to: 25344
+/* 17904 */   MCD_OPC_CheckField, 0, 1, 0, 9, 29, 0, // Skip to: 25344
+/* 17911 */   MCD_OPC_Decode, 221, 7, 143, 1, // Opcode: MVE_VBIC
+/* 17916 */   MCD_OPC_FilterValue, 2, 126, 0, 0, // Skip to: 18047
+/* 17921 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 17924 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 18004
+/* 17929 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 17932 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 17968
+/* 17937 */   MCD_OPC_CheckPredicate, 22, 234, 28, 0, // Skip to: 25344
+/* 17942 */   MCD_OPC_CheckField, 16, 1, 0, 227, 28, 0, // Skip to: 25344
+/* 17949 */   MCD_OPC_CheckField, 6, 1, 1, 220, 28, 0, // Skip to: 25344
+/* 17956 */   MCD_OPC_CheckField, 0, 1, 0, 213, 28, 0, // Skip to: 25344
+/* 17963 */   MCD_OPC_Decode, 163, 12, 143, 1, // Opcode: MVE_VRHADDs32
+/* 17968 */   MCD_OPC_FilterValue, 15, 203, 28, 0, // Skip to: 25344
+/* 17973 */   MCD_OPC_CheckPredicate, 22, 198, 28, 0, // Skip to: 25344
+/* 17978 */   MCD_OPC_CheckField, 16, 1, 0, 191, 28, 0, // Skip to: 25344
+/* 17985 */   MCD_OPC_CheckField, 6, 1, 1, 184, 28, 0, // Skip to: 25344
+/* 17992 */   MCD_OPC_CheckField, 0, 1, 0, 177, 28, 0, // Skip to: 25344
+/* 17999 */   MCD_OPC_Decode, 166, 12, 143, 1, // Opcode: MVE_VRHADDu32
+/* 18004 */   MCD_OPC_FilterValue, 1, 167, 28, 0, // Skip to: 25344
+/* 18009 */   MCD_OPC_CheckPredicate, 22, 162, 28, 0, // Skip to: 25344
+/* 18014 */   MCD_OPC_CheckField, 28, 4, 14, 155, 28, 0, // Skip to: 25344
+/* 18021 */   MCD_OPC_CheckField, 16, 1, 0, 148, 28, 0, // Skip to: 25344
+/* 18028 */   MCD_OPC_CheckField, 6, 1, 1, 141, 28, 0, // Skip to: 25344
+/* 18035 */   MCD_OPC_CheckField, 0, 1, 0, 134, 28, 0, // Skip to: 25344
+/* 18042 */   MCD_OPC_Decode, 229, 10, 143, 1, // Opcode: MVE_VORR
+/* 18047 */   MCD_OPC_FilterValue, 3, 124, 28, 0, // Skip to: 25344
+/* 18052 */   MCD_OPC_CheckPredicate, 22, 119, 28, 0, // Skip to: 25344
+/* 18057 */   MCD_OPC_CheckField, 28, 4, 14, 112, 28, 0, // Skip to: 25344
+/* 18064 */   MCD_OPC_CheckField, 16, 1, 0, 105, 28, 0, // Skip to: 25344
+/* 18071 */   MCD_OPC_CheckField, 6, 1, 1, 98, 28, 0, // Skip to: 25344
+/* 18078 */   MCD_OPC_CheckField, 4, 1, 1, 91, 28, 0, // Skip to: 25344
+/* 18085 */   MCD_OPC_CheckField, 0, 1, 0, 84, 28, 0, // Skip to: 25344
+/* 18092 */   MCD_OPC_Decode, 228, 10, 143, 1, // Opcode: MVE_VORN
+/* 18097 */   MCD_OPC_FilterValue, 2, 251, 1, 0, // Skip to: 18609
+/* 18102 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 18105 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 18273
+/* 18110 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 18113 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 18193
+/* 18118 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18121 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18157
+/* 18126 */   MCD_OPC_CheckPredicate, 22, 45, 28, 0, // Skip to: 25344
+/* 18131 */   MCD_OPC_CheckField, 16, 1, 0, 38, 28, 0, // Skip to: 25344
+/* 18138 */   MCD_OPC_CheckField, 6, 1, 1, 31, 28, 0, // Skip to: 25344
+/* 18145 */   MCD_OPC_CheckField, 0, 1, 0, 24, 28, 0, // Skip to: 25344
+/* 18152 */   MCD_OPC_Decode, 217, 8, 143, 1, // Opcode: MVE_VHSUBs8
+/* 18157 */   MCD_OPC_FilterValue, 15, 14, 28, 0, // Skip to: 25344
+/* 18162 */   MCD_OPC_CheckPredicate, 22, 9, 28, 0, // Skip to: 25344
+/* 18167 */   MCD_OPC_CheckField, 16, 1, 0, 2, 28, 0, // Skip to: 25344
+/* 18174 */   MCD_OPC_CheckField, 6, 1, 1, 251, 27, 0, // Skip to: 25344
+/* 18181 */   MCD_OPC_CheckField, 0, 1, 0, 244, 27, 0, // Skip to: 25344
+/* 18188 */   MCD_OPC_Decode, 220, 8, 143, 1, // Opcode: MVE_VHSUBu8
+/* 18193 */   MCD_OPC_FilterValue, 1, 234, 27, 0, // Skip to: 25344
+/* 18198 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18201 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18237
+/* 18206 */   MCD_OPC_CheckPredicate, 22, 221, 27, 0, // Skip to: 25344
+/* 18211 */   MCD_OPC_CheckField, 16, 1, 0, 214, 27, 0, // Skip to: 25344
+/* 18218 */   MCD_OPC_CheckField, 6, 1, 1, 207, 27, 0, // Skip to: 25344
+/* 18225 */   MCD_OPC_CheckField, 0, 1, 0, 200, 27, 0, // Skip to: 25344
+/* 18232 */   MCD_OPC_Decode, 152, 12, 143, 1, // Opcode: MVE_VQSUBs8
+/* 18237 */   MCD_OPC_FilterValue, 15, 190, 27, 0, // Skip to: 25344
+/* 18242 */   MCD_OPC_CheckPredicate, 22, 185, 27, 0, // Skip to: 25344
+/* 18247 */   MCD_OPC_CheckField, 16, 1, 0, 178, 27, 0, // Skip to: 25344
+/* 18254 */   MCD_OPC_CheckField, 6, 1, 1, 171, 27, 0, // Skip to: 25344
+/* 18261 */   MCD_OPC_CheckField, 0, 1, 0, 164, 27, 0, // Skip to: 25344
+/* 18268 */   MCD_OPC_Decode, 155, 12, 143, 1, // Opcode: MVE_VQSUBu8
+/* 18273 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 18441
+/* 18278 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 18281 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 18361
+/* 18286 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18289 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18325
+/* 18294 */   MCD_OPC_CheckPredicate, 22, 133, 27, 0, // Skip to: 25344
+/* 18299 */   MCD_OPC_CheckField, 16, 1, 0, 126, 27, 0, // Skip to: 25344
+/* 18306 */   MCD_OPC_CheckField, 6, 1, 1, 119, 27, 0, // Skip to: 25344
+/* 18313 */   MCD_OPC_CheckField, 0, 1, 0, 112, 27, 0, // Skip to: 25344
+/* 18320 */   MCD_OPC_Decode, 215, 8, 143, 1, // Opcode: MVE_VHSUBs16
+/* 18325 */   MCD_OPC_FilterValue, 15, 102, 27, 0, // Skip to: 25344
+/* 18330 */   MCD_OPC_CheckPredicate, 22, 97, 27, 0, // Skip to: 25344
+/* 18335 */   MCD_OPC_CheckField, 16, 1, 0, 90, 27, 0, // Skip to: 25344
+/* 18342 */   MCD_OPC_CheckField, 6, 1, 1, 83, 27, 0, // Skip to: 25344
+/* 18349 */   MCD_OPC_CheckField, 0, 1, 0, 76, 27, 0, // Skip to: 25344
+/* 18356 */   MCD_OPC_Decode, 218, 8, 143, 1, // Opcode: MVE_VHSUBu16
+/* 18361 */   MCD_OPC_FilterValue, 1, 66, 27, 0, // Skip to: 25344
+/* 18366 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18369 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18405
+/* 18374 */   MCD_OPC_CheckPredicate, 22, 53, 27, 0, // Skip to: 25344
+/* 18379 */   MCD_OPC_CheckField, 16, 1, 0, 46, 27, 0, // Skip to: 25344
+/* 18386 */   MCD_OPC_CheckField, 6, 1, 1, 39, 27, 0, // Skip to: 25344
+/* 18393 */   MCD_OPC_CheckField, 0, 1, 0, 32, 27, 0, // Skip to: 25344
+/* 18400 */   MCD_OPC_Decode, 150, 12, 143, 1, // Opcode: MVE_VQSUBs16
+/* 18405 */   MCD_OPC_FilterValue, 15, 22, 27, 0, // Skip to: 25344
+/* 18410 */   MCD_OPC_CheckPredicate, 22, 17, 27, 0, // Skip to: 25344
+/* 18415 */   MCD_OPC_CheckField, 16, 1, 0, 10, 27, 0, // Skip to: 25344
+/* 18422 */   MCD_OPC_CheckField, 6, 1, 1, 3, 27, 0, // Skip to: 25344
+/* 18429 */   MCD_OPC_CheckField, 0, 1, 0, 252, 26, 0, // Skip to: 25344
+/* 18436 */   MCD_OPC_Decode, 153, 12, 143, 1, // Opcode: MVE_VQSUBu16
+/* 18441 */   MCD_OPC_FilterValue, 2, 242, 26, 0, // Skip to: 25344
+/* 18446 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 18449 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 18529
+/* 18454 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18457 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18493
+/* 18462 */   MCD_OPC_CheckPredicate, 22, 221, 26, 0, // Skip to: 25344
+/* 18467 */   MCD_OPC_CheckField, 16, 1, 0, 214, 26, 0, // Skip to: 25344
+/* 18474 */   MCD_OPC_CheckField, 6, 1, 1, 207, 26, 0, // Skip to: 25344
+/* 18481 */   MCD_OPC_CheckField, 0, 1, 0, 200, 26, 0, // Skip to: 25344
+/* 18488 */   MCD_OPC_Decode, 216, 8, 143, 1, // Opcode: MVE_VHSUBs32
+/* 18493 */   MCD_OPC_FilterValue, 15, 190, 26, 0, // Skip to: 25344
+/* 18498 */   MCD_OPC_CheckPredicate, 22, 185, 26, 0, // Skip to: 25344
+/* 18503 */   MCD_OPC_CheckField, 16, 1, 0, 178, 26, 0, // Skip to: 25344
+/* 18510 */   MCD_OPC_CheckField, 6, 1, 1, 171, 26, 0, // Skip to: 25344
+/* 18517 */   MCD_OPC_CheckField, 0, 1, 0, 164, 26, 0, // Skip to: 25344
+/* 18524 */   MCD_OPC_Decode, 219, 8, 143, 1, // Opcode: MVE_VHSUBu32
+/* 18529 */   MCD_OPC_FilterValue, 1, 154, 26, 0, // Skip to: 25344
+/* 18534 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18537 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18573
+/* 18542 */   MCD_OPC_CheckPredicate, 22, 141, 26, 0, // Skip to: 25344
+/* 18547 */   MCD_OPC_CheckField, 16, 1, 0, 134, 26, 0, // Skip to: 25344
+/* 18554 */   MCD_OPC_CheckField, 6, 1, 1, 127, 26, 0, // Skip to: 25344
+/* 18561 */   MCD_OPC_CheckField, 0, 1, 0, 120, 26, 0, // Skip to: 25344
+/* 18568 */   MCD_OPC_Decode, 151, 12, 143, 1, // Opcode: MVE_VQSUBs32
+/* 18573 */   MCD_OPC_FilterValue, 15, 110, 26, 0, // Skip to: 25344
+/* 18578 */   MCD_OPC_CheckPredicate, 22, 105, 26, 0, // Skip to: 25344
+/* 18583 */   MCD_OPC_CheckField, 16, 1, 0, 98, 26, 0, // Skip to: 25344
+/* 18590 */   MCD_OPC_CheckField, 6, 1, 1, 91, 26, 0, // Skip to: 25344
+/* 18597 */   MCD_OPC_CheckField, 0, 1, 0, 84, 26, 0, // Skip to: 25344
+/* 18604 */   MCD_OPC_Decode, 154, 12, 143, 1, // Opcode: MVE_VQSUBu32
+/* 18609 */   MCD_OPC_FilterValue, 4, 251, 1, 0, // Skip to: 19121
+/* 18614 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 18617 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 18785
+/* 18622 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 18625 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 18705
+/* 18630 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18633 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18669
+/* 18638 */   MCD_OPC_CheckPredicate, 22, 45, 26, 0, // Skip to: 25344
+/* 18643 */   MCD_OPC_CheckField, 16, 1, 0, 38, 26, 0, // Skip to: 25344
+/* 18650 */   MCD_OPC_CheckField, 6, 1, 1, 31, 26, 0, // Skip to: 25344
+/* 18657 */   MCD_OPC_CheckField, 0, 1, 0, 24, 26, 0, // Skip to: 25344
+/* 18664 */   MCD_OPC_Decode, 239, 12, 189, 1, // Opcode: MVE_VSHL_by_vecs8
+/* 18669 */   MCD_OPC_FilterValue, 15, 14, 26, 0, // Skip to: 25344
+/* 18674 */   MCD_OPC_CheckPredicate, 22, 9, 26, 0, // Skip to: 25344
+/* 18679 */   MCD_OPC_CheckField, 16, 1, 0, 2, 26, 0, // Skip to: 25344
+/* 18686 */   MCD_OPC_CheckField, 6, 1, 1, 251, 25, 0, // Skip to: 25344
+/* 18693 */   MCD_OPC_CheckField, 0, 1, 0, 244, 25, 0, // Skip to: 25344
+/* 18700 */   MCD_OPC_Decode, 242, 12, 189, 1, // Opcode: MVE_VSHL_by_vecu8
+/* 18705 */   MCD_OPC_FilterValue, 1, 234, 25, 0, // Skip to: 25344
+/* 18710 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18713 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18749
+/* 18718 */   MCD_OPC_CheckPredicate, 22, 221, 25, 0, // Skip to: 25344
+/* 18723 */   MCD_OPC_CheckField, 16, 1, 0, 214, 25, 0, // Skip to: 25344
+/* 18730 */   MCD_OPC_CheckField, 6, 1, 1, 207, 25, 0, // Skip to: 25344
+/* 18737 */   MCD_OPC_CheckField, 0, 1, 0, 200, 25, 0, // Skip to: 25344
+/* 18744 */   MCD_OPC_Decode, 244, 11, 189, 1, // Opcode: MVE_VQSHL_by_vecs8
+/* 18749 */   MCD_OPC_FilterValue, 15, 190, 25, 0, // Skip to: 25344
+/* 18754 */   MCD_OPC_CheckPredicate, 22, 185, 25, 0, // Skip to: 25344
+/* 18759 */   MCD_OPC_CheckField, 16, 1, 0, 178, 25, 0, // Skip to: 25344
+/* 18766 */   MCD_OPC_CheckField, 6, 1, 1, 171, 25, 0, // Skip to: 25344
+/* 18773 */   MCD_OPC_CheckField, 0, 1, 0, 164, 25, 0, // Skip to: 25344
+/* 18780 */   MCD_OPC_Decode, 247, 11, 189, 1, // Opcode: MVE_VQSHL_by_vecu8
+/* 18785 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 18953
+/* 18790 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 18793 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 18873
+/* 18798 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18801 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18837
+/* 18806 */   MCD_OPC_CheckPredicate, 22, 133, 25, 0, // Skip to: 25344
+/* 18811 */   MCD_OPC_CheckField, 16, 1, 0, 126, 25, 0, // Skip to: 25344
+/* 18818 */   MCD_OPC_CheckField, 6, 1, 1, 119, 25, 0, // Skip to: 25344
+/* 18825 */   MCD_OPC_CheckField, 0, 1, 0, 112, 25, 0, // Skip to: 25344
+/* 18832 */   MCD_OPC_Decode, 237, 12, 189, 1, // Opcode: MVE_VSHL_by_vecs16
+/* 18837 */   MCD_OPC_FilterValue, 15, 102, 25, 0, // Skip to: 25344
+/* 18842 */   MCD_OPC_CheckPredicate, 22, 97, 25, 0, // Skip to: 25344
+/* 18847 */   MCD_OPC_CheckField, 16, 1, 0, 90, 25, 0, // Skip to: 25344
+/* 18854 */   MCD_OPC_CheckField, 6, 1, 1, 83, 25, 0, // Skip to: 25344
+/* 18861 */   MCD_OPC_CheckField, 0, 1, 0, 76, 25, 0, // Skip to: 25344
+/* 18868 */   MCD_OPC_Decode, 240, 12, 189, 1, // Opcode: MVE_VSHL_by_vecu16
+/* 18873 */   MCD_OPC_FilterValue, 1, 66, 25, 0, // Skip to: 25344
+/* 18878 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18881 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 18917
+/* 18886 */   MCD_OPC_CheckPredicate, 22, 53, 25, 0, // Skip to: 25344
+/* 18891 */   MCD_OPC_CheckField, 16, 1, 0, 46, 25, 0, // Skip to: 25344
+/* 18898 */   MCD_OPC_CheckField, 6, 1, 1, 39, 25, 0, // Skip to: 25344
+/* 18905 */   MCD_OPC_CheckField, 0, 1, 0, 32, 25, 0, // Skip to: 25344
+/* 18912 */   MCD_OPC_Decode, 242, 11, 189, 1, // Opcode: MVE_VQSHL_by_vecs16
+/* 18917 */   MCD_OPC_FilterValue, 15, 22, 25, 0, // Skip to: 25344
+/* 18922 */   MCD_OPC_CheckPredicate, 22, 17, 25, 0, // Skip to: 25344
+/* 18927 */   MCD_OPC_CheckField, 16, 1, 0, 10, 25, 0, // Skip to: 25344
+/* 18934 */   MCD_OPC_CheckField, 6, 1, 1, 3, 25, 0, // Skip to: 25344
+/* 18941 */   MCD_OPC_CheckField, 0, 1, 0, 252, 24, 0, // Skip to: 25344
+/* 18948 */   MCD_OPC_Decode, 245, 11, 189, 1, // Opcode: MVE_VQSHL_by_vecu16
+/* 18953 */   MCD_OPC_FilterValue, 2, 242, 24, 0, // Skip to: 25344
+/* 18958 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 18961 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 19041
+/* 18966 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 18969 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19005
+/* 18974 */   MCD_OPC_CheckPredicate, 22, 221, 24, 0, // Skip to: 25344
+/* 18979 */   MCD_OPC_CheckField, 16, 1, 0, 214, 24, 0, // Skip to: 25344
+/* 18986 */   MCD_OPC_CheckField, 6, 1, 1, 207, 24, 0, // Skip to: 25344
+/* 18993 */   MCD_OPC_CheckField, 0, 1, 0, 200, 24, 0, // Skip to: 25344
+/* 19000 */   MCD_OPC_Decode, 238, 12, 189, 1, // Opcode: MVE_VSHL_by_vecs32
+/* 19005 */   MCD_OPC_FilterValue, 15, 190, 24, 0, // Skip to: 25344
+/* 19010 */   MCD_OPC_CheckPredicate, 22, 185, 24, 0, // Skip to: 25344
+/* 19015 */   MCD_OPC_CheckField, 16, 1, 0, 178, 24, 0, // Skip to: 25344
+/* 19022 */   MCD_OPC_CheckField, 6, 1, 1, 171, 24, 0, // Skip to: 25344
+/* 19029 */   MCD_OPC_CheckField, 0, 1, 0, 164, 24, 0, // Skip to: 25344
+/* 19036 */   MCD_OPC_Decode, 241, 12, 189, 1, // Opcode: MVE_VSHL_by_vecu32
+/* 19041 */   MCD_OPC_FilterValue, 1, 154, 24, 0, // Skip to: 25344
+/* 19046 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19049 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19085
+/* 19054 */   MCD_OPC_CheckPredicate, 22, 141, 24, 0, // Skip to: 25344
+/* 19059 */   MCD_OPC_CheckField, 16, 1, 0, 134, 24, 0, // Skip to: 25344
+/* 19066 */   MCD_OPC_CheckField, 6, 1, 1, 127, 24, 0, // Skip to: 25344
+/* 19073 */   MCD_OPC_CheckField, 0, 1, 0, 120, 24, 0, // Skip to: 25344
+/* 19080 */   MCD_OPC_Decode, 243, 11, 189, 1, // Opcode: MVE_VQSHL_by_vecs32
+/* 19085 */   MCD_OPC_FilterValue, 15, 110, 24, 0, // Skip to: 25344
+/* 19090 */   MCD_OPC_CheckPredicate, 22, 105, 24, 0, // Skip to: 25344
+/* 19095 */   MCD_OPC_CheckField, 16, 1, 0, 98, 24, 0, // Skip to: 25344
+/* 19102 */   MCD_OPC_CheckField, 6, 1, 1, 91, 24, 0, // Skip to: 25344
+/* 19109 */   MCD_OPC_CheckField, 0, 1, 0, 84, 24, 0, // Skip to: 25344
+/* 19116 */   MCD_OPC_Decode, 246, 11, 189, 1, // Opcode: MVE_VQSHL_by_vecu32
+/* 19121 */   MCD_OPC_FilterValue, 5, 251, 1, 0, // Skip to: 19633
+/* 19126 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 19129 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 19297
+/* 19134 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 19137 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 19217
+/* 19142 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19145 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19181
+/* 19150 */   MCD_OPC_CheckPredicate, 22, 45, 24, 0, // Skip to: 25344
+/* 19155 */   MCD_OPC_CheckField, 16, 1, 0, 38, 24, 0, // Skip to: 25344
+/* 19162 */   MCD_OPC_CheckField, 6, 1, 1, 31, 24, 0, // Skip to: 25344
+/* 19169 */   MCD_OPC_CheckField, 0, 1, 0, 24, 24, 0, // Skip to: 25344
+/* 19176 */   MCD_OPC_Decode, 198, 12, 189, 1, // Opcode: MVE_VRSHL_by_vecs8
+/* 19181 */   MCD_OPC_FilterValue, 15, 14, 24, 0, // Skip to: 25344
+/* 19186 */   MCD_OPC_CheckPredicate, 22, 9, 24, 0, // Skip to: 25344
+/* 19191 */   MCD_OPC_CheckField, 16, 1, 0, 2, 24, 0, // Skip to: 25344
+/* 19198 */   MCD_OPC_CheckField, 6, 1, 1, 251, 23, 0, // Skip to: 25344
+/* 19205 */   MCD_OPC_CheckField, 0, 1, 0, 244, 23, 0, // Skip to: 25344
+/* 19212 */   MCD_OPC_Decode, 201, 12, 189, 1, // Opcode: MVE_VRSHL_by_vecu8
+/* 19217 */   MCD_OPC_FilterValue, 1, 234, 23, 0, // Skip to: 25344
+/* 19222 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19225 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19261
+/* 19230 */   MCD_OPC_CheckPredicate, 22, 221, 23, 0, // Skip to: 25344
+/* 19235 */   MCD_OPC_CheckField, 16, 1, 0, 214, 23, 0, // Skip to: 25344
+/* 19242 */   MCD_OPC_CheckField, 6, 1, 1, 207, 23, 0, // Skip to: 25344
+/* 19249 */   MCD_OPC_CheckField, 0, 1, 0, 200, 23, 0, // Skip to: 25344
+/* 19256 */   MCD_OPC_Decode, 217, 11, 189, 1, // Opcode: MVE_VQRSHL_by_vecs8
+/* 19261 */   MCD_OPC_FilterValue, 15, 190, 23, 0, // Skip to: 25344
+/* 19266 */   MCD_OPC_CheckPredicate, 22, 185, 23, 0, // Skip to: 25344
+/* 19271 */   MCD_OPC_CheckField, 16, 1, 0, 178, 23, 0, // Skip to: 25344
+/* 19278 */   MCD_OPC_CheckField, 6, 1, 1, 171, 23, 0, // Skip to: 25344
+/* 19285 */   MCD_OPC_CheckField, 0, 1, 0, 164, 23, 0, // Skip to: 25344
+/* 19292 */   MCD_OPC_Decode, 220, 11, 189, 1, // Opcode: MVE_VQRSHL_by_vecu8
+/* 19297 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 19465
+/* 19302 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 19305 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 19385
+/* 19310 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19313 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19349
+/* 19318 */   MCD_OPC_CheckPredicate, 22, 133, 23, 0, // Skip to: 25344
+/* 19323 */   MCD_OPC_CheckField, 16, 1, 0, 126, 23, 0, // Skip to: 25344
+/* 19330 */   MCD_OPC_CheckField, 6, 1, 1, 119, 23, 0, // Skip to: 25344
+/* 19337 */   MCD_OPC_CheckField, 0, 1, 0, 112, 23, 0, // Skip to: 25344
+/* 19344 */   MCD_OPC_Decode, 196, 12, 189, 1, // Opcode: MVE_VRSHL_by_vecs16
+/* 19349 */   MCD_OPC_FilterValue, 15, 102, 23, 0, // Skip to: 25344
+/* 19354 */   MCD_OPC_CheckPredicate, 22, 97, 23, 0, // Skip to: 25344
+/* 19359 */   MCD_OPC_CheckField, 16, 1, 0, 90, 23, 0, // Skip to: 25344
+/* 19366 */   MCD_OPC_CheckField, 6, 1, 1, 83, 23, 0, // Skip to: 25344
+/* 19373 */   MCD_OPC_CheckField, 0, 1, 0, 76, 23, 0, // Skip to: 25344
+/* 19380 */   MCD_OPC_Decode, 199, 12, 189, 1, // Opcode: MVE_VRSHL_by_vecu16
+/* 19385 */   MCD_OPC_FilterValue, 1, 66, 23, 0, // Skip to: 25344
+/* 19390 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19393 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19429
+/* 19398 */   MCD_OPC_CheckPredicate, 22, 53, 23, 0, // Skip to: 25344
+/* 19403 */   MCD_OPC_CheckField, 16, 1, 0, 46, 23, 0, // Skip to: 25344
+/* 19410 */   MCD_OPC_CheckField, 6, 1, 1, 39, 23, 0, // Skip to: 25344
+/* 19417 */   MCD_OPC_CheckField, 0, 1, 0, 32, 23, 0, // Skip to: 25344
+/* 19424 */   MCD_OPC_Decode, 215, 11, 189, 1, // Opcode: MVE_VQRSHL_by_vecs16
+/* 19429 */   MCD_OPC_FilterValue, 15, 22, 23, 0, // Skip to: 25344
+/* 19434 */   MCD_OPC_CheckPredicate, 22, 17, 23, 0, // Skip to: 25344
+/* 19439 */   MCD_OPC_CheckField, 16, 1, 0, 10, 23, 0, // Skip to: 25344
+/* 19446 */   MCD_OPC_CheckField, 6, 1, 1, 3, 23, 0, // Skip to: 25344
+/* 19453 */   MCD_OPC_CheckField, 0, 1, 0, 252, 22, 0, // Skip to: 25344
+/* 19460 */   MCD_OPC_Decode, 218, 11, 189, 1, // Opcode: MVE_VQRSHL_by_vecu16
+/* 19465 */   MCD_OPC_FilterValue, 2, 242, 22, 0, // Skip to: 25344
+/* 19470 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 19473 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 19553
+/* 19478 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19481 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19517
+/* 19486 */   MCD_OPC_CheckPredicate, 22, 221, 22, 0, // Skip to: 25344
+/* 19491 */   MCD_OPC_CheckField, 16, 1, 0, 214, 22, 0, // Skip to: 25344
+/* 19498 */   MCD_OPC_CheckField, 6, 1, 1, 207, 22, 0, // Skip to: 25344
+/* 19505 */   MCD_OPC_CheckField, 0, 1, 0, 200, 22, 0, // Skip to: 25344
+/* 19512 */   MCD_OPC_Decode, 197, 12, 189, 1, // Opcode: MVE_VRSHL_by_vecs32
+/* 19517 */   MCD_OPC_FilterValue, 15, 190, 22, 0, // Skip to: 25344
+/* 19522 */   MCD_OPC_CheckPredicate, 22, 185, 22, 0, // Skip to: 25344
+/* 19527 */   MCD_OPC_CheckField, 16, 1, 0, 178, 22, 0, // Skip to: 25344
+/* 19534 */   MCD_OPC_CheckField, 6, 1, 1, 171, 22, 0, // Skip to: 25344
+/* 19541 */   MCD_OPC_CheckField, 0, 1, 0, 164, 22, 0, // Skip to: 25344
+/* 19548 */   MCD_OPC_Decode, 200, 12, 189, 1, // Opcode: MVE_VRSHL_by_vecu32
+/* 19553 */   MCD_OPC_FilterValue, 1, 154, 22, 0, // Skip to: 25344
+/* 19558 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19561 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19597
+/* 19566 */   MCD_OPC_CheckPredicate, 22, 141, 22, 0, // Skip to: 25344
+/* 19571 */   MCD_OPC_CheckField, 16, 1, 0, 134, 22, 0, // Skip to: 25344
+/* 19578 */   MCD_OPC_CheckField, 6, 1, 1, 127, 22, 0, // Skip to: 25344
+/* 19585 */   MCD_OPC_CheckField, 0, 1, 0, 120, 22, 0, // Skip to: 25344
+/* 19592 */   MCD_OPC_Decode, 216, 11, 189, 1, // Opcode: MVE_VQRSHL_by_vecs32
+/* 19597 */   MCD_OPC_FilterValue, 15, 110, 22, 0, // Skip to: 25344
+/* 19602 */   MCD_OPC_CheckPredicate, 22, 105, 22, 0, // Skip to: 25344
+/* 19607 */   MCD_OPC_CheckField, 16, 1, 0, 98, 22, 0, // Skip to: 25344
+/* 19614 */   MCD_OPC_CheckField, 6, 1, 1, 91, 22, 0, // Skip to: 25344
+/* 19621 */   MCD_OPC_CheckField, 0, 1, 0, 84, 22, 0, // Skip to: 25344
+/* 19628 */   MCD_OPC_Decode, 219, 11, 189, 1, // Opcode: MVE_VQRSHL_by_vecu32
+/* 19633 */   MCD_OPC_FilterValue, 6, 251, 1, 0, // Skip to: 20145
+/* 19638 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 19641 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 19809
+/* 19646 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 19649 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 19729
+/* 19654 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19657 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19693
+/* 19662 */   MCD_OPC_CheckPredicate, 22, 45, 22, 0, // Skip to: 25344
+/* 19667 */   MCD_OPC_CheckField, 16, 1, 0, 38, 22, 0, // Skip to: 25344
+/* 19674 */   MCD_OPC_CheckField, 6, 1, 1, 31, 22, 0, // Skip to: 25344
+/* 19681 */   MCD_OPC_CheckField, 0, 1, 0, 24, 22, 0, // Skip to: 25344
+/* 19688 */   MCD_OPC_Decode, 203, 9, 143, 1, // Opcode: MVE_VMAXs8
+/* 19693 */   MCD_OPC_FilterValue, 15, 14, 22, 0, // Skip to: 25344
+/* 19698 */   MCD_OPC_CheckPredicate, 22, 9, 22, 0, // Skip to: 25344
+/* 19703 */   MCD_OPC_CheckField, 16, 1, 0, 2, 22, 0, // Skip to: 25344
+/* 19710 */   MCD_OPC_CheckField, 6, 1, 1, 251, 21, 0, // Skip to: 25344
+/* 19717 */   MCD_OPC_CheckField, 0, 1, 0, 244, 21, 0, // Skip to: 25344
+/* 19724 */   MCD_OPC_Decode, 206, 9, 143, 1, // Opcode: MVE_VMAXu8
+/* 19729 */   MCD_OPC_FilterValue, 1, 234, 21, 0, // Skip to: 25344
+/* 19734 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19737 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19773
+/* 19742 */   MCD_OPC_CheckPredicate, 22, 221, 21, 0, // Skip to: 25344
+/* 19747 */   MCD_OPC_CheckField, 16, 1, 0, 214, 21, 0, // Skip to: 25344
+/* 19754 */   MCD_OPC_CheckField, 6, 1, 1, 207, 21, 0, // Skip to: 25344
+/* 19761 */   MCD_OPC_CheckField, 0, 1, 0, 200, 21, 0, // Skip to: 25344
+/* 19768 */   MCD_OPC_Decode, 229, 9, 143, 1, // Opcode: MVE_VMINs8
+/* 19773 */   MCD_OPC_FilterValue, 15, 190, 21, 0, // Skip to: 25344
+/* 19778 */   MCD_OPC_CheckPredicate, 22, 185, 21, 0, // Skip to: 25344
+/* 19783 */   MCD_OPC_CheckField, 16, 1, 0, 178, 21, 0, // Skip to: 25344
+/* 19790 */   MCD_OPC_CheckField, 6, 1, 1, 171, 21, 0, // Skip to: 25344
+/* 19797 */   MCD_OPC_CheckField, 0, 1, 0, 164, 21, 0, // Skip to: 25344
+/* 19804 */   MCD_OPC_Decode, 232, 9, 143, 1, // Opcode: MVE_VMINu8
+/* 19809 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 19977
+/* 19814 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 19817 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 19897
+/* 19822 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19825 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19861
+/* 19830 */   MCD_OPC_CheckPredicate, 22, 133, 21, 0, // Skip to: 25344
+/* 19835 */   MCD_OPC_CheckField, 16, 1, 0, 126, 21, 0, // Skip to: 25344
+/* 19842 */   MCD_OPC_CheckField, 6, 1, 1, 119, 21, 0, // Skip to: 25344
+/* 19849 */   MCD_OPC_CheckField, 0, 1, 0, 112, 21, 0, // Skip to: 25344
+/* 19856 */   MCD_OPC_Decode, 201, 9, 143, 1, // Opcode: MVE_VMAXs16
+/* 19861 */   MCD_OPC_FilterValue, 15, 102, 21, 0, // Skip to: 25344
+/* 19866 */   MCD_OPC_CheckPredicate, 22, 97, 21, 0, // Skip to: 25344
+/* 19871 */   MCD_OPC_CheckField, 16, 1, 0, 90, 21, 0, // Skip to: 25344
+/* 19878 */   MCD_OPC_CheckField, 6, 1, 1, 83, 21, 0, // Skip to: 25344
+/* 19885 */   MCD_OPC_CheckField, 0, 1, 0, 76, 21, 0, // Skip to: 25344
+/* 19892 */   MCD_OPC_Decode, 204, 9, 143, 1, // Opcode: MVE_VMAXu16
+/* 19897 */   MCD_OPC_FilterValue, 1, 66, 21, 0, // Skip to: 25344
+/* 19902 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19905 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 19941
+/* 19910 */   MCD_OPC_CheckPredicate, 22, 53, 21, 0, // Skip to: 25344
+/* 19915 */   MCD_OPC_CheckField, 16, 1, 0, 46, 21, 0, // Skip to: 25344
+/* 19922 */   MCD_OPC_CheckField, 6, 1, 1, 39, 21, 0, // Skip to: 25344
+/* 19929 */   MCD_OPC_CheckField, 0, 1, 0, 32, 21, 0, // Skip to: 25344
+/* 19936 */   MCD_OPC_Decode, 227, 9, 143, 1, // Opcode: MVE_VMINs16
+/* 19941 */   MCD_OPC_FilterValue, 15, 22, 21, 0, // Skip to: 25344
+/* 19946 */   MCD_OPC_CheckPredicate, 22, 17, 21, 0, // Skip to: 25344
+/* 19951 */   MCD_OPC_CheckField, 16, 1, 0, 10, 21, 0, // Skip to: 25344
+/* 19958 */   MCD_OPC_CheckField, 6, 1, 1, 3, 21, 0, // Skip to: 25344
+/* 19965 */   MCD_OPC_CheckField, 0, 1, 0, 252, 20, 0, // Skip to: 25344
+/* 19972 */   MCD_OPC_Decode, 230, 9, 143, 1, // Opcode: MVE_VMINu16
+/* 19977 */   MCD_OPC_FilterValue, 2, 242, 20, 0, // Skip to: 25344
+/* 19982 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 19985 */   MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 20065
+/* 19990 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 19993 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 20029
+/* 19998 */   MCD_OPC_CheckPredicate, 22, 221, 20, 0, // Skip to: 25344
+/* 20003 */   MCD_OPC_CheckField, 16, 1, 0, 214, 20, 0, // Skip to: 25344
+/* 20010 */   MCD_OPC_CheckField, 6, 1, 1, 207, 20, 0, // Skip to: 25344
+/* 20017 */   MCD_OPC_CheckField, 0, 1, 0, 200, 20, 0, // Skip to: 25344
+/* 20024 */   MCD_OPC_Decode, 202, 9, 143, 1, // Opcode: MVE_VMAXs32
+/* 20029 */   MCD_OPC_FilterValue, 15, 190, 20, 0, // Skip to: 25344
+/* 20034 */   MCD_OPC_CheckPredicate, 22, 185, 20, 0, // Skip to: 25344
+/* 20039 */   MCD_OPC_CheckField, 16, 1, 0, 178, 20, 0, // Skip to: 25344
+/* 20046 */   MCD_OPC_CheckField, 6, 1, 1, 171, 20, 0, // Skip to: 25344
+/* 20053 */   MCD_OPC_CheckField, 0, 1, 0, 164, 20, 0, // Skip to: 25344
+/* 20060 */   MCD_OPC_Decode, 205, 9, 143, 1, // Opcode: MVE_VMAXu32
+/* 20065 */   MCD_OPC_FilterValue, 1, 154, 20, 0, // Skip to: 25344
+/* 20070 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20073 */   MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 20109
+/* 20078 */   MCD_OPC_CheckPredicate, 22, 141, 20, 0, // Skip to: 25344
+/* 20083 */   MCD_OPC_CheckField, 16, 1, 0, 134, 20, 0, // Skip to: 25344
+/* 20090 */   MCD_OPC_CheckField, 6, 1, 1, 127, 20, 0, // Skip to: 25344
+/* 20097 */   MCD_OPC_CheckField, 0, 1, 0, 120, 20, 0, // Skip to: 25344
+/* 20104 */   MCD_OPC_Decode, 228, 9, 143, 1, // Opcode: MVE_VMINs32
+/* 20109 */   MCD_OPC_FilterValue, 15, 110, 20, 0, // Skip to: 25344
+/* 20114 */   MCD_OPC_CheckPredicate, 22, 105, 20, 0, // Skip to: 25344
+/* 20119 */   MCD_OPC_CheckField, 16, 1, 0, 98, 20, 0, // Skip to: 25344
+/* 20126 */   MCD_OPC_CheckField, 6, 1, 1, 91, 20, 0, // Skip to: 25344
+/* 20133 */   MCD_OPC_CheckField, 0, 1, 0, 84, 20, 0, // Skip to: 25344
+/* 20140 */   MCD_OPC_Decode, 231, 9, 143, 1, // Opcode: MVE_VMINu32
+/* 20145 */   MCD_OPC_FilterValue, 7, 29, 1, 0, // Skip to: 20435
+/* 20150 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 20153 */   MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 20247
+/* 20158 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20161 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20204
+/* 20166 */   MCD_OPC_CheckPredicate, 22, 53, 20, 0, // Skip to: 25344
+/* 20171 */   MCD_OPC_CheckField, 16, 1, 0, 46, 20, 0, // Skip to: 25344
+/* 20178 */   MCD_OPC_CheckField, 6, 1, 1, 39, 20, 0, // Skip to: 25344
+/* 20185 */   MCD_OPC_CheckField, 4, 1, 0, 32, 20, 0, // Skip to: 25344
+/* 20192 */   MCD_OPC_CheckField, 0, 1, 0, 25, 20, 0, // Skip to: 25344
+/* 20199 */   MCD_OPC_Decode, 183, 7, 143, 1, // Opcode: MVE_VABDs8
+/* 20204 */   MCD_OPC_FilterValue, 15, 15, 20, 0, // Skip to: 25344
+/* 20209 */   MCD_OPC_CheckPredicate, 22, 10, 20, 0, // Skip to: 25344
+/* 20214 */   MCD_OPC_CheckField, 16, 1, 0, 3, 20, 0, // Skip to: 25344
+/* 20221 */   MCD_OPC_CheckField, 6, 1, 1, 252, 19, 0, // Skip to: 25344
+/* 20228 */   MCD_OPC_CheckField, 4, 1, 0, 245, 19, 0, // Skip to: 25344
+/* 20235 */   MCD_OPC_CheckField, 0, 1, 0, 238, 19, 0, // Skip to: 25344
+/* 20242 */   MCD_OPC_Decode, 186, 7, 143, 1, // Opcode: MVE_VABDu8
+/* 20247 */   MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 20341
+/* 20252 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20255 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20298
+/* 20260 */   MCD_OPC_CheckPredicate, 22, 215, 19, 0, // Skip to: 25344
+/* 20265 */   MCD_OPC_CheckField, 16, 1, 0, 208, 19, 0, // Skip to: 25344
+/* 20272 */   MCD_OPC_CheckField, 6, 1, 1, 201, 19, 0, // Skip to: 25344
+/* 20279 */   MCD_OPC_CheckField, 4, 1, 0, 194, 19, 0, // Skip to: 25344
+/* 20286 */   MCD_OPC_CheckField, 0, 1, 0, 187, 19, 0, // Skip to: 25344
+/* 20293 */   MCD_OPC_Decode, 181, 7, 143, 1, // Opcode: MVE_VABDs16
+/* 20298 */   MCD_OPC_FilterValue, 15, 177, 19, 0, // Skip to: 25344
+/* 20303 */   MCD_OPC_CheckPredicate, 22, 172, 19, 0, // Skip to: 25344
+/* 20308 */   MCD_OPC_CheckField, 16, 1, 0, 165, 19, 0, // Skip to: 25344
+/* 20315 */   MCD_OPC_CheckField, 6, 1, 1, 158, 19, 0, // Skip to: 25344
+/* 20322 */   MCD_OPC_CheckField, 4, 1, 0, 151, 19, 0, // Skip to: 25344
+/* 20329 */   MCD_OPC_CheckField, 0, 1, 0, 144, 19, 0, // Skip to: 25344
+/* 20336 */   MCD_OPC_Decode, 184, 7, 143, 1, // Opcode: MVE_VABDu16
+/* 20341 */   MCD_OPC_FilterValue, 2, 134, 19, 0, // Skip to: 25344
+/* 20346 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20349 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20392
+/* 20354 */   MCD_OPC_CheckPredicate, 22, 121, 19, 0, // Skip to: 25344
+/* 20359 */   MCD_OPC_CheckField, 16, 1, 0, 114, 19, 0, // Skip to: 25344
+/* 20366 */   MCD_OPC_CheckField, 6, 1, 1, 107, 19, 0, // Skip to: 25344
+/* 20373 */   MCD_OPC_CheckField, 4, 1, 0, 100, 19, 0, // Skip to: 25344
+/* 20380 */   MCD_OPC_CheckField, 0, 1, 0, 93, 19, 0, // Skip to: 25344
+/* 20387 */   MCD_OPC_Decode, 182, 7, 143, 1, // Opcode: MVE_VABDs32
+/* 20392 */   MCD_OPC_FilterValue, 15, 83, 19, 0, // Skip to: 25344
+/* 20397 */   MCD_OPC_CheckPredicate, 22, 78, 19, 0, // Skip to: 25344
+/* 20402 */   MCD_OPC_CheckField, 16, 1, 0, 71, 19, 0, // Skip to: 25344
+/* 20409 */   MCD_OPC_CheckField, 6, 1, 1, 64, 19, 0, // Skip to: 25344
+/* 20416 */   MCD_OPC_CheckField, 4, 1, 0, 57, 19, 0, // Skip to: 25344
+/* 20423 */   MCD_OPC_CheckField, 0, 1, 0, 50, 19, 0, // Skip to: 25344
+/* 20430 */   MCD_OPC_Decode, 185, 7, 143, 1, // Opcode: MVE_VABDu32
+/* 20435 */   MCD_OPC_FilterValue, 8, 29, 1, 0, // Skip to: 20725
+/* 20440 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 20443 */   MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 20537
+/* 20448 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20451 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20494
+/* 20456 */   MCD_OPC_CheckPredicate, 22, 19, 19, 0, // Skip to: 25344
+/* 20461 */   MCD_OPC_CheckField, 16, 1, 0, 12, 19, 0, // Skip to: 25344
+/* 20468 */   MCD_OPC_CheckField, 6, 1, 1, 5, 19, 0, // Skip to: 25344
+/* 20475 */   MCD_OPC_CheckField, 4, 1, 0, 254, 18, 0, // Skip to: 25344
+/* 20482 */   MCD_OPC_CheckField, 0, 1, 0, 247, 18, 0, // Skip to: 25344
+/* 20489 */   MCD_OPC_Decode, 219, 7, 143, 1, // Opcode: MVE_VADDi8
+/* 20494 */   MCD_OPC_FilterValue, 15, 237, 18, 0, // Skip to: 25344
+/* 20499 */   MCD_OPC_CheckPredicate, 22, 232, 18, 0, // Skip to: 25344
+/* 20504 */   MCD_OPC_CheckField, 16, 1, 0, 225, 18, 0, // Skip to: 25344
+/* 20511 */   MCD_OPC_CheckField, 6, 1, 1, 218, 18, 0, // Skip to: 25344
+/* 20518 */   MCD_OPC_CheckField, 4, 1, 0, 211, 18, 0, // Skip to: 25344
+/* 20525 */   MCD_OPC_CheckField, 0, 1, 0, 204, 18, 0, // Skip to: 25344
+/* 20532 */   MCD_OPC_Decode, 218, 13, 143, 1, // Opcode: MVE_VSUBi8
+/* 20537 */   MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 20631
+/* 20542 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20545 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20588
+/* 20550 */   MCD_OPC_CheckPredicate, 22, 181, 18, 0, // Skip to: 25344
+/* 20555 */   MCD_OPC_CheckField, 16, 1, 0, 174, 18, 0, // Skip to: 25344
+/* 20562 */   MCD_OPC_CheckField, 6, 1, 1, 167, 18, 0, // Skip to: 25344
+/* 20569 */   MCD_OPC_CheckField, 4, 1, 0, 160, 18, 0, // Skip to: 25344
+/* 20576 */   MCD_OPC_CheckField, 0, 1, 0, 153, 18, 0, // Skip to: 25344
+/* 20583 */   MCD_OPC_Decode, 217, 7, 143, 1, // Opcode: MVE_VADDi16
+/* 20588 */   MCD_OPC_FilterValue, 15, 143, 18, 0, // Skip to: 25344
+/* 20593 */   MCD_OPC_CheckPredicate, 22, 138, 18, 0, // Skip to: 25344
+/* 20598 */   MCD_OPC_CheckField, 16, 1, 0, 131, 18, 0, // Skip to: 25344
+/* 20605 */   MCD_OPC_CheckField, 6, 1, 1, 124, 18, 0, // Skip to: 25344
+/* 20612 */   MCD_OPC_CheckField, 4, 1, 0, 117, 18, 0, // Skip to: 25344
+/* 20619 */   MCD_OPC_CheckField, 0, 1, 0, 110, 18, 0, // Skip to: 25344
+/* 20626 */   MCD_OPC_Decode, 216, 13, 143, 1, // Opcode: MVE_VSUBi16
+/* 20631 */   MCD_OPC_FilterValue, 2, 100, 18, 0, // Skip to: 25344
+/* 20636 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20639 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20682
+/* 20644 */   MCD_OPC_CheckPredicate, 22, 87, 18, 0, // Skip to: 25344
+/* 20649 */   MCD_OPC_CheckField, 16, 1, 0, 80, 18, 0, // Skip to: 25344
+/* 20656 */   MCD_OPC_CheckField, 6, 1, 1, 73, 18, 0, // Skip to: 25344
+/* 20663 */   MCD_OPC_CheckField, 4, 1, 0, 66, 18, 0, // Skip to: 25344
+/* 20670 */   MCD_OPC_CheckField, 0, 1, 0, 59, 18, 0, // Skip to: 25344
+/* 20677 */   MCD_OPC_Decode, 218, 7, 143, 1, // Opcode: MVE_VADDi32
+/* 20682 */   MCD_OPC_FilterValue, 15, 49, 18, 0, // Skip to: 25344
+/* 20687 */   MCD_OPC_CheckPredicate, 22, 44, 18, 0, // Skip to: 25344
+/* 20692 */   MCD_OPC_CheckField, 16, 1, 0, 37, 18, 0, // Skip to: 25344
+/* 20699 */   MCD_OPC_CheckField, 6, 1, 1, 30, 18, 0, // Skip to: 25344
+/* 20706 */   MCD_OPC_CheckField, 4, 1, 0, 23, 18, 0, // Skip to: 25344
+/* 20713 */   MCD_OPC_CheckField, 0, 1, 0, 16, 18, 0, // Skip to: 25344
+/* 20720 */   MCD_OPC_Decode, 217, 13, 143, 1, // Opcode: MVE_VSUBi32
+/* 20725 */   MCD_OPC_FilterValue, 9, 153, 0, 0, // Skip to: 20883
+/* 20730 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 20733 */   MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 20783
+/* 20738 */   MCD_OPC_CheckPredicate, 22, 249, 17, 0, // Skip to: 25344
+/* 20743 */   MCD_OPC_CheckField, 28, 4, 14, 242, 17, 0, // Skip to: 25344
+/* 20750 */   MCD_OPC_CheckField, 16, 1, 0, 235, 17, 0, // Skip to: 25344
+/* 20757 */   MCD_OPC_CheckField, 6, 1, 1, 228, 17, 0, // Skip to: 25344
+/* 20764 */   MCD_OPC_CheckField, 4, 1, 1, 221, 17, 0, // Skip to: 25344
+/* 20771 */   MCD_OPC_CheckField, 0, 1, 0, 214, 17, 0, // Skip to: 25344
+/* 20778 */   MCD_OPC_Decode, 219, 10, 143, 1, // Opcode: MVE_VMULi8
+/* 20783 */   MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 20833
+/* 20788 */   MCD_OPC_CheckPredicate, 22, 199, 17, 0, // Skip to: 25344
+/* 20793 */   MCD_OPC_CheckField, 28, 4, 14, 192, 17, 0, // Skip to: 25344
+/* 20800 */   MCD_OPC_CheckField, 16, 1, 0, 185, 17, 0, // Skip to: 25344
+/* 20807 */   MCD_OPC_CheckField, 6, 1, 1, 178, 17, 0, // Skip to: 25344
+/* 20814 */   MCD_OPC_CheckField, 4, 1, 1, 171, 17, 0, // Skip to: 25344
+/* 20821 */   MCD_OPC_CheckField, 0, 1, 0, 164, 17, 0, // Skip to: 25344
+/* 20828 */   MCD_OPC_Decode, 217, 10, 143, 1, // Opcode: MVE_VMULi16
+/* 20833 */   MCD_OPC_FilterValue, 2, 154, 17, 0, // Skip to: 25344
+/* 20838 */   MCD_OPC_CheckPredicate, 22, 149, 17, 0, // Skip to: 25344
+/* 20843 */   MCD_OPC_CheckField, 28, 4, 14, 142, 17, 0, // Skip to: 25344
+/* 20850 */   MCD_OPC_CheckField, 16, 1, 0, 135, 17, 0, // Skip to: 25344
+/* 20857 */   MCD_OPC_CheckField, 6, 1, 1, 128, 17, 0, // Skip to: 25344
+/* 20864 */   MCD_OPC_CheckField, 4, 1, 1, 121, 17, 0, // Skip to: 25344
+/* 20871 */   MCD_OPC_CheckField, 0, 1, 0, 114, 17, 0, // Skip to: 25344
+/* 20878 */   MCD_OPC_Decode, 218, 10, 143, 1, // Opcode: MVE_VMULi32
+/* 20883 */   MCD_OPC_FilterValue, 11, 29, 1, 0, // Skip to: 21173
+/* 20888 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 20891 */   MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 20985
+/* 20896 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20899 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 20942
+/* 20904 */   MCD_OPC_CheckPredicate, 22, 83, 17, 0, // Skip to: 25344
+/* 20909 */   MCD_OPC_CheckField, 16, 1, 0, 76, 17, 0, // Skip to: 25344
+/* 20916 */   MCD_OPC_CheckField, 6, 1, 1, 69, 17, 0, // Skip to: 25344
+/* 20923 */   MCD_OPC_CheckField, 4, 1, 0, 62, 17, 0, // Skip to: 25344
+/* 20930 */   MCD_OPC_CheckField, 0, 1, 0, 55, 17, 0, // Skip to: 25344
+/* 20937 */   MCD_OPC_Decode, 167, 11, 143, 1, // Opcode: MVE_VQDMULHi8
+/* 20942 */   MCD_OPC_FilterValue, 15, 45, 17, 0, // Skip to: 25344
+/* 20947 */   MCD_OPC_CheckPredicate, 22, 40, 17, 0, // Skip to: 25344
+/* 20952 */   MCD_OPC_CheckField, 16, 1, 0, 33, 17, 0, // Skip to: 25344
+/* 20959 */   MCD_OPC_CheckField, 6, 1, 1, 26, 17, 0, // Skip to: 25344
+/* 20966 */   MCD_OPC_CheckField, 4, 1, 0, 19, 17, 0, // Skip to: 25344
+/* 20973 */   MCD_OPC_CheckField, 0, 1, 0, 12, 17, 0, // Skip to: 25344
+/* 20980 */   MCD_OPC_Decode, 214, 11, 143, 1, // Opcode: MVE_VQRDMULHi8
+/* 20985 */   MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 21079
+/* 20990 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 20993 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 21036
+/* 20998 */   MCD_OPC_CheckPredicate, 22, 245, 16, 0, // Skip to: 25344
+/* 21003 */   MCD_OPC_CheckField, 16, 1, 0, 238, 16, 0, // Skip to: 25344
+/* 21010 */   MCD_OPC_CheckField, 6, 1, 1, 231, 16, 0, // Skip to: 25344
+/* 21017 */   MCD_OPC_CheckField, 4, 1, 0, 224, 16, 0, // Skip to: 25344
+/* 21024 */   MCD_OPC_CheckField, 0, 1, 0, 217, 16, 0, // Skip to: 25344
+/* 21031 */   MCD_OPC_Decode, 165, 11, 143, 1, // Opcode: MVE_VQDMULHi16
+/* 21036 */   MCD_OPC_FilterValue, 15, 207, 16, 0, // Skip to: 25344
+/* 21041 */   MCD_OPC_CheckPredicate, 22, 202, 16, 0, // Skip to: 25344
+/* 21046 */   MCD_OPC_CheckField, 16, 1, 0, 195, 16, 0, // Skip to: 25344
+/* 21053 */   MCD_OPC_CheckField, 6, 1, 1, 188, 16, 0, // Skip to: 25344
+/* 21060 */   MCD_OPC_CheckField, 4, 1, 0, 181, 16, 0, // Skip to: 25344
+/* 21067 */   MCD_OPC_CheckField, 0, 1, 0, 174, 16, 0, // Skip to: 25344
+/* 21074 */   MCD_OPC_Decode, 212, 11, 143, 1, // Opcode: MVE_VQRDMULHi16
+/* 21079 */   MCD_OPC_FilterValue, 2, 164, 16, 0, // Skip to: 25344
+/* 21084 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 21087 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 21130
+/* 21092 */   MCD_OPC_CheckPredicate, 22, 151, 16, 0, // Skip to: 25344
+/* 21097 */   MCD_OPC_CheckField, 16, 1, 0, 144, 16, 0, // Skip to: 25344
+/* 21104 */   MCD_OPC_CheckField, 6, 1, 1, 137, 16, 0, // Skip to: 25344
+/* 21111 */   MCD_OPC_CheckField, 4, 1, 0, 130, 16, 0, // Skip to: 25344
+/* 21118 */   MCD_OPC_CheckField, 0, 1, 0, 123, 16, 0, // Skip to: 25344
+/* 21125 */   MCD_OPC_Decode, 166, 11, 143, 1, // Opcode: MVE_VQDMULHi32
+/* 21130 */   MCD_OPC_FilterValue, 15, 113, 16, 0, // Skip to: 25344
+/* 21135 */   MCD_OPC_CheckPredicate, 22, 108, 16, 0, // Skip to: 25344
+/* 21140 */   MCD_OPC_CheckField, 16, 1, 0, 101, 16, 0, // Skip to: 25344
+/* 21147 */   MCD_OPC_CheckField, 6, 1, 1, 94, 16, 0, // Skip to: 25344
+/* 21154 */   MCD_OPC_CheckField, 4, 1, 0, 87, 16, 0, // Skip to: 25344
+/* 21161 */   MCD_OPC_CheckField, 0, 1, 0, 80, 16, 0, // Skip to: 25344
+/* 21168 */   MCD_OPC_Decode, 213, 11, 143, 1, // Opcode: MVE_VQRDMULHi32
+/* 21173 */   MCD_OPC_FilterValue, 12, 203, 0, 0, // Skip to: 21381
+/* 21178 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 21181 */   MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 21231
+/* 21186 */   MCD_OPC_CheckPredicate, 24, 57, 16, 0, // Skip to: 25344
+/* 21191 */   MCD_OPC_CheckField, 28, 4, 14, 50, 16, 0, // Skip to: 25344
+/* 21198 */   MCD_OPC_CheckField, 16, 1, 0, 43, 16, 0, // Skip to: 25344
+/* 21205 */   MCD_OPC_CheckField, 6, 1, 1, 36, 16, 0, // Skip to: 25344
+/* 21212 */   MCD_OPC_CheckField, 4, 1, 1, 29, 16, 0, // Skip to: 25344
+/* 21219 */   MCD_OPC_CheckField, 0, 1, 0, 22, 16, 0, // Skip to: 25344
+/* 21226 */   MCD_OPC_Decode, 191, 8, 142, 1, // Opcode: MVE_VFMAf32
+/* 21231 */   MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 21281
+/* 21236 */   MCD_OPC_CheckPredicate, 24, 7, 16, 0, // Skip to: 25344
+/* 21241 */   MCD_OPC_CheckField, 28, 4, 14, 0, 16, 0, // Skip to: 25344
+/* 21248 */   MCD_OPC_CheckField, 16, 1, 0, 249, 15, 0, // Skip to: 25344
+/* 21255 */   MCD_OPC_CheckField, 6, 1, 1, 242, 15, 0, // Skip to: 25344
+/* 21262 */   MCD_OPC_CheckField, 4, 1, 1, 235, 15, 0, // Skip to: 25344
+/* 21269 */   MCD_OPC_CheckField, 0, 1, 0, 228, 15, 0, // Skip to: 25344
+/* 21276 */   MCD_OPC_Decode, 190, 8, 142, 1, // Opcode: MVE_VFMAf16
+/* 21281 */   MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 21331
+/* 21286 */   MCD_OPC_CheckPredicate, 24, 213, 15, 0, // Skip to: 25344
+/* 21291 */   MCD_OPC_CheckField, 28, 4, 14, 206, 15, 0, // Skip to: 25344
+/* 21298 */   MCD_OPC_CheckField, 16, 1, 0, 199, 15, 0, // Skip to: 25344
+/* 21305 */   MCD_OPC_CheckField, 6, 1, 1, 192, 15, 0, // Skip to: 25344
+/* 21312 */   MCD_OPC_CheckField, 4, 1, 1, 185, 15, 0, // Skip to: 25344
+/* 21319 */   MCD_OPC_CheckField, 0, 1, 0, 178, 15, 0, // Skip to: 25344
+/* 21326 */   MCD_OPC_Decode, 193, 8, 142, 1, // Opcode: MVE_VFMSf32
+/* 21331 */   MCD_OPC_FilterValue, 3, 168, 15, 0, // Skip to: 25344
+/* 21336 */   MCD_OPC_CheckPredicate, 24, 163, 15, 0, // Skip to: 25344
+/* 21341 */   MCD_OPC_CheckField, 28, 4, 14, 156, 15, 0, // Skip to: 25344
+/* 21348 */   MCD_OPC_CheckField, 16, 1, 0, 149, 15, 0, // Skip to: 25344
+/* 21355 */   MCD_OPC_CheckField, 6, 1, 1, 142, 15, 0, // Skip to: 25344
+/* 21362 */   MCD_OPC_CheckField, 4, 1, 1, 135, 15, 0, // Skip to: 25344
+/* 21369 */   MCD_OPC_CheckField, 0, 1, 0, 128, 15, 0, // Skip to: 25344
+/* 21376 */   MCD_OPC_Decode, 192, 8, 142, 1, // Opcode: MVE_VFMSf16
+/* 21381 */   MCD_OPC_FilterValue, 13, 123, 1, 0, // Skip to: 21765
+/* 21386 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 21389 */   MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 21483
+/* 21394 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 21397 */   MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 21440
+/* 21402 */   MCD_OPC_CheckPredicate, 24, 97, 15, 0, // Skip to: 25344
+/* 21407 */   MCD_OPC_CheckField, 28, 4, 14, 90, 15, 0, // Skip to: 25344
+/* 21414 */   MCD_OPC_CheckField, 16, 1, 0, 83, 15, 0, // Skip to: 25344
+/* 21421 */   MCD_OPC_CheckField, 6, 1, 1, 76, 15, 0, // Skip to: 25344
+/* 21428 */   MCD_OPC_CheckField, 0, 1, 0, 69, 15, 0, // Skip to: 25344
+/* 21435 */   MCD_OPC_Decode, 216, 7, 143, 1, // Opcode: MVE_VADDf32
+/* 21440 */   MCD_OPC_FilterValue, 1, 59, 15, 0, // Skip to: 25344
+/* 21445 */   MCD_OPC_CheckPredicate, 24, 54, 15, 0, // Skip to: 25344
+/* 21450 */   MCD_OPC_CheckField, 28, 4, 15, 47, 15, 0, // Skip to: 25344
+/* 21457 */   MCD_OPC_CheckField, 16, 1, 0, 40, 15, 0, // Skip to: 25344
+/* 21464 */   MCD_OPC_CheckField, 6, 1, 1, 33, 15, 0, // Skip to: 25344
+/* 21471 */   MCD_OPC_CheckField, 0, 1, 0, 26, 15, 0, // Skip to: 25344
+/* 21478 */   MCD_OPC_Decode, 216, 10, 143, 1, // Opcode: MVE_VMULf32
+/* 21483 */   MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 21577
+/* 21488 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 21491 */   MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 21534
+/* 21496 */   MCD_OPC_CheckPredicate, 24, 3, 15, 0, // Skip to: 25344
+/* 21501 */   MCD_OPC_CheckField, 28, 4, 14, 252, 14, 0, // Skip to: 25344
+/* 21508 */   MCD_OPC_CheckField, 16, 1, 0, 245, 14, 0, // Skip to: 25344
+/* 21515 */   MCD_OPC_CheckField, 6, 1, 1, 238, 14, 0, // Skip to: 25344
+/* 21522 */   MCD_OPC_CheckField, 0, 1, 0, 231, 14, 0, // Skip to: 25344
+/* 21529 */   MCD_OPC_Decode, 215, 7, 143, 1, // Opcode: MVE_VADDf16
+/* 21534 */   MCD_OPC_FilterValue, 1, 221, 14, 0, // Skip to: 25344
+/* 21539 */   MCD_OPC_CheckPredicate, 24, 216, 14, 0, // Skip to: 25344
+/* 21544 */   MCD_OPC_CheckField, 28, 4, 15, 209, 14, 0, // Skip to: 25344
+/* 21551 */   MCD_OPC_CheckField, 16, 1, 0, 202, 14, 0, // Skip to: 25344
+/* 21558 */   MCD_OPC_CheckField, 6, 1, 1, 195, 14, 0, // Skip to: 25344
+/* 21565 */   MCD_OPC_CheckField, 0, 1, 0, 188, 14, 0, // Skip to: 25344
+/* 21572 */   MCD_OPC_Decode, 215, 10, 143, 1, // Opcode: MVE_VMULf16
+/* 21577 */   MCD_OPC_FilterValue, 2, 89, 0, 0, // Skip to: 21671
+/* 21582 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 21585 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 21628
+/* 21590 */   MCD_OPC_CheckPredicate, 24, 165, 14, 0, // Skip to: 25344
+/* 21595 */   MCD_OPC_CheckField, 16, 1, 0, 158, 14, 0, // Skip to: 25344
+/* 21602 */   MCD_OPC_CheckField, 6, 1, 1, 151, 14, 0, // Skip to: 25344
+/* 21609 */   MCD_OPC_CheckField, 4, 1, 0, 144, 14, 0, // Skip to: 25344
+/* 21616 */   MCD_OPC_CheckField, 0, 1, 0, 137, 14, 0, // Skip to: 25344
+/* 21623 */   MCD_OPC_Decode, 215, 13, 143, 1, // Opcode: MVE_VSUBf32
+/* 21628 */   MCD_OPC_FilterValue, 15, 127, 14, 0, // Skip to: 25344
+/* 21633 */   MCD_OPC_CheckPredicate, 24, 122, 14, 0, // Skip to: 25344
+/* 21638 */   MCD_OPC_CheckField, 16, 1, 0, 115, 14, 0, // Skip to: 25344
+/* 21645 */   MCD_OPC_CheckField, 6, 1, 1, 108, 14, 0, // Skip to: 25344
+/* 21652 */   MCD_OPC_CheckField, 4, 1, 0, 101, 14, 0, // Skip to: 25344
+/* 21659 */   MCD_OPC_CheckField, 0, 1, 0, 94, 14, 0, // Skip to: 25344
+/* 21666 */   MCD_OPC_Decode, 180, 7, 143, 1, // Opcode: MVE_VABDf32
+/* 21671 */   MCD_OPC_FilterValue, 3, 84, 14, 0, // Skip to: 25344
+/* 21676 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 21679 */   MCD_OPC_FilterValue, 14, 38, 0, 0, // Skip to: 21722
+/* 21684 */   MCD_OPC_CheckPredicate, 24, 71, 14, 0, // Skip to: 25344
+/* 21689 */   MCD_OPC_CheckField, 16, 1, 0, 64, 14, 0, // Skip to: 25344
+/* 21696 */   MCD_OPC_CheckField, 6, 1, 1, 57, 14, 0, // Skip to: 25344
+/* 21703 */   MCD_OPC_CheckField, 4, 1, 0, 50, 14, 0, // Skip to: 25344
+/* 21710 */   MCD_OPC_CheckField, 0, 1, 0, 43, 14, 0, // Skip to: 25344
+/* 21717 */   MCD_OPC_Decode, 214, 13, 143, 1, // Opcode: MVE_VSUBf16
+/* 21722 */   MCD_OPC_FilterValue, 15, 33, 14, 0, // Skip to: 25344
+/* 21727 */   MCD_OPC_CheckPredicate, 24, 28, 14, 0, // Skip to: 25344
+/* 21732 */   MCD_OPC_CheckField, 16, 1, 0, 21, 14, 0, // Skip to: 25344
+/* 21739 */   MCD_OPC_CheckField, 6, 1, 1, 14, 14, 0, // Skip to: 25344
+/* 21746 */   MCD_OPC_CheckField, 4, 1, 0, 7, 14, 0, // Skip to: 25344
+/* 21753 */   MCD_OPC_CheckField, 0, 1, 0, 0, 14, 0, // Skip to: 25344
+/* 21760 */   MCD_OPC_Decode, 179, 7, 143, 1, // Opcode: MVE_VABDf16
+/* 21765 */   MCD_OPC_FilterValue, 15, 246, 13, 0, // Skip to: 25344
+/* 21770 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 21773 */   MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 21823
+/* 21778 */   MCD_OPC_CheckPredicate, 24, 233, 13, 0, // Skip to: 25344
+/* 21783 */   MCD_OPC_CheckField, 28, 4, 15, 226, 13, 0, // Skip to: 25344
+/* 21790 */   MCD_OPC_CheckField, 16, 1, 0, 219, 13, 0, // Skip to: 25344
+/* 21797 */   MCD_OPC_CheckField, 6, 1, 1, 212, 13, 0, // Skip to: 25344
+/* 21804 */   MCD_OPC_CheckField, 4, 1, 1, 205, 13, 0, // Skip to: 25344
+/* 21811 */   MCD_OPC_CheckField, 0, 1, 0, 198, 13, 0, // Skip to: 25344
+/* 21818 */   MCD_OPC_Decode, 194, 9, 143, 1, // Opcode: MVE_VMAXNMf32
+/* 21823 */   MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 21873
+/* 21828 */   MCD_OPC_CheckPredicate, 24, 183, 13, 0, // Skip to: 25344
+/* 21833 */   MCD_OPC_CheckField, 28, 4, 15, 176, 13, 0, // Skip to: 25344
+/* 21840 */   MCD_OPC_CheckField, 16, 1, 0, 169, 13, 0, // Skip to: 25344
+/* 21847 */   MCD_OPC_CheckField, 6, 1, 1, 162, 13, 0, // Skip to: 25344
+/* 21854 */   MCD_OPC_CheckField, 4, 1, 1, 155, 13, 0, // Skip to: 25344
+/* 21861 */   MCD_OPC_CheckField, 0, 1, 0, 148, 13, 0, // Skip to: 25344
+/* 21868 */   MCD_OPC_Decode, 193, 9, 143, 1, // Opcode: MVE_VMAXNMf16
+/* 21873 */   MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 21923
+/* 21878 */   MCD_OPC_CheckPredicate, 24, 133, 13, 0, // Skip to: 25344
+/* 21883 */   MCD_OPC_CheckField, 28, 4, 15, 126, 13, 0, // Skip to: 25344
+/* 21890 */   MCD_OPC_CheckField, 16, 1, 0, 119, 13, 0, // Skip to: 25344
+/* 21897 */   MCD_OPC_CheckField, 6, 1, 1, 112, 13, 0, // Skip to: 25344
+/* 21904 */   MCD_OPC_CheckField, 4, 1, 1, 105, 13, 0, // Skip to: 25344
+/* 21911 */   MCD_OPC_CheckField, 0, 1, 0, 98, 13, 0, // Skip to: 25344
+/* 21918 */   MCD_OPC_Decode, 220, 9, 143, 1, // Opcode: MVE_VMINNMf32
+/* 21923 */   MCD_OPC_FilterValue, 3, 88, 13, 0, // Skip to: 25344
+/* 21928 */   MCD_OPC_CheckPredicate, 24, 83, 13, 0, // Skip to: 25344
+/* 21933 */   MCD_OPC_CheckField, 28, 4, 15, 76, 13, 0, // Skip to: 25344
+/* 21940 */   MCD_OPC_CheckField, 16, 1, 0, 69, 13, 0, // Skip to: 25344
+/* 21947 */   MCD_OPC_CheckField, 6, 1, 1, 62, 13, 0, // Skip to: 25344
+/* 21954 */   MCD_OPC_CheckField, 4, 1, 1, 55, 13, 0, // Skip to: 25344
+/* 21961 */   MCD_OPC_CheckField, 0, 1, 0, 48, 13, 0, // Skip to: 25344
+/* 21968 */   MCD_OPC_Decode, 219, 9, 143, 1, // Opcode: MVE_VMINNMf16
+/* 21973 */   MCD_OPC_FilterValue, 3, 38, 13, 0, // Skip to: 25344
+/* 21978 */   MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 21981 */   MCD_OPC_FilterValue, 0, 224, 7, 0, // Skip to: 24002
+/* 21986 */   MCD_OPC_ExtractField, 6, 7,  // Inst{12-6} ...
+/* 21989 */   MCD_OPC_FilterValue, 1, 148, 0, 0, // Skip to: 22142
+/* 21994 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 21997 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 22026
+/* 22002 */   MCD_OPC_CheckPredicate, 22, 9, 13, 0, // Skip to: 25344
+/* 22007 */   MCD_OPC_CheckField, 28, 4, 15, 2, 13, 0, // Skip to: 25344
+/* 22014 */   MCD_OPC_CheckField, 0, 1, 0, 251, 12, 0, // Skip to: 25344
+/* 22021 */   MCD_OPC_Decode, 161, 12, 147, 1, // Opcode: MVE_VREV64_8
+/* 22026 */   MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 22055
+/* 22031 */   MCD_OPC_CheckPredicate, 22, 236, 12, 0, // Skip to: 25344
+/* 22036 */   MCD_OPC_CheckField, 28, 4, 15, 229, 12, 0, // Skip to: 25344
+/* 22043 */   MCD_OPC_CheckField, 0, 1, 0, 222, 12, 0, // Skip to: 25344
+/* 22050 */   MCD_OPC_Decode, 159, 12, 147, 1, // Opcode: MVE_VREV64_16
+/* 22055 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22084
+/* 22060 */   MCD_OPC_CheckPredicate, 24, 207, 12, 0, // Skip to: 25344
+/* 22065 */   MCD_OPC_CheckField, 28, 4, 15, 200, 12, 0, // Skip to: 25344
+/* 22072 */   MCD_OPC_CheckField, 0, 1, 0, 193, 12, 0, // Skip to: 25344
+/* 22079 */   MCD_OPC_Decode, 153, 8, 147, 1, // Opcode: MVE_VCVTs16f16a
+/* 22084 */   MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 22113
+/* 22089 */   MCD_OPC_CheckPredicate, 22, 178, 12, 0, // Skip to: 25344
+/* 22094 */   MCD_OPC_CheckField, 28, 4, 15, 171, 12, 0, // Skip to: 25344
+/* 22101 */   MCD_OPC_CheckField, 0, 1, 0, 164, 12, 0, // Skip to: 25344
+/* 22108 */   MCD_OPC_Decode, 160, 12, 147, 1, // Opcode: MVE_VREV64_32
+/* 22113 */   MCD_OPC_FilterValue, 59, 154, 12, 0, // Skip to: 25344
+/* 22118 */   MCD_OPC_CheckPredicate, 24, 149, 12, 0, // Skip to: 25344
+/* 22123 */   MCD_OPC_CheckField, 28, 4, 15, 142, 12, 0, // Skip to: 25344
+/* 22130 */   MCD_OPC_CheckField, 0, 1, 0, 135, 12, 0, // Skip to: 25344
+/* 22137 */   MCD_OPC_Decode, 159, 8, 147, 1, // Opcode: MVE_VCVTs32f32a
+/* 22142 */   MCD_OPC_FilterValue, 3, 119, 0, 0, // Skip to: 22266
+/* 22147 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22150 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 22179
+/* 22155 */   MCD_OPC_CheckPredicate, 22, 112, 12, 0, // Skip to: 25344
+/* 22160 */   MCD_OPC_CheckField, 28, 4, 15, 105, 12, 0, // Skip to: 25344
+/* 22167 */   MCD_OPC_CheckField, 0, 1, 0, 98, 12, 0, // Skip to: 25344
+/* 22174 */   MCD_OPC_Decode, 158, 12, 147, 1, // Opcode: MVE_VREV32_8
+/* 22179 */   MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 22208
+/* 22184 */   MCD_OPC_CheckPredicate, 22, 83, 12, 0, // Skip to: 25344
+/* 22189 */   MCD_OPC_CheckField, 28, 4, 15, 76, 12, 0, // Skip to: 25344
+/* 22196 */   MCD_OPC_CheckField, 0, 1, 0, 69, 12, 0, // Skip to: 25344
+/* 22203 */   MCD_OPC_Decode, 157, 12, 147, 1, // Opcode: MVE_VREV32_16
+/* 22208 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22237
+/* 22213 */   MCD_OPC_CheckPredicate, 24, 54, 12, 0, // Skip to: 25344
+/* 22218 */   MCD_OPC_CheckField, 28, 4, 15, 47, 12, 0, // Skip to: 25344
+/* 22225 */   MCD_OPC_CheckField, 0, 1, 0, 40, 12, 0, // Skip to: 25344
+/* 22232 */   MCD_OPC_Decode, 165, 8, 147, 1, // Opcode: MVE_VCVTu16f16a
+/* 22237 */   MCD_OPC_FilterValue, 59, 30, 12, 0, // Skip to: 25344
+/* 22242 */   MCD_OPC_CheckPredicate, 24, 25, 12, 0, // Skip to: 25344
+/* 22247 */   MCD_OPC_CheckField, 28, 4, 15, 18, 12, 0, // Skip to: 25344
+/* 22254 */   MCD_OPC_CheckField, 0, 1, 0, 11, 12, 0, // Skip to: 25344
+/* 22261 */   MCD_OPC_Decode, 171, 8, 147, 1, // Opcode: MVE_VCVTu32f32a
+/* 22266 */   MCD_OPC_FilterValue, 5, 90, 0, 0, // Skip to: 22361
+/* 22271 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22274 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 22303
+/* 22279 */   MCD_OPC_CheckPredicate, 22, 244, 11, 0, // Skip to: 25344
+/* 22284 */   MCD_OPC_CheckField, 28, 4, 15, 237, 11, 0, // Skip to: 25344
+/* 22291 */   MCD_OPC_CheckField, 0, 1, 0, 230, 11, 0, // Skip to: 25344
+/* 22298 */   MCD_OPC_Decode, 156, 12, 147, 1, // Opcode: MVE_VREV16_8
+/* 22303 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22332
+/* 22308 */   MCD_OPC_CheckPredicate, 24, 215, 11, 0, // Skip to: 25344
+/* 22313 */   MCD_OPC_CheckField, 28, 4, 15, 208, 11, 0, // Skip to: 25344
+/* 22320 */   MCD_OPC_CheckField, 0, 1, 0, 201, 11, 0, // Skip to: 25344
+/* 22327 */   MCD_OPC_Decode, 155, 8, 147, 1, // Opcode: MVE_VCVTs16f16n
+/* 22332 */   MCD_OPC_FilterValue, 59, 191, 11, 0, // Skip to: 25344
+/* 22337 */   MCD_OPC_CheckPredicate, 24, 186, 11, 0, // Skip to: 25344
+/* 22342 */   MCD_OPC_CheckField, 28, 4, 15, 179, 11, 0, // Skip to: 25344
+/* 22349 */   MCD_OPC_CheckField, 0, 1, 0, 172, 11, 0, // Skip to: 25344
+/* 22356 */   MCD_OPC_Decode, 161, 8, 147, 1, // Opcode: MVE_VCVTs32f32n
+/* 22361 */   MCD_OPC_FilterValue, 7, 61, 0, 0, // Skip to: 22427
+/* 22366 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22369 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22398
+/* 22374 */   MCD_OPC_CheckPredicate, 24, 149, 11, 0, // Skip to: 25344
+/* 22379 */   MCD_OPC_CheckField, 28, 4, 15, 142, 11, 0, // Skip to: 25344
+/* 22386 */   MCD_OPC_CheckField, 0, 1, 0, 135, 11, 0, // Skip to: 25344
+/* 22393 */   MCD_OPC_Decode, 167, 8, 147, 1, // Opcode: MVE_VCVTu16f16n
+/* 22398 */   MCD_OPC_FilterValue, 59, 125, 11, 0, // Skip to: 25344
+/* 22403 */   MCD_OPC_CheckPredicate, 24, 120, 11, 0, // Skip to: 25344
+/* 22408 */   MCD_OPC_CheckField, 28, 4, 15, 113, 11, 0, // Skip to: 25344
+/* 22415 */   MCD_OPC_CheckField, 0, 1, 0, 106, 11, 0, // Skip to: 25344
+/* 22422 */   MCD_OPC_Decode, 173, 8, 147, 1, // Opcode: MVE_VCVTu32f32n
+/* 22427 */   MCD_OPC_FilterValue, 9, 61, 0, 0, // Skip to: 22493
+/* 22432 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22435 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22464
+/* 22440 */   MCD_OPC_CheckPredicate, 24, 83, 11, 0, // Skip to: 25344
+/* 22445 */   MCD_OPC_CheckField, 28, 4, 15, 76, 11, 0, // Skip to: 25344
+/* 22452 */   MCD_OPC_CheckField, 0, 1, 0, 69, 11, 0, // Skip to: 25344
+/* 22459 */   MCD_OPC_Decode, 156, 8, 147, 1, // Opcode: MVE_VCVTs16f16p
+/* 22464 */   MCD_OPC_FilterValue, 59, 59, 11, 0, // Skip to: 25344
+/* 22469 */   MCD_OPC_CheckPredicate, 24, 54, 11, 0, // Skip to: 25344
+/* 22474 */   MCD_OPC_CheckField, 28, 4, 15, 47, 11, 0, // Skip to: 25344
+/* 22481 */   MCD_OPC_CheckField, 0, 1, 0, 40, 11, 0, // Skip to: 25344
+/* 22488 */   MCD_OPC_Decode, 162, 8, 147, 1, // Opcode: MVE_VCVTs32f32p
+/* 22493 */   MCD_OPC_FilterValue, 11, 61, 0, 0, // Skip to: 22559
+/* 22498 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22501 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22530
+/* 22506 */   MCD_OPC_CheckPredicate, 24, 17, 11, 0, // Skip to: 25344
+/* 22511 */   MCD_OPC_CheckField, 28, 4, 15, 10, 11, 0, // Skip to: 25344
+/* 22518 */   MCD_OPC_CheckField, 0, 1, 0, 3, 11, 0, // Skip to: 25344
+/* 22525 */   MCD_OPC_Decode, 168, 8, 147, 1, // Opcode: MVE_VCVTu16f16p
+/* 22530 */   MCD_OPC_FilterValue, 59, 249, 10, 0, // Skip to: 25344
+/* 22535 */   MCD_OPC_CheckPredicate, 24, 244, 10, 0, // Skip to: 25344
+/* 22540 */   MCD_OPC_CheckField, 28, 4, 15, 237, 10, 0, // Skip to: 25344
+/* 22547 */   MCD_OPC_CheckField, 0, 1, 0, 230, 10, 0, // Skip to: 25344
+/* 22554 */   MCD_OPC_Decode, 174, 8, 147, 1, // Opcode: MVE_VCVTu32f32p
+/* 22559 */   MCD_OPC_FilterValue, 13, 148, 0, 0, // Skip to: 22712
+/* 22564 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22567 */   MCD_OPC_FilterValue, 49, 24, 0, 0, // Skip to: 22596
+/* 22572 */   MCD_OPC_CheckPredicate, 22, 207, 10, 0, // Skip to: 25344
+/* 22577 */   MCD_OPC_CheckField, 28, 4, 15, 200, 10, 0, // Skip to: 25344
+/* 22584 */   MCD_OPC_CheckField, 0, 1, 0, 193, 10, 0, // Skip to: 25344
+/* 22591 */   MCD_OPC_Decode, 191, 7, 147, 1, // Opcode: MVE_VABSs8
+/* 22596 */   MCD_OPC_FilterValue, 53, 24, 0, 0, // Skip to: 22625
+/* 22601 */   MCD_OPC_CheckPredicate, 22, 178, 10, 0, // Skip to: 25344
+/* 22606 */   MCD_OPC_CheckField, 28, 4, 15, 171, 10, 0, // Skip to: 25344
+/* 22613 */   MCD_OPC_CheckField, 0, 1, 0, 164, 10, 0, // Skip to: 25344
+/* 22620 */   MCD_OPC_Decode, 189, 7, 147, 1, // Opcode: MVE_VABSs16
+/* 22625 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22654
+/* 22630 */   MCD_OPC_CheckPredicate, 24, 149, 10, 0, // Skip to: 25344
+/* 22635 */   MCD_OPC_CheckField, 28, 4, 15, 142, 10, 0, // Skip to: 25344
+/* 22642 */   MCD_OPC_CheckField, 0, 1, 0, 135, 10, 0, // Skip to: 25344
+/* 22649 */   MCD_OPC_Decode, 154, 8, 147, 1, // Opcode: MVE_VCVTs16f16m
+/* 22654 */   MCD_OPC_FilterValue, 57, 24, 0, 0, // Skip to: 22683
+/* 22659 */   MCD_OPC_CheckPredicate, 22, 120, 10, 0, // Skip to: 25344
+/* 22664 */   MCD_OPC_CheckField, 28, 4, 15, 113, 10, 0, // Skip to: 25344
+/* 22671 */   MCD_OPC_CheckField, 0, 1, 0, 106, 10, 0, // Skip to: 25344
+/* 22678 */   MCD_OPC_Decode, 190, 7, 147, 1, // Opcode: MVE_VABSs32
+/* 22683 */   MCD_OPC_FilterValue, 59, 96, 10, 0, // Skip to: 25344
+/* 22688 */   MCD_OPC_CheckPredicate, 24, 91, 10, 0, // Skip to: 25344
+/* 22693 */   MCD_OPC_CheckField, 28, 4, 15, 84, 10, 0, // Skip to: 25344
+/* 22700 */   MCD_OPC_CheckField, 0, 1, 0, 77, 10, 0, // Skip to: 25344
+/* 22707 */   MCD_OPC_Decode, 160, 8, 147, 1, // Opcode: MVE_VCVTs32f32m
+/* 22712 */   MCD_OPC_FilterValue, 15, 148, 0, 0, // Skip to: 22865
+/* 22717 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22720 */   MCD_OPC_FilterValue, 49, 24, 0, 0, // Skip to: 22749
+/* 22725 */   MCD_OPC_CheckPredicate, 22, 54, 10, 0, // Skip to: 25344
+/* 22730 */   MCD_OPC_CheckField, 28, 4, 15, 47, 10, 0, // Skip to: 25344
+/* 22737 */   MCD_OPC_CheckField, 0, 1, 0, 40, 10, 0, // Skip to: 25344
+/* 22744 */   MCD_OPC_Decode, 227, 10, 147, 1, // Opcode: MVE_VNEGs8
+/* 22749 */   MCD_OPC_FilterValue, 53, 24, 0, 0, // Skip to: 22778
+/* 22754 */   MCD_OPC_CheckPredicate, 22, 25, 10, 0, // Skip to: 25344
+/* 22759 */   MCD_OPC_CheckField, 28, 4, 15, 18, 10, 0, // Skip to: 25344
+/* 22766 */   MCD_OPC_CheckField, 0, 1, 0, 11, 10, 0, // Skip to: 25344
+/* 22773 */   MCD_OPC_Decode, 225, 10, 147, 1, // Opcode: MVE_VNEGs16
+/* 22778 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 22807
+/* 22783 */   MCD_OPC_CheckPredicate, 24, 252, 9, 0, // Skip to: 25344
+/* 22788 */   MCD_OPC_CheckField, 28, 4, 15, 245, 9, 0, // Skip to: 25344
+/* 22795 */   MCD_OPC_CheckField, 0, 1, 0, 238, 9, 0, // Skip to: 25344
+/* 22802 */   MCD_OPC_Decode, 166, 8, 147, 1, // Opcode: MVE_VCVTu16f16m
+/* 22807 */   MCD_OPC_FilterValue, 57, 24, 0, 0, // Skip to: 22836
+/* 22812 */   MCD_OPC_CheckPredicate, 22, 223, 9, 0, // Skip to: 25344
+/* 22817 */   MCD_OPC_CheckField, 28, 4, 15, 216, 9, 0, // Skip to: 25344
+/* 22824 */   MCD_OPC_CheckField, 0, 1, 0, 209, 9, 0, // Skip to: 25344
+/* 22831 */   MCD_OPC_Decode, 226, 10, 147, 1, // Opcode: MVE_VNEGs32
+/* 22836 */   MCD_OPC_FilterValue, 59, 199, 9, 0, // Skip to: 25344
+/* 22841 */   MCD_OPC_CheckPredicate, 24, 194, 9, 0, // Skip to: 25344
+/* 22846 */   MCD_OPC_CheckField, 28, 4, 15, 187, 9, 0, // Skip to: 25344
+/* 22853 */   MCD_OPC_CheckField, 0, 1, 0, 180, 9, 0, // Skip to: 25344
+/* 22860 */   MCD_OPC_Decode, 172, 8, 147, 1, // Opcode: MVE_VCVTu32f32m
+/* 22865 */   MCD_OPC_FilterValue, 17, 148, 0, 0, // Skip to: 23018
+/* 22870 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 22873 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 22902
+/* 22878 */   MCD_OPC_CheckPredicate, 22, 157, 9, 0, // Skip to: 25344
+/* 22883 */   MCD_OPC_CheckField, 28, 4, 15, 150, 9, 0, // Skip to: 25344
+/* 22890 */   MCD_OPC_CheckField, 0, 1, 0, 143, 9, 0, // Skip to: 25344
+/* 22897 */   MCD_OPC_Decode, 234, 7, 147, 1, // Opcode: MVE_VCLSs8
+/* 22902 */   MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 22931
+/* 22907 */   MCD_OPC_CheckPredicate, 22, 128, 9, 0, // Skip to: 25344
+/* 22912 */   MCD_OPC_CheckField, 28, 4, 15, 121, 9, 0, // Skip to: 25344
+/* 22919 */   MCD_OPC_CheckField, 0, 1, 0, 114, 9, 0, // Skip to: 25344
+/* 22926 */   MCD_OPC_Decode, 232, 7, 147, 1, // Opcode: MVE_VCLSs16
+/* 22931 */   MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 22960
+/* 22936 */   MCD_OPC_CheckPredicate, 24, 99, 9, 0, // Skip to: 25344
+/* 22941 */   MCD_OPC_CheckField, 28, 4, 15, 92, 9, 0, // Skip to: 25344
+/* 22948 */   MCD_OPC_CheckField, 0, 1, 0, 85, 9, 0, // Skip to: 25344
+/* 22955 */   MCD_OPC_Decode, 170, 12, 147, 1, // Opcode: MVE_VRINTf16N
+/* 22960 */   MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 22989
+/* 22965 */   MCD_OPC_CheckPredicate, 22, 70, 9, 0, // Skip to: 25344
+/* 22970 */   MCD_OPC_CheckField, 28, 4, 15, 63, 9, 0, // Skip to: 25344
+/* 22977 */   MCD_OPC_CheckField, 0, 1, 0, 56, 9, 0, // Skip to: 25344
+/* 22984 */   MCD_OPC_Decode, 233, 7, 147, 1, // Opcode: MVE_VCLSs32
+/* 22989 */   MCD_OPC_FilterValue, 58, 46, 9, 0, // Skip to: 25344
+/* 22994 */   MCD_OPC_CheckPredicate, 24, 41, 9, 0, // Skip to: 25344
+/* 22999 */   MCD_OPC_CheckField, 28, 4, 15, 34, 9, 0, // Skip to: 25344
+/* 23006 */   MCD_OPC_CheckField, 0, 1, 0, 27, 9, 0, // Skip to: 25344
+/* 23013 */   MCD_OPC_Decode, 176, 12, 147, 1, // Opcode: MVE_VRINTf32N
+/* 23018 */   MCD_OPC_FilterValue, 19, 148, 0, 0, // Skip to: 23171
+/* 23023 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23026 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 23055
+/* 23031 */   MCD_OPC_CheckPredicate, 22, 4, 9, 0, // Skip to: 25344
+/* 23036 */   MCD_OPC_CheckField, 28, 4, 15, 253, 8, 0, // Skip to: 25344
+/* 23043 */   MCD_OPC_CheckField, 0, 1, 0, 246, 8, 0, // Skip to: 25344
+/* 23050 */   MCD_OPC_Decode, 237, 7, 147, 1, // Opcode: MVE_VCLZs8
+/* 23055 */   MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 23084
+/* 23060 */   MCD_OPC_CheckPredicate, 22, 231, 8, 0, // Skip to: 25344
+/* 23065 */   MCD_OPC_CheckField, 28, 4, 15, 224, 8, 0, // Skip to: 25344
+/* 23072 */   MCD_OPC_CheckField, 0, 1, 0, 217, 8, 0, // Skip to: 25344
+/* 23079 */   MCD_OPC_Decode, 235, 7, 147, 1, // Opcode: MVE_VCLZs16
+/* 23084 */   MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 23113
+/* 23089 */   MCD_OPC_CheckPredicate, 24, 202, 8, 0, // Skip to: 25344
+/* 23094 */   MCD_OPC_CheckField, 28, 4, 15, 195, 8, 0, // Skip to: 25344
+/* 23101 */   MCD_OPC_CheckField, 0, 1, 0, 188, 8, 0, // Skip to: 25344
+/* 23108 */   MCD_OPC_Decode, 172, 12, 147, 1, // Opcode: MVE_VRINTf16X
+/* 23113 */   MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 23142
+/* 23118 */   MCD_OPC_CheckPredicate, 22, 173, 8, 0, // Skip to: 25344
+/* 23123 */   MCD_OPC_CheckField, 28, 4, 15, 166, 8, 0, // Skip to: 25344
+/* 23130 */   MCD_OPC_CheckField, 0, 1, 0, 159, 8, 0, // Skip to: 25344
+/* 23137 */   MCD_OPC_Decode, 236, 7, 147, 1, // Opcode: MVE_VCLZs32
+/* 23142 */   MCD_OPC_FilterValue, 58, 149, 8, 0, // Skip to: 25344
+/* 23147 */   MCD_OPC_CheckPredicate, 24, 144, 8, 0, // Skip to: 25344
+/* 23152 */   MCD_OPC_CheckField, 28, 4, 15, 137, 8, 0, // Skip to: 25344
+/* 23159 */   MCD_OPC_CheckField, 0, 1, 0, 130, 8, 0, // Skip to: 25344
+/* 23166 */   MCD_OPC_Decode, 178, 12, 147, 1, // Opcode: MVE_VRINTf32X
+/* 23171 */   MCD_OPC_FilterValue, 21, 61, 0, 0, // Skip to: 23237
+/* 23176 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23179 */   MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 23208
+/* 23184 */   MCD_OPC_CheckPredicate, 24, 107, 8, 0, // Skip to: 25344
+/* 23189 */   MCD_OPC_CheckField, 28, 4, 15, 100, 8, 0, // Skip to: 25344
+/* 23196 */   MCD_OPC_CheckField, 0, 1, 0, 93, 8, 0, // Skip to: 25344
+/* 23203 */   MCD_OPC_Decode, 168, 12, 147, 1, // Opcode: MVE_VRINTf16A
+/* 23208 */   MCD_OPC_FilterValue, 58, 83, 8, 0, // Skip to: 25344
+/* 23213 */   MCD_OPC_CheckPredicate, 24, 78, 8, 0, // Skip to: 25344
+/* 23218 */   MCD_OPC_CheckField, 28, 4, 15, 71, 8, 0, // Skip to: 25344
+/* 23225 */   MCD_OPC_CheckField, 0, 1, 0, 64, 8, 0, // Skip to: 25344
+/* 23232 */   MCD_OPC_Decode, 174, 12, 147, 1, // Opcode: MVE_VRINTf32A
+/* 23237 */   MCD_OPC_FilterValue, 23, 90, 0, 0, // Skip to: 23332
+/* 23242 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23245 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 23274
+/* 23250 */   MCD_OPC_CheckPredicate, 22, 41, 8, 0, // Skip to: 25344
+/* 23255 */   MCD_OPC_CheckField, 28, 4, 15, 34, 8, 0, // Skip to: 25344
+/* 23262 */   MCD_OPC_CheckField, 0, 1, 0, 27, 8, 0, // Skip to: 25344
+/* 23269 */   MCD_OPC_Decode, 220, 10, 147, 1, // Opcode: MVE_VMVN
+/* 23274 */   MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 23303
+/* 23279 */   MCD_OPC_CheckPredicate, 24, 12, 8, 0, // Skip to: 25344
+/* 23284 */   MCD_OPC_CheckField, 28, 4, 15, 5, 8, 0, // Skip to: 25344
+/* 23291 */   MCD_OPC_CheckField, 0, 1, 0, 254, 7, 0, // Skip to: 25344
+/* 23298 */   MCD_OPC_Decode, 173, 12, 147, 1, // Opcode: MVE_VRINTf16Z
+/* 23303 */   MCD_OPC_FilterValue, 58, 244, 7, 0, // Skip to: 25344
+/* 23308 */   MCD_OPC_CheckPredicate, 24, 239, 7, 0, // Skip to: 25344
+/* 23313 */   MCD_OPC_CheckField, 28, 4, 15, 232, 7, 0, // Skip to: 25344
+/* 23320 */   MCD_OPC_CheckField, 0, 1, 0, 225, 7, 0, // Skip to: 25344
+/* 23327 */   MCD_OPC_Decode, 179, 12, 147, 1, // Opcode: MVE_VRINTf32Z
+/* 23332 */   MCD_OPC_FilterValue, 25, 61, 0, 0, // Skip to: 23398
+/* 23337 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23340 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 23369
+/* 23345 */   MCD_OPC_CheckPredicate, 24, 202, 7, 0, // Skip to: 25344
+/* 23350 */   MCD_OPC_CheckField, 28, 4, 15, 195, 7, 0, // Skip to: 25344
+/* 23357 */   MCD_OPC_CheckField, 0, 1, 0, 188, 7, 0, // Skip to: 25344
+/* 23364 */   MCD_OPC_Decode, 143, 8, 147, 1, // Opcode: MVE_VCVTf16s16n
+/* 23369 */   MCD_OPC_FilterValue, 59, 178, 7, 0, // Skip to: 25344
+/* 23374 */   MCD_OPC_CheckPredicate, 24, 173, 7, 0, // Skip to: 25344
+/* 23379 */   MCD_OPC_CheckField, 28, 4, 15, 166, 7, 0, // Skip to: 25344
+/* 23386 */   MCD_OPC_CheckField, 0, 1, 0, 159, 7, 0, // Skip to: 25344
+/* 23393 */   MCD_OPC_Decode, 149, 8, 147, 1, // Opcode: MVE_VCVTf32s32n
+/* 23398 */   MCD_OPC_FilterValue, 27, 119, 0, 0, // Skip to: 23522
+/* 23403 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23406 */   MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 23435
+/* 23411 */   MCD_OPC_CheckPredicate, 24, 136, 7, 0, // Skip to: 25344
+/* 23416 */   MCD_OPC_CheckField, 28, 4, 15, 129, 7, 0, // Skip to: 25344
+/* 23423 */   MCD_OPC_CheckField, 0, 1, 0, 122, 7, 0, // Skip to: 25344
+/* 23430 */   MCD_OPC_Decode, 169, 12, 147, 1, // Opcode: MVE_VRINTf16M
+/* 23435 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 23464
+/* 23440 */   MCD_OPC_CheckPredicate, 24, 107, 7, 0, // Skip to: 25344
+/* 23445 */   MCD_OPC_CheckField, 28, 4, 15, 100, 7, 0, // Skip to: 25344
+/* 23452 */   MCD_OPC_CheckField, 0, 1, 0, 93, 7, 0, // Skip to: 25344
+/* 23459 */   MCD_OPC_Decode, 145, 8, 147, 1, // Opcode: MVE_VCVTf16u16n
+/* 23464 */   MCD_OPC_FilterValue, 58, 24, 0, 0, // Skip to: 23493
+/* 23469 */   MCD_OPC_CheckPredicate, 24, 78, 7, 0, // Skip to: 25344
+/* 23474 */   MCD_OPC_CheckField, 28, 4, 15, 71, 7, 0, // Skip to: 25344
+/* 23481 */   MCD_OPC_CheckField, 0, 1, 0, 64, 7, 0, // Skip to: 25344
+/* 23488 */   MCD_OPC_Decode, 175, 12, 147, 1, // Opcode: MVE_VRINTf32M
+/* 23493 */   MCD_OPC_FilterValue, 59, 54, 7, 0, // Skip to: 25344
+/* 23498 */   MCD_OPC_CheckPredicate, 24, 49, 7, 0, // Skip to: 25344
+/* 23503 */   MCD_OPC_CheckField, 28, 4, 15, 42, 7, 0, // Skip to: 25344
+/* 23510 */   MCD_OPC_CheckField, 0, 1, 0, 35, 7, 0, // Skip to: 25344
+/* 23517 */   MCD_OPC_Decode, 151, 8, 147, 1, // Opcode: MVE_VCVTf32u32n
+/* 23522 */   MCD_OPC_FilterValue, 29, 206, 0, 0, // Skip to: 23733
+/* 23527 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23530 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 23559
+/* 23535 */   MCD_OPC_CheckPredicate, 22, 12, 7, 0, // Skip to: 25344
+/* 23540 */   MCD_OPC_CheckField, 28, 4, 15, 5, 7, 0, // Skip to: 25344
+/* 23547 */   MCD_OPC_CheckField, 0, 1, 0, 254, 6, 0, // Skip to: 25344
+/* 23554 */   MCD_OPC_Decode, 131, 11, 147, 1, // Opcode: MVE_VQABSs8
+/* 23559 */   MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 23588
+/* 23564 */   MCD_OPC_CheckPredicate, 22, 239, 6, 0, // Skip to: 25344
+/* 23569 */   MCD_OPC_CheckField, 28, 4, 15, 232, 6, 0, // Skip to: 25344
+/* 23576 */   MCD_OPC_CheckField, 0, 1, 0, 225, 6, 0, // Skip to: 25344
+/* 23583 */   MCD_OPC_Decode, 129, 11, 147, 1, // Opcode: MVE_VQABSs16
+/* 23588 */   MCD_OPC_FilterValue, 53, 24, 0, 0, // Skip to: 23617
+/* 23593 */   MCD_OPC_CheckPredicate, 24, 210, 6, 0, // Skip to: 25344
+/* 23598 */   MCD_OPC_CheckField, 28, 4, 15, 203, 6, 0, // Skip to: 25344
+/* 23605 */   MCD_OPC_CheckField, 0, 1, 0, 196, 6, 0, // Skip to: 25344
+/* 23612 */   MCD_OPC_Decode, 187, 7, 147, 1, // Opcode: MVE_VABSf16
+/* 23617 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 23646
+/* 23622 */   MCD_OPC_CheckPredicate, 24, 181, 6, 0, // Skip to: 25344
+/* 23627 */   MCD_OPC_CheckField, 28, 4, 15, 174, 6, 0, // Skip to: 25344
+/* 23634 */   MCD_OPC_CheckField, 0, 1, 0, 167, 6, 0, // Skip to: 25344
+/* 23641 */   MCD_OPC_Decode, 157, 8, 147, 1, // Opcode: MVE_VCVTs16f16z
+/* 23646 */   MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 23675
+/* 23651 */   MCD_OPC_CheckPredicate, 22, 152, 6, 0, // Skip to: 25344
+/* 23656 */   MCD_OPC_CheckField, 28, 4, 15, 145, 6, 0, // Skip to: 25344
+/* 23663 */   MCD_OPC_CheckField, 0, 1, 0, 138, 6, 0, // Skip to: 25344
+/* 23670 */   MCD_OPC_Decode, 130, 11, 147, 1, // Opcode: MVE_VQABSs32
+/* 23675 */   MCD_OPC_FilterValue, 57, 24, 0, 0, // Skip to: 23704
+/* 23680 */   MCD_OPC_CheckPredicate, 24, 123, 6, 0, // Skip to: 25344
+/* 23685 */   MCD_OPC_CheckField, 28, 4, 15, 116, 6, 0, // Skip to: 25344
+/* 23692 */   MCD_OPC_CheckField, 0, 1, 0, 109, 6, 0, // Skip to: 25344
+/* 23699 */   MCD_OPC_Decode, 188, 7, 147, 1, // Opcode: MVE_VABSf32
+/* 23704 */   MCD_OPC_FilterValue, 59, 99, 6, 0, // Skip to: 25344
+/* 23709 */   MCD_OPC_CheckPredicate, 24, 94, 6, 0, // Skip to: 25344
+/* 23714 */   MCD_OPC_CheckField, 28, 4, 15, 87, 6, 0, // Skip to: 25344
+/* 23721 */   MCD_OPC_CheckField, 0, 1, 0, 80, 6, 0, // Skip to: 25344
+/* 23728 */   MCD_OPC_Decode, 163, 8, 147, 1, // Opcode: MVE_VCVTs32f32z
+/* 23733 */   MCD_OPC_FilterValue, 31, 70, 6, 0, // Skip to: 25344
+/* 23738 */   MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 23741 */   MCD_OPC_FilterValue, 48, 24, 0, 0, // Skip to: 23770
+/* 23746 */   MCD_OPC_CheckPredicate, 22, 57, 6, 0, // Skip to: 25344
+/* 23751 */   MCD_OPC_CheckField, 28, 4, 15, 50, 6, 0, // Skip to: 25344
+/* 23758 */   MCD_OPC_CheckField, 0, 1, 0, 43, 6, 0, // Skip to: 25344
+/* 23765 */   MCD_OPC_Decode, 190, 11, 147, 1, // Opcode: MVE_VQNEGs8
+/* 23770 */   MCD_OPC_FilterValue, 52, 24, 0, 0, // Skip to: 23799
+/* 23775 */   MCD_OPC_CheckPredicate, 22, 28, 6, 0, // Skip to: 25344
+/* 23780 */   MCD_OPC_CheckField, 28, 4, 15, 21, 6, 0, // Skip to: 25344
+/* 23787 */   MCD_OPC_CheckField, 0, 1, 0, 14, 6, 0, // Skip to: 25344
+/* 23794 */   MCD_OPC_Decode, 188, 11, 147, 1, // Opcode: MVE_VQNEGs16
+/* 23799 */   MCD_OPC_FilterValue, 53, 24, 0, 0, // Skip to: 23828
+/* 23804 */   MCD_OPC_CheckPredicate, 24, 255, 5, 0, // Skip to: 25344
+/* 23809 */   MCD_OPC_CheckField, 28, 4, 15, 248, 5, 0, // Skip to: 25344
+/* 23816 */   MCD_OPC_CheckField, 0, 1, 0, 241, 5, 0, // Skip to: 25344
+/* 23823 */   MCD_OPC_Decode, 223, 10, 147, 1, // Opcode: MVE_VNEGf16
+/* 23828 */   MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 23857
+/* 23833 */   MCD_OPC_CheckPredicate, 24, 226, 5, 0, // Skip to: 25344
+/* 23838 */   MCD_OPC_CheckField, 28, 4, 15, 219, 5, 0, // Skip to: 25344
+/* 23845 */   MCD_OPC_CheckField, 0, 1, 0, 212, 5, 0, // Skip to: 25344
+/* 23852 */   MCD_OPC_Decode, 171, 12, 147, 1, // Opcode: MVE_VRINTf16P
+/* 23857 */   MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 23886
+/* 23862 */   MCD_OPC_CheckPredicate, 24, 197, 5, 0, // Skip to: 25344
+/* 23867 */   MCD_OPC_CheckField, 28, 4, 15, 190, 5, 0, // Skip to: 25344
+/* 23874 */   MCD_OPC_CheckField, 0, 1, 0, 183, 5, 0, // Skip to: 25344
+/* 23881 */   MCD_OPC_Decode, 169, 8, 147, 1, // Opcode: MVE_VCVTu16f16z
+/* 23886 */   MCD_OPC_FilterValue, 56, 24, 0, 0, // Skip to: 23915
+/* 23891 */   MCD_OPC_CheckPredicate, 22, 168, 5, 0, // Skip to: 25344
+/* 23896 */   MCD_OPC_CheckField, 28, 4, 15, 161, 5, 0, // Skip to: 25344
+/* 23903 */   MCD_OPC_CheckField, 0, 1, 0, 154, 5, 0, // Skip to: 25344
+/* 23910 */   MCD_OPC_Decode, 189, 11, 147, 1, // Opcode: MVE_VQNEGs32
+/* 23915 */   MCD_OPC_FilterValue, 57, 24, 0, 0, // Skip to: 23944
+/* 23920 */   MCD_OPC_CheckPredicate, 24, 139, 5, 0, // Skip to: 25344
+/* 23925 */   MCD_OPC_CheckField, 28, 4, 15, 132, 5, 0, // Skip to: 25344
+/* 23932 */   MCD_OPC_CheckField, 0, 1, 0, 125, 5, 0, // Skip to: 25344
+/* 23939 */   MCD_OPC_Decode, 224, 10, 147, 1, // Opcode: MVE_VNEGf32
+/* 23944 */   MCD_OPC_FilterValue, 58, 24, 0, 0, // Skip to: 23973
+/* 23949 */   MCD_OPC_CheckPredicate, 24, 110, 5, 0, // Skip to: 25344
+/* 23954 */   MCD_OPC_CheckField, 28, 4, 15, 103, 5, 0, // Skip to: 25344
+/* 23961 */   MCD_OPC_CheckField, 0, 1, 0, 96, 5, 0, // Skip to: 25344
+/* 23968 */   MCD_OPC_Decode, 177, 12, 147, 1, // Opcode: MVE_VRINTf32P
+/* 23973 */   MCD_OPC_FilterValue, 59, 86, 5, 0, // Skip to: 25344
+/* 23978 */   MCD_OPC_CheckPredicate, 24, 81, 5, 0, // Skip to: 25344
+/* 23983 */   MCD_OPC_CheckField, 28, 4, 15, 74, 5, 0, // Skip to: 25344
+/* 23990 */   MCD_OPC_CheckField, 0, 1, 0, 67, 5, 0, // Skip to: 25344
+/* 23997 */   MCD_OPC_Decode, 175, 8, 147, 1, // Opcode: MVE_VCVTu32f32z
+/* 24002 */   MCD_OPC_FilterValue, 1, 57, 5, 0, // Skip to: 25344
+/* 24007 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 24010 */   MCD_OPC_FilterValue, 0, 51, 3, 0, // Skip to: 24834
+/* 24015 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 24018 */   MCD_OPC_FilterValue, 0, 25, 2, 0, // Skip to: 24560
+/* 24023 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 24026 */   MCD_OPC_FilterValue, 0, 255, 0, 0, // Skip to: 24286
+/* 24031 */   MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
+/* 24034 */   MCD_OPC_FilterValue, 2, 129, 0, 0, // Skip to: 24168
+/* 24039 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 24042 */   MCD_OPC_FilterValue, 0, 17, 5, 0, // Skip to: 25344
+/* 24047 */   MCD_OPC_ExtractField, 29, 3,  // Inst{31-29} ...
+/* 24050 */   MCD_OPC_FilterValue, 7, 9, 5, 0, // Skip to: 25344
+/* 24055 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 24058 */   MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 24073
+/* 24063 */   MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 24088
+/* 24068 */   MCD_OPC_Decode, 187, 10, 190, 1, // Opcode: MVE_VMOVimmi8
+/* 24073 */   MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 24088
+/* 24078 */   MCD_OPC_CheckPredicate, 22, 5, 0, 0, // Skip to: 24088
+/* 24083 */   MCD_OPC_Decode, 183, 10, 190, 1, // Opcode: MVE_VMOVimmf32
+/* 24088 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 24091 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 24113
+/* 24096 */   MCD_OPC_CheckPredicate, 22, 57, 0, 0, // Skip to: 24158
+/* 24101 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 24158
+/* 24108 */   MCD_OPC_Decode, 184, 10, 190, 1, // Opcode: MVE_VMOVimmi16
+/* 24113 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 24158
+/* 24118 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 24121 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24136
+/* 24126 */   MCD_OPC_CheckPredicate, 22, 27, 0, 0, // Skip to: 24158
+/* 24131 */   MCD_OPC_Decode, 231, 10, 191, 1, // Opcode: MVE_VORRimmi32
+/* 24136 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24158
+/* 24141 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 24158
+/* 24146 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 24158
+/* 24153 */   MCD_OPC_Decode, 230, 10, 192, 1, // Opcode: MVE_VORRimmi16
+/* 24158 */   MCD_OPC_CheckPredicate, 22, 157, 4, 0, // Skip to: 25344
+/* 24163 */   MCD_OPC_Decode, 185, 10, 190, 1, // Opcode: MVE_VMOVimmi32
+/* 24168 */   MCD_OPC_FilterValue, 3, 147, 4, 0, // Skip to: 25344
+/* 24173 */   MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 24176 */   MCD_OPC_FilterValue, 0, 139, 4, 0, // Skip to: 25344
+/* 24181 */   MCD_OPC_ExtractField, 29, 3,  // Inst{31-29} ...
+/* 24184 */   MCD_OPC_FilterValue, 7, 131, 4, 0, // Skip to: 25344
+/* 24189 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 24206
+/* 24194 */   MCD_OPC_CheckField, 8, 4, 14, 5, 0, 0, // Skip to: 24206
+/* 24201 */   MCD_OPC_Decode, 186, 10, 190, 1, // Opcode: MVE_VMOVimmi64
+/* 24206 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 24209 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 24231
+/* 24214 */   MCD_OPC_CheckPredicate, 22, 57, 0, 0, // Skip to: 24276
+/* 24219 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 24276
+/* 24226 */   MCD_OPC_Decode, 221, 10, 190, 1, // Opcode: MVE_VMVNimmi16
+/* 24231 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 24276
+/* 24236 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 24239 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24254
+/* 24244 */   MCD_OPC_CheckPredicate, 22, 27, 0, 0, // Skip to: 24276
+/* 24249 */   MCD_OPC_Decode, 223, 7, 191, 1, // Opcode: MVE_VBICimmi32
+/* 24254 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24276
+/* 24259 */   MCD_OPC_CheckPredicate, 22, 12, 0, 0, // Skip to: 24276
+/* 24264 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 24276
+/* 24271 */   MCD_OPC_Decode, 222, 7, 192, 1, // Opcode: MVE_VBICimmi16
+/* 24276 */   MCD_OPC_CheckPredicate, 22, 39, 4, 0, // Skip to: 25344
+/* 24281 */   MCD_OPC_Decode, 222, 10, 190, 1, // Opcode: MVE_VMVNimmi32
+/* 24286 */   MCD_OPC_FilterValue, 1, 29, 4, 0, // Skip to: 25344
+/* 24291 */   MCD_OPC_ExtractField, 6, 7,  // Inst{12-6} ...
+/* 24294 */   MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 24346
+/* 24299 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24302 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24324
+/* 24307 */   MCD_OPC_CheckPredicate, 22, 8, 4, 0, // Skip to: 25344
+/* 24312 */   MCD_OPC_CheckField, 0, 1, 0, 1, 4, 0, // Skip to: 25344
+/* 24319 */   MCD_OPC_Decode, 130, 13, 193, 1, // Opcode: MVE_VSHR_imms8
+/* 24324 */   MCD_OPC_FilterValue, 15, 247, 3, 0, // Skip to: 25344
+/* 24329 */   MCD_OPC_CheckPredicate, 22, 242, 3, 0, // Skip to: 25344
+/* 24334 */   MCD_OPC_CheckField, 0, 1, 0, 235, 3, 0, // Skip to: 25344
+/* 24341 */   MCD_OPC_Decode, 133, 13, 193, 1, // Opcode: MVE_VSHR_immu8
+/* 24346 */   MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 24398
+/* 24351 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24354 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24376
+/* 24359 */   MCD_OPC_CheckPredicate, 22, 212, 3, 0, // Skip to: 25344
+/* 24364 */   MCD_OPC_CheckField, 0, 1, 0, 205, 3, 0, // Skip to: 25344
+/* 24371 */   MCD_OPC_Decode, 214, 12, 193, 1, // Opcode: MVE_VRSHR_imms8
+/* 24376 */   MCD_OPC_FilterValue, 15, 195, 3, 0, // Skip to: 25344
+/* 24381 */   MCD_OPC_CheckPredicate, 22, 190, 3, 0, // Skip to: 25344
+/* 24386 */   MCD_OPC_CheckField, 0, 1, 0, 183, 3, 0, // Skip to: 25344
+/* 24393 */   MCD_OPC_Decode, 217, 12, 193, 1, // Opcode: MVE_VRSHR_immu8
+/* 24398 */   MCD_OPC_FilterValue, 17, 24, 0, 0, // Skip to: 24427
+/* 24403 */   MCD_OPC_CheckPredicate, 22, 168, 3, 0, // Skip to: 25344
+/* 24408 */   MCD_OPC_CheckField, 28, 4, 15, 161, 3, 0, // Skip to: 25344
+/* 24415 */   MCD_OPC_CheckField, 0, 1, 0, 154, 3, 0, // Skip to: 25344
+/* 24422 */   MCD_OPC_Decode, 139, 13, 184, 1, // Opcode: MVE_VSRIimm8
+/* 24427 */   MCD_OPC_FilterValue, 21, 47, 0, 0, // Skip to: 24479
+/* 24432 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24435 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24457
+/* 24440 */   MCD_OPC_CheckPredicate, 22, 131, 3, 0, // Skip to: 25344
+/* 24445 */   MCD_OPC_CheckField, 0, 1, 0, 124, 3, 0, // Skip to: 25344
+/* 24452 */   MCD_OPC_Decode, 245, 12, 186, 1, // Opcode: MVE_VSHL_immi8
+/* 24457 */   MCD_OPC_FilterValue, 15, 114, 3, 0, // Skip to: 25344
+/* 24462 */   MCD_OPC_CheckPredicate, 22, 109, 3, 0, // Skip to: 25344
+/* 24467 */   MCD_OPC_CheckField, 0, 1, 0, 102, 3, 0, // Skip to: 25344
+/* 24474 */   MCD_OPC_Decode, 136, 13, 194, 1, // Opcode: MVE_VSLIimm8
+/* 24479 */   MCD_OPC_FilterValue, 25, 24, 0, 0, // Skip to: 24508
+/* 24484 */   MCD_OPC_CheckPredicate, 22, 87, 3, 0, // Skip to: 25344
+/* 24489 */   MCD_OPC_CheckField, 28, 4, 15, 80, 3, 0, // Skip to: 25344
+/* 24496 */   MCD_OPC_CheckField, 0, 1, 0, 73, 3, 0, // Skip to: 25344
+/* 24503 */   MCD_OPC_Decode, 241, 11, 186, 1, // Opcode: MVE_VQSHLU_imms8
+/* 24508 */   MCD_OPC_FilterValue, 29, 63, 3, 0, // Skip to: 25344
+/* 24513 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24516 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24538
+/* 24521 */   MCD_OPC_CheckPredicate, 22, 50, 3, 0, // Skip to: 25344
+/* 24526 */   MCD_OPC_CheckField, 0, 1, 0, 43, 3, 0, // Skip to: 25344
+/* 24533 */   MCD_OPC_Decode, 128, 12, 186, 1, // Opcode: MVE_VQSHLimms8
+/* 24538 */   MCD_OPC_FilterValue, 15, 33, 3, 0, // Skip to: 25344
+/* 24543 */   MCD_OPC_CheckPredicate, 22, 28, 3, 0, // Skip to: 25344
+/* 24548 */   MCD_OPC_CheckField, 0, 1, 0, 21, 3, 0, // Skip to: 25344
+/* 24555 */   MCD_OPC_Decode, 131, 12, 186, 1, // Opcode: MVE_VQSHLimmu8
+/* 24560 */   MCD_OPC_FilterValue, 1, 11, 3, 0, // Skip to: 25344
+/* 24565 */   MCD_OPC_ExtractField, 6, 7,  // Inst{12-6} ...
+/* 24568 */   MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 24620
+/* 24573 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24576 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24598
+/* 24581 */   MCD_OPC_CheckPredicate, 22, 246, 2, 0, // Skip to: 25344
+/* 24586 */   MCD_OPC_CheckField, 0, 1, 0, 239, 2, 0, // Skip to: 25344
+/* 24593 */   MCD_OPC_Decode, 128, 13, 195, 1, // Opcode: MVE_VSHR_imms16
+/* 24598 */   MCD_OPC_FilterValue, 15, 229, 2, 0, // Skip to: 25344
+/* 24603 */   MCD_OPC_CheckPredicate, 22, 224, 2, 0, // Skip to: 25344
+/* 24608 */   MCD_OPC_CheckField, 0, 1, 0, 217, 2, 0, // Skip to: 25344
+/* 24615 */   MCD_OPC_Decode, 131, 13, 195, 1, // Opcode: MVE_VSHR_immu16
+/* 24620 */   MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 24672
+/* 24625 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24628 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24650
+/* 24633 */   MCD_OPC_CheckPredicate, 22, 194, 2, 0, // Skip to: 25344
+/* 24638 */   MCD_OPC_CheckField, 0, 1, 0, 187, 2, 0, // Skip to: 25344
+/* 24645 */   MCD_OPC_Decode, 212, 12, 195, 1, // Opcode: MVE_VRSHR_imms16
+/* 24650 */   MCD_OPC_FilterValue, 15, 177, 2, 0, // Skip to: 25344
+/* 24655 */   MCD_OPC_CheckPredicate, 22, 172, 2, 0, // Skip to: 25344
+/* 24660 */   MCD_OPC_CheckField, 0, 1, 0, 165, 2, 0, // Skip to: 25344
+/* 24667 */   MCD_OPC_Decode, 215, 12, 195, 1, // Opcode: MVE_VRSHR_immu16
+/* 24672 */   MCD_OPC_FilterValue, 17, 24, 0, 0, // Skip to: 24701
+/* 24677 */   MCD_OPC_CheckPredicate, 22, 150, 2, 0, // Skip to: 25344
+/* 24682 */   MCD_OPC_CheckField, 28, 4, 15, 143, 2, 0, // Skip to: 25344
+/* 24689 */   MCD_OPC_CheckField, 0, 1, 0, 136, 2, 0, // Skip to: 25344
+/* 24696 */   MCD_OPC_Decode, 137, 13, 185, 1, // Opcode: MVE_VSRIimm16
+/* 24701 */   MCD_OPC_FilterValue, 21, 47, 0, 0, // Skip to: 24753
+/* 24706 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24709 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24731
+/* 24714 */   MCD_OPC_CheckPredicate, 22, 113, 2, 0, // Skip to: 25344
+/* 24719 */   MCD_OPC_CheckField, 0, 1, 0, 106, 2, 0, // Skip to: 25344
+/* 24726 */   MCD_OPC_Decode, 243, 12, 187, 1, // Opcode: MVE_VSHL_immi16
+/* 24731 */   MCD_OPC_FilterValue, 15, 96, 2, 0, // Skip to: 25344
+/* 24736 */   MCD_OPC_CheckPredicate, 22, 91, 2, 0, // Skip to: 25344
+/* 24741 */   MCD_OPC_CheckField, 0, 1, 0, 84, 2, 0, // Skip to: 25344
+/* 24748 */   MCD_OPC_Decode, 134, 13, 196, 1, // Opcode: MVE_VSLIimm16
+/* 24753 */   MCD_OPC_FilterValue, 25, 24, 0, 0, // Skip to: 24782
+/* 24758 */   MCD_OPC_CheckPredicate, 22, 69, 2, 0, // Skip to: 25344
+/* 24763 */   MCD_OPC_CheckField, 28, 4, 15, 62, 2, 0, // Skip to: 25344
+/* 24770 */   MCD_OPC_CheckField, 0, 1, 0, 55, 2, 0, // Skip to: 25344
+/* 24777 */   MCD_OPC_Decode, 239, 11, 187, 1, // Opcode: MVE_VQSHLU_imms16
+/* 24782 */   MCD_OPC_FilterValue, 29, 45, 2, 0, // Skip to: 25344
+/* 24787 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24790 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24812
+/* 24795 */   MCD_OPC_CheckPredicate, 22, 32, 2, 0, // Skip to: 25344
+/* 24800 */   MCD_OPC_CheckField, 0, 1, 0, 25, 2, 0, // Skip to: 25344
+/* 24807 */   MCD_OPC_Decode, 254, 11, 187, 1, // Opcode: MVE_VQSHLimms16
+/* 24812 */   MCD_OPC_FilterValue, 15, 15, 2, 0, // Skip to: 25344
+/* 24817 */   MCD_OPC_CheckPredicate, 22, 10, 2, 0, // Skip to: 25344
+/* 24822 */   MCD_OPC_CheckField, 0, 1, 0, 3, 2, 0, // Skip to: 25344
+/* 24829 */   MCD_OPC_Decode, 129, 12, 187, 1, // Opcode: MVE_VQSHLimmu16
+/* 24834 */   MCD_OPC_FilterValue, 1, 249, 1, 0, // Skip to: 25344
+/* 24839 */   MCD_OPC_ExtractField, 6, 7,  // Inst{12-6} ...
+/* 24842 */   MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 24894
+/* 24847 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24850 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24872
+/* 24855 */   MCD_OPC_CheckPredicate, 22, 228, 1, 0, // Skip to: 25344
+/* 24860 */   MCD_OPC_CheckField, 0, 1, 0, 221, 1, 0, // Skip to: 25344
+/* 24867 */   MCD_OPC_Decode, 129, 13, 197, 1, // Opcode: MVE_VSHR_imms32
+/* 24872 */   MCD_OPC_FilterValue, 15, 211, 1, 0, // Skip to: 25344
+/* 24877 */   MCD_OPC_CheckPredicate, 22, 206, 1, 0, // Skip to: 25344
+/* 24882 */   MCD_OPC_CheckField, 0, 1, 0, 199, 1, 0, // Skip to: 25344
+/* 24889 */   MCD_OPC_Decode, 132, 13, 197, 1, // Opcode: MVE_VSHR_immu32
+/* 24894 */   MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 24946
+/* 24899 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24902 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 24924
+/* 24907 */   MCD_OPC_CheckPredicate, 22, 176, 1, 0, // Skip to: 25344
+/* 24912 */   MCD_OPC_CheckField, 0, 1, 0, 169, 1, 0, // Skip to: 25344
+/* 24919 */   MCD_OPC_Decode, 213, 12, 197, 1, // Opcode: MVE_VRSHR_imms32
+/* 24924 */   MCD_OPC_FilterValue, 15, 159, 1, 0, // Skip to: 25344
+/* 24929 */   MCD_OPC_CheckPredicate, 22, 154, 1, 0, // Skip to: 25344
+/* 24934 */   MCD_OPC_CheckField, 0, 1, 0, 147, 1, 0, // Skip to: 25344
+/* 24941 */   MCD_OPC_Decode, 216, 12, 197, 1, // Opcode: MVE_VRSHR_immu32
+/* 24946 */   MCD_OPC_FilterValue, 17, 24, 0, 0, // Skip to: 24975
+/* 24951 */   MCD_OPC_CheckPredicate, 22, 132, 1, 0, // Skip to: 25344
+/* 24956 */   MCD_OPC_CheckField, 28, 4, 15, 125, 1, 0, // Skip to: 25344
+/* 24963 */   MCD_OPC_CheckField, 0, 1, 0, 118, 1, 0, // Skip to: 25344
+/* 24970 */   MCD_OPC_Decode, 138, 13, 198, 1, // Opcode: MVE_VSRIimm32
+/* 24975 */   MCD_OPC_FilterValue, 21, 47, 0, 0, // Skip to: 25027
+/* 24980 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 24983 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 25005
+/* 24988 */   MCD_OPC_CheckPredicate, 22, 95, 1, 0, // Skip to: 25344
+/* 24993 */   MCD_OPC_CheckField, 0, 1, 0, 88, 1, 0, // Skip to: 25344
+/* 25000 */   MCD_OPC_Decode, 244, 12, 199, 1, // Opcode: MVE_VSHL_immi32
+/* 25005 */   MCD_OPC_FilterValue, 15, 78, 1, 0, // Skip to: 25344
+/* 25010 */   MCD_OPC_CheckPredicate, 22, 73, 1, 0, // Skip to: 25344
+/* 25015 */   MCD_OPC_CheckField, 0, 1, 0, 66, 1, 0, // Skip to: 25344
+/* 25022 */   MCD_OPC_Decode, 135, 13, 200, 1, // Opcode: MVE_VSLIimm32
+/* 25027 */   MCD_OPC_FilterValue, 25, 24, 0, 0, // Skip to: 25056
+/* 25032 */   MCD_OPC_CheckPredicate, 22, 51, 1, 0, // Skip to: 25344
+/* 25037 */   MCD_OPC_CheckField, 28, 4, 15, 44, 1, 0, // Skip to: 25344
+/* 25044 */   MCD_OPC_CheckField, 0, 1, 0, 37, 1, 0, // Skip to: 25344
+/* 25051 */   MCD_OPC_Decode, 240, 11, 199, 1, // Opcode: MVE_VQSHLU_imms32
+/* 25056 */   MCD_OPC_FilterValue, 29, 47, 0, 0, // Skip to: 25108
+/* 25061 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 25064 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 25086
+/* 25069 */   MCD_OPC_CheckPredicate, 22, 14, 1, 0, // Skip to: 25344
+/* 25074 */   MCD_OPC_CheckField, 0, 1, 0, 7, 1, 0, // Skip to: 25344
+/* 25081 */   MCD_OPC_Decode, 255, 11, 199, 1, // Opcode: MVE_VQSHLimms32
+/* 25086 */   MCD_OPC_FilterValue, 15, 253, 0, 0, // Skip to: 25344
+/* 25091 */   MCD_OPC_CheckPredicate, 22, 248, 0, 0, // Skip to: 25344
+/* 25096 */   MCD_OPC_CheckField, 0, 1, 0, 241, 0, 0, // Skip to: 25344
+/* 25103 */   MCD_OPC_Decode, 130, 12, 199, 1, // Opcode: MVE_VQSHLimmu32
+/* 25108 */   MCD_OPC_FilterValue, 49, 61, 0, 0, // Skip to: 25174
+/* 25113 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 25116 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 25145
+/* 25121 */   MCD_OPC_CheckPredicate, 24, 218, 0, 0, // Skip to: 25344
+/* 25126 */   MCD_OPC_CheckField, 20, 1, 1, 211, 0, 0, // Skip to: 25344
+/* 25133 */   MCD_OPC_CheckField, 0, 1, 0, 204, 0, 0, // Skip to: 25344
+/* 25140 */   MCD_OPC_Decode, 142, 8, 201, 1, // Opcode: MVE_VCVTf16s16_fix
+/* 25145 */   MCD_OPC_FilterValue, 15, 194, 0, 0, // Skip to: 25344
+/* 25150 */   MCD_OPC_CheckPredicate, 24, 189, 0, 0, // Skip to: 25344
+/* 25155 */   MCD_OPC_CheckField, 20, 1, 1, 182, 0, 0, // Skip to: 25344
+/* 25162 */   MCD_OPC_CheckField, 0, 1, 0, 175, 0, 0, // Skip to: 25344
+/* 25169 */   MCD_OPC_Decode, 144, 8, 201, 1, // Opcode: MVE_VCVTf16u16_fix
+/* 25174 */   MCD_OPC_FilterValue, 53, 61, 0, 0, // Skip to: 25240
+/* 25179 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 25182 */   MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 25211
+/* 25187 */   MCD_OPC_CheckPredicate, 24, 152, 0, 0, // Skip to: 25344
+/* 25192 */   MCD_OPC_CheckField, 20, 1, 1, 145, 0, 0, // Skip to: 25344
+/* 25199 */   MCD_OPC_CheckField, 0, 1, 0, 138, 0, 0, // Skip to: 25344
+/* 25206 */   MCD_OPC_Decode, 152, 8, 201, 1, // Opcode: MVE_VCVTs16f16_fix
+/* 25211 */   MCD_OPC_FilterValue, 15, 128, 0, 0, // Skip to: 25344
+/* 25216 */   MCD_OPC_CheckPredicate, 24, 123, 0, 0, // Skip to: 25344
+/* 25221 */   MCD_OPC_CheckField, 20, 1, 1, 116, 0, 0, // Skip to: 25344
+/* 25228 */   MCD_OPC_CheckField, 0, 1, 0, 109, 0, 0, // Skip to: 25344
+/* 25235 */   MCD_OPC_Decode, 164, 8, 201, 1, // Opcode: MVE_VCVTu16f16_fix
+/* 25240 */   MCD_OPC_FilterValue, 57, 47, 0, 0, // Skip to: 25292
+/* 25245 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 25248 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 25270
+/* 25253 */   MCD_OPC_CheckPredicate, 24, 86, 0, 0, // Skip to: 25344
+/* 25258 */   MCD_OPC_CheckField, 0, 1, 0, 79, 0, 0, // Skip to: 25344
+/* 25265 */   MCD_OPC_Decode, 148, 8, 201, 1, // Opcode: MVE_VCVTf32s32_fix
+/* 25270 */   MCD_OPC_FilterValue, 15, 69, 0, 0, // Skip to: 25344
+/* 25275 */   MCD_OPC_CheckPredicate, 24, 64, 0, 0, // Skip to: 25344
+/* 25280 */   MCD_OPC_CheckField, 0, 1, 0, 57, 0, 0, // Skip to: 25344
+/* 25287 */   MCD_OPC_Decode, 150, 8, 201, 1, // Opcode: MVE_VCVTf32u32_fix
+/* 25292 */   MCD_OPC_FilterValue, 61, 47, 0, 0, // Skip to: 25344
+/* 25297 */   MCD_OPC_ExtractField, 28, 4,  // Inst{31-28} ...
+/* 25300 */   MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 25322
+/* 25305 */   MCD_OPC_CheckPredicate, 24, 34, 0, 0, // Skip to: 25344
+/* 25310 */   MCD_OPC_CheckField, 0, 1, 0, 27, 0, 0, // Skip to: 25344
+/* 25317 */   MCD_OPC_Decode, 158, 8, 201, 1, // Opcode: MVE_VCVTs32f32_fix
+/* 25322 */   MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 25344
+/* 25327 */   MCD_OPC_CheckPredicate, 24, 12, 0, 0, // Skip to: 25344
+/* 25332 */   MCD_OPC_CheckField, 0, 1, 0, 5, 0, 0, // Skip to: 25344
+/* 25339 */   MCD_OPC_Decode, 170, 8, 201, 1, // Opcode: MVE_VCVTu32f32_fix
+/* 25344 */   MCD_OPC_Fail,
+  0
+};
+
 static const uint8_t DecoderTableNEONData32[] = {
 /* 0 */       MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 3 */       MCD_OPC_FilterValue, 0, 221, 39, 0, // Skip to: 10213
+/* 3 */       MCD_OPC_FilterValue, 0, 198, 41, 0, // Skip to: 10702
 /* 8 */       MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11 */      MCD_OPC_FilterValue, 0, 73, 6, 0, // Skip to: 1625
+/* 11 */      MCD_OPC_FilterValue, 0, 148, 6, 0, // Skip to: 1700
 /* 16 */      MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 19 */      MCD_OPC_FilterValue, 0, 121, 0, 0, // Skip to: 145
+/* 19 */      MCD_OPC_FilterValue, 0, 127, 0, 0, // Skip to: 151
 /* 24 */      MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 27 */      MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 64
+/* 27 */      MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 66
 /* 33 */      MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 36 */      MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 50
-/* 41 */      MCD_OPC_CheckPredicate, 21, 75, 72, 0, // Skip to: 18553
-/* 46 */      MCD_OPC_Decode, 179, 10, 97, // Opcode: VHADDsv8i8
-/* 50 */      MCD_OPC_FilterValue, 1, 66, 72, 0, // Skip to: 18553
-/* 55 */      MCD_OPC_CheckPredicate, 21, 61, 72, 0, // Skip to: 18553
-/* 60 */      MCD_OPC_Decode, 174, 10, 98, // Opcode: VHADDsv16i8
-/* 64 */      MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 86
-/* 70 */      MCD_OPC_CheckPredicate, 21, 46, 72, 0, // Skip to: 18553
-/* 75 */      MCD_OPC_CheckField, 6, 1, 0, 39, 72, 0, // Skip to: 18553
-/* 82 */      MCD_OPC_Decode, 242, 7, 99, // Opcode: VADDLsv8i16
-/* 86 */      MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 123
-/* 92 */      MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 95 */      MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 109
-/* 100 */     MCD_OPC_CheckPredicate, 21, 16, 72, 0, // Skip to: 18553
-/* 105 */     MCD_OPC_Decode, 185, 10, 97, // Opcode: VHADDuv8i8
-/* 109 */     MCD_OPC_FilterValue, 1, 7, 72, 0, // Skip to: 18553
-/* 114 */     MCD_OPC_CheckPredicate, 21, 2, 72, 0, // Skip to: 18553
-/* 119 */     MCD_OPC_Decode, 180, 10, 98, // Opcode: VHADDuv16i8
-/* 123 */     MCD_OPC_FilterValue, 231, 3, 248, 71, 0, // Skip to: 18553
-/* 129 */     MCD_OPC_CheckPredicate, 21, 243, 71, 0, // Skip to: 18553
-/* 134 */     MCD_OPC_CheckField, 6, 1, 0, 236, 71, 0, // Skip to: 18553
-/* 141 */     MCD_OPC_Decode, 245, 7, 99, // Opcode: VADDLuv8i16
-/* 145 */     MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 271
-/* 150 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 153 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 190
-/* 159 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 162 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 176
-/* 167 */     MCD_OPC_CheckPredicate, 21, 205, 71, 0, // Skip to: 18553
-/* 172 */     MCD_OPC_Decode, 240, 16, 97, // Opcode: VRHADDsv8i8
-/* 176 */     MCD_OPC_FilterValue, 1, 196, 71, 0, // Skip to: 18553
-/* 181 */     MCD_OPC_CheckPredicate, 21, 191, 71, 0, // Skip to: 18553
-/* 186 */     MCD_OPC_Decode, 235, 16, 98, // Opcode: VRHADDsv16i8
-/* 190 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 212
-/* 196 */     MCD_OPC_CheckPredicate, 21, 176, 71, 0, // Skip to: 18553
-/* 201 */     MCD_OPC_CheckField, 6, 1, 0, 169, 71, 0, // Skip to: 18553
-/* 208 */     MCD_OPC_Decode, 249, 7, 100, // Opcode: VADDWsv8i16
-/* 212 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 249
-/* 218 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 221 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 235
-/* 226 */     MCD_OPC_CheckPredicate, 21, 146, 71, 0, // Skip to: 18553
-/* 231 */     MCD_OPC_Decode, 246, 16, 97, // Opcode: VRHADDuv8i8
-/* 235 */     MCD_OPC_FilterValue, 1, 137, 71, 0, // Skip to: 18553
-/* 240 */     MCD_OPC_CheckPredicate, 21, 132, 71, 0, // Skip to: 18553
-/* 245 */     MCD_OPC_Decode, 241, 16, 98, // Opcode: VRHADDuv16i8
-/* 249 */     MCD_OPC_FilterValue, 231, 3, 122, 71, 0, // Skip to: 18553
-/* 255 */     MCD_OPC_CheckPredicate, 21, 117, 71, 0, // Skip to: 18553
-/* 260 */     MCD_OPC_CheckField, 6, 1, 0, 110, 71, 0, // Skip to: 18553
-/* 267 */     MCD_OPC_Decode, 252, 7, 100, // Opcode: VADDWuv8i16
-/* 271 */     MCD_OPC_FilterValue, 2, 121, 0, 0, // Skip to: 397
-/* 276 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 279 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 316
-/* 285 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 288 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 302
-/* 293 */     MCD_OPC_CheckPredicate, 21, 79, 71, 0, // Skip to: 18553
-/* 298 */     MCD_OPC_Decode, 191, 10, 97, // Opcode: VHSUBsv8i8
-/* 302 */     MCD_OPC_FilterValue, 1, 70, 71, 0, // Skip to: 18553
-/* 307 */     MCD_OPC_CheckPredicate, 21, 65, 71, 0, // Skip to: 18553
-/* 312 */     MCD_OPC_Decode, 186, 10, 98, // Opcode: VHSUBsv16i8
-/* 316 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 338
-/* 322 */     MCD_OPC_CheckPredicate, 21, 50, 71, 0, // Skip to: 18553
-/* 327 */     MCD_OPC_CheckField, 6, 1, 0, 43, 71, 0, // Skip to: 18553
-/* 334 */     MCD_OPC_Decode, 214, 20, 99, // Opcode: VSUBLsv8i16
-/* 338 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 375
-/* 344 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 347 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 361
-/* 352 */     MCD_OPC_CheckPredicate, 21, 20, 71, 0, // Skip to: 18553
-/* 357 */     MCD_OPC_Decode, 197, 10, 97, // Opcode: VHSUBuv8i8
-/* 361 */     MCD_OPC_FilterValue, 1, 11, 71, 0, // Skip to: 18553
-/* 366 */     MCD_OPC_CheckPredicate, 21, 6, 71, 0, // Skip to: 18553
-/* 371 */     MCD_OPC_Decode, 192, 10, 98, // Opcode: VHSUBuv16i8
-/* 375 */     MCD_OPC_FilterValue, 231, 3, 252, 70, 0, // Skip to: 18553
-/* 381 */     MCD_OPC_CheckPredicate, 21, 247, 70, 0, // Skip to: 18553
-/* 386 */     MCD_OPC_CheckField, 6, 1, 0, 240, 70, 0, // Skip to: 18553
-/* 393 */     MCD_OPC_Decode, 217, 20, 99, // Opcode: VSUBLuv8i16
-/* 397 */     MCD_OPC_FilterValue, 3, 121, 0, 0, // Skip to: 523
-/* 402 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 405 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 442
-/* 411 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 414 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 428
-/* 419 */     MCD_OPC_CheckPredicate, 21, 209, 70, 0, // Skip to: 18553
-/* 424 */     MCD_OPC_Decode, 210, 8, 97, // Opcode: VCGTsv8i8
-/* 428 */     MCD_OPC_FilterValue, 1, 200, 70, 0, // Skip to: 18553
-/* 433 */     MCD_OPC_CheckPredicate, 21, 195, 70, 0, // Skip to: 18553
-/* 438 */     MCD_OPC_Decode, 205, 8, 98, // Opcode: VCGTsv16i8
-/* 442 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 464
-/* 448 */     MCD_OPC_CheckPredicate, 21, 180, 70, 0, // Skip to: 18553
-/* 453 */     MCD_OPC_CheckField, 6, 1, 0, 173, 70, 0, // Skip to: 18553
-/* 460 */     MCD_OPC_Decode, 221, 20, 100, // Opcode: VSUBWsv8i16
-/* 464 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 501
-/* 470 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 473 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 487
-/* 478 */     MCD_OPC_CheckPredicate, 21, 150, 70, 0, // Skip to: 18553
-/* 483 */     MCD_OPC_Decode, 216, 8, 97, // Opcode: VCGTuv8i8
-/* 487 */     MCD_OPC_FilterValue, 1, 141, 70, 0, // Skip to: 18553
-/* 492 */     MCD_OPC_CheckPredicate, 21, 136, 70, 0, // Skip to: 18553
-/* 497 */     MCD_OPC_Decode, 211, 8, 98, // Opcode: VCGTuv16i8
-/* 501 */     MCD_OPC_FilterValue, 231, 3, 126, 70, 0, // Skip to: 18553
-/* 507 */     MCD_OPC_CheckPredicate, 21, 121, 70, 0, // Skip to: 18553
-/* 512 */     MCD_OPC_CheckField, 6, 1, 0, 114, 70, 0, // Skip to: 18553
-/* 519 */     MCD_OPC_Decode, 224, 20, 100, // Opcode: VSUBWuv8i16
-/* 523 */     MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 649
-/* 528 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 531 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 568
-/* 537 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 540 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 554
-/* 545 */     MCD_OPC_CheckPredicate, 21, 83, 70, 0, // Skip to: 18553
-/* 550 */     MCD_OPC_Decode, 143, 18, 101, // Opcode: VSHLsv8i8
-/* 554 */     MCD_OPC_FilterValue, 1, 74, 70, 0, // Skip to: 18553
-/* 559 */     MCD_OPC_CheckPredicate, 21, 69, 70, 0, // Skip to: 18553
-/* 564 */     MCD_OPC_Decode, 136, 18, 102, // Opcode: VSHLsv16i8
-/* 568 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 590
-/* 574 */     MCD_OPC_CheckPredicate, 21, 54, 70, 0, // Skip to: 18553
-/* 579 */     MCD_OPC_CheckField, 6, 1, 0, 47, 70, 0, // Skip to: 18553
-/* 586 */     MCD_OPC_Decode, 239, 7, 103, // Opcode: VADDHNv8i8
-/* 590 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 627
-/* 596 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 599 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 613
-/* 604 */     MCD_OPC_CheckPredicate, 21, 24, 70, 0, // Skip to: 18553
-/* 609 */     MCD_OPC_Decode, 151, 18, 101, // Opcode: VSHLuv8i8
-/* 613 */     MCD_OPC_FilterValue, 1, 15, 70, 0, // Skip to: 18553
-/* 618 */     MCD_OPC_CheckPredicate, 21, 10, 70, 0, // Skip to: 18553
-/* 623 */     MCD_OPC_Decode, 144, 18, 102, // Opcode: VSHLuv16i8
-/* 627 */     MCD_OPC_FilterValue, 231, 3, 0, 70, 0, // Skip to: 18553
-/* 633 */     MCD_OPC_CheckPredicate, 21, 251, 69, 0, // Skip to: 18553
-/* 638 */     MCD_OPC_CheckField, 6, 1, 0, 244, 69, 0, // Skip to: 18553
-/* 645 */     MCD_OPC_Decode, 212, 16, 103, // Opcode: VRADDHNv8i8
-/* 649 */     MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 775
-/* 654 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 657 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 694
-/* 663 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 666 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 680
-/* 671 */     MCD_OPC_CheckPredicate, 21, 213, 69, 0, // Skip to: 18553
-/* 676 */     MCD_OPC_Decode, 171, 17, 101, // Opcode: VRSHLsv8i8
-/* 680 */     MCD_OPC_FilterValue, 1, 204, 69, 0, // Skip to: 18553
-/* 685 */     MCD_OPC_CheckPredicate, 21, 199, 69, 0, // Skip to: 18553
-/* 690 */     MCD_OPC_Decode, 164, 17, 102, // Opcode: VRSHLsv16i8
-/* 694 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 716
-/* 700 */     MCD_OPC_CheckPredicate, 21, 184, 69, 0, // Skip to: 18553
-/* 705 */     MCD_OPC_CheckField, 6, 1, 0, 177, 69, 0, // Skip to: 18553
-/* 712 */     MCD_OPC_Decode, 176, 7, 104, // Opcode: VABALsv8i16
-/* 716 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 753
-/* 722 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 725 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 739
-/* 730 */     MCD_OPC_CheckPredicate, 21, 154, 69, 0, // Skip to: 18553
-/* 735 */     MCD_OPC_Decode, 179, 17, 101, // Opcode: VRSHLuv8i8
-/* 739 */     MCD_OPC_FilterValue, 1, 145, 69, 0, // Skip to: 18553
-/* 744 */     MCD_OPC_CheckPredicate, 21, 140, 69, 0, // Skip to: 18553
-/* 749 */     MCD_OPC_Decode, 172, 17, 102, // Opcode: VRSHLuv16i8
-/* 753 */     MCD_OPC_FilterValue, 231, 3, 130, 69, 0, // Skip to: 18553
-/* 759 */     MCD_OPC_CheckPredicate, 21, 125, 69, 0, // Skip to: 18553
-/* 764 */     MCD_OPC_CheckField, 6, 1, 0, 118, 69, 0, // Skip to: 18553
-/* 771 */     MCD_OPC_Decode, 179, 7, 104, // Opcode: VABALuv8i16
-/* 775 */     MCD_OPC_FilterValue, 6, 121, 0, 0, // Skip to: 901
-/* 780 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 783 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 820
-/* 789 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 792 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 806
-/* 797 */     MCD_OPC_CheckPredicate, 21, 87, 69, 0, // Skip to: 18553
-/* 802 */     MCD_OPC_Decode, 172, 13, 97, // Opcode: VMAXsv8i8
-/* 806 */     MCD_OPC_FilterValue, 1, 78, 69, 0, // Skip to: 18553
-/* 811 */     MCD_OPC_CheckPredicate, 21, 73, 69, 0, // Skip to: 18553
-/* 816 */     MCD_OPC_Decode, 167, 13, 98, // Opcode: VMAXsv16i8
-/* 820 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 842
-/* 826 */     MCD_OPC_CheckPredicate, 21, 58, 69, 0, // Skip to: 18553
-/* 831 */     MCD_OPC_CheckField, 6, 1, 0, 51, 69, 0, // Skip to: 18553
-/* 838 */     MCD_OPC_Decode, 211, 20, 103, // Opcode: VSUBHNv8i8
-/* 842 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 879
-/* 848 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 851 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865
-/* 856 */     MCD_OPC_CheckPredicate, 21, 28, 69, 0, // Skip to: 18553
-/* 861 */     MCD_OPC_Decode, 178, 13, 97, // Opcode: VMAXuv8i8
-/* 865 */     MCD_OPC_FilterValue, 1, 19, 69, 0, // Skip to: 18553
-/* 870 */     MCD_OPC_CheckPredicate, 21, 14, 69, 0, // Skip to: 18553
-/* 875 */     MCD_OPC_Decode, 173, 13, 98, // Opcode: VMAXuv16i8
-/* 879 */     MCD_OPC_FilterValue, 231, 3, 4, 69, 0, // Skip to: 18553
-/* 885 */     MCD_OPC_CheckPredicate, 21, 255, 68, 0, // Skip to: 18553
-/* 890 */     MCD_OPC_CheckField, 6, 1, 0, 248, 68, 0, // Skip to: 18553
-/* 897 */     MCD_OPC_Decode, 227, 17, 103, // Opcode: VRSUBHNv8i8
-/* 901 */     MCD_OPC_FilterValue, 7, 121, 0, 0, // Skip to: 1027
-/* 906 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 909 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 946
-/* 915 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 918 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 932
-/* 923 */     MCD_OPC_CheckPredicate, 21, 217, 68, 0, // Skip to: 18553
-/* 928 */     MCD_OPC_Decode, 207, 7, 97, // Opcode: VABDsv8i8
-/* 932 */     MCD_OPC_FilterValue, 1, 208, 68, 0, // Skip to: 18553
-/* 937 */     MCD_OPC_CheckPredicate, 21, 203, 68, 0, // Skip to: 18553
-/* 942 */     MCD_OPC_Decode, 202, 7, 98, // Opcode: VABDsv16i8
-/* 946 */     MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 968
-/* 952 */     MCD_OPC_CheckPredicate, 21, 188, 68, 0, // Skip to: 18553
-/* 957 */     MCD_OPC_CheckField, 6, 1, 0, 181, 68, 0, // Skip to: 18553
-/* 964 */     MCD_OPC_Decode, 194, 7, 99, // Opcode: VABDLsv8i16
-/* 968 */     MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1005
-/* 974 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 977 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 991
-/* 982 */     MCD_OPC_CheckPredicate, 21, 158, 68, 0, // Skip to: 18553
-/* 987 */     MCD_OPC_Decode, 213, 7, 97, // Opcode: VABDuv8i8
-/* 991 */     MCD_OPC_FilterValue, 1, 149, 68, 0, // Skip to: 18553
-/* 996 */     MCD_OPC_CheckPredicate, 21, 144, 68, 0, // Skip to: 18553
-/* 1001 */    MCD_OPC_Decode, 208, 7, 98, // Opcode: VABDuv16i8
-/* 1005 */    MCD_OPC_FilterValue, 231, 3, 134, 68, 0, // Skip to: 18553
-/* 1011 */    MCD_OPC_CheckPredicate, 21, 129, 68, 0, // Skip to: 18553
-/* 1016 */    MCD_OPC_CheckField, 6, 1, 0, 122, 68, 0, // Skip to: 18553
-/* 1023 */    MCD_OPC_Decode, 197, 7, 99, // Opcode: VABDLuv8i16
-/* 1027 */    MCD_OPC_FilterValue, 8, 121, 0, 0, // Skip to: 1153
-/* 1032 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1035 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1072
-/* 1041 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1044 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1058
-/* 1049 */    MCD_OPC_CheckPredicate, 21, 91, 68, 0, // Skip to: 18553
-/* 1054 */    MCD_OPC_Decode, 136, 8, 97, // Opcode: VADDv8i8
-/* 1058 */    MCD_OPC_FilterValue, 1, 82, 68, 0, // Skip to: 18553
-/* 1063 */    MCD_OPC_CheckPredicate, 21, 77, 68, 0, // Skip to: 18553
-/* 1068 */    MCD_OPC_Decode, 129, 8, 98, // Opcode: VADDv16i8
-/* 1072 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1094
-/* 1078 */    MCD_OPC_CheckPredicate, 21, 62, 68, 0, // Skip to: 18553
-/* 1083 */    MCD_OPC_CheckField, 6, 1, 0, 55, 68, 0, // Skip to: 18553
-/* 1090 */    MCD_OPC_Decode, 210, 13, 104, // Opcode: VMLALsv8i16
-/* 1094 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1131
-/* 1100 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1103 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1117
-/* 1108 */    MCD_OPC_CheckPredicate, 21, 32, 68, 0, // Skip to: 18553
-/* 1113 */    MCD_OPC_Decode, 236, 20, 97, // Opcode: VSUBv8i8
-/* 1117 */    MCD_OPC_FilterValue, 1, 23, 68, 0, // Skip to: 18553
-/* 1122 */    MCD_OPC_CheckPredicate, 21, 18, 68, 0, // Skip to: 18553
-/* 1127 */    MCD_OPC_Decode, 229, 20, 98, // Opcode: VSUBv16i8
-/* 1131 */    MCD_OPC_FilterValue, 231, 3, 8, 68, 0, // Skip to: 18553
-/* 1137 */    MCD_OPC_CheckPredicate, 21, 3, 68, 0, // Skip to: 18553
-/* 1142 */    MCD_OPC_CheckField, 6, 1, 0, 252, 67, 0, // Skip to: 18553
-/* 1149 */    MCD_OPC_Decode, 213, 13, 104, // Opcode: VMLALuv8i16
-/* 1153 */    MCD_OPC_FilterValue, 9, 79, 0, 0, // Skip to: 1237
-/* 1158 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1161 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1199
-/* 1166 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1169 */    MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1184
-/* 1175 */    MCD_OPC_CheckPredicate, 21, 221, 67, 0, // Skip to: 18553
-/* 1180 */    MCD_OPC_Decode, 232, 13, 105, // Opcode: VMLAv8i8
-/* 1184 */    MCD_OPC_FilterValue, 230, 3, 211, 67, 0, // Skip to: 18553
-/* 1190 */    MCD_OPC_CheckPredicate, 21, 206, 67, 0, // Skip to: 18553
-/* 1195 */    MCD_OPC_Decode, 135, 14, 105, // Opcode: VMLSv8i8
-/* 1199 */    MCD_OPC_FilterValue, 1, 197, 67, 0, // Skip to: 18553
-/* 1204 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1207 */    MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1222
-/* 1213 */    MCD_OPC_CheckPredicate, 21, 183, 67, 0, // Skip to: 18553
-/* 1218 */    MCD_OPC_Decode, 227, 13, 106, // Opcode: VMLAv16i8
-/* 1222 */    MCD_OPC_FilterValue, 230, 3, 173, 67, 0, // Skip to: 18553
-/* 1228 */    MCD_OPC_CheckPredicate, 21, 168, 67, 0, // Skip to: 18553
-/* 1233 */    MCD_OPC_Decode, 130, 14, 106, // Opcode: VMLSv16i8
-/* 1237 */    MCD_OPC_FilterValue, 10, 91, 0, 0, // Skip to: 1333
-/* 1242 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1245 */    MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 1267
-/* 1251 */    MCD_OPC_CheckPredicate, 21, 145, 67, 0, // Skip to: 18553
-/* 1256 */    MCD_OPC_CheckField, 6, 1, 0, 138, 67, 0, // Skip to: 18553
-/* 1263 */    MCD_OPC_Decode, 155, 15, 97, // Opcode: VPMAXs8
-/* 1267 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1289
-/* 1273 */    MCD_OPC_CheckPredicate, 21, 123, 67, 0, // Skip to: 18553
-/* 1278 */    MCD_OPC_CheckField, 6, 1, 0, 116, 67, 0, // Skip to: 18553
-/* 1285 */    MCD_OPC_Decode, 241, 13, 104, // Opcode: VMLSLsv8i16
-/* 1289 */    MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 1311
-/* 1295 */    MCD_OPC_CheckPredicate, 21, 101, 67, 0, // Skip to: 18553
-/* 1300 */    MCD_OPC_CheckField, 6, 1, 0, 94, 67, 0, // Skip to: 18553
-/* 1307 */    MCD_OPC_Decode, 158, 15, 97, // Opcode: VPMAXu8
-/* 1311 */    MCD_OPC_FilterValue, 231, 3, 84, 67, 0, // Skip to: 18553
-/* 1317 */    MCD_OPC_CheckPredicate, 21, 79, 67, 0, // Skip to: 18553
-/* 1322 */    MCD_OPC_CheckField, 6, 1, 0, 72, 67, 0, // Skip to: 18553
-/* 1329 */    MCD_OPC_Decode, 244, 13, 104, // Opcode: VMLSLuv8i16
-/* 1333 */    MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 1385
-/* 1338 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1341 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1363
-/* 1347 */    MCD_OPC_CheckPredicate, 21, 49, 67, 0, // Skip to: 18553
-/* 1352 */    MCD_OPC_CheckField, 6, 1, 0, 42, 67, 0, // Skip to: 18553
-/* 1359 */    MCD_OPC_Decode, 189, 14, 99, // Opcode: VMULLsv8i16
-/* 1363 */    MCD_OPC_FilterValue, 231, 3, 32, 67, 0, // Skip to: 18553
-/* 1369 */    MCD_OPC_CheckPredicate, 21, 27, 67, 0, // Skip to: 18553
-/* 1374 */    MCD_OPC_CheckField, 6, 1, 0, 20, 67, 0, // Skip to: 18553
-/* 1381 */    MCD_OPC_Decode, 192, 14, 99, // Opcode: VMULLuv8i16
-/* 1385 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1453
-/* 1390 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1393 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1431
-/* 1398 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1401 */    MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1416
-/* 1407 */    MCD_OPC_CheckPredicate, 21, 245, 66, 0, // Skip to: 18553
-/* 1412 */    MCD_OPC_Decode, 253, 7, 97, // Opcode: VADDfd
-/* 1416 */    MCD_OPC_FilterValue, 230, 3, 235, 66, 0, // Skip to: 18553
-/* 1422 */    MCD_OPC_CheckPredicate, 21, 230, 66, 0, // Skip to: 18553
-/* 1427 */    MCD_OPC_Decode, 146, 15, 97, // Opcode: VPADDf
-/* 1431 */    MCD_OPC_FilterValue, 1, 221, 66, 0, // Skip to: 18553
-/* 1436 */    MCD_OPC_CheckPredicate, 21, 216, 66, 0, // Skip to: 18553
-/* 1441 */    MCD_OPC_CheckField, 23, 9, 228, 3, 208, 66, 0, // Skip to: 18553
-/* 1449 */    MCD_OPC_Decode, 254, 7, 98, // Opcode: VADDfq
-/* 1453 */    MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 1557
-/* 1458 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1461 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1498
-/* 1467 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1470 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1484
-/* 1475 */    MCD_OPC_CheckPredicate, 21, 177, 66, 0, // Skip to: 18553
-/* 1480 */    MCD_OPC_Decode, 155, 8, 97, // Opcode: VCEQfd
-/* 1484 */    MCD_OPC_FilterValue, 1, 168, 66, 0, // Skip to: 18553
-/* 1489 */    MCD_OPC_CheckPredicate, 21, 163, 66, 0, // Skip to: 18553
-/* 1494 */    MCD_OPC_Decode, 156, 8, 98, // Opcode: VCEQfq
-/* 1498 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 1520
-/* 1504 */    MCD_OPC_CheckPredicate, 21, 148, 66, 0, // Skip to: 18553
-/* 1509 */    MCD_OPC_CheckField, 6, 1, 0, 141, 66, 0, // Skip to: 18553
-/* 1516 */    MCD_OPC_Decode, 182, 14, 99, // Opcode: VMULLp8
-/* 1520 */    MCD_OPC_FilterValue, 230, 3, 131, 66, 0, // Skip to: 18553
-/* 1526 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1529 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1543
-/* 1534 */    MCD_OPC_CheckPredicate, 21, 118, 66, 0, // Skip to: 18553
-/* 1539 */    MCD_OPC_Decode, 175, 8, 97, // Opcode: VCGEfd
-/* 1543 */    MCD_OPC_FilterValue, 1, 109, 66, 0, // Skip to: 18553
-/* 1548 */    MCD_OPC_CheckPredicate, 21, 104, 66, 0, // Skip to: 18553
-/* 1553 */    MCD_OPC_Decode, 176, 8, 98, // Opcode: VCGEfq
-/* 1557 */    MCD_OPC_FilterValue, 15, 95, 66, 0, // Skip to: 18553
-/* 1562 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1565 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1603
-/* 1570 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1573 */    MCD_OPC_FilterValue, 228, 3, 9, 0, 0, // Skip to: 1588
-/* 1579 */    MCD_OPC_CheckPredicate, 21, 73, 66, 0, // Skip to: 18553
-/* 1584 */    MCD_OPC_Decode, 163, 13, 97, // Opcode: VMAXfd
-/* 1588 */    MCD_OPC_FilterValue, 230, 3, 63, 66, 0, // Skip to: 18553
-/* 1594 */    MCD_OPC_CheckPredicate, 21, 58, 66, 0, // Skip to: 18553
-/* 1599 */    MCD_OPC_Decode, 151, 15, 97, // Opcode: VPMAXf
-/* 1603 */    MCD_OPC_FilterValue, 1, 49, 66, 0, // Skip to: 18553
-/* 1608 */    MCD_OPC_CheckPredicate, 21, 44, 66, 0, // Skip to: 18553
-/* 1613 */    MCD_OPC_CheckField, 23, 9, 228, 3, 36, 66, 0, // Skip to: 18553
-/* 1621 */    MCD_OPC_Decode, 164, 13, 98, // Opcode: VMAXfq
-/* 1625 */    MCD_OPC_FilterValue, 1, 162, 8, 0, // Skip to: 3840
-/* 1630 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1633 */    MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 1789
-/* 1638 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1641 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1678
-/* 1647 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1650 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1664
-/* 1655 */    MCD_OPC_CheckPredicate, 21, 253, 65, 0, // Skip to: 18553
-/* 1660 */    MCD_OPC_Decode, 176, 10, 97, // Opcode: VHADDsv4i16
-/* 1664 */    MCD_OPC_FilterValue, 1, 244, 65, 0, // Skip to: 18553
-/* 1669 */    MCD_OPC_CheckPredicate, 21, 239, 65, 0, // Skip to: 18553
-/* 1674 */    MCD_OPC_Decode, 178, 10, 98, // Opcode: VHADDsv8i16
-/* 1678 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1715
-/* 1684 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1687 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1701
-/* 1692 */    MCD_OPC_CheckPredicate, 21, 216, 65, 0, // Skip to: 18553
-/* 1697 */    MCD_OPC_Decode, 241, 7, 99, // Opcode: VADDLsv4i32
-/* 1701 */    MCD_OPC_FilterValue, 1, 207, 65, 0, // Skip to: 18553
-/* 1706 */    MCD_OPC_CheckPredicate, 21, 202, 65, 0, // Skip to: 18553
-/* 1711 */    MCD_OPC_Decode, 224, 13, 107, // Opcode: VMLAslv4i16
-/* 1715 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1752
-/* 1721 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1724 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1738
-/* 1729 */    MCD_OPC_CheckPredicate, 21, 179, 65, 0, // Skip to: 18553
-/* 1734 */    MCD_OPC_Decode, 182, 10, 97, // Opcode: VHADDuv4i16
-/* 1738 */    MCD_OPC_FilterValue, 1, 170, 65, 0, // Skip to: 18553
-/* 1743 */    MCD_OPC_CheckPredicate, 21, 165, 65, 0, // Skip to: 18553
-/* 1748 */    MCD_OPC_Decode, 184, 10, 98, // Opcode: VHADDuv8i16
-/* 1752 */    MCD_OPC_FilterValue, 231, 3, 155, 65, 0, // Skip to: 18553
-/* 1758 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1761 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1775
-/* 1766 */    MCD_OPC_CheckPredicate, 21, 142, 65, 0, // Skip to: 18553
-/* 1771 */    MCD_OPC_Decode, 244, 7, 99, // Opcode: VADDLuv4i32
-/* 1775 */    MCD_OPC_FilterValue, 1, 133, 65, 0, // Skip to: 18553
-/* 1780 */    MCD_OPC_CheckPredicate, 21, 128, 65, 0, // Skip to: 18553
-/* 1785 */    MCD_OPC_Decode, 226, 13, 108, // Opcode: VMLAslv8i16
-/* 1789 */    MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 1945
-/* 1794 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1797 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1834
-/* 1803 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1806 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1820
-/* 1811 */    MCD_OPC_CheckPredicate, 21, 97, 65, 0, // Skip to: 18553
-/* 1816 */    MCD_OPC_Decode, 237, 16, 97, // Opcode: VRHADDsv4i16
-/* 1820 */    MCD_OPC_FilterValue, 1, 88, 65, 0, // Skip to: 18553
-/* 1825 */    MCD_OPC_CheckPredicate, 21, 83, 65, 0, // Skip to: 18553
-/* 1830 */    MCD_OPC_Decode, 239, 16, 98, // Opcode: VRHADDsv8i16
-/* 1834 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 1871
-/* 1840 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1843 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1857
-/* 1848 */    MCD_OPC_CheckPredicate, 21, 60, 65, 0, // Skip to: 18553
-/* 1853 */    MCD_OPC_Decode, 248, 7, 100, // Opcode: VADDWsv4i32
-/* 1857 */    MCD_OPC_FilterValue, 1, 51, 65, 0, // Skip to: 18553
-/* 1862 */    MCD_OPC_CheckPredicate, 22, 46, 65, 0, // Skip to: 18553
-/* 1867 */    MCD_OPC_Decode, 221, 13, 107, // Opcode: VMLAslhd
-/* 1871 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 1908
-/* 1877 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1880 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1894
-/* 1885 */    MCD_OPC_CheckPredicate, 21, 23, 65, 0, // Skip to: 18553
-/* 1890 */    MCD_OPC_Decode, 243, 16, 97, // Opcode: VRHADDuv4i16
-/* 1894 */    MCD_OPC_FilterValue, 1, 14, 65, 0, // Skip to: 18553
-/* 1899 */    MCD_OPC_CheckPredicate, 21, 9, 65, 0, // Skip to: 18553
-/* 1904 */    MCD_OPC_Decode, 245, 16, 98, // Opcode: VRHADDuv8i16
-/* 1908 */    MCD_OPC_FilterValue, 231, 3, 255, 64, 0, // Skip to: 18553
-/* 1914 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1917 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1931
-/* 1922 */    MCD_OPC_CheckPredicate, 21, 242, 64, 0, // Skip to: 18553
-/* 1927 */    MCD_OPC_Decode, 251, 7, 100, // Opcode: VADDWuv4i32
-/* 1931 */    MCD_OPC_FilterValue, 1, 233, 64, 0, // Skip to: 18553
-/* 1936 */    MCD_OPC_CheckPredicate, 22, 228, 64, 0, // Skip to: 18553
-/* 1941 */    MCD_OPC_Decode, 222, 13, 108, // Opcode: VMLAslhq
-/* 1945 */    MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 2101
-/* 1950 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1953 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 1990
-/* 1959 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1962 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1976
-/* 1967 */    MCD_OPC_CheckPredicate, 21, 197, 64, 0, // Skip to: 18553
-/* 1972 */    MCD_OPC_Decode, 188, 10, 97, // Opcode: VHSUBsv4i16
-/* 1976 */    MCD_OPC_FilterValue, 1, 188, 64, 0, // Skip to: 18553
-/* 1981 */    MCD_OPC_CheckPredicate, 21, 183, 64, 0, // Skip to: 18553
-/* 1986 */    MCD_OPC_Decode, 190, 10, 98, // Opcode: VHSUBsv8i16
-/* 1990 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2027
-/* 1996 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1999 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2013
-/* 2004 */    MCD_OPC_CheckPredicate, 21, 160, 64, 0, // Skip to: 18553
-/* 2009 */    MCD_OPC_Decode, 213, 20, 99, // Opcode: VSUBLsv4i32
-/* 2013 */    MCD_OPC_FilterValue, 1, 151, 64, 0, // Skip to: 18553
-/* 2018 */    MCD_OPC_CheckPredicate, 21, 146, 64, 0, // Skip to: 18553
-/* 2023 */    MCD_OPC_Decode, 205, 13, 109, // Opcode: VMLALslsv4i16
-/* 2027 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2064
-/* 2033 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2036 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2050
-/* 2041 */    MCD_OPC_CheckPredicate, 21, 123, 64, 0, // Skip to: 18553
-/* 2046 */    MCD_OPC_Decode, 194, 10, 97, // Opcode: VHSUBuv4i16
-/* 2050 */    MCD_OPC_FilterValue, 1, 114, 64, 0, // Skip to: 18553
-/* 2055 */    MCD_OPC_CheckPredicate, 21, 109, 64, 0, // Skip to: 18553
-/* 2060 */    MCD_OPC_Decode, 196, 10, 98, // Opcode: VHSUBuv8i16
-/* 2064 */    MCD_OPC_FilterValue, 231, 3, 99, 64, 0, // Skip to: 18553
-/* 2070 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2073 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2087
-/* 2078 */    MCD_OPC_CheckPredicate, 21, 86, 64, 0, // Skip to: 18553
-/* 2083 */    MCD_OPC_Decode, 216, 20, 99, // Opcode: VSUBLuv4i32
-/* 2087 */    MCD_OPC_FilterValue, 1, 77, 64, 0, // Skip to: 18553
-/* 2092 */    MCD_OPC_CheckPredicate, 21, 72, 64, 0, // Skip to: 18553
-/* 2097 */    MCD_OPC_Decode, 207, 13, 109, // Opcode: VMLALsluv4i16
-/* 2101 */    MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 2242
-/* 2106 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2109 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2146
-/* 2115 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2118 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2132
-/* 2123 */    MCD_OPC_CheckPredicate, 21, 41, 64, 0, // Skip to: 18553
-/* 2128 */    MCD_OPC_Decode, 207, 8, 97, // Opcode: VCGTsv4i16
-/* 2132 */    MCD_OPC_FilterValue, 1, 32, 64, 0, // Skip to: 18553
-/* 2137 */    MCD_OPC_CheckPredicate, 21, 27, 64, 0, // Skip to: 18553
-/* 2142 */    MCD_OPC_Decode, 209, 8, 98, // Opcode: VCGTsv8i16
-/* 2146 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2183
-/* 2152 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2155 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2169
-/* 2160 */    MCD_OPC_CheckPredicate, 21, 4, 64, 0, // Skip to: 18553
-/* 2165 */    MCD_OPC_Decode, 220, 20, 100, // Opcode: VSUBWsv4i32
-/* 2169 */    MCD_OPC_FilterValue, 1, 251, 63, 0, // Skip to: 18553
-/* 2174 */    MCD_OPC_CheckPredicate, 21, 246, 63, 0, // Skip to: 18553
-/* 2179 */    MCD_OPC_Decode, 190, 15, 109, // Opcode: VQDMLALslv4i16
-/* 2183 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2220
-/* 2189 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2192 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2206
-/* 2197 */    MCD_OPC_CheckPredicate, 21, 223, 63, 0, // Skip to: 18553
-/* 2202 */    MCD_OPC_Decode, 213, 8, 97, // Opcode: VCGTuv4i16
-/* 2206 */    MCD_OPC_FilterValue, 1, 214, 63, 0, // Skip to: 18553
-/* 2211 */    MCD_OPC_CheckPredicate, 21, 209, 63, 0, // Skip to: 18553
-/* 2216 */    MCD_OPC_Decode, 215, 8, 98, // Opcode: VCGTuv8i16
-/* 2220 */    MCD_OPC_FilterValue, 231, 3, 199, 63, 0, // Skip to: 18553
-/* 2226 */    MCD_OPC_CheckPredicate, 21, 194, 63, 0, // Skip to: 18553
-/* 2231 */    MCD_OPC_CheckField, 6, 1, 0, 187, 63, 0, // Skip to: 18553
-/* 2238 */    MCD_OPC_Decode, 223, 20, 100, // Opcode: VSUBWuv4i32
-/* 2242 */    MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 2398
-/* 2247 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2250 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2287
-/* 2256 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2259 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2273
-/* 2264 */    MCD_OPC_CheckPredicate, 21, 156, 63, 0, // Skip to: 18553
-/* 2269 */    MCD_OPC_Decode, 140, 18, 101, // Opcode: VSHLsv4i16
-/* 2273 */    MCD_OPC_FilterValue, 1, 147, 63, 0, // Skip to: 18553
-/* 2278 */    MCD_OPC_CheckPredicate, 21, 142, 63, 0, // Skip to: 18553
-/* 2283 */    MCD_OPC_Decode, 142, 18, 102, // Opcode: VSHLsv8i16
-/* 2287 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2324
-/* 2293 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2296 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2310
-/* 2301 */    MCD_OPC_CheckPredicate, 21, 119, 63, 0, // Skip to: 18553
-/* 2306 */    MCD_OPC_Decode, 238, 7, 103, // Opcode: VADDHNv4i16
-/* 2310 */    MCD_OPC_FilterValue, 1, 110, 63, 0, // Skip to: 18553
-/* 2315 */    MCD_OPC_CheckPredicate, 21, 105, 63, 0, // Skip to: 18553
-/* 2320 */    MCD_OPC_Decode, 255, 13, 107, // Opcode: VMLSslv4i16
-/* 2324 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2361
-/* 2330 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2333 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2347
-/* 2338 */    MCD_OPC_CheckPredicate, 21, 82, 63, 0, // Skip to: 18553
-/* 2343 */    MCD_OPC_Decode, 148, 18, 101, // Opcode: VSHLuv4i16
-/* 2347 */    MCD_OPC_FilterValue, 1, 73, 63, 0, // Skip to: 18553
-/* 2352 */    MCD_OPC_CheckPredicate, 21, 68, 63, 0, // Skip to: 18553
-/* 2357 */    MCD_OPC_Decode, 150, 18, 102, // Opcode: VSHLuv8i16
-/* 2361 */    MCD_OPC_FilterValue, 231, 3, 58, 63, 0, // Skip to: 18553
-/* 2367 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2370 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2384
-/* 2375 */    MCD_OPC_CheckPredicate, 21, 45, 63, 0, // Skip to: 18553
-/* 2380 */    MCD_OPC_Decode, 211, 16, 103, // Opcode: VRADDHNv4i16
-/* 2384 */    MCD_OPC_FilterValue, 1, 36, 63, 0, // Skip to: 18553
-/* 2389 */    MCD_OPC_CheckPredicate, 21, 31, 63, 0, // Skip to: 18553
-/* 2394 */    MCD_OPC_Decode, 129, 14, 108, // Opcode: VMLSslv8i16
-/* 2398 */    MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 2554
-/* 2403 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2406 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2443
-/* 2412 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2415 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2429
-/* 2420 */    MCD_OPC_CheckPredicate, 21, 0, 63, 0, // Skip to: 18553
-/* 2425 */    MCD_OPC_Decode, 168, 17, 101, // Opcode: VRSHLsv4i16
-/* 2429 */    MCD_OPC_FilterValue, 1, 247, 62, 0, // Skip to: 18553
-/* 2434 */    MCD_OPC_CheckPredicate, 21, 242, 62, 0, // Skip to: 18553
-/* 2439 */    MCD_OPC_Decode, 170, 17, 102, // Opcode: VRSHLsv8i16
-/* 2443 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2480
-/* 2449 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2452 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2466
-/* 2457 */    MCD_OPC_CheckPredicate, 21, 219, 62, 0, // Skip to: 18553
-/* 2462 */    MCD_OPC_Decode, 175, 7, 104, // Opcode: VABALsv4i32
-/* 2466 */    MCD_OPC_FilterValue, 1, 210, 62, 0, // Skip to: 18553
-/* 2471 */    MCD_OPC_CheckPredicate, 22, 205, 62, 0, // Skip to: 18553
-/* 2476 */    MCD_OPC_Decode, 252, 13, 107, // Opcode: VMLSslhd
-/* 2480 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2517
-/* 2486 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2489 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2503
-/* 2494 */    MCD_OPC_CheckPredicate, 21, 182, 62, 0, // Skip to: 18553
-/* 2499 */    MCD_OPC_Decode, 176, 17, 101, // Opcode: VRSHLuv4i16
-/* 2503 */    MCD_OPC_FilterValue, 1, 173, 62, 0, // Skip to: 18553
-/* 2508 */    MCD_OPC_CheckPredicate, 21, 168, 62, 0, // Skip to: 18553
-/* 2513 */    MCD_OPC_Decode, 178, 17, 102, // Opcode: VRSHLuv8i16
-/* 2517 */    MCD_OPC_FilterValue, 231, 3, 158, 62, 0, // Skip to: 18553
-/* 2523 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2526 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2540
-/* 2531 */    MCD_OPC_CheckPredicate, 21, 145, 62, 0, // Skip to: 18553
-/* 2536 */    MCD_OPC_Decode, 178, 7, 104, // Opcode: VABALuv4i32
-/* 2540 */    MCD_OPC_FilterValue, 1, 136, 62, 0, // Skip to: 18553
-/* 2545 */    MCD_OPC_CheckPredicate, 22, 131, 62, 0, // Skip to: 18553
-/* 2550 */    MCD_OPC_Decode, 253, 13, 108, // Opcode: VMLSslhq
-/* 2554 */    MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 2710
-/* 2559 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2562 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2599
-/* 2568 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2571 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2585
-/* 2576 */    MCD_OPC_CheckPredicate, 21, 100, 62, 0, // Skip to: 18553
-/* 2581 */    MCD_OPC_Decode, 169, 13, 97, // Opcode: VMAXsv4i16
-/* 2585 */    MCD_OPC_FilterValue, 1, 91, 62, 0, // Skip to: 18553
-/* 2590 */    MCD_OPC_CheckPredicate, 21, 86, 62, 0, // Skip to: 18553
-/* 2595 */    MCD_OPC_Decode, 171, 13, 98, // Opcode: VMAXsv8i16
-/* 2599 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2636
-/* 2605 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2608 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2622
-/* 2613 */    MCD_OPC_CheckPredicate, 21, 63, 62, 0, // Skip to: 18553
-/* 2618 */    MCD_OPC_Decode, 210, 20, 103, // Opcode: VSUBHNv4i16
-/* 2622 */    MCD_OPC_FilterValue, 1, 54, 62, 0, // Skip to: 18553
-/* 2627 */    MCD_OPC_CheckPredicate, 21, 49, 62, 0, // Skip to: 18553
-/* 2632 */    MCD_OPC_Decode, 236, 13, 109, // Opcode: VMLSLslsv4i16
-/* 2636 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2673
-/* 2642 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2645 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2659
-/* 2650 */    MCD_OPC_CheckPredicate, 21, 26, 62, 0, // Skip to: 18553
-/* 2655 */    MCD_OPC_Decode, 175, 13, 97, // Opcode: VMAXuv4i16
-/* 2659 */    MCD_OPC_FilterValue, 1, 17, 62, 0, // Skip to: 18553
-/* 2664 */    MCD_OPC_CheckPredicate, 21, 12, 62, 0, // Skip to: 18553
-/* 2669 */    MCD_OPC_Decode, 177, 13, 98, // Opcode: VMAXuv8i16
-/* 2673 */    MCD_OPC_FilterValue, 231, 3, 2, 62, 0, // Skip to: 18553
-/* 2679 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2682 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2696
-/* 2687 */    MCD_OPC_CheckPredicate, 21, 245, 61, 0, // Skip to: 18553
-/* 2692 */    MCD_OPC_Decode, 226, 17, 103, // Opcode: VRSUBHNv4i16
-/* 2696 */    MCD_OPC_FilterValue, 1, 236, 61, 0, // Skip to: 18553
-/* 2701 */    MCD_OPC_CheckPredicate, 21, 231, 61, 0, // Skip to: 18553
-/* 2706 */    MCD_OPC_Decode, 238, 13, 109, // Opcode: VMLSLsluv4i16
-/* 2710 */    MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 2851
-/* 2715 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2718 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2755
-/* 2724 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2727 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2741
-/* 2732 */    MCD_OPC_CheckPredicate, 21, 200, 61, 0, // Skip to: 18553
-/* 2737 */    MCD_OPC_Decode, 204, 7, 97, // Opcode: VABDsv4i16
-/* 2741 */    MCD_OPC_FilterValue, 1, 191, 61, 0, // Skip to: 18553
-/* 2746 */    MCD_OPC_CheckPredicate, 21, 186, 61, 0, // Skip to: 18553
-/* 2751 */    MCD_OPC_Decode, 206, 7, 98, // Opcode: VABDsv8i16
-/* 2755 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2792
-/* 2761 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2764 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2778
-/* 2769 */    MCD_OPC_CheckPredicate, 21, 163, 61, 0, // Skip to: 18553
-/* 2774 */    MCD_OPC_Decode, 193, 7, 99, // Opcode: VABDLsv4i32
-/* 2778 */    MCD_OPC_FilterValue, 1, 154, 61, 0, // Skip to: 18553
-/* 2783 */    MCD_OPC_CheckPredicate, 21, 149, 61, 0, // Skip to: 18553
-/* 2788 */    MCD_OPC_Decode, 194, 15, 109, // Opcode: VQDMLSLslv4i16
-/* 2792 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2829
-/* 2798 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2801 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2815
-/* 2806 */    MCD_OPC_CheckPredicate, 21, 126, 61, 0, // Skip to: 18553
-/* 2811 */    MCD_OPC_Decode, 210, 7, 97, // Opcode: VABDuv4i16
-/* 2815 */    MCD_OPC_FilterValue, 1, 117, 61, 0, // Skip to: 18553
-/* 2820 */    MCD_OPC_CheckPredicate, 21, 112, 61, 0, // Skip to: 18553
-/* 2825 */    MCD_OPC_Decode, 212, 7, 98, // Opcode: VABDuv8i16
-/* 2829 */    MCD_OPC_FilterValue, 231, 3, 102, 61, 0, // Skip to: 18553
-/* 2835 */    MCD_OPC_CheckPredicate, 21, 97, 61, 0, // Skip to: 18553
-/* 2840 */    MCD_OPC_CheckField, 6, 1, 0, 90, 61, 0, // Skip to: 18553
-/* 2847 */    MCD_OPC_Decode, 196, 7, 99, // Opcode: VABDLuv4i32
-/* 2851 */    MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 3007
-/* 2856 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2859 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 2896
-/* 2865 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2868 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2882
-/* 2873 */    MCD_OPC_CheckPredicate, 21, 59, 61, 0, // Skip to: 18553
-/* 2878 */    MCD_OPC_Decode, 133, 8, 97, // Opcode: VADDv4i16
-/* 2882 */    MCD_OPC_FilterValue, 1, 50, 61, 0, // Skip to: 18553
-/* 2887 */    MCD_OPC_CheckPredicate, 21, 45, 61, 0, // Skip to: 18553
-/* 2892 */    MCD_OPC_Decode, 135, 8, 98, // Opcode: VADDv8i16
-/* 2896 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 2933
-/* 2902 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2905 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2919
-/* 2910 */    MCD_OPC_CheckPredicate, 21, 22, 61, 0, // Skip to: 18553
-/* 2915 */    MCD_OPC_Decode, 209, 13, 104, // Opcode: VMLALsv4i32
-/* 2919 */    MCD_OPC_FilterValue, 1, 13, 61, 0, // Skip to: 18553
-/* 2924 */    MCD_OPC_CheckPredicate, 21, 8, 61, 0, // Skip to: 18553
-/* 2929 */    MCD_OPC_Decode, 205, 14, 110, // Opcode: VMULslv4i16
-/* 2933 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 2970
-/* 2939 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2942 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2956
-/* 2947 */    MCD_OPC_CheckPredicate, 21, 241, 60, 0, // Skip to: 18553
-/* 2952 */    MCD_OPC_Decode, 233, 20, 97, // Opcode: VSUBv4i16
-/* 2956 */    MCD_OPC_FilterValue, 1, 232, 60, 0, // Skip to: 18553
-/* 2961 */    MCD_OPC_CheckPredicate, 21, 227, 60, 0, // Skip to: 18553
-/* 2966 */    MCD_OPC_Decode, 235, 20, 98, // Opcode: VSUBv8i16
-/* 2970 */    MCD_OPC_FilterValue, 231, 3, 217, 60, 0, // Skip to: 18553
-/* 2976 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2979 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2993
-/* 2984 */    MCD_OPC_CheckPredicate, 21, 204, 60, 0, // Skip to: 18553
-/* 2989 */    MCD_OPC_Decode, 212, 13, 104, // Opcode: VMLALuv4i32
-/* 2993 */    MCD_OPC_FilterValue, 1, 195, 60, 0, // Skip to: 18553
-/* 2998 */    MCD_OPC_CheckPredicate, 21, 190, 60, 0, // Skip to: 18553
-/* 3003 */    MCD_OPC_Decode, 207, 14, 111, // Opcode: VMULslv8i16
-/* 3007 */    MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 3148
-/* 3012 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3015 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3052
-/* 3021 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3024 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3038
-/* 3029 */    MCD_OPC_CheckPredicate, 21, 159, 60, 0, // Skip to: 18553
-/* 3034 */    MCD_OPC_Decode, 229, 13, 105, // Opcode: VMLAv4i16
-/* 3038 */    MCD_OPC_FilterValue, 1, 150, 60, 0, // Skip to: 18553
-/* 3043 */    MCD_OPC_CheckPredicate, 21, 145, 60, 0, // Skip to: 18553
-/* 3048 */    MCD_OPC_Decode, 231, 13, 106, // Opcode: VMLAv8i16
-/* 3052 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3089
-/* 3058 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3061 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3075
-/* 3066 */    MCD_OPC_CheckPredicate, 21, 122, 60, 0, // Skip to: 18553
-/* 3071 */    MCD_OPC_Decode, 192, 15, 104, // Opcode: VQDMLALv4i32
-/* 3075 */    MCD_OPC_FilterValue, 1, 113, 60, 0, // Skip to: 18553
-/* 3080 */    MCD_OPC_CheckPredicate, 22, 108, 60, 0, // Skip to: 18553
-/* 3085 */    MCD_OPC_Decode, 202, 14, 110, // Opcode: VMULslhd
-/* 3089 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3126
-/* 3095 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3098 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3112
-/* 3103 */    MCD_OPC_CheckPredicate, 21, 85, 60, 0, // Skip to: 18553
-/* 3108 */    MCD_OPC_Decode, 132, 14, 105, // Opcode: VMLSv4i16
-/* 3112 */    MCD_OPC_FilterValue, 1, 76, 60, 0, // Skip to: 18553
-/* 3117 */    MCD_OPC_CheckPredicate, 21, 71, 60, 0, // Skip to: 18553
-/* 3122 */    MCD_OPC_Decode, 134, 14, 106, // Opcode: VMLSv8i16
-/* 3126 */    MCD_OPC_FilterValue, 231, 3, 61, 60, 0, // Skip to: 18553
-/* 3132 */    MCD_OPC_CheckPredicate, 22, 56, 60, 0, // Skip to: 18553
-/* 3137 */    MCD_OPC_CheckField, 6, 1, 1, 49, 60, 0, // Skip to: 18553
-/* 3144 */    MCD_OPC_Decode, 203, 14, 111, // Opcode: VMULslhq
-/* 3148 */    MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 3274
-/* 3153 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3156 */    MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 3178
-/* 3162 */    MCD_OPC_CheckPredicate, 21, 26, 60, 0, // Skip to: 18553
-/* 3167 */    MCD_OPC_CheckField, 6, 1, 0, 19, 60, 0, // Skip to: 18553
-/* 3174 */    MCD_OPC_Decode, 153, 15, 97, // Opcode: VPMAXs16
-/* 3178 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3215
-/* 3184 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3187 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3201
-/* 3192 */    MCD_OPC_CheckPredicate, 21, 252, 59, 0, // Skip to: 18553
-/* 3197 */    MCD_OPC_Decode, 240, 13, 104, // Opcode: VMLSLsv4i32
-/* 3201 */    MCD_OPC_FilterValue, 1, 243, 59, 0, // Skip to: 18553
-/* 3206 */    MCD_OPC_CheckPredicate, 21, 238, 59, 0, // Skip to: 18553
-/* 3211 */    MCD_OPC_Decode, 184, 14, 112, // Opcode: VMULLslsv4i16
-/* 3215 */    MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3237
-/* 3221 */    MCD_OPC_CheckPredicate, 21, 223, 59, 0, // Skip to: 18553
-/* 3226 */    MCD_OPC_CheckField, 6, 1, 0, 216, 59, 0, // Skip to: 18553
-/* 3233 */    MCD_OPC_Decode, 156, 15, 97, // Opcode: VPMAXu16
-/* 3237 */    MCD_OPC_FilterValue, 231, 3, 206, 59, 0, // Skip to: 18553
-/* 3243 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3246 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3260
-/* 3251 */    MCD_OPC_CheckPredicate, 21, 193, 59, 0, // Skip to: 18553
-/* 3256 */    MCD_OPC_Decode, 243, 13, 104, // Opcode: VMLSLuv4i32
-/* 3260 */    MCD_OPC_FilterValue, 1, 184, 59, 0, // Skip to: 18553
-/* 3265 */    MCD_OPC_CheckPredicate, 21, 179, 59, 0, // Skip to: 18553
-/* 3270 */    MCD_OPC_Decode, 186, 14, 112, // Opcode: VMULLsluv4i16
-/* 3274 */    MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 3393
-/* 3279 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3282 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3319
-/* 3288 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3291 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3305
-/* 3296 */    MCD_OPC_CheckPredicate, 21, 148, 59, 0, // Skip to: 18553
-/* 3301 */    MCD_OPC_Decode, 202, 15, 97, // Opcode: VQDMULHv4i16
-/* 3305 */    MCD_OPC_FilterValue, 1, 139, 59, 0, // Skip to: 18553
-/* 3310 */    MCD_OPC_CheckPredicate, 21, 134, 59, 0, // Skip to: 18553
-/* 3315 */    MCD_OPC_Decode, 204, 15, 98, // Opcode: VQDMULHv8i16
-/* 3319 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3356
-/* 3325 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3328 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3342
-/* 3333 */    MCD_OPC_CheckPredicate, 21, 111, 59, 0, // Skip to: 18553
-/* 3338 */    MCD_OPC_Decode, 196, 15, 104, // Opcode: VQDMLSLv4i32
-/* 3342 */    MCD_OPC_FilterValue, 1, 102, 59, 0, // Skip to: 18553
-/* 3347 */    MCD_OPC_CheckPredicate, 21, 97, 59, 0, // Skip to: 18553
-/* 3352 */    MCD_OPC_Decode, 206, 15, 112, // Opcode: VQDMULLslv4i16
-/* 3356 */    MCD_OPC_FilterValue, 230, 3, 87, 59, 0, // Skip to: 18553
-/* 3362 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3365 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3379
-/* 3370 */    MCD_OPC_CheckPredicate, 21, 74, 59, 0, // Skip to: 18553
-/* 3375 */    MCD_OPC_Decode, 245, 15, 97, // Opcode: VQRDMULHv4i16
-/* 3379 */    MCD_OPC_FilterValue, 1, 65, 59, 0, // Skip to: 18553
-/* 3384 */    MCD_OPC_CheckPredicate, 21, 60, 59, 0, // Skip to: 18553
-/* 3389 */    MCD_OPC_Decode, 247, 15, 98, // Opcode: VQRDMULHv8i16
-/* 3393 */    MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 3477
-/* 3398 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3401 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 3439
-/* 3406 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3409 */    MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3424
-/* 3415 */    MCD_OPC_CheckPredicate, 21, 29, 59, 0, // Skip to: 18553
-/* 3420 */    MCD_OPC_Decode, 188, 14, 99, // Opcode: VMULLsv4i32
-/* 3424 */    MCD_OPC_FilterValue, 231, 3, 19, 59, 0, // Skip to: 18553
-/* 3430 */    MCD_OPC_CheckPredicate, 21, 14, 59, 0, // Skip to: 18553
-/* 3435 */    MCD_OPC_Decode, 191, 14, 99, // Opcode: VMULLuv4i32
-/* 3439 */    MCD_OPC_FilterValue, 1, 5, 59, 0, // Skip to: 18553
-/* 3444 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3447 */    MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 3462
-/* 3453 */    MCD_OPC_CheckPredicate, 21, 247, 58, 0, // Skip to: 18553
-/* 3458 */    MCD_OPC_Decode, 198, 15, 110, // Opcode: VQDMULHslv4i16
-/* 3462 */    MCD_OPC_FilterValue, 231, 3, 237, 58, 0, // Skip to: 18553
-/* 3468 */    MCD_OPC_CheckPredicate, 21, 232, 58, 0, // Skip to: 18553
-/* 3473 */    MCD_OPC_Decode, 200, 15, 111, // Opcode: VQDMULHslv8i16
-/* 3477 */    MCD_OPC_FilterValue, 13, 121, 0, 0, // Skip to: 3603
-/* 3482 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3485 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3522
-/* 3491 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3494 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3508
-/* 3499 */    MCD_OPC_CheckPredicate, 22, 201, 58, 0, // Skip to: 18553
-/* 3504 */    MCD_OPC_Decode, 255, 7, 97, // Opcode: VADDhd
-/* 3508 */    MCD_OPC_FilterValue, 1, 192, 58, 0, // Skip to: 18553
-/* 3513 */    MCD_OPC_CheckPredicate, 22, 187, 58, 0, // Skip to: 18553
-/* 3518 */    MCD_OPC_Decode, 128, 8, 98, // Opcode: VADDhq
-/* 3522 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3559
-/* 3528 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3531 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3545
-/* 3536 */    MCD_OPC_CheckPredicate, 21, 164, 58, 0, // Skip to: 18553
-/* 3541 */    MCD_OPC_Decode, 208, 15, 99, // Opcode: VQDMULLv4i32
-/* 3545 */    MCD_OPC_FilterValue, 1, 155, 58, 0, // Skip to: 18553
-/* 3550 */    MCD_OPC_CheckPredicate, 21, 150, 58, 0, // Skip to: 18553
-/* 3555 */    MCD_OPC_Decode, 241, 15, 110, // Opcode: VQRDMULHslv4i16
-/* 3559 */    MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3581
-/* 3565 */    MCD_OPC_CheckPredicate, 22, 135, 58, 0, // Skip to: 18553
-/* 3570 */    MCD_OPC_CheckField, 6, 1, 0, 128, 58, 0, // Skip to: 18553
-/* 3577 */    MCD_OPC_Decode, 147, 15, 97, // Opcode: VPADDh
-/* 3581 */    MCD_OPC_FilterValue, 231, 3, 118, 58, 0, // Skip to: 18553
-/* 3587 */    MCD_OPC_CheckPredicate, 21, 113, 58, 0, // Skip to: 18553
-/* 3592 */    MCD_OPC_CheckField, 6, 1, 1, 106, 58, 0, // Skip to: 18553
-/* 3599 */    MCD_OPC_Decode, 243, 15, 111, // Opcode: VQRDMULHslv8i16
-/* 3603 */    MCD_OPC_FilterValue, 14, 121, 0, 0, // Skip to: 3729
-/* 3608 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3611 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3648
-/* 3617 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3620 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3634
-/* 3625 */    MCD_OPC_CheckPredicate, 22, 75, 58, 0, // Skip to: 18553
-/* 3630 */    MCD_OPC_Decode, 157, 8, 97, // Opcode: VCEQhd
-/* 3634 */    MCD_OPC_FilterValue, 1, 66, 58, 0, // Skip to: 18553
-/* 3639 */    MCD_OPC_CheckPredicate, 22, 61, 58, 0, // Skip to: 18553
-/* 3644 */    MCD_OPC_Decode, 158, 8, 98, // Opcode: VCEQhq
-/* 3648 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3670
-/* 3654 */    MCD_OPC_CheckPredicate, 23, 46, 58, 0, // Skip to: 18553
-/* 3659 */    MCD_OPC_CheckField, 6, 1, 1, 39, 58, 0, // Skip to: 18553
-/* 3666 */    MCD_OPC_Decode, 225, 15, 107, // Opcode: VQRDMLAHslv4i16
-/* 3670 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3707
-/* 3676 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3679 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3693
-/* 3684 */    MCD_OPC_CheckPredicate, 22, 16, 58, 0, // Skip to: 18553
-/* 3689 */    MCD_OPC_Decode, 177, 8, 97, // Opcode: VCGEhd
-/* 3693 */    MCD_OPC_FilterValue, 1, 7, 58, 0, // Skip to: 18553
-/* 3698 */    MCD_OPC_CheckPredicate, 22, 2, 58, 0, // Skip to: 18553
-/* 3703 */    MCD_OPC_Decode, 178, 8, 98, // Opcode: VCGEhq
-/* 3707 */    MCD_OPC_FilterValue, 231, 3, 248, 57, 0, // Skip to: 18553
-/* 3713 */    MCD_OPC_CheckPredicate, 23, 243, 57, 0, // Skip to: 18553
-/* 3718 */    MCD_OPC_CheckField, 6, 1, 1, 236, 57, 0, // Skip to: 18553
-/* 3725 */    MCD_OPC_Decode, 227, 15, 108, // Opcode: VQRDMLAHslv8i16
-/* 3729 */    MCD_OPC_FilterValue, 15, 227, 57, 0, // Skip to: 18553
-/* 3734 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3737 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3774
-/* 3743 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3746 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3760
-/* 3751 */    MCD_OPC_CheckPredicate, 22, 205, 57, 0, // Skip to: 18553
-/* 3756 */    MCD_OPC_Decode, 165, 13, 97, // Opcode: VMAXhd
-/* 3760 */    MCD_OPC_FilterValue, 1, 196, 57, 0, // Skip to: 18553
-/* 3765 */    MCD_OPC_CheckPredicate, 22, 191, 57, 0, // Skip to: 18553
-/* 3770 */    MCD_OPC_Decode, 166, 13, 98, // Opcode: VMAXhq
-/* 3774 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 3796
-/* 3780 */    MCD_OPC_CheckPredicate, 23, 176, 57, 0, // Skip to: 18553
-/* 3785 */    MCD_OPC_CheckField, 6, 1, 1, 169, 57, 0, // Skip to: 18553
-/* 3792 */    MCD_OPC_Decode, 233, 15, 107, // Opcode: VQRDMLSHslv4i16
-/* 3796 */    MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 3818
-/* 3802 */    MCD_OPC_CheckPredicate, 22, 154, 57, 0, // Skip to: 18553
-/* 3807 */    MCD_OPC_CheckField, 6, 1, 0, 147, 57, 0, // Skip to: 18553
-/* 3814 */    MCD_OPC_Decode, 152, 15, 97, // Opcode: VPMAXh
-/* 3818 */    MCD_OPC_FilterValue, 231, 3, 137, 57, 0, // Skip to: 18553
-/* 3824 */    MCD_OPC_CheckPredicate, 23, 132, 57, 0, // Skip to: 18553
-/* 3829 */    MCD_OPC_CheckField, 6, 1, 1, 125, 57, 0, // Skip to: 18553
-/* 3836 */    MCD_OPC_Decode, 235, 15, 108, // Opcode: VQRDMLSHslv8i16
-/* 3840 */    MCD_OPC_FilterValue, 2, 155, 8, 0, // Skip to: 6048
-/* 3845 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 3848 */    MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 4004
-/* 3853 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 3856 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 3893
-/* 3862 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3865 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3879
-/* 3870 */    MCD_OPC_CheckPredicate, 21, 86, 57, 0, // Skip to: 18553
-/* 3875 */    MCD_OPC_Decode, 175, 10, 97, // Opcode: VHADDsv2i32
-/* 3879 */    MCD_OPC_FilterValue, 1, 77, 57, 0, // Skip to: 18553
-/* 3884 */    MCD_OPC_CheckPredicate, 21, 72, 57, 0, // Skip to: 18553
-/* 3889 */    MCD_OPC_Decode, 177, 10, 98, // Opcode: VHADDsv4i32
-/* 3893 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 3930
-/* 3899 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3902 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3916
-/* 3907 */    MCD_OPC_CheckPredicate, 21, 49, 57, 0, // Skip to: 18553
-/* 3912 */    MCD_OPC_Decode, 240, 7, 99, // Opcode: VADDLsv2i64
-/* 3916 */    MCD_OPC_FilterValue, 1, 40, 57, 0, // Skip to: 18553
-/* 3921 */    MCD_OPC_CheckPredicate, 21, 35, 57, 0, // Skip to: 18553
-/* 3926 */    MCD_OPC_Decode, 223, 13, 113, // Opcode: VMLAslv2i32
-/* 3930 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 3967
-/* 3936 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3939 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3953
-/* 3944 */    MCD_OPC_CheckPredicate, 21, 12, 57, 0, // Skip to: 18553
-/* 3949 */    MCD_OPC_Decode, 181, 10, 97, // Opcode: VHADDuv2i32
-/* 3953 */    MCD_OPC_FilterValue, 1, 3, 57, 0, // Skip to: 18553
-/* 3958 */    MCD_OPC_CheckPredicate, 21, 254, 56, 0, // Skip to: 18553
-/* 3963 */    MCD_OPC_Decode, 183, 10, 98, // Opcode: VHADDuv4i32
-/* 3967 */    MCD_OPC_FilterValue, 231, 3, 244, 56, 0, // Skip to: 18553
-/* 3973 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 3976 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3990
-/* 3981 */    MCD_OPC_CheckPredicate, 21, 231, 56, 0, // Skip to: 18553
-/* 3986 */    MCD_OPC_Decode, 243, 7, 99, // Opcode: VADDLuv2i64
-/* 3990 */    MCD_OPC_FilterValue, 1, 222, 56, 0, // Skip to: 18553
-/* 3995 */    MCD_OPC_CheckPredicate, 21, 217, 56, 0, // Skip to: 18553
-/* 4000 */    MCD_OPC_Decode, 225, 13, 114, // Opcode: VMLAslv4i32
-/* 4004 */    MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 4160
-/* 4009 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4012 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4049
-/* 4018 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4021 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4035
-/* 4026 */    MCD_OPC_CheckPredicate, 21, 186, 56, 0, // Skip to: 18553
-/* 4031 */    MCD_OPC_Decode, 236, 16, 97, // Opcode: VRHADDsv2i32
-/* 4035 */    MCD_OPC_FilterValue, 1, 177, 56, 0, // Skip to: 18553
-/* 4040 */    MCD_OPC_CheckPredicate, 21, 172, 56, 0, // Skip to: 18553
-/* 4045 */    MCD_OPC_Decode, 238, 16, 98, // Opcode: VRHADDsv4i32
-/* 4049 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4086
-/* 4055 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4058 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4072
-/* 4063 */    MCD_OPC_CheckPredicate, 21, 149, 56, 0, // Skip to: 18553
-/* 4068 */    MCD_OPC_Decode, 247, 7, 100, // Opcode: VADDWsv2i64
-/* 4072 */    MCD_OPC_FilterValue, 1, 140, 56, 0, // Skip to: 18553
-/* 4077 */    MCD_OPC_CheckPredicate, 21, 135, 56, 0, // Skip to: 18553
-/* 4082 */    MCD_OPC_Decode, 219, 13, 113, // Opcode: VMLAslfd
-/* 4086 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4123
-/* 4092 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4095 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109
-/* 4100 */    MCD_OPC_CheckPredicate, 21, 112, 56, 0, // Skip to: 18553
-/* 4105 */    MCD_OPC_Decode, 242, 16, 97, // Opcode: VRHADDuv2i32
-/* 4109 */    MCD_OPC_FilterValue, 1, 103, 56, 0, // Skip to: 18553
-/* 4114 */    MCD_OPC_CheckPredicate, 21, 98, 56, 0, // Skip to: 18553
-/* 4119 */    MCD_OPC_Decode, 244, 16, 98, // Opcode: VRHADDuv4i32
-/* 4123 */    MCD_OPC_FilterValue, 231, 3, 88, 56, 0, // Skip to: 18553
-/* 4129 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4132 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4146
-/* 4137 */    MCD_OPC_CheckPredicate, 21, 75, 56, 0, // Skip to: 18553
-/* 4142 */    MCD_OPC_Decode, 250, 7, 100, // Opcode: VADDWuv2i64
-/* 4146 */    MCD_OPC_FilterValue, 1, 66, 56, 0, // Skip to: 18553
-/* 4151 */    MCD_OPC_CheckPredicate, 21, 61, 56, 0, // Skip to: 18553
-/* 4156 */    MCD_OPC_Decode, 220, 13, 114, // Opcode: VMLAslfq
-/* 4160 */    MCD_OPC_FilterValue, 2, 151, 0, 0, // Skip to: 4316
-/* 4165 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4168 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4205
-/* 4174 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4177 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4191
-/* 4182 */    MCD_OPC_CheckPredicate, 21, 30, 56, 0, // Skip to: 18553
-/* 4187 */    MCD_OPC_Decode, 187, 10, 97, // Opcode: VHSUBsv2i32
-/* 4191 */    MCD_OPC_FilterValue, 1, 21, 56, 0, // Skip to: 18553
-/* 4196 */    MCD_OPC_CheckPredicate, 21, 16, 56, 0, // Skip to: 18553
-/* 4201 */    MCD_OPC_Decode, 189, 10, 98, // Opcode: VHSUBsv4i32
-/* 4205 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4242
+/* 36 */      MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51
+/* 41 */      MCD_OPC_CheckPredicate, 26, 241, 74, 0, // Skip to: 19231
+/* 46 */      MCD_OPC_Decode, 242, 18, 202, 1, // Opcode: VHADDsv8i8
+/* 51 */      MCD_OPC_FilterValue, 1, 231, 74, 0, // Skip to: 19231
+/* 56 */      MCD_OPC_CheckPredicate, 26, 226, 74, 0, // Skip to: 19231
+/* 61 */      MCD_OPC_Decode, 237, 18, 203, 1, // Opcode: VHADDsv16i8
+/* 66 */      MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 89
+/* 72 */      MCD_OPC_CheckPredicate, 26, 210, 74, 0, // Skip to: 19231
+/* 77 */      MCD_OPC_CheckField, 6, 1, 0, 203, 74, 0, // Skip to: 19231
+/* 84 */      MCD_OPC_Decode, 157, 16, 204, 1, // Opcode: VADDLsv8i16
+/* 89 */      MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 128
+/* 95 */      MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 98 */      MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 113
+/* 103 */     MCD_OPC_CheckPredicate, 26, 179, 74, 0, // Skip to: 19231
+/* 108 */     MCD_OPC_Decode, 248, 18, 202, 1, // Opcode: VHADDuv8i8
+/* 113 */     MCD_OPC_FilterValue, 1, 169, 74, 0, // Skip to: 19231
+/* 118 */     MCD_OPC_CheckPredicate, 26, 164, 74, 0, // Skip to: 19231
+/* 123 */     MCD_OPC_Decode, 243, 18, 203, 1, // Opcode: VHADDuv16i8
+/* 128 */     MCD_OPC_FilterValue, 231, 3, 153, 74, 0, // Skip to: 19231
+/* 134 */     MCD_OPC_CheckPredicate, 26, 148, 74, 0, // Skip to: 19231
+/* 139 */     MCD_OPC_CheckField, 6, 1, 0, 141, 74, 0, // Skip to: 19231
+/* 146 */     MCD_OPC_Decode, 160, 16, 204, 1, // Opcode: VADDLuv8i16
+/* 151 */     MCD_OPC_FilterValue, 1, 127, 0, 0, // Skip to: 283
+/* 156 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 159 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 198
+/* 165 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 168 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 183
+/* 173 */     MCD_OPC_CheckPredicate, 26, 109, 74, 0, // Skip to: 19231
+/* 178 */     MCD_OPC_Decode, 222, 25, 202, 1, // Opcode: VRHADDsv8i8
+/* 183 */     MCD_OPC_FilterValue, 1, 99, 74, 0, // Skip to: 19231
+/* 188 */     MCD_OPC_CheckPredicate, 26, 94, 74, 0, // Skip to: 19231
+/* 193 */     MCD_OPC_Decode, 217, 25, 203, 1, // Opcode: VRHADDsv16i8
+/* 198 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 221
+/* 204 */     MCD_OPC_CheckPredicate, 26, 78, 74, 0, // Skip to: 19231
+/* 209 */     MCD_OPC_CheckField, 6, 1, 0, 71, 74, 0, // Skip to: 19231
+/* 216 */     MCD_OPC_Decode, 164, 16, 205, 1, // Opcode: VADDWsv8i16
+/* 221 */     MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 260
+/* 227 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 230 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 245
+/* 235 */     MCD_OPC_CheckPredicate, 26, 47, 74, 0, // Skip to: 19231
+/* 240 */     MCD_OPC_Decode, 228, 25, 202, 1, // Opcode: VRHADDuv8i8
+/* 245 */     MCD_OPC_FilterValue, 1, 37, 74, 0, // Skip to: 19231
+/* 250 */     MCD_OPC_CheckPredicate, 26, 32, 74, 0, // Skip to: 19231
+/* 255 */     MCD_OPC_Decode, 223, 25, 203, 1, // Opcode: VRHADDuv16i8
+/* 260 */     MCD_OPC_FilterValue, 231, 3, 21, 74, 0, // Skip to: 19231
+/* 266 */     MCD_OPC_CheckPredicate, 26, 16, 74, 0, // Skip to: 19231
+/* 271 */     MCD_OPC_CheckField, 6, 1, 0, 9, 74, 0, // Skip to: 19231
+/* 278 */     MCD_OPC_Decode, 167, 16, 205, 1, // Opcode: VADDWuv8i16
+/* 283 */     MCD_OPC_FilterValue, 2, 127, 0, 0, // Skip to: 415
+/* 288 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 291 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 330
+/* 297 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 300 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 315
+/* 305 */     MCD_OPC_CheckPredicate, 26, 233, 73, 0, // Skip to: 19231
+/* 310 */     MCD_OPC_Decode, 254, 18, 202, 1, // Opcode: VHSUBsv8i8
+/* 315 */     MCD_OPC_FilterValue, 1, 223, 73, 0, // Skip to: 19231
+/* 320 */     MCD_OPC_CheckPredicate, 26, 218, 73, 0, // Skip to: 19231
+/* 325 */     MCD_OPC_Decode, 249, 18, 203, 1, // Opcode: VHSUBsv16i8
+/* 330 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 353
+/* 336 */     MCD_OPC_CheckPredicate, 26, 202, 73, 0, // Skip to: 19231
+/* 341 */     MCD_OPC_CheckField, 6, 1, 0, 195, 73, 0, // Skip to: 19231
+/* 348 */     MCD_OPC_Decode, 237, 29, 204, 1, // Opcode: VSUBLsv8i16
+/* 353 */     MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 392
+/* 359 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 362 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 377
+/* 367 */     MCD_OPC_CheckPredicate, 26, 171, 73, 0, // Skip to: 19231
+/* 372 */     MCD_OPC_Decode, 132, 19, 202, 1, // Opcode: VHSUBuv8i8
+/* 377 */     MCD_OPC_FilterValue, 1, 161, 73, 0, // Skip to: 19231
+/* 382 */     MCD_OPC_CheckPredicate, 26, 156, 73, 0, // Skip to: 19231
+/* 387 */     MCD_OPC_Decode, 255, 18, 203, 1, // Opcode: VHSUBuv16i8
+/* 392 */     MCD_OPC_FilterValue, 231, 3, 145, 73, 0, // Skip to: 19231
+/* 398 */     MCD_OPC_CheckPredicate, 26, 140, 73, 0, // Skip to: 19231
+/* 403 */     MCD_OPC_CheckField, 6, 1, 0, 133, 73, 0, // Skip to: 19231
+/* 410 */     MCD_OPC_Decode, 240, 29, 204, 1, // Opcode: VSUBLuv8i16
+/* 415 */     MCD_OPC_FilterValue, 3, 127, 0, 0, // Skip to: 547
+/* 420 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 423 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 462
+/* 429 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 432 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 447
+/* 437 */     MCD_OPC_CheckPredicate, 26, 101, 73, 0, // Skip to: 19231
+/* 442 */     MCD_OPC_Decode, 131, 17, 202, 1, // Opcode: VCGTsv8i8
+/* 447 */     MCD_OPC_FilterValue, 1, 91, 73, 0, // Skip to: 19231
+/* 452 */     MCD_OPC_CheckPredicate, 26, 86, 73, 0, // Skip to: 19231
+/* 457 */     MCD_OPC_Decode, 254, 16, 203, 1, // Opcode: VCGTsv16i8
+/* 462 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 485
+/* 468 */     MCD_OPC_CheckPredicate, 26, 70, 73, 0, // Skip to: 19231
+/* 473 */     MCD_OPC_CheckField, 6, 1, 0, 63, 73, 0, // Skip to: 19231
+/* 480 */     MCD_OPC_Decode, 244, 29, 205, 1, // Opcode: VSUBWsv8i16
+/* 485 */     MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 524
+/* 491 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 494 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 509
+/* 499 */     MCD_OPC_CheckPredicate, 26, 39, 73, 0, // Skip to: 19231
+/* 504 */     MCD_OPC_Decode, 137, 17, 202, 1, // Opcode: VCGTuv8i8
+/* 509 */     MCD_OPC_FilterValue, 1, 29, 73, 0, // Skip to: 19231
+/* 514 */     MCD_OPC_CheckPredicate, 26, 24, 73, 0, // Skip to: 19231
+/* 519 */     MCD_OPC_Decode, 132, 17, 203, 1, // Opcode: VCGTuv16i8
+/* 524 */     MCD_OPC_FilterValue, 231, 3, 13, 73, 0, // Skip to: 19231
+/* 530 */     MCD_OPC_CheckPredicate, 26, 8, 73, 0, // Skip to: 19231
+/* 535 */     MCD_OPC_CheckField, 6, 1, 0, 1, 73, 0, // Skip to: 19231
+/* 542 */     MCD_OPC_Decode, 247, 29, 205, 1, // Opcode: VSUBWuv8i16
+/* 547 */     MCD_OPC_FilterValue, 4, 127, 0, 0, // Skip to: 679
+/* 552 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 555 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 594
+/* 561 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 564 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 579
+/* 569 */     MCD_OPC_CheckPredicate, 26, 225, 72, 0, // Skip to: 19231
+/* 574 */     MCD_OPC_Decode, 255, 26, 206, 1, // Opcode: VSHLsv8i8
+/* 579 */     MCD_OPC_FilterValue, 1, 215, 72, 0, // Skip to: 19231
+/* 584 */     MCD_OPC_CheckPredicate, 26, 210, 72, 0, // Skip to: 19231
+/* 589 */     MCD_OPC_Decode, 248, 26, 207, 1, // Opcode: VSHLsv16i8
+/* 594 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 617
+/* 600 */     MCD_OPC_CheckPredicate, 26, 194, 72, 0, // Skip to: 19231
+/* 605 */     MCD_OPC_CheckField, 6, 1, 0, 187, 72, 0, // Skip to: 19231
+/* 612 */     MCD_OPC_Decode, 154, 16, 208, 1, // Opcode: VADDHNv8i8
+/* 617 */     MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 656
+/* 623 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 626 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 641
+/* 631 */     MCD_OPC_CheckPredicate, 26, 163, 72, 0, // Skip to: 19231
+/* 636 */     MCD_OPC_Decode, 135, 27, 206, 1, // Opcode: VSHLuv8i8
+/* 641 */     MCD_OPC_FilterValue, 1, 153, 72, 0, // Skip to: 19231
+/* 646 */     MCD_OPC_CheckPredicate, 26, 148, 72, 0, // Skip to: 19231
+/* 651 */     MCD_OPC_Decode, 128, 27, 207, 1, // Opcode: VSHLuv16i8
+/* 656 */     MCD_OPC_FilterValue, 231, 3, 137, 72, 0, // Skip to: 19231
+/* 662 */     MCD_OPC_CheckPredicate, 26, 132, 72, 0, // Skip to: 19231
+/* 667 */     MCD_OPC_CheckField, 6, 1, 0, 125, 72, 0, // Skip to: 19231
+/* 674 */     MCD_OPC_Decode, 194, 25, 208, 1, // Opcode: VRADDHNv8i8
+/* 679 */     MCD_OPC_FilterValue, 5, 127, 0, 0, // Skip to: 811
+/* 684 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 687 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 726
+/* 693 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 696 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 711
+/* 701 */     MCD_OPC_CheckPredicate, 26, 93, 72, 0, // Skip to: 19231
+/* 706 */     MCD_OPC_Decode, 153, 26, 206, 1, // Opcode: VRSHLsv8i8
+/* 711 */     MCD_OPC_FilterValue, 1, 83, 72, 0, // Skip to: 19231
+/* 716 */     MCD_OPC_CheckPredicate, 26, 78, 72, 0, // Skip to: 19231
+/* 721 */     MCD_OPC_Decode, 146, 26, 207, 1, // Opcode: VRSHLsv16i8
+/* 726 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 749
+/* 732 */     MCD_OPC_CheckPredicate, 26, 62, 72, 0, // Skip to: 19231
+/* 737 */     MCD_OPC_CheckField, 6, 1, 0, 55, 72, 0, // Skip to: 19231
+/* 744 */     MCD_OPC_Decode, 219, 15, 209, 1, // Opcode: VABALsv8i16
+/* 749 */     MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 788
+/* 755 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 758 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 773
+/* 763 */     MCD_OPC_CheckPredicate, 26, 31, 72, 0, // Skip to: 19231
+/* 768 */     MCD_OPC_Decode, 161, 26, 206, 1, // Opcode: VRSHLuv8i8
+/* 773 */     MCD_OPC_FilterValue, 1, 21, 72, 0, // Skip to: 19231
+/* 778 */     MCD_OPC_CheckPredicate, 26, 16, 72, 0, // Skip to: 19231
+/* 783 */     MCD_OPC_Decode, 154, 26, 207, 1, // Opcode: VRSHLuv16i8
+/* 788 */     MCD_OPC_FilterValue, 231, 3, 5, 72, 0, // Skip to: 19231
+/* 794 */     MCD_OPC_CheckPredicate, 26, 0, 72, 0, // Skip to: 19231
+/* 799 */     MCD_OPC_CheckField, 6, 1, 0, 249, 71, 0, // Skip to: 19231
+/* 806 */     MCD_OPC_Decode, 222, 15, 209, 1, // Opcode: VABALuv8i16
+/* 811 */     MCD_OPC_FilterValue, 6, 127, 0, 0, // Skip to: 943
+/* 816 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 819 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 858
+/* 825 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 828 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 843
+/* 833 */     MCD_OPC_CheckPredicate, 26, 217, 71, 0, // Skip to: 19231
+/* 838 */     MCD_OPC_Decode, 150, 22, 202, 1, // Opcode: VMAXsv8i8
+/* 843 */     MCD_OPC_FilterValue, 1, 207, 71, 0, // Skip to: 19231
+/* 848 */     MCD_OPC_CheckPredicate, 26, 202, 71, 0, // Skip to: 19231
+/* 853 */     MCD_OPC_Decode, 145, 22, 203, 1, // Opcode: VMAXsv16i8
+/* 858 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 881
+/* 864 */     MCD_OPC_CheckPredicate, 26, 186, 71, 0, // Skip to: 19231
+/* 869 */     MCD_OPC_CheckField, 6, 1, 0, 179, 71, 0, // Skip to: 19231
+/* 876 */     MCD_OPC_Decode, 234, 29, 208, 1, // Opcode: VSUBHNv8i8
+/* 881 */     MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 920
+/* 887 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 890 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 905
+/* 895 */     MCD_OPC_CheckPredicate, 26, 155, 71, 0, // Skip to: 19231
+/* 900 */     MCD_OPC_Decode, 156, 22, 202, 1, // Opcode: VMAXuv8i8
+/* 905 */     MCD_OPC_FilterValue, 1, 145, 71, 0, // Skip to: 19231
+/* 910 */     MCD_OPC_CheckPredicate, 26, 140, 71, 0, // Skip to: 19231
+/* 915 */     MCD_OPC_Decode, 151, 22, 203, 1, // Opcode: VMAXuv16i8
+/* 920 */     MCD_OPC_FilterValue, 231, 3, 129, 71, 0, // Skip to: 19231
+/* 926 */     MCD_OPC_CheckPredicate, 26, 124, 71, 0, // Skip to: 19231
+/* 931 */     MCD_OPC_CheckField, 6, 1, 0, 117, 71, 0, // Skip to: 19231
+/* 938 */     MCD_OPC_Decode, 209, 26, 208, 1, // Opcode: VRSUBHNv8i8
+/* 943 */     MCD_OPC_FilterValue, 7, 127, 0, 0, // Skip to: 1075
+/* 948 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 951 */     MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 990
+/* 957 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 960 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 975
+/* 965 */     MCD_OPC_CheckPredicate, 26, 85, 71, 0, // Skip to: 19231
+/* 970 */     MCD_OPC_Decode, 250, 15, 202, 1, // Opcode: VABDsv8i8
+/* 975 */     MCD_OPC_FilterValue, 1, 75, 71, 0, // Skip to: 19231
+/* 980 */     MCD_OPC_CheckPredicate, 26, 70, 71, 0, // Skip to: 19231
+/* 985 */     MCD_OPC_Decode, 245, 15, 203, 1, // Opcode: VABDsv16i8
+/* 990 */     MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 1013
+/* 996 */     MCD_OPC_CheckPredicate, 26, 54, 71, 0, // Skip to: 19231
+/* 1001 */    MCD_OPC_CheckField, 6, 1, 0, 47, 71, 0, // Skip to: 19231
+/* 1008 */    MCD_OPC_Decode, 237, 15, 204, 1, // Opcode: VABDLsv8i16
+/* 1013 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 1052
+/* 1019 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1022 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1037
+/* 1027 */    MCD_OPC_CheckPredicate, 26, 23, 71, 0, // Skip to: 19231
+/* 1032 */    MCD_OPC_Decode, 128, 16, 202, 1, // Opcode: VABDuv8i8
+/* 1037 */    MCD_OPC_FilterValue, 1, 13, 71, 0, // Skip to: 19231
+/* 1042 */    MCD_OPC_CheckPredicate, 26, 8, 71, 0, // Skip to: 19231
+/* 1047 */    MCD_OPC_Decode, 251, 15, 203, 1, // Opcode: VABDuv16i8
+/* 1052 */    MCD_OPC_FilterValue, 231, 3, 253, 70, 0, // Skip to: 19231
+/* 1058 */    MCD_OPC_CheckPredicate, 26, 248, 70, 0, // Skip to: 19231
+/* 1063 */    MCD_OPC_CheckField, 6, 1, 0, 241, 70, 0, // Skip to: 19231
+/* 1070 */    MCD_OPC_Decode, 240, 15, 204, 1, // Opcode: VABDLuv8i16
+/* 1075 */    MCD_OPC_FilterValue, 8, 127, 0, 0, // Skip to: 1207
+/* 1080 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1083 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 1122
+/* 1089 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1092 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1107
+/* 1097 */    MCD_OPC_CheckPredicate, 26, 209, 70, 0, // Skip to: 19231
+/* 1102 */    MCD_OPC_Decode, 179, 16, 202, 1, // Opcode: VADDv8i8
+/* 1107 */    MCD_OPC_FilterValue, 1, 199, 70, 0, // Skip to: 19231
+/* 1112 */    MCD_OPC_CheckPredicate, 26, 194, 70, 0, // Skip to: 19231
+/* 1117 */    MCD_OPC_Decode, 172, 16, 203, 1, // Opcode: VADDv16i8
+/* 1122 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 1145
+/* 1128 */    MCD_OPC_CheckPredicate, 26, 178, 70, 0, // Skip to: 19231
+/* 1133 */    MCD_OPC_CheckField, 6, 1, 0, 171, 70, 0, // Skip to: 19231
+/* 1140 */    MCD_OPC_Decode, 181, 22, 209, 1, // Opcode: VMLALsv8i16
+/* 1145 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 1184
+/* 1151 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1154 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1169
+/* 1159 */    MCD_OPC_CheckPredicate, 26, 147, 70, 0, // Skip to: 19231
+/* 1164 */    MCD_OPC_Decode, 131, 30, 202, 1, // Opcode: VSUBv8i8
+/* 1169 */    MCD_OPC_FilterValue, 1, 137, 70, 0, // Skip to: 19231
+/* 1174 */    MCD_OPC_CheckPredicate, 26, 132, 70, 0, // Skip to: 19231
+/* 1179 */    MCD_OPC_Decode, 252, 29, 203, 1, // Opcode: VSUBv16i8
+/* 1184 */    MCD_OPC_FilterValue, 231, 3, 121, 70, 0, // Skip to: 19231
+/* 1190 */    MCD_OPC_CheckPredicate, 26, 116, 70, 0, // Skip to: 19231
+/* 1195 */    MCD_OPC_CheckField, 6, 1, 0, 109, 70, 0, // Skip to: 19231
+/* 1202 */    MCD_OPC_Decode, 184, 22, 209, 1, // Opcode: VMLALuv8i16
+/* 1207 */    MCD_OPC_FilterValue, 9, 83, 0, 0, // Skip to: 1295
+/* 1212 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1215 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1255
+/* 1220 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1223 */    MCD_OPC_FilterValue, 228, 3, 10, 0, 0, // Skip to: 1239
+/* 1229 */    MCD_OPC_CheckPredicate, 26, 77, 70, 0, // Skip to: 19231
+/* 1234 */    MCD_OPC_Decode, 203, 22, 210, 1, // Opcode: VMLAv8i8
+/* 1239 */    MCD_OPC_FilterValue, 230, 3, 66, 70, 0, // Skip to: 19231
+/* 1245 */    MCD_OPC_CheckPredicate, 26, 61, 70, 0, // Skip to: 19231
+/* 1250 */    MCD_OPC_Decode, 234, 22, 210, 1, // Opcode: VMLSv8i8
+/* 1255 */    MCD_OPC_FilterValue, 1, 51, 70, 0, // Skip to: 19231
+/* 1260 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1263 */    MCD_OPC_FilterValue, 228, 3, 10, 0, 0, // Skip to: 1279
+/* 1269 */    MCD_OPC_CheckPredicate, 26, 37, 70, 0, // Skip to: 19231
+/* 1274 */    MCD_OPC_Decode, 198, 22, 211, 1, // Opcode: VMLAv16i8
+/* 1279 */    MCD_OPC_FilterValue, 230, 3, 26, 70, 0, // Skip to: 19231
+/* 1285 */    MCD_OPC_CheckPredicate, 26, 21, 70, 0, // Skip to: 19231
+/* 1290 */    MCD_OPC_Decode, 229, 22, 211, 1, // Opcode: VMLSv16i8
+/* 1295 */    MCD_OPC_FilterValue, 10, 95, 0, 0, // Skip to: 1395
+/* 1300 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1303 */    MCD_OPC_FilterValue, 228, 3, 17, 0, 0, // Skip to: 1326
+/* 1309 */    MCD_OPC_CheckPredicate, 26, 253, 69, 0, // Skip to: 19231
+/* 1314 */    MCD_OPC_CheckField, 6, 1, 0, 246, 69, 0, // Skip to: 19231
+/* 1321 */    MCD_OPC_Decode, 137, 24, 202, 1, // Opcode: VPMAXs8
+/* 1326 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 1349
+/* 1332 */    MCD_OPC_CheckPredicate, 26, 230, 69, 0, // Skip to: 19231
+/* 1337 */    MCD_OPC_CheckField, 6, 1, 0, 223, 69, 0, // Skip to: 19231
+/* 1344 */    MCD_OPC_Decode, 212, 22, 209, 1, // Opcode: VMLSLsv8i16
+/* 1349 */    MCD_OPC_FilterValue, 230, 3, 17, 0, 0, // Skip to: 1372
+/* 1355 */    MCD_OPC_CheckPredicate, 26, 207, 69, 0, // Skip to: 19231
+/* 1360 */    MCD_OPC_CheckField, 6, 1, 0, 200, 69, 0, // Skip to: 19231
+/* 1367 */    MCD_OPC_Decode, 140, 24, 202, 1, // Opcode: VPMAXu8
+/* 1372 */    MCD_OPC_FilterValue, 231, 3, 189, 69, 0, // Skip to: 19231
+/* 1378 */    MCD_OPC_CheckPredicate, 26, 184, 69, 0, // Skip to: 19231
+/* 1383 */    MCD_OPC_CheckField, 6, 1, 0, 177, 69, 0, // Skip to: 19231
+/* 1390 */    MCD_OPC_Decode, 215, 22, 209, 1, // Opcode: VMLSLuv8i16
+/* 1395 */    MCD_OPC_FilterValue, 12, 49, 0, 0, // Skip to: 1449
+/* 1400 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1403 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 1426
+/* 1409 */    MCD_OPC_CheckPredicate, 26, 153, 69, 0, // Skip to: 19231
+/* 1414 */    MCD_OPC_CheckField, 6, 1, 0, 146, 69, 0, // Skip to: 19231
+/* 1421 */    MCD_OPC_Decode, 171, 23, 204, 1, // Opcode: VMULLsv8i16
+/* 1426 */    MCD_OPC_FilterValue, 231, 3, 135, 69, 0, // Skip to: 19231
+/* 1432 */    MCD_OPC_CheckPredicate, 26, 130, 69, 0, // Skip to: 19231
+/* 1437 */    MCD_OPC_CheckField, 6, 1, 0, 123, 69, 0, // Skip to: 19231
+/* 1444 */    MCD_OPC_Decode, 174, 23, 204, 1, // Opcode: VMULLuv8i16
+/* 1449 */    MCD_OPC_FilterValue, 13, 66, 0, 0, // Skip to: 1520
+/* 1454 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1457 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1497
+/* 1462 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1465 */    MCD_OPC_FilterValue, 228, 3, 10, 0, 0, // Skip to: 1481
+/* 1471 */    MCD_OPC_CheckPredicate, 26, 91, 69, 0, // Skip to: 19231
+/* 1476 */    MCD_OPC_Decode, 168, 16, 202, 1, // Opcode: VADDfd
+/* 1481 */    MCD_OPC_FilterValue, 230, 3, 80, 69, 0, // Skip to: 19231
+/* 1487 */    MCD_OPC_CheckPredicate, 26, 75, 69, 0, // Skip to: 19231
+/* 1492 */    MCD_OPC_Decode, 128, 24, 202, 1, // Opcode: VPADDf
+/* 1497 */    MCD_OPC_FilterValue, 1, 65, 69, 0, // Skip to: 19231
+/* 1502 */    MCD_OPC_CheckPredicate, 26, 60, 69, 0, // Skip to: 19231
+/* 1507 */    MCD_OPC_CheckField, 23, 9, 228, 3, 52, 69, 0, // Skip to: 19231
+/* 1515 */    MCD_OPC_Decode, 169, 16, 203, 1, // Opcode: VADDfq
+/* 1520 */    MCD_OPC_FilterValue, 14, 104, 0, 0, // Skip to: 1629
+/* 1525 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1528 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 1567
+/* 1534 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1537 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1552
+/* 1542 */    MCD_OPC_CheckPredicate, 26, 20, 69, 0, // Skip to: 19231
+/* 1547 */    MCD_OPC_Decode, 204, 16, 202, 1, // Opcode: VCEQfd
+/* 1552 */    MCD_OPC_FilterValue, 1, 10, 69, 0, // Skip to: 19231
+/* 1557 */    MCD_OPC_CheckPredicate, 26, 5, 69, 0, // Skip to: 19231
+/* 1562 */    MCD_OPC_Decode, 205, 16, 203, 1, // Opcode: VCEQfq
+/* 1567 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 1590
+/* 1573 */    MCD_OPC_CheckPredicate, 26, 245, 68, 0, // Skip to: 19231
+/* 1578 */    MCD_OPC_CheckField, 6, 1, 0, 238, 68, 0, // Skip to: 19231
+/* 1585 */    MCD_OPC_Decode, 164, 23, 204, 1, // Opcode: VMULLp8
+/* 1590 */    MCD_OPC_FilterValue, 230, 3, 227, 68, 0, // Skip to: 19231
+/* 1596 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1599 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1614
+/* 1604 */    MCD_OPC_CheckPredicate, 26, 214, 68, 0, // Skip to: 19231
+/* 1609 */    MCD_OPC_Decode, 224, 16, 202, 1, // Opcode: VCGEfd
+/* 1614 */    MCD_OPC_FilterValue, 1, 204, 68, 0, // Skip to: 19231
+/* 1619 */    MCD_OPC_CheckPredicate, 26, 199, 68, 0, // Skip to: 19231
+/* 1624 */    MCD_OPC_Decode, 225, 16, 203, 1, // Opcode: VCGEfq
+/* 1629 */    MCD_OPC_FilterValue, 15, 189, 68, 0, // Skip to: 19231
+/* 1634 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1637 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1677
+/* 1642 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1645 */    MCD_OPC_FilterValue, 228, 3, 10, 0, 0, // Skip to: 1661
+/* 1651 */    MCD_OPC_CheckPredicate, 26, 167, 68, 0, // Skip to: 19231
+/* 1656 */    MCD_OPC_Decode, 141, 22, 202, 1, // Opcode: VMAXfd
+/* 1661 */    MCD_OPC_FilterValue, 230, 3, 156, 68, 0, // Skip to: 19231
+/* 1667 */    MCD_OPC_CheckPredicate, 26, 151, 68, 0, // Skip to: 19231
+/* 1672 */    MCD_OPC_Decode, 133, 24, 202, 1, // Opcode: VPMAXf
+/* 1677 */    MCD_OPC_FilterValue, 1, 141, 68, 0, // Skip to: 19231
+/* 1682 */    MCD_OPC_CheckPredicate, 26, 136, 68, 0, // Skip to: 19231
+/* 1687 */    MCD_OPC_CheckField, 23, 9, 228, 3, 128, 68, 0, // Skip to: 19231
+/* 1695 */    MCD_OPC_Decode, 142, 22, 203, 1, // Opcode: VMAXfq
+/* 1700 */    MCD_OPC_FilterValue, 1, 16, 9, 0, // Skip to: 4025
+/* 1705 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 1708 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 1872
+/* 1713 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1716 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 1755
+/* 1722 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1725 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1740
+/* 1730 */    MCD_OPC_CheckPredicate, 26, 88, 68, 0, // Skip to: 19231
+/* 1735 */    MCD_OPC_Decode, 239, 18, 202, 1, // Opcode: VHADDsv4i16
+/* 1740 */    MCD_OPC_FilterValue, 1, 78, 68, 0, // Skip to: 19231
+/* 1745 */    MCD_OPC_CheckPredicate, 26, 73, 68, 0, // Skip to: 19231
+/* 1750 */    MCD_OPC_Decode, 241, 18, 203, 1, // Opcode: VHADDsv8i16
+/* 1755 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 1794
+/* 1761 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1764 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1779
+/* 1769 */    MCD_OPC_CheckPredicate, 26, 49, 68, 0, // Skip to: 19231
+/* 1774 */    MCD_OPC_Decode, 156, 16, 204, 1, // Opcode: VADDLsv4i32
+/* 1779 */    MCD_OPC_FilterValue, 1, 39, 68, 0, // Skip to: 19231
+/* 1784 */    MCD_OPC_CheckPredicate, 26, 34, 68, 0, // Skip to: 19231
+/* 1789 */    MCD_OPC_Decode, 195, 22, 212, 1, // Opcode: VMLAslv4i16
+/* 1794 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 1833
+/* 1800 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1803 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1818
+/* 1808 */    MCD_OPC_CheckPredicate, 26, 10, 68, 0, // Skip to: 19231
+/* 1813 */    MCD_OPC_Decode, 245, 18, 202, 1, // Opcode: VHADDuv4i16
+/* 1818 */    MCD_OPC_FilterValue, 1, 0, 68, 0, // Skip to: 19231
+/* 1823 */    MCD_OPC_CheckPredicate, 26, 251, 67, 0, // Skip to: 19231
+/* 1828 */    MCD_OPC_Decode, 247, 18, 203, 1, // Opcode: VHADDuv8i16
+/* 1833 */    MCD_OPC_FilterValue, 231, 3, 240, 67, 0, // Skip to: 19231
+/* 1839 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1842 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1857
+/* 1847 */    MCD_OPC_CheckPredicate, 26, 227, 67, 0, // Skip to: 19231
+/* 1852 */    MCD_OPC_Decode, 159, 16, 204, 1, // Opcode: VADDLuv4i32
+/* 1857 */    MCD_OPC_FilterValue, 1, 217, 67, 0, // Skip to: 19231
+/* 1862 */    MCD_OPC_CheckPredicate, 26, 212, 67, 0, // Skip to: 19231
+/* 1867 */    MCD_OPC_Decode, 197, 22, 213, 1, // Opcode: VMLAslv8i16
+/* 1872 */    MCD_OPC_FilterValue, 1, 159, 0, 0, // Skip to: 2036
+/* 1877 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1880 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 1919
+/* 1886 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1889 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1904
+/* 1894 */    MCD_OPC_CheckPredicate, 26, 180, 67, 0, // Skip to: 19231
+/* 1899 */    MCD_OPC_Decode, 219, 25, 202, 1, // Opcode: VRHADDsv4i16
+/* 1904 */    MCD_OPC_FilterValue, 1, 170, 67, 0, // Skip to: 19231
+/* 1909 */    MCD_OPC_CheckPredicate, 26, 165, 67, 0, // Skip to: 19231
+/* 1914 */    MCD_OPC_Decode, 221, 25, 203, 1, // Opcode: VRHADDsv8i16
+/* 1919 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 1958
+/* 1925 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1928 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1943
+/* 1933 */    MCD_OPC_CheckPredicate, 26, 141, 67, 0, // Skip to: 19231
+/* 1938 */    MCD_OPC_Decode, 163, 16, 205, 1, // Opcode: VADDWsv4i32
+/* 1943 */    MCD_OPC_FilterValue, 1, 131, 67, 0, // Skip to: 19231
+/* 1948 */    MCD_OPC_CheckPredicate, 27, 126, 67, 0, // Skip to: 19231
+/* 1953 */    MCD_OPC_Decode, 192, 22, 212, 1, // Opcode: VMLAslhd
+/* 1958 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 1997
+/* 1964 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1967 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1982
+/* 1972 */    MCD_OPC_CheckPredicate, 26, 102, 67, 0, // Skip to: 19231
+/* 1977 */    MCD_OPC_Decode, 225, 25, 202, 1, // Opcode: VRHADDuv4i16
+/* 1982 */    MCD_OPC_FilterValue, 1, 92, 67, 0, // Skip to: 19231
+/* 1987 */    MCD_OPC_CheckPredicate, 26, 87, 67, 0, // Skip to: 19231
+/* 1992 */    MCD_OPC_Decode, 227, 25, 203, 1, // Opcode: VRHADDuv8i16
+/* 1997 */    MCD_OPC_FilterValue, 231, 3, 76, 67, 0, // Skip to: 19231
+/* 2003 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2006 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2021
+/* 2011 */    MCD_OPC_CheckPredicate, 26, 63, 67, 0, // Skip to: 19231
+/* 2016 */    MCD_OPC_Decode, 166, 16, 205, 1, // Opcode: VADDWuv4i32
+/* 2021 */    MCD_OPC_FilterValue, 1, 53, 67, 0, // Skip to: 19231
+/* 2026 */    MCD_OPC_CheckPredicate, 27, 48, 67, 0, // Skip to: 19231
+/* 2031 */    MCD_OPC_Decode, 193, 22, 213, 1, // Opcode: VMLAslhq
+/* 2036 */    MCD_OPC_FilterValue, 2, 159, 0, 0, // Skip to: 2200
+/* 2041 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2044 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 2083
+/* 2050 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2053 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2068
+/* 2058 */    MCD_OPC_CheckPredicate, 26, 16, 67, 0, // Skip to: 19231
+/* 2063 */    MCD_OPC_Decode, 251, 18, 202, 1, // Opcode: VHSUBsv4i16
+/* 2068 */    MCD_OPC_FilterValue, 1, 6, 67, 0, // Skip to: 19231
+/* 2073 */    MCD_OPC_CheckPredicate, 26, 1, 67, 0, // Skip to: 19231
+/* 2078 */    MCD_OPC_Decode, 253, 18, 203, 1, // Opcode: VHSUBsv8i16
+/* 2083 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 2122
+/* 2089 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2092 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2107
+/* 2097 */    MCD_OPC_CheckPredicate, 26, 233, 66, 0, // Skip to: 19231
+/* 2102 */    MCD_OPC_Decode, 236, 29, 204, 1, // Opcode: VSUBLsv4i32
+/* 2107 */    MCD_OPC_FilterValue, 1, 223, 66, 0, // Skip to: 19231
+/* 2112 */    MCD_OPC_CheckPredicate, 26, 218, 66, 0, // Skip to: 19231
+/* 2117 */    MCD_OPC_Decode, 176, 22, 214, 1, // Opcode: VMLALslsv4i16
+/* 2122 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 2161
+/* 2128 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2131 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2146
+/* 2136 */    MCD_OPC_CheckPredicate, 26, 194, 66, 0, // Skip to: 19231
+/* 2141 */    MCD_OPC_Decode, 129, 19, 202, 1, // Opcode: VHSUBuv4i16
+/* 2146 */    MCD_OPC_FilterValue, 1, 184, 66, 0, // Skip to: 19231
+/* 2151 */    MCD_OPC_CheckPredicate, 26, 179, 66, 0, // Skip to: 19231
+/* 2156 */    MCD_OPC_Decode, 131, 19, 203, 1, // Opcode: VHSUBuv8i16
+/* 2161 */    MCD_OPC_FilterValue, 231, 3, 168, 66, 0, // Skip to: 19231
+/* 2167 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2170 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2185
+/* 2175 */    MCD_OPC_CheckPredicate, 26, 155, 66, 0, // Skip to: 19231
+/* 2180 */    MCD_OPC_Decode, 239, 29, 204, 1, // Opcode: VSUBLuv4i32
+/* 2185 */    MCD_OPC_FilterValue, 1, 145, 66, 0, // Skip to: 19231
+/* 2190 */    MCD_OPC_CheckPredicate, 26, 140, 66, 0, // Skip to: 19231
+/* 2195 */    MCD_OPC_Decode, 178, 22, 214, 1, // Opcode: VMLALsluv4i16
+/* 2200 */    MCD_OPC_FilterValue, 3, 143, 0, 0, // Skip to: 2348
+/* 2205 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2208 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 2247
+/* 2214 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2217 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2232
+/* 2222 */    MCD_OPC_CheckPredicate, 26, 108, 66, 0, // Skip to: 19231
+/* 2227 */    MCD_OPC_Decode, 128, 17, 202, 1, // Opcode: VCGTsv4i16
+/* 2232 */    MCD_OPC_FilterValue, 1, 98, 66, 0, // Skip to: 19231
+/* 2237 */    MCD_OPC_CheckPredicate, 26, 93, 66, 0, // Skip to: 19231
+/* 2242 */    MCD_OPC_Decode, 130, 17, 203, 1, // Opcode: VCGTsv8i16
+/* 2247 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 2286
+/* 2253 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2256 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2271
+/* 2261 */    MCD_OPC_CheckPredicate, 26, 69, 66, 0, // Skip to: 19231
+/* 2266 */    MCD_OPC_Decode, 243, 29, 205, 1, // Opcode: VSUBWsv4i32
+/* 2271 */    MCD_OPC_FilterValue, 1, 59, 66, 0, // Skip to: 19231
+/* 2276 */    MCD_OPC_CheckPredicate, 26, 54, 66, 0, // Skip to: 19231
+/* 2281 */    MCD_OPC_Decode, 172, 24, 214, 1, // Opcode: VQDMLALslv4i16
+/* 2286 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 2325
+/* 2292 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2295 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2310
+/* 2300 */    MCD_OPC_CheckPredicate, 26, 30, 66, 0, // Skip to: 19231
+/* 2305 */    MCD_OPC_Decode, 134, 17, 202, 1, // Opcode: VCGTuv4i16
+/* 2310 */    MCD_OPC_FilterValue, 1, 20, 66, 0, // Skip to: 19231
+/* 2315 */    MCD_OPC_CheckPredicate, 26, 15, 66, 0, // Skip to: 19231
+/* 2320 */    MCD_OPC_Decode, 136, 17, 203, 1, // Opcode: VCGTuv8i16
+/* 2325 */    MCD_OPC_FilterValue, 231, 3, 4, 66, 0, // Skip to: 19231
+/* 2331 */    MCD_OPC_CheckPredicate, 26, 255, 65, 0, // Skip to: 19231
+/* 2336 */    MCD_OPC_CheckField, 6, 1, 0, 248, 65, 0, // Skip to: 19231
+/* 2343 */    MCD_OPC_Decode, 246, 29, 205, 1, // Opcode: VSUBWuv4i32
+/* 2348 */    MCD_OPC_FilterValue, 4, 159, 0, 0, // Skip to: 2512
+/* 2353 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2356 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 2395
+/* 2362 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2365 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2380
+/* 2370 */    MCD_OPC_CheckPredicate, 26, 216, 65, 0, // Skip to: 19231
+/* 2375 */    MCD_OPC_Decode, 252, 26, 206, 1, // Opcode: VSHLsv4i16
+/* 2380 */    MCD_OPC_FilterValue, 1, 206, 65, 0, // Skip to: 19231
+/* 2385 */    MCD_OPC_CheckPredicate, 26, 201, 65, 0, // Skip to: 19231
+/* 2390 */    MCD_OPC_Decode, 254, 26, 207, 1, // Opcode: VSHLsv8i16
+/* 2395 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 2434
+/* 2401 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2404 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2419
+/* 2409 */    MCD_OPC_CheckPredicate, 26, 177, 65, 0, // Skip to: 19231
+/* 2414 */    MCD_OPC_Decode, 153, 16, 208, 1, // Opcode: VADDHNv4i16
+/* 2419 */    MCD_OPC_FilterValue, 1, 167, 65, 0, // Skip to: 19231
+/* 2424 */    MCD_OPC_CheckPredicate, 26, 162, 65, 0, // Skip to: 19231
+/* 2429 */    MCD_OPC_Decode, 226, 22, 212, 1, // Opcode: VMLSslv4i16
+/* 2434 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 2473
+/* 2440 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2443 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2458
+/* 2448 */    MCD_OPC_CheckPredicate, 26, 138, 65, 0, // Skip to: 19231
+/* 2453 */    MCD_OPC_Decode, 132, 27, 206, 1, // Opcode: VSHLuv4i16
+/* 2458 */    MCD_OPC_FilterValue, 1, 128, 65, 0, // Skip to: 19231
+/* 2463 */    MCD_OPC_CheckPredicate, 26, 123, 65, 0, // Skip to: 19231
+/* 2468 */    MCD_OPC_Decode, 134, 27, 207, 1, // Opcode: VSHLuv8i16
+/* 2473 */    MCD_OPC_FilterValue, 231, 3, 112, 65, 0, // Skip to: 19231
+/* 2479 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2482 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2497
+/* 2487 */    MCD_OPC_CheckPredicate, 26, 99, 65, 0, // Skip to: 19231
+/* 2492 */    MCD_OPC_Decode, 193, 25, 208, 1, // Opcode: VRADDHNv4i16
+/* 2497 */    MCD_OPC_FilterValue, 1, 89, 65, 0, // Skip to: 19231
+/* 2502 */    MCD_OPC_CheckPredicate, 26, 84, 65, 0, // Skip to: 19231
+/* 2507 */    MCD_OPC_Decode, 228, 22, 213, 1, // Opcode: VMLSslv8i16
+/* 2512 */    MCD_OPC_FilterValue, 5, 159, 0, 0, // Skip to: 2676
+/* 2517 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2520 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 2559
+/* 2526 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2529 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2544
+/* 2534 */    MCD_OPC_CheckPredicate, 26, 52, 65, 0, // Skip to: 19231
+/* 2539 */    MCD_OPC_Decode, 150, 26, 206, 1, // Opcode: VRSHLsv4i16
+/* 2544 */    MCD_OPC_FilterValue, 1, 42, 65, 0, // Skip to: 19231
+/* 2549 */    MCD_OPC_CheckPredicate, 26, 37, 65, 0, // Skip to: 19231
+/* 2554 */    MCD_OPC_Decode, 152, 26, 207, 1, // Opcode: VRSHLsv8i16
+/* 2559 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 2598
+/* 2565 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2568 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2583
+/* 2573 */    MCD_OPC_CheckPredicate, 26, 13, 65, 0, // Skip to: 19231
+/* 2578 */    MCD_OPC_Decode, 218, 15, 209, 1, // Opcode: VABALsv4i32
+/* 2583 */    MCD_OPC_FilterValue, 1, 3, 65, 0, // Skip to: 19231
+/* 2588 */    MCD_OPC_CheckPredicate, 27, 254, 64, 0, // Skip to: 19231
+/* 2593 */    MCD_OPC_Decode, 223, 22, 212, 1, // Opcode: VMLSslhd
+/* 2598 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 2637
+/* 2604 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2607 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2622
+/* 2612 */    MCD_OPC_CheckPredicate, 26, 230, 64, 0, // Skip to: 19231
+/* 2617 */    MCD_OPC_Decode, 158, 26, 206, 1, // Opcode: VRSHLuv4i16
+/* 2622 */    MCD_OPC_FilterValue, 1, 220, 64, 0, // Skip to: 19231
+/* 2627 */    MCD_OPC_CheckPredicate, 26, 215, 64, 0, // Skip to: 19231
+/* 2632 */    MCD_OPC_Decode, 160, 26, 207, 1, // Opcode: VRSHLuv8i16
+/* 2637 */    MCD_OPC_FilterValue, 231, 3, 204, 64, 0, // Skip to: 19231
+/* 2643 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2646 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2661
+/* 2651 */    MCD_OPC_CheckPredicate, 26, 191, 64, 0, // Skip to: 19231
+/* 2656 */    MCD_OPC_Decode, 221, 15, 209, 1, // Opcode: VABALuv4i32
+/* 2661 */    MCD_OPC_FilterValue, 1, 181, 64, 0, // Skip to: 19231
+/* 2666 */    MCD_OPC_CheckPredicate, 27, 176, 64, 0, // Skip to: 19231
+/* 2671 */    MCD_OPC_Decode, 224, 22, 213, 1, // Opcode: VMLSslhq
+/* 2676 */    MCD_OPC_FilterValue, 6, 159, 0, 0, // Skip to: 2840
+/* 2681 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2684 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 2723
+/* 2690 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2693 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2708
+/* 2698 */    MCD_OPC_CheckPredicate, 26, 144, 64, 0, // Skip to: 19231
+/* 2703 */    MCD_OPC_Decode, 147, 22, 202, 1, // Opcode: VMAXsv4i16
+/* 2708 */    MCD_OPC_FilterValue, 1, 134, 64, 0, // Skip to: 19231
+/* 2713 */    MCD_OPC_CheckPredicate, 26, 129, 64, 0, // Skip to: 19231
+/* 2718 */    MCD_OPC_Decode, 149, 22, 203, 1, // Opcode: VMAXsv8i16
+/* 2723 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 2762
+/* 2729 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2732 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2747
+/* 2737 */    MCD_OPC_CheckPredicate, 26, 105, 64, 0, // Skip to: 19231
+/* 2742 */    MCD_OPC_Decode, 233, 29, 208, 1, // Opcode: VSUBHNv4i16
+/* 2747 */    MCD_OPC_FilterValue, 1, 95, 64, 0, // Skip to: 19231
+/* 2752 */    MCD_OPC_CheckPredicate, 26, 90, 64, 0, // Skip to: 19231
+/* 2757 */    MCD_OPC_Decode, 207, 22, 214, 1, // Opcode: VMLSLslsv4i16
+/* 2762 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 2801
+/* 2768 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2771 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2786
+/* 2776 */    MCD_OPC_CheckPredicate, 26, 66, 64, 0, // Skip to: 19231
+/* 2781 */    MCD_OPC_Decode, 153, 22, 202, 1, // Opcode: VMAXuv4i16
+/* 2786 */    MCD_OPC_FilterValue, 1, 56, 64, 0, // Skip to: 19231
+/* 2791 */    MCD_OPC_CheckPredicate, 26, 51, 64, 0, // Skip to: 19231
+/* 2796 */    MCD_OPC_Decode, 155, 22, 203, 1, // Opcode: VMAXuv8i16
+/* 2801 */    MCD_OPC_FilterValue, 231, 3, 40, 64, 0, // Skip to: 19231
+/* 2807 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2810 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2825
+/* 2815 */    MCD_OPC_CheckPredicate, 26, 27, 64, 0, // Skip to: 19231
+/* 2820 */    MCD_OPC_Decode, 208, 26, 208, 1, // Opcode: VRSUBHNv4i16
+/* 2825 */    MCD_OPC_FilterValue, 1, 17, 64, 0, // Skip to: 19231
+/* 2830 */    MCD_OPC_CheckPredicate, 26, 12, 64, 0, // Skip to: 19231
+/* 2835 */    MCD_OPC_Decode, 209, 22, 214, 1, // Opcode: VMLSLsluv4i16
+/* 2840 */    MCD_OPC_FilterValue, 7, 143, 0, 0, // Skip to: 2988
+/* 2845 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2848 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 2887
+/* 2854 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2857 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2872
+/* 2862 */    MCD_OPC_CheckPredicate, 26, 236, 63, 0, // Skip to: 19231
+/* 2867 */    MCD_OPC_Decode, 247, 15, 202, 1, // Opcode: VABDsv4i16
+/* 2872 */    MCD_OPC_FilterValue, 1, 226, 63, 0, // Skip to: 19231
+/* 2877 */    MCD_OPC_CheckPredicate, 26, 221, 63, 0, // Skip to: 19231
+/* 2882 */    MCD_OPC_Decode, 249, 15, 203, 1, // Opcode: VABDsv8i16
+/* 2887 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 2926
+/* 2893 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2896 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2911
+/* 2901 */    MCD_OPC_CheckPredicate, 26, 197, 63, 0, // Skip to: 19231
+/* 2906 */    MCD_OPC_Decode, 236, 15, 204, 1, // Opcode: VABDLsv4i32
+/* 2911 */    MCD_OPC_FilterValue, 1, 187, 63, 0, // Skip to: 19231
+/* 2916 */    MCD_OPC_CheckPredicate, 26, 182, 63, 0, // Skip to: 19231
+/* 2921 */    MCD_OPC_Decode, 176, 24, 214, 1, // Opcode: VQDMLSLslv4i16
+/* 2926 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 2965
+/* 2932 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2935 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2950
+/* 2940 */    MCD_OPC_CheckPredicate, 26, 158, 63, 0, // Skip to: 19231
+/* 2945 */    MCD_OPC_Decode, 253, 15, 202, 1, // Opcode: VABDuv4i16
+/* 2950 */    MCD_OPC_FilterValue, 1, 148, 63, 0, // Skip to: 19231
+/* 2955 */    MCD_OPC_CheckPredicate, 26, 143, 63, 0, // Skip to: 19231
+/* 2960 */    MCD_OPC_Decode, 255, 15, 203, 1, // Opcode: VABDuv8i16
+/* 2965 */    MCD_OPC_FilterValue, 231, 3, 132, 63, 0, // Skip to: 19231
+/* 2971 */    MCD_OPC_CheckPredicate, 26, 127, 63, 0, // Skip to: 19231
+/* 2976 */    MCD_OPC_CheckField, 6, 1, 0, 120, 63, 0, // Skip to: 19231
+/* 2983 */    MCD_OPC_Decode, 239, 15, 204, 1, // Opcode: VABDLuv4i32
+/* 2988 */    MCD_OPC_FilterValue, 8, 159, 0, 0, // Skip to: 3152
+/* 2993 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2996 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 3035
+/* 3002 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3005 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3020
+/* 3010 */    MCD_OPC_CheckPredicate, 26, 88, 63, 0, // Skip to: 19231
+/* 3015 */    MCD_OPC_Decode, 176, 16, 202, 1, // Opcode: VADDv4i16
+/* 3020 */    MCD_OPC_FilterValue, 1, 78, 63, 0, // Skip to: 19231
+/* 3025 */    MCD_OPC_CheckPredicate, 26, 73, 63, 0, // Skip to: 19231
+/* 3030 */    MCD_OPC_Decode, 178, 16, 203, 1, // Opcode: VADDv8i16
+/* 3035 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 3074
+/* 3041 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3044 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3059
+/* 3049 */    MCD_OPC_CheckPredicate, 26, 49, 63, 0, // Skip to: 19231
+/* 3054 */    MCD_OPC_Decode, 180, 22, 209, 1, // Opcode: VMLALsv4i32
+/* 3059 */    MCD_OPC_FilterValue, 1, 39, 63, 0, // Skip to: 19231
+/* 3064 */    MCD_OPC_CheckPredicate, 26, 34, 63, 0, // Skip to: 19231
+/* 3069 */    MCD_OPC_Decode, 187, 23, 215, 1, // Opcode: VMULslv4i16
+/* 3074 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 3113
+/* 3080 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3083 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3098
+/* 3088 */    MCD_OPC_CheckPredicate, 26, 10, 63, 0, // Skip to: 19231
+/* 3093 */    MCD_OPC_Decode, 128, 30, 202, 1, // Opcode: VSUBv4i16
+/* 3098 */    MCD_OPC_FilterValue, 1, 0, 63, 0, // Skip to: 19231
+/* 3103 */    MCD_OPC_CheckPredicate, 26, 251, 62, 0, // Skip to: 19231
+/* 3108 */    MCD_OPC_Decode, 130, 30, 203, 1, // Opcode: VSUBv8i16
+/* 3113 */    MCD_OPC_FilterValue, 231, 3, 240, 62, 0, // Skip to: 19231
+/* 3119 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3122 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3137
+/* 3127 */    MCD_OPC_CheckPredicate, 26, 227, 62, 0, // Skip to: 19231
+/* 3132 */    MCD_OPC_Decode, 183, 22, 209, 1, // Opcode: VMLALuv4i32
+/* 3137 */    MCD_OPC_FilterValue, 1, 217, 62, 0, // Skip to: 19231
+/* 3142 */    MCD_OPC_CheckPredicate, 26, 212, 62, 0, // Skip to: 19231
+/* 3147 */    MCD_OPC_Decode, 189, 23, 216, 1, // Opcode: VMULslv8i16
+/* 3152 */    MCD_OPC_FilterValue, 9, 143, 0, 0, // Skip to: 3300
+/* 3157 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3160 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 3199
+/* 3166 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3169 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3184
+/* 3174 */    MCD_OPC_CheckPredicate, 26, 180, 62, 0, // Skip to: 19231
+/* 3179 */    MCD_OPC_Decode, 200, 22, 210, 1, // Opcode: VMLAv4i16
+/* 3184 */    MCD_OPC_FilterValue, 1, 170, 62, 0, // Skip to: 19231
+/* 3189 */    MCD_OPC_CheckPredicate, 26, 165, 62, 0, // Skip to: 19231
+/* 3194 */    MCD_OPC_Decode, 202, 22, 211, 1, // Opcode: VMLAv8i16
+/* 3199 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 3238
+/* 3205 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3208 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3223
+/* 3213 */    MCD_OPC_CheckPredicate, 26, 141, 62, 0, // Skip to: 19231
+/* 3218 */    MCD_OPC_Decode, 174, 24, 209, 1, // Opcode: VQDMLALv4i32
+/* 3223 */    MCD_OPC_FilterValue, 1, 131, 62, 0, // Skip to: 19231
+/* 3228 */    MCD_OPC_CheckPredicate, 27, 126, 62, 0, // Skip to: 19231
+/* 3233 */    MCD_OPC_Decode, 184, 23, 215, 1, // Opcode: VMULslhd
+/* 3238 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 3277
+/* 3244 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3247 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3262
+/* 3252 */    MCD_OPC_CheckPredicate, 26, 102, 62, 0, // Skip to: 19231
+/* 3257 */    MCD_OPC_Decode, 231, 22, 210, 1, // Opcode: VMLSv4i16
+/* 3262 */    MCD_OPC_FilterValue, 1, 92, 62, 0, // Skip to: 19231
+/* 3267 */    MCD_OPC_CheckPredicate, 26, 87, 62, 0, // Skip to: 19231
+/* 3272 */    MCD_OPC_Decode, 233, 22, 211, 1, // Opcode: VMLSv8i16
+/* 3277 */    MCD_OPC_FilterValue, 231, 3, 76, 62, 0, // Skip to: 19231
+/* 3283 */    MCD_OPC_CheckPredicate, 27, 71, 62, 0, // Skip to: 19231
+/* 3288 */    MCD_OPC_CheckField, 6, 1, 1, 64, 62, 0, // Skip to: 19231
+/* 3295 */    MCD_OPC_Decode, 185, 23, 216, 1, // Opcode: VMULslhq
+/* 3300 */    MCD_OPC_FilterValue, 10, 127, 0, 0, // Skip to: 3432
+/* 3305 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3308 */    MCD_OPC_FilterValue, 228, 3, 17, 0, 0, // Skip to: 3331
+/* 3314 */    MCD_OPC_CheckPredicate, 26, 40, 62, 0, // Skip to: 19231
+/* 3319 */    MCD_OPC_CheckField, 6, 1, 0, 33, 62, 0, // Skip to: 19231
+/* 3326 */    MCD_OPC_Decode, 135, 24, 202, 1, // Opcode: VPMAXs16
+/* 3331 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 3370
+/* 3337 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3340 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3355
+/* 3345 */    MCD_OPC_CheckPredicate, 26, 9, 62, 0, // Skip to: 19231
+/* 3350 */    MCD_OPC_Decode, 211, 22, 209, 1, // Opcode: VMLSLsv4i32
+/* 3355 */    MCD_OPC_FilterValue, 1, 255, 61, 0, // Skip to: 19231
+/* 3360 */    MCD_OPC_CheckPredicate, 26, 250, 61, 0, // Skip to: 19231
+/* 3365 */    MCD_OPC_Decode, 166, 23, 217, 1, // Opcode: VMULLslsv4i16
+/* 3370 */    MCD_OPC_FilterValue, 230, 3, 17, 0, 0, // Skip to: 3393
+/* 3376 */    MCD_OPC_CheckPredicate, 26, 234, 61, 0, // Skip to: 19231
+/* 3381 */    MCD_OPC_CheckField, 6, 1, 0, 227, 61, 0, // Skip to: 19231
+/* 3388 */    MCD_OPC_Decode, 138, 24, 202, 1, // Opcode: VPMAXu16
+/* 3393 */    MCD_OPC_FilterValue, 231, 3, 216, 61, 0, // Skip to: 19231
+/* 3399 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3402 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3417
+/* 3407 */    MCD_OPC_CheckPredicate, 26, 203, 61, 0, // Skip to: 19231
+/* 3412 */    MCD_OPC_Decode, 214, 22, 209, 1, // Opcode: VMLSLuv4i32
+/* 3417 */    MCD_OPC_FilterValue, 1, 193, 61, 0, // Skip to: 19231
+/* 3422 */    MCD_OPC_CheckPredicate, 26, 188, 61, 0, // Skip to: 19231
+/* 3427 */    MCD_OPC_Decode, 168, 23, 217, 1, // Opcode: VMULLsluv4i16
+/* 3432 */    MCD_OPC_FilterValue, 11, 120, 0, 0, // Skip to: 3557
+/* 3437 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3440 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 3479
+/* 3446 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3449 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3464
+/* 3454 */    MCD_OPC_CheckPredicate, 26, 156, 61, 0, // Skip to: 19231
+/* 3459 */    MCD_OPC_Decode, 184, 24, 202, 1, // Opcode: VQDMULHv4i16
+/* 3464 */    MCD_OPC_FilterValue, 1, 146, 61, 0, // Skip to: 19231
+/* 3469 */    MCD_OPC_CheckPredicate, 26, 141, 61, 0, // Skip to: 19231
+/* 3474 */    MCD_OPC_Decode, 186, 24, 203, 1, // Opcode: VQDMULHv8i16
+/* 3479 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 3518
+/* 3485 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3488 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3503
+/* 3493 */    MCD_OPC_CheckPredicate, 26, 117, 61, 0, // Skip to: 19231
+/* 3498 */    MCD_OPC_Decode, 178, 24, 209, 1, // Opcode: VQDMLSLv4i32
+/* 3503 */    MCD_OPC_FilterValue, 1, 107, 61, 0, // Skip to: 19231
+/* 3508 */    MCD_OPC_CheckPredicate, 26, 102, 61, 0, // Skip to: 19231
+/* 3513 */    MCD_OPC_Decode, 188, 24, 217, 1, // Opcode: VQDMULLslv4i16
+/* 3518 */    MCD_OPC_FilterValue, 230, 3, 91, 61, 0, // Skip to: 19231
+/* 3524 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3527 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3542
+/* 3532 */    MCD_OPC_CheckPredicate, 26, 78, 61, 0, // Skip to: 19231
+/* 3537 */    MCD_OPC_Decode, 227, 24, 202, 1, // Opcode: VQRDMULHv4i16
+/* 3542 */    MCD_OPC_FilterValue, 1, 68, 61, 0, // Skip to: 19231
+/* 3547 */    MCD_OPC_CheckPredicate, 26, 63, 61, 0, // Skip to: 19231
+/* 3552 */    MCD_OPC_Decode, 229, 24, 203, 1, // Opcode: VQRDMULHv8i16
+/* 3557 */    MCD_OPC_FilterValue, 12, 83, 0, 0, // Skip to: 3645
+/* 3562 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3565 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3605
+/* 3570 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3573 */    MCD_OPC_FilterValue, 229, 3, 10, 0, 0, // Skip to: 3589
+/* 3579 */    MCD_OPC_CheckPredicate, 26, 31, 61, 0, // Skip to: 19231
+/* 3584 */    MCD_OPC_Decode, 170, 23, 204, 1, // Opcode: VMULLsv4i32
+/* 3589 */    MCD_OPC_FilterValue, 231, 3, 20, 61, 0, // Skip to: 19231
+/* 3595 */    MCD_OPC_CheckPredicate, 26, 15, 61, 0, // Skip to: 19231
+/* 3600 */    MCD_OPC_Decode, 173, 23, 204, 1, // Opcode: VMULLuv4i32
+/* 3605 */    MCD_OPC_FilterValue, 1, 5, 61, 0, // Skip to: 19231
+/* 3610 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3613 */    MCD_OPC_FilterValue, 229, 3, 10, 0, 0, // Skip to: 3629
+/* 3619 */    MCD_OPC_CheckPredicate, 26, 247, 60, 0, // Skip to: 19231
+/* 3624 */    MCD_OPC_Decode, 180, 24, 215, 1, // Opcode: VQDMULHslv4i16
+/* 3629 */    MCD_OPC_FilterValue, 231, 3, 236, 60, 0, // Skip to: 19231
+/* 3635 */    MCD_OPC_CheckPredicate, 26, 231, 60, 0, // Skip to: 19231
+/* 3640 */    MCD_OPC_Decode, 182, 24, 216, 1, // Opcode: VQDMULHslv8i16
+/* 3645 */    MCD_OPC_FilterValue, 13, 127, 0, 0, // Skip to: 3777
+/* 3650 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3653 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 3692
+/* 3659 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3662 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3677
+/* 3667 */    MCD_OPC_CheckPredicate, 27, 199, 60, 0, // Skip to: 19231
+/* 3672 */    MCD_OPC_Decode, 170, 16, 202, 1, // Opcode: VADDhd
+/* 3677 */    MCD_OPC_FilterValue, 1, 189, 60, 0, // Skip to: 19231
+/* 3682 */    MCD_OPC_CheckPredicate, 27, 184, 60, 0, // Skip to: 19231
+/* 3687 */    MCD_OPC_Decode, 171, 16, 203, 1, // Opcode: VADDhq
+/* 3692 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 3731
+/* 3698 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3701 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3716
+/* 3706 */    MCD_OPC_CheckPredicate, 26, 160, 60, 0, // Skip to: 19231
+/* 3711 */    MCD_OPC_Decode, 190, 24, 204, 1, // Opcode: VQDMULLv4i32
+/* 3716 */    MCD_OPC_FilterValue, 1, 150, 60, 0, // Skip to: 19231
+/* 3721 */    MCD_OPC_CheckPredicate, 26, 145, 60, 0, // Skip to: 19231
+/* 3726 */    MCD_OPC_Decode, 223, 24, 215, 1, // Opcode: VQRDMULHslv4i16
+/* 3731 */    MCD_OPC_FilterValue, 230, 3, 17, 0, 0, // Skip to: 3754
+/* 3737 */    MCD_OPC_CheckPredicate, 27, 129, 60, 0, // Skip to: 19231
+/* 3742 */    MCD_OPC_CheckField, 6, 1, 0, 122, 60, 0, // Skip to: 19231
+/* 3749 */    MCD_OPC_Decode, 129, 24, 202, 1, // Opcode: VPADDh
+/* 3754 */    MCD_OPC_FilterValue, 231, 3, 111, 60, 0, // Skip to: 19231
+/* 3760 */    MCD_OPC_CheckPredicate, 26, 106, 60, 0, // Skip to: 19231
+/* 3765 */    MCD_OPC_CheckField, 6, 1, 1, 99, 60, 0, // Skip to: 19231
+/* 3772 */    MCD_OPC_Decode, 225, 24, 216, 1, // Opcode: VQRDMULHslv8i16
+/* 3777 */    MCD_OPC_FilterValue, 14, 127, 0, 0, // Skip to: 3909
+/* 3782 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3785 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 3824
+/* 3791 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3794 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3809
+/* 3799 */    MCD_OPC_CheckPredicate, 27, 67, 60, 0, // Skip to: 19231
+/* 3804 */    MCD_OPC_Decode, 206, 16, 202, 1, // Opcode: VCEQhd
+/* 3809 */    MCD_OPC_FilterValue, 1, 57, 60, 0, // Skip to: 19231
+/* 3814 */    MCD_OPC_CheckPredicate, 27, 52, 60, 0, // Skip to: 19231
+/* 3819 */    MCD_OPC_Decode, 207, 16, 203, 1, // Opcode: VCEQhq
+/* 3824 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 3847
+/* 3830 */    MCD_OPC_CheckPredicate, 28, 36, 60, 0, // Skip to: 19231
+/* 3835 */    MCD_OPC_CheckField, 6, 1, 1, 29, 60, 0, // Skip to: 19231
+/* 3842 */    MCD_OPC_Decode, 207, 24, 212, 1, // Opcode: VQRDMLAHslv4i16
+/* 3847 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 3886
+/* 3853 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3856 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3871
+/* 3861 */    MCD_OPC_CheckPredicate, 27, 5, 60, 0, // Skip to: 19231
+/* 3866 */    MCD_OPC_Decode, 226, 16, 202, 1, // Opcode: VCGEhd
+/* 3871 */    MCD_OPC_FilterValue, 1, 251, 59, 0, // Skip to: 19231
+/* 3876 */    MCD_OPC_CheckPredicate, 27, 246, 59, 0, // Skip to: 19231
+/* 3881 */    MCD_OPC_Decode, 227, 16, 203, 1, // Opcode: VCGEhq
+/* 3886 */    MCD_OPC_FilterValue, 231, 3, 235, 59, 0, // Skip to: 19231
+/* 3892 */    MCD_OPC_CheckPredicate, 28, 230, 59, 0, // Skip to: 19231
+/* 3897 */    MCD_OPC_CheckField, 6, 1, 1, 223, 59, 0, // Skip to: 19231
+/* 3904 */    MCD_OPC_Decode, 209, 24, 213, 1, // Opcode: VQRDMLAHslv8i16
+/* 3909 */    MCD_OPC_FilterValue, 15, 213, 59, 0, // Skip to: 19231
+/* 3914 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 3917 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 3956
+/* 3923 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3926 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3941
+/* 3931 */    MCD_OPC_CheckPredicate, 27, 191, 59, 0, // Skip to: 19231
+/* 3936 */    MCD_OPC_Decode, 143, 22, 202, 1, // Opcode: VMAXhd
+/* 3941 */    MCD_OPC_FilterValue, 1, 181, 59, 0, // Skip to: 19231
+/* 3946 */    MCD_OPC_CheckPredicate, 27, 176, 59, 0, // Skip to: 19231
+/* 3951 */    MCD_OPC_Decode, 144, 22, 203, 1, // Opcode: VMAXhq
+/* 3956 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 3979
+/* 3962 */    MCD_OPC_CheckPredicate, 28, 160, 59, 0, // Skip to: 19231
+/* 3967 */    MCD_OPC_CheckField, 6, 1, 1, 153, 59, 0, // Skip to: 19231
+/* 3974 */    MCD_OPC_Decode, 215, 24, 212, 1, // Opcode: VQRDMLSHslv4i16
+/* 3979 */    MCD_OPC_FilterValue, 230, 3, 17, 0, 0, // Skip to: 4002
+/* 3985 */    MCD_OPC_CheckPredicate, 27, 137, 59, 0, // Skip to: 19231
+/* 3990 */    MCD_OPC_CheckField, 6, 1, 0, 130, 59, 0, // Skip to: 19231
+/* 3997 */    MCD_OPC_Decode, 134, 24, 202, 1, // Opcode: VPMAXh
+/* 4002 */    MCD_OPC_FilterValue, 231, 3, 119, 59, 0, // Skip to: 19231
+/* 4008 */    MCD_OPC_CheckPredicate, 28, 114, 59, 0, // Skip to: 19231
+/* 4013 */    MCD_OPC_CheckField, 6, 1, 1, 107, 59, 0, // Skip to: 19231
+/* 4020 */    MCD_OPC_Decode, 217, 24, 213, 1, // Opcode: VQRDMLSHslv8i16
+/* 4025 */    MCD_OPC_FilterValue, 2, 9, 9, 0, // Skip to: 6343
+/* 4030 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 4033 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 4197
+/* 4038 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 4041 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 4080
+/* 4047 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4050 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4065
+/* 4055 */    MCD_OPC_CheckPredicate, 26, 67, 59, 0, // Skip to: 19231
+/* 4060 */    MCD_OPC_Decode, 238, 18, 202, 1, // Opcode: VHADDsv2i32
+/* 4065 */    MCD_OPC_FilterValue, 1, 57, 59, 0, // Skip to: 19231
+/* 4070 */    MCD_OPC_CheckPredicate, 26, 52, 59, 0, // Skip to: 19231
+/* 4075 */    MCD_OPC_Decode, 240, 18, 203, 1, // Opcode: VHADDsv4i32
+/* 4080 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 4119
+/* 4086 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4089 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4104
+/* 4094 */    MCD_OPC_CheckPredicate, 26, 28, 59, 0, // Skip to: 19231
+/* 4099 */    MCD_OPC_Decode, 155, 16, 204, 1, // Opcode: VADDLsv2i64
+/* 4104 */    MCD_OPC_FilterValue, 1, 18, 59, 0, // Skip to: 19231
+/* 4109 */    MCD_OPC_CheckPredicate, 26, 13, 59, 0, // Skip to: 19231
+/* 4114 */    MCD_OPC_Decode, 194, 22, 218, 1, // Opcode: VMLAslv2i32
+/* 4119 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 4158
+/* 4125 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4128 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4143
+/* 4133 */    MCD_OPC_CheckPredicate, 26, 245, 58, 0, // Skip to: 19231
+/* 4138 */    MCD_OPC_Decode, 244, 18, 202, 1, // Opcode: VHADDuv2i32
+/* 4143 */    MCD_OPC_FilterValue, 1, 235, 58, 0, // Skip to: 19231
+/* 4148 */    MCD_OPC_CheckPredicate, 26, 230, 58, 0, // Skip to: 19231
+/* 4153 */    MCD_OPC_Decode, 246, 18, 203, 1, // Opcode: VHADDuv4i32
+/* 4158 */    MCD_OPC_FilterValue, 231, 3, 219, 58, 0, // Skip to: 19231
+/* 4164 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4167 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4182
+/* 4172 */    MCD_OPC_CheckPredicate, 26, 206, 58, 0, // Skip to: 19231
+/* 4177 */    MCD_OPC_Decode, 158, 16, 204, 1, // Opcode: VADDLuv2i64
+/* 4182 */    MCD_OPC_FilterValue, 1, 196, 58, 0, // Skip to: 19231
+/* 4187 */    MCD_OPC_CheckPredicate, 26, 191, 58, 0, // Skip to: 19231
+/* 4192 */    MCD_OPC_Decode, 196, 22, 219, 1, // Opcode: VMLAslv4i32
+/* 4197 */    MCD_OPC_FilterValue, 1, 159, 0, 0, // Skip to: 4361
+/* 4202 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 4205 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 4244
 /* 4211 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4214 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4228
-/* 4219 */    MCD_OPC_CheckPredicate, 21, 249, 55, 0, // Skip to: 18553
-/* 4224 */    MCD_OPC_Decode, 212, 20, 99, // Opcode: VSUBLsv2i64
-/* 4228 */    MCD_OPC_FilterValue, 1, 240, 55, 0, // Skip to: 18553
-/* 4233 */    MCD_OPC_CheckPredicate, 21, 235, 55, 0, // Skip to: 18553
-/* 4238 */    MCD_OPC_Decode, 204, 13, 115, // Opcode: VMLALslsv2i32
-/* 4242 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4279
-/* 4248 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4251 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4265
-/* 4256 */    MCD_OPC_CheckPredicate, 21, 212, 55, 0, // Skip to: 18553
-/* 4261 */    MCD_OPC_Decode, 193, 10, 97, // Opcode: VHSUBuv2i32
-/* 4265 */    MCD_OPC_FilterValue, 1, 203, 55, 0, // Skip to: 18553
-/* 4270 */    MCD_OPC_CheckPredicate, 21, 198, 55, 0, // Skip to: 18553
-/* 4275 */    MCD_OPC_Decode, 195, 10, 98, // Opcode: VHSUBuv4i32
-/* 4279 */    MCD_OPC_FilterValue, 231, 3, 188, 55, 0, // Skip to: 18553
-/* 4285 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4288 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4302
-/* 4293 */    MCD_OPC_CheckPredicate, 21, 175, 55, 0, // Skip to: 18553
-/* 4298 */    MCD_OPC_Decode, 215, 20, 99, // Opcode: VSUBLuv2i64
-/* 4302 */    MCD_OPC_FilterValue, 1, 166, 55, 0, // Skip to: 18553
-/* 4307 */    MCD_OPC_CheckPredicate, 21, 161, 55, 0, // Skip to: 18553
-/* 4312 */    MCD_OPC_Decode, 206, 13, 115, // Opcode: VMLALsluv2i32
-/* 4316 */    MCD_OPC_FilterValue, 3, 136, 0, 0, // Skip to: 4457
-/* 4321 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4324 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4361
-/* 4330 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4333 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4347
-/* 4338 */    MCD_OPC_CheckPredicate, 21, 130, 55, 0, // Skip to: 18553
-/* 4343 */    MCD_OPC_Decode, 206, 8, 97, // Opcode: VCGTsv2i32
-/* 4347 */    MCD_OPC_FilterValue, 1, 121, 55, 0, // Skip to: 18553
-/* 4352 */    MCD_OPC_CheckPredicate, 21, 116, 55, 0, // Skip to: 18553
-/* 4357 */    MCD_OPC_Decode, 208, 8, 98, // Opcode: VCGTsv4i32
-/* 4361 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4398
-/* 4367 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4370 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4384
-/* 4375 */    MCD_OPC_CheckPredicate, 21, 93, 55, 0, // Skip to: 18553
-/* 4380 */    MCD_OPC_Decode, 219, 20, 100, // Opcode: VSUBWsv2i64
-/* 4384 */    MCD_OPC_FilterValue, 1, 84, 55, 0, // Skip to: 18553
-/* 4389 */    MCD_OPC_CheckPredicate, 21, 79, 55, 0, // Skip to: 18553
-/* 4394 */    MCD_OPC_Decode, 189, 15, 115, // Opcode: VQDMLALslv2i32
-/* 4398 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4435
-/* 4404 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4407 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4421
-/* 4412 */    MCD_OPC_CheckPredicate, 21, 56, 55, 0, // Skip to: 18553
-/* 4417 */    MCD_OPC_Decode, 212, 8, 97, // Opcode: VCGTuv2i32
-/* 4421 */    MCD_OPC_FilterValue, 1, 47, 55, 0, // Skip to: 18553
-/* 4426 */    MCD_OPC_CheckPredicate, 21, 42, 55, 0, // Skip to: 18553
-/* 4431 */    MCD_OPC_Decode, 214, 8, 98, // Opcode: VCGTuv4i32
-/* 4435 */    MCD_OPC_FilterValue, 231, 3, 32, 55, 0, // Skip to: 18553
-/* 4441 */    MCD_OPC_CheckPredicate, 21, 27, 55, 0, // Skip to: 18553
-/* 4446 */    MCD_OPC_CheckField, 6, 1, 0, 20, 55, 0, // Skip to: 18553
-/* 4453 */    MCD_OPC_Decode, 222, 20, 100, // Opcode: VSUBWuv2i64
-/* 4457 */    MCD_OPC_FilterValue, 4, 151, 0, 0, // Skip to: 4613
-/* 4462 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4465 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4502
-/* 4471 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4474 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4488
-/* 4479 */    MCD_OPC_CheckPredicate, 21, 245, 54, 0, // Skip to: 18553
-/* 4484 */    MCD_OPC_Decode, 138, 18, 101, // Opcode: VSHLsv2i32
-/* 4488 */    MCD_OPC_FilterValue, 1, 236, 54, 0, // Skip to: 18553
-/* 4493 */    MCD_OPC_CheckPredicate, 21, 231, 54, 0, // Skip to: 18553
-/* 4498 */    MCD_OPC_Decode, 141, 18, 102, // Opcode: VSHLsv4i32
-/* 4502 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4539
-/* 4508 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4511 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4525
-/* 4516 */    MCD_OPC_CheckPredicate, 21, 208, 54, 0, // Skip to: 18553
-/* 4521 */    MCD_OPC_Decode, 237, 7, 103, // Opcode: VADDHNv2i32
-/* 4525 */    MCD_OPC_FilterValue, 1, 199, 54, 0, // Skip to: 18553
-/* 4530 */    MCD_OPC_CheckPredicate, 21, 194, 54, 0, // Skip to: 18553
-/* 4535 */    MCD_OPC_Decode, 254, 13, 113, // Opcode: VMLSslv2i32
-/* 4539 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4576
-/* 4545 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4548 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4562
-/* 4553 */    MCD_OPC_CheckPredicate, 21, 171, 54, 0, // Skip to: 18553
-/* 4558 */    MCD_OPC_Decode, 146, 18, 101, // Opcode: VSHLuv2i32
-/* 4562 */    MCD_OPC_FilterValue, 1, 162, 54, 0, // Skip to: 18553
-/* 4567 */    MCD_OPC_CheckPredicate, 21, 157, 54, 0, // Skip to: 18553
-/* 4572 */    MCD_OPC_Decode, 149, 18, 102, // Opcode: VSHLuv4i32
-/* 4576 */    MCD_OPC_FilterValue, 231, 3, 147, 54, 0, // Skip to: 18553
-/* 4582 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4585 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4599
-/* 4590 */    MCD_OPC_CheckPredicate, 21, 134, 54, 0, // Skip to: 18553
-/* 4595 */    MCD_OPC_Decode, 210, 16, 103, // Opcode: VRADDHNv2i32
-/* 4599 */    MCD_OPC_FilterValue, 1, 125, 54, 0, // Skip to: 18553
-/* 4604 */    MCD_OPC_CheckPredicate, 21, 120, 54, 0, // Skip to: 18553
-/* 4609 */    MCD_OPC_Decode, 128, 14, 114, // Opcode: VMLSslv4i32
-/* 4613 */    MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 4769
-/* 4618 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4621 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4658
-/* 4627 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4630 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4644
-/* 4635 */    MCD_OPC_CheckPredicate, 21, 89, 54, 0, // Skip to: 18553
-/* 4640 */    MCD_OPC_Decode, 166, 17, 101, // Opcode: VRSHLsv2i32
-/* 4644 */    MCD_OPC_FilterValue, 1, 80, 54, 0, // Skip to: 18553
-/* 4649 */    MCD_OPC_CheckPredicate, 21, 75, 54, 0, // Skip to: 18553
-/* 4654 */    MCD_OPC_Decode, 169, 17, 102, // Opcode: VRSHLsv4i32
-/* 4658 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4695
-/* 4664 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4667 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4681
-/* 4672 */    MCD_OPC_CheckPredicate, 21, 52, 54, 0, // Skip to: 18553
-/* 4677 */    MCD_OPC_Decode, 174, 7, 104, // Opcode: VABALsv2i64
-/* 4681 */    MCD_OPC_FilterValue, 1, 43, 54, 0, // Skip to: 18553
-/* 4686 */    MCD_OPC_CheckPredicate, 21, 38, 54, 0, // Skip to: 18553
-/* 4691 */    MCD_OPC_Decode, 250, 13, 113, // Opcode: VMLSslfd
-/* 4695 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4732
-/* 4701 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4704 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4718
-/* 4709 */    MCD_OPC_CheckPredicate, 21, 15, 54, 0, // Skip to: 18553
-/* 4714 */    MCD_OPC_Decode, 174, 17, 101, // Opcode: VRSHLuv2i32
-/* 4718 */    MCD_OPC_FilterValue, 1, 6, 54, 0, // Skip to: 18553
-/* 4723 */    MCD_OPC_CheckPredicate, 21, 1, 54, 0, // Skip to: 18553
-/* 4728 */    MCD_OPC_Decode, 177, 17, 102, // Opcode: VRSHLuv4i32
-/* 4732 */    MCD_OPC_FilterValue, 231, 3, 247, 53, 0, // Skip to: 18553
-/* 4738 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4741 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4755
-/* 4746 */    MCD_OPC_CheckPredicate, 21, 234, 53, 0, // Skip to: 18553
-/* 4751 */    MCD_OPC_Decode, 177, 7, 104, // Opcode: VABALuv2i64
-/* 4755 */    MCD_OPC_FilterValue, 1, 225, 53, 0, // Skip to: 18553
-/* 4760 */    MCD_OPC_CheckPredicate, 21, 220, 53, 0, // Skip to: 18553
-/* 4765 */    MCD_OPC_Decode, 251, 13, 114, // Opcode: VMLSslfq
-/* 4769 */    MCD_OPC_FilterValue, 6, 151, 0, 0, // Skip to: 4925
-/* 4774 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4777 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4814
-/* 4783 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4786 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4800
-/* 4791 */    MCD_OPC_CheckPredicate, 21, 189, 53, 0, // Skip to: 18553
-/* 4796 */    MCD_OPC_Decode, 168, 13, 97, // Opcode: VMAXsv2i32
-/* 4800 */    MCD_OPC_FilterValue, 1, 180, 53, 0, // Skip to: 18553
-/* 4805 */    MCD_OPC_CheckPredicate, 21, 175, 53, 0, // Skip to: 18553
-/* 4810 */    MCD_OPC_Decode, 170, 13, 98, // Opcode: VMAXsv4i32
-/* 4814 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 4851
-/* 4820 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4823 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4837
-/* 4828 */    MCD_OPC_CheckPredicate, 21, 152, 53, 0, // Skip to: 18553
-/* 4833 */    MCD_OPC_Decode, 209, 20, 103, // Opcode: VSUBHNv2i32
-/* 4837 */    MCD_OPC_FilterValue, 1, 143, 53, 0, // Skip to: 18553
-/* 4842 */    MCD_OPC_CheckPredicate, 21, 138, 53, 0, // Skip to: 18553
-/* 4847 */    MCD_OPC_Decode, 235, 13, 115, // Opcode: VMLSLslsv2i32
-/* 4851 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 4888
-/* 4857 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4860 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4874
-/* 4865 */    MCD_OPC_CheckPredicate, 21, 115, 53, 0, // Skip to: 18553
-/* 4870 */    MCD_OPC_Decode, 174, 13, 97, // Opcode: VMAXuv2i32
-/* 4874 */    MCD_OPC_FilterValue, 1, 106, 53, 0, // Skip to: 18553
-/* 4879 */    MCD_OPC_CheckPredicate, 21, 101, 53, 0, // Skip to: 18553
-/* 4884 */    MCD_OPC_Decode, 176, 13, 98, // Opcode: VMAXuv4i32
-/* 4888 */    MCD_OPC_FilterValue, 231, 3, 91, 53, 0, // Skip to: 18553
-/* 4894 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4897 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4911
-/* 4902 */    MCD_OPC_CheckPredicate, 21, 78, 53, 0, // Skip to: 18553
-/* 4907 */    MCD_OPC_Decode, 225, 17, 103, // Opcode: VRSUBHNv2i32
-/* 4911 */    MCD_OPC_FilterValue, 1, 69, 53, 0, // Skip to: 18553
-/* 4916 */    MCD_OPC_CheckPredicate, 21, 64, 53, 0, // Skip to: 18553
-/* 4921 */    MCD_OPC_Decode, 237, 13, 115, // Opcode: VMLSLsluv2i32
-/* 4925 */    MCD_OPC_FilterValue, 7, 136, 0, 0, // Skip to: 5066
-/* 4930 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 4933 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 4970
-/* 4939 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4942 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4956
-/* 4947 */    MCD_OPC_CheckPredicate, 21, 33, 53, 0, // Skip to: 18553
-/* 4952 */    MCD_OPC_Decode, 203, 7, 97, // Opcode: VABDsv2i32
-/* 4956 */    MCD_OPC_FilterValue, 1, 24, 53, 0, // Skip to: 18553
-/* 4961 */    MCD_OPC_CheckPredicate, 21, 19, 53, 0, // Skip to: 18553
-/* 4966 */    MCD_OPC_Decode, 205, 7, 98, // Opcode: VABDsv4i32
-/* 4970 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5007
-/* 4976 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 4979 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4993
-/* 4984 */    MCD_OPC_CheckPredicate, 21, 252, 52, 0, // Skip to: 18553
-/* 4989 */    MCD_OPC_Decode, 192, 7, 99, // Opcode: VABDLsv2i64
-/* 4993 */    MCD_OPC_FilterValue, 1, 243, 52, 0, // Skip to: 18553
-/* 4998 */    MCD_OPC_CheckPredicate, 21, 238, 52, 0, // Skip to: 18553
-/* 5003 */    MCD_OPC_Decode, 193, 15, 115, // Opcode: VQDMLSLslv2i32
-/* 5007 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5044
-/* 5013 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5016 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5030
-/* 5021 */    MCD_OPC_CheckPredicate, 21, 215, 52, 0, // Skip to: 18553
-/* 5026 */    MCD_OPC_Decode, 209, 7, 97, // Opcode: VABDuv2i32
-/* 5030 */    MCD_OPC_FilterValue, 1, 206, 52, 0, // Skip to: 18553
-/* 5035 */    MCD_OPC_CheckPredicate, 21, 201, 52, 0, // Skip to: 18553
-/* 5040 */    MCD_OPC_Decode, 211, 7, 98, // Opcode: VABDuv4i32
-/* 5044 */    MCD_OPC_FilterValue, 231, 3, 191, 52, 0, // Skip to: 18553
-/* 5050 */    MCD_OPC_CheckPredicate, 21, 186, 52, 0, // Skip to: 18553
-/* 5055 */    MCD_OPC_CheckField, 6, 1, 0, 179, 52, 0, // Skip to: 18553
-/* 5062 */    MCD_OPC_Decode, 195, 7, 99, // Opcode: VABDLuv2i64
-/* 5066 */    MCD_OPC_FilterValue, 8, 151, 0, 0, // Skip to: 5222
-/* 5071 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5074 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5111
-/* 5080 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5083 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5097
-/* 5088 */    MCD_OPC_CheckPredicate, 21, 148, 52, 0, // Skip to: 18553
-/* 5093 */    MCD_OPC_Decode, 131, 8, 97, // Opcode: VADDv2i32
-/* 5097 */    MCD_OPC_FilterValue, 1, 139, 52, 0, // Skip to: 18553
-/* 5102 */    MCD_OPC_CheckPredicate, 21, 134, 52, 0, // Skip to: 18553
-/* 5107 */    MCD_OPC_Decode, 134, 8, 98, // Opcode: VADDv4i32
-/* 5111 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5148
-/* 5117 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5120 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5134
-/* 5125 */    MCD_OPC_CheckPredicate, 21, 111, 52, 0, // Skip to: 18553
-/* 5130 */    MCD_OPC_Decode, 208, 13, 104, // Opcode: VMLALsv2i64
-/* 5134 */    MCD_OPC_FilterValue, 1, 102, 52, 0, // Skip to: 18553
-/* 5139 */    MCD_OPC_CheckPredicate, 21, 97, 52, 0, // Skip to: 18553
-/* 5144 */    MCD_OPC_Decode, 204, 14, 116, // Opcode: VMULslv2i32
-/* 5148 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5185
-/* 5154 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5157 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5171
-/* 5162 */    MCD_OPC_CheckPredicate, 21, 74, 52, 0, // Skip to: 18553
-/* 5167 */    MCD_OPC_Decode, 231, 20, 97, // Opcode: VSUBv2i32
-/* 5171 */    MCD_OPC_FilterValue, 1, 65, 52, 0, // Skip to: 18553
-/* 5176 */    MCD_OPC_CheckPredicate, 21, 60, 52, 0, // Skip to: 18553
-/* 5181 */    MCD_OPC_Decode, 234, 20, 98, // Opcode: VSUBv4i32
-/* 5185 */    MCD_OPC_FilterValue, 231, 3, 50, 52, 0, // Skip to: 18553
-/* 5191 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5194 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5208
-/* 5199 */    MCD_OPC_CheckPredicate, 21, 37, 52, 0, // Skip to: 18553
-/* 5204 */    MCD_OPC_Decode, 211, 13, 104, // Opcode: VMLALuv2i64
-/* 5208 */    MCD_OPC_FilterValue, 1, 28, 52, 0, // Skip to: 18553
-/* 5213 */    MCD_OPC_CheckPredicate, 21, 23, 52, 0, // Skip to: 18553
-/* 5218 */    MCD_OPC_Decode, 206, 14, 117, // Opcode: VMULslv4i32
-/* 5222 */    MCD_OPC_FilterValue, 9, 136, 0, 0, // Skip to: 5363
-/* 5227 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5230 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5267
-/* 5236 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5239 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5253
-/* 5244 */    MCD_OPC_CheckPredicate, 21, 248, 51, 0, // Skip to: 18553
-/* 5249 */    MCD_OPC_Decode, 228, 13, 105, // Opcode: VMLAv2i32
-/* 5253 */    MCD_OPC_FilterValue, 1, 239, 51, 0, // Skip to: 18553
-/* 5258 */    MCD_OPC_CheckPredicate, 21, 234, 51, 0, // Skip to: 18553
-/* 5263 */    MCD_OPC_Decode, 230, 13, 106, // Opcode: VMLAv4i32
-/* 5267 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5304
-/* 5273 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5276 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5290
-/* 5281 */    MCD_OPC_CheckPredicate, 21, 211, 51, 0, // Skip to: 18553
-/* 5286 */    MCD_OPC_Decode, 191, 15, 104, // Opcode: VQDMLALv2i64
-/* 5290 */    MCD_OPC_FilterValue, 1, 202, 51, 0, // Skip to: 18553
-/* 5295 */    MCD_OPC_CheckPredicate, 21, 197, 51, 0, // Skip to: 18553
-/* 5300 */    MCD_OPC_Decode, 200, 14, 116, // Opcode: VMULslfd
-/* 5304 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5341
-/* 5310 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5313 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5327
-/* 5318 */    MCD_OPC_CheckPredicate, 21, 174, 51, 0, // Skip to: 18553
-/* 5323 */    MCD_OPC_Decode, 131, 14, 105, // Opcode: VMLSv2i32
-/* 5327 */    MCD_OPC_FilterValue, 1, 165, 51, 0, // Skip to: 18553
-/* 5332 */    MCD_OPC_CheckPredicate, 21, 160, 51, 0, // Skip to: 18553
-/* 5337 */    MCD_OPC_Decode, 133, 14, 106, // Opcode: VMLSv4i32
-/* 5341 */    MCD_OPC_FilterValue, 231, 3, 150, 51, 0, // Skip to: 18553
-/* 5347 */    MCD_OPC_CheckPredicate, 21, 145, 51, 0, // Skip to: 18553
-/* 5352 */    MCD_OPC_CheckField, 6, 1, 1, 138, 51, 0, // Skip to: 18553
-/* 5359 */    MCD_OPC_Decode, 201, 14, 117, // Opcode: VMULslfq
-/* 5363 */    MCD_OPC_FilterValue, 10, 121, 0, 0, // Skip to: 5489
-/* 5368 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5371 */    MCD_OPC_FilterValue, 228, 3, 16, 0, 0, // Skip to: 5393
-/* 5377 */    MCD_OPC_CheckPredicate, 21, 115, 51, 0, // Skip to: 18553
-/* 5382 */    MCD_OPC_CheckField, 6, 1, 0, 108, 51, 0, // Skip to: 18553
-/* 5389 */    MCD_OPC_Decode, 154, 15, 97, // Opcode: VPMAXs32
-/* 5393 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5430
-/* 5399 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5402 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5416
-/* 5407 */    MCD_OPC_CheckPredicate, 21, 85, 51, 0, // Skip to: 18553
-/* 5412 */    MCD_OPC_Decode, 239, 13, 104, // Opcode: VMLSLsv2i64
-/* 5416 */    MCD_OPC_FilterValue, 1, 76, 51, 0, // Skip to: 18553
-/* 5421 */    MCD_OPC_CheckPredicate, 21, 71, 51, 0, // Skip to: 18553
-/* 5426 */    MCD_OPC_Decode, 183, 14, 118, // Opcode: VMULLslsv2i32
-/* 5430 */    MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 5452
-/* 5436 */    MCD_OPC_CheckPredicate, 21, 56, 51, 0, // Skip to: 18553
-/* 5441 */    MCD_OPC_CheckField, 6, 1, 0, 49, 51, 0, // Skip to: 18553
-/* 5448 */    MCD_OPC_Decode, 157, 15, 97, // Opcode: VPMAXu32
-/* 5452 */    MCD_OPC_FilterValue, 231, 3, 39, 51, 0, // Skip to: 18553
-/* 5458 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5461 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5475
-/* 5466 */    MCD_OPC_CheckPredicate, 21, 26, 51, 0, // Skip to: 18553
-/* 5471 */    MCD_OPC_Decode, 242, 13, 104, // Opcode: VMLSLuv2i64
-/* 5475 */    MCD_OPC_FilterValue, 1, 17, 51, 0, // Skip to: 18553
-/* 5480 */    MCD_OPC_CheckPredicate, 21, 12, 51, 0, // Skip to: 18553
-/* 5485 */    MCD_OPC_Decode, 185, 14, 118, // Opcode: VMULLsluv2i32
-/* 5489 */    MCD_OPC_FilterValue, 11, 114, 0, 0, // Skip to: 5608
-/* 5494 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5497 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5534
-/* 5503 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5506 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5520
-/* 5511 */    MCD_OPC_CheckPredicate, 21, 237, 50, 0, // Skip to: 18553
-/* 5516 */    MCD_OPC_Decode, 201, 15, 97, // Opcode: VQDMULHv2i32
-/* 5520 */    MCD_OPC_FilterValue, 1, 228, 50, 0, // Skip to: 18553
-/* 5525 */    MCD_OPC_CheckPredicate, 21, 223, 50, 0, // Skip to: 18553
-/* 5530 */    MCD_OPC_Decode, 203, 15, 98, // Opcode: VQDMULHv4i32
-/* 5534 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5571
-/* 5540 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5543 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5557
-/* 5548 */    MCD_OPC_CheckPredicate, 21, 200, 50, 0, // Skip to: 18553
-/* 5553 */    MCD_OPC_Decode, 195, 15, 104, // Opcode: VQDMLSLv2i64
-/* 5557 */    MCD_OPC_FilterValue, 1, 191, 50, 0, // Skip to: 18553
-/* 5562 */    MCD_OPC_CheckPredicate, 21, 186, 50, 0, // Skip to: 18553
-/* 5567 */    MCD_OPC_Decode, 205, 15, 118, // Opcode: VQDMULLslv2i32
-/* 5571 */    MCD_OPC_FilterValue, 230, 3, 176, 50, 0, // Skip to: 18553
-/* 5577 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5580 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5594
-/* 5585 */    MCD_OPC_CheckPredicate, 21, 163, 50, 0, // Skip to: 18553
-/* 5590 */    MCD_OPC_Decode, 244, 15, 97, // Opcode: VQRDMULHv2i32
-/* 5594 */    MCD_OPC_FilterValue, 1, 154, 50, 0, // Skip to: 18553
-/* 5599 */    MCD_OPC_CheckPredicate, 21, 149, 50, 0, // Skip to: 18553
-/* 5604 */    MCD_OPC_Decode, 246, 15, 98, // Opcode: VQRDMULHv4i32
-/* 5608 */    MCD_OPC_FilterValue, 12, 79, 0, 0, // Skip to: 5692
-/* 5613 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5616 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 5654
-/* 5621 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5624 */    MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5639
-/* 5630 */    MCD_OPC_CheckPredicate, 21, 118, 50, 0, // Skip to: 18553
-/* 5635 */    MCD_OPC_Decode, 187, 14, 99, // Opcode: VMULLsv2i64
-/* 5639 */    MCD_OPC_FilterValue, 231, 3, 108, 50, 0, // Skip to: 18553
-/* 5645 */    MCD_OPC_CheckPredicate, 21, 103, 50, 0, // Skip to: 18553
-/* 5650 */    MCD_OPC_Decode, 190, 14, 99, // Opcode: VMULLuv2i64
-/* 5654 */    MCD_OPC_FilterValue, 1, 94, 50, 0, // Skip to: 18553
-/* 5659 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5662 */    MCD_OPC_FilterValue, 229, 3, 9, 0, 0, // Skip to: 5677
-/* 5668 */    MCD_OPC_CheckPredicate, 21, 80, 50, 0, // Skip to: 18553
-/* 5673 */    MCD_OPC_Decode, 197, 15, 116, // Opcode: VQDMULHslv2i32
-/* 5677 */    MCD_OPC_FilterValue, 231, 3, 70, 50, 0, // Skip to: 18553
-/* 5683 */    MCD_OPC_CheckPredicate, 21, 65, 50, 0, // Skip to: 18553
-/* 5688 */    MCD_OPC_Decode, 199, 15, 117, // Opcode: VQDMULHslv4i32
-/* 5692 */    MCD_OPC_FilterValue, 13, 136, 0, 0, // Skip to: 5833
-/* 5697 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5700 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5737
-/* 5706 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5709 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5723
-/* 5714 */    MCD_OPC_CheckPredicate, 21, 34, 50, 0, // Skip to: 18553
-/* 5719 */    MCD_OPC_Decode, 225, 20, 97, // Opcode: VSUBfd
-/* 5723 */    MCD_OPC_FilterValue, 1, 25, 50, 0, // Skip to: 18553
-/* 5728 */    MCD_OPC_CheckPredicate, 21, 20, 50, 0, // Skip to: 18553
-/* 5733 */    MCD_OPC_Decode, 226, 20, 98, // Opcode: VSUBfq
-/* 5737 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5774
-/* 5743 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5746 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5760
-/* 5751 */    MCD_OPC_CheckPredicate, 21, 253, 49, 0, // Skip to: 18553
-/* 5756 */    MCD_OPC_Decode, 207, 15, 99, // Opcode: VQDMULLv2i64
-/* 5760 */    MCD_OPC_FilterValue, 1, 244, 49, 0, // Skip to: 18553
-/* 5765 */    MCD_OPC_CheckPredicate, 21, 239, 49, 0, // Skip to: 18553
-/* 5770 */    MCD_OPC_Decode, 240, 15, 116, // Opcode: VQRDMULHslv2i32
-/* 5774 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5811
-/* 5780 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5783 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5797
-/* 5788 */    MCD_OPC_CheckPredicate, 21, 216, 49, 0, // Skip to: 18553
-/* 5793 */    MCD_OPC_Decode, 198, 7, 97, // Opcode: VABDfd
-/* 5797 */    MCD_OPC_FilterValue, 1, 207, 49, 0, // Skip to: 18553
-/* 5802 */    MCD_OPC_CheckPredicate, 21, 202, 49, 0, // Skip to: 18553
-/* 5807 */    MCD_OPC_Decode, 199, 7, 98, // Opcode: VABDfq
-/* 5811 */    MCD_OPC_FilterValue, 231, 3, 192, 49, 0, // Skip to: 18553
-/* 5817 */    MCD_OPC_CheckPredicate, 21, 187, 49, 0, // Skip to: 18553
-/* 5822 */    MCD_OPC_CheckField, 6, 1, 1, 180, 49, 0, // Skip to: 18553
-/* 5829 */    MCD_OPC_Decode, 242, 15, 117, // Opcode: VQRDMULHslv4i32
-/* 5833 */    MCD_OPC_FilterValue, 14, 99, 0, 0, // Skip to: 5937
-/* 5838 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5841 */    MCD_OPC_FilterValue, 229, 3, 31, 0, 0, // Skip to: 5878
-/* 5847 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5850 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5864
-/* 5855 */    MCD_OPC_CheckPredicate, 24, 149, 49, 0, // Skip to: 18553
-/* 5860 */    MCD_OPC_Decode, 181, 14, 99, // Opcode: VMULLp64
-/* 5864 */    MCD_OPC_FilterValue, 1, 140, 49, 0, // Skip to: 18553
-/* 5869 */    MCD_OPC_CheckPredicate, 23, 135, 49, 0, // Skip to: 18553
-/* 5874 */    MCD_OPC_Decode, 224, 15, 113, // Opcode: VQRDMLAHslv2i32
-/* 5878 */    MCD_OPC_FilterValue, 230, 3, 31, 0, 0, // Skip to: 5915
-/* 5884 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5887 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5901
-/* 5892 */    MCD_OPC_CheckPredicate, 21, 112, 49, 0, // Skip to: 18553
-/* 5897 */    MCD_OPC_Decode, 201, 8, 97, // Opcode: VCGTfd
-/* 5901 */    MCD_OPC_FilterValue, 1, 103, 49, 0, // Skip to: 18553
-/* 5906 */    MCD_OPC_CheckPredicate, 21, 98, 49, 0, // Skip to: 18553
-/* 5911 */    MCD_OPC_Decode, 202, 8, 98, // Opcode: VCGTfq
-/* 5915 */    MCD_OPC_FilterValue, 231, 3, 88, 49, 0, // Skip to: 18553
-/* 5921 */    MCD_OPC_CheckPredicate, 23, 83, 49, 0, // Skip to: 18553
-/* 5926 */    MCD_OPC_CheckField, 6, 1, 1, 76, 49, 0, // Skip to: 18553
-/* 5933 */    MCD_OPC_Decode, 226, 15, 114, // Opcode: VQRDMLAHslv4i32
-/* 5937 */    MCD_OPC_FilterValue, 15, 67, 49, 0, // Skip to: 18553
-/* 5942 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 5945 */    MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 5982
-/* 5951 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 5954 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5968
-/* 5959 */    MCD_OPC_CheckPredicate, 21, 45, 49, 0, // Skip to: 18553
-/* 5964 */    MCD_OPC_Decode, 186, 13, 97, // Opcode: VMINfd
-/* 5968 */    MCD_OPC_FilterValue, 1, 36, 49, 0, // Skip to: 18553
-/* 5973 */    MCD_OPC_CheckPredicate, 21, 31, 49, 0, // Skip to: 18553
-/* 5978 */    MCD_OPC_Decode, 187, 13, 98, // Opcode: VMINfq
-/* 5982 */    MCD_OPC_FilterValue, 229, 3, 16, 0, 0, // Skip to: 6004
-/* 5988 */    MCD_OPC_CheckPredicate, 23, 16, 49, 0, // Skip to: 18553
-/* 5993 */    MCD_OPC_CheckField, 6, 1, 1, 9, 49, 0, // Skip to: 18553
-/* 6000 */    MCD_OPC_Decode, 232, 15, 113, // Opcode: VQRDMLSHslv2i32
-/* 6004 */    MCD_OPC_FilterValue, 230, 3, 16, 0, 0, // Skip to: 6026
-/* 6010 */    MCD_OPC_CheckPredicate, 21, 250, 48, 0, // Skip to: 18553
-/* 6015 */    MCD_OPC_CheckField, 6, 1, 0, 243, 48, 0, // Skip to: 18553
-/* 6022 */    MCD_OPC_Decode, 159, 15, 97, // Opcode: VPMINf
-/* 6026 */    MCD_OPC_FilterValue, 231, 3, 233, 48, 0, // Skip to: 18553
-/* 6032 */    MCD_OPC_CheckPredicate, 23, 228, 48, 0, // Skip to: 18553
-/* 6037 */    MCD_OPC_CheckField, 6, 1, 1, 221, 48, 0, // Skip to: 18553
-/* 6044 */    MCD_OPC_Decode, 234, 15, 114, // Opcode: VQRDMLSHslv4i32
-/* 6048 */    MCD_OPC_FilterValue, 3, 212, 48, 0, // Skip to: 18553
-/* 6053 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 6056 */    MCD_OPC_FilterValue, 228, 3, 183, 0, 0, // Skip to: 6245
-/* 6062 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 6065 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6101
-/* 6070 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6073 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6087
-/* 6078 */    MCD_OPC_CheckPredicate, 21, 182, 48, 0, // Skip to: 18553
-/* 6083 */    MCD_OPC_Decode, 137, 18, 101, // Opcode: VSHLsv1i64
-/* 6087 */    MCD_OPC_FilterValue, 1, 173, 48, 0, // Skip to: 18553
-/* 6092 */    MCD_OPC_CheckPredicate, 21, 168, 48, 0, // Skip to: 18553
-/* 6097 */    MCD_OPC_Decode, 139, 18, 102, // Opcode: VSHLsv2i64
-/* 6101 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6137
-/* 6106 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6109 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6123
-/* 6114 */    MCD_OPC_CheckPredicate, 21, 146, 48, 0, // Skip to: 18553
-/* 6119 */    MCD_OPC_Decode, 165, 17, 101, // Opcode: VRSHLsv1i64
-/* 6123 */    MCD_OPC_FilterValue, 1, 137, 48, 0, // Skip to: 18553
-/* 6128 */    MCD_OPC_CheckPredicate, 21, 132, 48, 0, // Skip to: 18553
-/* 6133 */    MCD_OPC_Decode, 167, 17, 102, // Opcode: VRSHLsv2i64
-/* 6137 */    MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6173
-/* 6142 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6145 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6159
-/* 6150 */    MCD_OPC_CheckPredicate, 21, 110, 48, 0, // Skip to: 18553
-/* 6155 */    MCD_OPC_Decode, 130, 8, 97, // Opcode: VADDv1i64
-/* 6159 */    MCD_OPC_FilterValue, 1, 101, 48, 0, // Skip to: 18553
-/* 6164 */    MCD_OPC_CheckPredicate, 21, 96, 48, 0, // Skip to: 18553
-/* 6169 */    MCD_OPC_Decode, 132, 8, 98, // Opcode: VADDv2i64
-/* 6173 */    MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6209
-/* 6178 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6181 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6195
-/* 6186 */    MCD_OPC_CheckPredicate, 22, 74, 48, 0, // Skip to: 18553
-/* 6191 */    MCD_OPC_Decode, 227, 20, 97, // Opcode: VSUBhd
-/* 6195 */    MCD_OPC_FilterValue, 1, 65, 48, 0, // Skip to: 18553
-/* 6200 */    MCD_OPC_CheckPredicate, 22, 60, 48, 0, // Skip to: 18553
-/* 6205 */    MCD_OPC_Decode, 228, 20, 98, // Opcode: VSUBhq
-/* 6209 */    MCD_OPC_FilterValue, 15, 51, 48, 0, // Skip to: 18553
-/* 6214 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6217 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6231
-/* 6222 */    MCD_OPC_CheckPredicate, 22, 38, 48, 0, // Skip to: 18553
-/* 6227 */    MCD_OPC_Decode, 188, 13, 97, // Opcode: VMINhd
-/* 6231 */    MCD_OPC_FilterValue, 1, 29, 48, 0, // Skip to: 18553
-/* 6236 */    MCD_OPC_CheckPredicate, 22, 24, 48, 0, // Skip to: 18553
-/* 6241 */    MCD_OPC_Decode, 189, 13, 98, // Opcode: VMINhq
-/* 6245 */    MCD_OPC_FilterValue, 229, 3, 119, 0, 0, // Skip to: 6370
-/* 6251 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6254 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 6308
-/* 6259 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
-/* 6262 */    MCD_OPC_FilterValue, 0, 254, 47, 0, // Skip to: 18553
-/* 6267 */    MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6283
-/* 6272 */    MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6283
-/* 6279 */    MCD_OPC_Decode, 143, 10, 119, // Opcode: VEXTd32
-/* 6283 */    MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6299
-/* 6288 */    MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6299
-/* 6295 */    MCD_OPC_Decode, 142, 10, 120, // Opcode: VEXTd16
-/* 6299 */    MCD_OPC_CheckPredicate, 21, 217, 47, 0, // Skip to: 18553
-/* 6304 */    MCD_OPC_Decode, 144, 10, 121, // Opcode: VEXTd8
-/* 6308 */    MCD_OPC_FilterValue, 1, 208, 47, 0, // Skip to: 18553
-/* 6313 */    MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6329
-/* 6318 */    MCD_OPC_CheckField, 8, 3, 0, 4, 0, 0, // Skip to: 6329
-/* 6325 */    MCD_OPC_Decode, 147, 10, 122, // Opcode: VEXTq64
-/* 6329 */    MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6345
-/* 6334 */    MCD_OPC_CheckField, 8, 2, 0, 4, 0, 0, // Skip to: 6345
-/* 6341 */    MCD_OPC_Decode, 146, 10, 123, // Opcode: VEXTq32
-/* 6345 */    MCD_OPC_CheckPredicate, 21, 11, 0, 0, // Skip to: 6361
-/* 6350 */    MCD_OPC_CheckField, 8, 1, 0, 4, 0, 0, // Skip to: 6361
-/* 6357 */    MCD_OPC_Decode, 145, 10, 124, // Opcode: VEXTq16
-/* 6361 */    MCD_OPC_CheckPredicate, 21, 155, 47, 0, // Skip to: 18553
-/* 6366 */    MCD_OPC_Decode, 148, 10, 125, // Opcode: VEXTq8
-/* 6370 */    MCD_OPC_FilterValue, 230, 3, 204, 0, 0, // Skip to: 6580
-/* 6376 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 6379 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6415
-/* 6384 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6387 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6401
-/* 6392 */    MCD_OPC_CheckPredicate, 21, 124, 47, 0, // Skip to: 18553
-/* 6397 */    MCD_OPC_Decode, 145, 18, 101, // Opcode: VSHLuv1i64
-/* 6401 */    MCD_OPC_FilterValue, 1, 115, 47, 0, // Skip to: 18553
-/* 6406 */    MCD_OPC_CheckPredicate, 21, 110, 47, 0, // Skip to: 18553
-/* 6411 */    MCD_OPC_Decode, 147, 18, 102, // Opcode: VSHLuv2i64
-/* 6415 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6451
-/* 6420 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6423 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6437
-/* 6428 */    MCD_OPC_CheckPredicate, 21, 88, 47, 0, // Skip to: 18553
-/* 6433 */    MCD_OPC_Decode, 173, 17, 101, // Opcode: VRSHLuv1i64
-/* 6437 */    MCD_OPC_FilterValue, 1, 79, 47, 0, // Skip to: 18553
-/* 6442 */    MCD_OPC_CheckPredicate, 21, 74, 47, 0, // Skip to: 18553
-/* 6447 */    MCD_OPC_Decode, 175, 17, 102, // Opcode: VRSHLuv2i64
-/* 6451 */    MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6487
-/* 6456 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6459 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6473
-/* 6464 */    MCD_OPC_CheckPredicate, 21, 52, 47, 0, // Skip to: 18553
-/* 6469 */    MCD_OPC_Decode, 230, 20, 97, // Opcode: VSUBv1i64
-/* 6473 */    MCD_OPC_FilterValue, 1, 43, 47, 0, // Skip to: 18553
-/* 6478 */    MCD_OPC_CheckPredicate, 21, 38, 47, 0, // Skip to: 18553
-/* 6483 */    MCD_OPC_Decode, 232, 20, 98, // Opcode: VSUBv2i64
-/* 6487 */    MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 6523
-/* 6492 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6495 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6509
-/* 6500 */    MCD_OPC_CheckPredicate, 22, 16, 47, 0, // Skip to: 18553
-/* 6505 */    MCD_OPC_Decode, 200, 7, 97, // Opcode: VABDhd
-/* 6509 */    MCD_OPC_FilterValue, 1, 7, 47, 0, // Skip to: 18553
-/* 6514 */    MCD_OPC_CheckPredicate, 22, 2, 47, 0, // Skip to: 18553
-/* 6519 */    MCD_OPC_Decode, 201, 7, 98, // Opcode: VABDhq
-/* 6523 */    MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 6559
-/* 6528 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 6531 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6545
-/* 6536 */    MCD_OPC_CheckPredicate, 22, 236, 46, 0, // Skip to: 18553
-/* 6541 */    MCD_OPC_Decode, 203, 8, 97, // Opcode: VCGThd
-/* 6545 */    MCD_OPC_FilterValue, 1, 227, 46, 0, // Skip to: 18553
-/* 6550 */    MCD_OPC_CheckPredicate, 22, 222, 46, 0, // Skip to: 18553
-/* 6555 */    MCD_OPC_Decode, 204, 8, 98, // Opcode: VCGThq
-/* 6559 */    MCD_OPC_FilterValue, 15, 213, 46, 0, // Skip to: 18553
-/* 6564 */    MCD_OPC_CheckPredicate, 22, 208, 46, 0, // Skip to: 18553
-/* 6569 */    MCD_OPC_CheckField, 6, 1, 0, 201, 46, 0, // Skip to: 18553
-/* 6576 */    MCD_OPC_Decode, 160, 15, 97, // Opcode: VPMINh
-/* 6580 */    MCD_OPC_FilterValue, 231, 3, 191, 46, 0, // Skip to: 18553
-/* 6586 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 6589 */    MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 7097
-/* 6594 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 6597 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 6661
-/* 6602 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6605 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6619
-/* 6610 */    MCD_OPC_CheckPredicate, 21, 162, 46, 0, // Skip to: 18553
-/* 6615 */    MCD_OPC_Decode, 231, 16, 126, // Opcode: VREV64d8
-/* 6619 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6633
-/* 6624 */    MCD_OPC_CheckPredicate, 21, 148, 46, 0, // Skip to: 18553
-/* 6629 */    MCD_OPC_Decode, 234, 16, 127, // Opcode: VREV64q8
-/* 6633 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6647
-/* 6638 */    MCD_OPC_CheckPredicate, 21, 134, 46, 0, // Skip to: 18553
-/* 6643 */    MCD_OPC_Decode, 226, 16, 126, // Opcode: VREV32d8
-/* 6647 */    MCD_OPC_FilterValue, 3, 125, 46, 0, // Skip to: 18553
-/* 6652 */    MCD_OPC_CheckPredicate, 21, 120, 46, 0, // Skip to: 18553
-/* 6657 */    MCD_OPC_Decode, 228, 16, 127, // Opcode: VREV32q8
-/* 6661 */    MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 6725
-/* 6666 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6669 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6683
-/* 6674 */    MCD_OPC_CheckPredicate, 21, 98, 46, 0, // Skip to: 18553
-/* 6679 */    MCD_OPC_Decode, 226, 8, 126, // Opcode: VCGTzv8i8
-/* 6683 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6697
-/* 6688 */    MCD_OPC_CheckPredicate, 21, 84, 46, 0, // Skip to: 18553
-/* 6693 */    MCD_OPC_Decode, 217, 8, 127, // Opcode: VCGTzv16i8
-/* 6697 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6711
-/* 6702 */    MCD_OPC_CheckPredicate, 21, 70, 46, 0, // Skip to: 18553
-/* 6707 */    MCD_OPC_Decode, 200, 8, 126, // Opcode: VCGEzv8i8
-/* 6711 */    MCD_OPC_FilterValue, 3, 61, 46, 0, // Skip to: 18553
-/* 6716 */    MCD_OPC_CheckPredicate, 21, 56, 46, 0, // Skip to: 18553
-/* 6721 */    MCD_OPC_Decode, 191, 8, 127, // Opcode: VCGEzv16i8
-/* 6725 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 6793
-/* 6730 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6733 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6748
-/* 6738 */    MCD_OPC_CheckPredicate, 21, 34, 46, 0, // Skip to: 18553
-/* 6743 */    MCD_OPC_Decode, 237, 20, 128, 1, // Opcode: VSWPd
-/* 6748 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6763
-/* 6753 */    MCD_OPC_CheckPredicate, 21, 19, 46, 0, // Skip to: 18553
-/* 6758 */    MCD_OPC_Decode, 238, 20, 129, 1, // Opcode: VSWPq
-/* 6763 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6778
-/* 6768 */    MCD_OPC_CheckPredicate, 21, 4, 46, 0, // Skip to: 18553
-/* 6773 */    MCD_OPC_Decode, 149, 21, 128, 1, // Opcode: VTRNd8
-/* 6778 */    MCD_OPC_FilterValue, 3, 250, 45, 0, // Skip to: 18553
-/* 6783 */    MCD_OPC_CheckPredicate, 21, 245, 45, 0, // Skip to: 18553
-/* 6788 */    MCD_OPC_Decode, 152, 21, 129, 1, // Opcode: VTRNq8
-/* 6793 */    MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 6857
-/* 6798 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6801 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6815
-/* 6806 */    MCD_OPC_CheckPredicate, 21, 222, 45, 0, // Skip to: 18553
-/* 6811 */    MCD_OPC_Decode, 229, 16, 126, // Opcode: VREV64d16
-/* 6815 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6829
-/* 6820 */    MCD_OPC_CheckPredicate, 21, 208, 45, 0, // Skip to: 18553
-/* 6825 */    MCD_OPC_Decode, 232, 16, 127, // Opcode: VREV64q16
-/* 6829 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6843
-/* 6834 */    MCD_OPC_CheckPredicate, 21, 194, 45, 0, // Skip to: 18553
-/* 6839 */    MCD_OPC_Decode, 225, 16, 126, // Opcode: VREV32d16
-/* 6843 */    MCD_OPC_FilterValue, 3, 185, 45, 0, // Skip to: 18553
-/* 6848 */    MCD_OPC_CheckPredicate, 21, 180, 45, 0, // Skip to: 18553
-/* 6853 */    MCD_OPC_Decode, 227, 16, 127, // Opcode: VREV32q16
-/* 6857 */    MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 6921
-/* 6862 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6865 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6879
-/* 6870 */    MCD_OPC_CheckPredicate, 21, 158, 45, 0, // Skip to: 18553
-/* 6875 */    MCD_OPC_Decode, 222, 8, 126, // Opcode: VCGTzv4i16
-/* 6879 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6893
-/* 6884 */    MCD_OPC_CheckPredicate, 21, 144, 45, 0, // Skip to: 18553
-/* 6889 */    MCD_OPC_Decode, 225, 8, 127, // Opcode: VCGTzv8i16
-/* 6893 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6907
-/* 6898 */    MCD_OPC_CheckPredicate, 21, 130, 45, 0, // Skip to: 18553
-/* 6903 */    MCD_OPC_Decode, 196, 8, 126, // Opcode: VCGEzv4i16
-/* 6907 */    MCD_OPC_FilterValue, 3, 121, 45, 0, // Skip to: 18553
-/* 6912 */    MCD_OPC_CheckPredicate, 21, 116, 45, 0, // Skip to: 18553
-/* 6917 */    MCD_OPC_Decode, 199, 8, 127, // Opcode: VCGEzv8i16
-/* 6921 */    MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 6959
-/* 6926 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6929 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6944
-/* 6934 */    MCD_OPC_CheckPredicate, 21, 94, 45, 0, // Skip to: 18553
-/* 6939 */    MCD_OPC_Decode, 147, 21, 128, 1, // Opcode: VTRNd16
-/* 6944 */    MCD_OPC_FilterValue, 3, 84, 45, 0, // Skip to: 18553
-/* 6949 */    MCD_OPC_CheckPredicate, 21, 79, 45, 0, // Skip to: 18553
-/* 6954 */    MCD_OPC_Decode, 150, 21, 129, 1, // Opcode: VTRNq16
-/* 6959 */    MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 6995
-/* 6964 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 6967 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6981
-/* 6972 */    MCD_OPC_CheckPredicate, 21, 56, 45, 0, // Skip to: 18553
-/* 6977 */    MCD_OPC_Decode, 230, 16, 126, // Opcode: VREV64d32
-/* 6981 */    MCD_OPC_FilterValue, 1, 47, 45, 0, // Skip to: 18553
-/* 6986 */    MCD_OPC_CheckPredicate, 21, 42, 45, 0, // Skip to: 18553
-/* 6991 */    MCD_OPC_Decode, 233, 16, 127, // Opcode: VREV64q32
-/* 6995 */    MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7059
-/* 7000 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7003 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7017
-/* 7008 */    MCD_OPC_CheckPredicate, 21, 20, 45, 0, // Skip to: 18553
-/* 7013 */    MCD_OPC_Decode, 219, 8, 126, // Opcode: VCGTzv2i32
-/* 7017 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7031
-/* 7022 */    MCD_OPC_CheckPredicate, 21, 6, 45, 0, // Skip to: 18553
-/* 7027 */    MCD_OPC_Decode, 223, 8, 127, // Opcode: VCGTzv4i32
-/* 7031 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7045
-/* 7036 */    MCD_OPC_CheckPredicate, 21, 248, 44, 0, // Skip to: 18553
-/* 7041 */    MCD_OPC_Decode, 193, 8, 126, // Opcode: VCGEzv2i32
-/* 7045 */    MCD_OPC_FilterValue, 3, 239, 44, 0, // Skip to: 18553
-/* 7050 */    MCD_OPC_CheckPredicate, 21, 234, 44, 0, // Skip to: 18553
-/* 7055 */    MCD_OPC_Decode, 197, 8, 127, // Opcode: VCGEzv4i32
-/* 7059 */    MCD_OPC_FilterValue, 10, 225, 44, 0, // Skip to: 18553
-/* 7064 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7067 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7082
-/* 7072 */    MCD_OPC_CheckPredicate, 21, 212, 44, 0, // Skip to: 18553
-/* 7077 */    MCD_OPC_Decode, 148, 21, 128, 1, // Opcode: VTRNd32
-/* 7082 */    MCD_OPC_FilterValue, 3, 202, 44, 0, // Skip to: 18553
-/* 7087 */    MCD_OPC_CheckPredicate, 21, 197, 44, 0, // Skip to: 18553
-/* 7092 */    MCD_OPC_Decode, 151, 21, 129, 1, // Opcode: VTRNq32
-/* 7097 */    MCD_OPC_FilterValue, 1, 149, 1, 0, // Skip to: 7507
-/* 7102 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 7105 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7141
-/* 7110 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7113 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7127
-/* 7118 */    MCD_OPC_CheckPredicate, 21, 166, 44, 0, // Skip to: 18553
-/* 7123 */    MCD_OPC_Decode, 223, 16, 126, // Opcode: VREV16d8
-/* 7127 */    MCD_OPC_FilterValue, 1, 157, 44, 0, // Skip to: 18553
-/* 7132 */    MCD_OPC_CheckPredicate, 21, 152, 44, 0, // Skip to: 18553
-/* 7137 */    MCD_OPC_Decode, 224, 16, 127, // Opcode: VREV16q8
-/* 7141 */    MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 7205
-/* 7146 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7149 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7163
-/* 7154 */    MCD_OPC_CheckPredicate, 21, 130, 44, 0, // Skip to: 18553
-/* 7159 */    MCD_OPC_Decode, 174, 8, 126, // Opcode: VCEQzv8i8
-/* 7163 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7177
-/* 7168 */    MCD_OPC_CheckPredicate, 21, 116, 44, 0, // Skip to: 18553
-/* 7173 */    MCD_OPC_Decode, 165, 8, 127, // Opcode: VCEQzv16i8
-/* 7177 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7191
-/* 7182 */    MCD_OPC_CheckPredicate, 21, 102, 44, 0, // Skip to: 18553
-/* 7187 */    MCD_OPC_Decode, 236, 8, 126, // Opcode: VCLEzv8i8
-/* 7191 */    MCD_OPC_FilterValue, 3, 93, 44, 0, // Skip to: 18553
-/* 7196 */    MCD_OPC_CheckPredicate, 21, 88, 44, 0, // Skip to: 18553
-/* 7201 */    MCD_OPC_Decode, 227, 8, 127, // Opcode: VCLEzv16i8
-/* 7205 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7273
-/* 7210 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7213 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7228
-/* 7218 */    MCD_OPC_CheckPredicate, 21, 66, 44, 0, // Skip to: 18553
-/* 7223 */    MCD_OPC_Decode, 173, 21, 128, 1, // Opcode: VUZPd8
-/* 7228 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7243
-/* 7233 */    MCD_OPC_CheckPredicate, 21, 51, 44, 0, // Skip to: 18553
-/* 7238 */    MCD_OPC_Decode, 176, 21, 129, 1, // Opcode: VUZPq8
-/* 7243 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7258
-/* 7248 */    MCD_OPC_CheckPredicate, 21, 36, 44, 0, // Skip to: 18553
-/* 7253 */    MCD_OPC_Decode, 178, 21, 128, 1, // Opcode: VZIPd8
-/* 7258 */    MCD_OPC_FilterValue, 3, 26, 44, 0, // Skip to: 18553
-/* 7263 */    MCD_OPC_CheckPredicate, 21, 21, 44, 0, // Skip to: 18553
-/* 7268 */    MCD_OPC_Decode, 181, 21, 129, 1, // Opcode: VZIPq8
-/* 7273 */    MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 7337
-/* 7278 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7281 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7295
-/* 7286 */    MCD_OPC_CheckPredicate, 21, 254, 43, 0, // Skip to: 18553
-/* 7291 */    MCD_OPC_Decode, 170, 8, 126, // Opcode: VCEQzv4i16
-/* 7295 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7309
-/* 7300 */    MCD_OPC_CheckPredicate, 21, 240, 43, 0, // Skip to: 18553
-/* 7305 */    MCD_OPC_Decode, 173, 8, 127, // Opcode: VCEQzv8i16
-/* 7309 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7323
-/* 7314 */    MCD_OPC_CheckPredicate, 21, 226, 43, 0, // Skip to: 18553
-/* 7319 */    MCD_OPC_Decode, 232, 8, 126, // Opcode: VCLEzv4i16
-/* 7323 */    MCD_OPC_FilterValue, 3, 217, 43, 0, // Skip to: 18553
-/* 7328 */    MCD_OPC_CheckPredicate, 21, 212, 43, 0, // Skip to: 18553
-/* 7333 */    MCD_OPC_Decode, 235, 8, 127, // Opcode: VCLEzv8i16
-/* 7337 */    MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7405
-/* 7342 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7345 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7360
-/* 7350 */    MCD_OPC_CheckPredicate, 21, 190, 43, 0, // Skip to: 18553
-/* 7355 */    MCD_OPC_Decode, 172, 21, 128, 1, // Opcode: VUZPd16
-/* 7360 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7375
-/* 7365 */    MCD_OPC_CheckPredicate, 21, 175, 43, 0, // Skip to: 18553
-/* 7370 */    MCD_OPC_Decode, 174, 21, 129, 1, // Opcode: VUZPq16
-/* 7375 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7390
-/* 7380 */    MCD_OPC_CheckPredicate, 21, 160, 43, 0, // Skip to: 18553
-/* 7385 */    MCD_OPC_Decode, 177, 21, 128, 1, // Opcode: VZIPd16
-/* 7390 */    MCD_OPC_FilterValue, 3, 150, 43, 0, // Skip to: 18553
-/* 7395 */    MCD_OPC_CheckPredicate, 21, 145, 43, 0, // Skip to: 18553
-/* 7400 */    MCD_OPC_Decode, 179, 21, 129, 1, // Opcode: VZIPq16
-/* 7405 */    MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 7469
-/* 7410 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7413 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7427
-/* 7418 */    MCD_OPC_CheckPredicate, 21, 122, 43, 0, // Skip to: 18553
-/* 7423 */    MCD_OPC_Decode, 167, 8, 126, // Opcode: VCEQzv2i32
-/* 7427 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7441
-/* 7432 */    MCD_OPC_CheckPredicate, 21, 108, 43, 0, // Skip to: 18553
-/* 7437 */    MCD_OPC_Decode, 171, 8, 127, // Opcode: VCEQzv4i32
-/* 7441 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7455
-/* 7446 */    MCD_OPC_CheckPredicate, 21, 94, 43, 0, // Skip to: 18553
-/* 7451 */    MCD_OPC_Decode, 229, 8, 126, // Opcode: VCLEzv2i32
-/* 7455 */    MCD_OPC_FilterValue, 3, 85, 43, 0, // Skip to: 18553
-/* 7460 */    MCD_OPC_CheckPredicate, 21, 80, 43, 0, // Skip to: 18553
-/* 7465 */    MCD_OPC_Decode, 233, 8, 127, // Opcode: VCLEzv4i32
-/* 7469 */    MCD_OPC_FilterValue, 10, 71, 43, 0, // Skip to: 18553
-/* 7474 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7477 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7492
-/* 7482 */    MCD_OPC_CheckPredicate, 21, 58, 43, 0, // Skip to: 18553
-/* 7487 */    MCD_OPC_Decode, 175, 21, 129, 1, // Opcode: VUZPq32
-/* 7492 */    MCD_OPC_FilterValue, 3, 48, 43, 0, // Skip to: 18553
-/* 7497 */    MCD_OPC_CheckPredicate, 21, 43, 43, 0, // Skip to: 18553
-/* 7502 */    MCD_OPC_Decode, 180, 21, 129, 1, // Opcode: VZIPq32
-/* 7507 */    MCD_OPC_FilterValue, 2, 251, 1, 0, // Skip to: 8019
-/* 7512 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 7515 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 7579
-/* 7520 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7523 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7537
-/* 7528 */    MCD_OPC_CheckPredicate, 21, 12, 43, 0, // Skip to: 18553
-/* 7533 */    MCD_OPC_Decode, 139, 15, 126, // Opcode: VPADDLsv8i8
-/* 7537 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7551
-/* 7542 */    MCD_OPC_CheckPredicate, 21, 254, 42, 0, // Skip to: 18553
-/* 7547 */    MCD_OPC_Decode, 134, 15, 127, // Opcode: VPADDLsv16i8
-/* 7551 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7565
-/* 7556 */    MCD_OPC_CheckPredicate, 21, 240, 42, 0, // Skip to: 18553
-/* 7561 */    MCD_OPC_Decode, 145, 15, 126, // Opcode: VPADDLuv8i8
-/* 7565 */    MCD_OPC_FilterValue, 3, 231, 42, 0, // Skip to: 18553
-/* 7570 */    MCD_OPC_CheckPredicate, 21, 226, 42, 0, // Skip to: 18553
-/* 7575 */    MCD_OPC_Decode, 140, 15, 127, // Opcode: VPADDLuv16i8
-/* 7579 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7615
-/* 7584 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7587 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7601
-/* 7592 */    MCD_OPC_CheckPredicate, 21, 204, 42, 0, // Skip to: 18553
-/* 7597 */    MCD_OPC_Decode, 252, 8, 126, // Opcode: VCLTzv8i8
-/* 7601 */    MCD_OPC_FilterValue, 1, 195, 42, 0, // Skip to: 18553
-/* 7606 */    MCD_OPC_CheckPredicate, 21, 190, 42, 0, // Skip to: 18553
-/* 7611 */    MCD_OPC_Decode, 243, 8, 127, // Opcode: VCLTzv16i8
-/* 7615 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7683
-/* 7620 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7623 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7638
-/* 7628 */    MCD_OPC_CheckPredicate, 21, 168, 42, 0, // Skip to: 18553
-/* 7633 */    MCD_OPC_Decode, 148, 14, 130, 1, // Opcode: VMOVNv8i8
-/* 7638 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7653
-/* 7643 */    MCD_OPC_CheckPredicate, 21, 153, 42, 0, // Skip to: 18553
-/* 7648 */    MCD_OPC_Decode, 211, 15, 130, 1, // Opcode: VQMOVNsuv8i8
-/* 7653 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7668
-/* 7658 */    MCD_OPC_CheckPredicate, 21, 138, 42, 0, // Skip to: 18553
-/* 7663 */    MCD_OPC_Decode, 214, 15, 130, 1, // Opcode: VQMOVNsv8i8
-/* 7668 */    MCD_OPC_FilterValue, 3, 128, 42, 0, // Skip to: 18553
-/* 7673 */    MCD_OPC_CheckPredicate, 21, 123, 42, 0, // Skip to: 18553
-/* 7678 */    MCD_OPC_Decode, 217, 15, 130, 1, // Opcode: VQMOVNuv8i8
-/* 7683 */    MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 7747
-/* 7688 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7691 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7705
-/* 7696 */    MCD_OPC_CheckPredicate, 21, 100, 42, 0, // Skip to: 18553
-/* 7701 */    MCD_OPC_Decode, 136, 15, 126, // Opcode: VPADDLsv4i16
-/* 7705 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7719
-/* 7710 */    MCD_OPC_CheckPredicate, 21, 86, 42, 0, // Skip to: 18553
-/* 7715 */    MCD_OPC_Decode, 138, 15, 127, // Opcode: VPADDLsv8i16
-/* 7719 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7733
-/* 7724 */    MCD_OPC_CheckPredicate, 21, 72, 42, 0, // Skip to: 18553
-/* 7729 */    MCD_OPC_Decode, 142, 15, 126, // Opcode: VPADDLuv4i16
-/* 7733 */    MCD_OPC_FilterValue, 3, 63, 42, 0, // Skip to: 18553
-/* 7738 */    MCD_OPC_CheckPredicate, 21, 58, 42, 0, // Skip to: 18553
-/* 7743 */    MCD_OPC_Decode, 144, 15, 127, // Opcode: VPADDLuv8i16
-/* 7747 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 7783
-/* 7752 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7755 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7769
-/* 7760 */    MCD_OPC_CheckPredicate, 21, 36, 42, 0, // Skip to: 18553
-/* 7765 */    MCD_OPC_Decode, 248, 8, 126, // Opcode: VCLTzv4i16
-/* 7769 */    MCD_OPC_FilterValue, 1, 27, 42, 0, // Skip to: 18553
-/* 7774 */    MCD_OPC_CheckPredicate, 21, 22, 42, 0, // Skip to: 18553
-/* 7779 */    MCD_OPC_Decode, 251, 8, 127, // Opcode: VCLTzv8i16
-/* 7783 */    MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7851
-/* 7788 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7791 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7806
-/* 7796 */    MCD_OPC_CheckPredicate, 21, 0, 42, 0, // Skip to: 18553
-/* 7801 */    MCD_OPC_Decode, 147, 14, 130, 1, // Opcode: VMOVNv4i16
-/* 7806 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7821
-/* 7811 */    MCD_OPC_CheckPredicate, 21, 241, 41, 0, // Skip to: 18553
-/* 7816 */    MCD_OPC_Decode, 210, 15, 130, 1, // Opcode: VQMOVNsuv4i16
-/* 7821 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7836
-/* 7826 */    MCD_OPC_CheckPredicate, 21, 226, 41, 0, // Skip to: 18553
-/* 7831 */    MCD_OPC_Decode, 213, 15, 130, 1, // Opcode: VQMOVNsv4i16
-/* 7836 */    MCD_OPC_FilterValue, 3, 216, 41, 0, // Skip to: 18553
-/* 7841 */    MCD_OPC_CheckPredicate, 21, 211, 41, 0, // Skip to: 18553
-/* 7846 */    MCD_OPC_Decode, 216, 15, 130, 1, // Opcode: VQMOVNuv4i16
-/* 7851 */    MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 7915
-/* 7856 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7859 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7873
-/* 7864 */    MCD_OPC_CheckPredicate, 21, 188, 41, 0, // Skip to: 18553
-/* 7869 */    MCD_OPC_Decode, 135, 15, 126, // Opcode: VPADDLsv2i32
-/* 7873 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 7887
-/* 7878 */    MCD_OPC_CheckPredicate, 21, 174, 41, 0, // Skip to: 18553
-/* 7883 */    MCD_OPC_Decode, 137, 15, 127, // Opcode: VPADDLsv4i32
-/* 7887 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 7901
-/* 7892 */    MCD_OPC_CheckPredicate, 21, 160, 41, 0, // Skip to: 18553
-/* 7897 */    MCD_OPC_Decode, 141, 15, 126, // Opcode: VPADDLuv2i32
-/* 7901 */    MCD_OPC_FilterValue, 3, 151, 41, 0, // Skip to: 18553
-/* 7906 */    MCD_OPC_CheckPredicate, 21, 146, 41, 0, // Skip to: 18553
-/* 7911 */    MCD_OPC_Decode, 143, 15, 127, // Opcode: VPADDLuv4i32
-/* 7915 */    MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7951
-/* 7920 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7923 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7937
-/* 7928 */    MCD_OPC_CheckPredicate, 21, 124, 41, 0, // Skip to: 18553
-/* 7933 */    MCD_OPC_Decode, 245, 8, 126, // Opcode: VCLTzv2i32
-/* 7937 */    MCD_OPC_FilterValue, 1, 115, 41, 0, // Skip to: 18553
-/* 7942 */    MCD_OPC_CheckPredicate, 21, 110, 41, 0, // Skip to: 18553
-/* 7947 */    MCD_OPC_Decode, 249, 8, 127, // Opcode: VCLTzv4i32
-/* 7951 */    MCD_OPC_FilterValue, 10, 101, 41, 0, // Skip to: 18553
-/* 7956 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 7959 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7974
-/* 7964 */    MCD_OPC_CheckPredicate, 21, 88, 41, 0, // Skip to: 18553
-/* 7969 */    MCD_OPC_Decode, 146, 14, 130, 1, // Opcode: VMOVNv2i32
-/* 7974 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7989
-/* 7979 */    MCD_OPC_CheckPredicate, 21, 73, 41, 0, // Skip to: 18553
-/* 7984 */    MCD_OPC_Decode, 209, 15, 130, 1, // Opcode: VQMOVNsuv2i32
-/* 7989 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8004
-/* 7994 */    MCD_OPC_CheckPredicate, 21, 58, 41, 0, // Skip to: 18553
-/* 7999 */    MCD_OPC_Decode, 212, 15, 130, 1, // Opcode: VQMOVNsv2i32
-/* 8004 */    MCD_OPC_FilterValue, 3, 48, 41, 0, // Skip to: 18553
-/* 8009 */    MCD_OPC_CheckPredicate, 21, 43, 41, 0, // Skip to: 18553
-/* 8014 */    MCD_OPC_Decode, 215, 15, 130, 1, // Opcode: VQMOVNuv2i32
-/* 8019 */    MCD_OPC_FilterValue, 3, 5, 1, 0, // Skip to: 8285
-/* 8024 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 8027 */    MCD_OPC_FilterValue, 1, 59, 0, 0, // Skip to: 8091
-/* 8032 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8035 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8049
-/* 8040 */    MCD_OPC_CheckPredicate, 21, 12, 41, 0, // Skip to: 18553
-/* 8045 */    MCD_OPC_Decode, 226, 7, 126, // Opcode: VABSv8i8
-/* 8049 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8063
-/* 8054 */    MCD_OPC_CheckPredicate, 21, 254, 40, 0, // Skip to: 18553
-/* 8059 */    MCD_OPC_Decode, 221, 7, 127, // Opcode: VABSv16i8
-/* 8063 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8077
-/* 8068 */    MCD_OPC_CheckPredicate, 21, 240, 40, 0, // Skip to: 18553
-/* 8073 */    MCD_OPC_Decode, 231, 14, 126, // Opcode: VNEGs8d
-/* 8077 */    MCD_OPC_FilterValue, 3, 231, 40, 0, // Skip to: 18553
-/* 8082 */    MCD_OPC_CheckPredicate, 21, 226, 40, 0, // Skip to: 18553
-/* 8087 */    MCD_OPC_Decode, 232, 14, 127, // Opcode: VNEGs8q
-/* 8091 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 8113
-/* 8096 */    MCD_OPC_CheckPredicate, 21, 212, 40, 0, // Skip to: 18553
-/* 8101 */    MCD_OPC_CheckField, 6, 2, 0, 205, 40, 0, // Skip to: 18553
-/* 8108 */    MCD_OPC_Decode, 249, 17, 131, 1, // Opcode: VSHLLi8
-/* 8113 */    MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8177
-/* 8118 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8121 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8135
-/* 8126 */    MCD_OPC_CheckPredicate, 21, 182, 40, 0, // Skip to: 18553
-/* 8131 */    MCD_OPC_Decode, 223, 7, 126, // Opcode: VABSv4i16
-/* 8135 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8149
-/* 8140 */    MCD_OPC_CheckPredicate, 21, 168, 40, 0, // Skip to: 18553
-/* 8145 */    MCD_OPC_Decode, 225, 7, 127, // Opcode: VABSv8i16
-/* 8149 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8163
-/* 8154 */    MCD_OPC_CheckPredicate, 21, 154, 40, 0, // Skip to: 18553
-/* 8159 */    MCD_OPC_Decode, 227, 14, 126, // Opcode: VNEGs16d
-/* 8163 */    MCD_OPC_FilterValue, 3, 145, 40, 0, // Skip to: 18553
-/* 8168 */    MCD_OPC_CheckPredicate, 21, 140, 40, 0, // Skip to: 18553
-/* 8173 */    MCD_OPC_Decode, 228, 14, 127, // Opcode: VNEGs16q
-/* 8177 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 8199
-/* 8182 */    MCD_OPC_CheckPredicate, 21, 126, 40, 0, // Skip to: 18553
-/* 8187 */    MCD_OPC_CheckField, 6, 2, 0, 119, 40, 0, // Skip to: 18553
-/* 8194 */    MCD_OPC_Decode, 247, 17, 131, 1, // Opcode: VSHLLi16
-/* 8199 */    MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8263
-/* 8204 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8207 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8221
-/* 8212 */    MCD_OPC_CheckPredicate, 21, 96, 40, 0, // Skip to: 18553
-/* 8217 */    MCD_OPC_Decode, 222, 7, 126, // Opcode: VABSv2i32
-/* 8221 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8235
-/* 8226 */    MCD_OPC_CheckPredicate, 21, 82, 40, 0, // Skip to: 18553
-/* 8231 */    MCD_OPC_Decode, 224, 7, 127, // Opcode: VABSv4i32
-/* 8235 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8249
-/* 8240 */    MCD_OPC_CheckPredicate, 21, 68, 40, 0, // Skip to: 18553
-/* 8245 */    MCD_OPC_Decode, 229, 14, 126, // Opcode: VNEGs32d
-/* 8249 */    MCD_OPC_FilterValue, 3, 59, 40, 0, // Skip to: 18553
-/* 8254 */    MCD_OPC_CheckPredicate, 21, 54, 40, 0, // Skip to: 18553
-/* 8259 */    MCD_OPC_Decode, 230, 14, 127, // Opcode: VNEGs32q
-/* 8263 */    MCD_OPC_FilterValue, 10, 45, 40, 0, // Skip to: 18553
-/* 8268 */    MCD_OPC_CheckPredicate, 21, 40, 40, 0, // Skip to: 18553
-/* 8273 */    MCD_OPC_CheckField, 6, 2, 0, 33, 40, 0, // Skip to: 18553
-/* 8280 */    MCD_OPC_Decode, 248, 17, 131, 1, // Opcode: VSHLLi32
-/* 8285 */    MCD_OPC_FilterValue, 4, 131, 1, 0, // Skip to: 8677
-/* 8290 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 8293 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8357
-/* 8298 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8301 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8315
-/* 8306 */    MCD_OPC_CheckPredicate, 21, 2, 40, 0, // Skip to: 18553
-/* 8311 */    MCD_OPC_Decode, 242, 8, 126, // Opcode: VCLSv8i8
-/* 8315 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8329
-/* 8320 */    MCD_OPC_CheckPredicate, 21, 244, 39, 0, // Skip to: 18553
-/* 8325 */    MCD_OPC_Decode, 237, 8, 127, // Opcode: VCLSv16i8
-/* 8329 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8343
-/* 8334 */    MCD_OPC_CheckPredicate, 21, 230, 39, 0, // Skip to: 18553
-/* 8339 */    MCD_OPC_Decode, 130, 9, 126, // Opcode: VCLZv8i8
-/* 8343 */    MCD_OPC_FilterValue, 3, 221, 39, 0, // Skip to: 18553
-/* 8348 */    MCD_OPC_CheckPredicate, 21, 216, 39, 0, // Skip to: 18553
-/* 8353 */    MCD_OPC_Decode, 253, 8, 127, // Opcode: VCLZv16i8
-/* 8357 */    MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 8421
-/* 8362 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8365 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8379
-/* 8370 */    MCD_OPC_CheckPredicate, 21, 194, 39, 0, // Skip to: 18553
-/* 8375 */    MCD_OPC_Decode, 239, 8, 126, // Opcode: VCLSv4i16
-/* 8379 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8393
-/* 8384 */    MCD_OPC_CheckPredicate, 21, 180, 39, 0, // Skip to: 18553
-/* 8389 */    MCD_OPC_Decode, 241, 8, 127, // Opcode: VCLSv8i16
-/* 8393 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8407
-/* 8398 */    MCD_OPC_CheckPredicate, 21, 166, 39, 0, // Skip to: 18553
-/* 8403 */    MCD_OPC_Decode, 255, 8, 126, // Opcode: VCLZv4i16
-/* 8407 */    MCD_OPC_FilterValue, 3, 157, 39, 0, // Skip to: 18553
-/* 8412 */    MCD_OPC_CheckPredicate, 21, 152, 39, 0, // Skip to: 18553
-/* 8417 */    MCD_OPC_Decode, 129, 9, 127, // Opcode: VCLZv8i16
-/* 8421 */    MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8485
-/* 8426 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8429 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8443
-/* 8434 */    MCD_OPC_CheckPredicate, 22, 130, 39, 0, // Skip to: 18553
-/* 8439 */    MCD_OPC_Decode, 220, 8, 126, // Opcode: VCGTzv4f16
-/* 8443 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8457
-/* 8448 */    MCD_OPC_CheckPredicate, 22, 116, 39, 0, // Skip to: 18553
-/* 8453 */    MCD_OPC_Decode, 224, 8, 127, // Opcode: VCGTzv8f16
-/* 8457 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8471
-/* 8462 */    MCD_OPC_CheckPredicate, 22, 102, 39, 0, // Skip to: 18553
-/* 8467 */    MCD_OPC_Decode, 194, 8, 126, // Opcode: VCGEzv4f16
-/* 8471 */    MCD_OPC_FilterValue, 3, 93, 39, 0, // Skip to: 18553
-/* 8476 */    MCD_OPC_CheckPredicate, 22, 88, 39, 0, // Skip to: 18553
-/* 8481 */    MCD_OPC_Decode, 198, 8, 127, // Opcode: VCGEzv8f16
-/* 8485 */    MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 8549
-/* 8490 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8493 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8507
-/* 8498 */    MCD_OPC_CheckPredicate, 21, 66, 39, 0, // Skip to: 18553
-/* 8503 */    MCD_OPC_Decode, 238, 8, 126, // Opcode: VCLSv2i32
-/* 8507 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8521
-/* 8512 */    MCD_OPC_CheckPredicate, 21, 52, 39, 0, // Skip to: 18553
-/* 8517 */    MCD_OPC_Decode, 240, 8, 127, // Opcode: VCLSv4i32
-/* 8521 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8535
-/* 8526 */    MCD_OPC_CheckPredicate, 21, 38, 39, 0, // Skip to: 18553
-/* 8531 */    MCD_OPC_Decode, 254, 8, 126, // Opcode: VCLZv2i32
-/* 8535 */    MCD_OPC_FilterValue, 3, 29, 39, 0, // Skip to: 18553
-/* 8540 */    MCD_OPC_CheckPredicate, 21, 24, 39, 0, // Skip to: 18553
-/* 8545 */    MCD_OPC_Decode, 128, 9, 127, // Opcode: VCLZv4i32
-/* 8549 */    MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8613
-/* 8554 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8557 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8571
-/* 8562 */    MCD_OPC_CheckPredicate, 21, 2, 39, 0, // Skip to: 18553
-/* 8567 */    MCD_OPC_Decode, 218, 8, 126, // Opcode: VCGTzv2f32
-/* 8571 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8585
-/* 8576 */    MCD_OPC_CheckPredicate, 21, 244, 38, 0, // Skip to: 18553
-/* 8581 */    MCD_OPC_Decode, 221, 8, 127, // Opcode: VCGTzv4f32
-/* 8585 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8599
-/* 8590 */    MCD_OPC_CheckPredicate, 21, 230, 38, 0, // Skip to: 18553
-/* 8595 */    MCD_OPC_Decode, 192, 8, 126, // Opcode: VCGEzv2f32
-/* 8599 */    MCD_OPC_FilterValue, 3, 221, 38, 0, // Skip to: 18553
-/* 8604 */    MCD_OPC_CheckPredicate, 21, 216, 38, 0, // Skip to: 18553
-/* 8609 */    MCD_OPC_Decode, 195, 8, 127, // Opcode: VCGEzv4f32
-/* 8613 */    MCD_OPC_FilterValue, 11, 207, 38, 0, // Skip to: 18553
-/* 8618 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8621 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8635
-/* 8626 */    MCD_OPC_CheckPredicate, 21, 194, 38, 0, // Skip to: 18553
-/* 8631 */    MCD_OPC_Decode, 213, 16, 126, // Opcode: VRECPEd
-/* 8635 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8649
-/* 8640 */    MCD_OPC_CheckPredicate, 21, 180, 38, 0, // Skip to: 18553
-/* 8645 */    MCD_OPC_Decode, 218, 16, 127, // Opcode: VRECPEq
-/* 8649 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8663
-/* 8654 */    MCD_OPC_CheckPredicate, 21, 166, 38, 0, // Skip to: 18553
-/* 8659 */    MCD_OPC_Decode, 199, 17, 126, // Opcode: VRSQRTEd
-/* 8663 */    MCD_OPC_FilterValue, 3, 157, 38, 0, // Skip to: 18553
-/* 8668 */    MCD_OPC_CheckPredicate, 21, 152, 38, 0, // Skip to: 18553
-/* 8673 */    MCD_OPC_Decode, 204, 17, 127, // Opcode: VRSQRTEq
-/* 8677 */    MCD_OPC_FilterValue, 5, 67, 1, 0, // Skip to: 9005
-/* 8682 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 8685 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 8749
-/* 8690 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8693 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8707
-/* 8698 */    MCD_OPC_CheckPredicate, 21, 122, 38, 0, // Skip to: 18553
-/* 8703 */    MCD_OPC_Decode, 151, 9, 126, // Opcode: VCNTd
-/* 8707 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8721
-/* 8712 */    MCD_OPC_CheckPredicate, 21, 108, 38, 0, // Skip to: 18553
-/* 8717 */    MCD_OPC_Decode, 152, 9, 127, // Opcode: VCNTq
-/* 8721 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8735
-/* 8726 */    MCD_OPC_CheckPredicate, 21, 94, 38, 0, // Skip to: 18553
-/* 8731 */    MCD_OPC_Decode, 214, 14, 126, // Opcode: VMVNd
-/* 8735 */    MCD_OPC_FilterValue, 3, 85, 38, 0, // Skip to: 18553
-/* 8740 */    MCD_OPC_CheckPredicate, 21, 80, 38, 0, // Skip to: 18553
-/* 8745 */    MCD_OPC_Decode, 215, 14, 127, // Opcode: VMVNq
-/* 8749 */    MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 8813
-/* 8754 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8757 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8771
-/* 8762 */    MCD_OPC_CheckPredicate, 22, 58, 38, 0, // Skip to: 18553
-/* 8767 */    MCD_OPC_Decode, 168, 8, 126, // Opcode: VCEQzv4f16
-/* 8771 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8785
-/* 8776 */    MCD_OPC_CheckPredicate, 22, 44, 38, 0, // Skip to: 18553
-/* 8781 */    MCD_OPC_Decode, 172, 8, 127, // Opcode: VCEQzv8f16
-/* 8785 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8799
-/* 8790 */    MCD_OPC_CheckPredicate, 22, 30, 38, 0, // Skip to: 18553
-/* 8795 */    MCD_OPC_Decode, 230, 8, 126, // Opcode: VCLEzv4f16
-/* 8799 */    MCD_OPC_FilterValue, 3, 21, 38, 0, // Skip to: 18553
-/* 8804 */    MCD_OPC_CheckPredicate, 22, 16, 38, 0, // Skip to: 18553
-/* 8809 */    MCD_OPC_Decode, 234, 8, 127, // Opcode: VCLEzv8f16
-/* 8813 */    MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 8877
-/* 8818 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8821 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8835
-/* 8826 */    MCD_OPC_CheckPredicate, 22, 250, 37, 0, // Skip to: 18553
-/* 8831 */    MCD_OPC_Decode, 216, 16, 126, // Opcode: VRECPEhd
-/* 8835 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8849
-/* 8840 */    MCD_OPC_CheckPredicate, 22, 236, 37, 0, // Skip to: 18553
-/* 8845 */    MCD_OPC_Decode, 217, 16, 127, // Opcode: VRECPEhq
-/* 8849 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8863
-/* 8854 */    MCD_OPC_CheckPredicate, 22, 222, 37, 0, // Skip to: 18553
-/* 8859 */    MCD_OPC_Decode, 202, 17, 126, // Opcode: VRSQRTEhd
-/* 8863 */    MCD_OPC_FilterValue, 3, 213, 37, 0, // Skip to: 18553
-/* 8868 */    MCD_OPC_CheckPredicate, 22, 208, 37, 0, // Skip to: 18553
-/* 8873 */    MCD_OPC_Decode, 203, 17, 127, // Opcode: VRSQRTEhq
-/* 8877 */    MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 8941
-/* 8882 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8885 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8899
-/* 8890 */    MCD_OPC_CheckPredicate, 21, 186, 37, 0, // Skip to: 18553
-/* 8895 */    MCD_OPC_Decode, 166, 8, 126, // Opcode: VCEQzv2f32
-/* 8899 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8913
-/* 8904 */    MCD_OPC_CheckPredicate, 21, 172, 37, 0, // Skip to: 18553
-/* 8909 */    MCD_OPC_Decode, 169, 8, 127, // Opcode: VCEQzv4f32
-/* 8913 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8927
-/* 8918 */    MCD_OPC_CheckPredicate, 21, 158, 37, 0, // Skip to: 18553
-/* 8923 */    MCD_OPC_Decode, 228, 8, 126, // Opcode: VCLEzv2f32
-/* 8927 */    MCD_OPC_FilterValue, 3, 149, 37, 0, // Skip to: 18553
-/* 8932 */    MCD_OPC_CheckPredicate, 21, 144, 37, 0, // Skip to: 18553
-/* 8937 */    MCD_OPC_Decode, 231, 8, 127, // Opcode: VCLEzv4f32
-/* 8941 */    MCD_OPC_FilterValue, 11, 135, 37, 0, // Skip to: 18553
-/* 8946 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 8949 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8963
-/* 8954 */    MCD_OPC_CheckPredicate, 21, 122, 37, 0, // Skip to: 18553
-/* 8959 */    MCD_OPC_Decode, 214, 16, 126, // Opcode: VRECPEfd
-/* 8963 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 8977
-/* 8968 */    MCD_OPC_CheckPredicate, 21, 108, 37, 0, // Skip to: 18553
-/* 8973 */    MCD_OPC_Decode, 215, 16, 127, // Opcode: VRECPEfq
-/* 8977 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 8991
-/* 8982 */    MCD_OPC_CheckPredicate, 21, 94, 37, 0, // Skip to: 18553
-/* 8987 */    MCD_OPC_Decode, 200, 17, 126, // Opcode: VRSQRTEfd
-/* 8991 */    MCD_OPC_FilterValue, 3, 85, 37, 0, // Skip to: 18553
-/* 8996 */    MCD_OPC_CheckPredicate, 21, 80, 37, 0, // Skip to: 18553
-/* 9001 */    MCD_OPC_Decode, 201, 17, 127, // Opcode: VRSQRTEfq
-/* 9005 */    MCD_OPC_FilterValue, 6, 173, 1, 0, // Skip to: 9439
-/* 9010 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 9013 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9081
-/* 9018 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9021 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9036
-/* 9026 */    MCD_OPC_CheckPredicate, 21, 50, 37, 0, // Skip to: 18553
-/* 9031 */    MCD_OPC_Decode, 255, 14, 132, 1, // Opcode: VPADALsv8i8
-/* 9036 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9051
-/* 9041 */    MCD_OPC_CheckPredicate, 21, 35, 37, 0, // Skip to: 18553
-/* 9046 */    MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: VPADALsv16i8
-/* 9051 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9066
-/* 9056 */    MCD_OPC_CheckPredicate, 21, 20, 37, 0, // Skip to: 18553
-/* 9061 */    MCD_OPC_Decode, 133, 15, 132, 1, // Opcode: VPADALuv8i8
-/* 9066 */    MCD_OPC_FilterValue, 3, 10, 37, 0, // Skip to: 18553
-/* 9071 */    MCD_OPC_CheckPredicate, 21, 5, 37, 0, // Skip to: 18553
-/* 9076 */    MCD_OPC_Decode, 128, 15, 133, 1, // Opcode: VPADALuv16i8
-/* 9081 */    MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 9149
-/* 9086 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9089 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9104
-/* 9094 */    MCD_OPC_CheckPredicate, 21, 238, 36, 0, // Skip to: 18553
-/* 9099 */    MCD_OPC_Decode, 252, 14, 132, 1, // Opcode: VPADALsv4i16
-/* 9104 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9119
-/* 9109 */    MCD_OPC_CheckPredicate, 21, 223, 36, 0, // Skip to: 18553
-/* 9114 */    MCD_OPC_Decode, 254, 14, 133, 1, // Opcode: VPADALsv8i16
-/* 9119 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9134
-/* 9124 */    MCD_OPC_CheckPredicate, 21, 208, 36, 0, // Skip to: 18553
-/* 9129 */    MCD_OPC_Decode, 130, 15, 132, 1, // Opcode: VPADALuv4i16
-/* 9134 */    MCD_OPC_FilterValue, 3, 198, 36, 0, // Skip to: 18553
-/* 9139 */    MCD_OPC_CheckPredicate, 21, 193, 36, 0, // Skip to: 18553
-/* 9144 */    MCD_OPC_Decode, 132, 15, 133, 1, // Opcode: VPADALuv8i16
-/* 9149 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 9185
-/* 9154 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9157 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9171
-/* 9162 */    MCD_OPC_CheckPredicate, 22, 170, 36, 0, // Skip to: 18553
-/* 9167 */    MCD_OPC_Decode, 246, 8, 126, // Opcode: VCLTzv4f16
-/* 9171 */    MCD_OPC_FilterValue, 1, 161, 36, 0, // Skip to: 18553
-/* 9176 */    MCD_OPC_CheckPredicate, 22, 156, 36, 0, // Skip to: 18553
-/* 9181 */    MCD_OPC_Decode, 250, 8, 127, // Opcode: VCLTzv8f16
-/* 9185 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9207
-/* 9190 */    MCD_OPC_CheckPredicate, 25, 142, 36, 0, // Skip to: 18553
-/* 9195 */    MCD_OPC_CheckField, 6, 2, 0, 135, 36, 0, // Skip to: 18553
-/* 9202 */    MCD_OPC_Decode, 219, 9, 130, 1, // Opcode: VCVTf2h
-/* 9207 */    MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9271
-/* 9212 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9215 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9229
-/* 9220 */    MCD_OPC_CheckPredicate, 22, 112, 36, 0, // Skip to: 18553
-/* 9225 */    MCD_OPC_Decode, 239, 9, 126, // Opcode: VCVTs2hd
-/* 9229 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9243
-/* 9234 */    MCD_OPC_CheckPredicate, 22, 98, 36, 0, // Skip to: 18553
-/* 9239 */    MCD_OPC_Decode, 240, 9, 127, // Opcode: VCVTs2hq
-/* 9243 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9257
-/* 9248 */    MCD_OPC_CheckPredicate, 22, 84, 36, 0, // Skip to: 18553
-/* 9253 */    MCD_OPC_Decode, 243, 9, 126, // Opcode: VCVTu2hd
-/* 9257 */    MCD_OPC_FilterValue, 3, 75, 36, 0, // Skip to: 18553
-/* 9262 */    MCD_OPC_CheckPredicate, 22, 70, 36, 0, // Skip to: 18553
-/* 9267 */    MCD_OPC_Decode, 244, 9, 127, // Opcode: VCVTu2hq
-/* 9271 */    MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 9339
-/* 9276 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9279 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9294
-/* 9284 */    MCD_OPC_CheckPredicate, 21, 48, 36, 0, // Skip to: 18553
-/* 9289 */    MCD_OPC_Decode, 251, 14, 132, 1, // Opcode: VPADALsv2i32
-/* 9294 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9309
-/* 9299 */    MCD_OPC_CheckPredicate, 21, 33, 36, 0, // Skip to: 18553
-/* 9304 */    MCD_OPC_Decode, 253, 14, 133, 1, // Opcode: VPADALsv4i32
-/* 9309 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9324
-/* 9314 */    MCD_OPC_CheckPredicate, 21, 18, 36, 0, // Skip to: 18553
-/* 9319 */    MCD_OPC_Decode, 129, 15, 132, 1, // Opcode: VPADALuv2i32
-/* 9324 */    MCD_OPC_FilterValue, 3, 8, 36, 0, // Skip to: 18553
-/* 9329 */    MCD_OPC_CheckPredicate, 21, 3, 36, 0, // Skip to: 18553
-/* 9334 */    MCD_OPC_Decode, 131, 15, 133, 1, // Opcode: VPADALuv4i32
-/* 9339 */    MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 9375
-/* 9344 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9347 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9361
-/* 9352 */    MCD_OPC_CheckPredicate, 21, 236, 35, 0, // Skip to: 18553
-/* 9357 */    MCD_OPC_Decode, 244, 8, 126, // Opcode: VCLTzv2f32
-/* 9361 */    MCD_OPC_FilterValue, 1, 227, 35, 0, // Skip to: 18553
-/* 9366 */    MCD_OPC_CheckPredicate, 21, 222, 35, 0, // Skip to: 18553
-/* 9371 */    MCD_OPC_Decode, 247, 8, 127, // Opcode: VCLTzv4f32
-/* 9375 */    MCD_OPC_FilterValue, 11, 213, 35, 0, // Skip to: 18553
-/* 9380 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9383 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9397
-/* 9388 */    MCD_OPC_CheckPredicate, 21, 200, 35, 0, // Skip to: 18553
-/* 9393 */    MCD_OPC_Decode, 237, 9, 126, // Opcode: VCVTs2fd
-/* 9397 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9411
-/* 9402 */    MCD_OPC_CheckPredicate, 21, 186, 35, 0, // Skip to: 18553
-/* 9407 */    MCD_OPC_Decode, 238, 9, 127, // Opcode: VCVTs2fq
-/* 9411 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9425
-/* 9416 */    MCD_OPC_CheckPredicate, 21, 172, 35, 0, // Skip to: 18553
-/* 9421 */    MCD_OPC_Decode, 241, 9, 126, // Opcode: VCVTu2fd
-/* 9425 */    MCD_OPC_FilterValue, 3, 163, 35, 0, // Skip to: 18553
-/* 9430 */    MCD_OPC_CheckPredicate, 21, 158, 35, 0, // Skip to: 18553
-/* 9435 */    MCD_OPC_Decode, 242, 9, 127, // Opcode: VCVTu2fq
-/* 9439 */    MCD_OPC_FilterValue, 7, 217, 1, 0, // Skip to: 9917
-/* 9444 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 9447 */    MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 9511
-/* 9452 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9455 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9469
-/* 9460 */    MCD_OPC_CheckPredicate, 21, 128, 35, 0, // Skip to: 18553
-/* 9465 */    MCD_OPC_Decode, 172, 15, 126, // Opcode: VQABSv8i8
-/* 9469 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9483
-/* 9474 */    MCD_OPC_CheckPredicate, 21, 114, 35, 0, // Skip to: 18553
-/* 9479 */    MCD_OPC_Decode, 167, 15, 127, // Opcode: VQABSv16i8
-/* 9483 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9497
-/* 9488 */    MCD_OPC_CheckPredicate, 21, 100, 35, 0, // Skip to: 18553
-/* 9493 */    MCD_OPC_Decode, 223, 15, 126, // Opcode: VQNEGv8i8
-/* 9497 */    MCD_OPC_FilterValue, 3, 91, 35, 0, // Skip to: 18553
-/* 9502 */    MCD_OPC_CheckPredicate, 21, 86, 35, 0, // Skip to: 18553
-/* 9507 */    MCD_OPC_Decode, 218, 15, 127, // Opcode: VQNEGv16i8
-/* 9511 */    MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 9575
-/* 9516 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9519 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9533
-/* 9524 */    MCD_OPC_CheckPredicate, 21, 64, 35, 0, // Skip to: 18553
-/* 9529 */    MCD_OPC_Decode, 169, 15, 126, // Opcode: VQABSv4i16
-/* 9533 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9547
-/* 9538 */    MCD_OPC_CheckPredicate, 21, 50, 35, 0, // Skip to: 18553
-/* 9543 */    MCD_OPC_Decode, 171, 15, 127, // Opcode: VQABSv8i16
-/* 9547 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9561
-/* 9552 */    MCD_OPC_CheckPredicate, 21, 36, 35, 0, // Skip to: 18553
-/* 9557 */    MCD_OPC_Decode, 220, 15, 126, // Opcode: VQNEGv4i16
-/* 9561 */    MCD_OPC_FilterValue, 3, 27, 35, 0, // Skip to: 18553
-/* 9566 */    MCD_OPC_CheckPredicate, 21, 22, 35, 0, // Skip to: 18553
-/* 9571 */    MCD_OPC_Decode, 222, 15, 127, // Opcode: VQNEGv8i16
-/* 9575 */    MCD_OPC_FilterValue, 5, 59, 0, 0, // Skip to: 9639
-/* 9580 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9583 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9597
-/* 9588 */    MCD_OPC_CheckPredicate, 22, 0, 35, 0, // Skip to: 18553
-/* 9593 */    MCD_OPC_Decode, 219, 7, 126, // Opcode: VABShd
-/* 9597 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9611
-/* 9602 */    MCD_OPC_CheckPredicate, 22, 242, 34, 0, // Skip to: 18553
-/* 9607 */    MCD_OPC_Decode, 220, 7, 127, // Opcode: VABShq
-/* 9611 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9625
-/* 9616 */    MCD_OPC_CheckPredicate, 22, 228, 34, 0, // Skip to: 18553
-/* 9621 */    MCD_OPC_Decode, 225, 14, 126, // Opcode: VNEGhd
-/* 9625 */    MCD_OPC_FilterValue, 3, 219, 34, 0, // Skip to: 18553
-/* 9630 */    MCD_OPC_CheckPredicate, 22, 214, 34, 0, // Skip to: 18553
-/* 9635 */    MCD_OPC_Decode, 226, 14, 127, // Opcode: VNEGhq
-/* 9639 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 9661
-/* 9644 */    MCD_OPC_CheckPredicate, 25, 200, 34, 0, // Skip to: 18553
-/* 9649 */    MCD_OPC_CheckField, 6, 2, 0, 193, 34, 0, // Skip to: 18553
-/* 9656 */    MCD_OPC_Decode, 228, 9, 134, 1, // Opcode: VCVTh2f
-/* 9661 */    MCD_OPC_FilterValue, 7, 59, 0, 0, // Skip to: 9725
-/* 9666 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9669 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9683
-/* 9674 */    MCD_OPC_CheckPredicate, 22, 170, 34, 0, // Skip to: 18553
-/* 9679 */    MCD_OPC_Decode, 229, 9, 126, // Opcode: VCVTh2sd
-/* 9683 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9697
-/* 9688 */    MCD_OPC_CheckPredicate, 22, 156, 34, 0, // Skip to: 18553
-/* 9693 */    MCD_OPC_Decode, 230, 9, 127, // Opcode: VCVTh2sq
-/* 9697 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9711
-/* 9702 */    MCD_OPC_CheckPredicate, 22, 142, 34, 0, // Skip to: 18553
-/* 9707 */    MCD_OPC_Decode, 231, 9, 126, // Opcode: VCVTh2ud
-/* 9711 */    MCD_OPC_FilterValue, 3, 133, 34, 0, // Skip to: 18553
-/* 9716 */    MCD_OPC_CheckPredicate, 22, 128, 34, 0, // Skip to: 18553
-/* 9721 */    MCD_OPC_Decode, 232, 9, 127, // Opcode: VCVTh2uq
-/* 9725 */    MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 9789
-/* 9730 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9733 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9747
-/* 9738 */    MCD_OPC_CheckPredicate, 21, 106, 34, 0, // Skip to: 18553
-/* 9743 */    MCD_OPC_Decode, 168, 15, 126, // Opcode: VQABSv2i32
-/* 9747 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9761
-/* 9752 */    MCD_OPC_CheckPredicate, 21, 92, 34, 0, // Skip to: 18553
-/* 9757 */    MCD_OPC_Decode, 170, 15, 127, // Opcode: VQABSv4i32
-/* 9761 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9775
-/* 9766 */    MCD_OPC_CheckPredicate, 21, 78, 34, 0, // Skip to: 18553
-/* 9771 */    MCD_OPC_Decode, 219, 15, 126, // Opcode: VQNEGv2i32
-/* 9775 */    MCD_OPC_FilterValue, 3, 69, 34, 0, // Skip to: 18553
-/* 9780 */    MCD_OPC_CheckPredicate, 21, 64, 34, 0, // Skip to: 18553
-/* 9785 */    MCD_OPC_Decode, 221, 15, 127, // Opcode: VQNEGv4i32
-/* 9789 */    MCD_OPC_FilterValue, 9, 59, 0, 0, // Skip to: 9853
-/* 9794 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9797 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9811
-/* 9802 */    MCD_OPC_CheckPredicate, 21, 42, 34, 0, // Skip to: 18553
-/* 9807 */    MCD_OPC_Decode, 217, 7, 126, // Opcode: VABSfd
-/* 9811 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9825
-/* 9816 */    MCD_OPC_CheckPredicate, 21, 28, 34, 0, // Skip to: 18553
-/* 9821 */    MCD_OPC_Decode, 218, 7, 127, // Opcode: VABSfq
-/* 9825 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9839
-/* 9830 */    MCD_OPC_CheckPredicate, 21, 14, 34, 0, // Skip to: 18553
-/* 9835 */    MCD_OPC_Decode, 224, 14, 126, // Opcode: VNEGfd
-/* 9839 */    MCD_OPC_FilterValue, 3, 5, 34, 0, // Skip to: 18553
-/* 9844 */    MCD_OPC_CheckPredicate, 21, 0, 34, 0, // Skip to: 18553
-/* 9849 */    MCD_OPC_Decode, 223, 14, 127, // Opcode: VNEGf32q
-/* 9853 */    MCD_OPC_FilterValue, 11, 247, 33, 0, // Skip to: 18553
-/* 9858 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 9861 */    MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9875
-/* 9866 */    MCD_OPC_CheckPredicate, 21, 234, 33, 0, // Skip to: 18553
-/* 9871 */    MCD_OPC_Decode, 220, 9, 126, // Opcode: VCVTf2sd
-/* 9875 */    MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 9889
-/* 9880 */    MCD_OPC_CheckPredicate, 21, 220, 33, 0, // Skip to: 18553
-/* 9885 */    MCD_OPC_Decode, 221, 9, 127, // Opcode: VCVTf2sq
-/* 9889 */    MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 9903
-/* 9894 */    MCD_OPC_CheckPredicate, 21, 206, 33, 0, // Skip to: 18553
-/* 9899 */    MCD_OPC_Decode, 222, 9, 126, // Opcode: VCVTf2ud
-/* 9903 */    MCD_OPC_FilterValue, 3, 197, 33, 0, // Skip to: 18553
-/* 9908 */    MCD_OPC_CheckPredicate, 21, 192, 33, 0, // Skip to: 18553
-/* 9913 */    MCD_OPC_Decode, 223, 9, 127, // Opcode: VCVTf2uq
-/* 9917 */    MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 9955
-/* 9922 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 9925 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9940
-/* 9930 */    MCD_OPC_CheckPredicate, 21, 170, 33, 0, // Skip to: 18553
-/* 9935 */    MCD_OPC_Decode, 239, 20, 135, 1, // Opcode: VTBL1
-/* 9940 */    MCD_OPC_FilterValue, 1, 160, 33, 0, // Skip to: 18553
-/* 9945 */    MCD_OPC_CheckPredicate, 21, 155, 33, 0, // Skip to: 18553
-/* 9950 */    MCD_OPC_Decode, 245, 20, 135, 1, // Opcode: VTBX1
-/* 9955 */    MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 9993
-/* 9960 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 9963 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9978
-/* 9968 */    MCD_OPC_CheckPredicate, 21, 132, 33, 0, // Skip to: 18553
-/* 9973 */    MCD_OPC_Decode, 240, 20, 135, 1, // Opcode: VTBL2
-/* 9978 */    MCD_OPC_FilterValue, 1, 122, 33, 0, // Skip to: 18553
-/* 9983 */    MCD_OPC_CheckPredicate, 21, 117, 33, 0, // Skip to: 18553
-/* 9988 */    MCD_OPC_Decode, 246, 20, 135, 1, // Opcode: VTBX2
-/* 9993 */    MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 10031
-/* 9998 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 10001 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10016
-/* 10006 */   MCD_OPC_CheckPredicate, 21, 94, 33, 0, // Skip to: 18553
-/* 10011 */   MCD_OPC_Decode, 241, 20, 135, 1, // Opcode: VTBL3
-/* 10016 */   MCD_OPC_FilterValue, 1, 84, 33, 0, // Skip to: 18553
-/* 10021 */   MCD_OPC_CheckPredicate, 21, 79, 33, 0, // Skip to: 18553
-/* 10026 */   MCD_OPC_Decode, 247, 20, 135, 1, // Opcode: VTBX3
-/* 10031 */   MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 10069
-/* 10036 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 10039 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10054
-/* 10044 */   MCD_OPC_CheckPredicate, 21, 56, 33, 0, // Skip to: 18553
-/* 10049 */   MCD_OPC_Decode, 243, 20, 135, 1, // Opcode: VTBL4
-/* 10054 */   MCD_OPC_FilterValue, 1, 46, 33, 0, // Skip to: 18553
-/* 10059 */   MCD_OPC_CheckPredicate, 21, 41, 33, 0, // Skip to: 18553
-/* 10064 */   MCD_OPC_Decode, 249, 20, 135, 1, // Opcode: VTBX4
-/* 10069 */   MCD_OPC_FilterValue, 12, 31, 33, 0, // Skip to: 18553
-/* 10074 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 10077 */   MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 10145
-/* 10082 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
-/* 10085 */   MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10130
-/* 10090 */   MCD_OPC_ExtractField, 17, 1,  // Inst{17} ...
-/* 10093 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10115
-/* 10098 */   MCD_OPC_CheckPredicate, 21, 2, 33, 0, // Skip to: 18553
-/* 10103 */   MCD_OPC_CheckField, 18, 1, 1, 251, 32, 0, // Skip to: 18553
-/* 10110 */   MCD_OPC_Decode, 136, 10, 136, 1, // Opcode: VDUPLN32d
-/* 10115 */   MCD_OPC_FilterValue, 1, 241, 32, 0, // Skip to: 18553
-/* 10120 */   MCD_OPC_CheckPredicate, 21, 236, 32, 0, // Skip to: 18553
-/* 10125 */   MCD_OPC_Decode, 134, 10, 137, 1, // Opcode: VDUPLN16d
-/* 10130 */   MCD_OPC_FilterValue, 1, 226, 32, 0, // Skip to: 18553
-/* 10135 */   MCD_OPC_CheckPredicate, 21, 221, 32, 0, // Skip to: 18553
-/* 10140 */   MCD_OPC_Decode, 138, 10, 138, 1, // Opcode: VDUPLN8d
-/* 10145 */   MCD_OPC_FilterValue, 1, 211, 32, 0, // Skip to: 18553
-/* 10150 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
-/* 10153 */   MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10198
-/* 10158 */   MCD_OPC_ExtractField, 17, 1,  // Inst{17} ...
-/* 10161 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10183
-/* 10166 */   MCD_OPC_CheckPredicate, 21, 190, 32, 0, // Skip to: 18553
-/* 10171 */   MCD_OPC_CheckField, 18, 1, 1, 183, 32, 0, // Skip to: 18553
-/* 10178 */   MCD_OPC_Decode, 137, 10, 139, 1, // Opcode: VDUPLN32q
-/* 10183 */   MCD_OPC_FilterValue, 1, 173, 32, 0, // Skip to: 18553
-/* 10188 */   MCD_OPC_CheckPredicate, 21, 168, 32, 0, // Skip to: 18553
-/* 10193 */   MCD_OPC_Decode, 135, 10, 140, 1, // Opcode: VDUPLN16q
-/* 10198 */   MCD_OPC_FilterValue, 1, 158, 32, 0, // Skip to: 18553
-/* 10203 */   MCD_OPC_CheckPredicate, 21, 153, 32, 0, // Skip to: 18553
-/* 10208 */   MCD_OPC_Decode, 139, 10, 141, 1, // Opcode: VDUPLN8q
-/* 10213 */   MCD_OPC_FilterValue, 1, 143, 32, 0, // Skip to: 18553
-/* 10218 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 10221 */   MCD_OPC_FilterValue, 0, 21, 17, 0, // Skip to: 14599
-/* 10226 */   MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 10229 */   MCD_OPC_FilterValue, 0, 9, 8, 0, // Skip to: 12291
-/* 10234 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 10237 */   MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 10397
-/* 10242 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 10245 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10283
-/* 10250 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10253 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10268
-/* 10259 */   MCD_OPC_CheckPredicate, 21, 97, 32, 0, // Skip to: 18553
-/* 10264 */   MCD_OPC_Decode, 180, 15, 97, // Opcode: VQADDsv8i8
-/* 10268 */   MCD_OPC_FilterValue, 243, 1, 87, 32, 0, // Skip to: 18553
-/* 10274 */   MCD_OPC_CheckPredicate, 21, 82, 32, 0, // Skip to: 18553
-/* 10279 */   MCD_OPC_Decode, 188, 15, 97, // Opcode: VQADDuv8i8
-/* 10283 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10321
-/* 10288 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10291 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10306
-/* 10297 */   MCD_OPC_CheckPredicate, 21, 59, 32, 0, // Skip to: 18553
-/* 10302 */   MCD_OPC_Decode, 177, 15, 97, // Opcode: VQADDsv4i16
-/* 10306 */   MCD_OPC_FilterValue, 243, 1, 49, 32, 0, // Skip to: 18553
-/* 10312 */   MCD_OPC_CheckPredicate, 21, 44, 32, 0, // Skip to: 18553
-/* 10317 */   MCD_OPC_Decode, 185, 15, 97, // Opcode: VQADDuv4i16
-/* 10321 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10359
-/* 10326 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10329 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10344
-/* 10335 */   MCD_OPC_CheckPredicate, 21, 21, 32, 0, // Skip to: 18553
-/* 10340 */   MCD_OPC_Decode, 175, 15, 97, // Opcode: VQADDsv2i32
-/* 10344 */   MCD_OPC_FilterValue, 243, 1, 11, 32, 0, // Skip to: 18553
-/* 10350 */   MCD_OPC_CheckPredicate, 21, 6, 32, 0, // Skip to: 18553
-/* 10355 */   MCD_OPC_Decode, 183, 15, 97, // Opcode: VQADDuv2i32
-/* 10359 */   MCD_OPC_FilterValue, 3, 253, 31, 0, // Skip to: 18553
-/* 10364 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10367 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10382
-/* 10373 */   MCD_OPC_CheckPredicate, 21, 239, 31, 0, // Skip to: 18553
-/* 10378 */   MCD_OPC_Decode, 174, 15, 97, // Opcode: VQADDsv1i64
-/* 10382 */   MCD_OPC_FilterValue, 243, 1, 229, 31, 0, // Skip to: 18553
-/* 10388 */   MCD_OPC_CheckPredicate, 21, 224, 31, 0, // Skip to: 18553
-/* 10393 */   MCD_OPC_Decode, 182, 15, 97, // Opcode: VQADDuv1i64
-/* 10397 */   MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 10557
-/* 10402 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 10405 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10443
-/* 10410 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10413 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10428
-/* 10419 */   MCD_OPC_CheckPredicate, 21, 193, 31, 0, // Skip to: 18553
-/* 10424 */   MCD_OPC_Decode, 137, 8, 97, // Opcode: VANDd
-/* 10428 */   MCD_OPC_FilterValue, 243, 1, 183, 31, 0, // Skip to: 18553
-/* 10434 */   MCD_OPC_CheckPredicate, 21, 178, 31, 0, // Skip to: 18553
-/* 10439 */   MCD_OPC_Decode, 140, 10, 97, // Opcode: VEORd
-/* 10443 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10481
-/* 10448 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10451 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10466
-/* 10457 */   MCD_OPC_CheckPredicate, 21, 155, 31, 0, // Skip to: 18553
-/* 10462 */   MCD_OPC_Decode, 139, 8, 97, // Opcode: VBICd
-/* 10466 */   MCD_OPC_FilterValue, 243, 1, 145, 31, 0, // Skip to: 18553
-/* 10472 */   MCD_OPC_CheckPredicate, 21, 140, 31, 0, // Skip to: 18553
-/* 10477 */   MCD_OPC_Decode, 149, 8, 105, // Opcode: VBSLd
-/* 10481 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10519
-/* 10486 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10489 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10504
-/* 10495 */   MCD_OPC_CheckPredicate, 21, 117, 31, 0, // Skip to: 18553
-/* 10500 */   MCD_OPC_Decode, 244, 14, 97, // Opcode: VORRd
-/* 10504 */   MCD_OPC_FilterValue, 243, 1, 107, 31, 0, // Skip to: 18553
-/* 10510 */   MCD_OPC_CheckPredicate, 21, 102, 31, 0, // Skip to: 18553
-/* 10515 */   MCD_OPC_Decode, 147, 8, 105, // Opcode: VBITd
-/* 10519 */   MCD_OPC_FilterValue, 3, 93, 31, 0, // Skip to: 18553
-/* 10524 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10527 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10542
-/* 10533 */   MCD_OPC_CheckPredicate, 21, 79, 31, 0, // Skip to: 18553
-/* 10538 */   MCD_OPC_Decode, 242, 14, 97, // Opcode: VORNd
-/* 10542 */   MCD_OPC_FilterValue, 243, 1, 69, 31, 0, // Skip to: 18553
-/* 10548 */   MCD_OPC_CheckPredicate, 21, 64, 31, 0, // Skip to: 18553
-/* 10553 */   MCD_OPC_Decode, 145, 8, 105, // Opcode: VBIFd
-/* 10557 */   MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 10717
-/* 10562 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 10565 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10603
-/* 10570 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10573 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10588
-/* 10579 */   MCD_OPC_CheckPredicate, 21, 33, 31, 0, // Skip to: 18553
-/* 10584 */   MCD_OPC_Decode, 201, 16, 97, // Opcode: VQSUBsv8i8
-/* 10588 */   MCD_OPC_FilterValue, 243, 1, 23, 31, 0, // Skip to: 18553
-/* 10594 */   MCD_OPC_CheckPredicate, 21, 18, 31, 0, // Skip to: 18553
-/* 10599 */   MCD_OPC_Decode, 209, 16, 97, // Opcode: VQSUBuv8i8
-/* 10603 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10641
-/* 10608 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10611 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10626
-/* 10617 */   MCD_OPC_CheckPredicate, 21, 251, 30, 0, // Skip to: 18553
-/* 10622 */   MCD_OPC_Decode, 198, 16, 97, // Opcode: VQSUBsv4i16
-/* 10626 */   MCD_OPC_FilterValue, 243, 1, 241, 30, 0, // Skip to: 18553
-/* 10632 */   MCD_OPC_CheckPredicate, 21, 236, 30, 0, // Skip to: 18553
-/* 10637 */   MCD_OPC_Decode, 206, 16, 97, // Opcode: VQSUBuv4i16
-/* 10641 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10679
-/* 10646 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10649 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10664
-/* 10655 */   MCD_OPC_CheckPredicate, 21, 213, 30, 0, // Skip to: 18553
-/* 10660 */   MCD_OPC_Decode, 196, 16, 97, // Opcode: VQSUBsv2i32
-/* 10664 */   MCD_OPC_FilterValue, 243, 1, 203, 30, 0, // Skip to: 18553
-/* 10670 */   MCD_OPC_CheckPredicate, 21, 198, 30, 0, // Skip to: 18553
-/* 10675 */   MCD_OPC_Decode, 204, 16, 97, // Opcode: VQSUBuv2i32
-/* 10679 */   MCD_OPC_FilterValue, 3, 189, 30, 0, // Skip to: 18553
-/* 10684 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10687 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10702
-/* 10693 */   MCD_OPC_CheckPredicate, 21, 175, 30, 0, // Skip to: 18553
-/* 10698 */   MCD_OPC_Decode, 195, 16, 97, // Opcode: VQSUBsv1i64
-/* 10702 */   MCD_OPC_FilterValue, 243, 1, 165, 30, 0, // Skip to: 18553
-/* 10708 */   MCD_OPC_CheckPredicate, 21, 160, 30, 0, // Skip to: 18553
-/* 10713 */   MCD_OPC_Decode, 203, 16, 97, // Opcode: VQSUBuv1i64
-/* 10717 */   MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 10839
-/* 10722 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 10725 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10763
-/* 10730 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10733 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10748
-/* 10739 */   MCD_OPC_CheckPredicate, 21, 129, 30, 0, // Skip to: 18553
-/* 10744 */   MCD_OPC_Decode, 184, 8, 97, // Opcode: VCGEsv8i8
-/* 10748 */   MCD_OPC_FilterValue, 243, 1, 119, 30, 0, // Skip to: 18553
-/* 10754 */   MCD_OPC_CheckPredicate, 21, 114, 30, 0, // Skip to: 18553
-/* 10759 */   MCD_OPC_Decode, 190, 8, 97, // Opcode: VCGEuv8i8
-/* 10763 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10801
-/* 10768 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10771 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10786
-/* 10777 */   MCD_OPC_CheckPredicate, 21, 91, 30, 0, // Skip to: 18553
-/* 10782 */   MCD_OPC_Decode, 181, 8, 97, // Opcode: VCGEsv4i16
-/* 10786 */   MCD_OPC_FilterValue, 243, 1, 81, 30, 0, // Skip to: 18553
-/* 10792 */   MCD_OPC_CheckPredicate, 21, 76, 30, 0, // Skip to: 18553
-/* 10797 */   MCD_OPC_Decode, 187, 8, 97, // Opcode: VCGEuv4i16
-/* 10801 */   MCD_OPC_FilterValue, 2, 67, 30, 0, // Skip to: 18553
-/* 10806 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10809 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10824
-/* 10815 */   MCD_OPC_CheckPredicate, 21, 53, 30, 0, // Skip to: 18553
-/* 10820 */   MCD_OPC_Decode, 180, 8, 97, // Opcode: VCGEsv2i32
-/* 10824 */   MCD_OPC_FilterValue, 243, 1, 43, 30, 0, // Skip to: 18553
-/* 10830 */   MCD_OPC_CheckPredicate, 21, 38, 30, 0, // Skip to: 18553
-/* 10835 */   MCD_OPC_Decode, 186, 8, 97, // Opcode: VCGEuv2i32
-/* 10839 */   MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 10999
-/* 10844 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 10847 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 10885
-/* 10852 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10855 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10870
-/* 10861 */   MCD_OPC_CheckPredicate, 21, 7, 30, 0, // Skip to: 18553
-/* 10866 */   MCD_OPC_Decode, 168, 16, 101, // Opcode: VQSHLsv8i8
-/* 10870 */   MCD_OPC_FilterValue, 243, 1, 253, 29, 0, // Skip to: 18553
-/* 10876 */   MCD_OPC_CheckPredicate, 21, 248, 29, 0, // Skip to: 18553
-/* 10881 */   MCD_OPC_Decode, 184, 16, 101, // Opcode: VQSHLuv8i8
-/* 10885 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 10923
-/* 10890 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10893 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10908
-/* 10899 */   MCD_OPC_CheckPredicate, 21, 225, 29, 0, // Skip to: 18553
-/* 10904 */   MCD_OPC_Decode, 165, 16, 101, // Opcode: VQSHLsv4i16
-/* 10908 */   MCD_OPC_FilterValue, 243, 1, 215, 29, 0, // Skip to: 18553
-/* 10914 */   MCD_OPC_CheckPredicate, 21, 210, 29, 0, // Skip to: 18553
-/* 10919 */   MCD_OPC_Decode, 181, 16, 101, // Opcode: VQSHLuv4i16
-/* 10923 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 10961
-/* 10928 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10931 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10946
-/* 10937 */   MCD_OPC_CheckPredicate, 21, 187, 29, 0, // Skip to: 18553
-/* 10942 */   MCD_OPC_Decode, 163, 16, 101, // Opcode: VQSHLsv2i32
-/* 10946 */   MCD_OPC_FilterValue, 243, 1, 177, 29, 0, // Skip to: 18553
-/* 10952 */   MCD_OPC_CheckPredicate, 21, 172, 29, 0, // Skip to: 18553
-/* 10957 */   MCD_OPC_Decode, 179, 16, 101, // Opcode: VQSHLuv2i32
-/* 10961 */   MCD_OPC_FilterValue, 3, 163, 29, 0, // Skip to: 18553
-/* 10966 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 10969 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 10984
-/* 10975 */   MCD_OPC_CheckPredicate, 21, 149, 29, 0, // Skip to: 18553
-/* 10980 */   MCD_OPC_Decode, 162, 16, 101, // Opcode: VQSHLsv1i64
-/* 10984 */   MCD_OPC_FilterValue, 243, 1, 139, 29, 0, // Skip to: 18553
-/* 10990 */   MCD_OPC_CheckPredicate, 21, 134, 29, 0, // Skip to: 18553
-/* 10995 */   MCD_OPC_Decode, 178, 16, 101, // Opcode: VQSHLuv1i64
-/* 10999 */   MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 11159
-/* 11004 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11007 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11045
-/* 11012 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11015 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11030
-/* 11021 */   MCD_OPC_CheckPredicate, 21, 103, 29, 0, // Skip to: 18553
-/* 11026 */   MCD_OPC_Decode, 255, 15, 101, // Opcode: VQRSHLsv8i8
-/* 11030 */   MCD_OPC_FilterValue, 243, 1, 93, 29, 0, // Skip to: 18553
-/* 11036 */   MCD_OPC_CheckPredicate, 21, 88, 29, 0, // Skip to: 18553
-/* 11041 */   MCD_OPC_Decode, 135, 16, 101, // Opcode: VQRSHLuv8i8
-/* 11045 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11083
-/* 11050 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11053 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11068
-/* 11059 */   MCD_OPC_CheckPredicate, 21, 65, 29, 0, // Skip to: 18553
-/* 11064 */   MCD_OPC_Decode, 252, 15, 101, // Opcode: VQRSHLsv4i16
-/* 11068 */   MCD_OPC_FilterValue, 243, 1, 55, 29, 0, // Skip to: 18553
-/* 11074 */   MCD_OPC_CheckPredicate, 21, 50, 29, 0, // Skip to: 18553
-/* 11079 */   MCD_OPC_Decode, 132, 16, 101, // Opcode: VQRSHLuv4i16
-/* 11083 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11121
-/* 11088 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11091 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11106
-/* 11097 */   MCD_OPC_CheckPredicate, 21, 27, 29, 0, // Skip to: 18553
-/* 11102 */   MCD_OPC_Decode, 250, 15, 101, // Opcode: VQRSHLsv2i32
-/* 11106 */   MCD_OPC_FilterValue, 243, 1, 17, 29, 0, // Skip to: 18553
-/* 11112 */   MCD_OPC_CheckPredicate, 21, 12, 29, 0, // Skip to: 18553
-/* 11117 */   MCD_OPC_Decode, 130, 16, 101, // Opcode: VQRSHLuv2i32
-/* 11121 */   MCD_OPC_FilterValue, 3, 3, 29, 0, // Skip to: 18553
-/* 11126 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11129 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11144
-/* 11135 */   MCD_OPC_CheckPredicate, 21, 245, 28, 0, // Skip to: 18553
-/* 11140 */   MCD_OPC_Decode, 249, 15, 101, // Opcode: VQRSHLsv1i64
-/* 11144 */   MCD_OPC_FilterValue, 243, 1, 235, 28, 0, // Skip to: 18553
-/* 11150 */   MCD_OPC_CheckPredicate, 21, 230, 28, 0, // Skip to: 18553
-/* 11155 */   MCD_OPC_Decode, 129, 16, 101, // Opcode: VQRSHLuv1i64
-/* 11159 */   MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 11281
-/* 11164 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11167 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11205
-/* 11172 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11175 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11190
-/* 11181 */   MCD_OPC_CheckPredicate, 21, 199, 28, 0, // Skip to: 18553
-/* 11186 */   MCD_OPC_Decode, 195, 13, 97, // Opcode: VMINsv8i8
-/* 11190 */   MCD_OPC_FilterValue, 243, 1, 189, 28, 0, // Skip to: 18553
-/* 11196 */   MCD_OPC_CheckPredicate, 21, 184, 28, 0, // Skip to: 18553
-/* 11201 */   MCD_OPC_Decode, 201, 13, 97, // Opcode: VMINuv8i8
-/* 11205 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11243
-/* 11210 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11213 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11228
-/* 11219 */   MCD_OPC_CheckPredicate, 21, 161, 28, 0, // Skip to: 18553
-/* 11224 */   MCD_OPC_Decode, 192, 13, 97, // Opcode: VMINsv4i16
-/* 11228 */   MCD_OPC_FilterValue, 243, 1, 151, 28, 0, // Skip to: 18553
-/* 11234 */   MCD_OPC_CheckPredicate, 21, 146, 28, 0, // Skip to: 18553
-/* 11239 */   MCD_OPC_Decode, 198, 13, 97, // Opcode: VMINuv4i16
-/* 11243 */   MCD_OPC_FilterValue, 2, 137, 28, 0, // Skip to: 18553
-/* 11248 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11251 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11266
-/* 11257 */   MCD_OPC_CheckPredicate, 21, 123, 28, 0, // Skip to: 18553
-/* 11262 */   MCD_OPC_Decode, 191, 13, 97, // Opcode: VMINsv2i32
-/* 11266 */   MCD_OPC_FilterValue, 243, 1, 113, 28, 0, // Skip to: 18553
-/* 11272 */   MCD_OPC_CheckPredicate, 21, 108, 28, 0, // Skip to: 18553
-/* 11277 */   MCD_OPC_Decode, 197, 13, 97, // Opcode: VMINuv2i32
-/* 11281 */   MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 11403
-/* 11286 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11289 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11327
-/* 11294 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11297 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11312
-/* 11303 */   MCD_OPC_CheckPredicate, 21, 77, 28, 0, // Skip to: 18553
-/* 11308 */   MCD_OPC_Decode, 185, 7, 105, // Opcode: VABAsv8i8
-/* 11312 */   MCD_OPC_FilterValue, 243, 1, 67, 28, 0, // Skip to: 18553
-/* 11318 */   MCD_OPC_CheckPredicate, 21, 62, 28, 0, // Skip to: 18553
-/* 11323 */   MCD_OPC_Decode, 191, 7, 105, // Opcode: VABAuv8i8
-/* 11327 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11365
-/* 11332 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11335 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11350
-/* 11341 */   MCD_OPC_CheckPredicate, 21, 39, 28, 0, // Skip to: 18553
-/* 11346 */   MCD_OPC_Decode, 182, 7, 105, // Opcode: VABAsv4i16
-/* 11350 */   MCD_OPC_FilterValue, 243, 1, 29, 28, 0, // Skip to: 18553
-/* 11356 */   MCD_OPC_CheckPredicate, 21, 24, 28, 0, // Skip to: 18553
-/* 11361 */   MCD_OPC_Decode, 188, 7, 105, // Opcode: VABAuv4i16
-/* 11365 */   MCD_OPC_FilterValue, 2, 15, 28, 0, // Skip to: 18553
-/* 11370 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11373 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11388
-/* 11379 */   MCD_OPC_CheckPredicate, 21, 1, 28, 0, // Skip to: 18553
-/* 11384 */   MCD_OPC_Decode, 181, 7, 105, // Opcode: VABAsv2i32
-/* 11388 */   MCD_OPC_FilterValue, 243, 1, 247, 27, 0, // Skip to: 18553
-/* 11394 */   MCD_OPC_CheckPredicate, 21, 242, 27, 0, // Skip to: 18553
-/* 11399 */   MCD_OPC_Decode, 187, 7, 105, // Opcode: VABAuv2i32
-/* 11403 */   MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 11525
-/* 11408 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11411 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11449
-/* 11416 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11419 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11434
-/* 11425 */   MCD_OPC_CheckPredicate, 21, 211, 27, 0, // Skip to: 18553
-/* 11430 */   MCD_OPC_Decode, 158, 21, 97, // Opcode: VTSTv8i8
-/* 11434 */   MCD_OPC_FilterValue, 243, 1, 201, 27, 0, // Skip to: 18553
-/* 11440 */   MCD_OPC_CheckPredicate, 21, 196, 27, 0, // Skip to: 18553
-/* 11445 */   MCD_OPC_Decode, 164, 8, 97, // Opcode: VCEQv8i8
-/* 11449 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11487
-/* 11454 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11457 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11472
-/* 11463 */   MCD_OPC_CheckPredicate, 21, 173, 27, 0, // Skip to: 18553
-/* 11468 */   MCD_OPC_Decode, 155, 21, 97, // Opcode: VTSTv4i16
-/* 11472 */   MCD_OPC_FilterValue, 243, 1, 163, 27, 0, // Skip to: 18553
-/* 11478 */   MCD_OPC_CheckPredicate, 21, 158, 27, 0, // Skip to: 18553
-/* 11483 */   MCD_OPC_Decode, 161, 8, 97, // Opcode: VCEQv4i16
-/* 11487 */   MCD_OPC_FilterValue, 2, 149, 27, 0, // Skip to: 18553
-/* 11492 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11495 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11510
-/* 11501 */   MCD_OPC_CheckPredicate, 21, 135, 27, 0, // Skip to: 18553
-/* 11506 */   MCD_OPC_Decode, 154, 21, 97, // Opcode: VTSTv2i32
-/* 11510 */   MCD_OPC_FilterValue, 243, 1, 125, 27, 0, // Skip to: 18553
-/* 11516 */   MCD_OPC_CheckPredicate, 21, 120, 27, 0, // Skip to: 18553
-/* 11521 */   MCD_OPC_Decode, 160, 8, 97, // Opcode: VCEQv2i32
-/* 11525 */   MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 11615
-/* 11530 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11533 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11571
-/* 11538 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11541 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11556
-/* 11547 */   MCD_OPC_CheckPredicate, 21, 89, 27, 0, // Skip to: 18553
-/* 11552 */   MCD_OPC_Decode, 213, 14, 97, // Opcode: VMULv8i8
-/* 11556 */   MCD_OPC_FilterValue, 243, 1, 79, 27, 0, // Skip to: 18553
-/* 11562 */   MCD_OPC_CheckPredicate, 21, 74, 27, 0, // Skip to: 18553
-/* 11567 */   MCD_OPC_Decode, 198, 14, 97, // Opcode: VMULpd
-/* 11571 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 11593
-/* 11576 */   MCD_OPC_CheckPredicate, 21, 60, 27, 0, // Skip to: 18553
-/* 11581 */   MCD_OPC_CheckField, 24, 8, 242, 1, 52, 27, 0, // Skip to: 18553
-/* 11589 */   MCD_OPC_Decode, 210, 14, 97, // Opcode: VMULv4i16
-/* 11593 */   MCD_OPC_FilterValue, 2, 43, 27, 0, // Skip to: 18553
-/* 11598 */   MCD_OPC_CheckPredicate, 21, 38, 27, 0, // Skip to: 18553
-/* 11603 */   MCD_OPC_CheckField, 24, 8, 242, 1, 30, 27, 0, // Skip to: 18553
-/* 11611 */   MCD_OPC_Decode, 209, 14, 97, // Opcode: VMULv2i32
-/* 11615 */   MCD_OPC_FilterValue, 10, 117, 0, 0, // Skip to: 11737
-/* 11620 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11623 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 11661
-/* 11628 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11631 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11646
-/* 11637 */   MCD_OPC_CheckPredicate, 21, 255, 26, 0, // Skip to: 18553
-/* 11642 */   MCD_OPC_Decode, 163, 15, 97, // Opcode: VPMINs8
-/* 11646 */   MCD_OPC_FilterValue, 243, 1, 245, 26, 0, // Skip to: 18553
-/* 11652 */   MCD_OPC_CheckPredicate, 21, 240, 26, 0, // Skip to: 18553
-/* 11657 */   MCD_OPC_Decode, 166, 15, 97, // Opcode: VPMINu8
-/* 11661 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11699
-/* 11666 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11669 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11684
-/* 11675 */   MCD_OPC_CheckPredicate, 21, 217, 26, 0, // Skip to: 18553
-/* 11680 */   MCD_OPC_Decode, 161, 15, 97, // Opcode: VPMINs16
-/* 11684 */   MCD_OPC_FilterValue, 243, 1, 207, 26, 0, // Skip to: 18553
-/* 11690 */   MCD_OPC_CheckPredicate, 21, 202, 26, 0, // Skip to: 18553
-/* 11695 */   MCD_OPC_Decode, 164, 15, 97, // Opcode: VPMINu16
-/* 11699 */   MCD_OPC_FilterValue, 2, 193, 26, 0, // Skip to: 18553
-/* 11704 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11707 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11722
-/* 11713 */   MCD_OPC_CheckPredicate, 21, 179, 26, 0, // Skip to: 18553
-/* 11718 */   MCD_OPC_Decode, 162, 15, 97, // Opcode: VPMINs32
-/* 11722 */   MCD_OPC_FilterValue, 243, 1, 169, 26, 0, // Skip to: 18553
-/* 11728 */   MCD_OPC_CheckPredicate, 21, 164, 26, 0, // Skip to: 18553
-/* 11733 */   MCD_OPC_Decode, 165, 15, 97, // Opcode: VPMINu32
-/* 11737 */   MCD_OPC_FilterValue, 11, 101, 0, 0, // Skip to: 11843
-/* 11742 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11745 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11767
-/* 11750 */   MCD_OPC_CheckPredicate, 21, 142, 26, 0, // Skip to: 18553
-/* 11755 */   MCD_OPC_CheckField, 24, 8, 242, 1, 134, 26, 0, // Skip to: 18553
-/* 11763 */   MCD_OPC_Decode, 150, 15, 97, // Opcode: VPADDi8
-/* 11767 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11805
-/* 11772 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11775 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11790
-/* 11781 */   MCD_OPC_CheckPredicate, 21, 111, 26, 0, // Skip to: 18553
-/* 11786 */   MCD_OPC_Decode, 148, 15, 97, // Opcode: VPADDi16
-/* 11790 */   MCD_OPC_FilterValue, 243, 1, 101, 26, 0, // Skip to: 18553
-/* 11796 */   MCD_OPC_CheckPredicate, 23, 96, 26, 0, // Skip to: 18553
-/* 11801 */   MCD_OPC_Decode, 229, 15, 105, // Opcode: VQRDMLAHv4i16
-/* 11805 */   MCD_OPC_FilterValue, 2, 87, 26, 0, // Skip to: 18553
-/* 11810 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11813 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11828
-/* 11819 */   MCD_OPC_CheckPredicate, 21, 73, 26, 0, // Skip to: 18553
-/* 11824 */   MCD_OPC_Decode, 149, 15, 97, // Opcode: VPADDi32
-/* 11828 */   MCD_OPC_FilterValue, 243, 1, 63, 26, 0, // Skip to: 18553
-/* 11834 */   MCD_OPC_CheckPredicate, 23, 58, 26, 0, // Skip to: 18553
-/* 11839 */   MCD_OPC_Decode, 228, 15, 105, // Opcode: VQRDMLAHv2i32
-/* 11843 */   MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 11971
-/* 11848 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11851 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 11873
-/* 11856 */   MCD_OPC_CheckPredicate, 26, 36, 26, 0, // Skip to: 18553
-/* 11861 */   MCD_OPC_CheckField, 24, 8, 242, 1, 28, 26, 0, // Skip to: 18553
-/* 11869 */   MCD_OPC_Decode, 152, 10, 105, // Opcode: VFMAfd
-/* 11873 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 11911
-/* 11878 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11881 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11896
-/* 11887 */   MCD_OPC_CheckPredicate, 22, 5, 26, 0, // Skip to: 18553
-/* 11892 */   MCD_OPC_Decode, 154, 10, 105, // Opcode: VFMAhd
-/* 11896 */   MCD_OPC_FilterValue, 243, 1, 251, 25, 0, // Skip to: 18553
-/* 11902 */   MCD_OPC_CheckPredicate, 23, 246, 25, 0, // Skip to: 18553
-/* 11907 */   MCD_OPC_Decode, 237, 15, 105, // Opcode: VQRDMLSHv4i16
-/* 11911 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 11949
-/* 11916 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11919 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 11934
-/* 11925 */   MCD_OPC_CheckPredicate, 26, 223, 25, 0, // Skip to: 18553
-/* 11930 */   MCD_OPC_Decode, 159, 10, 105, // Opcode: VFMSfd
-/* 11934 */   MCD_OPC_FilterValue, 243, 1, 213, 25, 0, // Skip to: 18553
-/* 11940 */   MCD_OPC_CheckPredicate, 23, 208, 25, 0, // Skip to: 18553
-/* 11945 */   MCD_OPC_Decode, 236, 15, 105, // Opcode: VQRDMLSHv2i32
-/* 11949 */   MCD_OPC_FilterValue, 3, 199, 25, 0, // Skip to: 18553
-/* 11954 */   MCD_OPC_CheckPredicate, 22, 194, 25, 0, // Skip to: 18553
-/* 11959 */   MCD_OPC_CheckField, 24, 8, 242, 1, 186, 25, 0, // Skip to: 18553
-/* 11967 */   MCD_OPC_Decode, 161, 10, 105, // Opcode: VFMShd
-/* 11971 */   MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 12099
-/* 11976 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 11979 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 12017
-/* 11984 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 11987 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12002
-/* 11993 */   MCD_OPC_CheckPredicate, 21, 155, 25, 0, // Skip to: 18553
-/* 11998 */   MCD_OPC_Decode, 215, 13, 105, // Opcode: VMLAfd
-/* 12002 */   MCD_OPC_FilterValue, 243, 1, 145, 25, 0, // Skip to: 18553
-/* 12008 */   MCD_OPC_CheckPredicate, 21, 140, 25, 0, // Skip to: 18553
-/* 12013 */   MCD_OPC_Decode, 194, 14, 97, // Opcode: VMULfd
-/* 12017 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 12055
-/* 12022 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 12025 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 12040
-/* 12031 */   MCD_OPC_CheckPredicate, 22, 117, 25, 0, // Skip to: 18553
-/* 12036 */   MCD_OPC_Decode, 217, 13, 105, // Opcode: VMLAhd
-/* 12040 */   MCD_OPC_FilterValue, 243, 1, 107, 25, 0, // Skip to: 18553
-/* 12046 */   MCD_OPC_CheckPredicate, 22, 102, 25, 0, // Skip to: 18553
-/* 12051 */   MCD_OPC_Decode, 196, 14, 97, // Opcode: VMULhd
-/* 12055 */   MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12077
-/* 12060 */   MCD_OPC_CheckPredicate, 21, 88, 25, 0, // Skip to: 18553
-/* 12065 */   MCD_OPC_CheckField, 24, 8, 242, 1, 80, 25, 0, // Skip to: 18553
-/* 12073 */   MCD_OPC_Decode, 246, 13, 105, // Opcode: VMLSfd
-/* 12077 */   MCD_OPC_FilterValue, 3, 71, 25, 0, // Skip to: 18553
-/* 12082 */   MCD_OPC_CheckPredicate, 22, 66, 25, 0, // Skip to: 18553
-/* 12087 */   MCD_OPC_CheckField, 24, 8, 242, 1, 58, 25, 0, // Skip to: 18553
-/* 12095 */   MCD_OPC_Decode, 248, 13, 105, // Opcode: VMLShd
-/* 12099 */   MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 12195
-/* 12104 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 12107 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12129
-/* 12112 */   MCD_OPC_CheckPredicate, 21, 36, 25, 0, // Skip to: 18553
-/* 12117 */   MCD_OPC_CheckField, 24, 8, 243, 1, 28, 25, 0, // Skip to: 18553
-/* 12125 */   MCD_OPC_Decode, 227, 7, 97, // Opcode: VACGEfd
-/* 12129 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12151
-/* 12134 */   MCD_OPC_CheckPredicate, 22, 14, 25, 0, // Skip to: 18553
-/* 12139 */   MCD_OPC_CheckField, 24, 8, 243, 1, 6, 25, 0, // Skip to: 18553
-/* 12147 */   MCD_OPC_Decode, 229, 7, 97, // Opcode: VACGEhd
-/* 12151 */   MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12173
-/* 12156 */   MCD_OPC_CheckPredicate, 21, 248, 24, 0, // Skip to: 18553
-/* 12161 */   MCD_OPC_CheckField, 24, 8, 243, 1, 240, 24, 0, // Skip to: 18553
-/* 12169 */   MCD_OPC_Decode, 231, 7, 97, // Opcode: VACGTfd
-/* 12173 */   MCD_OPC_FilterValue, 3, 231, 24, 0, // Skip to: 18553
-/* 12178 */   MCD_OPC_CheckPredicate, 22, 226, 24, 0, // Skip to: 18553
-/* 12183 */   MCD_OPC_CheckField, 24, 8, 243, 1, 218, 24, 0, // Skip to: 18553
-/* 12191 */   MCD_OPC_Decode, 233, 7, 97, // Opcode: VACGThd
-/* 12195 */   MCD_OPC_FilterValue, 15, 209, 24, 0, // Skip to: 18553
-/* 12200 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 12203 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12225
-/* 12208 */   MCD_OPC_CheckPredicate, 21, 196, 24, 0, // Skip to: 18553
-/* 12213 */   MCD_OPC_CheckField, 24, 8, 242, 1, 188, 24, 0, // Skip to: 18553
-/* 12221 */   MCD_OPC_Decode, 219, 16, 97, // Opcode: VRECPSfd
-/* 12225 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 12247
-/* 12230 */   MCD_OPC_CheckPredicate, 22, 174, 24, 0, // Skip to: 18553
-/* 12235 */   MCD_OPC_CheckField, 24, 8, 242, 1, 166, 24, 0, // Skip to: 18553
-/* 12243 */   MCD_OPC_Decode, 221, 16, 97, // Opcode: VRECPShd
-/* 12247 */   MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 12269
-/* 12252 */   MCD_OPC_CheckPredicate, 21, 152, 24, 0, // Skip to: 18553
-/* 12257 */   MCD_OPC_CheckField, 24, 8, 242, 1, 144, 24, 0, // Skip to: 18553
-/* 12265 */   MCD_OPC_Decode, 205, 17, 97, // Opcode: VRSQRTSfd
-/* 12269 */   MCD_OPC_FilterValue, 3, 135, 24, 0, // Skip to: 18553
-/* 12274 */   MCD_OPC_CheckPredicate, 22, 130, 24, 0, // Skip to: 18553
-/* 12279 */   MCD_OPC_CheckField, 24, 8, 242, 1, 122, 24, 0, // Skip to: 18553
-/* 12287 */   MCD_OPC_Decode, 207, 17, 97, // Opcode: VRSQRTShd
-/* 12291 */   MCD_OPC_FilterValue, 1, 113, 24, 0, // Skip to: 18553
-/* 12296 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 12299 */   MCD_OPC_FilterValue, 0, 209, 7, 0, // Skip to: 14305
-/* 12304 */   MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
-/* 12307 */   MCD_OPC_FilterValue, 121, 97, 24, 0, // Skip to: 18553
-/* 12312 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 12315 */   MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 12459
-/* 12320 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 12323 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12421
-/* 12328 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 12331 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12383
-/* 12336 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12339 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12361
-/* 12344 */   MCD_OPC_CheckPredicate, 21, 231, 6, 0, // Skip to: 14116
-/* 12349 */   MCD_OPC_CheckField, 19, 1, 1, 224, 6, 0, // Skip to: 14116
-/* 12356 */   MCD_OPC_Decode, 162, 18, 142, 1, // Opcode: VSHRsv8i8
-/* 12361 */   MCD_OPC_FilterValue, 1, 214, 6, 0, // Skip to: 14116
-/* 12366 */   MCD_OPC_CheckPredicate, 21, 209, 6, 0, // Skip to: 14116
-/* 12371 */   MCD_OPC_CheckField, 19, 1, 1, 202, 6, 0, // Skip to: 14116
-/* 12378 */   MCD_OPC_Decode, 170, 18, 142, 1, // Opcode: VSHRuv8i8
-/* 12383 */   MCD_OPC_FilterValue, 1, 192, 6, 0, // Skip to: 14116
-/* 12388 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12391 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12406
-/* 12396 */   MCD_OPC_CheckPredicate, 21, 179, 6, 0, // Skip to: 14116
-/* 12401 */   MCD_OPC_Decode, 159, 18, 143, 1, // Opcode: VSHRsv4i16
-/* 12406 */   MCD_OPC_FilterValue, 1, 169, 6, 0, // Skip to: 14116
-/* 12411 */   MCD_OPC_CheckPredicate, 21, 164, 6, 0, // Skip to: 14116
-/* 12416 */   MCD_OPC_Decode, 167, 18, 143, 1, // Opcode: VSHRuv4i16
-/* 12421 */   MCD_OPC_FilterValue, 1, 154, 6, 0, // Skip to: 14116
-/* 12426 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12429 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12444
-/* 12434 */   MCD_OPC_CheckPredicate, 21, 141, 6, 0, // Skip to: 14116
-/* 12439 */   MCD_OPC_Decode, 157, 18, 144, 1, // Opcode: VSHRsv2i32
-/* 12444 */   MCD_OPC_FilterValue, 1, 131, 6, 0, // Skip to: 14116
-/* 12449 */   MCD_OPC_CheckPredicate, 21, 126, 6, 0, // Skip to: 14116
-/* 12454 */   MCD_OPC_Decode, 165, 18, 144, 1, // Opcode: VSHRuv2i32
-/* 12459 */   MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 12603
-/* 12464 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 12467 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12565
-/* 12472 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 12475 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12527
-/* 12480 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12483 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12505
-/* 12488 */   MCD_OPC_CheckPredicate, 21, 87, 6, 0, // Skip to: 14116
-/* 12493 */   MCD_OPC_CheckField, 19, 1, 1, 80, 6, 0, // Skip to: 14116
-/* 12500 */   MCD_OPC_Decode, 198, 18, 145, 1, // Opcode: VSRAsv8i8
-/* 12505 */   MCD_OPC_FilterValue, 1, 70, 6, 0, // Skip to: 14116
-/* 12510 */   MCD_OPC_CheckPredicate, 21, 65, 6, 0, // Skip to: 14116
-/* 12515 */   MCD_OPC_CheckField, 19, 1, 1, 58, 6, 0, // Skip to: 14116
-/* 12522 */   MCD_OPC_Decode, 206, 18, 145, 1, // Opcode: VSRAuv8i8
-/* 12527 */   MCD_OPC_FilterValue, 1, 48, 6, 0, // Skip to: 14116
-/* 12532 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12535 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12550
-/* 12540 */   MCD_OPC_CheckPredicate, 21, 35, 6, 0, // Skip to: 14116
-/* 12545 */   MCD_OPC_Decode, 195, 18, 146, 1, // Opcode: VSRAsv4i16
-/* 12550 */   MCD_OPC_FilterValue, 1, 25, 6, 0, // Skip to: 14116
-/* 12555 */   MCD_OPC_CheckPredicate, 21, 20, 6, 0, // Skip to: 14116
-/* 12560 */   MCD_OPC_Decode, 203, 18, 146, 1, // Opcode: VSRAuv4i16
-/* 12565 */   MCD_OPC_FilterValue, 1, 10, 6, 0, // Skip to: 14116
-/* 12570 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12573 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12588
-/* 12578 */   MCD_OPC_CheckPredicate, 21, 253, 5, 0, // Skip to: 14116
-/* 12583 */   MCD_OPC_Decode, 193, 18, 147, 1, // Opcode: VSRAsv2i32
-/* 12588 */   MCD_OPC_FilterValue, 1, 243, 5, 0, // Skip to: 14116
-/* 12593 */   MCD_OPC_CheckPredicate, 21, 238, 5, 0, // Skip to: 14116
-/* 12598 */   MCD_OPC_Decode, 201, 18, 147, 1, // Opcode: VSRAuv2i32
-/* 12603 */   MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 12747
-/* 12608 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 12611 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12709
-/* 12616 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 12619 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12671
-/* 12624 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12627 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12649
-/* 12632 */   MCD_OPC_CheckPredicate, 21, 199, 5, 0, // Skip to: 14116
-/* 12637 */   MCD_OPC_CheckField, 19, 1, 1, 192, 5, 0, // Skip to: 14116
-/* 12644 */   MCD_OPC_Decode, 190, 17, 142, 1, // Opcode: VRSHRsv8i8
-/* 12649 */   MCD_OPC_FilterValue, 1, 182, 5, 0, // Skip to: 14116
-/* 12654 */   MCD_OPC_CheckPredicate, 21, 177, 5, 0, // Skip to: 14116
-/* 12659 */   MCD_OPC_CheckField, 19, 1, 1, 170, 5, 0, // Skip to: 14116
-/* 12666 */   MCD_OPC_Decode, 198, 17, 142, 1, // Opcode: VRSHRuv8i8
-/* 12671 */   MCD_OPC_FilterValue, 1, 160, 5, 0, // Skip to: 14116
-/* 12676 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12679 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12694
-/* 12684 */   MCD_OPC_CheckPredicate, 21, 147, 5, 0, // Skip to: 14116
-/* 12689 */   MCD_OPC_Decode, 187, 17, 143, 1, // Opcode: VRSHRsv4i16
-/* 12694 */   MCD_OPC_FilterValue, 1, 137, 5, 0, // Skip to: 14116
-/* 12699 */   MCD_OPC_CheckPredicate, 21, 132, 5, 0, // Skip to: 14116
-/* 12704 */   MCD_OPC_Decode, 195, 17, 143, 1, // Opcode: VRSHRuv4i16
-/* 12709 */   MCD_OPC_FilterValue, 1, 122, 5, 0, // Skip to: 14116
-/* 12714 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12717 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12732
-/* 12722 */   MCD_OPC_CheckPredicate, 21, 109, 5, 0, // Skip to: 14116
-/* 12727 */   MCD_OPC_Decode, 185, 17, 144, 1, // Opcode: VRSHRsv2i32
-/* 12732 */   MCD_OPC_FilterValue, 1, 99, 5, 0, // Skip to: 14116
-/* 12737 */   MCD_OPC_CheckPredicate, 21, 94, 5, 0, // Skip to: 14116
-/* 12742 */   MCD_OPC_Decode, 193, 17, 144, 1, // Opcode: VRSHRuv2i32
-/* 12747 */   MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 12891
-/* 12752 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 12755 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 12853
-/* 12760 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 12763 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12815
-/* 12768 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12771 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12793
-/* 12776 */   MCD_OPC_CheckPredicate, 21, 55, 5, 0, // Skip to: 14116
-/* 12781 */   MCD_OPC_CheckField, 19, 1, 1, 48, 5, 0, // Skip to: 14116
-/* 12788 */   MCD_OPC_Decode, 216, 17, 145, 1, // Opcode: VRSRAsv8i8
-/* 12793 */   MCD_OPC_FilterValue, 1, 38, 5, 0, // Skip to: 14116
-/* 12798 */   MCD_OPC_CheckPredicate, 21, 33, 5, 0, // Skip to: 14116
-/* 12803 */   MCD_OPC_CheckField, 19, 1, 1, 26, 5, 0, // Skip to: 14116
-/* 12810 */   MCD_OPC_Decode, 224, 17, 145, 1, // Opcode: VRSRAuv8i8
-/* 12815 */   MCD_OPC_FilterValue, 1, 16, 5, 0, // Skip to: 14116
-/* 12820 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12823 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12838
-/* 12828 */   MCD_OPC_CheckPredicate, 21, 3, 5, 0, // Skip to: 14116
-/* 12833 */   MCD_OPC_Decode, 213, 17, 146, 1, // Opcode: VRSRAsv4i16
-/* 12838 */   MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 14116
-/* 12843 */   MCD_OPC_CheckPredicate, 21, 244, 4, 0, // Skip to: 14116
-/* 12848 */   MCD_OPC_Decode, 221, 17, 146, 1, // Opcode: VRSRAuv4i16
-/* 12853 */   MCD_OPC_FilterValue, 1, 234, 4, 0, // Skip to: 14116
-/* 12858 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 12861 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12876
-/* 12866 */   MCD_OPC_CheckPredicate, 21, 221, 4, 0, // Skip to: 14116
-/* 12871 */   MCD_OPC_Decode, 211, 17, 147, 1, // Opcode: VRSRAsv2i32
-/* 12876 */   MCD_OPC_FilterValue, 1, 211, 4, 0, // Skip to: 14116
-/* 12881 */   MCD_OPC_CheckPredicate, 21, 206, 4, 0, // Skip to: 14116
-/* 12886 */   MCD_OPC_Decode, 219, 17, 147, 1, // Opcode: VRSRAuv2i32
-/* 12891 */   MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 12980
-/* 12896 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 12899 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 12958
-/* 12904 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 12907 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 12936
-/* 12912 */   MCD_OPC_CheckPredicate, 21, 175, 4, 0, // Skip to: 14116
-/* 12917 */   MCD_OPC_CheckField, 24, 1, 1, 168, 4, 0, // Skip to: 14116
-/* 12924 */   MCD_OPC_CheckField, 19, 1, 1, 161, 4, 0, // Skip to: 14116
-/* 12931 */   MCD_OPC_Decode, 214, 18, 145, 1, // Opcode: VSRIv8i8
-/* 12936 */   MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 14116
-/* 12941 */   MCD_OPC_CheckPredicate, 21, 146, 4, 0, // Skip to: 14116
-/* 12946 */   MCD_OPC_CheckField, 24, 1, 1, 139, 4, 0, // Skip to: 14116
-/* 12953 */   MCD_OPC_Decode, 211, 18, 146, 1, // Opcode: VSRIv4i16
-/* 12958 */   MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 14116
-/* 12963 */   MCD_OPC_CheckPredicate, 21, 124, 4, 0, // Skip to: 14116
-/* 12968 */   MCD_OPC_CheckField, 24, 1, 1, 117, 4, 0, // Skip to: 14116
-/* 12975 */   MCD_OPC_Decode, 209, 18, 147, 1, // Opcode: VSRIv2i32
-/* 12980 */   MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 13124
-/* 12985 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 12988 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13086
-/* 12993 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 12996 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13048
-/* 13001 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13004 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13026
-/* 13009 */   MCD_OPC_CheckPredicate, 21, 78, 4, 0, // Skip to: 14116
-/* 13014 */   MCD_OPC_CheckField, 19, 1, 1, 71, 4, 0, // Skip to: 14116
-/* 13021 */   MCD_OPC_Decode, 135, 18, 148, 1, // Opcode: VSHLiv8i8
-/* 13026 */   MCD_OPC_FilterValue, 1, 61, 4, 0, // Skip to: 14116
-/* 13031 */   MCD_OPC_CheckPredicate, 21, 56, 4, 0, // Skip to: 14116
-/* 13036 */   MCD_OPC_CheckField, 19, 1, 1, 49, 4, 0, // Skip to: 14116
-/* 13043 */   MCD_OPC_Decode, 184, 18, 149, 1, // Opcode: VSLIv8i8
-/* 13048 */   MCD_OPC_FilterValue, 1, 39, 4, 0, // Skip to: 14116
-/* 13053 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13056 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13071
-/* 13061 */   MCD_OPC_CheckPredicate, 21, 26, 4, 0, // Skip to: 14116
-/* 13066 */   MCD_OPC_Decode, 132, 18, 150, 1, // Opcode: VSHLiv4i16
-/* 13071 */   MCD_OPC_FilterValue, 1, 16, 4, 0, // Skip to: 14116
-/* 13076 */   MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 14116
-/* 13081 */   MCD_OPC_Decode, 181, 18, 151, 1, // Opcode: VSLIv4i16
-/* 13086 */   MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 14116
-/* 13091 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13094 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13109
-/* 13099 */   MCD_OPC_CheckPredicate, 21, 244, 3, 0, // Skip to: 14116
-/* 13104 */   MCD_OPC_Decode, 130, 18, 152, 1, // Opcode: VSHLiv2i32
-/* 13109 */   MCD_OPC_FilterValue, 1, 234, 3, 0, // Skip to: 14116
-/* 13114 */   MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 14116
-/* 13119 */   MCD_OPC_Decode, 179, 18, 153, 1, // Opcode: VSLIv2i32
-/* 13124 */   MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 13213
-/* 13129 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 13132 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 13191
-/* 13137 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 13140 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13169
-/* 13145 */   MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 14116
-/* 13150 */   MCD_OPC_CheckField, 24, 1, 1, 191, 3, 0, // Skip to: 14116
-/* 13157 */   MCD_OPC_CheckField, 19, 1, 1, 184, 3, 0, // Skip to: 14116
-/* 13164 */   MCD_OPC_Decode, 160, 16, 148, 1, // Opcode: VQSHLsuv8i8
-/* 13169 */   MCD_OPC_FilterValue, 1, 174, 3, 0, // Skip to: 14116
-/* 13174 */   MCD_OPC_CheckPredicate, 21, 169, 3, 0, // Skip to: 14116
-/* 13179 */   MCD_OPC_CheckField, 24, 1, 1, 162, 3, 0, // Skip to: 14116
-/* 13186 */   MCD_OPC_Decode, 157, 16, 150, 1, // Opcode: VQSHLsuv4i16
-/* 13191 */   MCD_OPC_FilterValue, 1, 152, 3, 0, // Skip to: 14116
-/* 13196 */   MCD_OPC_CheckPredicate, 21, 147, 3, 0, // Skip to: 14116
-/* 13201 */   MCD_OPC_CheckField, 24, 1, 1, 140, 3, 0, // Skip to: 14116
-/* 13208 */   MCD_OPC_Decode, 155, 16, 152, 1, // Opcode: VQSHLsuv2i32
-/* 13213 */   MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 13357
-/* 13218 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 13221 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13319
-/* 13226 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 13229 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13281
-/* 13234 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13237 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13259
-/* 13242 */   MCD_OPC_CheckPredicate, 21, 101, 3, 0, // Skip to: 14116
-/* 13247 */   MCD_OPC_CheckField, 19, 1, 1, 94, 3, 0, // Skip to: 14116
-/* 13254 */   MCD_OPC_Decode, 152, 16, 148, 1, // Opcode: VQSHLsiv8i8
-/* 13259 */   MCD_OPC_FilterValue, 1, 84, 3, 0, // Skip to: 14116
-/* 13264 */   MCD_OPC_CheckPredicate, 21, 79, 3, 0, // Skip to: 14116
-/* 13269 */   MCD_OPC_CheckField, 19, 1, 1, 72, 3, 0, // Skip to: 14116
-/* 13276 */   MCD_OPC_Decode, 176, 16, 148, 1, // Opcode: VQSHLuiv8i8
-/* 13281 */   MCD_OPC_FilterValue, 1, 62, 3, 0, // Skip to: 14116
-/* 13286 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13289 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13304
-/* 13294 */   MCD_OPC_CheckPredicate, 21, 49, 3, 0, // Skip to: 14116
-/* 13299 */   MCD_OPC_Decode, 149, 16, 150, 1, // Opcode: VQSHLsiv4i16
-/* 13304 */   MCD_OPC_FilterValue, 1, 39, 3, 0, // Skip to: 14116
-/* 13309 */   MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 14116
-/* 13314 */   MCD_OPC_Decode, 173, 16, 150, 1, // Opcode: VQSHLuiv4i16
-/* 13319 */   MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 14116
-/* 13324 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13327 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13342
-/* 13332 */   MCD_OPC_CheckPredicate, 21, 11, 3, 0, // Skip to: 14116
-/* 13337 */   MCD_OPC_Decode, 147, 16, 152, 1, // Opcode: VQSHLsiv2i32
-/* 13342 */   MCD_OPC_FilterValue, 1, 1, 3, 0, // Skip to: 14116
-/* 13347 */   MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 14116
-/* 13352 */   MCD_OPC_Decode, 171, 16, 152, 1, // Opcode: VQSHLuiv2i32
-/* 13357 */   MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 13501
-/* 13362 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 13365 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13463
-/* 13370 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 13373 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13425
-/* 13378 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13381 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13403
-/* 13386 */   MCD_OPC_CheckPredicate, 21, 213, 2, 0, // Skip to: 14116
-/* 13391 */   MCD_OPC_CheckField, 19, 1, 1, 206, 2, 0, // Skip to: 14116
-/* 13398 */   MCD_OPC_Decode, 154, 18, 154, 1, // Opcode: VSHRNv8i8
-/* 13403 */   MCD_OPC_FilterValue, 1, 196, 2, 0, // Skip to: 14116
-/* 13408 */   MCD_OPC_CheckPredicate, 21, 191, 2, 0, // Skip to: 14116
-/* 13413 */   MCD_OPC_CheckField, 19, 1, 1, 184, 2, 0, // Skip to: 14116
-/* 13420 */   MCD_OPC_Decode, 193, 16, 154, 1, // Opcode: VQSHRUNv8i8
-/* 13425 */   MCD_OPC_FilterValue, 1, 174, 2, 0, // Skip to: 14116
-/* 13430 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13433 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13448
-/* 13438 */   MCD_OPC_CheckPredicate, 21, 161, 2, 0, // Skip to: 14116
-/* 13443 */   MCD_OPC_Decode, 153, 18, 155, 1, // Opcode: VSHRNv4i16
-/* 13448 */   MCD_OPC_FilterValue, 1, 151, 2, 0, // Skip to: 14116
-/* 13453 */   MCD_OPC_CheckPredicate, 21, 146, 2, 0, // Skip to: 14116
-/* 13458 */   MCD_OPC_Decode, 192, 16, 155, 1, // Opcode: VQSHRUNv4i16
-/* 13463 */   MCD_OPC_FilterValue, 1, 136, 2, 0, // Skip to: 14116
-/* 13468 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13471 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13486
-/* 13476 */   MCD_OPC_CheckPredicate, 21, 123, 2, 0, // Skip to: 14116
-/* 13481 */   MCD_OPC_Decode, 152, 18, 156, 1, // Opcode: VSHRNv2i32
-/* 13486 */   MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 14116
-/* 13491 */   MCD_OPC_CheckPredicate, 21, 108, 2, 0, // Skip to: 14116
-/* 13496 */   MCD_OPC_Decode, 191, 16, 156, 1, // Opcode: VQSHRUNv2i32
-/* 13501 */   MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 13645
-/* 13506 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 13509 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13607
-/* 13514 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 13517 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13569
-/* 13522 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13525 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13547
-/* 13530 */   MCD_OPC_CheckPredicate, 21, 69, 2, 0, // Skip to: 14116
-/* 13535 */   MCD_OPC_CheckField, 19, 1, 1, 62, 2, 0, // Skip to: 14116
-/* 13542 */   MCD_OPC_Decode, 187, 16, 154, 1, // Opcode: VQSHRNsv8i8
-/* 13547 */   MCD_OPC_FilterValue, 1, 52, 2, 0, // Skip to: 14116
-/* 13552 */   MCD_OPC_CheckPredicate, 21, 47, 2, 0, // Skip to: 14116
-/* 13557 */   MCD_OPC_CheckField, 19, 1, 1, 40, 2, 0, // Skip to: 14116
-/* 13564 */   MCD_OPC_Decode, 190, 16, 154, 1, // Opcode: VQSHRNuv8i8
-/* 13569 */   MCD_OPC_FilterValue, 1, 30, 2, 0, // Skip to: 14116
-/* 13574 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13577 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13592
-/* 13582 */   MCD_OPC_CheckPredicate, 21, 17, 2, 0, // Skip to: 14116
-/* 13587 */   MCD_OPC_Decode, 186, 16, 155, 1, // Opcode: VQSHRNsv4i16
-/* 13592 */   MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 14116
-/* 13597 */   MCD_OPC_CheckPredicate, 21, 2, 2, 0, // Skip to: 14116
-/* 13602 */   MCD_OPC_Decode, 189, 16, 155, 1, // Opcode: VQSHRNuv4i16
-/* 13607 */   MCD_OPC_FilterValue, 1, 248, 1, 0, // Skip to: 14116
-/* 13612 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13615 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13630
-/* 13620 */   MCD_OPC_CheckPredicate, 21, 235, 1, 0, // Skip to: 14116
-/* 13625 */   MCD_OPC_Decode, 185, 16, 156, 1, // Opcode: VQSHRNsv2i32
-/* 13630 */   MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 14116
-/* 13635 */   MCD_OPC_CheckPredicate, 21, 220, 1, 0, // Skip to: 14116
-/* 13640 */   MCD_OPC_Decode, 188, 16, 156, 1, // Opcode: VQSHRNuv2i32
-/* 13645 */   MCD_OPC_FilterValue, 10, 243, 0, 0, // Skip to: 13893
-/* 13650 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 13653 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 13821
-/* 13658 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 13661 */   MCD_OPC_FilterValue, 0, 83, 0, 0, // Skip to: 13749
-/* 13666 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13669 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 13709
-/* 13674 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
-/* 13677 */   MCD_OPC_FilterValue, 1, 178, 1, 0, // Skip to: 14116
-/* 13682 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13699
-/* 13687 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13699
-/* 13694 */   MCD_OPC_Decode, 142, 14, 134, 1, // Opcode: VMOVLsv8i16
-/* 13699 */   MCD_OPC_CheckPredicate, 21, 156, 1, 0, // Skip to: 14116
-/* 13704 */   MCD_OPC_Decode, 252, 17, 157, 1, // Opcode: VSHLLsv8i16
-/* 13709 */   MCD_OPC_FilterValue, 1, 146, 1, 0, // Skip to: 14116
-/* 13714 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
-/* 13717 */   MCD_OPC_FilterValue, 1, 138, 1, 0, // Skip to: 14116
-/* 13722 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13739
-/* 13727 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 13739
-/* 13734 */   MCD_OPC_Decode, 145, 14, 134, 1, // Opcode: VMOVLuv8i16
-/* 13739 */   MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 14116
-/* 13744 */   MCD_OPC_Decode, 255, 17, 157, 1, // Opcode: VSHLLuv8i16
-/* 13749 */   MCD_OPC_FilterValue, 1, 106, 1, 0, // Skip to: 14116
-/* 13754 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13757 */   MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13789
-/* 13762 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13779
-/* 13767 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13779
-/* 13774 */   MCD_OPC_Decode, 141, 14, 134, 1, // Opcode: VMOVLsv4i32
-/* 13779 */   MCD_OPC_CheckPredicate, 21, 76, 1, 0, // Skip to: 14116
-/* 13784 */   MCD_OPC_Decode, 251, 17, 158, 1, // Opcode: VSHLLsv4i32
-/* 13789 */   MCD_OPC_FilterValue, 1, 66, 1, 0, // Skip to: 14116
-/* 13794 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13811
-/* 13799 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 13811
-/* 13806 */   MCD_OPC_Decode, 144, 14, 134, 1, // Opcode: VMOVLuv4i32
-/* 13811 */   MCD_OPC_CheckPredicate, 21, 44, 1, 0, // Skip to: 14116
-/* 13816 */   MCD_OPC_Decode, 254, 17, 158, 1, // Opcode: VSHLLuv4i32
-/* 13821 */   MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 14116
-/* 13826 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13829 */   MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 13861
-/* 13834 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13851
-/* 13839 */   MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13851
-/* 13846 */   MCD_OPC_Decode, 140, 14, 134, 1, // Opcode: VMOVLsv2i64
-/* 13851 */   MCD_OPC_CheckPredicate, 21, 4, 1, 0, // Skip to: 14116
-/* 13856 */   MCD_OPC_Decode, 250, 17, 159, 1, // Opcode: VSHLLsv2i64
-/* 13861 */   MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 14116
-/* 13866 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 13883
-/* 13871 */   MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 13883
-/* 13878 */   MCD_OPC_Decode, 143, 14, 134, 1, // Opcode: VMOVLuv2i64
-/* 13883 */   MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 14116
-/* 13888 */   MCD_OPC_Decode, 253, 17, 159, 1, // Opcode: VSHLLuv2i64
-/* 13893 */   MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 13931
-/* 13898 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13901 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13916
-/* 13906 */   MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 14116
-/* 13911 */   MCD_OPC_Decode, 247, 9, 160, 1, // Opcode: VCVTxs2hd
-/* 13916 */   MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 14116
-/* 13921 */   MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 14116
-/* 13926 */   MCD_OPC_Decode, 251, 9, 160, 1, // Opcode: VCVTxu2hd
-/* 13931 */   MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 13969
-/* 13936 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 13939 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13954
-/* 13944 */   MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 14116
-/* 13949 */   MCD_OPC_Decode, 233, 9, 160, 1, // Opcode: VCVTh2xsd
-/* 13954 */   MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 14116
-/* 13959 */   MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 14116
-/* 13964 */   MCD_OPC_Decode, 235, 9, 160, 1, // Opcode: VCVTh2xud
-/* 13969 */   MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 14054
-/* 13974 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 13977 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13999
-/* 13982 */   MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 14021
-/* 13987 */   MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 14021
-/* 13994 */   MCD_OPC_Decode, 165, 14, 161, 1, // Opcode: VMOVv8i8
-/* 13999 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14021
-/* 14004 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14021
-/* 14009 */   MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 14021
-/* 14016 */   MCD_OPC_Decode, 157, 14, 161, 1, // Opcode: VMOVv1i64
-/* 14021 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 14024 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14039
-/* 14029 */   MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 14116
-/* 14034 */   MCD_OPC_Decode, 245, 9, 160, 1, // Opcode: VCVTxs2fd
-/* 14039 */   MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 14116
-/* 14044 */   MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 14116
-/* 14049 */   MCD_OPC_Decode, 249, 9, 160, 1, // Opcode: VCVTxu2fd
-/* 14054 */   MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 14116
-/* 14059 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 14062 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14077
-/* 14067 */   MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 14092
-/* 14072 */   MCD_OPC_Decode, 224, 9, 160, 1, // Opcode: VCVTf2xsd
-/* 14077 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14092
-/* 14082 */   MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 14092
-/* 14087 */   MCD_OPC_Decode, 226, 9, 160, 1, // Opcode: VCVTf2xud
-/* 14092 */   MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 14116
-/* 14097 */   MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 14116
-/* 14104 */   MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 14116
-/* 14111 */   MCD_OPC_Decode, 158, 14, 161, 1, // Opcode: VMOVv2f32
-/* 14116 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 14119 */   MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 14212
-/* 14124 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
-/* 14127 */   MCD_OPC_FilterValue, 0, 69, 17, 0, // Skip to: 18553
-/* 14132 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 14135 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14157
-/* 14140 */   MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14202
-/* 14145 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14202
-/* 14152 */   MCD_OPC_Decode, 162, 14, 161, 1, // Opcode: VMOVv4i16
-/* 14157 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14202
-/* 14162 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 4214 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4229
+/* 4219 */    MCD_OPC_CheckPredicate, 26, 159, 58, 0, // Skip to: 19231
+/* 4224 */    MCD_OPC_Decode, 218, 25, 202, 1, // Opcode: VRHADDsv2i32
+/* 4229 */    MCD_OPC_FilterValue, 1, 149, 58, 0, // Skip to: 19231
+/* 4234 */    MCD_OPC_CheckPredicate, 26, 144, 58, 0, // Skip to: 19231
+/* 4239 */    MCD_OPC_Decode, 220, 25, 203, 1, // Opcode: VRHADDsv4i32
+/* 4244 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 4283
+/* 4250 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4253 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4268
+/* 4258 */    MCD_OPC_CheckPredicate, 26, 120, 58, 0, // Skip to: 19231
+/* 4263 */    MCD_OPC_Decode, 162, 16, 205, 1, // Opcode: VADDWsv2i64
+/* 4268 */    MCD_OPC_FilterValue, 1, 110, 58, 0, // Skip to: 19231
+/* 4273 */    MCD_OPC_CheckPredicate, 26, 105, 58, 0, // Skip to: 19231
+/* 4278 */    MCD_OPC_Decode, 190, 22, 218, 1, // Opcode: VMLAslfd
+/* 4283 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 4322
+/* 4289 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4292 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4307
+/* 4297 */    MCD_OPC_CheckPredicate, 26, 81, 58, 0, // Skip to: 19231
+/* 4302 */    MCD_OPC_Decode, 224, 25, 202, 1, // Opcode: VRHADDuv2i32
+/* 4307 */    MCD_OPC_FilterValue, 1, 71, 58, 0, // Skip to: 19231
+/* 4312 */    MCD_OPC_CheckPredicate, 26, 66, 58, 0, // Skip to: 19231
+/* 4317 */    MCD_OPC_Decode, 226, 25, 203, 1, // Opcode: VRHADDuv4i32
+/* 4322 */    MCD_OPC_FilterValue, 231, 3, 55, 58, 0, // Skip to: 19231
+/* 4328 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4331 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4346
+/* 4336 */    MCD_OPC_CheckPredicate, 26, 42, 58, 0, // Skip to: 19231
+/* 4341 */    MCD_OPC_Decode, 165, 16, 205, 1, // Opcode: VADDWuv2i64
+/* 4346 */    MCD_OPC_FilterValue, 1, 32, 58, 0, // Skip to: 19231
+/* 4351 */    MCD_OPC_CheckPredicate, 26, 27, 58, 0, // Skip to: 19231
+/* 4356 */    MCD_OPC_Decode, 191, 22, 219, 1, // Opcode: VMLAslfq
+/* 4361 */    MCD_OPC_FilterValue, 2, 159, 0, 0, // Skip to: 4525
+/* 4366 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 4369 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 4408
+/* 4375 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4378 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4393
+/* 4383 */    MCD_OPC_CheckPredicate, 26, 251, 57, 0, // Skip to: 19231
+/* 4388 */    MCD_OPC_Decode, 250, 18, 202, 1, // Opcode: VHSUBsv2i32
+/* 4393 */    MCD_OPC_FilterValue, 1, 241, 57, 0, // Skip to: 19231
+/* 4398 */    MCD_OPC_CheckPredicate, 26, 236, 57, 0, // Skip to: 19231
+/* 4403 */    MCD_OPC_Decode, 252, 18, 203, 1, // Opcode: VHSUBsv4i32
+/* 4408 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 4447
+/* 4414 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4417 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4432
+/* 4422 */    MCD_OPC_CheckPredicate, 26, 212, 57, 0, // Skip to: 19231
+/* 4427 */    MCD_OPC_Decode, 235, 29, 204, 1, // Opcode: VSUBLsv2i64
+/* 4432 */    MCD_OPC_FilterValue, 1, 202, 57, 0, // Skip to: 19231
+/* 4437 */    MCD_OPC_CheckPredicate, 26, 197, 57, 0, // Skip to: 19231
+/* 4442 */    MCD_OPC_Decode, 175, 22, 220, 1, // Opcode: VMLALslsv2i32
+/* 4447 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 4486
+/* 4453 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4456 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4471
+/* 4461 */    MCD_OPC_CheckPredicate, 26, 173, 57, 0, // Skip to: 19231
+/* 4466 */    MCD_OPC_Decode, 128, 19, 202, 1, // Opcode: VHSUBuv2i32
+/* 4471 */    MCD_OPC_FilterValue, 1, 163, 57, 0, // Skip to: 19231
+/* 4476 */    MCD_OPC_CheckPredicate, 26, 158, 57, 0, // Skip to: 19231
+/* 4481 */    MCD_OPC_Decode, 130, 19, 203, 1, // Opcode: VHSUBuv4i32
+/* 4486 */    MCD_OPC_FilterValue, 231, 3, 147, 57, 0, // Skip to: 19231
+/* 4492 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4495 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4510
+/* 4500 */    MCD_OPC_CheckPredicate, 26, 134, 57, 0, // Skip to: 19231
+/* 4505 */    MCD_OPC_Decode, 238, 29, 204, 1, // Opcode: VSUBLuv2i64
+/* 4510 */    MCD_OPC_FilterValue, 1, 124, 57, 0, // Skip to: 19231
+/* 4515 */    MCD_OPC_CheckPredicate, 26, 119, 57, 0, // Skip to: 19231
+/* 4520 */    MCD_OPC_Decode, 177, 22, 220, 1, // Opcode: VMLALsluv2i32
+/* 4525 */    MCD_OPC_FilterValue, 3, 143, 0, 0, // Skip to: 4673
+/* 4530 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 4533 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 4572
+/* 4539 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4542 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4557
+/* 4547 */    MCD_OPC_CheckPredicate, 26, 87, 57, 0, // Skip to: 19231
+/* 4552 */    MCD_OPC_Decode, 255, 16, 202, 1, // Opcode: VCGTsv2i32
+/* 4557 */    MCD_OPC_FilterValue, 1, 77, 57, 0, // Skip to: 19231
+/* 4562 */    MCD_OPC_CheckPredicate, 26, 72, 57, 0, // Skip to: 19231
+/* 4567 */    MCD_OPC_Decode, 129, 17, 203, 1, // Opcode: VCGTsv4i32
+/* 4572 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 4611
+/* 4578 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4581 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4596
+/* 4586 */    MCD_OPC_CheckPredicate, 26, 48, 57, 0, // Skip to: 19231
+/* 4591 */    MCD_OPC_Decode, 242, 29, 205, 1, // Opcode: VSUBWsv2i64
+/* 4596 */    MCD_OPC_FilterValue, 1, 38, 57, 0, // Skip to: 19231
+/* 4601 */    MCD_OPC_CheckPredicate, 26, 33, 57, 0, // Skip to: 19231
+/* 4606 */    MCD_OPC_Decode, 171, 24, 220, 1, // Opcode: VQDMLALslv2i32
+/* 4611 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 4650
+/* 4617 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4620 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4635
+/* 4625 */    MCD_OPC_CheckPredicate, 26, 9, 57, 0, // Skip to: 19231
+/* 4630 */    MCD_OPC_Decode, 133, 17, 202, 1, // Opcode: VCGTuv2i32
+/* 4635 */    MCD_OPC_FilterValue, 1, 255, 56, 0, // Skip to: 19231
+/* 4640 */    MCD_OPC_CheckPredicate, 26, 250, 56, 0, // Skip to: 19231
+/* 4645 */    MCD_OPC_Decode, 135, 17, 203, 1, // Opcode: VCGTuv4i32
+/* 4650 */    MCD_OPC_FilterValue, 231, 3, 239, 56, 0, // Skip to: 19231
+/* 4656 */    MCD_OPC_CheckPredicate, 26, 234, 56, 0, // Skip to: 19231
+/* 4661 */    MCD_OPC_CheckField, 6, 1, 0, 227, 56, 0, // Skip to: 19231
+/* 4668 */    MCD_OPC_Decode, 245, 29, 205, 1, // Opcode: VSUBWuv2i64
+/* 4673 */    MCD_OPC_FilterValue, 4, 159, 0, 0, // Skip to: 4837
+/* 4678 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 4681 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 4720
+/* 4687 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4690 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4705
+/* 4695 */    MCD_OPC_CheckPredicate, 26, 195, 56, 0, // Skip to: 19231
+/* 4700 */    MCD_OPC_Decode, 250, 26, 206, 1, // Opcode: VSHLsv2i32
+/* 4705 */    MCD_OPC_FilterValue, 1, 185, 56, 0, // Skip to: 19231
+/* 4710 */    MCD_OPC_CheckPredicate, 26, 180, 56, 0, // Skip to: 19231
+/* 4715 */    MCD_OPC_Decode, 253, 26, 207, 1, // Opcode: VSHLsv4i32
+/* 4720 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 4759
+/* 4726 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4729 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4744
+/* 4734 */    MCD_OPC_CheckPredicate, 26, 156, 56, 0, // Skip to: 19231
+/* 4739 */    MCD_OPC_Decode, 152, 16, 208, 1, // Opcode: VADDHNv2i32
+/* 4744 */    MCD_OPC_FilterValue, 1, 146, 56, 0, // Skip to: 19231
+/* 4749 */    MCD_OPC_CheckPredicate, 26, 141, 56, 0, // Skip to: 19231
+/* 4754 */    MCD_OPC_Decode, 225, 22, 218, 1, // Opcode: VMLSslv2i32
+/* 4759 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 4798
+/* 4765 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4768 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4783
+/* 4773 */    MCD_OPC_CheckPredicate, 26, 117, 56, 0, // Skip to: 19231
+/* 4778 */    MCD_OPC_Decode, 130, 27, 206, 1, // Opcode: VSHLuv2i32
+/* 4783 */    MCD_OPC_FilterValue, 1, 107, 56, 0, // Skip to: 19231
+/* 4788 */    MCD_OPC_CheckPredicate, 26, 102, 56, 0, // Skip to: 19231
+/* 4793 */    MCD_OPC_Decode, 133, 27, 207, 1, // Opcode: VSHLuv4i32
+/* 4798 */    MCD_OPC_FilterValue, 231, 3, 91, 56, 0, // Skip to: 19231
+/* 4804 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4807 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4822
+/* 4812 */    MCD_OPC_CheckPredicate, 26, 78, 56, 0, // Skip to: 19231
+/* 4817 */    MCD_OPC_Decode, 192, 25, 208, 1, // Opcode: VRADDHNv2i32
+/* 4822 */    MCD_OPC_FilterValue, 1, 68, 56, 0, // Skip to: 19231
+/* 4827 */    MCD_OPC_CheckPredicate, 26, 63, 56, 0, // Skip to: 19231
+/* 4832 */    MCD_OPC_Decode, 227, 22, 219, 1, // Opcode: VMLSslv4i32
+/* 4837 */    MCD_OPC_FilterValue, 5, 159, 0, 0, // Skip to: 5001
+/* 4842 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 4845 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 4884
+/* 4851 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4854 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4869
+/* 4859 */    MCD_OPC_CheckPredicate, 26, 31, 56, 0, // Skip to: 19231
+/* 4864 */    MCD_OPC_Decode, 148, 26, 206, 1, // Opcode: VRSHLsv2i32
+/* 4869 */    MCD_OPC_FilterValue, 1, 21, 56, 0, // Skip to: 19231
+/* 4874 */    MCD_OPC_CheckPredicate, 26, 16, 56, 0, // Skip to: 19231
+/* 4879 */    MCD_OPC_Decode, 151, 26, 207, 1, // Opcode: VRSHLsv4i32
+/* 4884 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 4923
+/* 4890 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4893 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4908
+/* 4898 */    MCD_OPC_CheckPredicate, 26, 248, 55, 0, // Skip to: 19231
+/* 4903 */    MCD_OPC_Decode, 217, 15, 209, 1, // Opcode: VABALsv2i64
+/* 4908 */    MCD_OPC_FilterValue, 1, 238, 55, 0, // Skip to: 19231
+/* 4913 */    MCD_OPC_CheckPredicate, 26, 233, 55, 0, // Skip to: 19231
+/* 4918 */    MCD_OPC_Decode, 221, 22, 218, 1, // Opcode: VMLSslfd
+/* 4923 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 4962
+/* 4929 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4932 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4947
+/* 4937 */    MCD_OPC_CheckPredicate, 26, 209, 55, 0, // Skip to: 19231
+/* 4942 */    MCD_OPC_Decode, 156, 26, 206, 1, // Opcode: VRSHLuv2i32
+/* 4947 */    MCD_OPC_FilterValue, 1, 199, 55, 0, // Skip to: 19231
+/* 4952 */    MCD_OPC_CheckPredicate, 26, 194, 55, 0, // Skip to: 19231
+/* 4957 */    MCD_OPC_Decode, 159, 26, 207, 1, // Opcode: VRSHLuv4i32
+/* 4962 */    MCD_OPC_FilterValue, 231, 3, 183, 55, 0, // Skip to: 19231
+/* 4968 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 4971 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4986
+/* 4976 */    MCD_OPC_CheckPredicate, 26, 170, 55, 0, // Skip to: 19231
+/* 4981 */    MCD_OPC_Decode, 220, 15, 209, 1, // Opcode: VABALuv2i64
+/* 4986 */    MCD_OPC_FilterValue, 1, 160, 55, 0, // Skip to: 19231
+/* 4991 */    MCD_OPC_CheckPredicate, 26, 155, 55, 0, // Skip to: 19231
+/* 4996 */    MCD_OPC_Decode, 222, 22, 219, 1, // Opcode: VMLSslfq
+/* 5001 */    MCD_OPC_FilterValue, 6, 159, 0, 0, // Skip to: 5165
+/* 5006 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5009 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 5048
+/* 5015 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5018 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5033
+/* 5023 */    MCD_OPC_CheckPredicate, 26, 123, 55, 0, // Skip to: 19231
+/* 5028 */    MCD_OPC_Decode, 146, 22, 202, 1, // Opcode: VMAXsv2i32
+/* 5033 */    MCD_OPC_FilterValue, 1, 113, 55, 0, // Skip to: 19231
+/* 5038 */    MCD_OPC_CheckPredicate, 26, 108, 55, 0, // Skip to: 19231
+/* 5043 */    MCD_OPC_Decode, 148, 22, 203, 1, // Opcode: VMAXsv4i32
+/* 5048 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 5087
+/* 5054 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5057 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5072
+/* 5062 */    MCD_OPC_CheckPredicate, 26, 84, 55, 0, // Skip to: 19231
+/* 5067 */    MCD_OPC_Decode, 232, 29, 208, 1, // Opcode: VSUBHNv2i32
+/* 5072 */    MCD_OPC_FilterValue, 1, 74, 55, 0, // Skip to: 19231
+/* 5077 */    MCD_OPC_CheckPredicate, 26, 69, 55, 0, // Skip to: 19231
+/* 5082 */    MCD_OPC_Decode, 206, 22, 220, 1, // Opcode: VMLSLslsv2i32
+/* 5087 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 5126
+/* 5093 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5096 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5111
+/* 5101 */    MCD_OPC_CheckPredicate, 26, 45, 55, 0, // Skip to: 19231
+/* 5106 */    MCD_OPC_Decode, 152, 22, 202, 1, // Opcode: VMAXuv2i32
+/* 5111 */    MCD_OPC_FilterValue, 1, 35, 55, 0, // Skip to: 19231
+/* 5116 */    MCD_OPC_CheckPredicate, 26, 30, 55, 0, // Skip to: 19231
+/* 5121 */    MCD_OPC_Decode, 154, 22, 203, 1, // Opcode: VMAXuv4i32
+/* 5126 */    MCD_OPC_FilterValue, 231, 3, 19, 55, 0, // Skip to: 19231
+/* 5132 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5135 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5150
+/* 5140 */    MCD_OPC_CheckPredicate, 26, 6, 55, 0, // Skip to: 19231
+/* 5145 */    MCD_OPC_Decode, 207, 26, 208, 1, // Opcode: VRSUBHNv2i32
+/* 5150 */    MCD_OPC_FilterValue, 1, 252, 54, 0, // Skip to: 19231
+/* 5155 */    MCD_OPC_CheckPredicate, 26, 247, 54, 0, // Skip to: 19231
+/* 5160 */    MCD_OPC_Decode, 208, 22, 220, 1, // Opcode: VMLSLsluv2i32
+/* 5165 */    MCD_OPC_FilterValue, 7, 143, 0, 0, // Skip to: 5313
+/* 5170 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5173 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 5212
+/* 5179 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5182 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5197
+/* 5187 */    MCD_OPC_CheckPredicate, 26, 215, 54, 0, // Skip to: 19231
+/* 5192 */    MCD_OPC_Decode, 246, 15, 202, 1, // Opcode: VABDsv2i32
+/* 5197 */    MCD_OPC_FilterValue, 1, 205, 54, 0, // Skip to: 19231
+/* 5202 */    MCD_OPC_CheckPredicate, 26, 200, 54, 0, // Skip to: 19231
+/* 5207 */    MCD_OPC_Decode, 248, 15, 203, 1, // Opcode: VABDsv4i32
+/* 5212 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 5251
+/* 5218 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5221 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5236
+/* 5226 */    MCD_OPC_CheckPredicate, 26, 176, 54, 0, // Skip to: 19231
+/* 5231 */    MCD_OPC_Decode, 235, 15, 204, 1, // Opcode: VABDLsv2i64
+/* 5236 */    MCD_OPC_FilterValue, 1, 166, 54, 0, // Skip to: 19231
+/* 5241 */    MCD_OPC_CheckPredicate, 26, 161, 54, 0, // Skip to: 19231
+/* 5246 */    MCD_OPC_Decode, 175, 24, 220, 1, // Opcode: VQDMLSLslv2i32
+/* 5251 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 5290
+/* 5257 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5260 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5275
+/* 5265 */    MCD_OPC_CheckPredicate, 26, 137, 54, 0, // Skip to: 19231
+/* 5270 */    MCD_OPC_Decode, 252, 15, 202, 1, // Opcode: VABDuv2i32
+/* 5275 */    MCD_OPC_FilterValue, 1, 127, 54, 0, // Skip to: 19231
+/* 5280 */    MCD_OPC_CheckPredicate, 26, 122, 54, 0, // Skip to: 19231
+/* 5285 */    MCD_OPC_Decode, 254, 15, 203, 1, // Opcode: VABDuv4i32
+/* 5290 */    MCD_OPC_FilterValue, 231, 3, 111, 54, 0, // Skip to: 19231
+/* 5296 */    MCD_OPC_CheckPredicate, 26, 106, 54, 0, // Skip to: 19231
+/* 5301 */    MCD_OPC_CheckField, 6, 1, 0, 99, 54, 0, // Skip to: 19231
+/* 5308 */    MCD_OPC_Decode, 238, 15, 204, 1, // Opcode: VABDLuv2i64
+/* 5313 */    MCD_OPC_FilterValue, 8, 159, 0, 0, // Skip to: 5477
+/* 5318 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5321 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 5360
+/* 5327 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5330 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5345
+/* 5335 */    MCD_OPC_CheckPredicate, 26, 67, 54, 0, // Skip to: 19231
+/* 5340 */    MCD_OPC_Decode, 174, 16, 202, 1, // Opcode: VADDv2i32
+/* 5345 */    MCD_OPC_FilterValue, 1, 57, 54, 0, // Skip to: 19231
+/* 5350 */    MCD_OPC_CheckPredicate, 26, 52, 54, 0, // Skip to: 19231
+/* 5355 */    MCD_OPC_Decode, 177, 16, 203, 1, // Opcode: VADDv4i32
+/* 5360 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 5399
+/* 5366 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5369 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5384
+/* 5374 */    MCD_OPC_CheckPredicate, 26, 28, 54, 0, // Skip to: 19231
+/* 5379 */    MCD_OPC_Decode, 179, 22, 209, 1, // Opcode: VMLALsv2i64
+/* 5384 */    MCD_OPC_FilterValue, 1, 18, 54, 0, // Skip to: 19231
+/* 5389 */    MCD_OPC_CheckPredicate, 26, 13, 54, 0, // Skip to: 19231
+/* 5394 */    MCD_OPC_Decode, 186, 23, 221, 1, // Opcode: VMULslv2i32
+/* 5399 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 5438
+/* 5405 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5408 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5423
+/* 5413 */    MCD_OPC_CheckPredicate, 26, 245, 53, 0, // Skip to: 19231
+/* 5418 */    MCD_OPC_Decode, 254, 29, 202, 1, // Opcode: VSUBv2i32
+/* 5423 */    MCD_OPC_FilterValue, 1, 235, 53, 0, // Skip to: 19231
+/* 5428 */    MCD_OPC_CheckPredicate, 26, 230, 53, 0, // Skip to: 19231
+/* 5433 */    MCD_OPC_Decode, 129, 30, 203, 1, // Opcode: VSUBv4i32
+/* 5438 */    MCD_OPC_FilterValue, 231, 3, 219, 53, 0, // Skip to: 19231
+/* 5444 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5447 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5462
+/* 5452 */    MCD_OPC_CheckPredicate, 26, 206, 53, 0, // Skip to: 19231
+/* 5457 */    MCD_OPC_Decode, 182, 22, 209, 1, // Opcode: VMLALuv2i64
+/* 5462 */    MCD_OPC_FilterValue, 1, 196, 53, 0, // Skip to: 19231
+/* 5467 */    MCD_OPC_CheckPredicate, 26, 191, 53, 0, // Skip to: 19231
+/* 5472 */    MCD_OPC_Decode, 188, 23, 222, 1, // Opcode: VMULslv4i32
+/* 5477 */    MCD_OPC_FilterValue, 9, 143, 0, 0, // Skip to: 5625
+/* 5482 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5485 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 5524
+/* 5491 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5494 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5509
+/* 5499 */    MCD_OPC_CheckPredicate, 26, 159, 53, 0, // Skip to: 19231
+/* 5504 */    MCD_OPC_Decode, 199, 22, 210, 1, // Opcode: VMLAv2i32
+/* 5509 */    MCD_OPC_FilterValue, 1, 149, 53, 0, // Skip to: 19231
+/* 5514 */    MCD_OPC_CheckPredicate, 26, 144, 53, 0, // Skip to: 19231
+/* 5519 */    MCD_OPC_Decode, 201, 22, 211, 1, // Opcode: VMLAv4i32
+/* 5524 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 5563
+/* 5530 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5533 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5548
+/* 5538 */    MCD_OPC_CheckPredicate, 26, 120, 53, 0, // Skip to: 19231
+/* 5543 */    MCD_OPC_Decode, 173, 24, 209, 1, // Opcode: VQDMLALv2i64
+/* 5548 */    MCD_OPC_FilterValue, 1, 110, 53, 0, // Skip to: 19231
+/* 5553 */    MCD_OPC_CheckPredicate, 26, 105, 53, 0, // Skip to: 19231
+/* 5558 */    MCD_OPC_Decode, 182, 23, 221, 1, // Opcode: VMULslfd
+/* 5563 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 5602
+/* 5569 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5572 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5587
+/* 5577 */    MCD_OPC_CheckPredicate, 26, 81, 53, 0, // Skip to: 19231
+/* 5582 */    MCD_OPC_Decode, 230, 22, 210, 1, // Opcode: VMLSv2i32
+/* 5587 */    MCD_OPC_FilterValue, 1, 71, 53, 0, // Skip to: 19231
+/* 5592 */    MCD_OPC_CheckPredicate, 26, 66, 53, 0, // Skip to: 19231
+/* 5597 */    MCD_OPC_Decode, 232, 22, 211, 1, // Opcode: VMLSv4i32
+/* 5602 */    MCD_OPC_FilterValue, 231, 3, 55, 53, 0, // Skip to: 19231
+/* 5608 */    MCD_OPC_CheckPredicate, 26, 50, 53, 0, // Skip to: 19231
+/* 5613 */    MCD_OPC_CheckField, 6, 1, 1, 43, 53, 0, // Skip to: 19231
+/* 5620 */    MCD_OPC_Decode, 183, 23, 222, 1, // Opcode: VMULslfq
+/* 5625 */    MCD_OPC_FilterValue, 10, 127, 0, 0, // Skip to: 5757
+/* 5630 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5633 */    MCD_OPC_FilterValue, 228, 3, 17, 0, 0, // Skip to: 5656
+/* 5639 */    MCD_OPC_CheckPredicate, 26, 19, 53, 0, // Skip to: 19231
+/* 5644 */    MCD_OPC_CheckField, 6, 1, 0, 12, 53, 0, // Skip to: 19231
+/* 5651 */    MCD_OPC_Decode, 136, 24, 202, 1, // Opcode: VPMAXs32
+/* 5656 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 5695
+/* 5662 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5665 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5680
+/* 5670 */    MCD_OPC_CheckPredicate, 26, 244, 52, 0, // Skip to: 19231
+/* 5675 */    MCD_OPC_Decode, 210, 22, 209, 1, // Opcode: VMLSLsv2i64
+/* 5680 */    MCD_OPC_FilterValue, 1, 234, 52, 0, // Skip to: 19231
+/* 5685 */    MCD_OPC_CheckPredicate, 26, 229, 52, 0, // Skip to: 19231
+/* 5690 */    MCD_OPC_Decode, 165, 23, 223, 1, // Opcode: VMULLslsv2i32
+/* 5695 */    MCD_OPC_FilterValue, 230, 3, 17, 0, 0, // Skip to: 5718
+/* 5701 */    MCD_OPC_CheckPredicate, 26, 213, 52, 0, // Skip to: 19231
+/* 5706 */    MCD_OPC_CheckField, 6, 1, 0, 206, 52, 0, // Skip to: 19231
+/* 5713 */    MCD_OPC_Decode, 139, 24, 202, 1, // Opcode: VPMAXu32
+/* 5718 */    MCD_OPC_FilterValue, 231, 3, 195, 52, 0, // Skip to: 19231
+/* 5724 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5727 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5742
+/* 5732 */    MCD_OPC_CheckPredicate, 26, 182, 52, 0, // Skip to: 19231
+/* 5737 */    MCD_OPC_Decode, 213, 22, 209, 1, // Opcode: VMLSLuv2i64
+/* 5742 */    MCD_OPC_FilterValue, 1, 172, 52, 0, // Skip to: 19231
+/* 5747 */    MCD_OPC_CheckPredicate, 26, 167, 52, 0, // Skip to: 19231
+/* 5752 */    MCD_OPC_Decode, 167, 23, 223, 1, // Opcode: VMULLsluv2i32
+/* 5757 */    MCD_OPC_FilterValue, 11, 120, 0, 0, // Skip to: 5882
+/* 5762 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5765 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 5804
+/* 5771 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5774 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5789
+/* 5779 */    MCD_OPC_CheckPredicate, 26, 135, 52, 0, // Skip to: 19231
+/* 5784 */    MCD_OPC_Decode, 183, 24, 202, 1, // Opcode: VQDMULHv2i32
+/* 5789 */    MCD_OPC_FilterValue, 1, 125, 52, 0, // Skip to: 19231
+/* 5794 */    MCD_OPC_CheckPredicate, 26, 120, 52, 0, // Skip to: 19231
+/* 5799 */    MCD_OPC_Decode, 185, 24, 203, 1, // Opcode: VQDMULHv4i32
+/* 5804 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 5843
+/* 5810 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5813 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5828
+/* 5818 */    MCD_OPC_CheckPredicate, 26, 96, 52, 0, // Skip to: 19231
+/* 5823 */    MCD_OPC_Decode, 177, 24, 209, 1, // Opcode: VQDMLSLv2i64
+/* 5828 */    MCD_OPC_FilterValue, 1, 86, 52, 0, // Skip to: 19231
+/* 5833 */    MCD_OPC_CheckPredicate, 26, 81, 52, 0, // Skip to: 19231
+/* 5838 */    MCD_OPC_Decode, 187, 24, 223, 1, // Opcode: VQDMULLslv2i32
+/* 5843 */    MCD_OPC_FilterValue, 230, 3, 70, 52, 0, // Skip to: 19231
+/* 5849 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5852 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 5867
+/* 5857 */    MCD_OPC_CheckPredicate, 26, 57, 52, 0, // Skip to: 19231
+/* 5862 */    MCD_OPC_Decode, 226, 24, 202, 1, // Opcode: VQRDMULHv2i32
+/* 5867 */    MCD_OPC_FilterValue, 1, 47, 52, 0, // Skip to: 19231
+/* 5872 */    MCD_OPC_CheckPredicate, 26, 42, 52, 0, // Skip to: 19231
+/* 5877 */    MCD_OPC_Decode, 228, 24, 203, 1, // Opcode: VQRDMULHv4i32
+/* 5882 */    MCD_OPC_FilterValue, 12, 83, 0, 0, // Skip to: 5970
+/* 5887 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5890 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5930
+/* 5895 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5898 */    MCD_OPC_FilterValue, 229, 3, 10, 0, 0, // Skip to: 5914
+/* 5904 */    MCD_OPC_CheckPredicate, 26, 10, 52, 0, // Skip to: 19231
+/* 5909 */    MCD_OPC_Decode, 169, 23, 204, 1, // Opcode: VMULLsv2i64
+/* 5914 */    MCD_OPC_FilterValue, 231, 3, 255, 51, 0, // Skip to: 19231
+/* 5920 */    MCD_OPC_CheckPredicate, 26, 250, 51, 0, // Skip to: 19231
+/* 5925 */    MCD_OPC_Decode, 172, 23, 204, 1, // Opcode: VMULLuv2i64
+/* 5930 */    MCD_OPC_FilterValue, 1, 240, 51, 0, // Skip to: 19231
+/* 5935 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5938 */    MCD_OPC_FilterValue, 229, 3, 10, 0, 0, // Skip to: 5954
+/* 5944 */    MCD_OPC_CheckPredicate, 26, 226, 51, 0, // Skip to: 19231
+/* 5949 */    MCD_OPC_Decode, 179, 24, 221, 1, // Opcode: VQDMULHslv2i32
+/* 5954 */    MCD_OPC_FilterValue, 231, 3, 215, 51, 0, // Skip to: 19231
+/* 5960 */    MCD_OPC_CheckPredicate, 26, 210, 51, 0, // Skip to: 19231
+/* 5965 */    MCD_OPC_Decode, 181, 24, 222, 1, // Opcode: VQDMULHslv4i32
+/* 5970 */    MCD_OPC_FilterValue, 13, 143, 0, 0, // Skip to: 6118
+/* 5975 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 5978 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 6017
+/* 5984 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 5987 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6002
+/* 5992 */    MCD_OPC_CheckPredicate, 26, 178, 51, 0, // Skip to: 19231
+/* 5997 */    MCD_OPC_Decode, 248, 29, 202, 1, // Opcode: VSUBfd
+/* 6002 */    MCD_OPC_FilterValue, 1, 168, 51, 0, // Skip to: 19231
+/* 6007 */    MCD_OPC_CheckPredicate, 26, 163, 51, 0, // Skip to: 19231
+/* 6012 */    MCD_OPC_Decode, 249, 29, 203, 1, // Opcode: VSUBfq
+/* 6017 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 6056
+/* 6023 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6026 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6041
+/* 6031 */    MCD_OPC_CheckPredicate, 26, 139, 51, 0, // Skip to: 19231
+/* 6036 */    MCD_OPC_Decode, 189, 24, 204, 1, // Opcode: VQDMULLv2i64
+/* 6041 */    MCD_OPC_FilterValue, 1, 129, 51, 0, // Skip to: 19231
+/* 6046 */    MCD_OPC_CheckPredicate, 26, 124, 51, 0, // Skip to: 19231
+/* 6051 */    MCD_OPC_Decode, 222, 24, 221, 1, // Opcode: VQRDMULHslv2i32
+/* 6056 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 6095
+/* 6062 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6065 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6080
+/* 6070 */    MCD_OPC_CheckPredicate, 26, 100, 51, 0, // Skip to: 19231
+/* 6075 */    MCD_OPC_Decode, 241, 15, 202, 1, // Opcode: VABDfd
+/* 6080 */    MCD_OPC_FilterValue, 1, 90, 51, 0, // Skip to: 19231
+/* 6085 */    MCD_OPC_CheckPredicate, 26, 85, 51, 0, // Skip to: 19231
+/* 6090 */    MCD_OPC_Decode, 242, 15, 203, 1, // Opcode: VABDfq
+/* 6095 */    MCD_OPC_FilterValue, 231, 3, 74, 51, 0, // Skip to: 19231
+/* 6101 */    MCD_OPC_CheckPredicate, 26, 69, 51, 0, // Skip to: 19231
+/* 6106 */    MCD_OPC_CheckField, 6, 1, 1, 62, 51, 0, // Skip to: 19231
+/* 6113 */    MCD_OPC_Decode, 224, 24, 222, 1, // Opcode: VQRDMULHslv4i32
+/* 6118 */    MCD_OPC_FilterValue, 14, 104, 0, 0, // Skip to: 6227
+/* 6123 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 6126 */    MCD_OPC_FilterValue, 229, 3, 33, 0, 0, // Skip to: 6165
+/* 6132 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6135 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6150
+/* 6140 */    MCD_OPC_CheckPredicate, 29, 30, 51, 0, // Skip to: 19231
+/* 6145 */    MCD_OPC_Decode, 163, 23, 204, 1, // Opcode: VMULLp64
+/* 6150 */    MCD_OPC_FilterValue, 1, 20, 51, 0, // Skip to: 19231
+/* 6155 */    MCD_OPC_CheckPredicate, 28, 15, 51, 0, // Skip to: 19231
+/* 6160 */    MCD_OPC_Decode, 206, 24, 218, 1, // Opcode: VQRDMLAHslv2i32
+/* 6165 */    MCD_OPC_FilterValue, 230, 3, 33, 0, 0, // Skip to: 6204
+/* 6171 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6174 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6189
+/* 6179 */    MCD_OPC_CheckPredicate, 26, 247, 50, 0, // Skip to: 19231
+/* 6184 */    MCD_OPC_Decode, 250, 16, 202, 1, // Opcode: VCGTfd
+/* 6189 */    MCD_OPC_FilterValue, 1, 237, 50, 0, // Skip to: 19231
+/* 6194 */    MCD_OPC_CheckPredicate, 26, 232, 50, 0, // Skip to: 19231
+/* 6199 */    MCD_OPC_Decode, 251, 16, 203, 1, // Opcode: VCGTfq
+/* 6204 */    MCD_OPC_FilterValue, 231, 3, 221, 50, 0, // Skip to: 19231
+/* 6210 */    MCD_OPC_CheckPredicate, 28, 216, 50, 0, // Skip to: 19231
+/* 6215 */    MCD_OPC_CheckField, 6, 1, 1, 209, 50, 0, // Skip to: 19231
+/* 6222 */    MCD_OPC_Decode, 208, 24, 219, 1, // Opcode: VQRDMLAHslv4i32
+/* 6227 */    MCD_OPC_FilterValue, 15, 199, 50, 0, // Skip to: 19231
+/* 6232 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 6235 */    MCD_OPC_FilterValue, 228, 3, 33, 0, 0, // Skip to: 6274
+/* 6241 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6244 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6259
+/* 6249 */    MCD_OPC_CheckPredicate, 26, 177, 50, 0, // Skip to: 19231
+/* 6254 */    MCD_OPC_Decode, 157, 22, 202, 1, // Opcode: VMINfd
+/* 6259 */    MCD_OPC_FilterValue, 1, 167, 50, 0, // Skip to: 19231
+/* 6264 */    MCD_OPC_CheckPredicate, 26, 162, 50, 0, // Skip to: 19231
+/* 6269 */    MCD_OPC_Decode, 158, 22, 203, 1, // Opcode: VMINfq
+/* 6274 */    MCD_OPC_FilterValue, 229, 3, 17, 0, 0, // Skip to: 6297
+/* 6280 */    MCD_OPC_CheckPredicate, 28, 146, 50, 0, // Skip to: 19231
+/* 6285 */    MCD_OPC_CheckField, 6, 1, 1, 139, 50, 0, // Skip to: 19231
+/* 6292 */    MCD_OPC_Decode, 214, 24, 218, 1, // Opcode: VQRDMLSHslv2i32
+/* 6297 */    MCD_OPC_FilterValue, 230, 3, 17, 0, 0, // Skip to: 6320
+/* 6303 */    MCD_OPC_CheckPredicate, 26, 123, 50, 0, // Skip to: 19231
+/* 6308 */    MCD_OPC_CheckField, 6, 1, 0, 116, 50, 0, // Skip to: 19231
+/* 6315 */    MCD_OPC_Decode, 141, 24, 202, 1, // Opcode: VPMINf
+/* 6320 */    MCD_OPC_FilterValue, 231, 3, 105, 50, 0, // Skip to: 19231
+/* 6326 */    MCD_OPC_CheckPredicate, 28, 100, 50, 0, // Skip to: 19231
+/* 6331 */    MCD_OPC_CheckField, 6, 1, 1, 93, 50, 0, // Skip to: 19231
+/* 6338 */    MCD_OPC_Decode, 216, 24, 219, 1, // Opcode: VQRDMLSHslv4i32
+/* 6343 */    MCD_OPC_FilterValue, 3, 83, 50, 0, // Skip to: 19231
+/* 6348 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 6351 */    MCD_OPC_FilterValue, 228, 3, 193, 0, 0, // Skip to: 6550
+/* 6357 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 6360 */    MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 6398
+/* 6365 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6368 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6383
+/* 6373 */    MCD_OPC_CheckPredicate, 26, 53, 50, 0, // Skip to: 19231
+/* 6378 */    MCD_OPC_Decode, 249, 26, 206, 1, // Opcode: VSHLsv1i64
+/* 6383 */    MCD_OPC_FilterValue, 1, 43, 50, 0, // Skip to: 19231
+/* 6388 */    MCD_OPC_CheckPredicate, 26, 38, 50, 0, // Skip to: 19231
+/* 6393 */    MCD_OPC_Decode, 251, 26, 207, 1, // Opcode: VSHLsv2i64
+/* 6398 */    MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 6436
+/* 6403 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6406 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6421
+/* 6411 */    MCD_OPC_CheckPredicate, 26, 15, 50, 0, // Skip to: 19231
+/* 6416 */    MCD_OPC_Decode, 147, 26, 206, 1, // Opcode: VRSHLsv1i64
+/* 6421 */    MCD_OPC_FilterValue, 1, 5, 50, 0, // Skip to: 19231
+/* 6426 */    MCD_OPC_CheckPredicate, 26, 0, 50, 0, // Skip to: 19231
+/* 6431 */    MCD_OPC_Decode, 149, 26, 207, 1, // Opcode: VRSHLsv2i64
+/* 6436 */    MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 6474
+/* 6441 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6444 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6459
+/* 6449 */    MCD_OPC_CheckPredicate, 26, 233, 49, 0, // Skip to: 19231
+/* 6454 */    MCD_OPC_Decode, 173, 16, 202, 1, // Opcode: VADDv1i64
+/* 6459 */    MCD_OPC_FilterValue, 1, 223, 49, 0, // Skip to: 19231
+/* 6464 */    MCD_OPC_CheckPredicate, 26, 218, 49, 0, // Skip to: 19231
+/* 6469 */    MCD_OPC_Decode, 175, 16, 203, 1, // Opcode: VADDv2i64
+/* 6474 */    MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 6512
+/* 6479 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6482 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6497
+/* 6487 */    MCD_OPC_CheckPredicate, 27, 195, 49, 0, // Skip to: 19231
+/* 6492 */    MCD_OPC_Decode, 250, 29, 202, 1, // Opcode: VSUBhd
+/* 6497 */    MCD_OPC_FilterValue, 1, 185, 49, 0, // Skip to: 19231
+/* 6502 */    MCD_OPC_CheckPredicate, 27, 180, 49, 0, // Skip to: 19231
+/* 6507 */    MCD_OPC_Decode, 251, 29, 203, 1, // Opcode: VSUBhq
+/* 6512 */    MCD_OPC_FilterValue, 15, 170, 49, 0, // Skip to: 19231
+/* 6517 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6520 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6535
+/* 6525 */    MCD_OPC_CheckPredicate, 27, 157, 49, 0, // Skip to: 19231
+/* 6530 */    MCD_OPC_Decode, 159, 22, 202, 1, // Opcode: VMINhd
+/* 6535 */    MCD_OPC_FilterValue, 1, 147, 49, 0, // Skip to: 19231
+/* 6540 */    MCD_OPC_CheckPredicate, 27, 142, 49, 0, // Skip to: 19231
+/* 6545 */    MCD_OPC_Decode, 160, 22, 203, 1, // Opcode: VMINhq
+/* 6550 */    MCD_OPC_FilterValue, 229, 3, 126, 0, 0, // Skip to: 6682
+/* 6556 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6559 */    MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 6616
+/* 6564 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 6567 */    MCD_OPC_FilterValue, 0, 115, 49, 0, // Skip to: 19231
+/* 6572 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6589
+/* 6577 */    MCD_OPC_CheckField, 8, 2, 0, 5, 0, 0, // Skip to: 6589
+/* 6584 */    MCD_OPC_Decode, 192, 18, 224, 1, // Opcode: VEXTd32
+/* 6589 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6606
+/* 6594 */    MCD_OPC_CheckField, 8, 1, 0, 5, 0, 0, // Skip to: 6606
+/* 6601 */    MCD_OPC_Decode, 191, 18, 225, 1, // Opcode: VEXTd16
+/* 6606 */    MCD_OPC_CheckPredicate, 26, 76, 49, 0, // Skip to: 19231
+/* 6611 */    MCD_OPC_Decode, 193, 18, 226, 1, // Opcode: VEXTd8
+/* 6616 */    MCD_OPC_FilterValue, 1, 66, 49, 0, // Skip to: 19231
+/* 6621 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6638
+/* 6626 */    MCD_OPC_CheckField, 8, 3, 0, 5, 0, 0, // Skip to: 6638
+/* 6633 */    MCD_OPC_Decode, 196, 18, 227, 1, // Opcode: VEXTq64
+/* 6638 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6655
+/* 6643 */    MCD_OPC_CheckField, 8, 2, 0, 5, 0, 0, // Skip to: 6655
+/* 6650 */    MCD_OPC_Decode, 195, 18, 228, 1, // Opcode: VEXTq32
+/* 6655 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6672
+/* 6660 */    MCD_OPC_CheckField, 8, 1, 0, 5, 0, 0, // Skip to: 6672
+/* 6667 */    MCD_OPC_Decode, 194, 18, 229, 1, // Opcode: VEXTq16
+/* 6672 */    MCD_OPC_CheckPredicate, 26, 10, 49, 0, // Skip to: 19231
+/* 6677 */    MCD_OPC_Decode, 197, 18, 230, 1, // Opcode: VEXTq8
+/* 6682 */    MCD_OPC_FilterValue, 230, 3, 215, 0, 0, // Skip to: 6903
+/* 6688 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 6691 */    MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 6729
+/* 6696 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6699 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6714
+/* 6704 */    MCD_OPC_CheckPredicate, 26, 234, 48, 0, // Skip to: 19231
+/* 6709 */    MCD_OPC_Decode, 129, 27, 206, 1, // Opcode: VSHLuv1i64
+/* 6714 */    MCD_OPC_FilterValue, 1, 224, 48, 0, // Skip to: 19231
+/* 6719 */    MCD_OPC_CheckPredicate, 26, 219, 48, 0, // Skip to: 19231
+/* 6724 */    MCD_OPC_Decode, 131, 27, 207, 1, // Opcode: VSHLuv2i64
+/* 6729 */    MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 6767
+/* 6734 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6737 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6752
+/* 6742 */    MCD_OPC_CheckPredicate, 26, 196, 48, 0, // Skip to: 19231
+/* 6747 */    MCD_OPC_Decode, 155, 26, 206, 1, // Opcode: VRSHLuv1i64
+/* 6752 */    MCD_OPC_FilterValue, 1, 186, 48, 0, // Skip to: 19231
+/* 6757 */    MCD_OPC_CheckPredicate, 26, 181, 48, 0, // Skip to: 19231
+/* 6762 */    MCD_OPC_Decode, 157, 26, 207, 1, // Opcode: VRSHLuv2i64
+/* 6767 */    MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 6805
+/* 6772 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6775 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6790
+/* 6780 */    MCD_OPC_CheckPredicate, 26, 158, 48, 0, // Skip to: 19231
+/* 6785 */    MCD_OPC_Decode, 253, 29, 202, 1, // Opcode: VSUBv1i64
+/* 6790 */    MCD_OPC_FilterValue, 1, 148, 48, 0, // Skip to: 19231
+/* 6795 */    MCD_OPC_CheckPredicate, 26, 143, 48, 0, // Skip to: 19231
+/* 6800 */    MCD_OPC_Decode, 255, 29, 203, 1, // Opcode: VSUBv2i64
+/* 6805 */    MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 6843
+/* 6810 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6813 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6828
+/* 6818 */    MCD_OPC_CheckPredicate, 27, 120, 48, 0, // Skip to: 19231
+/* 6823 */    MCD_OPC_Decode, 243, 15, 202, 1, // Opcode: VABDhd
+/* 6828 */    MCD_OPC_FilterValue, 1, 110, 48, 0, // Skip to: 19231
+/* 6833 */    MCD_OPC_CheckPredicate, 27, 105, 48, 0, // Skip to: 19231
+/* 6838 */    MCD_OPC_Decode, 244, 15, 203, 1, // Opcode: VABDhq
+/* 6843 */    MCD_OPC_FilterValue, 14, 33, 0, 0, // Skip to: 6881
+/* 6848 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 6851 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6866
+/* 6856 */    MCD_OPC_CheckPredicate, 27, 82, 48, 0, // Skip to: 19231
+/* 6861 */    MCD_OPC_Decode, 252, 16, 202, 1, // Opcode: VCGThd
+/* 6866 */    MCD_OPC_FilterValue, 1, 72, 48, 0, // Skip to: 19231
+/* 6871 */    MCD_OPC_CheckPredicate, 27, 67, 48, 0, // Skip to: 19231
+/* 6876 */    MCD_OPC_Decode, 253, 16, 203, 1, // Opcode: VCGThq
+/* 6881 */    MCD_OPC_FilterValue, 15, 57, 48, 0, // Skip to: 19231
+/* 6886 */    MCD_OPC_CheckPredicate, 27, 52, 48, 0, // Skip to: 19231
+/* 6891 */    MCD_OPC_CheckField, 6, 1, 0, 45, 48, 0, // Skip to: 19231
+/* 6898 */    MCD_OPC_Decode, 142, 24, 202, 1, // Opcode: VPMINh
+/* 6903 */    MCD_OPC_FilterValue, 231, 3, 34, 48, 0, // Skip to: 19231
+/* 6909 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 6912 */    MCD_OPC_FilterValue, 0, 13, 2, 0, // Skip to: 7442
+/* 6917 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 6920 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 6988
+/* 6925 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 6928 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 6943
+/* 6933 */    MCD_OPC_CheckPredicate, 26, 5, 48, 0, // Skip to: 19231
+/* 6938 */    MCD_OPC_Decode, 213, 25, 231, 1, // Opcode: VREV64d8
+/* 6943 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6958
+/* 6948 */    MCD_OPC_CheckPredicate, 26, 246, 47, 0, // Skip to: 19231
+/* 6953 */    MCD_OPC_Decode, 216, 25, 232, 1, // Opcode: VREV64q8
+/* 6958 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 6973
+/* 6963 */    MCD_OPC_CheckPredicate, 26, 231, 47, 0, // Skip to: 19231
+/* 6968 */    MCD_OPC_Decode, 208, 25, 231, 1, // Opcode: VREV32d8
+/* 6973 */    MCD_OPC_FilterValue, 3, 221, 47, 0, // Skip to: 19231
+/* 6978 */    MCD_OPC_CheckPredicate, 26, 216, 47, 0, // Skip to: 19231
+/* 6983 */    MCD_OPC_Decode, 210, 25, 232, 1, // Opcode: VREV32q8
+/* 6988 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 7056
+/* 6993 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 6996 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7011
+/* 7001 */    MCD_OPC_CheckPredicate, 26, 193, 47, 0, // Skip to: 19231
+/* 7006 */    MCD_OPC_Decode, 147, 17, 231, 1, // Opcode: VCGTzv8i8
+/* 7011 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7026
+/* 7016 */    MCD_OPC_CheckPredicate, 26, 178, 47, 0, // Skip to: 19231
+/* 7021 */    MCD_OPC_Decode, 138, 17, 232, 1, // Opcode: VCGTzv16i8
+/* 7026 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7041
+/* 7031 */    MCD_OPC_CheckPredicate, 26, 163, 47, 0, // Skip to: 19231
+/* 7036 */    MCD_OPC_Decode, 249, 16, 231, 1, // Opcode: VCGEzv8i8
+/* 7041 */    MCD_OPC_FilterValue, 3, 153, 47, 0, // Skip to: 19231
+/* 7046 */    MCD_OPC_CheckPredicate, 26, 148, 47, 0, // Skip to: 19231
+/* 7051 */    MCD_OPC_Decode, 240, 16, 232, 1, // Opcode: VCGEzv16i8
+/* 7056 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7124
+/* 7061 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7064 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7079
+/* 7069 */    MCD_OPC_CheckPredicate, 26, 125, 47, 0, // Skip to: 19231
+/* 7074 */    MCD_OPC_Decode, 134, 30, 233, 1, // Opcode: VSWPd
+/* 7079 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7094
+/* 7084 */    MCD_OPC_CheckPredicate, 26, 110, 47, 0, // Skip to: 19231
+/* 7089 */    MCD_OPC_Decode, 135, 30, 234, 1, // Opcode: VSWPq
+/* 7094 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7109
+/* 7099 */    MCD_OPC_CheckPredicate, 26, 95, 47, 0, // Skip to: 19231
+/* 7104 */    MCD_OPC_Decode, 174, 30, 233, 1, // Opcode: VTRNd8
+/* 7109 */    MCD_OPC_FilterValue, 3, 85, 47, 0, // Skip to: 19231
+/* 7114 */    MCD_OPC_CheckPredicate, 26, 80, 47, 0, // Skip to: 19231
+/* 7119 */    MCD_OPC_Decode, 177, 30, 234, 1, // Opcode: VTRNq8
+/* 7124 */    MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 7192
+/* 7129 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7132 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7147
+/* 7137 */    MCD_OPC_CheckPredicate, 26, 57, 47, 0, // Skip to: 19231
+/* 7142 */    MCD_OPC_Decode, 211, 25, 231, 1, // Opcode: VREV64d16
+/* 7147 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7162
+/* 7152 */    MCD_OPC_CheckPredicate, 26, 42, 47, 0, // Skip to: 19231
+/* 7157 */    MCD_OPC_Decode, 214, 25, 232, 1, // Opcode: VREV64q16
+/* 7162 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7177
+/* 7167 */    MCD_OPC_CheckPredicate, 26, 27, 47, 0, // Skip to: 19231
+/* 7172 */    MCD_OPC_Decode, 207, 25, 231, 1, // Opcode: VREV32d16
+/* 7177 */    MCD_OPC_FilterValue, 3, 17, 47, 0, // Skip to: 19231
+/* 7182 */    MCD_OPC_CheckPredicate, 26, 12, 47, 0, // Skip to: 19231
+/* 7187 */    MCD_OPC_Decode, 209, 25, 232, 1, // Opcode: VREV32q16
+/* 7192 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 7260
+/* 7197 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7200 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7215
+/* 7205 */    MCD_OPC_CheckPredicate, 26, 245, 46, 0, // Skip to: 19231
+/* 7210 */    MCD_OPC_Decode, 143, 17, 231, 1, // Opcode: VCGTzv4i16
+/* 7215 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7230
+/* 7220 */    MCD_OPC_CheckPredicate, 26, 230, 46, 0, // Skip to: 19231
+/* 7225 */    MCD_OPC_Decode, 146, 17, 232, 1, // Opcode: VCGTzv8i16
+/* 7230 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7245
+/* 7235 */    MCD_OPC_CheckPredicate, 26, 215, 46, 0, // Skip to: 19231
+/* 7240 */    MCD_OPC_Decode, 245, 16, 231, 1, // Opcode: VCGEzv4i16
+/* 7245 */    MCD_OPC_FilterValue, 3, 205, 46, 0, // Skip to: 19231
+/* 7250 */    MCD_OPC_CheckPredicate, 26, 200, 46, 0, // Skip to: 19231
+/* 7255 */    MCD_OPC_Decode, 248, 16, 232, 1, // Opcode: VCGEzv8i16
+/* 7260 */    MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 7298
+/* 7265 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7268 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7283
+/* 7273 */    MCD_OPC_CheckPredicate, 26, 177, 46, 0, // Skip to: 19231
+/* 7278 */    MCD_OPC_Decode, 172, 30, 233, 1, // Opcode: VTRNd16
+/* 7283 */    MCD_OPC_FilterValue, 3, 167, 46, 0, // Skip to: 19231
+/* 7288 */    MCD_OPC_CheckPredicate, 26, 162, 46, 0, // Skip to: 19231
+/* 7293 */    MCD_OPC_Decode, 175, 30, 234, 1, // Opcode: VTRNq16
+/* 7298 */    MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 7336
+/* 7303 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7306 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7321
+/* 7311 */    MCD_OPC_CheckPredicate, 26, 139, 46, 0, // Skip to: 19231
+/* 7316 */    MCD_OPC_Decode, 212, 25, 231, 1, // Opcode: VREV64d32
+/* 7321 */    MCD_OPC_FilterValue, 1, 129, 46, 0, // Skip to: 19231
+/* 7326 */    MCD_OPC_CheckPredicate, 26, 124, 46, 0, // Skip to: 19231
+/* 7331 */    MCD_OPC_Decode, 215, 25, 232, 1, // Opcode: VREV64q32
+/* 7336 */    MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 7404
+/* 7341 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7344 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7359
+/* 7349 */    MCD_OPC_CheckPredicate, 26, 101, 46, 0, // Skip to: 19231
+/* 7354 */    MCD_OPC_Decode, 140, 17, 231, 1, // Opcode: VCGTzv2i32
+/* 7359 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7374
+/* 7364 */    MCD_OPC_CheckPredicate, 26, 86, 46, 0, // Skip to: 19231
+/* 7369 */    MCD_OPC_Decode, 144, 17, 232, 1, // Opcode: VCGTzv4i32
+/* 7374 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7389
+/* 7379 */    MCD_OPC_CheckPredicate, 26, 71, 46, 0, // Skip to: 19231
+/* 7384 */    MCD_OPC_Decode, 242, 16, 231, 1, // Opcode: VCGEzv2i32
+/* 7389 */    MCD_OPC_FilterValue, 3, 61, 46, 0, // Skip to: 19231
+/* 7394 */    MCD_OPC_CheckPredicate, 26, 56, 46, 0, // Skip to: 19231
+/* 7399 */    MCD_OPC_Decode, 246, 16, 232, 1, // Opcode: VCGEzv4i32
+/* 7404 */    MCD_OPC_FilterValue, 10, 46, 46, 0, // Skip to: 19231
+/* 7409 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7412 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7427
+/* 7417 */    MCD_OPC_CheckPredicate, 26, 33, 46, 0, // Skip to: 19231
+/* 7422 */    MCD_OPC_Decode, 173, 30, 233, 1, // Opcode: VTRNd32
+/* 7427 */    MCD_OPC_FilterValue, 3, 23, 46, 0, // Skip to: 19231
+/* 7432 */    MCD_OPC_CheckPredicate, 26, 18, 46, 0, // Skip to: 19231
+/* 7437 */    MCD_OPC_Decode, 176, 30, 234, 1, // Opcode: VTRNq32
+/* 7442 */    MCD_OPC_FilterValue, 1, 163, 1, 0, // Skip to: 7866
+/* 7447 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 7450 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 7488
+/* 7455 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7458 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7473
+/* 7463 */    MCD_OPC_CheckPredicate, 26, 243, 45, 0, // Skip to: 19231
+/* 7468 */    MCD_OPC_Decode, 205, 25, 231, 1, // Opcode: VREV16d8
+/* 7473 */    MCD_OPC_FilterValue, 1, 233, 45, 0, // Skip to: 19231
+/* 7478 */    MCD_OPC_CheckPredicate, 26, 228, 45, 0, // Skip to: 19231
+/* 7483 */    MCD_OPC_Decode, 206, 25, 232, 1, // Opcode: VREV16q8
+/* 7488 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 7556
+/* 7493 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7496 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7511
+/* 7501 */    MCD_OPC_CheckPredicate, 26, 205, 45, 0, // Skip to: 19231
+/* 7506 */    MCD_OPC_Decode, 223, 16, 231, 1, // Opcode: VCEQzv8i8
+/* 7511 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7526
+/* 7516 */    MCD_OPC_CheckPredicate, 26, 190, 45, 0, // Skip to: 19231
+/* 7521 */    MCD_OPC_Decode, 214, 16, 232, 1, // Opcode: VCEQzv16i8
+/* 7526 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7541
+/* 7531 */    MCD_OPC_CheckPredicate, 26, 175, 45, 0, // Skip to: 19231
+/* 7536 */    MCD_OPC_Decode, 157, 17, 231, 1, // Opcode: VCLEzv8i8
+/* 7541 */    MCD_OPC_FilterValue, 3, 165, 45, 0, // Skip to: 19231
+/* 7546 */    MCD_OPC_CheckPredicate, 26, 160, 45, 0, // Skip to: 19231
+/* 7551 */    MCD_OPC_Decode, 148, 17, 232, 1, // Opcode: VCLEzv16i8
+/* 7556 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 7624
+/* 7561 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7564 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7579
+/* 7569 */    MCD_OPC_CheckPredicate, 26, 137, 45, 0, // Skip to: 19231
+/* 7574 */    MCD_OPC_Decode, 204, 30, 233, 1, // Opcode: VUZPd8
+/* 7579 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7594
+/* 7584 */    MCD_OPC_CheckPredicate, 26, 122, 45, 0, // Skip to: 19231
+/* 7589 */    MCD_OPC_Decode, 207, 30, 234, 1, // Opcode: VUZPq8
+/* 7594 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7609
+/* 7599 */    MCD_OPC_CheckPredicate, 26, 107, 45, 0, // Skip to: 19231
+/* 7604 */    MCD_OPC_Decode, 209, 30, 233, 1, // Opcode: VZIPd8
+/* 7609 */    MCD_OPC_FilterValue, 3, 97, 45, 0, // Skip to: 19231
+/* 7614 */    MCD_OPC_CheckPredicate, 26, 92, 45, 0, // Skip to: 19231
+/* 7619 */    MCD_OPC_Decode, 212, 30, 234, 1, // Opcode: VZIPq8
+/* 7624 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 7692
+/* 7629 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7632 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7647
+/* 7637 */    MCD_OPC_CheckPredicate, 26, 69, 45, 0, // Skip to: 19231
+/* 7642 */    MCD_OPC_Decode, 219, 16, 231, 1, // Opcode: VCEQzv4i16
+/* 7647 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7662
+/* 7652 */    MCD_OPC_CheckPredicate, 26, 54, 45, 0, // Skip to: 19231
+/* 7657 */    MCD_OPC_Decode, 222, 16, 232, 1, // Opcode: VCEQzv8i16
+/* 7662 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7677
+/* 7667 */    MCD_OPC_CheckPredicate, 26, 39, 45, 0, // Skip to: 19231
+/* 7672 */    MCD_OPC_Decode, 153, 17, 231, 1, // Opcode: VCLEzv4i16
+/* 7677 */    MCD_OPC_FilterValue, 3, 29, 45, 0, // Skip to: 19231
+/* 7682 */    MCD_OPC_CheckPredicate, 26, 24, 45, 0, // Skip to: 19231
+/* 7687 */    MCD_OPC_Decode, 156, 17, 232, 1, // Opcode: VCLEzv8i16
+/* 7692 */    MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 7760
+/* 7697 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7700 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7715
+/* 7705 */    MCD_OPC_CheckPredicate, 26, 1, 45, 0, // Skip to: 19231
+/* 7710 */    MCD_OPC_Decode, 203, 30, 233, 1, // Opcode: VUZPd16
+/* 7715 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7730
+/* 7720 */    MCD_OPC_CheckPredicate, 26, 242, 44, 0, // Skip to: 19231
+/* 7725 */    MCD_OPC_Decode, 205, 30, 234, 1, // Opcode: VUZPq16
+/* 7730 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7745
+/* 7735 */    MCD_OPC_CheckPredicate, 26, 227, 44, 0, // Skip to: 19231
+/* 7740 */    MCD_OPC_Decode, 208, 30, 233, 1, // Opcode: VZIPd16
+/* 7745 */    MCD_OPC_FilterValue, 3, 217, 44, 0, // Skip to: 19231
+/* 7750 */    MCD_OPC_CheckPredicate, 26, 212, 44, 0, // Skip to: 19231
+/* 7755 */    MCD_OPC_Decode, 210, 30, 234, 1, // Opcode: VZIPq16
+/* 7760 */    MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 7828
+/* 7765 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7768 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7783
+/* 7773 */    MCD_OPC_CheckPredicate, 26, 189, 44, 0, // Skip to: 19231
+/* 7778 */    MCD_OPC_Decode, 216, 16, 231, 1, // Opcode: VCEQzv2i32
+/* 7783 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7798
+/* 7788 */    MCD_OPC_CheckPredicate, 26, 174, 44, 0, // Skip to: 19231
+/* 7793 */    MCD_OPC_Decode, 220, 16, 232, 1, // Opcode: VCEQzv4i32
+/* 7798 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7813
+/* 7803 */    MCD_OPC_CheckPredicate, 26, 159, 44, 0, // Skip to: 19231
+/* 7808 */    MCD_OPC_Decode, 150, 17, 231, 1, // Opcode: VCLEzv2i32
+/* 7813 */    MCD_OPC_FilterValue, 3, 149, 44, 0, // Skip to: 19231
+/* 7818 */    MCD_OPC_CheckPredicate, 26, 144, 44, 0, // Skip to: 19231
+/* 7823 */    MCD_OPC_Decode, 154, 17, 232, 1, // Opcode: VCLEzv4i32
+/* 7828 */    MCD_OPC_FilterValue, 10, 134, 44, 0, // Skip to: 19231
+/* 7833 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7836 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7851
+/* 7841 */    MCD_OPC_CheckPredicate, 26, 121, 44, 0, // Skip to: 19231
+/* 7846 */    MCD_OPC_Decode, 206, 30, 234, 1, // Opcode: VUZPq32
+/* 7851 */    MCD_OPC_FilterValue, 3, 111, 44, 0, // Skip to: 19231
+/* 7856 */    MCD_OPC_CheckPredicate, 26, 106, 44, 0, // Skip to: 19231
+/* 7861 */    MCD_OPC_Decode, 211, 30, 234, 1, // Opcode: VZIPq32
+/* 7866 */    MCD_OPC_FilterValue, 2, 13, 2, 0, // Skip to: 8396
+/* 7871 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 7874 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 7942
+/* 7879 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7882 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7897
+/* 7887 */    MCD_OPC_CheckPredicate, 26, 75, 44, 0, // Skip to: 19231
+/* 7892 */    MCD_OPC_Decode, 249, 23, 231, 1, // Opcode: VPADDLsv8i8
+/* 7897 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7912
+/* 7902 */    MCD_OPC_CheckPredicate, 26, 60, 44, 0, // Skip to: 19231
+/* 7907 */    MCD_OPC_Decode, 244, 23, 232, 1, // Opcode: VPADDLsv16i8
+/* 7912 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 7927
+/* 7917 */    MCD_OPC_CheckPredicate, 26, 45, 44, 0, // Skip to: 19231
+/* 7922 */    MCD_OPC_Decode, 255, 23, 231, 1, // Opcode: VPADDLuv8i8
+/* 7927 */    MCD_OPC_FilterValue, 3, 35, 44, 0, // Skip to: 19231
+/* 7932 */    MCD_OPC_CheckPredicate, 26, 30, 44, 0, // Skip to: 19231
+/* 7937 */    MCD_OPC_Decode, 250, 23, 232, 1, // Opcode: VPADDLuv16i8
+/* 7942 */    MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 7980
+/* 7947 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7950 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7965
+/* 7955 */    MCD_OPC_CheckPredicate, 26, 7, 44, 0, // Skip to: 19231
+/* 7960 */    MCD_OPC_Decode, 173, 17, 231, 1, // Opcode: VCLTzv8i8
+/* 7965 */    MCD_OPC_FilterValue, 1, 253, 43, 0, // Skip to: 19231
+/* 7970 */    MCD_OPC_CheckPredicate, 26, 248, 43, 0, // Skip to: 19231
+/* 7975 */    MCD_OPC_Decode, 164, 17, 232, 1, // Opcode: VCLTzv16i8
+/* 7980 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 8048
+/* 7985 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 7988 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8003
+/* 7993 */    MCD_OPC_CheckPredicate, 26, 225, 43, 0, // Skip to: 19231
+/* 7998 */    MCD_OPC_Decode, 248, 22, 235, 1, // Opcode: VMOVNv8i8
+/* 8003 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8018
+/* 8008 */    MCD_OPC_CheckPredicate, 26, 210, 43, 0, // Skip to: 19231
+/* 8013 */    MCD_OPC_Decode, 193, 24, 235, 1, // Opcode: VQMOVNsuv8i8
+/* 8018 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8033
+/* 8023 */    MCD_OPC_CheckPredicate, 26, 195, 43, 0, // Skip to: 19231
+/* 8028 */    MCD_OPC_Decode, 196, 24, 235, 1, // Opcode: VQMOVNsv8i8
+/* 8033 */    MCD_OPC_FilterValue, 3, 185, 43, 0, // Skip to: 19231
+/* 8038 */    MCD_OPC_CheckPredicate, 26, 180, 43, 0, // Skip to: 19231
+/* 8043 */    MCD_OPC_Decode, 199, 24, 235, 1, // Opcode: VQMOVNuv8i8
+/* 8048 */    MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 8116
+/* 8053 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8056 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8071
+/* 8061 */    MCD_OPC_CheckPredicate, 26, 157, 43, 0, // Skip to: 19231
+/* 8066 */    MCD_OPC_Decode, 246, 23, 231, 1, // Opcode: VPADDLsv4i16
+/* 8071 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8086
+/* 8076 */    MCD_OPC_CheckPredicate, 26, 142, 43, 0, // Skip to: 19231
+/* 8081 */    MCD_OPC_Decode, 248, 23, 232, 1, // Opcode: VPADDLsv8i16
+/* 8086 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8101
+/* 8091 */    MCD_OPC_CheckPredicate, 26, 127, 43, 0, // Skip to: 19231
+/* 8096 */    MCD_OPC_Decode, 252, 23, 231, 1, // Opcode: VPADDLuv4i16
+/* 8101 */    MCD_OPC_FilterValue, 3, 117, 43, 0, // Skip to: 19231
+/* 8106 */    MCD_OPC_CheckPredicate, 26, 112, 43, 0, // Skip to: 19231
+/* 8111 */    MCD_OPC_Decode, 254, 23, 232, 1, // Opcode: VPADDLuv8i16
+/* 8116 */    MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 8154
+/* 8121 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8124 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8139
+/* 8129 */    MCD_OPC_CheckPredicate, 26, 89, 43, 0, // Skip to: 19231
+/* 8134 */    MCD_OPC_Decode, 169, 17, 231, 1, // Opcode: VCLTzv4i16
+/* 8139 */    MCD_OPC_FilterValue, 1, 79, 43, 0, // Skip to: 19231
+/* 8144 */    MCD_OPC_CheckPredicate, 26, 74, 43, 0, // Skip to: 19231
+/* 8149 */    MCD_OPC_Decode, 172, 17, 232, 1, // Opcode: VCLTzv8i16
+/* 8154 */    MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 8222
+/* 8159 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8162 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8177
+/* 8167 */    MCD_OPC_CheckPredicate, 26, 51, 43, 0, // Skip to: 19231
+/* 8172 */    MCD_OPC_Decode, 247, 22, 235, 1, // Opcode: VMOVNv4i16
+/* 8177 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8192
+/* 8182 */    MCD_OPC_CheckPredicate, 26, 36, 43, 0, // Skip to: 19231
+/* 8187 */    MCD_OPC_Decode, 192, 24, 235, 1, // Opcode: VQMOVNsuv4i16
+/* 8192 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8207
+/* 8197 */    MCD_OPC_CheckPredicate, 26, 21, 43, 0, // Skip to: 19231
+/* 8202 */    MCD_OPC_Decode, 195, 24, 235, 1, // Opcode: VQMOVNsv4i16
+/* 8207 */    MCD_OPC_FilterValue, 3, 11, 43, 0, // Skip to: 19231
+/* 8212 */    MCD_OPC_CheckPredicate, 26, 6, 43, 0, // Skip to: 19231
+/* 8217 */    MCD_OPC_Decode, 198, 24, 235, 1, // Opcode: VQMOVNuv4i16
+/* 8222 */    MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 8290
+/* 8227 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8230 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8245
+/* 8235 */    MCD_OPC_CheckPredicate, 26, 239, 42, 0, // Skip to: 19231
+/* 8240 */    MCD_OPC_Decode, 245, 23, 231, 1, // Opcode: VPADDLsv2i32
+/* 8245 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8260
+/* 8250 */    MCD_OPC_CheckPredicate, 26, 224, 42, 0, // Skip to: 19231
+/* 8255 */    MCD_OPC_Decode, 247, 23, 232, 1, // Opcode: VPADDLsv4i32
+/* 8260 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8275
+/* 8265 */    MCD_OPC_CheckPredicate, 26, 209, 42, 0, // Skip to: 19231
+/* 8270 */    MCD_OPC_Decode, 251, 23, 231, 1, // Opcode: VPADDLuv2i32
+/* 8275 */    MCD_OPC_FilterValue, 3, 199, 42, 0, // Skip to: 19231
+/* 8280 */    MCD_OPC_CheckPredicate, 26, 194, 42, 0, // Skip to: 19231
+/* 8285 */    MCD_OPC_Decode, 253, 23, 232, 1, // Opcode: VPADDLuv4i32
+/* 8290 */    MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 8328
+/* 8295 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8298 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8313
+/* 8303 */    MCD_OPC_CheckPredicate, 26, 171, 42, 0, // Skip to: 19231
+/* 8308 */    MCD_OPC_Decode, 166, 17, 231, 1, // Opcode: VCLTzv2i32
+/* 8313 */    MCD_OPC_FilterValue, 1, 161, 42, 0, // Skip to: 19231
+/* 8318 */    MCD_OPC_CheckPredicate, 26, 156, 42, 0, // Skip to: 19231
+/* 8323 */    MCD_OPC_Decode, 170, 17, 232, 1, // Opcode: VCLTzv4i32
+/* 8328 */    MCD_OPC_FilterValue, 10, 146, 42, 0, // Skip to: 19231
+/* 8333 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8336 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8351
+/* 8341 */    MCD_OPC_CheckPredicate, 26, 133, 42, 0, // Skip to: 19231
+/* 8346 */    MCD_OPC_Decode, 246, 22, 235, 1, // Opcode: VMOVNv2i32
+/* 8351 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8366
+/* 8356 */    MCD_OPC_CheckPredicate, 26, 118, 42, 0, // Skip to: 19231
+/* 8361 */    MCD_OPC_Decode, 191, 24, 235, 1, // Opcode: VQMOVNsuv2i32
+/* 8366 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8381
+/* 8371 */    MCD_OPC_CheckPredicate, 26, 103, 42, 0, // Skip to: 19231
+/* 8376 */    MCD_OPC_Decode, 194, 24, 235, 1, // Opcode: VQMOVNsv2i32
+/* 8381 */    MCD_OPC_FilterValue, 3, 93, 42, 0, // Skip to: 19231
+/* 8386 */    MCD_OPC_CheckPredicate, 26, 88, 42, 0, // Skip to: 19231
+/* 8391 */    MCD_OPC_Decode, 197, 24, 235, 1, // Opcode: VQMOVNuv2i32
+/* 8396 */    MCD_OPC_FilterValue, 3, 17, 1, 0, // Skip to: 8674
+/* 8401 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 8404 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 8472
+/* 8409 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8412 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8427
+/* 8417 */    MCD_OPC_CheckPredicate, 26, 57, 42, 0, // Skip to: 19231
+/* 8422 */    MCD_OPC_Decode, 141, 16, 231, 1, // Opcode: VABSv8i8
+/* 8427 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8442
+/* 8432 */    MCD_OPC_CheckPredicate, 26, 42, 42, 0, // Skip to: 19231
+/* 8437 */    MCD_OPC_Decode, 136, 16, 232, 1, // Opcode: VABSv16i8
+/* 8442 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8457
+/* 8447 */    MCD_OPC_CheckPredicate, 26, 27, 42, 0, // Skip to: 19231
+/* 8452 */    MCD_OPC_Decode, 213, 23, 231, 1, // Opcode: VNEGs8d
+/* 8457 */    MCD_OPC_FilterValue, 3, 17, 42, 0, // Skip to: 19231
+/* 8462 */    MCD_OPC_CheckPredicate, 26, 12, 42, 0, // Skip to: 19231
+/* 8467 */    MCD_OPC_Decode, 214, 23, 232, 1, // Opcode: VNEGs8q
+/* 8472 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 8494
+/* 8477 */    MCD_OPC_CheckPredicate, 26, 253, 41, 0, // Skip to: 19231
+/* 8482 */    MCD_OPC_CheckField, 6, 2, 0, 246, 41, 0, // Skip to: 19231
+/* 8489 */    MCD_OPC_Decode, 233, 26, 236, 1, // Opcode: VSHLLi8
+/* 8494 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8562
+/* 8499 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8502 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8517
+/* 8507 */    MCD_OPC_CheckPredicate, 26, 223, 41, 0, // Skip to: 19231
+/* 8512 */    MCD_OPC_Decode, 138, 16, 231, 1, // Opcode: VABSv4i16
+/* 8517 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8532
+/* 8522 */    MCD_OPC_CheckPredicate, 26, 208, 41, 0, // Skip to: 19231
+/* 8527 */    MCD_OPC_Decode, 140, 16, 232, 1, // Opcode: VABSv8i16
+/* 8532 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8547
+/* 8537 */    MCD_OPC_CheckPredicate, 26, 193, 41, 0, // Skip to: 19231
+/* 8542 */    MCD_OPC_Decode, 209, 23, 231, 1, // Opcode: VNEGs16d
+/* 8547 */    MCD_OPC_FilterValue, 3, 183, 41, 0, // Skip to: 19231
+/* 8552 */    MCD_OPC_CheckPredicate, 26, 178, 41, 0, // Skip to: 19231
+/* 8557 */    MCD_OPC_Decode, 210, 23, 232, 1, // Opcode: VNEGs16q
+/* 8562 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 8584
+/* 8567 */    MCD_OPC_CheckPredicate, 26, 163, 41, 0, // Skip to: 19231
+/* 8572 */    MCD_OPC_CheckField, 6, 2, 0, 156, 41, 0, // Skip to: 19231
+/* 8579 */    MCD_OPC_Decode, 231, 26, 236, 1, // Opcode: VSHLLi16
+/* 8584 */    MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 8652
+/* 8589 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8592 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8607
+/* 8597 */    MCD_OPC_CheckPredicate, 26, 133, 41, 0, // Skip to: 19231
+/* 8602 */    MCD_OPC_Decode, 137, 16, 231, 1, // Opcode: VABSv2i32
+/* 8607 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8622
+/* 8612 */    MCD_OPC_CheckPredicate, 26, 118, 41, 0, // Skip to: 19231
+/* 8617 */    MCD_OPC_Decode, 139, 16, 232, 1, // Opcode: VABSv4i32
+/* 8622 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8637
+/* 8627 */    MCD_OPC_CheckPredicate, 26, 103, 41, 0, // Skip to: 19231
+/* 8632 */    MCD_OPC_Decode, 211, 23, 231, 1, // Opcode: VNEGs32d
+/* 8637 */    MCD_OPC_FilterValue, 3, 93, 41, 0, // Skip to: 19231
+/* 8642 */    MCD_OPC_CheckPredicate, 26, 88, 41, 0, // Skip to: 19231
+/* 8647 */    MCD_OPC_Decode, 212, 23, 232, 1, // Opcode: VNEGs32q
+/* 8652 */    MCD_OPC_FilterValue, 10, 78, 41, 0, // Skip to: 19231
+/* 8657 */    MCD_OPC_CheckPredicate, 26, 73, 41, 0, // Skip to: 19231
+/* 8662 */    MCD_OPC_CheckField, 6, 2, 0, 66, 41, 0, // Skip to: 19231
+/* 8669 */    MCD_OPC_Decode, 232, 26, 236, 1, // Opcode: VSHLLi32
+/* 8674 */    MCD_OPC_FilterValue, 4, 155, 1, 0, // Skip to: 9090
+/* 8679 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 8682 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 8750
+/* 8687 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8690 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8705
+/* 8695 */    MCD_OPC_CheckPredicate, 26, 35, 41, 0, // Skip to: 19231
+/* 8700 */    MCD_OPC_Decode, 163, 17, 231, 1, // Opcode: VCLSv8i8
+/* 8705 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8720
+/* 8710 */    MCD_OPC_CheckPredicate, 26, 20, 41, 0, // Skip to: 19231
+/* 8715 */    MCD_OPC_Decode, 158, 17, 232, 1, // Opcode: VCLSv16i8
+/* 8720 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8735
+/* 8725 */    MCD_OPC_CheckPredicate, 26, 5, 41, 0, // Skip to: 19231
+/* 8730 */    MCD_OPC_Decode, 179, 17, 231, 1, // Opcode: VCLZv8i8
+/* 8735 */    MCD_OPC_FilterValue, 3, 251, 40, 0, // Skip to: 19231
+/* 8740 */    MCD_OPC_CheckPredicate, 26, 246, 40, 0, // Skip to: 19231
+/* 8745 */    MCD_OPC_Decode, 174, 17, 232, 1, // Opcode: VCLZv16i8
+/* 8750 */    MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 8818
+/* 8755 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8758 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8773
+/* 8763 */    MCD_OPC_CheckPredicate, 26, 223, 40, 0, // Skip to: 19231
+/* 8768 */    MCD_OPC_Decode, 160, 17, 231, 1, // Opcode: VCLSv4i16
+/* 8773 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8788
+/* 8778 */    MCD_OPC_CheckPredicate, 26, 208, 40, 0, // Skip to: 19231
+/* 8783 */    MCD_OPC_Decode, 162, 17, 232, 1, // Opcode: VCLSv8i16
+/* 8788 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8803
+/* 8793 */    MCD_OPC_CheckPredicate, 26, 193, 40, 0, // Skip to: 19231
+/* 8798 */    MCD_OPC_Decode, 176, 17, 231, 1, // Opcode: VCLZv4i16
+/* 8803 */    MCD_OPC_FilterValue, 3, 183, 40, 0, // Skip to: 19231
+/* 8808 */    MCD_OPC_CheckPredicate, 26, 178, 40, 0, // Skip to: 19231
+/* 8813 */    MCD_OPC_Decode, 178, 17, 232, 1, // Opcode: VCLZv8i16
+/* 8818 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 8886
+/* 8823 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8826 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8841
+/* 8831 */    MCD_OPC_CheckPredicate, 27, 155, 40, 0, // Skip to: 19231
+/* 8836 */    MCD_OPC_Decode, 141, 17, 231, 1, // Opcode: VCGTzv4f16
+/* 8841 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8856
+/* 8846 */    MCD_OPC_CheckPredicate, 27, 140, 40, 0, // Skip to: 19231
+/* 8851 */    MCD_OPC_Decode, 145, 17, 232, 1, // Opcode: VCGTzv8f16
+/* 8856 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8871
+/* 8861 */    MCD_OPC_CheckPredicate, 27, 125, 40, 0, // Skip to: 19231
+/* 8866 */    MCD_OPC_Decode, 243, 16, 231, 1, // Opcode: VCGEzv4f16
+/* 8871 */    MCD_OPC_FilterValue, 3, 115, 40, 0, // Skip to: 19231
+/* 8876 */    MCD_OPC_CheckPredicate, 27, 110, 40, 0, // Skip to: 19231
+/* 8881 */    MCD_OPC_Decode, 247, 16, 232, 1, // Opcode: VCGEzv8f16
+/* 8886 */    MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 8954
+/* 8891 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8894 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8909
+/* 8899 */    MCD_OPC_CheckPredicate, 26, 87, 40, 0, // Skip to: 19231
+/* 8904 */    MCD_OPC_Decode, 159, 17, 231, 1, // Opcode: VCLSv2i32
+/* 8909 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8924
+/* 8914 */    MCD_OPC_CheckPredicate, 26, 72, 40, 0, // Skip to: 19231
+/* 8919 */    MCD_OPC_Decode, 161, 17, 232, 1, // Opcode: VCLSv4i32
+/* 8924 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 8939
+/* 8929 */    MCD_OPC_CheckPredicate, 26, 57, 40, 0, // Skip to: 19231
+/* 8934 */    MCD_OPC_Decode, 175, 17, 231, 1, // Opcode: VCLZv2i32
+/* 8939 */    MCD_OPC_FilterValue, 3, 47, 40, 0, // Skip to: 19231
+/* 8944 */    MCD_OPC_CheckPredicate, 26, 42, 40, 0, // Skip to: 19231
+/* 8949 */    MCD_OPC_Decode, 177, 17, 232, 1, // Opcode: VCLZv4i32
+/* 8954 */    MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 9022
+/* 8959 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 8962 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 8977
+/* 8967 */    MCD_OPC_CheckPredicate, 26, 19, 40, 0, // Skip to: 19231
+/* 8972 */    MCD_OPC_Decode, 139, 17, 231, 1, // Opcode: VCGTzv2f32
+/* 8977 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 8992
+/* 8982 */    MCD_OPC_CheckPredicate, 26, 4, 40, 0, // Skip to: 19231
+/* 8987 */    MCD_OPC_Decode, 142, 17, 232, 1, // Opcode: VCGTzv4f32
+/* 8992 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9007
+/* 8997 */    MCD_OPC_CheckPredicate, 26, 245, 39, 0, // Skip to: 19231
+/* 9002 */    MCD_OPC_Decode, 241, 16, 231, 1, // Opcode: VCGEzv2f32
+/* 9007 */    MCD_OPC_FilterValue, 3, 235, 39, 0, // Skip to: 19231
+/* 9012 */    MCD_OPC_CheckPredicate, 26, 230, 39, 0, // Skip to: 19231
+/* 9017 */    MCD_OPC_Decode, 244, 16, 232, 1, // Opcode: VCGEzv4f32
+/* 9022 */    MCD_OPC_FilterValue, 11, 220, 39, 0, // Skip to: 19231
+/* 9027 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9030 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9045
+/* 9035 */    MCD_OPC_CheckPredicate, 26, 207, 39, 0, // Skip to: 19231
+/* 9040 */    MCD_OPC_Decode, 195, 25, 231, 1, // Opcode: VRECPEd
+/* 9045 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9060
+/* 9050 */    MCD_OPC_CheckPredicate, 26, 192, 39, 0, // Skip to: 19231
+/* 9055 */    MCD_OPC_Decode, 200, 25, 232, 1, // Opcode: VRECPEq
+/* 9060 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9075
+/* 9065 */    MCD_OPC_CheckPredicate, 26, 177, 39, 0, // Skip to: 19231
+/* 9070 */    MCD_OPC_Decode, 181, 26, 231, 1, // Opcode: VRSQRTEd
+/* 9075 */    MCD_OPC_FilterValue, 3, 167, 39, 0, // Skip to: 19231
+/* 9080 */    MCD_OPC_CheckPredicate, 26, 162, 39, 0, // Skip to: 19231
+/* 9085 */    MCD_OPC_Decode, 186, 26, 232, 1, // Opcode: VRSQRTEq
+/* 9090 */    MCD_OPC_FilterValue, 5, 87, 1, 0, // Skip to: 9438
+/* 9095 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 9098 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9166
+/* 9103 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9106 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9121
+/* 9111 */    MCD_OPC_CheckPredicate, 26, 131, 39, 0, // Skip to: 19231
+/* 9116 */    MCD_OPC_Decode, 200, 17, 231, 1, // Opcode: VCNTd
+/* 9121 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9136
+/* 9126 */    MCD_OPC_CheckPredicate, 26, 116, 39, 0, // Skip to: 19231
+/* 9131 */    MCD_OPC_Decode, 201, 17, 232, 1, // Opcode: VCNTq
+/* 9136 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9151
+/* 9141 */    MCD_OPC_CheckPredicate, 26, 101, 39, 0, // Skip to: 19231
+/* 9146 */    MCD_OPC_Decode, 196, 23, 231, 1, // Opcode: VMVNd
+/* 9151 */    MCD_OPC_FilterValue, 3, 91, 39, 0, // Skip to: 19231
+/* 9156 */    MCD_OPC_CheckPredicate, 26, 86, 39, 0, // Skip to: 19231
+/* 9161 */    MCD_OPC_Decode, 197, 23, 232, 1, // Opcode: VMVNq
+/* 9166 */    MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 9234
+/* 9171 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9174 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9189
+/* 9179 */    MCD_OPC_CheckPredicate, 27, 63, 39, 0, // Skip to: 19231
+/* 9184 */    MCD_OPC_Decode, 217, 16, 231, 1, // Opcode: VCEQzv4f16
+/* 9189 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9204
+/* 9194 */    MCD_OPC_CheckPredicate, 27, 48, 39, 0, // Skip to: 19231
+/* 9199 */    MCD_OPC_Decode, 221, 16, 232, 1, // Opcode: VCEQzv8f16
+/* 9204 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9219
+/* 9209 */    MCD_OPC_CheckPredicate, 27, 33, 39, 0, // Skip to: 19231
+/* 9214 */    MCD_OPC_Decode, 151, 17, 231, 1, // Opcode: VCLEzv4f16
+/* 9219 */    MCD_OPC_FilterValue, 3, 23, 39, 0, // Skip to: 19231
+/* 9224 */    MCD_OPC_CheckPredicate, 27, 18, 39, 0, // Skip to: 19231
+/* 9229 */    MCD_OPC_Decode, 155, 17, 232, 1, // Opcode: VCLEzv8f16
+/* 9234 */    MCD_OPC_FilterValue, 7, 63, 0, 0, // Skip to: 9302
+/* 9239 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9242 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9257
+/* 9247 */    MCD_OPC_CheckPredicate, 27, 251, 38, 0, // Skip to: 19231
+/* 9252 */    MCD_OPC_Decode, 198, 25, 231, 1, // Opcode: VRECPEhd
+/* 9257 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9272
+/* 9262 */    MCD_OPC_CheckPredicate, 27, 236, 38, 0, // Skip to: 19231
+/* 9267 */    MCD_OPC_Decode, 199, 25, 232, 1, // Opcode: VRECPEhq
+/* 9272 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9287
+/* 9277 */    MCD_OPC_CheckPredicate, 27, 221, 38, 0, // Skip to: 19231
+/* 9282 */    MCD_OPC_Decode, 184, 26, 231, 1, // Opcode: VRSQRTEhd
+/* 9287 */    MCD_OPC_FilterValue, 3, 211, 38, 0, // Skip to: 19231
+/* 9292 */    MCD_OPC_CheckPredicate, 27, 206, 38, 0, // Skip to: 19231
+/* 9297 */    MCD_OPC_Decode, 185, 26, 232, 1, // Opcode: VRSQRTEhq
+/* 9302 */    MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 9370
+/* 9307 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9310 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9325
+/* 9315 */    MCD_OPC_CheckPredicate, 26, 183, 38, 0, // Skip to: 19231
+/* 9320 */    MCD_OPC_Decode, 215, 16, 231, 1, // Opcode: VCEQzv2f32
+/* 9325 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9340
+/* 9330 */    MCD_OPC_CheckPredicate, 26, 168, 38, 0, // Skip to: 19231
+/* 9335 */    MCD_OPC_Decode, 218, 16, 232, 1, // Opcode: VCEQzv4f32
+/* 9340 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9355
+/* 9345 */    MCD_OPC_CheckPredicate, 26, 153, 38, 0, // Skip to: 19231
+/* 9350 */    MCD_OPC_Decode, 149, 17, 231, 1, // Opcode: VCLEzv2f32
+/* 9355 */    MCD_OPC_FilterValue, 3, 143, 38, 0, // Skip to: 19231
+/* 9360 */    MCD_OPC_CheckPredicate, 26, 138, 38, 0, // Skip to: 19231
+/* 9365 */    MCD_OPC_Decode, 152, 17, 232, 1, // Opcode: VCLEzv4f32
+/* 9370 */    MCD_OPC_FilterValue, 11, 128, 38, 0, // Skip to: 19231
+/* 9375 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9378 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9393
+/* 9383 */    MCD_OPC_CheckPredicate, 26, 115, 38, 0, // Skip to: 19231
+/* 9388 */    MCD_OPC_Decode, 196, 25, 231, 1, // Opcode: VRECPEfd
+/* 9393 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9408
+/* 9398 */    MCD_OPC_CheckPredicate, 26, 100, 38, 0, // Skip to: 19231
+/* 9403 */    MCD_OPC_Decode, 197, 25, 232, 1, // Opcode: VRECPEfq
+/* 9408 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9423
+/* 9413 */    MCD_OPC_CheckPredicate, 26, 85, 38, 0, // Skip to: 19231
+/* 9418 */    MCD_OPC_Decode, 182, 26, 231, 1, // Opcode: VRSQRTEfd
+/* 9423 */    MCD_OPC_FilterValue, 3, 75, 38, 0, // Skip to: 19231
+/* 9428 */    MCD_OPC_CheckPredicate, 26, 70, 38, 0, // Skip to: 19231
+/* 9433 */    MCD_OPC_Decode, 183, 26, 232, 1, // Opcode: VRSQRTEfq
+/* 9438 */    MCD_OPC_FilterValue, 6, 201, 1, 0, // Skip to: 9900
+/* 9443 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 9446 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9514
+/* 9451 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9454 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9469
+/* 9459 */    MCD_OPC_CheckPredicate, 26, 39, 38, 0, // Skip to: 19231
+/* 9464 */    MCD_OPC_Decode, 237, 23, 237, 1, // Opcode: VPADALsv8i8
+/* 9469 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9484
+/* 9474 */    MCD_OPC_CheckPredicate, 26, 24, 38, 0, // Skip to: 19231
+/* 9479 */    MCD_OPC_Decode, 232, 23, 238, 1, // Opcode: VPADALsv16i8
+/* 9484 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9499
+/* 9489 */    MCD_OPC_CheckPredicate, 26, 9, 38, 0, // Skip to: 19231
+/* 9494 */    MCD_OPC_Decode, 243, 23, 237, 1, // Opcode: VPADALuv8i8
+/* 9499 */    MCD_OPC_FilterValue, 3, 255, 37, 0, // Skip to: 19231
+/* 9504 */    MCD_OPC_CheckPredicate, 26, 250, 37, 0, // Skip to: 19231
+/* 9509 */    MCD_OPC_Decode, 238, 23, 238, 1, // Opcode: VPADALuv16i8
+/* 9514 */    MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 9582
+/* 9519 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9522 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9537
+/* 9527 */    MCD_OPC_CheckPredicate, 26, 227, 37, 0, // Skip to: 19231
+/* 9532 */    MCD_OPC_Decode, 234, 23, 237, 1, // Opcode: VPADALsv4i16
+/* 9537 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9552
+/* 9542 */    MCD_OPC_CheckPredicate, 26, 212, 37, 0, // Skip to: 19231
+/* 9547 */    MCD_OPC_Decode, 236, 23, 238, 1, // Opcode: VPADALsv8i16
+/* 9552 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9567
+/* 9557 */    MCD_OPC_CheckPredicate, 26, 197, 37, 0, // Skip to: 19231
+/* 9562 */    MCD_OPC_Decode, 240, 23, 237, 1, // Opcode: VPADALuv4i16
+/* 9567 */    MCD_OPC_FilterValue, 3, 187, 37, 0, // Skip to: 19231
+/* 9572 */    MCD_OPC_CheckPredicate, 26, 182, 37, 0, // Skip to: 19231
+/* 9577 */    MCD_OPC_Decode, 242, 23, 238, 1, // Opcode: VPADALuv8i16
+/* 9582 */    MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 9620
+/* 9587 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9590 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9605
+/* 9595 */    MCD_OPC_CheckPredicate, 27, 159, 37, 0, // Skip to: 19231
+/* 9600 */    MCD_OPC_Decode, 167, 17, 231, 1, // Opcode: VCLTzv4f16
+/* 9605 */    MCD_OPC_FilterValue, 1, 149, 37, 0, // Skip to: 19231
+/* 9610 */    MCD_OPC_CheckPredicate, 27, 144, 37, 0, // Skip to: 19231
+/* 9615 */    MCD_OPC_Decode, 171, 17, 232, 1, // Opcode: VCLTzv8f16
+/* 9620 */    MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 9658
+/* 9625 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9628 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9643
+/* 9633 */    MCD_OPC_CheckPredicate, 30, 121, 37, 0, // Skip to: 19231
+/* 9638 */    MCD_OPC_Decode, 140, 18, 235, 1, // Opcode: VCVTf2h
+/* 9643 */    MCD_OPC_FilterValue, 1, 111, 37, 0, // Skip to: 19231
+/* 9648 */    MCD_OPC_CheckPredicate, 31, 106, 37, 0, // Skip to: 19231
+/* 9653 */    MCD_OPC_Decode, 218, 5, 235, 1, // Opcode: BF16_VCVT
+/* 9658 */    MCD_OPC_FilterValue, 7, 63, 0, 0, // Skip to: 9726
+/* 9663 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9666 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9681
+/* 9671 */    MCD_OPC_CheckPredicate, 27, 83, 37, 0, // Skip to: 19231
+/* 9676 */    MCD_OPC_Decode, 160, 18, 231, 1, // Opcode: VCVTs2hd
+/* 9681 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9696
+/* 9686 */    MCD_OPC_CheckPredicate, 27, 68, 37, 0, // Skip to: 19231
+/* 9691 */    MCD_OPC_Decode, 161, 18, 232, 1, // Opcode: VCVTs2hq
+/* 9696 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9711
+/* 9701 */    MCD_OPC_CheckPredicate, 27, 53, 37, 0, // Skip to: 19231
+/* 9706 */    MCD_OPC_Decode, 164, 18, 231, 1, // Opcode: VCVTu2hd
+/* 9711 */    MCD_OPC_FilterValue, 3, 43, 37, 0, // Skip to: 19231
+/* 9716 */    MCD_OPC_CheckPredicate, 27, 38, 37, 0, // Skip to: 19231
+/* 9721 */    MCD_OPC_Decode, 165, 18, 232, 1, // Opcode: VCVTu2hq
+/* 9726 */    MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 9794
+/* 9731 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9734 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9749
+/* 9739 */    MCD_OPC_CheckPredicate, 26, 15, 37, 0, // Skip to: 19231
+/* 9744 */    MCD_OPC_Decode, 233, 23, 237, 1, // Opcode: VPADALsv2i32
+/* 9749 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9764
+/* 9754 */    MCD_OPC_CheckPredicate, 26, 0, 37, 0, // Skip to: 19231
+/* 9759 */    MCD_OPC_Decode, 235, 23, 238, 1, // Opcode: VPADALsv4i32
+/* 9764 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9779
+/* 9769 */    MCD_OPC_CheckPredicate, 26, 241, 36, 0, // Skip to: 19231
+/* 9774 */    MCD_OPC_Decode, 239, 23, 237, 1, // Opcode: VPADALuv2i32
+/* 9779 */    MCD_OPC_FilterValue, 3, 231, 36, 0, // Skip to: 19231
+/* 9784 */    MCD_OPC_CheckPredicate, 26, 226, 36, 0, // Skip to: 19231
+/* 9789 */    MCD_OPC_Decode, 241, 23, 238, 1, // Opcode: VPADALuv4i32
+/* 9794 */    MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 9832
+/* 9799 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9802 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9817
+/* 9807 */    MCD_OPC_CheckPredicate, 26, 203, 36, 0, // Skip to: 19231
+/* 9812 */    MCD_OPC_Decode, 165, 17, 231, 1, // Opcode: VCLTzv2f32
+/* 9817 */    MCD_OPC_FilterValue, 1, 193, 36, 0, // Skip to: 19231
+/* 9822 */    MCD_OPC_CheckPredicate, 26, 188, 36, 0, // Skip to: 19231
+/* 9827 */    MCD_OPC_Decode, 168, 17, 232, 1, // Opcode: VCLTzv4f32
+/* 9832 */    MCD_OPC_FilterValue, 11, 178, 36, 0, // Skip to: 19231
+/* 9837 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9840 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9855
+/* 9845 */    MCD_OPC_CheckPredicate, 26, 165, 36, 0, // Skip to: 19231
+/* 9850 */    MCD_OPC_Decode, 158, 18, 231, 1, // Opcode: VCVTs2fd
+/* 9855 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9870
+/* 9860 */    MCD_OPC_CheckPredicate, 26, 150, 36, 0, // Skip to: 19231
+/* 9865 */    MCD_OPC_Decode, 159, 18, 232, 1, // Opcode: VCVTs2fq
+/* 9870 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9885
+/* 9875 */    MCD_OPC_CheckPredicate, 26, 135, 36, 0, // Skip to: 19231
+/* 9880 */    MCD_OPC_Decode, 162, 18, 231, 1, // Opcode: VCVTu2fd
+/* 9885 */    MCD_OPC_FilterValue, 3, 125, 36, 0, // Skip to: 19231
+/* 9890 */    MCD_OPC_CheckPredicate, 26, 120, 36, 0, // Skip to: 19231
+/* 9895 */    MCD_OPC_Decode, 163, 18, 232, 1, // Opcode: VCVTu2fq
+/* 9900 */    MCD_OPC_FilterValue, 7, 245, 1, 0, // Skip to: 10406
+/* 9905 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 9908 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 9976
+/* 9913 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9916 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9931
+/* 9921 */    MCD_OPC_CheckPredicate, 26, 89, 36, 0, // Skip to: 19231
+/* 9926 */    MCD_OPC_Decode, 154, 24, 231, 1, // Opcode: VQABSv8i8
+/* 9931 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 9946
+/* 9936 */    MCD_OPC_CheckPredicate, 26, 74, 36, 0, // Skip to: 19231
+/* 9941 */    MCD_OPC_Decode, 149, 24, 232, 1, // Opcode: VQABSv16i8
+/* 9946 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 9961
+/* 9951 */    MCD_OPC_CheckPredicate, 26, 59, 36, 0, // Skip to: 19231
+/* 9956 */    MCD_OPC_Decode, 205, 24, 231, 1, // Opcode: VQNEGv8i8
+/* 9961 */    MCD_OPC_FilterValue, 3, 49, 36, 0, // Skip to: 19231
+/* 9966 */    MCD_OPC_CheckPredicate, 26, 44, 36, 0, // Skip to: 19231
+/* 9971 */    MCD_OPC_Decode, 200, 24, 232, 1, // Opcode: VQNEGv16i8
+/* 9976 */    MCD_OPC_FilterValue, 4, 63, 0, 0, // Skip to: 10044
+/* 9981 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 9984 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 9999
+/* 9989 */    MCD_OPC_CheckPredicate, 26, 21, 36, 0, // Skip to: 19231
+/* 9994 */    MCD_OPC_Decode, 151, 24, 231, 1, // Opcode: VQABSv4i16
+/* 9999 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10014
+/* 10004 */   MCD_OPC_CheckPredicate, 26, 6, 36, 0, // Skip to: 19231
+/* 10009 */   MCD_OPC_Decode, 153, 24, 232, 1, // Opcode: VQABSv8i16
+/* 10014 */   MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10029
+/* 10019 */   MCD_OPC_CheckPredicate, 26, 247, 35, 0, // Skip to: 19231
+/* 10024 */   MCD_OPC_Decode, 202, 24, 231, 1, // Opcode: VQNEGv4i16
+/* 10029 */   MCD_OPC_FilterValue, 3, 237, 35, 0, // Skip to: 19231
+/* 10034 */   MCD_OPC_CheckPredicate, 26, 232, 35, 0, // Skip to: 19231
+/* 10039 */   MCD_OPC_Decode, 204, 24, 232, 1, // Opcode: VQNEGv8i16
+/* 10044 */   MCD_OPC_FilterValue, 5, 63, 0, 0, // Skip to: 10112
+/* 10049 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 10052 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10067
+/* 10057 */   MCD_OPC_CheckPredicate, 27, 209, 35, 0, // Skip to: 19231
+/* 10062 */   MCD_OPC_Decode, 134, 16, 231, 1, // Opcode: VABShd
+/* 10067 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10082
+/* 10072 */   MCD_OPC_CheckPredicate, 27, 194, 35, 0, // Skip to: 19231
+/* 10077 */   MCD_OPC_Decode, 135, 16, 232, 1, // Opcode: VABShq
+/* 10082 */   MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10097
+/* 10087 */   MCD_OPC_CheckPredicate, 27, 179, 35, 0, // Skip to: 19231
+/* 10092 */   MCD_OPC_Decode, 207, 23, 231, 1, // Opcode: VNEGhd
+/* 10097 */   MCD_OPC_FilterValue, 3, 169, 35, 0, // Skip to: 19231
+/* 10102 */   MCD_OPC_CheckPredicate, 27, 164, 35, 0, // Skip to: 19231
+/* 10107 */   MCD_OPC_Decode, 208, 23, 232, 1, // Opcode: VNEGhq
+/* 10112 */   MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 10134
+/* 10117 */   MCD_OPC_CheckPredicate, 30, 149, 35, 0, // Skip to: 19231
+/* 10122 */   MCD_OPC_CheckField, 6, 2, 0, 142, 35, 0, // Skip to: 19231
+/* 10129 */   MCD_OPC_Decode, 149, 18, 239, 1, // Opcode: VCVTh2f
+/* 10134 */   MCD_OPC_FilterValue, 7, 63, 0, 0, // Skip to: 10202
+/* 10139 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 10142 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10157
+/* 10147 */   MCD_OPC_CheckPredicate, 27, 119, 35, 0, // Skip to: 19231
+/* 10152 */   MCD_OPC_Decode, 150, 18, 231, 1, // Opcode: VCVTh2sd
+/* 10157 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10172
+/* 10162 */   MCD_OPC_CheckPredicate, 27, 104, 35, 0, // Skip to: 19231
+/* 10167 */   MCD_OPC_Decode, 151, 18, 232, 1, // Opcode: VCVTh2sq
+/* 10172 */   MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10187
+/* 10177 */   MCD_OPC_CheckPredicate, 27, 89, 35, 0, // Skip to: 19231
+/* 10182 */   MCD_OPC_Decode, 152, 18, 231, 1, // Opcode: VCVTh2ud
+/* 10187 */   MCD_OPC_FilterValue, 3, 79, 35, 0, // Skip to: 19231
+/* 10192 */   MCD_OPC_CheckPredicate, 27, 74, 35, 0, // Skip to: 19231
+/* 10197 */   MCD_OPC_Decode, 153, 18, 232, 1, // Opcode: VCVTh2uq
+/* 10202 */   MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 10270
+/* 10207 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 10210 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10225
+/* 10215 */   MCD_OPC_CheckPredicate, 26, 51, 35, 0, // Skip to: 19231
+/* 10220 */   MCD_OPC_Decode, 150, 24, 231, 1, // Opcode: VQABSv2i32
+/* 10225 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10240
+/* 10230 */   MCD_OPC_CheckPredicate, 26, 36, 35, 0, // Skip to: 19231
+/* 10235 */   MCD_OPC_Decode, 152, 24, 232, 1, // Opcode: VQABSv4i32
+/* 10240 */   MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10255
+/* 10245 */   MCD_OPC_CheckPredicate, 26, 21, 35, 0, // Skip to: 19231
+/* 10250 */   MCD_OPC_Decode, 201, 24, 231, 1, // Opcode: VQNEGv2i32
+/* 10255 */   MCD_OPC_FilterValue, 3, 11, 35, 0, // Skip to: 19231
+/* 10260 */   MCD_OPC_CheckPredicate, 26, 6, 35, 0, // Skip to: 19231
+/* 10265 */   MCD_OPC_Decode, 203, 24, 232, 1, // Opcode: VQNEGv4i32
+/* 10270 */   MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 10338
+/* 10275 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 10278 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10293
+/* 10283 */   MCD_OPC_CheckPredicate, 26, 239, 34, 0, // Skip to: 19231
+/* 10288 */   MCD_OPC_Decode, 132, 16, 231, 1, // Opcode: VABSfd
+/* 10293 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10308
+/* 10298 */   MCD_OPC_CheckPredicate, 26, 224, 34, 0, // Skip to: 19231
+/* 10303 */   MCD_OPC_Decode, 133, 16, 232, 1, // Opcode: VABSfq
+/* 10308 */   MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10323
+/* 10313 */   MCD_OPC_CheckPredicate, 26, 209, 34, 0, // Skip to: 19231
+/* 10318 */   MCD_OPC_Decode, 206, 23, 231, 1, // Opcode: VNEGfd
+/* 10323 */   MCD_OPC_FilterValue, 3, 199, 34, 0, // Skip to: 19231
+/* 10328 */   MCD_OPC_CheckPredicate, 26, 194, 34, 0, // Skip to: 19231
+/* 10333 */   MCD_OPC_Decode, 205, 23, 232, 1, // Opcode: VNEGf32q
+/* 10338 */   MCD_OPC_FilterValue, 11, 184, 34, 0, // Skip to: 19231
+/* 10343 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 10346 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10361
+/* 10351 */   MCD_OPC_CheckPredicate, 26, 171, 34, 0, // Skip to: 19231
+/* 10356 */   MCD_OPC_Decode, 141, 18, 231, 1, // Opcode: VCVTf2sd
+/* 10361 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 10376
+/* 10366 */   MCD_OPC_CheckPredicate, 26, 156, 34, 0, // Skip to: 19231
+/* 10371 */   MCD_OPC_Decode, 142, 18, 232, 1, // Opcode: VCVTf2sq
+/* 10376 */   MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 10391
+/* 10381 */   MCD_OPC_CheckPredicate, 26, 141, 34, 0, // Skip to: 19231
+/* 10386 */   MCD_OPC_Decode, 143, 18, 231, 1, // Opcode: VCVTf2ud
+/* 10391 */   MCD_OPC_FilterValue, 3, 131, 34, 0, // Skip to: 19231
+/* 10396 */   MCD_OPC_CheckPredicate, 26, 126, 34, 0, // Skip to: 19231
+/* 10401 */   MCD_OPC_Decode, 144, 18, 232, 1, // Opcode: VCVTf2uq
+/* 10406 */   MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 10444
+/* 10411 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10414 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10429
+/* 10419 */   MCD_OPC_CheckPredicate, 26, 103, 34, 0, // Skip to: 19231
+/* 10424 */   MCD_OPC_Decode, 136, 30, 240, 1, // Opcode: VTBL1
+/* 10429 */   MCD_OPC_FilterValue, 1, 93, 34, 0, // Skip to: 19231
+/* 10434 */   MCD_OPC_CheckPredicate, 26, 88, 34, 0, // Skip to: 19231
+/* 10439 */   MCD_OPC_Decode, 142, 30, 240, 1, // Opcode: VTBX1
+/* 10444 */   MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 10482
+/* 10449 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10452 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10467
+/* 10457 */   MCD_OPC_CheckPredicate, 26, 65, 34, 0, // Skip to: 19231
+/* 10462 */   MCD_OPC_Decode, 137, 30, 240, 1, // Opcode: VTBL2
+/* 10467 */   MCD_OPC_FilterValue, 1, 55, 34, 0, // Skip to: 19231
+/* 10472 */   MCD_OPC_CheckPredicate, 26, 50, 34, 0, // Skip to: 19231
+/* 10477 */   MCD_OPC_Decode, 143, 30, 240, 1, // Opcode: VTBX2
+/* 10482 */   MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 10520
+/* 10487 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10490 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10505
+/* 10495 */   MCD_OPC_CheckPredicate, 26, 27, 34, 0, // Skip to: 19231
+/* 10500 */   MCD_OPC_Decode, 138, 30, 240, 1, // Opcode: VTBL3
+/* 10505 */   MCD_OPC_FilterValue, 1, 17, 34, 0, // Skip to: 19231
+/* 10510 */   MCD_OPC_CheckPredicate, 26, 12, 34, 0, // Skip to: 19231
+/* 10515 */   MCD_OPC_Decode, 144, 30, 240, 1, // Opcode: VTBX3
+/* 10520 */   MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 10558
+/* 10525 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10528 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 10543
+/* 10533 */   MCD_OPC_CheckPredicate, 26, 245, 33, 0, // Skip to: 19231
+/* 10538 */   MCD_OPC_Decode, 140, 30, 240, 1, // Opcode: VTBL4
+/* 10543 */   MCD_OPC_FilterValue, 1, 235, 33, 0, // Skip to: 19231
+/* 10548 */   MCD_OPC_CheckPredicate, 26, 230, 33, 0, // Skip to: 19231
+/* 10553 */   MCD_OPC_Decode, 146, 30, 240, 1, // Opcode: VTBX4
+/* 10558 */   MCD_OPC_FilterValue, 12, 220, 33, 0, // Skip to: 19231
+/* 10563 */   MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 10566 */   MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 10634
+/* 10571 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10574 */   MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10619
+/* 10579 */   MCD_OPC_ExtractField, 17, 1,  // Inst{17} ...
+/* 10582 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10604
+/* 10587 */   MCD_OPC_CheckPredicate, 26, 191, 33, 0, // Skip to: 19231
+/* 10592 */   MCD_OPC_CheckField, 18, 1, 1, 184, 33, 0, // Skip to: 19231
+/* 10599 */   MCD_OPC_Decode, 185, 18, 241, 1, // Opcode: VDUPLN32d
+/* 10604 */   MCD_OPC_FilterValue, 1, 174, 33, 0, // Skip to: 19231
+/* 10609 */   MCD_OPC_CheckPredicate, 26, 169, 33, 0, // Skip to: 19231
+/* 10614 */   MCD_OPC_Decode, 183, 18, 242, 1, // Opcode: VDUPLN16d
+/* 10619 */   MCD_OPC_FilterValue, 1, 159, 33, 0, // Skip to: 19231
+/* 10624 */   MCD_OPC_CheckPredicate, 26, 154, 33, 0, // Skip to: 19231
+/* 10629 */   MCD_OPC_Decode, 187, 18, 243, 1, // Opcode: VDUPLN8d
+/* 10634 */   MCD_OPC_FilterValue, 1, 144, 33, 0, // Skip to: 19231
+/* 10639 */   MCD_OPC_ExtractField, 16, 1,  // Inst{16} ...
+/* 10642 */   MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 10687
+/* 10647 */   MCD_OPC_ExtractField, 17, 1,  // Inst{17} ...
+/* 10650 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 10672
+/* 10655 */   MCD_OPC_CheckPredicate, 26, 123, 33, 0, // Skip to: 19231
+/* 10660 */   MCD_OPC_CheckField, 18, 1, 1, 116, 33, 0, // Skip to: 19231
+/* 10667 */   MCD_OPC_Decode, 186, 18, 244, 1, // Opcode: VDUPLN32q
+/* 10672 */   MCD_OPC_FilterValue, 1, 106, 33, 0, // Skip to: 19231
+/* 10677 */   MCD_OPC_CheckPredicate, 26, 101, 33, 0, // Skip to: 19231
+/* 10682 */   MCD_OPC_Decode, 184, 18, 245, 1, // Opcode: VDUPLN16q
+/* 10687 */   MCD_OPC_FilterValue, 1, 91, 33, 0, // Skip to: 19231
+/* 10692 */   MCD_OPC_CheckPredicate, 26, 86, 33, 0, // Skip to: 19231
+/* 10697 */   MCD_OPC_Decode, 188, 18, 246, 1, // Opcode: VDUPLN8q
+/* 10702 */   MCD_OPC_FilterValue, 1, 76, 33, 0, // Skip to: 19231
+/* 10707 */   MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 10710 */   MCD_OPC_FilterValue, 0, 120, 17, 0, // Skip to: 15187
+/* 10715 */   MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 10718 */   MCD_OPC_FilterValue, 0, 108, 8, 0, // Skip to: 12879
+/* 10723 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 10726 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 10894
+/* 10731 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 10734 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 10774
+/* 10739 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10742 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 10758
+/* 10748 */   MCD_OPC_CheckPredicate, 26, 30, 33, 0, // Skip to: 19231
+/* 10753 */   MCD_OPC_Decode, 162, 24, 202, 1, // Opcode: VQADDsv8i8
+/* 10758 */   MCD_OPC_FilterValue, 243, 1, 19, 33, 0, // Skip to: 19231
+/* 10764 */   MCD_OPC_CheckPredicate, 26, 14, 33, 0, // Skip to: 19231
+/* 10769 */   MCD_OPC_Decode, 170, 24, 202, 1, // Opcode: VQADDuv8i8
+/* 10774 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 10814
+/* 10779 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10782 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 10798
+/* 10788 */   MCD_OPC_CheckPredicate, 26, 246, 32, 0, // Skip to: 19231
+/* 10793 */   MCD_OPC_Decode, 159, 24, 202, 1, // Opcode: VQADDsv4i16
+/* 10798 */   MCD_OPC_FilterValue, 243, 1, 235, 32, 0, // Skip to: 19231
+/* 10804 */   MCD_OPC_CheckPredicate, 26, 230, 32, 0, // Skip to: 19231
+/* 10809 */   MCD_OPC_Decode, 167, 24, 202, 1, // Opcode: VQADDuv4i16
+/* 10814 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 10854
+/* 10819 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10822 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 10838
+/* 10828 */   MCD_OPC_CheckPredicate, 26, 206, 32, 0, // Skip to: 19231
+/* 10833 */   MCD_OPC_Decode, 157, 24, 202, 1, // Opcode: VQADDsv2i32
+/* 10838 */   MCD_OPC_FilterValue, 243, 1, 195, 32, 0, // Skip to: 19231
+/* 10844 */   MCD_OPC_CheckPredicate, 26, 190, 32, 0, // Skip to: 19231
+/* 10849 */   MCD_OPC_Decode, 165, 24, 202, 1, // Opcode: VQADDuv2i32
+/* 10854 */   MCD_OPC_FilterValue, 3, 180, 32, 0, // Skip to: 19231
+/* 10859 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10862 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 10878
+/* 10868 */   MCD_OPC_CheckPredicate, 26, 166, 32, 0, // Skip to: 19231
+/* 10873 */   MCD_OPC_Decode, 156, 24, 202, 1, // Opcode: VQADDsv1i64
+/* 10878 */   MCD_OPC_FilterValue, 243, 1, 155, 32, 0, // Skip to: 19231
+/* 10884 */   MCD_OPC_CheckPredicate, 26, 150, 32, 0, // Skip to: 19231
+/* 10889 */   MCD_OPC_Decode, 164, 24, 202, 1, // Opcode: VQADDuv1i64
+/* 10894 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 11062
+/* 10899 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 10902 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 10942
+/* 10907 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10910 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 10926
+/* 10916 */   MCD_OPC_CheckPredicate, 26, 118, 32, 0, // Skip to: 19231
+/* 10921 */   MCD_OPC_Decode, 180, 16, 202, 1, // Opcode: VANDd
+/* 10926 */   MCD_OPC_FilterValue, 243, 1, 107, 32, 0, // Skip to: 19231
+/* 10932 */   MCD_OPC_CheckPredicate, 26, 102, 32, 0, // Skip to: 19231
+/* 10937 */   MCD_OPC_Decode, 189, 18, 202, 1, // Opcode: VEORd
+/* 10942 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 10982
+/* 10947 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10950 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 10966
+/* 10956 */   MCD_OPC_CheckPredicate, 26, 78, 32, 0, // Skip to: 19231
+/* 10961 */   MCD_OPC_Decode, 186, 16, 202, 1, // Opcode: VBICd
+/* 10966 */   MCD_OPC_FilterValue, 243, 1, 67, 32, 0, // Skip to: 19231
+/* 10972 */   MCD_OPC_CheckPredicate, 26, 62, 32, 0, // Skip to: 19231
+/* 10977 */   MCD_OPC_Decode, 196, 16, 210, 1, // Opcode: VBSLd
+/* 10982 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 11022
+/* 10987 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 10990 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11006
+/* 10996 */   MCD_OPC_CheckPredicate, 26, 38, 32, 0, // Skip to: 19231
+/* 11001 */   MCD_OPC_Decode, 226, 23, 202, 1, // Opcode: VORRd
+/* 11006 */   MCD_OPC_FilterValue, 243, 1, 27, 32, 0, // Skip to: 19231
+/* 11012 */   MCD_OPC_CheckPredicate, 26, 22, 32, 0, // Skip to: 19231
+/* 11017 */   MCD_OPC_Decode, 194, 16, 210, 1, // Opcode: VBITd
+/* 11022 */   MCD_OPC_FilterValue, 3, 12, 32, 0, // Skip to: 19231
+/* 11027 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11030 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11046
+/* 11036 */   MCD_OPC_CheckPredicate, 26, 254, 31, 0, // Skip to: 19231
+/* 11041 */   MCD_OPC_Decode, 224, 23, 202, 1, // Opcode: VORNd
+/* 11046 */   MCD_OPC_FilterValue, 243, 1, 243, 31, 0, // Skip to: 19231
+/* 11052 */   MCD_OPC_CheckPredicate, 26, 238, 31, 0, // Skip to: 19231
+/* 11057 */   MCD_OPC_Decode, 192, 16, 210, 1, // Opcode: VBIFd
+/* 11062 */   MCD_OPC_FilterValue, 2, 163, 0, 0, // Skip to: 11230
+/* 11067 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11070 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11110
+/* 11075 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11078 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11094
+/* 11084 */   MCD_OPC_CheckPredicate, 26, 206, 31, 0, // Skip to: 19231
+/* 11089 */   MCD_OPC_Decode, 183, 25, 202, 1, // Opcode: VQSUBsv8i8
+/* 11094 */   MCD_OPC_FilterValue, 243, 1, 195, 31, 0, // Skip to: 19231
+/* 11100 */   MCD_OPC_CheckPredicate, 26, 190, 31, 0, // Skip to: 19231
+/* 11105 */   MCD_OPC_Decode, 191, 25, 202, 1, // Opcode: VQSUBuv8i8
+/* 11110 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 11150
+/* 11115 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11118 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11134
+/* 11124 */   MCD_OPC_CheckPredicate, 26, 166, 31, 0, // Skip to: 19231
+/* 11129 */   MCD_OPC_Decode, 180, 25, 202, 1, // Opcode: VQSUBsv4i16
+/* 11134 */   MCD_OPC_FilterValue, 243, 1, 155, 31, 0, // Skip to: 19231
+/* 11140 */   MCD_OPC_CheckPredicate, 26, 150, 31, 0, // Skip to: 19231
+/* 11145 */   MCD_OPC_Decode, 188, 25, 202, 1, // Opcode: VQSUBuv4i16
+/* 11150 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 11190
+/* 11155 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11158 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11174
+/* 11164 */   MCD_OPC_CheckPredicate, 26, 126, 31, 0, // Skip to: 19231
+/* 11169 */   MCD_OPC_Decode, 178, 25, 202, 1, // Opcode: VQSUBsv2i32
+/* 11174 */   MCD_OPC_FilterValue, 243, 1, 115, 31, 0, // Skip to: 19231
+/* 11180 */   MCD_OPC_CheckPredicate, 26, 110, 31, 0, // Skip to: 19231
+/* 11185 */   MCD_OPC_Decode, 186, 25, 202, 1, // Opcode: VQSUBuv2i32
+/* 11190 */   MCD_OPC_FilterValue, 3, 100, 31, 0, // Skip to: 19231
+/* 11195 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11198 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11214
+/* 11204 */   MCD_OPC_CheckPredicate, 26, 86, 31, 0, // Skip to: 19231
+/* 11209 */   MCD_OPC_Decode, 177, 25, 202, 1, // Opcode: VQSUBsv1i64
+/* 11214 */   MCD_OPC_FilterValue, 243, 1, 75, 31, 0, // Skip to: 19231
+/* 11220 */   MCD_OPC_CheckPredicate, 26, 70, 31, 0, // Skip to: 19231
+/* 11225 */   MCD_OPC_Decode, 185, 25, 202, 1, // Opcode: VQSUBuv1i64
+/* 11230 */   MCD_OPC_FilterValue, 3, 123, 0, 0, // Skip to: 11358
+/* 11235 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11238 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11278
+/* 11243 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11246 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11262
+/* 11252 */   MCD_OPC_CheckPredicate, 26, 38, 31, 0, // Skip to: 19231
+/* 11257 */   MCD_OPC_Decode, 233, 16, 202, 1, // Opcode: VCGEsv8i8
+/* 11262 */   MCD_OPC_FilterValue, 243, 1, 27, 31, 0, // Skip to: 19231
+/* 11268 */   MCD_OPC_CheckPredicate, 26, 22, 31, 0, // Skip to: 19231
+/* 11273 */   MCD_OPC_Decode, 239, 16, 202, 1, // Opcode: VCGEuv8i8
+/* 11278 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 11318
+/* 11283 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11286 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11302
+/* 11292 */   MCD_OPC_CheckPredicate, 26, 254, 30, 0, // Skip to: 19231
+/* 11297 */   MCD_OPC_Decode, 230, 16, 202, 1, // Opcode: VCGEsv4i16
+/* 11302 */   MCD_OPC_FilterValue, 243, 1, 243, 30, 0, // Skip to: 19231
+/* 11308 */   MCD_OPC_CheckPredicate, 26, 238, 30, 0, // Skip to: 19231
+/* 11313 */   MCD_OPC_Decode, 236, 16, 202, 1, // Opcode: VCGEuv4i16
+/* 11318 */   MCD_OPC_FilterValue, 2, 228, 30, 0, // Skip to: 19231
+/* 11323 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11326 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11342
+/* 11332 */   MCD_OPC_CheckPredicate, 26, 214, 30, 0, // Skip to: 19231
+/* 11337 */   MCD_OPC_Decode, 229, 16, 202, 1, // Opcode: VCGEsv2i32
+/* 11342 */   MCD_OPC_FilterValue, 243, 1, 203, 30, 0, // Skip to: 19231
+/* 11348 */   MCD_OPC_CheckPredicate, 26, 198, 30, 0, // Skip to: 19231
+/* 11353 */   MCD_OPC_Decode, 235, 16, 202, 1, // Opcode: VCGEuv2i32
+/* 11358 */   MCD_OPC_FilterValue, 4, 163, 0, 0, // Skip to: 11526
+/* 11363 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11366 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11406
+/* 11371 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11374 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11390
+/* 11380 */   MCD_OPC_CheckPredicate, 26, 166, 30, 0, // Skip to: 19231
+/* 11385 */   MCD_OPC_Decode, 150, 25, 206, 1, // Opcode: VQSHLsv8i8
+/* 11390 */   MCD_OPC_FilterValue, 243, 1, 155, 30, 0, // Skip to: 19231
+/* 11396 */   MCD_OPC_CheckPredicate, 26, 150, 30, 0, // Skip to: 19231
+/* 11401 */   MCD_OPC_Decode, 166, 25, 206, 1, // Opcode: VQSHLuv8i8
+/* 11406 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 11446
+/* 11411 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11414 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11430
+/* 11420 */   MCD_OPC_CheckPredicate, 26, 126, 30, 0, // Skip to: 19231
+/* 11425 */   MCD_OPC_Decode, 147, 25, 206, 1, // Opcode: VQSHLsv4i16
+/* 11430 */   MCD_OPC_FilterValue, 243, 1, 115, 30, 0, // Skip to: 19231
+/* 11436 */   MCD_OPC_CheckPredicate, 26, 110, 30, 0, // Skip to: 19231
+/* 11441 */   MCD_OPC_Decode, 163, 25, 206, 1, // Opcode: VQSHLuv4i16
+/* 11446 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 11486
+/* 11451 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11454 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11470
+/* 11460 */   MCD_OPC_CheckPredicate, 26, 86, 30, 0, // Skip to: 19231
+/* 11465 */   MCD_OPC_Decode, 145, 25, 206, 1, // Opcode: VQSHLsv2i32
+/* 11470 */   MCD_OPC_FilterValue, 243, 1, 75, 30, 0, // Skip to: 19231
+/* 11476 */   MCD_OPC_CheckPredicate, 26, 70, 30, 0, // Skip to: 19231
+/* 11481 */   MCD_OPC_Decode, 161, 25, 206, 1, // Opcode: VQSHLuv2i32
+/* 11486 */   MCD_OPC_FilterValue, 3, 60, 30, 0, // Skip to: 19231
+/* 11491 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11494 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11510
+/* 11500 */   MCD_OPC_CheckPredicate, 26, 46, 30, 0, // Skip to: 19231
+/* 11505 */   MCD_OPC_Decode, 144, 25, 206, 1, // Opcode: VQSHLsv1i64
+/* 11510 */   MCD_OPC_FilterValue, 243, 1, 35, 30, 0, // Skip to: 19231
+/* 11516 */   MCD_OPC_CheckPredicate, 26, 30, 30, 0, // Skip to: 19231
+/* 11521 */   MCD_OPC_Decode, 160, 25, 206, 1, // Opcode: VQSHLuv1i64
+/* 11526 */   MCD_OPC_FilterValue, 5, 163, 0, 0, // Skip to: 11694
+/* 11531 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11534 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11574
+/* 11539 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11542 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11558
+/* 11548 */   MCD_OPC_CheckPredicate, 26, 254, 29, 0, // Skip to: 19231
+/* 11553 */   MCD_OPC_Decode, 237, 24, 206, 1, // Opcode: VQRSHLsv8i8
+/* 11558 */   MCD_OPC_FilterValue, 243, 1, 243, 29, 0, // Skip to: 19231
+/* 11564 */   MCD_OPC_CheckPredicate, 26, 238, 29, 0, // Skip to: 19231
+/* 11569 */   MCD_OPC_Decode, 245, 24, 206, 1, // Opcode: VQRSHLuv8i8
+/* 11574 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 11614
+/* 11579 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11582 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11598
+/* 11588 */   MCD_OPC_CheckPredicate, 26, 214, 29, 0, // Skip to: 19231
+/* 11593 */   MCD_OPC_Decode, 234, 24, 206, 1, // Opcode: VQRSHLsv4i16
+/* 11598 */   MCD_OPC_FilterValue, 243, 1, 203, 29, 0, // Skip to: 19231
+/* 11604 */   MCD_OPC_CheckPredicate, 26, 198, 29, 0, // Skip to: 19231
+/* 11609 */   MCD_OPC_Decode, 242, 24, 206, 1, // Opcode: VQRSHLuv4i16
+/* 11614 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 11654
+/* 11619 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11622 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11638
+/* 11628 */   MCD_OPC_CheckPredicate, 26, 174, 29, 0, // Skip to: 19231
+/* 11633 */   MCD_OPC_Decode, 232, 24, 206, 1, // Opcode: VQRSHLsv2i32
+/* 11638 */   MCD_OPC_FilterValue, 243, 1, 163, 29, 0, // Skip to: 19231
+/* 11644 */   MCD_OPC_CheckPredicate, 26, 158, 29, 0, // Skip to: 19231
+/* 11649 */   MCD_OPC_Decode, 240, 24, 206, 1, // Opcode: VQRSHLuv2i32
+/* 11654 */   MCD_OPC_FilterValue, 3, 148, 29, 0, // Skip to: 19231
+/* 11659 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11662 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11678
+/* 11668 */   MCD_OPC_CheckPredicate, 26, 134, 29, 0, // Skip to: 19231
+/* 11673 */   MCD_OPC_Decode, 231, 24, 206, 1, // Opcode: VQRSHLsv1i64
+/* 11678 */   MCD_OPC_FilterValue, 243, 1, 123, 29, 0, // Skip to: 19231
+/* 11684 */   MCD_OPC_CheckPredicate, 26, 118, 29, 0, // Skip to: 19231
+/* 11689 */   MCD_OPC_Decode, 239, 24, 206, 1, // Opcode: VQRSHLuv1i64
+/* 11694 */   MCD_OPC_FilterValue, 6, 123, 0, 0, // Skip to: 11822
+/* 11699 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11702 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11742
+/* 11707 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11710 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11726
+/* 11716 */   MCD_OPC_CheckPredicate, 26, 86, 29, 0, // Skip to: 19231
+/* 11721 */   MCD_OPC_Decode, 166, 22, 202, 1, // Opcode: VMINsv8i8
+/* 11726 */   MCD_OPC_FilterValue, 243, 1, 75, 29, 0, // Skip to: 19231
+/* 11732 */   MCD_OPC_CheckPredicate, 26, 70, 29, 0, // Skip to: 19231
+/* 11737 */   MCD_OPC_Decode, 172, 22, 202, 1, // Opcode: VMINuv8i8
+/* 11742 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 11782
+/* 11747 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11750 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11766
+/* 11756 */   MCD_OPC_CheckPredicate, 26, 46, 29, 0, // Skip to: 19231
+/* 11761 */   MCD_OPC_Decode, 163, 22, 202, 1, // Opcode: VMINsv4i16
+/* 11766 */   MCD_OPC_FilterValue, 243, 1, 35, 29, 0, // Skip to: 19231
+/* 11772 */   MCD_OPC_CheckPredicate, 26, 30, 29, 0, // Skip to: 19231
+/* 11777 */   MCD_OPC_Decode, 169, 22, 202, 1, // Opcode: VMINuv4i16
+/* 11782 */   MCD_OPC_FilterValue, 2, 20, 29, 0, // Skip to: 19231
+/* 11787 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11790 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11806
+/* 11796 */   MCD_OPC_CheckPredicate, 26, 6, 29, 0, // Skip to: 19231
+/* 11801 */   MCD_OPC_Decode, 162, 22, 202, 1, // Opcode: VMINsv2i32
+/* 11806 */   MCD_OPC_FilterValue, 243, 1, 251, 28, 0, // Skip to: 19231
+/* 11812 */   MCD_OPC_CheckPredicate, 26, 246, 28, 0, // Skip to: 19231
+/* 11817 */   MCD_OPC_Decode, 168, 22, 202, 1, // Opcode: VMINuv2i32
+/* 11822 */   MCD_OPC_FilterValue, 7, 123, 0, 0, // Skip to: 11950
+/* 11827 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11830 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11870
+/* 11835 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11838 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11854
+/* 11844 */   MCD_OPC_CheckPredicate, 26, 214, 28, 0, // Skip to: 19231
+/* 11849 */   MCD_OPC_Decode, 228, 15, 210, 1, // Opcode: VABAsv8i8
+/* 11854 */   MCD_OPC_FilterValue, 243, 1, 203, 28, 0, // Skip to: 19231
+/* 11860 */   MCD_OPC_CheckPredicate, 26, 198, 28, 0, // Skip to: 19231
+/* 11865 */   MCD_OPC_Decode, 234, 15, 210, 1, // Opcode: VABAuv8i8
+/* 11870 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 11910
+/* 11875 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11878 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11894
+/* 11884 */   MCD_OPC_CheckPredicate, 26, 174, 28, 0, // Skip to: 19231
+/* 11889 */   MCD_OPC_Decode, 225, 15, 210, 1, // Opcode: VABAsv4i16
+/* 11894 */   MCD_OPC_FilterValue, 243, 1, 163, 28, 0, // Skip to: 19231
+/* 11900 */   MCD_OPC_CheckPredicate, 26, 158, 28, 0, // Skip to: 19231
+/* 11905 */   MCD_OPC_Decode, 231, 15, 210, 1, // Opcode: VABAuv4i16
+/* 11910 */   MCD_OPC_FilterValue, 2, 148, 28, 0, // Skip to: 19231
+/* 11915 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11918 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11934
+/* 11924 */   MCD_OPC_CheckPredicate, 26, 134, 28, 0, // Skip to: 19231
+/* 11929 */   MCD_OPC_Decode, 224, 15, 210, 1, // Opcode: VABAsv2i32
+/* 11934 */   MCD_OPC_FilterValue, 243, 1, 123, 28, 0, // Skip to: 19231
+/* 11940 */   MCD_OPC_CheckPredicate, 26, 118, 28, 0, // Skip to: 19231
+/* 11945 */   MCD_OPC_Decode, 230, 15, 210, 1, // Opcode: VABAuv2i32
+/* 11950 */   MCD_OPC_FilterValue, 8, 123, 0, 0, // Skip to: 12078
+/* 11955 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11958 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 11998
+/* 11963 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 11966 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 11982
+/* 11972 */   MCD_OPC_CheckPredicate, 26, 86, 28, 0, // Skip to: 19231
+/* 11977 */   MCD_OPC_Decode, 183, 30, 202, 1, // Opcode: VTSTv8i8
+/* 11982 */   MCD_OPC_FilterValue, 243, 1, 75, 28, 0, // Skip to: 19231
+/* 11988 */   MCD_OPC_CheckPredicate, 26, 70, 28, 0, // Skip to: 19231
+/* 11993 */   MCD_OPC_Decode, 213, 16, 202, 1, // Opcode: VCEQv8i8
+/* 11998 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 12038
+/* 12003 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12006 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12022
+/* 12012 */   MCD_OPC_CheckPredicate, 26, 46, 28, 0, // Skip to: 19231
+/* 12017 */   MCD_OPC_Decode, 180, 30, 202, 1, // Opcode: VTSTv4i16
+/* 12022 */   MCD_OPC_FilterValue, 243, 1, 35, 28, 0, // Skip to: 19231
+/* 12028 */   MCD_OPC_CheckPredicate, 26, 30, 28, 0, // Skip to: 19231
+/* 12033 */   MCD_OPC_Decode, 210, 16, 202, 1, // Opcode: VCEQv4i16
+/* 12038 */   MCD_OPC_FilterValue, 2, 20, 28, 0, // Skip to: 19231
+/* 12043 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12046 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12062
+/* 12052 */   MCD_OPC_CheckPredicate, 26, 6, 28, 0, // Skip to: 19231
+/* 12057 */   MCD_OPC_Decode, 179, 30, 202, 1, // Opcode: VTSTv2i32
+/* 12062 */   MCD_OPC_FilterValue, 243, 1, 251, 27, 0, // Skip to: 19231
+/* 12068 */   MCD_OPC_CheckPredicate, 26, 246, 27, 0, // Skip to: 19231
+/* 12073 */   MCD_OPC_Decode, 209, 16, 202, 1, // Opcode: VCEQv2i32
+/* 12078 */   MCD_OPC_FilterValue, 9, 89, 0, 0, // Skip to: 12172
+/* 12083 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12086 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 12126
+/* 12091 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12094 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12110
+/* 12100 */   MCD_OPC_CheckPredicate, 26, 214, 27, 0, // Skip to: 19231
+/* 12105 */   MCD_OPC_Decode, 195, 23, 202, 1, // Opcode: VMULv8i8
+/* 12110 */   MCD_OPC_FilterValue, 243, 1, 203, 27, 0, // Skip to: 19231
+/* 12116 */   MCD_OPC_CheckPredicate, 26, 198, 27, 0, // Skip to: 19231
+/* 12121 */   MCD_OPC_Decode, 180, 23, 202, 1, // Opcode: VMULpd
+/* 12126 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 12149
+/* 12131 */   MCD_OPC_CheckPredicate, 26, 183, 27, 0, // Skip to: 19231
+/* 12136 */   MCD_OPC_CheckField, 24, 8, 242, 1, 175, 27, 0, // Skip to: 19231
+/* 12144 */   MCD_OPC_Decode, 192, 23, 202, 1, // Opcode: VMULv4i16
+/* 12149 */   MCD_OPC_FilterValue, 2, 165, 27, 0, // Skip to: 19231
+/* 12154 */   MCD_OPC_CheckPredicate, 26, 160, 27, 0, // Skip to: 19231
+/* 12159 */   MCD_OPC_CheckField, 24, 8, 242, 1, 152, 27, 0, // Skip to: 19231
+/* 12167 */   MCD_OPC_Decode, 191, 23, 202, 1, // Opcode: VMULv2i32
+/* 12172 */   MCD_OPC_FilterValue, 10, 123, 0, 0, // Skip to: 12300
+/* 12177 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12180 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 12220
+/* 12185 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12188 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12204
+/* 12194 */   MCD_OPC_CheckPredicate, 26, 120, 27, 0, // Skip to: 19231
+/* 12199 */   MCD_OPC_Decode, 145, 24, 202, 1, // Opcode: VPMINs8
+/* 12204 */   MCD_OPC_FilterValue, 243, 1, 109, 27, 0, // Skip to: 19231
+/* 12210 */   MCD_OPC_CheckPredicate, 26, 104, 27, 0, // Skip to: 19231
+/* 12215 */   MCD_OPC_Decode, 148, 24, 202, 1, // Opcode: VPMINu8
+/* 12220 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 12260
+/* 12225 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12228 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12244
+/* 12234 */   MCD_OPC_CheckPredicate, 26, 80, 27, 0, // Skip to: 19231
+/* 12239 */   MCD_OPC_Decode, 143, 24, 202, 1, // Opcode: VPMINs16
+/* 12244 */   MCD_OPC_FilterValue, 243, 1, 69, 27, 0, // Skip to: 19231
+/* 12250 */   MCD_OPC_CheckPredicate, 26, 64, 27, 0, // Skip to: 19231
+/* 12255 */   MCD_OPC_Decode, 146, 24, 202, 1, // Opcode: VPMINu16
+/* 12260 */   MCD_OPC_FilterValue, 2, 54, 27, 0, // Skip to: 19231
+/* 12265 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12268 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12284
+/* 12274 */   MCD_OPC_CheckPredicate, 26, 40, 27, 0, // Skip to: 19231
+/* 12279 */   MCD_OPC_Decode, 144, 24, 202, 1, // Opcode: VPMINs32
+/* 12284 */   MCD_OPC_FilterValue, 243, 1, 29, 27, 0, // Skip to: 19231
+/* 12290 */   MCD_OPC_CheckPredicate, 26, 24, 27, 0, // Skip to: 19231
+/* 12295 */   MCD_OPC_Decode, 147, 24, 202, 1, // Opcode: VPMINu32
+/* 12300 */   MCD_OPC_FilterValue, 11, 106, 0, 0, // Skip to: 12411
+/* 12305 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12308 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 12331
+/* 12313 */   MCD_OPC_CheckPredicate, 26, 1, 27, 0, // Skip to: 19231
+/* 12318 */   MCD_OPC_CheckField, 24, 8, 242, 1, 249, 26, 0, // Skip to: 19231
+/* 12326 */   MCD_OPC_Decode, 132, 24, 202, 1, // Opcode: VPADDi8
+/* 12331 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 12371
+/* 12336 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12339 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12355
+/* 12345 */   MCD_OPC_CheckPredicate, 26, 225, 26, 0, // Skip to: 19231
+/* 12350 */   MCD_OPC_Decode, 130, 24, 202, 1, // Opcode: VPADDi16
+/* 12355 */   MCD_OPC_FilterValue, 243, 1, 214, 26, 0, // Skip to: 19231
+/* 12361 */   MCD_OPC_CheckPredicate, 28, 209, 26, 0, // Skip to: 19231
+/* 12366 */   MCD_OPC_Decode, 211, 24, 210, 1, // Opcode: VQRDMLAHv4i16
+/* 12371 */   MCD_OPC_FilterValue, 2, 199, 26, 0, // Skip to: 19231
+/* 12376 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12379 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12395
+/* 12385 */   MCD_OPC_CheckPredicate, 26, 185, 26, 0, // Skip to: 19231
+/* 12390 */   MCD_OPC_Decode, 131, 24, 202, 1, // Opcode: VPADDi32
+/* 12395 */   MCD_OPC_FilterValue, 243, 1, 174, 26, 0, // Skip to: 19231
+/* 12401 */   MCD_OPC_CheckPredicate, 28, 169, 26, 0, // Skip to: 19231
+/* 12406 */   MCD_OPC_Decode, 210, 24, 210, 1, // Opcode: VQRDMLAHv2i32
+/* 12411 */   MCD_OPC_FilterValue, 12, 129, 0, 0, // Skip to: 12545
+/* 12416 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12419 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 12442
+/* 12424 */   MCD_OPC_CheckPredicate, 32, 146, 26, 0, // Skip to: 19231
+/* 12429 */   MCD_OPC_CheckField, 24, 8, 242, 1, 138, 26, 0, // Skip to: 19231
+/* 12437 */   MCD_OPC_Decode, 205, 18, 210, 1, // Opcode: VFMAfd
+/* 12442 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 12482
+/* 12447 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12450 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12466
+/* 12456 */   MCD_OPC_CheckPredicate, 27, 114, 26, 0, // Skip to: 19231
+/* 12461 */   MCD_OPC_Decode, 207, 18, 210, 1, // Opcode: VFMAhd
+/* 12466 */   MCD_OPC_FilterValue, 243, 1, 103, 26, 0, // Skip to: 19231
+/* 12472 */   MCD_OPC_CheckPredicate, 28, 98, 26, 0, // Skip to: 19231
+/* 12477 */   MCD_OPC_Decode, 219, 24, 210, 1, // Opcode: VQRDMLSHv4i16
+/* 12482 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 12522
+/* 12487 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12490 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12506
+/* 12496 */   MCD_OPC_CheckPredicate, 32, 74, 26, 0, // Skip to: 19231
+/* 12501 */   MCD_OPC_Decode, 216, 18, 210, 1, // Opcode: VFMSfd
+/* 12506 */   MCD_OPC_FilterValue, 243, 1, 63, 26, 0, // Skip to: 19231
+/* 12512 */   MCD_OPC_CheckPredicate, 28, 58, 26, 0, // Skip to: 19231
+/* 12517 */   MCD_OPC_Decode, 218, 24, 210, 1, // Opcode: VQRDMLSHv2i32
+/* 12522 */   MCD_OPC_FilterValue, 3, 48, 26, 0, // Skip to: 19231
+/* 12527 */   MCD_OPC_CheckPredicate, 27, 43, 26, 0, // Skip to: 19231
+/* 12532 */   MCD_OPC_CheckField, 24, 8, 242, 1, 35, 26, 0, // Skip to: 19231
+/* 12540 */   MCD_OPC_Decode, 218, 18, 210, 1, // Opcode: VFMShd
+/* 12545 */   MCD_OPC_FilterValue, 13, 129, 0, 0, // Skip to: 12679
+/* 12550 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12553 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 12593
+/* 12558 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12561 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12577
+/* 12567 */   MCD_OPC_CheckPredicate, 26, 3, 26, 0, // Skip to: 19231
+/* 12572 */   MCD_OPC_Decode, 186, 22, 210, 1, // Opcode: VMLAfd
+/* 12577 */   MCD_OPC_FilterValue, 243, 1, 248, 25, 0, // Skip to: 19231
+/* 12583 */   MCD_OPC_CheckPredicate, 26, 243, 25, 0, // Skip to: 19231
+/* 12588 */   MCD_OPC_Decode, 176, 23, 202, 1, // Opcode: VMULfd
+/* 12593 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 12633
+/* 12598 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 12601 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 12617
+/* 12607 */   MCD_OPC_CheckPredicate, 27, 219, 25, 0, // Skip to: 19231
+/* 12612 */   MCD_OPC_Decode, 188, 22, 210, 1, // Opcode: VMLAhd
+/* 12617 */   MCD_OPC_FilterValue, 243, 1, 208, 25, 0, // Skip to: 19231
+/* 12623 */   MCD_OPC_CheckPredicate, 27, 203, 25, 0, // Skip to: 19231
+/* 12628 */   MCD_OPC_Decode, 178, 23, 202, 1, // Opcode: VMULhd
+/* 12633 */   MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 12656
+/* 12638 */   MCD_OPC_CheckPredicate, 26, 188, 25, 0, // Skip to: 19231
+/* 12643 */   MCD_OPC_CheckField, 24, 8, 242, 1, 180, 25, 0, // Skip to: 19231
+/* 12651 */   MCD_OPC_Decode, 217, 22, 210, 1, // Opcode: VMLSfd
+/* 12656 */   MCD_OPC_FilterValue, 3, 170, 25, 0, // Skip to: 19231
+/* 12661 */   MCD_OPC_CheckPredicate, 27, 165, 25, 0, // Skip to: 19231
+/* 12666 */   MCD_OPC_CheckField, 24, 8, 242, 1, 157, 25, 0, // Skip to: 19231
+/* 12674 */   MCD_OPC_Decode, 219, 22, 210, 1, // Opcode: VMLShd
+/* 12679 */   MCD_OPC_FilterValue, 14, 95, 0, 0, // Skip to: 12779
+/* 12684 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12687 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 12710
+/* 12692 */   MCD_OPC_CheckPredicate, 26, 134, 25, 0, // Skip to: 19231
+/* 12697 */   MCD_OPC_CheckField, 24, 8, 243, 1, 126, 25, 0, // Skip to: 19231
+/* 12705 */   MCD_OPC_Decode, 142, 16, 202, 1, // Opcode: VACGEfd
+/* 12710 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 12733
+/* 12715 */   MCD_OPC_CheckPredicate, 27, 111, 25, 0, // Skip to: 19231
+/* 12720 */   MCD_OPC_CheckField, 24, 8, 243, 1, 103, 25, 0, // Skip to: 19231
+/* 12728 */   MCD_OPC_Decode, 144, 16, 202, 1, // Opcode: VACGEhd
+/* 12733 */   MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 12756
+/* 12738 */   MCD_OPC_CheckPredicate, 26, 88, 25, 0, // Skip to: 19231
+/* 12743 */   MCD_OPC_CheckField, 24, 8, 243, 1, 80, 25, 0, // Skip to: 19231
+/* 12751 */   MCD_OPC_Decode, 146, 16, 202, 1, // Opcode: VACGTfd
+/* 12756 */   MCD_OPC_FilterValue, 3, 70, 25, 0, // Skip to: 19231
+/* 12761 */   MCD_OPC_CheckPredicate, 27, 65, 25, 0, // Skip to: 19231
+/* 12766 */   MCD_OPC_CheckField, 24, 8, 243, 1, 57, 25, 0, // Skip to: 19231
+/* 12774 */   MCD_OPC_Decode, 148, 16, 202, 1, // Opcode: VACGThd
+/* 12779 */   MCD_OPC_FilterValue, 15, 47, 25, 0, // Skip to: 19231
+/* 12784 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 12787 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 12810
+/* 12792 */   MCD_OPC_CheckPredicate, 26, 34, 25, 0, // Skip to: 19231
+/* 12797 */   MCD_OPC_CheckField, 24, 8, 242, 1, 26, 25, 0, // Skip to: 19231
+/* 12805 */   MCD_OPC_Decode, 201, 25, 202, 1, // Opcode: VRECPSfd
+/* 12810 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 12833
+/* 12815 */   MCD_OPC_CheckPredicate, 27, 11, 25, 0, // Skip to: 19231
+/* 12820 */   MCD_OPC_CheckField, 24, 8, 242, 1, 3, 25, 0, // Skip to: 19231
+/* 12828 */   MCD_OPC_Decode, 203, 25, 202, 1, // Opcode: VRECPShd
+/* 12833 */   MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 12856
+/* 12838 */   MCD_OPC_CheckPredicate, 26, 244, 24, 0, // Skip to: 19231
+/* 12843 */   MCD_OPC_CheckField, 24, 8, 242, 1, 236, 24, 0, // Skip to: 19231
+/* 12851 */   MCD_OPC_Decode, 187, 26, 202, 1, // Opcode: VRSQRTSfd
+/* 12856 */   MCD_OPC_FilterValue, 3, 226, 24, 0, // Skip to: 19231
+/* 12861 */   MCD_OPC_CheckPredicate, 27, 221, 24, 0, // Skip to: 19231
+/* 12866 */   MCD_OPC_CheckField, 24, 8, 242, 1, 213, 24, 0, // Skip to: 19231
+/* 12874 */   MCD_OPC_Decode, 189, 26, 202, 1, // Opcode: VRSQRTShd
+/* 12879 */   MCD_OPC_FilterValue, 1, 203, 24, 0, // Skip to: 19231
+/* 12884 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 12887 */   MCD_OPC_FilterValue, 0, 209, 7, 0, // Skip to: 14893
+/* 12892 */   MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
+/* 12895 */   MCD_OPC_FilterValue, 121, 187, 24, 0, // Skip to: 19231
+/* 12900 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 12903 */   MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 13047
+/* 12908 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 12911 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13009
+/* 12916 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 12919 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 12971
+/* 12924 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 12927 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 12949
+/* 12932 */   MCD_OPC_CheckPredicate, 26, 231, 6, 0, // Skip to: 14704
+/* 12937 */   MCD_OPC_CheckField, 19, 1, 1, 224, 6, 0, // Skip to: 14704
+/* 12944 */   MCD_OPC_Decode, 146, 27, 247, 1, // Opcode: VSHRsv8i8
+/* 12949 */   MCD_OPC_FilterValue, 1, 214, 6, 0, // Skip to: 14704
+/* 12954 */   MCD_OPC_CheckPredicate, 26, 209, 6, 0, // Skip to: 14704
+/* 12959 */   MCD_OPC_CheckField, 19, 1, 1, 202, 6, 0, // Skip to: 14704
+/* 12966 */   MCD_OPC_Decode, 154, 27, 247, 1, // Opcode: VSHRuv8i8
+/* 12971 */   MCD_OPC_FilterValue, 1, 192, 6, 0, // Skip to: 14704
+/* 12976 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 12979 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 12994
+/* 12984 */   MCD_OPC_CheckPredicate, 26, 179, 6, 0, // Skip to: 14704
+/* 12989 */   MCD_OPC_Decode, 143, 27, 248, 1, // Opcode: VSHRsv4i16
+/* 12994 */   MCD_OPC_FilterValue, 1, 169, 6, 0, // Skip to: 14704
+/* 12999 */   MCD_OPC_CheckPredicate, 26, 164, 6, 0, // Skip to: 14704
+/* 13004 */   MCD_OPC_Decode, 151, 27, 248, 1, // Opcode: VSHRuv4i16
+/* 13009 */   MCD_OPC_FilterValue, 1, 154, 6, 0, // Skip to: 14704
+/* 13014 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13017 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13032
+/* 13022 */   MCD_OPC_CheckPredicate, 26, 141, 6, 0, // Skip to: 14704
+/* 13027 */   MCD_OPC_Decode, 141, 27, 249, 1, // Opcode: VSHRsv2i32
+/* 13032 */   MCD_OPC_FilterValue, 1, 131, 6, 0, // Skip to: 14704
+/* 13037 */   MCD_OPC_CheckPredicate, 26, 126, 6, 0, // Skip to: 14704
+/* 13042 */   MCD_OPC_Decode, 149, 27, 249, 1, // Opcode: VSHRuv2i32
+/* 13047 */   MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 13191
+/* 13052 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13055 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13153
+/* 13060 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13063 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13115
+/* 13068 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13071 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13093
+/* 13076 */   MCD_OPC_CheckPredicate, 26, 87, 6, 0, // Skip to: 14704
+/* 13081 */   MCD_OPC_CheckField, 19, 1, 1, 80, 6, 0, // Skip to: 14704
+/* 13088 */   MCD_OPC_Decode, 183, 27, 250, 1, // Opcode: VSRAsv8i8
+/* 13093 */   MCD_OPC_FilterValue, 1, 70, 6, 0, // Skip to: 14704
+/* 13098 */   MCD_OPC_CheckPredicate, 26, 65, 6, 0, // Skip to: 14704
+/* 13103 */   MCD_OPC_CheckField, 19, 1, 1, 58, 6, 0, // Skip to: 14704
+/* 13110 */   MCD_OPC_Decode, 191, 27, 250, 1, // Opcode: VSRAuv8i8
+/* 13115 */   MCD_OPC_FilterValue, 1, 48, 6, 0, // Skip to: 14704
+/* 13120 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13123 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13138
+/* 13128 */   MCD_OPC_CheckPredicate, 26, 35, 6, 0, // Skip to: 14704
+/* 13133 */   MCD_OPC_Decode, 180, 27, 251, 1, // Opcode: VSRAsv4i16
+/* 13138 */   MCD_OPC_FilterValue, 1, 25, 6, 0, // Skip to: 14704
+/* 13143 */   MCD_OPC_CheckPredicate, 26, 20, 6, 0, // Skip to: 14704
+/* 13148 */   MCD_OPC_Decode, 188, 27, 251, 1, // Opcode: VSRAuv4i16
+/* 13153 */   MCD_OPC_FilterValue, 1, 10, 6, 0, // Skip to: 14704
+/* 13158 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13161 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13176
+/* 13166 */   MCD_OPC_CheckPredicate, 26, 253, 5, 0, // Skip to: 14704
+/* 13171 */   MCD_OPC_Decode, 178, 27, 252, 1, // Opcode: VSRAsv2i32
+/* 13176 */   MCD_OPC_FilterValue, 1, 243, 5, 0, // Skip to: 14704
+/* 13181 */   MCD_OPC_CheckPredicate, 26, 238, 5, 0, // Skip to: 14704
+/* 13186 */   MCD_OPC_Decode, 186, 27, 252, 1, // Opcode: VSRAuv2i32
+/* 13191 */   MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 13335
+/* 13196 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13199 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13297
+/* 13204 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13207 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13259
+/* 13212 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13215 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13237
+/* 13220 */   MCD_OPC_CheckPredicate, 26, 199, 5, 0, // Skip to: 14704
+/* 13225 */   MCD_OPC_CheckField, 19, 1, 1, 192, 5, 0, // Skip to: 14704
+/* 13232 */   MCD_OPC_Decode, 172, 26, 247, 1, // Opcode: VRSHRsv8i8
+/* 13237 */   MCD_OPC_FilterValue, 1, 182, 5, 0, // Skip to: 14704
+/* 13242 */   MCD_OPC_CheckPredicate, 26, 177, 5, 0, // Skip to: 14704
+/* 13247 */   MCD_OPC_CheckField, 19, 1, 1, 170, 5, 0, // Skip to: 14704
+/* 13254 */   MCD_OPC_Decode, 180, 26, 247, 1, // Opcode: VRSHRuv8i8
+/* 13259 */   MCD_OPC_FilterValue, 1, 160, 5, 0, // Skip to: 14704
+/* 13264 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13267 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13282
+/* 13272 */   MCD_OPC_CheckPredicate, 26, 147, 5, 0, // Skip to: 14704
+/* 13277 */   MCD_OPC_Decode, 169, 26, 248, 1, // Opcode: VRSHRsv4i16
+/* 13282 */   MCD_OPC_FilterValue, 1, 137, 5, 0, // Skip to: 14704
+/* 13287 */   MCD_OPC_CheckPredicate, 26, 132, 5, 0, // Skip to: 14704
+/* 13292 */   MCD_OPC_Decode, 177, 26, 248, 1, // Opcode: VRSHRuv4i16
+/* 13297 */   MCD_OPC_FilterValue, 1, 122, 5, 0, // Skip to: 14704
+/* 13302 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13305 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13320
+/* 13310 */   MCD_OPC_CheckPredicate, 26, 109, 5, 0, // Skip to: 14704
+/* 13315 */   MCD_OPC_Decode, 167, 26, 249, 1, // Opcode: VRSHRsv2i32
+/* 13320 */   MCD_OPC_FilterValue, 1, 99, 5, 0, // Skip to: 14704
+/* 13325 */   MCD_OPC_CheckPredicate, 26, 94, 5, 0, // Skip to: 14704
+/* 13330 */   MCD_OPC_Decode, 175, 26, 249, 1, // Opcode: VRSHRuv2i32
+/* 13335 */   MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 13479
+/* 13340 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13343 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13441
+/* 13348 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13351 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13403
+/* 13356 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13359 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13381
+/* 13364 */   MCD_OPC_CheckPredicate, 26, 55, 5, 0, // Skip to: 14704
+/* 13369 */   MCD_OPC_CheckField, 19, 1, 1, 48, 5, 0, // Skip to: 14704
+/* 13376 */   MCD_OPC_Decode, 198, 26, 250, 1, // Opcode: VRSRAsv8i8
+/* 13381 */   MCD_OPC_FilterValue, 1, 38, 5, 0, // Skip to: 14704
+/* 13386 */   MCD_OPC_CheckPredicate, 26, 33, 5, 0, // Skip to: 14704
+/* 13391 */   MCD_OPC_CheckField, 19, 1, 1, 26, 5, 0, // Skip to: 14704
+/* 13398 */   MCD_OPC_Decode, 206, 26, 250, 1, // Opcode: VRSRAuv8i8
+/* 13403 */   MCD_OPC_FilterValue, 1, 16, 5, 0, // Skip to: 14704
+/* 13408 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13411 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13426
+/* 13416 */   MCD_OPC_CheckPredicate, 26, 3, 5, 0, // Skip to: 14704
+/* 13421 */   MCD_OPC_Decode, 195, 26, 251, 1, // Opcode: VRSRAsv4i16
+/* 13426 */   MCD_OPC_FilterValue, 1, 249, 4, 0, // Skip to: 14704
+/* 13431 */   MCD_OPC_CheckPredicate, 26, 244, 4, 0, // Skip to: 14704
+/* 13436 */   MCD_OPC_Decode, 203, 26, 251, 1, // Opcode: VRSRAuv4i16
+/* 13441 */   MCD_OPC_FilterValue, 1, 234, 4, 0, // Skip to: 14704
+/* 13446 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13449 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13464
+/* 13454 */   MCD_OPC_CheckPredicate, 26, 221, 4, 0, // Skip to: 14704
+/* 13459 */   MCD_OPC_Decode, 193, 26, 252, 1, // Opcode: VRSRAsv2i32
+/* 13464 */   MCD_OPC_FilterValue, 1, 211, 4, 0, // Skip to: 14704
+/* 13469 */   MCD_OPC_CheckPredicate, 26, 206, 4, 0, // Skip to: 14704
+/* 13474 */   MCD_OPC_Decode, 201, 26, 252, 1, // Opcode: VRSRAuv2i32
+/* 13479 */   MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 13568
+/* 13484 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13487 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 13546
+/* 13492 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13495 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13524
+/* 13500 */   MCD_OPC_CheckPredicate, 26, 175, 4, 0, // Skip to: 14704
+/* 13505 */   MCD_OPC_CheckField, 24, 1, 1, 168, 4, 0, // Skip to: 14704
+/* 13512 */   MCD_OPC_CheckField, 19, 1, 1, 161, 4, 0, // Skip to: 14704
+/* 13519 */   MCD_OPC_Decode, 199, 27, 250, 1, // Opcode: VSRIv8i8
+/* 13524 */   MCD_OPC_FilterValue, 1, 151, 4, 0, // Skip to: 14704
+/* 13529 */   MCD_OPC_CheckPredicate, 26, 146, 4, 0, // Skip to: 14704
+/* 13534 */   MCD_OPC_CheckField, 24, 1, 1, 139, 4, 0, // Skip to: 14704
+/* 13541 */   MCD_OPC_Decode, 196, 27, 251, 1, // Opcode: VSRIv4i16
+/* 13546 */   MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 14704
+/* 13551 */   MCD_OPC_CheckPredicate, 26, 124, 4, 0, // Skip to: 14704
+/* 13556 */   MCD_OPC_CheckField, 24, 1, 1, 117, 4, 0, // Skip to: 14704
+/* 13563 */   MCD_OPC_Decode, 194, 27, 252, 1, // Opcode: VSRIv2i32
+/* 13568 */   MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 13712
+/* 13573 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13576 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13674
+/* 13581 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13584 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13636
+/* 13589 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13592 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13614
+/* 13597 */   MCD_OPC_CheckPredicate, 26, 78, 4, 0, // Skip to: 14704
+/* 13602 */   MCD_OPC_CheckField, 19, 1, 1, 71, 4, 0, // Skip to: 14704
+/* 13609 */   MCD_OPC_Decode, 247, 26, 253, 1, // Opcode: VSHLiv8i8
+/* 13614 */   MCD_OPC_FilterValue, 1, 61, 4, 0, // Skip to: 14704
+/* 13619 */   MCD_OPC_CheckPredicate, 26, 56, 4, 0, // Skip to: 14704
+/* 13624 */   MCD_OPC_CheckField, 19, 1, 1, 49, 4, 0, // Skip to: 14704
+/* 13631 */   MCD_OPC_Decode, 168, 27, 254, 1, // Opcode: VSLIv8i8
+/* 13636 */   MCD_OPC_FilterValue, 1, 39, 4, 0, // Skip to: 14704
+/* 13641 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13644 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13659
+/* 13649 */   MCD_OPC_CheckPredicate, 26, 26, 4, 0, // Skip to: 14704
+/* 13654 */   MCD_OPC_Decode, 244, 26, 255, 1, // Opcode: VSHLiv4i16
+/* 13659 */   MCD_OPC_FilterValue, 1, 16, 4, 0, // Skip to: 14704
+/* 13664 */   MCD_OPC_CheckPredicate, 26, 11, 4, 0, // Skip to: 14704
+/* 13669 */   MCD_OPC_Decode, 165, 27, 128, 2, // Opcode: VSLIv4i16
+/* 13674 */   MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 14704
+/* 13679 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13682 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13697
+/* 13687 */   MCD_OPC_CheckPredicate, 26, 244, 3, 0, // Skip to: 14704
+/* 13692 */   MCD_OPC_Decode, 242, 26, 129, 2, // Opcode: VSHLiv2i32
+/* 13697 */   MCD_OPC_FilterValue, 1, 234, 3, 0, // Skip to: 14704
+/* 13702 */   MCD_OPC_CheckPredicate, 26, 229, 3, 0, // Skip to: 14704
+/* 13707 */   MCD_OPC_Decode, 163, 27, 130, 2, // Opcode: VSLIv2i32
+/* 13712 */   MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 13801
+/* 13717 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13720 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 13779
+/* 13725 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13728 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 13757
+/* 13733 */   MCD_OPC_CheckPredicate, 26, 198, 3, 0, // Skip to: 14704
+/* 13738 */   MCD_OPC_CheckField, 24, 1, 1, 191, 3, 0, // Skip to: 14704
+/* 13745 */   MCD_OPC_CheckField, 19, 1, 1, 184, 3, 0, // Skip to: 14704
+/* 13752 */   MCD_OPC_Decode, 142, 25, 253, 1, // Opcode: VQSHLsuv8i8
+/* 13757 */   MCD_OPC_FilterValue, 1, 174, 3, 0, // Skip to: 14704
+/* 13762 */   MCD_OPC_CheckPredicate, 26, 169, 3, 0, // Skip to: 14704
+/* 13767 */   MCD_OPC_CheckField, 24, 1, 1, 162, 3, 0, // Skip to: 14704
+/* 13774 */   MCD_OPC_Decode, 139, 25, 255, 1, // Opcode: VQSHLsuv4i16
+/* 13779 */   MCD_OPC_FilterValue, 1, 152, 3, 0, // Skip to: 14704
+/* 13784 */   MCD_OPC_CheckPredicate, 26, 147, 3, 0, // Skip to: 14704
+/* 13789 */   MCD_OPC_CheckField, 24, 1, 1, 140, 3, 0, // Skip to: 14704
+/* 13796 */   MCD_OPC_Decode, 137, 25, 129, 2, // Opcode: VQSHLsuv2i32
+/* 13801 */   MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 13945
+/* 13806 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13809 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 13907
+/* 13814 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13817 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 13869
+/* 13822 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13825 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13847
+/* 13830 */   MCD_OPC_CheckPredicate, 26, 101, 3, 0, // Skip to: 14704
+/* 13835 */   MCD_OPC_CheckField, 19, 1, 1, 94, 3, 0, // Skip to: 14704
+/* 13842 */   MCD_OPC_Decode, 134, 25, 253, 1, // Opcode: VQSHLsiv8i8
+/* 13847 */   MCD_OPC_FilterValue, 1, 84, 3, 0, // Skip to: 14704
+/* 13852 */   MCD_OPC_CheckPredicate, 26, 79, 3, 0, // Skip to: 14704
+/* 13857 */   MCD_OPC_CheckField, 19, 1, 1, 72, 3, 0, // Skip to: 14704
+/* 13864 */   MCD_OPC_Decode, 158, 25, 253, 1, // Opcode: VQSHLuiv8i8
+/* 13869 */   MCD_OPC_FilterValue, 1, 62, 3, 0, // Skip to: 14704
+/* 13874 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13877 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13892
+/* 13882 */   MCD_OPC_CheckPredicate, 26, 49, 3, 0, // Skip to: 14704
+/* 13887 */   MCD_OPC_Decode, 131, 25, 255, 1, // Opcode: VQSHLsiv4i16
+/* 13892 */   MCD_OPC_FilterValue, 1, 39, 3, 0, // Skip to: 14704
+/* 13897 */   MCD_OPC_CheckPredicate, 26, 34, 3, 0, // Skip to: 14704
+/* 13902 */   MCD_OPC_Decode, 155, 25, 255, 1, // Opcode: VQSHLuiv4i16
+/* 13907 */   MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 14704
+/* 13912 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13915 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 13930
+/* 13920 */   MCD_OPC_CheckPredicate, 26, 11, 3, 0, // Skip to: 14704
+/* 13925 */   MCD_OPC_Decode, 129, 25, 129, 2, // Opcode: VQSHLsiv2i32
+/* 13930 */   MCD_OPC_FilterValue, 1, 1, 3, 0, // Skip to: 14704
+/* 13935 */   MCD_OPC_CheckPredicate, 26, 252, 2, 0, // Skip to: 14704
+/* 13940 */   MCD_OPC_Decode, 153, 25, 129, 2, // Opcode: VQSHLuiv2i32
+/* 13945 */   MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 14089
+/* 13950 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 13953 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 14051
+/* 13958 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 13961 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 14013
+/* 13966 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 13969 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 13991
+/* 13974 */   MCD_OPC_CheckPredicate, 26, 213, 2, 0, // Skip to: 14704
+/* 13979 */   MCD_OPC_CheckField, 19, 1, 1, 206, 2, 0, // Skip to: 14704
+/* 13986 */   MCD_OPC_Decode, 138, 27, 131, 2, // Opcode: VSHRNv8i8
+/* 13991 */   MCD_OPC_FilterValue, 1, 196, 2, 0, // Skip to: 14704
+/* 13996 */   MCD_OPC_CheckPredicate, 26, 191, 2, 0, // Skip to: 14704
+/* 14001 */   MCD_OPC_CheckField, 19, 1, 1, 184, 2, 0, // Skip to: 14704
+/* 14008 */   MCD_OPC_Decode, 175, 25, 131, 2, // Opcode: VQSHRUNv8i8
+/* 14013 */   MCD_OPC_FilterValue, 1, 174, 2, 0, // Skip to: 14704
+/* 14018 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14021 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14036
+/* 14026 */   MCD_OPC_CheckPredicate, 26, 161, 2, 0, // Skip to: 14704
+/* 14031 */   MCD_OPC_Decode, 137, 27, 132, 2, // Opcode: VSHRNv4i16
+/* 14036 */   MCD_OPC_FilterValue, 1, 151, 2, 0, // Skip to: 14704
+/* 14041 */   MCD_OPC_CheckPredicate, 26, 146, 2, 0, // Skip to: 14704
+/* 14046 */   MCD_OPC_Decode, 174, 25, 132, 2, // Opcode: VQSHRUNv4i16
+/* 14051 */   MCD_OPC_FilterValue, 1, 136, 2, 0, // Skip to: 14704
+/* 14056 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14059 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14074
+/* 14064 */   MCD_OPC_CheckPredicate, 26, 123, 2, 0, // Skip to: 14704
+/* 14069 */   MCD_OPC_Decode, 136, 27, 133, 2, // Opcode: VSHRNv2i32
+/* 14074 */   MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 14704
+/* 14079 */   MCD_OPC_CheckPredicate, 26, 108, 2, 0, // Skip to: 14704
+/* 14084 */   MCD_OPC_Decode, 173, 25, 133, 2, // Opcode: VQSHRUNv2i32
+/* 14089 */   MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 14233
+/* 14094 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 14097 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 14195
+/* 14102 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 14105 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 14157
+/* 14110 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14113 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14135
+/* 14118 */   MCD_OPC_CheckPredicate, 26, 69, 2, 0, // Skip to: 14704
+/* 14123 */   MCD_OPC_CheckField, 19, 1, 1, 62, 2, 0, // Skip to: 14704
+/* 14130 */   MCD_OPC_Decode, 169, 25, 131, 2, // Opcode: VQSHRNsv8i8
+/* 14135 */   MCD_OPC_FilterValue, 1, 52, 2, 0, // Skip to: 14704
+/* 14140 */   MCD_OPC_CheckPredicate, 26, 47, 2, 0, // Skip to: 14704
+/* 14145 */   MCD_OPC_CheckField, 19, 1, 1, 40, 2, 0, // Skip to: 14704
+/* 14152 */   MCD_OPC_Decode, 172, 25, 131, 2, // Opcode: VQSHRNuv8i8
+/* 14157 */   MCD_OPC_FilterValue, 1, 30, 2, 0, // Skip to: 14704
+/* 14162 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
 /* 14165 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14180
-/* 14170 */   MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14202
-/* 14175 */   MCD_OPC_Decode, 245, 14, 161, 1, // Opcode: VORRiv2i32
-/* 14180 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14202
-/* 14185 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14202
-/* 14190 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14202
-/* 14197 */   MCD_OPC_Decode, 246, 14, 161, 1, // Opcode: VORRiv4i16
-/* 14202 */   MCD_OPC_CheckPredicate, 21, 250, 16, 0, // Skip to: 18553
-/* 14207 */   MCD_OPC_Decode, 159, 14, 161, 1, // Opcode: VMOVv2i32
-/* 14212 */   MCD_OPC_FilterValue, 1, 240, 16, 0, // Skip to: 18553
-/* 14217 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
-/* 14220 */   MCD_OPC_FilterValue, 0, 232, 16, 0, // Skip to: 18553
-/* 14225 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 14228 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14250
-/* 14233 */   MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 14295
-/* 14238 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14295
-/* 14245 */   MCD_OPC_Decode, 217, 14, 161, 1, // Opcode: VMVNv4i16
-/* 14250 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14295
-/* 14255 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
-/* 14258 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14273
-/* 14263 */   MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 14295
-/* 14268 */   MCD_OPC_Decode, 140, 8, 161, 1, // Opcode: VBICiv2i32
-/* 14273 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14295
-/* 14278 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 14295
-/* 14283 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14295
-/* 14290 */   MCD_OPC_Decode, 141, 8, 161, 1, // Opcode: VBICiv4i16
-/* 14295 */   MCD_OPC_CheckPredicate, 21, 157, 16, 0, // Skip to: 18553
-/* 14300 */   MCD_OPC_Decode, 216, 14, 161, 1, // Opcode: VMVNv2i32
-/* 14305 */   MCD_OPC_FilterValue, 1, 147, 16, 0, // Skip to: 18553
-/* 14310 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 14313 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 14353
-/* 14318 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14321 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14337
-/* 14327 */   MCD_OPC_CheckPredicate, 21, 125, 16, 0, // Skip to: 18553
-/* 14332 */   MCD_OPC_Decode, 156, 18, 162, 1, // Opcode: VSHRsv1i64
-/* 14337 */   MCD_OPC_FilterValue, 243, 1, 114, 16, 0, // Skip to: 18553
-/* 14343 */   MCD_OPC_CheckPredicate, 21, 109, 16, 0, // Skip to: 18553
-/* 14348 */   MCD_OPC_Decode, 164, 18, 162, 1, // Opcode: VSHRuv1i64
-/* 14353 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 14393
-/* 14358 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14361 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14377
-/* 14367 */   MCD_OPC_CheckPredicate, 21, 85, 16, 0, // Skip to: 18553
-/* 14372 */   MCD_OPC_Decode, 192, 18, 163, 1, // Opcode: VSRAsv1i64
-/* 14377 */   MCD_OPC_FilterValue, 243, 1, 74, 16, 0, // Skip to: 18553
-/* 14383 */   MCD_OPC_CheckPredicate, 21, 69, 16, 0, // Skip to: 18553
-/* 14388 */   MCD_OPC_Decode, 200, 18, 163, 1, // Opcode: VSRAuv1i64
-/* 14393 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 14433
-/* 14398 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14401 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14417
-/* 14407 */   MCD_OPC_CheckPredicate, 21, 45, 16, 0, // Skip to: 18553
-/* 14412 */   MCD_OPC_Decode, 184, 17, 162, 1, // Opcode: VRSHRsv1i64
-/* 14417 */   MCD_OPC_FilterValue, 243, 1, 34, 16, 0, // Skip to: 18553
-/* 14423 */   MCD_OPC_CheckPredicate, 21, 29, 16, 0, // Skip to: 18553
-/* 14428 */   MCD_OPC_Decode, 192, 17, 162, 1, // Opcode: VRSHRuv1i64
-/* 14433 */   MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 14473
-/* 14438 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14441 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14457
-/* 14447 */   MCD_OPC_CheckPredicate, 21, 5, 16, 0, // Skip to: 18553
-/* 14452 */   MCD_OPC_Decode, 210, 17, 163, 1, // Opcode: VRSRAsv1i64
-/* 14457 */   MCD_OPC_FilterValue, 243, 1, 250, 15, 0, // Skip to: 18553
-/* 14463 */   MCD_OPC_CheckPredicate, 21, 245, 15, 0, // Skip to: 18553
-/* 14468 */   MCD_OPC_Decode, 218, 17, 163, 1, // Opcode: VRSRAuv1i64
-/* 14473 */   MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 14496
-/* 14478 */   MCD_OPC_CheckPredicate, 21, 230, 15, 0, // Skip to: 18553
-/* 14483 */   MCD_OPC_CheckField, 24, 8, 243, 1, 222, 15, 0, // Skip to: 18553
-/* 14491 */   MCD_OPC_Decode, 208, 18, 163, 1, // Opcode: VSRIv1i64
-/* 14496 */   MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 14536
-/* 14501 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14504 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14520
-/* 14510 */   MCD_OPC_CheckPredicate, 21, 198, 15, 0, // Skip to: 18553
-/* 14515 */   MCD_OPC_Decode, 129, 18, 164, 1, // Opcode: VSHLiv1i64
-/* 14520 */   MCD_OPC_FilterValue, 243, 1, 187, 15, 0, // Skip to: 18553
-/* 14526 */   MCD_OPC_CheckPredicate, 21, 182, 15, 0, // Skip to: 18553
-/* 14531 */   MCD_OPC_Decode, 178, 18, 165, 1, // Opcode: VSLIv1i64
-/* 14536 */   MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 14559
-/* 14541 */   MCD_OPC_CheckPredicate, 21, 167, 15, 0, // Skip to: 18553
-/* 14546 */   MCD_OPC_CheckField, 24, 8, 243, 1, 159, 15, 0, // Skip to: 18553
-/* 14554 */   MCD_OPC_Decode, 154, 16, 164, 1, // Opcode: VQSHLsuv1i64
-/* 14559 */   MCD_OPC_FilterValue, 7, 149, 15, 0, // Skip to: 18553
-/* 14564 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14567 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14583
-/* 14573 */   MCD_OPC_CheckPredicate, 21, 135, 15, 0, // Skip to: 18553
-/* 14578 */   MCD_OPC_Decode, 146, 16, 164, 1, // Opcode: VQSHLsiv1i64
-/* 14583 */   MCD_OPC_FilterValue, 243, 1, 124, 15, 0, // Skip to: 18553
-/* 14589 */   MCD_OPC_CheckPredicate, 21, 119, 15, 0, // Skip to: 18553
-/* 14594 */   MCD_OPC_Decode, 170, 16, 164, 1, // Opcode: VQSHLuiv1i64
-/* 14599 */   MCD_OPC_FilterValue, 1, 109, 15, 0, // Skip to: 18553
-/* 14604 */   MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 14607 */   MCD_OPC_FilterValue, 0, 89, 7, 0, // Skip to: 16493
-/* 14612 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 14615 */   MCD_OPC_FilterValue, 0, 155, 0, 0, // Skip to: 14775
-/* 14620 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 14623 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14661
-/* 14628 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14631 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14646
-/* 14637 */   MCD_OPC_CheckPredicate, 21, 71, 15, 0, // Skip to: 18553
-/* 14642 */   MCD_OPC_Decode, 173, 15, 98, // Opcode: VQADDsv16i8
-/* 14646 */   MCD_OPC_FilterValue, 243, 1, 61, 15, 0, // Skip to: 18553
-/* 14652 */   MCD_OPC_CheckPredicate, 21, 56, 15, 0, // Skip to: 18553
-/* 14657 */   MCD_OPC_Decode, 181, 15, 98, // Opcode: VQADDuv16i8
-/* 14661 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14699
-/* 14666 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14669 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14684
-/* 14675 */   MCD_OPC_CheckPredicate, 21, 33, 15, 0, // Skip to: 18553
-/* 14680 */   MCD_OPC_Decode, 179, 15, 98, // Opcode: VQADDsv8i16
-/* 14684 */   MCD_OPC_FilterValue, 243, 1, 23, 15, 0, // Skip to: 18553
-/* 14690 */   MCD_OPC_CheckPredicate, 21, 18, 15, 0, // Skip to: 18553
-/* 14695 */   MCD_OPC_Decode, 187, 15, 98, // Opcode: VQADDuv8i16
-/* 14699 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14737
-/* 14704 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14707 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14722
-/* 14713 */   MCD_OPC_CheckPredicate, 21, 251, 14, 0, // Skip to: 18553
-/* 14718 */   MCD_OPC_Decode, 178, 15, 98, // Opcode: VQADDsv4i32
-/* 14722 */   MCD_OPC_FilterValue, 243, 1, 241, 14, 0, // Skip to: 18553
-/* 14728 */   MCD_OPC_CheckPredicate, 21, 236, 14, 0, // Skip to: 18553
-/* 14733 */   MCD_OPC_Decode, 186, 15, 98, // Opcode: VQADDuv4i32
-/* 14737 */   MCD_OPC_FilterValue, 3, 227, 14, 0, // Skip to: 18553
-/* 14742 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14745 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14760
-/* 14751 */   MCD_OPC_CheckPredicate, 21, 213, 14, 0, // Skip to: 18553
-/* 14756 */   MCD_OPC_Decode, 176, 15, 98, // Opcode: VQADDsv2i64
-/* 14760 */   MCD_OPC_FilterValue, 243, 1, 203, 14, 0, // Skip to: 18553
-/* 14766 */   MCD_OPC_CheckPredicate, 21, 198, 14, 0, // Skip to: 18553
-/* 14771 */   MCD_OPC_Decode, 184, 15, 98, // Opcode: VQADDuv2i64
-/* 14775 */   MCD_OPC_FilterValue, 1, 155, 0, 0, // Skip to: 14935
-/* 14780 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 14783 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14821
-/* 14788 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14791 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14806
-/* 14797 */   MCD_OPC_CheckPredicate, 21, 167, 14, 0, // Skip to: 18553
-/* 14802 */   MCD_OPC_Decode, 138, 8, 98, // Opcode: VANDq
-/* 14806 */   MCD_OPC_FilterValue, 243, 1, 157, 14, 0, // Skip to: 18553
-/* 14812 */   MCD_OPC_CheckPredicate, 21, 152, 14, 0, // Skip to: 18553
-/* 14817 */   MCD_OPC_Decode, 141, 10, 98, // Opcode: VEORq
-/* 14821 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 14859
-/* 14826 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14829 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14844
-/* 14835 */   MCD_OPC_CheckPredicate, 21, 129, 14, 0, // Skip to: 18553
-/* 14840 */   MCD_OPC_Decode, 144, 8, 98, // Opcode: VBICq
-/* 14844 */   MCD_OPC_FilterValue, 243, 1, 119, 14, 0, // Skip to: 18553
-/* 14850 */   MCD_OPC_CheckPredicate, 21, 114, 14, 0, // Skip to: 18553
-/* 14855 */   MCD_OPC_Decode, 150, 8, 106, // Opcode: VBSLq
-/* 14859 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 14897
-/* 14864 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14867 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14882
-/* 14873 */   MCD_OPC_CheckPredicate, 21, 91, 14, 0, // Skip to: 18553
-/* 14878 */   MCD_OPC_Decode, 249, 14, 98, // Opcode: VORRq
-/* 14882 */   MCD_OPC_FilterValue, 243, 1, 81, 14, 0, // Skip to: 18553
-/* 14888 */   MCD_OPC_CheckPredicate, 21, 76, 14, 0, // Skip to: 18553
-/* 14893 */   MCD_OPC_Decode, 148, 8, 106, // Opcode: VBITq
-/* 14897 */   MCD_OPC_FilterValue, 3, 67, 14, 0, // Skip to: 18553
-/* 14902 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14905 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14920
-/* 14911 */   MCD_OPC_CheckPredicate, 21, 53, 14, 0, // Skip to: 18553
-/* 14916 */   MCD_OPC_Decode, 243, 14, 98, // Opcode: VORNq
-/* 14920 */   MCD_OPC_FilterValue, 243, 1, 43, 14, 0, // Skip to: 18553
-/* 14926 */   MCD_OPC_CheckPredicate, 21, 38, 14, 0, // Skip to: 18553
-/* 14931 */   MCD_OPC_Decode, 146, 8, 106, // Opcode: VBIFq
-/* 14935 */   MCD_OPC_FilterValue, 2, 155, 0, 0, // Skip to: 15095
-/* 14940 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 14943 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 14981
-/* 14948 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14951 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 14966
-/* 14957 */   MCD_OPC_CheckPredicate, 21, 7, 14, 0, // Skip to: 18553
-/* 14962 */   MCD_OPC_Decode, 194, 16, 98, // Opcode: VQSUBsv16i8
-/* 14966 */   MCD_OPC_FilterValue, 243, 1, 253, 13, 0, // Skip to: 18553
-/* 14972 */   MCD_OPC_CheckPredicate, 21, 248, 13, 0, // Skip to: 18553
-/* 14977 */   MCD_OPC_Decode, 202, 16, 98, // Opcode: VQSUBuv16i8
-/* 14981 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15019
+/* 14170 */   MCD_OPC_CheckPredicate, 26, 17, 2, 0, // Skip to: 14704
+/* 14175 */   MCD_OPC_Decode, 168, 25, 132, 2, // Opcode: VQSHRNsv4i16
+/* 14180 */   MCD_OPC_FilterValue, 1, 7, 2, 0, // Skip to: 14704
+/* 14185 */   MCD_OPC_CheckPredicate, 26, 2, 2, 0, // Skip to: 14704
+/* 14190 */   MCD_OPC_Decode, 171, 25, 132, 2, // Opcode: VQSHRNuv4i16
+/* 14195 */   MCD_OPC_FilterValue, 1, 248, 1, 0, // Skip to: 14704
+/* 14200 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14203 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14218
+/* 14208 */   MCD_OPC_CheckPredicate, 26, 235, 1, 0, // Skip to: 14704
+/* 14213 */   MCD_OPC_Decode, 167, 25, 133, 2, // Opcode: VQSHRNsv2i32
+/* 14218 */   MCD_OPC_FilterValue, 1, 225, 1, 0, // Skip to: 14704
+/* 14223 */   MCD_OPC_CheckPredicate, 26, 220, 1, 0, // Skip to: 14704
+/* 14228 */   MCD_OPC_Decode, 170, 25, 133, 2, // Opcode: VQSHRNuv2i32
+/* 14233 */   MCD_OPC_FilterValue, 10, 243, 0, 0, // Skip to: 14481
+/* 14238 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 14241 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 14409
+/* 14246 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 14249 */   MCD_OPC_FilterValue, 0, 83, 0, 0, // Skip to: 14337
+/* 14254 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14257 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 14297
+/* 14262 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 14265 */   MCD_OPC_FilterValue, 1, 178, 1, 0, // Skip to: 14704
+/* 14270 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14287
+/* 14275 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 14287
+/* 14282 */   MCD_OPC_Decode, 242, 22, 239, 1, // Opcode: VMOVLsv8i16
+/* 14287 */   MCD_OPC_CheckPredicate, 26, 156, 1, 0, // Skip to: 14704
+/* 14292 */   MCD_OPC_Decode, 236, 26, 134, 2, // Opcode: VSHLLsv8i16
+/* 14297 */   MCD_OPC_FilterValue, 1, 146, 1, 0, // Skip to: 14704
+/* 14302 */   MCD_OPC_ExtractField, 19, 1,  // Inst{19} ...
+/* 14305 */   MCD_OPC_FilterValue, 1, 138, 1, 0, // Skip to: 14704
+/* 14310 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14327
+/* 14315 */   MCD_OPC_CheckField, 16, 3, 0, 5, 0, 0, // Skip to: 14327
+/* 14322 */   MCD_OPC_Decode, 245, 22, 239, 1, // Opcode: VMOVLuv8i16
+/* 14327 */   MCD_OPC_CheckPredicate, 26, 116, 1, 0, // Skip to: 14704
+/* 14332 */   MCD_OPC_Decode, 239, 26, 134, 2, // Opcode: VSHLLuv8i16
+/* 14337 */   MCD_OPC_FilterValue, 1, 106, 1, 0, // Skip to: 14704
+/* 14342 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14345 */   MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 14377
+/* 14350 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14367
+/* 14355 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 14367
+/* 14362 */   MCD_OPC_Decode, 241, 22, 239, 1, // Opcode: VMOVLsv4i32
+/* 14367 */   MCD_OPC_CheckPredicate, 26, 76, 1, 0, // Skip to: 14704
+/* 14372 */   MCD_OPC_Decode, 235, 26, 135, 2, // Opcode: VSHLLsv4i32
+/* 14377 */   MCD_OPC_FilterValue, 1, 66, 1, 0, // Skip to: 14704
+/* 14382 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14399
+/* 14387 */   MCD_OPC_CheckField, 16, 4, 0, 5, 0, 0, // Skip to: 14399
+/* 14394 */   MCD_OPC_Decode, 244, 22, 239, 1, // Opcode: VMOVLuv4i32
+/* 14399 */   MCD_OPC_CheckPredicate, 26, 44, 1, 0, // Skip to: 14704
+/* 14404 */   MCD_OPC_Decode, 238, 26, 135, 2, // Opcode: VSHLLuv4i32
+/* 14409 */   MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 14704
+/* 14414 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14417 */   MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 14449
+/* 14422 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14439
+/* 14427 */   MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 14439
+/* 14434 */   MCD_OPC_Decode, 240, 22, 239, 1, // Opcode: VMOVLsv2i64
+/* 14439 */   MCD_OPC_CheckPredicate, 26, 4, 1, 0, // Skip to: 14704
+/* 14444 */   MCD_OPC_Decode, 234, 26, 136, 2, // Opcode: VSHLLsv2i64
+/* 14449 */   MCD_OPC_FilterValue, 1, 250, 0, 0, // Skip to: 14704
+/* 14454 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14471
+/* 14459 */   MCD_OPC_CheckField, 16, 5, 0, 5, 0, 0, // Skip to: 14471
+/* 14466 */   MCD_OPC_Decode, 243, 22, 239, 1, // Opcode: VMOVLuv2i64
+/* 14471 */   MCD_OPC_CheckPredicate, 26, 228, 0, 0, // Skip to: 14704
+/* 14476 */   MCD_OPC_Decode, 237, 26, 136, 2, // Opcode: VSHLLuv2i64
+/* 14481 */   MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 14519
+/* 14486 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14489 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14504
+/* 14494 */   MCD_OPC_CheckPredicate, 27, 205, 0, 0, // Skip to: 14704
+/* 14499 */   MCD_OPC_Decode, 168, 18, 137, 2, // Opcode: VCVTxs2hd
+/* 14504 */   MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 14704
+/* 14509 */   MCD_OPC_CheckPredicate, 27, 190, 0, 0, // Skip to: 14704
+/* 14514 */   MCD_OPC_Decode, 172, 18, 137, 2, // Opcode: VCVTxu2hd
+/* 14519 */   MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 14557
+/* 14524 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14527 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14542
+/* 14532 */   MCD_OPC_CheckPredicate, 27, 167, 0, 0, // Skip to: 14704
+/* 14537 */   MCD_OPC_Decode, 154, 18, 137, 2, // Opcode: VCVTh2xsd
+/* 14542 */   MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 14704
+/* 14547 */   MCD_OPC_CheckPredicate, 27, 152, 0, 0, // Skip to: 14704
+/* 14552 */   MCD_OPC_Decode, 156, 18, 137, 2, // Opcode: VCVTh2xud
+/* 14557 */   MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 14642
+/* 14562 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 14565 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14587
+/* 14570 */   MCD_OPC_CheckPredicate, 26, 34, 0, 0, // Skip to: 14609
+/* 14575 */   MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 14609
+/* 14582 */   MCD_OPC_Decode, 137, 23, 138, 2, // Opcode: VMOVv8i8
+/* 14587 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14609
+/* 14592 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14609
+/* 14597 */   MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 14609
+/* 14604 */   MCD_OPC_Decode, 129, 23, 138, 2, // Opcode: VMOVv1i64
+/* 14609 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14612 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14627
+/* 14617 */   MCD_OPC_CheckPredicate, 26, 82, 0, 0, // Skip to: 14704
+/* 14622 */   MCD_OPC_Decode, 166, 18, 137, 2, // Opcode: VCVTxs2fd
+/* 14627 */   MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 14704
+/* 14632 */   MCD_OPC_CheckPredicate, 26, 67, 0, 0, // Skip to: 14704
+/* 14637 */   MCD_OPC_Decode, 170, 18, 137, 2, // Opcode: VCVTxu2fd
+/* 14642 */   MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 14704
+/* 14647 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 14650 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14665
+/* 14655 */   MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 14680
+/* 14660 */   MCD_OPC_Decode, 145, 18, 137, 2, // Opcode: VCVTf2xsd
+/* 14665 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 14680
+/* 14670 */   MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 14680
+/* 14675 */   MCD_OPC_Decode, 147, 18, 137, 2, // Opcode: VCVTf2xud
+/* 14680 */   MCD_OPC_CheckPredicate, 26, 19, 0, 0, // Skip to: 14704
+/* 14685 */   MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 14704
+/* 14692 */   MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 14704
+/* 14699 */   MCD_OPC_Decode, 130, 23, 138, 2, // Opcode: VMOVv2f32
+/* 14704 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 14707 */   MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 14800
+/* 14712 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
+/* 14715 */   MCD_OPC_FilterValue, 0, 159, 17, 0, // Skip to: 19231
+/* 14720 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 14723 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14745
+/* 14728 */   MCD_OPC_CheckPredicate, 26, 57, 0, 0, // Skip to: 14790
+/* 14733 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14790
+/* 14740 */   MCD_OPC_Decode, 134, 23, 138, 2, // Opcode: VMOVv4i16
+/* 14745 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14790
+/* 14750 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 14753 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14768
+/* 14758 */   MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 14790
+/* 14763 */   MCD_OPC_Decode, 227, 23, 138, 2, // Opcode: VORRiv2i32
+/* 14768 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14790
+/* 14773 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14790
+/* 14778 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14790
+/* 14785 */   MCD_OPC_Decode, 228, 23, 138, 2, // Opcode: VORRiv4i16
+/* 14790 */   MCD_OPC_CheckPredicate, 26, 84, 17, 0, // Skip to: 19231
+/* 14795 */   MCD_OPC_Decode, 131, 23, 138, 2, // Opcode: VMOVv2i32
+/* 14800 */   MCD_OPC_FilterValue, 1, 74, 17, 0, // Skip to: 19231
+/* 14805 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
+/* 14808 */   MCD_OPC_FilterValue, 0, 66, 17, 0, // Skip to: 19231
+/* 14813 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 14816 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 14838
+/* 14821 */   MCD_OPC_CheckPredicate, 26, 57, 0, 0, // Skip to: 14883
+/* 14826 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 14883
+/* 14833 */   MCD_OPC_Decode, 199, 23, 138, 2, // Opcode: VMVNv4i16
+/* 14838 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 14883
+/* 14843 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 14846 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 14861
+/* 14851 */   MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 14883
+/* 14856 */   MCD_OPC_Decode, 187, 16, 138, 2, // Opcode: VBICiv2i32
+/* 14861 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 14883
+/* 14866 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 14883
+/* 14871 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 14883
+/* 14878 */   MCD_OPC_Decode, 188, 16, 138, 2, // Opcode: VBICiv4i16
+/* 14883 */   MCD_OPC_CheckPredicate, 26, 247, 16, 0, // Skip to: 19231
+/* 14888 */   MCD_OPC_Decode, 198, 23, 138, 2, // Opcode: VMVNv2i32
+/* 14893 */   MCD_OPC_FilterValue, 1, 237, 16, 0, // Skip to: 19231
+/* 14898 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 14901 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 14941
+/* 14906 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 14909 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14925
+/* 14915 */   MCD_OPC_CheckPredicate, 26, 215, 16, 0, // Skip to: 19231
+/* 14920 */   MCD_OPC_Decode, 140, 27, 139, 2, // Opcode: VSHRsv1i64
+/* 14925 */   MCD_OPC_FilterValue, 243, 1, 204, 16, 0, // Skip to: 19231
+/* 14931 */   MCD_OPC_CheckPredicate, 26, 199, 16, 0, // Skip to: 19231
+/* 14936 */   MCD_OPC_Decode, 148, 27, 139, 2, // Opcode: VSHRuv1i64
+/* 14941 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 14981
+/* 14946 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 14949 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 14965
+/* 14955 */   MCD_OPC_CheckPredicate, 26, 175, 16, 0, // Skip to: 19231
+/* 14960 */   MCD_OPC_Decode, 177, 27, 140, 2, // Opcode: VSRAsv1i64
+/* 14965 */   MCD_OPC_FilterValue, 243, 1, 164, 16, 0, // Skip to: 19231
+/* 14971 */   MCD_OPC_CheckPredicate, 26, 159, 16, 0, // Skip to: 19231
+/* 14976 */   MCD_OPC_Decode, 185, 27, 140, 2, // Opcode: VSRAuv1i64
+/* 14981 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 15021
 /* 14986 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 14989 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15004
-/* 14995 */   MCD_OPC_CheckPredicate, 21, 225, 13, 0, // Skip to: 18553
-/* 15000 */   MCD_OPC_Decode, 200, 16, 98, // Opcode: VQSUBsv8i16
-/* 15004 */   MCD_OPC_FilterValue, 243, 1, 215, 13, 0, // Skip to: 18553
-/* 15010 */   MCD_OPC_CheckPredicate, 21, 210, 13, 0, // Skip to: 18553
-/* 15015 */   MCD_OPC_Decode, 208, 16, 98, // Opcode: VQSUBuv8i16
-/* 15019 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15057
-/* 15024 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15027 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15042
-/* 15033 */   MCD_OPC_CheckPredicate, 21, 187, 13, 0, // Skip to: 18553
-/* 15038 */   MCD_OPC_Decode, 199, 16, 98, // Opcode: VQSUBsv4i32
-/* 15042 */   MCD_OPC_FilterValue, 243, 1, 177, 13, 0, // Skip to: 18553
-/* 15048 */   MCD_OPC_CheckPredicate, 21, 172, 13, 0, // Skip to: 18553
-/* 15053 */   MCD_OPC_Decode, 207, 16, 98, // Opcode: VQSUBuv4i32
-/* 15057 */   MCD_OPC_FilterValue, 3, 163, 13, 0, // Skip to: 18553
-/* 15062 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15065 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15080
-/* 15071 */   MCD_OPC_CheckPredicate, 21, 149, 13, 0, // Skip to: 18553
-/* 15076 */   MCD_OPC_Decode, 197, 16, 98, // Opcode: VQSUBsv2i64
-/* 15080 */   MCD_OPC_FilterValue, 243, 1, 139, 13, 0, // Skip to: 18553
-/* 15086 */   MCD_OPC_CheckPredicate, 21, 134, 13, 0, // Skip to: 18553
-/* 15091 */   MCD_OPC_Decode, 205, 16, 98, // Opcode: VQSUBuv2i64
-/* 15095 */   MCD_OPC_FilterValue, 3, 117, 0, 0, // Skip to: 15217
-/* 15100 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15103 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15141
-/* 15108 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15111 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15126
-/* 15117 */   MCD_OPC_CheckPredicate, 21, 103, 13, 0, // Skip to: 18553
-/* 15122 */   MCD_OPC_Decode, 179, 8, 98, // Opcode: VCGEsv16i8
-/* 15126 */   MCD_OPC_FilterValue, 243, 1, 93, 13, 0, // Skip to: 18553
-/* 15132 */   MCD_OPC_CheckPredicate, 21, 88, 13, 0, // Skip to: 18553
-/* 15137 */   MCD_OPC_Decode, 185, 8, 98, // Opcode: VCGEuv16i8
-/* 15141 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15179
-/* 15146 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15149 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15164
-/* 15155 */   MCD_OPC_CheckPredicate, 21, 65, 13, 0, // Skip to: 18553
-/* 15160 */   MCD_OPC_Decode, 183, 8, 98, // Opcode: VCGEsv8i16
-/* 15164 */   MCD_OPC_FilterValue, 243, 1, 55, 13, 0, // Skip to: 18553
-/* 15170 */   MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 18553
-/* 15175 */   MCD_OPC_Decode, 189, 8, 98, // Opcode: VCGEuv8i16
-/* 15179 */   MCD_OPC_FilterValue, 2, 41, 13, 0, // Skip to: 18553
-/* 15184 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15187 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15202
-/* 15193 */   MCD_OPC_CheckPredicate, 21, 27, 13, 0, // Skip to: 18553
-/* 15198 */   MCD_OPC_Decode, 182, 8, 98, // Opcode: VCGEsv4i32
-/* 15202 */   MCD_OPC_FilterValue, 243, 1, 17, 13, 0, // Skip to: 18553
-/* 15208 */   MCD_OPC_CheckPredicate, 21, 12, 13, 0, // Skip to: 18553
-/* 15213 */   MCD_OPC_Decode, 188, 8, 98, // Opcode: VCGEuv4i32
-/* 15217 */   MCD_OPC_FilterValue, 4, 155, 0, 0, // Skip to: 15377
-/* 15222 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15225 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15263
-/* 15230 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15233 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15248
-/* 15239 */   MCD_OPC_CheckPredicate, 21, 237, 12, 0, // Skip to: 18553
-/* 15244 */   MCD_OPC_Decode, 161, 16, 102, // Opcode: VQSHLsv16i8
-/* 15248 */   MCD_OPC_FilterValue, 243, 1, 227, 12, 0, // Skip to: 18553
-/* 15254 */   MCD_OPC_CheckPredicate, 21, 222, 12, 0, // Skip to: 18553
-/* 15259 */   MCD_OPC_Decode, 177, 16, 102, // Opcode: VQSHLuv16i8
-/* 15263 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15301
-/* 15268 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15271 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15286
-/* 15277 */   MCD_OPC_CheckPredicate, 21, 199, 12, 0, // Skip to: 18553
-/* 15282 */   MCD_OPC_Decode, 167, 16, 102, // Opcode: VQSHLsv8i16
-/* 15286 */   MCD_OPC_FilterValue, 243, 1, 189, 12, 0, // Skip to: 18553
-/* 15292 */   MCD_OPC_CheckPredicate, 21, 184, 12, 0, // Skip to: 18553
-/* 15297 */   MCD_OPC_Decode, 183, 16, 102, // Opcode: VQSHLuv8i16
-/* 15301 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15339
-/* 15306 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15309 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15324
-/* 15315 */   MCD_OPC_CheckPredicate, 21, 161, 12, 0, // Skip to: 18553
-/* 15320 */   MCD_OPC_Decode, 166, 16, 102, // Opcode: VQSHLsv4i32
-/* 15324 */   MCD_OPC_FilterValue, 243, 1, 151, 12, 0, // Skip to: 18553
-/* 15330 */   MCD_OPC_CheckPredicate, 21, 146, 12, 0, // Skip to: 18553
-/* 15335 */   MCD_OPC_Decode, 182, 16, 102, // Opcode: VQSHLuv4i32
-/* 15339 */   MCD_OPC_FilterValue, 3, 137, 12, 0, // Skip to: 18553
-/* 15344 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15347 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15362
-/* 15353 */   MCD_OPC_CheckPredicate, 21, 123, 12, 0, // Skip to: 18553
-/* 15358 */   MCD_OPC_Decode, 164, 16, 102, // Opcode: VQSHLsv2i64
-/* 15362 */   MCD_OPC_FilterValue, 243, 1, 113, 12, 0, // Skip to: 18553
-/* 15368 */   MCD_OPC_CheckPredicate, 21, 108, 12, 0, // Skip to: 18553
-/* 15373 */   MCD_OPC_Decode, 180, 16, 102, // Opcode: VQSHLuv2i64
-/* 15377 */   MCD_OPC_FilterValue, 5, 155, 0, 0, // Skip to: 15537
-/* 15382 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15385 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15423
-/* 15390 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15393 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15408
-/* 15399 */   MCD_OPC_CheckPredicate, 21, 77, 12, 0, // Skip to: 18553
-/* 15404 */   MCD_OPC_Decode, 248, 15, 102, // Opcode: VQRSHLsv16i8
-/* 15408 */   MCD_OPC_FilterValue, 243, 1, 67, 12, 0, // Skip to: 18553
-/* 15414 */   MCD_OPC_CheckPredicate, 21, 62, 12, 0, // Skip to: 18553
-/* 15419 */   MCD_OPC_Decode, 128, 16, 102, // Opcode: VQRSHLuv16i8
-/* 15423 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15461
-/* 15428 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15431 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15446
-/* 15437 */   MCD_OPC_CheckPredicate, 21, 39, 12, 0, // Skip to: 18553
-/* 15442 */   MCD_OPC_Decode, 254, 15, 102, // Opcode: VQRSHLsv8i16
-/* 15446 */   MCD_OPC_FilterValue, 243, 1, 29, 12, 0, // Skip to: 18553
-/* 15452 */   MCD_OPC_CheckPredicate, 21, 24, 12, 0, // Skip to: 18553
-/* 15457 */   MCD_OPC_Decode, 134, 16, 102, // Opcode: VQRSHLuv8i16
-/* 15461 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 15499
-/* 15466 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15469 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15484
-/* 15475 */   MCD_OPC_CheckPredicate, 21, 1, 12, 0, // Skip to: 18553
-/* 15480 */   MCD_OPC_Decode, 253, 15, 102, // Opcode: VQRSHLsv4i32
-/* 15484 */   MCD_OPC_FilterValue, 243, 1, 247, 11, 0, // Skip to: 18553
-/* 15490 */   MCD_OPC_CheckPredicate, 21, 242, 11, 0, // Skip to: 18553
-/* 15495 */   MCD_OPC_Decode, 133, 16, 102, // Opcode: VQRSHLuv4i32
-/* 15499 */   MCD_OPC_FilterValue, 3, 233, 11, 0, // Skip to: 18553
+/* 14989 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15005
+/* 14995 */   MCD_OPC_CheckPredicate, 26, 135, 16, 0, // Skip to: 19231
+/* 15000 */   MCD_OPC_Decode, 166, 26, 139, 2, // Opcode: VRSHRsv1i64
+/* 15005 */   MCD_OPC_FilterValue, 243, 1, 124, 16, 0, // Skip to: 19231
+/* 15011 */   MCD_OPC_CheckPredicate, 26, 119, 16, 0, // Skip to: 19231
+/* 15016 */   MCD_OPC_Decode, 174, 26, 139, 2, // Opcode: VRSHRuv1i64
+/* 15021 */   MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 15061
+/* 15026 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15029 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15045
+/* 15035 */   MCD_OPC_CheckPredicate, 26, 95, 16, 0, // Skip to: 19231
+/* 15040 */   MCD_OPC_Decode, 192, 26, 140, 2, // Opcode: VRSRAsv1i64
+/* 15045 */   MCD_OPC_FilterValue, 243, 1, 84, 16, 0, // Skip to: 19231
+/* 15051 */   MCD_OPC_CheckPredicate, 26, 79, 16, 0, // Skip to: 19231
+/* 15056 */   MCD_OPC_Decode, 200, 26, 140, 2, // Opcode: VRSRAuv1i64
+/* 15061 */   MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 15084
+/* 15066 */   MCD_OPC_CheckPredicate, 26, 64, 16, 0, // Skip to: 19231
+/* 15071 */   MCD_OPC_CheckField, 24, 8, 243, 1, 56, 16, 0, // Skip to: 19231
+/* 15079 */   MCD_OPC_Decode, 193, 27, 140, 2, // Opcode: VSRIv1i64
+/* 15084 */   MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 15124
+/* 15089 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15092 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15108
+/* 15098 */   MCD_OPC_CheckPredicate, 26, 32, 16, 0, // Skip to: 19231
+/* 15103 */   MCD_OPC_Decode, 241, 26, 141, 2, // Opcode: VSHLiv1i64
+/* 15108 */   MCD_OPC_FilterValue, 243, 1, 21, 16, 0, // Skip to: 19231
+/* 15114 */   MCD_OPC_CheckPredicate, 26, 16, 16, 0, // Skip to: 19231
+/* 15119 */   MCD_OPC_Decode, 162, 27, 142, 2, // Opcode: VSLIv1i64
+/* 15124 */   MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 15147
+/* 15129 */   MCD_OPC_CheckPredicate, 26, 1, 16, 0, // Skip to: 19231
+/* 15134 */   MCD_OPC_CheckField, 24, 8, 243, 1, 249, 15, 0, // Skip to: 19231
+/* 15142 */   MCD_OPC_Decode, 136, 25, 141, 2, // Opcode: VQSHLsuv1i64
+/* 15147 */   MCD_OPC_FilterValue, 7, 239, 15, 0, // Skip to: 19231
+/* 15152 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15155 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15171
+/* 15161 */   MCD_OPC_CheckPredicate, 26, 225, 15, 0, // Skip to: 19231
+/* 15166 */   MCD_OPC_Decode, 128, 25, 141, 2, // Opcode: VQSHLsiv1i64
+/* 15171 */   MCD_OPC_FilterValue, 243, 1, 214, 15, 0, // Skip to: 19231
+/* 15177 */   MCD_OPC_CheckPredicate, 26, 209, 15, 0, // Skip to: 19231
+/* 15182 */   MCD_OPC_Decode, 152, 25, 141, 2, // Opcode: VQSHLuiv1i64
+/* 15187 */   MCD_OPC_FilterValue, 1, 199, 15, 0, // Skip to: 19231
+/* 15192 */   MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 15195 */   MCD_OPC_FilterValue, 0, 179, 7, 0, // Skip to: 17171
+/* 15200 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 15203 */   MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 15371
+/* 15208 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 15211 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 15251
+/* 15216 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15219 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15235
+/* 15225 */   MCD_OPC_CheckPredicate, 26, 161, 15, 0, // Skip to: 19231
+/* 15230 */   MCD_OPC_Decode, 155, 24, 203, 1, // Opcode: VQADDsv16i8
+/* 15235 */   MCD_OPC_FilterValue, 243, 1, 150, 15, 0, // Skip to: 19231
+/* 15241 */   MCD_OPC_CheckPredicate, 26, 145, 15, 0, // Skip to: 19231
+/* 15246 */   MCD_OPC_Decode, 163, 24, 203, 1, // Opcode: VQADDuv16i8
+/* 15251 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 15291
+/* 15256 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15259 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15275
+/* 15265 */   MCD_OPC_CheckPredicate, 26, 121, 15, 0, // Skip to: 19231
+/* 15270 */   MCD_OPC_Decode, 161, 24, 203, 1, // Opcode: VQADDsv8i16
+/* 15275 */   MCD_OPC_FilterValue, 243, 1, 110, 15, 0, // Skip to: 19231
+/* 15281 */   MCD_OPC_CheckPredicate, 26, 105, 15, 0, // Skip to: 19231
+/* 15286 */   MCD_OPC_Decode, 169, 24, 203, 1, // Opcode: VQADDuv8i16
+/* 15291 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 15331
+/* 15296 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15299 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15315
+/* 15305 */   MCD_OPC_CheckPredicate, 26, 81, 15, 0, // Skip to: 19231
+/* 15310 */   MCD_OPC_Decode, 160, 24, 203, 1, // Opcode: VQADDsv4i32
+/* 15315 */   MCD_OPC_FilterValue, 243, 1, 70, 15, 0, // Skip to: 19231
+/* 15321 */   MCD_OPC_CheckPredicate, 26, 65, 15, 0, // Skip to: 19231
+/* 15326 */   MCD_OPC_Decode, 168, 24, 203, 1, // Opcode: VQADDuv4i32
+/* 15331 */   MCD_OPC_FilterValue, 3, 55, 15, 0, // Skip to: 19231
+/* 15336 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15339 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15355
+/* 15345 */   MCD_OPC_CheckPredicate, 26, 41, 15, 0, // Skip to: 19231
+/* 15350 */   MCD_OPC_Decode, 158, 24, 203, 1, // Opcode: VQADDsv2i64
+/* 15355 */   MCD_OPC_FilterValue, 243, 1, 30, 15, 0, // Skip to: 19231
+/* 15361 */   MCD_OPC_CheckPredicate, 26, 25, 15, 0, // Skip to: 19231
+/* 15366 */   MCD_OPC_Decode, 166, 24, 203, 1, // Opcode: VQADDuv2i64
+/* 15371 */   MCD_OPC_FilterValue, 1, 163, 0, 0, // Skip to: 15539
+/* 15376 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 15379 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 15419
+/* 15384 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15387 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15403
+/* 15393 */   MCD_OPC_CheckPredicate, 26, 249, 14, 0, // Skip to: 19231
+/* 15398 */   MCD_OPC_Decode, 181, 16, 203, 1, // Opcode: VANDq
+/* 15403 */   MCD_OPC_FilterValue, 243, 1, 238, 14, 0, // Skip to: 19231
+/* 15409 */   MCD_OPC_CheckPredicate, 26, 233, 14, 0, // Skip to: 19231
+/* 15414 */   MCD_OPC_Decode, 190, 18, 203, 1, // Opcode: VEORq
+/* 15419 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 15459
+/* 15424 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15427 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15443
+/* 15433 */   MCD_OPC_CheckPredicate, 26, 209, 14, 0, // Skip to: 19231
+/* 15438 */   MCD_OPC_Decode, 191, 16, 203, 1, // Opcode: VBICq
+/* 15443 */   MCD_OPC_FilterValue, 243, 1, 198, 14, 0, // Skip to: 19231
+/* 15449 */   MCD_OPC_CheckPredicate, 26, 193, 14, 0, // Skip to: 19231
+/* 15454 */   MCD_OPC_Decode, 197, 16, 211, 1, // Opcode: VBSLq
+/* 15459 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 15499
+/* 15464 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15467 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15483
+/* 15473 */   MCD_OPC_CheckPredicate, 26, 169, 14, 0, // Skip to: 19231
+/* 15478 */   MCD_OPC_Decode, 231, 23, 203, 1, // Opcode: VORRq
+/* 15483 */   MCD_OPC_FilterValue, 243, 1, 158, 14, 0, // Skip to: 19231
+/* 15489 */   MCD_OPC_CheckPredicate, 26, 153, 14, 0, // Skip to: 19231
+/* 15494 */   MCD_OPC_Decode, 195, 16, 211, 1, // Opcode: VBITq
+/* 15499 */   MCD_OPC_FilterValue, 3, 143, 14, 0, // Skip to: 19231
 /* 15504 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15507 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15522
-/* 15513 */   MCD_OPC_CheckPredicate, 21, 219, 11, 0, // Skip to: 18553
-/* 15518 */   MCD_OPC_Decode, 251, 15, 102, // Opcode: VQRSHLsv2i64
-/* 15522 */   MCD_OPC_FilterValue, 243, 1, 209, 11, 0, // Skip to: 18553
-/* 15528 */   MCD_OPC_CheckPredicate, 21, 204, 11, 0, // Skip to: 18553
-/* 15533 */   MCD_OPC_Decode, 131, 16, 102, // Opcode: VQRSHLuv2i64
-/* 15537 */   MCD_OPC_FilterValue, 6, 117, 0, 0, // Skip to: 15659
-/* 15542 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15545 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15583
-/* 15550 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15553 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15568
-/* 15559 */   MCD_OPC_CheckPredicate, 21, 173, 11, 0, // Skip to: 18553
-/* 15564 */   MCD_OPC_Decode, 190, 13, 98, // Opcode: VMINsv16i8
-/* 15568 */   MCD_OPC_FilterValue, 243, 1, 163, 11, 0, // Skip to: 18553
-/* 15574 */   MCD_OPC_CheckPredicate, 21, 158, 11, 0, // Skip to: 18553
-/* 15579 */   MCD_OPC_Decode, 196, 13, 98, // Opcode: VMINuv16i8
-/* 15583 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15621
-/* 15588 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15591 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15606
-/* 15597 */   MCD_OPC_CheckPredicate, 21, 135, 11, 0, // Skip to: 18553
-/* 15602 */   MCD_OPC_Decode, 194, 13, 98, // Opcode: VMINsv8i16
-/* 15606 */   MCD_OPC_FilterValue, 243, 1, 125, 11, 0, // Skip to: 18553
-/* 15612 */   MCD_OPC_CheckPredicate, 21, 120, 11, 0, // Skip to: 18553
-/* 15617 */   MCD_OPC_Decode, 200, 13, 98, // Opcode: VMINuv8i16
-/* 15621 */   MCD_OPC_FilterValue, 2, 111, 11, 0, // Skip to: 18553
-/* 15626 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15629 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15644
-/* 15635 */   MCD_OPC_CheckPredicate, 21, 97, 11, 0, // Skip to: 18553
-/* 15640 */   MCD_OPC_Decode, 193, 13, 98, // Opcode: VMINsv4i32
-/* 15644 */   MCD_OPC_FilterValue, 243, 1, 87, 11, 0, // Skip to: 18553
-/* 15650 */   MCD_OPC_CheckPredicate, 21, 82, 11, 0, // Skip to: 18553
-/* 15655 */   MCD_OPC_Decode, 199, 13, 98, // Opcode: VMINuv4i32
-/* 15659 */   MCD_OPC_FilterValue, 7, 117, 0, 0, // Skip to: 15781
-/* 15664 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15667 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15705
+/* 15507 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15523
+/* 15513 */   MCD_OPC_CheckPredicate, 26, 129, 14, 0, // Skip to: 19231
+/* 15518 */   MCD_OPC_Decode, 225, 23, 203, 1, // Opcode: VORNq
+/* 15523 */   MCD_OPC_FilterValue, 243, 1, 118, 14, 0, // Skip to: 19231
+/* 15529 */   MCD_OPC_CheckPredicate, 26, 113, 14, 0, // Skip to: 19231
+/* 15534 */   MCD_OPC_Decode, 193, 16, 211, 1, // Opcode: VBIFq
+/* 15539 */   MCD_OPC_FilterValue, 2, 163, 0, 0, // Skip to: 15707
+/* 15544 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 15547 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 15587
+/* 15552 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15555 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15571
+/* 15561 */   MCD_OPC_CheckPredicate, 26, 81, 14, 0, // Skip to: 19231
+/* 15566 */   MCD_OPC_Decode, 176, 25, 203, 1, // Opcode: VQSUBsv16i8
+/* 15571 */   MCD_OPC_FilterValue, 243, 1, 70, 14, 0, // Skip to: 19231
+/* 15577 */   MCD_OPC_CheckPredicate, 26, 65, 14, 0, // Skip to: 19231
+/* 15582 */   MCD_OPC_Decode, 184, 25, 203, 1, // Opcode: VQSUBuv16i8
+/* 15587 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 15627
+/* 15592 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15595 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15611
+/* 15601 */   MCD_OPC_CheckPredicate, 26, 41, 14, 0, // Skip to: 19231
+/* 15606 */   MCD_OPC_Decode, 182, 25, 203, 1, // Opcode: VQSUBsv8i16
+/* 15611 */   MCD_OPC_FilterValue, 243, 1, 30, 14, 0, // Skip to: 19231
+/* 15617 */   MCD_OPC_CheckPredicate, 26, 25, 14, 0, // Skip to: 19231
+/* 15622 */   MCD_OPC_Decode, 190, 25, 203, 1, // Opcode: VQSUBuv8i16
+/* 15627 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 15667
+/* 15632 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15635 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15651
+/* 15641 */   MCD_OPC_CheckPredicate, 26, 1, 14, 0, // Skip to: 19231
+/* 15646 */   MCD_OPC_Decode, 181, 25, 203, 1, // Opcode: VQSUBsv4i32
+/* 15651 */   MCD_OPC_FilterValue, 243, 1, 246, 13, 0, // Skip to: 19231
+/* 15657 */   MCD_OPC_CheckPredicate, 26, 241, 13, 0, // Skip to: 19231
+/* 15662 */   MCD_OPC_Decode, 189, 25, 203, 1, // Opcode: VQSUBuv4i32
+/* 15667 */   MCD_OPC_FilterValue, 3, 231, 13, 0, // Skip to: 19231
 /* 15672 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15675 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15690
-/* 15681 */   MCD_OPC_CheckPredicate, 21, 51, 11, 0, // Skip to: 18553
-/* 15686 */   MCD_OPC_Decode, 180, 7, 106, // Opcode: VABAsv16i8
-/* 15690 */   MCD_OPC_FilterValue, 243, 1, 41, 11, 0, // Skip to: 18553
-/* 15696 */   MCD_OPC_CheckPredicate, 21, 36, 11, 0, // Skip to: 18553
-/* 15701 */   MCD_OPC_Decode, 186, 7, 106, // Opcode: VABAuv16i8
-/* 15705 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15743
-/* 15710 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15713 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15728
-/* 15719 */   MCD_OPC_CheckPredicate, 21, 13, 11, 0, // Skip to: 18553
-/* 15724 */   MCD_OPC_Decode, 184, 7, 106, // Opcode: VABAsv8i16
-/* 15728 */   MCD_OPC_FilterValue, 243, 1, 3, 11, 0, // Skip to: 18553
-/* 15734 */   MCD_OPC_CheckPredicate, 21, 254, 10, 0, // Skip to: 18553
-/* 15739 */   MCD_OPC_Decode, 190, 7, 106, // Opcode: VABAuv8i16
-/* 15743 */   MCD_OPC_FilterValue, 2, 245, 10, 0, // Skip to: 18553
-/* 15748 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15751 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15766
-/* 15757 */   MCD_OPC_CheckPredicate, 21, 231, 10, 0, // Skip to: 18553
-/* 15762 */   MCD_OPC_Decode, 183, 7, 106, // Opcode: VABAsv4i32
-/* 15766 */   MCD_OPC_FilterValue, 243, 1, 221, 10, 0, // Skip to: 18553
-/* 15772 */   MCD_OPC_CheckPredicate, 21, 216, 10, 0, // Skip to: 18553
-/* 15777 */   MCD_OPC_Decode, 189, 7, 106, // Opcode: VABAuv4i32
-/* 15781 */   MCD_OPC_FilterValue, 8, 117, 0, 0, // Skip to: 15903
-/* 15786 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15789 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15827
-/* 15794 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15797 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15812
-/* 15803 */   MCD_OPC_CheckPredicate, 21, 185, 10, 0, // Skip to: 18553
-/* 15808 */   MCD_OPC_Decode, 153, 21, 98, // Opcode: VTSTv16i8
-/* 15812 */   MCD_OPC_FilterValue, 243, 1, 175, 10, 0, // Skip to: 18553
-/* 15818 */   MCD_OPC_CheckPredicate, 21, 170, 10, 0, // Skip to: 18553
-/* 15823 */   MCD_OPC_Decode, 159, 8, 98, // Opcode: VCEQv16i8
-/* 15827 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 15865
-/* 15832 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15835 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15850
-/* 15841 */   MCD_OPC_CheckPredicate, 21, 147, 10, 0, // Skip to: 18553
-/* 15846 */   MCD_OPC_Decode, 157, 21, 98, // Opcode: VTSTv8i16
-/* 15850 */   MCD_OPC_FilterValue, 243, 1, 137, 10, 0, // Skip to: 18553
-/* 15856 */   MCD_OPC_CheckPredicate, 21, 132, 10, 0, // Skip to: 18553
-/* 15861 */   MCD_OPC_Decode, 163, 8, 98, // Opcode: VCEQv8i16
-/* 15865 */   MCD_OPC_FilterValue, 2, 123, 10, 0, // Skip to: 18553
-/* 15870 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15873 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15888
-/* 15879 */   MCD_OPC_CheckPredicate, 21, 109, 10, 0, // Skip to: 18553
-/* 15884 */   MCD_OPC_Decode, 156, 21, 98, // Opcode: VTSTv4i32
-/* 15888 */   MCD_OPC_FilterValue, 243, 1, 99, 10, 0, // Skip to: 18553
-/* 15894 */   MCD_OPC_CheckPredicate, 21, 94, 10, 0, // Skip to: 18553
-/* 15899 */   MCD_OPC_Decode, 162, 8, 98, // Opcode: VCEQv4i32
-/* 15903 */   MCD_OPC_FilterValue, 9, 85, 0, 0, // Skip to: 15993
-/* 15908 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 15911 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 15949
-/* 15916 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 15919 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 15934
-/* 15925 */   MCD_OPC_CheckPredicate, 21, 63, 10, 0, // Skip to: 18553
-/* 15930 */   MCD_OPC_Decode, 208, 14, 98, // Opcode: VMULv16i8
-/* 15934 */   MCD_OPC_FilterValue, 243, 1, 53, 10, 0, // Skip to: 18553
-/* 15940 */   MCD_OPC_CheckPredicate, 21, 48, 10, 0, // Skip to: 18553
-/* 15945 */   MCD_OPC_Decode, 199, 14, 98, // Opcode: VMULpq
-/* 15949 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 15971
-/* 15954 */   MCD_OPC_CheckPredicate, 21, 34, 10, 0, // Skip to: 18553
-/* 15959 */   MCD_OPC_CheckField, 24, 8, 242, 1, 26, 10, 0, // Skip to: 18553
-/* 15967 */   MCD_OPC_Decode, 212, 14, 98, // Opcode: VMULv8i16
-/* 15971 */   MCD_OPC_FilterValue, 2, 17, 10, 0, // Skip to: 18553
-/* 15976 */   MCD_OPC_CheckPredicate, 21, 12, 10, 0, // Skip to: 18553
-/* 15981 */   MCD_OPC_CheckField, 24, 8, 242, 1, 4, 10, 0, // Skip to: 18553
-/* 15989 */   MCD_OPC_Decode, 211, 14, 98, // Opcode: VMULv4i32
-/* 15993 */   MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 16045
-/* 15998 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 16001 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16023
-/* 16006 */   MCD_OPC_CheckPredicate, 23, 238, 9, 0, // Skip to: 18553
-/* 16011 */   MCD_OPC_CheckField, 24, 8, 243, 1, 230, 9, 0, // Skip to: 18553
-/* 16019 */   MCD_OPC_Decode, 231, 15, 106, // Opcode: VQRDMLAHv8i16
-/* 16023 */   MCD_OPC_FilterValue, 2, 221, 9, 0, // Skip to: 18553
-/* 16028 */   MCD_OPC_CheckPredicate, 23, 216, 9, 0, // Skip to: 18553
-/* 16033 */   MCD_OPC_CheckField, 24, 8, 243, 1, 208, 9, 0, // Skip to: 18553
-/* 16041 */   MCD_OPC_Decode, 230, 15, 106, // Opcode: VQRDMLAHv4i32
-/* 16045 */   MCD_OPC_FilterValue, 12, 123, 0, 0, // Skip to: 16173
-/* 16050 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 16053 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16075
-/* 16058 */   MCD_OPC_CheckPredicate, 26, 186, 9, 0, // Skip to: 18553
-/* 16063 */   MCD_OPC_CheckField, 24, 8, 242, 1, 178, 9, 0, // Skip to: 18553
-/* 16071 */   MCD_OPC_Decode, 153, 10, 106, // Opcode: VFMAfq
-/* 16075 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16113
-/* 16080 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 16083 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16098
-/* 16089 */   MCD_OPC_CheckPredicate, 22, 155, 9, 0, // Skip to: 18553
-/* 16094 */   MCD_OPC_Decode, 155, 10, 106, // Opcode: VFMAhq
-/* 16098 */   MCD_OPC_FilterValue, 243, 1, 145, 9, 0, // Skip to: 18553
-/* 16104 */   MCD_OPC_CheckPredicate, 23, 140, 9, 0, // Skip to: 18553
-/* 16109 */   MCD_OPC_Decode, 239, 15, 106, // Opcode: VQRDMLSHv8i16
-/* 16113 */   MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 16151
-/* 16118 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 16121 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16136
-/* 16127 */   MCD_OPC_CheckPredicate, 26, 117, 9, 0, // Skip to: 18553
-/* 16132 */   MCD_OPC_Decode, 160, 10, 106, // Opcode: VFMSfq
-/* 16136 */   MCD_OPC_FilterValue, 243, 1, 107, 9, 0, // Skip to: 18553
-/* 16142 */   MCD_OPC_CheckPredicate, 23, 102, 9, 0, // Skip to: 18553
-/* 16147 */   MCD_OPC_Decode, 238, 15, 106, // Opcode: VQRDMLSHv4i32
-/* 16151 */   MCD_OPC_FilterValue, 3, 93, 9, 0, // Skip to: 18553
-/* 16156 */   MCD_OPC_CheckPredicate, 22, 88, 9, 0, // Skip to: 18553
-/* 16161 */   MCD_OPC_CheckField, 24, 8, 242, 1, 80, 9, 0, // Skip to: 18553
-/* 16169 */   MCD_OPC_Decode, 162, 10, 106, // Opcode: VFMShq
-/* 16173 */   MCD_OPC_FilterValue, 13, 123, 0, 0, // Skip to: 16301
-/* 16178 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 16181 */   MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 16219
-/* 16186 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 16189 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16204
-/* 16195 */   MCD_OPC_CheckPredicate, 21, 49, 9, 0, // Skip to: 18553
-/* 16200 */   MCD_OPC_Decode, 216, 13, 106, // Opcode: VMLAfq
-/* 16204 */   MCD_OPC_FilterValue, 243, 1, 39, 9, 0, // Skip to: 18553
-/* 16210 */   MCD_OPC_CheckPredicate, 21, 34, 9, 0, // Skip to: 18553
-/* 16215 */   MCD_OPC_Decode, 195, 14, 98, // Opcode: VMULfq
-/* 16219 */   MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 16257
+/* 15675 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15691
+/* 15681 */   MCD_OPC_CheckPredicate, 26, 217, 13, 0, // Skip to: 19231
+/* 15686 */   MCD_OPC_Decode, 179, 25, 203, 1, // Opcode: VQSUBsv2i64
+/* 15691 */   MCD_OPC_FilterValue, 243, 1, 206, 13, 0, // Skip to: 19231
+/* 15697 */   MCD_OPC_CheckPredicate, 26, 201, 13, 0, // Skip to: 19231
+/* 15702 */   MCD_OPC_Decode, 187, 25, 203, 1, // Opcode: VQSUBuv2i64
+/* 15707 */   MCD_OPC_FilterValue, 3, 123, 0, 0, // Skip to: 15835
+/* 15712 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 15715 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 15755
+/* 15720 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15723 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15739
+/* 15729 */   MCD_OPC_CheckPredicate, 26, 169, 13, 0, // Skip to: 19231
+/* 15734 */   MCD_OPC_Decode, 228, 16, 203, 1, // Opcode: VCGEsv16i8
+/* 15739 */   MCD_OPC_FilterValue, 243, 1, 158, 13, 0, // Skip to: 19231
+/* 15745 */   MCD_OPC_CheckPredicate, 26, 153, 13, 0, // Skip to: 19231
+/* 15750 */   MCD_OPC_Decode, 234, 16, 203, 1, // Opcode: VCGEuv16i8
+/* 15755 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 15795
+/* 15760 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15763 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15779
+/* 15769 */   MCD_OPC_CheckPredicate, 26, 129, 13, 0, // Skip to: 19231
+/* 15774 */   MCD_OPC_Decode, 232, 16, 203, 1, // Opcode: VCGEsv8i16
+/* 15779 */   MCD_OPC_FilterValue, 243, 1, 118, 13, 0, // Skip to: 19231
+/* 15785 */   MCD_OPC_CheckPredicate, 26, 113, 13, 0, // Skip to: 19231
+/* 15790 */   MCD_OPC_Decode, 238, 16, 203, 1, // Opcode: VCGEuv8i16
+/* 15795 */   MCD_OPC_FilterValue, 2, 103, 13, 0, // Skip to: 19231
+/* 15800 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15803 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15819
+/* 15809 */   MCD_OPC_CheckPredicate, 26, 89, 13, 0, // Skip to: 19231
+/* 15814 */   MCD_OPC_Decode, 231, 16, 203, 1, // Opcode: VCGEsv4i32
+/* 15819 */   MCD_OPC_FilterValue, 243, 1, 78, 13, 0, // Skip to: 19231
+/* 15825 */   MCD_OPC_CheckPredicate, 26, 73, 13, 0, // Skip to: 19231
+/* 15830 */   MCD_OPC_Decode, 237, 16, 203, 1, // Opcode: VCGEuv4i32
+/* 15835 */   MCD_OPC_FilterValue, 4, 163, 0, 0, // Skip to: 16003
+/* 15840 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 15843 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 15883
+/* 15848 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15851 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15867
+/* 15857 */   MCD_OPC_CheckPredicate, 26, 41, 13, 0, // Skip to: 19231
+/* 15862 */   MCD_OPC_Decode, 143, 25, 207, 1, // Opcode: VQSHLsv16i8
+/* 15867 */   MCD_OPC_FilterValue, 243, 1, 30, 13, 0, // Skip to: 19231
+/* 15873 */   MCD_OPC_CheckPredicate, 26, 25, 13, 0, // Skip to: 19231
+/* 15878 */   MCD_OPC_Decode, 159, 25, 207, 1, // Opcode: VQSHLuv16i8
+/* 15883 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 15923
+/* 15888 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15891 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15907
+/* 15897 */   MCD_OPC_CheckPredicate, 26, 1, 13, 0, // Skip to: 19231
+/* 15902 */   MCD_OPC_Decode, 149, 25, 207, 1, // Opcode: VQSHLsv8i16
+/* 15907 */   MCD_OPC_FilterValue, 243, 1, 246, 12, 0, // Skip to: 19231
+/* 15913 */   MCD_OPC_CheckPredicate, 26, 241, 12, 0, // Skip to: 19231
+/* 15918 */   MCD_OPC_Decode, 165, 25, 207, 1, // Opcode: VQSHLuv8i16
+/* 15923 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 15963
+/* 15928 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15931 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15947
+/* 15937 */   MCD_OPC_CheckPredicate, 26, 217, 12, 0, // Skip to: 19231
+/* 15942 */   MCD_OPC_Decode, 148, 25, 207, 1, // Opcode: VQSHLsv4i32
+/* 15947 */   MCD_OPC_FilterValue, 243, 1, 206, 12, 0, // Skip to: 19231
+/* 15953 */   MCD_OPC_CheckPredicate, 26, 201, 12, 0, // Skip to: 19231
+/* 15958 */   MCD_OPC_Decode, 164, 25, 207, 1, // Opcode: VQSHLuv4i32
+/* 15963 */   MCD_OPC_FilterValue, 3, 191, 12, 0, // Skip to: 19231
+/* 15968 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 15971 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 15987
+/* 15977 */   MCD_OPC_CheckPredicate, 26, 177, 12, 0, // Skip to: 19231
+/* 15982 */   MCD_OPC_Decode, 146, 25, 207, 1, // Opcode: VQSHLsv2i64
+/* 15987 */   MCD_OPC_FilterValue, 243, 1, 166, 12, 0, // Skip to: 19231
+/* 15993 */   MCD_OPC_CheckPredicate, 26, 161, 12, 0, // Skip to: 19231
+/* 15998 */   MCD_OPC_Decode, 162, 25, 207, 1, // Opcode: VQSHLuv2i64
+/* 16003 */   MCD_OPC_FilterValue, 5, 163, 0, 0, // Skip to: 16171
+/* 16008 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16011 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 16051
+/* 16016 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16019 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16035
+/* 16025 */   MCD_OPC_CheckPredicate, 26, 129, 12, 0, // Skip to: 19231
+/* 16030 */   MCD_OPC_Decode, 230, 24, 207, 1, // Opcode: VQRSHLsv16i8
+/* 16035 */   MCD_OPC_FilterValue, 243, 1, 118, 12, 0, // Skip to: 19231
+/* 16041 */   MCD_OPC_CheckPredicate, 26, 113, 12, 0, // Skip to: 19231
+/* 16046 */   MCD_OPC_Decode, 238, 24, 207, 1, // Opcode: VQRSHLuv16i8
+/* 16051 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 16091
+/* 16056 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16059 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16075
+/* 16065 */   MCD_OPC_CheckPredicate, 26, 89, 12, 0, // Skip to: 19231
+/* 16070 */   MCD_OPC_Decode, 236, 24, 207, 1, // Opcode: VQRSHLsv8i16
+/* 16075 */   MCD_OPC_FilterValue, 243, 1, 78, 12, 0, // Skip to: 19231
+/* 16081 */   MCD_OPC_CheckPredicate, 26, 73, 12, 0, // Skip to: 19231
+/* 16086 */   MCD_OPC_Decode, 244, 24, 207, 1, // Opcode: VQRSHLuv8i16
+/* 16091 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 16131
+/* 16096 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16099 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16115
+/* 16105 */   MCD_OPC_CheckPredicate, 26, 49, 12, 0, // Skip to: 19231
+/* 16110 */   MCD_OPC_Decode, 235, 24, 207, 1, // Opcode: VQRSHLsv4i32
+/* 16115 */   MCD_OPC_FilterValue, 243, 1, 38, 12, 0, // Skip to: 19231
+/* 16121 */   MCD_OPC_CheckPredicate, 26, 33, 12, 0, // Skip to: 19231
+/* 16126 */   MCD_OPC_Decode, 243, 24, 207, 1, // Opcode: VQRSHLuv4i32
+/* 16131 */   MCD_OPC_FilterValue, 3, 23, 12, 0, // Skip to: 19231
+/* 16136 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16139 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16155
+/* 16145 */   MCD_OPC_CheckPredicate, 26, 9, 12, 0, // Skip to: 19231
+/* 16150 */   MCD_OPC_Decode, 233, 24, 207, 1, // Opcode: VQRSHLsv2i64
+/* 16155 */   MCD_OPC_FilterValue, 243, 1, 254, 11, 0, // Skip to: 19231
+/* 16161 */   MCD_OPC_CheckPredicate, 26, 249, 11, 0, // Skip to: 19231
+/* 16166 */   MCD_OPC_Decode, 241, 24, 207, 1, // Opcode: VQRSHLuv2i64
+/* 16171 */   MCD_OPC_FilterValue, 6, 123, 0, 0, // Skip to: 16299
+/* 16176 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16179 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 16219
+/* 16184 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16187 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16203
+/* 16193 */   MCD_OPC_CheckPredicate, 26, 217, 11, 0, // Skip to: 19231
+/* 16198 */   MCD_OPC_Decode, 161, 22, 203, 1, // Opcode: VMINsv16i8
+/* 16203 */   MCD_OPC_FilterValue, 243, 1, 206, 11, 0, // Skip to: 19231
+/* 16209 */   MCD_OPC_CheckPredicate, 26, 201, 11, 0, // Skip to: 19231
+/* 16214 */   MCD_OPC_Decode, 167, 22, 203, 1, // Opcode: VMINuv16i8
+/* 16219 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 16259
 /* 16224 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 16227 */   MCD_OPC_FilterValue, 242, 1, 9, 0, 0, // Skip to: 16242
-/* 16233 */   MCD_OPC_CheckPredicate, 22, 11, 9, 0, // Skip to: 18553
-/* 16238 */   MCD_OPC_Decode, 218, 13, 106, // Opcode: VMLAhq
-/* 16242 */   MCD_OPC_FilterValue, 243, 1, 1, 9, 0, // Skip to: 18553
-/* 16248 */   MCD_OPC_CheckPredicate, 22, 252, 8, 0, // Skip to: 18553
-/* 16253 */   MCD_OPC_Decode, 197, 14, 98, // Opcode: VMULhq
-/* 16257 */   MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16279
-/* 16262 */   MCD_OPC_CheckPredicate, 21, 238, 8, 0, // Skip to: 18553
-/* 16267 */   MCD_OPC_CheckField, 24, 8, 242, 1, 230, 8, 0, // Skip to: 18553
-/* 16275 */   MCD_OPC_Decode, 247, 13, 106, // Opcode: VMLSfq
-/* 16279 */   MCD_OPC_FilterValue, 3, 221, 8, 0, // Skip to: 18553
-/* 16284 */   MCD_OPC_CheckPredicate, 22, 216, 8, 0, // Skip to: 18553
-/* 16289 */   MCD_OPC_CheckField, 24, 8, 242, 1, 208, 8, 0, // Skip to: 18553
-/* 16297 */   MCD_OPC_Decode, 249, 13, 106, // Opcode: VMLShq
-/* 16301 */   MCD_OPC_FilterValue, 14, 91, 0, 0, // Skip to: 16397
-/* 16306 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 16309 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16331
-/* 16314 */   MCD_OPC_CheckPredicate, 21, 186, 8, 0, // Skip to: 18553
-/* 16319 */   MCD_OPC_CheckField, 24, 8, 243, 1, 178, 8, 0, // Skip to: 18553
-/* 16327 */   MCD_OPC_Decode, 228, 7, 98, // Opcode: VACGEfq
-/* 16331 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16353
-/* 16336 */   MCD_OPC_CheckPredicate, 22, 164, 8, 0, // Skip to: 18553
-/* 16341 */   MCD_OPC_CheckField, 24, 8, 243, 1, 156, 8, 0, // Skip to: 18553
-/* 16349 */   MCD_OPC_Decode, 230, 7, 98, // Opcode: VACGEhq
-/* 16353 */   MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16375
-/* 16358 */   MCD_OPC_CheckPredicate, 21, 142, 8, 0, // Skip to: 18553
-/* 16363 */   MCD_OPC_CheckField, 24, 8, 243, 1, 134, 8, 0, // Skip to: 18553
-/* 16371 */   MCD_OPC_Decode, 232, 7, 98, // Opcode: VACGTfq
-/* 16375 */   MCD_OPC_FilterValue, 3, 125, 8, 0, // Skip to: 18553
-/* 16380 */   MCD_OPC_CheckPredicate, 22, 120, 8, 0, // Skip to: 18553
-/* 16385 */   MCD_OPC_CheckField, 24, 8, 243, 1, 112, 8, 0, // Skip to: 18553
-/* 16393 */   MCD_OPC_Decode, 234, 7, 98, // Opcode: VACGThq
-/* 16397 */   MCD_OPC_FilterValue, 15, 103, 8, 0, // Skip to: 18553
-/* 16402 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 16405 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16427
-/* 16410 */   MCD_OPC_CheckPredicate, 21, 90, 8, 0, // Skip to: 18553
-/* 16415 */   MCD_OPC_CheckField, 24, 8, 242, 1, 82, 8, 0, // Skip to: 18553
-/* 16423 */   MCD_OPC_Decode, 220, 16, 98, // Opcode: VRECPSfq
-/* 16427 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 16449
-/* 16432 */   MCD_OPC_CheckPredicate, 22, 68, 8, 0, // Skip to: 18553
-/* 16437 */   MCD_OPC_CheckField, 24, 8, 242, 1, 60, 8, 0, // Skip to: 18553
-/* 16445 */   MCD_OPC_Decode, 222, 16, 98, // Opcode: VRECPShq
-/* 16449 */   MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 16471
-/* 16454 */   MCD_OPC_CheckPredicate, 21, 46, 8, 0, // Skip to: 18553
-/* 16459 */   MCD_OPC_CheckField, 24, 8, 242, 1, 38, 8, 0, // Skip to: 18553
-/* 16467 */   MCD_OPC_Decode, 206, 17, 98, // Opcode: VRSQRTSfq
-/* 16471 */   MCD_OPC_FilterValue, 3, 29, 8, 0, // Skip to: 18553
-/* 16476 */   MCD_OPC_CheckPredicate, 22, 24, 8, 0, // Skip to: 18553
-/* 16481 */   MCD_OPC_CheckField, 24, 8, 242, 1, 16, 8, 0, // Skip to: 18553
-/* 16489 */   MCD_OPC_Decode, 208, 17, 98, // Opcode: VRSQRTShq
-/* 16493 */   MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 18553
-/* 16498 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 16501 */   MCD_OPC_FilterValue, 0, 217, 6, 0, // Skip to: 18259
-/* 16506 */   MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
-/* 16509 */   MCD_OPC_FilterValue, 121, 247, 7, 0, // Skip to: 18553
-/* 16514 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 16517 */   MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 16661
-/* 16522 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 16525 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16623
-/* 16530 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 16533 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16585
-/* 16538 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16541 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16563
-/* 16546 */   MCD_OPC_CheckPredicate, 21, 239, 5, 0, // Skip to: 18070
-/* 16551 */   MCD_OPC_CheckField, 19, 1, 1, 232, 5, 0, // Skip to: 18070
-/* 16558 */   MCD_OPC_Decode, 155, 18, 166, 1, // Opcode: VSHRsv16i8
-/* 16563 */   MCD_OPC_FilterValue, 1, 222, 5, 0, // Skip to: 18070
-/* 16568 */   MCD_OPC_CheckPredicate, 21, 217, 5, 0, // Skip to: 18070
-/* 16573 */   MCD_OPC_CheckField, 19, 1, 1, 210, 5, 0, // Skip to: 18070
-/* 16580 */   MCD_OPC_Decode, 163, 18, 166, 1, // Opcode: VSHRuv16i8
-/* 16585 */   MCD_OPC_FilterValue, 1, 200, 5, 0, // Skip to: 18070
-/* 16590 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16593 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16608
-/* 16598 */   MCD_OPC_CheckPredicate, 21, 187, 5, 0, // Skip to: 18070
-/* 16603 */   MCD_OPC_Decode, 161, 18, 167, 1, // Opcode: VSHRsv8i16
-/* 16608 */   MCD_OPC_FilterValue, 1, 177, 5, 0, // Skip to: 18070
-/* 16613 */   MCD_OPC_CheckPredicate, 21, 172, 5, 0, // Skip to: 18070
-/* 16618 */   MCD_OPC_Decode, 169, 18, 167, 1, // Opcode: VSHRuv8i16
-/* 16623 */   MCD_OPC_FilterValue, 1, 162, 5, 0, // Skip to: 18070
-/* 16628 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16631 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16646
-/* 16636 */   MCD_OPC_CheckPredicate, 21, 149, 5, 0, // Skip to: 18070
-/* 16641 */   MCD_OPC_Decode, 160, 18, 168, 1, // Opcode: VSHRsv4i32
-/* 16646 */   MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 18070
-/* 16651 */   MCD_OPC_CheckPredicate, 21, 134, 5, 0, // Skip to: 18070
-/* 16656 */   MCD_OPC_Decode, 168, 18, 168, 1, // Opcode: VSHRuv4i32
-/* 16661 */   MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 16805
-/* 16666 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 16669 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16767
-/* 16674 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 16677 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16729
-/* 16682 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16685 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16707
-/* 16690 */   MCD_OPC_CheckPredicate, 21, 95, 5, 0, // Skip to: 18070
-/* 16695 */   MCD_OPC_CheckField, 19, 1, 1, 88, 5, 0, // Skip to: 18070
-/* 16702 */   MCD_OPC_Decode, 191, 18, 169, 1, // Opcode: VSRAsv16i8
-/* 16707 */   MCD_OPC_FilterValue, 1, 78, 5, 0, // Skip to: 18070
-/* 16712 */   MCD_OPC_CheckPredicate, 21, 73, 5, 0, // Skip to: 18070
-/* 16717 */   MCD_OPC_CheckField, 19, 1, 1, 66, 5, 0, // Skip to: 18070
-/* 16724 */   MCD_OPC_Decode, 199, 18, 169, 1, // Opcode: VSRAuv16i8
-/* 16729 */   MCD_OPC_FilterValue, 1, 56, 5, 0, // Skip to: 18070
-/* 16734 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16737 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16752
-/* 16742 */   MCD_OPC_CheckPredicate, 21, 43, 5, 0, // Skip to: 18070
-/* 16747 */   MCD_OPC_Decode, 197, 18, 170, 1, // Opcode: VSRAsv8i16
-/* 16752 */   MCD_OPC_FilterValue, 1, 33, 5, 0, // Skip to: 18070
-/* 16757 */   MCD_OPC_CheckPredicate, 21, 28, 5, 0, // Skip to: 18070
-/* 16762 */   MCD_OPC_Decode, 205, 18, 170, 1, // Opcode: VSRAuv8i16
-/* 16767 */   MCD_OPC_FilterValue, 1, 18, 5, 0, // Skip to: 18070
-/* 16772 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16775 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16790
-/* 16780 */   MCD_OPC_CheckPredicate, 21, 5, 5, 0, // Skip to: 18070
-/* 16785 */   MCD_OPC_Decode, 196, 18, 171, 1, // Opcode: VSRAsv4i32
-/* 16790 */   MCD_OPC_FilterValue, 1, 251, 4, 0, // Skip to: 18070
-/* 16795 */   MCD_OPC_CheckPredicate, 21, 246, 4, 0, // Skip to: 18070
-/* 16800 */   MCD_OPC_Decode, 204, 18, 171, 1, // Opcode: VSRAuv4i32
-/* 16805 */   MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 16949
-/* 16810 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 16813 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 16911
-/* 16818 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 16821 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 16873
-/* 16826 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16829 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16851
-/* 16834 */   MCD_OPC_CheckPredicate, 21, 207, 4, 0, // Skip to: 18070
-/* 16839 */   MCD_OPC_CheckField, 19, 1, 1, 200, 4, 0, // Skip to: 18070
-/* 16846 */   MCD_OPC_Decode, 183, 17, 166, 1, // Opcode: VRSHRsv16i8
-/* 16851 */   MCD_OPC_FilterValue, 1, 190, 4, 0, // Skip to: 18070
-/* 16856 */   MCD_OPC_CheckPredicate, 21, 185, 4, 0, // Skip to: 18070
-/* 16861 */   MCD_OPC_CheckField, 19, 1, 1, 178, 4, 0, // Skip to: 18070
-/* 16868 */   MCD_OPC_Decode, 191, 17, 166, 1, // Opcode: VRSHRuv16i8
-/* 16873 */   MCD_OPC_FilterValue, 1, 168, 4, 0, // Skip to: 18070
-/* 16878 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16881 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16896
-/* 16886 */   MCD_OPC_CheckPredicate, 21, 155, 4, 0, // Skip to: 18070
-/* 16891 */   MCD_OPC_Decode, 189, 17, 167, 1, // Opcode: VRSHRsv8i16
-/* 16896 */   MCD_OPC_FilterValue, 1, 145, 4, 0, // Skip to: 18070
-/* 16901 */   MCD_OPC_CheckPredicate, 21, 140, 4, 0, // Skip to: 18070
-/* 16906 */   MCD_OPC_Decode, 197, 17, 167, 1, // Opcode: VRSHRuv8i16
-/* 16911 */   MCD_OPC_FilterValue, 1, 130, 4, 0, // Skip to: 18070
-/* 16916 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16919 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 16934
-/* 16924 */   MCD_OPC_CheckPredicate, 21, 117, 4, 0, // Skip to: 18070
-/* 16929 */   MCD_OPC_Decode, 188, 17, 168, 1, // Opcode: VRSHRsv4i32
-/* 16934 */   MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 18070
-/* 16939 */   MCD_OPC_CheckPredicate, 21, 102, 4, 0, // Skip to: 18070
-/* 16944 */   MCD_OPC_Decode, 196, 17, 168, 1, // Opcode: VRSHRuv4i32
-/* 16949 */   MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 17093
-/* 16954 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 16957 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17055
-/* 16962 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 16965 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17017
-/* 16970 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 16973 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 16995
-/* 16978 */   MCD_OPC_CheckPredicate, 21, 63, 4, 0, // Skip to: 18070
-/* 16983 */   MCD_OPC_CheckField, 19, 1, 1, 56, 4, 0, // Skip to: 18070
-/* 16990 */   MCD_OPC_Decode, 209, 17, 169, 1, // Opcode: VRSRAsv16i8
-/* 16995 */   MCD_OPC_FilterValue, 1, 46, 4, 0, // Skip to: 18070
-/* 17000 */   MCD_OPC_CheckPredicate, 21, 41, 4, 0, // Skip to: 18070
-/* 17005 */   MCD_OPC_CheckField, 19, 1, 1, 34, 4, 0, // Skip to: 18070
-/* 17012 */   MCD_OPC_Decode, 217, 17, 169, 1, // Opcode: VRSRAuv16i8
-/* 17017 */   MCD_OPC_FilterValue, 1, 24, 4, 0, // Skip to: 18070
-/* 17022 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17025 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17040
-/* 17030 */   MCD_OPC_CheckPredicate, 21, 11, 4, 0, // Skip to: 18070
-/* 17035 */   MCD_OPC_Decode, 215, 17, 170, 1, // Opcode: VRSRAsv8i16
-/* 17040 */   MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 18070
-/* 17045 */   MCD_OPC_CheckPredicate, 21, 252, 3, 0, // Skip to: 18070
-/* 17050 */   MCD_OPC_Decode, 223, 17, 170, 1, // Opcode: VRSRAuv8i16
-/* 17055 */   MCD_OPC_FilterValue, 1, 242, 3, 0, // Skip to: 18070
-/* 17060 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17063 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17078
-/* 17068 */   MCD_OPC_CheckPredicate, 21, 229, 3, 0, // Skip to: 18070
-/* 17073 */   MCD_OPC_Decode, 214, 17, 171, 1, // Opcode: VRSRAsv4i32
-/* 17078 */   MCD_OPC_FilterValue, 1, 219, 3, 0, // Skip to: 18070
-/* 17083 */   MCD_OPC_CheckPredicate, 21, 214, 3, 0, // Skip to: 18070
-/* 17088 */   MCD_OPC_Decode, 222, 17, 171, 1, // Opcode: VRSRAuv4i32
-/* 17093 */   MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 17182
-/* 17098 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 17101 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17160
-/* 17106 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 17109 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17138
-/* 17114 */   MCD_OPC_CheckPredicate, 21, 183, 3, 0, // Skip to: 18070
-/* 17119 */   MCD_OPC_CheckField, 24, 1, 1, 176, 3, 0, // Skip to: 18070
-/* 17126 */   MCD_OPC_CheckField, 19, 1, 1, 169, 3, 0, // Skip to: 18070
-/* 17133 */   MCD_OPC_Decode, 207, 18, 169, 1, // Opcode: VSRIv16i8
-/* 17138 */   MCD_OPC_FilterValue, 1, 159, 3, 0, // Skip to: 18070
-/* 17143 */   MCD_OPC_CheckPredicate, 21, 154, 3, 0, // Skip to: 18070
-/* 17148 */   MCD_OPC_CheckField, 24, 1, 1, 147, 3, 0, // Skip to: 18070
-/* 17155 */   MCD_OPC_Decode, 213, 18, 170, 1, // Opcode: VSRIv8i16
-/* 17160 */   MCD_OPC_FilterValue, 1, 137, 3, 0, // Skip to: 18070
-/* 17165 */   MCD_OPC_CheckPredicate, 21, 132, 3, 0, // Skip to: 18070
-/* 17170 */   MCD_OPC_CheckField, 24, 1, 1, 125, 3, 0, // Skip to: 18070
-/* 17177 */   MCD_OPC_Decode, 212, 18, 171, 1, // Opcode: VSRIv4i32
-/* 17182 */   MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 17326
-/* 17187 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 17190 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17288
-/* 17195 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 17198 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17250
-/* 17203 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17206 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17228
-/* 17211 */   MCD_OPC_CheckPredicate, 21, 86, 3, 0, // Skip to: 18070
-/* 17216 */   MCD_OPC_CheckField, 19, 1, 1, 79, 3, 0, // Skip to: 18070
-/* 17223 */   MCD_OPC_Decode, 128, 18, 172, 1, // Opcode: VSHLiv16i8
-/* 17228 */   MCD_OPC_FilterValue, 1, 69, 3, 0, // Skip to: 18070
-/* 17233 */   MCD_OPC_CheckPredicate, 21, 64, 3, 0, // Skip to: 18070
-/* 17238 */   MCD_OPC_CheckField, 19, 1, 1, 57, 3, 0, // Skip to: 18070
-/* 17245 */   MCD_OPC_Decode, 177, 18, 173, 1, // Opcode: VSLIv16i8
-/* 17250 */   MCD_OPC_FilterValue, 1, 47, 3, 0, // Skip to: 18070
-/* 17255 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17258 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17273
-/* 17263 */   MCD_OPC_CheckPredicate, 21, 34, 3, 0, // Skip to: 18070
-/* 17268 */   MCD_OPC_Decode, 134, 18, 174, 1, // Opcode: VSHLiv8i16
-/* 17273 */   MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 18070
-/* 17278 */   MCD_OPC_CheckPredicate, 21, 19, 3, 0, // Skip to: 18070
-/* 17283 */   MCD_OPC_Decode, 183, 18, 175, 1, // Opcode: VSLIv8i16
-/* 17288 */   MCD_OPC_FilterValue, 1, 9, 3, 0, // Skip to: 18070
-/* 17293 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17296 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17311
-/* 17301 */   MCD_OPC_CheckPredicate, 21, 252, 2, 0, // Skip to: 18070
-/* 17306 */   MCD_OPC_Decode, 133, 18, 176, 1, // Opcode: VSHLiv4i32
-/* 17311 */   MCD_OPC_FilterValue, 1, 242, 2, 0, // Skip to: 18070
-/* 17316 */   MCD_OPC_CheckPredicate, 21, 237, 2, 0, // Skip to: 18070
-/* 17321 */   MCD_OPC_Decode, 182, 18, 177, 1, // Opcode: VSLIv4i32
-/* 17326 */   MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 17415
-/* 17331 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 17334 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17393
-/* 17339 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 17342 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17371
-/* 17347 */   MCD_OPC_CheckPredicate, 21, 206, 2, 0, // Skip to: 18070
-/* 17352 */   MCD_OPC_CheckField, 24, 1, 1, 199, 2, 0, // Skip to: 18070
-/* 17359 */   MCD_OPC_CheckField, 19, 1, 1, 192, 2, 0, // Skip to: 18070
-/* 17366 */   MCD_OPC_Decode, 153, 16, 172, 1, // Opcode: VQSHLsuv16i8
-/* 17371 */   MCD_OPC_FilterValue, 1, 182, 2, 0, // Skip to: 18070
-/* 17376 */   MCD_OPC_CheckPredicate, 21, 177, 2, 0, // Skip to: 18070
-/* 17381 */   MCD_OPC_CheckField, 24, 1, 1, 170, 2, 0, // Skip to: 18070
-/* 17388 */   MCD_OPC_Decode, 159, 16, 174, 1, // Opcode: VQSHLsuv8i16
-/* 17393 */   MCD_OPC_FilterValue, 1, 160, 2, 0, // Skip to: 18070
-/* 17398 */   MCD_OPC_CheckPredicate, 21, 155, 2, 0, // Skip to: 18070
-/* 17403 */   MCD_OPC_CheckField, 24, 1, 1, 148, 2, 0, // Skip to: 18070
-/* 17410 */   MCD_OPC_Decode, 158, 16, 176, 1, // Opcode: VQSHLsuv4i32
-/* 17415 */   MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 17559
-/* 17420 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 17423 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17521
-/* 17428 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 17431 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17483
-/* 17436 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17439 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17461
-/* 17444 */   MCD_OPC_CheckPredicate, 21, 109, 2, 0, // Skip to: 18070
-/* 17449 */   MCD_OPC_CheckField, 19, 1, 1, 102, 2, 0, // Skip to: 18070
-/* 17456 */   MCD_OPC_Decode, 145, 16, 172, 1, // Opcode: VQSHLsiv16i8
-/* 17461 */   MCD_OPC_FilterValue, 1, 92, 2, 0, // Skip to: 18070
-/* 17466 */   MCD_OPC_CheckPredicate, 21, 87, 2, 0, // Skip to: 18070
-/* 17471 */   MCD_OPC_CheckField, 19, 1, 1, 80, 2, 0, // Skip to: 18070
-/* 17478 */   MCD_OPC_Decode, 169, 16, 172, 1, // Opcode: VQSHLuiv16i8
-/* 17483 */   MCD_OPC_FilterValue, 1, 70, 2, 0, // Skip to: 18070
-/* 17488 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17491 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17506
-/* 17496 */   MCD_OPC_CheckPredicate, 21, 57, 2, 0, // Skip to: 18070
-/* 17501 */   MCD_OPC_Decode, 151, 16, 174, 1, // Opcode: VQSHLsiv8i16
-/* 17506 */   MCD_OPC_FilterValue, 1, 47, 2, 0, // Skip to: 18070
-/* 17511 */   MCD_OPC_CheckPredicate, 21, 42, 2, 0, // Skip to: 18070
-/* 17516 */   MCD_OPC_Decode, 175, 16, 174, 1, // Opcode: VQSHLuiv8i16
-/* 17521 */   MCD_OPC_FilterValue, 1, 32, 2, 0, // Skip to: 18070
-/* 17526 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17529 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17544
-/* 17534 */   MCD_OPC_CheckPredicate, 21, 19, 2, 0, // Skip to: 18070
-/* 17539 */   MCD_OPC_Decode, 150, 16, 176, 1, // Opcode: VQSHLsiv4i32
-/* 17544 */   MCD_OPC_FilterValue, 1, 9, 2, 0, // Skip to: 18070
-/* 17549 */   MCD_OPC_CheckPredicate, 21, 4, 2, 0, // Skip to: 18070
-/* 17554 */   MCD_OPC_Decode, 174, 16, 176, 1, // Opcode: VQSHLuiv4i32
-/* 17559 */   MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 17703
-/* 17564 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 17567 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17665
-/* 17572 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 17575 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17627
-/* 17580 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17583 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17605
-/* 17588 */   MCD_OPC_CheckPredicate, 21, 221, 1, 0, // Skip to: 18070
-/* 17593 */   MCD_OPC_CheckField, 19, 1, 1, 214, 1, 0, // Skip to: 18070
-/* 17600 */   MCD_OPC_Decode, 182, 17, 154, 1, // Opcode: VRSHRNv8i8
-/* 17605 */   MCD_OPC_FilterValue, 1, 204, 1, 0, // Skip to: 18070
-/* 17610 */   MCD_OPC_CheckPredicate, 21, 199, 1, 0, // Skip to: 18070
-/* 17615 */   MCD_OPC_CheckField, 19, 1, 1, 192, 1, 0, // Skip to: 18070
-/* 17622 */   MCD_OPC_Decode, 144, 16, 154, 1, // Opcode: VQRSHRUNv8i8
-/* 17627 */   MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 18070
-/* 17632 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17635 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17650
-/* 17640 */   MCD_OPC_CheckPredicate, 21, 169, 1, 0, // Skip to: 18070
-/* 17645 */   MCD_OPC_Decode, 181, 17, 155, 1, // Opcode: VRSHRNv4i16
-/* 17650 */   MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 18070
-/* 17655 */   MCD_OPC_CheckPredicate, 21, 154, 1, 0, // Skip to: 18070
-/* 17660 */   MCD_OPC_Decode, 143, 16, 155, 1, // Opcode: VQRSHRUNv4i16
-/* 17665 */   MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 18070
-/* 17670 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17673 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17688
-/* 17678 */   MCD_OPC_CheckPredicate, 21, 131, 1, 0, // Skip to: 18070
-/* 17683 */   MCD_OPC_Decode, 180, 17, 156, 1, // Opcode: VRSHRNv2i32
-/* 17688 */   MCD_OPC_FilterValue, 1, 121, 1, 0, // Skip to: 18070
-/* 17693 */   MCD_OPC_CheckPredicate, 21, 116, 1, 0, // Skip to: 18070
-/* 17698 */   MCD_OPC_Decode, 142, 16, 156, 1, // Opcode: VQRSHRUNv2i32
-/* 17703 */   MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 17847
-/* 17708 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 17711 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17809
-/* 17716 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 17719 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17771
-/* 17724 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17727 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17749
-/* 17732 */   MCD_OPC_CheckPredicate, 21, 77, 1, 0, // Skip to: 18070
-/* 17737 */   MCD_OPC_CheckField, 19, 1, 1, 70, 1, 0, // Skip to: 18070
-/* 17744 */   MCD_OPC_Decode, 138, 16, 154, 1, // Opcode: VQRSHRNsv8i8
-/* 17749 */   MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 18070
-/* 17754 */   MCD_OPC_CheckPredicate, 21, 55, 1, 0, // Skip to: 18070
-/* 17759 */   MCD_OPC_CheckField, 19, 1, 1, 48, 1, 0, // Skip to: 18070
-/* 17766 */   MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: VQRSHRNuv8i8
-/* 17771 */   MCD_OPC_FilterValue, 1, 38, 1, 0, // Skip to: 18070
-/* 17776 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17779 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17794
-/* 17784 */   MCD_OPC_CheckPredicate, 21, 25, 1, 0, // Skip to: 18070
-/* 17789 */   MCD_OPC_Decode, 137, 16, 155, 1, // Opcode: VQRSHRNsv4i16
-/* 17794 */   MCD_OPC_FilterValue, 1, 15, 1, 0, // Skip to: 18070
-/* 17799 */   MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 18070
-/* 17804 */   MCD_OPC_Decode, 140, 16, 155, 1, // Opcode: VQRSHRNuv4i16
-/* 17809 */   MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 18070
-/* 17814 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17817 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17832
-/* 17822 */   MCD_OPC_CheckPredicate, 21, 243, 0, 0, // Skip to: 18070
-/* 17827 */   MCD_OPC_Decode, 136, 16, 156, 1, // Opcode: VQRSHRNsv2i32
-/* 17832 */   MCD_OPC_FilterValue, 1, 233, 0, 0, // Skip to: 18070
-/* 17837 */   MCD_OPC_CheckPredicate, 21, 228, 0, 0, // Skip to: 18070
-/* 17842 */   MCD_OPC_Decode, 139, 16, 156, 1, // Opcode: VQRSHRNuv2i32
-/* 17847 */   MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 17885
-/* 17852 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17855 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17870
-/* 17860 */   MCD_OPC_CheckPredicate, 22, 205, 0, 0, // Skip to: 18070
-/* 17865 */   MCD_OPC_Decode, 248, 9, 178, 1, // Opcode: VCVTxs2hq
-/* 17870 */   MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 18070
-/* 17875 */   MCD_OPC_CheckPredicate, 22, 190, 0, 0, // Skip to: 18070
-/* 17880 */   MCD_OPC_Decode, 252, 9, 178, 1, // Opcode: VCVTxu2hq
-/* 17885 */   MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 17923
-/* 17890 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17893 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17908
-/* 17898 */   MCD_OPC_CheckPredicate, 22, 167, 0, 0, // Skip to: 18070
-/* 17903 */   MCD_OPC_Decode, 234, 9, 178, 1, // Opcode: VCVTh2xsq
-/* 17908 */   MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 18070
-/* 17913 */   MCD_OPC_CheckPredicate, 22, 152, 0, 0, // Skip to: 18070
-/* 17918 */   MCD_OPC_Decode, 236, 9, 178, 1, // Opcode: VCVTh2xuq
-/* 17923 */   MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 18008
-/* 17928 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 17931 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17953
-/* 17936 */   MCD_OPC_CheckPredicate, 21, 34, 0, 0, // Skip to: 17975
-/* 17941 */   MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 17975
-/* 17948 */   MCD_OPC_Decode, 156, 14, 161, 1, // Opcode: VMOVv16i8
-/* 17953 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 17975
-/* 17958 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 17975
-/* 17963 */   MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 17975
-/* 17970 */   MCD_OPC_Decode, 160, 14, 161, 1, // Opcode: VMOVv2i64
-/* 17975 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 17978 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17993
-/* 17983 */   MCD_OPC_CheckPredicate, 21, 82, 0, 0, // Skip to: 18070
-/* 17988 */   MCD_OPC_Decode, 246, 9, 178, 1, // Opcode: VCVTxs2fq
-/* 17993 */   MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 18070
-/* 17998 */   MCD_OPC_CheckPredicate, 21, 67, 0, 0, // Skip to: 18070
-/* 18003 */   MCD_OPC_Decode, 250, 9, 178, 1, // Opcode: VCVTxu2fq
-/* 18008 */   MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 18070
-/* 18013 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
-/* 18016 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18031
-/* 18021 */   MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 18046
-/* 18026 */   MCD_OPC_Decode, 225, 9, 178, 1, // Opcode: VCVTf2xsq
-/* 18031 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18046
-/* 18036 */   MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18046
-/* 18041 */   MCD_OPC_Decode, 227, 9, 178, 1, // Opcode: VCVTf2xuq
-/* 18046 */   MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 18070
-/* 18051 */   MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 18070
-/* 18058 */   MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 18070
-/* 18065 */   MCD_OPC_Decode, 161, 14, 161, 1, // Opcode: VMOVv4f32
-/* 18070 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 18073 */   MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 18166
-/* 18078 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
-/* 18081 */   MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 18553
-/* 18086 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 18089 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18111
-/* 18094 */   MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18156
-/* 18099 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18156
-/* 18106 */   MCD_OPC_Decode, 164, 14, 161, 1, // Opcode: VMOVv8i16
-/* 18111 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18156
-/* 18116 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
-/* 18119 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18134
-/* 18124 */   MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18156
-/* 18129 */   MCD_OPC_Decode, 247, 14, 161, 1, // Opcode: VORRiv4i32
-/* 18134 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18156
-/* 18139 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18156
-/* 18144 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18156
-/* 18151 */   MCD_OPC_Decode, 248, 14, 161, 1, // Opcode: VORRiv8i16
-/* 18156 */   MCD_OPC_CheckPredicate, 21, 136, 1, 0, // Skip to: 18553
-/* 18161 */   MCD_OPC_Decode, 163, 14, 161, 1, // Opcode: VMOVv4i32
-/* 18166 */   MCD_OPC_FilterValue, 1, 126, 1, 0, // Skip to: 18553
-/* 18171 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
-/* 18174 */   MCD_OPC_FilterValue, 0, 118, 1, 0, // Skip to: 18553
-/* 18179 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 18182 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18204
-/* 18187 */   MCD_OPC_CheckPredicate, 21, 57, 0, 0, // Skip to: 18249
-/* 18192 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18249
-/* 18199 */   MCD_OPC_Decode, 219, 14, 161, 1, // Opcode: VMVNv8i16
-/* 18204 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18249
-/* 18209 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
-/* 18212 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18227
-/* 18217 */   MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 18249
-/* 18222 */   MCD_OPC_Decode, 142, 8, 161, 1, // Opcode: VBICiv4i32
-/* 18227 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18249
-/* 18232 */   MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 18249
-/* 18237 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18249
-/* 18244 */   MCD_OPC_Decode, 143, 8, 161, 1, // Opcode: VBICiv8i16
-/* 18249 */   MCD_OPC_CheckPredicate, 21, 43, 1, 0, // Skip to: 18553
-/* 18254 */   MCD_OPC_Decode, 218, 14, 161, 1, // Opcode: VMVNv4i32
-/* 18259 */   MCD_OPC_FilterValue, 1, 33, 1, 0, // Skip to: 18553
-/* 18264 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 18267 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 18307
-/* 18272 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 18275 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18291
-/* 18281 */   MCD_OPC_CheckPredicate, 21, 11, 1, 0, // Skip to: 18553
-/* 18286 */   MCD_OPC_Decode, 158, 18, 179, 1, // Opcode: VSHRsv2i64
-/* 18291 */   MCD_OPC_FilterValue, 243, 1, 0, 1, 0, // Skip to: 18553
-/* 18297 */   MCD_OPC_CheckPredicate, 21, 251, 0, 0, // Skip to: 18553
-/* 18302 */   MCD_OPC_Decode, 166, 18, 179, 1, // Opcode: VSHRuv2i64
-/* 18307 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 18347
-/* 18312 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 18315 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18331
-/* 18321 */   MCD_OPC_CheckPredicate, 21, 227, 0, 0, // Skip to: 18553
-/* 18326 */   MCD_OPC_Decode, 194, 18, 180, 1, // Opcode: VSRAsv2i64
-/* 18331 */   MCD_OPC_FilterValue, 243, 1, 216, 0, 0, // Skip to: 18553
-/* 18337 */   MCD_OPC_CheckPredicate, 21, 211, 0, 0, // Skip to: 18553
-/* 18342 */   MCD_OPC_Decode, 202, 18, 180, 1, // Opcode: VSRAuv2i64
-/* 18347 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 18387
-/* 18352 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 18355 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18371
-/* 18361 */   MCD_OPC_CheckPredicate, 21, 187, 0, 0, // Skip to: 18553
-/* 18366 */   MCD_OPC_Decode, 186, 17, 179, 1, // Opcode: VRSHRsv2i64
-/* 18371 */   MCD_OPC_FilterValue, 243, 1, 176, 0, 0, // Skip to: 18553
-/* 18377 */   MCD_OPC_CheckPredicate, 21, 171, 0, 0, // Skip to: 18553
-/* 18382 */   MCD_OPC_Decode, 194, 17, 179, 1, // Opcode: VRSHRuv2i64
-/* 18387 */   MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 18427
-/* 18392 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 18395 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18411
-/* 18401 */   MCD_OPC_CheckPredicate, 21, 147, 0, 0, // Skip to: 18553
-/* 18406 */   MCD_OPC_Decode, 212, 17, 180, 1, // Opcode: VRSRAsv2i64
-/* 18411 */   MCD_OPC_FilterValue, 243, 1, 136, 0, 0, // Skip to: 18553
-/* 18417 */   MCD_OPC_CheckPredicate, 21, 131, 0, 0, // Skip to: 18553
-/* 18422 */   MCD_OPC_Decode, 220, 17, 180, 1, // Opcode: VRSRAuv2i64
-/* 18427 */   MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 18450
-/* 18432 */   MCD_OPC_CheckPredicate, 21, 116, 0, 0, // Skip to: 18553
-/* 18437 */   MCD_OPC_CheckField, 24, 8, 243, 1, 108, 0, 0, // Skip to: 18553
-/* 18445 */   MCD_OPC_Decode, 210, 18, 180, 1, // Opcode: VSRIv2i64
-/* 18450 */   MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 18490
-/* 18455 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 18458 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18474
-/* 18464 */   MCD_OPC_CheckPredicate, 21, 84, 0, 0, // Skip to: 18553
-/* 18469 */   MCD_OPC_Decode, 131, 18, 181, 1, // Opcode: VSHLiv2i64
-/* 18474 */   MCD_OPC_FilterValue, 243, 1, 73, 0, 0, // Skip to: 18553
-/* 18480 */   MCD_OPC_CheckPredicate, 21, 68, 0, 0, // Skip to: 18553
-/* 18485 */   MCD_OPC_Decode, 180, 18, 182, 1, // Opcode: VSLIv2i64
-/* 18490 */   MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 18513
-/* 18495 */   MCD_OPC_CheckPredicate, 21, 53, 0, 0, // Skip to: 18553
-/* 18500 */   MCD_OPC_CheckField, 24, 8, 243, 1, 45, 0, 0, // Skip to: 18553
-/* 18508 */   MCD_OPC_Decode, 156, 16, 181, 1, // Opcode: VQSHLsuv2i64
-/* 18513 */   MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 18553
-/* 18518 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
-/* 18521 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18537
-/* 18527 */   MCD_OPC_CheckPredicate, 21, 21, 0, 0, // Skip to: 18553
-/* 18532 */   MCD_OPC_Decode, 148, 16, 181, 1, // Opcode: VQSHLsiv2i64
-/* 18537 */   MCD_OPC_FilterValue, 243, 1, 10, 0, 0, // Skip to: 18553
-/* 18543 */   MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 18553
-/* 18548 */   MCD_OPC_Decode, 172, 16, 181, 1, // Opcode: VQSHLuiv2i64
-/* 18553 */   MCD_OPC_Fail,
+/* 16227 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16243
+/* 16233 */   MCD_OPC_CheckPredicate, 26, 177, 11, 0, // Skip to: 19231
+/* 16238 */   MCD_OPC_Decode, 165, 22, 203, 1, // Opcode: VMINsv8i16
+/* 16243 */   MCD_OPC_FilterValue, 243, 1, 166, 11, 0, // Skip to: 19231
+/* 16249 */   MCD_OPC_CheckPredicate, 26, 161, 11, 0, // Skip to: 19231
+/* 16254 */   MCD_OPC_Decode, 171, 22, 203, 1, // Opcode: VMINuv8i16
+/* 16259 */   MCD_OPC_FilterValue, 2, 151, 11, 0, // Skip to: 19231
+/* 16264 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16267 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16283
+/* 16273 */   MCD_OPC_CheckPredicate, 26, 137, 11, 0, // Skip to: 19231
+/* 16278 */   MCD_OPC_Decode, 164, 22, 203, 1, // Opcode: VMINsv4i32
+/* 16283 */   MCD_OPC_FilterValue, 243, 1, 126, 11, 0, // Skip to: 19231
+/* 16289 */   MCD_OPC_CheckPredicate, 26, 121, 11, 0, // Skip to: 19231
+/* 16294 */   MCD_OPC_Decode, 170, 22, 203, 1, // Opcode: VMINuv4i32
+/* 16299 */   MCD_OPC_FilterValue, 7, 123, 0, 0, // Skip to: 16427
+/* 16304 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16307 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 16347
+/* 16312 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16315 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16331
+/* 16321 */   MCD_OPC_CheckPredicate, 26, 89, 11, 0, // Skip to: 19231
+/* 16326 */   MCD_OPC_Decode, 223, 15, 211, 1, // Opcode: VABAsv16i8
+/* 16331 */   MCD_OPC_FilterValue, 243, 1, 78, 11, 0, // Skip to: 19231
+/* 16337 */   MCD_OPC_CheckPredicate, 26, 73, 11, 0, // Skip to: 19231
+/* 16342 */   MCD_OPC_Decode, 229, 15, 211, 1, // Opcode: VABAuv16i8
+/* 16347 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 16387
+/* 16352 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16355 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16371
+/* 16361 */   MCD_OPC_CheckPredicate, 26, 49, 11, 0, // Skip to: 19231
+/* 16366 */   MCD_OPC_Decode, 227, 15, 211, 1, // Opcode: VABAsv8i16
+/* 16371 */   MCD_OPC_FilterValue, 243, 1, 38, 11, 0, // Skip to: 19231
+/* 16377 */   MCD_OPC_CheckPredicate, 26, 33, 11, 0, // Skip to: 19231
+/* 16382 */   MCD_OPC_Decode, 233, 15, 211, 1, // Opcode: VABAuv8i16
+/* 16387 */   MCD_OPC_FilterValue, 2, 23, 11, 0, // Skip to: 19231
+/* 16392 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16395 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16411
+/* 16401 */   MCD_OPC_CheckPredicate, 26, 9, 11, 0, // Skip to: 19231
+/* 16406 */   MCD_OPC_Decode, 226, 15, 211, 1, // Opcode: VABAsv4i32
+/* 16411 */   MCD_OPC_FilterValue, 243, 1, 254, 10, 0, // Skip to: 19231
+/* 16417 */   MCD_OPC_CheckPredicate, 26, 249, 10, 0, // Skip to: 19231
+/* 16422 */   MCD_OPC_Decode, 232, 15, 211, 1, // Opcode: VABAuv4i32
+/* 16427 */   MCD_OPC_FilterValue, 8, 123, 0, 0, // Skip to: 16555
+/* 16432 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16435 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 16475
+/* 16440 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16443 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16459
+/* 16449 */   MCD_OPC_CheckPredicate, 26, 217, 10, 0, // Skip to: 19231
+/* 16454 */   MCD_OPC_Decode, 178, 30, 203, 1, // Opcode: VTSTv16i8
+/* 16459 */   MCD_OPC_FilterValue, 243, 1, 206, 10, 0, // Skip to: 19231
+/* 16465 */   MCD_OPC_CheckPredicate, 26, 201, 10, 0, // Skip to: 19231
+/* 16470 */   MCD_OPC_Decode, 208, 16, 203, 1, // Opcode: VCEQv16i8
+/* 16475 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 16515
+/* 16480 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16483 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16499
+/* 16489 */   MCD_OPC_CheckPredicate, 26, 177, 10, 0, // Skip to: 19231
+/* 16494 */   MCD_OPC_Decode, 182, 30, 203, 1, // Opcode: VTSTv8i16
+/* 16499 */   MCD_OPC_FilterValue, 243, 1, 166, 10, 0, // Skip to: 19231
+/* 16505 */   MCD_OPC_CheckPredicate, 26, 161, 10, 0, // Skip to: 19231
+/* 16510 */   MCD_OPC_Decode, 212, 16, 203, 1, // Opcode: VCEQv8i16
+/* 16515 */   MCD_OPC_FilterValue, 2, 151, 10, 0, // Skip to: 19231
+/* 16520 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16523 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16539
+/* 16529 */   MCD_OPC_CheckPredicate, 26, 137, 10, 0, // Skip to: 19231
+/* 16534 */   MCD_OPC_Decode, 181, 30, 203, 1, // Opcode: VTSTv4i32
+/* 16539 */   MCD_OPC_FilterValue, 243, 1, 126, 10, 0, // Skip to: 19231
+/* 16545 */   MCD_OPC_CheckPredicate, 26, 121, 10, 0, // Skip to: 19231
+/* 16550 */   MCD_OPC_Decode, 211, 16, 203, 1, // Opcode: VCEQv4i32
+/* 16555 */   MCD_OPC_FilterValue, 9, 89, 0, 0, // Skip to: 16649
+/* 16560 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16563 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 16603
+/* 16568 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16571 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16587
+/* 16577 */   MCD_OPC_CheckPredicate, 26, 89, 10, 0, // Skip to: 19231
+/* 16582 */   MCD_OPC_Decode, 190, 23, 203, 1, // Opcode: VMULv16i8
+/* 16587 */   MCD_OPC_FilterValue, 243, 1, 78, 10, 0, // Skip to: 19231
+/* 16593 */   MCD_OPC_CheckPredicate, 26, 73, 10, 0, // Skip to: 19231
+/* 16598 */   MCD_OPC_Decode, 181, 23, 203, 1, // Opcode: VMULpq
+/* 16603 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 16626
+/* 16608 */   MCD_OPC_CheckPredicate, 26, 58, 10, 0, // Skip to: 19231
+/* 16613 */   MCD_OPC_CheckField, 24, 8, 242, 1, 50, 10, 0, // Skip to: 19231
+/* 16621 */   MCD_OPC_Decode, 194, 23, 203, 1, // Opcode: VMULv8i16
+/* 16626 */   MCD_OPC_FilterValue, 2, 40, 10, 0, // Skip to: 19231
+/* 16631 */   MCD_OPC_CheckPredicate, 26, 35, 10, 0, // Skip to: 19231
+/* 16636 */   MCD_OPC_CheckField, 24, 8, 242, 1, 27, 10, 0, // Skip to: 19231
+/* 16644 */   MCD_OPC_Decode, 193, 23, 203, 1, // Opcode: VMULv4i32
+/* 16649 */   MCD_OPC_FilterValue, 11, 49, 0, 0, // Skip to: 16703
+/* 16654 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16657 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 16680
+/* 16662 */   MCD_OPC_CheckPredicate, 28, 4, 10, 0, // Skip to: 19231
+/* 16667 */   MCD_OPC_CheckField, 24, 8, 243, 1, 252, 9, 0, // Skip to: 19231
+/* 16675 */   MCD_OPC_Decode, 213, 24, 211, 1, // Opcode: VQRDMLAHv8i16
+/* 16680 */   MCD_OPC_FilterValue, 2, 242, 9, 0, // Skip to: 19231
+/* 16685 */   MCD_OPC_CheckPredicate, 28, 237, 9, 0, // Skip to: 19231
+/* 16690 */   MCD_OPC_CheckField, 24, 8, 243, 1, 229, 9, 0, // Skip to: 19231
+/* 16698 */   MCD_OPC_Decode, 212, 24, 211, 1, // Opcode: VQRDMLAHv4i32
+/* 16703 */   MCD_OPC_FilterValue, 12, 129, 0, 0, // Skip to: 16837
+/* 16708 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16711 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 16734
+/* 16716 */   MCD_OPC_CheckPredicate, 32, 206, 9, 0, // Skip to: 19231
+/* 16721 */   MCD_OPC_CheckField, 24, 8, 242, 1, 198, 9, 0, // Skip to: 19231
+/* 16729 */   MCD_OPC_Decode, 206, 18, 211, 1, // Opcode: VFMAfq
+/* 16734 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 16774
+/* 16739 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16742 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16758
+/* 16748 */   MCD_OPC_CheckPredicate, 27, 174, 9, 0, // Skip to: 19231
+/* 16753 */   MCD_OPC_Decode, 208, 18, 211, 1, // Opcode: VFMAhq
+/* 16758 */   MCD_OPC_FilterValue, 243, 1, 163, 9, 0, // Skip to: 19231
+/* 16764 */   MCD_OPC_CheckPredicate, 28, 158, 9, 0, // Skip to: 19231
+/* 16769 */   MCD_OPC_Decode, 221, 24, 211, 1, // Opcode: VQRDMLSHv8i16
+/* 16774 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 16814
+/* 16779 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16782 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16798
+/* 16788 */   MCD_OPC_CheckPredicate, 32, 134, 9, 0, // Skip to: 19231
+/* 16793 */   MCD_OPC_Decode, 217, 18, 211, 1, // Opcode: VFMSfq
+/* 16798 */   MCD_OPC_FilterValue, 243, 1, 123, 9, 0, // Skip to: 19231
+/* 16804 */   MCD_OPC_CheckPredicate, 28, 118, 9, 0, // Skip to: 19231
+/* 16809 */   MCD_OPC_Decode, 220, 24, 211, 1, // Opcode: VQRDMLSHv4i32
+/* 16814 */   MCD_OPC_FilterValue, 3, 108, 9, 0, // Skip to: 19231
+/* 16819 */   MCD_OPC_CheckPredicate, 27, 103, 9, 0, // Skip to: 19231
+/* 16824 */   MCD_OPC_CheckField, 24, 8, 242, 1, 95, 9, 0, // Skip to: 19231
+/* 16832 */   MCD_OPC_Decode, 219, 18, 211, 1, // Opcode: VFMShq
+/* 16837 */   MCD_OPC_FilterValue, 13, 129, 0, 0, // Skip to: 16971
+/* 16842 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16845 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 16885
+/* 16850 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16853 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16869
+/* 16859 */   MCD_OPC_CheckPredicate, 26, 63, 9, 0, // Skip to: 19231
+/* 16864 */   MCD_OPC_Decode, 187, 22, 211, 1, // Opcode: VMLAfq
+/* 16869 */   MCD_OPC_FilterValue, 243, 1, 52, 9, 0, // Skip to: 19231
+/* 16875 */   MCD_OPC_CheckPredicate, 26, 47, 9, 0, // Skip to: 19231
+/* 16880 */   MCD_OPC_Decode, 177, 23, 203, 1, // Opcode: VMULfq
+/* 16885 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 16925
+/* 16890 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 16893 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 16909
+/* 16899 */   MCD_OPC_CheckPredicate, 27, 23, 9, 0, // Skip to: 19231
+/* 16904 */   MCD_OPC_Decode, 189, 22, 211, 1, // Opcode: VMLAhq
+/* 16909 */   MCD_OPC_FilterValue, 243, 1, 12, 9, 0, // Skip to: 19231
+/* 16915 */   MCD_OPC_CheckPredicate, 27, 7, 9, 0, // Skip to: 19231
+/* 16920 */   MCD_OPC_Decode, 179, 23, 203, 1, // Opcode: VMULhq
+/* 16925 */   MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 16948
+/* 16930 */   MCD_OPC_CheckPredicate, 26, 248, 8, 0, // Skip to: 19231
+/* 16935 */   MCD_OPC_CheckField, 24, 8, 242, 1, 240, 8, 0, // Skip to: 19231
+/* 16943 */   MCD_OPC_Decode, 218, 22, 211, 1, // Opcode: VMLSfq
+/* 16948 */   MCD_OPC_FilterValue, 3, 230, 8, 0, // Skip to: 19231
+/* 16953 */   MCD_OPC_CheckPredicate, 27, 225, 8, 0, // Skip to: 19231
+/* 16958 */   MCD_OPC_CheckField, 24, 8, 242, 1, 217, 8, 0, // Skip to: 19231
+/* 16966 */   MCD_OPC_Decode, 220, 22, 211, 1, // Opcode: VMLShq
+/* 16971 */   MCD_OPC_FilterValue, 14, 95, 0, 0, // Skip to: 17071
+/* 16976 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 16979 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 17002
+/* 16984 */   MCD_OPC_CheckPredicate, 26, 194, 8, 0, // Skip to: 19231
+/* 16989 */   MCD_OPC_CheckField, 24, 8, 243, 1, 186, 8, 0, // Skip to: 19231
+/* 16997 */   MCD_OPC_Decode, 143, 16, 203, 1, // Opcode: VACGEfq
+/* 17002 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 17025
+/* 17007 */   MCD_OPC_CheckPredicate, 27, 171, 8, 0, // Skip to: 19231
+/* 17012 */   MCD_OPC_CheckField, 24, 8, 243, 1, 163, 8, 0, // Skip to: 19231
+/* 17020 */   MCD_OPC_Decode, 145, 16, 203, 1, // Opcode: VACGEhq
+/* 17025 */   MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 17048
+/* 17030 */   MCD_OPC_CheckPredicate, 26, 148, 8, 0, // Skip to: 19231
+/* 17035 */   MCD_OPC_CheckField, 24, 8, 243, 1, 140, 8, 0, // Skip to: 19231
+/* 17043 */   MCD_OPC_Decode, 147, 16, 203, 1, // Opcode: VACGTfq
+/* 17048 */   MCD_OPC_FilterValue, 3, 130, 8, 0, // Skip to: 19231
+/* 17053 */   MCD_OPC_CheckPredicate, 27, 125, 8, 0, // Skip to: 19231
+/* 17058 */   MCD_OPC_CheckField, 24, 8, 243, 1, 117, 8, 0, // Skip to: 19231
+/* 17066 */   MCD_OPC_Decode, 149, 16, 203, 1, // Opcode: VACGThq
+/* 17071 */   MCD_OPC_FilterValue, 15, 107, 8, 0, // Skip to: 19231
+/* 17076 */   MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 17079 */   MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 17102
+/* 17084 */   MCD_OPC_CheckPredicate, 26, 94, 8, 0, // Skip to: 19231
+/* 17089 */   MCD_OPC_CheckField, 24, 8, 242, 1, 86, 8, 0, // Skip to: 19231
+/* 17097 */   MCD_OPC_Decode, 202, 25, 203, 1, // Opcode: VRECPSfq
+/* 17102 */   MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 17125
+/* 17107 */   MCD_OPC_CheckPredicate, 27, 71, 8, 0, // Skip to: 19231
+/* 17112 */   MCD_OPC_CheckField, 24, 8, 242, 1, 63, 8, 0, // Skip to: 19231
+/* 17120 */   MCD_OPC_Decode, 204, 25, 203, 1, // Opcode: VRECPShq
+/* 17125 */   MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 17148
+/* 17130 */   MCD_OPC_CheckPredicate, 26, 48, 8, 0, // Skip to: 19231
+/* 17135 */   MCD_OPC_CheckField, 24, 8, 242, 1, 40, 8, 0, // Skip to: 19231
+/* 17143 */   MCD_OPC_Decode, 188, 26, 203, 1, // Opcode: VRSQRTSfq
+/* 17148 */   MCD_OPC_FilterValue, 3, 30, 8, 0, // Skip to: 19231
+/* 17153 */   MCD_OPC_CheckPredicate, 27, 25, 8, 0, // Skip to: 19231
+/* 17158 */   MCD_OPC_CheckField, 24, 8, 242, 1, 17, 8, 0, // Skip to: 19231
+/* 17166 */   MCD_OPC_Decode, 190, 26, 203, 1, // Opcode: VRSQRTShq
+/* 17171 */   MCD_OPC_FilterValue, 1, 7, 8, 0, // Skip to: 19231
+/* 17176 */   MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 17179 */   MCD_OPC_FilterValue, 0, 217, 6, 0, // Skip to: 18937
+/* 17184 */   MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
+/* 17187 */   MCD_OPC_FilterValue, 121, 247, 7, 0, // Skip to: 19231
+/* 17192 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 17195 */   MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 17339
+/* 17200 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 17203 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17301
+/* 17208 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 17211 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17263
+/* 17216 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17219 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17241
+/* 17224 */   MCD_OPC_CheckPredicate, 26, 239, 5, 0, // Skip to: 18748
+/* 17229 */   MCD_OPC_CheckField, 19, 1, 1, 232, 5, 0, // Skip to: 18748
+/* 17236 */   MCD_OPC_Decode, 139, 27, 143, 2, // Opcode: VSHRsv16i8
+/* 17241 */   MCD_OPC_FilterValue, 1, 222, 5, 0, // Skip to: 18748
+/* 17246 */   MCD_OPC_CheckPredicate, 26, 217, 5, 0, // Skip to: 18748
+/* 17251 */   MCD_OPC_CheckField, 19, 1, 1, 210, 5, 0, // Skip to: 18748
+/* 17258 */   MCD_OPC_Decode, 147, 27, 143, 2, // Opcode: VSHRuv16i8
+/* 17263 */   MCD_OPC_FilterValue, 1, 200, 5, 0, // Skip to: 18748
+/* 17268 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17271 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17286
+/* 17276 */   MCD_OPC_CheckPredicate, 26, 187, 5, 0, // Skip to: 18748
+/* 17281 */   MCD_OPC_Decode, 145, 27, 144, 2, // Opcode: VSHRsv8i16
+/* 17286 */   MCD_OPC_FilterValue, 1, 177, 5, 0, // Skip to: 18748
+/* 17291 */   MCD_OPC_CheckPredicate, 26, 172, 5, 0, // Skip to: 18748
+/* 17296 */   MCD_OPC_Decode, 153, 27, 144, 2, // Opcode: VSHRuv8i16
+/* 17301 */   MCD_OPC_FilterValue, 1, 162, 5, 0, // Skip to: 18748
+/* 17306 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17309 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17324
+/* 17314 */   MCD_OPC_CheckPredicate, 26, 149, 5, 0, // Skip to: 18748
+/* 17319 */   MCD_OPC_Decode, 144, 27, 145, 2, // Opcode: VSHRsv4i32
+/* 17324 */   MCD_OPC_FilterValue, 1, 139, 5, 0, // Skip to: 18748
+/* 17329 */   MCD_OPC_CheckPredicate, 26, 134, 5, 0, // Skip to: 18748
+/* 17334 */   MCD_OPC_Decode, 152, 27, 145, 2, // Opcode: VSHRuv4i32
+/* 17339 */   MCD_OPC_FilterValue, 1, 139, 0, 0, // Skip to: 17483
+/* 17344 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 17347 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17445
+/* 17352 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 17355 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17407
+/* 17360 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17363 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17385
+/* 17368 */   MCD_OPC_CheckPredicate, 26, 95, 5, 0, // Skip to: 18748
+/* 17373 */   MCD_OPC_CheckField, 19, 1, 1, 88, 5, 0, // Skip to: 18748
+/* 17380 */   MCD_OPC_Decode, 176, 27, 146, 2, // Opcode: VSRAsv16i8
+/* 17385 */   MCD_OPC_FilterValue, 1, 78, 5, 0, // Skip to: 18748
+/* 17390 */   MCD_OPC_CheckPredicate, 26, 73, 5, 0, // Skip to: 18748
+/* 17395 */   MCD_OPC_CheckField, 19, 1, 1, 66, 5, 0, // Skip to: 18748
+/* 17402 */   MCD_OPC_Decode, 184, 27, 146, 2, // Opcode: VSRAuv16i8
+/* 17407 */   MCD_OPC_FilterValue, 1, 56, 5, 0, // Skip to: 18748
+/* 17412 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17415 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17430
+/* 17420 */   MCD_OPC_CheckPredicate, 26, 43, 5, 0, // Skip to: 18748
+/* 17425 */   MCD_OPC_Decode, 182, 27, 147, 2, // Opcode: VSRAsv8i16
+/* 17430 */   MCD_OPC_FilterValue, 1, 33, 5, 0, // Skip to: 18748
+/* 17435 */   MCD_OPC_CheckPredicate, 26, 28, 5, 0, // Skip to: 18748
+/* 17440 */   MCD_OPC_Decode, 190, 27, 147, 2, // Opcode: VSRAuv8i16
+/* 17445 */   MCD_OPC_FilterValue, 1, 18, 5, 0, // Skip to: 18748
+/* 17450 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17453 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17468
+/* 17458 */   MCD_OPC_CheckPredicate, 26, 5, 5, 0, // Skip to: 18748
+/* 17463 */   MCD_OPC_Decode, 181, 27, 148, 2, // Opcode: VSRAsv4i32
+/* 17468 */   MCD_OPC_FilterValue, 1, 251, 4, 0, // Skip to: 18748
+/* 17473 */   MCD_OPC_CheckPredicate, 26, 246, 4, 0, // Skip to: 18748
+/* 17478 */   MCD_OPC_Decode, 189, 27, 148, 2, // Opcode: VSRAuv4i32
+/* 17483 */   MCD_OPC_FilterValue, 2, 139, 0, 0, // Skip to: 17627
+/* 17488 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 17491 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17589
+/* 17496 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 17499 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17551
+/* 17504 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17507 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17529
+/* 17512 */   MCD_OPC_CheckPredicate, 26, 207, 4, 0, // Skip to: 18748
+/* 17517 */   MCD_OPC_CheckField, 19, 1, 1, 200, 4, 0, // Skip to: 18748
+/* 17524 */   MCD_OPC_Decode, 165, 26, 143, 2, // Opcode: VRSHRsv16i8
+/* 17529 */   MCD_OPC_FilterValue, 1, 190, 4, 0, // Skip to: 18748
+/* 17534 */   MCD_OPC_CheckPredicate, 26, 185, 4, 0, // Skip to: 18748
+/* 17539 */   MCD_OPC_CheckField, 19, 1, 1, 178, 4, 0, // Skip to: 18748
+/* 17546 */   MCD_OPC_Decode, 173, 26, 143, 2, // Opcode: VRSHRuv16i8
+/* 17551 */   MCD_OPC_FilterValue, 1, 168, 4, 0, // Skip to: 18748
+/* 17556 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17559 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17574
+/* 17564 */   MCD_OPC_CheckPredicate, 26, 155, 4, 0, // Skip to: 18748
+/* 17569 */   MCD_OPC_Decode, 171, 26, 144, 2, // Opcode: VRSHRsv8i16
+/* 17574 */   MCD_OPC_FilterValue, 1, 145, 4, 0, // Skip to: 18748
+/* 17579 */   MCD_OPC_CheckPredicate, 26, 140, 4, 0, // Skip to: 18748
+/* 17584 */   MCD_OPC_Decode, 179, 26, 144, 2, // Opcode: VRSHRuv8i16
+/* 17589 */   MCD_OPC_FilterValue, 1, 130, 4, 0, // Skip to: 18748
+/* 17594 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17597 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17612
+/* 17602 */   MCD_OPC_CheckPredicate, 26, 117, 4, 0, // Skip to: 18748
+/* 17607 */   MCD_OPC_Decode, 170, 26, 145, 2, // Opcode: VRSHRsv4i32
+/* 17612 */   MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 18748
+/* 17617 */   MCD_OPC_CheckPredicate, 26, 102, 4, 0, // Skip to: 18748
+/* 17622 */   MCD_OPC_Decode, 178, 26, 145, 2, // Opcode: VRSHRuv4i32
+/* 17627 */   MCD_OPC_FilterValue, 3, 139, 0, 0, // Skip to: 17771
+/* 17632 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 17635 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17733
+/* 17640 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 17643 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17695
+/* 17648 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17651 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17673
+/* 17656 */   MCD_OPC_CheckPredicate, 26, 63, 4, 0, // Skip to: 18748
+/* 17661 */   MCD_OPC_CheckField, 19, 1, 1, 56, 4, 0, // Skip to: 18748
+/* 17668 */   MCD_OPC_Decode, 191, 26, 146, 2, // Opcode: VRSRAsv16i8
+/* 17673 */   MCD_OPC_FilterValue, 1, 46, 4, 0, // Skip to: 18748
+/* 17678 */   MCD_OPC_CheckPredicate, 26, 41, 4, 0, // Skip to: 18748
+/* 17683 */   MCD_OPC_CheckField, 19, 1, 1, 34, 4, 0, // Skip to: 18748
+/* 17690 */   MCD_OPC_Decode, 199, 26, 146, 2, // Opcode: VRSRAuv16i8
+/* 17695 */   MCD_OPC_FilterValue, 1, 24, 4, 0, // Skip to: 18748
+/* 17700 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17703 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17718
+/* 17708 */   MCD_OPC_CheckPredicate, 26, 11, 4, 0, // Skip to: 18748
+/* 17713 */   MCD_OPC_Decode, 197, 26, 147, 2, // Opcode: VRSRAsv8i16
+/* 17718 */   MCD_OPC_FilterValue, 1, 1, 4, 0, // Skip to: 18748
+/* 17723 */   MCD_OPC_CheckPredicate, 26, 252, 3, 0, // Skip to: 18748
+/* 17728 */   MCD_OPC_Decode, 205, 26, 147, 2, // Opcode: VRSRAuv8i16
+/* 17733 */   MCD_OPC_FilterValue, 1, 242, 3, 0, // Skip to: 18748
+/* 17738 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17741 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17756
+/* 17746 */   MCD_OPC_CheckPredicate, 26, 229, 3, 0, // Skip to: 18748
+/* 17751 */   MCD_OPC_Decode, 196, 26, 148, 2, // Opcode: VRSRAsv4i32
+/* 17756 */   MCD_OPC_FilterValue, 1, 219, 3, 0, // Skip to: 18748
+/* 17761 */   MCD_OPC_CheckPredicate, 26, 214, 3, 0, // Skip to: 18748
+/* 17766 */   MCD_OPC_Decode, 204, 26, 148, 2, // Opcode: VRSRAuv4i32
+/* 17771 */   MCD_OPC_FilterValue, 4, 84, 0, 0, // Skip to: 17860
+/* 17776 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 17779 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 17838
+/* 17784 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 17787 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 17816
+/* 17792 */   MCD_OPC_CheckPredicate, 26, 183, 3, 0, // Skip to: 18748
+/* 17797 */   MCD_OPC_CheckField, 24, 1, 1, 176, 3, 0, // Skip to: 18748
+/* 17804 */   MCD_OPC_CheckField, 19, 1, 1, 169, 3, 0, // Skip to: 18748
+/* 17811 */   MCD_OPC_Decode, 192, 27, 146, 2, // Opcode: VSRIv16i8
+/* 17816 */   MCD_OPC_FilterValue, 1, 159, 3, 0, // Skip to: 18748
+/* 17821 */   MCD_OPC_CheckPredicate, 26, 154, 3, 0, // Skip to: 18748
+/* 17826 */   MCD_OPC_CheckField, 24, 1, 1, 147, 3, 0, // Skip to: 18748
+/* 17833 */   MCD_OPC_Decode, 198, 27, 147, 2, // Opcode: VSRIv8i16
+/* 17838 */   MCD_OPC_FilterValue, 1, 137, 3, 0, // Skip to: 18748
+/* 17843 */   MCD_OPC_CheckPredicate, 26, 132, 3, 0, // Skip to: 18748
+/* 17848 */   MCD_OPC_CheckField, 24, 1, 1, 125, 3, 0, // Skip to: 18748
+/* 17855 */   MCD_OPC_Decode, 197, 27, 148, 2, // Opcode: VSRIv4i32
+/* 17860 */   MCD_OPC_FilterValue, 5, 139, 0, 0, // Skip to: 18004
+/* 17865 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 17868 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 17966
+/* 17873 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 17876 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 17928
+/* 17881 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17884 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 17906
+/* 17889 */   MCD_OPC_CheckPredicate, 26, 86, 3, 0, // Skip to: 18748
+/* 17894 */   MCD_OPC_CheckField, 19, 1, 1, 79, 3, 0, // Skip to: 18748
+/* 17901 */   MCD_OPC_Decode, 240, 26, 149, 2, // Opcode: VSHLiv16i8
+/* 17906 */   MCD_OPC_FilterValue, 1, 69, 3, 0, // Skip to: 18748
+/* 17911 */   MCD_OPC_CheckPredicate, 26, 64, 3, 0, // Skip to: 18748
+/* 17916 */   MCD_OPC_CheckField, 19, 1, 1, 57, 3, 0, // Skip to: 18748
+/* 17923 */   MCD_OPC_Decode, 161, 27, 150, 2, // Opcode: VSLIv16i8
+/* 17928 */   MCD_OPC_FilterValue, 1, 47, 3, 0, // Skip to: 18748
+/* 17933 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17936 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17951
+/* 17941 */   MCD_OPC_CheckPredicate, 26, 34, 3, 0, // Skip to: 18748
+/* 17946 */   MCD_OPC_Decode, 246, 26, 151, 2, // Opcode: VSHLiv8i16
+/* 17951 */   MCD_OPC_FilterValue, 1, 24, 3, 0, // Skip to: 18748
+/* 17956 */   MCD_OPC_CheckPredicate, 26, 19, 3, 0, // Skip to: 18748
+/* 17961 */   MCD_OPC_Decode, 167, 27, 152, 2, // Opcode: VSLIv8i16
+/* 17966 */   MCD_OPC_FilterValue, 1, 9, 3, 0, // Skip to: 18748
+/* 17971 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 17974 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 17989
+/* 17979 */   MCD_OPC_CheckPredicate, 26, 252, 2, 0, // Skip to: 18748
+/* 17984 */   MCD_OPC_Decode, 245, 26, 153, 2, // Opcode: VSHLiv4i32
+/* 17989 */   MCD_OPC_FilterValue, 1, 242, 2, 0, // Skip to: 18748
+/* 17994 */   MCD_OPC_CheckPredicate, 26, 237, 2, 0, // Skip to: 18748
+/* 17999 */   MCD_OPC_Decode, 166, 27, 154, 2, // Opcode: VSLIv4i32
+/* 18004 */   MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 18093
+/* 18009 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 18012 */   MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 18071
+/* 18017 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 18020 */   MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 18049
+/* 18025 */   MCD_OPC_CheckPredicate, 26, 206, 2, 0, // Skip to: 18748
+/* 18030 */   MCD_OPC_CheckField, 24, 1, 1, 199, 2, 0, // Skip to: 18748
+/* 18037 */   MCD_OPC_CheckField, 19, 1, 1, 192, 2, 0, // Skip to: 18748
+/* 18044 */   MCD_OPC_Decode, 135, 25, 149, 2, // Opcode: VQSHLsuv16i8
+/* 18049 */   MCD_OPC_FilterValue, 1, 182, 2, 0, // Skip to: 18748
+/* 18054 */   MCD_OPC_CheckPredicate, 26, 177, 2, 0, // Skip to: 18748
+/* 18059 */   MCD_OPC_CheckField, 24, 1, 1, 170, 2, 0, // Skip to: 18748
+/* 18066 */   MCD_OPC_Decode, 141, 25, 151, 2, // Opcode: VQSHLsuv8i16
+/* 18071 */   MCD_OPC_FilterValue, 1, 160, 2, 0, // Skip to: 18748
+/* 18076 */   MCD_OPC_CheckPredicate, 26, 155, 2, 0, // Skip to: 18748
+/* 18081 */   MCD_OPC_CheckField, 24, 1, 1, 148, 2, 0, // Skip to: 18748
+/* 18088 */   MCD_OPC_Decode, 140, 25, 153, 2, // Opcode: VQSHLsuv4i32
+/* 18093 */   MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 18237
+/* 18098 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 18101 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 18199
+/* 18106 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 18109 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 18161
+/* 18114 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18117 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18139
+/* 18122 */   MCD_OPC_CheckPredicate, 26, 109, 2, 0, // Skip to: 18748
+/* 18127 */   MCD_OPC_CheckField, 19, 1, 1, 102, 2, 0, // Skip to: 18748
+/* 18134 */   MCD_OPC_Decode, 255, 24, 149, 2, // Opcode: VQSHLsiv16i8
+/* 18139 */   MCD_OPC_FilterValue, 1, 92, 2, 0, // Skip to: 18748
+/* 18144 */   MCD_OPC_CheckPredicate, 26, 87, 2, 0, // Skip to: 18748
+/* 18149 */   MCD_OPC_CheckField, 19, 1, 1, 80, 2, 0, // Skip to: 18748
+/* 18156 */   MCD_OPC_Decode, 151, 25, 149, 2, // Opcode: VQSHLuiv16i8
+/* 18161 */   MCD_OPC_FilterValue, 1, 70, 2, 0, // Skip to: 18748
+/* 18166 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18169 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18184
+/* 18174 */   MCD_OPC_CheckPredicate, 26, 57, 2, 0, // Skip to: 18748
+/* 18179 */   MCD_OPC_Decode, 133, 25, 151, 2, // Opcode: VQSHLsiv8i16
+/* 18184 */   MCD_OPC_FilterValue, 1, 47, 2, 0, // Skip to: 18748
+/* 18189 */   MCD_OPC_CheckPredicate, 26, 42, 2, 0, // Skip to: 18748
+/* 18194 */   MCD_OPC_Decode, 157, 25, 151, 2, // Opcode: VQSHLuiv8i16
+/* 18199 */   MCD_OPC_FilterValue, 1, 32, 2, 0, // Skip to: 18748
+/* 18204 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18207 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18222
+/* 18212 */   MCD_OPC_CheckPredicate, 26, 19, 2, 0, // Skip to: 18748
+/* 18217 */   MCD_OPC_Decode, 132, 25, 153, 2, // Opcode: VQSHLsiv4i32
+/* 18222 */   MCD_OPC_FilterValue, 1, 9, 2, 0, // Skip to: 18748
+/* 18227 */   MCD_OPC_CheckPredicate, 26, 4, 2, 0, // Skip to: 18748
+/* 18232 */   MCD_OPC_Decode, 156, 25, 153, 2, // Opcode: VQSHLuiv4i32
+/* 18237 */   MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 18381
+/* 18242 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 18245 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 18343
+/* 18250 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 18253 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 18305
+/* 18258 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18261 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18283
+/* 18266 */   MCD_OPC_CheckPredicate, 26, 221, 1, 0, // Skip to: 18748
+/* 18271 */   MCD_OPC_CheckField, 19, 1, 1, 214, 1, 0, // Skip to: 18748
+/* 18278 */   MCD_OPC_Decode, 164, 26, 131, 2, // Opcode: VRSHRNv8i8
+/* 18283 */   MCD_OPC_FilterValue, 1, 204, 1, 0, // Skip to: 18748
+/* 18288 */   MCD_OPC_CheckPredicate, 26, 199, 1, 0, // Skip to: 18748
+/* 18293 */   MCD_OPC_CheckField, 19, 1, 1, 192, 1, 0, // Skip to: 18748
+/* 18300 */   MCD_OPC_Decode, 254, 24, 131, 2, // Opcode: VQRSHRUNv8i8
+/* 18305 */   MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 18748
+/* 18310 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18313 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18328
+/* 18318 */   MCD_OPC_CheckPredicate, 26, 169, 1, 0, // Skip to: 18748
+/* 18323 */   MCD_OPC_Decode, 163, 26, 132, 2, // Opcode: VRSHRNv4i16
+/* 18328 */   MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 18748
+/* 18333 */   MCD_OPC_CheckPredicate, 26, 154, 1, 0, // Skip to: 18748
+/* 18338 */   MCD_OPC_Decode, 253, 24, 132, 2, // Opcode: VQRSHRUNv4i16
+/* 18343 */   MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 18748
+/* 18348 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18351 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18366
+/* 18356 */   MCD_OPC_CheckPredicate, 26, 131, 1, 0, // Skip to: 18748
+/* 18361 */   MCD_OPC_Decode, 162, 26, 133, 2, // Opcode: VRSHRNv2i32
+/* 18366 */   MCD_OPC_FilterValue, 1, 121, 1, 0, // Skip to: 18748
+/* 18371 */   MCD_OPC_CheckPredicate, 26, 116, 1, 0, // Skip to: 18748
+/* 18376 */   MCD_OPC_Decode, 252, 24, 133, 2, // Opcode: VQRSHRUNv2i32
+/* 18381 */   MCD_OPC_FilterValue, 9, 139, 0, 0, // Skip to: 18525
+/* 18386 */   MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 18389 */   MCD_OPC_FilterValue, 0, 93, 0, 0, // Skip to: 18487
+/* 18394 */   MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 18397 */   MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 18449
+/* 18402 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18405 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18427
+/* 18410 */   MCD_OPC_CheckPredicate, 26, 77, 1, 0, // Skip to: 18748
+/* 18415 */   MCD_OPC_CheckField, 19, 1, 1, 70, 1, 0, // Skip to: 18748
+/* 18422 */   MCD_OPC_Decode, 248, 24, 131, 2, // Opcode: VQRSHRNsv8i8
+/* 18427 */   MCD_OPC_FilterValue, 1, 60, 1, 0, // Skip to: 18748
+/* 18432 */   MCD_OPC_CheckPredicate, 26, 55, 1, 0, // Skip to: 18748
+/* 18437 */   MCD_OPC_CheckField, 19, 1, 1, 48, 1, 0, // Skip to: 18748
+/* 18444 */   MCD_OPC_Decode, 251, 24, 131, 2, // Opcode: VQRSHRNuv8i8
+/* 18449 */   MCD_OPC_FilterValue, 1, 38, 1, 0, // Skip to: 18748
+/* 18454 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18457 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18472
+/* 18462 */   MCD_OPC_CheckPredicate, 26, 25, 1, 0, // Skip to: 18748
+/* 18467 */   MCD_OPC_Decode, 247, 24, 132, 2, // Opcode: VQRSHRNsv4i16
+/* 18472 */   MCD_OPC_FilterValue, 1, 15, 1, 0, // Skip to: 18748
+/* 18477 */   MCD_OPC_CheckPredicate, 26, 10, 1, 0, // Skip to: 18748
+/* 18482 */   MCD_OPC_Decode, 250, 24, 132, 2, // Opcode: VQRSHRNuv4i16
+/* 18487 */   MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 18748
+/* 18492 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18495 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18510
+/* 18500 */   MCD_OPC_CheckPredicate, 26, 243, 0, 0, // Skip to: 18748
+/* 18505 */   MCD_OPC_Decode, 246, 24, 133, 2, // Opcode: VQRSHRNsv2i32
+/* 18510 */   MCD_OPC_FilterValue, 1, 233, 0, 0, // Skip to: 18748
+/* 18515 */   MCD_OPC_CheckPredicate, 26, 228, 0, 0, // Skip to: 18748
+/* 18520 */   MCD_OPC_Decode, 249, 24, 133, 2, // Opcode: VQRSHRNuv2i32
+/* 18525 */   MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 18563
+/* 18530 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18533 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18548
+/* 18538 */   MCD_OPC_CheckPredicate, 27, 205, 0, 0, // Skip to: 18748
+/* 18543 */   MCD_OPC_Decode, 169, 18, 155, 2, // Opcode: VCVTxs2hq
+/* 18548 */   MCD_OPC_FilterValue, 1, 195, 0, 0, // Skip to: 18748
+/* 18553 */   MCD_OPC_CheckPredicate, 27, 190, 0, 0, // Skip to: 18748
+/* 18558 */   MCD_OPC_Decode, 173, 18, 155, 2, // Opcode: VCVTxu2hq
+/* 18563 */   MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 18601
+/* 18568 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18571 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18586
+/* 18576 */   MCD_OPC_CheckPredicate, 27, 167, 0, 0, // Skip to: 18748
+/* 18581 */   MCD_OPC_Decode, 155, 18, 155, 2, // Opcode: VCVTh2xsq
+/* 18586 */   MCD_OPC_FilterValue, 1, 157, 0, 0, // Skip to: 18748
+/* 18591 */   MCD_OPC_CheckPredicate, 27, 152, 0, 0, // Skip to: 18748
+/* 18596 */   MCD_OPC_Decode, 157, 18, 155, 2, // Opcode: VCVTh2xuq
+/* 18601 */   MCD_OPC_FilterValue, 14, 80, 0, 0, // Skip to: 18686
+/* 18606 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 18609 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18631
+/* 18614 */   MCD_OPC_CheckPredicate, 26, 34, 0, 0, // Skip to: 18653
+/* 18619 */   MCD_OPC_CheckField, 19, 3, 0, 27, 0, 0, // Skip to: 18653
+/* 18626 */   MCD_OPC_Decode, 128, 23, 138, 2, // Opcode: VMOVv16i8
+/* 18631 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18653
+/* 18636 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 18653
+/* 18641 */   MCD_OPC_CheckField, 19, 3, 0, 5, 0, 0, // Skip to: 18653
+/* 18648 */   MCD_OPC_Decode, 132, 23, 138, 2, // Opcode: VMOVv2i64
+/* 18653 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18656 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18671
+/* 18661 */   MCD_OPC_CheckPredicate, 26, 82, 0, 0, // Skip to: 18748
+/* 18666 */   MCD_OPC_Decode, 167, 18, 155, 2, // Opcode: VCVTxs2fq
+/* 18671 */   MCD_OPC_FilterValue, 1, 72, 0, 0, // Skip to: 18748
+/* 18676 */   MCD_OPC_CheckPredicate, 26, 67, 0, 0, // Skip to: 18748
+/* 18681 */   MCD_OPC_Decode, 171, 18, 155, 2, // Opcode: VCVTxu2fq
+/* 18686 */   MCD_OPC_FilterValue, 15, 57, 0, 0, // Skip to: 18748
+/* 18691 */   MCD_OPC_ExtractField, 24, 1,  // Inst{24} ...
+/* 18694 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18709
+/* 18699 */   MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 18724
+/* 18704 */   MCD_OPC_Decode, 146, 18, 155, 2, // Opcode: VCVTf2xsq
+/* 18709 */   MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 18724
+/* 18714 */   MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 18724
+/* 18719 */   MCD_OPC_Decode, 148, 18, 155, 2, // Opcode: VCVTf2xuq
+/* 18724 */   MCD_OPC_CheckPredicate, 26, 19, 0, 0, // Skip to: 18748
+/* 18729 */   MCD_OPC_CheckField, 19, 3, 0, 12, 0, 0, // Skip to: 18748
+/* 18736 */   MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 18748
+/* 18743 */   MCD_OPC_Decode, 133, 23, 138, 2, // Opcode: VMOVv4f32
+/* 18748 */   MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 18751 */   MCD_OPC_FilterValue, 0, 88, 0, 0, // Skip to: 18844
+/* 18756 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
+/* 18759 */   MCD_OPC_FilterValue, 0, 211, 1, 0, // Skip to: 19231
+/* 18764 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 18767 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18789
+/* 18772 */   MCD_OPC_CheckPredicate, 26, 57, 0, 0, // Skip to: 18834
+/* 18777 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18834
+/* 18784 */   MCD_OPC_Decode, 136, 23, 138, 2, // Opcode: VMOVv8i16
+/* 18789 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18834
+/* 18794 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 18797 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18812
+/* 18802 */   MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 18834
+/* 18807 */   MCD_OPC_Decode, 229, 23, 138, 2, // Opcode: VORRiv4i32
+/* 18812 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18834
+/* 18817 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 18834
+/* 18822 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18834
+/* 18829 */   MCD_OPC_Decode, 230, 23, 138, 2, // Opcode: VORRiv8i16
+/* 18834 */   MCD_OPC_CheckPredicate, 26, 136, 1, 0, // Skip to: 19231
+/* 18839 */   MCD_OPC_Decode, 135, 23, 138, 2, // Opcode: VMOVv4i32
+/* 18844 */   MCD_OPC_FilterValue, 1, 126, 1, 0, // Skip to: 19231
+/* 18849 */   MCD_OPC_ExtractField, 19, 3,  // Inst{21-19} ...
+/* 18852 */   MCD_OPC_FilterValue, 0, 118, 1, 0, // Skip to: 19231
+/* 18857 */   MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 18860 */   MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 18882
+/* 18865 */   MCD_OPC_CheckPredicate, 26, 57, 0, 0, // Skip to: 18927
+/* 18870 */   MCD_OPC_CheckField, 10, 2, 2, 50, 0, 0, // Skip to: 18927
+/* 18877 */   MCD_OPC_Decode, 201, 23, 138, 2, // Opcode: VMVNv8i16
+/* 18882 */   MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 18927
+/* 18887 */   MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 18890 */   MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18905
+/* 18895 */   MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 18927
+/* 18900 */   MCD_OPC_Decode, 189, 16, 138, 2, // Opcode: VBICiv4i32
+/* 18905 */   MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 18927
+/* 18910 */   MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 18927
+/* 18915 */   MCD_OPC_CheckField, 10, 1, 0, 5, 0, 0, // Skip to: 18927
+/* 18922 */   MCD_OPC_Decode, 190, 16, 138, 2, // Opcode: VBICiv8i16
+/* 18927 */   MCD_OPC_CheckPredicate, 26, 43, 1, 0, // Skip to: 19231
+/* 18932 */   MCD_OPC_Decode, 200, 23, 138, 2, // Opcode: VMVNv4i32
+/* 18937 */   MCD_OPC_FilterValue, 1, 33, 1, 0, // Skip to: 19231
+/* 18942 */   MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 18945 */   MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 18985
+/* 18950 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 18953 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 18969
+/* 18959 */   MCD_OPC_CheckPredicate, 26, 11, 1, 0, // Skip to: 19231
+/* 18964 */   MCD_OPC_Decode, 142, 27, 156, 2, // Opcode: VSHRsv2i64
+/* 18969 */   MCD_OPC_FilterValue, 243, 1, 0, 1, 0, // Skip to: 19231
+/* 18975 */   MCD_OPC_CheckPredicate, 26, 251, 0, 0, // Skip to: 19231
+/* 18980 */   MCD_OPC_Decode, 150, 27, 156, 2, // Opcode: VSHRuv2i64
+/* 18985 */   MCD_OPC_FilterValue, 1, 35, 0, 0, // Skip to: 19025
+/* 18990 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 18993 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 19009
+/* 18999 */   MCD_OPC_CheckPredicate, 26, 227, 0, 0, // Skip to: 19231
+/* 19004 */   MCD_OPC_Decode, 179, 27, 157, 2, // Opcode: VSRAsv2i64
+/* 19009 */   MCD_OPC_FilterValue, 243, 1, 216, 0, 0, // Skip to: 19231
+/* 19015 */   MCD_OPC_CheckPredicate, 26, 211, 0, 0, // Skip to: 19231
+/* 19020 */   MCD_OPC_Decode, 187, 27, 157, 2, // Opcode: VSRAuv2i64
+/* 19025 */   MCD_OPC_FilterValue, 2, 35, 0, 0, // Skip to: 19065
+/* 19030 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 19033 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 19049
+/* 19039 */   MCD_OPC_CheckPredicate, 26, 187, 0, 0, // Skip to: 19231
+/* 19044 */   MCD_OPC_Decode, 168, 26, 156, 2, // Opcode: VRSHRsv2i64
+/* 19049 */   MCD_OPC_FilterValue, 243, 1, 176, 0, 0, // Skip to: 19231
+/* 19055 */   MCD_OPC_CheckPredicate, 26, 171, 0, 0, // Skip to: 19231
+/* 19060 */   MCD_OPC_Decode, 176, 26, 156, 2, // Opcode: VRSHRuv2i64
+/* 19065 */   MCD_OPC_FilterValue, 3, 35, 0, 0, // Skip to: 19105
+/* 19070 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 19073 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 19089
+/* 19079 */   MCD_OPC_CheckPredicate, 26, 147, 0, 0, // Skip to: 19231
+/* 19084 */   MCD_OPC_Decode, 194, 26, 157, 2, // Opcode: VRSRAsv2i64
+/* 19089 */   MCD_OPC_FilterValue, 243, 1, 136, 0, 0, // Skip to: 19231
+/* 19095 */   MCD_OPC_CheckPredicate, 26, 131, 0, 0, // Skip to: 19231
+/* 19100 */   MCD_OPC_Decode, 202, 26, 157, 2, // Opcode: VRSRAuv2i64
+/* 19105 */   MCD_OPC_FilterValue, 4, 18, 0, 0, // Skip to: 19128
+/* 19110 */   MCD_OPC_CheckPredicate, 26, 116, 0, 0, // Skip to: 19231
+/* 19115 */   MCD_OPC_CheckField, 24, 8, 243, 1, 108, 0, 0, // Skip to: 19231
+/* 19123 */   MCD_OPC_Decode, 195, 27, 157, 2, // Opcode: VSRIv2i64
+/* 19128 */   MCD_OPC_FilterValue, 5, 35, 0, 0, // Skip to: 19168
+/* 19133 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 19136 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 19152
+/* 19142 */   MCD_OPC_CheckPredicate, 26, 84, 0, 0, // Skip to: 19231
+/* 19147 */   MCD_OPC_Decode, 243, 26, 158, 2, // Opcode: VSHLiv2i64
+/* 19152 */   MCD_OPC_FilterValue, 243, 1, 73, 0, 0, // Skip to: 19231
+/* 19158 */   MCD_OPC_CheckPredicate, 26, 68, 0, 0, // Skip to: 19231
+/* 19163 */   MCD_OPC_Decode, 164, 27, 159, 2, // Opcode: VSLIv2i64
+/* 19168 */   MCD_OPC_FilterValue, 6, 18, 0, 0, // Skip to: 19191
+/* 19173 */   MCD_OPC_CheckPredicate, 26, 53, 0, 0, // Skip to: 19231
+/* 19178 */   MCD_OPC_CheckField, 24, 8, 243, 1, 45, 0, 0, // Skip to: 19231
+/* 19186 */   MCD_OPC_Decode, 138, 25, 158, 2, // Opcode: VQSHLsuv2i64
+/* 19191 */   MCD_OPC_FilterValue, 7, 35, 0, 0, // Skip to: 19231
+/* 19196 */   MCD_OPC_ExtractField, 24, 8,  // Inst{31-24} ...
+/* 19199 */   MCD_OPC_FilterValue, 242, 1, 10, 0, 0, // Skip to: 19215
+/* 19205 */   MCD_OPC_CheckPredicate, 26, 21, 0, 0, // Skip to: 19231
+/* 19210 */   MCD_OPC_Decode, 130, 25, 158, 2, // Opcode: VQSHLsiv2i64
+/* 19215 */   MCD_OPC_FilterValue, 243, 1, 10, 0, 0, // Skip to: 19231
+/* 19221 */   MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 19231
+/* 19226 */   MCD_OPC_Decode, 154, 25, 158, 2, // Opcode: VQSHLuiv2i64
+/* 19231 */   MCD_OPC_Fail,
   0
 };
 
@@ -5810,88 +10703,88 @@ static const uint8_t DecoderTableNEONDup32[] = {
 /* 11 */      MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 77
 /* 16 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 19 */      MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 48
-/* 24 */      MCD_OPC_CheckPredicate, 27, 183, 1, 0, // Skip to: 468
+/* 24 */      MCD_OPC_CheckPredicate, 33, 183, 1, 0, // Skip to: 468
 /* 29 */      MCD_OPC_CheckField, 8, 4, 11, 176, 1, 0, // Skip to: 468
 /* 36 */      MCD_OPC_CheckField, 6, 1, 0, 169, 1, 0, // Skip to: 468
-/* 43 */      MCD_OPC_Decode, 245, 17, 183, 1, // Opcode: VSETLNi32
+/* 43 */      MCD_OPC_Decode, 229, 26, 160, 2, // Opcode: VSETLNi32
 /* 48 */      MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 468
-/* 53 */      MCD_OPC_CheckPredicate, 27, 154, 1, 0, // Skip to: 468
+/* 53 */      MCD_OPC_CheckPredicate, 34, 154, 1, 0, // Skip to: 468
 /* 58 */      MCD_OPC_CheckField, 8, 4, 11, 147, 1, 0, // Skip to: 468
 /* 65 */      MCD_OPC_CheckField, 6, 1, 0, 140, 1, 0, // Skip to: 468
-/* 72 */      MCD_OPC_Decode, 169, 10, 184, 1, // Opcode: VGETLNi32
+/* 72 */      MCD_OPC_Decode, 232, 18, 161, 2, // Opcode: VGETLNi32
 /* 77 */      MCD_OPC_FilterValue, 48, 130, 1, 0, // Skip to: 468
 /* 82 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 85 */      MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 107
-/* 90 */      MCD_OPC_CheckPredicate, 21, 117, 1, 0, // Skip to: 468
+/* 90 */      MCD_OPC_CheckPredicate, 26, 117, 1, 0, // Skip to: 468
 /* 95 */      MCD_OPC_CheckField, 8, 4, 11, 110, 1, 0, // Skip to: 468
-/* 102 */     MCD_OPC_Decode, 244, 17, 185, 1, // Opcode: VSETLNi16
+/* 102 */     MCD_OPC_Decode, 228, 26, 162, 2, // Opcode: VSETLNi16
 /* 107 */     MCD_OPC_FilterValue, 1, 100, 1, 0, // Skip to: 468
-/* 112 */     MCD_OPC_CheckPredicate, 21, 95, 1, 0, // Skip to: 468
+/* 112 */     MCD_OPC_CheckPredicate, 26, 95, 1, 0, // Skip to: 468
 /* 117 */     MCD_OPC_CheckField, 8, 4, 11, 88, 1, 0, // Skip to: 468
-/* 124 */     MCD_OPC_Decode, 170, 10, 186, 1, // Opcode: VGETLNs16
+/* 124 */     MCD_OPC_Decode, 233, 18, 163, 2, // Opcode: VGETLNs16
 /* 129 */     MCD_OPC_FilterValue, 57, 61, 0, 0, // Skip to: 195
 /* 134 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 137 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 166
-/* 142 */     MCD_OPC_CheckPredicate, 21, 65, 1, 0, // Skip to: 468
+/* 142 */     MCD_OPC_CheckPredicate, 26, 65, 1, 0, // Skip to: 468
 /* 147 */     MCD_OPC_CheckField, 8, 4, 11, 58, 1, 0, // Skip to: 468
 /* 154 */     MCD_OPC_CheckField, 0, 5, 16, 51, 1, 0, // Skip to: 468
-/* 161 */     MCD_OPC_Decode, 246, 17, 187, 1, // Opcode: VSETLNi8
+/* 161 */     MCD_OPC_Decode, 230, 26, 164, 2, // Opcode: VSETLNi8
 /* 166 */     MCD_OPC_FilterValue, 1, 41, 1, 0, // Skip to: 468
-/* 171 */     MCD_OPC_CheckPredicate, 21, 36, 1, 0, // Skip to: 468
+/* 171 */     MCD_OPC_CheckPredicate, 26, 36, 1, 0, // Skip to: 468
 /* 176 */     MCD_OPC_CheckField, 8, 4, 11, 29, 1, 0, // Skip to: 468
 /* 183 */     MCD_OPC_CheckField, 0, 5, 16, 22, 1, 0, // Skip to: 468
-/* 190 */     MCD_OPC_Decode, 171, 10, 188, 1, // Opcode: VGETLNs8
+/* 190 */     MCD_OPC_Decode, 234, 18, 165, 2, // Opcode: VGETLNs8
 /* 195 */     MCD_OPC_FilterValue, 58, 165, 0, 0, // Skip to: 365
 /* 200 */     MCD_OPC_ExtractField, 0, 6,  // Inst{5-0} ...
 /* 203 */     MCD_OPC_FilterValue, 16, 61, 0, 0, // Skip to: 269
 /* 208 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 211 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 240
-/* 216 */     MCD_OPC_CheckPredicate, 21, 247, 0, 0, // Skip to: 468
+/* 216 */     MCD_OPC_CheckPredicate, 26, 247, 0, 0, // Skip to: 468
 /* 221 */     MCD_OPC_CheckField, 8, 4, 11, 240, 0, 0, // Skip to: 468
 /* 228 */     MCD_OPC_CheckField, 6, 1, 0, 233, 0, 0, // Skip to: 468
-/* 235 */     MCD_OPC_Decode, 130, 10, 189, 1, // Opcode: VDUP32d
+/* 235 */     MCD_OPC_Decode, 179, 18, 166, 2, // Opcode: VDUP32d
 /* 240 */     MCD_OPC_FilterValue, 2, 223, 0, 0, // Skip to: 468
-/* 245 */     MCD_OPC_CheckPredicate, 21, 218, 0, 0, // Skip to: 468
+/* 245 */     MCD_OPC_CheckPredicate, 26, 218, 0, 0, // Skip to: 468
 /* 250 */     MCD_OPC_CheckField, 8, 4, 11, 211, 0, 0, // Skip to: 468
 /* 257 */     MCD_OPC_CheckField, 6, 1, 0, 204, 0, 0, // Skip to: 468
-/* 264 */     MCD_OPC_Decode, 131, 10, 190, 1, // Opcode: VDUP32q
+/* 264 */     MCD_OPC_Decode, 180, 18, 167, 2, // Opcode: VDUP32q
 /* 269 */     MCD_OPC_FilterValue, 48, 194, 0, 0, // Skip to: 468
 /* 274 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 277 */     MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 343
 /* 282 */     MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
 /* 285 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 314
-/* 290 */     MCD_OPC_CheckPredicate, 21, 173, 0, 0, // Skip to: 468
+/* 290 */     MCD_OPC_CheckPredicate, 26, 173, 0, 0, // Skip to: 468
 /* 295 */     MCD_OPC_CheckField, 8, 4, 11, 166, 0, 0, // Skip to: 468
 /* 302 */     MCD_OPC_CheckField, 6, 1, 0, 159, 0, 0, // Skip to: 468
-/* 309 */     MCD_OPC_Decode, 128, 10, 189, 1, // Opcode: VDUP16d
+/* 309 */     MCD_OPC_Decode, 177, 18, 166, 2, // Opcode: VDUP16d
 /* 314 */     MCD_OPC_FilterValue, 1, 149, 0, 0, // Skip to: 468
-/* 319 */     MCD_OPC_CheckPredicate, 21, 144, 0, 0, // Skip to: 468
+/* 319 */     MCD_OPC_CheckPredicate, 26, 144, 0, 0, // Skip to: 468
 /* 324 */     MCD_OPC_CheckField, 8, 4, 11, 137, 0, 0, // Skip to: 468
 /* 331 */     MCD_OPC_CheckField, 6, 1, 0, 130, 0, 0, // Skip to: 468
-/* 338 */     MCD_OPC_Decode, 129, 10, 190, 1, // Opcode: VDUP16q
+/* 338 */     MCD_OPC_Decode, 178, 18, 167, 2, // Opcode: VDUP16q
 /* 343 */     MCD_OPC_FilterValue, 1, 120, 0, 0, // Skip to: 468
-/* 348 */     MCD_OPC_CheckPredicate, 21, 115, 0, 0, // Skip to: 468
+/* 348 */     MCD_OPC_CheckPredicate, 26, 115, 0, 0, // Skip to: 468
 /* 353 */     MCD_OPC_CheckField, 8, 4, 11, 108, 0, 0, // Skip to: 468
-/* 360 */     MCD_OPC_Decode, 172, 10, 186, 1, // Opcode: VGETLNu16
+/* 360 */     MCD_OPC_Decode, 235, 18, 163, 2, // Opcode: VGETLNu16
 /* 365 */     MCD_OPC_FilterValue, 59, 98, 0, 0, // Skip to: 468
 /* 370 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 373 */     MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 439
 /* 378 */     MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
 /* 381 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 410
-/* 386 */     MCD_OPC_CheckPredicate, 21, 77, 0, 0, // Skip to: 468
+/* 386 */     MCD_OPC_CheckPredicate, 26, 77, 0, 0, // Skip to: 468
 /* 391 */     MCD_OPC_CheckField, 8, 4, 11, 70, 0, 0, // Skip to: 468
 /* 398 */     MCD_OPC_CheckField, 0, 7, 16, 63, 0, 0, // Skip to: 468
-/* 405 */     MCD_OPC_Decode, 132, 10, 189, 1, // Opcode: VDUP8d
+/* 405 */     MCD_OPC_Decode, 181, 18, 166, 2, // Opcode: VDUP8d
 /* 410 */     MCD_OPC_FilterValue, 1, 53, 0, 0, // Skip to: 468
-/* 415 */     MCD_OPC_CheckPredicate, 21, 48, 0, 0, // Skip to: 468
+/* 415 */     MCD_OPC_CheckPredicate, 26, 48, 0, 0, // Skip to: 468
 /* 420 */     MCD_OPC_CheckField, 8, 4, 11, 41, 0, 0, // Skip to: 468
 /* 427 */     MCD_OPC_CheckField, 0, 7, 16, 34, 0, 0, // Skip to: 468
-/* 434 */     MCD_OPC_Decode, 133, 10, 190, 1, // Opcode: VDUP8q
+/* 434 */     MCD_OPC_Decode, 182, 18, 167, 2, // Opcode: VDUP8q
 /* 439 */     MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 468
-/* 444 */     MCD_OPC_CheckPredicate, 21, 19, 0, 0, // Skip to: 468
+/* 444 */     MCD_OPC_CheckPredicate, 26, 19, 0, 0, // Skip to: 468
 /* 449 */     MCD_OPC_CheckField, 8, 4, 11, 12, 0, 0, // Skip to: 468
 /* 456 */     MCD_OPC_CheckField, 0, 5, 16, 5, 0, 0, // Skip to: 468
-/* 463 */     MCD_OPC_Decode, 173, 10, 188, 1, // Opcode: VGETLNu8
+/* 463 */     MCD_OPC_Decode, 236, 18, 165, 2, // Opcode: VGETLNu8
 /* 468 */     MCD_OPC_Fail,
   0
 };
@@ -5905,61 +10798,61 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 19 */      MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 124
 /* 25 */      MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 28 */      MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 60
-/* 33 */      MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 50
+/* 33 */      MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 50
 /* 38 */      MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 50
-/* 45 */      MCD_OPC_Decode, 178, 20, 191, 1, // Opcode: VST4d8
-/* 50 */      MCD_OPC_CheckPredicate, 21, 246, 25, 0, // Skip to: 6701
-/* 55 */      MCD_OPC_Decode, 181, 20, 191, 1, // Opcode: VST4d8_UPD
+/* 45 */      MCD_OPC_Decode, 183, 29, 168, 2, // Opcode: VST4d8
+/* 50 */      MCD_OPC_CheckPredicate, 26, 246, 25, 0, // Skip to: 6701
+/* 55 */      MCD_OPC_Decode, 186, 29, 168, 2, // Opcode: VST4d8_UPD
 /* 60 */      MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 92
-/* 65 */      MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 82
+/* 65 */      MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 82
 /* 70 */      MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 82
-/* 77 */      MCD_OPC_Decode, 170, 20, 191, 1, // Opcode: VST4d16
-/* 82 */      MCD_OPC_CheckPredicate, 21, 214, 25, 0, // Skip to: 6701
-/* 87 */      MCD_OPC_Decode, 173, 20, 191, 1, // Opcode: VST4d16_UPD
+/* 77 */      MCD_OPC_Decode, 175, 29, 168, 2, // Opcode: VST4d16
+/* 82 */      MCD_OPC_CheckPredicate, 26, 214, 25, 0, // Skip to: 6701
+/* 87 */      MCD_OPC_Decode, 178, 29, 168, 2, // Opcode: VST4d16_UPD
 /* 92 */      MCD_OPC_FilterValue, 2, 204, 25, 0, // Skip to: 6701
-/* 97 */      MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 114
+/* 97 */      MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 114
 /* 102 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 114
-/* 109 */     MCD_OPC_Decode, 174, 20, 191, 1, // Opcode: VST4d32
-/* 114 */     MCD_OPC_CheckPredicate, 21, 182, 25, 0, // Skip to: 6701
-/* 119 */     MCD_OPC_Decode, 177, 20, 191, 1, // Opcode: VST4d32_UPD
+/* 109 */     MCD_OPC_Decode, 179, 29, 168, 2, // Opcode: VST4d32
+/* 114 */     MCD_OPC_CheckPredicate, 26, 182, 25, 0, // Skip to: 6701
+/* 119 */     MCD_OPC_Decode, 182, 29, 168, 2, // Opcode: VST4d32_UPD
 /* 124 */     MCD_OPC_FilterValue, 233, 3, 171, 25, 0, // Skip to: 6701
 /* 130 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 133 */     MCD_OPC_FilterValue, 0, 163, 25, 0, // Skip to: 6701
-/* 138 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 155
+/* 138 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 155
 /* 143 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 155
-/* 150 */     MCD_OPC_Decode, 219, 18, 192, 1, // Opcode: VST1LNd8
-/* 155 */     MCD_OPC_CheckPredicate, 21, 141, 25, 0, // Skip to: 6701
-/* 160 */     MCD_OPC_Decode, 220, 18, 192, 1, // Opcode: VST1LNd8_UPD
+/* 150 */     MCD_OPC_Decode, 204, 27, 169, 2, // Opcode: VST1LNd8
+/* 155 */     MCD_OPC_CheckPredicate, 26, 141, 25, 0, // Skip to: 6701
+/* 160 */     MCD_OPC_Decode, 205, 27, 169, 2, // Opcode: VST1LNd8_UPD
 /* 165 */     MCD_OPC_FilterValue, 2, 131, 25, 0, // Skip to: 6701
 /* 170 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 173 */     MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 278
 /* 179 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 182 */     MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 214
-/* 187 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 204
+/* 187 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 204
 /* 192 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 204
-/* 199 */     MCD_OPC_Decode, 253, 12, 191, 1, // Opcode: VLD4d8
-/* 204 */     MCD_OPC_CheckPredicate, 21, 92, 25, 0, // Skip to: 6701
-/* 209 */     MCD_OPC_Decode, 128, 13, 191, 1, // Opcode: VLD4d8_UPD
+/* 199 */     MCD_OPC_Decode, 220, 21, 168, 2, // Opcode: VLD4d8
+/* 204 */     MCD_OPC_CheckPredicate, 26, 92, 25, 0, // Skip to: 6701
+/* 209 */     MCD_OPC_Decode, 223, 21, 168, 2, // Opcode: VLD4d8_UPD
 /* 214 */     MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 246
-/* 219 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 236
+/* 219 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 236
 /* 224 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 236
-/* 231 */     MCD_OPC_Decode, 245, 12, 191, 1, // Opcode: VLD4d16
-/* 236 */     MCD_OPC_CheckPredicate, 21, 60, 25, 0, // Skip to: 6701
-/* 241 */     MCD_OPC_Decode, 248, 12, 191, 1, // Opcode: VLD4d16_UPD
+/* 231 */     MCD_OPC_Decode, 212, 21, 168, 2, // Opcode: VLD4d16
+/* 236 */     MCD_OPC_CheckPredicate, 26, 60, 25, 0, // Skip to: 6701
+/* 241 */     MCD_OPC_Decode, 215, 21, 168, 2, // Opcode: VLD4d16_UPD
 /* 246 */     MCD_OPC_FilterValue, 2, 50, 25, 0, // Skip to: 6701
-/* 251 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 268
+/* 251 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 268
 /* 256 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 268
-/* 263 */     MCD_OPC_Decode, 249, 12, 191, 1, // Opcode: VLD4d32
-/* 268 */     MCD_OPC_CheckPredicate, 21, 28, 25, 0, // Skip to: 6701
-/* 273 */     MCD_OPC_Decode, 252, 12, 191, 1, // Opcode: VLD4d32_UPD
+/* 263 */     MCD_OPC_Decode, 216, 21, 168, 2, // Opcode: VLD4d32
+/* 268 */     MCD_OPC_CheckPredicate, 26, 28, 25, 0, // Skip to: 6701
+/* 273 */     MCD_OPC_Decode, 219, 21, 168, 2, // Opcode: VLD4d32_UPD
 /* 278 */     MCD_OPC_FilterValue, 233, 3, 17, 25, 0, // Skip to: 6701
 /* 284 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 287 */     MCD_OPC_FilterValue, 0, 9, 25, 0, // Skip to: 6701
-/* 292 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 309
+/* 292 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 309
 /* 297 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 309
-/* 304 */     MCD_OPC_Decode, 222, 10, 193, 1, // Opcode: VLD1LNd8
-/* 309 */     MCD_OPC_CheckPredicate, 21, 243, 24, 0, // Skip to: 6701
-/* 314 */     MCD_OPC_Decode, 223, 10, 193, 1, // Opcode: VLD1LNd8_UPD
+/* 304 */     MCD_OPC_Decode, 157, 19, 170, 2, // Opcode: VLD1LNd8
+/* 309 */     MCD_OPC_CheckPredicate, 26, 243, 24, 0, // Skip to: 6701
+/* 314 */     MCD_OPC_Decode, 158, 19, 170, 2, // Opcode: VLD1LNd8_UPD
 /* 319 */     MCD_OPC_FilterValue, 1, 39, 1, 0, // Skip to: 619
 /* 324 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 327 */     MCD_OPC_FilterValue, 0, 141, 0, 0, // Skip to: 473
@@ -5967,57 +10860,57 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 335 */     MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 440
 /* 341 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 344 */     MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 376
-/* 349 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 366
+/* 349 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 366
 /* 354 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 366
-/* 361 */     MCD_OPC_Decode, 192, 20, 191, 1, // Opcode: VST4q8
-/* 366 */     MCD_OPC_CheckPredicate, 21, 186, 24, 0, // Skip to: 6701
-/* 371 */     MCD_OPC_Decode, 194, 20, 191, 1, // Opcode: VST4q8_UPD
+/* 361 */     MCD_OPC_Decode, 197, 29, 168, 2, // Opcode: VST4q8
+/* 366 */     MCD_OPC_CheckPredicate, 26, 186, 24, 0, // Skip to: 6701
+/* 371 */     MCD_OPC_Decode, 199, 29, 168, 2, // Opcode: VST4q8_UPD
 /* 376 */     MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 408
-/* 381 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 398
+/* 381 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 398
 /* 386 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 398
-/* 393 */     MCD_OPC_Decode, 182, 20, 191, 1, // Opcode: VST4q16
-/* 398 */     MCD_OPC_CheckPredicate, 21, 154, 24, 0, // Skip to: 6701
-/* 403 */     MCD_OPC_Decode, 184, 20, 191, 1, // Opcode: VST4q16_UPD
+/* 393 */     MCD_OPC_Decode, 187, 29, 168, 2, // Opcode: VST4q16
+/* 398 */     MCD_OPC_CheckPredicate, 26, 154, 24, 0, // Skip to: 6701
+/* 403 */     MCD_OPC_Decode, 189, 29, 168, 2, // Opcode: VST4q16_UPD
 /* 408 */     MCD_OPC_FilterValue, 2, 144, 24, 0, // Skip to: 6701
-/* 413 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 430
+/* 413 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 430
 /* 418 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 430
-/* 425 */     MCD_OPC_Decode, 187, 20, 191, 1, // Opcode: VST4q32
-/* 430 */     MCD_OPC_CheckPredicate, 21, 122, 24, 0, // Skip to: 6701
-/* 435 */     MCD_OPC_Decode, 189, 20, 191, 1, // Opcode: VST4q32_UPD
+/* 425 */     MCD_OPC_Decode, 192, 29, 168, 2, // Opcode: VST4q32
+/* 430 */     MCD_OPC_CheckPredicate, 26, 122, 24, 0, // Skip to: 6701
+/* 435 */     MCD_OPC_Decode, 194, 29, 168, 2, // Opcode: VST4q32_UPD
 /* 440 */     MCD_OPC_FilterValue, 233, 3, 111, 24, 0, // Skip to: 6701
-/* 446 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 463
+/* 446 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 463
 /* 451 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 463
-/* 458 */     MCD_OPC_Decode, 183, 19, 194, 1, // Opcode: VST2LNd8
-/* 463 */     MCD_OPC_CheckPredicate, 21, 89, 24, 0, // Skip to: 6701
-/* 468 */     MCD_OPC_Decode, 186, 19, 194, 1, // Opcode: VST2LNd8_UPD
+/* 458 */     MCD_OPC_Decode, 188, 28, 171, 2, // Opcode: VST2LNd8
+/* 463 */     MCD_OPC_CheckPredicate, 26, 89, 24, 0, // Skip to: 6701
+/* 468 */     MCD_OPC_Decode, 191, 28, 171, 2, // Opcode: VST2LNd8_UPD
 /* 473 */     MCD_OPC_FilterValue, 2, 79, 24, 0, // Skip to: 6701
 /* 478 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 481 */     MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 586
 /* 487 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 490 */     MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 522
-/* 495 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 512
+/* 495 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 512
 /* 500 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 512
-/* 507 */     MCD_OPC_Decode, 139, 13, 191, 1, // Opcode: VLD4q8
-/* 512 */     MCD_OPC_CheckPredicate, 21, 40, 24, 0, // Skip to: 6701
-/* 517 */     MCD_OPC_Decode, 141, 13, 191, 1, // Opcode: VLD4q8_UPD
+/* 507 */     MCD_OPC_Decode, 234, 21, 168, 2, // Opcode: VLD4q8
+/* 512 */     MCD_OPC_CheckPredicate, 26, 40, 24, 0, // Skip to: 6701
+/* 517 */     MCD_OPC_Decode, 236, 21, 168, 2, // Opcode: VLD4q8_UPD
 /* 522 */     MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 554
-/* 527 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 544
+/* 527 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 544
 /* 532 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 544
-/* 539 */     MCD_OPC_Decode, 129, 13, 191, 1, // Opcode: VLD4q16
-/* 544 */     MCD_OPC_CheckPredicate, 21, 8, 24, 0, // Skip to: 6701
-/* 549 */     MCD_OPC_Decode, 131, 13, 191, 1, // Opcode: VLD4q16_UPD
+/* 539 */     MCD_OPC_Decode, 224, 21, 168, 2, // Opcode: VLD4q16
+/* 544 */     MCD_OPC_CheckPredicate, 26, 8, 24, 0, // Skip to: 6701
+/* 549 */     MCD_OPC_Decode, 226, 21, 168, 2, // Opcode: VLD4q16_UPD
 /* 554 */     MCD_OPC_FilterValue, 2, 254, 23, 0, // Skip to: 6701
-/* 559 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 576
+/* 559 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 576
 /* 564 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 576
-/* 571 */     MCD_OPC_Decode, 134, 13, 191, 1, // Opcode: VLD4q32
-/* 576 */     MCD_OPC_CheckPredicate, 21, 232, 23, 0, // Skip to: 6701
-/* 581 */     MCD_OPC_Decode, 136, 13, 191, 1, // Opcode: VLD4q32_UPD
+/* 571 */     MCD_OPC_Decode, 229, 21, 168, 2, // Opcode: VLD4q32
+/* 576 */     MCD_OPC_CheckPredicate, 26, 232, 23, 0, // Skip to: 6701
+/* 581 */     MCD_OPC_Decode, 231, 21, 168, 2, // Opcode: VLD4q32_UPD
 /* 586 */     MCD_OPC_FilterValue, 233, 3, 221, 23, 0, // Skip to: 6701
-/* 592 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 609
+/* 592 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 609
 /* 597 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 609
-/* 604 */     MCD_OPC_Decode, 210, 11, 195, 1, // Opcode: VLD2LNd8
-/* 609 */     MCD_OPC_CheckPredicate, 21, 199, 23, 0, // Skip to: 6701
-/* 614 */     MCD_OPC_Decode, 213, 11, 195, 1, // Opcode: VLD2LNd8_UPD
+/* 604 */     MCD_OPC_Decode, 171, 20, 172, 2, // Opcode: VLD2LNd8
+/* 609 */     MCD_OPC_CheckPredicate, 26, 199, 23, 0, // Skip to: 6701
+/* 614 */     MCD_OPC_Decode, 174, 20, 172, 2, // Opcode: VLD2LNd8_UPD
 /* 619 */     MCD_OPC_FilterValue, 2, 247, 1, 0, // Skip to: 1127
 /* 624 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 627 */     MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 877
@@ -6027,51 +10920,51 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 644 */     MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 692
 /* 649 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 652 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 667
-/* 657 */     MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 682
-/* 662 */     MCD_OPC_Decode, 139, 19, 196, 1, // Opcode: VST1d8Qwb_fixed
+/* 657 */     MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 682
+/* 662 */     MCD_OPC_Decode, 134, 28, 173, 2, // Opcode: VST1d8Qwb_fixed
 /* 667 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 682
-/* 672 */     MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 682
-/* 677 */     MCD_OPC_Decode, 137, 19, 196, 1, // Opcode: VST1d8Q
-/* 682 */     MCD_OPC_CheckPredicate, 21, 126, 23, 0, // Skip to: 6701
-/* 687 */     MCD_OPC_Decode, 140, 19, 196, 1, // Opcode: VST1d8Qwb_register
+/* 672 */     MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 682
+/* 677 */     MCD_OPC_Decode, 130, 28, 173, 2, // Opcode: VST1d8Q
+/* 682 */     MCD_OPC_CheckPredicate, 26, 126, 23, 0, // Skip to: 6701
+/* 687 */     MCD_OPC_Decode, 135, 28, 173, 2, // Opcode: VST1d8Qwb_register
 /* 692 */     MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 740
 /* 697 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 700 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 715
-/* 705 */     MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 730
-/* 710 */     MCD_OPC_Decode, 230, 18, 196, 1, // Opcode: VST1d16Qwb_fixed
+/* 705 */     MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 730
+/* 710 */     MCD_OPC_Decode, 217, 27, 173, 2, // Opcode: VST1d16Qwb_fixed
 /* 715 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 730
-/* 720 */     MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 730
-/* 725 */     MCD_OPC_Decode, 228, 18, 196, 1, // Opcode: VST1d16Q
-/* 730 */     MCD_OPC_CheckPredicate, 21, 78, 23, 0, // Skip to: 6701
-/* 735 */     MCD_OPC_Decode, 231, 18, 196, 1, // Opcode: VST1d16Qwb_register
+/* 720 */     MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 730
+/* 725 */     MCD_OPC_Decode, 213, 27, 173, 2, // Opcode: VST1d16Q
+/* 730 */     MCD_OPC_CheckPredicate, 26, 78, 23, 0, // Skip to: 6701
+/* 735 */     MCD_OPC_Decode, 218, 27, 173, 2, // Opcode: VST1d16Qwb_register
 /* 740 */     MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 788
 /* 745 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 748 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 763
-/* 753 */     MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 778
-/* 758 */     MCD_OPC_Decode, 241, 18, 196, 1, // Opcode: VST1d32Qwb_fixed
+/* 753 */     MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 778
+/* 758 */     MCD_OPC_Decode, 232, 27, 173, 2, // Opcode: VST1d32Qwb_fixed
 /* 763 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 778
-/* 768 */     MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 778
-/* 773 */     MCD_OPC_Decode, 239, 18, 196, 1, // Opcode: VST1d32Q
-/* 778 */     MCD_OPC_CheckPredicate, 21, 30, 23, 0, // Skip to: 6701
-/* 783 */     MCD_OPC_Decode, 242, 18, 196, 1, // Opcode: VST1d32Qwb_register
+/* 768 */     MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 778
+/* 773 */     MCD_OPC_Decode, 228, 27, 173, 2, // Opcode: VST1d32Q
+/* 778 */     MCD_OPC_CheckPredicate, 26, 30, 23, 0, // Skip to: 6701
+/* 783 */     MCD_OPC_Decode, 233, 27, 173, 2, // Opcode: VST1d32Qwb_register
 /* 788 */     MCD_OPC_FilterValue, 3, 20, 23, 0, // Skip to: 6701
 /* 793 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 796 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 811
-/* 801 */     MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 826
-/* 806 */     MCD_OPC_Decode, 254, 18, 196, 1, // Opcode: VST1d64Qwb_fixed
+/* 801 */     MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 826
+/* 806 */     MCD_OPC_Decode, 247, 27, 173, 2, // Opcode: VST1d64Qwb_fixed
 /* 811 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 826
-/* 816 */     MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 826
-/* 821 */     MCD_OPC_Decode, 250, 18, 196, 1, // Opcode: VST1d64Q
-/* 826 */     MCD_OPC_CheckPredicate, 21, 238, 22, 0, // Skip to: 6701
-/* 831 */     MCD_OPC_Decode, 255, 18, 196, 1, // Opcode: VST1d64Qwb_register
+/* 816 */     MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 826
+/* 821 */     MCD_OPC_Decode, 243, 27, 173, 2, // Opcode: VST1d64Q
+/* 826 */     MCD_OPC_CheckPredicate, 26, 238, 22, 0, // Skip to: 6701
+/* 831 */     MCD_OPC_Decode, 248, 27, 173, 2, // Opcode: VST1d64Qwb_register
 /* 836 */     MCD_OPC_FilterValue, 233, 3, 227, 22, 0, // Skip to: 6701
 /* 842 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 845 */     MCD_OPC_FilterValue, 0, 219, 22, 0, // Skip to: 6701
-/* 850 */     MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 867
+/* 850 */     MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 867
 /* 855 */     MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 867
-/* 862 */     MCD_OPC_Decode, 239, 19, 197, 1, // Opcode: VST3LNd8
-/* 867 */     MCD_OPC_CheckPredicate, 21, 197, 22, 0, // Skip to: 6701
-/* 872 */     MCD_OPC_Decode, 242, 19, 197, 1, // Opcode: VST3LNd8_UPD
+/* 862 */     MCD_OPC_Decode, 244, 28, 174, 2, // Opcode: VST3LNd8
+/* 867 */     MCD_OPC_CheckPredicate, 26, 197, 22, 0, // Skip to: 6701
+/* 872 */     MCD_OPC_Decode, 247, 28, 174, 2, // Opcode: VST3LNd8_UPD
 /* 877 */     MCD_OPC_FilterValue, 2, 187, 22, 0, // Skip to: 6701
 /* 882 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 885 */     MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 1086
@@ -6079,51 +10972,51 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 894 */     MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 942
 /* 899 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 902 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 917
-/* 907 */     MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 932
-/* 912 */     MCD_OPC_Decode, 142, 11, 196, 1, // Opcode: VLD1d8Qwb_fixed
+/* 907 */     MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 932
+/* 912 */     MCD_OPC_Decode, 215, 19, 173, 2, // Opcode: VLD1d8Qwb_fixed
 /* 917 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 932
-/* 922 */     MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 932
-/* 927 */     MCD_OPC_Decode, 140, 11, 196, 1, // Opcode: VLD1d8Q
-/* 932 */     MCD_OPC_CheckPredicate, 21, 132, 22, 0, // Skip to: 6701
-/* 937 */     MCD_OPC_Decode, 143, 11, 196, 1, // Opcode: VLD1d8Qwb_register
+/* 922 */     MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 932
+/* 927 */     MCD_OPC_Decode, 211, 19, 173, 2, // Opcode: VLD1d8Q
+/* 932 */     MCD_OPC_CheckPredicate, 26, 132, 22, 0, // Skip to: 6701
+/* 937 */     MCD_OPC_Decode, 216, 19, 173, 2, // Opcode: VLD1d8Qwb_register
 /* 942 */     MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 990
 /* 947 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 950 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 965
-/* 955 */     MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 980
-/* 960 */     MCD_OPC_Decode, 233, 10, 196, 1, // Opcode: VLD1d16Qwb_fixed
+/* 955 */     MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 980
+/* 960 */     MCD_OPC_Decode, 170, 19, 173, 2, // Opcode: VLD1d16Qwb_fixed
 /* 965 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 980
-/* 970 */     MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 980
-/* 975 */     MCD_OPC_Decode, 231, 10, 196, 1, // Opcode: VLD1d16Q
-/* 980 */     MCD_OPC_CheckPredicate, 21, 84, 22, 0, // Skip to: 6701
-/* 985 */     MCD_OPC_Decode, 234, 10, 196, 1, // Opcode: VLD1d16Qwb_register
+/* 970 */     MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 980
+/* 975 */     MCD_OPC_Decode, 166, 19, 173, 2, // Opcode: VLD1d16Q
+/* 980 */     MCD_OPC_CheckPredicate, 26, 84, 22, 0, // Skip to: 6701
+/* 985 */     MCD_OPC_Decode, 171, 19, 173, 2, // Opcode: VLD1d16Qwb_register
 /* 990 */     MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 1038
 /* 995 */     MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 998 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1013
-/* 1003 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1028
-/* 1008 */    MCD_OPC_Decode, 244, 10, 196, 1, // Opcode: VLD1d32Qwb_fixed
+/* 1003 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1028
+/* 1008 */    MCD_OPC_Decode, 185, 19, 173, 2, // Opcode: VLD1d32Qwb_fixed
 /* 1013 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1028
-/* 1018 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1028
-/* 1023 */    MCD_OPC_Decode, 242, 10, 196, 1, // Opcode: VLD1d32Q
-/* 1028 */    MCD_OPC_CheckPredicate, 21, 36, 22, 0, // Skip to: 6701
-/* 1033 */    MCD_OPC_Decode, 245, 10, 196, 1, // Opcode: VLD1d32Qwb_register
+/* 1018 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1028
+/* 1023 */    MCD_OPC_Decode, 181, 19, 173, 2, // Opcode: VLD1d32Q
+/* 1028 */    MCD_OPC_CheckPredicate, 26, 36, 22, 0, // Skip to: 6701
+/* 1033 */    MCD_OPC_Decode, 186, 19, 173, 2, // Opcode: VLD1d32Qwb_register
 /* 1038 */    MCD_OPC_FilterValue, 3, 26, 22, 0, // Skip to: 6701
 /* 1043 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1046 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1061
-/* 1051 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1076
-/* 1056 */    MCD_OPC_Decode, 129, 11, 196, 1, // Opcode: VLD1d64Qwb_fixed
+/* 1051 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1076
+/* 1056 */    MCD_OPC_Decode, 200, 19, 173, 2, // Opcode: VLD1d64Qwb_fixed
 /* 1061 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1076
-/* 1066 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1076
-/* 1071 */    MCD_OPC_Decode, 253, 10, 196, 1, // Opcode: VLD1d64Q
-/* 1076 */    MCD_OPC_CheckPredicate, 21, 244, 21, 0, // Skip to: 6701
-/* 1081 */    MCD_OPC_Decode, 130, 11, 196, 1, // Opcode: VLD1d64Qwb_register
+/* 1066 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1076
+/* 1071 */    MCD_OPC_Decode, 196, 19, 173, 2, // Opcode: VLD1d64Q
+/* 1076 */    MCD_OPC_CheckPredicate, 26, 244, 21, 0, // Skip to: 6701
+/* 1081 */    MCD_OPC_Decode, 201, 19, 173, 2, // Opcode: VLD1d64Qwb_register
 /* 1086 */    MCD_OPC_FilterValue, 233, 3, 233, 21, 0, // Skip to: 6701
 /* 1092 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 1095 */    MCD_OPC_FilterValue, 0, 225, 21, 0, // Skip to: 6701
-/* 1100 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1117
+/* 1100 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1117
 /* 1105 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1117
-/* 1112 */    MCD_OPC_Decode, 162, 12, 198, 1, // Opcode: VLD3LNd8
-/* 1117 */    MCD_OPC_CheckPredicate, 21, 203, 21, 0, // Skip to: 6701
-/* 1122 */    MCD_OPC_Decode, 165, 12, 198, 1, // Opcode: VLD3LNd8_UPD
+/* 1112 */    MCD_OPC_Decode, 254, 20, 175, 2, // Opcode: VLD3LNd8
+/* 1117 */    MCD_OPC_CheckPredicate, 26, 203, 21, 0, // Skip to: 6701
+/* 1122 */    MCD_OPC_Decode, 129, 21, 175, 2, // Opcode: VLD3LNd8_UPD
 /* 1127 */    MCD_OPC_FilterValue, 3, 135, 1, 0, // Skip to: 1523
 /* 1132 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 1135 */    MCD_OPC_FilterValue, 0, 189, 0, 0, // Skip to: 1329
@@ -6133,39 +11026,39 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 1152 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1200
 /* 1157 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1160 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1175
-/* 1165 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1190
-/* 1170 */    MCD_OPC_Decode, 229, 19, 199, 1, // Opcode: VST2q8wb_fixed
+/* 1165 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1190
+/* 1170 */    MCD_OPC_Decode, 234, 28, 176, 2, // Opcode: VST2q8wb_fixed
 /* 1175 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1190
-/* 1180 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1190
-/* 1185 */    MCD_OPC_Decode, 225, 19, 199, 1, // Opcode: VST2q8
-/* 1190 */    MCD_OPC_CheckPredicate, 21, 130, 21, 0, // Skip to: 6701
-/* 1195 */    MCD_OPC_Decode, 230, 19, 199, 1, // Opcode: VST2q8wb_register
+/* 1180 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1190
+/* 1185 */    MCD_OPC_Decode, 230, 28, 176, 2, // Opcode: VST2q8
+/* 1190 */    MCD_OPC_CheckPredicate, 26, 130, 21, 0, // Skip to: 6701
+/* 1195 */    MCD_OPC_Decode, 235, 28, 176, 2, // Opcode: VST2q8wb_register
 /* 1200 */    MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1248
 /* 1205 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1208 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1223
-/* 1213 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1238
-/* 1218 */    MCD_OPC_Decode, 217, 19, 199, 1, // Opcode: VST2q16wb_fixed
+/* 1213 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1238
+/* 1218 */    MCD_OPC_Decode, 222, 28, 176, 2, // Opcode: VST2q16wb_fixed
 /* 1223 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1238
-/* 1228 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1238
-/* 1233 */    MCD_OPC_Decode, 213, 19, 199, 1, // Opcode: VST2q16
-/* 1238 */    MCD_OPC_CheckPredicate, 21, 82, 21, 0, // Skip to: 6701
-/* 1243 */    MCD_OPC_Decode, 218, 19, 199, 1, // Opcode: VST2q16wb_register
+/* 1228 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1238
+/* 1233 */    MCD_OPC_Decode, 218, 28, 176, 2, // Opcode: VST2q16
+/* 1238 */    MCD_OPC_CheckPredicate, 26, 82, 21, 0, // Skip to: 6701
+/* 1243 */    MCD_OPC_Decode, 223, 28, 176, 2, // Opcode: VST2q16wb_register
 /* 1248 */    MCD_OPC_FilterValue, 2, 72, 21, 0, // Skip to: 6701
 /* 1253 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1256 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1271
-/* 1261 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1286
-/* 1266 */    MCD_OPC_Decode, 223, 19, 199, 1, // Opcode: VST2q32wb_fixed
+/* 1261 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1286
+/* 1266 */    MCD_OPC_Decode, 228, 28, 176, 2, // Opcode: VST2q32wb_fixed
 /* 1271 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1286
-/* 1276 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1286
-/* 1281 */    MCD_OPC_Decode, 219, 19, 199, 1, // Opcode: VST2q32
-/* 1286 */    MCD_OPC_CheckPredicate, 21, 34, 21, 0, // Skip to: 6701
-/* 1291 */    MCD_OPC_Decode, 224, 19, 199, 1, // Opcode: VST2q32wb_register
+/* 1276 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1286
+/* 1281 */    MCD_OPC_Decode, 224, 28, 176, 2, // Opcode: VST2q32
+/* 1286 */    MCD_OPC_CheckPredicate, 26, 34, 21, 0, // Skip to: 6701
+/* 1291 */    MCD_OPC_Decode, 229, 28, 176, 2, // Opcode: VST2q32wb_register
 /* 1296 */    MCD_OPC_FilterValue, 233, 3, 23, 21, 0, // Skip to: 6701
-/* 1302 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1319
+/* 1302 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1319
 /* 1307 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1319
-/* 1314 */    MCD_OPC_Decode, 158, 20, 200, 1, // Opcode: VST4LNd8
-/* 1319 */    MCD_OPC_CheckPredicate, 21, 1, 21, 0, // Skip to: 6701
-/* 1324 */    MCD_OPC_Decode, 161, 20, 200, 1, // Opcode: VST4LNd8_UPD
+/* 1314 */    MCD_OPC_Decode, 163, 29, 177, 2, // Opcode: VST4LNd8
+/* 1319 */    MCD_OPC_CheckPredicate, 26, 1, 21, 0, // Skip to: 6701
+/* 1324 */    MCD_OPC_Decode, 166, 29, 177, 2, // Opcode: VST4LNd8_UPD
 /* 1329 */    MCD_OPC_FilterValue, 2, 247, 20, 0, // Skip to: 6701
 /* 1334 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 1337 */    MCD_OPC_FilterValue, 232, 3, 147, 0, 0, // Skip to: 1490
@@ -6173,39 +11066,39 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 1346 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 1394
 /* 1351 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1354 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1369
-/* 1359 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1384
-/* 1364 */    MCD_OPC_Decode, 128, 12, 199, 1, // Opcode: VLD2q8wb_fixed
+/* 1359 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1384
+/* 1364 */    MCD_OPC_Decode, 217, 20, 176, 2, // Opcode: VLD2q8wb_fixed
 /* 1369 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1384
-/* 1374 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1384
-/* 1379 */    MCD_OPC_Decode, 252, 11, 199, 1, // Opcode: VLD2q8
-/* 1384 */    MCD_OPC_CheckPredicate, 21, 192, 20, 0, // Skip to: 6701
-/* 1389 */    MCD_OPC_Decode, 129, 12, 199, 1, // Opcode: VLD2q8wb_register
+/* 1374 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1384
+/* 1379 */    MCD_OPC_Decode, 213, 20, 176, 2, // Opcode: VLD2q8
+/* 1384 */    MCD_OPC_CheckPredicate, 26, 192, 20, 0, // Skip to: 6701
+/* 1389 */    MCD_OPC_Decode, 218, 20, 176, 2, // Opcode: VLD2q8wb_register
 /* 1394 */    MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 1442
 /* 1399 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1402 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1417
-/* 1407 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1432
-/* 1412 */    MCD_OPC_Decode, 244, 11, 199, 1, // Opcode: VLD2q16wb_fixed
+/* 1407 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1432
+/* 1412 */    MCD_OPC_Decode, 205, 20, 176, 2, // Opcode: VLD2q16wb_fixed
 /* 1417 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1432
-/* 1422 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1432
-/* 1427 */    MCD_OPC_Decode, 240, 11, 199, 1, // Opcode: VLD2q16
-/* 1432 */    MCD_OPC_CheckPredicate, 21, 144, 20, 0, // Skip to: 6701
-/* 1437 */    MCD_OPC_Decode, 245, 11, 199, 1, // Opcode: VLD2q16wb_register
+/* 1422 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1432
+/* 1427 */    MCD_OPC_Decode, 201, 20, 176, 2, // Opcode: VLD2q16
+/* 1432 */    MCD_OPC_CheckPredicate, 26, 144, 20, 0, // Skip to: 6701
+/* 1437 */    MCD_OPC_Decode, 206, 20, 176, 2, // Opcode: VLD2q16wb_register
 /* 1442 */    MCD_OPC_FilterValue, 2, 134, 20, 0, // Skip to: 6701
 /* 1447 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 1450 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1465
-/* 1455 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 1480
-/* 1460 */    MCD_OPC_Decode, 250, 11, 199, 1, // Opcode: VLD2q32wb_fixed
+/* 1455 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 1480
+/* 1460 */    MCD_OPC_Decode, 211, 20, 176, 2, // Opcode: VLD2q32wb_fixed
 /* 1465 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1480
-/* 1470 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 1480
-/* 1475 */    MCD_OPC_Decode, 246, 11, 199, 1, // Opcode: VLD2q32
-/* 1480 */    MCD_OPC_CheckPredicate, 21, 96, 20, 0, // Skip to: 6701
-/* 1485 */    MCD_OPC_Decode, 251, 11, 199, 1, // Opcode: VLD2q32wb_register
+/* 1470 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 1480
+/* 1475 */    MCD_OPC_Decode, 207, 20, 176, 2, // Opcode: VLD2q32
+/* 1480 */    MCD_OPC_CheckPredicate, 26, 96, 20, 0, // Skip to: 6701
+/* 1485 */    MCD_OPC_Decode, 212, 20, 176, 2, // Opcode: VLD2q32wb_register
 /* 1490 */    MCD_OPC_FilterValue, 233, 3, 85, 20, 0, // Skip to: 6701
-/* 1496 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1513
+/* 1496 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1513
 /* 1501 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1513
-/* 1508 */    MCD_OPC_Decode, 233, 12, 201, 1, // Opcode: VLD4LNd8
-/* 1513 */    MCD_OPC_CheckPredicate, 21, 63, 20, 0, // Skip to: 6701
-/* 1518 */    MCD_OPC_Decode, 236, 12, 201, 1, // Opcode: VLD4LNd8_UPD
+/* 1508 */    MCD_OPC_Decode, 200, 21, 178, 2, // Opcode: VLD4LNd8
+/* 1513 */    MCD_OPC_CheckPredicate, 26, 63, 20, 0, // Skip to: 6701
+/* 1518 */    MCD_OPC_Decode, 203, 21, 178, 2, // Opcode: VLD4LNd8_UPD
 /* 1523 */    MCD_OPC_FilterValue, 4, 54, 1, 0, // Skip to: 1838
 /* 1528 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 1531 */    MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 1685
@@ -6213,60 +11106,60 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 1539 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1644
 /* 1545 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
 /* 1548 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1580
-/* 1553 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1570
+/* 1553 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1570
 /* 1558 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1570
-/* 1565 */    MCD_OPC_Decode, 131, 20, 202, 1, // Opcode: VST3d8
-/* 1570 */    MCD_OPC_CheckPredicate, 21, 6, 20, 0, // Skip to: 6701
-/* 1575 */    MCD_OPC_Decode, 134, 20, 202, 1, // Opcode: VST3d8_UPD
+/* 1565 */    MCD_OPC_Decode, 136, 29, 179, 2, // Opcode: VST3d8
+/* 1570 */    MCD_OPC_CheckPredicate, 26, 6, 20, 0, // Skip to: 6701
+/* 1575 */    MCD_OPC_Decode, 139, 29, 179, 2, // Opcode: VST3d8_UPD
 /* 1580 */    MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1612
-/* 1585 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1602
+/* 1585 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1602
 /* 1590 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1602
-/* 1597 */    MCD_OPC_Decode, 251, 19, 202, 1, // Opcode: VST3d16
-/* 1602 */    MCD_OPC_CheckPredicate, 21, 230, 19, 0, // Skip to: 6701
-/* 1607 */    MCD_OPC_Decode, 254, 19, 202, 1, // Opcode: VST3d16_UPD
+/* 1597 */    MCD_OPC_Decode, 128, 29, 179, 2, // Opcode: VST3d16
+/* 1602 */    MCD_OPC_CheckPredicate, 26, 230, 19, 0, // Skip to: 6701
+/* 1607 */    MCD_OPC_Decode, 131, 29, 179, 2, // Opcode: VST3d16_UPD
 /* 1612 */    MCD_OPC_FilterValue, 4, 220, 19, 0, // Skip to: 6701
-/* 1617 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1634
+/* 1617 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1634
 /* 1622 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1634
-/* 1629 */    MCD_OPC_Decode, 255, 19, 202, 1, // Opcode: VST3d32
-/* 1634 */    MCD_OPC_CheckPredicate, 21, 198, 19, 0, // Skip to: 6701
-/* 1639 */    MCD_OPC_Decode, 130, 20, 202, 1, // Opcode: VST3d32_UPD
+/* 1629 */    MCD_OPC_Decode, 132, 29, 179, 2, // Opcode: VST3d32
+/* 1634 */    MCD_OPC_CheckPredicate, 26, 198, 19, 0, // Skip to: 6701
+/* 1639 */    MCD_OPC_Decode, 135, 29, 179, 2, // Opcode: VST3d32_UPD
 /* 1644 */    MCD_OPC_FilterValue, 233, 3, 187, 19, 0, // Skip to: 6701
 /* 1650 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 1653 */    MCD_OPC_FilterValue, 0, 179, 19, 0, // Skip to: 6701
-/* 1658 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1675
+/* 1658 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1675
 /* 1663 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1675
-/* 1670 */    MCD_OPC_Decode, 215, 18, 192, 1, // Opcode: VST1LNd16
-/* 1675 */    MCD_OPC_CheckPredicate, 21, 157, 19, 0, // Skip to: 6701
-/* 1680 */    MCD_OPC_Decode, 216, 18, 192, 1, // Opcode: VST1LNd16_UPD
+/* 1670 */    MCD_OPC_Decode, 200, 27, 169, 2, // Opcode: VST1LNd16
+/* 1675 */    MCD_OPC_CheckPredicate, 26, 157, 19, 0, // Skip to: 6701
+/* 1680 */    MCD_OPC_Decode, 201, 27, 169, 2, // Opcode: VST1LNd16_UPD
 /* 1685 */    MCD_OPC_FilterValue, 2, 147, 19, 0, // Skip to: 6701
 /* 1690 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 1693 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1798
 /* 1699 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
 /* 1702 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1734
-/* 1707 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1724
+/* 1707 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1724
 /* 1712 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1724
-/* 1719 */    MCD_OPC_Decode, 182, 12, 202, 1, // Opcode: VLD3d8
-/* 1724 */    MCD_OPC_CheckPredicate, 21, 108, 19, 0, // Skip to: 6701
-/* 1729 */    MCD_OPC_Decode, 185, 12, 202, 1, // Opcode: VLD3d8_UPD
+/* 1719 */    MCD_OPC_Decode, 146, 21, 179, 2, // Opcode: VLD3d8
+/* 1724 */    MCD_OPC_CheckPredicate, 26, 108, 19, 0, // Skip to: 6701
+/* 1729 */    MCD_OPC_Decode, 149, 21, 179, 2, // Opcode: VLD3d8_UPD
 /* 1734 */    MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 1766
-/* 1739 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1756
+/* 1739 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1756
 /* 1744 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1756
-/* 1751 */    MCD_OPC_Decode, 174, 12, 202, 1, // Opcode: VLD3d16
-/* 1756 */    MCD_OPC_CheckPredicate, 21, 76, 19, 0, // Skip to: 6701
-/* 1761 */    MCD_OPC_Decode, 177, 12, 202, 1, // Opcode: VLD3d16_UPD
+/* 1751 */    MCD_OPC_Decode, 138, 21, 179, 2, // Opcode: VLD3d16
+/* 1756 */    MCD_OPC_CheckPredicate, 26, 76, 19, 0, // Skip to: 6701
+/* 1761 */    MCD_OPC_Decode, 141, 21, 179, 2, // Opcode: VLD3d16_UPD
 /* 1766 */    MCD_OPC_FilterValue, 4, 66, 19, 0, // Skip to: 6701
-/* 1771 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1788
+/* 1771 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1788
 /* 1776 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1788
-/* 1783 */    MCD_OPC_Decode, 178, 12, 202, 1, // Opcode: VLD3d32
-/* 1788 */    MCD_OPC_CheckPredicate, 21, 44, 19, 0, // Skip to: 6701
-/* 1793 */    MCD_OPC_Decode, 181, 12, 202, 1, // Opcode: VLD3d32_UPD
+/* 1783 */    MCD_OPC_Decode, 142, 21, 179, 2, // Opcode: VLD3d32
+/* 1788 */    MCD_OPC_CheckPredicate, 26, 44, 19, 0, // Skip to: 6701
+/* 1793 */    MCD_OPC_Decode, 145, 21, 179, 2, // Opcode: VLD3d32_UPD
 /* 1798 */    MCD_OPC_FilterValue, 233, 3, 33, 19, 0, // Skip to: 6701
-/* 1804 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1821
+/* 1804 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1821
 /* 1809 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1821
-/* 1816 */    MCD_OPC_Decode, 218, 10, 193, 1, // Opcode: VLD1LNd16
-/* 1821 */    MCD_OPC_CheckPredicate, 21, 11, 19, 0, // Skip to: 6701
+/* 1816 */    MCD_OPC_Decode, 153, 19, 170, 2, // Opcode: VLD1LNd16
+/* 1821 */    MCD_OPC_CheckPredicate, 26, 11, 19, 0, // Skip to: 6701
 /* 1826 */    MCD_OPC_CheckField, 5, 1, 0, 4, 19, 0, // Skip to: 6701
-/* 1833 */    MCD_OPC_Decode, 219, 10, 193, 1, // Opcode: VLD1LNd16_UPD
+/* 1833 */    MCD_OPC_Decode, 154, 19, 170, 2, // Opcode: VLD1LNd16_UPD
 /* 1838 */    MCD_OPC_FilterValue, 5, 137, 1, 0, // Skip to: 2236
 /* 1843 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 1846 */    MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 2146
@@ -6276,75 +11169,75 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 1862 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 1967
 /* 1868 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 1871 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 1903
-/* 1876 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1893
+/* 1876 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1893
 /* 1881 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1893
-/* 1888 */    MCD_OPC_Decode, 145, 20, 202, 1, // Opcode: VST3q8
-/* 1893 */    MCD_OPC_CheckPredicate, 21, 195, 18, 0, // Skip to: 6701
-/* 1898 */    MCD_OPC_Decode, 147, 20, 202, 1, // Opcode: VST3q8_UPD
+/* 1888 */    MCD_OPC_Decode, 150, 29, 179, 2, // Opcode: VST3q8
+/* 1893 */    MCD_OPC_CheckPredicate, 26, 195, 18, 0, // Skip to: 6701
+/* 1898 */    MCD_OPC_Decode, 152, 29, 179, 2, // Opcode: VST3q8_UPD
 /* 1903 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 1935
-/* 1908 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1925
+/* 1908 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1925
 /* 1913 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1925
-/* 1920 */    MCD_OPC_Decode, 135, 20, 202, 1, // Opcode: VST3q16
-/* 1925 */    MCD_OPC_CheckPredicate, 21, 163, 18, 0, // Skip to: 6701
-/* 1930 */    MCD_OPC_Decode, 137, 20, 202, 1, // Opcode: VST3q16_UPD
+/* 1920 */    MCD_OPC_Decode, 140, 29, 179, 2, // Opcode: VST3q16
+/* 1925 */    MCD_OPC_CheckPredicate, 26, 163, 18, 0, // Skip to: 6701
+/* 1930 */    MCD_OPC_Decode, 142, 29, 179, 2, // Opcode: VST3q16_UPD
 /* 1935 */    MCD_OPC_FilterValue, 2, 153, 18, 0, // Skip to: 6701
-/* 1940 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1957
+/* 1940 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1957
 /* 1945 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1957
-/* 1952 */    MCD_OPC_Decode, 140, 20, 202, 1, // Opcode: VST3q32
-/* 1957 */    MCD_OPC_CheckPredicate, 21, 131, 18, 0, // Skip to: 6701
-/* 1962 */    MCD_OPC_Decode, 142, 20, 202, 1, // Opcode: VST3q32_UPD
+/* 1952 */    MCD_OPC_Decode, 145, 29, 179, 2, // Opcode: VST3q32
+/* 1957 */    MCD_OPC_CheckPredicate, 26, 131, 18, 0, // Skip to: 6701
+/* 1962 */    MCD_OPC_Decode, 147, 29, 179, 2, // Opcode: VST3q32_UPD
 /* 1967 */    MCD_OPC_FilterValue, 233, 3, 120, 18, 0, // Skip to: 6701
-/* 1973 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 1990
+/* 1973 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 1990
 /* 1978 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 1990
-/* 1985 */    MCD_OPC_Decode, 175, 19, 194, 1, // Opcode: VST2LNd16
-/* 1990 */    MCD_OPC_CheckPredicate, 21, 98, 18, 0, // Skip to: 6701
-/* 1995 */    MCD_OPC_Decode, 178, 19, 194, 1, // Opcode: VST2LNd16_UPD
+/* 1985 */    MCD_OPC_Decode, 180, 28, 171, 2, // Opcode: VST2LNd16
+/* 1990 */    MCD_OPC_CheckPredicate, 26, 98, 18, 0, // Skip to: 6701
+/* 1995 */    MCD_OPC_Decode, 183, 28, 171, 2, // Opcode: VST2LNd16_UPD
 /* 2000 */    MCD_OPC_FilterValue, 2, 88, 18, 0, // Skip to: 6701
 /* 2005 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 2008 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 2113
 /* 2014 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 2017 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2049
-/* 2022 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2039
+/* 2022 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2039
 /* 2027 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2039
-/* 2034 */    MCD_OPC_Decode, 196, 12, 202, 1, // Opcode: VLD3q8
-/* 2039 */    MCD_OPC_CheckPredicate, 21, 49, 18, 0, // Skip to: 6701
-/* 2044 */    MCD_OPC_Decode, 198, 12, 202, 1, // Opcode: VLD3q8_UPD
+/* 2034 */    MCD_OPC_Decode, 160, 21, 179, 2, // Opcode: VLD3q8
+/* 2039 */    MCD_OPC_CheckPredicate, 26, 49, 18, 0, // Skip to: 6701
+/* 2044 */    MCD_OPC_Decode, 162, 21, 179, 2, // Opcode: VLD3q8_UPD
 /* 2049 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 2081
-/* 2054 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2071
+/* 2054 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2071
 /* 2059 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2071
-/* 2066 */    MCD_OPC_Decode, 186, 12, 202, 1, // Opcode: VLD3q16
-/* 2071 */    MCD_OPC_CheckPredicate, 21, 17, 18, 0, // Skip to: 6701
-/* 2076 */    MCD_OPC_Decode, 188, 12, 202, 1, // Opcode: VLD3q16_UPD
+/* 2066 */    MCD_OPC_Decode, 150, 21, 179, 2, // Opcode: VLD3q16
+/* 2071 */    MCD_OPC_CheckPredicate, 26, 17, 18, 0, // Skip to: 6701
+/* 2076 */    MCD_OPC_Decode, 152, 21, 179, 2, // Opcode: VLD3q16_UPD
 /* 2081 */    MCD_OPC_FilterValue, 2, 7, 18, 0, // Skip to: 6701
-/* 2086 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2103
+/* 2086 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2103
 /* 2091 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2103
-/* 2098 */    MCD_OPC_Decode, 191, 12, 202, 1, // Opcode: VLD3q32
-/* 2103 */    MCD_OPC_CheckPredicate, 21, 241, 17, 0, // Skip to: 6701
-/* 2108 */    MCD_OPC_Decode, 193, 12, 202, 1, // Opcode: VLD3q32_UPD
+/* 2098 */    MCD_OPC_Decode, 155, 21, 179, 2, // Opcode: VLD3q32
+/* 2103 */    MCD_OPC_CheckPredicate, 26, 241, 17, 0, // Skip to: 6701
+/* 2108 */    MCD_OPC_Decode, 157, 21, 179, 2, // Opcode: VLD3q32_UPD
 /* 2113 */    MCD_OPC_FilterValue, 233, 3, 230, 17, 0, // Skip to: 6701
-/* 2119 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2136
+/* 2119 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2136
 /* 2124 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2136
-/* 2131 */    MCD_OPC_Decode, 202, 11, 195, 1, // Opcode: VLD2LNd16
-/* 2136 */    MCD_OPC_CheckPredicate, 21, 208, 17, 0, // Skip to: 6701
-/* 2141 */    MCD_OPC_Decode, 205, 11, 195, 1, // Opcode: VLD2LNd16_UPD
+/* 2131 */    MCD_OPC_Decode, 163, 20, 172, 2, // Opcode: VLD2LNd16
+/* 2136 */    MCD_OPC_CheckPredicate, 26, 208, 17, 0, // Skip to: 6701
+/* 2141 */    MCD_OPC_Decode, 166, 20, 172, 2, // Opcode: VLD2LNd16_UPD
 /* 2146 */    MCD_OPC_FilterValue, 1, 198, 17, 0, // Skip to: 6701
 /* 2151 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 2154 */    MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 2195
 /* 2159 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 2162 */    MCD_OPC_FilterValue, 233, 3, 181, 17, 0, // Skip to: 6701
-/* 2168 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2185
+/* 2168 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2185
 /* 2173 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2185
-/* 2180 */    MCD_OPC_Decode, 187, 19, 194, 1, // Opcode: VST2LNq16
-/* 2185 */    MCD_OPC_CheckPredicate, 21, 159, 17, 0, // Skip to: 6701
-/* 2190 */    MCD_OPC_Decode, 190, 19, 194, 1, // Opcode: VST2LNq16_UPD
+/* 2180 */    MCD_OPC_Decode, 192, 28, 171, 2, // Opcode: VST2LNq16
+/* 2185 */    MCD_OPC_CheckPredicate, 26, 159, 17, 0, // Skip to: 6701
+/* 2190 */    MCD_OPC_Decode, 195, 28, 171, 2, // Opcode: VST2LNq16_UPD
 /* 2195 */    MCD_OPC_FilterValue, 2, 149, 17, 0, // Skip to: 6701
 /* 2200 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 2203 */    MCD_OPC_FilterValue, 233, 3, 140, 17, 0, // Skip to: 6701
-/* 2209 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2226
+/* 2209 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2226
 /* 2214 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2226
-/* 2221 */    MCD_OPC_Decode, 214, 11, 195, 1, // Opcode: VLD2LNq16
-/* 2226 */    MCD_OPC_CheckPredicate, 21, 118, 17, 0, // Skip to: 6701
-/* 2231 */    MCD_OPC_Decode, 217, 11, 195, 1, // Opcode: VLD2LNq16_UPD
+/* 2221 */    MCD_OPC_Decode, 175, 20, 172, 2, // Opcode: VLD2LNq16
+/* 2226 */    MCD_OPC_CheckPredicate, 26, 118, 17, 0, // Skip to: 6701
+/* 2231 */    MCD_OPC_Decode, 178, 20, 172, 2, // Opcode: VLD2LNq16_UPD
 /* 2236 */    MCD_OPC_FilterValue, 6, 108, 2, 0, // Skip to: 2861
 /* 2241 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 2244 */    MCD_OPC_FilterValue, 0, 49, 1, 0, // Skip to: 2554
@@ -6354,61 +11247,61 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 2261 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 2316
 /* 2266 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2269 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2284
-/* 2274 */    MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2306
-/* 2279 */    MCD_OPC_Decode, 143, 19, 196, 1, // Opcode: VST1d8Twb_fixed
+/* 2274 */    MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 2306
+/* 2279 */    MCD_OPC_Decode, 140, 28, 173, 2, // Opcode: VST1d8Twb_fixed
 /* 2284 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2306
-/* 2289 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2306
+/* 2289 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2306
 /* 2294 */    MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2306
-/* 2301 */    MCD_OPC_Decode, 141, 19, 196, 1, // Opcode: VST1d8T
-/* 2306 */    MCD_OPC_CheckPredicate, 21, 38, 17, 0, // Skip to: 6701
-/* 2311 */    MCD_OPC_Decode, 144, 19, 196, 1, // Opcode: VST1d8Twb_register
+/* 2301 */    MCD_OPC_Decode, 136, 28, 173, 2, // Opcode: VST1d8T
+/* 2306 */    MCD_OPC_CheckPredicate, 26, 38, 17, 0, // Skip to: 6701
+/* 2311 */    MCD_OPC_Decode, 141, 28, 173, 2, // Opcode: VST1d8Twb_register
 /* 2316 */    MCD_OPC_FilterValue, 1, 50, 0, 0, // Skip to: 2371
 /* 2321 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2324 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2339
-/* 2329 */    MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2361
-/* 2334 */    MCD_OPC_Decode, 234, 18, 196, 1, // Opcode: VST1d16Twb_fixed
+/* 2329 */    MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 2361
+/* 2334 */    MCD_OPC_Decode, 223, 27, 173, 2, // Opcode: VST1d16Twb_fixed
 /* 2339 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2361
-/* 2344 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2361
+/* 2344 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2361
 /* 2349 */    MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2361
-/* 2356 */    MCD_OPC_Decode, 232, 18, 196, 1, // Opcode: VST1d16T
-/* 2361 */    MCD_OPC_CheckPredicate, 21, 239, 16, 0, // Skip to: 6701
-/* 2366 */    MCD_OPC_Decode, 235, 18, 196, 1, // Opcode: VST1d16Twb_register
+/* 2356 */    MCD_OPC_Decode, 219, 27, 173, 2, // Opcode: VST1d16T
+/* 2361 */    MCD_OPC_CheckPredicate, 26, 239, 16, 0, // Skip to: 6701
+/* 2366 */    MCD_OPC_Decode, 224, 27, 173, 2, // Opcode: VST1d16Twb_register
 /* 2371 */    MCD_OPC_FilterValue, 2, 50, 0, 0, // Skip to: 2426
 /* 2376 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2379 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2394
-/* 2384 */    MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2416
-/* 2389 */    MCD_OPC_Decode, 245, 18, 196, 1, // Opcode: VST1d32Twb_fixed
+/* 2384 */    MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 2416
+/* 2389 */    MCD_OPC_Decode, 238, 27, 173, 2, // Opcode: VST1d32Twb_fixed
 /* 2394 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2416
-/* 2399 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2416
+/* 2399 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2416
 /* 2404 */    MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2416
-/* 2411 */    MCD_OPC_Decode, 243, 18, 196, 1, // Opcode: VST1d32T
-/* 2416 */    MCD_OPC_CheckPredicate, 21, 184, 16, 0, // Skip to: 6701
-/* 2421 */    MCD_OPC_Decode, 246, 18, 196, 1, // Opcode: VST1d32Twb_register
+/* 2411 */    MCD_OPC_Decode, 234, 27, 173, 2, // Opcode: VST1d32T
+/* 2416 */    MCD_OPC_CheckPredicate, 26, 184, 16, 0, // Skip to: 6701
+/* 2421 */    MCD_OPC_Decode, 239, 27, 173, 2, // Opcode: VST1d32Twb_register
 /* 2426 */    MCD_OPC_FilterValue, 3, 174, 16, 0, // Skip to: 6701
 /* 2431 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2434 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2449
-/* 2439 */    MCD_OPC_CheckPredicate, 21, 27, 0, 0, // Skip to: 2471
-/* 2444 */    MCD_OPC_Decode, 132, 19, 196, 1, // Opcode: VST1d64Twb_fixed
+/* 2439 */    MCD_OPC_CheckPredicate, 26, 27, 0, 0, // Skip to: 2471
+/* 2444 */    MCD_OPC_Decode, 253, 27, 173, 2, // Opcode: VST1d64Twb_fixed
 /* 2449 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2471
-/* 2454 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2471
+/* 2454 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2471
 /* 2459 */    MCD_OPC_CheckField, 5, 1, 0, 5, 0, 0, // Skip to: 2471
-/* 2466 */    MCD_OPC_Decode, 128, 19, 196, 1, // Opcode: VST1d64T
-/* 2471 */    MCD_OPC_CheckPredicate, 21, 129, 16, 0, // Skip to: 6701
-/* 2476 */    MCD_OPC_Decode, 133, 19, 196, 1, // Opcode: VST1d64Twb_register
+/* 2466 */    MCD_OPC_Decode, 249, 27, 173, 2, // Opcode: VST1d64T
+/* 2471 */    MCD_OPC_CheckPredicate, 26, 129, 16, 0, // Skip to: 6701
+/* 2476 */    MCD_OPC_Decode, 254, 27, 173, 2, // Opcode: VST1d64Twb_register
 /* 2481 */    MCD_OPC_FilterValue, 233, 3, 118, 16, 0, // Skip to: 6701
 /* 2487 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
 /* 2490 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2522
-/* 2495 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2512
+/* 2495 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2512
 /* 2500 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2512
-/* 2507 */    MCD_OPC_Decode, 231, 19, 197, 1, // Opcode: VST3LNd16
-/* 2512 */    MCD_OPC_CheckPredicate, 21, 88, 16, 0, // Skip to: 6701
-/* 2517 */    MCD_OPC_Decode, 234, 19, 197, 1, // Opcode: VST3LNd16_UPD
+/* 2507 */    MCD_OPC_Decode, 236, 28, 174, 2, // Opcode: VST3LNd16
+/* 2512 */    MCD_OPC_CheckPredicate, 26, 88, 16, 0, // Skip to: 6701
+/* 2517 */    MCD_OPC_Decode, 239, 28, 174, 2, // Opcode: VST3LNd16_UPD
 /* 2522 */    MCD_OPC_FilterValue, 2, 78, 16, 0, // Skip to: 6701
-/* 2527 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2544
+/* 2527 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2544
 /* 2532 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2544
-/* 2539 */    MCD_OPC_Decode, 243, 19, 197, 1, // Opcode: VST3LNq16
-/* 2544 */    MCD_OPC_CheckPredicate, 21, 56, 16, 0, // Skip to: 6701
-/* 2549 */    MCD_OPC_Decode, 246, 19, 197, 1, // Opcode: VST3LNq16_UPD
+/* 2539 */    MCD_OPC_Decode, 248, 28, 174, 2, // Opcode: VST3LNq16
+/* 2544 */    MCD_OPC_CheckPredicate, 26, 56, 16, 0, // Skip to: 6701
+/* 2549 */    MCD_OPC_Decode, 251, 28, 174, 2, // Opcode: VST3LNq16_UPD
 /* 2554 */    MCD_OPC_FilterValue, 2, 46, 16, 0, // Skip to: 6701
 /* 2559 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 2562 */    MCD_OPC_FilterValue, 0, 245, 0, 0, // Skip to: 2812
@@ -6418,61 +11311,61 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 2579 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2627
 /* 2584 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2587 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2602
-/* 2592 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2617
-/* 2597 */    MCD_OPC_Decode, 146, 11, 196, 1, // Opcode: VLD1d8Twb_fixed
+/* 2592 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 2617
+/* 2597 */    MCD_OPC_Decode, 221, 19, 173, 2, // Opcode: VLD1d8Twb_fixed
 /* 2602 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2617
-/* 2607 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2617
-/* 2612 */    MCD_OPC_Decode, 144, 11, 196, 1, // Opcode: VLD1d8T
-/* 2617 */    MCD_OPC_CheckPredicate, 21, 239, 15, 0, // Skip to: 6701
-/* 2622 */    MCD_OPC_Decode, 147, 11, 196, 1, // Opcode: VLD1d8Twb_register
+/* 2607 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 2617
+/* 2612 */    MCD_OPC_Decode, 217, 19, 173, 2, // Opcode: VLD1d8T
+/* 2617 */    MCD_OPC_CheckPredicate, 26, 239, 15, 0, // Skip to: 6701
+/* 2622 */    MCD_OPC_Decode, 222, 19, 173, 2, // Opcode: VLD1d8Twb_register
 /* 2627 */    MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2675
 /* 2632 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2635 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2650
-/* 2640 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2665
-/* 2645 */    MCD_OPC_Decode, 237, 10, 196, 1, // Opcode: VLD1d16Twb_fixed
+/* 2640 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 2665
+/* 2645 */    MCD_OPC_Decode, 176, 19, 173, 2, // Opcode: VLD1d16Twb_fixed
 /* 2650 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2665
-/* 2655 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2665
-/* 2660 */    MCD_OPC_Decode, 235, 10, 196, 1, // Opcode: VLD1d16T
-/* 2665 */    MCD_OPC_CheckPredicate, 21, 191, 15, 0, // Skip to: 6701
-/* 2670 */    MCD_OPC_Decode, 238, 10, 196, 1, // Opcode: VLD1d16Twb_register
+/* 2655 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 2665
+/* 2660 */    MCD_OPC_Decode, 172, 19, 173, 2, // Opcode: VLD1d16T
+/* 2665 */    MCD_OPC_CheckPredicate, 26, 191, 15, 0, // Skip to: 6701
+/* 2670 */    MCD_OPC_Decode, 177, 19, 173, 2, // Opcode: VLD1d16Twb_register
 /* 2675 */    MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 2723
 /* 2680 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2683 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2698
-/* 2688 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2713
-/* 2693 */    MCD_OPC_Decode, 248, 10, 196, 1, // Opcode: VLD1d32Twb_fixed
+/* 2688 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 2713
+/* 2693 */    MCD_OPC_Decode, 191, 19, 173, 2, // Opcode: VLD1d32Twb_fixed
 /* 2698 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2713
-/* 2703 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2713
-/* 2708 */    MCD_OPC_Decode, 246, 10, 196, 1, // Opcode: VLD1d32T
-/* 2713 */    MCD_OPC_CheckPredicate, 21, 143, 15, 0, // Skip to: 6701
-/* 2718 */    MCD_OPC_Decode, 249, 10, 196, 1, // Opcode: VLD1d32Twb_register
+/* 2703 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 2713
+/* 2708 */    MCD_OPC_Decode, 187, 19, 173, 2, // Opcode: VLD1d32T
+/* 2713 */    MCD_OPC_CheckPredicate, 26, 143, 15, 0, // Skip to: 6701
+/* 2718 */    MCD_OPC_Decode, 192, 19, 173, 2, // Opcode: VLD1d32Twb_register
 /* 2723 */    MCD_OPC_FilterValue, 3, 133, 15, 0, // Skip to: 6701
 /* 2728 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2731 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2746
-/* 2736 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2761
-/* 2741 */    MCD_OPC_Decode, 135, 11, 196, 1, // Opcode: VLD1d64Twb_fixed
+/* 2736 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 2761
+/* 2741 */    MCD_OPC_Decode, 206, 19, 173, 2, // Opcode: VLD1d64Twb_fixed
 /* 2746 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2761
-/* 2751 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2761
-/* 2756 */    MCD_OPC_Decode, 131, 11, 196, 1, // Opcode: VLD1d64T
-/* 2761 */    MCD_OPC_CheckPredicate, 21, 95, 15, 0, // Skip to: 6701
-/* 2766 */    MCD_OPC_Decode, 136, 11, 196, 1, // Opcode: VLD1d64Twb_register
+/* 2751 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 2761
+/* 2756 */    MCD_OPC_Decode, 202, 19, 173, 2, // Opcode: VLD1d64T
+/* 2761 */    MCD_OPC_CheckPredicate, 26, 95, 15, 0, // Skip to: 6701
+/* 2766 */    MCD_OPC_Decode, 207, 19, 173, 2, // Opcode: VLD1d64Twb_register
 /* 2771 */    MCD_OPC_FilterValue, 233, 3, 84, 15, 0, // Skip to: 6701
 /* 2777 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 2780 */    MCD_OPC_FilterValue, 0, 76, 15, 0, // Skip to: 6701
-/* 2785 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2802
+/* 2785 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2802
 /* 2790 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2802
-/* 2797 */    MCD_OPC_Decode, 154, 12, 198, 1, // Opcode: VLD3LNd16
-/* 2802 */    MCD_OPC_CheckPredicate, 21, 54, 15, 0, // Skip to: 6701
-/* 2807 */    MCD_OPC_Decode, 157, 12, 198, 1, // Opcode: VLD3LNd16_UPD
+/* 2797 */    MCD_OPC_Decode, 246, 20, 175, 2, // Opcode: VLD3LNd16
+/* 2802 */    MCD_OPC_CheckPredicate, 26, 54, 15, 0, // Skip to: 6701
+/* 2807 */    MCD_OPC_Decode, 249, 20, 175, 2, // Opcode: VLD3LNd16_UPD
 /* 2812 */    MCD_OPC_FilterValue, 1, 44, 15, 0, // Skip to: 6701
 /* 2817 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 2820 */    MCD_OPC_FilterValue, 0, 36, 15, 0, // Skip to: 6701
 /* 2825 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 2828 */    MCD_OPC_FilterValue, 233, 3, 27, 15, 0, // Skip to: 6701
-/* 2834 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 2851
+/* 2834 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 2851
 /* 2839 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 2851
-/* 2846 */    MCD_OPC_Decode, 166, 12, 198, 1, // Opcode: VLD3LNq16
-/* 2851 */    MCD_OPC_CheckPredicate, 21, 5, 15, 0, // Skip to: 6701
-/* 2856 */    MCD_OPC_Decode, 169, 12, 198, 1, // Opcode: VLD3LNq16_UPD
+/* 2846 */    MCD_OPC_Decode, 130, 21, 175, 2, // Opcode: VLD3LNq16
+/* 2851 */    MCD_OPC_CheckPredicate, 26, 5, 15, 0, // Skip to: 6701
+/* 2856 */    MCD_OPC_Decode, 133, 21, 175, 2, // Opcode: VLD3LNq16_UPD
 /* 2861 */    MCD_OPC_FilterValue, 7, 73, 2, 0, // Skip to: 3451
 /* 2866 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 2869 */    MCD_OPC_FilterValue, 0, 231, 1, 0, // Skip to: 3361
@@ -6484,49 +11377,49 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 2894 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 2942
 /* 2899 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2902 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2917
-/* 2907 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2932
-/* 2912 */    MCD_OPC_Decode, 145, 19, 196, 1, // Opcode: VST1d8wb_fixed
+/* 2907 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 2932
+/* 2912 */    MCD_OPC_Decode, 142, 28, 173, 2, // Opcode: VST1d8wb_fixed
 /* 2917 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2932
-/* 2922 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2932
-/* 2927 */    MCD_OPC_Decode, 136, 19, 196, 1, // Opcode: VST1d8
-/* 2932 */    MCD_OPC_CheckPredicate, 21, 180, 14, 0, // Skip to: 6701
-/* 2937 */    MCD_OPC_Decode, 146, 19, 196, 1, // Opcode: VST1d8wb_register
+/* 2922 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 2932
+/* 2927 */    MCD_OPC_Decode, 129, 28, 173, 2, // Opcode: VST1d8
+/* 2932 */    MCD_OPC_CheckPredicate, 26, 180, 14, 0, // Skip to: 6701
+/* 2937 */    MCD_OPC_Decode, 143, 28, 173, 2, // Opcode: VST1d8wb_register
 /* 2942 */    MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2990
 /* 2947 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2950 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2965
-/* 2955 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 2980
-/* 2960 */    MCD_OPC_Decode, 236, 18, 196, 1, // Opcode: VST1d16wb_fixed
+/* 2955 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 2980
+/* 2960 */    MCD_OPC_Decode, 225, 27, 173, 2, // Opcode: VST1d16wb_fixed
 /* 2965 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2980
-/* 2970 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 2980
-/* 2975 */    MCD_OPC_Decode, 227, 18, 196, 1, // Opcode: VST1d16
-/* 2980 */    MCD_OPC_CheckPredicate, 21, 132, 14, 0, // Skip to: 6701
-/* 2985 */    MCD_OPC_Decode, 237, 18, 196, 1, // Opcode: VST1d16wb_register
+/* 2970 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 2980
+/* 2975 */    MCD_OPC_Decode, 212, 27, 173, 2, // Opcode: VST1d16
+/* 2980 */    MCD_OPC_CheckPredicate, 26, 132, 14, 0, // Skip to: 6701
+/* 2985 */    MCD_OPC_Decode, 226, 27, 173, 2, // Opcode: VST1d16wb_register
 /* 2990 */    MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3038
 /* 2995 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 2998 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3013
-/* 3003 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3028
-/* 3008 */    MCD_OPC_Decode, 247, 18, 196, 1, // Opcode: VST1d32wb_fixed
+/* 3003 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3028
+/* 3008 */    MCD_OPC_Decode, 240, 27, 173, 2, // Opcode: VST1d32wb_fixed
 /* 3013 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3028
-/* 3018 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3028
-/* 3023 */    MCD_OPC_Decode, 238, 18, 196, 1, // Opcode: VST1d32
-/* 3028 */    MCD_OPC_CheckPredicate, 21, 84, 14, 0, // Skip to: 6701
-/* 3033 */    MCD_OPC_Decode, 248, 18, 196, 1, // Opcode: VST1d32wb_register
+/* 3018 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3028
+/* 3023 */    MCD_OPC_Decode, 227, 27, 173, 2, // Opcode: VST1d32
+/* 3028 */    MCD_OPC_CheckPredicate, 26, 84, 14, 0, // Skip to: 6701
+/* 3033 */    MCD_OPC_Decode, 241, 27, 173, 2, // Opcode: VST1d32wb_register
 /* 3038 */    MCD_OPC_FilterValue, 3, 74, 14, 0, // Skip to: 6701
 /* 3043 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3046 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3061
-/* 3051 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3076
-/* 3056 */    MCD_OPC_Decode, 134, 19, 196, 1, // Opcode: VST1d64wb_fixed
+/* 3051 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3076
+/* 3056 */    MCD_OPC_Decode, 255, 27, 173, 2, // Opcode: VST1d64wb_fixed
 /* 3061 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3076
-/* 3066 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3076
-/* 3071 */    MCD_OPC_Decode, 249, 18, 196, 1, // Opcode: VST1d64
-/* 3076 */    MCD_OPC_CheckPredicate, 21, 36, 14, 0, // Skip to: 6701
-/* 3081 */    MCD_OPC_Decode, 135, 19, 196, 1, // Opcode: VST1d64wb_register
+/* 3066 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3076
+/* 3071 */    MCD_OPC_Decode, 242, 27, 173, 2, // Opcode: VST1d64
+/* 3076 */    MCD_OPC_CheckPredicate, 26, 36, 14, 0, // Skip to: 6701
+/* 3081 */    MCD_OPC_Decode, 128, 28, 173, 2, // Opcode: VST1d64wb_register
 /* 3086 */    MCD_OPC_FilterValue, 233, 3, 25, 14, 0, // Skip to: 6701
-/* 3092 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3109
+/* 3092 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 3109
 /* 3097 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3109
-/* 3104 */    MCD_OPC_Decode, 150, 20, 200, 1, // Opcode: VST4LNd16
-/* 3109 */    MCD_OPC_CheckPredicate, 21, 3, 14, 0, // Skip to: 6701
-/* 3114 */    MCD_OPC_Decode, 153, 20, 200, 1, // Opcode: VST4LNd16_UPD
+/* 3104 */    MCD_OPC_Decode, 155, 29, 177, 2, // Opcode: VST4LNd16
+/* 3109 */    MCD_OPC_CheckPredicate, 26, 3, 14, 0, // Skip to: 6701
+/* 3114 */    MCD_OPC_Decode, 158, 29, 177, 2, // Opcode: VST4LNd16_UPD
 /* 3119 */    MCD_OPC_FilterValue, 2, 249, 13, 0, // Skip to: 6701
 /* 3124 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 3127 */    MCD_OPC_FilterValue, 232, 3, 195, 0, 0, // Skip to: 3328
@@ -6534,67 +11427,67 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 3136 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3184
 /* 3141 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3144 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3159
-/* 3149 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3174
-/* 3154 */    MCD_OPC_Decode, 148, 11, 196, 1, // Opcode: VLD1d8wb_fixed
+/* 3149 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3174
+/* 3154 */    MCD_OPC_Decode, 223, 19, 173, 2, // Opcode: VLD1d8wb_fixed
 /* 3159 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3174
-/* 3164 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3174
-/* 3169 */    MCD_OPC_Decode, 139, 11, 196, 1, // Opcode: VLD1d8
-/* 3174 */    MCD_OPC_CheckPredicate, 21, 194, 13, 0, // Skip to: 6701
-/* 3179 */    MCD_OPC_Decode, 149, 11, 196, 1, // Opcode: VLD1d8wb_register
+/* 3164 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3174
+/* 3169 */    MCD_OPC_Decode, 210, 19, 173, 2, // Opcode: VLD1d8
+/* 3174 */    MCD_OPC_CheckPredicate, 26, 194, 13, 0, // Skip to: 6701
+/* 3179 */    MCD_OPC_Decode, 224, 19, 173, 2, // Opcode: VLD1d8wb_register
 /* 3184 */    MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 3232
 /* 3189 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3192 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3207
-/* 3197 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3222
-/* 3202 */    MCD_OPC_Decode, 239, 10, 196, 1, // Opcode: VLD1d16wb_fixed
+/* 3197 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3222
+/* 3202 */    MCD_OPC_Decode, 178, 19, 173, 2, // Opcode: VLD1d16wb_fixed
 /* 3207 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3222
-/* 3212 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3222
-/* 3217 */    MCD_OPC_Decode, 230, 10, 196, 1, // Opcode: VLD1d16
-/* 3222 */    MCD_OPC_CheckPredicate, 21, 146, 13, 0, // Skip to: 6701
-/* 3227 */    MCD_OPC_Decode, 240, 10, 196, 1, // Opcode: VLD1d16wb_register
+/* 3212 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3222
+/* 3217 */    MCD_OPC_Decode, 165, 19, 173, 2, // Opcode: VLD1d16
+/* 3222 */    MCD_OPC_CheckPredicate, 26, 146, 13, 0, // Skip to: 6701
+/* 3227 */    MCD_OPC_Decode, 179, 19, 173, 2, // Opcode: VLD1d16wb_register
 /* 3232 */    MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 3280
 /* 3237 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3240 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3255
-/* 3245 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3270
-/* 3250 */    MCD_OPC_Decode, 250, 10, 196, 1, // Opcode: VLD1d32wb_fixed
+/* 3245 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3270
+/* 3250 */    MCD_OPC_Decode, 193, 19, 173, 2, // Opcode: VLD1d32wb_fixed
 /* 3255 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3270
-/* 3260 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3270
-/* 3265 */    MCD_OPC_Decode, 241, 10, 196, 1, // Opcode: VLD1d32
-/* 3270 */    MCD_OPC_CheckPredicate, 21, 98, 13, 0, // Skip to: 6701
-/* 3275 */    MCD_OPC_Decode, 251, 10, 196, 1, // Opcode: VLD1d32wb_register
+/* 3260 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3270
+/* 3265 */    MCD_OPC_Decode, 180, 19, 173, 2, // Opcode: VLD1d32
+/* 3270 */    MCD_OPC_CheckPredicate, 26, 98, 13, 0, // Skip to: 6701
+/* 3275 */    MCD_OPC_Decode, 194, 19, 173, 2, // Opcode: VLD1d32wb_register
 /* 3280 */    MCD_OPC_FilterValue, 3, 88, 13, 0, // Skip to: 6701
 /* 3285 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3288 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3303
-/* 3293 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3318
-/* 3298 */    MCD_OPC_Decode, 137, 11, 196, 1, // Opcode: VLD1d64wb_fixed
+/* 3293 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3318
+/* 3298 */    MCD_OPC_Decode, 208, 19, 173, 2, // Opcode: VLD1d64wb_fixed
 /* 3303 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3318
-/* 3308 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3318
-/* 3313 */    MCD_OPC_Decode, 252, 10, 196, 1, // Opcode: VLD1d64
-/* 3318 */    MCD_OPC_CheckPredicate, 21, 50, 13, 0, // Skip to: 6701
-/* 3323 */    MCD_OPC_Decode, 138, 11, 196, 1, // Opcode: VLD1d64wb_register
+/* 3308 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3318
+/* 3313 */    MCD_OPC_Decode, 195, 19, 173, 2, // Opcode: VLD1d64
+/* 3318 */    MCD_OPC_CheckPredicate, 26, 50, 13, 0, // Skip to: 6701
+/* 3323 */    MCD_OPC_Decode, 209, 19, 173, 2, // Opcode: VLD1d64wb_register
 /* 3328 */    MCD_OPC_FilterValue, 233, 3, 39, 13, 0, // Skip to: 6701
-/* 3334 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3351
+/* 3334 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 3351
 /* 3339 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3351
-/* 3346 */    MCD_OPC_Decode, 225, 12, 201, 1, // Opcode: VLD4LNd16
-/* 3351 */    MCD_OPC_CheckPredicate, 21, 17, 13, 0, // Skip to: 6701
-/* 3356 */    MCD_OPC_Decode, 228, 12, 201, 1, // Opcode: VLD4LNd16_UPD
+/* 3346 */    MCD_OPC_Decode, 192, 21, 178, 2, // Opcode: VLD4LNd16
+/* 3351 */    MCD_OPC_CheckPredicate, 26, 17, 13, 0, // Skip to: 6701
+/* 3356 */    MCD_OPC_Decode, 195, 21, 178, 2, // Opcode: VLD4LNd16_UPD
 /* 3361 */    MCD_OPC_FilterValue, 1, 7, 13, 0, // Skip to: 6701
 /* 3366 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 3369 */    MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 3410
 /* 3374 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 3377 */    MCD_OPC_FilterValue, 233, 3, 246, 12, 0, // Skip to: 6701
-/* 3383 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3400
+/* 3383 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 3400
 /* 3388 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3400
-/* 3395 */    MCD_OPC_Decode, 162, 20, 200, 1, // Opcode: VST4LNq16
-/* 3400 */    MCD_OPC_CheckPredicate, 21, 224, 12, 0, // Skip to: 6701
-/* 3405 */    MCD_OPC_Decode, 165, 20, 200, 1, // Opcode: VST4LNq16_UPD
+/* 3395 */    MCD_OPC_Decode, 167, 29, 177, 2, // Opcode: VST4LNq16
+/* 3400 */    MCD_OPC_CheckPredicate, 26, 224, 12, 0, // Skip to: 6701
+/* 3405 */    MCD_OPC_Decode, 170, 29, 177, 2, // Opcode: VST4LNq16_UPD
 /* 3410 */    MCD_OPC_FilterValue, 2, 214, 12, 0, // Skip to: 6701
 /* 3415 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 3418 */    MCD_OPC_FilterValue, 233, 3, 205, 12, 0, // Skip to: 6701
-/* 3424 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3441
+/* 3424 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 3441
 /* 3429 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3441
-/* 3436 */    MCD_OPC_Decode, 237, 12, 201, 1, // Opcode: VLD4LNq16
-/* 3441 */    MCD_OPC_CheckPredicate, 21, 183, 12, 0, // Skip to: 6701
-/* 3446 */    MCD_OPC_Decode, 240, 12, 201, 1, // Opcode: VLD4LNq16_UPD
+/* 3436 */    MCD_OPC_Decode, 204, 21, 178, 2, // Opcode: VLD4LNq16
+/* 3441 */    MCD_OPC_CheckPredicate, 26, 183, 12, 0, // Skip to: 6701
+/* 3446 */    MCD_OPC_Decode, 207, 21, 178, 2, // Opcode: VLD4LNq16_UPD
 /* 3451 */    MCD_OPC_FilterValue, 8, 185, 1, 0, // Skip to: 3897
 /* 3456 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 3459 */    MCD_OPC_FilterValue, 0, 39, 1, 0, // Skip to: 3759
@@ -6606,29 +11499,29 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 3484 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3532
 /* 3489 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3492 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3507
-/* 3497 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3522
-/* 3502 */    MCD_OPC_Decode, 211, 19, 199, 1, // Opcode: VST2d8wb_fixed
+/* 3497 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3522
+/* 3502 */    MCD_OPC_Decode, 216, 28, 176, 2, // Opcode: VST2d8wb_fixed
 /* 3507 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3522
-/* 3512 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3522
-/* 3517 */    MCD_OPC_Decode, 210, 19, 199, 1, // Opcode: VST2d8
-/* 3522 */    MCD_OPC_CheckPredicate, 21, 102, 12, 0, // Skip to: 6701
-/* 3527 */    MCD_OPC_Decode, 212, 19, 199, 1, // Opcode: VST2d8wb_register
+/* 3512 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3522
+/* 3517 */    MCD_OPC_Decode, 215, 28, 176, 2, // Opcode: VST2d8
+/* 3522 */    MCD_OPC_CheckPredicate, 26, 102, 12, 0, // Skip to: 6701
+/* 3527 */    MCD_OPC_Decode, 217, 28, 176, 2, // Opcode: VST2d8wb_register
 /* 3532 */    MCD_OPC_FilterValue, 1, 92, 12, 0, // Skip to: 6701
 /* 3537 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3540 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3555
-/* 3545 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3570
-/* 3550 */    MCD_OPC_Decode, 208, 19, 199, 1, // Opcode: VST2d32wb_fixed
+/* 3545 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3570
+/* 3550 */    MCD_OPC_Decode, 213, 28, 176, 2, // Opcode: VST2d32wb_fixed
 /* 3555 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3570
-/* 3560 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3570
-/* 3565 */    MCD_OPC_Decode, 207, 19, 199, 1, // Opcode: VST2d32
-/* 3570 */    MCD_OPC_CheckPredicate, 21, 54, 12, 0, // Skip to: 6701
-/* 3575 */    MCD_OPC_Decode, 209, 19, 199, 1, // Opcode: VST2d32wb_register
+/* 3560 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3570
+/* 3565 */    MCD_OPC_Decode, 212, 28, 176, 2, // Opcode: VST2d32
+/* 3570 */    MCD_OPC_CheckPredicate, 26, 54, 12, 0, // Skip to: 6701
+/* 3575 */    MCD_OPC_Decode, 214, 28, 176, 2, // Opcode: VST2d32wb_register
 /* 3580 */    MCD_OPC_FilterValue, 233, 3, 43, 12, 0, // Skip to: 6701
-/* 3586 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3603
+/* 3586 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 3603
 /* 3591 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3603
-/* 3598 */    MCD_OPC_Decode, 217, 18, 192, 1, // Opcode: VST1LNd32
-/* 3603 */    MCD_OPC_CheckPredicate, 21, 21, 12, 0, // Skip to: 6701
-/* 3608 */    MCD_OPC_Decode, 218, 18, 192, 1, // Opcode: VST1LNd32_UPD
+/* 3598 */    MCD_OPC_Decode, 202, 27, 169, 2, // Opcode: VST1LNd32
+/* 3603 */    MCD_OPC_CheckPredicate, 26, 21, 12, 0, // Skip to: 6701
+/* 3608 */    MCD_OPC_Decode, 203, 27, 169, 2, // Opcode: VST1LNd32_UPD
 /* 3613 */    MCD_OPC_FilterValue, 2, 11, 12, 0, // Skip to: 6701
 /* 3618 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 3621 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 3726
@@ -6636,29 +11529,29 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 3630 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3678
 /* 3635 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3638 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3653
-/* 3643 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3668
-/* 3648 */    MCD_OPC_Decode, 238, 11, 199, 1, // Opcode: VLD2d8wb_fixed
+/* 3643 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3668
+/* 3648 */    MCD_OPC_Decode, 199, 20, 176, 2, // Opcode: VLD2d8wb_fixed
 /* 3653 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3668
-/* 3658 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3668
-/* 3663 */    MCD_OPC_Decode, 237, 11, 199, 1, // Opcode: VLD2d8
-/* 3668 */    MCD_OPC_CheckPredicate, 21, 212, 11, 0, // Skip to: 6701
-/* 3673 */    MCD_OPC_Decode, 239, 11, 199, 1, // Opcode: VLD2d8wb_register
+/* 3658 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3668
+/* 3663 */    MCD_OPC_Decode, 198, 20, 176, 2, // Opcode: VLD2d8
+/* 3668 */    MCD_OPC_CheckPredicate, 26, 212, 11, 0, // Skip to: 6701
+/* 3673 */    MCD_OPC_Decode, 200, 20, 176, 2, // Opcode: VLD2d8wb_register
 /* 3678 */    MCD_OPC_FilterValue, 1, 202, 11, 0, // Skip to: 6701
 /* 3683 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3686 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3701
-/* 3691 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3716
-/* 3696 */    MCD_OPC_Decode, 235, 11, 199, 1, // Opcode: VLD2d32wb_fixed
+/* 3691 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3716
+/* 3696 */    MCD_OPC_Decode, 196, 20, 176, 2, // Opcode: VLD2d32wb_fixed
 /* 3701 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3716
-/* 3706 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3716
-/* 3711 */    MCD_OPC_Decode, 234, 11, 199, 1, // Opcode: VLD2d32
-/* 3716 */    MCD_OPC_CheckPredicate, 21, 164, 11, 0, // Skip to: 6701
-/* 3721 */    MCD_OPC_Decode, 236, 11, 199, 1, // Opcode: VLD2d32wb_register
+/* 3706 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3716
+/* 3711 */    MCD_OPC_Decode, 195, 20, 176, 2, // Opcode: VLD2d32
+/* 3716 */    MCD_OPC_CheckPredicate, 26, 164, 11, 0, // Skip to: 6701
+/* 3721 */    MCD_OPC_Decode, 197, 20, 176, 2, // Opcode: VLD2d32wb_register
 /* 3726 */    MCD_OPC_FilterValue, 233, 3, 153, 11, 0, // Skip to: 6701
-/* 3732 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 3749
+/* 3732 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 3749
 /* 3737 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 3749
-/* 3744 */    MCD_OPC_Decode, 220, 10, 193, 1, // Opcode: VLD1LNd32
-/* 3749 */    MCD_OPC_CheckPredicate, 21, 131, 11, 0, // Skip to: 6701
-/* 3754 */    MCD_OPC_Decode, 221, 10, 193, 1, // Opcode: VLD1LNd32_UPD
+/* 3744 */    MCD_OPC_Decode, 155, 19, 170, 2, // Opcode: VLD1LNd32
+/* 3749 */    MCD_OPC_CheckPredicate, 26, 131, 11, 0, // Skip to: 6701
+/* 3754 */    MCD_OPC_Decode, 156, 19, 170, 2, // Opcode: VLD1LNd32_UPD
 /* 3759 */    MCD_OPC_FilterValue, 1, 121, 11, 0, // Skip to: 6701
 /* 3764 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 3767 */    MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 3832
@@ -6668,13 +11561,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 3783 */    MCD_OPC_FilterValue, 232, 3, 96, 11, 0, // Skip to: 6701
 /* 3789 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3792 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3807
-/* 3797 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3822
-/* 3802 */    MCD_OPC_Decode, 205, 19, 199, 1, // Opcode: VST2d16wb_fixed
+/* 3797 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3822
+/* 3802 */    MCD_OPC_Decode, 210, 28, 176, 2, // Opcode: VST2d16wb_fixed
 /* 3807 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3822
-/* 3812 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3822
-/* 3817 */    MCD_OPC_Decode, 204, 19, 199, 1, // Opcode: VST2d16
-/* 3822 */    MCD_OPC_CheckPredicate, 21, 58, 11, 0, // Skip to: 6701
-/* 3827 */    MCD_OPC_Decode, 206, 19, 199, 1, // Opcode: VST2d16wb_register
+/* 3812 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3822
+/* 3817 */    MCD_OPC_Decode, 209, 28, 176, 2, // Opcode: VST2d16
+/* 3822 */    MCD_OPC_CheckPredicate, 26, 58, 11, 0, // Skip to: 6701
+/* 3827 */    MCD_OPC_Decode, 211, 28, 176, 2, // Opcode: VST2d16wb_register
 /* 3832 */    MCD_OPC_FilterValue, 2, 48, 11, 0, // Skip to: 6701
 /* 3837 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 3840 */    MCD_OPC_FilterValue, 0, 40, 11, 0, // Skip to: 6701
@@ -6682,13 +11575,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 3848 */    MCD_OPC_FilterValue, 232, 3, 31, 11, 0, // Skip to: 6701
 /* 3854 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3857 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3872
-/* 3862 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3887
-/* 3867 */    MCD_OPC_Decode, 232, 11, 199, 1, // Opcode: VLD2d16wb_fixed
+/* 3862 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3887
+/* 3867 */    MCD_OPC_Decode, 193, 20, 176, 2, // Opcode: VLD2d16wb_fixed
 /* 3872 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3887
-/* 3877 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3887
-/* 3882 */    MCD_OPC_Decode, 231, 11, 199, 1, // Opcode: VLD2d16
-/* 3887 */    MCD_OPC_CheckPredicate, 21, 249, 10, 0, // Skip to: 6701
-/* 3892 */    MCD_OPC_Decode, 233, 11, 199, 1, // Opcode: VLD2d16wb_register
+/* 3877 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3887
+/* 3882 */    MCD_OPC_Decode, 192, 20, 176, 2, // Opcode: VLD2d16
+/* 3887 */    MCD_OPC_CheckPredicate, 26, 249, 10, 0, // Skip to: 6701
+/* 3892 */    MCD_OPC_Decode, 194, 20, 176, 2, // Opcode: VLD2d16wb_register
 /* 3897 */    MCD_OPC_FilterValue, 9, 27, 2, 0, // Skip to: 4441
 /* 3902 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 3905 */    MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4221
@@ -6700,31 +11593,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 3930 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 3978
 /* 3935 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3938 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3953
-/* 3943 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 3968
-/* 3948 */    MCD_OPC_Decode, 202, 19, 199, 1, // Opcode: VST2b8wb_fixed
+/* 3943 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 3968
+/* 3948 */    MCD_OPC_Decode, 207, 28, 176, 2, // Opcode: VST2b8wb_fixed
 /* 3953 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 3968
-/* 3958 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 3968
-/* 3963 */    MCD_OPC_Decode, 201, 19, 199, 1, // Opcode: VST2b8
-/* 3968 */    MCD_OPC_CheckPredicate, 21, 168, 10, 0, // Skip to: 6701
-/* 3973 */    MCD_OPC_Decode, 203, 19, 199, 1, // Opcode: VST2b8wb_register
+/* 3958 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 3968
+/* 3963 */    MCD_OPC_Decode, 206, 28, 176, 2, // Opcode: VST2b8
+/* 3968 */    MCD_OPC_CheckPredicate, 26, 168, 10, 0, // Skip to: 6701
+/* 3973 */    MCD_OPC_Decode, 208, 28, 176, 2, // Opcode: VST2b8wb_register
 /* 3978 */    MCD_OPC_FilterValue, 1, 158, 10, 0, // Skip to: 6701
 /* 3983 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 3986 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4001
-/* 3991 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4016
-/* 3996 */    MCD_OPC_Decode, 199, 19, 199, 1, // Opcode: VST2b32wb_fixed
+/* 3991 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4016
+/* 3996 */    MCD_OPC_Decode, 204, 28, 176, 2, // Opcode: VST2b32wb_fixed
 /* 4001 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4016
-/* 4006 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4016
-/* 4011 */    MCD_OPC_Decode, 198, 19, 199, 1, // Opcode: VST2b32
-/* 4016 */    MCD_OPC_CheckPredicate, 21, 120, 10, 0, // Skip to: 6701
-/* 4021 */    MCD_OPC_Decode, 200, 19, 199, 1, // Opcode: VST2b32wb_register
+/* 4006 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4016
+/* 4011 */    MCD_OPC_Decode, 203, 28, 176, 2, // Opcode: VST2b32
+/* 4016 */    MCD_OPC_CheckPredicate, 26, 120, 10, 0, // Skip to: 6701
+/* 4021 */    MCD_OPC_Decode, 205, 28, 176, 2, // Opcode: VST2b32wb_register
 /* 4026 */    MCD_OPC_FilterValue, 233, 3, 109, 10, 0, // Skip to: 6701
 /* 4032 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 4035 */    MCD_OPC_FilterValue, 0, 101, 10, 0, // Skip to: 6701
-/* 4040 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4057
+/* 4040 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4057
 /* 4045 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4057
-/* 4052 */    MCD_OPC_Decode, 179, 19, 194, 1, // Opcode: VST2LNd32
-/* 4057 */    MCD_OPC_CheckPredicate, 21, 79, 10, 0, // Skip to: 6701
-/* 4062 */    MCD_OPC_Decode, 182, 19, 194, 1, // Opcode: VST2LNd32_UPD
+/* 4052 */    MCD_OPC_Decode, 184, 28, 171, 2, // Opcode: VST2LNd32
+/* 4057 */    MCD_OPC_CheckPredicate, 26, 79, 10, 0, // Skip to: 6701
+/* 4062 */    MCD_OPC_Decode, 187, 28, 171, 2, // Opcode: VST2LNd32_UPD
 /* 4067 */    MCD_OPC_FilterValue, 2, 69, 10, 0, // Skip to: 6701
 /* 4072 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 4075 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4180
@@ -6732,31 +11625,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4084 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4132
 /* 4089 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4092 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4107
-/* 4097 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4122
-/* 4102 */    MCD_OPC_Decode, 229, 11, 199, 1, // Opcode: VLD2b8wb_fixed
+/* 4097 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4122
+/* 4102 */    MCD_OPC_Decode, 190, 20, 176, 2, // Opcode: VLD2b8wb_fixed
 /* 4107 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4122
-/* 4112 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4122
-/* 4117 */    MCD_OPC_Decode, 228, 11, 199, 1, // Opcode: VLD2b8
-/* 4122 */    MCD_OPC_CheckPredicate, 21, 14, 10, 0, // Skip to: 6701
-/* 4127 */    MCD_OPC_Decode, 230, 11, 199, 1, // Opcode: VLD2b8wb_register
+/* 4112 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4122
+/* 4117 */    MCD_OPC_Decode, 189, 20, 176, 2, // Opcode: VLD2b8
+/* 4122 */    MCD_OPC_CheckPredicate, 26, 14, 10, 0, // Skip to: 6701
+/* 4127 */    MCD_OPC_Decode, 191, 20, 176, 2, // Opcode: VLD2b8wb_register
 /* 4132 */    MCD_OPC_FilterValue, 1, 4, 10, 0, // Skip to: 6701
 /* 4137 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4140 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4155
-/* 4145 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4170
-/* 4150 */    MCD_OPC_Decode, 226, 11, 199, 1, // Opcode: VLD2b32wb_fixed
+/* 4145 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4170
+/* 4150 */    MCD_OPC_Decode, 187, 20, 176, 2, // Opcode: VLD2b32wb_fixed
 /* 4155 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4170
-/* 4160 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4170
-/* 4165 */    MCD_OPC_Decode, 225, 11, 199, 1, // Opcode: VLD2b32
-/* 4170 */    MCD_OPC_CheckPredicate, 21, 222, 9, 0, // Skip to: 6701
-/* 4175 */    MCD_OPC_Decode, 227, 11, 199, 1, // Opcode: VLD2b32wb_register
+/* 4160 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4170
+/* 4165 */    MCD_OPC_Decode, 186, 20, 176, 2, // Opcode: VLD2b32
+/* 4170 */    MCD_OPC_CheckPredicate, 26, 222, 9, 0, // Skip to: 6701
+/* 4175 */    MCD_OPC_Decode, 188, 20, 176, 2, // Opcode: VLD2b32wb_register
 /* 4180 */    MCD_OPC_FilterValue, 233, 3, 211, 9, 0, // Skip to: 6701
 /* 4186 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 4189 */    MCD_OPC_FilterValue, 0, 203, 9, 0, // Skip to: 6701
-/* 4194 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4211
+/* 4194 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4211
 /* 4199 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4211
-/* 4206 */    MCD_OPC_Decode, 206, 11, 195, 1, // Opcode: VLD2LNd32
-/* 4211 */    MCD_OPC_CheckPredicate, 21, 181, 9, 0, // Skip to: 6701
-/* 4216 */    MCD_OPC_Decode, 209, 11, 195, 1, // Opcode: VLD2LNd32_UPD
+/* 4206 */    MCD_OPC_Decode, 167, 20, 172, 2, // Opcode: VLD2LNd32
+/* 4211 */    MCD_OPC_CheckPredicate, 26, 181, 9, 0, // Skip to: 6701
+/* 4216 */    MCD_OPC_Decode, 170, 20, 172, 2, // Opcode: VLD2LNd32_UPD
 /* 4221 */    MCD_OPC_FilterValue, 1, 171, 9, 0, // Skip to: 6701
 /* 4226 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 4229 */    MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 4335
@@ -6766,21 +11659,21 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4246 */    MCD_OPC_FilterValue, 0, 146, 9, 0, // Skip to: 6701
 /* 4251 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4254 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4269
-/* 4259 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4284
-/* 4264 */    MCD_OPC_Decode, 196, 19, 199, 1, // Opcode: VST2b16wb_fixed
+/* 4259 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4284
+/* 4264 */    MCD_OPC_Decode, 201, 28, 176, 2, // Opcode: VST2b16wb_fixed
 /* 4269 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4284
-/* 4274 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4284
-/* 4279 */    MCD_OPC_Decode, 195, 19, 199, 1, // Opcode: VST2b16
-/* 4284 */    MCD_OPC_CheckPredicate, 21, 108, 9, 0, // Skip to: 6701
-/* 4289 */    MCD_OPC_Decode, 197, 19, 199, 1, // Opcode: VST2b16wb_register
+/* 4274 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4284
+/* 4279 */    MCD_OPC_Decode, 200, 28, 176, 2, // Opcode: VST2b16
+/* 4284 */    MCD_OPC_CheckPredicate, 26, 108, 9, 0, // Skip to: 6701
+/* 4289 */    MCD_OPC_Decode, 202, 28, 176, 2, // Opcode: VST2b16wb_register
 /* 4294 */    MCD_OPC_FilterValue, 233, 3, 97, 9, 0, // Skip to: 6701
 /* 4300 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 4303 */    MCD_OPC_FilterValue, 0, 89, 9, 0, // Skip to: 6701
-/* 4308 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4325
+/* 4308 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4325
 /* 4313 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4325
-/* 4320 */    MCD_OPC_Decode, 191, 19, 194, 1, // Opcode: VST2LNq32
-/* 4325 */    MCD_OPC_CheckPredicate, 21, 67, 9, 0, // Skip to: 6701
-/* 4330 */    MCD_OPC_Decode, 194, 19, 194, 1, // Opcode: VST2LNq32_UPD
+/* 4320 */    MCD_OPC_Decode, 196, 28, 171, 2, // Opcode: VST2LNq32
+/* 4325 */    MCD_OPC_CheckPredicate, 26, 67, 9, 0, // Skip to: 6701
+/* 4330 */    MCD_OPC_Decode, 199, 28, 171, 2, // Opcode: VST2LNq32_UPD
 /* 4335 */    MCD_OPC_FilterValue, 2, 57, 9, 0, // Skip to: 6701
 /* 4340 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 4343 */    MCD_OPC_FilterValue, 232, 3, 51, 0, 0, // Skip to: 4400
@@ -6788,21 +11681,21 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4352 */    MCD_OPC_FilterValue, 0, 40, 9, 0, // Skip to: 6701
 /* 4357 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4360 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4375
-/* 4365 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4390
-/* 4370 */    MCD_OPC_Decode, 223, 11, 199, 1, // Opcode: VLD2b16wb_fixed
+/* 4365 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4390
+/* 4370 */    MCD_OPC_Decode, 184, 20, 176, 2, // Opcode: VLD2b16wb_fixed
 /* 4375 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4390
-/* 4380 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4390
-/* 4385 */    MCD_OPC_Decode, 222, 11, 199, 1, // Opcode: VLD2b16
-/* 4390 */    MCD_OPC_CheckPredicate, 21, 2, 9, 0, // Skip to: 6701
-/* 4395 */    MCD_OPC_Decode, 224, 11, 199, 1, // Opcode: VLD2b16wb_register
+/* 4380 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4390
+/* 4385 */    MCD_OPC_Decode, 183, 20, 176, 2, // Opcode: VLD2b16
+/* 4390 */    MCD_OPC_CheckPredicate, 26, 2, 9, 0, // Skip to: 6701
+/* 4395 */    MCD_OPC_Decode, 185, 20, 176, 2, // Opcode: VLD2b16wb_register
 /* 4400 */    MCD_OPC_FilterValue, 233, 3, 247, 8, 0, // Skip to: 6701
 /* 4406 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 4409 */    MCD_OPC_FilterValue, 0, 239, 8, 0, // Skip to: 6701
-/* 4414 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4431
+/* 4414 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4431
 /* 4419 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4431
-/* 4426 */    MCD_OPC_Decode, 218, 11, 195, 1, // Opcode: VLD2LNq32
-/* 4431 */    MCD_OPC_CheckPredicate, 21, 217, 8, 0, // Skip to: 6701
-/* 4436 */    MCD_OPC_Decode, 221, 11, 195, 1, // Opcode: VLD2LNq32_UPD
+/* 4426 */    MCD_OPC_Decode, 179, 20, 172, 2, // Opcode: VLD2LNq32
+/* 4431 */    MCD_OPC_CheckPredicate, 26, 217, 8, 0, // Skip to: 6701
+/* 4436 */    MCD_OPC_Decode, 182, 20, 172, 2, // Opcode: VLD2LNq32_UPD
 /* 4441 */    MCD_OPC_FilterValue, 10, 123, 2, 0, // Skip to: 5081
 /* 4446 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 4449 */    MCD_OPC_FilterValue, 0, 55, 1, 0, // Skip to: 4765
@@ -6814,31 +11707,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4474 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4522
 /* 4479 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4482 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4497
-/* 4487 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4512
-/* 4492 */    MCD_OPC_Decode, 173, 19, 196, 1, // Opcode: VST1q8wb_fixed
+/* 4487 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4512
+/* 4492 */    MCD_OPC_Decode, 178, 28, 173, 2, // Opcode: VST1q8wb_fixed
 /* 4497 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4512
-/* 4502 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4512
-/* 4507 */    MCD_OPC_Decode, 168, 19, 196, 1, // Opcode: VST1q8
-/* 4512 */    MCD_OPC_CheckPredicate, 21, 136, 8, 0, // Skip to: 6701
-/* 4517 */    MCD_OPC_Decode, 174, 19, 196, 1, // Opcode: VST1q8wb_register
+/* 4502 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4512
+/* 4507 */    MCD_OPC_Decode, 171, 28, 173, 2, // Opcode: VST1q8
+/* 4512 */    MCD_OPC_CheckPredicate, 26, 136, 8, 0, // Skip to: 6701
+/* 4517 */    MCD_OPC_Decode, 179, 28, 173, 2, // Opcode: VST1q8wb_register
 /* 4522 */    MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 6701
 /* 4527 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4530 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4545
-/* 4535 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4560
-/* 4540 */    MCD_OPC_Decode, 159, 19, 196, 1, // Opcode: VST1q32wb_fixed
+/* 4535 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4560
+/* 4540 */    MCD_OPC_Decode, 160, 28, 173, 2, // Opcode: VST1q32wb_fixed
 /* 4545 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4560
-/* 4550 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4560
-/* 4555 */    MCD_OPC_Decode, 154, 19, 196, 1, // Opcode: VST1q32
-/* 4560 */    MCD_OPC_CheckPredicate, 21, 88, 8, 0, // Skip to: 6701
-/* 4565 */    MCD_OPC_Decode, 160, 19, 196, 1, // Opcode: VST1q32wb_register
+/* 4550 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4560
+/* 4555 */    MCD_OPC_Decode, 153, 28, 173, 2, // Opcode: VST1q32
+/* 4560 */    MCD_OPC_CheckPredicate, 26, 88, 8, 0, // Skip to: 6701
+/* 4565 */    MCD_OPC_Decode, 161, 28, 173, 2, // Opcode: VST1q32wb_register
 /* 4570 */    MCD_OPC_FilterValue, 233, 3, 77, 8, 0, // Skip to: 6701
 /* 4576 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
 /* 4579 */    MCD_OPC_FilterValue, 0, 69, 8, 0, // Skip to: 6701
-/* 4584 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4601
+/* 4584 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4601
 /* 4589 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4601
-/* 4596 */    MCD_OPC_Decode, 235, 19, 197, 1, // Opcode: VST3LNd32
-/* 4601 */    MCD_OPC_CheckPredicate, 21, 47, 8, 0, // Skip to: 6701
-/* 4606 */    MCD_OPC_Decode, 238, 19, 197, 1, // Opcode: VST3LNd32_UPD
+/* 4596 */    MCD_OPC_Decode, 240, 28, 174, 2, // Opcode: VST3LNd32
+/* 4601 */    MCD_OPC_CheckPredicate, 26, 47, 8, 0, // Skip to: 6701
+/* 4606 */    MCD_OPC_Decode, 243, 28, 174, 2, // Opcode: VST3LNd32_UPD
 /* 4611 */    MCD_OPC_FilterValue, 2, 37, 8, 0, // Skip to: 6701
 /* 4616 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 4619 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 4724
@@ -6846,31 +11739,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4628 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4676
 /* 4633 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4636 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4651
-/* 4641 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4666
-/* 4646 */    MCD_OPC_Decode, 176, 11, 196, 1, // Opcode: VLD1q8wb_fixed
+/* 4641 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4666
+/* 4646 */    MCD_OPC_Decode, 131, 20, 173, 2, // Opcode: VLD1q8wb_fixed
 /* 4651 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4666
-/* 4656 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4666
-/* 4661 */    MCD_OPC_Decode, 171, 11, 196, 1, // Opcode: VLD1q8
-/* 4666 */    MCD_OPC_CheckPredicate, 21, 238, 7, 0, // Skip to: 6701
-/* 4671 */    MCD_OPC_Decode, 177, 11, 196, 1, // Opcode: VLD1q8wb_register
+/* 4656 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4666
+/* 4661 */    MCD_OPC_Decode, 252, 19, 173, 2, // Opcode: VLD1q8
+/* 4666 */    MCD_OPC_CheckPredicate, 26, 238, 7, 0, // Skip to: 6701
+/* 4671 */    MCD_OPC_Decode, 132, 20, 173, 2, // Opcode: VLD1q8wb_register
 /* 4676 */    MCD_OPC_FilterValue, 1, 228, 7, 0, // Skip to: 6701
 /* 4681 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4684 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4699
-/* 4689 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4714
-/* 4694 */    MCD_OPC_Decode, 162, 11, 196, 1, // Opcode: VLD1q32wb_fixed
+/* 4689 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4714
+/* 4694 */    MCD_OPC_Decode, 241, 19, 173, 2, // Opcode: VLD1q32wb_fixed
 /* 4699 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4714
-/* 4704 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4714
-/* 4709 */    MCD_OPC_Decode, 157, 11, 196, 1, // Opcode: VLD1q32
-/* 4714 */    MCD_OPC_CheckPredicate, 21, 190, 7, 0, // Skip to: 6701
-/* 4719 */    MCD_OPC_Decode, 163, 11, 196, 1, // Opcode: VLD1q32wb_register
+/* 4704 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4714
+/* 4709 */    MCD_OPC_Decode, 234, 19, 173, 2, // Opcode: VLD1q32
+/* 4714 */    MCD_OPC_CheckPredicate, 26, 190, 7, 0, // Skip to: 6701
+/* 4719 */    MCD_OPC_Decode, 242, 19, 173, 2, // Opcode: VLD1q32wb_register
 /* 4724 */    MCD_OPC_FilterValue, 233, 3, 179, 7, 0, // Skip to: 6701
 /* 4730 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
 /* 4733 */    MCD_OPC_FilterValue, 0, 171, 7, 0, // Skip to: 6701
-/* 4738 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4755
+/* 4738 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4755
 /* 4743 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4755
-/* 4750 */    MCD_OPC_Decode, 158, 12, 198, 1, // Opcode: VLD3LNd32
-/* 4755 */    MCD_OPC_CheckPredicate, 21, 149, 7, 0, // Skip to: 6701
-/* 4760 */    MCD_OPC_Decode, 161, 12, 198, 1, // Opcode: VLD3LNd32_UPD
+/* 4750 */    MCD_OPC_Decode, 250, 20, 175, 2, // Opcode: VLD3LNd32
+/* 4755 */    MCD_OPC_CheckPredicate, 26, 149, 7, 0, // Skip to: 6701
+/* 4760 */    MCD_OPC_Decode, 253, 20, 175, 2, // Opcode: VLD3LNd32_UPD
 /* 4765 */    MCD_OPC_FilterValue, 1, 139, 7, 0, // Skip to: 6701
 /* 4770 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 4773 */    MCD_OPC_FilterValue, 0, 149, 0, 0, // Skip to: 4927
@@ -6880,31 +11773,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4790 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4838
 /* 4795 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4798 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4813
-/* 4803 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4828
-/* 4808 */    MCD_OPC_Decode, 152, 19, 196, 1, // Opcode: VST1q16wb_fixed
+/* 4803 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4828
+/* 4808 */    MCD_OPC_Decode, 151, 28, 173, 2, // Opcode: VST1q16wb_fixed
 /* 4813 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4828
-/* 4818 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4828
-/* 4823 */    MCD_OPC_Decode, 147, 19, 196, 1, // Opcode: VST1q16
-/* 4828 */    MCD_OPC_CheckPredicate, 21, 76, 7, 0, // Skip to: 6701
-/* 4833 */    MCD_OPC_Decode, 153, 19, 196, 1, // Opcode: VST1q16wb_register
+/* 4818 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4828
+/* 4823 */    MCD_OPC_Decode, 144, 28, 173, 2, // Opcode: VST1q16
+/* 4828 */    MCD_OPC_CheckPredicate, 26, 76, 7, 0, // Skip to: 6701
+/* 4833 */    MCD_OPC_Decode, 152, 28, 173, 2, // Opcode: VST1q16wb_register
 /* 4838 */    MCD_OPC_FilterValue, 1, 66, 7, 0, // Skip to: 6701
 /* 4843 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4846 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4861
-/* 4851 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4876
-/* 4856 */    MCD_OPC_Decode, 166, 19, 196, 1, // Opcode: VST1q64wb_fixed
+/* 4851 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4876
+/* 4856 */    MCD_OPC_Decode, 169, 28, 173, 2, // Opcode: VST1q64wb_fixed
 /* 4861 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4876
-/* 4866 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4876
-/* 4871 */    MCD_OPC_Decode, 161, 19, 196, 1, // Opcode: VST1q64
-/* 4876 */    MCD_OPC_CheckPredicate, 21, 28, 7, 0, // Skip to: 6701
-/* 4881 */    MCD_OPC_Decode, 167, 19, 196, 1, // Opcode: VST1q64wb_register
+/* 4866 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4876
+/* 4871 */    MCD_OPC_Decode, 162, 28, 173, 2, // Opcode: VST1q64
+/* 4876 */    MCD_OPC_CheckPredicate, 26, 28, 7, 0, // Skip to: 6701
+/* 4881 */    MCD_OPC_Decode, 170, 28, 173, 2, // Opcode: VST1q64wb_register
 /* 4886 */    MCD_OPC_FilterValue, 233, 3, 17, 7, 0, // Skip to: 6701
 /* 4892 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
 /* 4895 */    MCD_OPC_FilterValue, 0, 9, 7, 0, // Skip to: 6701
-/* 4900 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 4917
+/* 4900 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 4917
 /* 4905 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 4917
-/* 4912 */    MCD_OPC_Decode, 247, 19, 197, 1, // Opcode: VST3LNq32
-/* 4917 */    MCD_OPC_CheckPredicate, 21, 243, 6, 0, // Skip to: 6701
-/* 4922 */    MCD_OPC_Decode, 250, 19, 197, 1, // Opcode: VST3LNq32_UPD
+/* 4912 */    MCD_OPC_Decode, 252, 28, 174, 2, // Opcode: VST3LNq32
+/* 4917 */    MCD_OPC_CheckPredicate, 26, 243, 6, 0, // Skip to: 6701
+/* 4922 */    MCD_OPC_Decode, 255, 28, 174, 2, // Opcode: VST3LNq32_UPD
 /* 4927 */    MCD_OPC_FilterValue, 2, 233, 6, 0, // Skip to: 6701
 /* 4932 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 4935 */    MCD_OPC_FilterValue, 232, 3, 99, 0, 0, // Skip to: 5040
@@ -6912,31 +11805,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 4944 */    MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 4992
 /* 4949 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 4952 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 4967
-/* 4957 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 4982
-/* 4962 */    MCD_OPC_Decode, 155, 11, 196, 1, // Opcode: VLD1q16wb_fixed
+/* 4957 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 4982
+/* 4962 */    MCD_OPC_Decode, 232, 19, 173, 2, // Opcode: VLD1q16wb_fixed
 /* 4967 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4982
-/* 4972 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 4982
-/* 4977 */    MCD_OPC_Decode, 150, 11, 196, 1, // Opcode: VLD1q16
-/* 4982 */    MCD_OPC_CheckPredicate, 21, 178, 6, 0, // Skip to: 6701
-/* 4987 */    MCD_OPC_Decode, 156, 11, 196, 1, // Opcode: VLD1q16wb_register
+/* 4972 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 4982
+/* 4977 */    MCD_OPC_Decode, 225, 19, 173, 2, // Opcode: VLD1q16
+/* 4982 */    MCD_OPC_CheckPredicate, 26, 178, 6, 0, // Skip to: 6701
+/* 4987 */    MCD_OPC_Decode, 233, 19, 173, 2, // Opcode: VLD1q16wb_register
 /* 4992 */    MCD_OPC_FilterValue, 1, 168, 6, 0, // Skip to: 6701
 /* 4997 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5000 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5015
-/* 5005 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5030
-/* 5010 */    MCD_OPC_Decode, 169, 11, 196, 1, // Opcode: VLD1q64wb_fixed
+/* 5005 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5030
+/* 5010 */    MCD_OPC_Decode, 250, 19, 173, 2, // Opcode: VLD1q64wb_fixed
 /* 5015 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5030
-/* 5020 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5030
-/* 5025 */    MCD_OPC_Decode, 164, 11, 196, 1, // Opcode: VLD1q64
-/* 5030 */    MCD_OPC_CheckPredicate, 21, 130, 6, 0, // Skip to: 6701
-/* 5035 */    MCD_OPC_Decode, 170, 11, 196, 1, // Opcode: VLD1q64wb_register
+/* 5020 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5030
+/* 5025 */    MCD_OPC_Decode, 243, 19, 173, 2, // Opcode: VLD1q64
+/* 5030 */    MCD_OPC_CheckPredicate, 26, 130, 6, 0, // Skip to: 6701
+/* 5035 */    MCD_OPC_Decode, 251, 19, 173, 2, // Opcode: VLD1q64wb_register
 /* 5040 */    MCD_OPC_FilterValue, 233, 3, 119, 6, 0, // Skip to: 6701
 /* 5046 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
 /* 5049 */    MCD_OPC_FilterValue, 0, 111, 6, 0, // Skip to: 6701
-/* 5054 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5071
+/* 5054 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 5071
 /* 5059 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5071
-/* 5066 */    MCD_OPC_Decode, 170, 12, 198, 1, // Opcode: VLD3LNq32
-/* 5071 */    MCD_OPC_CheckPredicate, 21, 89, 6, 0, // Skip to: 6701
-/* 5076 */    MCD_OPC_Decode, 173, 12, 198, 1, // Opcode: VLD3LNq32_UPD
+/* 5066 */    MCD_OPC_Decode, 134, 21, 175, 2, // Opcode: VLD3LNq32
+/* 5071 */    MCD_OPC_CheckPredicate, 26, 89, 6, 0, // Skip to: 6701
+/* 5076 */    MCD_OPC_Decode, 137, 21, 175, 2, // Opcode: VLD3LNq32_UPD
 /* 5081 */    MCD_OPC_FilterValue, 11, 183, 0, 0, // Skip to: 5269
 /* 5086 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 5089 */    MCD_OPC_FilterValue, 0, 85, 0, 0, // Skip to: 5179
@@ -6944,37 +11837,37 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5097 */    MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5138
 /* 5102 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 5105 */    MCD_OPC_FilterValue, 233, 3, 54, 6, 0, // Skip to: 6701
-/* 5111 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5128
+/* 5111 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 5128
 /* 5116 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5128
-/* 5123 */    MCD_OPC_Decode, 154, 20, 200, 1, // Opcode: VST4LNd32
-/* 5128 */    MCD_OPC_CheckPredicate, 21, 32, 6, 0, // Skip to: 6701
-/* 5133 */    MCD_OPC_Decode, 157, 20, 200, 1, // Opcode: VST4LNd32_UPD
+/* 5123 */    MCD_OPC_Decode, 159, 29, 177, 2, // Opcode: VST4LNd32
+/* 5128 */    MCD_OPC_CheckPredicate, 26, 32, 6, 0, // Skip to: 6701
+/* 5133 */    MCD_OPC_Decode, 162, 29, 177, 2, // Opcode: VST4LNd32_UPD
 /* 5138 */    MCD_OPC_FilterValue, 2, 22, 6, 0, // Skip to: 6701
 /* 5143 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 5146 */    MCD_OPC_FilterValue, 233, 3, 13, 6, 0, // Skip to: 6701
-/* 5152 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5169
+/* 5152 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 5169
 /* 5157 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5169
-/* 5164 */    MCD_OPC_Decode, 229, 12, 201, 1, // Opcode: VLD4LNd32
-/* 5169 */    MCD_OPC_CheckPredicate, 21, 247, 5, 0, // Skip to: 6701
-/* 5174 */    MCD_OPC_Decode, 232, 12, 201, 1, // Opcode: VLD4LNd32_UPD
+/* 5164 */    MCD_OPC_Decode, 196, 21, 178, 2, // Opcode: VLD4LNd32
+/* 5169 */    MCD_OPC_CheckPredicate, 26, 247, 5, 0, // Skip to: 6701
+/* 5174 */    MCD_OPC_Decode, 199, 21, 178, 2, // Opcode: VLD4LNd32_UPD
 /* 5179 */    MCD_OPC_FilterValue, 1, 237, 5, 0, // Skip to: 6701
 /* 5184 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5187 */    MCD_OPC_FilterValue, 0, 36, 0, 0, // Skip to: 5228
 /* 5192 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 5195 */    MCD_OPC_FilterValue, 233, 3, 220, 5, 0, // Skip to: 6701
-/* 5201 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5218
+/* 5201 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 5218
 /* 5206 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5218
-/* 5213 */    MCD_OPC_Decode, 166, 20, 200, 1, // Opcode: VST4LNq32
-/* 5218 */    MCD_OPC_CheckPredicate, 21, 198, 5, 0, // Skip to: 6701
-/* 5223 */    MCD_OPC_Decode, 169, 20, 200, 1, // Opcode: VST4LNq32_UPD
+/* 5213 */    MCD_OPC_Decode, 171, 29, 177, 2, // Opcode: VST4LNq32
+/* 5218 */    MCD_OPC_CheckPredicate, 26, 198, 5, 0, // Skip to: 6701
+/* 5223 */    MCD_OPC_Decode, 174, 29, 177, 2, // Opcode: VST4LNq32_UPD
 /* 5228 */    MCD_OPC_FilterValue, 2, 188, 5, 0, // Skip to: 6701
 /* 5233 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 5236 */    MCD_OPC_FilterValue, 233, 3, 179, 5, 0, // Skip to: 6701
-/* 5242 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 5259
+/* 5242 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 5259
 /* 5247 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 5259
-/* 5254 */    MCD_OPC_Decode, 241, 12, 201, 1, // Opcode: VLD4LNq32
-/* 5259 */    MCD_OPC_CheckPredicate, 21, 157, 5, 0, // Skip to: 6701
-/* 5264 */    MCD_OPC_Decode, 244, 12, 201, 1, // Opcode: VLD4LNq32_UPD
+/* 5254 */    MCD_OPC_Decode, 208, 21, 178, 2, // Opcode: VLD4LNq32
+/* 5259 */    MCD_OPC_CheckPredicate, 26, 157, 5, 0, // Skip to: 6701
+/* 5264 */    MCD_OPC_Decode, 211, 21, 178, 2, // Opcode: VLD4LNq32_UPD
 /* 5269 */    MCD_OPC_FilterValue, 12, 137, 1, 0, // Skip to: 5667
 /* 5274 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
 /* 5277 */    MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5342
@@ -6984,13 +11877,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5293 */    MCD_OPC_FilterValue, 233, 3, 122, 5, 0, // Skip to: 6701
 /* 5299 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5302 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5317
-/* 5307 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5332
-/* 5312 */    MCD_OPC_Decode, 207, 10, 203, 1, // Opcode: VLD1DUPd8wb_fixed
+/* 5307 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5332
+/* 5312 */    MCD_OPC_Decode, 142, 19, 180, 2, // Opcode: VLD1DUPd8wb_fixed
 /* 5317 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5332
-/* 5322 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5332
-/* 5327 */    MCD_OPC_Decode, 206, 10, 203, 1, // Opcode: VLD1DUPd8
-/* 5332 */    MCD_OPC_CheckPredicate, 21, 84, 5, 0, // Skip to: 6701
-/* 5337 */    MCD_OPC_Decode, 208, 10, 203, 1, // Opcode: VLD1DUPd8wb_register
+/* 5322 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5332
+/* 5327 */    MCD_OPC_Decode, 141, 19, 180, 2, // Opcode: VLD1DUPd8
+/* 5332 */    MCD_OPC_CheckPredicate, 26, 84, 5, 0, // Skip to: 6701
+/* 5337 */    MCD_OPC_Decode, 143, 19, 180, 2, // Opcode: VLD1DUPd8wb_register
 /* 5342 */    MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5407
 /* 5347 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5350 */    MCD_OPC_FilterValue, 2, 66, 5, 0, // Skip to: 6701
@@ -6998,13 +11891,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5358 */    MCD_OPC_FilterValue, 233, 3, 57, 5, 0, // Skip to: 6701
 /* 5364 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5367 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5382
-/* 5372 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5397
-/* 5377 */    MCD_OPC_Decode, 216, 10, 203, 1, // Opcode: VLD1DUPq8wb_fixed
+/* 5372 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5397
+/* 5377 */    MCD_OPC_Decode, 151, 19, 180, 2, // Opcode: VLD1DUPq8wb_fixed
 /* 5382 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5397
-/* 5387 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5397
-/* 5392 */    MCD_OPC_Decode, 215, 10, 203, 1, // Opcode: VLD1DUPq8
-/* 5397 */    MCD_OPC_CheckPredicate, 21, 19, 5, 0, // Skip to: 6701
-/* 5402 */    MCD_OPC_Decode, 217, 10, 203, 1, // Opcode: VLD1DUPq8wb_register
+/* 5387 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5397
+/* 5392 */    MCD_OPC_Decode, 150, 19, 180, 2, // Opcode: VLD1DUPq8
+/* 5397 */    MCD_OPC_CheckPredicate, 26, 19, 5, 0, // Skip to: 6701
+/* 5402 */    MCD_OPC_Decode, 152, 19, 180, 2, // Opcode: VLD1DUPq8wb_register
 /* 5407 */    MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5472
 /* 5412 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5415 */    MCD_OPC_FilterValue, 2, 1, 5, 0, // Skip to: 6701
@@ -7012,13 +11905,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5423 */    MCD_OPC_FilterValue, 233, 3, 248, 4, 0, // Skip to: 6701
 /* 5429 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5432 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5447
-/* 5437 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5462
-/* 5442 */    MCD_OPC_Decode, 201, 10, 203, 1, // Opcode: VLD1DUPd16wb_fixed
+/* 5437 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5462
+/* 5442 */    MCD_OPC_Decode, 136, 19, 180, 2, // Opcode: VLD1DUPd16wb_fixed
 /* 5447 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5462
-/* 5452 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5462
-/* 5457 */    MCD_OPC_Decode, 200, 10, 203, 1, // Opcode: VLD1DUPd16
-/* 5462 */    MCD_OPC_CheckPredicate, 21, 210, 4, 0, // Skip to: 6701
-/* 5467 */    MCD_OPC_Decode, 202, 10, 203, 1, // Opcode: VLD1DUPd16wb_register
+/* 5452 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5462
+/* 5457 */    MCD_OPC_Decode, 135, 19, 180, 2, // Opcode: VLD1DUPd16
+/* 5462 */    MCD_OPC_CheckPredicate, 26, 210, 4, 0, // Skip to: 6701
+/* 5467 */    MCD_OPC_Decode, 137, 19, 180, 2, // Opcode: VLD1DUPd16wb_register
 /* 5472 */    MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5537
 /* 5477 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5480 */    MCD_OPC_FilterValue, 2, 192, 4, 0, // Skip to: 6701
@@ -7026,13 +11919,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5488 */    MCD_OPC_FilterValue, 233, 3, 183, 4, 0, // Skip to: 6701
 /* 5494 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5497 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5512
-/* 5502 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5527
-/* 5507 */    MCD_OPC_Decode, 210, 10, 203, 1, // Opcode: VLD1DUPq16wb_fixed
+/* 5502 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5527
+/* 5507 */    MCD_OPC_Decode, 145, 19, 180, 2, // Opcode: VLD1DUPq16wb_fixed
 /* 5512 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5527
-/* 5517 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5527
-/* 5522 */    MCD_OPC_Decode, 209, 10, 203, 1, // Opcode: VLD1DUPq16
-/* 5527 */    MCD_OPC_CheckPredicate, 21, 145, 4, 0, // Skip to: 6701
-/* 5532 */    MCD_OPC_Decode, 211, 10, 203, 1, // Opcode: VLD1DUPq16wb_register
+/* 5517 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5527
+/* 5522 */    MCD_OPC_Decode, 144, 19, 180, 2, // Opcode: VLD1DUPq16
+/* 5527 */    MCD_OPC_CheckPredicate, 26, 145, 4, 0, // Skip to: 6701
+/* 5532 */    MCD_OPC_Decode, 146, 19, 180, 2, // Opcode: VLD1DUPq16wb_register
 /* 5537 */    MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 5602
 /* 5542 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5545 */    MCD_OPC_FilterValue, 2, 127, 4, 0, // Skip to: 6701
@@ -7040,13 +11933,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5553 */    MCD_OPC_FilterValue, 233, 3, 118, 4, 0, // Skip to: 6701
 /* 5559 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5562 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5577
-/* 5567 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5592
-/* 5572 */    MCD_OPC_Decode, 204, 10, 203, 1, // Opcode: VLD1DUPd32wb_fixed
+/* 5567 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5592
+/* 5572 */    MCD_OPC_Decode, 139, 19, 180, 2, // Opcode: VLD1DUPd32wb_fixed
 /* 5577 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5592
-/* 5582 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5592
-/* 5587 */    MCD_OPC_Decode, 203, 10, 203, 1, // Opcode: VLD1DUPd32
-/* 5592 */    MCD_OPC_CheckPredicate, 21, 80, 4, 0, // Skip to: 6701
-/* 5597 */    MCD_OPC_Decode, 205, 10, 203, 1, // Opcode: VLD1DUPd32wb_register
+/* 5582 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5592
+/* 5587 */    MCD_OPC_Decode, 138, 19, 180, 2, // Opcode: VLD1DUPd32
+/* 5592 */    MCD_OPC_CheckPredicate, 26, 80, 4, 0, // Skip to: 6701
+/* 5597 */    MCD_OPC_Decode, 140, 19, 180, 2, // Opcode: VLD1DUPd32wb_register
 /* 5602 */    MCD_OPC_FilterValue, 5, 70, 4, 0, // Skip to: 6701
 /* 5607 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5610 */    MCD_OPC_FilterValue, 2, 62, 4, 0, // Skip to: 6701
@@ -7054,13 +11947,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5618 */    MCD_OPC_FilterValue, 233, 3, 53, 4, 0, // Skip to: 6701
 /* 5624 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5627 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5642
-/* 5632 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5657
-/* 5637 */    MCD_OPC_Decode, 213, 10, 203, 1, // Opcode: VLD1DUPq32wb_fixed
+/* 5632 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5657
+/* 5637 */    MCD_OPC_Decode, 148, 19, 180, 2, // Opcode: VLD1DUPq32wb_fixed
 /* 5642 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5657
-/* 5647 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5657
-/* 5652 */    MCD_OPC_Decode, 212, 10, 203, 1, // Opcode: VLD1DUPq32
-/* 5657 */    MCD_OPC_CheckPredicate, 21, 15, 4, 0, // Skip to: 6701
-/* 5662 */    MCD_OPC_Decode, 214, 10, 203, 1, // Opcode: VLD1DUPq32wb_register
+/* 5647 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5657
+/* 5652 */    MCD_OPC_Decode, 147, 19, 180, 2, // Opcode: VLD1DUPq32
+/* 5657 */    MCD_OPC_CheckPredicate, 26, 15, 4, 0, // Skip to: 6701
+/* 5662 */    MCD_OPC_Decode, 149, 19, 180, 2, // Opcode: VLD1DUPq32wb_register
 /* 5667 */    MCD_OPC_FilterValue, 13, 137, 1, 0, // Skip to: 6065
 /* 5672 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
 /* 5675 */    MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 5740
@@ -7070,13 +11963,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5691 */    MCD_OPC_FilterValue, 233, 3, 236, 3, 0, // Skip to: 6701
 /* 5697 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5700 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5715
-/* 5705 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5730
-/* 5710 */    MCD_OPC_Decode, 191, 11, 204, 1, // Opcode: VLD2DUPd8wb_fixed
+/* 5705 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5730
+/* 5710 */    MCD_OPC_Decode, 146, 20, 181, 2, // Opcode: VLD2DUPd8wb_fixed
 /* 5715 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5730
-/* 5720 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5730
-/* 5725 */    MCD_OPC_Decode, 190, 11, 204, 1, // Opcode: VLD2DUPd8
-/* 5730 */    MCD_OPC_CheckPredicate, 21, 198, 3, 0, // Skip to: 6701
-/* 5735 */    MCD_OPC_Decode, 192, 11, 204, 1, // Opcode: VLD2DUPd8wb_register
+/* 5720 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5730
+/* 5725 */    MCD_OPC_Decode, 145, 20, 181, 2, // Opcode: VLD2DUPd8
+/* 5730 */    MCD_OPC_CheckPredicate, 26, 198, 3, 0, // Skip to: 6701
+/* 5735 */    MCD_OPC_Decode, 147, 20, 181, 2, // Opcode: VLD2DUPd8wb_register
 /* 5740 */    MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 5805
 /* 5745 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5748 */    MCD_OPC_FilterValue, 2, 180, 3, 0, // Skip to: 6701
@@ -7084,13 +11977,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5756 */    MCD_OPC_FilterValue, 233, 3, 171, 3, 0, // Skip to: 6701
 /* 5762 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5765 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5780
-/* 5770 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5795
-/* 5775 */    MCD_OPC_Decode, 194, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_fixed
+/* 5770 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5795
+/* 5775 */    MCD_OPC_Decode, 149, 20, 181, 2, // Opcode: VLD2DUPd8x2wb_fixed
 /* 5780 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5795
-/* 5785 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5795
-/* 5790 */    MCD_OPC_Decode, 193, 11, 204, 1, // Opcode: VLD2DUPd8x2
-/* 5795 */    MCD_OPC_CheckPredicate, 21, 133, 3, 0, // Skip to: 6701
-/* 5800 */    MCD_OPC_Decode, 195, 11, 204, 1, // Opcode: VLD2DUPd8x2wb_register
+/* 5785 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5795
+/* 5790 */    MCD_OPC_Decode, 148, 20, 181, 2, // Opcode: VLD2DUPd8x2
+/* 5795 */    MCD_OPC_CheckPredicate, 26, 133, 3, 0, // Skip to: 6701
+/* 5800 */    MCD_OPC_Decode, 150, 20, 181, 2, // Opcode: VLD2DUPd8x2wb_register
 /* 5805 */    MCD_OPC_FilterValue, 2, 60, 0, 0, // Skip to: 5870
 /* 5810 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5813 */    MCD_OPC_FilterValue, 2, 115, 3, 0, // Skip to: 6701
@@ -7098,13 +11991,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5821 */    MCD_OPC_FilterValue, 233, 3, 106, 3, 0, // Skip to: 6701
 /* 5827 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5830 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5845
-/* 5835 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5860
-/* 5840 */    MCD_OPC_Decode, 179, 11, 204, 1, // Opcode: VLD2DUPd16wb_fixed
+/* 5835 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5860
+/* 5840 */    MCD_OPC_Decode, 134, 20, 181, 2, // Opcode: VLD2DUPd16wb_fixed
 /* 5845 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5860
-/* 5850 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5860
-/* 5855 */    MCD_OPC_Decode, 178, 11, 204, 1, // Opcode: VLD2DUPd16
-/* 5860 */    MCD_OPC_CheckPredicate, 21, 68, 3, 0, // Skip to: 6701
-/* 5865 */    MCD_OPC_Decode, 180, 11, 204, 1, // Opcode: VLD2DUPd16wb_register
+/* 5850 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5860
+/* 5855 */    MCD_OPC_Decode, 133, 20, 181, 2, // Opcode: VLD2DUPd16
+/* 5860 */    MCD_OPC_CheckPredicate, 26, 68, 3, 0, // Skip to: 6701
+/* 5865 */    MCD_OPC_Decode, 135, 20, 181, 2, // Opcode: VLD2DUPd16wb_register
 /* 5870 */    MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 5935
 /* 5875 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5878 */    MCD_OPC_FilterValue, 2, 50, 3, 0, // Skip to: 6701
@@ -7112,13 +12005,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5886 */    MCD_OPC_FilterValue, 233, 3, 41, 3, 0, // Skip to: 6701
 /* 5892 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5895 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5910
-/* 5900 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5925
-/* 5905 */    MCD_OPC_Decode, 182, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_fixed
+/* 5900 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5925
+/* 5905 */    MCD_OPC_Decode, 137, 20, 181, 2, // Opcode: VLD2DUPd16x2wb_fixed
 /* 5910 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5925
-/* 5915 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5925
-/* 5920 */    MCD_OPC_Decode, 181, 11, 204, 1, // Opcode: VLD2DUPd16x2
-/* 5925 */    MCD_OPC_CheckPredicate, 21, 3, 3, 0, // Skip to: 6701
-/* 5930 */    MCD_OPC_Decode, 183, 11, 204, 1, // Opcode: VLD2DUPd16x2wb_register
+/* 5915 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5925
+/* 5920 */    MCD_OPC_Decode, 136, 20, 181, 2, // Opcode: VLD2DUPd16x2
+/* 5925 */    MCD_OPC_CheckPredicate, 26, 3, 3, 0, // Skip to: 6701
+/* 5930 */    MCD_OPC_Decode, 138, 20, 181, 2, // Opcode: VLD2DUPd16x2wb_register
 /* 5935 */    MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 6000
 /* 5940 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 5943 */    MCD_OPC_FilterValue, 2, 241, 2, 0, // Skip to: 6701
@@ -7126,13 +12019,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 5951 */    MCD_OPC_FilterValue, 233, 3, 232, 2, 0, // Skip to: 6701
 /* 5957 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 5960 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 5975
-/* 5965 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 5990
-/* 5970 */    MCD_OPC_Decode, 185, 11, 204, 1, // Opcode: VLD2DUPd32wb_fixed
+/* 5965 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 5990
+/* 5970 */    MCD_OPC_Decode, 140, 20, 181, 2, // Opcode: VLD2DUPd32wb_fixed
 /* 5975 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 5990
-/* 5980 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 5990
-/* 5985 */    MCD_OPC_Decode, 184, 11, 204, 1, // Opcode: VLD2DUPd32
-/* 5990 */    MCD_OPC_CheckPredicate, 21, 194, 2, 0, // Skip to: 6701
-/* 5995 */    MCD_OPC_Decode, 186, 11, 204, 1, // Opcode: VLD2DUPd32wb_register
+/* 5980 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 5990
+/* 5985 */    MCD_OPC_Decode, 139, 20, 181, 2, // Opcode: VLD2DUPd32
+/* 5990 */    MCD_OPC_CheckPredicate, 26, 194, 2, 0, // Skip to: 6701
+/* 5995 */    MCD_OPC_Decode, 141, 20, 181, 2, // Opcode: VLD2DUPd32wb_register
 /* 6000 */    MCD_OPC_FilterValue, 5, 184, 2, 0, // Skip to: 6701
 /* 6005 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6008 */    MCD_OPC_FilterValue, 2, 176, 2, 0, // Skip to: 6701
@@ -7140,13 +12033,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 6016 */    MCD_OPC_FilterValue, 233, 3, 167, 2, 0, // Skip to: 6701
 /* 6022 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
 /* 6025 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 6040
-/* 6030 */    MCD_OPC_CheckPredicate, 21, 20, 0, 0, // Skip to: 6055
-/* 6035 */    MCD_OPC_Decode, 188, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_fixed
+/* 6030 */    MCD_OPC_CheckPredicate, 26, 20, 0, 0, // Skip to: 6055
+/* 6035 */    MCD_OPC_Decode, 143, 20, 181, 2, // Opcode: VLD2DUPd32x2wb_fixed
 /* 6040 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 6055
-/* 6045 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6055
-/* 6050 */    MCD_OPC_Decode, 187, 11, 204, 1, // Opcode: VLD2DUPd32x2
-/* 6055 */    MCD_OPC_CheckPredicate, 21, 129, 2, 0, // Skip to: 6701
-/* 6060 */    MCD_OPC_Decode, 189, 11, 204, 1, // Opcode: VLD2DUPd32x2wb_register
+/* 6045 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 6055
+/* 6050 */    MCD_OPC_Decode, 142, 20, 181, 2, // Opcode: VLD2DUPd32x2
+/* 6055 */    MCD_OPC_CheckPredicate, 26, 129, 2, 0, // Skip to: 6701
+/* 6060 */    MCD_OPC_Decode, 144, 20, 181, 2, // Opcode: VLD2DUPd32x2wb_register
 /* 6065 */    MCD_OPC_FilterValue, 14, 41, 1, 0, // Skip to: 6367
 /* 6070 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
 /* 6073 */    MCD_OPC_FilterValue, 0, 44, 0, 0, // Skip to: 6122
@@ -7154,61 +12047,61 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 6081 */    MCD_OPC_FilterValue, 2, 103, 2, 0, // Skip to: 6701
 /* 6086 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6089 */    MCD_OPC_FilterValue, 233, 3, 94, 2, 0, // Skip to: 6701
-/* 6095 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6112
+/* 6095 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6112
 /* 6100 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6112
-/* 6107 */    MCD_OPC_Decode, 138, 12, 205, 1, // Opcode: VLD3DUPd8
-/* 6112 */    MCD_OPC_CheckPredicate, 21, 72, 2, 0, // Skip to: 6701
-/* 6117 */    MCD_OPC_Decode, 141, 12, 205, 1, // Opcode: VLD3DUPd8_UPD
+/* 6107 */    MCD_OPC_Decode, 227, 20, 182, 2, // Opcode: VLD3DUPd8
+/* 6112 */    MCD_OPC_CheckPredicate, 26, 72, 2, 0, // Skip to: 6701
+/* 6117 */    MCD_OPC_Decode, 230, 20, 182, 2, // Opcode: VLD3DUPd8_UPD
 /* 6122 */    MCD_OPC_FilterValue, 2, 44, 0, 0, // Skip to: 6171
 /* 6127 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6130 */    MCD_OPC_FilterValue, 2, 54, 2, 0, // Skip to: 6701
 /* 6135 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6138 */    MCD_OPC_FilterValue, 233, 3, 45, 2, 0, // Skip to: 6701
-/* 6144 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6161
+/* 6144 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6161
 /* 6149 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6161
-/* 6156 */    MCD_OPC_Decode, 150, 12, 205, 1, // Opcode: VLD3DUPq8
-/* 6161 */    MCD_OPC_CheckPredicate, 21, 23, 2, 0, // Skip to: 6701
-/* 6166 */    MCD_OPC_Decode, 153, 12, 205, 1, // Opcode: VLD3DUPq8_UPD
+/* 6156 */    MCD_OPC_Decode, 241, 20, 182, 2, // Opcode: VLD3DUPq8
+/* 6161 */    MCD_OPC_CheckPredicate, 26, 23, 2, 0, // Skip to: 6701
+/* 6166 */    MCD_OPC_Decode, 245, 20, 182, 2, // Opcode: VLD3DUPq8_UPD
 /* 6171 */    MCD_OPC_FilterValue, 4, 44, 0, 0, // Skip to: 6220
 /* 6176 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6179 */    MCD_OPC_FilterValue, 2, 5, 2, 0, // Skip to: 6701
 /* 6184 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6187 */    MCD_OPC_FilterValue, 233, 3, 252, 1, 0, // Skip to: 6701
-/* 6193 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6210
+/* 6193 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6210
 /* 6198 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6210
-/* 6205 */    MCD_OPC_Decode, 130, 12, 205, 1, // Opcode: VLD3DUPd16
-/* 6210 */    MCD_OPC_CheckPredicate, 21, 230, 1, 0, // Skip to: 6701
-/* 6215 */    MCD_OPC_Decode, 133, 12, 205, 1, // Opcode: VLD3DUPd16_UPD
+/* 6205 */    MCD_OPC_Decode, 219, 20, 182, 2, // Opcode: VLD3DUPd16
+/* 6210 */    MCD_OPC_CheckPredicate, 26, 230, 1, 0, // Skip to: 6701
+/* 6215 */    MCD_OPC_Decode, 222, 20, 182, 2, // Opcode: VLD3DUPd16_UPD
 /* 6220 */    MCD_OPC_FilterValue, 6, 44, 0, 0, // Skip to: 6269
 /* 6225 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6228 */    MCD_OPC_FilterValue, 2, 212, 1, 0, // Skip to: 6701
 /* 6233 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6236 */    MCD_OPC_FilterValue, 233, 3, 203, 1, 0, // Skip to: 6701
-/* 6242 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6259
+/* 6242 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6259
 /* 6247 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6259
-/* 6254 */    MCD_OPC_Decode, 142, 12, 205, 1, // Opcode: VLD3DUPq16
-/* 6259 */    MCD_OPC_CheckPredicate, 21, 181, 1, 0, // Skip to: 6701
-/* 6264 */    MCD_OPC_Decode, 145, 12, 205, 1, // Opcode: VLD3DUPq16_UPD
+/* 6254 */    MCD_OPC_Decode, 231, 20, 182, 2, // Opcode: VLD3DUPq16
+/* 6259 */    MCD_OPC_CheckPredicate, 26, 181, 1, 0, // Skip to: 6701
+/* 6264 */    MCD_OPC_Decode, 235, 20, 182, 2, // Opcode: VLD3DUPq16_UPD
 /* 6269 */    MCD_OPC_FilterValue, 8, 44, 0, 0, // Skip to: 6318
 /* 6274 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6277 */    MCD_OPC_FilterValue, 2, 163, 1, 0, // Skip to: 6701
 /* 6282 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6285 */    MCD_OPC_FilterValue, 233, 3, 154, 1, 0, // Skip to: 6701
-/* 6291 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6308
+/* 6291 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6308
 /* 6296 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6308
-/* 6303 */    MCD_OPC_Decode, 134, 12, 205, 1, // Opcode: VLD3DUPd32
-/* 6308 */    MCD_OPC_CheckPredicate, 21, 132, 1, 0, // Skip to: 6701
-/* 6313 */    MCD_OPC_Decode, 137, 12, 205, 1, // Opcode: VLD3DUPd32_UPD
+/* 6303 */    MCD_OPC_Decode, 223, 20, 182, 2, // Opcode: VLD3DUPd32
+/* 6308 */    MCD_OPC_CheckPredicate, 26, 132, 1, 0, // Skip to: 6701
+/* 6313 */    MCD_OPC_Decode, 226, 20, 182, 2, // Opcode: VLD3DUPd32_UPD
 /* 6318 */    MCD_OPC_FilterValue, 10, 122, 1, 0, // Skip to: 6701
 /* 6323 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6326 */    MCD_OPC_FilterValue, 2, 114, 1, 0, // Skip to: 6701
 /* 6331 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6334 */    MCD_OPC_FilterValue, 233, 3, 105, 1, 0, // Skip to: 6701
-/* 6340 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6357
+/* 6340 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6357
 /* 6345 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6357
-/* 6352 */    MCD_OPC_Decode, 146, 12, 205, 1, // Opcode: VLD3DUPq32
-/* 6357 */    MCD_OPC_CheckPredicate, 21, 83, 1, 0, // Skip to: 6701
-/* 6362 */    MCD_OPC_Decode, 149, 12, 205, 1, // Opcode: VLD3DUPq32_UPD
+/* 6352 */    MCD_OPC_Decode, 236, 20, 182, 2, // Opcode: VLD3DUPq32
+/* 6357 */    MCD_OPC_CheckPredicate, 26, 83, 1, 0, // Skip to: 6701
+/* 6362 */    MCD_OPC_Decode, 240, 20, 182, 2, // Opcode: VLD3DUPq32_UPD
 /* 6367 */    MCD_OPC_FilterValue, 15, 73, 1, 0, // Skip to: 6701
 /* 6372 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
 /* 6375 */    MCD_OPC_FilterValue, 0, 158, 0, 0, // Skip to: 6538
@@ -7220,31 +12113,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 6399 */    MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 6701
 /* 6404 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6407 */    MCD_OPC_FilterValue, 233, 3, 32, 1, 0, // Skip to: 6701
-/* 6413 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6430
+/* 6413 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6430
 /* 6418 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6430
-/* 6425 */    MCD_OPC_Decode, 209, 12, 206, 1, // Opcode: VLD4DUPd8
-/* 6430 */    MCD_OPC_CheckPredicate, 21, 10, 1, 0, // Skip to: 6701
-/* 6435 */    MCD_OPC_Decode, 212, 12, 206, 1, // Opcode: VLD4DUPd8_UPD
+/* 6425 */    MCD_OPC_Decode, 173, 21, 183, 2, // Opcode: VLD4DUPd8
+/* 6430 */    MCD_OPC_CheckPredicate, 26, 10, 1, 0, // Skip to: 6701
+/* 6435 */    MCD_OPC_Decode, 176, 21, 183, 2, // Opcode: VLD4DUPd8_UPD
 /* 6440 */    MCD_OPC_FilterValue, 1, 0, 1, 0, // Skip to: 6701
 /* 6445 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6448 */    MCD_OPC_FilterValue, 2, 248, 0, 0, // Skip to: 6701
 /* 6453 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6456 */    MCD_OPC_FilterValue, 233, 3, 239, 0, 0, // Skip to: 6701
-/* 6462 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6479
+/* 6462 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6479
 /* 6467 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6479
-/* 6474 */    MCD_OPC_Decode, 201, 12, 206, 1, // Opcode: VLD4DUPd16
-/* 6479 */    MCD_OPC_CheckPredicate, 21, 217, 0, 0, // Skip to: 6701
-/* 6484 */    MCD_OPC_Decode, 204, 12, 206, 1, // Opcode: VLD4DUPd16_UPD
+/* 6474 */    MCD_OPC_Decode, 165, 21, 183, 2, // Opcode: VLD4DUPd16
+/* 6479 */    MCD_OPC_CheckPredicate, 26, 217, 0, 0, // Skip to: 6701
+/* 6484 */    MCD_OPC_Decode, 168, 21, 183, 2, // Opcode: VLD4DUPd16_UPD
 /* 6489 */    MCD_OPC_FilterValue, 1, 207, 0, 0, // Skip to: 6701
 /* 6494 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6497 */    MCD_OPC_FilterValue, 2, 199, 0, 0, // Skip to: 6701
 /* 6502 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6505 */    MCD_OPC_FilterValue, 233, 3, 190, 0, 0, // Skip to: 6701
-/* 6511 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6528
+/* 6511 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6528
 /* 6516 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6528
-/* 6523 */    MCD_OPC_Decode, 205, 12, 206, 1, // Opcode: VLD4DUPd32
-/* 6528 */    MCD_OPC_CheckPredicate, 21, 168, 0, 0, // Skip to: 6701
-/* 6533 */    MCD_OPC_Decode, 208, 12, 206, 1, // Opcode: VLD4DUPd32_UPD
+/* 6523 */    MCD_OPC_Decode, 169, 21, 183, 2, // Opcode: VLD4DUPd32
+/* 6528 */    MCD_OPC_CheckPredicate, 26, 168, 0, 0, // Skip to: 6701
+/* 6533 */    MCD_OPC_Decode, 172, 21, 183, 2, // Opcode: VLD4DUPd32_UPD
 /* 6538 */    MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 6701
 /* 6543 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 6546 */    MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 6652
@@ -7254,31 +12147,31 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 /* 6562 */    MCD_OPC_FilterValue, 2, 134, 0, 0, // Skip to: 6701
 /* 6567 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6570 */    MCD_OPC_FilterValue, 233, 3, 125, 0, 0, // Skip to: 6701
-/* 6576 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6593
+/* 6576 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6593
 /* 6581 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6593
-/* 6588 */    MCD_OPC_Decode, 221, 12, 206, 1, // Opcode: VLD4DUPq8
-/* 6593 */    MCD_OPC_CheckPredicate, 21, 103, 0, 0, // Skip to: 6701
-/* 6598 */    MCD_OPC_Decode, 224, 12, 206, 1, // Opcode: VLD4DUPq8_UPD
+/* 6588 */    MCD_OPC_Decode, 187, 21, 183, 2, // Opcode: VLD4DUPq8
+/* 6593 */    MCD_OPC_CheckPredicate, 26, 103, 0, 0, // Skip to: 6701
+/* 6598 */    MCD_OPC_Decode, 191, 21, 183, 2, // Opcode: VLD4DUPq8_UPD
 /* 6603 */    MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 6701
 /* 6608 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6611 */    MCD_OPC_FilterValue, 2, 85, 0, 0, // Skip to: 6701
 /* 6616 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6619 */    MCD_OPC_FilterValue, 233, 3, 76, 0, 0, // Skip to: 6701
-/* 6625 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6642
+/* 6625 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6642
 /* 6630 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6642
-/* 6637 */    MCD_OPC_Decode, 213, 12, 206, 1, // Opcode: VLD4DUPq16
-/* 6642 */    MCD_OPC_CheckPredicate, 21, 54, 0, 0, // Skip to: 6701
-/* 6647 */    MCD_OPC_Decode, 216, 12, 206, 1, // Opcode: VLD4DUPq16_UPD
+/* 6637 */    MCD_OPC_Decode, 177, 21, 183, 2, // Opcode: VLD4DUPq16
+/* 6642 */    MCD_OPC_CheckPredicate, 26, 54, 0, 0, // Skip to: 6701
+/* 6647 */    MCD_OPC_Decode, 181, 21, 183, 2, // Opcode: VLD4DUPq16_UPD
 /* 6652 */    MCD_OPC_FilterValue, 1, 44, 0, 0, // Skip to: 6701
 /* 6657 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
 /* 6660 */    MCD_OPC_FilterValue, 2, 36, 0, 0, // Skip to: 6701
 /* 6665 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
 /* 6668 */    MCD_OPC_FilterValue, 233, 3, 27, 0, 0, // Skip to: 6701
-/* 6674 */    MCD_OPC_CheckPredicate, 21, 12, 0, 0, // Skip to: 6691
+/* 6674 */    MCD_OPC_CheckPredicate, 26, 12, 0, 0, // Skip to: 6691
 /* 6679 */    MCD_OPC_CheckField, 0, 4, 15, 5, 0, 0, // Skip to: 6691
-/* 6686 */    MCD_OPC_Decode, 217, 12, 206, 1, // Opcode: VLD4DUPq32
-/* 6691 */    MCD_OPC_CheckPredicate, 21, 5, 0, 0, // Skip to: 6701
-/* 6696 */    MCD_OPC_Decode, 220, 12, 206, 1, // Opcode: VLD4DUPq32_UPD
+/* 6686 */    MCD_OPC_Decode, 182, 21, 183, 2, // Opcode: VLD4DUPq32
+/* 6691 */    MCD_OPC_CheckPredicate, 26, 5, 0, 0, // Skip to: 6701
+/* 6696 */    MCD_OPC_Decode, 186, 21, 183, 2, // Opcode: VLD4DUPq32_UPD
 /* 6701 */    MCD_OPC_Fail,
   0
 };
@@ -7286,13 +12179,13 @@ static const uint8_t DecoderTableNEONLoadStore32[] = {
 static const uint8_t DecoderTableThumb16[] = {
 /* 0 */       MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
 /* 3 */       MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25
-/* 8 */       MCD_OPC_CheckPredicate, 28, 181, 4, 0, // Skip to: 1218
+/* 8 */       MCD_OPC_CheckPredicate, 35, 181, 4, 0, // Skip to: 1218
 /* 13 */      MCD_OPC_CheckField, 6, 6, 0, 174, 4, 0, // Skip to: 1218
-/* 20 */      MCD_OPC_Decode, 236, 24, 207, 1, // Opcode: tMOVSr
+/* 20 */      MCD_OPC_Decode, 165, 34, 184, 2, // Opcode: tMOVSr
 /* 25 */      MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 47
-/* 30 */      MCD_OPC_CheckPredicate, 28, 159, 4, 0, // Skip to: 1218
+/* 30 */      MCD_OPC_CheckPredicate, 35, 159, 4, 0, // Skip to: 1218
 /* 35 */      MCD_OPC_CheckField, 11, 1, 1, 152, 4, 0, // Skip to: 1218
-/* 42 */      MCD_OPC_Decode, 212, 24, 208, 1, // Opcode: tCMPi8
+/* 42 */      MCD_OPC_Decode, 141, 34, 185, 2, // Opcode: tCMPi8
 /* 47 */      MCD_OPC_FilterValue, 4, 3, 1, 0, // Skip to: 311
 /* 52 */      MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 55 */      MCD_OPC_FilterValue, 0, 236, 0, 0, // Skip to: 296
@@ -7300,119 +12193,119 @@ static const uint8_t DecoderTableThumb16[] = {
 /* 63 */      MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 116
 /* 68 */      MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 71 */      MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 86
-/* 76 */      MCD_OPC_CheckPredicate, 28, 113, 4, 0, // Skip to: 1218
-/* 81 */      MCD_OPC_Decode, 140, 25, 207, 1, // Opcode: tTST
+/* 76 */      MCD_OPC_CheckPredicate, 35, 113, 4, 0, // Skip to: 1218
+/* 81 */      MCD_OPC_Decode, 197, 34, 184, 2, // Opcode: tTST
 /* 86 */      MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101
-/* 91 */      MCD_OPC_CheckPredicate, 28, 98, 4, 0, // Skip to: 1218
-/* 96 */      MCD_OPC_Decode, 213, 24, 207, 1, // Opcode: tCMPr
+/* 91 */      MCD_OPC_CheckPredicate, 35, 98, 4, 0, // Skip to: 1218
+/* 96 */      MCD_OPC_Decode, 142, 34, 184, 2, // Opcode: tCMPr
 /* 101 */     MCD_OPC_FilterValue, 3, 88, 4, 0, // Skip to: 1218
-/* 106 */     MCD_OPC_CheckPredicate, 28, 83, 4, 0, // Skip to: 1218
-/* 111 */     MCD_OPC_Decode, 210, 24, 207, 1, // Opcode: tCMNz
+/* 106 */     MCD_OPC_CheckPredicate, 35, 83, 4, 0, // Skip to: 1218
+/* 111 */     MCD_OPC_Decode, 139, 34, 184, 2, // Opcode: tCMNz
 /* 116 */     MCD_OPC_FilterValue, 4, 51, 0, 0, // Skip to: 172
-/* 121 */     MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 138
+/* 121 */     MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 138
 /* 126 */     MCD_OPC_CheckField, 3, 4, 13, 5, 0, 0, // Skip to: 138
-/* 133 */     MCD_OPC_Decode, 189, 24, 209, 1, // Opcode: tADDrSP
-/* 138 */     MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 162
+/* 133 */     MCD_OPC_Decode, 246, 33, 186, 2, // Opcode: tADDrSP
+/* 138 */     MCD_OPC_CheckPredicate, 35, 19, 0, 0, // Skip to: 162
 /* 143 */     MCD_OPC_CheckField, 7, 1, 1, 12, 0, 0, // Skip to: 162
 /* 150 */     MCD_OPC_CheckField, 0, 3, 5, 5, 0, 0, // Skip to: 162
-/* 157 */     MCD_OPC_Decode, 193, 24, 209, 1, // Opcode: tADDspr
-/* 162 */     MCD_OPC_CheckPredicate, 28, 27, 4, 0, // Skip to: 1218
-/* 167 */     MCD_OPC_Decode, 186, 24, 210, 1, // Opcode: tADDhirr
+/* 157 */     MCD_OPC_Decode, 250, 33, 186, 2, // Opcode: tADDspr
+/* 162 */     MCD_OPC_CheckPredicate, 35, 27, 4, 0, // Skip to: 1218
+/* 167 */     MCD_OPC_Decode, 243, 33, 187, 2, // Opcode: tADDhirr
 /* 172 */     MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 187
-/* 177 */     MCD_OPC_CheckPredicate, 28, 12, 4, 0, // Skip to: 1218
-/* 182 */     MCD_OPC_Decode, 211, 24, 211, 1, // Opcode: tCMPhir
+/* 177 */     MCD_OPC_CheckPredicate, 35, 12, 4, 0, // Skip to: 1218
+/* 182 */     MCD_OPC_Decode, 140, 34, 188, 2, // Opcode: tCMPhir
 /* 187 */     MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 202
-/* 192 */     MCD_OPC_CheckPredicate, 28, 253, 3, 0, // Skip to: 1218
-/* 197 */     MCD_OPC_Decode, 238, 24, 211, 1, // Opcode: tMOVr
+/* 192 */     MCD_OPC_CheckPredicate, 35, 253, 3, 0, // Skip to: 1218
+/* 197 */     MCD_OPC_Decode, 167, 34, 188, 2, // Opcode: tMOVr
 /* 202 */     MCD_OPC_FilterValue, 7, 243, 3, 0, // Skip to: 1218
 /* 207 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
 /* 210 */     MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 248
-/* 215 */     MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 235
+/* 215 */     MCD_OPC_CheckPredicate, 36, 15, 0, 0, // Skip to: 235
 /* 220 */     MCD_OPC_CheckField, 2, 1, 1, 8, 0, 0, // Skip to: 235
 /* 227 */     MCD_OPC_SoftFail, 3, 0,
-/* 230 */     MCD_OPC_Decode, 206, 24, 212, 1, // Opcode: tBXNS
-/* 235 */     MCD_OPC_CheckPredicate, 28, 210, 3, 0, // Skip to: 1218
+/* 230 */     MCD_OPC_Decode, 135, 34, 189, 2, // Opcode: tBXNS
+/* 235 */     MCD_OPC_CheckPredicate, 35, 210, 3, 0, // Skip to: 1218
 /* 240 */     MCD_OPC_SoftFail, 7, 0,
-/* 243 */     MCD_OPC_Decode, 205, 24, 212, 1, // Opcode: tBX
+/* 243 */     MCD_OPC_Decode, 134, 34, 189, 2, // Opcode: tBX
 /* 248 */     MCD_OPC_FilterValue, 1, 197, 3, 0, // Skip to: 1218
 /* 253 */     MCD_OPC_ExtractField, 2, 1,  // Inst{2} ...
 /* 256 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 278
-/* 261 */     MCD_OPC_CheckPredicate, 30, 184, 3, 0, // Skip to: 1218
+/* 261 */     MCD_OPC_CheckPredicate, 37, 184, 3, 0, // Skip to: 1218
 /* 266 */     MCD_OPC_CheckField, 0, 2, 0, 177, 3, 0, // Skip to: 1218
-/* 273 */     MCD_OPC_Decode, 204, 24, 212, 1, // Opcode: tBLXr
+/* 273 */     MCD_OPC_Decode, 133, 34, 189, 2, // Opcode: tBLXr
 /* 278 */     MCD_OPC_FilterValue, 1, 167, 3, 0, // Skip to: 1218
-/* 283 */     MCD_OPC_CheckPredicate, 29, 162, 3, 0, // Skip to: 1218
+/* 283 */     MCD_OPC_CheckPredicate, 36, 162, 3, 0, // Skip to: 1218
 /* 288 */     MCD_OPC_SoftFail, 3, 0,
-/* 291 */     MCD_OPC_Decode, 202, 24, 213, 1, // Opcode: tBLXNSr
+/* 291 */     MCD_OPC_Decode, 131, 34, 190, 2, // Opcode: tBLXNSr
 /* 296 */     MCD_OPC_FilterValue, 1, 149, 3, 0, // Skip to: 1218
-/* 301 */     MCD_OPC_CheckPredicate, 28, 144, 3, 0, // Skip to: 1218
-/* 306 */     MCD_OPC_Decode, 229, 24, 214, 1, // Opcode: tLDRpci
+/* 301 */     MCD_OPC_CheckPredicate, 35, 144, 3, 0, // Skip to: 1218
+/* 306 */     MCD_OPC_Decode, 158, 34, 191, 2, // Opcode: tLDRpci
 /* 311 */     MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 439
 /* 316 */     MCD_OPC_ExtractField, 9, 3,  // Inst{11-9} ...
 /* 319 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 334
-/* 324 */     MCD_OPC_CheckPredicate, 28, 121, 3, 0, // Skip to: 1218
-/* 329 */     MCD_OPC_Decode, 130, 25, 215, 1, // Opcode: tSTRr
+/* 324 */     MCD_OPC_CheckPredicate, 35, 121, 3, 0, // Skip to: 1218
+/* 329 */     MCD_OPC_Decode, 187, 34, 192, 2, // Opcode: tSTRr
 /* 334 */     MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 349
-/* 339 */     MCD_OPC_CheckPredicate, 28, 106, 3, 0, // Skip to: 1218
-/* 344 */     MCD_OPC_Decode, 128, 25, 215, 1, // Opcode: tSTRHr
+/* 339 */     MCD_OPC_CheckPredicate, 35, 106, 3, 0, // Skip to: 1218
+/* 344 */     MCD_OPC_Decode, 185, 34, 192, 2, // Opcode: tSTRHr
 /* 349 */     MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 364
-/* 354 */     MCD_OPC_CheckPredicate, 28, 91, 3, 0, // Skip to: 1218
-/* 359 */     MCD_OPC_Decode, 254, 24, 215, 1, // Opcode: tSTRBr
+/* 354 */     MCD_OPC_CheckPredicate, 35, 91, 3, 0, // Skip to: 1218
+/* 359 */     MCD_OPC_Decode, 183, 34, 192, 2, // Opcode: tSTRBr
 /* 364 */     MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 379
-/* 369 */     MCD_OPC_CheckPredicate, 28, 76, 3, 0, // Skip to: 1218
-/* 374 */     MCD_OPC_Decode, 226, 24, 215, 1, // Opcode: tLDRSB
+/* 369 */     MCD_OPC_CheckPredicate, 35, 76, 3, 0, // Skip to: 1218
+/* 374 */     MCD_OPC_Decode, 155, 34, 192, 2, // Opcode: tLDRSB
 /* 379 */     MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 394
-/* 384 */     MCD_OPC_CheckPredicate, 28, 61, 3, 0, // Skip to: 1218
-/* 389 */     MCD_OPC_Decode, 230, 24, 215, 1, // Opcode: tLDRr
+/* 384 */     MCD_OPC_CheckPredicate, 35, 61, 3, 0, // Skip to: 1218
+/* 389 */     MCD_OPC_Decode, 159, 34, 192, 2, // Opcode: tLDRr
 /* 394 */     MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 409
-/* 399 */     MCD_OPC_CheckPredicate, 28, 46, 3, 0, // Skip to: 1218
-/* 404 */     MCD_OPC_Decode, 225, 24, 215, 1, // Opcode: tLDRHr
+/* 399 */     MCD_OPC_CheckPredicate, 35, 46, 3, 0, // Skip to: 1218
+/* 404 */     MCD_OPC_Decode, 154, 34, 192, 2, // Opcode: tLDRHr
 /* 409 */     MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 424
-/* 414 */     MCD_OPC_CheckPredicate, 28, 31, 3, 0, // Skip to: 1218
-/* 419 */     MCD_OPC_Decode, 223, 24, 215, 1, // Opcode: tLDRBr
+/* 414 */     MCD_OPC_CheckPredicate, 35, 31, 3, 0, // Skip to: 1218
+/* 419 */     MCD_OPC_Decode, 152, 34, 192, 2, // Opcode: tLDRBr
 /* 424 */     MCD_OPC_FilterValue, 7, 21, 3, 0, // Skip to: 1218
-/* 429 */     MCD_OPC_CheckPredicate, 28, 16, 3, 0, // Skip to: 1218
-/* 434 */     MCD_OPC_Decode, 227, 24, 215, 1, // Opcode: tLDRSH
+/* 429 */     MCD_OPC_CheckPredicate, 35, 16, 3, 0, // Skip to: 1218
+/* 434 */     MCD_OPC_Decode, 156, 34, 192, 2, // Opcode: tLDRSH
 /* 439 */     MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 477
 /* 444 */     MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 447 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 462
-/* 452 */     MCD_OPC_CheckPredicate, 28, 249, 2, 0, // Skip to: 1218
-/* 457 */     MCD_OPC_Decode, 129, 25, 216, 1, // Opcode: tSTRi
+/* 452 */     MCD_OPC_CheckPredicate, 35, 249, 2, 0, // Skip to: 1218
+/* 457 */     MCD_OPC_Decode, 186, 34, 193, 2, // Opcode: tSTRi
 /* 462 */     MCD_OPC_FilterValue, 1, 239, 2, 0, // Skip to: 1218
-/* 467 */     MCD_OPC_CheckPredicate, 28, 234, 2, 0, // Skip to: 1218
-/* 472 */     MCD_OPC_Decode, 228, 24, 216, 1, // Opcode: tLDRi
+/* 467 */     MCD_OPC_CheckPredicate, 35, 234, 2, 0, // Skip to: 1218
+/* 472 */     MCD_OPC_Decode, 157, 34, 193, 2, // Opcode: tLDRi
 /* 477 */     MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 515
 /* 482 */     MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 485 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 500
-/* 490 */     MCD_OPC_CheckPredicate, 28, 211, 2, 0, // Skip to: 1218
-/* 495 */     MCD_OPC_Decode, 253, 24, 216, 1, // Opcode: tSTRBi
+/* 490 */     MCD_OPC_CheckPredicate, 35, 211, 2, 0, // Skip to: 1218
+/* 495 */     MCD_OPC_Decode, 182, 34, 193, 2, // Opcode: tSTRBi
 /* 500 */     MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 1218
-/* 505 */     MCD_OPC_CheckPredicate, 28, 196, 2, 0, // Skip to: 1218
-/* 510 */     MCD_OPC_Decode, 222, 24, 216, 1, // Opcode: tLDRBi
+/* 505 */     MCD_OPC_CheckPredicate, 35, 196, 2, 0, // Skip to: 1218
+/* 510 */     MCD_OPC_Decode, 151, 34, 193, 2, // Opcode: tLDRBi
 /* 515 */     MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 553
 /* 520 */     MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 523 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 538
-/* 528 */     MCD_OPC_CheckPredicate, 28, 173, 2, 0, // Skip to: 1218
-/* 533 */     MCD_OPC_Decode, 255, 24, 216, 1, // Opcode: tSTRHi
+/* 528 */     MCD_OPC_CheckPredicate, 35, 173, 2, 0, // Skip to: 1218
+/* 533 */     MCD_OPC_Decode, 184, 34, 193, 2, // Opcode: tSTRHi
 /* 538 */     MCD_OPC_FilterValue, 1, 163, 2, 0, // Skip to: 1218
-/* 543 */     MCD_OPC_CheckPredicate, 28, 158, 2, 0, // Skip to: 1218
-/* 548 */     MCD_OPC_Decode, 224, 24, 216, 1, // Opcode: tLDRHi
+/* 543 */     MCD_OPC_CheckPredicate, 35, 158, 2, 0, // Skip to: 1218
+/* 548 */     MCD_OPC_Decode, 153, 34, 193, 2, // Opcode: tLDRHi
 /* 553 */     MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 591
 /* 558 */     MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 561 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 576
-/* 566 */     MCD_OPC_CheckPredicate, 28, 135, 2, 0, // Skip to: 1218
-/* 571 */     MCD_OPC_Decode, 131, 25, 217, 1, // Opcode: tSTRspi
+/* 566 */     MCD_OPC_CheckPredicate, 35, 135, 2, 0, // Skip to: 1218
+/* 571 */     MCD_OPC_Decode, 188, 34, 194, 2, // Opcode: tSTRspi
 /* 576 */     MCD_OPC_FilterValue, 1, 125, 2, 0, // Skip to: 1218
-/* 581 */     MCD_OPC_CheckPredicate, 28, 120, 2, 0, // Skip to: 1218
-/* 586 */     MCD_OPC_Decode, 231, 24, 217, 1, // Opcode: tLDRspi
+/* 581 */     MCD_OPC_CheckPredicate, 35, 120, 2, 0, // Skip to: 1218
+/* 586 */     MCD_OPC_Decode, 160, 34, 194, 2, // Opcode: tLDRspi
 /* 591 */     MCD_OPC_FilterValue, 10, 33, 0, 0, // Skip to: 629
 /* 596 */     MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 599 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 614
-/* 604 */     MCD_OPC_CheckPredicate, 28, 97, 2, 0, // Skip to: 1218
-/* 609 */     MCD_OPC_Decode, 194, 24, 218, 1, // Opcode: tADR
+/* 604 */     MCD_OPC_CheckPredicate, 35, 97, 2, 0, // Skip to: 1218
+/* 609 */     MCD_OPC_Decode, 251, 33, 195, 2, // Opcode: tADR
 /* 614 */     MCD_OPC_FilterValue, 1, 87, 2, 0, // Skip to: 1218
-/* 619 */     MCD_OPC_CheckPredicate, 28, 82, 2, 0, // Skip to: 1218
-/* 624 */     MCD_OPC_Decode, 190, 24, 218, 1, // Opcode: tADDrSPi
+/* 619 */     MCD_OPC_CheckPredicate, 35, 82, 2, 0, // Skip to: 1218
+/* 624 */     MCD_OPC_Decode, 247, 33, 195, 2, // Opcode: tADDrSPi
 /* 629 */     MCD_OPC_FilterValue, 11, 187, 1, 0, // Skip to: 1077
 /* 634 */     MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
 /* 637 */     MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 790
@@ -7422,118 +12315,118 @@ static const uint8_t DecoderTableThumb16[] = {
 /* 653 */     MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 714
 /* 658 */     MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 661 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 676
-/* 666 */     MCD_OPC_CheckPredicate, 28, 35, 2, 0, // Skip to: 1218
-/* 671 */     MCD_OPC_Decode, 192, 24, 219, 1, // Opcode: tADDspi
+/* 666 */     MCD_OPC_CheckPredicate, 35, 35, 2, 0, // Skip to: 1218
+/* 671 */     MCD_OPC_Decode, 249, 33, 196, 2, // Opcode: tADDspi
 /* 676 */     MCD_OPC_FilterValue, 1, 25, 2, 0, // Skip to: 1218
 /* 681 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 684 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 699
-/* 689 */     MCD_OPC_CheckPredicate, 31, 12, 2, 0, // Skip to: 1218
-/* 694 */     MCD_OPC_Decode, 138, 25, 207, 1, // Opcode: tSXTH
+/* 689 */     MCD_OPC_CheckPredicate, 38, 12, 2, 0, // Skip to: 1218
+/* 694 */     MCD_OPC_Decode, 195, 34, 184, 2, // Opcode: tSXTH
 /* 699 */     MCD_OPC_FilterValue, 1, 2, 2, 0, // Skip to: 1218
-/* 704 */     MCD_OPC_CheckPredicate, 31, 253, 1, 0, // Skip to: 1218
-/* 709 */     MCD_OPC_Decode, 137, 25, 207, 1, // Opcode: tSXTB
+/* 704 */     MCD_OPC_CheckPredicate, 38, 253, 1, 0, // Skip to: 1218
+/* 709 */     MCD_OPC_Decode, 194, 34, 184, 2, // Opcode: tSXTB
 /* 714 */     MCD_OPC_FilterValue, 1, 243, 1, 0, // Skip to: 1218
 /* 719 */     MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 722 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 737
-/* 727 */     MCD_OPC_CheckPredicate, 28, 230, 1, 0, // Skip to: 1218
-/* 732 */     MCD_OPC_Decode, 135, 25, 219, 1, // Opcode: tSUBspi
+/* 727 */     MCD_OPC_CheckPredicate, 35, 230, 1, 0, // Skip to: 1218
+/* 732 */     MCD_OPC_Decode, 192, 34, 196, 2, // Opcode: tSUBspi
 /* 737 */     MCD_OPC_FilterValue, 1, 220, 1, 0, // Skip to: 1218
 /* 742 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 745 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 760
-/* 750 */     MCD_OPC_CheckPredicate, 31, 207, 1, 0, // Skip to: 1218
-/* 755 */     MCD_OPC_Decode, 143, 25, 207, 1, // Opcode: tUXTH
+/* 750 */     MCD_OPC_CheckPredicate, 38, 207, 1, 0, // Skip to: 1218
+/* 755 */     MCD_OPC_Decode, 200, 34, 184, 2, // Opcode: tUXTH
 /* 760 */     MCD_OPC_FilterValue, 1, 197, 1, 0, // Skip to: 1218
-/* 765 */     MCD_OPC_CheckPredicate, 31, 192, 1, 0, // Skip to: 1218
-/* 770 */     MCD_OPC_Decode, 142, 25, 207, 1, // Opcode: tUXTB
+/* 765 */     MCD_OPC_CheckPredicate, 38, 192, 1, 0, // Skip to: 1218
+/* 770 */     MCD_OPC_Decode, 199, 34, 184, 2, // Opcode: tUXTB
 /* 775 */     MCD_OPC_FilterValue, 1, 182, 1, 0, // Skip to: 1218
-/* 780 */     MCD_OPC_CheckPredicate, 32, 177, 1, 0, // Skip to: 1218
-/* 785 */     MCD_OPC_Decode, 209, 24, 220, 1, // Opcode: tCBZ
+/* 780 */     MCD_OPC_CheckPredicate, 39, 177, 1, 0, // Skip to: 1218
+/* 785 */     MCD_OPC_Decode, 138, 34, 197, 2, // Opcode: tCBZ
 /* 790 */     MCD_OPC_FilterValue, 1, 95, 0, 0, // Skip to: 890
 /* 795 */     MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 798 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 813
-/* 803 */     MCD_OPC_CheckPredicate, 28, 154, 1, 0, // Skip to: 1218
-/* 808 */     MCD_OPC_Decode, 244, 24, 221, 1, // Opcode: tPUSH
+/* 803 */     MCD_OPC_CheckPredicate, 35, 154, 1, 0, // Skip to: 1218
+/* 808 */     MCD_OPC_Decode, 173, 34, 198, 2, // Opcode: tPUSH
 /* 813 */     MCD_OPC_FilterValue, 1, 144, 1, 0, // Skip to: 1218
 /* 818 */     MCD_OPC_ExtractField, 5, 4,  // Inst{8-5} ...
 /* 821 */     MCD_OPC_FilterValue, 0, 13, 0, 0, // Skip to: 839
-/* 826 */     MCD_OPC_CheckPredicate, 33, 131, 1, 0, // Skip to: 1218
+/* 826 */     MCD_OPC_CheckPredicate, 40, 131, 1, 0, // Skip to: 1218
 /* 831 */     MCD_OPC_SoftFail, 7, 16,
-/* 834 */     MCD_OPC_Decode, 149, 23, 222, 1, // Opcode: t2SETPAN
+/* 834 */     MCD_OPC_Decode, 203, 32, 199, 2, // Opcode: t2SETPAN
 /* 839 */     MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 868
-/* 844 */     MCD_OPC_CheckPredicate, 34, 113, 1, 0, // Skip to: 1218
+/* 844 */     MCD_OPC_CheckPredicate, 41, 113, 1, 0, // Skip to: 1218
 /* 849 */     MCD_OPC_CheckField, 4, 1, 1, 106, 1, 0, // Skip to: 1218
 /* 856 */     MCD_OPC_CheckField, 0, 3, 0, 99, 1, 0, // Skip to: 1218
-/* 863 */     MCD_OPC_Decode, 251, 24, 222, 1, // Opcode: tSETEND
+/* 863 */     MCD_OPC_Decode, 180, 34, 199, 2, // Opcode: tSETEND
 /* 868 */     MCD_OPC_FilterValue, 3, 89, 1, 0, // Skip to: 1218
-/* 873 */     MCD_OPC_CheckPredicate, 28, 84, 1, 0, // Skip to: 1218
+/* 873 */     MCD_OPC_CheckPredicate, 35, 84, 1, 0, // Skip to: 1218
 /* 878 */     MCD_OPC_CheckField, 3, 1, 0, 77, 1, 0, // Skip to: 1218
-/* 885 */     MCD_OPC_Decode, 214, 24, 223, 1, // Opcode: tCPS
+/* 885 */     MCD_OPC_Decode, 143, 34, 200, 2, // Opcode: tCPS
 /* 890 */     MCD_OPC_FilterValue, 2, 114, 0, 0, // Skip to: 1009
 /* 895 */     MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
 /* 898 */     MCD_OPC_FilterValue, 0, 91, 0, 0, // Skip to: 994
 /* 903 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
 /* 906 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 928
-/* 911 */     MCD_OPC_CheckPredicate, 31, 46, 1, 0, // Skip to: 1218
+/* 911 */     MCD_OPC_CheckPredicate, 38, 46, 1, 0, // Skip to: 1218
 /* 916 */     MCD_OPC_CheckField, 9, 1, 1, 39, 1, 0, // Skip to: 1218
-/* 923 */     MCD_OPC_Decode, 245, 24, 207, 1, // Opcode: tREV
+/* 923 */     MCD_OPC_Decode, 174, 34, 184, 2, // Opcode: tREV
 /* 928 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 950
-/* 933 */     MCD_OPC_CheckPredicate, 31, 24, 1, 0, // Skip to: 1218
+/* 933 */     MCD_OPC_CheckPredicate, 38, 24, 1, 0, // Skip to: 1218
 /* 938 */     MCD_OPC_CheckField, 9, 1, 1, 17, 1, 0, // Skip to: 1218
-/* 945 */     MCD_OPC_Decode, 246, 24, 207, 1, // Opcode: tREV16
+/* 945 */     MCD_OPC_Decode, 175, 34, 184, 2, // Opcode: tREV16
 /* 950 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 972
-/* 955 */     MCD_OPC_CheckPredicate, 35, 2, 1, 0, // Skip to: 1218
+/* 955 */     MCD_OPC_CheckPredicate, 42, 2, 1, 0, // Skip to: 1218
 /* 960 */     MCD_OPC_CheckField, 9, 1, 1, 251, 0, 0, // Skip to: 1218
-/* 967 */     MCD_OPC_Decode, 217, 24, 224, 1, // Opcode: tHLT
+/* 967 */     MCD_OPC_Decode, 146, 34, 201, 2, // Opcode: tHLT
 /* 972 */     MCD_OPC_FilterValue, 3, 241, 0, 0, // Skip to: 1218
-/* 977 */     MCD_OPC_CheckPredicate, 31, 236, 0, 0, // Skip to: 1218
+/* 977 */     MCD_OPC_CheckPredicate, 38, 236, 0, 0, // Skip to: 1218
 /* 982 */     MCD_OPC_CheckField, 9, 1, 1, 229, 0, 0, // Skip to: 1218
-/* 989 */     MCD_OPC_Decode, 247, 24, 207, 1, // Opcode: tREVSH
+/* 989 */     MCD_OPC_Decode, 176, 34, 184, 2, // Opcode: tREVSH
 /* 994 */     MCD_OPC_FilterValue, 1, 219, 0, 0, // Skip to: 1218
-/* 999 */     MCD_OPC_CheckPredicate, 32, 214, 0, 0, // Skip to: 1218
-/* 1004 */    MCD_OPC_Decode, 208, 24, 220, 1, // Opcode: tCBNZ
+/* 999 */     MCD_OPC_CheckPredicate, 39, 214, 0, 0, // Skip to: 1218
+/* 1004 */    MCD_OPC_Decode, 137, 34, 197, 2, // Opcode: tCBNZ
 /* 1009 */    MCD_OPC_FilterValue, 3, 204, 0, 0, // Skip to: 1218
 /* 1014 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
 /* 1017 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1032
-/* 1022 */    MCD_OPC_CheckPredicate, 28, 191, 0, 0, // Skip to: 1218
-/* 1027 */    MCD_OPC_Decode, 243, 24, 225, 1, // Opcode: tPOP
+/* 1022 */    MCD_OPC_CheckPredicate, 35, 191, 0, 0, // Skip to: 1218
+/* 1027 */    MCD_OPC_Decode, 172, 34, 202, 2, // Opcode: tPOP
 /* 1032 */    MCD_OPC_FilterValue, 1, 181, 0, 0, // Skip to: 1218
 /* 1037 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
 /* 1040 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1055
-/* 1045 */    MCD_OPC_CheckPredicate, 28, 168, 0, 0, // Skip to: 1218
-/* 1050 */    MCD_OPC_Decode, 200, 24, 226, 1, // Opcode: tBKPT
+/* 1045 */    MCD_OPC_CheckPredicate, 35, 168, 0, 0, // Skip to: 1218
+/* 1050 */    MCD_OPC_Decode, 129, 34, 203, 2, // Opcode: tBKPT
 /* 1055 */    MCD_OPC_FilterValue, 1, 158, 0, 0, // Skip to: 1218
-/* 1060 */    MCD_OPC_CheckPredicate, 36, 153, 0, 0, // Skip to: 1218
+/* 1060 */    MCD_OPC_CheckPredicate, 43, 153, 0, 0, // Skip to: 1218
 /* 1065 */    MCD_OPC_CheckField, 0, 4, 0, 146, 0, 0, // Skip to: 1218
-/* 1072 */    MCD_OPC_Decode, 216, 24, 227, 1, // Opcode: tHINT
+/* 1072 */    MCD_OPC_Decode, 145, 34, 204, 2, // Opcode: tHINT
 /* 1077 */    MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 1115
 /* 1082 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
 /* 1085 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1100
-/* 1090 */    MCD_OPC_CheckPredicate, 28, 123, 0, 0, // Skip to: 1218
-/* 1095 */    MCD_OPC_Decode, 252, 24, 228, 1, // Opcode: tSTMIA_UPD
+/* 1090 */    MCD_OPC_CheckPredicate, 35, 123, 0, 0, // Skip to: 1218
+/* 1095 */    MCD_OPC_Decode, 181, 34, 205, 2, // Opcode: tSTMIA_UPD
 /* 1100 */    MCD_OPC_FilterValue, 1, 113, 0, 0, // Skip to: 1218
-/* 1105 */    MCD_OPC_CheckPredicate, 28, 108, 0, 0, // Skip to: 1218
-/* 1110 */    MCD_OPC_Decode, 221, 24, 229, 1, // Opcode: tLDMIA
+/* 1105 */    MCD_OPC_CheckPredicate, 35, 108, 0, 0, // Skip to: 1218
+/* 1110 */    MCD_OPC_Decode, 150, 34, 206, 2, // Opcode: tLDMIA
 /* 1115 */    MCD_OPC_FilterValue, 13, 76, 0, 0, // Skip to: 1196
 /* 1120 */    MCD_OPC_ExtractField, 0, 12,  // Inst{11-0} ...
 /* 1123 */    MCD_OPC_FilterValue, 249, 29, 9, 0, 0, // Skip to: 1138
-/* 1129 */    MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 1153
-/* 1134 */    MCD_OPC_Decode, 144, 25, 51, // Opcode: t__brkdiv0
+/* 1129 */    MCD_OPC_CheckPredicate, 35, 19, 0, 0, // Skip to: 1153
+/* 1134 */    MCD_OPC_Decode, 201, 34, 61, // Opcode: t__brkdiv0
 /* 1138 */    MCD_OPC_FilterValue, 254, 29, 9, 0, 0, // Skip to: 1153
-/* 1144 */    MCD_OPC_CheckPredicate, 28, 4, 0, 0, // Skip to: 1153
-/* 1149 */    MCD_OPC_Decode, 139, 25, 51, // Opcode: tTRAP
+/* 1144 */    MCD_OPC_CheckPredicate, 35, 4, 0, 0, // Skip to: 1153
+/* 1149 */    MCD_OPC_Decode, 196, 34, 61, // Opcode: tTRAP
 /* 1153 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
 /* 1156 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 1171
-/* 1161 */    MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 1186
-/* 1166 */    MCD_OPC_Decode, 141, 25, 226, 1, // Opcode: tUDF
+/* 1161 */    MCD_OPC_CheckPredicate, 35, 20, 0, 0, // Skip to: 1186
+/* 1166 */    MCD_OPC_Decode, 198, 34, 203, 2, // Opcode: tUDF
 /* 1171 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 1186
-/* 1176 */    MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 1186
-/* 1181 */    MCD_OPC_Decode, 136, 25, 226, 1, // Opcode: tSVC
-/* 1186 */    MCD_OPC_CheckPredicate, 28, 27, 0, 0, // Skip to: 1218
-/* 1191 */    MCD_OPC_Decode, 207, 24, 230, 1, // Opcode: tBcc
+/* 1176 */    MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 1186
+/* 1181 */    MCD_OPC_Decode, 193, 34, 203, 2, // Opcode: tSVC
+/* 1186 */    MCD_OPC_CheckPredicate, 35, 27, 0, 0, // Skip to: 1218
+/* 1191 */    MCD_OPC_Decode, 136, 34, 207, 2, // Opcode: tBcc
 /* 1196 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1218
-/* 1201 */    MCD_OPC_CheckPredicate, 28, 12, 0, 0, // Skip to: 1218
+/* 1201 */    MCD_OPC_CheckPredicate, 35, 12, 0, 0, // Skip to: 1218
 /* 1206 */    MCD_OPC_CheckField, 11, 1, 0, 5, 0, 0, // Skip to: 1218
-/* 1213 */    MCD_OPC_Decode, 198, 24, 231, 1, // Opcode: tB
+/* 1213 */    MCD_OPC_Decode, 255, 33, 208, 2, // Opcode: tB
 /* 1218 */    MCD_OPC_Fail,
   0
 };
@@ -7541,1605 +12434,1965 @@ static const uint8_t DecoderTableThumb16[] = {
 static const uint8_t DecoderTableThumb32[] = {
 /* 0 */       MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
 /* 3 */       MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 39
-/* 8 */       MCD_OPC_CheckPredicate, 37, 55, 0, 0, // Skip to: 68
+/* 8 */       MCD_OPC_CheckPredicate, 44, 55, 0, 0, // Skip to: 68
 /* 13 */      MCD_OPC_CheckField, 27, 5, 30, 48, 0, 0, // Skip to: 68
 /* 20 */      MCD_OPC_CheckField, 14, 2, 3, 41, 0, 0, // Skip to: 68
 /* 27 */      MCD_OPC_CheckField, 0, 1, 0, 34, 0, 0, // Skip to: 68
-/* 34 */      MCD_OPC_Decode, 203, 24, 232, 1, // Opcode: tBLXi
+/* 34 */      MCD_OPC_Decode, 132, 34, 209, 2, // Opcode: tBLXi
 /* 39 */      MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 68
-/* 44 */      MCD_OPC_CheckPredicate, 28, 19, 0, 0, // Skip to: 68
+/* 44 */      MCD_OPC_CheckPredicate, 35, 19, 0, 0, // Skip to: 68
 /* 49 */      MCD_OPC_CheckField, 27, 5, 30, 12, 0, 0, // Skip to: 68
 /* 56 */      MCD_OPC_CheckField, 14, 2, 3, 5, 0, 0, // Skip to: 68
-/* 63 */      MCD_OPC_Decode, 201, 24, 233, 1, // Opcode: tBL
+/* 63 */      MCD_OPC_Decode, 130, 34, 210, 2, // Opcode: tBL
 /* 68 */      MCD_OPC_Fail,
   0
 };
 
 static const uint8_t DecoderTableThumb216[] = {
-/* 0 */       MCD_OPC_CheckPredicate, 38, 13, 0, 0, // Skip to: 18
+/* 0 */       MCD_OPC_CheckPredicate, 45, 13, 0, 0, // Skip to: 18
 /* 5 */       MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, 0, // Skip to: 18
-/* 13 */      MCD_OPC_Decode, 250, 21, 234, 1, // Opcode: t2IT
+/* 13 */      MCD_OPC_Decode, 170, 31, 211, 2, // Opcode: t2IT
 /* 18 */      MCD_OPC_Fail,
   0
 };
 
 static const uint8_t DecoderTableThumb232[] = {
 /* 0 */       MCD_OPC_ExtractField, 27, 5,  // Inst{31-27} ...
-/* 3 */       MCD_OPC_FilterValue, 29, 124, 8, 0, // Skip to: 2180
+/* 3 */       MCD_OPC_FilterValue, 29, 41, 9, 0, // Skip to: 2353
 /* 8 */       MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
-/* 11 */      MCD_OPC_FilterValue, 0, 223, 1, 0, // Skip to: 495
+/* 11 */      MCD_OPC_FilterValue, 0, 11, 2, 0, // Skip to: 539
 /* 16 */      MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
 /* 19 */      MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 73
 /* 24 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 27 */      MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 50
-/* 32 */      MCD_OPC_CheckPredicate, 39, 210, 31, 0, // Skip to: 8183
-/* 37 */      MCD_OPC_CheckField, 5, 15, 128, 220, 1, 201, 31, 0, // Skip to: 8183
-/* 46 */      MCD_OPC_Decode, 194, 23, 83, // Opcode: t2SRSDB
-/* 50 */      MCD_OPC_FilterValue, 1, 192, 31, 0, // Skip to: 8183
-/* 55 */      MCD_OPC_CheckPredicate, 39, 187, 31, 0, // Skip to: 8183
-/* 60 */      MCD_OPC_CheckField, 0, 16, 128, 128, 3, 178, 31, 0, // Skip to: 8183
-/* 69 */      MCD_OPC_Decode, 130, 23, 81, // Opcode: t2RFEDB
-/* 73 */      MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 125
+/* 32 */      MCD_OPC_CheckPredicate, 46, 109, 35, 0, // Skip to: 9106
+/* 37 */      MCD_OPC_CheckField, 5, 15, 128, 220, 1, 100, 35, 0, // Skip to: 9106
+/* 46 */      MCD_OPC_Decode, 248, 32, 85, // Opcode: t2SRSDB
+/* 50 */      MCD_OPC_FilterValue, 1, 91, 35, 0, // Skip to: 9106
+/* 55 */      MCD_OPC_CheckPredicate, 46, 86, 35, 0, // Skip to: 9106
+/* 60 */      MCD_OPC_CheckField, 0, 16, 128, 128, 3, 77, 35, 0, // Skip to: 9106
+/* 69 */      MCD_OPC_Decode, 183, 32, 82, // Opcode: t2RFEDB
+/* 73 */      MCD_OPC_FilterValue, 1, 71, 0, 0, // Skip to: 149
 /* 78 */      MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 81 */      MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 110
-/* 86 */      MCD_OPC_CheckPredicate, 38, 156, 31, 0, // Skip to: 8183
-/* 91 */      MCD_OPC_CheckField, 15, 1, 0, 149, 31, 0, // Skip to: 8183
-/* 98 */      MCD_OPC_CheckField, 13, 1, 0, 142, 31, 0, // Skip to: 8183
-/* 105 */     MCD_OPC_Decode, 228, 23, 235, 1, // Opcode: t2STMIA
-/* 110 */     MCD_OPC_FilterValue, 1, 132, 31, 0, // Skip to: 8183
-/* 115 */     MCD_OPC_CheckPredicate, 38, 127, 31, 0, // Skip to: 8183
-/* 120 */     MCD_OPC_Decode, 150, 22, 236, 1, // Opcode: t2LDMIA
-/* 125 */     MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 177
-/* 130 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 133 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 162
-/* 138 */     MCD_OPC_CheckPredicate, 38, 104, 31, 0, // Skip to: 8183
-/* 143 */     MCD_OPC_CheckField, 15, 1, 0, 97, 31, 0, // Skip to: 8183
-/* 150 */     MCD_OPC_CheckField, 13, 1, 0, 90, 31, 0, // Skip to: 8183
-/* 157 */     MCD_OPC_Decode, 226, 23, 235, 1, // Opcode: t2STMDB
-/* 162 */     MCD_OPC_FilterValue, 1, 80, 31, 0, // Skip to: 8183
-/* 167 */     MCD_OPC_CheckPredicate, 38, 75, 31, 0, // Skip to: 8183
-/* 172 */     MCD_OPC_Decode, 148, 22, 236, 1, // Opcode: t2LDMDB
-/* 177 */     MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 231
-/* 182 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 185 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 208
-/* 190 */     MCD_OPC_CheckPredicate, 39, 52, 31, 0, // Skip to: 8183
-/* 195 */     MCD_OPC_CheckField, 5, 15, 128, 220, 1, 43, 31, 0, // Skip to: 8183
-/* 204 */     MCD_OPC_Decode, 196, 23, 83, // Opcode: t2SRSIA
-/* 208 */     MCD_OPC_FilterValue, 1, 34, 31, 0, // Skip to: 8183
-/* 213 */     MCD_OPC_CheckPredicate, 39, 29, 31, 0, // Skip to: 8183
-/* 218 */     MCD_OPC_CheckField, 0, 16, 128, 128, 3, 20, 31, 0, // Skip to: 8183
-/* 227 */     MCD_OPC_Decode, 132, 23, 81, // Opcode: t2RFEIA
-/* 231 */     MCD_OPC_FilterValue, 4, 83, 0, 0, // Skip to: 319
-/* 236 */     MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 261
-/* 241 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 261
-/* 248 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 261
-/* 256 */     MCD_OPC_Decode, 145, 24, 237, 1, // Opcode: t2TSTrr
-/* 261 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 285
-/* 266 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 285
-/* 273 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 285
-/* 280 */     MCD_OPC_Decode, 146, 24, 238, 1, // Opcode: t2TSTrs
-/* 285 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 309
-/* 290 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 309
-/* 297 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 309
-/* 304 */     MCD_OPC_Decode, 207, 21, 239, 1, // Opcode: t2ANDrr
-/* 309 */     MCD_OPC_CheckPredicate, 38, 189, 30, 0, // Skip to: 8183
-/* 314 */     MCD_OPC_Decode, 208, 21, 240, 1, // Opcode: t2ANDrs
-/* 319 */     MCD_OPC_FilterValue, 5, 83, 0, 0, // Skip to: 407
-/* 324 */     MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 349
-/* 329 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 349
-/* 336 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 349
-/* 344 */     MCD_OPC_Decode, 141, 24, 237, 1, // Opcode: t2TEQrr
-/* 349 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 373
-/* 354 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 373
-/* 361 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 373
-/* 368 */     MCD_OPC_Decode, 142, 24, 238, 1, // Opcode: t2TEQrs
-/* 373 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 397
-/* 378 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 397
-/* 385 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 397
-/* 392 */     MCD_OPC_Decode, 245, 21, 239, 1, // Opcode: t2EORrr
-/* 397 */     MCD_OPC_CheckPredicate, 38, 101, 30, 0, // Skip to: 8183
-/* 402 */     MCD_OPC_Decode, 246, 21, 240, 1, // Opcode: t2EORrs
-/* 407 */     MCD_OPC_FilterValue, 6, 91, 30, 0, // Skip to: 8183
-/* 412 */     MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 437
-/* 417 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 437
-/* 424 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 437
-/* 432 */     MCD_OPC_Decode, 224, 21, 237, 1, // Opcode: t2CMNzrr
-/* 437 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 461
-/* 442 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 461
-/* 449 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 461
-/* 456 */     MCD_OPC_Decode, 225, 21, 238, 1, // Opcode: t2CMNzrs
-/* 461 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 485
-/* 466 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 485
-/* 473 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 485
-/* 480 */     MCD_OPC_Decode, 203, 21, 241, 1, // Opcode: t2ADDrr
-/* 485 */     MCD_OPC_CheckPredicate, 38, 13, 30, 0, // Skip to: 8183
-/* 490 */     MCD_OPC_Decode, 204, 21, 242, 1, // Opcode: t2ADDrs
-/* 495 */     MCD_OPC_FilterValue, 1, 86, 1, 0, // Skip to: 842
-/* 500 */     MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
-/* 503 */     MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 557
-/* 508 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 511 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 534
-/* 516 */     MCD_OPC_CheckPredicate, 39, 238, 29, 0, // Skip to: 8183
-/* 521 */     MCD_OPC_CheckField, 5, 15, 128, 220, 1, 229, 29, 0, // Skip to: 8183
-/* 530 */     MCD_OPC_Decode, 195, 23, 83, // Opcode: t2SRSDB_UPD
-/* 534 */     MCD_OPC_FilterValue, 1, 220, 29, 0, // Skip to: 8183
-/* 539 */     MCD_OPC_CheckPredicate, 39, 215, 29, 0, // Skip to: 8183
-/* 544 */     MCD_OPC_CheckField, 0, 16, 128, 128, 3, 206, 29, 0, // Skip to: 8183
-/* 553 */     MCD_OPC_Decode, 131, 23, 81, // Opcode: t2RFEDBW
-/* 557 */     MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 609
-/* 562 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 565 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 594
-/* 570 */     MCD_OPC_CheckPredicate, 38, 184, 29, 0, // Skip to: 8183
-/* 575 */     MCD_OPC_CheckField, 15, 1, 0, 177, 29, 0, // Skip to: 8183
-/* 582 */     MCD_OPC_CheckField, 13, 1, 0, 170, 29, 0, // Skip to: 8183
-/* 589 */     MCD_OPC_Decode, 229, 23, 243, 1, // Opcode: t2STMIA_UPD
-/* 594 */     MCD_OPC_FilterValue, 1, 160, 29, 0, // Skip to: 8183
-/* 599 */     MCD_OPC_CheckPredicate, 38, 155, 29, 0, // Skip to: 8183
-/* 604 */     MCD_OPC_Decode, 151, 22, 244, 1, // Opcode: t2LDMIA_UPD
-/* 609 */     MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 661
-/* 614 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 617 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 646
-/* 622 */     MCD_OPC_CheckPredicate, 38, 132, 29, 0, // Skip to: 8183
-/* 627 */     MCD_OPC_CheckField, 15, 1, 0, 125, 29, 0, // Skip to: 8183
-/* 634 */     MCD_OPC_CheckField, 13, 1, 0, 118, 29, 0, // Skip to: 8183
-/* 641 */     MCD_OPC_Decode, 227, 23, 243, 1, // Opcode: t2STMDB_UPD
-/* 646 */     MCD_OPC_FilterValue, 1, 108, 29, 0, // Skip to: 8183
-/* 651 */     MCD_OPC_CheckPredicate, 38, 103, 29, 0, // Skip to: 8183
-/* 656 */     MCD_OPC_Decode, 149, 22, 244, 1, // Opcode: t2LDMDB_UPD
-/* 661 */     MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 715
-/* 666 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 669 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 692
-/* 674 */     MCD_OPC_CheckPredicate, 39, 80, 29, 0, // Skip to: 8183
-/* 679 */     MCD_OPC_CheckField, 5, 15, 128, 220, 1, 71, 29, 0, // Skip to: 8183
-/* 688 */     MCD_OPC_Decode, 197, 23, 83, // Opcode: t2SRSIA_UPD
-/* 692 */     MCD_OPC_FilterValue, 1, 62, 29, 0, // Skip to: 8183
-/* 697 */     MCD_OPC_CheckPredicate, 39, 57, 29, 0, // Skip to: 8183
-/* 702 */     MCD_OPC_CheckField, 0, 16, 128, 128, 3, 48, 29, 0, // Skip to: 8183
-/* 711 */     MCD_OPC_Decode, 133, 23, 81, // Opcode: t2RFEIAW
-/* 715 */     MCD_OPC_FilterValue, 4, 34, 0, 0, // Skip to: 754
-/* 720 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 744
-/* 725 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 744
-/* 732 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 744
-/* 739 */     MCD_OPC_Decode, 215, 21, 239, 1, // Opcode: t2BICrr
-/* 744 */     MCD_OPC_CheckPredicate, 38, 10, 29, 0, // Skip to: 8183
-/* 749 */     MCD_OPC_Decode, 216, 21, 240, 1, // Opcode: t2BICrs
-/* 754 */     MCD_OPC_FilterValue, 7, 0, 29, 0, // Skip to: 8183
-/* 759 */     MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 784
-/* 764 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 784
-/* 771 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 784
-/* 779 */     MCD_OPC_Decode, 227, 21, 237, 1, // Opcode: t2CMPrr
-/* 784 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 808
-/* 789 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 808
-/* 796 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 808
-/* 803 */     MCD_OPC_Decode, 228, 21, 238, 1, // Opcode: t2CMPrs
-/* 808 */     MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 832
-/* 813 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 832
-/* 820 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 832
-/* 827 */     MCD_OPC_Decode, 130, 24, 241, 1, // Opcode: t2SUBrr
-/* 832 */     MCD_OPC_CheckPredicate, 38, 178, 28, 0, // Skip to: 8183
-/* 837 */     MCD_OPC_Decode, 131, 24, 242, 1, // Opcode: t2SUBrs
-/* 842 */     MCD_OPC_FilterValue, 2, 70, 4, 0, // Skip to: 1941
-/* 847 */     MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
-/* 850 */     MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1579
-/* 855 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 858 */     MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 1219
-/* 863 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 866 */     MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 984
-/* 871 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 874 */     MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 899
-/* 879 */     MCD_OPC_CheckPredicate, 29, 90, 0, 0, // Skip to: 974
-/* 884 */     MCD_OPC_CheckField, 12, 4, 15, 83, 0, 0, // Skip to: 974
-/* 891 */     MCD_OPC_SoftFail, 63, 0,
-/* 894 */     MCD_OPC_Decode, 147, 24, 245, 1, // Opcode: t2TT
-/* 899 */     MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 924
-/* 904 */     MCD_OPC_CheckPredicate, 29, 65, 0, 0, // Skip to: 974
-/* 909 */     MCD_OPC_CheckField, 12, 4, 15, 58, 0, 0, // Skip to: 974
-/* 916 */     MCD_OPC_SoftFail, 63, 0,
-/* 919 */     MCD_OPC_Decode, 150, 24, 245, 1, // Opcode: t2TTT
-/* 924 */     MCD_OPC_FilterValue, 2, 20, 0, 0, // Skip to: 949
-/* 929 */     MCD_OPC_CheckPredicate, 29, 40, 0, 0, // Skip to: 974
-/* 934 */     MCD_OPC_CheckField, 12, 4, 15, 33, 0, 0, // Skip to: 974
-/* 941 */     MCD_OPC_SoftFail, 63, 0,
-/* 944 */     MCD_OPC_Decode, 148, 24, 245, 1, // Opcode: t2TTA
-/* 949 */     MCD_OPC_FilterValue, 3, 20, 0, 0, // Skip to: 974
-/* 954 */     MCD_OPC_CheckPredicate, 29, 15, 0, 0, // Skip to: 974
-/* 959 */     MCD_OPC_CheckField, 12, 4, 15, 8, 0, 0, // Skip to: 974
-/* 966 */     MCD_OPC_SoftFail, 63, 0,
-/* 969 */     MCD_OPC_Decode, 149, 24, 245, 1, // Opcode: t2TTAT
-/* 974 */     MCD_OPC_CheckPredicate, 32, 36, 28, 0, // Skip to: 8183
-/* 979 */     MCD_OPC_Decode, 239, 23, 246, 1, // Opcode: t2STREX
-/* 984 */     MCD_OPC_FilterValue, 1, 26, 28, 0, // Skip to: 8183
-/* 989 */     MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 992 */     MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1014
-/* 997 */     MCD_OPC_CheckPredicate, 32, 13, 28, 0, // Skip to: 8183
-/* 1002 */    MCD_OPC_CheckField, 8, 4, 15, 6, 28, 0, // Skip to: 8183
-/* 1009 */    MCD_OPC_Decode, 240, 23, 247, 1, // Opcode: t2STREXB
-/* 1014 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1036
-/* 1019 */    MCD_OPC_CheckPredicate, 32, 247, 27, 0, // Skip to: 8183
-/* 1024 */    MCD_OPC_CheckField, 8, 4, 15, 240, 27, 0, // Skip to: 8183
-/* 1031 */    MCD_OPC_Decode, 242, 23, 247, 1, // Opcode: t2STREXH
-/* 1036 */    MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1051
-/* 1041 */    MCD_OPC_CheckPredicate, 39, 225, 27, 0, // Skip to: 8183
-/* 1046 */    MCD_OPC_Decode, 241, 23, 248, 1, // Opcode: t2STREXD
-/* 1051 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1080
-/* 1056 */    MCD_OPC_CheckPredicate, 40, 210, 27, 0, // Skip to: 8183
-/* 1061 */    MCD_OPC_CheckField, 8, 4, 15, 203, 27, 0, // Skip to: 8183
-/* 1068 */    MCD_OPC_CheckField, 0, 4, 15, 196, 27, 0, // Skip to: 8183
-/* 1075 */    MCD_OPC_Decode, 220, 23, 249, 1, // Opcode: t2STLB
-/* 1080 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1109
-/* 1085 */    MCD_OPC_CheckPredicate, 40, 181, 27, 0, // Skip to: 8183
-/* 1090 */    MCD_OPC_CheckField, 8, 4, 15, 174, 27, 0, // Skip to: 8183
-/* 1097 */    MCD_OPC_CheckField, 0, 4, 15, 167, 27, 0, // Skip to: 8183
-/* 1104 */    MCD_OPC_Decode, 225, 23, 249, 1, // Opcode: t2STLH
-/* 1109 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1138
-/* 1114 */    MCD_OPC_CheckPredicate, 40, 152, 27, 0, // Skip to: 8183
-/* 1119 */    MCD_OPC_CheckField, 8, 4, 15, 145, 27, 0, // Skip to: 8183
-/* 1126 */    MCD_OPC_CheckField, 0, 4, 15, 138, 27, 0, // Skip to: 8183
-/* 1133 */    MCD_OPC_Decode, 219, 23, 249, 1, // Opcode: t2STL
-/* 1138 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1160
-/* 1143 */    MCD_OPC_CheckPredicate, 41, 123, 27, 0, // Skip to: 8183
-/* 1148 */    MCD_OPC_CheckField, 8, 4, 15, 116, 27, 0, // Skip to: 8183
-/* 1155 */    MCD_OPC_Decode, 222, 23, 247, 1, // Opcode: t2STLEXB
-/* 1160 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1182
-/* 1165 */    MCD_OPC_CheckPredicate, 41, 101, 27, 0, // Skip to: 8183
-/* 1170 */    MCD_OPC_CheckField, 8, 4, 15, 94, 27, 0, // Skip to: 8183
-/* 1177 */    MCD_OPC_Decode, 224, 23, 247, 1, // Opcode: t2STLEXH
-/* 1182 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1204
-/* 1187 */    MCD_OPC_CheckPredicate, 41, 79, 27, 0, // Skip to: 8183
-/* 1192 */    MCD_OPC_CheckField, 8, 4, 15, 72, 27, 0, // Skip to: 8183
-/* 1199 */    MCD_OPC_Decode, 221, 23, 247, 1, // Opcode: t2STLEX
-/* 1204 */    MCD_OPC_FilterValue, 15, 62, 27, 0, // Skip to: 8183
-/* 1209 */    MCD_OPC_CheckPredicate, 42, 57, 27, 0, // Skip to: 8183
-/* 1214 */    MCD_OPC_Decode, 223, 23, 248, 1, // Opcode: t2STLEXD
-/* 1219 */    MCD_OPC_FilterValue, 1, 47, 27, 0, // Skip to: 8183
-/* 1224 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 1227 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1249
-/* 1232 */    MCD_OPC_CheckPredicate, 32, 34, 27, 0, // Skip to: 8183
-/* 1237 */    MCD_OPC_CheckField, 8, 4, 15, 27, 27, 0, // Skip to: 8183
-/* 1244 */    MCD_OPC_Decode, 162, 22, 250, 1, // Opcode: t2LDREX
-/* 1249 */    MCD_OPC_FilterValue, 1, 17, 27, 0, // Skip to: 8183
-/* 1254 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 1257 */    MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1280
-/* 1262 */    MCD_OPC_CheckPredicate, 38, 4, 27, 0, // Skip to: 8183
-/* 1267 */    MCD_OPC_CheckField, 8, 8, 240, 1, 252, 26, 0, // Skip to: 8183
-/* 1275 */    MCD_OPC_Decode, 138, 24, 251, 1, // Opcode: t2TBB
-/* 1280 */    MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 1303
-/* 1285 */    MCD_OPC_CheckPredicate, 38, 237, 26, 0, // Skip to: 8183
-/* 1290 */    MCD_OPC_CheckField, 8, 8, 240, 1, 229, 26, 0, // Skip to: 8183
-/* 1298 */    MCD_OPC_Decode, 139, 24, 251, 1, // Opcode: t2TBH
-/* 1303 */    MCD_OPC_FilterValue, 4, 24, 0, 0, // Skip to: 1332
-/* 1308 */    MCD_OPC_CheckPredicate, 32, 214, 26, 0, // Skip to: 8183
-/* 1313 */    MCD_OPC_CheckField, 8, 4, 15, 207, 26, 0, // Skip to: 8183
-/* 1320 */    MCD_OPC_CheckField, 0, 4, 15, 200, 26, 0, // Skip to: 8183
-/* 1327 */    MCD_OPC_Decode, 163, 22, 249, 1, // Opcode: t2LDREXB
-/* 1332 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1361
-/* 1337 */    MCD_OPC_CheckPredicate, 32, 185, 26, 0, // Skip to: 8183
-/* 1342 */    MCD_OPC_CheckField, 8, 4, 15, 178, 26, 0, // Skip to: 8183
-/* 1349 */    MCD_OPC_CheckField, 0, 4, 15, 171, 26, 0, // Skip to: 8183
-/* 1356 */    MCD_OPC_Decode, 165, 22, 249, 1, // Opcode: t2LDREXH
-/* 1361 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1383
-/* 1366 */    MCD_OPC_CheckPredicate, 39, 156, 26, 0, // Skip to: 8183
-/* 1371 */    MCD_OPC_CheckField, 0, 4, 15, 149, 26, 0, // Skip to: 8183
-/* 1378 */    MCD_OPC_Decode, 164, 22, 252, 1, // Opcode: t2LDREXD
-/* 1383 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1412
-/* 1388 */    MCD_OPC_CheckPredicate, 40, 134, 26, 0, // Skip to: 8183
-/* 1393 */    MCD_OPC_CheckField, 8, 4, 15, 127, 26, 0, // Skip to: 8183
-/* 1400 */    MCD_OPC_CheckField, 0, 4, 15, 120, 26, 0, // Skip to: 8183
-/* 1407 */    MCD_OPC_Decode, 254, 21, 249, 1, // Opcode: t2LDAB
-/* 1412 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1441
-/* 1417 */    MCD_OPC_CheckPredicate, 40, 105, 26, 0, // Skip to: 8183
-/* 1422 */    MCD_OPC_CheckField, 8, 4, 15, 98, 26, 0, // Skip to: 8183
-/* 1429 */    MCD_OPC_CheckField, 0, 4, 15, 91, 26, 0, // Skip to: 8183
-/* 1436 */    MCD_OPC_Decode, 131, 22, 249, 1, // Opcode: t2LDAH
-/* 1441 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1470
-/* 1446 */    MCD_OPC_CheckPredicate, 40, 76, 26, 0, // Skip to: 8183
-/* 1451 */    MCD_OPC_CheckField, 8, 4, 15, 69, 26, 0, // Skip to: 8183
-/* 1458 */    MCD_OPC_CheckField, 0, 4, 15, 62, 26, 0, // Skip to: 8183
-/* 1465 */    MCD_OPC_Decode, 253, 21, 249, 1, // Opcode: t2LDA
-/* 1470 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 1499
-/* 1475 */    MCD_OPC_CheckPredicate, 41, 47, 26, 0, // Skip to: 8183
-/* 1480 */    MCD_OPC_CheckField, 8, 4, 15, 40, 26, 0, // Skip to: 8183
-/* 1487 */    MCD_OPC_CheckField, 0, 4, 15, 33, 26, 0, // Skip to: 8183
-/* 1494 */    MCD_OPC_Decode, 128, 22, 249, 1, // Opcode: t2LDAEXB
-/* 1499 */    MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 1528
-/* 1504 */    MCD_OPC_CheckPredicate, 41, 18, 26, 0, // Skip to: 8183
-/* 1509 */    MCD_OPC_CheckField, 8, 4, 15, 11, 26, 0, // Skip to: 8183
-/* 1516 */    MCD_OPC_CheckField, 0, 4, 15, 4, 26, 0, // Skip to: 8183
-/* 1523 */    MCD_OPC_Decode, 130, 22, 249, 1, // Opcode: t2LDAEXH
-/* 1528 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 1557
-/* 1533 */    MCD_OPC_CheckPredicate, 41, 245, 25, 0, // Skip to: 8183
-/* 1538 */    MCD_OPC_CheckField, 8, 4, 15, 238, 25, 0, // Skip to: 8183
-/* 1545 */    MCD_OPC_CheckField, 0, 4, 15, 231, 25, 0, // Skip to: 8183
-/* 1552 */    MCD_OPC_Decode, 255, 21, 249, 1, // Opcode: t2LDAEX
-/* 1557 */    MCD_OPC_FilterValue, 15, 221, 25, 0, // Skip to: 8183
-/* 1562 */    MCD_OPC_CheckPredicate, 42, 216, 25, 0, // Skip to: 8183
-/* 1567 */    MCD_OPC_CheckField, 0, 4, 15, 209, 25, 0, // Skip to: 8183
-/* 1574 */    MCD_OPC_Decode, 129, 22, 252, 1, // Opcode: t2LDAEXD
-/* 1579 */    MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1617
-/* 1584 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 1587 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1602
-/* 1592 */    MCD_OPC_CheckPredicate, 38, 186, 25, 0, // Skip to: 8183
-/* 1597 */    MCD_OPC_Decode, 238, 23, 253, 1, // Opcode: t2STRDi8
-/* 1602 */    MCD_OPC_FilterValue, 1, 176, 25, 0, // Skip to: 8183
-/* 1607 */    MCD_OPC_CheckPredicate, 38, 171, 25, 0, // Skip to: 8183
-/* 1612 */    MCD_OPC_Decode, 161, 22, 253, 1, // Opcode: t2LDRDi8
-/* 1617 */    MCD_OPC_FilterValue, 2, 233, 0, 0, // Skip to: 1855
-/* 1622 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 1625 */    MCD_OPC_FilterValue, 0, 173, 0, 0, // Skip to: 1803
-/* 1630 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 1633 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1673
-/* 1638 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
-/* 1641 */    MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 1702
-/* 1646 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1663
-/* 1651 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1663
-/* 1658 */    MCD_OPC_Decode, 207, 22, 254, 1, // Opcode: t2MOVr
-/* 1663 */    MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1702
-/* 1668 */    MCD_OPC_Decode, 229, 22, 239, 1, // Opcode: t2ORRrr
-/* 1673 */    MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 1702
-/* 1678 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1702
-/* 1683 */    MCD_OPC_CheckField, 16, 4, 15, 12, 0, 0, // Skip to: 1702
-/* 1690 */    MCD_OPC_CheckField, 12, 3, 0, 5, 0, 0, // Skip to: 1702
-/* 1697 */    MCD_OPC_Decode, 136, 23, 255, 1, // Opcode: t2RRX
-/* 1702 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
-/* 1705 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1727
-/* 1710 */    MCD_OPC_CheckPredicate, 38, 78, 0, 0, // Skip to: 1793
-/* 1715 */    MCD_OPC_CheckField, 16, 4, 15, 71, 0, 0, // Skip to: 1793
-/* 1722 */    MCD_OPC_Decode, 194, 22, 128, 2, // Opcode: t2LSLri
-/* 1727 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1749
-/* 1732 */    MCD_OPC_CheckPredicate, 38, 56, 0, 0, // Skip to: 1793
-/* 1737 */    MCD_OPC_CheckField, 16, 4, 15, 49, 0, 0, // Skip to: 1793
-/* 1744 */    MCD_OPC_Decode, 196, 22, 128, 2, // Opcode: t2LSRri
-/* 1749 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1771
-/* 1754 */    MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 1793
-/* 1759 */    MCD_OPC_CheckField, 16, 4, 15, 27, 0, 0, // Skip to: 1793
-/* 1766 */    MCD_OPC_Decode, 209, 21, 128, 2, // Opcode: t2ASRri
-/* 1771 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1793
-/* 1776 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 1793
-/* 1781 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1793
-/* 1788 */    MCD_OPC_Decode, 134, 23, 128, 2, // Opcode: t2RORri
-/* 1793 */    MCD_OPC_CheckPredicate, 38, 241, 24, 0, // Skip to: 8183
-/* 1798 */    MCD_OPC_Decode, 230, 22, 240, 1, // Opcode: t2ORRrs
-/* 1803 */    MCD_OPC_FilterValue, 1, 231, 24, 0, // Skip to: 8183
-/* 1808 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
-/* 1811 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1833
-/* 1816 */    MCD_OPC_CheckPredicate, 43, 218, 24, 0, // Skip to: 8183
-/* 1821 */    MCD_OPC_CheckField, 20, 1, 0, 211, 24, 0, // Skip to: 8183
-/* 1828 */    MCD_OPC_Decode, 231, 22, 129, 2, // Opcode: t2PKHBT
-/* 1833 */    MCD_OPC_FilterValue, 2, 201, 24, 0, // Skip to: 8183
-/* 1838 */    MCD_OPC_CheckPredicate, 43, 196, 24, 0, // Skip to: 8183
-/* 1843 */    MCD_OPC_CheckField, 20, 1, 0, 189, 24, 0, // Skip to: 8183
-/* 1850 */    MCD_OPC_Decode, 232, 22, 129, 2, // Opcode: t2PKHTB
-/* 1855 */    MCD_OPC_FilterValue, 3, 179, 24, 0, // Skip to: 8183
-/* 1860 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 1863 */    MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 1902
-/* 1868 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1892
-/* 1873 */    MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1892
-/* 1880 */    MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1892
-/* 1887 */    MCD_OPC_Decode, 199, 21, 239, 1, // Opcode: t2ADCrr
-/* 1892 */    MCD_OPC_CheckPredicate, 38, 142, 24, 0, // Skip to: 8183
-/* 1897 */    MCD_OPC_Decode, 200, 21, 240, 1, // Opcode: t2ADCrs
-/* 1902 */    MCD_OPC_FilterValue, 1, 132, 24, 0, // Skip to: 8183
-/* 1907 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 1931
-/* 1912 */    MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 1931
-/* 1919 */    MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 1931
-/* 1926 */    MCD_OPC_Decode, 138, 23, 239, 1, // Opcode: t2RSBrr
-/* 1931 */    MCD_OPC_CheckPredicate, 38, 103, 24, 0, // Skip to: 8183
-/* 1936 */    MCD_OPC_Decode, 139, 23, 240, 1, // Opcode: t2RSBrs
-/* 1941 */    MCD_OPC_FilterValue, 3, 93, 24, 0, // Skip to: 8183
-/* 1946 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
-/* 1949 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1987
-/* 1954 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 1957 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1972
-/* 1962 */    MCD_OPC_CheckPredicate, 38, 72, 24, 0, // Skip to: 8183
-/* 1967 */    MCD_OPC_Decode, 236, 23, 130, 2, // Opcode: t2STRD_POST
-/* 1972 */    MCD_OPC_FilterValue, 1, 62, 24, 0, // Skip to: 8183
-/* 1977 */    MCD_OPC_CheckPredicate, 38, 57, 24, 0, // Skip to: 8183
-/* 1982 */    MCD_OPC_Decode, 159, 22, 131, 2, // Opcode: t2LDRD_POST
-/* 1987 */    MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 2050
-/* 1992 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 1995 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2010
-/* 2000 */    MCD_OPC_CheckPredicate, 38, 34, 24, 0, // Skip to: 8183
-/* 2005 */    MCD_OPC_Decode, 237, 23, 132, 2, // Opcode: t2STRD_PRE
-/* 2010 */    MCD_OPC_FilterValue, 1, 24, 24, 0, // Skip to: 8183
-/* 2015 */    MCD_OPC_CheckPredicate, 44, 20, 0, 0, // Skip to: 2040
-/* 2020 */    MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 2040
-/* 2027 */    MCD_OPC_CheckField, 0, 20, 255, 210, 63, 4, 0, 0, // Skip to: 2040
-/* 2036 */    MCD_OPC_Decode, 150, 23, 51, // Opcode: t2SG
-/* 2040 */    MCD_OPC_CheckPredicate, 38, 250, 23, 0, // Skip to: 8183
-/* 2045 */    MCD_OPC_Decode, 160, 22, 133, 2, // Opcode: t2LDRD_PRE
-/* 2050 */    MCD_OPC_FilterValue, 2, 78, 0, 0, // Skip to: 2133
-/* 2055 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 2058 */    MCD_OPC_FilterValue, 0, 232, 23, 0, // Skip to: 8183
-/* 2063 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 2066 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 2106
-/* 2071 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
-/* 2074 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 2106
-/* 2079 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2096
-/* 2084 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2096
-/* 2091 */    MCD_OPC_Decode, 223, 22, 255, 1, // Opcode: t2MVNr
-/* 2096 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 2106
-/* 2101 */    MCD_OPC_Decode, 226, 22, 239, 1, // Opcode: t2ORNrr
-/* 2106 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2123
-/* 2111 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2123
-/* 2118 */    MCD_OPC_Decode, 224, 22, 134, 2, // Opcode: t2MVNs
-/* 2123 */    MCD_OPC_CheckPredicate, 38, 167, 23, 0, // Skip to: 8183
-/* 2128 */    MCD_OPC_Decode, 227, 22, 240, 1, // Opcode: t2ORNrs
-/* 2133 */    MCD_OPC_FilterValue, 3, 157, 23, 0, // Skip to: 8183
-/* 2138 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 2141 */    MCD_OPC_FilterValue, 0, 149, 23, 0, // Skip to: 8183
-/* 2146 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2170
-/* 2151 */    MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2170
-/* 2158 */    MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2170
-/* 2165 */    MCD_OPC_Decode, 144, 23, 239, 1, // Opcode: t2SBCrr
-/* 2170 */    MCD_OPC_CheckPredicate, 38, 120, 23, 0, // Skip to: 8183
-/* 2175 */    MCD_OPC_Decode, 145, 23, 240, 1, // Opcode: t2SBCrs
-/* 2180 */    MCD_OPC_FilterValue, 30, 153, 5, 0, // Skip to: 3618
-/* 2185 */    MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
-/* 2188 */    MCD_OPC_FilterValue, 0, 179, 2, 0, // Skip to: 2884
-/* 2193 */    MCD_OPC_ExtractField, 24, 2,  // Inst{25-24} ...
-/* 2196 */    MCD_OPC_FilterValue, 0, 160, 0, 0, // Skip to: 2361
-/* 2201 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
-/* 2204 */    MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2243
-/* 2209 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2233
-/* 2214 */    MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2233
-/* 2221 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2233
-/* 2228 */    MCD_OPC_Decode, 144, 24, 135, 2, // Opcode: t2TSTri
-/* 2233 */    MCD_OPC_CheckPredicate, 38, 57, 23, 0, // Skip to: 8183
-/* 2238 */    MCD_OPC_Decode, 206, 21, 136, 2, // Opcode: t2ANDri
-/* 2243 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2258
-/* 2248 */    MCD_OPC_CheckPredicate, 38, 42, 23, 0, // Skip to: 8183
-/* 2253 */    MCD_OPC_Decode, 214, 21, 136, 2, // Opcode: t2BICri
-/* 2258 */    MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 2290
-/* 2263 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2280
-/* 2268 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2280
-/* 2275 */    MCD_OPC_Decode, 205, 22, 137, 2, // Opcode: t2MOVi
-/* 2280 */    MCD_OPC_CheckPredicate, 38, 10, 23, 0, // Skip to: 8183
-/* 2285 */    MCD_OPC_Decode, 228, 22, 136, 2, // Opcode: t2ORRri
-/* 2290 */    MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2322
-/* 2295 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2312
-/* 2300 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2312
-/* 2307 */    MCD_OPC_Decode, 222, 22, 137, 2, // Opcode: t2MVNi
-/* 2312 */    MCD_OPC_CheckPredicate, 38, 234, 22, 0, // Skip to: 8183
-/* 2317 */    MCD_OPC_Decode, 225, 22, 136, 2, // Opcode: t2ORNri
-/* 2322 */    MCD_OPC_FilterValue, 4, 224, 22, 0, // Skip to: 8183
-/* 2327 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2351
-/* 2332 */    MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2351
-/* 2339 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2351
-/* 2346 */    MCD_OPC_Decode, 140, 24, 135, 2, // Opcode: t2TEQri
-/* 2351 */    MCD_OPC_CheckPredicate, 38, 195, 22, 0, // Skip to: 8183
-/* 2356 */    MCD_OPC_Decode, 244, 21, 136, 2, // Opcode: t2EORri
-/* 2361 */    MCD_OPC_FilterValue, 1, 126, 0, 0, // Skip to: 2492
-/* 2366 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
-/* 2369 */    MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2408
-/* 2374 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2398
-/* 2379 */    MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2398
-/* 2386 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2398
-/* 2393 */    MCD_OPC_Decode, 223, 21, 135, 2, // Opcode: t2CMNri
-/* 2398 */    MCD_OPC_CheckPredicate, 38, 148, 22, 0, // Skip to: 8183
-/* 2403 */    MCD_OPC_Decode, 201, 21, 138, 2, // Opcode: t2ADDri
-/* 2408 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2423
-/* 2413 */    MCD_OPC_CheckPredicate, 38, 133, 22, 0, // Skip to: 8183
-/* 2418 */    MCD_OPC_Decode, 198, 21, 136, 2, // Opcode: t2ADCri
-/* 2423 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2438
-/* 2428 */    MCD_OPC_CheckPredicate, 38, 118, 22, 0, // Skip to: 8183
-/* 2433 */    MCD_OPC_Decode, 143, 23, 136, 2, // Opcode: t2SBCri
-/* 2438 */    MCD_OPC_FilterValue, 5, 34, 0, 0, // Skip to: 2477
-/* 2443 */    MCD_OPC_CheckPredicate, 38, 19, 0, 0, // Skip to: 2467
-/* 2448 */    MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2467
-/* 2455 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2467
-/* 2462 */    MCD_OPC_Decode, 226, 21, 135, 2, // Opcode: t2CMPri
-/* 2467 */    MCD_OPC_CheckPredicate, 38, 79, 22, 0, // Skip to: 8183
-/* 2472 */    MCD_OPC_Decode, 128, 24, 138, 2, // Opcode: t2SUBri
-/* 2477 */    MCD_OPC_FilterValue, 6, 69, 22, 0, // Skip to: 8183
-/* 2482 */    MCD_OPC_CheckPredicate, 38, 64, 22, 0, // Skip to: 8183
-/* 2487 */    MCD_OPC_Decode, 137, 23, 136, 2, // Opcode: t2RSBri
-/* 2492 */    MCD_OPC_FilterValue, 2, 132, 0, 0, // Skip to: 2629
-/* 2497 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
-/* 2500 */    MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2577
-/* 2505 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 2508 */    MCD_OPC_FilterValue, 0, 38, 22, 0, // Skip to: 8183
-/* 2513 */    MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
-/* 2516 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2538
-/* 2521 */    MCD_OPC_CheckPredicate, 38, 34, 0, 0, // Skip to: 2560
-/* 2526 */    MCD_OPC_CheckField, 23, 1, 0, 27, 0, 0, // Skip to: 2560
-/* 2533 */    MCD_OPC_Decode, 202, 21, 139, 2, // Opcode: t2ADDri12
-/* 2538 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2560
-/* 2543 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2560
-/* 2548 */    MCD_OPC_CheckField, 23, 1, 1, 5, 0, 0, // Skip to: 2560
-/* 2555 */    MCD_OPC_Decode, 129, 24, 139, 2, // Opcode: t2SUBri12
-/* 2560 */    MCD_OPC_CheckPredicate, 38, 242, 21, 0, // Skip to: 8183
-/* 2565 */    MCD_OPC_CheckField, 16, 4, 15, 235, 21, 0, // Skip to: 8183
-/* 2572 */    MCD_OPC_Decode, 205, 21, 140, 2, // Opcode: t2ADR
-/* 2577 */    MCD_OPC_FilterValue, 1, 225, 21, 0, // Skip to: 8183
-/* 2582 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 2585 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2607
-/* 2590 */    MCD_OPC_CheckPredicate, 32, 212, 21, 0, // Skip to: 8183
-/* 2595 */    MCD_OPC_CheckField, 20, 2, 0, 205, 21, 0, // Skip to: 8183
-/* 2602 */    MCD_OPC_Decode, 206, 22, 141, 2, // Opcode: t2MOVi16
-/* 2607 */    MCD_OPC_FilterValue, 1, 195, 21, 0, // Skip to: 8183
-/* 2612 */    MCD_OPC_CheckPredicate, 32, 190, 21, 0, // Skip to: 8183
-/* 2617 */    MCD_OPC_CheckField, 20, 2, 0, 183, 21, 0, // Skip to: 8183
-/* 2624 */    MCD_OPC_Decode, 204, 22, 141, 2, // Opcode: t2MOVTi16
-/* 2629 */    MCD_OPC_FilterValue, 3, 173, 21, 0, // Skip to: 8183
-/* 2634 */    MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
-/* 2637 */    MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 2714
-/* 2642 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 2645 */    MCD_OPC_FilterValue, 0, 157, 21, 0, // Skip to: 8183
-/* 2650 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 2653 */    MCD_OPC_FilterValue, 0, 149, 21, 0, // Skip to: 8183
-/* 2658 */    MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
-/* 2661 */    MCD_OPC_FilterValue, 0, 141, 21, 0, // Skip to: 8183
-/* 2666 */    MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2704
-/* 2671 */    MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2704
-/* 2678 */    MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2704
-/* 2685 */    MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2704
-/* 2692 */    MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2704
-/* 2699 */    MCD_OPC_Decode, 199, 23, 142, 2, // Opcode: t2SSAT16
-/* 2704 */    MCD_OPC_CheckPredicate, 38, 98, 21, 0, // Skip to: 8183
-/* 2709 */    MCD_OPC_Decode, 198, 23, 143, 2, // Opcode: t2SSAT
-/* 2714 */    MCD_OPC_FilterValue, 1, 66, 0, 0, // Skip to: 2785
-/* 2719 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 2722 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2737
-/* 2727 */    MCD_OPC_CheckPredicate, 38, 75, 21, 0, // Skip to: 8183
-/* 2732 */    MCD_OPC_Decode, 146, 23, 144, 2, // Opcode: t2SBFX
-/* 2737 */    MCD_OPC_FilterValue, 2, 65, 21, 0, // Skip to: 8183
-/* 2742 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 2745 */    MCD_OPC_FilterValue, 0, 57, 21, 0, // Skip to: 8183
-/* 2750 */    MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
-/* 2753 */    MCD_OPC_FilterValue, 0, 49, 21, 0, // Skip to: 8183
-/* 2758 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 2775
-/* 2763 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2775
-/* 2770 */    MCD_OPC_Decode, 212, 21, 145, 2, // Opcode: t2BFC
-/* 2775 */    MCD_OPC_CheckPredicate, 38, 27, 21, 0, // Skip to: 8183
-/* 2780 */    MCD_OPC_Decode, 213, 21, 146, 2, // Opcode: t2BFI
-/* 2785 */    MCD_OPC_FilterValue, 2, 72, 0, 0, // Skip to: 2862
-/* 2790 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
-/* 2793 */    MCD_OPC_FilterValue, 0, 9, 21, 0, // Skip to: 8183
-/* 2798 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 2801 */    MCD_OPC_FilterValue, 0, 1, 21, 0, // Skip to: 8183
-/* 2806 */    MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
-/* 2809 */    MCD_OPC_FilterValue, 0, 249, 20, 0, // Skip to: 8183
-/* 2814 */    MCD_OPC_CheckPredicate, 45, 33, 0, 0, // Skip to: 2852
-/* 2819 */    MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2852
-/* 2826 */    MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2852
-/* 2833 */    MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2852
-/* 2840 */    MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2852
-/* 2847 */    MCD_OPC_Decode, 175, 24, 142, 2, // Opcode: t2USAT16
-/* 2852 */    MCD_OPC_CheckPredicate, 38, 206, 20, 0, // Skip to: 8183
-/* 2857 */    MCD_OPC_Decode, 174, 24, 143, 2, // Opcode: t2USAT
-/* 2862 */    MCD_OPC_FilterValue, 3, 196, 20, 0, // Skip to: 8183
-/* 2867 */    MCD_OPC_CheckPredicate, 38, 191, 20, 0, // Skip to: 8183
-/* 2872 */    MCD_OPC_CheckField, 20, 2, 0, 184, 20, 0, // Skip to: 8183
-/* 2879 */    MCD_OPC_Decode, 154, 24, 144, 2, // Opcode: t2UBFX
-/* 2884 */    MCD_OPC_FilterValue, 1, 174, 20, 0, // Skip to: 8183
-/* 2889 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
-/* 2892 */    MCD_OPC_FilterValue, 0, 187, 2, 0, // Skip to: 3596
-/* 2897 */    MCD_OPC_ExtractField, 14, 1,  // Inst{14} ...
-/* 2900 */    MCD_OPC_FilterValue, 0, 158, 20, 0, // Skip to: 8183
-/* 2905 */    MCD_OPC_ExtractField, 0, 12,  // Inst{11-0} ...
-/* 2908 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2937
-/* 2913 */    MCD_OPC_CheckPredicate, 46, 166, 0, 0, // Skip to: 3084
-/* 2918 */    MCD_OPC_CheckField, 16, 11, 143, 15, 158, 0, 0, // Skip to: 3084
-/* 2926 */    MCD_OPC_CheckField, 13, 1, 0, 151, 0, 0, // Skip to: 3084
-/* 2933 */    MCD_OPC_Decode, 239, 21, 51, // Opcode: t2DCPS1
-/* 2937 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 2966
-/* 2942 */    MCD_OPC_CheckPredicate, 46, 137, 0, 0, // Skip to: 3084
-/* 2947 */    MCD_OPC_CheckField, 16, 11, 143, 15, 129, 0, 0, // Skip to: 3084
-/* 2955 */    MCD_OPC_CheckField, 13, 1, 0, 122, 0, 0, // Skip to: 3084
-/* 2962 */    MCD_OPC_Decode, 240, 21, 51, // Opcode: t2DCPS2
-/* 2966 */    MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 2995
-/* 2971 */    MCD_OPC_CheckPredicate, 46, 108, 0, 0, // Skip to: 3084
-/* 2976 */    MCD_OPC_CheckField, 16, 11, 143, 15, 100, 0, 0, // Skip to: 3084
-/* 2984 */    MCD_OPC_CheckField, 13, 1, 0, 93, 0, 0, // Skip to: 3084
-/* 2991 */    MCD_OPC_Decode, 241, 21, 51, // Opcode: t2DCPS3
-/* 2995 */    MCD_OPC_FilterValue, 18, 24, 0, 0, // Skip to: 3024
-/* 3000 */    MCD_OPC_CheckPredicate, 47, 79, 0, 0, // Skip to: 3084
-/* 3005 */    MCD_OPC_CheckField, 16, 11, 175, 7, 71, 0, 0, // Skip to: 3084
-/* 3013 */    MCD_OPC_CheckField, 13, 1, 0, 64, 0, 0, // Skip to: 3084
-/* 3020 */    MCD_OPC_Decode, 143, 24, 51, // Opcode: t2TSB
-/* 3024 */    MCD_OPC_FilterValue, 128, 30, 24, 0, 0, // Skip to: 3054
-/* 3030 */    MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3084
-/* 3035 */    MCD_OPC_CheckField, 20, 7, 60, 42, 0, 0, // Skip to: 3084
-/* 3042 */    MCD_OPC_CheckField, 13, 1, 0, 35, 0, 0, // Skip to: 3084
-/* 3049 */    MCD_OPC_Decode, 217, 21, 147, 2, // Opcode: t2BXJ
-/* 3054 */    MCD_OPC_FilterValue, 175, 30, 24, 0, 0, // Skip to: 3084
-/* 3060 */    MCD_OPC_CheckPredicate, 48, 19, 0, 0, // Skip to: 3084
-/* 3065 */    MCD_OPC_CheckField, 16, 11, 191, 7, 11, 0, 0, // Skip to: 3084
-/* 3073 */    MCD_OPC_CheckField, 13, 1, 0, 4, 0, 0, // Skip to: 3084
-/* 3080 */    MCD_OPC_Decode, 221, 21, 51, // Opcode: t2CLREX
-/* 3084 */    MCD_OPC_ExtractField, 16, 11,  // Inst{26-16} ...
-/* 3087 */    MCD_OPC_FilterValue, 175, 7, 131, 0, 0, // Skip to: 3224
-/* 3093 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 3096 */    MCD_OPC_FilterValue, 0, 68, 0, 0, // Skip to: 3169
-/* 3101 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
-/* 3104 */    MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 3389
-/* 3109 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
-/* 3112 */    MCD_OPC_FilterValue, 0, 16, 1, 0, // Skip to: 3389
-/* 3117 */    MCD_OPC_ExtractField, 9, 2,  // Inst{10-9} ...
-/* 3120 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3152
-/* 3125 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3142
-/* 3130 */    MCD_OPC_CheckField, 4, 4, 15, 5, 0, 0, // Skip to: 3142
-/* 3137 */    MCD_OPC_Decode, 238, 21, 148, 2, // Opcode: t2DBG
-/* 3142 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3152
-/* 3147 */    MCD_OPC_Decode, 247, 21, 226, 1, // Opcode: t2HINT
-/* 3152 */    MCD_OPC_CheckPredicate, 39, 232, 0, 0, // Skip to: 3389
-/* 3157 */    MCD_OPC_CheckField, 0, 5, 0, 225, 0, 0, // Skip to: 3389
-/* 3164 */    MCD_OPC_Decode, 230, 21, 149, 2, // Opcode: t2CPS2p
-/* 3169 */    MCD_OPC_FilterValue, 1, 215, 0, 0, // Skip to: 3389
-/* 3174 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
-/* 3177 */    MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 3389
-/* 3182 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
-/* 3185 */    MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 3389
-/* 3190 */    MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3214
-/* 3195 */    MCD_OPC_CheckField, 9, 2, 0, 12, 0, 0, // Skip to: 3214
-/* 3202 */    MCD_OPC_CheckField, 5, 3, 0, 5, 0, 0, // Skip to: 3214
-/* 3209 */    MCD_OPC_Decode, 229, 21, 149, 2, // Opcode: t2CPS1p
-/* 3214 */    MCD_OPC_CheckPredicate, 39, 170, 0, 0, // Skip to: 3389
-/* 3219 */    MCD_OPC_Decode, 231, 21, 149, 2, // Opcode: t2CPS3p
-/* 3224 */    MCD_OPC_FilterValue, 191, 7, 69, 0, 0, // Skip to: 3299
-/* 3230 */    MCD_OPC_ExtractField, 4, 8,  // Inst{11-4} ...
-/* 3233 */    MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 3255
-/* 3239 */    MCD_OPC_CheckPredicate, 49, 145, 0, 0, // Skip to: 3389
-/* 3244 */    MCD_OPC_CheckField, 13, 1, 0, 138, 0, 0, // Skip to: 3389
-/* 3251 */    MCD_OPC_Decode, 243, 21, 61, // Opcode: t2DSB
-/* 3255 */    MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 3277
-/* 3261 */    MCD_OPC_CheckPredicate, 49, 123, 0, 0, // Skip to: 3389
-/* 3266 */    MCD_OPC_CheckField, 13, 1, 0, 116, 0, 0, // Skip to: 3389
-/* 3273 */    MCD_OPC_Decode, 242, 21, 61, // Opcode: t2DMB
-/* 3277 */    MCD_OPC_FilterValue, 246, 1, 106, 0, 0, // Skip to: 3389
-/* 3283 */    MCD_OPC_CheckPredicate, 49, 101, 0, 0, // Skip to: 3389
-/* 3288 */    MCD_OPC_CheckField, 13, 1, 0, 94, 0, 0, // Skip to: 3389
-/* 3295 */    MCD_OPC_Decode, 249, 21, 62, // Opcode: t2ISB
-/* 3299 */    MCD_OPC_FilterValue, 222, 7, 24, 0, 0, // Skip to: 3329
-/* 3305 */    MCD_OPC_CheckPredicate, 39, 79, 0, 0, // Skip to: 3389
-/* 3310 */    MCD_OPC_CheckField, 13, 1, 0, 72, 0, 0, // Skip to: 3389
-/* 3317 */    MCD_OPC_CheckField, 8, 4, 15, 65, 0, 0, // Skip to: 3389
-/* 3324 */    MCD_OPC_Decode, 255, 23, 226, 1, // Opcode: t2SUBS_PC_LR
-/* 3329 */    MCD_OPC_FilterValue, 239, 7, 24, 0, 0, // Skip to: 3359
-/* 3335 */    MCD_OPC_CheckPredicate, 39, 49, 0, 0, // Skip to: 3389
-/* 3340 */    MCD_OPC_CheckField, 13, 1, 0, 42, 0, 0, // Skip to: 3389
-/* 3347 */    MCD_OPC_CheckField, 0, 8, 0, 35, 0, 0, // Skip to: 3389
-/* 3354 */    MCD_OPC_Decode, 214, 22, 150, 2, // Opcode: t2MRS_AR
-/* 3359 */    MCD_OPC_FilterValue, 255, 7, 24, 0, 0, // Skip to: 3389
-/* 3365 */    MCD_OPC_CheckPredicate, 39, 19, 0, 0, // Skip to: 3389
-/* 3370 */    MCD_OPC_CheckField, 13, 1, 0, 12, 0, 0, // Skip to: 3389
-/* 3377 */    MCD_OPC_CheckField, 0, 8, 0, 5, 0, 0, // Skip to: 3389
-/* 3384 */    MCD_OPC_Decode, 217, 22, 150, 2, // Opcode: t2MRSsys_AR
-/* 3389 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
-/* 3392 */    MCD_OPC_FilterValue, 0, 122, 0, 0, // Skip to: 3519
-/* 3397 */    MCD_OPC_ExtractField, 21, 6,  // Inst{26-21} ...
-/* 3400 */    MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3452
-/* 3405 */    MCD_OPC_ExtractField, 5, 3,  // Inst{7-5} ...
-/* 3408 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3430
-/* 3413 */    MCD_OPC_CheckPredicate, 39, 123, 0, 0, // Skip to: 3541
-/* 3418 */    MCD_OPC_CheckField, 0, 5, 0, 116, 0, 0, // Skip to: 3541
-/* 3425 */    MCD_OPC_Decode, 218, 22, 151, 2, // Opcode: t2MSR_AR
-/* 3430 */    MCD_OPC_FilterValue, 1, 106, 0, 0, // Skip to: 3541
-/* 3435 */    MCD_OPC_CheckPredicate, 50, 101, 0, 0, // Skip to: 3541
-/* 3440 */    MCD_OPC_CheckField, 0, 4, 0, 94, 0, 0, // Skip to: 3541
-/* 3447 */    MCD_OPC_Decode, 220, 22, 152, 2, // Opcode: t2MSRbanked
-/* 3452 */    MCD_OPC_FilterValue, 31, 24, 0, 0, // Skip to: 3481
-/* 3457 */    MCD_OPC_CheckPredicate, 50, 79, 0, 0, // Skip to: 3541
-/* 3462 */    MCD_OPC_CheckField, 5, 3, 1, 72, 0, 0, // Skip to: 3541
-/* 3469 */    MCD_OPC_CheckField, 0, 4, 0, 65, 0, 0, // Skip to: 3541
-/* 3476 */    MCD_OPC_Decode, 216, 22, 153, 2, // Opcode: t2MRSbanked
-/* 3481 */    MCD_OPC_FilterValue, 63, 55, 0, 0, // Skip to: 3541
-/* 3486 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 3489 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3504
-/* 3494 */    MCD_OPC_CheckPredicate, 51, 42, 0, 0, // Skip to: 3541
-/* 3499 */    MCD_OPC_Decode, 248, 21, 154, 2, // Opcode: t2HVC
-/* 3504 */    MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 3541
-/* 3509 */    MCD_OPC_CheckPredicate, 52, 27, 0, 0, // Skip to: 3541
-/* 3514 */    MCD_OPC_Decode, 157, 23, 155, 2, // Opcode: t2SMC
-/* 3519 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3541
-/* 3524 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3541
-/* 3529 */    MCD_OPC_CheckField, 20, 7, 127, 5, 0, 0, // Skip to: 3541
-/* 3536 */    MCD_OPC_Decode, 155, 24, 154, 2, // Opcode: t2UDF
-/* 3541 */    MCD_OPC_ExtractField, 21, 6,  // Inst{26-21} ...
-/* 3544 */    MCD_OPC_FilterValue, 28, 15, 0, 0, // Skip to: 3564
-/* 3549 */    MCD_OPC_CheckPredicate, 53, 32, 0, 0, // Skip to: 3586
-/* 3554 */    MCD_OPC_SoftFail, 128, 198, 64 /* 0x102300 */, 0,
-/* 3559 */    MCD_OPC_Decode, 219, 22, 156, 2, // Opcode: t2MSR_M
-/* 3564 */    MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 3586
-/* 3569 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 3586
-/* 3574 */    MCD_OPC_SoftFail, 128, 192, 64 /* 0x102000 */, 128, 128, 60 /* 0xf0000 */,
-/* 3581 */    MCD_OPC_Decode, 215, 22, 157, 2, // Opcode: t2MRS_M
-/* 3586 */    MCD_OPC_CheckPredicate, 38, 240, 17, 0, // Skip to: 8183
-/* 3591 */    MCD_OPC_Decode, 218, 21, 158, 2, // Opcode: t2Bcc
-/* 3596 */    MCD_OPC_FilterValue, 1, 230, 17, 0, // Skip to: 8183
-/* 3601 */    MCD_OPC_CheckPredicate, 32, 225, 17, 0, // Skip to: 8183
-/* 3606 */    MCD_OPC_CheckField, 14, 1, 0, 218, 17, 0, // Skip to: 8183
-/* 3613 */    MCD_OPC_Decode, 211, 21, 159, 2, // Opcode: t2B
-/* 3618 */    MCD_OPC_FilterValue, 31, 208, 17, 0, // Skip to: 8183
-/* 3623 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
-/* 3626 */    MCD_OPC_FilterValue, 0, 96, 6, 0, // Skip to: 5263
-/* 3631 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
-/* 3634 */    MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 3995
-/* 3639 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 3642 */    MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 3772
-/* 3647 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 3650 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 3757
-/* 3655 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 3658 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3680
-/* 3663 */    MCD_OPC_CheckPredicate, 38, 163, 17, 0, // Skip to: 8183
-/* 3668 */    MCD_OPC_CheckField, 6, 4, 0, 156, 17, 0, // Skip to: 8183
-/* 3675 */    MCD_OPC_Decode, 235, 23, 160, 2, // Opcode: t2STRBs
-/* 3680 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3702
-/* 3685 */    MCD_OPC_CheckPredicate, 38, 141, 17, 0, // Skip to: 8183
-/* 3690 */    MCD_OPC_CheckField, 8, 1, 1, 134, 17, 0, // Skip to: 8183
-/* 3697 */    MCD_OPC_Decode, 231, 23, 161, 2, // Opcode: t2STRB_POST
-/* 3702 */    MCD_OPC_FilterValue, 3, 124, 17, 0, // Skip to: 8183
-/* 3707 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 3710 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3742
-/* 3715 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3732
-/* 3720 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 3732
-/* 3727 */    MCD_OPC_Decode, 230, 23, 162, 2, // Opcode: t2STRBT
-/* 3732 */    MCD_OPC_CheckPredicate, 38, 94, 17, 0, // Skip to: 8183
-/* 3737 */    MCD_OPC_Decode, 234, 23, 163, 2, // Opcode: t2STRBi8
-/* 3742 */    MCD_OPC_FilterValue, 1, 84, 17, 0, // Skip to: 8183
-/* 3747 */    MCD_OPC_CheckPredicate, 38, 79, 17, 0, // Skip to: 8183
-/* 3752 */    MCD_OPC_Decode, 232, 23, 161, 2, // Opcode: t2STRB_PRE
-/* 3757 */    MCD_OPC_FilterValue, 1, 69, 17, 0, // Skip to: 8183
-/* 3762 */    MCD_OPC_CheckPredicate, 38, 64, 17, 0, // Skip to: 8183
-/* 3767 */    MCD_OPC_Decode, 233, 23, 164, 2, // Opcode: t2STRBi12
-/* 3772 */    MCD_OPC_FilterValue, 1, 54, 17, 0, // Skip to: 8183
-/* 3777 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 3780 */    MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 3928
-/* 3785 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 3788 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 3828
-/* 3793 */    MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
-/* 3796 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 3960
-/* 3801 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3818
-/* 3806 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3818
-/* 3813 */    MCD_OPC_Decode, 239, 22, 165, 2, // Opcode: t2PLDs
-/* 3818 */    MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 3960
-/* 3823 */    MCD_OPC_Decode, 158, 22, 165, 2, // Opcode: t2LDRBs
-/* 3828 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3850
-/* 3833 */    MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 3960
-/* 3838 */    MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 3960
-/* 3845 */    MCD_OPC_Decode, 153, 22, 161, 2, // Opcode: t2LDRB_POST
-/* 3850 */    MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 3960
-/* 3855 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 3858 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 3913
-/* 3863 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
-/* 3866 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3888
-/* 3871 */    MCD_OPC_CheckPredicate, 38, 27, 0, 0, // Skip to: 3903
-/* 3876 */    MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 3903
-/* 3883 */    MCD_OPC_Decode, 237, 22, 166, 2, // Opcode: t2PLDi8
-/* 3888 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3903
-/* 3893 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3903
-/* 3898 */    MCD_OPC_Decode, 152, 22, 167, 2, // Opcode: t2LDRBT
-/* 3903 */    MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 3960
-/* 3908 */    MCD_OPC_Decode, 156, 22, 166, 2, // Opcode: t2LDRBi8
-/* 3913 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 3960
-/* 3918 */    MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 3960
-/* 3923 */    MCD_OPC_Decode, 154, 22, 161, 2, // Opcode: t2LDRB_PRE
-/* 3928 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 3960
-/* 3933 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3950
-/* 3938 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3950
-/* 3945 */    MCD_OPC_Decode, 236, 22, 168, 2, // Opcode: t2PLDi12
-/* 3950 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 3960
-/* 3955 */    MCD_OPC_Decode, 155, 22, 168, 2, // Opcode: t2LDRBi12
-/* 3960 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 3963 */    MCD_OPC_FilterValue, 15, 119, 16, 0, // Skip to: 8183
-/* 3968 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 3985
-/* 3973 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 3985
-/* 3980 */    MCD_OPC_Decode, 238, 22, 169, 2, // Opcode: t2PLDpci
-/* 3985 */    MCD_OPC_CheckPredicate, 38, 97, 16, 0, // Skip to: 8183
-/* 3990 */    MCD_OPC_Decode, 157, 22, 169, 2, // Opcode: t2LDRBpci
-/* 3995 */    MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 4226
-/* 4000 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4003 */    MCD_OPC_FilterValue, 1, 79, 16, 0, // Skip to: 8183
-/* 4008 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 4011 */    MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 4159
-/* 4016 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 4019 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4059
-/* 4024 */    MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
-/* 4027 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 4191
-/* 4032 */    MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4049
-/* 4037 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4049
-/* 4044 */    MCD_OPC_Decode, 243, 22, 165, 2, // Opcode: t2PLIs
-/* 4049 */    MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 4191
-/* 4054 */    MCD_OPC_Decode, 179, 22, 165, 2, // Opcode: t2LDRSBs
-/* 4059 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4081
-/* 4064 */    MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 4191
-/* 4069 */    MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 4191
-/* 4076 */    MCD_OPC_Decode, 174, 22, 161, 2, // Opcode: t2LDRSB_POST
-/* 4081 */    MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 4191
-/* 4086 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 4089 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 4144
-/* 4094 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
-/* 4097 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4119
-/* 4102 */    MCD_OPC_CheckPredicate, 54, 27, 0, 0, // Skip to: 4134
-/* 4107 */    MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 4134
-/* 4114 */    MCD_OPC_Decode, 241, 22, 166, 2, // Opcode: t2PLIi8
-/* 4119 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4134
-/* 4124 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4134
-/* 4129 */    MCD_OPC_Decode, 173, 22, 167, 2, // Opcode: t2LDRSBT
-/* 4134 */    MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 4191
-/* 4139 */    MCD_OPC_Decode, 177, 22, 166, 2, // Opcode: t2LDRSBi8
-/* 4144 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4191
-/* 4149 */    MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 4191
-/* 4154 */    MCD_OPC_Decode, 175, 22, 161, 2, // Opcode: t2LDRSB_PRE
-/* 4159 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 4191
-/* 4164 */    MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4181
-/* 4169 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4181
-/* 4176 */    MCD_OPC_Decode, 240, 22, 168, 2, // Opcode: t2PLIi12
-/* 4181 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 4191
-/* 4186 */    MCD_OPC_Decode, 176, 22, 168, 2, // Opcode: t2LDRSBi12
-/* 4191 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 4194 */    MCD_OPC_FilterValue, 15, 144, 15, 0, // Skip to: 8183
-/* 4199 */    MCD_OPC_CheckPredicate, 54, 12, 0, 0, // Skip to: 4216
-/* 4204 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4216
-/* 4211 */    MCD_OPC_Decode, 242, 22, 169, 2, // Opcode: t2PLIpci
-/* 4216 */    MCD_OPC_CheckPredicate, 38, 122, 15, 0, // Skip to: 8183
-/* 4221 */    MCD_OPC_Decode, 178, 22, 169, 2, // Opcode: t2LDRSBpci
-/* 4226 */    MCD_OPC_FilterValue, 2, 207, 2, 0, // Skip to: 4950
-/* 4231 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 4234 */    MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 4654
-/* 4239 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 4242 */    MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 4324
-/* 4247 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 4250 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4272
-/* 4255 */    MCD_OPC_CheckPredicate, 38, 83, 15, 0, // Skip to: 8183
-/* 4260 */    MCD_OPC_CheckField, 12, 4, 15, 76, 15, 0, // Skip to: 8183
-/* 4267 */    MCD_OPC_Decode, 195, 22, 239, 1, // Opcode: t2LSLrr
-/* 4272 */    MCD_OPC_FilterValue, 1, 66, 15, 0, // Skip to: 8183
-/* 4277 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4280 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4302
-/* 4285 */    MCD_OPC_CheckPredicate, 45, 53, 15, 0, // Skip to: 8183
-/* 4290 */    MCD_OPC_CheckField, 12, 4, 15, 46, 15, 0, // Skip to: 8183
-/* 4297 */    MCD_OPC_Decode, 141, 23, 170, 2, // Opcode: t2SADD8
-/* 4302 */    MCD_OPC_FilterValue, 1, 36, 15, 0, // Skip to: 8183
-/* 4307 */    MCD_OPC_CheckPredicate, 45, 31, 15, 0, // Skip to: 8183
-/* 4312 */    MCD_OPC_CheckField, 12, 4, 15, 24, 15, 0, // Skip to: 8183
-/* 4319 */    MCD_OPC_Decode, 140, 23, 170, 2, // Opcode: t2SADD16
-/* 4324 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 4390
-/* 4329 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4332 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4361
-/* 4337 */    MCD_OPC_CheckPredicate, 45, 1, 15, 0, // Skip to: 8183
-/* 4342 */    MCD_OPC_CheckField, 23, 1, 1, 250, 14, 0, // Skip to: 8183
-/* 4349 */    MCD_OPC_CheckField, 12, 4, 15, 243, 14, 0, // Skip to: 8183
-/* 4356 */    MCD_OPC_Decode, 246, 22, 170, 2, // Opcode: t2QADD8
-/* 4361 */    MCD_OPC_FilterValue, 1, 233, 14, 0, // Skip to: 8183
-/* 4366 */    MCD_OPC_CheckPredicate, 45, 228, 14, 0, // Skip to: 8183
-/* 4371 */    MCD_OPC_CheckField, 23, 1, 1, 221, 14, 0, // Skip to: 8183
-/* 4378 */    MCD_OPC_CheckField, 12, 4, 15, 214, 14, 0, // Skip to: 8183
-/* 4385 */    MCD_OPC_Decode, 245, 22, 170, 2, // Opcode: t2QADD16
-/* 4390 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 4456
-/* 4395 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4398 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4427
-/* 4403 */    MCD_OPC_CheckPredicate, 45, 191, 14, 0, // Skip to: 8183
-/* 4408 */    MCD_OPC_CheckField, 23, 1, 1, 184, 14, 0, // Skip to: 8183
-/* 4415 */    MCD_OPC_CheckField, 12, 4, 15, 177, 14, 0, // Skip to: 8183
-/* 4422 */    MCD_OPC_Decode, 152, 23, 170, 2, // Opcode: t2SHADD8
-/* 4427 */    MCD_OPC_FilterValue, 1, 167, 14, 0, // Skip to: 8183
-/* 4432 */    MCD_OPC_CheckPredicate, 45, 162, 14, 0, // Skip to: 8183
-/* 4437 */    MCD_OPC_CheckField, 23, 1, 1, 155, 14, 0, // Skip to: 8183
-/* 4444 */    MCD_OPC_CheckField, 12, 4, 15, 148, 14, 0, // Skip to: 8183
-/* 4451 */    MCD_OPC_Decode, 151, 23, 170, 2, // Opcode: t2SHADD16
-/* 4456 */    MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 4522
-/* 4461 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4464 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4493
-/* 4469 */    MCD_OPC_CheckPredicate, 45, 125, 14, 0, // Skip to: 8183
-/* 4474 */    MCD_OPC_CheckField, 23, 1, 1, 118, 14, 0, // Skip to: 8183
-/* 4481 */    MCD_OPC_CheckField, 12, 4, 15, 111, 14, 0, // Skip to: 8183
-/* 4488 */    MCD_OPC_Decode, 152, 24, 170, 2, // Opcode: t2UADD8
-/* 4493 */    MCD_OPC_FilterValue, 1, 101, 14, 0, // Skip to: 8183
-/* 4498 */    MCD_OPC_CheckPredicate, 45, 96, 14, 0, // Skip to: 8183
-/* 4503 */    MCD_OPC_CheckField, 23, 1, 1, 89, 14, 0, // Skip to: 8183
-/* 4510 */    MCD_OPC_CheckField, 12, 4, 15, 82, 14, 0, // Skip to: 8183
-/* 4517 */    MCD_OPC_Decode, 151, 24, 170, 2, // Opcode: t2UADD16
-/* 4522 */    MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 4588
-/* 4527 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4530 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4559
-/* 4535 */    MCD_OPC_CheckPredicate, 45, 59, 14, 0, // Skip to: 8183
-/* 4540 */    MCD_OPC_CheckField, 23, 1, 1, 52, 14, 0, // Skip to: 8183
-/* 4547 */    MCD_OPC_CheckField, 12, 4, 15, 45, 14, 0, // Skip to: 8183
-/* 4554 */    MCD_OPC_Decode, 167, 24, 170, 2, // Opcode: t2UQADD8
-/* 4559 */    MCD_OPC_FilterValue, 1, 35, 14, 0, // Skip to: 8183
-/* 4564 */    MCD_OPC_CheckPredicate, 45, 30, 14, 0, // Skip to: 8183
-/* 4569 */    MCD_OPC_CheckField, 23, 1, 1, 23, 14, 0, // Skip to: 8183
-/* 4576 */    MCD_OPC_CheckField, 12, 4, 15, 16, 14, 0, // Skip to: 8183
-/* 4583 */    MCD_OPC_Decode, 166, 24, 170, 2, // Opcode: t2UQADD16
-/* 4588 */    MCD_OPC_FilterValue, 6, 6, 14, 0, // Skip to: 8183
-/* 4593 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4596 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 4625
-/* 4601 */    MCD_OPC_CheckPredicate, 45, 249, 13, 0, // Skip to: 8183
-/* 4606 */    MCD_OPC_CheckField, 23, 1, 1, 242, 13, 0, // Skip to: 8183
-/* 4613 */    MCD_OPC_CheckField, 12, 4, 15, 235, 13, 0, // Skip to: 8183
-/* 4620 */    MCD_OPC_Decode, 158, 24, 170, 2, // Opcode: t2UHADD8
-/* 4625 */    MCD_OPC_FilterValue, 1, 225, 13, 0, // Skip to: 8183
-/* 4630 */    MCD_OPC_CheckPredicate, 45, 220, 13, 0, // Skip to: 8183
-/* 4635 */    MCD_OPC_CheckField, 23, 1, 1, 213, 13, 0, // Skip to: 8183
-/* 4642 */    MCD_OPC_CheckField, 12, 4, 15, 206, 13, 0, // Skip to: 8183
-/* 4649 */    MCD_OPC_Decode, 157, 24, 170, 2, // Opcode: t2UHADD16
-/* 4654 */    MCD_OPC_FilterValue, 1, 196, 13, 0, // Skip to: 8183
-/* 4659 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4662 */    MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 4806
-/* 4667 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 4670 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4710
-/* 4675 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 4678 */    MCD_OPC_FilterValue, 15, 172, 13, 0, // Skip to: 8183
-/* 4683 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4700
-/* 4688 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4700
-/* 4695 */    MCD_OPC_Decode, 137, 24, 171, 2, // Opcode: t2SXTH
-/* 4700 */    MCD_OPC_CheckPredicate, 43, 150, 13, 0, // Skip to: 8183
-/* 4705 */    MCD_OPC_Decode, 134, 24, 172, 2, // Opcode: t2SXTAH
-/* 4710 */    MCD_OPC_FilterValue, 1, 140, 13, 0, // Skip to: 8183
-/* 4715 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 4718 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4740
-/* 4723 */    MCD_OPC_CheckPredicate, 45, 127, 13, 0, // Skip to: 8183
-/* 4728 */    MCD_OPC_CheckField, 12, 4, 15, 120, 13, 0, // Skip to: 8183
-/* 4735 */    MCD_OPC_Decode, 244, 22, 173, 2, // Opcode: t2QADD
-/* 4740 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4762
-/* 4745 */    MCD_OPC_CheckPredicate, 45, 105, 13, 0, // Skip to: 8183
-/* 4750 */    MCD_OPC_CheckField, 12, 4, 15, 98, 13, 0, // Skip to: 8183
-/* 4757 */    MCD_OPC_Decode, 248, 22, 173, 2, // Opcode: t2QDADD
-/* 4762 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4784
-/* 4767 */    MCD_OPC_CheckPredicate, 45, 83, 13, 0, // Skip to: 8183
-/* 4772 */    MCD_OPC_CheckField, 12, 4, 15, 76, 13, 0, // Skip to: 8183
-/* 4779 */    MCD_OPC_Decode, 251, 22, 173, 2, // Opcode: t2QSUB
-/* 4784 */    MCD_OPC_FilterValue, 3, 66, 13, 0, // Skip to: 8183
-/* 4789 */    MCD_OPC_CheckPredicate, 45, 61, 13, 0, // Skip to: 8183
-/* 4794 */    MCD_OPC_CheckField, 12, 4, 15, 54, 13, 0, // Skip to: 8183
-/* 4801 */    MCD_OPC_Decode, 249, 22, 173, 2, // Opcode: t2QDSUB
-/* 4806 */    MCD_OPC_FilterValue, 1, 44, 13, 0, // Skip to: 8183
-/* 4811 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 4814 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4854
-/* 4819 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 4822 */    MCD_OPC_FilterValue, 15, 28, 13, 0, // Skip to: 8183
-/* 4827 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4844
-/* 4832 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 4844
-/* 4839 */    MCD_OPC_Decode, 184, 24, 171, 2, // Opcode: t2UXTH
-/* 4844 */    MCD_OPC_CheckPredicate, 43, 6, 13, 0, // Skip to: 8183
-/* 4849 */    MCD_OPC_Decode, 181, 24, 172, 2, // Opcode: t2UXTAH
-/* 4854 */    MCD_OPC_FilterValue, 1, 252, 12, 0, // Skip to: 8183
-/* 4859 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 4862 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4884
-/* 4867 */    MCD_OPC_CheckPredicate, 38, 239, 12, 0, // Skip to: 8183
-/* 4872 */    MCD_OPC_CheckField, 12, 4, 15, 232, 12, 0, // Skip to: 8183
-/* 4879 */    MCD_OPC_Decode, 255, 22, 174, 2, // Opcode: t2REV
-/* 4884 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4906
-/* 4889 */    MCD_OPC_CheckPredicate, 38, 217, 12, 0, // Skip to: 8183
-/* 4894 */    MCD_OPC_CheckField, 12, 4, 15, 210, 12, 0, // Skip to: 8183
-/* 4901 */    MCD_OPC_Decode, 128, 23, 174, 2, // Opcode: t2REV16
-/* 4906 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4928
-/* 4911 */    MCD_OPC_CheckPredicate, 38, 195, 12, 0, // Skip to: 8183
-/* 4916 */    MCD_OPC_CheckField, 12, 4, 15, 188, 12, 0, // Skip to: 8183
-/* 4923 */    MCD_OPC_Decode, 254, 22, 174, 2, // Opcode: t2RBIT
-/* 4928 */    MCD_OPC_FilterValue, 3, 178, 12, 0, // Skip to: 8183
-/* 4933 */    MCD_OPC_CheckPredicate, 38, 173, 12, 0, // Skip to: 8183
-/* 4938 */    MCD_OPC_CheckField, 12, 4, 15, 166, 12, 0, // Skip to: 8183
-/* 4945 */    MCD_OPC_Decode, 129, 23, 174, 2, // Opcode: t2REVSH
-/* 4950 */    MCD_OPC_FilterValue, 3, 156, 12, 0, // Skip to: 8183
-/* 4955 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 4958 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 5061
-/* 4963 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 4966 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5021
-/* 4971 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 4974 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5006
-/* 4979 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 4996
-/* 4984 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4996
-/* 4991 */    MCD_OPC_Decode, 221, 22, 170, 2, // Opcode: t2MUL
-/* 4996 */    MCD_OPC_CheckPredicate, 38, 110, 12, 0, // Skip to: 8183
-/* 5001 */    MCD_OPC_Decode, 202, 22, 175, 2, // Opcode: t2MLA
-/* 5006 */    MCD_OPC_FilterValue, 1, 100, 12, 0, // Skip to: 8183
-/* 5011 */    MCD_OPC_CheckPredicate, 38, 95, 12, 0, // Skip to: 8183
-/* 5016 */    MCD_OPC_Decode, 187, 23, 176, 2, // Opcode: t2SMULL
-/* 5021 */    MCD_OPC_FilterValue, 1, 85, 12, 0, // Skip to: 8183
-/* 5026 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5029 */    MCD_OPC_FilterValue, 0, 77, 12, 0, // Skip to: 8183
-/* 5034 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5051
-/* 5039 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5051
-/* 5046 */    MCD_OPC_Decode, 185, 23, 170, 2, // Opcode: t2SMULBB
-/* 5051 */    MCD_OPC_CheckPredicate, 45, 55, 12, 0, // Skip to: 8183
-/* 5056 */    MCD_OPC_Decode, 158, 23, 175, 2, // Opcode: t2SMLABB
-/* 5061 */    MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 5131
-/* 5066 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5069 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5091
-/* 5074 */    MCD_OPC_CheckPredicate, 38, 32, 12, 0, // Skip to: 8183
-/* 5079 */    MCD_OPC_CheckField, 23, 1, 0, 25, 12, 0, // Skip to: 8183
-/* 5086 */    MCD_OPC_Decode, 203, 22, 175, 2, // Opcode: t2MLS
-/* 5091 */    MCD_OPC_FilterValue, 1, 15, 12, 0, // Skip to: 8183
-/* 5096 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5099 */    MCD_OPC_FilterValue, 0, 7, 12, 0, // Skip to: 8183
-/* 5104 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5121
-/* 5109 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5121
-/* 5116 */    MCD_OPC_Decode, 186, 23, 170, 2, // Opcode: t2SMULBT
-/* 5121 */    MCD_OPC_CheckPredicate, 45, 241, 11, 0, // Skip to: 8183
-/* 5126 */    MCD_OPC_Decode, 159, 23, 175, 2, // Opcode: t2SMLABT
-/* 5131 */    MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 5179
-/* 5136 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5139 */    MCD_OPC_FilterValue, 1, 223, 11, 0, // Skip to: 8183
-/* 5144 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5147 */    MCD_OPC_FilterValue, 0, 215, 11, 0, // Skip to: 8183
-/* 5152 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5169
-/* 5157 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5169
-/* 5164 */    MCD_OPC_Decode, 188, 23, 170, 2, // Opcode: t2SMULTB
-/* 5169 */    MCD_OPC_CheckPredicate, 45, 193, 11, 0, // Skip to: 8183
-/* 5174 */    MCD_OPC_Decode, 169, 23, 175, 2, // Opcode: t2SMLATB
-/* 5179 */    MCD_OPC_FilterValue, 3, 43, 0, 0, // Skip to: 5227
-/* 5184 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5187 */    MCD_OPC_FilterValue, 1, 175, 11, 0, // Skip to: 8183
-/* 5192 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5195 */    MCD_OPC_FilterValue, 0, 167, 11, 0, // Skip to: 8183
-/* 5200 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5217
-/* 5205 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5217
-/* 5212 */    MCD_OPC_Decode, 189, 23, 170, 2, // Opcode: t2SMULTT
-/* 5217 */    MCD_OPC_CheckPredicate, 45, 145, 11, 0, // Skip to: 8183
-/* 5222 */    MCD_OPC_Decode, 170, 23, 175, 2, // Opcode: t2SMLATT
-/* 5227 */    MCD_OPC_FilterValue, 15, 135, 11, 0, // Skip to: 8183
-/* 5232 */    MCD_OPC_CheckPredicate, 55, 130, 11, 0, // Skip to: 8183
-/* 5237 */    MCD_OPC_CheckField, 23, 1, 1, 123, 11, 0, // Skip to: 8183
-/* 5244 */    MCD_OPC_CheckField, 20, 1, 1, 116, 11, 0, // Skip to: 8183
-/* 5251 */    MCD_OPC_CheckField, 12, 4, 15, 109, 11, 0, // Skip to: 8183
-/* 5258 */    MCD_OPC_Decode, 147, 23, 170, 2, // Opcode: t2SDIV
-/* 5263 */    MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 6421
-/* 5268 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
-/* 5271 */    MCD_OPC_FilterValue, 0, 82, 1, 0, // Skip to: 5614
-/* 5276 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5279 */    MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 5409
-/* 5284 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5287 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5394
-/* 5292 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 5295 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5317
-/* 5300 */    MCD_OPC_CheckPredicate, 38, 62, 11, 0, // Skip to: 8183
-/* 5305 */    MCD_OPC_CheckField, 6, 4, 0, 55, 11, 0, // Skip to: 8183
-/* 5312 */    MCD_OPC_Decode, 248, 23, 160, 2, // Opcode: t2STRHs
-/* 5317 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5339
-/* 5322 */    MCD_OPC_CheckPredicate, 38, 40, 11, 0, // Skip to: 8183
-/* 5327 */    MCD_OPC_CheckField, 8, 1, 1, 33, 11, 0, // Skip to: 8183
-/* 5334 */    MCD_OPC_Decode, 244, 23, 161, 2, // Opcode: t2STRH_POST
-/* 5339 */    MCD_OPC_FilterValue, 3, 23, 11, 0, // Skip to: 8183
-/* 5344 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 5347 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5379
-/* 5352 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5369
-/* 5357 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5369
-/* 5364 */    MCD_OPC_Decode, 243, 23, 162, 2, // Opcode: t2STRHT
-/* 5369 */    MCD_OPC_CheckPredicate, 38, 249, 10, 0, // Skip to: 8183
-/* 5374 */    MCD_OPC_Decode, 247, 23, 163, 2, // Opcode: t2STRHi8
-/* 5379 */    MCD_OPC_FilterValue, 1, 239, 10, 0, // Skip to: 8183
-/* 5384 */    MCD_OPC_CheckPredicate, 38, 234, 10, 0, // Skip to: 8183
-/* 5389 */    MCD_OPC_Decode, 245, 23, 161, 2, // Opcode: t2STRH_PRE
-/* 5394 */    MCD_OPC_FilterValue, 1, 224, 10, 0, // Skip to: 8183
-/* 5399 */    MCD_OPC_CheckPredicate, 38, 219, 10, 0, // Skip to: 8183
-/* 5404 */    MCD_OPC_Decode, 246, 23, 164, 2, // Opcode: t2STRHi12
-/* 5409 */    MCD_OPC_FilterValue, 1, 209, 10, 0, // Skip to: 8183
-/* 5414 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5417 */    MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 5565
-/* 5422 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 5425 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5465
-/* 5430 */    MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
-/* 5433 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 5597
-/* 5438 */    MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5455
-/* 5443 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5455
-/* 5450 */    MCD_OPC_Decode, 235, 22, 165, 2, // Opcode: t2PLDWs
-/* 5455 */    MCD_OPC_CheckPredicate, 38, 137, 0, 0, // Skip to: 5597
-/* 5460 */    MCD_OPC_Decode, 172, 22, 165, 2, // Opcode: t2LDRHs
-/* 5465 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5487
-/* 5470 */    MCD_OPC_CheckPredicate, 38, 122, 0, 0, // Skip to: 5597
-/* 5475 */    MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 5597
-/* 5482 */    MCD_OPC_Decode, 167, 22, 161, 2, // Opcode: t2LDRH_POST
-/* 5487 */    MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 5597
-/* 5492 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 5495 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5550
-/* 5500 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
-/* 5503 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5525
-/* 5508 */    MCD_OPC_CheckPredicate, 56, 27, 0, 0, // Skip to: 5540
-/* 5513 */    MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 5540
-/* 5520 */    MCD_OPC_Decode, 234, 22, 166, 2, // Opcode: t2PLDWi8
-/* 5525 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5540
-/* 5530 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5540
-/* 5535 */    MCD_OPC_Decode, 166, 22, 167, 2, // Opcode: t2LDRHT
-/* 5540 */    MCD_OPC_CheckPredicate, 38, 52, 0, 0, // Skip to: 5597
-/* 5545 */    MCD_OPC_Decode, 170, 22, 166, 2, // Opcode: t2LDRHi8
-/* 5550 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 5597
-/* 5555 */    MCD_OPC_CheckPredicate, 38, 37, 0, 0, // Skip to: 5597
-/* 5560 */    MCD_OPC_Decode, 168, 22, 161, 2, // Opcode: t2LDRH_PRE
-/* 5565 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5597
-/* 5570 */    MCD_OPC_CheckPredicate, 56, 12, 0, 0, // Skip to: 5587
-/* 5575 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5587
-/* 5582 */    MCD_OPC_Decode, 233, 22, 168, 2, // Opcode: t2PLDWi12
-/* 5587 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5597
-/* 5592 */    MCD_OPC_Decode, 169, 22, 168, 2, // Opcode: t2LDRHi12
-/* 5597 */    MCD_OPC_CheckPredicate, 38, 21, 10, 0, // Skip to: 8183
-/* 5602 */    MCD_OPC_CheckField, 16, 4, 15, 14, 10, 0, // Skip to: 8183
-/* 5609 */    MCD_OPC_Decode, 171, 22, 169, 2, // Opcode: t2LDRHpci
-/* 5614 */    MCD_OPC_FilterValue, 1, 150, 0, 0, // Skip to: 5769
-/* 5619 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 5622 */    MCD_OPC_FilterValue, 1, 252, 9, 0, // Skip to: 8183
-/* 5627 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5630 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 5737
-/* 5635 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 5638 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5660
-/* 5643 */    MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 5752
-/* 5648 */    MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 5752
-/* 5655 */    MCD_OPC_Decode, 186, 22, 165, 2, // Opcode: t2LDRSHs
-/* 5660 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5682
-/* 5665 */    MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 5752
-/* 5670 */    MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 5752
-/* 5677 */    MCD_OPC_Decode, 181, 22, 161, 2, // Opcode: t2LDRSH_POST
-/* 5682 */    MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 5752
-/* 5687 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 5690 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5722
-/* 5695 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 5712
-/* 5700 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 5712
-/* 5707 */    MCD_OPC_Decode, 180, 22, 167, 2, // Opcode: t2LDRSHT
-/* 5712 */    MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 5752
-/* 5717 */    MCD_OPC_Decode, 184, 22, 166, 2, // Opcode: t2LDRSHi8
-/* 5722 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 5752
-/* 5727 */    MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 5752
-/* 5732 */    MCD_OPC_Decode, 182, 22, 161, 2, // Opcode: t2LDRSH_PRE
-/* 5737 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5752
-/* 5742 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 5752
-/* 5747 */    MCD_OPC_Decode, 183, 22, 168, 2, // Opcode: t2LDRSHi12
-/* 5752 */    MCD_OPC_CheckPredicate, 38, 122, 9, 0, // Skip to: 8183
-/* 5757 */    MCD_OPC_CheckField, 16, 4, 15, 115, 9, 0, // Skip to: 8183
-/* 5764 */    MCD_OPC_Decode, 185, 22, 169, 2, // Opcode: t2LDRSHpci
-/* 5769 */    MCD_OPC_FilterValue, 2, 156, 1, 0, // Skip to: 6186
-/* 5774 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 5777 */    MCD_OPC_FilterValue, 0, 242, 0, 0, // Skip to: 6024
-/* 5782 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 5785 */    MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 5844
-/* 5790 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 5793 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5815
-/* 5798 */    MCD_OPC_CheckPredicate, 38, 76, 9, 0, // Skip to: 8183
-/* 5803 */    MCD_OPC_CheckField, 12, 4, 15, 69, 9, 0, // Skip to: 8183
-/* 5810 */    MCD_OPC_Decode, 197, 22, 239, 1, // Opcode: t2LSRrr
-/* 5815 */    MCD_OPC_FilterValue, 1, 59, 9, 0, // Skip to: 8183
-/* 5820 */    MCD_OPC_CheckPredicate, 45, 54, 9, 0, // Skip to: 8183
-/* 5825 */    MCD_OPC_CheckField, 20, 1, 0, 47, 9, 0, // Skip to: 8183
-/* 5832 */    MCD_OPC_CheckField, 12, 4, 15, 40, 9, 0, // Skip to: 8183
-/* 5839 */    MCD_OPC_Decode, 142, 23, 170, 2, // Opcode: t2SASX
-/* 5844 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5880
-/* 5849 */    MCD_OPC_CheckPredicate, 45, 25, 9, 0, // Skip to: 8183
-/* 5854 */    MCD_OPC_CheckField, 23, 1, 1, 18, 9, 0, // Skip to: 8183
-/* 5861 */    MCD_OPC_CheckField, 20, 1, 0, 11, 9, 0, // Skip to: 8183
-/* 5868 */    MCD_OPC_CheckField, 12, 4, 15, 4, 9, 0, // Skip to: 8183
-/* 5875 */    MCD_OPC_Decode, 247, 22, 170, 2, // Opcode: t2QASX
-/* 5880 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 5916
-/* 5885 */    MCD_OPC_CheckPredicate, 45, 245, 8, 0, // Skip to: 8183
-/* 5890 */    MCD_OPC_CheckField, 23, 1, 1, 238, 8, 0, // Skip to: 8183
-/* 5897 */    MCD_OPC_CheckField, 20, 1, 0, 231, 8, 0, // Skip to: 8183
-/* 5904 */    MCD_OPC_CheckField, 12, 4, 15, 224, 8, 0, // Skip to: 8183
-/* 5911 */    MCD_OPC_Decode, 153, 23, 170, 2, // Opcode: t2SHASX
-/* 5916 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 5952
-/* 5921 */    MCD_OPC_CheckPredicate, 45, 209, 8, 0, // Skip to: 8183
-/* 5926 */    MCD_OPC_CheckField, 23, 1, 1, 202, 8, 0, // Skip to: 8183
-/* 5933 */    MCD_OPC_CheckField, 20, 1, 0, 195, 8, 0, // Skip to: 8183
-/* 5940 */    MCD_OPC_CheckField, 12, 4, 15, 188, 8, 0, // Skip to: 8183
-/* 5947 */    MCD_OPC_Decode, 153, 24, 170, 2, // Opcode: t2UASX
-/* 5952 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 5988
-/* 5957 */    MCD_OPC_CheckPredicate, 45, 173, 8, 0, // Skip to: 8183
-/* 5962 */    MCD_OPC_CheckField, 23, 1, 1, 166, 8, 0, // Skip to: 8183
-/* 5969 */    MCD_OPC_CheckField, 20, 1, 0, 159, 8, 0, // Skip to: 8183
-/* 5976 */    MCD_OPC_CheckField, 12, 4, 15, 152, 8, 0, // Skip to: 8183
-/* 5983 */    MCD_OPC_Decode, 168, 24, 170, 2, // Opcode: t2UQASX
-/* 5988 */    MCD_OPC_FilterValue, 6, 142, 8, 0, // Skip to: 8183
-/* 5993 */    MCD_OPC_CheckPredicate, 45, 137, 8, 0, // Skip to: 8183
-/* 5998 */    MCD_OPC_CheckField, 23, 1, 1, 130, 8, 0, // Skip to: 8183
-/* 6005 */    MCD_OPC_CheckField, 20, 1, 0, 123, 8, 0, // Skip to: 8183
-/* 6012 */    MCD_OPC_CheckField, 12, 4, 15, 116, 8, 0, // Skip to: 8183
-/* 6019 */    MCD_OPC_Decode, 159, 24, 170, 2, // Opcode: t2UHASX
-/* 6024 */    MCD_OPC_FilterValue, 1, 106, 8, 0, // Skip to: 8183
-/* 6029 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6032 */    MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 6109
-/* 6037 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6040 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6080
-/* 6045 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 6048 */    MCD_OPC_FilterValue, 15, 82, 8, 0, // Skip to: 8183
-/* 6053 */    MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6070
-/* 6058 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6070
-/* 6065 */    MCD_OPC_Decode, 136, 24, 171, 2, // Opcode: t2SXTB16
-/* 6070 */    MCD_OPC_CheckPredicate, 43, 60, 8, 0, // Skip to: 8183
-/* 6075 */    MCD_OPC_Decode, 133, 24, 172, 2, // Opcode: t2SXTAB16
-/* 6080 */    MCD_OPC_FilterValue, 1, 50, 8, 0, // Skip to: 8183
-/* 6085 */    MCD_OPC_CheckPredicate, 45, 45, 8, 0, // Skip to: 8183
-/* 6090 */    MCD_OPC_CheckField, 12, 4, 15, 38, 8, 0, // Skip to: 8183
-/* 6097 */    MCD_OPC_CheckField, 4, 3, 0, 31, 8, 0, // Skip to: 8183
-/* 6104 */    MCD_OPC_Decode, 148, 23, 177, 2, // Opcode: t2SEL
-/* 6109 */    MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 8183
-/* 6114 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6117 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6157
-/* 6122 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 6125 */    MCD_OPC_FilterValue, 15, 5, 8, 0, // Skip to: 8183
-/* 6130 */    MCD_OPC_CheckPredicate, 43, 12, 0, 0, // Skip to: 6147
-/* 6135 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6147
-/* 6142 */    MCD_OPC_Decode, 183, 24, 171, 2, // Opcode: t2UXTB16
-/* 6147 */    MCD_OPC_CheckPredicate, 43, 239, 7, 0, // Skip to: 8183
-/* 6152 */    MCD_OPC_Decode, 180, 24, 172, 2, // Opcode: t2UXTAB16
-/* 6157 */    MCD_OPC_FilterValue, 1, 229, 7, 0, // Skip to: 8183
-/* 6162 */    MCD_OPC_CheckPredicate, 38, 224, 7, 0, // Skip to: 8183
-/* 6167 */    MCD_OPC_CheckField, 12, 4, 15, 217, 7, 0, // Skip to: 8183
-/* 6174 */    MCD_OPC_CheckField, 4, 3, 0, 210, 7, 0, // Skip to: 8183
-/* 6181 */    MCD_OPC_Decode, 222, 21, 174, 2, // Opcode: t2CLZ
-/* 6186 */    MCD_OPC_FilterValue, 3, 200, 7, 0, // Skip to: 8183
-/* 6191 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 6194 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 6297
-/* 6199 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6202 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 6257
-/* 6207 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6210 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6242
-/* 6215 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6232
-/* 6220 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6232
-/* 6227 */    MCD_OPC_Decode, 183, 23, 170, 2, // Opcode: t2SMUAD
-/* 6232 */    MCD_OPC_CheckPredicate, 45, 154, 7, 0, // Skip to: 8183
-/* 6237 */    MCD_OPC_Decode, 160, 23, 175, 2, // Opcode: t2SMLAD
-/* 6242 */    MCD_OPC_FilterValue, 1, 144, 7, 0, // Skip to: 8183
-/* 6247 */    MCD_OPC_CheckPredicate, 38, 139, 7, 0, // Skip to: 8183
-/* 6252 */    MCD_OPC_Decode, 165, 24, 176, 2, // Opcode: t2UMULL
-/* 6257 */    MCD_OPC_FilterValue, 1, 129, 7, 0, // Skip to: 8183
-/* 6262 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6265 */    MCD_OPC_FilterValue, 0, 121, 7, 0, // Skip to: 8183
-/* 6270 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6287
-/* 6275 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6287
-/* 6282 */    MCD_OPC_Decode, 190, 23, 170, 2, // Opcode: t2SMULWB
-/* 6287 */    MCD_OPC_CheckPredicate, 45, 99, 7, 0, // Skip to: 8183
-/* 6292 */    MCD_OPC_Decode, 171, 23, 175, 2, // Opcode: t2SMLAWB
-/* 6297 */    MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 6385
-/* 6302 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6305 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6345
-/* 6310 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6313 */    MCD_OPC_FilterValue, 0, 73, 7, 0, // Skip to: 8183
-/* 6318 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6335
-/* 6323 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6335
-/* 6330 */    MCD_OPC_Decode, 184, 23, 170, 2, // Opcode: t2SMUADX
-/* 6335 */    MCD_OPC_CheckPredicate, 45, 51, 7, 0, // Skip to: 8183
-/* 6340 */    MCD_OPC_Decode, 161, 23, 175, 2, // Opcode: t2SMLADX
-/* 6345 */    MCD_OPC_FilterValue, 1, 41, 7, 0, // Skip to: 8183
-/* 6350 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6353 */    MCD_OPC_FilterValue, 0, 33, 7, 0, // Skip to: 8183
-/* 6358 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6375
-/* 6363 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6375
-/* 6370 */    MCD_OPC_Decode, 191, 23, 170, 2, // Opcode: t2SMULWT
-/* 6375 */    MCD_OPC_CheckPredicate, 45, 11, 7, 0, // Skip to: 8183
-/* 6380 */    MCD_OPC_Decode, 172, 23, 175, 2, // Opcode: t2SMLAWT
-/* 6385 */    MCD_OPC_FilterValue, 15, 1, 7, 0, // Skip to: 8183
-/* 6390 */    MCD_OPC_CheckPredicate, 55, 252, 6, 0, // Skip to: 8183
-/* 6395 */    MCD_OPC_CheckField, 23, 1, 1, 245, 6, 0, // Skip to: 8183
-/* 6402 */    MCD_OPC_CheckField, 20, 1, 1, 238, 6, 0, // Skip to: 8183
-/* 6409 */    MCD_OPC_CheckField, 12, 4, 15, 231, 6, 0, // Skip to: 8183
-/* 6416 */    MCD_OPC_Decode, 156, 24, 170, 2, // Opcode: t2UDIV
-/* 6421 */    MCD_OPC_FilterValue, 2, 107, 5, 0, // Skip to: 7813
-/* 6426 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
-/* 6429 */    MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 6714
-/* 6434 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6437 */    MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 6567
-/* 6442 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6445 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6552
-/* 6450 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 6453 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6475
-/* 6458 */    MCD_OPC_CheckPredicate, 38, 184, 6, 0, // Skip to: 8183
-/* 6463 */    MCD_OPC_CheckField, 6, 4, 0, 177, 6, 0, // Skip to: 8183
-/* 6470 */    MCD_OPC_Decode, 254, 23, 178, 2, // Opcode: t2STRs
-/* 6475 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6497
-/* 6480 */    MCD_OPC_CheckPredicate, 38, 162, 6, 0, // Skip to: 8183
-/* 6485 */    MCD_OPC_CheckField, 8, 1, 1, 155, 6, 0, // Skip to: 8183
-/* 6492 */    MCD_OPC_Decode, 250, 23, 161, 2, // Opcode: t2STR_POST
-/* 6497 */    MCD_OPC_FilterValue, 3, 145, 6, 0, // Skip to: 8183
-/* 6502 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 6505 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6537
-/* 6510 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6527
-/* 6515 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6527
-/* 6522 */    MCD_OPC_Decode, 249, 23, 162, 2, // Opcode: t2STRT
-/* 6527 */    MCD_OPC_CheckPredicate, 38, 115, 6, 0, // Skip to: 8183
-/* 6532 */    MCD_OPC_Decode, 253, 23, 179, 2, // Opcode: t2STRi8
-/* 6537 */    MCD_OPC_FilterValue, 1, 105, 6, 0, // Skip to: 8183
-/* 6542 */    MCD_OPC_CheckPredicate, 38, 100, 6, 0, // Skip to: 8183
-/* 6547 */    MCD_OPC_Decode, 251, 23, 161, 2, // Opcode: t2STR_PRE
-/* 6552 */    MCD_OPC_FilterValue, 1, 90, 6, 0, // Skip to: 8183
-/* 6557 */    MCD_OPC_CheckPredicate, 38, 85, 6, 0, // Skip to: 8183
-/* 6562 */    MCD_OPC_Decode, 252, 23, 180, 2, // Opcode: t2STRi12
-/* 6567 */    MCD_OPC_FilterValue, 1, 75, 6, 0, // Skip to: 8183
-/* 6572 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6575 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6682
-/* 6580 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
-/* 6583 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6605
-/* 6588 */    MCD_OPC_CheckPredicate, 38, 104, 0, 0, // Skip to: 6697
-/* 6593 */    MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 6697
-/* 6600 */    MCD_OPC_Decode, 193, 22, 165, 2, // Opcode: t2LDRs
-/* 6605 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6627
-/* 6610 */    MCD_OPC_CheckPredicate, 38, 82, 0, 0, // Skip to: 6697
-/* 6615 */    MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 6697
-/* 6622 */    MCD_OPC_Decode, 188, 22, 161, 2, // Opcode: t2LDR_POST
-/* 6627 */    MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 6697
-/* 6632 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
-/* 6635 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6667
-/* 6640 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 6657
-/* 6645 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6657
-/* 6652 */    MCD_OPC_Decode, 187, 22, 167, 2, // Opcode: t2LDRT
-/* 6657 */    MCD_OPC_CheckPredicate, 38, 35, 0, 0, // Skip to: 6697
-/* 6662 */    MCD_OPC_Decode, 191, 22, 166, 2, // Opcode: t2LDRi8
-/* 6667 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 6697
-/* 6672 */    MCD_OPC_CheckPredicate, 38, 20, 0, 0, // Skip to: 6697
-/* 6677 */    MCD_OPC_Decode, 189, 22, 161, 2, // Opcode: t2LDR_PRE
-/* 6682 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6697
-/* 6687 */    MCD_OPC_CheckPredicate, 38, 5, 0, 0, // Skip to: 6697
-/* 6692 */    MCD_OPC_Decode, 190, 22, 168, 2, // Opcode: t2LDRi12
-/* 6697 */    MCD_OPC_CheckPredicate, 38, 201, 5, 0, // Skip to: 8183
-/* 6702 */    MCD_OPC_CheckField, 16, 4, 15, 194, 5, 0, // Skip to: 8183
-/* 6709 */    MCD_OPC_Decode, 192, 22, 169, 2, // Opcode: t2LDRpci
-/* 6714 */    MCD_OPC_FilterValue, 2, 163, 2, 0, // Skip to: 7394
-/* 6719 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 6722 */    MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 7142
-/* 6727 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 6730 */    MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 6812
-/* 6735 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 6738 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6760
-/* 6743 */    MCD_OPC_CheckPredicate, 38, 155, 5, 0, // Skip to: 8183
-/* 6748 */    MCD_OPC_CheckField, 12, 4, 15, 148, 5, 0, // Skip to: 8183
-/* 6755 */    MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: t2ASRrr
-/* 6760 */    MCD_OPC_FilterValue, 1, 138, 5, 0, // Skip to: 8183
-/* 6765 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6768 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6790
-/* 6773 */    MCD_OPC_CheckPredicate, 45, 125, 5, 0, // Skip to: 8183
-/* 6778 */    MCD_OPC_CheckField, 12, 4, 15, 118, 5, 0, // Skip to: 8183
-/* 6785 */    MCD_OPC_Decode, 202, 23, 170, 2, // Opcode: t2SSUB8
-/* 6790 */    MCD_OPC_FilterValue, 1, 108, 5, 0, // Skip to: 8183
-/* 6795 */    MCD_OPC_CheckPredicate, 45, 103, 5, 0, // Skip to: 8183
-/* 6800 */    MCD_OPC_CheckField, 12, 4, 15, 96, 5, 0, // Skip to: 8183
-/* 6807 */    MCD_OPC_Decode, 201, 23, 170, 2, // Opcode: t2SSUB16
-/* 6812 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 6878
-/* 6817 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6820 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6849
-/* 6825 */    MCD_OPC_CheckPredicate, 45, 73, 5, 0, // Skip to: 8183
-/* 6830 */    MCD_OPC_CheckField, 23, 1, 1, 66, 5, 0, // Skip to: 8183
-/* 6837 */    MCD_OPC_CheckField, 12, 4, 15, 59, 5, 0, // Skip to: 8183
-/* 6844 */    MCD_OPC_Decode, 253, 22, 170, 2, // Opcode: t2QSUB8
-/* 6849 */    MCD_OPC_FilterValue, 1, 49, 5, 0, // Skip to: 8183
-/* 6854 */    MCD_OPC_CheckPredicate, 45, 44, 5, 0, // Skip to: 8183
-/* 6859 */    MCD_OPC_CheckField, 23, 1, 1, 37, 5, 0, // Skip to: 8183
-/* 6866 */    MCD_OPC_CheckField, 12, 4, 15, 30, 5, 0, // Skip to: 8183
-/* 6873 */    MCD_OPC_Decode, 252, 22, 170, 2, // Opcode: t2QSUB16
-/* 6878 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 6944
-/* 6883 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6886 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6915
-/* 6891 */    MCD_OPC_CheckPredicate, 45, 7, 5, 0, // Skip to: 8183
-/* 6896 */    MCD_OPC_CheckField, 23, 1, 1, 0, 5, 0, // Skip to: 8183
-/* 6903 */    MCD_OPC_CheckField, 12, 4, 15, 249, 4, 0, // Skip to: 8183
-/* 6910 */    MCD_OPC_Decode, 156, 23, 170, 2, // Opcode: t2SHSUB8
-/* 6915 */    MCD_OPC_FilterValue, 1, 239, 4, 0, // Skip to: 8183
-/* 6920 */    MCD_OPC_CheckPredicate, 45, 234, 4, 0, // Skip to: 8183
-/* 6925 */    MCD_OPC_CheckField, 23, 1, 1, 227, 4, 0, // Skip to: 8183
-/* 6932 */    MCD_OPC_CheckField, 12, 4, 15, 220, 4, 0, // Skip to: 8183
-/* 6939 */    MCD_OPC_Decode, 155, 23, 170, 2, // Opcode: t2SHSUB16
-/* 6944 */    MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 7010
-/* 6949 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 6952 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 6981
-/* 6957 */    MCD_OPC_CheckPredicate, 45, 197, 4, 0, // Skip to: 8183
-/* 6962 */    MCD_OPC_CheckField, 23, 1, 1, 190, 4, 0, // Skip to: 8183
-/* 6969 */    MCD_OPC_CheckField, 12, 4, 15, 183, 4, 0, // Skip to: 8183
-/* 6976 */    MCD_OPC_Decode, 178, 24, 170, 2, // Opcode: t2USUB8
-/* 6981 */    MCD_OPC_FilterValue, 1, 173, 4, 0, // Skip to: 8183
-/* 6986 */    MCD_OPC_CheckPredicate, 45, 168, 4, 0, // Skip to: 8183
-/* 6991 */    MCD_OPC_CheckField, 23, 1, 1, 161, 4, 0, // Skip to: 8183
-/* 6998 */    MCD_OPC_CheckField, 12, 4, 15, 154, 4, 0, // Skip to: 8183
-/* 7005 */    MCD_OPC_Decode, 177, 24, 170, 2, // Opcode: t2USUB16
-/* 7010 */    MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 7076
-/* 7015 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7018 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7047
-/* 7023 */    MCD_OPC_CheckPredicate, 45, 131, 4, 0, // Skip to: 8183
-/* 7028 */    MCD_OPC_CheckField, 23, 1, 1, 124, 4, 0, // Skip to: 8183
-/* 7035 */    MCD_OPC_CheckField, 12, 4, 15, 117, 4, 0, // Skip to: 8183
-/* 7042 */    MCD_OPC_Decode, 171, 24, 170, 2, // Opcode: t2UQSUB8
-/* 7047 */    MCD_OPC_FilterValue, 1, 107, 4, 0, // Skip to: 8183
-/* 7052 */    MCD_OPC_CheckPredicate, 45, 102, 4, 0, // Skip to: 8183
-/* 7057 */    MCD_OPC_CheckField, 23, 1, 1, 95, 4, 0, // Skip to: 8183
-/* 7064 */    MCD_OPC_CheckField, 12, 4, 15, 88, 4, 0, // Skip to: 8183
-/* 7071 */    MCD_OPC_Decode, 170, 24, 170, 2, // Opcode: t2UQSUB16
-/* 7076 */    MCD_OPC_FilterValue, 6, 78, 4, 0, // Skip to: 8183
-/* 7081 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7084 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7113
-/* 7089 */    MCD_OPC_CheckPredicate, 45, 65, 4, 0, // Skip to: 8183
-/* 7094 */    MCD_OPC_CheckField, 23, 1, 1, 58, 4, 0, // Skip to: 8183
-/* 7101 */    MCD_OPC_CheckField, 12, 4, 15, 51, 4, 0, // Skip to: 8183
-/* 7108 */    MCD_OPC_Decode, 162, 24, 170, 2, // Opcode: t2UHSUB8
-/* 7113 */    MCD_OPC_FilterValue, 1, 41, 4, 0, // Skip to: 8183
-/* 7118 */    MCD_OPC_CheckPredicate, 45, 36, 4, 0, // Skip to: 8183
-/* 7123 */    MCD_OPC_CheckField, 23, 1, 1, 29, 4, 0, // Skip to: 8183
-/* 7130 */    MCD_OPC_CheckField, 12, 4, 15, 22, 4, 0, // Skip to: 8183
-/* 7137 */    MCD_OPC_Decode, 161, 24, 170, 2, // Opcode: t2UHSUB16
-/* 7142 */    MCD_OPC_FilterValue, 1, 12, 4, 0, // Skip to: 8183
-/* 7147 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7150 */    MCD_OPC_FilterValue, 0, 117, 0, 0, // Skip to: 7272
-/* 7155 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 7158 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7198
-/* 7163 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 7166 */    MCD_OPC_FilterValue, 15, 244, 3, 0, // Skip to: 8183
-/* 7171 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7188
-/* 7176 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7188
-/* 7183 */    MCD_OPC_Decode, 135, 24, 171, 2, // Opcode: t2SXTB
-/* 7188 */    MCD_OPC_CheckPredicate, 43, 222, 3, 0, // Skip to: 8183
-/* 7193 */    MCD_OPC_Decode, 132, 24, 172, 2, // Opcode: t2SXTAB
-/* 7198 */    MCD_OPC_FilterValue, 1, 212, 3, 0, // Skip to: 8183
-/* 7203 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 7206 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7228
-/* 7211 */    MCD_OPC_CheckPredicate, 57, 199, 3, 0, // Skip to: 8183
-/* 7216 */    MCD_OPC_CheckField, 12, 4, 15, 192, 3, 0, // Skip to: 8183
-/* 7223 */    MCD_OPC_Decode, 232, 21, 170, 2, // Opcode: t2CRC32B
-/* 7228 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7250
-/* 7233 */    MCD_OPC_CheckPredicate, 57, 177, 3, 0, // Skip to: 8183
-/* 7238 */    MCD_OPC_CheckField, 12, 4, 15, 170, 3, 0, // Skip to: 8183
-/* 7245 */    MCD_OPC_Decode, 236, 21, 170, 2, // Opcode: t2CRC32H
-/* 7250 */    MCD_OPC_FilterValue, 2, 160, 3, 0, // Skip to: 8183
-/* 7255 */    MCD_OPC_CheckPredicate, 57, 155, 3, 0, // Skip to: 8183
-/* 7260 */    MCD_OPC_CheckField, 12, 4, 15, 148, 3, 0, // Skip to: 8183
-/* 7267 */    MCD_OPC_Decode, 237, 21, 170, 2, // Opcode: t2CRC32W
-/* 7272 */    MCD_OPC_FilterValue, 1, 138, 3, 0, // Skip to: 8183
-/* 7277 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 7280 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7320
-/* 7285 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
-/* 7288 */    MCD_OPC_FilterValue, 15, 122, 3, 0, // Skip to: 8183
-/* 7293 */    MCD_OPC_CheckPredicate, 38, 12, 0, 0, // Skip to: 7310
-/* 7298 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7310
-/* 7305 */    MCD_OPC_Decode, 182, 24, 171, 2, // Opcode: t2UXTB
-/* 7310 */    MCD_OPC_CheckPredicate, 43, 100, 3, 0, // Skip to: 8183
-/* 7315 */    MCD_OPC_Decode, 179, 24, 172, 2, // Opcode: t2UXTAB
-/* 7320 */    MCD_OPC_FilterValue, 1, 90, 3, 0, // Skip to: 8183
-/* 7325 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
-/* 7328 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7350
-/* 7333 */    MCD_OPC_CheckPredicate, 57, 77, 3, 0, // Skip to: 8183
-/* 7338 */    MCD_OPC_CheckField, 12, 4, 15, 70, 3, 0, // Skip to: 8183
-/* 7345 */    MCD_OPC_Decode, 233, 21, 170, 2, // Opcode: t2CRC32CB
-/* 7350 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 7372
-/* 7355 */    MCD_OPC_CheckPredicate, 57, 55, 3, 0, // Skip to: 8183
-/* 7360 */    MCD_OPC_CheckField, 12, 4, 15, 48, 3, 0, // Skip to: 8183
-/* 7367 */    MCD_OPC_Decode, 234, 21, 170, 2, // Opcode: t2CRC32CH
-/* 7372 */    MCD_OPC_FilterValue, 2, 38, 3, 0, // Skip to: 8183
-/* 7377 */    MCD_OPC_CheckPredicate, 57, 33, 3, 0, // Skip to: 8183
-/* 7382 */    MCD_OPC_CheckField, 12, 4, 15, 26, 3, 0, // Skip to: 8183
-/* 7389 */    MCD_OPC_Decode, 235, 21, 170, 2, // Opcode: t2CRC32CW
-/* 7394 */    MCD_OPC_FilterValue, 3, 16, 3, 0, // Skip to: 8183
-/* 7399 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 7402 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 7505
-/* 7407 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7410 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 7465
-/* 7415 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 7418 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7450
-/* 7423 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7440
-/* 7428 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7440
-/* 7435 */    MCD_OPC_Decode, 192, 23, 170, 2, // Opcode: t2SMUSD
-/* 7440 */    MCD_OPC_CheckPredicate, 45, 226, 2, 0, // Skip to: 8183
-/* 7445 */    MCD_OPC_Decode, 173, 23, 175, 2, // Opcode: t2SMLSD
-/* 7450 */    MCD_OPC_FilterValue, 1, 216, 2, 0, // Skip to: 8183
-/* 7455 */    MCD_OPC_CheckPredicate, 38, 211, 2, 0, // Skip to: 8183
-/* 7460 */    MCD_OPC_Decode, 162, 23, 181, 2, // Opcode: t2SMLAL
-/* 7465 */    MCD_OPC_FilterValue, 1, 201, 2, 0, // Skip to: 8183
-/* 7470 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 7473 */    MCD_OPC_FilterValue, 0, 193, 2, 0, // Skip to: 8183
-/* 7478 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7495
-/* 7483 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7495
-/* 7490 */    MCD_OPC_Decode, 181, 23, 170, 2, // Opcode: t2SMMUL
-/* 7495 */    MCD_OPC_CheckPredicate, 45, 171, 2, 0, // Skip to: 8183
-/* 7500 */    MCD_OPC_Decode, 177, 23, 175, 2, // Opcode: t2SMMLA
-/* 7505 */    MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 7593
-/* 7510 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7513 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7553
-/* 7518 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 7521 */    MCD_OPC_FilterValue, 0, 145, 2, 0, // Skip to: 8183
-/* 7526 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7543
-/* 7531 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7543
-/* 7538 */    MCD_OPC_Decode, 193, 23, 170, 2, // Opcode: t2SMUSDX
-/* 7543 */    MCD_OPC_CheckPredicate, 45, 123, 2, 0, // Skip to: 8183
-/* 7548 */    MCD_OPC_Decode, 174, 23, 175, 2, // Opcode: t2SMLSDX
-/* 7553 */    MCD_OPC_FilterValue, 1, 113, 2, 0, // Skip to: 8183
-/* 7558 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 7561 */    MCD_OPC_FilterValue, 0, 105, 2, 0, // Skip to: 8183
-/* 7566 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7583
-/* 7571 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7583
-/* 7578 */    MCD_OPC_Decode, 182, 23, 170, 2, // Opcode: t2SMMULR
-/* 7583 */    MCD_OPC_CheckPredicate, 45, 83, 2, 0, // Skip to: 8183
-/* 7588 */    MCD_OPC_Decode, 178, 23, 175, 2, // Opcode: t2SMMLAR
-/* 7593 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 7622
-/* 7598 */    MCD_OPC_CheckPredicate, 45, 68, 2, 0, // Skip to: 8183
-/* 7603 */    MCD_OPC_CheckField, 23, 1, 1, 61, 2, 0, // Skip to: 8183
-/* 7610 */    MCD_OPC_CheckField, 20, 1, 0, 54, 2, 0, // Skip to: 8183
-/* 7617 */    MCD_OPC_Decode, 163, 23, 181, 2, // Opcode: t2SMLALBB
-/* 7622 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 7651
-/* 7627 */    MCD_OPC_CheckPredicate, 45, 39, 2, 0, // Skip to: 8183
-/* 7632 */    MCD_OPC_CheckField, 23, 1, 1, 32, 2, 0, // Skip to: 8183
-/* 7639 */    MCD_OPC_CheckField, 20, 1, 0, 25, 2, 0, // Skip to: 8183
-/* 7646 */    MCD_OPC_Decode, 164, 23, 181, 2, // Opcode: t2SMLALBT
-/* 7651 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 7680
-/* 7656 */    MCD_OPC_CheckPredicate, 45, 10, 2, 0, // Skip to: 8183
-/* 7661 */    MCD_OPC_CheckField, 23, 1, 1, 3, 2, 0, // Skip to: 8183
-/* 7668 */    MCD_OPC_CheckField, 20, 1, 0, 252, 1, 0, // Skip to: 8183
-/* 7675 */    MCD_OPC_Decode, 167, 23, 181, 2, // Opcode: t2SMLALTB
-/* 7680 */    MCD_OPC_FilterValue, 11, 24, 0, 0, // Skip to: 7709
-/* 7685 */    MCD_OPC_CheckPredicate, 45, 237, 1, 0, // Skip to: 8183
-/* 7690 */    MCD_OPC_CheckField, 23, 1, 1, 230, 1, 0, // Skip to: 8183
-/* 7697 */    MCD_OPC_CheckField, 20, 1, 0, 223, 1, 0, // Skip to: 8183
-/* 7704 */    MCD_OPC_Decode, 168, 23, 181, 2, // Opcode: t2SMLALTT
-/* 7709 */    MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 7761
-/* 7714 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7717 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7739
-/* 7722 */    MCD_OPC_CheckPredicate, 45, 200, 1, 0, // Skip to: 8183
-/* 7727 */    MCD_OPC_CheckField, 23, 1, 1, 193, 1, 0, // Skip to: 8183
-/* 7734 */    MCD_OPC_Decode, 165, 23, 181, 2, // Opcode: t2SMLALD
-/* 7739 */    MCD_OPC_FilterValue, 1, 183, 1, 0, // Skip to: 8183
-/* 7744 */    MCD_OPC_CheckPredicate, 45, 178, 1, 0, // Skip to: 8183
-/* 7749 */    MCD_OPC_CheckField, 23, 1, 1, 171, 1, 0, // Skip to: 8183
-/* 7756 */    MCD_OPC_Decode, 175, 23, 181, 2, // Opcode: t2SMLSLD
-/* 7761 */    MCD_OPC_FilterValue, 13, 161, 1, 0, // Skip to: 8183
-/* 7766 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7769 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7791
-/* 7774 */    MCD_OPC_CheckPredicate, 45, 148, 1, 0, // Skip to: 8183
-/* 7779 */    MCD_OPC_CheckField, 23, 1, 1, 141, 1, 0, // Skip to: 8183
-/* 7786 */    MCD_OPC_Decode, 166, 23, 181, 2, // Opcode: t2SMLALDX
-/* 7791 */    MCD_OPC_FilterValue, 1, 131, 1, 0, // Skip to: 8183
-/* 7796 */    MCD_OPC_CheckPredicate, 45, 126, 1, 0, // Skip to: 8183
-/* 7801 */    MCD_OPC_CheckField, 23, 1, 1, 119, 1, 0, // Skip to: 8183
-/* 7808 */    MCD_OPC_Decode, 176, 23, 181, 2, // Opcode: t2SMLSLDX
-/* 7813 */    MCD_OPC_FilterValue, 3, 109, 1, 0, // Skip to: 8183
-/* 7818 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
-/* 7821 */    MCD_OPC_FilterValue, 0, 131, 0, 0, // Skip to: 7957
-/* 7826 */    MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
-/* 7829 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 7851
-/* 7834 */    MCD_OPC_CheckPredicate, 38, 88, 1, 0, // Skip to: 8183
-/* 7839 */    MCD_OPC_CheckField, 12, 4, 15, 81, 1, 0, // Skip to: 8183
-/* 7846 */    MCD_OPC_Decode, 135, 23, 239, 1, // Opcode: t2RORrr
-/* 7851 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7880
-/* 7856 */    MCD_OPC_CheckPredicate, 45, 66, 1, 0, // Skip to: 8183
-/* 7861 */    MCD_OPC_CheckField, 20, 1, 0, 59, 1, 0, // Skip to: 8183
-/* 7868 */    MCD_OPC_CheckField, 12, 4, 15, 52, 1, 0, // Skip to: 8183
-/* 7875 */    MCD_OPC_Decode, 200, 23, 170, 2, // Opcode: t2SSAX
-/* 7880 */    MCD_OPC_FilterValue, 6, 50, 0, 0, // Skip to: 7935
-/* 7885 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
-/* 7888 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 7903
-/* 7893 */    MCD_OPC_CheckPredicate, 45, 29, 1, 0, // Skip to: 8183
-/* 7898 */    MCD_OPC_Decode, 179, 23, 175, 2, // Opcode: t2SMMLS
-/* 7903 */    MCD_OPC_FilterValue, 1, 19, 1, 0, // Skip to: 8183
-/* 7908 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7925
-/* 7913 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7925
-/* 7920 */    MCD_OPC_Decode, 172, 24, 170, 2, // Opcode: t2USAD8
-/* 7925 */    MCD_OPC_CheckPredicate, 45, 253, 0, 0, // Skip to: 8183
-/* 7930 */    MCD_OPC_Decode, 173, 24, 175, 2, // Opcode: t2USADA8
-/* 7935 */    MCD_OPC_FilterValue, 7, 243, 0, 0, // Skip to: 8183
-/* 7940 */    MCD_OPC_CheckPredicate, 38, 238, 0, 0, // Skip to: 8183
-/* 7945 */    MCD_OPC_CheckField, 20, 1, 0, 231, 0, 0, // Skip to: 8183
-/* 7952 */    MCD_OPC_Decode, 164, 24, 181, 2, // Opcode: t2UMLAL
-/* 7957 */    MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 8016
-/* 7962 */    MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
-/* 7965 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 7994
-/* 7970 */    MCD_OPC_CheckPredicate, 45, 208, 0, 0, // Skip to: 8183
-/* 7975 */    MCD_OPC_CheckField, 20, 1, 0, 201, 0, 0, // Skip to: 8183
-/* 7982 */    MCD_OPC_CheckField, 12, 4, 15, 194, 0, 0, // Skip to: 8183
-/* 7989 */    MCD_OPC_Decode, 250, 22, 170, 2, // Opcode: t2QSAX
-/* 7994 */    MCD_OPC_FilterValue, 6, 184, 0, 0, // Skip to: 8183
-/* 7999 */    MCD_OPC_CheckPredicate, 45, 179, 0, 0, // Skip to: 8183
-/* 8004 */    MCD_OPC_CheckField, 20, 1, 0, 172, 0, 0, // Skip to: 8183
-/* 8011 */    MCD_OPC_Decode, 180, 23, 175, 2, // Opcode: t2SMMLSR
-/* 8016 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 8052
-/* 8021 */    MCD_OPC_CheckPredicate, 45, 157, 0, 0, // Skip to: 8183
-/* 8026 */    MCD_OPC_CheckField, 23, 4, 5, 150, 0, 0, // Skip to: 8183
-/* 8033 */    MCD_OPC_CheckField, 20, 1, 0, 143, 0, 0, // Skip to: 8183
-/* 8040 */    MCD_OPC_CheckField, 12, 4, 15, 136, 0, 0, // Skip to: 8183
-/* 8047 */    MCD_OPC_Decode, 154, 23, 170, 2, // Opcode: t2SHSAX
-/* 8052 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 8088
-/* 8057 */    MCD_OPC_CheckPredicate, 45, 121, 0, 0, // Skip to: 8183
-/* 8062 */    MCD_OPC_CheckField, 23, 4, 5, 114, 0, 0, // Skip to: 8183
-/* 8069 */    MCD_OPC_CheckField, 20, 1, 0, 107, 0, 0, // Skip to: 8183
-/* 8076 */    MCD_OPC_CheckField, 12, 4, 15, 100, 0, 0, // Skip to: 8183
-/* 8083 */    MCD_OPC_Decode, 176, 24, 170, 2, // Opcode: t2USAX
-/* 8088 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 8124
-/* 8093 */    MCD_OPC_CheckPredicate, 45, 85, 0, 0, // Skip to: 8183
-/* 8098 */    MCD_OPC_CheckField, 23, 4, 5, 78, 0, 0, // Skip to: 8183
-/* 8105 */    MCD_OPC_CheckField, 20, 1, 0, 71, 0, 0, // Skip to: 8183
-/* 8112 */    MCD_OPC_CheckField, 12, 4, 15, 64, 0, 0, // Skip to: 8183
-/* 8119 */    MCD_OPC_Decode, 169, 24, 170, 2, // Opcode: t2UQSAX
-/* 8124 */    MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 8183
-/* 8129 */    MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
-/* 8132 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 8161
-/* 8137 */    MCD_OPC_CheckPredicate, 45, 41, 0, 0, // Skip to: 8183
-/* 8142 */    MCD_OPC_CheckField, 20, 1, 0, 34, 0, 0, // Skip to: 8183
-/* 8149 */    MCD_OPC_CheckField, 12, 4, 15, 27, 0, 0, // Skip to: 8183
-/* 8156 */    MCD_OPC_Decode, 160, 24, 170, 2, // Opcode: t2UHSAX
-/* 8161 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 8183
-/* 8166 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 8183
-/* 8171 */    MCD_OPC_CheckField, 20, 1, 0, 5, 0, 0, // Skip to: 8183
-/* 8178 */    MCD_OPC_Decode, 163, 24, 181, 2, // Opcode: t2UMAAL
-/* 8183 */    MCD_OPC_Fail,
+/* 86 */      MCD_OPC_CheckPredicate, 45, 55, 35, 0, // Skip to: 9106
+/* 91 */      MCD_OPC_CheckField, 15, 1, 0, 48, 35, 0, // Skip to: 9106
+/* 98 */      MCD_OPC_CheckField, 13, 1, 0, 41, 35, 0, // Skip to: 9106
+/* 105 */     MCD_OPC_Decode, 154, 33, 212, 2, // Opcode: t2STMIA
+/* 110 */     MCD_OPC_FilterValue, 1, 31, 35, 0, // Skip to: 9106
+/* 115 */     MCD_OPC_CheckPredicate, 47, 19, 0, 0, // Skip to: 139
+/* 120 */     MCD_OPC_CheckField, 16, 4, 15, 12, 0, 0, // Skip to: 139
+/* 127 */     MCD_OPC_CheckField, 13, 1, 0, 5, 0, 0, // Skip to: 139
+/* 134 */     MCD_OPC_Decode, 136, 31, 213, 2, // Opcode: t2CLRM
+/* 139 */     MCD_OPC_CheckPredicate, 45, 2, 35, 0, // Skip to: 9106
+/* 144 */     MCD_OPC_Decode, 198, 31, 214, 2, // Opcode: t2LDMIA
+/* 149 */     MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 201
+/* 154 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 157 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 186
+/* 162 */     MCD_OPC_CheckPredicate, 45, 235, 34, 0, // Skip to: 9106
+/* 167 */     MCD_OPC_CheckField, 15, 1, 0, 228, 34, 0, // Skip to: 9106
+/* 174 */     MCD_OPC_CheckField, 13, 1, 0, 221, 34, 0, // Skip to: 9106
+/* 181 */     MCD_OPC_Decode, 152, 33, 212, 2, // Opcode: t2STMDB
+/* 186 */     MCD_OPC_FilterValue, 1, 211, 34, 0, // Skip to: 9106
+/* 191 */     MCD_OPC_CheckPredicate, 45, 206, 34, 0, // Skip to: 9106
+/* 196 */     MCD_OPC_Decode, 196, 31, 214, 2, // Opcode: t2LDMDB
+/* 201 */     MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 255
+/* 206 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 209 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 232
+/* 214 */     MCD_OPC_CheckPredicate, 46, 183, 34, 0, // Skip to: 9106
+/* 219 */     MCD_OPC_CheckField, 5, 15, 128, 220, 1, 174, 34, 0, // Skip to: 9106
+/* 228 */     MCD_OPC_Decode, 250, 32, 85, // Opcode: t2SRSIA
+/* 232 */     MCD_OPC_FilterValue, 1, 165, 34, 0, // Skip to: 9106
+/* 237 */     MCD_OPC_CheckPredicate, 46, 160, 34, 0, // Skip to: 9106
+/* 242 */     MCD_OPC_CheckField, 0, 16, 128, 128, 3, 151, 34, 0, // Skip to: 9106
+/* 251 */     MCD_OPC_Decode, 185, 32, 82, // Opcode: t2RFEIA
+/* 255 */     MCD_OPC_FilterValue, 4, 93, 0, 0, // Skip to: 353
+/* 260 */     MCD_OPC_CheckPredicate, 45, 20, 0, 0, // Skip to: 285
+/* 265 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 285
+/* 272 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 285
+/* 280 */     MCD_OPC_Decode, 201, 33, 215, 2, // Opcode: t2TSTrr
+/* 285 */     MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 309
+/* 290 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 309
+/* 297 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 309
+/* 304 */     MCD_OPC_Decode, 202, 33, 216, 2, // Opcode: t2TSTrs
+/* 309 */     MCD_OPC_CheckPredicate, 45, 24, 0, 0, // Skip to: 338
+/* 314 */     MCD_OPC_CheckField, 12, 3, 0, 17, 0, 0, // Skip to: 338
+/* 321 */     MCD_OPC_CheckField, 4, 4, 0, 10, 0, 0, // Skip to: 338
+/* 328 */     MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 333 */     MCD_OPC_Decode, 240, 30, 217, 2, // Opcode: t2ANDrr
+/* 338 */     MCD_OPC_CheckPredicate, 45, 59, 34, 0, // Skip to: 9106
+/* 343 */     MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 348 */     MCD_OPC_Decode, 241, 30, 218, 2, // Opcode: t2ANDrs
+/* 353 */     MCD_OPC_FilterValue, 5, 93, 0, 0, // Skip to: 451
+/* 358 */     MCD_OPC_CheckPredicate, 45, 20, 0, 0, // Skip to: 383
+/* 363 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 383
+/* 370 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 383
+/* 378 */     MCD_OPC_Decode, 197, 33, 215, 2, // Opcode: t2TEQrr
+/* 383 */     MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 407
+/* 388 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 407
+/* 395 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 407
+/* 402 */     MCD_OPC_Decode, 198, 33, 216, 2, // Opcode: t2TEQrs
+/* 407 */     MCD_OPC_CheckPredicate, 45, 24, 0, 0, // Skip to: 436
+/* 412 */     MCD_OPC_CheckField, 12, 3, 0, 17, 0, 0, // Skip to: 436
+/* 419 */     MCD_OPC_CheckField, 4, 4, 0, 10, 0, 0, // Skip to: 436
+/* 426 */     MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 431 */     MCD_OPC_Decode, 165, 31, 217, 2, // Opcode: t2EORrr
+/* 436 */     MCD_OPC_CheckPredicate, 45, 217, 33, 0, // Skip to: 9106
+/* 441 */     MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 446 */     MCD_OPC_Decode, 166, 31, 218, 2, // Opcode: t2EORrs
+/* 451 */     MCD_OPC_FilterValue, 6, 202, 33, 0, // Skip to: 9106
+/* 456 */     MCD_OPC_CheckPredicate, 45, 20, 0, 0, // Skip to: 481
+/* 461 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 481
+/* 468 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 481
+/* 476 */     MCD_OPC_Decode, 139, 31, 219, 2, // Opcode: t2CMNzrr
+/* 481 */     MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 505
+/* 486 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 505
+/* 493 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 505
+/* 500 */     MCD_OPC_Decode, 140, 31, 220, 2, // Opcode: t2CMNzrs
+/* 505 */     MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 529
+/* 510 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 529
+/* 517 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 529
+/* 524 */     MCD_OPC_Decode, 234, 30, 221, 2, // Opcode: t2ADDrr
+/* 529 */     MCD_OPC_CheckPredicate, 45, 124, 33, 0, // Skip to: 9106
+/* 534 */     MCD_OPC_Decode, 235, 30, 222, 2, // Opcode: t2ADDrs
+/* 539 */     MCD_OPC_FilterValue, 1, 96, 1, 0, // Skip to: 896
+/* 544 */     MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
+/* 547 */     MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 601
+/* 552 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 555 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 578
+/* 560 */     MCD_OPC_CheckPredicate, 46, 93, 33, 0, // Skip to: 9106
+/* 565 */     MCD_OPC_CheckField, 5, 15, 128, 220, 1, 84, 33, 0, // Skip to: 9106
+/* 574 */     MCD_OPC_Decode, 249, 32, 85, // Opcode: t2SRSDB_UPD
+/* 578 */     MCD_OPC_FilterValue, 1, 75, 33, 0, // Skip to: 9106
+/* 583 */     MCD_OPC_CheckPredicate, 46, 70, 33, 0, // Skip to: 9106
+/* 588 */     MCD_OPC_CheckField, 0, 16, 128, 128, 3, 61, 33, 0, // Skip to: 9106
+/* 597 */     MCD_OPC_Decode, 184, 32, 82, // Opcode: t2RFEDBW
+/* 601 */     MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 653
+/* 606 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 609 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 638
+/* 614 */     MCD_OPC_CheckPredicate, 45, 39, 33, 0, // Skip to: 9106
+/* 619 */     MCD_OPC_CheckField, 15, 1, 0, 32, 33, 0, // Skip to: 9106
+/* 626 */     MCD_OPC_CheckField, 13, 1, 0, 25, 33, 0, // Skip to: 9106
+/* 633 */     MCD_OPC_Decode, 155, 33, 223, 2, // Opcode: t2STMIA_UPD
+/* 638 */     MCD_OPC_FilterValue, 1, 15, 33, 0, // Skip to: 9106
+/* 643 */     MCD_OPC_CheckPredicate, 45, 10, 33, 0, // Skip to: 9106
+/* 648 */     MCD_OPC_Decode, 199, 31, 224, 2, // Opcode: t2LDMIA_UPD
+/* 653 */     MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 705
+/* 658 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 661 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 690
+/* 666 */     MCD_OPC_CheckPredicate, 45, 243, 32, 0, // Skip to: 9106
+/* 671 */     MCD_OPC_CheckField, 15, 1, 0, 236, 32, 0, // Skip to: 9106
+/* 678 */     MCD_OPC_CheckField, 13, 1, 0, 229, 32, 0, // Skip to: 9106
+/* 685 */     MCD_OPC_Decode, 153, 33, 223, 2, // Opcode: t2STMDB_UPD
+/* 690 */     MCD_OPC_FilterValue, 1, 219, 32, 0, // Skip to: 9106
+/* 695 */     MCD_OPC_CheckPredicate, 45, 214, 32, 0, // Skip to: 9106
+/* 700 */     MCD_OPC_Decode, 197, 31, 224, 2, // Opcode: t2LDMDB_UPD
+/* 705 */     MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 759
+/* 710 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 713 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 736
+/* 718 */     MCD_OPC_CheckPredicate, 46, 191, 32, 0, // Skip to: 9106
+/* 723 */     MCD_OPC_CheckField, 5, 15, 128, 220, 1, 182, 32, 0, // Skip to: 9106
+/* 732 */     MCD_OPC_Decode, 251, 32, 85, // Opcode: t2SRSIA_UPD
+/* 736 */     MCD_OPC_FilterValue, 1, 173, 32, 0, // Skip to: 9106
+/* 741 */     MCD_OPC_CheckPredicate, 46, 168, 32, 0, // Skip to: 9106
+/* 746 */     MCD_OPC_CheckField, 0, 16, 128, 128, 3, 159, 32, 0, // Skip to: 9106
+/* 755 */     MCD_OPC_Decode, 186, 32, 82, // Opcode: t2RFEIAW
+/* 759 */     MCD_OPC_FilterValue, 4, 44, 0, 0, // Skip to: 808
+/* 764 */     MCD_OPC_CheckPredicate, 45, 24, 0, 0, // Skip to: 793
+/* 769 */     MCD_OPC_CheckField, 12, 3, 0, 17, 0, 0, // Skip to: 793
+/* 776 */     MCD_OPC_CheckField, 4, 4, 0, 10, 0, 0, // Skip to: 793
+/* 783 */     MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 788 */     MCD_OPC_Decode, 255, 30, 217, 2, // Opcode: t2BICrr
+/* 793 */     MCD_OPC_CheckPredicate, 45, 116, 32, 0, // Skip to: 9106
+/* 798 */     MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 803 */     MCD_OPC_Decode, 128, 31, 218, 2, // Opcode: t2BICrs
+/* 808 */     MCD_OPC_FilterValue, 7, 101, 32, 0, // Skip to: 9106
+/* 813 */     MCD_OPC_CheckPredicate, 45, 20, 0, 0, // Skip to: 838
+/* 818 */     MCD_OPC_CheckField, 20, 1, 1, 13, 0, 0, // Skip to: 838
+/* 825 */     MCD_OPC_CheckField, 4, 11, 240, 1, 5, 0, 0, // Skip to: 838
+/* 833 */     MCD_OPC_Decode, 142, 31, 219, 2, // Opcode: t2CMPrr
+/* 838 */     MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 862
+/* 843 */     MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 862
+/* 850 */     MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 862
+/* 857 */     MCD_OPC_Decode, 143, 31, 220, 2, // Opcode: t2CMPrs
+/* 862 */     MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 886
+/* 867 */     MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 886
+/* 874 */     MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 886
+/* 881 */     MCD_OPC_Decode, 184, 33, 221, 2, // Opcode: t2SUBrr
+/* 886 */     MCD_OPC_CheckPredicate, 45, 23, 32, 0, // Skip to: 9106
+/* 891 */     MCD_OPC_Decode, 185, 33, 222, 2, // Opcode: t2SUBrs
+/* 896 */     MCD_OPC_FilterValue, 2, 179, 4, 0, // Skip to: 2104
+/* 901 */     MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
+/* 904 */     MCD_OPC_FilterValue, 0, 212, 2, 0, // Skip to: 1633
+/* 909 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 912 */     MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 1273
+/* 917 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 920 */     MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 1038
+/* 925 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 928 */     MCD_OPC_FilterValue, 0, 20, 0, 0, // Skip to: 953
+/* 933 */     MCD_OPC_CheckPredicate, 36, 90, 0, 0, // Skip to: 1028
+/* 938 */     MCD_OPC_CheckField, 12, 4, 15, 83, 0, 0, // Skip to: 1028
+/* 945 */     MCD_OPC_SoftFail, 63, 0,
+/* 948 */     MCD_OPC_Decode, 203, 33, 225, 2, // Opcode: t2TT
+/* 953 */     MCD_OPC_FilterValue, 1, 20, 0, 0, // Skip to: 978
+/* 958 */     MCD_OPC_CheckPredicate, 36, 65, 0, 0, // Skip to: 1028
+/* 963 */     MCD_OPC_CheckField, 12, 4, 15, 58, 0, 0, // Skip to: 1028
+/* 970 */     MCD_OPC_SoftFail, 63, 0,
+/* 973 */     MCD_OPC_Decode, 206, 33, 225, 2, // Opcode: t2TTT
+/* 978 */     MCD_OPC_FilterValue, 2, 20, 0, 0, // Skip to: 1003
+/* 983 */     MCD_OPC_CheckPredicate, 36, 40, 0, 0, // Skip to: 1028
+/* 988 */     MCD_OPC_CheckField, 12, 4, 15, 33, 0, 0, // Skip to: 1028
+/* 995 */     MCD_OPC_SoftFail, 63, 0,
+/* 998 */     MCD_OPC_Decode, 204, 33, 225, 2, // Opcode: t2TTA
+/* 1003 */    MCD_OPC_FilterValue, 3, 20, 0, 0, // Skip to: 1028
+/* 1008 */    MCD_OPC_CheckPredicate, 36, 15, 0, 0, // Skip to: 1028
+/* 1013 */    MCD_OPC_CheckField, 12, 4, 15, 8, 0, 0, // Skip to: 1028
+/* 1020 */    MCD_OPC_SoftFail, 63, 0,
+/* 1023 */    MCD_OPC_Decode, 205, 33, 225, 2, // Opcode: t2TTAT
+/* 1028 */    MCD_OPC_CheckPredicate, 39, 137, 31, 0, // Skip to: 9106
+/* 1033 */    MCD_OPC_Decode, 165, 33, 226, 2, // Opcode: t2STREX
+/* 1038 */    MCD_OPC_FilterValue, 1, 127, 31, 0, // Skip to: 9106
+/* 1043 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 1046 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 1068
+/* 1051 */    MCD_OPC_CheckPredicate, 39, 114, 31, 0, // Skip to: 9106
+/* 1056 */    MCD_OPC_CheckField, 8, 4, 15, 107, 31, 0, // Skip to: 9106
+/* 1063 */    MCD_OPC_Decode, 166, 33, 227, 2, // Opcode: t2STREXB
+/* 1068 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 1090
+/* 1073 */    MCD_OPC_CheckPredicate, 39, 92, 31, 0, // Skip to: 9106
+/* 1078 */    MCD_OPC_CheckField, 8, 4, 15, 85, 31, 0, // Skip to: 9106
+/* 1085 */    MCD_OPC_Decode, 168, 33, 227, 2, // Opcode: t2STREXH
+/* 1090 */    MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 1105
+/* 1095 */    MCD_OPC_CheckPredicate, 46, 70, 31, 0, // Skip to: 9106
+/* 1100 */    MCD_OPC_Decode, 167, 33, 228, 2, // Opcode: t2STREXD
+/* 1105 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1134
+/* 1110 */    MCD_OPC_CheckPredicate, 48, 55, 31, 0, // Skip to: 9106
+/* 1115 */    MCD_OPC_CheckField, 8, 4, 15, 48, 31, 0, // Skip to: 9106
+/* 1122 */    MCD_OPC_CheckField, 0, 4, 15, 41, 31, 0, // Skip to: 9106
+/* 1129 */    MCD_OPC_Decode, 146, 33, 229, 2, // Opcode: t2STLB
+/* 1134 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1163
+/* 1139 */    MCD_OPC_CheckPredicate, 48, 26, 31, 0, // Skip to: 9106
+/* 1144 */    MCD_OPC_CheckField, 8, 4, 15, 19, 31, 0, // Skip to: 9106
+/* 1151 */    MCD_OPC_CheckField, 0, 4, 15, 12, 31, 0, // Skip to: 9106
+/* 1158 */    MCD_OPC_Decode, 151, 33, 229, 2, // Opcode: t2STLH
+/* 1163 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1192
+/* 1168 */    MCD_OPC_CheckPredicate, 48, 253, 30, 0, // Skip to: 9106
+/* 1173 */    MCD_OPC_CheckField, 8, 4, 15, 246, 30, 0, // Skip to: 9106
+/* 1180 */    MCD_OPC_CheckField, 0, 4, 15, 239, 30, 0, // Skip to: 9106
+/* 1187 */    MCD_OPC_Decode, 145, 33, 229, 2, // Opcode: t2STL
+/* 1192 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 1214
+/* 1197 */    MCD_OPC_CheckPredicate, 49, 224, 30, 0, // Skip to: 9106
+/* 1202 */    MCD_OPC_CheckField, 8, 4, 15, 217, 30, 0, // Skip to: 9106
+/* 1209 */    MCD_OPC_Decode, 148, 33, 227, 2, // Opcode: t2STLEXB
+/* 1214 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 1236
+/* 1219 */    MCD_OPC_CheckPredicate, 49, 202, 30, 0, // Skip to: 9106
+/* 1224 */    MCD_OPC_CheckField, 8, 4, 15, 195, 30, 0, // Skip to: 9106
+/* 1231 */    MCD_OPC_Decode, 150, 33, 227, 2, // Opcode: t2STLEXH
+/* 1236 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 1258
+/* 1241 */    MCD_OPC_CheckPredicate, 49, 180, 30, 0, // Skip to: 9106
+/* 1246 */    MCD_OPC_CheckField, 8, 4, 15, 173, 30, 0, // Skip to: 9106
+/* 1253 */    MCD_OPC_Decode, 147, 33, 227, 2, // Opcode: t2STLEX
+/* 1258 */    MCD_OPC_FilterValue, 15, 163, 30, 0, // Skip to: 9106
+/* 1263 */    MCD_OPC_CheckPredicate, 50, 158, 30, 0, // Skip to: 9106
+/* 1268 */    MCD_OPC_Decode, 149, 33, 228, 2, // Opcode: t2STLEXD
+/* 1273 */    MCD_OPC_FilterValue, 1, 148, 30, 0, // Skip to: 9106
+/* 1278 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1281 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1303
+/* 1286 */    MCD_OPC_CheckPredicate, 39, 135, 30, 0, // Skip to: 9106
+/* 1291 */    MCD_OPC_CheckField, 8, 4, 15, 128, 30, 0, // Skip to: 9106
+/* 1298 */    MCD_OPC_Decode, 210, 31, 230, 2, // Opcode: t2LDREX
+/* 1303 */    MCD_OPC_FilterValue, 1, 118, 30, 0, // Skip to: 9106
+/* 1308 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 1311 */    MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 1334
+/* 1316 */    MCD_OPC_CheckPredicate, 45, 105, 30, 0, // Skip to: 9106
+/* 1321 */    MCD_OPC_CheckField, 8, 8, 240, 1, 97, 30, 0, // Skip to: 9106
+/* 1329 */    MCD_OPC_Decode, 194, 33, 231, 2, // Opcode: t2TBB
+/* 1334 */    MCD_OPC_FilterValue, 1, 18, 0, 0, // Skip to: 1357
+/* 1339 */    MCD_OPC_CheckPredicate, 45, 82, 30, 0, // Skip to: 9106
+/* 1344 */    MCD_OPC_CheckField, 8, 8, 240, 1, 74, 30, 0, // Skip to: 9106
+/* 1352 */    MCD_OPC_Decode, 195, 33, 231, 2, // Opcode: t2TBH
+/* 1357 */    MCD_OPC_FilterValue, 4, 24, 0, 0, // Skip to: 1386
+/* 1362 */    MCD_OPC_CheckPredicate, 39, 59, 30, 0, // Skip to: 9106
+/* 1367 */    MCD_OPC_CheckField, 8, 4, 15, 52, 30, 0, // Skip to: 9106
+/* 1374 */    MCD_OPC_CheckField, 0, 4, 15, 45, 30, 0, // Skip to: 9106
+/* 1381 */    MCD_OPC_Decode, 211, 31, 229, 2, // Opcode: t2LDREXB
+/* 1386 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 1415
+/* 1391 */    MCD_OPC_CheckPredicate, 39, 30, 30, 0, // Skip to: 9106
+/* 1396 */    MCD_OPC_CheckField, 8, 4, 15, 23, 30, 0, // Skip to: 9106
+/* 1403 */    MCD_OPC_CheckField, 0, 4, 15, 16, 30, 0, // Skip to: 9106
+/* 1410 */    MCD_OPC_Decode, 213, 31, 229, 2, // Opcode: t2LDREXH
+/* 1415 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 1437
+/* 1420 */    MCD_OPC_CheckPredicate, 46, 1, 30, 0, // Skip to: 9106
+/* 1425 */    MCD_OPC_CheckField, 0, 4, 15, 250, 29, 0, // Skip to: 9106
+/* 1432 */    MCD_OPC_Decode, 212, 31, 232, 2, // Opcode: t2LDREXD
+/* 1437 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1466
+/* 1442 */    MCD_OPC_CheckPredicate, 48, 235, 29, 0, // Skip to: 9106
+/* 1447 */    MCD_OPC_CheckField, 8, 4, 15, 228, 29, 0, // Skip to: 9106
+/* 1454 */    MCD_OPC_CheckField, 0, 4, 15, 221, 29, 0, // Skip to: 9106
+/* 1461 */    MCD_OPC_Decode, 174, 31, 229, 2, // Opcode: t2LDAB
+/* 1466 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1495
+/* 1471 */    MCD_OPC_CheckPredicate, 48, 206, 29, 0, // Skip to: 9106
+/* 1476 */    MCD_OPC_CheckField, 8, 4, 15, 199, 29, 0, // Skip to: 9106
+/* 1483 */    MCD_OPC_CheckField, 0, 4, 15, 192, 29, 0, // Skip to: 9106
+/* 1490 */    MCD_OPC_Decode, 179, 31, 229, 2, // Opcode: t2LDAH
+/* 1495 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 1524
+/* 1500 */    MCD_OPC_CheckPredicate, 48, 177, 29, 0, // Skip to: 9106
+/* 1505 */    MCD_OPC_CheckField, 8, 4, 15, 170, 29, 0, // Skip to: 9106
+/* 1512 */    MCD_OPC_CheckField, 0, 4, 15, 163, 29, 0, // Skip to: 9106
+/* 1519 */    MCD_OPC_Decode, 173, 31, 229, 2, // Opcode: t2LDA
+/* 1524 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 1553
+/* 1529 */    MCD_OPC_CheckPredicate, 49, 148, 29, 0, // Skip to: 9106
+/* 1534 */    MCD_OPC_CheckField, 8, 4, 15, 141, 29, 0, // Skip to: 9106
+/* 1541 */    MCD_OPC_CheckField, 0, 4, 15, 134, 29, 0, // Skip to: 9106
+/* 1548 */    MCD_OPC_Decode, 176, 31, 229, 2, // Opcode: t2LDAEXB
+/* 1553 */    MCD_OPC_FilterValue, 13, 24, 0, 0, // Skip to: 1582
+/* 1558 */    MCD_OPC_CheckPredicate, 49, 119, 29, 0, // Skip to: 9106
+/* 1563 */    MCD_OPC_CheckField, 8, 4, 15, 112, 29, 0, // Skip to: 9106
+/* 1570 */    MCD_OPC_CheckField, 0, 4, 15, 105, 29, 0, // Skip to: 9106
+/* 1577 */    MCD_OPC_Decode, 178, 31, 229, 2, // Opcode: t2LDAEXH
+/* 1582 */    MCD_OPC_FilterValue, 14, 24, 0, 0, // Skip to: 1611
+/* 1587 */    MCD_OPC_CheckPredicate, 49, 90, 29, 0, // Skip to: 9106
+/* 1592 */    MCD_OPC_CheckField, 8, 4, 15, 83, 29, 0, // Skip to: 9106
+/* 1599 */    MCD_OPC_CheckField, 0, 4, 15, 76, 29, 0, // Skip to: 9106
+/* 1606 */    MCD_OPC_Decode, 175, 31, 229, 2, // Opcode: t2LDAEX
+/* 1611 */    MCD_OPC_FilterValue, 15, 66, 29, 0, // Skip to: 9106
+/* 1616 */    MCD_OPC_CheckPredicate, 50, 61, 29, 0, // Skip to: 9106
+/* 1621 */    MCD_OPC_CheckField, 0, 4, 15, 54, 29, 0, // Skip to: 9106
+/* 1628 */    MCD_OPC_Decode, 177, 31, 232, 2, // Opcode: t2LDAEXD
+/* 1633 */    MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 1671
+/* 1638 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 1641 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1656
+/* 1646 */    MCD_OPC_CheckPredicate, 45, 31, 29, 0, // Skip to: 9106
+/* 1651 */    MCD_OPC_Decode, 164, 33, 233, 2, // Opcode: t2STRDi8
+/* 1656 */    MCD_OPC_FilterValue, 1, 21, 29, 0, // Skip to: 9106
+/* 1661 */    MCD_OPC_CheckPredicate, 45, 16, 29, 0, // Skip to: 9106
+/* 1666 */    MCD_OPC_Decode, 209, 31, 233, 2, // Opcode: t2LDRDi8
+/* 1671 */    MCD_OPC_FilterValue, 2, 86, 1, 0, // Skip to: 2018
+/* 1676 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1679 */    MCD_OPC_FilterValue, 0, 26, 1, 0, // Skip to: 1966
+/* 1684 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 1687 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 1727
+/* 1692 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 1695 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1761
+/* 1700 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 1717
+/* 1705 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1717
+/* 1712 */    MCD_OPC_Decode, 129, 32, 234, 2, // Opcode: t2MOVr
+/* 1717 */    MCD_OPC_CheckPredicate, 45, 39, 0, 0, // Skip to: 1761
+/* 1722 */    MCD_OPC_Decode, 151, 32, 217, 2, // Opcode: t2ORRrr
+/* 1727 */    MCD_OPC_FilterValue, 3, 29, 0, 0, // Skip to: 1761
+/* 1732 */    MCD_OPC_CheckPredicate, 45, 24, 0, 0, // Skip to: 1761
+/* 1737 */    MCD_OPC_CheckField, 16, 4, 15, 17, 0, 0, // Skip to: 1761
+/* 1744 */    MCD_OPC_CheckField, 12, 3, 0, 10, 0, 0, // Skip to: 1761
+/* 1751 */    MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 1756 */    MCD_OPC_Decode, 189, 32, 235, 2, // Opcode: t2RRX
+/* 1761 */    MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
+/* 1764 */    MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 1870
+/* 1769 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 1772 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1794
+/* 1777 */    MCD_OPC_CheckPredicate, 45, 78, 0, 0, // Skip to: 1860
+/* 1782 */    MCD_OPC_CheckField, 16, 4, 15, 71, 0, 0, // Skip to: 1860
+/* 1789 */    MCD_OPC_Decode, 244, 31, 236, 2, // Opcode: t2LSLri
+/* 1794 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1816
+/* 1799 */    MCD_OPC_CheckPredicate, 45, 56, 0, 0, // Skip to: 1860
+/* 1804 */    MCD_OPC_CheckField, 16, 4, 15, 49, 0, 0, // Skip to: 1860
+/* 1811 */    MCD_OPC_Decode, 246, 31, 236, 2, // Opcode: t2LSRri
+/* 1816 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1838
+/* 1821 */    MCD_OPC_CheckPredicate, 45, 34, 0, 0, // Skip to: 1860
+/* 1826 */    MCD_OPC_CheckField, 16, 4, 15, 27, 0, 0, // Skip to: 1860
+/* 1833 */    MCD_OPC_Decode, 242, 30, 236, 2, // Opcode: t2ASRri
+/* 1838 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 1860
+/* 1843 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 1860
+/* 1848 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1860
+/* 1855 */    MCD_OPC_Decode, 187, 32, 236, 2, // Opcode: t2RORri
+/* 1860 */    MCD_OPC_CheckPredicate, 45, 73, 28, 0, // Skip to: 9106
+/* 1865 */    MCD_OPC_Decode, 152, 32, 218, 2, // Opcode: t2ORRrs
+/* 1870 */    MCD_OPC_FilterValue, 1, 63, 28, 0, // Skip to: 9106
+/* 1875 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
+/* 1878 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1900
+/* 1883 */    MCD_OPC_CheckPredicate, 47, 50, 28, 0, // Skip to: 9106
+/* 1888 */    MCD_OPC_CheckField, 20, 1, 1, 43, 28, 0, // Skip to: 9106
+/* 1895 */    MCD_OPC_Decode, 153, 31, 237, 2, // Opcode: t2CSEL
+/* 1900 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 1922
+/* 1905 */    MCD_OPC_CheckPredicate, 47, 28, 28, 0, // Skip to: 9106
+/* 1910 */    MCD_OPC_CheckField, 20, 1, 1, 21, 28, 0, // Skip to: 9106
+/* 1917 */    MCD_OPC_Decode, 154, 31, 237, 2, // Opcode: t2CSINC
+/* 1922 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 1944
+/* 1927 */    MCD_OPC_CheckPredicate, 47, 6, 28, 0, // Skip to: 9106
+/* 1932 */    MCD_OPC_CheckField, 20, 1, 1, 255, 27, 0, // Skip to: 9106
+/* 1939 */    MCD_OPC_Decode, 155, 31, 237, 2, // Opcode: t2CSINV
+/* 1944 */    MCD_OPC_FilterValue, 3, 245, 27, 0, // Skip to: 9106
+/* 1949 */    MCD_OPC_CheckPredicate, 47, 240, 27, 0, // Skip to: 9106
+/* 1954 */    MCD_OPC_CheckField, 20, 1, 1, 233, 27, 0, // Skip to: 9106
+/* 1961 */    MCD_OPC_Decode, 156, 31, 237, 2, // Opcode: t2CSNEG
+/* 1966 */    MCD_OPC_FilterValue, 1, 223, 27, 0, // Skip to: 9106
+/* 1971 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
+/* 1974 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1996
+/* 1979 */    MCD_OPC_CheckPredicate, 51, 210, 27, 0, // Skip to: 9106
+/* 1984 */    MCD_OPC_CheckField, 20, 1, 0, 203, 27, 0, // Skip to: 9106
+/* 1991 */    MCD_OPC_Decode, 156, 32, 238, 2, // Opcode: t2PKHBT
+/* 1996 */    MCD_OPC_FilterValue, 2, 193, 27, 0, // Skip to: 9106
+/* 2001 */    MCD_OPC_CheckPredicate, 51, 188, 27, 0, // Skip to: 9106
+/* 2006 */    MCD_OPC_CheckField, 20, 1, 0, 181, 27, 0, // Skip to: 9106
+/* 2013 */    MCD_OPC_Decode, 157, 32, 238, 2, // Opcode: t2PKHTB
+/* 2018 */    MCD_OPC_FilterValue, 3, 171, 27, 0, // Skip to: 9106
+/* 2023 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 2026 */    MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2065
+/* 2031 */    MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 2055
+/* 2036 */    MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2055
+/* 2043 */    MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2055
+/* 2050 */    MCD_OPC_Decode, 230, 30, 217, 2, // Opcode: t2ADCrr
+/* 2055 */    MCD_OPC_CheckPredicate, 45, 134, 27, 0, // Skip to: 9106
+/* 2060 */    MCD_OPC_Decode, 231, 30, 218, 2, // Opcode: t2ADCrs
+/* 2065 */    MCD_OPC_FilterValue, 1, 124, 27, 0, // Skip to: 9106
+/* 2070 */    MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 2094
+/* 2075 */    MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2094
+/* 2082 */    MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2094
+/* 2089 */    MCD_OPC_Decode, 191, 32, 217, 2, // Opcode: t2RSBrr
+/* 2094 */    MCD_OPC_CheckPredicate, 45, 95, 27, 0, // Skip to: 9106
+/* 2099 */    MCD_OPC_Decode, 192, 32, 218, 2, // Opcode: t2RSBrs
+/* 2104 */    MCD_OPC_FilterValue, 3, 85, 27, 0, // Skip to: 9106
+/* 2109 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
+/* 2112 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 2150
+/* 2117 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 2120 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2135
+/* 2125 */    MCD_OPC_CheckPredicate, 45, 64, 27, 0, // Skip to: 9106
+/* 2130 */    MCD_OPC_Decode, 162, 33, 239, 2, // Opcode: t2STRD_POST
+/* 2135 */    MCD_OPC_FilterValue, 1, 54, 27, 0, // Skip to: 9106
+/* 2140 */    MCD_OPC_CheckPredicate, 45, 49, 27, 0, // Skip to: 9106
+/* 2145 */    MCD_OPC_Decode, 207, 31, 240, 2, // Opcode: t2LDRD_POST
+/* 2150 */    MCD_OPC_FilterValue, 1, 58, 0, 0, // Skip to: 2213
+/* 2155 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 2158 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2173
+/* 2163 */    MCD_OPC_CheckPredicate, 45, 26, 27, 0, // Skip to: 9106
+/* 2168 */    MCD_OPC_Decode, 163, 33, 241, 2, // Opcode: t2STRD_PRE
+/* 2173 */    MCD_OPC_FilterValue, 1, 16, 27, 0, // Skip to: 9106
+/* 2178 */    MCD_OPC_CheckPredicate, 52, 20, 0, 0, // Skip to: 2203
+/* 2183 */    MCD_OPC_CheckField, 23, 1, 0, 13, 0, 0, // Skip to: 2203
+/* 2190 */    MCD_OPC_CheckField, 0, 20, 255, 210, 63, 4, 0, 0, // Skip to: 2203
+/* 2199 */    MCD_OPC_Decode, 204, 32, 61, // Opcode: t2SG
+/* 2203 */    MCD_OPC_CheckPredicate, 45, 242, 26, 0, // Skip to: 9106
+/* 2208 */    MCD_OPC_Decode, 208, 31, 242, 2, // Opcode: t2LDRD_PRE
+/* 2213 */    MCD_OPC_FilterValue, 2, 88, 0, 0, // Skip to: 2306
+/* 2218 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 2221 */    MCD_OPC_FilterValue, 0, 224, 26, 0, // Skip to: 9106
+/* 2226 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 2229 */    MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 2274
+/* 2234 */    MCD_OPC_ExtractField, 12, 3,  // Inst{14-12} ...
+/* 2237 */    MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 2274
+/* 2242 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 2259
+/* 2247 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2259
+/* 2254 */    MCD_OPC_Decode, 145, 32, 235, 2, // Opcode: t2MVNr
+/* 2259 */    MCD_OPC_CheckPredicate, 45, 10, 0, 0, // Skip to: 2274
+/* 2264 */    MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 2269 */    MCD_OPC_Decode, 148, 32, 217, 2, // Opcode: t2ORNrr
+/* 2274 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 2291
+/* 2279 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2291
+/* 2286 */    MCD_OPC_Decode, 146, 32, 243, 2, // Opcode: t2MVNs
+/* 2291 */    MCD_OPC_CheckPredicate, 45, 154, 26, 0, // Skip to: 9106
+/* 2296 */    MCD_OPC_SoftFail, 128, 128, 2 /* 0x8000 */, 0,
+/* 2301 */    MCD_OPC_Decode, 149, 32, 218, 2, // Opcode: t2ORNrs
+/* 2306 */    MCD_OPC_FilterValue, 3, 139, 26, 0, // Skip to: 9106
+/* 2311 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 2314 */    MCD_OPC_FilterValue, 0, 131, 26, 0, // Skip to: 9106
+/* 2319 */    MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 2343
+/* 2324 */    MCD_OPC_CheckField, 12, 3, 0, 12, 0, 0, // Skip to: 2343
+/* 2331 */    MCD_OPC_CheckField, 4, 4, 0, 5, 0, 0, // Skip to: 2343
+/* 2338 */    MCD_OPC_Decode, 198, 32, 217, 2, // Opcode: t2SBCrr
+/* 2343 */    MCD_OPC_CheckPredicate, 45, 102, 26, 0, // Skip to: 9106
+/* 2348 */    MCD_OPC_Decode, 199, 32, 218, 2, // Opcode: t2SBCrs
+/* 2353 */    MCD_OPC_FilterValue, 30, 84, 8, 0, // Skip to: 4490
+/* 2358 */    MCD_OPC_ExtractField, 15, 1,  // Inst{15} ...
+/* 2361 */    MCD_OPC_FilterValue, 0, 36, 3, 0, // Skip to: 3170
+/* 2366 */    MCD_OPC_ExtractField, 24, 2,  // Inst{25-24} ...
+/* 2369 */    MCD_OPC_FilterValue, 0, 160, 0, 0, // Skip to: 2534
+/* 2374 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 2377 */    MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 2416
+/* 2382 */    MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 2406
+/* 2387 */    MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2406
+/* 2394 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2406
+/* 2401 */    MCD_OPC_Decode, 200, 33, 244, 2, // Opcode: t2TSTri
+/* 2406 */    MCD_OPC_CheckPredicate, 45, 39, 26, 0, // Skip to: 9106
+/* 2411 */    MCD_OPC_Decode, 239, 30, 245, 2, // Opcode: t2ANDri
+/* 2416 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2431
+/* 2421 */    MCD_OPC_CheckPredicate, 45, 24, 26, 0, // Skip to: 9106
+/* 2426 */    MCD_OPC_Decode, 254, 30, 245, 2, // Opcode: t2BICri
+/* 2431 */    MCD_OPC_FilterValue, 2, 27, 0, 0, // Skip to: 2463
+/* 2436 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 2453
+/* 2441 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2453
+/* 2448 */    MCD_OPC_Decode, 255, 31, 246, 2, // Opcode: t2MOVi
+/* 2453 */    MCD_OPC_CheckPredicate, 45, 248, 25, 0, // Skip to: 9106
+/* 2458 */    MCD_OPC_Decode, 150, 32, 245, 2, // Opcode: t2ORRri
+/* 2463 */    MCD_OPC_FilterValue, 3, 27, 0, 0, // Skip to: 2495
+/* 2468 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 2485
+/* 2473 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 2485
+/* 2480 */    MCD_OPC_Decode, 144, 32, 246, 2, // Opcode: t2MVNi
+/* 2485 */    MCD_OPC_CheckPredicate, 45, 216, 25, 0, // Skip to: 9106
+/* 2490 */    MCD_OPC_Decode, 147, 32, 245, 2, // Opcode: t2ORNri
+/* 2495 */    MCD_OPC_FilterValue, 4, 206, 25, 0, // Skip to: 9106
+/* 2500 */    MCD_OPC_CheckPredicate, 45, 19, 0, 0, // Skip to: 2524
+/* 2505 */    MCD_OPC_CheckField, 20, 1, 1, 12, 0, 0, // Skip to: 2524
+/* 2512 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 2524
+/* 2519 */    MCD_OPC_Decode, 196, 33, 244, 2, // Opcode: t2TEQri
+/* 2524 */    MCD_OPC_CheckPredicate, 45, 177, 25, 0, // Skip to: 9106
+/* 2529 */    MCD_OPC_Decode, 164, 31, 245, 2, // Opcode: t2EORri
+/* 2534 */    MCD_OPC_FilterValue, 1, 172, 0, 0, // Skip to: 2711
+/* 2539 */    MCD_OPC_ExtractField, 21, 3,  // Inst{23-21} ...
+/* 2542 */    MCD_OPC_FilterValue, 0, 57, 0, 0, // Skip to: 2604
+/* 2547 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 2550 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2572
+/* 2555 */    MCD_OPC_CheckPredicate, 45, 34, 0, 0, // Skip to: 2594
+/* 2560 */    MCD_OPC_CheckField, 16, 4, 13, 27, 0, 0, // Skip to: 2594
+/* 2567 */    MCD_OPC_Decode, 236, 30, 247, 2, // Opcode: t2ADDspImm
+/* 2572 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2594
+/* 2577 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 2594
+/* 2582 */    MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 2594
+/* 2589 */    MCD_OPC_Decode, 138, 31, 248, 2, // Opcode: t2CMNri
+/* 2594 */    MCD_OPC_CheckPredicate, 45, 107, 25, 0, // Skip to: 9106
+/* 2599 */    MCD_OPC_Decode, 232, 30, 249, 2, // Opcode: t2ADDri
+/* 2604 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2619
+/* 2609 */    MCD_OPC_CheckPredicate, 45, 92, 25, 0, // Skip to: 9106
+/* 2614 */    MCD_OPC_Decode, 229, 30, 245, 2, // Opcode: t2ADCri
+/* 2619 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2634
+/* 2624 */    MCD_OPC_CheckPredicate, 45, 77, 25, 0, // Skip to: 9106
+/* 2629 */    MCD_OPC_Decode, 197, 32, 245, 2, // Opcode: t2SBCri
+/* 2634 */    MCD_OPC_FilterValue, 5, 57, 0, 0, // Skip to: 2696
+/* 2639 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 2642 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2664
+/* 2647 */    MCD_OPC_CheckPredicate, 45, 34, 0, 0, // Skip to: 2686
+/* 2652 */    MCD_OPC_CheckField, 16, 4, 13, 27, 0, 0, // Skip to: 2686
+/* 2659 */    MCD_OPC_Decode, 186, 33, 247, 2, // Opcode: t2SUBspImm
+/* 2664 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 2686
+/* 2669 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 2686
+/* 2674 */    MCD_OPC_CheckField, 20, 1, 1, 5, 0, 0, // Skip to: 2686
+/* 2681 */    MCD_OPC_Decode, 141, 31, 248, 2, // Opcode: t2CMPri
+/* 2686 */    MCD_OPC_CheckPredicate, 45, 15, 25, 0, // Skip to: 9106
+/* 2691 */    MCD_OPC_Decode, 182, 33, 249, 2, // Opcode: t2SUBri
+/* 2696 */    MCD_OPC_FilterValue, 6, 5, 25, 0, // Skip to: 9106
+/* 2701 */    MCD_OPC_CheckPredicate, 45, 0, 25, 0, // Skip to: 9106
+/* 2706 */    MCD_OPC_Decode, 190, 32, 245, 2, // Opcode: t2RSBri
+/* 2711 */    MCD_OPC_FilterValue, 2, 199, 0, 0, // Skip to: 2915
+/* 2716 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 2719 */    MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 2863
+/* 2724 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 2727 */    MCD_OPC_FilterValue, 0, 230, 24, 0, // Skip to: 9106
+/* 2732 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 2735 */    MCD_OPC_FilterValue, 13, 61, 0, 0, // Skip to: 2801
+/* 2740 */    MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 2743 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2772
+/* 2748 */    MCD_OPC_CheckPredicate, 45, 63, 0, 0, // Skip to: 2816
+/* 2753 */    MCD_OPC_CheckField, 23, 1, 0, 56, 0, 0, // Skip to: 2816
+/* 2760 */    MCD_OPC_CheckField, 8, 4, 13, 49, 0, 0, // Skip to: 2816
+/* 2767 */    MCD_OPC_Decode, 237, 30, 247, 2, // Opcode: t2ADDspImm12
+/* 2772 */    MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 2816
+/* 2777 */    MCD_OPC_CheckPredicate, 45, 34, 0, 0, // Skip to: 2816
+/* 2782 */    MCD_OPC_CheckField, 23, 1, 1, 27, 0, 0, // Skip to: 2816
+/* 2789 */    MCD_OPC_CheckField, 8, 4, 13, 20, 0, 0, // Skip to: 2816
+/* 2796 */    MCD_OPC_Decode, 187, 33, 247, 2, // Opcode: t2SUBspImm12
+/* 2801 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 2816
+/* 2806 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 2816
+/* 2811 */    MCD_OPC_Decode, 238, 30, 250, 2, // Opcode: t2ADR
+/* 2816 */    MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 2819 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2841
+/* 2824 */    MCD_OPC_CheckPredicate, 45, 133, 24, 0, // Skip to: 9106
+/* 2829 */    MCD_OPC_CheckField, 23, 1, 0, 126, 24, 0, // Skip to: 9106
+/* 2836 */    MCD_OPC_Decode, 233, 30, 251, 2, // Opcode: t2ADDri12
+/* 2841 */    MCD_OPC_FilterValue, 1, 116, 24, 0, // Skip to: 9106
+/* 2846 */    MCD_OPC_CheckPredicate, 45, 111, 24, 0, // Skip to: 9106
+/* 2851 */    MCD_OPC_CheckField, 23, 1, 1, 104, 24, 0, // Skip to: 9106
+/* 2858 */    MCD_OPC_Decode, 183, 33, 251, 2, // Opcode: t2SUBri12
+/* 2863 */    MCD_OPC_FilterValue, 1, 94, 24, 0, // Skip to: 9106
+/* 2868 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 2871 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2893
+/* 2876 */    MCD_OPC_CheckPredicate, 39, 81, 24, 0, // Skip to: 9106
+/* 2881 */    MCD_OPC_CheckField, 20, 2, 0, 74, 24, 0, // Skip to: 9106
+/* 2888 */    MCD_OPC_Decode, 128, 32, 252, 2, // Opcode: t2MOVi16
+/* 2893 */    MCD_OPC_FilterValue, 1, 64, 24, 0, // Skip to: 9106
+/* 2898 */    MCD_OPC_CheckPredicate, 39, 59, 24, 0, // Skip to: 9106
+/* 2903 */    MCD_OPC_CheckField, 20, 2, 0, 52, 24, 0, // Skip to: 9106
+/* 2910 */    MCD_OPC_Decode, 254, 31, 252, 2, // Opcode: t2MOVTi16
+/* 2915 */    MCD_OPC_FilterValue, 3, 42, 24, 0, // Skip to: 9106
+/* 2920 */    MCD_OPC_ExtractField, 22, 2,  // Inst{23-22} ...
+/* 2923 */    MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 3000
+/* 2928 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 2931 */    MCD_OPC_FilterValue, 0, 26, 24, 0, // Skip to: 9106
+/* 2936 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 2939 */    MCD_OPC_FilterValue, 0, 18, 24, 0, // Skip to: 9106
+/* 2944 */    MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 2947 */    MCD_OPC_FilterValue, 0, 10, 24, 0, // Skip to: 9106
+/* 2952 */    MCD_OPC_CheckPredicate, 53, 33, 0, 0, // Skip to: 2990
+/* 2957 */    MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 2990
+/* 2964 */    MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 2990
+/* 2971 */    MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 2990
+/* 2978 */    MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 2990
+/* 2985 */    MCD_OPC_Decode, 253, 32, 253, 2, // Opcode: t2SSAT16
+/* 2990 */    MCD_OPC_CheckPredicate, 45, 223, 23, 0, // Skip to: 9106
+/* 2995 */    MCD_OPC_Decode, 252, 32, 254, 2, // Opcode: t2SSAT
+/* 3000 */    MCD_OPC_FilterValue, 1, 66, 0, 0, // Skip to: 3071
+/* 3005 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 3008 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3023
+/* 3013 */    MCD_OPC_CheckPredicate, 45, 200, 23, 0, // Skip to: 9106
+/* 3018 */    MCD_OPC_Decode, 200, 32, 255, 2, // Opcode: t2SBFX
+/* 3023 */    MCD_OPC_FilterValue, 2, 190, 23, 0, // Skip to: 9106
+/* 3028 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 3031 */    MCD_OPC_FilterValue, 0, 182, 23, 0, // Skip to: 9106
+/* 3036 */    MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 3039 */    MCD_OPC_FilterValue, 0, 174, 23, 0, // Skip to: 9106
+/* 3044 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 3061
+/* 3049 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 3061
+/* 3056 */    MCD_OPC_Decode, 247, 30, 128, 3, // Opcode: t2BFC
+/* 3061 */    MCD_OPC_CheckPredicate, 45, 152, 23, 0, // Skip to: 9106
+/* 3066 */    MCD_OPC_Decode, 248, 30, 129, 3, // Opcode: t2BFI
+/* 3071 */    MCD_OPC_FilterValue, 2, 72, 0, 0, // Skip to: 3148
+/* 3076 */    MCD_OPC_ExtractField, 5, 1,  // Inst{5} ...
+/* 3079 */    MCD_OPC_FilterValue, 0, 134, 23, 0, // Skip to: 9106
+/* 3084 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 3087 */    MCD_OPC_FilterValue, 0, 126, 23, 0, // Skip to: 9106
+/* 3092 */    MCD_OPC_ExtractField, 26, 1,  // Inst{26} ...
+/* 3095 */    MCD_OPC_FilterValue, 0, 118, 23, 0, // Skip to: 9106
+/* 3100 */    MCD_OPC_CheckPredicate, 53, 33, 0, 0, // Skip to: 3138
+/* 3105 */    MCD_OPC_CheckField, 21, 1, 1, 26, 0, 0, // Skip to: 3138
+/* 3112 */    MCD_OPC_CheckField, 12, 3, 0, 19, 0, 0, // Skip to: 3138
+/* 3119 */    MCD_OPC_CheckField, 6, 2, 0, 12, 0, 0, // Skip to: 3138
+/* 3126 */    MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 3138
+/* 3133 */    MCD_OPC_Decode, 231, 33, 253, 2, // Opcode: t2USAT16
+/* 3138 */    MCD_OPC_CheckPredicate, 45, 75, 23, 0, // Skip to: 9106
+/* 3143 */    MCD_OPC_Decode, 230, 33, 254, 2, // Opcode: t2USAT
+/* 3148 */    MCD_OPC_FilterValue, 3, 65, 23, 0, // Skip to: 9106
+/* 3153 */    MCD_OPC_CheckPredicate, 45, 60, 23, 0, // Skip to: 9106
+/* 3158 */    MCD_OPC_CheckField, 20, 2, 0, 53, 23, 0, // Skip to: 9106
+/* 3165 */    MCD_OPC_Decode, 210, 33, 255, 2, // Opcode: t2UBFX
+/* 3170 */    MCD_OPC_FilterValue, 1, 43, 23, 0, // Skip to: 9106
+/* 3175 */    MCD_OPC_ExtractField, 12, 1,  // Inst{12} ...
+/* 3178 */    MCD_OPC_FilterValue, 0, 5, 5, 0, // Skip to: 4468
+/* 3183 */    MCD_OPC_ExtractField, 14, 1,  // Inst{14} ...
+/* 3186 */    MCD_OPC_FilterValue, 0, 62, 3, 0, // Skip to: 4021
+/* 3191 */    MCD_OPC_ExtractField, 0, 12,  // Inst{11-0} ...
+/* 3194 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 3223
+/* 3199 */    MCD_OPC_CheckPredicate, 54, 166, 0, 0, // Skip to: 3370
+/* 3204 */    MCD_OPC_CheckField, 16, 11, 143, 15, 158, 0, 0, // Skip to: 3370
+/* 3212 */    MCD_OPC_CheckField, 13, 1, 0, 151, 0, 0, // Skip to: 3370
+/* 3219 */    MCD_OPC_Decode, 158, 31, 61, // Opcode: t2DCPS1
+/* 3223 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 3252
+/* 3228 */    MCD_OPC_CheckPredicate, 54, 137, 0, 0, // Skip to: 3370
+/* 3233 */    MCD_OPC_CheckField, 16, 11, 143, 15, 129, 0, 0, // Skip to: 3370
+/* 3241 */    MCD_OPC_CheckField, 13, 1, 0, 122, 0, 0, // Skip to: 3370
+/* 3248 */    MCD_OPC_Decode, 159, 31, 61, // Opcode: t2DCPS2
+/* 3252 */    MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 3281
+/* 3257 */    MCD_OPC_CheckPredicate, 54, 108, 0, 0, // Skip to: 3370
+/* 3262 */    MCD_OPC_CheckField, 16, 11, 143, 15, 100, 0, 0, // Skip to: 3370
+/* 3270 */    MCD_OPC_CheckField, 13, 1, 0, 93, 0, 0, // Skip to: 3370
+/* 3277 */    MCD_OPC_Decode, 160, 31, 61, // Opcode: t2DCPS3
+/* 3281 */    MCD_OPC_FilterValue, 18, 24, 0, 0, // Skip to: 3310
+/* 3286 */    MCD_OPC_CheckPredicate, 55, 79, 0, 0, // Skip to: 3370
+/* 3291 */    MCD_OPC_CheckField, 16, 11, 175, 7, 71, 0, 0, // Skip to: 3370
+/* 3299 */    MCD_OPC_CheckField, 13, 1, 0, 64, 0, 0, // Skip to: 3370
+/* 3306 */    MCD_OPC_Decode, 199, 33, 51, // Opcode: t2TSB
+/* 3310 */    MCD_OPC_FilterValue, 128, 30, 24, 0, 0, // Skip to: 3340
+/* 3316 */    MCD_OPC_CheckPredicate, 46, 49, 0, 0, // Skip to: 3370
+/* 3321 */    MCD_OPC_CheckField, 20, 7, 60, 42, 0, 0, // Skip to: 3370
+/* 3328 */    MCD_OPC_CheckField, 13, 1, 0, 35, 0, 0, // Skip to: 3370
+/* 3335 */    MCD_OPC_Decode, 131, 31, 130, 3, // Opcode: t2BXJ
+/* 3340 */    MCD_OPC_FilterValue, 175, 30, 24, 0, 0, // Skip to: 3370
+/* 3346 */    MCD_OPC_CheckPredicate, 56, 19, 0, 0, // Skip to: 3370
+/* 3351 */    MCD_OPC_CheckField, 16, 11, 191, 7, 11, 0, 0, // Skip to: 3370
+/* 3359 */    MCD_OPC_CheckField, 13, 1, 0, 4, 0, 0, // Skip to: 3370
+/* 3366 */    MCD_OPC_Decode, 135, 31, 61, // Opcode: t2CLREX
+/* 3370 */    MCD_OPC_ExtractField, 16, 11,  // Inst{26-16} ...
+/* 3373 */    MCD_OPC_FilterValue, 175, 7, 131, 0, 0, // Skip to: 3510
+/* 3379 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 3382 */    MCD_OPC_FilterValue, 0, 68, 0, 0, // Skip to: 3455
+/* 3387 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 3390 */    MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 3675
+/* 3395 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
+/* 3398 */    MCD_OPC_FilterValue, 0, 16, 1, 0, // Skip to: 3675
+/* 3403 */    MCD_OPC_ExtractField, 9, 2,  // Inst{10-9} ...
+/* 3406 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 3438
+/* 3411 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 3428
+/* 3416 */    MCD_OPC_CheckField, 4, 4, 15, 5, 0, 0, // Skip to: 3428
+/* 3423 */    MCD_OPC_Decode, 157, 31, 131, 3, // Opcode: t2DBG
+/* 3428 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 3438
+/* 3433 */    MCD_OPC_Decode, 167, 31, 132, 3, // Opcode: t2HINT
+/* 3438 */    MCD_OPC_CheckPredicate, 46, 232, 0, 0, // Skip to: 3675
+/* 3443 */    MCD_OPC_CheckField, 0, 5, 0, 225, 0, 0, // Skip to: 3675
+/* 3450 */    MCD_OPC_Decode, 145, 31, 133, 3, // Opcode: t2CPS2p
+/* 3455 */    MCD_OPC_FilterValue, 1, 215, 0, 0, // Skip to: 3675
+/* 3460 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 3463 */    MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 3675
+/* 3468 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
+/* 3471 */    MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 3675
+/* 3476 */    MCD_OPC_CheckPredicate, 46, 19, 0, 0, // Skip to: 3500
+/* 3481 */    MCD_OPC_CheckField, 9, 2, 0, 12, 0, 0, // Skip to: 3500
+/* 3488 */    MCD_OPC_CheckField, 5, 3, 0, 5, 0, 0, // Skip to: 3500
+/* 3495 */    MCD_OPC_Decode, 144, 31, 133, 3, // Opcode: t2CPS1p
+/* 3500 */    MCD_OPC_CheckPredicate, 46, 170, 0, 0, // Skip to: 3675
+/* 3505 */    MCD_OPC_Decode, 146, 31, 133, 3, // Opcode: t2CPS3p
+/* 3510 */    MCD_OPC_FilterValue, 191, 7, 69, 0, 0, // Skip to: 3585
+/* 3516 */    MCD_OPC_ExtractField, 4, 8,  // Inst{11-4} ...
+/* 3519 */    MCD_OPC_FilterValue, 244, 1, 16, 0, 0, // Skip to: 3541
+/* 3525 */    MCD_OPC_CheckPredicate, 57, 145, 0, 0, // Skip to: 3675
+/* 3530 */    MCD_OPC_CheckField, 13, 1, 0, 138, 0, 0, // Skip to: 3675
+/* 3537 */    MCD_OPC_Decode, 163, 31, 62, // Opcode: t2DSB
+/* 3541 */    MCD_OPC_FilterValue, 245, 1, 16, 0, 0, // Skip to: 3563
+/* 3547 */    MCD_OPC_CheckPredicate, 57, 123, 0, 0, // Skip to: 3675
+/* 3552 */    MCD_OPC_CheckField, 13, 1, 0, 116, 0, 0, // Skip to: 3675
+/* 3559 */    MCD_OPC_Decode, 162, 31, 62, // Opcode: t2DMB
+/* 3563 */    MCD_OPC_FilterValue, 246, 1, 106, 0, 0, // Skip to: 3675
+/* 3569 */    MCD_OPC_CheckPredicate, 57, 101, 0, 0, // Skip to: 3675
+/* 3574 */    MCD_OPC_CheckField, 13, 1, 0, 94, 0, 0, // Skip to: 3675
+/* 3581 */    MCD_OPC_Decode, 169, 31, 63, // Opcode: t2ISB
+/* 3585 */    MCD_OPC_FilterValue, 222, 7, 24, 0, 0, // Skip to: 3615
+/* 3591 */    MCD_OPC_CheckPredicate, 46, 79, 0, 0, // Skip to: 3675
+/* 3596 */    MCD_OPC_CheckField, 13, 1, 0, 72, 0, 0, // Skip to: 3675
+/* 3603 */    MCD_OPC_CheckField, 8, 4, 15, 65, 0, 0, // Skip to: 3675
+/* 3610 */    MCD_OPC_Decode, 181, 33, 203, 2, // Opcode: t2SUBS_PC_LR
+/* 3615 */    MCD_OPC_FilterValue, 239, 7, 24, 0, 0, // Skip to: 3645
+/* 3621 */    MCD_OPC_CheckPredicate, 46, 49, 0, 0, // Skip to: 3675
+/* 3626 */    MCD_OPC_CheckField, 13, 1, 0, 42, 0, 0, // Skip to: 3675
+/* 3633 */    MCD_OPC_CheckField, 0, 8, 0, 35, 0, 0, // Skip to: 3675
+/* 3640 */    MCD_OPC_Decode, 136, 32, 134, 3, // Opcode: t2MRS_AR
+/* 3645 */    MCD_OPC_FilterValue, 255, 7, 24, 0, 0, // Skip to: 3675
+/* 3651 */    MCD_OPC_CheckPredicate, 46, 19, 0, 0, // Skip to: 3675
+/* 3656 */    MCD_OPC_CheckField, 13, 1, 0, 12, 0, 0, // Skip to: 3675
+/* 3663 */    MCD_OPC_CheckField, 0, 8, 0, 5, 0, 0, // Skip to: 3675
+/* 3670 */    MCD_OPC_Decode, 139, 32, 134, 3, // Opcode: t2MRSsys_AR
+/* 3675 */    MCD_OPC_ExtractField, 0, 11,  // Inst{10-0} ...
+/* 3678 */    MCD_OPC_FilterValue, 13, 23, 0, 0, // Skip to: 3706
+/* 3683 */    MCD_OPC_CheckPredicate, 58, 102, 0, 0, // Skip to: 3790
+/* 3688 */    MCD_OPC_CheckField, 20, 7, 58, 95, 0, 0, // Skip to: 3790
+/* 3695 */    MCD_OPC_SoftFail, 128, 80 /* 0x2800 */, 128, 128, 60 /* 0xf0000 */,
+/* 3701 */    MCD_OPC_Decode, 154, 32, 132, 3, // Opcode: t2PACBTI
+/* 3706 */    MCD_OPC_FilterValue, 15, 23, 0, 0, // Skip to: 3734
+/* 3711 */    MCD_OPC_CheckPredicate, 58, 74, 0, 0, // Skip to: 3790
+/* 3716 */    MCD_OPC_CheckField, 20, 7, 58, 67, 0, 0, // Skip to: 3790
+/* 3723 */    MCD_OPC_SoftFail, 128, 80 /* 0x2800 */, 128, 128, 60 /* 0xf0000 */,
+/* 3729 */    MCD_OPC_Decode, 129, 31, 132, 3, // Opcode: t2BTI
+/* 3734 */    MCD_OPC_FilterValue, 29, 23, 0, 0, // Skip to: 3762
+/* 3739 */    MCD_OPC_CheckPredicate, 58, 46, 0, 0, // Skip to: 3790
+/* 3744 */    MCD_OPC_CheckField, 20, 7, 58, 39, 0, 0, // Skip to: 3790
+/* 3751 */    MCD_OPC_SoftFail, 128, 80 /* 0x2800 */, 128, 128, 60 /* 0xf0000 */,
+/* 3757 */    MCD_OPC_Decode, 153, 32, 132, 3, // Opcode: t2PAC
+/* 3762 */    MCD_OPC_FilterValue, 45, 23, 0, 0, // Skip to: 3790
+/* 3767 */    MCD_OPC_CheckPredicate, 58, 18, 0, 0, // Skip to: 3790
+/* 3772 */    MCD_OPC_CheckField, 20, 7, 58, 11, 0, 0, // Skip to: 3790
+/* 3779 */    MCD_OPC_SoftFail, 128, 80 /* 0x2800 */, 128, 128, 60 /* 0xf0000 */,
+/* 3785 */    MCD_OPC_Decode, 244, 30, 132, 3, // Opcode: t2AUT
+/* 3790 */    MCD_OPC_ExtractField, 20, 7,  // Inst{26-20} ...
+/* 3793 */    MCD_OPC_FilterValue, 59, 22, 0, 0, // Skip to: 3820
+/* 3798 */    MCD_OPC_CheckPredicate, 59, 77, 0, 0, // Skip to: 3880
+/* 3803 */    MCD_OPC_CheckField, 4, 4, 7, 70, 0, 0, // Skip to: 3880
+/* 3810 */    MCD_OPC_SoftFail, 143, 64 /* 0x200f */, 128, 158, 60 /* 0xf0f00 */,
+/* 3816 */    MCD_OPC_Decode, 196, 32, 61, // Opcode: t2SB
+/* 3820 */    MCD_OPC_FilterValue, 126, 17, 0, 0, // Skip to: 3842
+/* 3825 */    MCD_OPC_CheckPredicate, 60, 50, 0, 0, // Skip to: 3880
+/* 3830 */    MCD_OPC_CheckField, 13, 1, 0, 43, 0, 0, // Skip to: 3880
+/* 3837 */    MCD_OPC_Decode, 168, 31, 135, 3, // Opcode: t2HVC
+/* 3842 */    MCD_OPC_FilterValue, 127, 33, 0, 0, // Skip to: 3880
+/* 3847 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
+/* 3850 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3865
+/* 3855 */    MCD_OPC_CheckPredicate, 61, 20, 0, 0, // Skip to: 3880
+/* 3860 */    MCD_OPC_Decode, 211, 32, 136, 3, // Opcode: t2SMC
+/* 3865 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 3880
+/* 3870 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 3880
+/* 3875 */    MCD_OPC_Decode, 211, 33, 135, 3, // Opcode: t2UDF
+/* 3880 */    MCD_OPC_ExtractField, 21, 6,  // Inst{26-21} ...
+/* 3883 */    MCD_OPC_FilterValue, 28, 70, 0, 0, // Skip to: 3958
+/* 3888 */    MCD_OPC_CheckPredicate, 46, 19, 0, 0, // Skip to: 3912
+/* 3893 */    MCD_OPC_CheckField, 13, 1, 0, 12, 0, 0, // Skip to: 3912
+/* 3900 */    MCD_OPC_CheckField, 0, 8, 0, 5, 0, 0, // Skip to: 3912
+/* 3907 */    MCD_OPC_Decode, 140, 32, 137, 3, // Opcode: t2MSR_AR
+/* 3912 */    MCD_OPC_CheckPredicate, 62, 26, 0, 0, // Skip to: 3943
+/* 3917 */    MCD_OPC_CheckField, 13, 1, 0, 19, 0, 0, // Skip to: 3943
+/* 3924 */    MCD_OPC_CheckField, 5, 3, 1, 12, 0, 0, // Skip to: 3943
+/* 3931 */    MCD_OPC_CheckField, 0, 4, 0, 5, 0, 0, // Skip to: 3943
+/* 3938 */    MCD_OPC_Decode, 142, 32, 138, 3, // Opcode: t2MSRbanked
+/* 3943 */    MCD_OPC_CheckPredicate, 63, 63, 0, 0, // Skip to: 4011
+/* 3948 */    MCD_OPC_SoftFail, 128, 198, 64 /* 0x102300 */, 0,
+/* 3953 */    MCD_OPC_Decode, 141, 32, 139, 3, // Opcode: t2MSR_M
+/* 3958 */    MCD_OPC_FilterValue, 31, 48, 0, 0, // Skip to: 4011
+/* 3963 */    MCD_OPC_CheckPredicate, 62, 26, 0, 0, // Skip to: 3994
+/* 3968 */    MCD_OPC_CheckField, 13, 1, 0, 19, 0, 0, // Skip to: 3994
+/* 3975 */    MCD_OPC_CheckField, 5, 3, 1, 12, 0, 0, // Skip to: 3994
+/* 3982 */    MCD_OPC_CheckField, 0, 4, 0, 5, 0, 0, // Skip to: 3994
+/* 3989 */    MCD_OPC_Decode, 138, 32, 140, 3, // Opcode: t2MRSbanked
+/* 3994 */    MCD_OPC_CheckPredicate, 63, 12, 0, 0, // Skip to: 4011
+/* 3999 */    MCD_OPC_SoftFail, 128, 192, 64 /* 0x102000 */, 128, 128, 60 /* 0xf0000 */,
+/* 4006 */    MCD_OPC_Decode, 137, 32, 141, 3, // Opcode: t2MRS_M
+/* 4011 */    MCD_OPC_CheckPredicate, 45, 226, 19, 0, // Skip to: 9106
+/* 4016 */    MCD_OPC_Decode, 132, 31, 142, 3, // Opcode: t2Bcc
+/* 4021 */    MCD_OPC_FilterValue, 1, 216, 19, 0, // Skip to: 9106
+/* 4026 */    MCD_OPC_ExtractField, 13, 1,  // Inst{13} ...
+/* 4029 */    MCD_OPC_FilterValue, 0, 144, 0, 0, // Skip to: 4178
+/* 4034 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 4037 */    MCD_OPC_FilterValue, 1, 200, 19, 0, // Skip to: 9106
+/* 4042 */    MCD_OPC_ExtractField, 16, 11,  // Inst{26-16} ...
+/* 4045 */    MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 4060
+/* 4050 */    MCD_OPC_CheckPredicate, 64, 35, 0, 0, // Skip to: 4090
+/* 4055 */    MCD_OPC_Decode, 243, 31, 143, 3, // Opcode: t2LEUpdate
+/* 4060 */    MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 4075
+/* 4065 */    MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 4090
+/* 4070 */    MCD_OPC_Decode, 157, 7, 143, 3, // Opcode: MVE_LETP
+/* 4075 */    MCD_OPC_FilterValue, 47, 10, 0, 0, // Skip to: 4090
+/* 4080 */    MCD_OPC_CheckPredicate, 64, 5, 0, 0, // Skip to: 4090
+/* 4085 */    MCD_OPC_Decode, 242, 31, 143, 3, // Opcode: t2LE
+/* 4090 */    MCD_OPC_ExtractField, 20, 7,  // Inst{26-20} ...
+/* 4093 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 4108
+/* 4098 */    MCD_OPC_CheckPredicate, 22, 65, 0, 0, // Skip to: 4168
+/* 4103 */    MCD_OPC_Decode, 222, 13, 143, 3, // Opcode: MVE_WLSTP_8
+/* 4108 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4123
+/* 4113 */    MCD_OPC_CheckPredicate, 22, 50, 0, 0, // Skip to: 4168
+/* 4118 */    MCD_OPC_Decode, 219, 13, 143, 3, // Opcode: MVE_WLSTP_16
+/* 4123 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 4138
+/* 4128 */    MCD_OPC_CheckPredicate, 22, 35, 0, 0, // Skip to: 4168
+/* 4133 */    MCD_OPC_Decode, 220, 13, 143, 3, // Opcode: MVE_WLSTP_32
+/* 4138 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 4153
+/* 4143 */    MCD_OPC_CheckPredicate, 22, 20, 0, 0, // Skip to: 4168
+/* 4148 */    MCD_OPC_Decode, 221, 13, 143, 3, // Opcode: MVE_WLSTP_64
+/* 4153 */    MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 4168
+/* 4158 */    MCD_OPC_CheckPredicate, 64, 5, 0, 0, // Skip to: 4168
+/* 4163 */    MCD_OPC_Decode, 241, 33, 143, 3, // Opcode: t2WLS
+/* 4168 */    MCD_OPC_CheckPredicate, 64, 69, 19, 0, // Skip to: 9106
+/* 4173 */    MCD_OPC_Decode, 249, 30, 144, 3, // Opcode: t2BFLi
+/* 4178 */    MCD_OPC_FilterValue, 1, 59, 19, 0, // Skip to: 9106
+/* 4183 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 4186 */    MCD_OPC_FilterValue, 0, 163, 0, 0, // Skip to: 4354
+/* 4191 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 4194 */    MCD_OPC_FilterValue, 1, 43, 19, 0, // Skip to: 9106
+/* 4199 */    MCD_OPC_ExtractField, 11, 1,  // Inst{11} ...
+/* 4202 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 4314
+/* 4207 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 4210 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 4236
+/* 4215 */    MCD_OPC_CheckPredicate, 22, 94, 0, 0, // Skip to: 4314
+/* 4220 */    MCD_OPC_CheckField, 23, 4, 0, 87, 0, 0, // Skip to: 4314
+/* 4227 */    MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 0,
+/* 4231 */    MCD_OPC_Decode, 155, 7, 143, 3, // Opcode: MVE_DLSTP_8
+/* 4236 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 4262
+/* 4241 */    MCD_OPC_CheckPredicate, 22, 68, 0, 0, // Skip to: 4314
+/* 4246 */    MCD_OPC_CheckField, 23, 4, 0, 61, 0, 0, // Skip to: 4314
+/* 4253 */    MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 0,
+/* 4257 */    MCD_OPC_Decode, 152, 7, 143, 3, // Opcode: MVE_DLSTP_16
+/* 4262 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 4288
+/* 4267 */    MCD_OPC_CheckPredicate, 22, 42, 0, 0, // Skip to: 4314
+/* 4272 */    MCD_OPC_CheckField, 23, 4, 0, 35, 0, 0, // Skip to: 4314
+/* 4279 */    MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 0,
+/* 4283 */    MCD_OPC_Decode, 153, 7, 143, 3, // Opcode: MVE_DLSTP_32
+/* 4288 */    MCD_OPC_FilterValue, 3, 21, 0, 0, // Skip to: 4314
+/* 4293 */    MCD_OPC_CheckPredicate, 22, 16, 0, 0, // Skip to: 4314
+/* 4298 */    MCD_OPC_CheckField, 23, 4, 0, 9, 0, 0, // Skip to: 4314
+/* 4305 */    MCD_OPC_SoftFail, 254, 15 /* 0x7fe */, 0,
+/* 4309 */    MCD_OPC_Decode, 154, 7, 143, 3, // Opcode: MVE_DLSTP_64
+/* 4314 */    MCD_OPC_CheckPredicate, 22, 25, 0, 0, // Skip to: 4344
+/* 4319 */    MCD_OPC_CheckField, 23, 4, 0, 18, 0, 0, // Skip to: 4344
+/* 4326 */    MCD_OPC_CheckField, 16, 4, 15, 11, 0, 0, // Skip to: 4344
+/* 4333 */    MCD_OPC_SoftFail, 254, 159, 192, 1 /* 0x300ffe */, 0,
+/* 4339 */    MCD_OPC_Decode, 156, 7, 143, 3, // Opcode: MVE_LCTP
+/* 4344 */    MCD_OPC_CheckPredicate, 64, 149, 18, 0, // Skip to: 9106
+/* 4349 */    MCD_OPC_Decode, 252, 30, 145, 3, // Opcode: t2BFic
+/* 4354 */    MCD_OPC_FilterValue, 1, 139, 18, 0, // Skip to: 9106
+/* 4359 */    MCD_OPC_ExtractField, 21, 1,  // Inst{21} ...
+/* 4362 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 4416
+/* 4367 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 4370 */    MCD_OPC_FilterValue, 1, 123, 18, 0, // Skip to: 9106
+/* 4375 */    MCD_OPC_CheckPredicate, 64, 26, 0, 0, // Skip to: 4406
+/* 4380 */    MCD_OPC_CheckField, 23, 4, 0, 19, 0, 0, // Skip to: 4406
+/* 4387 */    MCD_OPC_CheckField, 20, 1, 0, 12, 0, 0, // Skip to: 4406
+/* 4394 */    MCD_OPC_CheckField, 1, 11, 0, 5, 0, 0, // Skip to: 4406
+/* 4401 */    MCD_OPC_Decode, 161, 31, 143, 3, // Opcode: t2DLS
+/* 4406 */    MCD_OPC_CheckPredicate, 64, 87, 18, 0, // Skip to: 9106
+/* 4411 */    MCD_OPC_Decode, 251, 30, 146, 3, // Opcode: t2BFi
+/* 4416 */    MCD_OPC_FilterValue, 1, 77, 18, 0, // Skip to: 9106
+/* 4421 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 4424 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4446
+/* 4429 */    MCD_OPC_CheckPredicate, 64, 64, 18, 0, // Skip to: 9106
+/* 4434 */    MCD_OPC_CheckField, 0, 12, 1, 57, 18, 0, // Skip to: 9106
+/* 4441 */    MCD_OPC_Decode, 253, 30, 147, 3, // Opcode: t2BFr
+/* 4446 */    MCD_OPC_FilterValue, 1, 47, 18, 0, // Skip to: 9106
+/* 4451 */    MCD_OPC_CheckPredicate, 64, 42, 18, 0, // Skip to: 9106
+/* 4456 */    MCD_OPC_CheckField, 0, 12, 1, 35, 18, 0, // Skip to: 9106
+/* 4463 */    MCD_OPC_Decode, 250, 30, 147, 3, // Opcode: t2BFLr
+/* 4468 */    MCD_OPC_FilterValue, 1, 25, 18, 0, // Skip to: 9106
+/* 4473 */    MCD_OPC_CheckPredicate, 39, 20, 18, 0, // Skip to: 9106
+/* 4478 */    MCD_OPC_CheckField, 14, 1, 0, 13, 18, 0, // Skip to: 9106
+/* 4485 */    MCD_OPC_Decode, 246, 30, 148, 3, // Opcode: t2B
+/* 4490 */    MCD_OPC_FilterValue, 31, 3, 18, 0, // Skip to: 9106
+/* 4495 */    MCD_OPC_ExtractField, 21, 2,  // Inst{22-21} ...
+/* 4498 */    MCD_OPC_FilterValue, 0, 96, 6, 0, // Skip to: 6135
+/* 4503 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
+/* 4506 */    MCD_OPC_FilterValue, 0, 100, 1, 0, // Skip to: 4867
+/* 4511 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 4514 */    MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 4644
+/* 4519 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 4522 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 4629
+/* 4527 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 4530 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4552
+/* 4535 */    MCD_OPC_CheckPredicate, 45, 214, 17, 0, // Skip to: 9106
+/* 4540 */    MCD_OPC_CheckField, 6, 4, 0, 207, 17, 0, // Skip to: 9106
+/* 4547 */    MCD_OPC_Decode, 161, 33, 149, 3, // Opcode: t2STRBs
+/* 4552 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4574
+/* 4557 */    MCD_OPC_CheckPredicate, 45, 192, 17, 0, // Skip to: 9106
+/* 4562 */    MCD_OPC_CheckField, 8, 1, 1, 185, 17, 0, // Skip to: 9106
+/* 4569 */    MCD_OPC_Decode, 157, 33, 150, 3, // Opcode: t2STRB_POST
+/* 4574 */    MCD_OPC_FilterValue, 3, 175, 17, 0, // Skip to: 9106
+/* 4579 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 4582 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 4614
+/* 4587 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 4604
+/* 4592 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 4604
+/* 4599 */    MCD_OPC_Decode, 156, 33, 151, 3, // Opcode: t2STRBT
+/* 4604 */    MCD_OPC_CheckPredicate, 45, 145, 17, 0, // Skip to: 9106
+/* 4609 */    MCD_OPC_Decode, 160, 33, 152, 3, // Opcode: t2STRBi8
+/* 4614 */    MCD_OPC_FilterValue, 1, 135, 17, 0, // Skip to: 9106
+/* 4619 */    MCD_OPC_CheckPredicate, 45, 130, 17, 0, // Skip to: 9106
+/* 4624 */    MCD_OPC_Decode, 158, 33, 150, 3, // Opcode: t2STRB_PRE
+/* 4629 */    MCD_OPC_FilterValue, 1, 120, 17, 0, // Skip to: 9106
+/* 4634 */    MCD_OPC_CheckPredicate, 45, 115, 17, 0, // Skip to: 9106
+/* 4639 */    MCD_OPC_Decode, 159, 33, 153, 3, // Opcode: t2STRBi12
+/* 4644 */    MCD_OPC_FilterValue, 1, 105, 17, 0, // Skip to: 9106
+/* 4649 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 4652 */    MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 4800
+/* 4657 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 4660 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4700
+/* 4665 */    MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 4668 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 4832
+/* 4673 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 4690
+/* 4678 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4690
+/* 4685 */    MCD_OPC_Decode, 164, 32, 154, 3, // Opcode: t2PLDs
+/* 4690 */    MCD_OPC_CheckPredicate, 45, 137, 0, 0, // Skip to: 4832
+/* 4695 */    MCD_OPC_Decode, 206, 31, 154, 3, // Opcode: t2LDRBs
+/* 4700 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4722
+/* 4705 */    MCD_OPC_CheckPredicate, 45, 122, 0, 0, // Skip to: 4832
+/* 4710 */    MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 4832
+/* 4717 */    MCD_OPC_Decode, 201, 31, 150, 3, // Opcode: t2LDRB_POST
+/* 4722 */    MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 4832
+/* 4727 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 4730 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 4785
+/* 4735 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
+/* 4738 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4760
+/* 4743 */    MCD_OPC_CheckPredicate, 45, 27, 0, 0, // Skip to: 4775
+/* 4748 */    MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 4775
+/* 4755 */    MCD_OPC_Decode, 162, 32, 155, 3, // Opcode: t2PLDi8
+/* 4760 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 4775
+/* 4765 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 4775
+/* 4770 */    MCD_OPC_Decode, 200, 31, 156, 3, // Opcode: t2LDRBT
+/* 4775 */    MCD_OPC_CheckPredicate, 45, 52, 0, 0, // Skip to: 4832
+/* 4780 */    MCD_OPC_Decode, 204, 31, 155, 3, // Opcode: t2LDRBi8
+/* 4785 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 4832
+/* 4790 */    MCD_OPC_CheckPredicate, 45, 37, 0, 0, // Skip to: 4832
+/* 4795 */    MCD_OPC_Decode, 202, 31, 150, 3, // Opcode: t2LDRB_PRE
+/* 4800 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 4832
+/* 4805 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 4822
+/* 4810 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4822
+/* 4817 */    MCD_OPC_Decode, 161, 32, 157, 3, // Opcode: t2PLDi12
+/* 4822 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 4832
+/* 4827 */    MCD_OPC_Decode, 203, 31, 157, 3, // Opcode: t2LDRBi12
+/* 4832 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 4835 */    MCD_OPC_FilterValue, 15, 170, 16, 0, // Skip to: 9106
+/* 4840 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 4857
+/* 4845 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4857
+/* 4852 */    MCD_OPC_Decode, 163, 32, 158, 3, // Opcode: t2PLDpci
+/* 4857 */    MCD_OPC_CheckPredicate, 45, 148, 16, 0, // Skip to: 9106
+/* 4862 */    MCD_OPC_Decode, 205, 31, 158, 3, // Opcode: t2LDRBpci
+/* 4867 */    MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 5098
+/* 4872 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 4875 */    MCD_OPC_FilterValue, 1, 130, 16, 0, // Skip to: 9106
+/* 4880 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 4883 */    MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 5031
+/* 4888 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 4891 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 4931
+/* 4896 */    MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 4899 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 5063
+/* 4904 */    MCD_OPC_CheckPredicate, 65, 12, 0, 0, // Skip to: 4921
+/* 4909 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 4921
+/* 4916 */    MCD_OPC_Decode, 168, 32, 154, 3, // Opcode: t2PLIs
+/* 4921 */    MCD_OPC_CheckPredicate, 45, 137, 0, 0, // Skip to: 5063
+/* 4926 */    MCD_OPC_Decode, 227, 31, 154, 3, // Opcode: t2LDRSBs
+/* 4931 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4953
+/* 4936 */    MCD_OPC_CheckPredicate, 45, 122, 0, 0, // Skip to: 5063
+/* 4941 */    MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 5063
+/* 4948 */    MCD_OPC_Decode, 222, 31, 150, 3, // Opcode: t2LDRSB_POST
+/* 4953 */    MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 5063
+/* 4958 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 4961 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5016
+/* 4966 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
+/* 4969 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4991
+/* 4974 */    MCD_OPC_CheckPredicate, 65, 27, 0, 0, // Skip to: 5006
+/* 4979 */    MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 5006
+/* 4986 */    MCD_OPC_Decode, 166, 32, 155, 3, // Opcode: t2PLIi8
+/* 4991 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 5006
+/* 4996 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 5006
+/* 5001 */    MCD_OPC_Decode, 221, 31, 156, 3, // Opcode: t2LDRSBT
+/* 5006 */    MCD_OPC_CheckPredicate, 45, 52, 0, 0, // Skip to: 5063
+/* 5011 */    MCD_OPC_Decode, 225, 31, 155, 3, // Opcode: t2LDRSBi8
+/* 5016 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 5063
+/* 5021 */    MCD_OPC_CheckPredicate, 45, 37, 0, 0, // Skip to: 5063
+/* 5026 */    MCD_OPC_Decode, 223, 31, 150, 3, // Opcode: t2LDRSB_PRE
+/* 5031 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 5063
+/* 5036 */    MCD_OPC_CheckPredicate, 65, 12, 0, 0, // Skip to: 5053
+/* 5041 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5053
+/* 5048 */    MCD_OPC_Decode, 165, 32, 157, 3, // Opcode: t2PLIi12
+/* 5053 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 5063
+/* 5058 */    MCD_OPC_Decode, 224, 31, 157, 3, // Opcode: t2LDRSBi12
+/* 5063 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 5066 */    MCD_OPC_FilterValue, 15, 195, 15, 0, // Skip to: 9106
+/* 5071 */    MCD_OPC_CheckPredicate, 65, 12, 0, 0, // Skip to: 5088
+/* 5076 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5088
+/* 5083 */    MCD_OPC_Decode, 167, 32, 158, 3, // Opcode: t2PLIpci
+/* 5088 */    MCD_OPC_CheckPredicate, 45, 173, 15, 0, // Skip to: 9106
+/* 5093 */    MCD_OPC_Decode, 226, 31, 158, 3, // Opcode: t2LDRSBpci
+/* 5098 */    MCD_OPC_FilterValue, 2, 207, 2, 0, // Skip to: 5822
+/* 5103 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 5106 */    MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 5526
+/* 5111 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 5114 */    MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 5196
+/* 5119 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 5122 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5144
+/* 5127 */    MCD_OPC_CheckPredicate, 45, 134, 15, 0, // Skip to: 9106
+/* 5132 */    MCD_OPC_CheckField, 12, 4, 15, 127, 15, 0, // Skip to: 9106
+/* 5139 */    MCD_OPC_Decode, 245, 31, 217, 2, // Opcode: t2LSLrr
+/* 5144 */    MCD_OPC_FilterValue, 1, 117, 15, 0, // Skip to: 9106
+/* 5149 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5152 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5174
+/* 5157 */    MCD_OPC_CheckPredicate, 53, 104, 15, 0, // Skip to: 9106
+/* 5162 */    MCD_OPC_CheckField, 12, 4, 15, 97, 15, 0, // Skip to: 9106
+/* 5169 */    MCD_OPC_Decode, 194, 32, 159, 3, // Opcode: t2SADD8
+/* 5174 */    MCD_OPC_FilterValue, 1, 87, 15, 0, // Skip to: 9106
+/* 5179 */    MCD_OPC_CheckPredicate, 53, 82, 15, 0, // Skip to: 9106
+/* 5184 */    MCD_OPC_CheckField, 12, 4, 15, 75, 15, 0, // Skip to: 9106
+/* 5191 */    MCD_OPC_Decode, 193, 32, 159, 3, // Opcode: t2SADD16
+/* 5196 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 5262
+/* 5201 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5204 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 5233
+/* 5209 */    MCD_OPC_CheckPredicate, 53, 52, 15, 0, // Skip to: 9106
+/* 5214 */    MCD_OPC_CheckField, 23, 1, 1, 45, 15, 0, // Skip to: 9106
+/* 5221 */    MCD_OPC_CheckField, 12, 4, 15, 38, 15, 0, // Skip to: 9106
+/* 5228 */    MCD_OPC_Decode, 171, 32, 159, 3, // Opcode: t2QADD8
+/* 5233 */    MCD_OPC_FilterValue, 1, 28, 15, 0, // Skip to: 9106
+/* 5238 */    MCD_OPC_CheckPredicate, 53, 23, 15, 0, // Skip to: 9106
+/* 5243 */    MCD_OPC_CheckField, 23, 1, 1, 16, 15, 0, // Skip to: 9106
+/* 5250 */    MCD_OPC_CheckField, 12, 4, 15, 9, 15, 0, // Skip to: 9106
+/* 5257 */    MCD_OPC_Decode, 170, 32, 159, 3, // Opcode: t2QADD16
+/* 5262 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 5328
+/* 5267 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5270 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 5299
+/* 5275 */    MCD_OPC_CheckPredicate, 53, 242, 14, 0, // Skip to: 9106
+/* 5280 */    MCD_OPC_CheckField, 23, 1, 1, 235, 14, 0, // Skip to: 9106
+/* 5287 */    MCD_OPC_CheckField, 12, 4, 15, 228, 14, 0, // Skip to: 9106
+/* 5294 */    MCD_OPC_Decode, 206, 32, 159, 3, // Opcode: t2SHADD8
+/* 5299 */    MCD_OPC_FilterValue, 1, 218, 14, 0, // Skip to: 9106
+/* 5304 */    MCD_OPC_CheckPredicate, 53, 213, 14, 0, // Skip to: 9106
+/* 5309 */    MCD_OPC_CheckField, 23, 1, 1, 206, 14, 0, // Skip to: 9106
+/* 5316 */    MCD_OPC_CheckField, 12, 4, 15, 199, 14, 0, // Skip to: 9106
+/* 5323 */    MCD_OPC_Decode, 205, 32, 159, 3, // Opcode: t2SHADD16
+/* 5328 */    MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 5394
+/* 5333 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5336 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 5365
+/* 5341 */    MCD_OPC_CheckPredicate, 53, 176, 14, 0, // Skip to: 9106
+/* 5346 */    MCD_OPC_CheckField, 23, 1, 1, 169, 14, 0, // Skip to: 9106
+/* 5353 */    MCD_OPC_CheckField, 12, 4, 15, 162, 14, 0, // Skip to: 9106
+/* 5360 */    MCD_OPC_Decode, 208, 33, 159, 3, // Opcode: t2UADD8
+/* 5365 */    MCD_OPC_FilterValue, 1, 152, 14, 0, // Skip to: 9106
+/* 5370 */    MCD_OPC_CheckPredicate, 53, 147, 14, 0, // Skip to: 9106
+/* 5375 */    MCD_OPC_CheckField, 23, 1, 1, 140, 14, 0, // Skip to: 9106
+/* 5382 */    MCD_OPC_CheckField, 12, 4, 15, 133, 14, 0, // Skip to: 9106
+/* 5389 */    MCD_OPC_Decode, 207, 33, 159, 3, // Opcode: t2UADD16
+/* 5394 */    MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 5460
+/* 5399 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5402 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 5431
+/* 5407 */    MCD_OPC_CheckPredicate, 53, 110, 14, 0, // Skip to: 9106
+/* 5412 */    MCD_OPC_CheckField, 23, 1, 1, 103, 14, 0, // Skip to: 9106
+/* 5419 */    MCD_OPC_CheckField, 12, 4, 15, 96, 14, 0, // Skip to: 9106
+/* 5426 */    MCD_OPC_Decode, 223, 33, 159, 3, // Opcode: t2UQADD8
+/* 5431 */    MCD_OPC_FilterValue, 1, 86, 14, 0, // Skip to: 9106
+/* 5436 */    MCD_OPC_CheckPredicate, 53, 81, 14, 0, // Skip to: 9106
+/* 5441 */    MCD_OPC_CheckField, 23, 1, 1, 74, 14, 0, // Skip to: 9106
+/* 5448 */    MCD_OPC_CheckField, 12, 4, 15, 67, 14, 0, // Skip to: 9106
+/* 5455 */    MCD_OPC_Decode, 222, 33, 159, 3, // Opcode: t2UQADD16
+/* 5460 */    MCD_OPC_FilterValue, 6, 57, 14, 0, // Skip to: 9106
+/* 5465 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5468 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 5497
+/* 5473 */    MCD_OPC_CheckPredicate, 53, 44, 14, 0, // Skip to: 9106
+/* 5478 */    MCD_OPC_CheckField, 23, 1, 1, 37, 14, 0, // Skip to: 9106
+/* 5485 */    MCD_OPC_CheckField, 12, 4, 15, 30, 14, 0, // Skip to: 9106
+/* 5492 */    MCD_OPC_Decode, 214, 33, 159, 3, // Opcode: t2UHADD8
+/* 5497 */    MCD_OPC_FilterValue, 1, 20, 14, 0, // Skip to: 9106
+/* 5502 */    MCD_OPC_CheckPredicate, 53, 15, 14, 0, // Skip to: 9106
+/* 5507 */    MCD_OPC_CheckField, 23, 1, 1, 8, 14, 0, // Skip to: 9106
+/* 5514 */    MCD_OPC_CheckField, 12, 4, 15, 1, 14, 0, // Skip to: 9106
+/* 5521 */    MCD_OPC_Decode, 213, 33, 159, 3, // Opcode: t2UHADD16
+/* 5526 */    MCD_OPC_FilterValue, 1, 247, 13, 0, // Skip to: 9106
+/* 5531 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5534 */    MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 5678
+/* 5539 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 5542 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5582
+/* 5547 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 5550 */    MCD_OPC_FilterValue, 15, 223, 13, 0, // Skip to: 9106
+/* 5555 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5572
+/* 5560 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 5572
+/* 5567 */    MCD_OPC_Decode, 193, 33, 160, 3, // Opcode: t2SXTH
+/* 5572 */    MCD_OPC_CheckPredicate, 51, 201, 13, 0, // Skip to: 9106
+/* 5577 */    MCD_OPC_Decode, 190, 33, 161, 3, // Opcode: t2SXTAH
+/* 5582 */    MCD_OPC_FilterValue, 1, 191, 13, 0, // Skip to: 9106
+/* 5587 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 5590 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5612
+/* 5595 */    MCD_OPC_CheckPredicate, 53, 178, 13, 0, // Skip to: 9106
+/* 5600 */    MCD_OPC_CheckField, 12, 4, 15, 171, 13, 0, // Skip to: 9106
+/* 5607 */    MCD_OPC_Decode, 169, 32, 162, 3, // Opcode: t2QADD
+/* 5612 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 5634
+/* 5617 */    MCD_OPC_CheckPredicate, 53, 156, 13, 0, // Skip to: 9106
+/* 5622 */    MCD_OPC_CheckField, 12, 4, 15, 149, 13, 0, // Skip to: 9106
+/* 5629 */    MCD_OPC_Decode, 173, 32, 162, 3, // Opcode: t2QDADD
+/* 5634 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5656
+/* 5639 */    MCD_OPC_CheckPredicate, 53, 134, 13, 0, // Skip to: 9106
+/* 5644 */    MCD_OPC_CheckField, 12, 4, 15, 127, 13, 0, // Skip to: 9106
+/* 5651 */    MCD_OPC_Decode, 176, 32, 162, 3, // Opcode: t2QSUB
+/* 5656 */    MCD_OPC_FilterValue, 3, 117, 13, 0, // Skip to: 9106
+/* 5661 */    MCD_OPC_CheckPredicate, 53, 112, 13, 0, // Skip to: 9106
+/* 5666 */    MCD_OPC_CheckField, 12, 4, 15, 105, 13, 0, // Skip to: 9106
+/* 5673 */    MCD_OPC_Decode, 174, 32, 162, 3, // Opcode: t2QDSUB
+/* 5678 */    MCD_OPC_FilterValue, 1, 95, 13, 0, // Skip to: 9106
+/* 5683 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 5686 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 5726
+/* 5691 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 5694 */    MCD_OPC_FilterValue, 15, 79, 13, 0, // Skip to: 9106
+/* 5699 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5716
+/* 5704 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 5716
+/* 5711 */    MCD_OPC_Decode, 240, 33, 160, 3, // Opcode: t2UXTH
+/* 5716 */    MCD_OPC_CheckPredicate, 51, 57, 13, 0, // Skip to: 9106
+/* 5721 */    MCD_OPC_Decode, 237, 33, 161, 3, // Opcode: t2UXTAH
+/* 5726 */    MCD_OPC_FilterValue, 1, 47, 13, 0, // Skip to: 9106
+/* 5731 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 5734 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5756
+/* 5739 */    MCD_OPC_CheckPredicate, 45, 34, 13, 0, // Skip to: 9106
+/* 5744 */    MCD_OPC_CheckField, 12, 4, 15, 27, 13, 0, // Skip to: 9106
+/* 5751 */    MCD_OPC_Decode, 180, 32, 163, 3, // Opcode: t2REV
+/* 5756 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 5778
+/* 5761 */    MCD_OPC_CheckPredicate, 45, 12, 13, 0, // Skip to: 9106
+/* 5766 */    MCD_OPC_CheckField, 12, 4, 15, 5, 13, 0, // Skip to: 9106
+/* 5773 */    MCD_OPC_Decode, 181, 32, 163, 3, // Opcode: t2REV16
+/* 5778 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 5800
+/* 5783 */    MCD_OPC_CheckPredicate, 45, 246, 12, 0, // Skip to: 9106
+/* 5788 */    MCD_OPC_CheckField, 12, 4, 15, 239, 12, 0, // Skip to: 9106
+/* 5795 */    MCD_OPC_Decode, 179, 32, 163, 3, // Opcode: t2RBIT
+/* 5800 */    MCD_OPC_FilterValue, 3, 229, 12, 0, // Skip to: 9106
+/* 5805 */    MCD_OPC_CheckPredicate, 45, 224, 12, 0, // Skip to: 9106
+/* 5810 */    MCD_OPC_CheckField, 12, 4, 15, 217, 12, 0, // Skip to: 9106
+/* 5817 */    MCD_OPC_Decode, 182, 32, 163, 3, // Opcode: t2REVSH
+/* 5822 */    MCD_OPC_FilterValue, 3, 207, 12, 0, // Skip to: 9106
+/* 5827 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 5830 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 5933
+/* 5835 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5838 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 5893
+/* 5843 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 5846 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 5878
+/* 5851 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 5868
+/* 5856 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5868
+/* 5863 */    MCD_OPC_Decode, 143, 32, 159, 3, // Opcode: t2MUL
+/* 5868 */    MCD_OPC_CheckPredicate, 66, 161, 12, 0, // Skip to: 9106
+/* 5873 */    MCD_OPC_Decode, 252, 31, 164, 3, // Opcode: t2MLA
+/* 5878 */    MCD_OPC_FilterValue, 1, 151, 12, 0, // Skip to: 9106
+/* 5883 */    MCD_OPC_CheckPredicate, 45, 146, 12, 0, // Skip to: 9106
+/* 5888 */    MCD_OPC_Decode, 241, 32, 165, 3, // Opcode: t2SMULL
+/* 5893 */    MCD_OPC_FilterValue, 1, 136, 12, 0, // Skip to: 9106
+/* 5898 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 5901 */    MCD_OPC_FilterValue, 0, 128, 12, 0, // Skip to: 9106
+/* 5906 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 5923
+/* 5911 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5923
+/* 5918 */    MCD_OPC_Decode, 239, 32, 159, 3, // Opcode: t2SMULBB
+/* 5923 */    MCD_OPC_CheckPredicate, 53, 106, 12, 0, // Skip to: 9106
+/* 5928 */    MCD_OPC_Decode, 212, 32, 164, 3, // Opcode: t2SMLABB
+/* 5933 */    MCD_OPC_FilterValue, 1, 65, 0, 0, // Skip to: 6003
+/* 5938 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 5941 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 5963
+/* 5946 */    MCD_OPC_CheckPredicate, 66, 83, 12, 0, // Skip to: 9106
+/* 5951 */    MCD_OPC_CheckField, 23, 1, 0, 76, 12, 0, // Skip to: 9106
+/* 5958 */    MCD_OPC_Decode, 253, 31, 164, 3, // Opcode: t2MLS
+/* 5963 */    MCD_OPC_FilterValue, 1, 66, 12, 0, // Skip to: 9106
+/* 5968 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 5971 */    MCD_OPC_FilterValue, 0, 58, 12, 0, // Skip to: 9106
+/* 5976 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 5993
+/* 5981 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 5993
+/* 5988 */    MCD_OPC_Decode, 240, 32, 159, 3, // Opcode: t2SMULBT
+/* 5993 */    MCD_OPC_CheckPredicate, 53, 36, 12, 0, // Skip to: 9106
+/* 5998 */    MCD_OPC_Decode, 213, 32, 164, 3, // Opcode: t2SMLABT
+/* 6003 */    MCD_OPC_FilterValue, 2, 43, 0, 0, // Skip to: 6051
+/* 6008 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6011 */    MCD_OPC_FilterValue, 1, 18, 12, 0, // Skip to: 9106
+/* 6016 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6019 */    MCD_OPC_FilterValue, 0, 10, 12, 0, // Skip to: 9106
+/* 6024 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 6041
+/* 6029 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6041
+/* 6036 */    MCD_OPC_Decode, 242, 32, 159, 3, // Opcode: t2SMULTB
+/* 6041 */    MCD_OPC_CheckPredicate, 53, 244, 11, 0, // Skip to: 9106
+/* 6046 */    MCD_OPC_Decode, 223, 32, 164, 3, // Opcode: t2SMLATB
+/* 6051 */    MCD_OPC_FilterValue, 3, 43, 0, 0, // Skip to: 6099
+/* 6056 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6059 */    MCD_OPC_FilterValue, 1, 226, 11, 0, // Skip to: 9106
+/* 6064 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6067 */    MCD_OPC_FilterValue, 0, 218, 11, 0, // Skip to: 9106
+/* 6072 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 6089
+/* 6077 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6089
+/* 6084 */    MCD_OPC_Decode, 243, 32, 159, 3, // Opcode: t2SMULTT
+/* 6089 */    MCD_OPC_CheckPredicate, 53, 196, 11, 0, // Skip to: 9106
+/* 6094 */    MCD_OPC_Decode, 224, 32, 164, 3, // Opcode: t2SMLATT
+/* 6099 */    MCD_OPC_FilterValue, 15, 186, 11, 0, // Skip to: 9106
+/* 6104 */    MCD_OPC_CheckPredicate, 67, 181, 11, 0, // Skip to: 9106
+/* 6109 */    MCD_OPC_CheckField, 23, 1, 1, 174, 11, 0, // Skip to: 9106
+/* 6116 */    MCD_OPC_CheckField, 20, 1, 1, 167, 11, 0, // Skip to: 9106
+/* 6123 */    MCD_OPC_CheckField, 12, 4, 15, 160, 11, 0, // Skip to: 9106
+/* 6130 */    MCD_OPC_Decode, 201, 32, 159, 3, // Opcode: t2SDIV
+/* 6135 */    MCD_OPC_FilterValue, 1, 129, 4, 0, // Skip to: 7293
+/* 6140 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
+/* 6143 */    MCD_OPC_FilterValue, 0, 82, 1, 0, // Skip to: 6486
+/* 6148 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6151 */    MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 6281
+/* 6156 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6159 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6266
+/* 6164 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 6167 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6189
+/* 6172 */    MCD_OPC_CheckPredicate, 45, 113, 11, 0, // Skip to: 9106
+/* 6177 */    MCD_OPC_CheckField, 6, 4, 0, 106, 11, 0, // Skip to: 9106
+/* 6184 */    MCD_OPC_Decode, 174, 33, 149, 3, // Opcode: t2STRHs
+/* 6189 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6211
+/* 6194 */    MCD_OPC_CheckPredicate, 45, 91, 11, 0, // Skip to: 9106
+/* 6199 */    MCD_OPC_CheckField, 8, 1, 1, 84, 11, 0, // Skip to: 9106
+/* 6206 */    MCD_OPC_Decode, 170, 33, 150, 3, // Opcode: t2STRH_POST
+/* 6211 */    MCD_OPC_FilterValue, 3, 74, 11, 0, // Skip to: 9106
+/* 6216 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 6219 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6251
+/* 6224 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6241
+/* 6229 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6241
+/* 6236 */    MCD_OPC_Decode, 169, 33, 151, 3, // Opcode: t2STRHT
+/* 6241 */    MCD_OPC_CheckPredicate, 45, 44, 11, 0, // Skip to: 9106
+/* 6246 */    MCD_OPC_Decode, 173, 33, 152, 3, // Opcode: t2STRHi8
+/* 6251 */    MCD_OPC_FilterValue, 1, 34, 11, 0, // Skip to: 9106
+/* 6256 */    MCD_OPC_CheckPredicate, 45, 29, 11, 0, // Skip to: 9106
+/* 6261 */    MCD_OPC_Decode, 171, 33, 150, 3, // Opcode: t2STRH_PRE
+/* 6266 */    MCD_OPC_FilterValue, 1, 19, 11, 0, // Skip to: 9106
+/* 6271 */    MCD_OPC_CheckPredicate, 45, 14, 11, 0, // Skip to: 9106
+/* 6276 */    MCD_OPC_Decode, 172, 33, 153, 3, // Opcode: t2STRHi12
+/* 6281 */    MCD_OPC_FilterValue, 1, 4, 11, 0, // Skip to: 9106
+/* 6286 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6289 */    MCD_OPC_FilterValue, 0, 143, 0, 0, // Skip to: 6437
+/* 6294 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 6297 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6337
+/* 6302 */    MCD_OPC_ExtractField, 6, 4,  // Inst{9-6} ...
+/* 6305 */    MCD_OPC_FilterValue, 0, 159, 0, 0, // Skip to: 6469
+/* 6310 */    MCD_OPC_CheckPredicate, 68, 12, 0, 0, // Skip to: 6327
+/* 6315 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6327
+/* 6322 */    MCD_OPC_Decode, 160, 32, 154, 3, // Opcode: t2PLDWs
+/* 6327 */    MCD_OPC_CheckPredicate, 45, 137, 0, 0, // Skip to: 6469
+/* 6332 */    MCD_OPC_Decode, 220, 31, 154, 3, // Opcode: t2LDRHs
+/* 6337 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6359
+/* 6342 */    MCD_OPC_CheckPredicate, 45, 122, 0, 0, // Skip to: 6469
+/* 6347 */    MCD_OPC_CheckField, 8, 1, 1, 115, 0, 0, // Skip to: 6469
+/* 6354 */    MCD_OPC_Decode, 215, 31, 150, 3, // Opcode: t2LDRH_POST
+/* 6359 */    MCD_OPC_FilterValue, 3, 105, 0, 0, // Skip to: 6469
+/* 6364 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 6367 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 6422
+/* 6372 */    MCD_OPC_ExtractField, 9, 1,  // Inst{9} ...
+/* 6375 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6397
+/* 6380 */    MCD_OPC_CheckPredicate, 68, 27, 0, 0, // Skip to: 6412
+/* 6385 */    MCD_OPC_CheckField, 12, 4, 15, 20, 0, 0, // Skip to: 6412
+/* 6392 */    MCD_OPC_Decode, 159, 32, 155, 3, // Opcode: t2PLDWi8
+/* 6397 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6412
+/* 6402 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 6412
+/* 6407 */    MCD_OPC_Decode, 214, 31, 156, 3, // Opcode: t2LDRHT
+/* 6412 */    MCD_OPC_CheckPredicate, 45, 52, 0, 0, // Skip to: 6469
+/* 6417 */    MCD_OPC_Decode, 218, 31, 155, 3, // Opcode: t2LDRHi8
+/* 6422 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 6469
+/* 6427 */    MCD_OPC_CheckPredicate, 45, 37, 0, 0, // Skip to: 6469
+/* 6432 */    MCD_OPC_Decode, 216, 31, 150, 3, // Opcode: t2LDRH_PRE
+/* 6437 */    MCD_OPC_FilterValue, 1, 27, 0, 0, // Skip to: 6469
+/* 6442 */    MCD_OPC_CheckPredicate, 68, 12, 0, 0, // Skip to: 6459
+/* 6447 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 6459
+/* 6454 */    MCD_OPC_Decode, 158, 32, 157, 3, // Opcode: t2PLDWi12
+/* 6459 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 6469
+/* 6464 */    MCD_OPC_Decode, 217, 31, 157, 3, // Opcode: t2LDRHi12
+/* 6469 */    MCD_OPC_CheckPredicate, 45, 72, 10, 0, // Skip to: 9106
+/* 6474 */    MCD_OPC_CheckField, 16, 4, 15, 65, 10, 0, // Skip to: 9106
+/* 6481 */    MCD_OPC_Decode, 219, 31, 158, 3, // Opcode: t2LDRHpci
+/* 6486 */    MCD_OPC_FilterValue, 1, 150, 0, 0, // Skip to: 6641
+/* 6491 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6494 */    MCD_OPC_FilterValue, 1, 47, 10, 0, // Skip to: 9106
+/* 6499 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6502 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 6609
+/* 6507 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 6510 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6532
+/* 6515 */    MCD_OPC_CheckPredicate, 45, 104, 0, 0, // Skip to: 6624
+/* 6520 */    MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 6624
+/* 6527 */    MCD_OPC_Decode, 234, 31, 154, 3, // Opcode: t2LDRSHs
+/* 6532 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 6554
+/* 6537 */    MCD_OPC_CheckPredicate, 45, 82, 0, 0, // Skip to: 6624
+/* 6542 */    MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 6624
+/* 6549 */    MCD_OPC_Decode, 229, 31, 150, 3, // Opcode: t2LDRSH_POST
+/* 6554 */    MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 6624
+/* 6559 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 6562 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 6594
+/* 6567 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 6584
+/* 6572 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 6584
+/* 6579 */    MCD_OPC_Decode, 228, 31, 156, 3, // Opcode: t2LDRSHT
+/* 6584 */    MCD_OPC_CheckPredicate, 45, 35, 0, 0, // Skip to: 6624
+/* 6589 */    MCD_OPC_Decode, 232, 31, 155, 3, // Opcode: t2LDRSHi8
+/* 6594 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 6624
+/* 6599 */    MCD_OPC_CheckPredicate, 45, 20, 0, 0, // Skip to: 6624
+/* 6604 */    MCD_OPC_Decode, 230, 31, 150, 3, // Opcode: t2LDRSH_PRE
+/* 6609 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 6624
+/* 6614 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 6624
+/* 6619 */    MCD_OPC_Decode, 231, 31, 157, 3, // Opcode: t2LDRSHi12
+/* 6624 */    MCD_OPC_CheckPredicate, 45, 173, 9, 0, // Skip to: 9106
+/* 6629 */    MCD_OPC_CheckField, 16, 4, 15, 166, 9, 0, // Skip to: 9106
+/* 6636 */    MCD_OPC_Decode, 233, 31, 158, 3, // Opcode: t2LDRSHpci
+/* 6641 */    MCD_OPC_FilterValue, 2, 156, 1, 0, // Skip to: 7058
+/* 6646 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 6649 */    MCD_OPC_FilterValue, 0, 242, 0, 0, // Skip to: 6896
+/* 6654 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 6657 */    MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 6716
+/* 6662 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6665 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 6687
+/* 6670 */    MCD_OPC_CheckPredicate, 45, 127, 9, 0, // Skip to: 9106
+/* 6675 */    MCD_OPC_CheckField, 12, 4, 15, 120, 9, 0, // Skip to: 9106
+/* 6682 */    MCD_OPC_Decode, 247, 31, 217, 2, // Opcode: t2LSRrr
+/* 6687 */    MCD_OPC_FilterValue, 1, 110, 9, 0, // Skip to: 9106
+/* 6692 */    MCD_OPC_CheckPredicate, 53, 105, 9, 0, // Skip to: 9106
+/* 6697 */    MCD_OPC_CheckField, 20, 1, 0, 98, 9, 0, // Skip to: 9106
+/* 6704 */    MCD_OPC_CheckField, 12, 4, 15, 91, 9, 0, // Skip to: 9106
+/* 6711 */    MCD_OPC_Decode, 195, 32, 159, 3, // Opcode: t2SASX
+/* 6716 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 6752
+/* 6721 */    MCD_OPC_CheckPredicate, 53, 76, 9, 0, // Skip to: 9106
+/* 6726 */    MCD_OPC_CheckField, 23, 1, 1, 69, 9, 0, // Skip to: 9106
+/* 6733 */    MCD_OPC_CheckField, 20, 1, 0, 62, 9, 0, // Skip to: 9106
+/* 6740 */    MCD_OPC_CheckField, 12, 4, 15, 55, 9, 0, // Skip to: 9106
+/* 6747 */    MCD_OPC_Decode, 172, 32, 159, 3, // Opcode: t2QASX
+/* 6752 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 6788
+/* 6757 */    MCD_OPC_CheckPredicate, 53, 40, 9, 0, // Skip to: 9106
+/* 6762 */    MCD_OPC_CheckField, 23, 1, 1, 33, 9, 0, // Skip to: 9106
+/* 6769 */    MCD_OPC_CheckField, 20, 1, 0, 26, 9, 0, // Skip to: 9106
+/* 6776 */    MCD_OPC_CheckField, 12, 4, 15, 19, 9, 0, // Skip to: 9106
+/* 6783 */    MCD_OPC_Decode, 207, 32, 159, 3, // Opcode: t2SHASX
+/* 6788 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 6824
+/* 6793 */    MCD_OPC_CheckPredicate, 53, 4, 9, 0, // Skip to: 9106
+/* 6798 */    MCD_OPC_CheckField, 23, 1, 1, 253, 8, 0, // Skip to: 9106
+/* 6805 */    MCD_OPC_CheckField, 20, 1, 0, 246, 8, 0, // Skip to: 9106
+/* 6812 */    MCD_OPC_CheckField, 12, 4, 15, 239, 8, 0, // Skip to: 9106
+/* 6819 */    MCD_OPC_Decode, 209, 33, 159, 3, // Opcode: t2UASX
+/* 6824 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 6860
+/* 6829 */    MCD_OPC_CheckPredicate, 53, 224, 8, 0, // Skip to: 9106
+/* 6834 */    MCD_OPC_CheckField, 23, 1, 1, 217, 8, 0, // Skip to: 9106
+/* 6841 */    MCD_OPC_CheckField, 20, 1, 0, 210, 8, 0, // Skip to: 9106
+/* 6848 */    MCD_OPC_CheckField, 12, 4, 15, 203, 8, 0, // Skip to: 9106
+/* 6855 */    MCD_OPC_Decode, 224, 33, 159, 3, // Opcode: t2UQASX
+/* 6860 */    MCD_OPC_FilterValue, 6, 193, 8, 0, // Skip to: 9106
+/* 6865 */    MCD_OPC_CheckPredicate, 53, 188, 8, 0, // Skip to: 9106
+/* 6870 */    MCD_OPC_CheckField, 23, 1, 1, 181, 8, 0, // Skip to: 9106
+/* 6877 */    MCD_OPC_CheckField, 20, 1, 0, 174, 8, 0, // Skip to: 9106
+/* 6884 */    MCD_OPC_CheckField, 12, 4, 15, 167, 8, 0, // Skip to: 9106
+/* 6891 */    MCD_OPC_Decode, 215, 33, 159, 3, // Opcode: t2UHASX
+/* 6896 */    MCD_OPC_FilterValue, 1, 157, 8, 0, // Skip to: 9106
+/* 6901 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 6904 */    MCD_OPC_FilterValue, 0, 72, 0, 0, // Skip to: 6981
+/* 6909 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6912 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 6952
+/* 6917 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 6920 */    MCD_OPC_FilterValue, 15, 133, 8, 0, // Skip to: 9106
+/* 6925 */    MCD_OPC_CheckPredicate, 51, 12, 0, 0, // Skip to: 6942
+/* 6930 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 6942
+/* 6937 */    MCD_OPC_Decode, 192, 33, 160, 3, // Opcode: t2SXTB16
+/* 6942 */    MCD_OPC_CheckPredicate, 51, 111, 8, 0, // Skip to: 9106
+/* 6947 */    MCD_OPC_Decode, 189, 33, 161, 3, // Opcode: t2SXTAB16
+/* 6952 */    MCD_OPC_FilterValue, 1, 101, 8, 0, // Skip to: 9106
+/* 6957 */    MCD_OPC_CheckPredicate, 53, 96, 8, 0, // Skip to: 9106
+/* 6962 */    MCD_OPC_CheckField, 12, 4, 15, 89, 8, 0, // Skip to: 9106
+/* 6969 */    MCD_OPC_CheckField, 4, 3, 0, 82, 8, 0, // Skip to: 9106
+/* 6976 */    MCD_OPC_Decode, 202, 32, 166, 3, // Opcode: t2SEL
+/* 6981 */    MCD_OPC_FilterValue, 1, 72, 8, 0, // Skip to: 9106
+/* 6986 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 6989 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7029
+/* 6994 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 6997 */    MCD_OPC_FilterValue, 15, 56, 8, 0, // Skip to: 9106
+/* 7002 */    MCD_OPC_CheckPredicate, 51, 12, 0, 0, // Skip to: 7019
+/* 7007 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 7019
+/* 7014 */    MCD_OPC_Decode, 239, 33, 160, 3, // Opcode: t2UXTB16
+/* 7019 */    MCD_OPC_CheckPredicate, 51, 34, 8, 0, // Skip to: 9106
+/* 7024 */    MCD_OPC_Decode, 236, 33, 161, 3, // Opcode: t2UXTAB16
+/* 7029 */    MCD_OPC_FilterValue, 1, 24, 8, 0, // Skip to: 9106
+/* 7034 */    MCD_OPC_CheckPredicate, 45, 19, 8, 0, // Skip to: 9106
+/* 7039 */    MCD_OPC_CheckField, 12, 4, 15, 12, 8, 0, // Skip to: 9106
+/* 7046 */    MCD_OPC_CheckField, 4, 3, 0, 5, 8, 0, // Skip to: 9106
+/* 7053 */    MCD_OPC_Decode, 137, 31, 163, 3, // Opcode: t2CLZ
+/* 7058 */    MCD_OPC_FilterValue, 3, 251, 7, 0, // Skip to: 9106
+/* 7063 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 7066 */    MCD_OPC_FilterValue, 0, 98, 0, 0, // Skip to: 7169
+/* 7071 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7074 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 7129
+/* 7079 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7082 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7114
+/* 7087 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 7104
+/* 7092 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7104
+/* 7099 */    MCD_OPC_Decode, 237, 32, 159, 3, // Opcode: t2SMUAD
+/* 7104 */    MCD_OPC_CheckPredicate, 53, 205, 7, 0, // Skip to: 9106
+/* 7109 */    MCD_OPC_Decode, 214, 32, 164, 3, // Opcode: t2SMLAD
+/* 7114 */    MCD_OPC_FilterValue, 1, 195, 7, 0, // Skip to: 9106
+/* 7119 */    MCD_OPC_CheckPredicate, 45, 190, 7, 0, // Skip to: 9106
+/* 7124 */    MCD_OPC_Decode, 221, 33, 165, 3, // Opcode: t2UMULL
+/* 7129 */    MCD_OPC_FilterValue, 1, 180, 7, 0, // Skip to: 9106
+/* 7134 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7137 */    MCD_OPC_FilterValue, 0, 172, 7, 0, // Skip to: 9106
+/* 7142 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 7159
+/* 7147 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7159
+/* 7154 */    MCD_OPC_Decode, 244, 32, 159, 3, // Opcode: t2SMULWB
+/* 7159 */    MCD_OPC_CheckPredicate, 53, 150, 7, 0, // Skip to: 9106
+/* 7164 */    MCD_OPC_Decode, 225, 32, 164, 3, // Opcode: t2SMLAWB
+/* 7169 */    MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 7257
+/* 7174 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7177 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 7217
+/* 7182 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7185 */    MCD_OPC_FilterValue, 0, 124, 7, 0, // Skip to: 9106
+/* 7190 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 7207
+/* 7195 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7207
+/* 7202 */    MCD_OPC_Decode, 238, 32, 159, 3, // Opcode: t2SMUADX
+/* 7207 */    MCD_OPC_CheckPredicate, 53, 102, 7, 0, // Skip to: 9106
+/* 7212 */    MCD_OPC_Decode, 215, 32, 164, 3, // Opcode: t2SMLADX
+/* 7217 */    MCD_OPC_FilterValue, 1, 92, 7, 0, // Skip to: 9106
+/* 7222 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7225 */    MCD_OPC_FilterValue, 0, 84, 7, 0, // Skip to: 9106
+/* 7230 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 7247
+/* 7235 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 7247
+/* 7242 */    MCD_OPC_Decode, 245, 32, 159, 3, // Opcode: t2SMULWT
+/* 7247 */    MCD_OPC_CheckPredicate, 53, 62, 7, 0, // Skip to: 9106
+/* 7252 */    MCD_OPC_Decode, 226, 32, 164, 3, // Opcode: t2SMLAWT
+/* 7257 */    MCD_OPC_FilterValue, 15, 52, 7, 0, // Skip to: 9106
+/* 7262 */    MCD_OPC_CheckPredicate, 67, 47, 7, 0, // Skip to: 9106
+/* 7267 */    MCD_OPC_CheckField, 23, 1, 1, 40, 7, 0, // Skip to: 9106
+/* 7274 */    MCD_OPC_CheckField, 20, 1, 1, 33, 7, 0, // Skip to: 9106
+/* 7281 */    MCD_OPC_CheckField, 12, 4, 15, 26, 7, 0, // Skip to: 9106
+/* 7288 */    MCD_OPC_Decode, 212, 33, 159, 3, // Opcode: t2UDIV
+/* 7293 */    MCD_OPC_FilterValue, 2, 141, 5, 0, // Skip to: 8719
+/* 7298 */    MCD_OPC_ExtractField, 24, 3,  // Inst{26-24} ...
+/* 7301 */    MCD_OPC_FilterValue, 0, 24, 1, 0, // Skip to: 7586
+/* 7306 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7309 */    MCD_OPC_FilterValue, 0, 125, 0, 0, // Skip to: 7439
+/* 7314 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7317 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 7424
+/* 7322 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 7325 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7347
+/* 7330 */    MCD_OPC_CheckPredicate, 45, 235, 6, 0, // Skip to: 9106
+/* 7335 */    MCD_OPC_CheckField, 6, 4, 0, 228, 6, 0, // Skip to: 9106
+/* 7342 */    MCD_OPC_Decode, 180, 33, 167, 3, // Opcode: t2STRs
+/* 7347 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 7369
+/* 7352 */    MCD_OPC_CheckPredicate, 45, 213, 6, 0, // Skip to: 9106
+/* 7357 */    MCD_OPC_CheckField, 8, 1, 1, 206, 6, 0, // Skip to: 9106
+/* 7364 */    MCD_OPC_Decode, 176, 33, 150, 3, // Opcode: t2STR_POST
+/* 7369 */    MCD_OPC_FilterValue, 3, 196, 6, 0, // Skip to: 9106
+/* 7374 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 7377 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7409
+/* 7382 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7399
+/* 7387 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 7399
+/* 7394 */    MCD_OPC_Decode, 175, 33, 151, 3, // Opcode: t2STRT
+/* 7399 */    MCD_OPC_CheckPredicate, 45, 166, 6, 0, // Skip to: 9106
+/* 7404 */    MCD_OPC_Decode, 179, 33, 168, 3, // Opcode: t2STRi8
+/* 7409 */    MCD_OPC_FilterValue, 1, 156, 6, 0, // Skip to: 9106
+/* 7414 */    MCD_OPC_CheckPredicate, 45, 151, 6, 0, // Skip to: 9106
+/* 7419 */    MCD_OPC_Decode, 177, 33, 150, 3, // Opcode: t2STR_PRE
+/* 7424 */    MCD_OPC_FilterValue, 1, 141, 6, 0, // Skip to: 9106
+/* 7429 */    MCD_OPC_CheckPredicate, 45, 136, 6, 0, // Skip to: 9106
+/* 7434 */    MCD_OPC_Decode, 178, 33, 169, 3, // Opcode: t2STRi12
+/* 7439 */    MCD_OPC_FilterValue, 1, 126, 6, 0, // Skip to: 9106
+/* 7444 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7447 */    MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 7554
+/* 7452 */    MCD_OPC_ExtractField, 10, 2,  // Inst{11-10} ...
+/* 7455 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7477
+/* 7460 */    MCD_OPC_CheckPredicate, 45, 104, 0, 0, // Skip to: 7569
+/* 7465 */    MCD_OPC_CheckField, 6, 4, 0, 97, 0, 0, // Skip to: 7569
+/* 7472 */    MCD_OPC_Decode, 241, 31, 154, 3, // Opcode: t2LDRs
+/* 7477 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 7499
+/* 7482 */    MCD_OPC_CheckPredicate, 45, 82, 0, 0, // Skip to: 7569
+/* 7487 */    MCD_OPC_CheckField, 8, 1, 1, 75, 0, 0, // Skip to: 7569
+/* 7494 */    MCD_OPC_Decode, 236, 31, 150, 3, // Opcode: t2LDR_POST
+/* 7499 */    MCD_OPC_FilterValue, 3, 65, 0, 0, // Skip to: 7569
+/* 7504 */    MCD_OPC_ExtractField, 8, 1,  // Inst{8} ...
+/* 7507 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 7539
+/* 7512 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 7529
+/* 7517 */    MCD_OPC_CheckField, 9, 1, 1, 5, 0, 0, // Skip to: 7529
+/* 7524 */    MCD_OPC_Decode, 235, 31, 156, 3, // Opcode: t2LDRT
+/* 7529 */    MCD_OPC_CheckPredicate, 45, 35, 0, 0, // Skip to: 7569
+/* 7534 */    MCD_OPC_Decode, 239, 31, 155, 3, // Opcode: t2LDRi8
+/* 7539 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 7569
+/* 7544 */    MCD_OPC_CheckPredicate, 45, 20, 0, 0, // Skip to: 7569
+/* 7549 */    MCD_OPC_Decode, 237, 31, 150, 3, // Opcode: t2LDR_PRE
+/* 7554 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 7569
+/* 7559 */    MCD_OPC_CheckPredicate, 45, 5, 0, 0, // Skip to: 7569
+/* 7564 */    MCD_OPC_Decode, 238, 31, 157, 3, // Opcode: t2LDRi12
+/* 7569 */    MCD_OPC_CheckPredicate, 45, 252, 5, 0, // Skip to: 9106
+/* 7574 */    MCD_OPC_CheckField, 16, 4, 15, 245, 5, 0, // Skip to: 9106
+/* 7581 */    MCD_OPC_Decode, 240, 31, 158, 3, // Opcode: t2LDRpci
+/* 7586 */    MCD_OPC_FilterValue, 2, 163, 2, 0, // Skip to: 8266
+/* 7591 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 7594 */    MCD_OPC_FilterValue, 0, 159, 1, 0, // Skip to: 8014
+/* 7599 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 7602 */    MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 7684
+/* 7607 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 7610 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7632
+/* 7615 */    MCD_OPC_CheckPredicate, 45, 206, 5, 0, // Skip to: 9106
+/* 7620 */    MCD_OPC_CheckField, 12, 4, 15, 199, 5, 0, // Skip to: 9106
+/* 7627 */    MCD_OPC_Decode, 243, 30, 217, 2, // Opcode: t2ASRrr
+/* 7632 */    MCD_OPC_FilterValue, 1, 189, 5, 0, // Skip to: 9106
+/* 7637 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7640 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 7662
+/* 7645 */    MCD_OPC_CheckPredicate, 53, 176, 5, 0, // Skip to: 9106
+/* 7650 */    MCD_OPC_CheckField, 12, 4, 15, 169, 5, 0, // Skip to: 9106
+/* 7657 */    MCD_OPC_Decode, 128, 33, 159, 3, // Opcode: t2SSUB8
+/* 7662 */    MCD_OPC_FilterValue, 1, 159, 5, 0, // Skip to: 9106
+/* 7667 */    MCD_OPC_CheckPredicate, 53, 154, 5, 0, // Skip to: 9106
+/* 7672 */    MCD_OPC_CheckField, 12, 4, 15, 147, 5, 0, // Skip to: 9106
+/* 7679 */    MCD_OPC_Decode, 255, 32, 159, 3, // Opcode: t2SSUB16
+/* 7684 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 7750
+/* 7689 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7692 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7721
+/* 7697 */    MCD_OPC_CheckPredicate, 53, 124, 5, 0, // Skip to: 9106
+/* 7702 */    MCD_OPC_CheckField, 23, 1, 1, 117, 5, 0, // Skip to: 9106
+/* 7709 */    MCD_OPC_CheckField, 12, 4, 15, 110, 5, 0, // Skip to: 9106
+/* 7716 */    MCD_OPC_Decode, 178, 32, 159, 3, // Opcode: t2QSUB8
+/* 7721 */    MCD_OPC_FilterValue, 1, 100, 5, 0, // Skip to: 9106
+/* 7726 */    MCD_OPC_CheckPredicate, 53, 95, 5, 0, // Skip to: 9106
+/* 7731 */    MCD_OPC_CheckField, 23, 1, 1, 88, 5, 0, // Skip to: 9106
+/* 7738 */    MCD_OPC_CheckField, 12, 4, 15, 81, 5, 0, // Skip to: 9106
+/* 7745 */    MCD_OPC_Decode, 177, 32, 159, 3, // Opcode: t2QSUB16
+/* 7750 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 7816
+/* 7755 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7758 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7787
+/* 7763 */    MCD_OPC_CheckPredicate, 53, 58, 5, 0, // Skip to: 9106
+/* 7768 */    MCD_OPC_CheckField, 23, 1, 1, 51, 5, 0, // Skip to: 9106
+/* 7775 */    MCD_OPC_CheckField, 12, 4, 15, 44, 5, 0, // Skip to: 9106
+/* 7782 */    MCD_OPC_Decode, 210, 32, 159, 3, // Opcode: t2SHSUB8
+/* 7787 */    MCD_OPC_FilterValue, 1, 34, 5, 0, // Skip to: 9106
+/* 7792 */    MCD_OPC_CheckPredicate, 53, 29, 5, 0, // Skip to: 9106
+/* 7797 */    MCD_OPC_CheckField, 23, 1, 1, 22, 5, 0, // Skip to: 9106
+/* 7804 */    MCD_OPC_CheckField, 12, 4, 15, 15, 5, 0, // Skip to: 9106
+/* 7811 */    MCD_OPC_Decode, 209, 32, 159, 3, // Opcode: t2SHSUB16
+/* 7816 */    MCD_OPC_FilterValue, 4, 61, 0, 0, // Skip to: 7882
+/* 7821 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7824 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7853
+/* 7829 */    MCD_OPC_CheckPredicate, 53, 248, 4, 0, // Skip to: 9106
+/* 7834 */    MCD_OPC_CheckField, 23, 1, 1, 241, 4, 0, // Skip to: 9106
+/* 7841 */    MCD_OPC_CheckField, 12, 4, 15, 234, 4, 0, // Skip to: 9106
+/* 7848 */    MCD_OPC_Decode, 234, 33, 159, 3, // Opcode: t2USUB8
+/* 7853 */    MCD_OPC_FilterValue, 1, 224, 4, 0, // Skip to: 9106
+/* 7858 */    MCD_OPC_CheckPredicate, 53, 219, 4, 0, // Skip to: 9106
+/* 7863 */    MCD_OPC_CheckField, 23, 1, 1, 212, 4, 0, // Skip to: 9106
+/* 7870 */    MCD_OPC_CheckField, 12, 4, 15, 205, 4, 0, // Skip to: 9106
+/* 7877 */    MCD_OPC_Decode, 233, 33, 159, 3, // Opcode: t2USUB16
+/* 7882 */    MCD_OPC_FilterValue, 5, 61, 0, 0, // Skip to: 7948
+/* 7887 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7890 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7919
+/* 7895 */    MCD_OPC_CheckPredicate, 53, 182, 4, 0, // Skip to: 9106
+/* 7900 */    MCD_OPC_CheckField, 23, 1, 1, 175, 4, 0, // Skip to: 9106
+/* 7907 */    MCD_OPC_CheckField, 12, 4, 15, 168, 4, 0, // Skip to: 9106
+/* 7914 */    MCD_OPC_Decode, 227, 33, 159, 3, // Opcode: t2UQSUB8
+/* 7919 */    MCD_OPC_FilterValue, 1, 158, 4, 0, // Skip to: 9106
+/* 7924 */    MCD_OPC_CheckPredicate, 53, 153, 4, 0, // Skip to: 9106
+/* 7929 */    MCD_OPC_CheckField, 23, 1, 1, 146, 4, 0, // Skip to: 9106
+/* 7936 */    MCD_OPC_CheckField, 12, 4, 15, 139, 4, 0, // Skip to: 9106
+/* 7943 */    MCD_OPC_Decode, 226, 33, 159, 3, // Opcode: t2UQSUB16
+/* 7948 */    MCD_OPC_FilterValue, 6, 129, 4, 0, // Skip to: 9106
+/* 7953 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 7956 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 7985
+/* 7961 */    MCD_OPC_CheckPredicate, 53, 116, 4, 0, // Skip to: 9106
+/* 7966 */    MCD_OPC_CheckField, 23, 1, 1, 109, 4, 0, // Skip to: 9106
+/* 7973 */    MCD_OPC_CheckField, 12, 4, 15, 102, 4, 0, // Skip to: 9106
+/* 7980 */    MCD_OPC_Decode, 218, 33, 159, 3, // Opcode: t2UHSUB8
+/* 7985 */    MCD_OPC_FilterValue, 1, 92, 4, 0, // Skip to: 9106
+/* 7990 */    MCD_OPC_CheckPredicate, 53, 87, 4, 0, // Skip to: 9106
+/* 7995 */    MCD_OPC_CheckField, 23, 1, 1, 80, 4, 0, // Skip to: 9106
+/* 8002 */    MCD_OPC_CheckField, 12, 4, 15, 73, 4, 0, // Skip to: 9106
+/* 8009 */    MCD_OPC_Decode, 217, 33, 159, 3, // Opcode: t2UHSUB16
+/* 8014 */    MCD_OPC_FilterValue, 1, 63, 4, 0, // Skip to: 9106
+/* 8019 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 8022 */    MCD_OPC_FilterValue, 0, 117, 0, 0, // Skip to: 8144
+/* 8027 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 8030 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 8070
+/* 8035 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 8038 */    MCD_OPC_FilterValue, 15, 39, 4, 0, // Skip to: 9106
+/* 8043 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 8060
+/* 8048 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 8060
+/* 8055 */    MCD_OPC_Decode, 191, 33, 160, 3, // Opcode: t2SXTB
+/* 8060 */    MCD_OPC_CheckPredicate, 51, 17, 4, 0, // Skip to: 9106
+/* 8065 */    MCD_OPC_Decode, 188, 33, 161, 3, // Opcode: t2SXTAB
+/* 8070 */    MCD_OPC_FilterValue, 1, 7, 4, 0, // Skip to: 9106
+/* 8075 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 8078 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 8100
+/* 8083 */    MCD_OPC_CheckPredicate, 69, 250, 3, 0, // Skip to: 9106
+/* 8088 */    MCD_OPC_CheckField, 12, 4, 15, 243, 3, 0, // Skip to: 9106
+/* 8095 */    MCD_OPC_Decode, 147, 31, 159, 3, // Opcode: t2CRC32B
+/* 8100 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 8122
+/* 8105 */    MCD_OPC_CheckPredicate, 69, 228, 3, 0, // Skip to: 9106
+/* 8110 */    MCD_OPC_CheckField, 12, 4, 15, 221, 3, 0, // Skip to: 9106
+/* 8117 */    MCD_OPC_Decode, 151, 31, 159, 3, // Opcode: t2CRC32H
+/* 8122 */    MCD_OPC_FilterValue, 2, 211, 3, 0, // Skip to: 9106
+/* 8127 */    MCD_OPC_CheckPredicate, 69, 206, 3, 0, // Skip to: 9106
+/* 8132 */    MCD_OPC_CheckField, 12, 4, 15, 199, 3, 0, // Skip to: 9106
+/* 8139 */    MCD_OPC_Decode, 152, 31, 159, 3, // Opcode: t2CRC32W
+/* 8144 */    MCD_OPC_FilterValue, 1, 189, 3, 0, // Skip to: 9106
+/* 8149 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 8152 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 8192
+/* 8157 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 8160 */    MCD_OPC_FilterValue, 15, 173, 3, 0, // Skip to: 9106
+/* 8165 */    MCD_OPC_CheckPredicate, 45, 12, 0, 0, // Skip to: 8182
+/* 8170 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 8182
+/* 8177 */    MCD_OPC_Decode, 238, 33, 160, 3, // Opcode: t2UXTB
+/* 8182 */    MCD_OPC_CheckPredicate, 51, 151, 3, 0, // Skip to: 9106
+/* 8187 */    MCD_OPC_Decode, 235, 33, 161, 3, // Opcode: t2UXTAB
+/* 8192 */    MCD_OPC_FilterValue, 1, 141, 3, 0, // Skip to: 9106
+/* 8197 */    MCD_OPC_ExtractField, 4, 3,  // Inst{6-4} ...
+/* 8200 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 8222
+/* 8205 */    MCD_OPC_CheckPredicate, 69, 128, 3, 0, // Skip to: 9106
+/* 8210 */    MCD_OPC_CheckField, 12, 4, 15, 121, 3, 0, // Skip to: 9106
+/* 8217 */    MCD_OPC_Decode, 148, 31, 159, 3, // Opcode: t2CRC32CB
+/* 8222 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 8244
+/* 8227 */    MCD_OPC_CheckPredicate, 69, 106, 3, 0, // Skip to: 9106
+/* 8232 */    MCD_OPC_CheckField, 12, 4, 15, 99, 3, 0, // Skip to: 9106
+/* 8239 */    MCD_OPC_Decode, 149, 31, 159, 3, // Opcode: t2CRC32CH
+/* 8244 */    MCD_OPC_FilterValue, 2, 89, 3, 0, // Skip to: 9106
+/* 8249 */    MCD_OPC_CheckPredicate, 69, 84, 3, 0, // Skip to: 9106
+/* 8254 */    MCD_OPC_CheckField, 12, 4, 15, 77, 3, 0, // Skip to: 9106
+/* 8261 */    MCD_OPC_Decode, 150, 31, 159, 3, // Opcode: t2CRC32CW
+/* 8266 */    MCD_OPC_FilterValue, 3, 67, 3, 0, // Skip to: 9106
+/* 8271 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 8274 */    MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 8394
+/* 8279 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 8282 */    MCD_OPC_FilterValue, 0, 50, 0, 0, // Skip to: 8337
+/* 8287 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 8290 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 8322
+/* 8295 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 8312
+/* 8300 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 8312
+/* 8307 */    MCD_OPC_Decode, 246, 32, 159, 3, // Opcode: t2SMUSD
+/* 8312 */    MCD_OPC_CheckPredicate, 53, 21, 3, 0, // Skip to: 9106
+/* 8317 */    MCD_OPC_Decode, 227, 32, 164, 3, // Opcode: t2SMLSD
+/* 8322 */    MCD_OPC_FilterValue, 1, 11, 3, 0, // Skip to: 9106
+/* 8327 */    MCD_OPC_CheckPredicate, 45, 6, 3, 0, // Skip to: 9106
+/* 8332 */    MCD_OPC_Decode, 216, 32, 170, 3, // Opcode: t2SMLAL
+/* 8337 */    MCD_OPC_FilterValue, 1, 252, 2, 0, // Skip to: 9106
+/* 8342 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 8345 */    MCD_OPC_FilterValue, 0, 244, 2, 0, // Skip to: 9106
+/* 8350 */    MCD_OPC_CheckPredicate, 70, 12, 0, 0, // Skip to: 8367
+/* 8355 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 8367
+/* 8362 */    MCD_OPC_Decode, 245, 30, 171, 3, // Opcode: t2AUTG
+/* 8367 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 8384
+/* 8372 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 8384
+/* 8379 */    MCD_OPC_Decode, 235, 32, 159, 3, // Opcode: t2SMMUL
+/* 8384 */    MCD_OPC_CheckPredicate, 53, 205, 2, 0, // Skip to: 9106
+/* 8389 */    MCD_OPC_Decode, 231, 32, 164, 3, // Opcode: t2SMMLA
+/* 8394 */    MCD_OPC_FilterValue, 1, 100, 0, 0, // Skip to: 8499
+/* 8399 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 8402 */    MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 8442
+/* 8407 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 8410 */    MCD_OPC_FilterValue, 0, 179, 2, 0, // Skip to: 9106
+/* 8415 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 8432
+/* 8420 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 8432
+/* 8427 */    MCD_OPC_Decode, 247, 32, 159, 3, // Opcode: t2SMUSDX
+/* 8432 */    MCD_OPC_CheckPredicate, 53, 157, 2, 0, // Skip to: 9106
+/* 8437 */    MCD_OPC_Decode, 228, 32, 164, 3, // Opcode: t2SMLSDX
+/* 8442 */    MCD_OPC_FilterValue, 1, 147, 2, 0, // Skip to: 9106
+/* 8447 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 8450 */    MCD_OPC_FilterValue, 0, 139, 2, 0, // Skip to: 9106
+/* 8455 */    MCD_OPC_CheckPredicate, 70, 12, 0, 0, // Skip to: 8472
+/* 8460 */    MCD_OPC_CheckField, 8, 4, 15, 5, 0, 0, // Skip to: 8472
+/* 8467 */    MCD_OPC_Decode, 130, 31, 172, 3, // Opcode: t2BXAUT
+/* 8472 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 8489
+/* 8477 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 8489
+/* 8484 */    MCD_OPC_Decode, 236, 32, 159, 3, // Opcode: t2SMMULR
+/* 8489 */    MCD_OPC_CheckPredicate, 53, 100, 2, 0, // Skip to: 9106
+/* 8494 */    MCD_OPC_Decode, 232, 32, 164, 3, // Opcode: t2SMMLAR
+/* 8499 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 8528
+/* 8504 */    MCD_OPC_CheckPredicate, 53, 85, 2, 0, // Skip to: 9106
+/* 8509 */    MCD_OPC_CheckField, 23, 1, 1, 78, 2, 0, // Skip to: 9106
+/* 8516 */    MCD_OPC_CheckField, 20, 1, 0, 71, 2, 0, // Skip to: 9106
+/* 8523 */    MCD_OPC_Decode, 217, 32, 170, 3, // Opcode: t2SMLALBB
+/* 8528 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 8557
+/* 8533 */    MCD_OPC_CheckPredicate, 53, 56, 2, 0, // Skip to: 9106
+/* 8538 */    MCD_OPC_CheckField, 23, 1, 1, 49, 2, 0, // Skip to: 9106
+/* 8545 */    MCD_OPC_CheckField, 20, 1, 0, 42, 2, 0, // Skip to: 9106
+/* 8552 */    MCD_OPC_Decode, 218, 32, 170, 3, // Opcode: t2SMLALBT
+/* 8557 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 8586
+/* 8562 */    MCD_OPC_CheckPredicate, 53, 27, 2, 0, // Skip to: 9106
+/* 8567 */    MCD_OPC_CheckField, 23, 1, 1, 20, 2, 0, // Skip to: 9106
+/* 8574 */    MCD_OPC_CheckField, 20, 1, 0, 13, 2, 0, // Skip to: 9106
+/* 8581 */    MCD_OPC_Decode, 221, 32, 170, 3, // Opcode: t2SMLALTB
+/* 8586 */    MCD_OPC_FilterValue, 11, 24, 0, 0, // Skip to: 8615
+/* 8591 */    MCD_OPC_CheckPredicate, 53, 254, 1, 0, // Skip to: 9106
+/* 8596 */    MCD_OPC_CheckField, 23, 1, 1, 247, 1, 0, // Skip to: 9106
+/* 8603 */    MCD_OPC_CheckField, 20, 1, 0, 240, 1, 0, // Skip to: 9106
+/* 8610 */    MCD_OPC_Decode, 222, 32, 170, 3, // Opcode: t2SMLALTT
+/* 8615 */    MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 8667
+/* 8620 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 8623 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 8645
+/* 8628 */    MCD_OPC_CheckPredicate, 53, 217, 1, 0, // Skip to: 9106
+/* 8633 */    MCD_OPC_CheckField, 23, 1, 1, 210, 1, 0, // Skip to: 9106
+/* 8640 */    MCD_OPC_Decode, 219, 32, 170, 3, // Opcode: t2SMLALD
+/* 8645 */    MCD_OPC_FilterValue, 1, 200, 1, 0, // Skip to: 9106
+/* 8650 */    MCD_OPC_CheckPredicate, 53, 195, 1, 0, // Skip to: 9106
+/* 8655 */    MCD_OPC_CheckField, 23, 1, 1, 188, 1, 0, // Skip to: 9106
+/* 8662 */    MCD_OPC_Decode, 229, 32, 170, 3, // Opcode: t2SMLSLD
+/* 8667 */    MCD_OPC_FilterValue, 13, 178, 1, 0, // Skip to: 9106
+/* 8672 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 8675 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 8697
+/* 8680 */    MCD_OPC_CheckPredicate, 53, 165, 1, 0, // Skip to: 9106
+/* 8685 */    MCD_OPC_CheckField, 23, 1, 1, 158, 1, 0, // Skip to: 9106
+/* 8692 */    MCD_OPC_Decode, 220, 32, 170, 3, // Opcode: t2SMLALDX
+/* 8697 */    MCD_OPC_FilterValue, 1, 148, 1, 0, // Skip to: 9106
+/* 8702 */    MCD_OPC_CheckPredicate, 53, 143, 1, 0, // Skip to: 9106
+/* 8707 */    MCD_OPC_CheckField, 23, 1, 1, 136, 1, 0, // Skip to: 9106
+/* 8714 */    MCD_OPC_Decode, 230, 32, 170, 3, // Opcode: t2SMLSLDX
+/* 8719 */    MCD_OPC_FilterValue, 3, 126, 1, 0, // Skip to: 9106
+/* 8724 */    MCD_OPC_ExtractField, 4, 4,  // Inst{7-4} ...
+/* 8727 */    MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 8880
+/* 8732 */    MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
+/* 8735 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 8757
+/* 8740 */    MCD_OPC_CheckPredicate, 45, 105, 1, 0, // Skip to: 9106
+/* 8745 */    MCD_OPC_CheckField, 12, 4, 15, 98, 1, 0, // Skip to: 9106
+/* 8752 */    MCD_OPC_Decode, 188, 32, 217, 2, // Opcode: t2RORrr
+/* 8757 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 8786
+/* 8762 */    MCD_OPC_CheckPredicate, 53, 83, 1, 0, // Skip to: 9106
+/* 8767 */    MCD_OPC_CheckField, 20, 1, 0, 76, 1, 0, // Skip to: 9106
+/* 8774 */    MCD_OPC_CheckField, 12, 4, 15, 69, 1, 0, // Skip to: 9106
+/* 8781 */    MCD_OPC_Decode, 254, 32, 159, 3, // Opcode: t2SSAX
+/* 8786 */    MCD_OPC_FilterValue, 6, 67, 0, 0, // Skip to: 8858
+/* 8791 */    MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
+/* 8794 */    MCD_OPC_FilterValue, 0, 27, 0, 0, // Skip to: 8826
+/* 8799 */    MCD_OPC_CheckPredicate, 70, 12, 0, 0, // Skip to: 8816
+/* 8804 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 8816
+/* 8811 */    MCD_OPC_Decode, 155, 32, 173, 3, // Opcode: t2PACG
+/* 8816 */    MCD_OPC_CheckPredicate, 53, 29, 1, 0, // Skip to: 9106
+/* 8821 */    MCD_OPC_Decode, 233, 32, 164, 3, // Opcode: t2SMMLS
+/* 8826 */    MCD_OPC_FilterValue, 1, 19, 1, 0, // Skip to: 9106
+/* 8831 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 8848
+/* 8836 */    MCD_OPC_CheckField, 12, 4, 15, 5, 0, 0, // Skip to: 8848
+/* 8843 */    MCD_OPC_Decode, 228, 33, 159, 3, // Opcode: t2USAD8
+/* 8848 */    MCD_OPC_CheckPredicate, 53, 253, 0, 0, // Skip to: 9106
+/* 8853 */    MCD_OPC_Decode, 229, 33, 164, 3, // Opcode: t2USADA8
+/* 8858 */    MCD_OPC_FilterValue, 7, 243, 0, 0, // Skip to: 9106
+/* 8863 */    MCD_OPC_CheckPredicate, 45, 238, 0, 0, // Skip to: 9106
+/* 8868 */    MCD_OPC_CheckField, 20, 1, 0, 231, 0, 0, // Skip to: 9106
+/* 8875 */    MCD_OPC_Decode, 220, 33, 170, 3, // Opcode: t2UMLAL
+/* 8880 */    MCD_OPC_FilterValue, 1, 54, 0, 0, // Skip to: 8939
+/* 8885 */    MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
+/* 8888 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 8917
+/* 8893 */    MCD_OPC_CheckPredicate, 53, 208, 0, 0, // Skip to: 9106
+/* 8898 */    MCD_OPC_CheckField, 20, 1, 0, 201, 0, 0, // Skip to: 9106
+/* 8905 */    MCD_OPC_CheckField, 12, 4, 15, 194, 0, 0, // Skip to: 9106
+/* 8912 */    MCD_OPC_Decode, 175, 32, 159, 3, // Opcode: t2QSAX
+/* 8917 */    MCD_OPC_FilterValue, 6, 184, 0, 0, // Skip to: 9106
+/* 8922 */    MCD_OPC_CheckPredicate, 53, 179, 0, 0, // Skip to: 9106
+/* 8927 */    MCD_OPC_CheckField, 20, 1, 0, 172, 0, 0, // Skip to: 9106
+/* 8934 */    MCD_OPC_Decode, 234, 32, 164, 3, // Opcode: t2SMMLSR
+/* 8939 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 8975
+/* 8944 */    MCD_OPC_CheckPredicate, 53, 157, 0, 0, // Skip to: 9106
+/* 8949 */    MCD_OPC_CheckField, 23, 4, 5, 150, 0, 0, // Skip to: 9106
+/* 8956 */    MCD_OPC_CheckField, 20, 1, 0, 143, 0, 0, // Skip to: 9106
+/* 8963 */    MCD_OPC_CheckField, 12, 4, 15, 136, 0, 0, // Skip to: 9106
+/* 8970 */    MCD_OPC_Decode, 208, 32, 159, 3, // Opcode: t2SHSAX
+/* 8975 */    MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 9011
+/* 8980 */    MCD_OPC_CheckPredicate, 53, 121, 0, 0, // Skip to: 9106
+/* 8985 */    MCD_OPC_CheckField, 23, 4, 5, 114, 0, 0, // Skip to: 9106
+/* 8992 */    MCD_OPC_CheckField, 20, 1, 0, 107, 0, 0, // Skip to: 9106
+/* 8999 */    MCD_OPC_CheckField, 12, 4, 15, 100, 0, 0, // Skip to: 9106
+/* 9006 */    MCD_OPC_Decode, 232, 33, 159, 3, // Opcode: t2USAX
+/* 9011 */    MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 9047
+/* 9016 */    MCD_OPC_CheckPredicate, 53, 85, 0, 0, // Skip to: 9106
+/* 9021 */    MCD_OPC_CheckField, 23, 4, 5, 78, 0, 0, // Skip to: 9106
+/* 9028 */    MCD_OPC_CheckField, 20, 1, 0, 71, 0, 0, // Skip to: 9106
+/* 9035 */    MCD_OPC_CheckField, 12, 4, 15, 64, 0, 0, // Skip to: 9106
+/* 9042 */    MCD_OPC_Decode, 225, 33, 159, 3, // Opcode: t2UQSAX
+/* 9047 */    MCD_OPC_FilterValue, 6, 54, 0, 0, // Skip to: 9106
+/* 9052 */    MCD_OPC_ExtractField, 23, 4,  // Inst{26-23} ...
+/* 9055 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 9084
+/* 9060 */    MCD_OPC_CheckPredicate, 53, 41, 0, 0, // Skip to: 9106
+/* 9065 */    MCD_OPC_CheckField, 20, 1, 0, 34, 0, 0, // Skip to: 9106
+/* 9072 */    MCD_OPC_CheckField, 12, 4, 15, 27, 0, 0, // Skip to: 9106
+/* 9079 */    MCD_OPC_Decode, 216, 33, 159, 3, // Opcode: t2UHSAX
+/* 9084 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 9106
+/* 9089 */    MCD_OPC_CheckPredicate, 53, 12, 0, 0, // Skip to: 9106
+/* 9094 */    MCD_OPC_CheckField, 20, 1, 0, 5, 0, 0, // Skip to: 9106
+/* 9101 */    MCD_OPC_Decode, 219, 33, 170, 3, // Opcode: t2UMAAL
+/* 9106 */    MCD_OPC_Fail,
+  0
+};
+
+static const uint8_t DecoderTableThumb2CDE32[] = {
+/* 0 */       MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
+/* 3 */       MCD_OPC_FilterValue, 118, 24, 1, 0, // Skip to: 288
+/* 8 */       MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 167
+/* 16 */      MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 19 */      MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 71
+/* 24 */      MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 27 */      MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 49
+/* 32 */      MCD_OPC_CheckPredicate, 71, 112, 3, 0, // Skip to: 917
+/* 37 */      MCD_OPC_CheckField, 11, 1, 0, 105, 3, 0, // Skip to: 917
+/* 44 */      MCD_OPC_Decode, 254, 5, 174, 3, // Opcode: CDE_VCX1_fpsp
+/* 49 */      MCD_OPC_FilterValue, 3, 95, 3, 0, // Skip to: 917
+/* 54 */      MCD_OPC_CheckPredicate, 71, 90, 3, 0, // Skip to: 917
+/* 59 */      MCD_OPC_CheckField, 11, 1, 0, 83, 3, 0, // Skip to: 917
+/* 66 */      MCD_OPC_Decode, 132, 6, 175, 3, // Opcode: CDE_VCX2_fpsp
+/* 71 */      MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 93
+/* 76 */      MCD_OPC_CheckPredicate, 71, 68, 3, 0, // Skip to: 917
+/* 81 */      MCD_OPC_CheckField, 11, 1, 0, 61, 3, 0, // Skip to: 917
+/* 88 */      MCD_OPC_Decode, 138, 6, 176, 3, // Opcode: CDE_VCX3_fpsp
+/* 93 */      MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 145
+/* 98 */      MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 101 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 123
+/* 106 */     MCD_OPC_CheckPredicate, 71, 38, 3, 0, // Skip to: 917
+/* 111 */     MCD_OPC_CheckField, 11, 1, 0, 31, 3, 0, // Skip to: 917
+/* 118 */     MCD_OPC_Decode, 253, 5, 177, 3, // Opcode: CDE_VCX1_fpdp
+/* 123 */     MCD_OPC_FilterValue, 3, 21, 3, 0, // Skip to: 917
+/* 128 */     MCD_OPC_CheckPredicate, 71, 16, 3, 0, // Skip to: 917
+/* 133 */     MCD_OPC_CheckField, 11, 1, 0, 9, 3, 0, // Skip to: 917
+/* 140 */     MCD_OPC_Decode, 131, 6, 178, 3, // Opcode: CDE_VCX2_fpdp
+/* 145 */     MCD_OPC_FilterValue, 3, 255, 2, 0, // Skip to: 917
+/* 150 */     MCD_OPC_CheckPredicate, 71, 250, 2, 0, // Skip to: 917
+/* 155 */     MCD_OPC_CheckField, 11, 1, 0, 243, 2, 0, // Skip to: 917
+/* 162 */     MCD_OPC_Decode, 137, 6, 179, 3, // Opcode: CDE_VCX3_fpdp
+/* 167 */     MCD_OPC_FilterValue, 1, 233, 2, 0, // Skip to: 917
+/* 172 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 175 */     MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 246
+/* 180 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 183 */     MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 211
+/* 188 */     MCD_OPC_CheckPredicate, 72, 212, 2, 0, // Skip to: 917
+/* 193 */     MCD_OPC_CheckField, 11, 2, 0, 205, 2, 0, // Skip to: 917
+/* 200 */     MCD_OPC_SoftFail, 128, 128, 128, 2 /* 0x400000 */, 0,
+/* 206 */     MCD_OPC_Decode, 255, 5, 180, 3, // Opcode: CDE_VCX1_vec
+/* 211 */     MCD_OPC_FilterValue, 3, 189, 2, 0, // Skip to: 917
+/* 216 */     MCD_OPC_CheckPredicate, 72, 184, 2, 0, // Skip to: 917
+/* 221 */     MCD_OPC_CheckField, 11, 2, 0, 177, 2, 0, // Skip to: 917
+/* 228 */     MCD_OPC_CheckField, 0, 1, 0, 170, 2, 0, // Skip to: 917
+/* 235 */     MCD_OPC_SoftFail, 160, 128, 128, 2 /* 0x400020 */, 0,
+/* 241 */     MCD_OPC_Decode, 133, 6, 181, 3, // Opcode: CDE_VCX2_vec
+/* 246 */     MCD_OPC_FilterValue, 1, 154, 2, 0, // Skip to: 917
+/* 251 */     MCD_OPC_CheckPredicate, 72, 149, 2, 0, // Skip to: 917
+/* 256 */     MCD_OPC_CheckField, 16, 1, 0, 142, 2, 0, // Skip to: 917
+/* 263 */     MCD_OPC_CheckField, 11, 2, 0, 135, 2, 0, // Skip to: 917
+/* 270 */     MCD_OPC_CheckField, 0, 1, 0, 128, 2, 0, // Skip to: 917
+/* 277 */     MCD_OPC_SoftFail, 160, 129, 128, 2 /* 0x4000a0 */, 0,
+/* 283 */     MCD_OPC_Decode, 139, 6, 182, 3, // Opcode: CDE_VCX3_vec
+/* 288 */     MCD_OPC_FilterValue, 119, 167, 0, 0, // Skip to: 460
+/* 293 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 296 */     MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 378
+/* 301 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 304 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 356
+/* 309 */     MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 312 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 334
+/* 317 */     MCD_OPC_CheckPredicate, 73, 83, 2, 0, // Skip to: 917
+/* 322 */     MCD_OPC_CheckField, 11, 1, 0, 76, 2, 0, // Skip to: 917
+/* 329 */     MCD_OPC_Decode, 238, 5, 183, 3, // Opcode: CDE_CX1
+/* 334 */     MCD_OPC_FilterValue, 1, 66, 2, 0, // Skip to: 917
+/* 339 */     MCD_OPC_CheckPredicate, 73, 61, 2, 0, // Skip to: 917
+/* 344 */     MCD_OPC_CheckField, 11, 1, 0, 54, 2, 0, // Skip to: 917
+/* 351 */     MCD_OPC_Decode, 242, 5, 184, 3, // Opcode: CDE_CX2
+/* 356 */     MCD_OPC_FilterValue, 1, 44, 2, 0, // Skip to: 917
+/* 361 */     MCD_OPC_CheckPredicate, 73, 39, 2, 0, // Skip to: 917
+/* 366 */     MCD_OPC_CheckField, 11, 1, 0, 32, 2, 0, // Skip to: 917
+/* 373 */     MCD_OPC_Decode, 246, 5, 185, 3, // Opcode: CDE_CX3
+/* 378 */     MCD_OPC_FilterValue, 1, 22, 2, 0, // Skip to: 917
+/* 383 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 386 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 438
+/* 391 */     MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 394 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 416
+/* 399 */     MCD_OPC_CheckPredicate, 73, 1, 2, 0, // Skip to: 917
+/* 404 */     MCD_OPC_CheckField, 11, 1, 0, 250, 1, 0, // Skip to: 917
+/* 411 */     MCD_OPC_Decode, 240, 5, 186, 3, // Opcode: CDE_CX1D
+/* 416 */     MCD_OPC_FilterValue, 1, 240, 1, 0, // Skip to: 917
+/* 421 */     MCD_OPC_CheckPredicate, 73, 235, 1, 0, // Skip to: 917
+/* 426 */     MCD_OPC_CheckField, 11, 1, 0, 228, 1, 0, // Skip to: 917
+/* 433 */     MCD_OPC_Decode, 244, 5, 187, 3, // Opcode: CDE_CX2D
+/* 438 */     MCD_OPC_FilterValue, 1, 218, 1, 0, // Skip to: 917
+/* 443 */     MCD_OPC_CheckPredicate, 73, 213, 1, 0, // Skip to: 917
+/* 448 */     MCD_OPC_CheckField, 11, 1, 0, 206, 1, 0, // Skip to: 917
+/* 455 */     MCD_OPC_Decode, 248, 5, 188, 3, // Opcode: CDE_CX3D
+/* 460 */     MCD_OPC_FilterValue, 126, 24, 1, 0, // Skip to: 745
+/* 465 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 468 */     MCD_OPC_FilterValue, 0, 151, 0, 0, // Skip to: 624
+/* 473 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 476 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 528
+/* 481 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 484 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 506
+/* 489 */     MCD_OPC_CheckPredicate, 71, 167, 1, 0, // Skip to: 917
+/* 494 */     MCD_OPC_CheckField, 11, 1, 0, 160, 1, 0, // Skip to: 917
+/* 501 */     MCD_OPC_Decode, 251, 5, 189, 3, // Opcode: CDE_VCX1A_fpsp
+/* 506 */     MCD_OPC_FilterValue, 3, 150, 1, 0, // Skip to: 917
+/* 511 */     MCD_OPC_CheckPredicate, 71, 145, 1, 0, // Skip to: 917
+/* 516 */     MCD_OPC_CheckField, 11, 1, 0, 138, 1, 0, // Skip to: 917
+/* 523 */     MCD_OPC_Decode, 129, 6, 190, 3, // Opcode: CDE_VCX2A_fpsp
+/* 528 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 550
+/* 533 */     MCD_OPC_CheckPredicate, 71, 123, 1, 0, // Skip to: 917
+/* 538 */     MCD_OPC_CheckField, 11, 1, 0, 116, 1, 0, // Skip to: 917
+/* 545 */     MCD_OPC_Decode, 135, 6, 191, 3, // Opcode: CDE_VCX3A_fpsp
+/* 550 */     MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 602
+/* 555 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 558 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 580
+/* 563 */     MCD_OPC_CheckPredicate, 71, 93, 1, 0, // Skip to: 917
+/* 568 */     MCD_OPC_CheckField, 11, 1, 0, 86, 1, 0, // Skip to: 917
+/* 575 */     MCD_OPC_Decode, 250, 5, 192, 3, // Opcode: CDE_VCX1A_fpdp
+/* 580 */     MCD_OPC_FilterValue, 3, 76, 1, 0, // Skip to: 917
+/* 585 */     MCD_OPC_CheckPredicate, 71, 71, 1, 0, // Skip to: 917
+/* 590 */     MCD_OPC_CheckField, 11, 1, 0, 64, 1, 0, // Skip to: 917
+/* 597 */     MCD_OPC_Decode, 128, 6, 193, 3, // Opcode: CDE_VCX2A_fpdp
+/* 602 */     MCD_OPC_FilterValue, 3, 54, 1, 0, // Skip to: 917
+/* 607 */     MCD_OPC_CheckPredicate, 71, 49, 1, 0, // Skip to: 917
+/* 612 */     MCD_OPC_CheckField, 11, 1, 0, 42, 1, 0, // Skip to: 917
+/* 619 */     MCD_OPC_Decode, 134, 6, 194, 3, // Opcode: CDE_VCX3A_fpdp
+/* 624 */     MCD_OPC_FilterValue, 1, 32, 1, 0, // Skip to: 917
+/* 629 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 632 */     MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 703
+/* 637 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 640 */     MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 668
+/* 645 */     MCD_OPC_CheckPredicate, 72, 11, 1, 0, // Skip to: 917
+/* 650 */     MCD_OPC_CheckField, 11, 2, 0, 4, 1, 0, // Skip to: 917
+/* 657 */     MCD_OPC_SoftFail, 128, 128, 128, 2 /* 0x400000 */, 0,
+/* 663 */     MCD_OPC_Decode, 252, 5, 195, 3, // Opcode: CDE_VCX1A_vec
+/* 668 */     MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 917
+/* 673 */     MCD_OPC_CheckPredicate, 72, 239, 0, 0, // Skip to: 917
+/* 678 */     MCD_OPC_CheckField, 11, 2, 0, 232, 0, 0, // Skip to: 917
+/* 685 */     MCD_OPC_CheckField, 0, 1, 0, 225, 0, 0, // Skip to: 917
+/* 692 */     MCD_OPC_SoftFail, 160, 128, 128, 2 /* 0x400020 */, 0,
+/* 698 */     MCD_OPC_Decode, 130, 6, 196, 3, // Opcode: CDE_VCX2A_vec
+/* 703 */     MCD_OPC_FilterValue, 1, 209, 0, 0, // Skip to: 917
+/* 708 */     MCD_OPC_CheckPredicate, 72, 204, 0, 0, // Skip to: 917
+/* 713 */     MCD_OPC_CheckField, 16, 1, 0, 197, 0, 0, // Skip to: 917
+/* 720 */     MCD_OPC_CheckField, 11, 2, 0, 190, 0, 0, // Skip to: 917
+/* 727 */     MCD_OPC_CheckField, 0, 1, 0, 183, 0, 0, // Skip to: 917
+/* 734 */     MCD_OPC_SoftFail, 160, 129, 128, 2 /* 0x4000a0 */, 0,
+/* 740 */     MCD_OPC_Decode, 136, 6, 197, 3, // Opcode: CDE_VCX3A_vec
+/* 745 */     MCD_OPC_FilterValue, 127, 167, 0, 0, // Skip to: 917
+/* 750 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 753 */     MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 835
+/* 758 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 761 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 813
+/* 766 */     MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 769 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 791
+/* 774 */     MCD_OPC_CheckPredicate, 73, 138, 0, 0, // Skip to: 917
+/* 779 */     MCD_OPC_CheckField, 11, 1, 0, 131, 0, 0, // Skip to: 917
+/* 786 */     MCD_OPC_Decode, 239, 5, 198, 3, // Opcode: CDE_CX1A
+/* 791 */     MCD_OPC_FilterValue, 1, 121, 0, 0, // Skip to: 917
+/* 796 */     MCD_OPC_CheckPredicate, 73, 116, 0, 0, // Skip to: 917
+/* 801 */     MCD_OPC_CheckField, 11, 1, 0, 109, 0, 0, // Skip to: 917
+/* 808 */     MCD_OPC_Decode, 243, 5, 199, 3, // Opcode: CDE_CX2A
+/* 813 */     MCD_OPC_FilterValue, 1, 99, 0, 0, // Skip to: 917
+/* 818 */     MCD_OPC_CheckPredicate, 73, 94, 0, 0, // Skip to: 917
+/* 823 */     MCD_OPC_CheckField, 11, 1, 0, 87, 0, 0, // Skip to: 917
+/* 830 */     MCD_OPC_Decode, 247, 5, 200, 3, // Opcode: CDE_CX3A
+/* 835 */     MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 917
+/* 840 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 843 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 895
+/* 848 */     MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 851 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 873
+/* 856 */     MCD_OPC_CheckPredicate, 73, 56, 0, 0, // Skip to: 917
+/* 861 */     MCD_OPC_CheckField, 11, 1, 0, 49, 0, 0, // Skip to: 917
+/* 868 */     MCD_OPC_Decode, 241, 5, 201, 3, // Opcode: CDE_CX1DA
+/* 873 */     MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 917
+/* 878 */     MCD_OPC_CheckPredicate, 73, 34, 0, 0, // Skip to: 917
+/* 883 */     MCD_OPC_CheckField, 11, 1, 0, 27, 0, 0, // Skip to: 917
+/* 890 */     MCD_OPC_Decode, 245, 5, 202, 3, // Opcode: CDE_CX2DA
+/* 895 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 917
+/* 900 */     MCD_OPC_CheckPredicate, 73, 12, 0, 0, // Skip to: 917
+/* 905 */     MCD_OPC_CheckField, 11, 1, 0, 5, 0, 0, // Skip to: 917
+/* 912 */     MCD_OPC_Decode, 249, 5, 203, 3, // Opcode: CDE_CX3DA
+/* 917 */     MCD_OPC_Fail,
   0
 };
 
@@ -9148,157 +14401,157 @@ static const uint8_t DecoderTableThumb2CoProc32[] = {
 /* 3 */       MCD_OPC_FilterValue, 236, 1, 175, 0, 0, // Skip to: 184
 /* 9 */       MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
 /* 12 */      MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 33
-/* 17 */      MCD_OPC_CheckPredicate, 38, 191, 2, 0, // Skip to: 725
+/* 17 */      MCD_OPC_CheckPredicate, 45, 191, 2, 0, // Skip to: 725
 /* 22 */      MCD_OPC_CheckField, 23, 1, 1, 184, 2, 0, // Skip to: 725
-/* 29 */      MCD_OPC_Decode, 216, 23, 90, // Opcode: t2STC_OPTION
+/* 29 */      MCD_OPC_Decode, 142, 33, 92, // Opcode: t2STC_OPTION
 /* 33 */      MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 54
-/* 38 */      MCD_OPC_CheckPredicate, 38, 170, 2, 0, // Skip to: 725
+/* 38 */      MCD_OPC_CheckPredicate, 45, 170, 2, 0, // Skip to: 725
 /* 43 */      MCD_OPC_CheckField, 23, 1, 1, 163, 2, 0, // Skip to: 725
-/* 50 */      MCD_OPC_Decode, 145, 22, 90, // Opcode: t2LDC_OPTION
+/* 50 */      MCD_OPC_Decode, 193, 31, 92, // Opcode: t2LDC_OPTION
 /* 54 */      MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 68
-/* 59 */      MCD_OPC_CheckPredicate, 38, 149, 2, 0, // Skip to: 725
-/* 64 */      MCD_OPC_Decode, 217, 23, 90, // Opcode: t2STC_POST
+/* 59 */      MCD_OPC_CheckPredicate, 45, 149, 2, 0, // Skip to: 725
+/* 64 */      MCD_OPC_Decode, 143, 33, 92, // Opcode: t2STC_POST
 /* 68 */      MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 82
-/* 73 */      MCD_OPC_CheckPredicate, 38, 135, 2, 0, // Skip to: 725
-/* 78 */      MCD_OPC_Decode, 146, 22, 90, // Opcode: t2LDC_POST
+/* 73 */      MCD_OPC_CheckPredicate, 45, 135, 2, 0, // Skip to: 725
+/* 78 */      MCD_OPC_Decode, 194, 31, 92, // Opcode: t2LDC_POST
 /* 82 */      MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 119
 /* 87 */      MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 90 */      MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 105
-/* 95 */      MCD_OPC_CheckPredicate, 38, 113, 2, 0, // Skip to: 725
-/* 100 */     MCD_OPC_Decode, 200, 22, 182, 2, // Opcode: t2MCRR
+/* 95 */      MCD_OPC_CheckPredicate, 45, 113, 2, 0, // Skip to: 725
+/* 100 */     MCD_OPC_Decode, 250, 31, 204, 3, // Opcode: t2MCRR
 /* 105 */     MCD_OPC_FilterValue, 1, 103, 2, 0, // Skip to: 725
-/* 110 */     MCD_OPC_CheckPredicate, 38, 98, 2, 0, // Skip to: 725
-/* 115 */     MCD_OPC_Decode, 212, 23, 90, // Opcode: t2STCL_OPTION
+/* 110 */     MCD_OPC_CheckPredicate, 45, 98, 2, 0, // Skip to: 725
+/* 115 */     MCD_OPC_Decode, 138, 33, 92, // Opcode: t2STCL_OPTION
 /* 119 */     MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 156
 /* 124 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 127 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 142
-/* 132 */     MCD_OPC_CheckPredicate, 38, 76, 2, 0, // Skip to: 725
-/* 137 */     MCD_OPC_Decode, 212, 22, 183, 2, // Opcode: t2MRRC
+/* 132 */     MCD_OPC_CheckPredicate, 45, 76, 2, 0, // Skip to: 725
+/* 137 */     MCD_OPC_Decode, 134, 32, 205, 3, // Opcode: t2MRRC
 /* 142 */     MCD_OPC_FilterValue, 1, 66, 2, 0, // Skip to: 725
-/* 147 */     MCD_OPC_CheckPredicate, 38, 61, 2, 0, // Skip to: 725
-/* 152 */     MCD_OPC_Decode, 141, 22, 90, // Opcode: t2LDCL_OPTION
+/* 147 */     MCD_OPC_CheckPredicate, 45, 61, 2, 0, // Skip to: 725
+/* 152 */     MCD_OPC_Decode, 189, 31, 92, // Opcode: t2LDCL_OPTION
 /* 156 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 170
-/* 161 */     MCD_OPC_CheckPredicate, 38, 47, 2, 0, // Skip to: 725
-/* 166 */     MCD_OPC_Decode, 213, 23, 90, // Opcode: t2STCL_POST
+/* 161 */     MCD_OPC_CheckPredicate, 45, 47, 2, 0, // Skip to: 725
+/* 166 */     MCD_OPC_Decode, 139, 33, 92, // Opcode: t2STCL_POST
 /* 170 */     MCD_OPC_FilterValue, 7, 38, 2, 0, // Skip to: 725
-/* 175 */     MCD_OPC_CheckPredicate, 38, 33, 2, 0, // Skip to: 725
-/* 180 */     MCD_OPC_Decode, 142, 22, 90, // Opcode: t2LDCL_POST
+/* 175 */     MCD_OPC_CheckPredicate, 45, 33, 2, 0, // Skip to: 725
+/* 180 */     MCD_OPC_Decode, 190, 31, 92, // Opcode: t2LDCL_POST
 /* 184 */     MCD_OPC_FilterValue, 237, 1, 115, 0, 0, // Skip to: 305
 /* 190 */     MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
 /* 193 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 207
-/* 198 */     MCD_OPC_CheckPredicate, 38, 10, 2, 0, // Skip to: 725
-/* 203 */     MCD_OPC_Decode, 215, 23, 90, // Opcode: t2STC_OFFSET
+/* 198 */     MCD_OPC_CheckPredicate, 45, 10, 2, 0, // Skip to: 725
+/* 203 */     MCD_OPC_Decode, 141, 33, 92, // Opcode: t2STC_OFFSET
 /* 207 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 221
-/* 212 */     MCD_OPC_CheckPredicate, 38, 252, 1, 0, // Skip to: 725
-/* 217 */     MCD_OPC_Decode, 144, 22, 90, // Opcode: t2LDC_OFFSET
+/* 212 */     MCD_OPC_CheckPredicate, 45, 252, 1, 0, // Skip to: 725
+/* 217 */     MCD_OPC_Decode, 192, 31, 92, // Opcode: t2LDC_OFFSET
 /* 221 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 235
-/* 226 */     MCD_OPC_CheckPredicate, 38, 238, 1, 0, // Skip to: 725
-/* 231 */     MCD_OPC_Decode, 218, 23, 90, // Opcode: t2STC_PRE
+/* 226 */     MCD_OPC_CheckPredicate, 45, 238, 1, 0, // Skip to: 725
+/* 231 */     MCD_OPC_Decode, 144, 33, 92, // Opcode: t2STC_PRE
 /* 235 */     MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 249
-/* 240 */     MCD_OPC_CheckPredicate, 38, 224, 1, 0, // Skip to: 725
-/* 245 */     MCD_OPC_Decode, 147, 22, 90, // Opcode: t2LDC_PRE
+/* 240 */     MCD_OPC_CheckPredicate, 45, 224, 1, 0, // Skip to: 725
+/* 245 */     MCD_OPC_Decode, 195, 31, 92, // Opcode: t2LDC_PRE
 /* 249 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 263
-/* 254 */     MCD_OPC_CheckPredicate, 38, 210, 1, 0, // Skip to: 725
-/* 259 */     MCD_OPC_Decode, 211, 23, 90, // Opcode: t2STCL_OFFSET
+/* 254 */     MCD_OPC_CheckPredicate, 45, 210, 1, 0, // Skip to: 725
+/* 259 */     MCD_OPC_Decode, 137, 33, 92, // Opcode: t2STCL_OFFSET
 /* 263 */     MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 277
-/* 268 */     MCD_OPC_CheckPredicate, 38, 196, 1, 0, // Skip to: 725
-/* 273 */     MCD_OPC_Decode, 140, 22, 90, // Opcode: t2LDCL_OFFSET
+/* 268 */     MCD_OPC_CheckPredicate, 45, 196, 1, 0, // Skip to: 725
+/* 273 */     MCD_OPC_Decode, 188, 31, 92, // Opcode: t2LDCL_OFFSET
 /* 277 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 291
-/* 282 */     MCD_OPC_CheckPredicate, 38, 182, 1, 0, // Skip to: 725
-/* 287 */     MCD_OPC_Decode, 214, 23, 90, // Opcode: t2STCL_PRE
+/* 282 */     MCD_OPC_CheckPredicate, 45, 182, 1, 0, // Skip to: 725
+/* 287 */     MCD_OPC_Decode, 140, 33, 92, // Opcode: t2STCL_PRE
 /* 291 */     MCD_OPC_FilterValue, 7, 173, 1, 0, // Skip to: 725
-/* 296 */     MCD_OPC_CheckPredicate, 38, 168, 1, 0, // Skip to: 725
-/* 301 */     MCD_OPC_Decode, 143, 22, 90, // Opcode: t2LDCL_PRE
+/* 296 */     MCD_OPC_CheckPredicate, 45, 168, 1, 0, // Skip to: 725
+/* 301 */     MCD_OPC_Decode, 191, 31, 92, // Opcode: t2LDCL_PRE
 /* 305 */     MCD_OPC_FilterValue, 238, 1, 53, 0, 0, // Skip to: 364
 /* 311 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 314 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 328
-/* 319 */     MCD_OPC_CheckPredicate, 58, 145, 1, 0, // Skip to: 725
-/* 324 */     MCD_OPC_Decode, 219, 21, 91, // Opcode: t2CDP
+/* 319 */     MCD_OPC_CheckPredicate, 74, 145, 1, 0, // Skip to: 725
+/* 324 */     MCD_OPC_Decode, 133, 31, 93, // Opcode: t2CDP
 /* 328 */     MCD_OPC_FilterValue, 1, 136, 1, 0, // Skip to: 725
 /* 333 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 336 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 350
-/* 341 */     MCD_OPC_CheckPredicate, 38, 123, 1, 0, // Skip to: 725
-/* 346 */     MCD_OPC_Decode, 198, 22, 93, // Opcode: t2MCR
+/* 341 */     MCD_OPC_CheckPredicate, 45, 123, 1, 0, // Skip to: 725
+/* 346 */     MCD_OPC_Decode, 248, 31, 95, // Opcode: t2MCR
 /* 350 */     MCD_OPC_FilterValue, 1, 114, 1, 0, // Skip to: 725
-/* 355 */     MCD_OPC_CheckPredicate, 38, 109, 1, 0, // Skip to: 725
-/* 360 */     MCD_OPC_Decode, 210, 22, 95, // Opcode: t2MRC
+/* 355 */     MCD_OPC_CheckPredicate, 45, 109, 1, 0, // Skip to: 725
+/* 360 */     MCD_OPC_Decode, 132, 32, 97, // Opcode: t2MRC
 /* 364 */     MCD_OPC_FilterValue, 252, 1, 175, 0, 0, // Skip to: 545
 /* 370 */     MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
 /* 373 */     MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 394
-/* 378 */     MCD_OPC_CheckPredicate, 59, 86, 1, 0, // Skip to: 725
+/* 378 */     MCD_OPC_CheckPredicate, 75, 86, 1, 0, // Skip to: 725
 /* 383 */     MCD_OPC_CheckField, 23, 1, 1, 79, 1, 0, // Skip to: 725
-/* 390 */     MCD_OPC_Decode, 208, 23, 90, // Opcode: t2STC2_OPTION
+/* 390 */     MCD_OPC_Decode, 134, 33, 92, // Opcode: t2STC2_OPTION
 /* 394 */     MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 415
-/* 399 */     MCD_OPC_CheckPredicate, 59, 65, 1, 0, // Skip to: 725
+/* 399 */     MCD_OPC_CheckPredicate, 75, 65, 1, 0, // Skip to: 725
 /* 404 */     MCD_OPC_CheckField, 23, 1, 1, 58, 1, 0, // Skip to: 725
-/* 411 */     MCD_OPC_Decode, 137, 22, 90, // Opcode: t2LDC2_OPTION
+/* 411 */     MCD_OPC_Decode, 185, 31, 92, // Opcode: t2LDC2_OPTION
 /* 415 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 429
-/* 420 */     MCD_OPC_CheckPredicate, 59, 44, 1, 0, // Skip to: 725
-/* 425 */     MCD_OPC_Decode, 209, 23, 90, // Opcode: t2STC2_POST
+/* 420 */     MCD_OPC_CheckPredicate, 75, 44, 1, 0, // Skip to: 725
+/* 425 */     MCD_OPC_Decode, 135, 33, 92, // Opcode: t2STC2_POST
 /* 429 */     MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 443
-/* 434 */     MCD_OPC_CheckPredicate, 59, 30, 1, 0, // Skip to: 725
-/* 439 */     MCD_OPC_Decode, 138, 22, 90, // Opcode: t2LDC2_POST
+/* 434 */     MCD_OPC_CheckPredicate, 75, 30, 1, 0, // Skip to: 725
+/* 439 */     MCD_OPC_Decode, 186, 31, 92, // Opcode: t2LDC2_POST
 /* 443 */     MCD_OPC_FilterValue, 4, 32, 0, 0, // Skip to: 480
 /* 448 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 451 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 466
-/* 456 */     MCD_OPC_CheckPredicate, 58, 8, 1, 0, // Skip to: 725
-/* 461 */     MCD_OPC_Decode, 201, 22, 182, 2, // Opcode: t2MCRR2
+/* 456 */     MCD_OPC_CheckPredicate, 74, 8, 1, 0, // Skip to: 725
+/* 461 */     MCD_OPC_Decode, 251, 31, 204, 3, // Opcode: t2MCRR2
 /* 466 */     MCD_OPC_FilterValue, 1, 254, 0, 0, // Skip to: 725
-/* 471 */     MCD_OPC_CheckPredicate, 59, 249, 0, 0, // Skip to: 725
-/* 476 */     MCD_OPC_Decode, 204, 23, 90, // Opcode: t2STC2L_OPTION
+/* 471 */     MCD_OPC_CheckPredicate, 75, 249, 0, 0, // Skip to: 725
+/* 476 */     MCD_OPC_Decode, 130, 33, 92, // Opcode: t2STC2L_OPTION
 /* 480 */     MCD_OPC_FilterValue, 5, 32, 0, 0, // Skip to: 517
 /* 485 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 488 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 503
-/* 493 */     MCD_OPC_CheckPredicate, 58, 227, 0, 0, // Skip to: 725
-/* 498 */     MCD_OPC_Decode, 213, 22, 183, 2, // Opcode: t2MRRC2
+/* 493 */     MCD_OPC_CheckPredicate, 74, 227, 0, 0, // Skip to: 725
+/* 498 */     MCD_OPC_Decode, 135, 32, 205, 3, // Opcode: t2MRRC2
 /* 503 */     MCD_OPC_FilterValue, 1, 217, 0, 0, // Skip to: 725
-/* 508 */     MCD_OPC_CheckPredicate, 59, 212, 0, 0, // Skip to: 725
-/* 513 */     MCD_OPC_Decode, 133, 22, 90, // Opcode: t2LDC2L_OPTION
+/* 508 */     MCD_OPC_CheckPredicate, 75, 212, 0, 0, // Skip to: 725
+/* 513 */     MCD_OPC_Decode, 181, 31, 92, // Opcode: t2LDC2L_OPTION
 /* 517 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 531
-/* 522 */     MCD_OPC_CheckPredicate, 59, 198, 0, 0, // Skip to: 725
-/* 527 */     MCD_OPC_Decode, 205, 23, 90, // Opcode: t2STC2L_POST
+/* 522 */     MCD_OPC_CheckPredicate, 75, 198, 0, 0, // Skip to: 725
+/* 527 */     MCD_OPC_Decode, 131, 33, 92, // Opcode: t2STC2L_POST
 /* 531 */     MCD_OPC_FilterValue, 7, 189, 0, 0, // Skip to: 725
-/* 536 */     MCD_OPC_CheckPredicate, 59, 184, 0, 0, // Skip to: 725
-/* 541 */     MCD_OPC_Decode, 134, 22, 90, // Opcode: t2LDC2L_POST
+/* 536 */     MCD_OPC_CheckPredicate, 75, 184, 0, 0, // Skip to: 725
+/* 541 */     MCD_OPC_Decode, 182, 31, 92, // Opcode: t2LDC2L_POST
 /* 545 */     MCD_OPC_FilterValue, 253, 1, 115, 0, 0, // Skip to: 666
 /* 551 */     MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
 /* 554 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 568
-/* 559 */     MCD_OPC_CheckPredicate, 59, 161, 0, 0, // Skip to: 725
-/* 564 */     MCD_OPC_Decode, 207, 23, 90, // Opcode: t2STC2_OFFSET
+/* 559 */     MCD_OPC_CheckPredicate, 75, 161, 0, 0, // Skip to: 725
+/* 564 */     MCD_OPC_Decode, 133, 33, 92, // Opcode: t2STC2_OFFSET
 /* 568 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 582
-/* 573 */     MCD_OPC_CheckPredicate, 59, 147, 0, 0, // Skip to: 725
-/* 578 */     MCD_OPC_Decode, 136, 22, 90, // Opcode: t2LDC2_OFFSET
+/* 573 */     MCD_OPC_CheckPredicate, 75, 147, 0, 0, // Skip to: 725
+/* 578 */     MCD_OPC_Decode, 184, 31, 92, // Opcode: t2LDC2_OFFSET
 /* 582 */     MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 596
-/* 587 */     MCD_OPC_CheckPredicate, 59, 133, 0, 0, // Skip to: 725
-/* 592 */     MCD_OPC_Decode, 210, 23, 90, // Opcode: t2STC2_PRE
+/* 587 */     MCD_OPC_CheckPredicate, 75, 133, 0, 0, // Skip to: 725
+/* 592 */     MCD_OPC_Decode, 136, 33, 92, // Opcode: t2STC2_PRE
 /* 596 */     MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 610
-/* 601 */     MCD_OPC_CheckPredicate, 59, 119, 0, 0, // Skip to: 725
-/* 606 */     MCD_OPC_Decode, 139, 22, 90, // Opcode: t2LDC2_PRE
+/* 601 */     MCD_OPC_CheckPredicate, 75, 119, 0, 0, // Skip to: 725
+/* 606 */     MCD_OPC_Decode, 187, 31, 92, // Opcode: t2LDC2_PRE
 /* 610 */     MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 624
-/* 615 */     MCD_OPC_CheckPredicate, 59, 105, 0, 0, // Skip to: 725
-/* 620 */     MCD_OPC_Decode, 203, 23, 90, // Opcode: t2STC2L_OFFSET
+/* 615 */     MCD_OPC_CheckPredicate, 75, 105, 0, 0, // Skip to: 725
+/* 620 */     MCD_OPC_Decode, 129, 33, 92, // Opcode: t2STC2L_OFFSET
 /* 624 */     MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 638
-/* 629 */     MCD_OPC_CheckPredicate, 59, 91, 0, 0, // Skip to: 725
-/* 634 */     MCD_OPC_Decode, 132, 22, 90, // Opcode: t2LDC2L_OFFSET
+/* 629 */     MCD_OPC_CheckPredicate, 75, 91, 0, 0, // Skip to: 725
+/* 634 */     MCD_OPC_Decode, 180, 31, 92, // Opcode: t2LDC2L_OFFSET
 /* 638 */     MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 652
-/* 643 */     MCD_OPC_CheckPredicate, 59, 77, 0, 0, // Skip to: 725
-/* 648 */     MCD_OPC_Decode, 206, 23, 90, // Opcode: t2STC2L_PRE
+/* 643 */     MCD_OPC_CheckPredicate, 75, 77, 0, 0, // Skip to: 725
+/* 648 */     MCD_OPC_Decode, 132, 33, 92, // Opcode: t2STC2L_PRE
 /* 652 */     MCD_OPC_FilterValue, 7, 68, 0, 0, // Skip to: 725
-/* 657 */     MCD_OPC_CheckPredicate, 59, 63, 0, 0, // Skip to: 725
-/* 662 */     MCD_OPC_Decode, 135, 22, 90, // Opcode: t2LDC2L_PRE
+/* 657 */     MCD_OPC_CheckPredicate, 75, 63, 0, 0, // Skip to: 725
+/* 662 */     MCD_OPC_Decode, 183, 31, 92, // Opcode: t2LDC2L_PRE
 /* 666 */     MCD_OPC_FilterValue, 254, 1, 53, 0, 0, // Skip to: 725
 /* 672 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 675 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 689
-/* 680 */     MCD_OPC_CheckPredicate, 58, 40, 0, 0, // Skip to: 725
-/* 685 */     MCD_OPC_Decode, 220, 21, 91, // Opcode: t2CDP2
+/* 680 */     MCD_OPC_CheckPredicate, 74, 40, 0, 0, // Skip to: 725
+/* 685 */     MCD_OPC_Decode, 134, 31, 93, // Opcode: t2CDP2
 /* 689 */     MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 725
 /* 694 */     MCD_OPC_ExtractField, 20, 1,  // Inst{20} ...
 /* 697 */     MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 711
-/* 702 */     MCD_OPC_CheckPredicate, 58, 18, 0, 0, // Skip to: 725
-/* 707 */     MCD_OPC_Decode, 199, 22, 93, // Opcode: t2MCR2
+/* 702 */     MCD_OPC_CheckPredicate, 74, 18, 0, 0, // Skip to: 725
+/* 707 */     MCD_OPC_Decode, 249, 31, 95, // Opcode: t2MCR2
 /* 711 */     MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 725
-/* 716 */     MCD_OPC_CheckPredicate, 58, 4, 0, 0, // Skip to: 725
-/* 721 */     MCD_OPC_Decode, 211, 22, 95, // Opcode: t2MRC2
+/* 716 */     MCD_OPC_CheckPredicate, 74, 4, 0, 0, // Skip to: 725
+/* 721 */     MCD_OPC_Decode, 133, 32, 97, // Opcode: t2MRC2
 /* 725 */     MCD_OPC_Fail,
   0
 };
@@ -9306,2051 +14559,2489 @@ static const uint8_t DecoderTableThumb2CoProc32[] = {
 static const uint8_t DecoderTableThumbSBit16[] = {
 /* 0 */       MCD_OPC_ExtractField, 11, 5,  // Inst{15-11} ...
 /* 3 */       MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 18
-/* 8 */       MCD_OPC_CheckPredicate, 28, 95, 1, 0, // Skip to: 364
-/* 13 */      MCD_OPC_Decode, 232, 24, 184, 2, // Opcode: tLSLri
+/* 8 */       MCD_OPC_CheckPredicate, 35, 95, 1, 0, // Skip to: 364
+/* 13 */      MCD_OPC_Decode, 161, 34, 206, 3, // Opcode: tLSLri
 /* 18 */      MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 33
-/* 23 */      MCD_OPC_CheckPredicate, 28, 80, 1, 0, // Skip to: 364
-/* 28 */      MCD_OPC_Decode, 234, 24, 184, 2, // Opcode: tLSRri
+/* 23 */      MCD_OPC_CheckPredicate, 35, 80, 1, 0, // Skip to: 364
+/* 28 */      MCD_OPC_Decode, 163, 34, 206, 3, // Opcode: tLSRri
 /* 33 */      MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 48
-/* 38 */      MCD_OPC_CheckPredicate, 28, 65, 1, 0, // Skip to: 364
-/* 43 */      MCD_OPC_Decode, 196, 24, 184, 2, // Opcode: tASRri
+/* 38 */      MCD_OPC_CheckPredicate, 35, 65, 1, 0, // Skip to: 364
+/* 43 */      MCD_OPC_Decode, 253, 33, 206, 3, // Opcode: tASRri
 /* 48 */      MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 116
 /* 53 */      MCD_OPC_ExtractField, 9, 2,  // Inst{10-9} ...
 /* 56 */      MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71
-/* 61 */      MCD_OPC_CheckPredicate, 28, 42, 1, 0, // Skip to: 364
-/* 66 */      MCD_OPC_Decode, 191, 24, 185, 2, // Opcode: tADDrr
+/* 61 */      MCD_OPC_CheckPredicate, 35, 42, 1, 0, // Skip to: 364
+/* 66 */      MCD_OPC_Decode, 248, 33, 207, 3, // Opcode: tADDrr
 /* 71 */      MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 86
-/* 76 */      MCD_OPC_CheckPredicate, 28, 27, 1, 0, // Skip to: 364
-/* 81 */      MCD_OPC_Decode, 134, 25, 185, 2, // Opcode: tSUBrr
+/* 76 */      MCD_OPC_CheckPredicate, 35, 27, 1, 0, // Skip to: 364
+/* 81 */      MCD_OPC_Decode, 191, 34, 207, 3, // Opcode: tSUBrr
 /* 86 */      MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 101
-/* 91 */      MCD_OPC_CheckPredicate, 28, 12, 1, 0, // Skip to: 364
-/* 96 */      MCD_OPC_Decode, 187, 24, 186, 2, // Opcode: tADDi3
+/* 91 */      MCD_OPC_CheckPredicate, 35, 12, 1, 0, // Skip to: 364
+/* 96 */      MCD_OPC_Decode, 244, 33, 208, 3, // Opcode: tADDi3
 /* 101 */     MCD_OPC_FilterValue, 3, 2, 1, 0, // Skip to: 364
-/* 106 */     MCD_OPC_CheckPredicate, 28, 253, 0, 0, // Skip to: 364
-/* 111 */     MCD_OPC_Decode, 132, 25, 186, 2, // Opcode: tSUBi3
+/* 106 */     MCD_OPC_CheckPredicate, 35, 253, 0, 0, // Skip to: 364
+/* 111 */     MCD_OPC_Decode, 189, 34, 208, 3, // Opcode: tSUBi3
 /* 116 */     MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 131
-/* 121 */     MCD_OPC_CheckPredicate, 28, 238, 0, 0, // Skip to: 364
-/* 126 */     MCD_OPC_Decode, 237, 24, 208, 1, // Opcode: tMOVi8
+/* 121 */     MCD_OPC_CheckPredicate, 35, 238, 0, 0, // Skip to: 364
+/* 126 */     MCD_OPC_Decode, 166, 34, 185, 2, // Opcode: tMOVi8
 /* 131 */     MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 146
-/* 136 */     MCD_OPC_CheckPredicate, 28, 223, 0, 0, // Skip to: 364
-/* 141 */     MCD_OPC_Decode, 188, 24, 187, 2, // Opcode: tADDi8
+/* 136 */     MCD_OPC_CheckPredicate, 35, 223, 0, 0, // Skip to: 364
+/* 141 */     MCD_OPC_Decode, 245, 33, 209, 3, // Opcode: tADDi8
 /* 146 */     MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 161
-/* 151 */     MCD_OPC_CheckPredicate, 28, 208, 0, 0, // Skip to: 364
-/* 156 */     MCD_OPC_Decode, 133, 25, 187, 2, // Opcode: tSUBi8
+/* 151 */     MCD_OPC_CheckPredicate, 35, 208, 0, 0, // Skip to: 364
+/* 156 */     MCD_OPC_Decode, 190, 34, 209, 3, // Opcode: tSUBi8
 /* 161 */     MCD_OPC_FilterValue, 8, 198, 0, 0, // Skip to: 364
 /* 166 */     MCD_OPC_ExtractField, 6, 5,  // Inst{10-6} ...
 /* 169 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 184
-/* 174 */     MCD_OPC_CheckPredicate, 28, 185, 0, 0, // Skip to: 364
-/* 179 */     MCD_OPC_Decode, 195, 24, 188, 2, // Opcode: tAND
+/* 174 */     MCD_OPC_CheckPredicate, 35, 185, 0, 0, // Skip to: 364
+/* 179 */     MCD_OPC_Decode, 252, 33, 210, 3, // Opcode: tAND
 /* 184 */     MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 199
-/* 189 */     MCD_OPC_CheckPredicate, 28, 170, 0, 0, // Skip to: 364
-/* 194 */     MCD_OPC_Decode, 215, 24, 188, 2, // Opcode: tEOR
+/* 189 */     MCD_OPC_CheckPredicate, 35, 170, 0, 0, // Skip to: 364
+/* 194 */     MCD_OPC_Decode, 144, 34, 210, 3, // Opcode: tEOR
 /* 199 */     MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 214
-/* 204 */     MCD_OPC_CheckPredicate, 28, 155, 0, 0, // Skip to: 364
-/* 209 */     MCD_OPC_Decode, 233, 24, 188, 2, // Opcode: tLSLrr
+/* 204 */     MCD_OPC_CheckPredicate, 35, 155, 0, 0, // Skip to: 364
+/* 209 */     MCD_OPC_Decode, 162, 34, 210, 3, // Opcode: tLSLrr
 /* 214 */     MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 229
-/* 219 */     MCD_OPC_CheckPredicate, 28, 140, 0, 0, // Skip to: 364
-/* 224 */     MCD_OPC_Decode, 235, 24, 188, 2, // Opcode: tLSRrr
+/* 219 */     MCD_OPC_CheckPredicate, 35, 140, 0, 0, // Skip to: 364
+/* 224 */     MCD_OPC_Decode, 164, 34, 210, 3, // Opcode: tLSRrr
 /* 229 */     MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 244
-/* 234 */     MCD_OPC_CheckPredicate, 28, 125, 0, 0, // Skip to: 364
-/* 239 */     MCD_OPC_Decode, 197, 24, 188, 2, // Opcode: tASRrr
+/* 234 */     MCD_OPC_CheckPredicate, 35, 125, 0, 0, // Skip to: 364
+/* 239 */     MCD_OPC_Decode, 254, 33, 210, 3, // Opcode: tASRrr
 /* 244 */     MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 259
-/* 249 */     MCD_OPC_CheckPredicate, 28, 110, 0, 0, // Skip to: 364
-/* 254 */     MCD_OPC_Decode, 185, 24, 188, 2, // Opcode: tADC
+/* 249 */     MCD_OPC_CheckPredicate, 35, 110, 0, 0, // Skip to: 364
+/* 254 */     MCD_OPC_Decode, 242, 33, 210, 3, // Opcode: tADC
 /* 259 */     MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 274
-/* 264 */     MCD_OPC_CheckPredicate, 28, 95, 0, 0, // Skip to: 364
-/* 269 */     MCD_OPC_Decode, 250, 24, 188, 2, // Opcode: tSBC
+/* 264 */     MCD_OPC_CheckPredicate, 35, 95, 0, 0, // Skip to: 364
+/* 269 */     MCD_OPC_Decode, 179, 34, 210, 3, // Opcode: tSBC
 /* 274 */     MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 289
-/* 279 */     MCD_OPC_CheckPredicate, 28, 80, 0, 0, // Skip to: 364
-/* 284 */     MCD_OPC_Decode, 248, 24, 188, 2, // Opcode: tROR
+/* 279 */     MCD_OPC_CheckPredicate, 35, 80, 0, 0, // Skip to: 364
+/* 284 */     MCD_OPC_Decode, 177, 34, 210, 3, // Opcode: tROR
 /* 289 */     MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 304
-/* 294 */     MCD_OPC_CheckPredicate, 28, 65, 0, 0, // Skip to: 364
-/* 299 */     MCD_OPC_Decode, 249, 24, 207, 1, // Opcode: tRSB
+/* 294 */     MCD_OPC_CheckPredicate, 35, 65, 0, 0, // Skip to: 364
+/* 299 */     MCD_OPC_Decode, 178, 34, 184, 2, // Opcode: tRSB
 /* 304 */     MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 319
-/* 309 */     MCD_OPC_CheckPredicate, 28, 50, 0, 0, // Skip to: 364
-/* 314 */     MCD_OPC_Decode, 241, 24, 188, 2, // Opcode: tORR
+/* 309 */     MCD_OPC_CheckPredicate, 35, 50, 0, 0, // Skip to: 364
+/* 314 */     MCD_OPC_Decode, 170, 34, 210, 3, // Opcode: tORR
 /* 319 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 334
-/* 324 */     MCD_OPC_CheckPredicate, 28, 35, 0, 0, // Skip to: 364
-/* 329 */     MCD_OPC_Decode, 239, 24, 189, 2, // Opcode: tMUL
+/* 324 */     MCD_OPC_CheckPredicate, 35, 35, 0, 0, // Skip to: 364
+/* 329 */     MCD_OPC_Decode, 168, 34, 211, 3, // Opcode: tMUL
 /* 334 */     MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 349
-/* 339 */     MCD_OPC_CheckPredicate, 28, 20, 0, 0, // Skip to: 364
-/* 344 */     MCD_OPC_Decode, 199, 24, 188, 2, // Opcode: tBIC
+/* 339 */     MCD_OPC_CheckPredicate, 35, 20, 0, 0, // Skip to: 364
+/* 344 */     MCD_OPC_Decode, 128, 34, 210, 3, // Opcode: tBIC
 /* 349 */     MCD_OPC_FilterValue, 15, 10, 0, 0, // Skip to: 364
-/* 354 */     MCD_OPC_CheckPredicate, 28, 5, 0, 0, // Skip to: 364
-/* 359 */     MCD_OPC_Decode, 240, 24, 207, 1, // Opcode: tMVN
+/* 354 */     MCD_OPC_CheckPredicate, 35, 5, 0, 0, // Skip to: 364
+/* 359 */     MCD_OPC_Decode, 169, 34, 184, 2, // Opcode: tMVN
 /* 364 */     MCD_OPC_Fail,
   0
 };
 
 static const uint8_t DecoderTableVFP32[] = {
-/* 0 */       MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 3 */       MCD_OPC_FilterValue, 0, 21, 2, 0, // Skip to: 541
-/* 8 */       MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 11 */      MCD_OPC_FilterValue, 9, 130, 0, 0, // Skip to: 146
+/* 0 */       MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 3 */       MCD_OPC_FilterValue, 9, 112, 4, 0, // Skip to: 1144
+/* 8 */       MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 130, 0, 0, // Skip to: 146
 /* 16 */      MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
 /* 19 */      MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 34
-/* 24 */      MCD_OPC_CheckPredicate, 60, 247, 16, 0, // Skip to: 4372
-/* 29 */      MCD_OPC_Decode, 205, 20, 190, 2, // Opcode: VSTRH
-/* 34 */      MCD_OPC_FilterValue, 14, 237, 16, 0, // Skip to: 4372
+/* 24 */      MCD_OPC_CheckPredicate, 76, 222, 21, 0, // Skip to: 5627
+/* 29 */      MCD_OPC_Decode, 210, 29, 212, 3, // Opcode: VSTRH
+/* 34 */      MCD_OPC_FilterValue, 14, 212, 21, 0, // Skip to: 5627
 /* 39 */      MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
 /* 42 */      MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 110
 /* 47 */      MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
 /* 50 */      MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 88
 /* 55 */      MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
 /* 58 */      MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73
-/* 63 */      MCD_OPC_CheckPredicate, 60, 208, 16, 0, // Skip to: 4372
-/* 68 */      MCD_OPC_Decode, 203, 13, 191, 2, // Opcode: VMLAH
-/* 73 */      MCD_OPC_FilterValue, 1, 198, 16, 0, // Skip to: 4372
-/* 78 */      MCD_OPC_CheckPredicate, 60, 193, 16, 0, // Skip to: 4372
-/* 83 */      MCD_OPC_Decode, 254, 9, 192, 2, // Opcode: VDIVH
-/* 88 */      MCD_OPC_FilterValue, 1, 183, 16, 0, // Skip to: 4372
-/* 93 */      MCD_OPC_CheckPredicate, 60, 178, 16, 0, // Skip to: 4372
-/* 98 */      MCD_OPC_CheckField, 23, 1, 0, 171, 16, 0, // Skip to: 4372
-/* 105 */     MCD_OPC_Decode, 234, 13, 191, 2, // Opcode: VMLSH
-/* 110 */     MCD_OPC_FilterValue, 1, 161, 16, 0, // Skip to: 4372
-/* 115 */     MCD_OPC_CheckPredicate, 60, 156, 16, 0, // Skip to: 4372
-/* 120 */     MCD_OPC_CheckField, 22, 2, 0, 149, 16, 0, // Skip to: 4372
-/* 127 */     MCD_OPC_CheckField, 5, 2, 0, 142, 16, 0, // Skip to: 4372
-/* 134 */     MCD_OPC_CheckField, 0, 4, 0, 135, 16, 0, // Skip to: 4372
-/* 141 */     MCD_OPC_Decode, 139, 14, 193, 2, // Opcode: VMOVHR
-/* 146 */     MCD_OPC_FilterValue, 10, 189, 0, 0, // Skip to: 340
+/* 63 */      MCD_OPC_CheckPredicate, 77, 183, 21, 0, // Skip to: 5627
+/* 68 */      MCD_OPC_Decode, 174, 22, 213, 3, // Opcode: VMLAH
+/* 73 */      MCD_OPC_FilterValue, 1, 173, 21, 0, // Skip to: 5627
+/* 78 */      MCD_OPC_CheckPredicate, 77, 168, 21, 0, // Skip to: 5627
+/* 83 */      MCD_OPC_Decode, 175, 18, 214, 3, // Opcode: VDIVH
+/* 88 */      MCD_OPC_FilterValue, 1, 158, 21, 0, // Skip to: 5627
+/* 93 */      MCD_OPC_CheckPredicate, 77, 153, 21, 0, // Skip to: 5627
+/* 98 */      MCD_OPC_CheckField, 23, 1, 0, 146, 21, 0, // Skip to: 5627
+/* 105 */     MCD_OPC_Decode, 205, 22, 213, 3, // Opcode: VMLSH
+/* 110 */     MCD_OPC_FilterValue, 1, 136, 21, 0, // Skip to: 5627
+/* 115 */     MCD_OPC_CheckPredicate, 76, 131, 21, 0, // Skip to: 5627
+/* 120 */     MCD_OPC_CheckField, 22, 2, 0, 124, 21, 0, // Skip to: 5627
+/* 127 */     MCD_OPC_CheckField, 5, 2, 0, 117, 21, 0, // Skip to: 5627
+/* 134 */     MCD_OPC_CheckField, 0, 4, 0, 110, 21, 0, // Skip to: 5627
+/* 141 */     MCD_OPC_Decode, 239, 22, 215, 3, // Opcode: VMOVHR
+/* 146 */     MCD_OPC_FilterValue, 1, 146, 0, 0, // Skip to: 297
 /* 151 */     MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
-/* 154 */     MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 213
-/* 159 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 162 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 198
-/* 167 */     MCD_OPC_CheckPredicate, 27, 104, 16, 0, // Skip to: 4372
-/* 172 */     MCD_OPC_CheckField, 22, 1, 1, 97, 16, 0, // Skip to: 4372
-/* 179 */     MCD_OPC_CheckField, 6, 2, 0, 90, 16, 0, // Skip to: 4372
-/* 186 */     MCD_OPC_CheckField, 4, 1, 1, 83, 16, 0, // Skip to: 4372
-/* 193 */     MCD_OPC_Decode, 155, 14, 194, 2, // Opcode: VMOVSRR
-/* 198 */     MCD_OPC_FilterValue, 1, 73, 16, 0, // Skip to: 4372
-/* 203 */     MCD_OPC_CheckPredicate, 27, 68, 16, 0, // Skip to: 4372
-/* 208 */     MCD_OPC_Decode, 202, 20, 195, 2, // Opcode: VSTMSIA
-/* 213 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 228
-/* 218 */     MCD_OPC_CheckPredicate, 27, 53, 16, 0, // Skip to: 4372
-/* 223 */     MCD_OPC_Decode, 206, 20, 196, 2, // Opcode: VSTRS
-/* 228 */     MCD_OPC_FilterValue, 14, 43, 16, 0, // Skip to: 4372
-/* 233 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 236 */     MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 304
-/* 241 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 244 */     MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 282
-/* 249 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 252 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 267
-/* 257 */     MCD_OPC_CheckPredicate, 27, 14, 16, 0, // Skip to: 4372
-/* 262 */     MCD_OPC_Decode, 214, 13, 197, 2, // Opcode: VMLAS
-/* 267 */     MCD_OPC_FilterValue, 1, 4, 16, 0, // Skip to: 4372
-/* 272 */     MCD_OPC_CheckPredicate, 27, 255, 15, 0, // Skip to: 4372
-/* 277 */     MCD_OPC_Decode, 255, 9, 198, 2, // Opcode: VDIVS
-/* 282 */     MCD_OPC_FilterValue, 1, 245, 15, 0, // Skip to: 4372
-/* 287 */     MCD_OPC_CheckPredicate, 27, 240, 15, 0, // Skip to: 4372
-/* 292 */     MCD_OPC_CheckField, 23, 1, 0, 233, 15, 0, // Skip to: 4372
-/* 299 */     MCD_OPC_Decode, 245, 13, 197, 2, // Opcode: VMLSS
-/* 304 */     MCD_OPC_FilterValue, 1, 223, 15, 0, // Skip to: 4372
-/* 309 */     MCD_OPC_CheckPredicate, 27, 218, 15, 0, // Skip to: 4372
-/* 314 */     MCD_OPC_CheckField, 22, 2, 0, 211, 15, 0, // Skip to: 4372
-/* 321 */     MCD_OPC_CheckField, 5, 2, 0, 204, 15, 0, // Skip to: 4372
-/* 328 */     MCD_OPC_CheckField, 0, 4, 0, 197, 15, 0, // Skip to: 4372
-/* 335 */     MCD_OPC_Decode, 154, 14, 199, 2, // Opcode: VMOVSR
-/* 340 */     MCD_OPC_FilterValue, 11, 187, 15, 0, // Skip to: 4372
-/* 345 */     MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
-/* 348 */     MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 437
-/* 353 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 356 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 392
-/* 361 */     MCD_OPC_CheckPredicate, 27, 166, 15, 0, // Skip to: 4372
-/* 366 */     MCD_OPC_CheckField, 22, 1, 1, 159, 15, 0, // Skip to: 4372
-/* 373 */     MCD_OPC_CheckField, 6, 2, 0, 152, 15, 0, // Skip to: 4372
-/* 380 */     MCD_OPC_CheckField, 4, 1, 1, 145, 15, 0, // Skip to: 4372
-/* 387 */     MCD_OPC_Decode, 137, 14, 200, 2, // Opcode: VMOVDRR
-/* 392 */     MCD_OPC_FilterValue, 1, 135, 15, 0, // Skip to: 4372
-/* 397 */     MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
-/* 400 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 415
-/* 405 */     MCD_OPC_CheckPredicate, 27, 122, 15, 0, // Skip to: 4372
-/* 410 */     MCD_OPC_Decode, 198, 20, 201, 2, // Opcode: VSTMDIA
-/* 415 */     MCD_OPC_FilterValue, 1, 112, 15, 0, // Skip to: 4372
-/* 420 */     MCD_OPC_CheckPredicate, 27, 107, 15, 0, // Skip to: 4372
-/* 425 */     MCD_OPC_CheckField, 22, 1, 0, 100, 15, 0, // Skip to: 4372
-/* 432 */     MCD_OPC_Decode, 216, 4, 202, 2, // Opcode: FSTMXIA
-/* 437 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 452
-/* 442 */     MCD_OPC_CheckPredicate, 27, 85, 15, 0, // Skip to: 4372
-/* 447 */     MCD_OPC_Decode, 204, 20, 203, 2, // Opcode: VSTRD
-/* 452 */     MCD_OPC_FilterValue, 14, 75, 15, 0, // Skip to: 4372
-/* 457 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 460 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 512
-/* 465 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 468 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 490
-/* 473 */     MCD_OPC_CheckPredicate, 61, 54, 15, 0, // Skip to: 4372
-/* 478 */     MCD_OPC_CheckField, 4, 1, 0, 47, 15, 0, // Skip to: 4372
-/* 485 */     MCD_OPC_Decode, 202, 13, 204, 2, // Opcode: VMLAD
-/* 490 */     MCD_OPC_FilterValue, 1, 37, 15, 0, // Skip to: 4372
-/* 495 */     MCD_OPC_CheckPredicate, 61, 32, 15, 0, // Skip to: 4372
-/* 500 */     MCD_OPC_CheckField, 4, 1, 0, 25, 15, 0, // Skip to: 4372
-/* 507 */     MCD_OPC_Decode, 253, 9, 205, 2, // Opcode: VDIVD
-/* 512 */     MCD_OPC_FilterValue, 1, 15, 15, 0, // Skip to: 4372
-/* 517 */     MCD_OPC_CheckPredicate, 61, 10, 15, 0, // Skip to: 4372
-/* 522 */     MCD_OPC_CheckField, 23, 1, 0, 3, 15, 0, // Skip to: 4372
-/* 529 */     MCD_OPC_CheckField, 4, 1, 0, 252, 14, 0, // Skip to: 4372
-/* 536 */     MCD_OPC_Decode, 233, 13, 204, 2, // Opcode: VMLSD
-/* 541 */     MCD_OPC_FilterValue, 1, 76, 2, 0, // Skip to: 1134
-/* 546 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 549 */     MCD_OPC_FilterValue, 9, 146, 0, 0, // Skip to: 700
-/* 554 */     MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
-/* 557 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 572
-/* 562 */     MCD_OPC_CheckPredicate, 60, 221, 14, 0, // Skip to: 4372
-/* 567 */     MCD_OPC_Decode, 152, 13, 190, 2, // Opcode: VLDRH
-/* 572 */     MCD_OPC_FilterValue, 14, 211, 14, 0, // Skip to: 4372
-/* 577 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 580 */     MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 664
-/* 585 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 588 */     MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 626
-/* 593 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 596 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 611
-/* 601 */     MCD_OPC_CheckPredicate, 60, 182, 14, 0, // Skip to: 4372
-/* 606 */     MCD_OPC_Decode, 237, 14, 191, 2, // Opcode: VNMLSH
-/* 611 */     MCD_OPC_FilterValue, 1, 172, 14, 0, // Skip to: 4372
-/* 616 */     MCD_OPC_CheckPredicate, 60, 167, 14, 0, // Skip to: 4372
-/* 621 */     MCD_OPC_Decode, 167, 10, 191, 2, // Opcode: VFNMSH
-/* 626 */     MCD_OPC_FilterValue, 1, 157, 14, 0, // Skip to: 4372
-/* 631 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 634 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 649
-/* 639 */     MCD_OPC_CheckPredicate, 60, 144, 14, 0, // Skip to: 4372
-/* 644 */     MCD_OPC_Decode, 234, 14, 191, 2, // Opcode: VNMLAH
-/* 649 */     MCD_OPC_FilterValue, 1, 134, 14, 0, // Skip to: 4372
-/* 654 */     MCD_OPC_CheckPredicate, 60, 129, 14, 0, // Skip to: 4372
-/* 659 */     MCD_OPC_Decode, 164, 10, 191, 2, // Opcode: VFNMAH
-/* 664 */     MCD_OPC_FilterValue, 1, 119, 14, 0, // Skip to: 4372
-/* 669 */     MCD_OPC_CheckPredicate, 60, 114, 14, 0, // Skip to: 4372
-/* 674 */     MCD_OPC_CheckField, 22, 2, 0, 107, 14, 0, // Skip to: 4372
-/* 681 */     MCD_OPC_CheckField, 5, 2, 0, 100, 14, 0, // Skip to: 4372
-/* 688 */     MCD_OPC_CheckField, 0, 4, 0, 93, 14, 0, // Skip to: 4372
-/* 695 */     MCD_OPC_Decode, 149, 14, 206, 2, // Opcode: VMOVRH
-/* 700 */     MCD_OPC_FilterValue, 10, 205, 0, 0, // Skip to: 910
-/* 705 */     MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
-/* 708 */     MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 767
-/* 713 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 716 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 752
-/* 721 */     MCD_OPC_CheckPredicate, 27, 62, 14, 0, // Skip to: 4372
-/* 726 */     MCD_OPC_CheckField, 22, 1, 1, 55, 14, 0, // Skip to: 4372
-/* 733 */     MCD_OPC_CheckField, 6, 2, 0, 48, 14, 0, // Skip to: 4372
-/* 740 */     MCD_OPC_CheckField, 4, 1, 1, 41, 14, 0, // Skip to: 4372
-/* 747 */     MCD_OPC_Decode, 151, 14, 207, 2, // Opcode: VMOVRRS
-/* 752 */     MCD_OPC_FilterValue, 1, 31, 14, 0, // Skip to: 4372
-/* 757 */     MCD_OPC_CheckPredicate, 27, 26, 14, 0, // Skip to: 4372
-/* 762 */     MCD_OPC_Decode, 149, 13, 195, 2, // Opcode: VLDMSIA
-/* 767 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 782
-/* 772 */     MCD_OPC_CheckPredicate, 27, 11, 14, 0, // Skip to: 4372
-/* 777 */     MCD_OPC_Decode, 153, 13, 196, 2, // Opcode: VLDRS
-/* 782 */     MCD_OPC_FilterValue, 14, 1, 14, 0, // Skip to: 4372
-/* 787 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 790 */     MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 874
-/* 795 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 798 */     MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 836
-/* 803 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 806 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 821
-/* 811 */     MCD_OPC_CheckPredicate, 27, 228, 13, 0, // Skip to: 4372
-/* 816 */     MCD_OPC_Decode, 238, 14, 197, 2, // Opcode: VNMLSS
-/* 821 */     MCD_OPC_FilterValue, 1, 218, 13, 0, // Skip to: 4372
-/* 826 */     MCD_OPC_CheckPredicate, 62, 213, 13, 0, // Skip to: 4372
-/* 831 */     MCD_OPC_Decode, 168, 10, 197, 2, // Opcode: VFNMSS
-/* 836 */     MCD_OPC_FilterValue, 1, 203, 13, 0, // Skip to: 4372
-/* 841 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 844 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 859
-/* 849 */     MCD_OPC_CheckPredicate, 27, 190, 13, 0, // Skip to: 4372
-/* 854 */     MCD_OPC_Decode, 235, 14, 197, 2, // Opcode: VNMLAS
-/* 859 */     MCD_OPC_FilterValue, 1, 180, 13, 0, // Skip to: 4372
-/* 864 */     MCD_OPC_CheckPredicate, 62, 175, 13, 0, // Skip to: 4372
-/* 869 */     MCD_OPC_Decode, 165, 10, 197, 2, // Opcode: VFNMAS
-/* 874 */     MCD_OPC_FilterValue, 1, 165, 13, 0, // Skip to: 4372
-/* 879 */     MCD_OPC_CheckPredicate, 27, 160, 13, 0, // Skip to: 4372
-/* 884 */     MCD_OPC_CheckField, 22, 2, 0, 153, 13, 0, // Skip to: 4372
-/* 891 */     MCD_OPC_CheckField, 5, 2, 0, 146, 13, 0, // Skip to: 4372
-/* 898 */     MCD_OPC_CheckField, 0, 4, 0, 139, 13, 0, // Skip to: 4372
-/* 905 */     MCD_OPC_Decode, 152, 14, 208, 2, // Opcode: VMOVRS
-/* 910 */     MCD_OPC_FilterValue, 11, 129, 13, 0, // Skip to: 4372
-/* 915 */     MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
-/* 918 */     MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 1007
-/* 923 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 926 */     MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 962
-/* 931 */     MCD_OPC_CheckPredicate, 27, 108, 13, 0, // Skip to: 4372
-/* 936 */     MCD_OPC_CheckField, 22, 1, 1, 101, 13, 0, // Skip to: 4372
-/* 943 */     MCD_OPC_CheckField, 6, 2, 0, 94, 13, 0, // Skip to: 4372
-/* 950 */     MCD_OPC_CheckField, 4, 1, 1, 87, 13, 0, // Skip to: 4372
-/* 957 */     MCD_OPC_Decode, 150, 14, 209, 2, // Opcode: VMOVRRD
-/* 962 */     MCD_OPC_FilterValue, 1, 77, 13, 0, // Skip to: 4372
-/* 967 */     MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
-/* 970 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 985
-/* 975 */     MCD_OPC_CheckPredicate, 27, 64, 13, 0, // Skip to: 4372
-/* 980 */     MCD_OPC_Decode, 145, 13, 201, 2, // Opcode: VLDMDIA
-/* 985 */     MCD_OPC_FilterValue, 1, 54, 13, 0, // Skip to: 4372
-/* 990 */     MCD_OPC_CheckPredicate, 27, 49, 13, 0, // Skip to: 4372
-/* 995 */     MCD_OPC_CheckField, 22, 1, 0, 42, 13, 0, // Skip to: 4372
-/* 1002 */    MCD_OPC_Decode, 212, 4, 202, 2, // Opcode: FLDMXIA
-/* 1007 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1022
-/* 1012 */    MCD_OPC_CheckPredicate, 27, 27, 13, 0, // Skip to: 4372
-/* 1017 */    MCD_OPC_Decode, 151, 13, 203, 2, // Opcode: VLDRD
-/* 1022 */    MCD_OPC_FilterValue, 14, 17, 13, 0, // Skip to: 4372
-/* 1027 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1030 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1082
-/* 1035 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 1038 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1060
-/* 1043 */    MCD_OPC_CheckPredicate, 61, 252, 12, 0, // Skip to: 4372
-/* 1048 */    MCD_OPC_CheckField, 4, 1, 0, 245, 12, 0, // Skip to: 4372
-/* 1055 */    MCD_OPC_Decode, 236, 14, 204, 2, // Opcode: VNMLSD
-/* 1060 */    MCD_OPC_FilterValue, 1, 235, 12, 0, // Skip to: 4372
-/* 1065 */    MCD_OPC_CheckPredicate, 63, 230, 12, 0, // Skip to: 4372
-/* 1070 */    MCD_OPC_CheckField, 4, 1, 0, 223, 12, 0, // Skip to: 4372
-/* 1077 */    MCD_OPC_Decode, 166, 10, 204, 2, // Opcode: VFNMSD
-/* 1082 */    MCD_OPC_FilterValue, 1, 213, 12, 0, // Skip to: 4372
-/* 1087 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
-/* 1090 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1112
-/* 1095 */    MCD_OPC_CheckPredicate, 61, 200, 12, 0, // Skip to: 4372
-/* 1100 */    MCD_OPC_CheckField, 4, 1, 0, 193, 12, 0, // Skip to: 4372
-/* 1107 */    MCD_OPC_Decode, 233, 14, 204, 2, // Opcode: VNMLAD
-/* 1112 */    MCD_OPC_FilterValue, 1, 183, 12, 0, // Skip to: 4372
-/* 1117 */    MCD_OPC_CheckPredicate, 63, 178, 12, 0, // Skip to: 4372
-/* 1122 */    MCD_OPC_CheckField, 4, 1, 0, 171, 12, 0, // Skip to: 4372
-/* 1129 */    MCD_OPC_Decode, 163, 10, 204, 2, // Opcode: VFNMAD
-/* 1134 */    MCD_OPC_FilterValue, 2, 132, 2, 0, // Skip to: 1783
-/* 1139 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
-/* 1142 */    MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1172
-/* 1147 */    MCD_OPC_CheckPredicate, 64, 148, 12, 0, // Skip to: 4372
-/* 1152 */    MCD_OPC_CheckField, 22, 1, 0, 141, 12, 0, // Skip to: 4372
-/* 1159 */    MCD_OPC_CheckField, 0, 16, 128, 20, 133, 12, 0, // Skip to: 4372
-/* 1167 */    MCD_OPC_Decode, 155, 13, 210, 2, // Opcode: VLSTM
-/* 1172 */    MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1240
-/* 1177 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1180 */    MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1195
-/* 1185 */    MCD_OPC_CheckPredicate, 27, 110, 12, 0, // Skip to: 4372
-/* 1190 */    MCD_OPC_Decode, 203, 20, 211, 2, // Opcode: VSTMSIA_UPD
-/* 1195 */    MCD_OPC_FilterValue, 11, 100, 12, 0, // Skip to: 4372
-/* 1200 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
-/* 1203 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1218
-/* 1208 */    MCD_OPC_CheckPredicate, 27, 87, 12, 0, // Skip to: 4372
-/* 1213 */    MCD_OPC_Decode, 199, 20, 212, 2, // Opcode: VSTMDIA_UPD
-/* 1218 */    MCD_OPC_FilterValue, 1, 77, 12, 0, // Skip to: 4372
-/* 1223 */    MCD_OPC_CheckPredicate, 27, 72, 12, 0, // Skip to: 4372
-/* 1228 */    MCD_OPC_CheckField, 22, 1, 0, 65, 12, 0, // Skip to: 4372
-/* 1235 */    MCD_OPC_Decode, 217, 4, 213, 2, // Opcode: FSTMXIA_UPD
-/* 1240 */    MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1308
-/* 1245 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1248 */    MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1263
-/* 1253 */    MCD_OPC_CheckPredicate, 27, 42, 12, 0, // Skip to: 4372
-/* 1258 */    MCD_OPC_Decode, 201, 20, 211, 2, // Opcode: VSTMSDB_UPD
-/* 1263 */    MCD_OPC_FilterValue, 11, 32, 12, 0, // Skip to: 4372
-/* 1268 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
-/* 1271 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1286
-/* 1276 */    MCD_OPC_CheckPredicate, 27, 19, 12, 0, // Skip to: 4372
-/* 1281 */    MCD_OPC_Decode, 197, 20, 212, 2, // Opcode: VSTMDDB_UPD
-/* 1286 */    MCD_OPC_FilterValue, 1, 9, 12, 0, // Skip to: 4372
-/* 1291 */    MCD_OPC_CheckPredicate, 27, 4, 12, 0, // Skip to: 4372
-/* 1296 */    MCD_OPC_CheckField, 22, 1, 0, 253, 11, 0, // Skip to: 4372
-/* 1303 */    MCD_OPC_Decode, 215, 4, 213, 2, // Opcode: FSTMXDB_UPD
-/* 1308 */    MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 1472
-/* 1313 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1316 */    MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1368
-/* 1321 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1324 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1346
-/* 1329 */    MCD_OPC_CheckPredicate, 60, 222, 11, 0, // Skip to: 4372
-/* 1334 */    MCD_OPC_CheckField, 4, 1, 0, 215, 11, 0, // Skip to: 4372
-/* 1341 */    MCD_OPC_Decode, 180, 14, 192, 2, // Opcode: VMULH
-/* 1346 */    MCD_OPC_FilterValue, 1, 205, 11, 0, // Skip to: 4372
-/* 1351 */    MCD_OPC_CheckPredicate, 60, 200, 11, 0, // Skip to: 4372
-/* 1356 */    MCD_OPC_CheckField, 4, 1, 0, 193, 11, 0, // Skip to: 4372
-/* 1363 */    MCD_OPC_Decode, 240, 14, 192, 2, // Opcode: VNMULH
-/* 1368 */    MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 1420
-/* 1373 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1376 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1398
-/* 1381 */    MCD_OPC_CheckPredicate, 27, 170, 11, 0, // Skip to: 4372
-/* 1386 */    MCD_OPC_CheckField, 4, 1, 0, 163, 11, 0, // Skip to: 4372
-/* 1393 */    MCD_OPC_Decode, 193, 14, 198, 2, // Opcode: VMULS
-/* 1398 */    MCD_OPC_FilterValue, 1, 153, 11, 0, // Skip to: 4372
-/* 1403 */    MCD_OPC_CheckPredicate, 27, 148, 11, 0, // Skip to: 4372
-/* 1408 */    MCD_OPC_CheckField, 4, 1, 0, 141, 11, 0, // Skip to: 4372
-/* 1415 */    MCD_OPC_Decode, 241, 14, 198, 2, // Opcode: VNMULS
-/* 1420 */    MCD_OPC_FilterValue, 11, 131, 11, 0, // Skip to: 4372
-/* 1425 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1428 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1450
-/* 1433 */    MCD_OPC_CheckPredicate, 61, 118, 11, 0, // Skip to: 4372
-/* 1438 */    MCD_OPC_CheckField, 4, 1, 0, 111, 11, 0, // Skip to: 4372
-/* 1445 */    MCD_OPC_Decode, 179, 14, 205, 2, // Opcode: VMULD
-/* 1450 */    MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 4372
-/* 1455 */    MCD_OPC_CheckPredicate, 61, 96, 11, 0, // Skip to: 4372
-/* 1460 */    MCD_OPC_CheckField, 4, 1, 0, 89, 11, 0, // Skip to: 4372
-/* 1467 */    MCD_OPC_Decode, 239, 14, 205, 2, // Opcode: VNMULD
-/* 1472 */    MCD_OPC_FilterValue, 29, 79, 11, 0, // Skip to: 4372
-/* 1477 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1480 */    MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 1532
-/* 1485 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1488 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1510
-/* 1493 */    MCD_OPC_CheckPredicate, 60, 58, 11, 0, // Skip to: 4372
-/* 1498 */    MCD_OPC_CheckField, 4, 1, 0, 51, 11, 0, // Skip to: 4372
-/* 1505 */    MCD_OPC_Decode, 150, 10, 191, 2, // Opcode: VFMAH
-/* 1510 */    MCD_OPC_FilterValue, 1, 41, 11, 0, // Skip to: 4372
-/* 1515 */    MCD_OPC_CheckPredicate, 60, 36, 11, 0, // Skip to: 4372
-/* 1520 */    MCD_OPC_CheckField, 4, 1, 0, 29, 11, 0, // Skip to: 4372
-/* 1527 */    MCD_OPC_Decode, 157, 10, 191, 2, // Opcode: VFMSH
-/* 1532 */    MCD_OPC_FilterValue, 10, 194, 0, 0, // Skip to: 1731
-/* 1537 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 1540 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1578
-/* 1545 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1548 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1563
-/* 1553 */    MCD_OPC_CheckPredicate, 62, 254, 10, 0, // Skip to: 4372
-/* 1558 */    MCD_OPC_Decode, 151, 10, 197, 2, // Opcode: VFMAS
-/* 1563 */    MCD_OPC_FilterValue, 1, 244, 10, 0, // Skip to: 4372
-/* 1568 */    MCD_OPC_CheckPredicate, 62, 239, 10, 0, // Skip to: 4372
-/* 1573 */    MCD_OPC_Decode, 158, 10, 197, 2, // Opcode: VFMSS
-/* 1578 */    MCD_OPC_FilterValue, 1, 229, 10, 0, // Skip to: 4372
-/* 1583 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 1586 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1615
-/* 1591 */    MCD_OPC_CheckPredicate, 27, 216, 10, 0, // Skip to: 4372
-/* 1596 */    MCD_OPC_CheckField, 22, 1, 1, 209, 10, 0, // Skip to: 4372
-/* 1603 */    MCD_OPC_CheckField, 7, 1, 0, 202, 10, 0, // Skip to: 4372
-/* 1610 */    MCD_OPC_Decode, 178, 14, 214, 2, // Opcode: VMSR_FPSID
-/* 1615 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 1644
-/* 1620 */    MCD_OPC_CheckPredicate, 27, 187, 10, 0, // Skip to: 4372
-/* 1625 */    MCD_OPC_CheckField, 22, 1, 1, 180, 10, 0, // Skip to: 4372
-/* 1632 */    MCD_OPC_CheckField, 7, 1, 0, 173, 10, 0, // Skip to: 4372
-/* 1639 */    MCD_OPC_Decode, 174, 14, 214, 2, // Opcode: VMSR
-/* 1644 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 1673
-/* 1649 */    MCD_OPC_CheckPredicate, 27, 158, 10, 0, // Skip to: 4372
-/* 1654 */    MCD_OPC_CheckField, 22, 1, 1, 151, 10, 0, // Skip to: 4372
-/* 1661 */    MCD_OPC_CheckField, 7, 1, 0, 144, 10, 0, // Skip to: 4372
-/* 1668 */    MCD_OPC_Decode, 175, 14, 214, 2, // Opcode: VMSR_FPEXC
-/* 1673 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 1702
-/* 1678 */    MCD_OPC_CheckPredicate, 27, 129, 10, 0, // Skip to: 4372
-/* 1683 */    MCD_OPC_CheckField, 22, 1, 1, 122, 10, 0, // Skip to: 4372
-/* 1690 */    MCD_OPC_CheckField, 7, 1, 0, 115, 10, 0, // Skip to: 4372
-/* 1697 */    MCD_OPC_Decode, 176, 14, 214, 2, // Opcode: VMSR_FPINST
-/* 1702 */    MCD_OPC_FilterValue, 10, 105, 10, 0, // Skip to: 4372
-/* 1707 */    MCD_OPC_CheckPredicate, 27, 100, 10, 0, // Skip to: 4372
-/* 1712 */    MCD_OPC_CheckField, 22, 1, 1, 93, 10, 0, // Skip to: 4372
-/* 1719 */    MCD_OPC_CheckField, 7, 1, 0, 86, 10, 0, // Skip to: 4372
-/* 1726 */    MCD_OPC_Decode, 177, 14, 214, 2, // Opcode: VMSR_FPINST2
-/* 1731 */    MCD_OPC_FilterValue, 11, 76, 10, 0, // Skip to: 4372
-/* 1736 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1739 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1761
-/* 1744 */    MCD_OPC_CheckPredicate, 63, 63, 10, 0, // Skip to: 4372
-/* 1749 */    MCD_OPC_CheckField, 4, 1, 0, 56, 10, 0, // Skip to: 4372
-/* 1756 */    MCD_OPC_Decode, 149, 10, 204, 2, // Opcode: VFMAD
-/* 1761 */    MCD_OPC_FilterValue, 1, 46, 10, 0, // Skip to: 4372
-/* 1766 */    MCD_OPC_CheckPredicate, 63, 41, 10, 0, // Skip to: 4372
-/* 1771 */    MCD_OPC_CheckField, 4, 1, 0, 34, 10, 0, // Skip to: 4372
-/* 1778 */    MCD_OPC_Decode, 156, 10, 204, 2, // Opcode: VFMSD
-/* 1783 */    MCD_OPC_FilterValue, 3, 24, 10, 0, // Skip to: 4372
-/* 1788 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
-/* 1791 */    MCD_OPC_FilterValue, 24, 25, 0, 0, // Skip to: 1821
-/* 1796 */    MCD_OPC_CheckPredicate, 64, 11, 10, 0, // Skip to: 4372
-/* 1801 */    MCD_OPC_CheckField, 22, 1, 0, 4, 10, 0, // Skip to: 4372
-/* 1808 */    MCD_OPC_CheckField, 0, 16, 128, 20, 252, 9, 0, // Skip to: 4372
-/* 1816 */    MCD_OPC_Decode, 154, 13, 210, 2, // Opcode: VLLDM
-/* 1821 */    MCD_OPC_FilterValue, 25, 63, 0, 0, // Skip to: 1889
-/* 1826 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1829 */    MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1844
-/* 1834 */    MCD_OPC_CheckPredicate, 27, 229, 9, 0, // Skip to: 4372
-/* 1839 */    MCD_OPC_Decode, 150, 13, 211, 2, // Opcode: VLDMSIA_UPD
-/* 1844 */    MCD_OPC_FilterValue, 11, 219, 9, 0, // Skip to: 4372
-/* 1849 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
-/* 1852 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1867
-/* 1857 */    MCD_OPC_CheckPredicate, 27, 206, 9, 0, // Skip to: 4372
-/* 1862 */    MCD_OPC_Decode, 146, 13, 212, 2, // Opcode: VLDMDIA_UPD
-/* 1867 */    MCD_OPC_FilterValue, 1, 196, 9, 0, // Skip to: 4372
-/* 1872 */    MCD_OPC_CheckPredicate, 27, 191, 9, 0, // Skip to: 4372
-/* 1877 */    MCD_OPC_CheckField, 22, 1, 0, 184, 9, 0, // Skip to: 4372
-/* 1884 */    MCD_OPC_Decode, 213, 4, 213, 2, // Opcode: FLDMXIA_UPD
-/* 1889 */    MCD_OPC_FilterValue, 26, 63, 0, 0, // Skip to: 1957
-/* 1894 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1897 */    MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 1912
-/* 1902 */    MCD_OPC_CheckPredicate, 27, 161, 9, 0, // Skip to: 4372
-/* 1907 */    MCD_OPC_Decode, 148, 13, 211, 2, // Opcode: VLDMSDB_UPD
-/* 1912 */    MCD_OPC_FilterValue, 11, 151, 9, 0, // Skip to: 4372
-/* 1917 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
-/* 1920 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1935
-/* 1925 */    MCD_OPC_CheckPredicate, 27, 138, 9, 0, // Skip to: 4372
-/* 1930 */    MCD_OPC_Decode, 144, 13, 212, 2, // Opcode: VLDMDDB_UPD
-/* 1935 */    MCD_OPC_FilterValue, 1, 128, 9, 0, // Skip to: 4372
-/* 1940 */    MCD_OPC_CheckPredicate, 27, 123, 9, 0, // Skip to: 4372
-/* 1945 */    MCD_OPC_CheckField, 22, 1, 0, 116, 9, 0, // Skip to: 4372
-/* 1952 */    MCD_OPC_Decode, 211, 4, 213, 2, // Opcode: FLDMXDB_UPD
-/* 1957 */    MCD_OPC_FilterValue, 28, 159, 0, 0, // Skip to: 2121
-/* 1962 */    MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 1965 */    MCD_OPC_FilterValue, 9, 47, 0, 0, // Skip to: 2017
-/* 1970 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1973 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1995
-/* 1978 */    MCD_OPC_CheckPredicate, 60, 85, 9, 0, // Skip to: 4372
-/* 1983 */    MCD_OPC_CheckField, 4, 1, 0, 78, 9, 0, // Skip to: 4372
-/* 1990 */    MCD_OPC_Decode, 236, 7, 192, 2, // Opcode: VADDH
-/* 1995 */    MCD_OPC_FilterValue, 1, 68, 9, 0, // Skip to: 4372
-/* 2000 */    MCD_OPC_CheckPredicate, 60, 63, 9, 0, // Skip to: 4372
-/* 2005 */    MCD_OPC_CheckField, 4, 1, 0, 56, 9, 0, // Skip to: 4372
-/* 2012 */    MCD_OPC_Decode, 208, 20, 192, 2, // Opcode: VSUBH
-/* 2017 */    MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 2069
-/* 2022 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2025 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2047
-/* 2030 */    MCD_OPC_CheckPredicate, 27, 33, 9, 0, // Skip to: 4372
-/* 2035 */    MCD_OPC_CheckField, 4, 1, 0, 26, 9, 0, // Skip to: 4372
-/* 2042 */    MCD_OPC_Decode, 246, 7, 198, 2, // Opcode: VADDS
-/* 2047 */    MCD_OPC_FilterValue, 1, 16, 9, 0, // Skip to: 4372
-/* 2052 */    MCD_OPC_CheckPredicate, 27, 11, 9, 0, // Skip to: 4372
-/* 2057 */    MCD_OPC_CheckField, 4, 1, 0, 4, 9, 0, // Skip to: 4372
-/* 2064 */    MCD_OPC_Decode, 218, 20, 198, 2, // Opcode: VSUBS
-/* 2069 */    MCD_OPC_FilterValue, 11, 250, 8, 0, // Skip to: 4372
-/* 2074 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2077 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2099
-/* 2082 */    MCD_OPC_CheckPredicate, 61, 237, 8, 0, // Skip to: 4372
-/* 2087 */    MCD_OPC_CheckField, 4, 1, 0, 230, 8, 0, // Skip to: 4372
-/* 2094 */    MCD_OPC_Decode, 235, 7, 205, 2, // Opcode: VADDD
-/* 2099 */    MCD_OPC_FilterValue, 1, 220, 8, 0, // Skip to: 4372
-/* 2104 */    MCD_OPC_CheckPredicate, 61, 215, 8, 0, // Skip to: 4372
-/* 2109 */    MCD_OPC_CheckField, 4, 1, 0, 208, 8, 0, // Skip to: 4372
-/* 2116 */    MCD_OPC_Decode, 207, 20, 205, 2, // Opcode: VSUBD
-/* 2121 */    MCD_OPC_FilterValue, 29, 198, 8, 0, // Skip to: 4372
-/* 2126 */    MCD_OPC_ExtractField, 6, 6,  // Inst{11-6} ...
-/* 2129 */    MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 2151
-/* 2134 */    MCD_OPC_CheckPredicate, 60, 185, 8, 0, // Skip to: 4372
-/* 2139 */    MCD_OPC_CheckField, 4, 2, 0, 178, 8, 0, // Skip to: 4372
-/* 2146 */    MCD_OPC_Decode, 209, 4, 215, 2, // Opcode: FCONSTH
-/* 2151 */    MCD_OPC_FilterValue, 37, 11, 1, 0, // Skip to: 2423
-/* 2156 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 2159 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2181
-/* 2164 */    MCD_OPC_CheckPredicate, 60, 155, 8, 0, // Skip to: 4372
-/* 2169 */    MCD_OPC_CheckField, 4, 1, 0, 148, 8, 0, // Skip to: 4372
-/* 2176 */    MCD_OPC_Decode, 221, 14, 216, 2, // Opcode: VNEGH
-/* 2181 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2203
-/* 2186 */    MCD_OPC_CheckPredicate, 60, 133, 8, 0, // Skip to: 4372
-/* 2191 */    MCD_OPC_CheckField, 4, 1, 0, 126, 8, 0, // Skip to: 4372
-/* 2198 */    MCD_OPC_Decode, 146, 9, 216, 2, // Opcode: VCMPH
-/* 2203 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2225
-/* 2208 */    MCD_OPC_CheckPredicate, 60, 111, 8, 0, // Skip to: 4372
-/* 2213 */    MCD_OPC_CheckField, 0, 6, 0, 104, 8, 0, // Skip to: 4372
-/* 2220 */    MCD_OPC_Decode, 149, 9, 217, 2, // Opcode: VCMPZH
-/* 2225 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2247
-/* 2230 */    MCD_OPC_CheckPredicate, 60, 89, 8, 0, // Skip to: 4372
-/* 2235 */    MCD_OPC_CheckField, 4, 1, 0, 82, 8, 0, // Skip to: 4372
-/* 2242 */    MCD_OPC_Decode, 148, 17, 218, 2, // Opcode: VRINTRH
-/* 2247 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 2269
-/* 2252 */    MCD_OPC_CheckPredicate, 60, 67, 8, 0, // Skip to: 4372
-/* 2257 */    MCD_OPC_CheckField, 4, 1, 0, 60, 8, 0, // Skip to: 4372
-/* 2264 */    MCD_OPC_Decode, 151, 17, 218, 2, // Opcode: VRINTXH
-/* 2269 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2291
-/* 2274 */    MCD_OPC_CheckPredicate, 60, 45, 8, 0, // Skip to: 4372
-/* 2279 */    MCD_OPC_CheckField, 4, 1, 0, 38, 8, 0, // Skip to: 4372
-/* 2286 */    MCD_OPC_Decode, 167, 21, 219, 2, // Opcode: VUITOH
-/* 2291 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2313
-/* 2296 */    MCD_OPC_CheckPredicate, 60, 23, 8, 0, // Skip to: 4372
-/* 2301 */    MCD_OPC_CheckField, 4, 1, 0, 16, 8, 0, // Skip to: 4372
-/* 2308 */    MCD_OPC_Decode, 172, 18, 220, 2, // Opcode: VSHTOH
-/* 2313 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2335
-/* 2318 */    MCD_OPC_CheckPredicate, 60, 1, 8, 0, // Skip to: 4372
-/* 2323 */    MCD_OPC_CheckField, 4, 1, 0, 250, 7, 0, // Skip to: 4372
-/* 2330 */    MCD_OPC_Decode, 164, 21, 220, 2, // Opcode: VUHTOH
-/* 2335 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2357
-/* 2340 */    MCD_OPC_CheckPredicate, 60, 235, 7, 0, // Skip to: 4372
-/* 2345 */    MCD_OPC_CheckField, 4, 1, 0, 228, 7, 0, // Skip to: 4372
-/* 2352 */    MCD_OPC_Decode, 139, 21, 218, 2, // Opcode: VTOUIRH
-/* 2357 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2379
-/* 2362 */    MCD_OPC_CheckPredicate, 60, 213, 7, 0, // Skip to: 4372
-/* 2367 */    MCD_OPC_CheckField, 4, 1, 0, 206, 7, 0, // Skip to: 4372
-/* 2374 */    MCD_OPC_Decode, 255, 20, 218, 2, // Opcode: VTOSIRH
-/* 2379 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2401
-/* 2384 */    MCD_OPC_CheckPredicate, 60, 191, 7, 0, // Skip to: 4372
-/* 2389 */    MCD_OPC_CheckField, 4, 1, 0, 184, 7, 0, // Skip to: 4372
-/* 2396 */    MCD_OPC_Decode, 252, 20, 220, 2, // Opcode: VTOSHH
-/* 2401 */    MCD_OPC_FilterValue, 15, 174, 7, 0, // Skip to: 4372
-/* 2406 */    MCD_OPC_CheckPredicate, 60, 169, 7, 0, // Skip to: 4372
-/* 2411 */    MCD_OPC_CheckField, 4, 1, 0, 162, 7, 0, // Skip to: 4372
-/* 2418 */    MCD_OPC_Decode, 136, 21, 220, 2, // Opcode: VTOUHH
-/* 2423 */    MCD_OPC_FilterValue, 39, 11, 1, 0, // Skip to: 2695
-/* 2428 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 2431 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2453
-/* 2436 */    MCD_OPC_CheckPredicate, 60, 139, 7, 0, // Skip to: 4372
-/* 2441 */    MCD_OPC_CheckField, 4, 1, 0, 132, 7, 0, // Skip to: 4372
-/* 2448 */    MCD_OPC_Decode, 215, 7, 218, 2, // Opcode: VABSH
-/* 2453 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 2475
-/* 2458 */    MCD_OPC_CheckPredicate, 60, 117, 7, 0, // Skip to: 4372
-/* 2463 */    MCD_OPC_CheckField, 4, 1, 0, 110, 7, 0, // Skip to: 4372
-/* 2470 */    MCD_OPC_Decode, 189, 18, 218, 2, // Opcode: VSQRTH
-/* 2475 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 2497
-/* 2480 */    MCD_OPC_CheckPredicate, 60, 95, 7, 0, // Skip to: 4372
-/* 2485 */    MCD_OPC_CheckField, 4, 1, 0, 88, 7, 0, // Skip to: 4372
-/* 2492 */    MCD_OPC_Decode, 141, 9, 216, 2, // Opcode: VCMPEH
-/* 2497 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 2519
-/* 2502 */    MCD_OPC_CheckPredicate, 60, 73, 7, 0, // Skip to: 4372
-/* 2507 */    MCD_OPC_CheckField, 0, 6, 0, 66, 7, 0, // Skip to: 4372
-/* 2514 */    MCD_OPC_Decode, 144, 9, 217, 2, // Opcode: VCMPEZH
-/* 2519 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 2541
-/* 2524 */    MCD_OPC_CheckPredicate, 60, 51, 7, 0, // Skip to: 4372
-/* 2529 */    MCD_OPC_CheckField, 4, 1, 0, 44, 7, 0, // Skip to: 4372
-/* 2536 */    MCD_OPC_Decode, 158, 17, 218, 2, // Opcode: VRINTZH
-/* 2541 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 2563
-/* 2546 */    MCD_OPC_CheckPredicate, 60, 29, 7, 0, // Skip to: 4372
-/* 2551 */    MCD_OPC_CheckField, 4, 1, 0, 22, 7, 0, // Skip to: 4372
-/* 2558 */    MCD_OPC_Decode, 175, 18, 219, 2, // Opcode: VSITOH
-/* 2563 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 2585
-/* 2568 */    MCD_OPC_CheckPredicate, 60, 7, 7, 0, // Skip to: 4372
-/* 2573 */    MCD_OPC_CheckField, 4, 1, 0, 0, 7, 0, // Skip to: 4372
-/* 2580 */    MCD_OPC_Decode, 186, 18, 220, 2, // Opcode: VSLTOH
-/* 2585 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 2607
-/* 2590 */    MCD_OPC_CheckPredicate, 60, 241, 6, 0, // Skip to: 4372
-/* 2595 */    MCD_OPC_CheckField, 4, 1, 0, 234, 6, 0, // Skip to: 4372
-/* 2602 */    MCD_OPC_Decode, 170, 21, 220, 2, // Opcode: VULTOH
-/* 2607 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 2629
-/* 2612 */    MCD_OPC_CheckPredicate, 60, 219, 6, 0, // Skip to: 4372
-/* 2617 */    MCD_OPC_CheckField, 4, 1, 0, 212, 6, 0, // Skip to: 4372
-/* 2624 */    MCD_OPC_Decode, 142, 21, 221, 2, // Opcode: VTOUIZH
-/* 2629 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 2651
-/* 2634 */    MCD_OPC_CheckPredicate, 60, 197, 6, 0, // Skip to: 4372
-/* 2639 */    MCD_OPC_CheckField, 4, 1, 0, 190, 6, 0, // Skip to: 4372
-/* 2646 */    MCD_OPC_Decode, 130, 21, 221, 2, // Opcode: VTOSIZH
-/* 2651 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 2673
-/* 2656 */    MCD_OPC_CheckPredicate, 60, 175, 6, 0, // Skip to: 4372
-/* 2661 */    MCD_OPC_CheckField, 4, 1, 0, 168, 6, 0, // Skip to: 4372
-/* 2668 */    MCD_OPC_Decode, 133, 21, 220, 2, // Opcode: VTOSLH
-/* 2673 */    MCD_OPC_FilterValue, 15, 158, 6, 0, // Skip to: 4372
-/* 2678 */    MCD_OPC_CheckPredicate, 60, 153, 6, 0, // Skip to: 4372
-/* 2683 */    MCD_OPC_CheckField, 4, 1, 0, 146, 6, 0, // Skip to: 4372
-/* 2690 */    MCD_OPC_Decode, 145, 21, 220, 2, // Opcode: VTOULH
-/* 2695 */    MCD_OPC_FilterValue, 40, 20, 1, 0, // Skip to: 2976
-/* 2700 */    MCD_OPC_ExtractField, 4, 2,  // Inst{5-4} ...
-/* 2703 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2718
-/* 2708 */    MCD_OPC_CheckPredicate, 65, 123, 6, 0, // Skip to: 4372
-/* 2713 */    MCD_OPC_Decode, 210, 4, 222, 2, // Opcode: FCONSTS
-/* 2718 */    MCD_OPC_FilterValue, 1, 113, 6, 0, // Skip to: 4372
-/* 2723 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 2726 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2755
-/* 2731 */    MCD_OPC_CheckPredicate, 27, 100, 6, 0, // Skip to: 4372
-/* 2736 */    MCD_OPC_CheckField, 22, 1, 1, 93, 6, 0, // Skip to: 4372
-/* 2743 */    MCD_OPC_CheckField, 0, 4, 0, 86, 6, 0, // Skip to: 4372
-/* 2750 */    MCD_OPC_Decode, 170, 14, 214, 2, // Opcode: VMRS_FPSID
-/* 2755 */    MCD_OPC_FilterValue, 1, 42, 0, 0, // Skip to: 2802
-/* 2760 */    MCD_OPC_ExtractField, 0, 4,  // Inst{3-0} ...
-/* 2763 */    MCD_OPC_FilterValue, 0, 68, 6, 0, // Skip to: 4372
-/* 2768 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
-/* 2771 */    MCD_OPC_FilterValue, 1, 60, 6, 0, // Skip to: 4372
-/* 2776 */    MCD_OPC_CheckPredicate, 27, 11, 0, 0, // Skip to: 2792
-/* 2781 */    MCD_OPC_CheckField, 12, 4, 15, 4, 0, 0, // Skip to: 2792
-/* 2788 */    MCD_OPC_Decode, 214, 4, 29, // Opcode: FMSTAT
-/* 2792 */    MCD_OPC_CheckPredicate, 27, 39, 6, 0, // Skip to: 4372
-/* 2797 */    MCD_OPC_Decode, 166, 14, 214, 2, // Opcode: VMRS
-/* 2802 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 2831
-/* 2807 */    MCD_OPC_CheckPredicate, 66, 24, 6, 0, // Skip to: 4372
-/* 2812 */    MCD_OPC_CheckField, 22, 1, 1, 17, 6, 0, // Skip to: 4372
-/* 2819 */    MCD_OPC_CheckField, 0, 4, 0, 10, 6, 0, // Skip to: 4372
-/* 2826 */    MCD_OPC_Decode, 173, 14, 214, 2, // Opcode: VMRS_MVFR2
-/* 2831 */    MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 2860
-/* 2836 */    MCD_OPC_CheckPredicate, 27, 251, 5, 0, // Skip to: 4372
-/* 2841 */    MCD_OPC_CheckField, 22, 1, 1, 244, 5, 0, // Skip to: 4372
-/* 2848 */    MCD_OPC_CheckField, 0, 4, 0, 237, 5, 0, // Skip to: 4372
-/* 2855 */    MCD_OPC_Decode, 172, 14, 214, 2, // Opcode: VMRS_MVFR1
-/* 2860 */    MCD_OPC_FilterValue, 7, 24, 0, 0, // Skip to: 2889
-/* 2865 */    MCD_OPC_CheckPredicate, 27, 222, 5, 0, // Skip to: 4372
-/* 2870 */    MCD_OPC_CheckField, 22, 1, 1, 215, 5, 0, // Skip to: 4372
-/* 2877 */    MCD_OPC_CheckField, 0, 4, 0, 208, 5, 0, // Skip to: 4372
-/* 2884 */    MCD_OPC_Decode, 171, 14, 214, 2, // Opcode: VMRS_MVFR0
-/* 2889 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 2918
-/* 2894 */    MCD_OPC_CheckPredicate, 27, 193, 5, 0, // Skip to: 4372
-/* 2899 */    MCD_OPC_CheckField, 22, 1, 1, 186, 5, 0, // Skip to: 4372
-/* 2906 */    MCD_OPC_CheckField, 0, 4, 0, 179, 5, 0, // Skip to: 4372
-/* 2913 */    MCD_OPC_Decode, 167, 14, 214, 2, // Opcode: VMRS_FPEXC
-/* 2918 */    MCD_OPC_FilterValue, 9, 24, 0, 0, // Skip to: 2947
-/* 2923 */    MCD_OPC_CheckPredicate, 27, 164, 5, 0, // Skip to: 4372
-/* 2928 */    MCD_OPC_CheckField, 22, 1, 1, 157, 5, 0, // Skip to: 4372
-/* 2935 */    MCD_OPC_CheckField, 0, 4, 0, 150, 5, 0, // Skip to: 4372
-/* 2942 */    MCD_OPC_Decode, 168, 14, 214, 2, // Opcode: VMRS_FPINST
-/* 2947 */    MCD_OPC_FilterValue, 10, 140, 5, 0, // Skip to: 4372
-/* 2952 */    MCD_OPC_CheckPredicate, 27, 135, 5, 0, // Skip to: 4372
-/* 2957 */    MCD_OPC_CheckField, 22, 1, 1, 128, 5, 0, // Skip to: 4372
-/* 2964 */    MCD_OPC_CheckField, 0, 4, 0, 121, 5, 0, // Skip to: 4372
-/* 2971 */    MCD_OPC_Decode, 169, 14, 214, 2, // Opcode: VMRS_FPINST2
-/* 2976 */    MCD_OPC_FilterValue, 41, 77, 1, 0, // Skip to: 3314
-/* 2981 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 2984 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3006
-/* 2989 */    MCD_OPC_CheckPredicate, 27, 98, 5, 0, // Skip to: 4372
-/* 2994 */    MCD_OPC_CheckField, 4, 1, 0, 91, 5, 0, // Skip to: 4372
-/* 3001 */    MCD_OPC_Decode, 153, 14, 218, 2, // Opcode: VMOVS
-/* 3006 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3028
-/* 3011 */    MCD_OPC_CheckPredicate, 27, 76, 5, 0, // Skip to: 4372
-/* 3016 */    MCD_OPC_CheckField, 4, 1, 0, 69, 5, 0, // Skip to: 4372
-/* 3023 */    MCD_OPC_Decode, 222, 14, 218, 2, // Opcode: VNEGS
-/* 3028 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3050
-/* 3033 */    MCD_OPC_CheckPredicate, 67, 54, 5, 0, // Skip to: 4372
-/* 3038 */    MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 4372
-/* 3045 */    MCD_OPC_Decode, 169, 9, 218, 2, // Opcode: VCVTBHS
-/* 3050 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3072
-/* 3055 */    MCD_OPC_CheckPredicate, 67, 32, 5, 0, // Skip to: 4372
-/* 3060 */    MCD_OPC_CheckField, 4, 1, 0, 25, 5, 0, // Skip to: 4372
-/* 3067 */    MCD_OPC_Decode, 170, 9, 218, 2, // Opcode: VCVTBSH
-/* 3072 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3094
-/* 3077 */    MCD_OPC_CheckPredicate, 27, 10, 5, 0, // Skip to: 4372
-/* 3082 */    MCD_OPC_CheckField, 4, 1, 0, 3, 5, 0, // Skip to: 4372
-/* 3089 */    MCD_OPC_Decode, 147, 9, 218, 2, // Opcode: VCMPS
-/* 3094 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3116
-/* 3099 */    MCD_OPC_CheckPredicate, 27, 244, 4, 0, // Skip to: 4372
-/* 3104 */    MCD_OPC_CheckField, 0, 6, 0, 237, 4, 0, // Skip to: 4372
-/* 3111 */    MCD_OPC_Decode, 150, 9, 223, 2, // Opcode: VCMPZS
-/* 3116 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3138
-/* 3121 */    MCD_OPC_CheckPredicate, 66, 222, 4, 0, // Skip to: 4372
-/* 3126 */    MCD_OPC_CheckField, 4, 1, 0, 215, 4, 0, // Skip to: 4372
-/* 3133 */    MCD_OPC_Decode, 149, 17, 218, 2, // Opcode: VRINTRS
-/* 3138 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3160
-/* 3143 */    MCD_OPC_CheckPredicate, 66, 200, 4, 0, // Skip to: 4372
-/* 3148 */    MCD_OPC_CheckField, 4, 1, 0, 193, 4, 0, // Skip to: 4372
-/* 3155 */    MCD_OPC_Decode, 156, 17, 218, 2, // Opcode: VRINTXS
-/* 3160 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3182
-/* 3165 */    MCD_OPC_CheckPredicate, 27, 178, 4, 0, // Skip to: 4372
-/* 3170 */    MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 4372
-/* 3177 */    MCD_OPC_Decode, 168, 21, 218, 2, // Opcode: VUITOS
-/* 3182 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3204
-/* 3187 */    MCD_OPC_CheckPredicate, 27, 156, 4, 0, // Skip to: 4372
-/* 3192 */    MCD_OPC_CheckField, 4, 1, 0, 149, 4, 0, // Skip to: 4372
-/* 3199 */    MCD_OPC_Decode, 173, 18, 220, 2, // Opcode: VSHTOS
-/* 3204 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3226
-/* 3209 */    MCD_OPC_CheckPredicate, 27, 134, 4, 0, // Skip to: 4372
-/* 3214 */    MCD_OPC_CheckField, 4, 1, 0, 127, 4, 0, // Skip to: 4372
-/* 3221 */    MCD_OPC_Decode, 165, 21, 220, 2, // Opcode: VUHTOS
-/* 3226 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3248
-/* 3231 */    MCD_OPC_CheckPredicate, 27, 112, 4, 0, // Skip to: 4372
-/* 3236 */    MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 4372
-/* 3243 */    MCD_OPC_Decode, 140, 21, 218, 2, // Opcode: VTOUIRS
-/* 3248 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3270
-/* 3253 */    MCD_OPC_CheckPredicate, 27, 90, 4, 0, // Skip to: 4372
-/* 3258 */    MCD_OPC_CheckField, 4, 1, 0, 83, 4, 0, // Skip to: 4372
-/* 3265 */    MCD_OPC_Decode, 128, 21, 218, 2, // Opcode: VTOSIRS
-/* 3270 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3292
-/* 3275 */    MCD_OPC_CheckPredicate, 27, 68, 4, 0, // Skip to: 4372
-/* 3280 */    MCD_OPC_CheckField, 4, 1, 0, 61, 4, 0, // Skip to: 4372
-/* 3287 */    MCD_OPC_Decode, 253, 20, 220, 2, // Opcode: VTOSHS
-/* 3292 */    MCD_OPC_FilterValue, 15, 51, 4, 0, // Skip to: 4372
-/* 3297 */    MCD_OPC_CheckPredicate, 27, 46, 4, 0, // Skip to: 4372
-/* 3302 */    MCD_OPC_CheckField, 4, 1, 0, 39, 4, 0, // Skip to: 4372
-/* 3309 */    MCD_OPC_Decode, 137, 21, 220, 2, // Opcode: VTOUHS
-/* 3314 */    MCD_OPC_FilterValue, 43, 77, 1, 0, // Skip to: 3652
-/* 3319 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 3322 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3344
-/* 3327 */    MCD_OPC_CheckPredicate, 27, 16, 4, 0, // Skip to: 4372
-/* 3332 */    MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 4372
-/* 3339 */    MCD_OPC_Decode, 216, 7, 218, 2, // Opcode: VABSS
-/* 3344 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3366
-/* 3349 */    MCD_OPC_CheckPredicate, 27, 250, 3, 0, // Skip to: 4372
-/* 3354 */    MCD_OPC_CheckField, 4, 1, 0, 243, 3, 0, // Skip to: 4372
-/* 3361 */    MCD_OPC_Decode, 190, 18, 218, 2, // Opcode: VSQRTS
-/* 3366 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3388
-/* 3371 */    MCD_OPC_CheckPredicate, 67, 228, 3, 0, // Skip to: 4372
-/* 3376 */    MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 4372
-/* 3383 */    MCD_OPC_Decode, 217, 9, 218, 2, // Opcode: VCVTTHS
-/* 3388 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3410
-/* 3393 */    MCD_OPC_CheckPredicate, 67, 206, 3, 0, // Skip to: 4372
-/* 3398 */    MCD_OPC_CheckField, 4, 1, 0, 199, 3, 0, // Skip to: 4372
-/* 3405 */    MCD_OPC_Decode, 218, 9, 218, 2, // Opcode: VCVTTSH
-/* 3410 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3432
-/* 3415 */    MCD_OPC_CheckPredicate, 27, 184, 3, 0, // Skip to: 4372
-/* 3420 */    MCD_OPC_CheckField, 4, 1, 0, 177, 3, 0, // Skip to: 4372
-/* 3427 */    MCD_OPC_Decode, 142, 9, 218, 2, // Opcode: VCMPES
-/* 3432 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3454
-/* 3437 */    MCD_OPC_CheckPredicate, 27, 162, 3, 0, // Skip to: 4372
-/* 3442 */    MCD_OPC_CheckField, 0, 6, 0, 155, 3, 0, // Skip to: 4372
-/* 3449 */    MCD_OPC_Decode, 145, 9, 223, 2, // Opcode: VCMPEZS
-/* 3454 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3476
-/* 3459 */    MCD_OPC_CheckPredicate, 66, 140, 3, 0, // Skip to: 4372
-/* 3464 */    MCD_OPC_CheckField, 4, 1, 0, 133, 3, 0, // Skip to: 4372
-/* 3471 */    MCD_OPC_Decode, 163, 17, 218, 2, // Opcode: VRINTZS
-/* 3476 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3498
-/* 3481 */    MCD_OPC_CheckPredicate, 61, 118, 3, 0, // Skip to: 4372
-/* 3486 */    MCD_OPC_CheckField, 4, 1, 0, 111, 3, 0, // Skip to: 4372
-/* 3493 */    MCD_OPC_Decode, 171, 9, 224, 2, // Opcode: VCVTDS
-/* 3498 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3520
-/* 3503 */    MCD_OPC_CheckPredicate, 27, 96, 3, 0, // Skip to: 4372
-/* 3508 */    MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 4372
-/* 3515 */    MCD_OPC_Decode, 176, 18, 218, 2, // Opcode: VSITOS
-/* 3520 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3542
-/* 3525 */    MCD_OPC_CheckPredicate, 27, 74, 3, 0, // Skip to: 4372
-/* 3530 */    MCD_OPC_CheckField, 4, 1, 0, 67, 3, 0, // Skip to: 4372
-/* 3537 */    MCD_OPC_Decode, 187, 18, 220, 2, // Opcode: VSLTOS
-/* 3542 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3564
-/* 3547 */    MCD_OPC_CheckPredicate, 27, 52, 3, 0, // Skip to: 4372
-/* 3552 */    MCD_OPC_CheckField, 4, 1, 0, 45, 3, 0, // Skip to: 4372
-/* 3559 */    MCD_OPC_Decode, 171, 21, 220, 2, // Opcode: VULTOS
-/* 3564 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3586
-/* 3569 */    MCD_OPC_CheckPredicate, 27, 30, 3, 0, // Skip to: 4372
-/* 3574 */    MCD_OPC_CheckField, 4, 1, 0, 23, 3, 0, // Skip to: 4372
-/* 3581 */    MCD_OPC_Decode, 143, 21, 218, 2, // Opcode: VTOUIZS
-/* 3586 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3608
-/* 3591 */    MCD_OPC_CheckPredicate, 27, 8, 3, 0, // Skip to: 4372
-/* 3596 */    MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 4372
-/* 3603 */    MCD_OPC_Decode, 131, 21, 218, 2, // Opcode: VTOSIZS
-/* 3608 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3630
-/* 3613 */    MCD_OPC_CheckPredicate, 27, 242, 2, 0, // Skip to: 4372
-/* 3618 */    MCD_OPC_CheckField, 4, 1, 0, 235, 2, 0, // Skip to: 4372
-/* 3625 */    MCD_OPC_Decode, 134, 21, 220, 2, // Opcode: VTOSLS
-/* 3630 */    MCD_OPC_FilterValue, 15, 225, 2, 0, // Skip to: 4372
-/* 3635 */    MCD_OPC_CheckPredicate, 27, 220, 2, 0, // Skip to: 4372
-/* 3640 */    MCD_OPC_CheckField, 4, 1, 0, 213, 2, 0, // Skip to: 4372
-/* 3647 */    MCD_OPC_Decode, 146, 21, 220, 2, // Opcode: VTOULS
-/* 3652 */    MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 3674
-/* 3657 */    MCD_OPC_CheckPredicate, 68, 198, 2, 0, // Skip to: 4372
-/* 3662 */    MCD_OPC_CheckField, 4, 2, 0, 191, 2, 0, // Skip to: 4372
-/* 3669 */    MCD_OPC_Decode, 208, 4, 225, 2, // Opcode: FCONSTD
-/* 3674 */    MCD_OPC_FilterValue, 45, 77, 1, 0, // Skip to: 4012
-/* 3679 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 3682 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3704
-/* 3687 */    MCD_OPC_CheckPredicate, 61, 168, 2, 0, // Skip to: 4372
-/* 3692 */    MCD_OPC_CheckField, 4, 1, 0, 161, 2, 0, // Skip to: 4372
-/* 3699 */    MCD_OPC_Decode, 136, 14, 226, 2, // Opcode: VMOVD
-/* 3704 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3726
-/* 3709 */    MCD_OPC_CheckPredicate, 61, 146, 2, 0, // Skip to: 4372
-/* 3714 */    MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 4372
-/* 3721 */    MCD_OPC_Decode, 220, 14, 226, 2, // Opcode: VNEGD
-/* 3726 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3748
-/* 3731 */    MCD_OPC_CheckPredicate, 69, 124, 2, 0, // Skip to: 4372
-/* 3736 */    MCD_OPC_CheckField, 4, 1, 0, 117, 2, 0, // Skip to: 4372
-/* 3743 */    MCD_OPC_Decode, 168, 9, 224, 2, // Opcode: VCVTBHD
-/* 3748 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3770
-/* 3753 */    MCD_OPC_CheckPredicate, 69, 102, 2, 0, // Skip to: 4372
-/* 3758 */    MCD_OPC_CheckField, 4, 1, 0, 95, 2, 0, // Skip to: 4372
-/* 3765 */    MCD_OPC_Decode, 167, 9, 227, 2, // Opcode: VCVTBDH
-/* 3770 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 3792
-/* 3775 */    MCD_OPC_CheckPredicate, 61, 80, 2, 0, // Skip to: 4372
-/* 3780 */    MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 4372
-/* 3787 */    MCD_OPC_Decode, 139, 9, 226, 2, // Opcode: VCMPD
-/* 3792 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 3814
-/* 3797 */    MCD_OPC_CheckPredicate, 61, 58, 2, 0, // Skip to: 4372
-/* 3802 */    MCD_OPC_CheckField, 0, 6, 0, 51, 2, 0, // Skip to: 4372
-/* 3809 */    MCD_OPC_Decode, 148, 9, 228, 2, // Opcode: VCMPZD
-/* 3814 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 3836
-/* 3819 */    MCD_OPC_CheckPredicate, 69, 36, 2, 0, // Skip to: 4372
-/* 3824 */    MCD_OPC_CheckField, 4, 1, 0, 29, 2, 0, // Skip to: 4372
-/* 3831 */    MCD_OPC_Decode, 147, 17, 226, 2, // Opcode: VRINTRD
-/* 3836 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 3858
-/* 3841 */    MCD_OPC_CheckPredicate, 69, 14, 2, 0, // Skip to: 4372
-/* 3846 */    MCD_OPC_CheckField, 4, 1, 0, 7, 2, 0, // Skip to: 4372
-/* 3853 */    MCD_OPC_Decode, 150, 17, 226, 2, // Opcode: VRINTXD
-/* 3858 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 3880
-/* 3863 */    MCD_OPC_CheckPredicate, 61, 248, 1, 0, // Skip to: 4372
-/* 3868 */    MCD_OPC_CheckField, 4, 1, 0, 241, 1, 0, // Skip to: 4372
-/* 3875 */    MCD_OPC_Decode, 166, 21, 224, 2, // Opcode: VUITOD
-/* 3880 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 3902
-/* 3885 */    MCD_OPC_CheckPredicate, 61, 226, 1, 0, // Skip to: 4372
-/* 3890 */    MCD_OPC_CheckField, 4, 1, 0, 219, 1, 0, // Skip to: 4372
-/* 3897 */    MCD_OPC_Decode, 171, 18, 229, 2, // Opcode: VSHTOD
-/* 3902 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 3924
-/* 3907 */    MCD_OPC_CheckPredicate, 61, 204, 1, 0, // Skip to: 4372
-/* 3912 */    MCD_OPC_CheckField, 4, 1, 0, 197, 1, 0, // Skip to: 4372
-/* 3919 */    MCD_OPC_Decode, 163, 21, 229, 2, // Opcode: VUHTOD
-/* 3924 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 3946
-/* 3929 */    MCD_OPC_CheckPredicate, 61, 182, 1, 0, // Skip to: 4372
-/* 3934 */    MCD_OPC_CheckField, 4, 1, 0, 175, 1, 0, // Skip to: 4372
-/* 3941 */    MCD_OPC_Decode, 138, 21, 227, 2, // Opcode: VTOUIRD
-/* 3946 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 3968
-/* 3951 */    MCD_OPC_CheckPredicate, 61, 160, 1, 0, // Skip to: 4372
-/* 3956 */    MCD_OPC_CheckField, 4, 1, 0, 153, 1, 0, // Skip to: 4372
-/* 3963 */    MCD_OPC_Decode, 254, 20, 227, 2, // Opcode: VTOSIRD
-/* 3968 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 3990
-/* 3973 */    MCD_OPC_CheckPredicate, 61, 138, 1, 0, // Skip to: 4372
-/* 3978 */    MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 4372
-/* 3985 */    MCD_OPC_Decode, 251, 20, 229, 2, // Opcode: VTOSHD
-/* 3990 */    MCD_OPC_FilterValue, 15, 121, 1, 0, // Skip to: 4372
-/* 3995 */    MCD_OPC_CheckPredicate, 61, 116, 1, 0, // Skip to: 4372
-/* 4000 */    MCD_OPC_CheckField, 4, 1, 0, 109, 1, 0, // Skip to: 4372
-/* 4007 */    MCD_OPC_Decode, 135, 21, 229, 2, // Opcode: VTOUHD
-/* 4012 */    MCD_OPC_FilterValue, 47, 99, 1, 0, // Skip to: 4372
-/* 4017 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 4020 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4042
-/* 4025 */    MCD_OPC_CheckPredicate, 61, 86, 1, 0, // Skip to: 4372
-/* 4030 */    MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 4372
-/* 4037 */    MCD_OPC_Decode, 214, 7, 226, 2, // Opcode: VABSD
-/* 4042 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4064
-/* 4047 */    MCD_OPC_CheckPredicate, 61, 64, 1, 0, // Skip to: 4372
-/* 4052 */    MCD_OPC_CheckField, 4, 1, 0, 57, 1, 0, // Skip to: 4372
-/* 4059 */    MCD_OPC_Decode, 188, 18, 226, 2, // Opcode: VSQRTD
-/* 4064 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4086
-/* 4069 */    MCD_OPC_CheckPredicate, 69, 42, 1, 0, // Skip to: 4372
-/* 4074 */    MCD_OPC_CheckField, 4, 1, 0, 35, 1, 0, // Skip to: 4372
-/* 4081 */    MCD_OPC_Decode, 216, 9, 224, 2, // Opcode: VCVTTHD
-/* 4086 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4108
-/* 4091 */    MCD_OPC_CheckPredicate, 69, 20, 1, 0, // Skip to: 4372
-/* 4096 */    MCD_OPC_CheckField, 4, 1, 0, 13, 1, 0, // Skip to: 4372
-/* 4103 */    MCD_OPC_Decode, 215, 9, 227, 2, // Opcode: VCVTTDH
-/* 4108 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4130
-/* 4113 */    MCD_OPC_CheckPredicate, 61, 254, 0, 0, // Skip to: 4372
-/* 4118 */    MCD_OPC_CheckField, 4, 1, 0, 247, 0, 0, // Skip to: 4372
-/* 4125 */    MCD_OPC_Decode, 140, 9, 226, 2, // Opcode: VCMPED
-/* 4130 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4152
-/* 4135 */    MCD_OPC_CheckPredicate, 61, 232, 0, 0, // Skip to: 4372
-/* 4140 */    MCD_OPC_CheckField, 0, 6, 0, 225, 0, 0, // Skip to: 4372
-/* 4147 */    MCD_OPC_Decode, 143, 9, 228, 2, // Opcode: VCMPEZD
-/* 4152 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4174
-/* 4157 */    MCD_OPC_CheckPredicate, 69, 210, 0, 0, // Skip to: 4372
-/* 4162 */    MCD_OPC_CheckField, 4, 1, 0, 203, 0, 0, // Skip to: 4372
-/* 4169 */    MCD_OPC_Decode, 157, 17, 226, 2, // Opcode: VRINTZD
-/* 4174 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4196
-/* 4179 */    MCD_OPC_CheckPredicate, 61, 188, 0, 0, // Skip to: 4372
-/* 4184 */    MCD_OPC_CheckField, 4, 1, 0, 181, 0, 0, // Skip to: 4372
-/* 4191 */    MCD_OPC_Decode, 214, 9, 227, 2, // Opcode: VCVTSD
-/* 4196 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4218
-/* 4201 */    MCD_OPC_CheckPredicate, 61, 166, 0, 0, // Skip to: 4372
-/* 4206 */    MCD_OPC_CheckField, 4, 1, 0, 159, 0, 0, // Skip to: 4372
-/* 4213 */    MCD_OPC_Decode, 174, 18, 224, 2, // Opcode: VSITOD
-/* 4218 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4240
-/* 4223 */    MCD_OPC_CheckPredicate, 70, 144, 0, 0, // Skip to: 4372
-/* 4228 */    MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 4372
-/* 4235 */    MCD_OPC_Decode, 199, 10, 227, 2, // Opcode: VJCVT
-/* 4240 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4262
-/* 4245 */    MCD_OPC_CheckPredicate, 61, 122, 0, 0, // Skip to: 4372
-/* 4250 */    MCD_OPC_CheckField, 4, 1, 0, 115, 0, 0, // Skip to: 4372
-/* 4257 */    MCD_OPC_Decode, 185, 18, 229, 2, // Opcode: VSLTOD
-/* 4262 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4284
-/* 4267 */    MCD_OPC_CheckPredicate, 61, 100, 0, 0, // Skip to: 4372
-/* 4272 */    MCD_OPC_CheckField, 4, 1, 0, 93, 0, 0, // Skip to: 4372
-/* 4279 */    MCD_OPC_Decode, 169, 21, 229, 2, // Opcode: VULTOD
-/* 4284 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4306
-/* 4289 */    MCD_OPC_CheckPredicate, 61, 78, 0, 0, // Skip to: 4372
-/* 4294 */    MCD_OPC_CheckField, 4, 1, 0, 71, 0, 0, // Skip to: 4372
-/* 4301 */    MCD_OPC_Decode, 141, 21, 227, 2, // Opcode: VTOUIZD
-/* 4306 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4328
-/* 4311 */    MCD_OPC_CheckPredicate, 61, 56, 0, 0, // Skip to: 4372
-/* 4316 */    MCD_OPC_CheckField, 4, 1, 0, 49, 0, 0, // Skip to: 4372
-/* 4323 */    MCD_OPC_Decode, 129, 21, 227, 2, // Opcode: VTOSIZD
-/* 4328 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4350
-/* 4333 */    MCD_OPC_CheckPredicate, 61, 34, 0, 0, // Skip to: 4372
-/* 4338 */    MCD_OPC_CheckField, 4, 1, 0, 27, 0, 0, // Skip to: 4372
-/* 4345 */    MCD_OPC_Decode, 132, 21, 229, 2, // Opcode: VTOSLD
-/* 4350 */    MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 4372
-/* 4355 */    MCD_OPC_CheckPredicate, 61, 12, 0, 0, // Skip to: 4372
-/* 4360 */    MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 4372
-/* 4367 */    MCD_OPC_Decode, 144, 21, 229, 2, // Opcode: VTOULD
-/* 4372 */    MCD_OPC_Fail,
+/* 154 */     MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 169
+/* 159 */     MCD_OPC_CheckPredicate, 76, 87, 21, 0, // Skip to: 5627
+/* 164 */     MCD_OPC_Decode, 247, 21, 212, 3, // Opcode: VLDRH
+/* 169 */     MCD_OPC_FilterValue, 14, 77, 21, 0, // Skip to: 5627
+/* 174 */     MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 177 */     MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 261
+/* 182 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 185 */     MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 223
+/* 190 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 193 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 208
+/* 198 */     MCD_OPC_CheckPredicate, 77, 48, 21, 0, // Skip to: 5627
+/* 203 */     MCD_OPC_Decode, 219, 23, 213, 3, // Opcode: VNMLSH
+/* 208 */     MCD_OPC_FilterValue, 1, 38, 21, 0, // Skip to: 5627
+/* 213 */     MCD_OPC_CheckPredicate, 77, 33, 21, 0, // Skip to: 5627
+/* 218 */     MCD_OPC_Decode, 224, 18, 213, 3, // Opcode: VFNMSH
+/* 223 */     MCD_OPC_FilterValue, 1, 23, 21, 0, // Skip to: 5627
+/* 228 */     MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 231 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 246
+/* 236 */     MCD_OPC_CheckPredicate, 77, 10, 21, 0, // Skip to: 5627
+/* 241 */     MCD_OPC_Decode, 216, 23, 213, 3, // Opcode: VNMLAH
+/* 246 */     MCD_OPC_FilterValue, 1, 0, 21, 0, // Skip to: 5627
+/* 251 */     MCD_OPC_CheckPredicate, 77, 251, 20, 0, // Skip to: 5627
+/* 256 */     MCD_OPC_Decode, 221, 18, 213, 3, // Opcode: VFNMAH
+/* 261 */     MCD_OPC_FilterValue, 1, 241, 20, 0, // Skip to: 5627
+/* 266 */     MCD_OPC_CheckPredicate, 76, 236, 20, 0, // Skip to: 5627
+/* 271 */     MCD_OPC_CheckField, 22, 2, 0, 229, 20, 0, // Skip to: 5627
+/* 278 */     MCD_OPC_CheckField, 5, 2, 0, 222, 20, 0, // Skip to: 5627
+/* 285 */     MCD_OPC_CheckField, 0, 4, 0, 215, 20, 0, // Skip to: 5627
+/* 292 */     MCD_OPC_Decode, 249, 22, 216, 3, // Opcode: VMOVRH
+/* 297 */     MCD_OPC_FilterValue, 2, 107, 0, 0, // Skip to: 409
+/* 302 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 305 */     MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 357
+/* 310 */     MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 313 */     MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 335
+/* 318 */     MCD_OPC_CheckPredicate, 77, 184, 20, 0, // Skip to: 5627
+/* 323 */     MCD_OPC_CheckField, 4, 1, 0, 177, 20, 0, // Skip to: 5627
+/* 330 */     MCD_OPC_Decode, 162, 23, 214, 3, // Opcode: VMULH
+/* 335 */     MCD_OPC_FilterValue, 29, 167, 20, 0, // Skip to: 5627
+/* 340 */     MCD_OPC_CheckPredicate, 77, 162, 20, 0, // Skip to: 5627
+/* 345 */     MCD_OPC_CheckField, 4, 1, 0, 155, 20, 0, // Skip to: 5627
+/* 352 */     MCD_OPC_Decode, 199, 18, 213, 3, // Opcode: VFMAH
+/* 357 */     MCD_OPC_FilterValue, 1, 145, 20, 0, // Skip to: 5627
+/* 362 */     MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 365 */     MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 387
+/* 370 */     MCD_OPC_CheckPredicate, 77, 132, 20, 0, // Skip to: 5627
+/* 375 */     MCD_OPC_CheckField, 4, 1, 0, 125, 20, 0, // Skip to: 5627
+/* 382 */     MCD_OPC_Decode, 222, 23, 214, 3, // Opcode: VNMULH
+/* 387 */     MCD_OPC_FilterValue, 29, 115, 20, 0, // Skip to: 5627
+/* 392 */     MCD_OPC_CheckPredicate, 77, 110, 20, 0, // Skip to: 5627
+/* 397 */     MCD_OPC_CheckField, 4, 1, 0, 103, 20, 0, // Skip to: 5627
+/* 404 */     MCD_OPC_Decode, 210, 18, 213, 3, // Opcode: VFMSH
+/* 409 */     MCD_OPC_FilterValue, 3, 93, 20, 0, // Skip to: 5627
+/* 414 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 417 */     MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 476
+/* 422 */     MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 425 */     MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 447
+/* 430 */     MCD_OPC_CheckPredicate, 77, 72, 20, 0, // Skip to: 5627
+/* 435 */     MCD_OPC_CheckField, 4, 1, 0, 65, 20, 0, // Skip to: 5627
+/* 442 */     MCD_OPC_Decode, 151, 16, 214, 3, // Opcode: VADDH
+/* 447 */     MCD_OPC_FilterValue, 29, 55, 20, 0, // Skip to: 5627
+/* 452 */     MCD_OPC_CheckPredicate, 77, 50, 20, 0, // Skip to: 5627
+/* 457 */     MCD_OPC_CheckField, 7, 1, 0, 43, 20, 0, // Skip to: 5627
+/* 464 */     MCD_OPC_CheckField, 4, 2, 0, 36, 20, 0, // Skip to: 5627
+/* 471 */     MCD_OPC_Decode, 170, 6, 217, 3, // Opcode: FCONSTH
+/* 476 */     MCD_OPC_FilterValue, 1, 26, 20, 0, // Skip to: 5627
+/* 481 */     MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 484 */     MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 506
+/* 489 */     MCD_OPC_CheckPredicate, 77, 13, 20, 0, // Skip to: 5627
+/* 494 */     MCD_OPC_CheckField, 4, 1, 0, 6, 20, 0, // Skip to: 5627
+/* 501 */     MCD_OPC_Decode, 231, 29, 214, 3, // Opcode: VSUBH
+/* 506 */     MCD_OPC_FilterValue, 29, 252, 19, 0, // Skip to: 5627
+/* 511 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 514 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 543
+/* 519 */     MCD_OPC_CheckPredicate, 77, 239, 19, 0, // Skip to: 5627
+/* 524 */     MCD_OPC_CheckField, 7, 1, 1, 232, 19, 0, // Skip to: 5627
+/* 531 */     MCD_OPC_CheckField, 4, 1, 0, 225, 19, 0, // Skip to: 5627
+/* 538 */     MCD_OPC_Decode, 130, 16, 218, 3, // Opcode: VABSH
+/* 543 */     MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 595
+/* 548 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 551 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 573
+/* 556 */     MCD_OPC_CheckPredicate, 77, 202, 19, 0, // Skip to: 5627
+/* 561 */     MCD_OPC_CheckField, 4, 1, 0, 195, 19, 0, // Skip to: 5627
+/* 568 */     MCD_OPC_Decode, 203, 23, 218, 3, // Opcode: VNEGH
+/* 573 */     MCD_OPC_FilterValue, 1, 185, 19, 0, // Skip to: 5627
+/* 578 */     MCD_OPC_CheckPredicate, 77, 180, 19, 0, // Skip to: 5627
+/* 583 */     MCD_OPC_CheckField, 4, 1, 0, 173, 19, 0, // Skip to: 5627
+/* 590 */     MCD_OPC_Decode, 174, 27, 218, 3, // Opcode: VSQRTH
+/* 595 */     MCD_OPC_FilterValue, 4, 47, 0, 0, // Skip to: 647
+/* 600 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 603 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 625
+/* 608 */     MCD_OPC_CheckPredicate, 77, 150, 19, 0, // Skip to: 5627
+/* 613 */     MCD_OPC_CheckField, 4, 1, 0, 143, 19, 0, // Skip to: 5627
+/* 620 */     MCD_OPC_Decode, 195, 17, 218, 3, // Opcode: VCMPH
+/* 625 */     MCD_OPC_FilterValue, 1, 133, 19, 0, // Skip to: 5627
+/* 630 */     MCD_OPC_CheckPredicate, 77, 128, 19, 0, // Skip to: 5627
+/* 635 */     MCD_OPC_CheckField, 4, 1, 0, 121, 19, 0, // Skip to: 5627
+/* 642 */     MCD_OPC_Decode, 190, 17, 218, 3, // Opcode: VCMPEH
+/* 647 */     MCD_OPC_FilterValue, 5, 47, 0, 0, // Skip to: 699
+/* 652 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 655 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 677
+/* 660 */     MCD_OPC_CheckPredicate, 77, 98, 19, 0, // Skip to: 5627
+/* 665 */     MCD_OPC_CheckField, 0, 6, 0, 91, 19, 0, // Skip to: 5627
+/* 672 */     MCD_OPC_Decode, 198, 17, 219, 3, // Opcode: VCMPZH
+/* 677 */     MCD_OPC_FilterValue, 1, 81, 19, 0, // Skip to: 5627
+/* 682 */     MCD_OPC_CheckPredicate, 77, 76, 19, 0, // Skip to: 5627
+/* 687 */     MCD_OPC_CheckField, 0, 6, 0, 69, 19, 0, // Skip to: 5627
+/* 694 */     MCD_OPC_Decode, 193, 17, 219, 3, // Opcode: VCMPEZH
+/* 699 */     MCD_OPC_FilterValue, 6, 47, 0, 0, // Skip to: 751
+/* 704 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 707 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 729
+/* 712 */     MCD_OPC_CheckPredicate, 77, 46, 19, 0, // Skip to: 5627
+/* 717 */     MCD_OPC_CheckField, 4, 1, 0, 39, 19, 0, // Skip to: 5627
+/* 724 */     MCD_OPC_Decode, 130, 26, 218, 3, // Opcode: VRINTRH
+/* 729 */     MCD_OPC_FilterValue, 1, 29, 19, 0, // Skip to: 5627
+/* 734 */     MCD_OPC_CheckPredicate, 77, 24, 19, 0, // Skip to: 5627
+/* 739 */     MCD_OPC_CheckField, 4, 1, 0, 17, 19, 0, // Skip to: 5627
+/* 746 */     MCD_OPC_Decode, 140, 26, 218, 3, // Opcode: VRINTZH
+/* 751 */     MCD_OPC_FilterValue, 7, 24, 0, 0, // Skip to: 780
+/* 756 */     MCD_OPC_CheckPredicate, 77, 2, 19, 0, // Skip to: 5627
+/* 761 */     MCD_OPC_CheckField, 7, 1, 0, 251, 18, 0, // Skip to: 5627
+/* 768 */     MCD_OPC_CheckField, 4, 1, 0, 244, 18, 0, // Skip to: 5627
+/* 775 */     MCD_OPC_Decode, 133, 26, 218, 3, // Opcode: VRINTXH
+/* 780 */     MCD_OPC_FilterValue, 8, 47, 0, 0, // Skip to: 832
+/* 785 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 788 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 810
+/* 793 */     MCD_OPC_CheckPredicate, 77, 221, 18, 0, // Skip to: 5627
+/* 798 */     MCD_OPC_CheckField, 4, 1, 0, 214, 18, 0, // Skip to: 5627
+/* 805 */     MCD_OPC_Decode, 192, 30, 220, 3, // Opcode: VUITOH
+/* 810 */     MCD_OPC_FilterValue, 1, 204, 18, 0, // Skip to: 5627
+/* 815 */     MCD_OPC_CheckPredicate, 77, 199, 18, 0, // Skip to: 5627
+/* 820 */     MCD_OPC_CheckField, 4, 1, 0, 192, 18, 0, // Skip to: 5627
+/* 827 */     MCD_OPC_Decode, 159, 27, 220, 3, // Opcode: VSITOH
+/* 832 */     MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 884
+/* 837 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 840 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 862
+/* 845 */     MCD_OPC_CheckPredicate, 77, 169, 18, 0, // Skip to: 5627
+/* 850 */     MCD_OPC_CheckField, 4, 1, 0, 162, 18, 0, // Skip to: 5627
+/* 857 */     MCD_OPC_Decode, 156, 27, 221, 3, // Opcode: VSHTOH
+/* 862 */     MCD_OPC_FilterValue, 1, 152, 18, 0, // Skip to: 5627
+/* 867 */     MCD_OPC_CheckPredicate, 77, 147, 18, 0, // Skip to: 5627
+/* 872 */     MCD_OPC_CheckField, 4, 1, 0, 140, 18, 0, // Skip to: 5627
+/* 879 */     MCD_OPC_Decode, 170, 27, 221, 3, // Opcode: VSLTOH
+/* 884 */     MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 936
+/* 889 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 892 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 914
+/* 897 */     MCD_OPC_CheckPredicate, 77, 117, 18, 0, // Skip to: 5627
+/* 902 */     MCD_OPC_CheckField, 4, 1, 0, 110, 18, 0, // Skip to: 5627
+/* 909 */     MCD_OPC_Decode, 189, 30, 221, 3, // Opcode: VUHTOH
+/* 914 */     MCD_OPC_FilterValue, 1, 100, 18, 0, // Skip to: 5627
+/* 919 */     MCD_OPC_CheckPredicate, 77, 95, 18, 0, // Skip to: 5627
+/* 924 */     MCD_OPC_CheckField, 4, 1, 0, 88, 18, 0, // Skip to: 5627
+/* 931 */     MCD_OPC_Decode, 195, 30, 221, 3, // Opcode: VULTOH
+/* 936 */     MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 988
+/* 941 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 944 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 966
+/* 949 */     MCD_OPC_CheckPredicate, 77, 65, 18, 0, // Skip to: 5627
+/* 954 */     MCD_OPC_CheckField, 4, 1, 0, 58, 18, 0, // Skip to: 5627
+/* 961 */     MCD_OPC_Decode, 164, 30, 222, 3, // Opcode: VTOUIRH
+/* 966 */     MCD_OPC_FilterValue, 1, 48, 18, 0, // Skip to: 5627
+/* 971 */     MCD_OPC_CheckPredicate, 77, 43, 18, 0, // Skip to: 5627
+/* 976 */     MCD_OPC_CheckField, 4, 1, 0, 36, 18, 0, // Skip to: 5627
+/* 983 */     MCD_OPC_Decode, 167, 30, 223, 3, // Opcode: VTOUIZH
+/* 988 */     MCD_OPC_FilterValue, 13, 47, 0, 0, // Skip to: 1040
+/* 993 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 996 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1018
+/* 1001 */    MCD_OPC_CheckPredicate, 77, 13, 18, 0, // Skip to: 5627
+/* 1006 */    MCD_OPC_CheckField, 4, 1, 0, 6, 18, 0, // Skip to: 5627
+/* 1013 */    MCD_OPC_Decode, 152, 30, 222, 3, // Opcode: VTOSIRH
+/* 1018 */    MCD_OPC_FilterValue, 1, 252, 17, 0, // Skip to: 5627
+/* 1023 */    MCD_OPC_CheckPredicate, 77, 247, 17, 0, // Skip to: 5627
+/* 1028 */    MCD_OPC_CheckField, 4, 1, 0, 240, 17, 0, // Skip to: 5627
+/* 1035 */    MCD_OPC_Decode, 155, 30, 223, 3, // Opcode: VTOSIZH
+/* 1040 */    MCD_OPC_FilterValue, 14, 47, 0, 0, // Skip to: 1092
+/* 1045 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1048 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1070
+/* 1053 */    MCD_OPC_CheckPredicate, 77, 217, 17, 0, // Skip to: 5627
+/* 1058 */    MCD_OPC_CheckField, 4, 1, 0, 210, 17, 0, // Skip to: 5627
+/* 1065 */    MCD_OPC_Decode, 149, 30, 221, 3, // Opcode: VTOSHH
+/* 1070 */    MCD_OPC_FilterValue, 1, 200, 17, 0, // Skip to: 5627
+/* 1075 */    MCD_OPC_CheckPredicate, 77, 195, 17, 0, // Skip to: 5627
+/* 1080 */    MCD_OPC_CheckField, 4, 1, 0, 188, 17, 0, // Skip to: 5627
+/* 1087 */    MCD_OPC_Decode, 158, 30, 221, 3, // Opcode: VTOSLH
+/* 1092 */    MCD_OPC_FilterValue, 15, 178, 17, 0, // Skip to: 5627
+/* 1097 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1100 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1122
+/* 1105 */    MCD_OPC_CheckPredicate, 77, 165, 17, 0, // Skip to: 5627
+/* 1110 */    MCD_OPC_CheckField, 4, 1, 0, 158, 17, 0, // Skip to: 5627
+/* 1117 */    MCD_OPC_Decode, 161, 30, 221, 3, // Opcode: VTOUHH
+/* 1122 */    MCD_OPC_FilterValue, 1, 148, 17, 0, // Skip to: 5627
+/* 1127 */    MCD_OPC_CheckPredicate, 77, 143, 17, 0, // Skip to: 5627
+/* 1132 */    MCD_OPC_CheckField, 4, 1, 0, 136, 17, 0, // Skip to: 5627
+/* 1139 */    MCD_OPC_Decode, 170, 30, 221, 3, // Opcode: VTOULH
+/* 1144 */    MCD_OPC_FilterValue, 10, 105, 7, 0, // Skip to: 3046
+/* 1149 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 1152 */    MCD_OPC_FilterValue, 0, 189, 0, 0, // Skip to: 1346
+/* 1157 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 1160 */    MCD_OPC_FilterValue, 12, 54, 0, 0, // Skip to: 1219
+/* 1165 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1168 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1204
+/* 1173 */    MCD_OPC_CheckPredicate, 34, 97, 17, 0, // Skip to: 5627
+/* 1178 */    MCD_OPC_CheckField, 22, 1, 1, 90, 17, 0, // Skip to: 5627
+/* 1185 */    MCD_OPC_CheckField, 6, 2, 0, 83, 17, 0, // Skip to: 5627
+/* 1192 */    MCD_OPC_CheckField, 4, 1, 1, 76, 17, 0, // Skip to: 5627
+/* 1199 */    MCD_OPC_Decode, 255, 22, 224, 3, // Opcode: VMOVSRR
+/* 1204 */    MCD_OPC_FilterValue, 1, 66, 17, 0, // Skip to: 5627
+/* 1209 */    MCD_OPC_CheckPredicate, 34, 61, 17, 0, // Skip to: 5627
+/* 1214 */    MCD_OPC_Decode, 207, 29, 225, 3, // Opcode: VSTMSIA
+/* 1219 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1234
+/* 1224 */    MCD_OPC_CheckPredicate, 34, 46, 17, 0, // Skip to: 5627
+/* 1229 */    MCD_OPC_Decode, 211, 29, 226, 3, // Opcode: VSTRS
+/* 1234 */    MCD_OPC_FilterValue, 14, 36, 17, 0, // Skip to: 5627
+/* 1239 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1242 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1310
+/* 1247 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1250 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1288
+/* 1255 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1258 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1273
+/* 1263 */    MCD_OPC_CheckPredicate, 33, 7, 17, 0, // Skip to: 5627
+/* 1268 */    MCD_OPC_Decode, 185, 22, 227, 3, // Opcode: VMLAS
+/* 1273 */    MCD_OPC_FilterValue, 1, 253, 16, 0, // Skip to: 5627
+/* 1278 */    MCD_OPC_CheckPredicate, 33, 248, 16, 0, // Skip to: 5627
+/* 1283 */    MCD_OPC_Decode, 176, 18, 228, 3, // Opcode: VDIVS
+/* 1288 */    MCD_OPC_FilterValue, 1, 238, 16, 0, // Skip to: 5627
+/* 1293 */    MCD_OPC_CheckPredicate, 33, 233, 16, 0, // Skip to: 5627
+/* 1298 */    MCD_OPC_CheckField, 23, 1, 0, 226, 16, 0, // Skip to: 5627
+/* 1305 */    MCD_OPC_Decode, 216, 22, 227, 3, // Opcode: VMLSS
+/* 1310 */    MCD_OPC_FilterValue, 1, 216, 16, 0, // Skip to: 5627
+/* 1315 */    MCD_OPC_CheckPredicate, 34, 211, 16, 0, // Skip to: 5627
+/* 1320 */    MCD_OPC_CheckField, 22, 2, 0, 204, 16, 0, // Skip to: 5627
+/* 1327 */    MCD_OPC_CheckField, 5, 2, 0, 197, 16, 0, // Skip to: 5627
+/* 1334 */    MCD_OPC_CheckField, 0, 4, 0, 190, 16, 0, // Skip to: 5627
+/* 1341 */    MCD_OPC_Decode, 254, 22, 229, 3, // Opcode: VMOVSR
+/* 1346 */    MCD_OPC_FilterValue, 1, 229, 0, 0, // Skip to: 1580
+/* 1351 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 1354 */    MCD_OPC_FilterValue, 12, 78, 0, 0, // Skip to: 1437
+/* 1359 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1362 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 1398
+/* 1367 */    MCD_OPC_CheckPredicate, 34, 159, 16, 0, // Skip to: 5627
+/* 1372 */    MCD_OPC_CheckField, 22, 1, 1, 152, 16, 0, // Skip to: 5627
+/* 1379 */    MCD_OPC_CheckField, 6, 2, 0, 145, 16, 0, // Skip to: 5627
+/* 1386 */    MCD_OPC_CheckField, 4, 1, 1, 138, 16, 0, // Skip to: 5627
+/* 1393 */    MCD_OPC_Decode, 251, 22, 230, 3, // Opcode: VMOVRRS
+/* 1398 */    MCD_OPC_FilterValue, 1, 128, 16, 0, // Skip to: 5627
+/* 1403 */    MCD_OPC_CheckPredicate, 78, 19, 0, 0, // Skip to: 1427
+/* 1408 */    MCD_OPC_CheckField, 28, 4, 14, 12, 0, 0, // Skip to: 1427
+/* 1415 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 1427
+/* 1422 */    MCD_OPC_Decode, 211, 26, 231, 3, // Opcode: VSCCLRMS
+/* 1427 */    MCD_OPC_CheckPredicate, 34, 99, 16, 0, // Skip to: 5627
+/* 1432 */    MCD_OPC_Decode, 244, 21, 225, 3, // Opcode: VLDMSIA
+/* 1437 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 1452
+/* 1442 */    MCD_OPC_CheckPredicate, 34, 84, 16, 0, // Skip to: 5627
+/* 1447 */    MCD_OPC_Decode, 248, 21, 226, 3, // Opcode: VLDRS
+/* 1452 */    MCD_OPC_FilterValue, 14, 74, 16, 0, // Skip to: 5627
+/* 1457 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1460 */    MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 1544
+/* 1465 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1468 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1506
+/* 1473 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1476 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1491
+/* 1481 */    MCD_OPC_CheckPredicate, 33, 45, 16, 0, // Skip to: 5627
+/* 1486 */    MCD_OPC_Decode, 220, 23, 227, 3, // Opcode: VNMLSS
+/* 1491 */    MCD_OPC_FilterValue, 1, 35, 16, 0, // Skip to: 5627
+/* 1496 */    MCD_OPC_CheckPredicate, 79, 30, 16, 0, // Skip to: 5627
+/* 1501 */    MCD_OPC_Decode, 225, 18, 227, 3, // Opcode: VFNMSS
+/* 1506 */    MCD_OPC_FilterValue, 1, 20, 16, 0, // Skip to: 5627
+/* 1511 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 1514 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1529
+/* 1519 */    MCD_OPC_CheckPredicate, 33, 7, 16, 0, // Skip to: 5627
+/* 1524 */    MCD_OPC_Decode, 217, 23, 227, 3, // Opcode: VNMLAS
+/* 1529 */    MCD_OPC_FilterValue, 1, 253, 15, 0, // Skip to: 5627
+/* 1534 */    MCD_OPC_CheckPredicate, 79, 248, 15, 0, // Skip to: 5627
+/* 1539 */    MCD_OPC_Decode, 222, 18, 227, 3, // Opcode: VFNMAS
+/* 1544 */    MCD_OPC_FilterValue, 1, 238, 15, 0, // Skip to: 5627
+/* 1549 */    MCD_OPC_CheckPredicate, 34, 233, 15, 0, // Skip to: 5627
+/* 1554 */    MCD_OPC_CheckField, 22, 2, 0, 226, 15, 0, // Skip to: 5627
+/* 1561 */    MCD_OPC_CheckField, 5, 2, 0, 219, 15, 0, // Skip to: 5627
+/* 1568 */    MCD_OPC_CheckField, 0, 4, 0, 212, 15, 0, // Skip to: 5627
+/* 1575 */    MCD_OPC_Decode, 252, 22, 232, 3, // Opcode: VMOVRS
+/* 1580 */    MCD_OPC_FilterValue, 2, 179, 1, 0, // Skip to: 2020
+/* 1585 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 1588 */    MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1624
+/* 1593 */    MCD_OPC_CheckPredicate, 80, 189, 15, 0, // Skip to: 5627
+/* 1598 */    MCD_OPC_CheckField, 22, 1, 0, 182, 15, 0, // Skip to: 5627
+/* 1605 */    MCD_OPC_CheckField, 12, 4, 0, 175, 15, 0, // Skip to: 5627
+/* 1612 */    MCD_OPC_CheckField, 0, 8, 0, 168, 15, 0, // Skip to: 5627
+/* 1619 */    MCD_OPC_Decode, 140, 22, 233, 3, // Opcode: VLSTM
+/* 1624 */    MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 1639
+/* 1629 */    MCD_OPC_CheckPredicate, 34, 153, 15, 0, // Skip to: 5627
+/* 1634 */    MCD_OPC_Decode, 208, 29, 234, 3, // Opcode: VSTMSIA_UPD
+/* 1639 */    MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 1654
+/* 1644 */    MCD_OPC_CheckPredicate, 34, 138, 15, 0, // Skip to: 5627
+/* 1649 */    MCD_OPC_Decode, 206, 29, 234, 3, // Opcode: VSTMSDB_UPD
+/* 1654 */    MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 1706
+/* 1659 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1662 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 1684
+/* 1667 */    MCD_OPC_CheckPredicate, 33, 115, 15, 0, // Skip to: 5627
+/* 1672 */    MCD_OPC_CheckField, 4, 1, 0, 108, 15, 0, // Skip to: 5627
+/* 1679 */    MCD_OPC_Decode, 175, 23, 228, 3, // Opcode: VMULS
+/* 1684 */    MCD_OPC_FilterValue, 1, 98, 15, 0, // Skip to: 5627
+/* 1689 */    MCD_OPC_CheckPredicate, 33, 93, 15, 0, // Skip to: 5627
+/* 1694 */    MCD_OPC_CheckField, 4, 1, 0, 86, 15, 0, // Skip to: 5627
+/* 1701 */    MCD_OPC_Decode, 223, 23, 228, 3, // Opcode: VNMULS
+/* 1706 */    MCD_OPC_FilterValue, 29, 76, 15, 0, // Skip to: 5627
+/* 1711 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 1714 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 1752
+/* 1719 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1722 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 1737
+/* 1727 */    MCD_OPC_CheckPredicate, 79, 55, 15, 0, // Skip to: 5627
+/* 1732 */    MCD_OPC_Decode, 204, 18, 227, 3, // Opcode: VFMAS
+/* 1737 */    MCD_OPC_FilterValue, 1, 45, 15, 0, // Skip to: 5627
+/* 1742 */    MCD_OPC_CheckPredicate, 79, 40, 15, 0, // Skip to: 5627
+/* 1747 */    MCD_OPC_Decode, 215, 18, 227, 3, // Opcode: VFMSS
+/* 1752 */    MCD_OPC_FilterValue, 1, 30, 15, 0, // Skip to: 5627
+/* 1757 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 1760 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 1786
+/* 1765 */    MCD_OPC_CheckPredicate, 33, 17, 15, 0, // Skip to: 5627
+/* 1770 */    MCD_OPC_CheckField, 22, 1, 1, 10, 15, 0, // Skip to: 5627
+/* 1777 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1781 */    MCD_OPC_Decode, 158, 23, 235, 3, // Opcode: VMSR_FPSID
+/* 1786 */    MCD_OPC_FilterValue, 1, 21, 0, 0, // Skip to: 1812
+/* 1791 */    MCD_OPC_CheckPredicate, 34, 247, 14, 0, // Skip to: 5627
+/* 1796 */    MCD_OPC_CheckField, 22, 1, 1, 240, 14, 0, // Skip to: 5627
+/* 1803 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1807 */    MCD_OPC_Decode, 151, 23, 235, 3, // Opcode: VMSR
+/* 1812 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 1838
+/* 1817 */    MCD_OPC_CheckPredicate, 81, 221, 14, 0, // Skip to: 5627
+/* 1822 */    MCD_OPC_CheckField, 22, 1, 1, 214, 14, 0, // Skip to: 5627
+/* 1829 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1833 */    MCD_OPC_Decode, 157, 23, 235, 3, // Opcode: VMSR_FPSCR_NZCVQC
+/* 1838 */    MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 1864
+/* 1843 */    MCD_OPC_CheckPredicate, 33, 195, 14, 0, // Skip to: 5627
+/* 1848 */    MCD_OPC_CheckField, 22, 1, 1, 188, 14, 0, // Skip to: 5627
+/* 1855 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1859 */    MCD_OPC_Decode, 154, 23, 235, 3, // Opcode: VMSR_FPEXC
+/* 1864 */    MCD_OPC_FilterValue, 9, 21, 0, 0, // Skip to: 1890
+/* 1869 */    MCD_OPC_CheckPredicate, 33, 169, 14, 0, // Skip to: 5627
+/* 1874 */    MCD_OPC_CheckField, 22, 1, 1, 162, 14, 0, // Skip to: 5627
+/* 1881 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1885 */    MCD_OPC_Decode, 155, 23, 235, 3, // Opcode: VMSR_FPINST
+/* 1890 */    MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 1916
+/* 1895 */    MCD_OPC_CheckPredicate, 33, 143, 14, 0, // Skip to: 5627
+/* 1900 */    MCD_OPC_CheckField, 22, 1, 1, 136, 14, 0, // Skip to: 5627
+/* 1907 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1911 */    MCD_OPC_Decode, 156, 23, 235, 3, // Opcode: VMSR_FPINST2
+/* 1916 */    MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 1942
+/* 1921 */    MCD_OPC_CheckPredicate, 23, 117, 14, 0, // Skip to: 5627
+/* 1926 */    MCD_OPC_CheckField, 22, 1, 1, 110, 14, 0, // Skip to: 5627
+/* 1933 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1937 */    MCD_OPC_Decode, 160, 23, 235, 3, // Opcode: VMSR_VPR
+/* 1942 */    MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 1968
+/* 1947 */    MCD_OPC_CheckPredicate, 23, 91, 14, 0, // Skip to: 5627
+/* 1952 */    MCD_OPC_CheckField, 22, 1, 1, 84, 14, 0, // Skip to: 5627
+/* 1959 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1963 */    MCD_OPC_Decode, 159, 23, 235, 3, // Opcode: VMSR_P0
+/* 1968 */    MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 1994
+/* 1973 */    MCD_OPC_CheckPredicate, 78, 65, 14, 0, // Skip to: 5627
+/* 1978 */    MCD_OPC_CheckField, 22, 1, 1, 58, 14, 0, // Skip to: 5627
+/* 1985 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 1989 */    MCD_OPC_Decode, 152, 23, 235, 3, // Opcode: VMSR_FPCXTNS
+/* 1994 */    MCD_OPC_FilterValue, 15, 44, 14, 0, // Skip to: 5627
+/* 1999 */    MCD_OPC_CheckPredicate, 78, 39, 14, 0, // Skip to: 5627
+/* 2004 */    MCD_OPC_CheckField, 22, 1, 1, 32, 14, 0, // Skip to: 5627
+/* 2011 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2015 */    MCD_OPC_Decode, 153, 23, 235, 3, // Opcode: VMSR_FPCXTS
+/* 2020 */    MCD_OPC_FilterValue, 3, 18, 14, 0, // Skip to: 5627
+/* 2025 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 2028 */    MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 2064
+/* 2033 */    MCD_OPC_CheckPredicate, 80, 5, 14, 0, // Skip to: 5627
+/* 2038 */    MCD_OPC_CheckField, 22, 1, 0, 254, 13, 0, // Skip to: 5627
+/* 2045 */    MCD_OPC_CheckField, 12, 4, 0, 247, 13, 0, // Skip to: 5627
+/* 2052 */    MCD_OPC_CheckField, 0, 8, 0, 240, 13, 0, // Skip to: 5627
+/* 2059 */    MCD_OPC_Decode, 139, 22, 233, 3, // Opcode: VLLDM
+/* 2064 */    MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 2079
+/* 2069 */    MCD_OPC_CheckPredicate, 34, 225, 13, 0, // Skip to: 5627
+/* 2074 */    MCD_OPC_Decode, 245, 21, 234, 3, // Opcode: VLDMSIA_UPD
+/* 2079 */    MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 2094
+/* 2084 */    MCD_OPC_CheckPredicate, 34, 210, 13, 0, // Skip to: 5627
+/* 2089 */    MCD_OPC_Decode, 243, 21, 234, 3, // Opcode: VLDMSDB_UPD
+/* 2094 */    MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 2146
+/* 2099 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2102 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2124
+/* 2107 */    MCD_OPC_CheckPredicate, 33, 187, 13, 0, // Skip to: 5627
+/* 2112 */    MCD_OPC_CheckField, 4, 1, 0, 180, 13, 0, // Skip to: 5627
+/* 2119 */    MCD_OPC_Decode, 161, 16, 228, 3, // Opcode: VADDS
+/* 2124 */    MCD_OPC_FilterValue, 1, 170, 13, 0, // Skip to: 5627
+/* 2129 */    MCD_OPC_CheckPredicate, 33, 165, 13, 0, // Skip to: 5627
+/* 2134 */    MCD_OPC_CheckField, 4, 1, 0, 158, 13, 0, // Skip to: 5627
+/* 2141 */    MCD_OPC_Decode, 241, 29, 228, 3, // Opcode: VSUBS
+/* 2146 */    MCD_OPC_FilterValue, 29, 148, 13, 0, // Skip to: 5627
+/* 2151 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 2154 */    MCD_OPC_FilterValue, 0, 7, 2, 0, // Skip to: 2678
+/* 2159 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 2162 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2184
+/* 2167 */    MCD_OPC_CheckPredicate, 82, 127, 13, 0, // Skip to: 5627
+/* 2172 */    MCD_OPC_CheckField, 5, 1, 0, 120, 13, 0, // Skip to: 5627
+/* 2179 */    MCD_OPC_Decode, 171, 6, 236, 3, // Opcode: FCONSTS
+/* 2184 */    MCD_OPC_FilterValue, 1, 242, 0, 0, // Skip to: 2431
+/* 2189 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 2192 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2207
+/* 2197 */    MCD_OPC_CheckPredicate, 34, 97, 13, 0, // Skip to: 5627
+/* 2202 */    MCD_OPC_Decode, 253, 22, 222, 3, // Opcode: VMOVS
+/* 2207 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2222
+/* 2212 */    MCD_OPC_CheckPredicate, 33, 82, 13, 0, // Skip to: 5627
+/* 2217 */    MCD_OPC_Decode, 204, 23, 222, 3, // Opcode: VNEGS
+/* 2222 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2237
+/* 2227 */    MCD_OPC_CheckPredicate, 83, 67, 13, 0, // Skip to: 5627
+/* 2232 */    MCD_OPC_Decode, 218, 17, 222, 3, // Opcode: VCVTBHS
+/* 2237 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2252
+/* 2242 */    MCD_OPC_CheckPredicate, 83, 52, 13, 0, // Skip to: 5627
+/* 2247 */    MCD_OPC_Decode, 219, 17, 237, 3, // Opcode: VCVTBSH
+/* 2252 */    MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2267
+/* 2257 */    MCD_OPC_CheckPredicate, 33, 37, 13, 0, // Skip to: 5627
+/* 2262 */    MCD_OPC_Decode, 196, 17, 222, 3, // Opcode: VCMPS
+/* 2267 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 2296
+/* 2272 */    MCD_OPC_CheckPredicate, 33, 22, 13, 0, // Skip to: 5627
+/* 2277 */    MCD_OPC_CheckField, 5, 1, 0, 15, 13, 0, // Skip to: 5627
+/* 2284 */    MCD_OPC_CheckField, 0, 4, 0, 8, 13, 0, // Skip to: 5627
+/* 2291 */    MCD_OPC_Decode, 199, 17, 238, 3, // Opcode: VCMPZS
+/* 2296 */    MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2311
+/* 2301 */    MCD_OPC_CheckPredicate, 84, 249, 12, 0, // Skip to: 5627
+/* 2306 */    MCD_OPC_Decode, 131, 26, 222, 3, // Opcode: VRINTRS
+/* 2311 */    MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 2326
+/* 2316 */    MCD_OPC_CheckPredicate, 84, 234, 12, 0, // Skip to: 5627
+/* 2321 */    MCD_OPC_Decode, 138, 26, 222, 3, // Opcode: VRINTXS
+/* 2326 */    MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 2341
+/* 2331 */    MCD_OPC_CheckPredicate, 33, 219, 12, 0, // Skip to: 5627
+/* 2336 */    MCD_OPC_Decode, 193, 30, 222, 3, // Opcode: VUITOS
+/* 2341 */    MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 2356
+/* 2346 */    MCD_OPC_CheckPredicate, 33, 204, 12, 0, // Skip to: 5627
+/* 2351 */    MCD_OPC_Decode, 157, 27, 221, 3, // Opcode: VSHTOS
+/* 2356 */    MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 2371
+/* 2361 */    MCD_OPC_CheckPredicate, 33, 189, 12, 0, // Skip to: 5627
+/* 2366 */    MCD_OPC_Decode, 190, 30, 221, 3, // Opcode: VUHTOS
+/* 2371 */    MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 2386
+/* 2376 */    MCD_OPC_CheckPredicate, 33, 174, 12, 0, // Skip to: 5627
+/* 2381 */    MCD_OPC_Decode, 165, 30, 222, 3, // Opcode: VTOUIRS
+/* 2386 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2401
+/* 2391 */    MCD_OPC_CheckPredicate, 33, 159, 12, 0, // Skip to: 5627
+/* 2396 */    MCD_OPC_Decode, 153, 30, 222, 3, // Opcode: VTOSIRS
+/* 2401 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 2416
+/* 2406 */    MCD_OPC_CheckPredicate, 33, 144, 12, 0, // Skip to: 5627
+/* 2411 */    MCD_OPC_Decode, 150, 30, 221, 3, // Opcode: VTOSHS
+/* 2416 */    MCD_OPC_FilterValue, 15, 134, 12, 0, // Skip to: 5627
+/* 2421 */    MCD_OPC_CheckPredicate, 33, 129, 12, 0, // Skip to: 5627
+/* 2426 */    MCD_OPC_Decode, 162, 30, 221, 3, // Opcode: VTOUHS
+/* 2431 */    MCD_OPC_FilterValue, 3, 119, 12, 0, // Skip to: 5627
+/* 2436 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 2439 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2454
+/* 2444 */    MCD_OPC_CheckPredicate, 33, 106, 12, 0, // Skip to: 5627
+/* 2449 */    MCD_OPC_Decode, 131, 16, 222, 3, // Opcode: VABSS
+/* 2454 */    MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 2469
+/* 2459 */    MCD_OPC_CheckPredicate, 33, 91, 12, 0, // Skip to: 5627
+/* 2464 */    MCD_OPC_Decode, 175, 27, 222, 3, // Opcode: VSQRTS
+/* 2469 */    MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 2484
+/* 2474 */    MCD_OPC_CheckPredicate, 83, 76, 12, 0, // Skip to: 5627
+/* 2479 */    MCD_OPC_Decode, 138, 18, 222, 3, // Opcode: VCVTTHS
+/* 2484 */    MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 2499
+/* 2489 */    MCD_OPC_CheckPredicate, 83, 61, 12, 0, // Skip to: 5627
+/* 2494 */    MCD_OPC_Decode, 139, 18, 237, 3, // Opcode: VCVTTSH
+/* 2499 */    MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 2514
+/* 2504 */    MCD_OPC_CheckPredicate, 33, 46, 12, 0, // Skip to: 5627
+/* 2509 */    MCD_OPC_Decode, 191, 17, 222, 3, // Opcode: VCMPES
+/* 2514 */    MCD_OPC_FilterValue, 5, 24, 0, 0, // Skip to: 2543
+/* 2519 */    MCD_OPC_CheckPredicate, 33, 31, 12, 0, // Skip to: 5627
+/* 2524 */    MCD_OPC_CheckField, 5, 1, 0, 24, 12, 0, // Skip to: 5627
+/* 2531 */    MCD_OPC_CheckField, 0, 4, 0, 17, 12, 0, // Skip to: 5627
+/* 2538 */    MCD_OPC_Decode, 194, 17, 238, 3, // Opcode: VCMPEZS
+/* 2543 */    MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 2558
+/* 2548 */    MCD_OPC_CheckPredicate, 84, 2, 12, 0, // Skip to: 5627
+/* 2553 */    MCD_OPC_Decode, 145, 26, 222, 3, // Opcode: VRINTZS
+/* 2558 */    MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 2573
+/* 2563 */    MCD_OPC_CheckPredicate, 85, 243, 11, 0, // Skip to: 5627
+/* 2568 */    MCD_OPC_Decode, 220, 17, 239, 3, // Opcode: VCVTDS
+/* 2573 */    MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 2588
+/* 2578 */    MCD_OPC_CheckPredicate, 33, 228, 11, 0, // Skip to: 5627
+/* 2583 */    MCD_OPC_Decode, 160, 27, 222, 3, // Opcode: VSITOS
+/* 2588 */    MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 2603
+/* 2593 */    MCD_OPC_CheckPredicate, 33, 213, 11, 0, // Skip to: 5627
+/* 2598 */    MCD_OPC_Decode, 171, 27, 221, 3, // Opcode: VSLTOS
+/* 2603 */    MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 2618
+/* 2608 */    MCD_OPC_CheckPredicate, 33, 198, 11, 0, // Skip to: 5627
+/* 2613 */    MCD_OPC_Decode, 196, 30, 221, 3, // Opcode: VULTOS
+/* 2618 */    MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 2633
+/* 2623 */    MCD_OPC_CheckPredicate, 33, 183, 11, 0, // Skip to: 5627
+/* 2628 */    MCD_OPC_Decode, 168, 30, 222, 3, // Opcode: VTOUIZS
+/* 2633 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 2648
+/* 2638 */    MCD_OPC_CheckPredicate, 33, 168, 11, 0, // Skip to: 5627
+/* 2643 */    MCD_OPC_Decode, 156, 30, 222, 3, // Opcode: VTOSIZS
+/* 2648 */    MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 2663
+/* 2653 */    MCD_OPC_CheckPredicate, 33, 153, 11, 0, // Skip to: 5627
+/* 2658 */    MCD_OPC_Decode, 159, 30, 221, 3, // Opcode: VTOSLS
+/* 2663 */    MCD_OPC_FilterValue, 15, 143, 11, 0, // Skip to: 5627
+/* 2668 */    MCD_OPC_CheckPredicate, 33, 138, 11, 0, // Skip to: 5627
+/* 2673 */    MCD_OPC_Decode, 171, 30, 221, 3, // Opcode: VTOULS
+/* 2678 */    MCD_OPC_FilterValue, 1, 128, 11, 0, // Skip to: 5627
+/* 2683 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 2686 */    MCD_OPC_FilterValue, 0, 21, 0, 0, // Skip to: 2712
+/* 2691 */    MCD_OPC_CheckPredicate, 33, 115, 11, 0, // Skip to: 5627
+/* 2696 */    MCD_OPC_CheckField, 22, 1, 1, 108, 11, 0, // Skip to: 5627
+/* 2703 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2707 */    MCD_OPC_Decode, 145, 23, 235, 3, // Opcode: VMRS_FPSID
+/* 2712 */    MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 2760
+/* 2717 */    MCD_OPC_ExtractField, 22, 1,  // Inst{22} ...
+/* 2720 */    MCD_OPC_FilterValue, 1, 86, 11, 0, // Skip to: 5627
+/* 2725 */    MCD_OPC_CheckPredicate, 34, 16, 0, 0, // Skip to: 2746
+/* 2730 */    MCD_OPC_CheckField, 12, 4, 15, 9, 0, 0, // Skip to: 2746
+/* 2737 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2741 */    MCD_OPC_Decode, 175, 6, 235, 3, // Opcode: FMSTAT
+/* 2746 */    MCD_OPC_CheckPredicate, 34, 60, 11, 0, // Skip to: 5627
+/* 2751 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2755 */    MCD_OPC_Decode, 138, 23, 235, 3, // Opcode: VMRS
+/* 2760 */    MCD_OPC_FilterValue, 2, 21, 0, 0, // Skip to: 2786
+/* 2765 */    MCD_OPC_CheckPredicate, 81, 41, 11, 0, // Skip to: 5627
+/* 2770 */    MCD_OPC_CheckField, 22, 1, 1, 34, 11, 0, // Skip to: 5627
+/* 2777 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2781 */    MCD_OPC_Decode, 144, 23, 235, 3, // Opcode: VMRS_FPSCR_NZCVQC
+/* 2786 */    MCD_OPC_FilterValue, 5, 21, 0, 0, // Skip to: 2812
+/* 2791 */    MCD_OPC_CheckPredicate, 84, 15, 11, 0, // Skip to: 5627
+/* 2796 */    MCD_OPC_CheckField, 22, 1, 1, 8, 11, 0, // Skip to: 5627
+/* 2803 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2807 */    MCD_OPC_Decode, 148, 23, 235, 3, // Opcode: VMRS_MVFR2
+/* 2812 */    MCD_OPC_FilterValue, 6, 21, 0, 0, // Skip to: 2838
+/* 2817 */    MCD_OPC_CheckPredicate, 33, 245, 10, 0, // Skip to: 5627
+/* 2822 */    MCD_OPC_CheckField, 22, 1, 1, 238, 10, 0, // Skip to: 5627
+/* 2829 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2833 */    MCD_OPC_Decode, 147, 23, 235, 3, // Opcode: VMRS_MVFR1
+/* 2838 */    MCD_OPC_FilterValue, 7, 21, 0, 0, // Skip to: 2864
+/* 2843 */    MCD_OPC_CheckPredicate, 33, 219, 10, 0, // Skip to: 5627
+/* 2848 */    MCD_OPC_CheckField, 22, 1, 1, 212, 10, 0, // Skip to: 5627
+/* 2855 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2859 */    MCD_OPC_Decode, 146, 23, 235, 3, // Opcode: VMRS_MVFR0
+/* 2864 */    MCD_OPC_FilterValue, 8, 21, 0, 0, // Skip to: 2890
+/* 2869 */    MCD_OPC_CheckPredicate, 33, 193, 10, 0, // Skip to: 5627
+/* 2874 */    MCD_OPC_CheckField, 22, 1, 1, 186, 10, 0, // Skip to: 5627
+/* 2881 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2885 */    MCD_OPC_Decode, 141, 23, 235, 3, // Opcode: VMRS_FPEXC
+/* 2890 */    MCD_OPC_FilterValue, 9, 21, 0, 0, // Skip to: 2916
+/* 2895 */    MCD_OPC_CheckPredicate, 33, 167, 10, 0, // Skip to: 5627
+/* 2900 */    MCD_OPC_CheckField, 22, 1, 1, 160, 10, 0, // Skip to: 5627
+/* 2907 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2911 */    MCD_OPC_Decode, 142, 23, 235, 3, // Opcode: VMRS_FPINST
+/* 2916 */    MCD_OPC_FilterValue, 10, 21, 0, 0, // Skip to: 2942
+/* 2921 */    MCD_OPC_CheckPredicate, 33, 141, 10, 0, // Skip to: 5627
+/* 2926 */    MCD_OPC_CheckField, 22, 1, 1, 134, 10, 0, // Skip to: 5627
+/* 2933 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2937 */    MCD_OPC_Decode, 143, 23, 235, 3, // Opcode: VMRS_FPINST2
+/* 2942 */    MCD_OPC_FilterValue, 12, 21, 0, 0, // Skip to: 2968
+/* 2947 */    MCD_OPC_CheckPredicate, 23, 115, 10, 0, // Skip to: 5627
+/* 2952 */    MCD_OPC_CheckField, 22, 1, 1, 108, 10, 0, // Skip to: 5627
+/* 2959 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2963 */    MCD_OPC_Decode, 150, 23, 235, 3, // Opcode: VMRS_VPR
+/* 2968 */    MCD_OPC_FilterValue, 13, 21, 0, 0, // Skip to: 2994
+/* 2973 */    MCD_OPC_CheckPredicate, 23, 89, 10, 0, // Skip to: 5627
+/* 2978 */    MCD_OPC_CheckField, 22, 1, 1, 82, 10, 0, // Skip to: 5627
+/* 2985 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 2989 */    MCD_OPC_Decode, 149, 23, 235, 3, // Opcode: VMRS_P0
+/* 2994 */    MCD_OPC_FilterValue, 14, 21, 0, 0, // Skip to: 3020
+/* 2999 */    MCD_OPC_CheckPredicate, 78, 63, 10, 0, // Skip to: 5627
+/* 3004 */    MCD_OPC_CheckField, 22, 1, 1, 56, 10, 0, // Skip to: 5627
+/* 3011 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 3015 */    MCD_OPC_Decode, 139, 23, 235, 3, // Opcode: VMRS_FPCXTNS
+/* 3020 */    MCD_OPC_FilterValue, 15, 42, 10, 0, // Skip to: 5627
+/* 3025 */    MCD_OPC_CheckPredicate, 78, 37, 10, 0, // Skip to: 5627
+/* 3030 */    MCD_OPC_CheckField, 22, 1, 1, 30, 10, 0, // Skip to: 5627
+/* 3037 */    MCD_OPC_SoftFail, 239, 1 /* 0xef */, 0,
+/* 3041 */    MCD_OPC_Decode, 140, 23, 235, 3, // Opcode: VMRS_FPCXTS
+/* 3046 */    MCD_OPC_FilterValue, 11, 252, 5, 0, // Skip to: 4583
+/* 3051 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 3054 */    MCD_OPC_FilterValue, 0, 196, 0, 0, // Skip to: 3255
+/* 3059 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 3062 */    MCD_OPC_FilterValue, 12, 84, 0, 0, // Skip to: 3151
+/* 3067 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 3070 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3106
+/* 3075 */    MCD_OPC_CheckPredicate, 34, 243, 9, 0, // Skip to: 5627
+/* 3080 */    MCD_OPC_CheckField, 22, 1, 1, 236, 9, 0, // Skip to: 5627
+/* 3087 */    MCD_OPC_CheckField, 6, 2, 0, 229, 9, 0, // Skip to: 5627
+/* 3094 */    MCD_OPC_CheckField, 4, 1, 1, 222, 9, 0, // Skip to: 5627
+/* 3101 */    MCD_OPC_Decode, 237, 22, 240, 3, // Opcode: VMOVDRR
+/* 3106 */    MCD_OPC_FilterValue, 1, 212, 9, 0, // Skip to: 5627
+/* 3111 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 3114 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3129
+/* 3119 */    MCD_OPC_CheckPredicate, 34, 199, 9, 0, // Skip to: 5627
+/* 3124 */    MCD_OPC_Decode, 203, 29, 241, 3, // Opcode: VSTMDIA
+/* 3129 */    MCD_OPC_FilterValue, 1, 189, 9, 0, // Skip to: 5627
+/* 3134 */    MCD_OPC_CheckPredicate, 34, 184, 9, 0, // Skip to: 5627
+/* 3139 */    MCD_OPC_CheckField, 22, 1, 0, 177, 9, 0, // Skip to: 5627
+/* 3146 */    MCD_OPC_Decode, 177, 6, 242, 3, // Opcode: FSTMXIA
+/* 3151 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3166
+/* 3156 */    MCD_OPC_CheckPredicate, 34, 162, 9, 0, // Skip to: 5627
+/* 3161 */    MCD_OPC_Decode, 209, 29, 243, 3, // Opcode: VSTRD
+/* 3166 */    MCD_OPC_FilterValue, 14, 152, 9, 0, // Skip to: 5627
+/* 3171 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3174 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 3226
+/* 3179 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 3182 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3204
+/* 3187 */    MCD_OPC_CheckPredicate, 85, 131, 9, 0, // Skip to: 5627
+/* 3192 */    MCD_OPC_CheckField, 4, 1, 0, 124, 9, 0, // Skip to: 5627
+/* 3199 */    MCD_OPC_Decode, 173, 22, 244, 3, // Opcode: VMLAD
+/* 3204 */    MCD_OPC_FilterValue, 1, 114, 9, 0, // Skip to: 5627
+/* 3209 */    MCD_OPC_CheckPredicate, 85, 109, 9, 0, // Skip to: 5627
+/* 3214 */    MCD_OPC_CheckField, 4, 1, 0, 102, 9, 0, // Skip to: 5627
+/* 3221 */    MCD_OPC_Decode, 174, 18, 245, 3, // Opcode: VDIVD
+/* 3226 */    MCD_OPC_FilterValue, 1, 92, 9, 0, // Skip to: 5627
+/* 3231 */    MCD_OPC_CheckPredicate, 85, 87, 9, 0, // Skip to: 5627
+/* 3236 */    MCD_OPC_CheckField, 23, 1, 0, 80, 9, 0, // Skip to: 5627
+/* 3243 */    MCD_OPC_CheckField, 4, 1, 0, 73, 9, 0, // Skip to: 5627
+/* 3250 */    MCD_OPC_Decode, 204, 22, 244, 3, // Opcode: VMLSD
+/* 3255 */    MCD_OPC_FilterValue, 1, 243, 0, 0, // Skip to: 3503
+/* 3260 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 3263 */    MCD_OPC_FilterValue, 12, 108, 0, 0, // Skip to: 3376
+/* 3268 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 3271 */    MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 3307
+/* 3276 */    MCD_OPC_CheckPredicate, 34, 42, 9, 0, // Skip to: 5627
+/* 3281 */    MCD_OPC_CheckField, 22, 1, 1, 35, 9, 0, // Skip to: 5627
+/* 3288 */    MCD_OPC_CheckField, 6, 2, 0, 28, 9, 0, // Skip to: 5627
+/* 3295 */    MCD_OPC_CheckField, 4, 1, 1, 21, 9, 0, // Skip to: 5627
+/* 3302 */    MCD_OPC_Decode, 250, 22, 246, 3, // Opcode: VMOVRRD
+/* 3307 */    MCD_OPC_FilterValue, 1, 11, 9, 0, // Skip to: 5627
+/* 3312 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 3315 */    MCD_OPC_FilterValue, 0, 34, 0, 0, // Skip to: 3354
+/* 3320 */    MCD_OPC_CheckPredicate, 78, 19, 0, 0, // Skip to: 3344
+/* 3325 */    MCD_OPC_CheckField, 28, 4, 14, 12, 0, 0, // Skip to: 3344
+/* 3332 */    MCD_OPC_CheckField, 16, 4, 15, 5, 0, 0, // Skip to: 3344
+/* 3339 */    MCD_OPC_Decode, 210, 26, 231, 3, // Opcode: VSCCLRMD
+/* 3344 */    MCD_OPC_CheckPredicate, 34, 230, 8, 0, // Skip to: 5627
+/* 3349 */    MCD_OPC_Decode, 240, 21, 241, 3, // Opcode: VLDMDIA
+/* 3354 */    MCD_OPC_FilterValue, 1, 220, 8, 0, // Skip to: 5627
+/* 3359 */    MCD_OPC_CheckPredicate, 34, 215, 8, 0, // Skip to: 5627
+/* 3364 */    MCD_OPC_CheckField, 22, 1, 0, 208, 8, 0, // Skip to: 5627
+/* 3371 */    MCD_OPC_Decode, 173, 6, 242, 3, // Opcode: FLDMXIA
+/* 3376 */    MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 3391
+/* 3381 */    MCD_OPC_CheckPredicate, 34, 193, 8, 0, // Skip to: 5627
+/* 3386 */    MCD_OPC_Decode, 246, 21, 243, 3, // Opcode: VLDRD
+/* 3391 */    MCD_OPC_FilterValue, 14, 183, 8, 0, // Skip to: 5627
+/* 3396 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3399 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 3451
+/* 3404 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 3407 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3429
+/* 3412 */    MCD_OPC_CheckPredicate, 85, 162, 8, 0, // Skip to: 5627
+/* 3417 */    MCD_OPC_CheckField, 4, 1, 0, 155, 8, 0, // Skip to: 5627
+/* 3424 */    MCD_OPC_Decode, 218, 23, 244, 3, // Opcode: VNMLSD
+/* 3429 */    MCD_OPC_FilterValue, 1, 145, 8, 0, // Skip to: 5627
+/* 3434 */    MCD_OPC_CheckPredicate, 86, 140, 8, 0, // Skip to: 5627
+/* 3439 */    MCD_OPC_CheckField, 4, 1, 0, 133, 8, 0, // Skip to: 5627
+/* 3446 */    MCD_OPC_Decode, 223, 18, 244, 3, // Opcode: VFNMSD
+/* 3451 */    MCD_OPC_FilterValue, 1, 123, 8, 0, // Skip to: 5627
+/* 3456 */    MCD_OPC_ExtractField, 23, 1,  // Inst{23} ...
+/* 3459 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3481
+/* 3464 */    MCD_OPC_CheckPredicate, 85, 110, 8, 0, // Skip to: 5627
+/* 3469 */    MCD_OPC_CheckField, 4, 1, 0, 103, 8, 0, // Skip to: 5627
+/* 3476 */    MCD_OPC_Decode, 215, 23, 244, 3, // Opcode: VNMLAD
+/* 3481 */    MCD_OPC_FilterValue, 1, 93, 8, 0, // Skip to: 5627
+/* 3486 */    MCD_OPC_CheckPredicate, 86, 88, 8, 0, // Skip to: 5627
+/* 3491 */    MCD_OPC_CheckField, 4, 1, 0, 81, 8, 0, // Skip to: 5627
+/* 3498 */    MCD_OPC_Decode, 220, 18, 244, 3, // Opcode: VFNMAD
+/* 3503 */    MCD_OPC_FilterValue, 2, 197, 0, 0, // Skip to: 3705
+/* 3508 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 3511 */    MCD_OPC_FilterValue, 25, 40, 0, 0, // Skip to: 3556
+/* 3516 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 3519 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3534
+/* 3524 */    MCD_OPC_CheckPredicate, 34, 50, 8, 0, // Skip to: 5627
+/* 3529 */    MCD_OPC_Decode, 204, 29, 247, 3, // Opcode: VSTMDIA_UPD
+/* 3534 */    MCD_OPC_FilterValue, 1, 40, 8, 0, // Skip to: 5627
+/* 3539 */    MCD_OPC_CheckPredicate, 34, 35, 8, 0, // Skip to: 5627
+/* 3544 */    MCD_OPC_CheckField, 22, 1, 0, 28, 8, 0, // Skip to: 5627
+/* 3551 */    MCD_OPC_Decode, 178, 6, 248, 3, // Opcode: FSTMXIA_UPD
+/* 3556 */    MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 3601
+/* 3561 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 3564 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3579
+/* 3569 */    MCD_OPC_CheckPredicate, 34, 5, 8, 0, // Skip to: 5627
+/* 3574 */    MCD_OPC_Decode, 202, 29, 247, 3, // Opcode: VSTMDDB_UPD
+/* 3579 */    MCD_OPC_FilterValue, 1, 251, 7, 0, // Skip to: 5627
+/* 3584 */    MCD_OPC_CheckPredicate, 34, 246, 7, 0, // Skip to: 5627
+/* 3589 */    MCD_OPC_CheckField, 22, 1, 0, 239, 7, 0, // Skip to: 5627
+/* 3596 */    MCD_OPC_Decode, 176, 6, 248, 3, // Opcode: FSTMXDB_UPD
+/* 3601 */    MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3653
+/* 3606 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3609 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3631
+/* 3614 */    MCD_OPC_CheckPredicate, 85, 216, 7, 0, // Skip to: 5627
+/* 3619 */    MCD_OPC_CheckField, 4, 1, 0, 209, 7, 0, // Skip to: 5627
+/* 3626 */    MCD_OPC_Decode, 161, 23, 245, 3, // Opcode: VMULD
+/* 3631 */    MCD_OPC_FilterValue, 1, 199, 7, 0, // Skip to: 5627
+/* 3636 */    MCD_OPC_CheckPredicate, 85, 194, 7, 0, // Skip to: 5627
+/* 3641 */    MCD_OPC_CheckField, 4, 1, 0, 187, 7, 0, // Skip to: 5627
+/* 3648 */    MCD_OPC_Decode, 221, 23, 245, 3, // Opcode: VNMULD
+/* 3653 */    MCD_OPC_FilterValue, 29, 177, 7, 0, // Skip to: 5627
+/* 3658 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3661 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3683
+/* 3666 */    MCD_OPC_CheckPredicate, 86, 164, 7, 0, // Skip to: 5627
+/* 3671 */    MCD_OPC_CheckField, 4, 1, 0, 157, 7, 0, // Skip to: 5627
+/* 3678 */    MCD_OPC_Decode, 198, 18, 244, 3, // Opcode: VFMAD
+/* 3683 */    MCD_OPC_FilterValue, 1, 147, 7, 0, // Skip to: 5627
+/* 3688 */    MCD_OPC_CheckPredicate, 86, 142, 7, 0, // Skip to: 5627
+/* 3693 */    MCD_OPC_CheckField, 4, 1, 0, 135, 7, 0, // Skip to: 5627
+/* 3700 */    MCD_OPC_Decode, 209, 18, 244, 3, // Opcode: VFMSD
+/* 3705 */    MCD_OPC_FilterValue, 3, 125, 7, 0, // Skip to: 5627
+/* 3710 */    MCD_OPC_ExtractField, 23, 5,  // Inst{27-23} ...
+/* 3713 */    MCD_OPC_FilterValue, 25, 40, 0, 0, // Skip to: 3758
+/* 3718 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 3721 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3736
+/* 3726 */    MCD_OPC_CheckPredicate, 34, 104, 7, 0, // Skip to: 5627
+/* 3731 */    MCD_OPC_Decode, 241, 21, 247, 3, // Opcode: VLDMDIA_UPD
+/* 3736 */    MCD_OPC_FilterValue, 1, 94, 7, 0, // Skip to: 5627
+/* 3741 */    MCD_OPC_CheckPredicate, 34, 89, 7, 0, // Skip to: 5627
+/* 3746 */    MCD_OPC_CheckField, 22, 1, 0, 82, 7, 0, // Skip to: 5627
+/* 3753 */    MCD_OPC_Decode, 174, 6, 248, 3, // Opcode: FLDMXIA_UPD
+/* 3758 */    MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 3803
+/* 3763 */    MCD_OPC_ExtractField, 0, 1,  // Inst{0} ...
+/* 3766 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3781
+/* 3771 */    MCD_OPC_CheckPredicate, 34, 59, 7, 0, // Skip to: 5627
+/* 3776 */    MCD_OPC_Decode, 239, 21, 247, 3, // Opcode: VLDMDDB_UPD
+/* 3781 */    MCD_OPC_FilterValue, 1, 49, 7, 0, // Skip to: 5627
+/* 3786 */    MCD_OPC_CheckPredicate, 34, 44, 7, 0, // Skip to: 5627
+/* 3791 */    MCD_OPC_CheckField, 22, 1, 0, 37, 7, 0, // Skip to: 5627
+/* 3798 */    MCD_OPC_Decode, 172, 6, 248, 3, // Opcode: FLDMXDB_UPD
+/* 3803 */    MCD_OPC_FilterValue, 28, 47, 0, 0, // Skip to: 3855
+/* 3808 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3811 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3833
+/* 3816 */    MCD_OPC_CheckPredicate, 85, 14, 7, 0, // Skip to: 5627
+/* 3821 */    MCD_OPC_CheckField, 4, 1, 0, 7, 7, 0, // Skip to: 5627
+/* 3828 */    MCD_OPC_Decode, 150, 16, 245, 3, // Opcode: VADDD
+/* 3833 */    MCD_OPC_FilterValue, 1, 253, 6, 0, // Skip to: 5627
+/* 3838 */    MCD_OPC_CheckPredicate, 85, 248, 6, 0, // Skip to: 5627
+/* 3843 */    MCD_OPC_CheckField, 4, 1, 0, 241, 6, 0, // Skip to: 5627
+/* 3850 */    MCD_OPC_Decode, 230, 29, 245, 3, // Opcode: VSUBD
+/* 3855 */    MCD_OPC_FilterValue, 29, 231, 6, 0, // Skip to: 5627
+/* 3860 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 3863 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3885
+/* 3868 */    MCD_OPC_CheckPredicate, 87, 218, 6, 0, // Skip to: 5627
+/* 3873 */    MCD_OPC_CheckField, 4, 2, 0, 211, 6, 0, // Skip to: 5627
+/* 3880 */    MCD_OPC_Decode, 169, 6, 249, 3, // Opcode: FCONSTD
+/* 3885 */    MCD_OPC_FilterValue, 1, 77, 1, 0, // Skip to: 4223
+/* 3890 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 3893 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3915
+/* 3898 */    MCD_OPC_CheckPredicate, 88, 188, 6, 0, // Skip to: 5627
+/* 3903 */    MCD_OPC_CheckField, 4, 1, 0, 181, 6, 0, // Skip to: 5627
+/* 3910 */    MCD_OPC_Decode, 236, 22, 250, 3, // Opcode: VMOVD
+/* 3915 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3937
+/* 3920 */    MCD_OPC_CheckPredicate, 85, 166, 6, 0, // Skip to: 5627
+/* 3925 */    MCD_OPC_CheckField, 4, 1, 0, 159, 6, 0, // Skip to: 5627
+/* 3932 */    MCD_OPC_Decode, 202, 23, 250, 3, // Opcode: VNEGD
+/* 3937 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 3959
+/* 3942 */    MCD_OPC_CheckPredicate, 89, 144, 6, 0, // Skip to: 5627
+/* 3947 */    MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 5627
+/* 3954 */    MCD_OPC_Decode, 217, 17, 239, 3, // Opcode: VCVTBHD
+/* 3959 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 3981
+/* 3964 */    MCD_OPC_CheckPredicate, 89, 122, 6, 0, // Skip to: 5627
+/* 3969 */    MCD_OPC_CheckField, 4, 1, 0, 115, 6, 0, // Skip to: 5627
+/* 3976 */    MCD_OPC_Decode, 216, 17, 251, 3, // Opcode: VCVTBDH
+/* 3981 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4003
+/* 3986 */    MCD_OPC_CheckPredicate, 85, 100, 6, 0, // Skip to: 5627
+/* 3991 */    MCD_OPC_CheckField, 4, 1, 0, 93, 6, 0, // Skip to: 5627
+/* 3998 */    MCD_OPC_Decode, 188, 17, 250, 3, // Opcode: VCMPD
+/* 4003 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4025
+/* 4008 */    MCD_OPC_CheckPredicate, 85, 78, 6, 0, // Skip to: 5627
+/* 4013 */    MCD_OPC_CheckField, 0, 6, 0, 71, 6, 0, // Skip to: 5627
+/* 4020 */    MCD_OPC_Decode, 197, 17, 252, 3, // Opcode: VCMPZD
+/* 4025 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4047
+/* 4030 */    MCD_OPC_CheckPredicate, 89, 56, 6, 0, // Skip to: 5627
+/* 4035 */    MCD_OPC_CheckField, 4, 1, 0, 49, 6, 0, // Skip to: 5627
+/* 4042 */    MCD_OPC_Decode, 129, 26, 250, 3, // Opcode: VRINTRD
+/* 4047 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4069
+/* 4052 */    MCD_OPC_CheckPredicate, 89, 34, 6, 0, // Skip to: 5627
+/* 4057 */    MCD_OPC_CheckField, 4, 1, 0, 27, 6, 0, // Skip to: 5627
+/* 4064 */    MCD_OPC_Decode, 132, 26, 250, 3, // Opcode: VRINTXD
+/* 4069 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4091
+/* 4074 */    MCD_OPC_CheckPredicate, 85, 12, 6, 0, // Skip to: 5627
+/* 4079 */    MCD_OPC_CheckField, 4, 1, 0, 5, 6, 0, // Skip to: 5627
+/* 4086 */    MCD_OPC_Decode, 191, 30, 239, 3, // Opcode: VUITOD
+/* 4091 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4113
+/* 4096 */    MCD_OPC_CheckPredicate, 85, 246, 5, 0, // Skip to: 5627
+/* 4101 */    MCD_OPC_CheckField, 4, 1, 0, 239, 5, 0, // Skip to: 5627
+/* 4108 */    MCD_OPC_Decode, 155, 27, 253, 3, // Opcode: VSHTOD
+/* 4113 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4135
+/* 4118 */    MCD_OPC_CheckPredicate, 85, 224, 5, 0, // Skip to: 5627
+/* 4123 */    MCD_OPC_CheckField, 4, 1, 0, 217, 5, 0, // Skip to: 5627
+/* 4130 */    MCD_OPC_Decode, 188, 30, 253, 3, // Opcode: VUHTOD
+/* 4135 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4157
+/* 4140 */    MCD_OPC_CheckPredicate, 85, 202, 5, 0, // Skip to: 5627
+/* 4145 */    MCD_OPC_CheckField, 4, 1, 0, 195, 5, 0, // Skip to: 5627
+/* 4152 */    MCD_OPC_Decode, 163, 30, 254, 3, // Opcode: VTOUIRD
+/* 4157 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4179
+/* 4162 */    MCD_OPC_CheckPredicate, 85, 180, 5, 0, // Skip to: 5627
+/* 4167 */    MCD_OPC_CheckField, 4, 1, 0, 173, 5, 0, // Skip to: 5627
+/* 4174 */    MCD_OPC_Decode, 151, 30, 254, 3, // Opcode: VTOSIRD
+/* 4179 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4201
+/* 4184 */    MCD_OPC_CheckPredicate, 85, 158, 5, 0, // Skip to: 5627
+/* 4189 */    MCD_OPC_CheckField, 4, 1, 0, 151, 5, 0, // Skip to: 5627
+/* 4196 */    MCD_OPC_Decode, 148, 30, 253, 3, // Opcode: VTOSHD
+/* 4201 */    MCD_OPC_FilterValue, 15, 141, 5, 0, // Skip to: 5627
+/* 4206 */    MCD_OPC_CheckPredicate, 85, 136, 5, 0, // Skip to: 5627
+/* 4211 */    MCD_OPC_CheckField, 4, 1, 0, 129, 5, 0, // Skip to: 5627
+/* 4218 */    MCD_OPC_Decode, 160, 30, 253, 3, // Opcode: VTOUHD
+/* 4223 */    MCD_OPC_FilterValue, 3, 119, 5, 0, // Skip to: 5627
+/* 4228 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 4231 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 4253
+/* 4236 */    MCD_OPC_CheckPredicate, 85, 106, 5, 0, // Skip to: 5627
+/* 4241 */    MCD_OPC_CheckField, 4, 1, 0, 99, 5, 0, // Skip to: 5627
+/* 4248 */    MCD_OPC_Decode, 129, 16, 250, 3, // Opcode: VABSD
+/* 4253 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 4275
+/* 4258 */    MCD_OPC_CheckPredicate, 85, 84, 5, 0, // Skip to: 5627
+/* 4263 */    MCD_OPC_CheckField, 4, 1, 0, 77, 5, 0, // Skip to: 5627
+/* 4270 */    MCD_OPC_Decode, 173, 27, 250, 3, // Opcode: VSQRTD
+/* 4275 */    MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 4297
+/* 4280 */    MCD_OPC_CheckPredicate, 89, 62, 5, 0, // Skip to: 5627
+/* 4285 */    MCD_OPC_CheckField, 4, 1, 0, 55, 5, 0, // Skip to: 5627
+/* 4292 */    MCD_OPC_Decode, 137, 18, 239, 3, // Opcode: VCVTTHD
+/* 4297 */    MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 4319
+/* 4302 */    MCD_OPC_CheckPredicate, 89, 40, 5, 0, // Skip to: 5627
+/* 4307 */    MCD_OPC_CheckField, 4, 1, 0, 33, 5, 0, // Skip to: 5627
+/* 4314 */    MCD_OPC_Decode, 136, 18, 251, 3, // Opcode: VCVTTDH
+/* 4319 */    MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 4341
+/* 4324 */    MCD_OPC_CheckPredicate, 85, 18, 5, 0, // Skip to: 5627
+/* 4329 */    MCD_OPC_CheckField, 4, 1, 0, 11, 5, 0, // Skip to: 5627
+/* 4336 */    MCD_OPC_Decode, 189, 17, 250, 3, // Opcode: VCMPED
+/* 4341 */    MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 4363
+/* 4346 */    MCD_OPC_CheckPredicate, 85, 252, 4, 0, // Skip to: 5627
+/* 4351 */    MCD_OPC_CheckField, 0, 6, 0, 245, 4, 0, // Skip to: 5627
+/* 4358 */    MCD_OPC_Decode, 192, 17, 252, 3, // Opcode: VCMPEZD
+/* 4363 */    MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 4385
+/* 4368 */    MCD_OPC_CheckPredicate, 89, 230, 4, 0, // Skip to: 5627
+/* 4373 */    MCD_OPC_CheckField, 4, 1, 0, 223, 4, 0, // Skip to: 5627
+/* 4380 */    MCD_OPC_Decode, 139, 26, 250, 3, // Opcode: VRINTZD
+/* 4385 */    MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 4407
+/* 4390 */    MCD_OPC_CheckPredicate, 85, 208, 4, 0, // Skip to: 5627
+/* 4395 */    MCD_OPC_CheckField, 4, 1, 0, 201, 4, 0, // Skip to: 5627
+/* 4402 */    MCD_OPC_Decode, 135, 18, 254, 3, // Opcode: VCVTSD
+/* 4407 */    MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 4429
+/* 4412 */    MCD_OPC_CheckPredicate, 85, 186, 4, 0, // Skip to: 5627
+/* 4417 */    MCD_OPC_CheckField, 4, 1, 0, 179, 4, 0, // Skip to: 5627
+/* 4424 */    MCD_OPC_Decode, 158, 27, 239, 3, // Opcode: VSITOD
+/* 4429 */    MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 4451
+/* 4434 */    MCD_OPC_CheckPredicate, 90, 164, 4, 0, // Skip to: 5627
+/* 4439 */    MCD_OPC_CheckField, 4, 1, 0, 157, 4, 0, // Skip to: 5627
+/* 4446 */    MCD_OPC_Decode, 134, 19, 254, 3, // Opcode: VJCVT
+/* 4451 */    MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 4473
+/* 4456 */    MCD_OPC_CheckPredicate, 85, 142, 4, 0, // Skip to: 5627
+/* 4461 */    MCD_OPC_CheckField, 4, 1, 0, 135, 4, 0, // Skip to: 5627
+/* 4468 */    MCD_OPC_Decode, 169, 27, 253, 3, // Opcode: VSLTOD
+/* 4473 */    MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 4495
+/* 4478 */    MCD_OPC_CheckPredicate, 85, 120, 4, 0, // Skip to: 5627
+/* 4483 */    MCD_OPC_CheckField, 4, 1, 0, 113, 4, 0, // Skip to: 5627
+/* 4490 */    MCD_OPC_Decode, 194, 30, 253, 3, // Opcode: VULTOD
+/* 4495 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4517
+/* 4500 */    MCD_OPC_CheckPredicate, 85, 98, 4, 0, // Skip to: 5627
+/* 4505 */    MCD_OPC_CheckField, 4, 1, 0, 91, 4, 0, // Skip to: 5627
+/* 4512 */    MCD_OPC_Decode, 166, 30, 254, 3, // Opcode: VTOUIZD
+/* 4517 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 4539
+/* 4522 */    MCD_OPC_CheckPredicate, 85, 76, 4, 0, // Skip to: 5627
+/* 4527 */    MCD_OPC_CheckField, 4, 1, 0, 69, 4, 0, // Skip to: 5627
+/* 4534 */    MCD_OPC_Decode, 154, 30, 254, 3, // Opcode: VTOSIZD
+/* 4539 */    MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 4561
+/* 4544 */    MCD_OPC_CheckPredicate, 85, 54, 4, 0, // Skip to: 5627
+/* 4549 */    MCD_OPC_CheckField, 4, 1, 0, 47, 4, 0, // Skip to: 5627
+/* 4556 */    MCD_OPC_Decode, 157, 30, 253, 3, // Opcode: VTOSLD
+/* 4561 */    MCD_OPC_FilterValue, 15, 37, 4, 0, // Skip to: 5627
+/* 4566 */    MCD_OPC_CheckPredicate, 85, 32, 4, 0, // Skip to: 5627
+/* 4571 */    MCD_OPC_CheckField, 4, 1, 0, 25, 4, 0, // Skip to: 5627
+/* 4578 */    MCD_OPC_Decode, 169, 30, 253, 3, // Opcode: VTOULD
+/* 4583 */    MCD_OPC_FilterValue, 15, 15, 4, 0, // Skip to: 5627
+/* 4588 */    MCD_OPC_ExtractField, 20, 3,  // Inst{22-20} ...
+/* 4591 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 4657
+/* 4596 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 4599 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 4628
+/* 4604 */    MCD_OPC_CheckPredicate, 25, 250, 3, 0, // Skip to: 5627
+/* 4609 */    MCD_OPC_CheckField, 24, 4, 13, 243, 3, 0, // Skip to: 5627
+/* 4616 */    MCD_OPC_CheckField, 7, 1, 1, 236, 3, 0, // Skip to: 5627
+/* 4623 */    MCD_OPC_Decode, 221, 29, 255, 3, // Opcode: VSTR_FPSCR_off
+/* 4628 */    MCD_OPC_FilterValue, 4, 226, 3, 0, // Skip to: 5627
+/* 4633 */    MCD_OPC_CheckPredicate, 25, 221, 3, 0, // Skip to: 5627
+/* 4638 */    MCD_OPC_CheckField, 24, 4, 13, 214, 3, 0, // Skip to: 5627
+/* 4645 */    MCD_OPC_CheckField, 7, 1, 1, 207, 3, 0, // Skip to: 5627
+/* 4652 */    MCD_OPC_Decode, 218, 29, 255, 3, // Opcode: VSTR_FPSCR_NZCVQC_off
+/* 4657 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 4723
+/* 4662 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 4665 */    MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 4694
+/* 4670 */    MCD_OPC_CheckPredicate, 25, 184, 3, 0, // Skip to: 5627
+/* 4675 */    MCD_OPC_CheckField, 24, 4, 13, 177, 3, 0, // Skip to: 5627
+/* 4682 */    MCD_OPC_CheckField, 7, 1, 1, 170, 3, 0, // Skip to: 5627
+/* 4689 */    MCD_OPC_Decode, 130, 22, 255, 3, // Opcode: VLDR_FPSCR_off
+/* 4694 */    MCD_OPC_FilterValue, 4, 160, 3, 0, // Skip to: 5627
+/* 4699 */    MCD_OPC_CheckPredicate, 25, 155, 3, 0, // Skip to: 5627
+/* 4704 */    MCD_OPC_CheckField, 24, 4, 13, 148, 3, 0, // Skip to: 5627
+/* 4711 */    MCD_OPC_CheckField, 7, 1, 1, 141, 3, 0, // Skip to: 5627
+/* 4718 */    MCD_OPC_Decode, 255, 21, 255, 3, // Opcode: VLDR_FPSCR_NZCVQC_off
+/* 4723 */    MCD_OPC_FilterValue, 2, 107, 0, 0, // Skip to: 4835
+/* 4728 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 4731 */    MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 4783
+/* 4736 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 4739 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4761
+/* 4744 */    MCD_OPC_CheckPredicate, 25, 110, 3, 0, // Skip to: 5627
+/* 4749 */    MCD_OPC_CheckField, 7, 1, 1, 103, 3, 0, // Skip to: 5627
+/* 4756 */    MCD_OPC_Decode, 222, 29, 128, 4, // Opcode: VSTR_FPSCR_post
+/* 4761 */    MCD_OPC_FilterValue, 13, 93, 3, 0, // Skip to: 5627
+/* 4766 */    MCD_OPC_CheckPredicate, 25, 88, 3, 0, // Skip to: 5627
+/* 4771 */    MCD_OPC_CheckField, 7, 1, 1, 81, 3, 0, // Skip to: 5627
+/* 4778 */    MCD_OPC_Decode, 223, 29, 128, 4, // Opcode: VSTR_FPSCR_pre
+/* 4783 */    MCD_OPC_FilterValue, 4, 71, 3, 0, // Skip to: 5627
+/* 4788 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 4791 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4813
+/* 4796 */    MCD_OPC_CheckPredicate, 25, 58, 3, 0, // Skip to: 5627
+/* 4801 */    MCD_OPC_CheckField, 7, 1, 1, 51, 3, 0, // Skip to: 5627
+/* 4808 */    MCD_OPC_Decode, 219, 29, 128, 4, // Opcode: VSTR_FPSCR_NZCVQC_post
+/* 4813 */    MCD_OPC_FilterValue, 13, 41, 3, 0, // Skip to: 5627
+/* 4818 */    MCD_OPC_CheckPredicate, 25, 36, 3, 0, // Skip to: 5627
+/* 4823 */    MCD_OPC_CheckField, 7, 1, 1, 29, 3, 0, // Skip to: 5627
+/* 4830 */    MCD_OPC_Decode, 220, 29, 128, 4, // Opcode: VSTR_FPSCR_NZCVQC_pre
+/* 4835 */    MCD_OPC_FilterValue, 3, 107, 0, 0, // Skip to: 4947
+/* 4840 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 4843 */    MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 4895
+/* 4848 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 4851 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4873
+/* 4856 */    MCD_OPC_CheckPredicate, 25, 254, 2, 0, // Skip to: 5627
+/* 4861 */    MCD_OPC_CheckField, 7, 1, 1, 247, 2, 0, // Skip to: 5627
+/* 4868 */    MCD_OPC_Decode, 131, 22, 128, 4, // Opcode: VLDR_FPSCR_post
+/* 4873 */    MCD_OPC_FilterValue, 13, 237, 2, 0, // Skip to: 5627
+/* 4878 */    MCD_OPC_CheckPredicate, 25, 232, 2, 0, // Skip to: 5627
+/* 4883 */    MCD_OPC_CheckField, 7, 1, 1, 225, 2, 0, // Skip to: 5627
+/* 4890 */    MCD_OPC_Decode, 132, 22, 128, 4, // Opcode: VLDR_FPSCR_pre
+/* 4895 */    MCD_OPC_FilterValue, 4, 215, 2, 0, // Skip to: 5627
+/* 4900 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 4903 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 4925
+/* 4908 */    MCD_OPC_CheckPredicate, 25, 202, 2, 0, // Skip to: 5627
+/* 4913 */    MCD_OPC_CheckField, 7, 1, 1, 195, 2, 0, // Skip to: 5627
+/* 4920 */    MCD_OPC_Decode, 128, 22, 128, 4, // Opcode: VLDR_FPSCR_NZCVQC_post
+/* 4925 */    MCD_OPC_FilterValue, 13, 185, 2, 0, // Skip to: 5627
+/* 4930 */    MCD_OPC_CheckPredicate, 25, 180, 2, 0, // Skip to: 5627
+/* 4935 */    MCD_OPC_CheckField, 7, 1, 1, 173, 2, 0, // Skip to: 5627
+/* 4942 */    MCD_OPC_Decode, 129, 22, 128, 4, // Opcode: VLDR_FPSCR_NZCVQC_pre
+/* 4947 */    MCD_OPC_FilterValue, 4, 119, 0, 0, // Skip to: 5071
+/* 4952 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 4955 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 4984
+/* 4960 */    MCD_OPC_CheckPredicate, 23, 150, 2, 0, // Skip to: 5627
+/* 4965 */    MCD_OPC_CheckField, 24, 4, 13, 143, 2, 0, // Skip to: 5627
+/* 4972 */    MCD_OPC_CheckField, 7, 1, 1, 136, 2, 0, // Skip to: 5627
+/* 4979 */    MCD_OPC_Decode, 227, 29, 255, 3, // Opcode: VSTR_VPR_off
+/* 4984 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 5013
+/* 4989 */    MCD_OPC_CheckPredicate, 23, 121, 2, 0, // Skip to: 5627
+/* 4994 */    MCD_OPC_CheckField, 24, 4, 13, 114, 2, 0, // Skip to: 5627
+/* 5001 */    MCD_OPC_CheckField, 7, 1, 1, 107, 2, 0, // Skip to: 5627
+/* 5008 */    MCD_OPC_Decode, 224, 29, 255, 3, // Opcode: VSTR_P0_off
+/* 5013 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 5042
+/* 5018 */    MCD_OPC_CheckPredicate, 78, 92, 2, 0, // Skip to: 5627
+/* 5023 */    MCD_OPC_CheckField, 24, 4, 13, 85, 2, 0, // Skip to: 5627
+/* 5030 */    MCD_OPC_CheckField, 7, 1, 1, 78, 2, 0, // Skip to: 5627
+/* 5037 */    MCD_OPC_Decode, 212, 29, 255, 3, // Opcode: VSTR_FPCXTNS_off
+/* 5042 */    MCD_OPC_FilterValue, 14, 68, 2, 0, // Skip to: 5627
+/* 5047 */    MCD_OPC_CheckPredicate, 78, 63, 2, 0, // Skip to: 5627
+/* 5052 */    MCD_OPC_CheckField, 24, 4, 13, 56, 2, 0, // Skip to: 5627
+/* 5059 */    MCD_OPC_CheckField, 7, 1, 1, 49, 2, 0, // Skip to: 5627
+/* 5066 */    MCD_OPC_Decode, 215, 29, 255, 3, // Opcode: VSTR_FPCXTS_off
+/* 5071 */    MCD_OPC_FilterValue, 5, 119, 0, 0, // Skip to: 5195
+/* 5076 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 5079 */    MCD_OPC_FilterValue, 8, 24, 0, 0, // Skip to: 5108
+/* 5084 */    MCD_OPC_CheckPredicate, 23, 26, 2, 0, // Skip to: 5627
+/* 5089 */    MCD_OPC_CheckField, 24, 4, 13, 19, 2, 0, // Skip to: 5627
+/* 5096 */    MCD_OPC_CheckField, 7, 1, 1, 12, 2, 0, // Skip to: 5627
+/* 5103 */    MCD_OPC_Decode, 136, 22, 255, 3, // Opcode: VLDR_VPR_off
+/* 5108 */    MCD_OPC_FilterValue, 10, 24, 0, 0, // Skip to: 5137
+/* 5113 */    MCD_OPC_CheckPredicate, 23, 253, 1, 0, // Skip to: 5627
+/* 5118 */    MCD_OPC_CheckField, 24, 4, 13, 246, 1, 0, // Skip to: 5627
+/* 5125 */    MCD_OPC_CheckField, 7, 1, 1, 239, 1, 0, // Skip to: 5627
+/* 5132 */    MCD_OPC_Decode, 133, 22, 255, 3, // Opcode: VLDR_P0_off
+/* 5137 */    MCD_OPC_FilterValue, 12, 24, 0, 0, // Skip to: 5166
+/* 5142 */    MCD_OPC_CheckPredicate, 78, 224, 1, 0, // Skip to: 5627
+/* 5147 */    MCD_OPC_CheckField, 24, 4, 13, 217, 1, 0, // Skip to: 5627
+/* 5154 */    MCD_OPC_CheckField, 7, 1, 1, 210, 1, 0, // Skip to: 5627
+/* 5161 */    MCD_OPC_Decode, 249, 21, 255, 3, // Opcode: VLDR_FPCXTNS_off
+/* 5166 */    MCD_OPC_FilterValue, 14, 200, 1, 0, // Skip to: 5627
+/* 5171 */    MCD_OPC_CheckPredicate, 78, 195, 1, 0, // Skip to: 5627
+/* 5176 */    MCD_OPC_CheckField, 24, 4, 13, 188, 1, 0, // Skip to: 5627
+/* 5183 */    MCD_OPC_CheckField, 7, 1, 1, 181, 1, 0, // Skip to: 5627
+/* 5190 */    MCD_OPC_Decode, 252, 21, 255, 3, // Opcode: VLDR_FPCXTS_off
+/* 5195 */    MCD_OPC_FilterValue, 6, 211, 0, 0, // Skip to: 5411
+/* 5200 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 5203 */    MCD_OPC_FilterValue, 8, 47, 0, 0, // Skip to: 5255
+/* 5208 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5211 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5233
+/* 5216 */    MCD_OPC_CheckPredicate, 23, 150, 1, 0, // Skip to: 5627
+/* 5221 */    MCD_OPC_CheckField, 7, 1, 1, 143, 1, 0, // Skip to: 5627
+/* 5228 */    MCD_OPC_Decode, 228, 29, 128, 4, // Opcode: VSTR_VPR_post
+/* 5233 */    MCD_OPC_FilterValue, 13, 133, 1, 0, // Skip to: 5627
+/* 5238 */    MCD_OPC_CheckPredicate, 23, 128, 1, 0, // Skip to: 5627
+/* 5243 */    MCD_OPC_CheckField, 7, 1, 1, 121, 1, 0, // Skip to: 5627
+/* 5250 */    MCD_OPC_Decode, 229, 29, 128, 4, // Opcode: VSTR_VPR_pre
+/* 5255 */    MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 5307
+/* 5260 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5263 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5285
+/* 5268 */    MCD_OPC_CheckPredicate, 23, 98, 1, 0, // Skip to: 5627
+/* 5273 */    MCD_OPC_CheckField, 7, 1, 1, 91, 1, 0, // Skip to: 5627
+/* 5280 */    MCD_OPC_Decode, 225, 29, 128, 4, // Opcode: VSTR_P0_post
+/* 5285 */    MCD_OPC_FilterValue, 13, 81, 1, 0, // Skip to: 5627
+/* 5290 */    MCD_OPC_CheckPredicate, 23, 76, 1, 0, // Skip to: 5627
+/* 5295 */    MCD_OPC_CheckField, 7, 1, 1, 69, 1, 0, // Skip to: 5627
+/* 5302 */    MCD_OPC_Decode, 226, 29, 128, 4, // Opcode: VSTR_P0_pre
+/* 5307 */    MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 5359
+/* 5312 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5315 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5337
+/* 5320 */    MCD_OPC_CheckPredicate, 78, 46, 1, 0, // Skip to: 5627
+/* 5325 */    MCD_OPC_CheckField, 7, 1, 1, 39, 1, 0, // Skip to: 5627
+/* 5332 */    MCD_OPC_Decode, 213, 29, 128, 4, // Opcode: VSTR_FPCXTNS_post
+/* 5337 */    MCD_OPC_FilterValue, 13, 29, 1, 0, // Skip to: 5627
+/* 5342 */    MCD_OPC_CheckPredicate, 78, 24, 1, 0, // Skip to: 5627
+/* 5347 */    MCD_OPC_CheckField, 7, 1, 1, 17, 1, 0, // Skip to: 5627
+/* 5354 */    MCD_OPC_Decode, 214, 29, 128, 4, // Opcode: VSTR_FPCXTNS_pre
+/* 5359 */    MCD_OPC_FilterValue, 14, 7, 1, 0, // Skip to: 5627
+/* 5364 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5367 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5389
+/* 5372 */    MCD_OPC_CheckPredicate, 78, 250, 0, 0, // Skip to: 5627
+/* 5377 */    MCD_OPC_CheckField, 7, 1, 1, 243, 0, 0, // Skip to: 5627
+/* 5384 */    MCD_OPC_Decode, 216, 29, 128, 4, // Opcode: VSTR_FPCXTS_post
+/* 5389 */    MCD_OPC_FilterValue, 13, 233, 0, 0, // Skip to: 5627
+/* 5394 */    MCD_OPC_CheckPredicate, 78, 228, 0, 0, // Skip to: 5627
+/* 5399 */    MCD_OPC_CheckField, 7, 1, 1, 221, 0, 0, // Skip to: 5627
+/* 5406 */    MCD_OPC_Decode, 217, 29, 128, 4, // Opcode: VSTR_FPCXTS_pre
+/* 5411 */    MCD_OPC_FilterValue, 7, 211, 0, 0, // Skip to: 5627
+/* 5416 */    MCD_OPC_ExtractField, 12, 4,  // Inst{15-12} ...
+/* 5419 */    MCD_OPC_FilterValue, 8, 47, 0, 0, // Skip to: 5471
+/* 5424 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5427 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5449
+/* 5432 */    MCD_OPC_CheckPredicate, 23, 190, 0, 0, // Skip to: 5627
+/* 5437 */    MCD_OPC_CheckField, 7, 1, 1, 183, 0, 0, // Skip to: 5627
+/* 5444 */    MCD_OPC_Decode, 137, 22, 128, 4, // Opcode: VLDR_VPR_post
+/* 5449 */    MCD_OPC_FilterValue, 13, 173, 0, 0, // Skip to: 5627
+/* 5454 */    MCD_OPC_CheckPredicate, 23, 168, 0, 0, // Skip to: 5627
+/* 5459 */    MCD_OPC_CheckField, 7, 1, 1, 161, 0, 0, // Skip to: 5627
+/* 5466 */    MCD_OPC_Decode, 138, 22, 128, 4, // Opcode: VLDR_VPR_pre
+/* 5471 */    MCD_OPC_FilterValue, 10, 47, 0, 0, // Skip to: 5523
+/* 5476 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5479 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5501
+/* 5484 */    MCD_OPC_CheckPredicate, 23, 138, 0, 0, // Skip to: 5627
+/* 5489 */    MCD_OPC_CheckField, 7, 1, 1, 131, 0, 0, // Skip to: 5627
+/* 5496 */    MCD_OPC_Decode, 134, 22, 128, 4, // Opcode: VLDR_P0_post
+/* 5501 */    MCD_OPC_FilterValue, 13, 121, 0, 0, // Skip to: 5627
+/* 5506 */    MCD_OPC_CheckPredicate, 23, 116, 0, 0, // Skip to: 5627
+/* 5511 */    MCD_OPC_CheckField, 7, 1, 1, 109, 0, 0, // Skip to: 5627
+/* 5518 */    MCD_OPC_Decode, 135, 22, 128, 4, // Opcode: VLDR_P0_pre
+/* 5523 */    MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 5575
+/* 5528 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5531 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5553
+/* 5536 */    MCD_OPC_CheckPredicate, 78, 86, 0, 0, // Skip to: 5627
+/* 5541 */    MCD_OPC_CheckField, 7, 1, 1, 79, 0, 0, // Skip to: 5627
+/* 5548 */    MCD_OPC_Decode, 250, 21, 128, 4, // Opcode: VLDR_FPCXTNS_post
+/* 5553 */    MCD_OPC_FilterValue, 13, 69, 0, 0, // Skip to: 5627
+/* 5558 */    MCD_OPC_CheckPredicate, 78, 64, 0, 0, // Skip to: 5627
+/* 5563 */    MCD_OPC_CheckField, 7, 1, 1, 57, 0, 0, // Skip to: 5627
+/* 5570 */    MCD_OPC_Decode, 251, 21, 128, 4, // Opcode: VLDR_FPCXTNS_pre
+/* 5575 */    MCD_OPC_FilterValue, 14, 47, 0, 0, // Skip to: 5627
+/* 5580 */    MCD_OPC_ExtractField, 24, 4,  // Inst{27-24} ...
+/* 5583 */    MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 5605
+/* 5588 */    MCD_OPC_CheckPredicate, 78, 34, 0, 0, // Skip to: 5627
+/* 5593 */    MCD_OPC_CheckField, 7, 1, 1, 27, 0, 0, // Skip to: 5627
+/* 5600 */    MCD_OPC_Decode, 253, 21, 128, 4, // Opcode: VLDR_FPCXTS_post
+/* 5605 */    MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 5627
+/* 5610 */    MCD_OPC_CheckPredicate, 78, 12, 0, 0, // Skip to: 5627
+/* 5615 */    MCD_OPC_CheckField, 7, 1, 1, 5, 0, 0, // Skip to: 5627
+/* 5622 */    MCD_OPC_Decode, 254, 21, 128, 4, // Opcode: VLDR_FPCXTS_pre
+/* 5627 */    MCD_OPC_Fail,
   0
 };
 
 static const uint8_t DecoderTableVFPV832[] = {
 /* 0 */       MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 3 */       MCD_OPC_FilterValue, 8, 87, 1, 0, // Skip to: 351
-/* 8 */       MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 11 */      MCD_OPC_FilterValue, 0, 165, 0, 0, // Skip to: 181
-/* 16 */      MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
-/* 19 */      MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 129
-/* 24 */      MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 27 */      MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 56
-/* 32 */      MCD_OPC_CheckPredicate, 71, 220, 9, 0, // Skip to: 2561
-/* 37 */      MCD_OPC_CheckField, 23, 1, 1, 213, 9, 0, // Skip to: 2561
-/* 44 */      MCD_OPC_CheckField, 4, 1, 0, 206, 9, 0, // Skip to: 2561
-/* 51 */      MCD_OPC_Decode, 152, 8, 230, 2, // Opcode: VCADDv4f16
-/* 56 */      MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 85
-/* 61 */      MCD_OPC_CheckPredicate, 72, 191, 9, 0, // Skip to: 2561
-/* 66 */      MCD_OPC_CheckField, 23, 1, 1, 184, 9, 0, // Skip to: 2561
-/* 73 */      MCD_OPC_CheckField, 4, 1, 0, 177, 9, 0, // Skip to: 2561
-/* 80 */      MCD_OPC_Decode, 151, 8, 230, 2, // Opcode: VCADDv2f32
-/* 85 */      MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 107
-/* 90 */      MCD_OPC_CheckPredicate, 71, 162, 9, 0, // Skip to: 2561
-/* 95 */      MCD_OPC_CheckField, 4, 1, 0, 155, 9, 0, // Skip to: 2561
-/* 102 */     MCD_OPC_Decode, 133, 9, 231, 2, // Opcode: VCMLAv4f16
-/* 107 */     MCD_OPC_FilterValue, 3, 145, 9, 0, // Skip to: 2561
-/* 112 */     MCD_OPC_CheckPredicate, 72, 140, 9, 0, // Skip to: 2561
-/* 117 */     MCD_OPC_CheckField, 4, 1, 0, 133, 9, 0, // Skip to: 2561
-/* 124 */     MCD_OPC_Decode, 131, 9, 231, 2, // Opcode: VCMLAv2f32
-/* 129 */     MCD_OPC_FilterValue, 127, 123, 9, 0, // Skip to: 2561
-/* 134 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 137 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 159
-/* 142 */     MCD_OPC_CheckPredicate, 71, 110, 9, 0, // Skip to: 2561
-/* 147 */     MCD_OPC_CheckField, 4, 1, 0, 103, 9, 0, // Skip to: 2561
-/* 154 */     MCD_OPC_Decode, 134, 9, 232, 2, // Opcode: VCMLAv4f16_indexed
-/* 159 */     MCD_OPC_FilterValue, 1, 93, 9, 0, // Skip to: 2561
-/* 164 */     MCD_OPC_CheckPredicate, 72, 88, 9, 0, // Skip to: 2561
-/* 169 */     MCD_OPC_CheckField, 4, 1, 0, 81, 9, 0, // Skip to: 2561
-/* 176 */     MCD_OPC_Decode, 132, 9, 233, 2, // Opcode: VCMLAv2f32_indexed
-/* 181 */     MCD_OPC_FilterValue, 1, 71, 9, 0, // Skip to: 2561
-/* 186 */     MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
-/* 189 */     MCD_OPC_FilterValue, 126, 105, 0, 0, // Skip to: 299
-/* 194 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 197 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 226
-/* 202 */     MCD_OPC_CheckPredicate, 71, 50, 9, 0, // Skip to: 2561
-/* 207 */     MCD_OPC_CheckField, 23, 1, 1, 43, 9, 0, // Skip to: 2561
-/* 214 */     MCD_OPC_CheckField, 4, 1, 0, 36, 9, 0, // Skip to: 2561
-/* 221 */     MCD_OPC_Decode, 154, 8, 234, 2, // Opcode: VCADDv8f16
-/* 226 */     MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 255
-/* 231 */     MCD_OPC_CheckPredicate, 72, 21, 9, 0, // Skip to: 2561
-/* 236 */     MCD_OPC_CheckField, 23, 1, 1, 14, 9, 0, // Skip to: 2561
-/* 243 */     MCD_OPC_CheckField, 4, 1, 0, 7, 9, 0, // Skip to: 2561
-/* 250 */     MCD_OPC_Decode, 153, 8, 234, 2, // Opcode: VCADDv4f32
-/* 255 */     MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 277
-/* 260 */     MCD_OPC_CheckPredicate, 71, 248, 8, 0, // Skip to: 2561
-/* 265 */     MCD_OPC_CheckField, 4, 1, 0, 241, 8, 0, // Skip to: 2561
-/* 272 */     MCD_OPC_Decode, 137, 9, 235, 2, // Opcode: VCMLAv8f16
-/* 277 */     MCD_OPC_FilterValue, 3, 231, 8, 0, // Skip to: 2561
-/* 282 */     MCD_OPC_CheckPredicate, 72, 226, 8, 0, // Skip to: 2561
-/* 287 */     MCD_OPC_CheckField, 4, 1, 0, 219, 8, 0, // Skip to: 2561
-/* 294 */     MCD_OPC_Decode, 135, 9, 235, 2, // Opcode: VCMLAv4f32
-/* 299 */     MCD_OPC_FilterValue, 127, 209, 8, 0, // Skip to: 2561
-/* 304 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
-/* 307 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 329
-/* 312 */     MCD_OPC_CheckPredicate, 71, 196, 8, 0, // Skip to: 2561
-/* 317 */     MCD_OPC_CheckField, 4, 1, 0, 189, 8, 0, // Skip to: 2561
-/* 324 */     MCD_OPC_Decode, 138, 9, 236, 2, // Opcode: VCMLAv8f16_indexed
-/* 329 */     MCD_OPC_FilterValue, 1, 179, 8, 0, // Skip to: 2561
-/* 334 */     MCD_OPC_CheckPredicate, 72, 174, 8, 0, // Skip to: 2561
-/* 339 */     MCD_OPC_CheckField, 4, 1, 0, 167, 8, 0, // Skip to: 2561
-/* 346 */     MCD_OPC_Decode, 136, 9, 233, 2, // Opcode: VCMLAv4f32_indexed
-/* 351 */     MCD_OPC_FilterValue, 9, 123, 2, 0, // Skip to: 991
-/* 356 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 359 */     MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 451
-/* 364 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 367 */     MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 421
-/* 372 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 375 */     MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 398
-/* 381 */     MCD_OPC_CheckPredicate, 60, 127, 8, 0, // Skip to: 2561
-/* 386 */     MCD_OPC_CheckField, 4, 1, 0, 120, 8, 0, // Skip to: 2561
-/* 393 */     MCD_OPC_Decode, 233, 17, 237, 2, // Opcode: VSELEQH
-/* 398 */     MCD_OPC_FilterValue, 253, 3, 109, 8, 0, // Skip to: 2561
-/* 404 */     MCD_OPC_CheckPredicate, 60, 104, 8, 0, // Skip to: 2561
-/* 409 */     MCD_OPC_CheckField, 4, 1, 0, 97, 8, 0, // Skip to: 2561
-/* 416 */     MCD_OPC_Decode, 157, 13, 237, 2, // Opcode: VMAXNMH
-/* 421 */     MCD_OPC_FilterValue, 1, 87, 8, 0, // Skip to: 2561
-/* 426 */     MCD_OPC_CheckPredicate, 60, 82, 8, 0, // Skip to: 2561
-/* 431 */     MCD_OPC_CheckField, 23, 9, 253, 3, 74, 8, 0, // Skip to: 2561
-/* 439 */     MCD_OPC_CheckField, 4, 1, 0, 67, 8, 0, // Skip to: 2561
-/* 446 */     MCD_OPC_Decode, 180, 13, 237, 2, // Opcode: VMINNMH
-/* 451 */     MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 488
-/* 456 */     MCD_OPC_CheckPredicate, 60, 52, 8, 0, // Skip to: 2561
-/* 461 */     MCD_OPC_CheckField, 23, 9, 252, 3, 44, 8, 0, // Skip to: 2561
-/* 469 */     MCD_OPC_CheckField, 6, 1, 0, 37, 8, 0, // Skip to: 2561
-/* 476 */     MCD_OPC_CheckField, 4, 1, 0, 30, 8, 0, // Skip to: 2561
-/* 483 */     MCD_OPC_Decode, 242, 17, 237, 2, // Opcode: VSELVSH
-/* 488 */     MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 525
-/* 493 */     MCD_OPC_CheckPredicate, 60, 15, 8, 0, // Skip to: 2561
-/* 498 */     MCD_OPC_CheckField, 23, 9, 252, 3, 7, 8, 0, // Skip to: 2561
-/* 506 */     MCD_OPC_CheckField, 6, 1, 0, 0, 8, 0, // Skip to: 2561
-/* 513 */     MCD_OPC_CheckField, 4, 1, 0, 249, 7, 0, // Skip to: 2561
-/* 520 */     MCD_OPC_Decode, 236, 17, 237, 2, // Opcode: VSELGEH
-/* 525 */     MCD_OPC_FilterValue, 3, 239, 7, 0, // Skip to: 2561
-/* 530 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 533 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 563
-/* 538 */     MCD_OPC_CheckPredicate, 60, 226, 7, 0, // Skip to: 2561
-/* 543 */     MCD_OPC_CheckField, 23, 9, 252, 3, 218, 7, 0, // Skip to: 2561
-/* 551 */     MCD_OPC_CheckField, 4, 1, 0, 211, 7, 0, // Skip to: 2561
-/* 558 */     MCD_OPC_Decode, 239, 17, 237, 2, // Opcode: VSELGTH
-/* 563 */     MCD_OPC_FilterValue, 1, 201, 7, 0, // Skip to: 2561
-/* 568 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 571 */     MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 608
-/* 576 */     MCD_OPC_CheckPredicate, 60, 188, 7, 0, // Skip to: 2561
-/* 581 */     MCD_OPC_CheckField, 23, 9, 253, 3, 180, 7, 0, // Skip to: 2561
-/* 589 */     MCD_OPC_CheckField, 7, 1, 0, 173, 7, 0, // Skip to: 2561
-/* 596 */     MCD_OPC_CheckField, 4, 1, 0, 166, 7, 0, // Skip to: 2561
-/* 603 */     MCD_OPC_Decode, 248, 16, 238, 2, // Opcode: VRINTAH
-/* 608 */     MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 645
-/* 613 */     MCD_OPC_CheckPredicate, 60, 151, 7, 0, // Skip to: 2561
-/* 618 */     MCD_OPC_CheckField, 23, 9, 253, 3, 143, 7, 0, // Skip to: 2561
-/* 626 */     MCD_OPC_CheckField, 7, 1, 0, 136, 7, 0, // Skip to: 2561
-/* 633 */     MCD_OPC_CheckField, 4, 1, 0, 129, 7, 0, // Skip to: 2561
-/* 640 */     MCD_OPC_Decode, 134, 17, 238, 2, // Opcode: VRINTNH
-/* 645 */     MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 682
-/* 650 */     MCD_OPC_CheckPredicate, 60, 114, 7, 0, // Skip to: 2561
-/* 655 */     MCD_OPC_CheckField, 23, 9, 253, 3, 106, 7, 0, // Skip to: 2561
-/* 663 */     MCD_OPC_CheckField, 7, 1, 0, 99, 7, 0, // Skip to: 2561
-/* 670 */     MCD_OPC_CheckField, 4, 1, 0, 92, 7, 0, // Skip to: 2561
-/* 677 */     MCD_OPC_Decode, 141, 17, 238, 2, // Opcode: VRINTPH
-/* 682 */     MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 719
-/* 687 */     MCD_OPC_CheckPredicate, 60, 77, 7, 0, // Skip to: 2561
-/* 692 */     MCD_OPC_CheckField, 23, 9, 253, 3, 69, 7, 0, // Skip to: 2561
-/* 700 */     MCD_OPC_CheckField, 7, 1, 0, 62, 7, 0, // Skip to: 2561
-/* 707 */     MCD_OPC_CheckField, 4, 1, 0, 55, 7, 0, // Skip to: 2561
-/* 714 */     MCD_OPC_Decode, 255, 16, 238, 2, // Opcode: VRINTMH
-/* 719 */     MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 787
-/* 724 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 727 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 757
-/* 732 */     MCD_OPC_CheckPredicate, 60, 32, 7, 0, // Skip to: 2561
-/* 737 */     MCD_OPC_CheckField, 23, 9, 253, 3, 24, 7, 0, // Skip to: 2561
-/* 745 */     MCD_OPC_CheckField, 4, 1, 0, 17, 7, 0, // Skip to: 2561
-/* 752 */     MCD_OPC_Decode, 165, 9, 239, 2, // Opcode: VCVTAUH
-/* 757 */     MCD_OPC_FilterValue, 1, 7, 7, 0, // Skip to: 2561
-/* 762 */     MCD_OPC_CheckPredicate, 60, 2, 7, 0, // Skip to: 2561
-/* 767 */     MCD_OPC_CheckField, 23, 9, 253, 3, 250, 6, 0, // Skip to: 2561
-/* 775 */     MCD_OPC_CheckField, 4, 1, 0, 243, 6, 0, // Skip to: 2561
-/* 782 */     MCD_OPC_Decode, 162, 9, 239, 2, // Opcode: VCVTASH
-/* 787 */     MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 855
+/* 3 */       MCD_OPC_FilterValue, 8, 47, 2, 0, // Skip to: 567
+/* 8 */       MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 11 */      MCD_OPC_FilterValue, 0, 3, 1, 0, // Skip to: 275
+/* 16 */      MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 19 */      MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 147
+/* 24 */      MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
+/* 27 */      MCD_OPC_FilterValue, 126, 77, 0, 0, // Skip to: 109
+/* 32 */      MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 35 */      MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57
+/* 40 */      MCD_OPC_CheckPredicate, 91, 119, 12, 0, // Skip to: 3236
+/* 45 */      MCD_OPC_CheckField, 23, 1, 1, 112, 12, 0, // Skip to: 3236
+/* 52 */      MCD_OPC_Decode, 201, 16, 129, 4, // Opcode: VCADDv4f16
+/* 57 */      MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 79
+/* 62 */      MCD_OPC_CheckPredicate, 92, 97, 12, 0, // Skip to: 3236
+/* 67 */      MCD_OPC_CheckField, 23, 1, 1, 90, 12, 0, // Skip to: 3236
+/* 74 */      MCD_OPC_Decode, 200, 16, 129, 4, // Opcode: VCADDv2f32
+/* 79 */      MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 94
+/* 84 */      MCD_OPC_CheckPredicate, 91, 75, 12, 0, // Skip to: 3236
+/* 89 */      MCD_OPC_Decode, 182, 17, 130, 4, // Opcode: VCMLAv4f16
+/* 94 */      MCD_OPC_FilterValue, 3, 65, 12, 0, // Skip to: 3236
+/* 99 */      MCD_OPC_CheckPredicate, 92, 60, 12, 0, // Skip to: 3236
+/* 104 */     MCD_OPC_Decode, 180, 17, 130, 4, // Opcode: VCMLAv2f32
+/* 109 */     MCD_OPC_FilterValue, 127, 50, 12, 0, // Skip to: 3236
+/* 114 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 117 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 132
+/* 122 */     MCD_OPC_CheckPredicate, 91, 37, 12, 0, // Skip to: 3236
+/* 127 */     MCD_OPC_Decode, 183, 17, 131, 4, // Opcode: VCMLAv4f16_indexed
+/* 132 */     MCD_OPC_FilterValue, 1, 27, 12, 0, // Skip to: 3236
+/* 137 */     MCD_OPC_CheckPredicate, 92, 22, 12, 0, // Skip to: 3236
+/* 142 */     MCD_OPC_Decode, 181, 17, 132, 4, // Opcode: VCMLAv2f32_indexed
+/* 147 */     MCD_OPC_FilterValue, 1, 12, 12, 0, // Skip to: 3236
+/* 152 */     MCD_OPC_ExtractField, 25, 7,  // Inst{31-25} ...
+/* 155 */     MCD_OPC_FilterValue, 126, 77, 0, 0, // Skip to: 237
+/* 160 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 163 */     MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 185
+/* 168 */     MCD_OPC_CheckPredicate, 91, 247, 11, 0, // Skip to: 3236
+/* 173 */     MCD_OPC_CheckField, 23, 1, 1, 240, 11, 0, // Skip to: 3236
+/* 180 */     MCD_OPC_Decode, 203, 16, 133, 4, // Opcode: VCADDv8f16
+/* 185 */     MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 207
+/* 190 */     MCD_OPC_CheckPredicate, 92, 225, 11, 0, // Skip to: 3236
+/* 195 */     MCD_OPC_CheckField, 23, 1, 1, 218, 11, 0, // Skip to: 3236
+/* 202 */     MCD_OPC_Decode, 202, 16, 133, 4, // Opcode: VCADDv4f32
+/* 207 */     MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 222
+/* 212 */     MCD_OPC_CheckPredicate, 91, 203, 11, 0, // Skip to: 3236
+/* 217 */     MCD_OPC_Decode, 186, 17, 134, 4, // Opcode: VCMLAv8f16
+/* 222 */     MCD_OPC_FilterValue, 3, 193, 11, 0, // Skip to: 3236
+/* 227 */     MCD_OPC_CheckPredicate, 92, 188, 11, 0, // Skip to: 3236
+/* 232 */     MCD_OPC_Decode, 184, 17, 134, 4, // Opcode: VCMLAv4f32
+/* 237 */     MCD_OPC_FilterValue, 127, 178, 11, 0, // Skip to: 3236
+/* 242 */     MCD_OPC_ExtractField, 23, 2,  // Inst{24-23} ...
+/* 245 */     MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 260
+/* 250 */     MCD_OPC_CheckPredicate, 91, 165, 11, 0, // Skip to: 3236
+/* 255 */     MCD_OPC_Decode, 187, 17, 135, 4, // Opcode: VCMLAv8f16_indexed
+/* 260 */     MCD_OPC_FilterValue, 1, 155, 11, 0, // Skip to: 3236
+/* 265 */     MCD_OPC_CheckPredicate, 92, 150, 11, 0, // Skip to: 3236
+/* 270 */     MCD_OPC_Decode, 185, 17, 132, 4, // Opcode: VCMLAv4f32_indexed
+/* 275 */     MCD_OPC_FilterValue, 1, 140, 11, 0, // Skip to: 3236
+/* 280 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 283 */     MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 337
+/* 288 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 291 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 314
+/* 296 */     MCD_OPC_CheckPredicate, 93, 119, 11, 0, // Skip to: 3236
+/* 301 */     MCD_OPC_CheckField, 23, 9, 252, 3, 111, 11, 0, // Skip to: 3236
+/* 309 */     MCD_OPC_Decode, 201, 18, 136, 4, // Opcode: VFMALDI
+/* 314 */     MCD_OPC_FilterValue, 1, 101, 11, 0, // Skip to: 3236
+/* 319 */     MCD_OPC_CheckPredicate, 93, 96, 11, 0, // Skip to: 3236
+/* 324 */     MCD_OPC_CheckField, 23, 9, 252, 3, 88, 11, 0, // Skip to: 3236
+/* 332 */     MCD_OPC_Decode, 203, 18, 217, 1, // Opcode: VFMALQI
+/* 337 */     MCD_OPC_FilterValue, 1, 49, 0, 0, // Skip to: 391
+/* 342 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 345 */     MCD_OPC_FilterValue, 0, 18, 0, 0, // Skip to: 368
+/* 350 */     MCD_OPC_CheckPredicate, 93, 65, 11, 0, // Skip to: 3236
+/* 355 */     MCD_OPC_CheckField, 23, 9, 252, 3, 57, 11, 0, // Skip to: 3236
+/* 363 */     MCD_OPC_Decode, 212, 18, 136, 4, // Opcode: VFMSLDI
+/* 368 */     MCD_OPC_FilterValue, 1, 47, 11, 0, // Skip to: 3236
+/* 373 */     MCD_OPC_CheckPredicate, 93, 42, 11, 0, // Skip to: 3236
+/* 378 */     MCD_OPC_CheckField, 23, 9, 252, 3, 34, 11, 0, // Skip to: 3236
+/* 386 */     MCD_OPC_Decode, 214, 18, 217, 1, // Opcode: VFMSLQI
+/* 391 */     MCD_OPC_FilterValue, 2, 83, 0, 0, // Skip to: 479
+/* 396 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 399 */     MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 439
+/* 404 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 407 */     MCD_OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 423
+/* 413 */     MCD_OPC_CheckPredicate, 93, 2, 11, 0, // Skip to: 3236
+/* 418 */     MCD_OPC_Decode, 200, 18, 137, 4, // Opcode: VFMALD
+/* 423 */     MCD_OPC_FilterValue, 249, 3, 247, 10, 0, // Skip to: 3236
+/* 429 */     MCD_OPC_CheckPredicate, 93, 242, 10, 0, // Skip to: 3236
+/* 434 */     MCD_OPC_Decode, 211, 18, 137, 4, // Opcode: VFMSLD
+/* 439 */     MCD_OPC_FilterValue, 1, 232, 10, 0, // Skip to: 3236
+/* 444 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 447 */     MCD_OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 463
+/* 453 */     MCD_OPC_CheckPredicate, 93, 218, 10, 0, // Skip to: 3236
+/* 458 */     MCD_OPC_Decode, 202, 18, 204, 1, // Opcode: VFMALQ
+/* 463 */     MCD_OPC_FilterValue, 249, 3, 207, 10, 0, // Skip to: 3236
+/* 469 */     MCD_OPC_CheckPredicate, 93, 202, 10, 0, // Skip to: 3236
+/* 474 */     MCD_OPC_Decode, 213, 18, 204, 1, // Opcode: VFMSLQ
+/* 479 */     MCD_OPC_FilterValue, 3, 192, 10, 0, // Skip to: 3236
+/* 484 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 487 */     MCD_OPC_FilterValue, 0, 35, 0, 0, // Skip to: 527
+/* 492 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 495 */     MCD_OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 511
+/* 501 */     MCD_OPC_CheckPredicate, 31, 170, 10, 0, // Skip to: 3236
+/* 506 */     MCD_OPC_Decode, 182, 16, 211, 1, // Opcode: VBF16MALBQ
+/* 511 */     MCD_OPC_FilterValue, 252, 3, 159, 10, 0, // Skip to: 3236
+/* 517 */     MCD_OPC_CheckPredicate, 31, 154, 10, 0, // Skip to: 3236
+/* 522 */     MCD_OPC_Decode, 183, 16, 213, 1, // Opcode: VBF16MALBQI
+/* 527 */     MCD_OPC_FilterValue, 1, 144, 10, 0, // Skip to: 3236
+/* 532 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 535 */     MCD_OPC_FilterValue, 248, 3, 10, 0, 0, // Skip to: 551
+/* 541 */     MCD_OPC_CheckPredicate, 31, 130, 10, 0, // Skip to: 3236
+/* 546 */     MCD_OPC_Decode, 184, 16, 211, 1, // Opcode: VBF16MALTQ
+/* 551 */     MCD_OPC_FilterValue, 252, 3, 119, 10, 0, // Skip to: 3236
+/* 557 */     MCD_OPC_CheckPredicate, 31, 114, 10, 0, // Skip to: 3236
+/* 562 */     MCD_OPC_Decode, 185, 16, 213, 1, // Opcode: VBF16MALTQI
+/* 567 */     MCD_OPC_FilterValue, 9, 189, 2, 0, // Skip to: 1273
+/* 572 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 575 */     MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 667
+/* 580 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 583 */     MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 637
+/* 588 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 591 */     MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 614
+/* 597 */     MCD_OPC_CheckPredicate, 77, 74, 10, 0, // Skip to: 3236
+/* 602 */     MCD_OPC_CheckField, 4, 1, 0, 67, 10, 0, // Skip to: 3236
+/* 609 */     MCD_OPC_Decode, 217, 26, 138, 4, // Opcode: VSELEQH
+/* 614 */     MCD_OPC_FilterValue, 253, 3, 56, 10, 0, // Skip to: 3236
+/* 620 */     MCD_OPC_CheckPredicate, 77, 51, 10, 0, // Skip to: 3236
+/* 625 */     MCD_OPC_CheckField, 4, 1, 0, 44, 10, 0, // Skip to: 3236
+/* 632 */     MCD_OPC_Decode, 227, 18, 138, 4, // Opcode: VFP_VMAXNMH
+/* 637 */     MCD_OPC_FilterValue, 1, 34, 10, 0, // Skip to: 3236
+/* 642 */     MCD_OPC_CheckPredicate, 77, 29, 10, 0, // Skip to: 3236
+/* 647 */     MCD_OPC_CheckField, 23, 9, 253, 3, 21, 10, 0, // Skip to: 3236
+/* 655 */     MCD_OPC_CheckField, 4, 1, 0, 14, 10, 0, // Skip to: 3236
+/* 662 */     MCD_OPC_Decode, 230, 18, 138, 4, // Opcode: VFP_VMINNMH
+/* 667 */     MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 704
+/* 672 */     MCD_OPC_CheckPredicate, 77, 255, 9, 0, // Skip to: 3236
+/* 677 */     MCD_OPC_CheckField, 23, 9, 252, 3, 247, 9, 0, // Skip to: 3236
+/* 685 */     MCD_OPC_CheckField, 6, 1, 0, 240, 9, 0, // Skip to: 3236
+/* 692 */     MCD_OPC_CheckField, 4, 1, 0, 233, 9, 0, // Skip to: 3236
+/* 699 */     MCD_OPC_Decode, 226, 26, 138, 4, // Opcode: VSELVSH
+/* 704 */     MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 741
+/* 709 */     MCD_OPC_CheckPredicate, 77, 218, 9, 0, // Skip to: 3236
+/* 714 */     MCD_OPC_CheckField, 23, 9, 252, 3, 210, 9, 0, // Skip to: 3236
+/* 722 */     MCD_OPC_CheckField, 6, 1, 0, 203, 9, 0, // Skip to: 3236
+/* 729 */     MCD_OPC_CheckField, 4, 1, 0, 196, 9, 0, // Skip to: 3236
+/* 736 */     MCD_OPC_Decode, 220, 26, 138, 4, // Opcode: VSELGEH
+/* 741 */     MCD_OPC_FilterValue, 3, 186, 9, 0, // Skip to: 3236
+/* 746 */     MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 749 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 779
+/* 754 */     MCD_OPC_CheckPredicate, 77, 173, 9, 0, // Skip to: 3236
+/* 759 */     MCD_OPC_CheckField, 23, 9, 252, 3, 165, 9, 0, // Skip to: 3236
+/* 767 */     MCD_OPC_CheckField, 4, 1, 0, 158, 9, 0, // Skip to: 3236
+/* 774 */     MCD_OPC_Decode, 223, 26, 138, 4, // Opcode: VSELGTH
+/* 779 */     MCD_OPC_FilterValue, 1, 148, 9, 0, // Skip to: 3236
+/* 784 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 787 */     MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 853
 /* 792 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 795 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 825
-/* 800 */     MCD_OPC_CheckPredicate, 60, 220, 6, 0, // Skip to: 2561
-/* 805 */     MCD_OPC_CheckField, 23, 9, 253, 3, 212, 6, 0, // Skip to: 2561
-/* 813 */     MCD_OPC_CheckField, 4, 1, 0, 205, 6, 0, // Skip to: 2561
-/* 820 */     MCD_OPC_Decode, 198, 9, 239, 2, // Opcode: VCVTNUH
-/* 825 */     MCD_OPC_FilterValue, 1, 195, 6, 0, // Skip to: 2561
-/* 830 */     MCD_OPC_CheckPredicate, 60, 190, 6, 0, // Skip to: 2561
-/* 835 */     MCD_OPC_CheckField, 23, 9, 253, 3, 182, 6, 0, // Skip to: 2561
-/* 843 */     MCD_OPC_CheckField, 4, 1, 0, 175, 6, 0, // Skip to: 2561
-/* 850 */     MCD_OPC_Decode, 195, 9, 239, 2, // Opcode: VCVTNSH
-/* 855 */     MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 923
-/* 860 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 863 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 893
-/* 868 */     MCD_OPC_CheckPredicate, 60, 152, 6, 0, // Skip to: 2561
-/* 873 */     MCD_OPC_CheckField, 23, 9, 253, 3, 144, 6, 0, // Skip to: 2561
-/* 881 */     MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2561
-/* 888 */     MCD_OPC_Decode, 212, 9, 239, 2, // Opcode: VCVTPUH
-/* 893 */     MCD_OPC_FilterValue, 1, 127, 6, 0, // Skip to: 2561
-/* 898 */     MCD_OPC_CheckPredicate, 60, 122, 6, 0, // Skip to: 2561
-/* 903 */     MCD_OPC_CheckField, 23, 9, 253, 3, 114, 6, 0, // Skip to: 2561
-/* 911 */     MCD_OPC_CheckField, 4, 1, 0, 107, 6, 0, // Skip to: 2561
-/* 918 */     MCD_OPC_Decode, 209, 9, 239, 2, // Opcode: VCVTPSH
-/* 923 */     MCD_OPC_FilterValue, 15, 97, 6, 0, // Skip to: 2561
-/* 928 */     MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 931 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 961
-/* 936 */     MCD_OPC_CheckPredicate, 60, 84, 6, 0, // Skip to: 2561
-/* 941 */     MCD_OPC_CheckField, 23, 9, 253, 3, 76, 6, 0, // Skip to: 2561
-/* 949 */     MCD_OPC_CheckField, 4, 1, 0, 69, 6, 0, // Skip to: 2561
-/* 956 */     MCD_OPC_Decode, 184, 9, 239, 2, // Opcode: VCVTMUH
-/* 961 */     MCD_OPC_FilterValue, 1, 59, 6, 0, // Skip to: 2561
-/* 966 */     MCD_OPC_CheckPredicate, 60, 54, 6, 0, // Skip to: 2561
-/* 971 */     MCD_OPC_CheckField, 23, 9, 253, 3, 46, 6, 0, // Skip to: 2561
-/* 979 */     MCD_OPC_CheckField, 4, 1, 0, 39, 6, 0, // Skip to: 2561
-/* 986 */     MCD_OPC_Decode, 181, 9, 239, 2, // Opcode: VCVTMSH
-/* 991 */     MCD_OPC_FilterValue, 10, 191, 2, 0, // Skip to: 1699
-/* 996 */     MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 999 */     MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 1091
-/* 1004 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1007 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 1061
-/* 1012 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1015 */    MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 1038
-/* 1021 */    MCD_OPC_CheckPredicate, 66, 255, 5, 0, // Skip to: 2561
-/* 1026 */    MCD_OPC_CheckField, 4, 1, 0, 248, 5, 0, // Skip to: 2561
-/* 1033 */    MCD_OPC_Decode, 234, 17, 240, 2, // Opcode: VSELEQS
-/* 1038 */    MCD_OPC_FilterValue, 253, 3, 237, 5, 0, // Skip to: 2561
-/* 1044 */    MCD_OPC_CheckPredicate, 66, 232, 5, 0, // Skip to: 2561
-/* 1049 */    MCD_OPC_CheckField, 4, 1, 0, 225, 5, 0, // Skip to: 2561
-/* 1056 */    MCD_OPC_Decode, 162, 13, 240, 2, // Opcode: VMAXNMS
-/* 1061 */    MCD_OPC_FilterValue, 1, 215, 5, 0, // Skip to: 2561
-/* 1066 */    MCD_OPC_CheckPredicate, 66, 210, 5, 0, // Skip to: 2561
-/* 1071 */    MCD_OPC_CheckField, 23, 9, 253, 3, 202, 5, 0, // Skip to: 2561
-/* 1079 */    MCD_OPC_CheckField, 4, 1, 0, 195, 5, 0, // Skip to: 2561
-/* 1086 */    MCD_OPC_Decode, 185, 13, 240, 2, // Opcode: VMINNMS
-/* 1091 */    MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 1128
-/* 1096 */    MCD_OPC_CheckPredicate, 66, 180, 5, 0, // Skip to: 2561
-/* 1101 */    MCD_OPC_CheckField, 23, 9, 252, 3, 172, 5, 0, // Skip to: 2561
-/* 1109 */    MCD_OPC_CheckField, 6, 1, 0, 165, 5, 0, // Skip to: 2561
-/* 1116 */    MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2561
-/* 1123 */    MCD_OPC_Decode, 243, 17, 240, 2, // Opcode: VSELVSS
-/* 1128 */    MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 1165
-/* 1133 */    MCD_OPC_CheckPredicate, 66, 143, 5, 0, // Skip to: 2561
-/* 1138 */    MCD_OPC_CheckField, 23, 9, 252, 3, 135, 5, 0, // Skip to: 2561
-/* 1146 */    MCD_OPC_CheckField, 6, 1, 0, 128, 5, 0, // Skip to: 2561
-/* 1153 */    MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2561
-/* 1160 */    MCD_OPC_Decode, 237, 17, 240, 2, // Opcode: VSELGES
-/* 1165 */    MCD_OPC_FilterValue, 3, 111, 5, 0, // Skip to: 2561
-/* 1170 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1173 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1203
-/* 1178 */    MCD_OPC_CheckPredicate, 66, 98, 5, 0, // Skip to: 2561
-/* 1183 */    MCD_OPC_CheckField, 23, 9, 252, 3, 90, 5, 0, // Skip to: 2561
-/* 1191 */    MCD_OPC_CheckField, 4, 1, 0, 83, 5, 0, // Skip to: 2561
-/* 1198 */    MCD_OPC_Decode, 240, 17, 240, 2, // Opcode: VSELGTS
-/* 1203 */    MCD_OPC_FilterValue, 1, 73, 5, 0, // Skip to: 2561
-/* 1208 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 1211 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1279
-/* 1216 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 1219 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1249
-/* 1224 */    MCD_OPC_CheckPredicate, 60, 52, 5, 0, // Skip to: 2561
-/* 1229 */    MCD_OPC_CheckField, 23, 9, 253, 3, 44, 5, 0, // Skip to: 2561
-/* 1237 */    MCD_OPC_CheckField, 4, 1, 0, 37, 5, 0, // Skip to: 2561
-/* 1244 */    MCD_OPC_Decode, 138, 14, 238, 2, // Opcode: VMOVH
-/* 1249 */    MCD_OPC_FilterValue, 1, 27, 5, 0, // Skip to: 2561
-/* 1254 */    MCD_OPC_CheckPredicate, 60, 22, 5, 0, // Skip to: 2561
-/* 1259 */    MCD_OPC_CheckField, 23, 9, 253, 3, 14, 5, 0, // Skip to: 2561
-/* 1267 */    MCD_OPC_CheckField, 4, 1, 0, 7, 5, 0, // Skip to: 2561
-/* 1274 */    MCD_OPC_Decode, 198, 10, 238, 2, // Opcode: VINSH
-/* 1279 */    MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 1316
-/* 1284 */    MCD_OPC_CheckPredicate, 66, 248, 4, 0, // Skip to: 2561
-/* 1289 */    MCD_OPC_CheckField, 23, 9, 253, 3, 240, 4, 0, // Skip to: 2561
-/* 1297 */    MCD_OPC_CheckField, 7, 1, 0, 233, 4, 0, // Skip to: 2561
-/* 1304 */    MCD_OPC_CheckField, 4, 1, 0, 226, 4, 0, // Skip to: 2561
-/* 1311 */    MCD_OPC_Decode, 253, 16, 238, 2, // Opcode: VRINTAS
-/* 1316 */    MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 1353
-/* 1321 */    MCD_OPC_CheckPredicate, 66, 211, 4, 0, // Skip to: 2561
-/* 1326 */    MCD_OPC_CheckField, 23, 9, 253, 3, 203, 4, 0, // Skip to: 2561
-/* 1334 */    MCD_OPC_CheckField, 7, 1, 0, 196, 4, 0, // Skip to: 2561
-/* 1341 */    MCD_OPC_CheckField, 4, 1, 0, 189, 4, 0, // Skip to: 2561
-/* 1348 */    MCD_OPC_Decode, 139, 17, 238, 2, // Opcode: VRINTNS
-/* 1353 */    MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 1390
-/* 1358 */    MCD_OPC_CheckPredicate, 66, 174, 4, 0, // Skip to: 2561
-/* 1363 */    MCD_OPC_CheckField, 23, 9, 253, 3, 166, 4, 0, // Skip to: 2561
-/* 1371 */    MCD_OPC_CheckField, 7, 1, 0, 159, 4, 0, // Skip to: 2561
-/* 1378 */    MCD_OPC_CheckField, 4, 1, 0, 152, 4, 0, // Skip to: 2561
-/* 1385 */    MCD_OPC_Decode, 146, 17, 238, 2, // Opcode: VRINTPS
-/* 1390 */    MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 1427
-/* 1395 */    MCD_OPC_CheckPredicate, 66, 137, 4, 0, // Skip to: 2561
-/* 1400 */    MCD_OPC_CheckField, 23, 9, 253, 3, 129, 4, 0, // Skip to: 2561
-/* 1408 */    MCD_OPC_CheckField, 7, 1, 0, 122, 4, 0, // Skip to: 2561
-/* 1415 */    MCD_OPC_CheckField, 4, 1, 0, 115, 4, 0, // Skip to: 2561
-/* 1422 */    MCD_OPC_Decode, 132, 17, 238, 2, // Opcode: VRINTMS
-/* 1427 */    MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 1495
-/* 1432 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 1435 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1465
-/* 1440 */    MCD_OPC_CheckPredicate, 66, 92, 4, 0, // Skip to: 2561
-/* 1445 */    MCD_OPC_CheckField, 23, 9, 253, 3, 84, 4, 0, // Skip to: 2561
-/* 1453 */    MCD_OPC_CheckField, 4, 1, 0, 77, 4, 0, // Skip to: 2561
-/* 1460 */    MCD_OPC_Decode, 166, 9, 238, 2, // Opcode: VCVTAUS
-/* 1465 */    MCD_OPC_FilterValue, 1, 67, 4, 0, // Skip to: 2561
-/* 1470 */    MCD_OPC_CheckPredicate, 66, 62, 4, 0, // Skip to: 2561
-/* 1475 */    MCD_OPC_CheckField, 23, 9, 253, 3, 54, 4, 0, // Skip to: 2561
-/* 1483 */    MCD_OPC_CheckField, 4, 1, 0, 47, 4, 0, // Skip to: 2561
-/* 1490 */    MCD_OPC_Decode, 163, 9, 238, 2, // Opcode: VCVTASS
-/* 1495 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1563
-/* 1500 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 1503 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1533
-/* 1508 */    MCD_OPC_CheckPredicate, 66, 24, 4, 0, // Skip to: 2561
-/* 1513 */    MCD_OPC_CheckField, 23, 9, 253, 3, 16, 4, 0, // Skip to: 2561
-/* 1521 */    MCD_OPC_CheckField, 4, 1, 0, 9, 4, 0, // Skip to: 2561
-/* 1528 */    MCD_OPC_Decode, 199, 9, 238, 2, // Opcode: VCVTNUS
-/* 1533 */    MCD_OPC_FilterValue, 1, 255, 3, 0, // Skip to: 2561
-/* 1538 */    MCD_OPC_CheckPredicate, 66, 250, 3, 0, // Skip to: 2561
-/* 1543 */    MCD_OPC_CheckField, 23, 9, 253, 3, 242, 3, 0, // Skip to: 2561
-/* 1551 */    MCD_OPC_CheckField, 4, 1, 0, 235, 3, 0, // Skip to: 2561
-/* 1558 */    MCD_OPC_Decode, 196, 9, 238, 2, // Opcode: VCVTNSS
-/* 1563 */    MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 1631
-/* 1568 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 1571 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1601
-/* 1576 */    MCD_OPC_CheckPredicate, 66, 212, 3, 0, // Skip to: 2561
-/* 1581 */    MCD_OPC_CheckField, 23, 9, 253, 3, 204, 3, 0, // Skip to: 2561
-/* 1589 */    MCD_OPC_CheckField, 4, 1, 0, 197, 3, 0, // Skip to: 2561
-/* 1596 */    MCD_OPC_Decode, 213, 9, 238, 2, // Opcode: VCVTPUS
-/* 1601 */    MCD_OPC_FilterValue, 1, 187, 3, 0, // Skip to: 2561
-/* 1606 */    MCD_OPC_CheckPredicate, 66, 182, 3, 0, // Skip to: 2561
-/* 1611 */    MCD_OPC_CheckField, 23, 9, 253, 3, 174, 3, 0, // Skip to: 2561
-/* 1619 */    MCD_OPC_CheckField, 4, 1, 0, 167, 3, 0, // Skip to: 2561
-/* 1626 */    MCD_OPC_Decode, 210, 9, 238, 2, // Opcode: VCVTPSS
-/* 1631 */    MCD_OPC_FilterValue, 15, 157, 3, 0, // Skip to: 2561
-/* 1636 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 1639 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1669
-/* 1644 */    MCD_OPC_CheckPredicate, 66, 144, 3, 0, // Skip to: 2561
-/* 1649 */    MCD_OPC_CheckField, 23, 9, 253, 3, 136, 3, 0, // Skip to: 2561
-/* 1657 */    MCD_OPC_CheckField, 4, 1, 0, 129, 3, 0, // Skip to: 2561
-/* 1664 */    MCD_OPC_Decode, 185, 9, 238, 2, // Opcode: VCVTMUS
-/* 1669 */    MCD_OPC_FilterValue, 1, 119, 3, 0, // Skip to: 2561
-/* 1674 */    MCD_OPC_CheckPredicate, 66, 114, 3, 0, // Skip to: 2561
-/* 1679 */    MCD_OPC_CheckField, 23, 9, 253, 3, 106, 3, 0, // Skip to: 2561
-/* 1687 */    MCD_OPC_CheckField, 4, 1, 0, 99, 3, 0, // Skip to: 2561
-/* 1694 */    MCD_OPC_Decode, 182, 9, 238, 2, // Opcode: VCVTMSS
-/* 1699 */    MCD_OPC_FilterValue, 11, 113, 2, 0, // Skip to: 2329
-/* 1704 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 1707 */    MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 1796
-/* 1712 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1715 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 1767
-/* 1720 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 1723 */    MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 1745
-/* 1729 */    MCD_OPC_CheckPredicate, 69, 59, 3, 0, // Skip to: 2561
-/* 1734 */    MCD_OPC_CheckField, 4, 1, 0, 52, 3, 0, // Skip to: 2561
-/* 1741 */    MCD_OPC_Decode, 232, 17, 97, // Opcode: VSELEQD
-/* 1745 */    MCD_OPC_FilterValue, 253, 3, 42, 3, 0, // Skip to: 2561
-/* 1751 */    MCD_OPC_CheckPredicate, 69, 37, 3, 0, // Skip to: 2561
-/* 1756 */    MCD_OPC_CheckField, 4, 1, 0, 30, 3, 0, // Skip to: 2561
-/* 1763 */    MCD_OPC_Decode, 156, 13, 97, // Opcode: VMAXNMD
-/* 1767 */    MCD_OPC_FilterValue, 1, 21, 3, 0, // Skip to: 2561
-/* 1772 */    MCD_OPC_CheckPredicate, 69, 16, 3, 0, // Skip to: 2561
-/* 1777 */    MCD_OPC_CheckField, 23, 9, 253, 3, 8, 3, 0, // Skip to: 2561
-/* 1785 */    MCD_OPC_CheckField, 4, 1, 0, 1, 3, 0, // Skip to: 2561
-/* 1792 */    MCD_OPC_Decode, 179, 13, 97, // Opcode: VMINNMD
-/* 1796 */    MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 1832
-/* 1801 */    MCD_OPC_CheckPredicate, 69, 243, 2, 0, // Skip to: 2561
-/* 1806 */    MCD_OPC_CheckField, 23, 9, 252, 3, 235, 2, 0, // Skip to: 2561
-/* 1814 */    MCD_OPC_CheckField, 6, 1, 0, 228, 2, 0, // Skip to: 2561
-/* 1821 */    MCD_OPC_CheckField, 4, 1, 0, 221, 2, 0, // Skip to: 2561
-/* 1828 */    MCD_OPC_Decode, 241, 17, 97, // Opcode: VSELVSD
-/* 1832 */    MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1868
-/* 1837 */    MCD_OPC_CheckPredicate, 69, 207, 2, 0, // Skip to: 2561
-/* 1842 */    MCD_OPC_CheckField, 23, 9, 252, 3, 199, 2, 0, // Skip to: 2561
-/* 1850 */    MCD_OPC_CheckField, 6, 1, 0, 192, 2, 0, // Skip to: 2561
-/* 1857 */    MCD_OPC_CheckField, 4, 1, 0, 185, 2, 0, // Skip to: 2561
-/* 1864 */    MCD_OPC_Decode, 235, 17, 97, // Opcode: VSELGED
-/* 1868 */    MCD_OPC_FilterValue, 3, 176, 2, 0, // Skip to: 2561
-/* 1873 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1876 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1905
-/* 1881 */    MCD_OPC_CheckPredicate, 69, 163, 2, 0, // Skip to: 2561
-/* 1886 */    MCD_OPC_CheckField, 23, 9, 252, 3, 155, 2, 0, // Skip to: 2561
-/* 1894 */    MCD_OPC_CheckField, 4, 1, 0, 148, 2, 0, // Skip to: 2561
-/* 1901 */    MCD_OPC_Decode, 238, 17, 97, // Opcode: VSELGTD
-/* 1905 */    MCD_OPC_FilterValue, 1, 139, 2, 0, // Skip to: 2561
-/* 1910 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 1913 */    MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 1949
-/* 1918 */    MCD_OPC_CheckPredicate, 69, 126, 2, 0, // Skip to: 2561
-/* 1923 */    MCD_OPC_CheckField, 23, 9, 253, 3, 118, 2, 0, // Skip to: 2561
-/* 1931 */    MCD_OPC_CheckField, 7, 1, 0, 111, 2, 0, // Skip to: 2561
-/* 1938 */    MCD_OPC_CheckField, 4, 1, 0, 104, 2, 0, // Skip to: 2561
-/* 1945 */    MCD_OPC_Decode, 247, 16, 126, // Opcode: VRINTAD
-/* 1949 */    MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 1985
-/* 1954 */    MCD_OPC_CheckPredicate, 69, 90, 2, 0, // Skip to: 2561
-/* 1959 */    MCD_OPC_CheckField, 23, 9, 253, 3, 82, 2, 0, // Skip to: 2561
-/* 1967 */    MCD_OPC_CheckField, 7, 1, 0, 75, 2, 0, // Skip to: 2561
-/* 1974 */    MCD_OPC_CheckField, 4, 1, 0, 68, 2, 0, // Skip to: 2561
-/* 1981 */    MCD_OPC_Decode, 133, 17, 126, // Opcode: VRINTND
-/* 1985 */    MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2021
-/* 1990 */    MCD_OPC_CheckPredicate, 69, 54, 2, 0, // Skip to: 2561
-/* 1995 */    MCD_OPC_CheckField, 23, 9, 253, 3, 46, 2, 0, // Skip to: 2561
-/* 2003 */    MCD_OPC_CheckField, 7, 1, 0, 39, 2, 0, // Skip to: 2561
-/* 2010 */    MCD_OPC_CheckField, 4, 1, 0, 32, 2, 0, // Skip to: 2561
-/* 2017 */    MCD_OPC_Decode, 140, 17, 126, // Opcode: VRINTPD
-/* 2021 */    MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2057
-/* 2026 */    MCD_OPC_CheckPredicate, 69, 18, 2, 0, // Skip to: 2561
-/* 2031 */    MCD_OPC_CheckField, 23, 9, 253, 3, 10, 2, 0, // Skip to: 2561
-/* 2039 */    MCD_OPC_CheckField, 7, 1, 0, 3, 2, 0, // Skip to: 2561
-/* 2046 */    MCD_OPC_CheckField, 4, 1, 0, 252, 1, 0, // Skip to: 2561
-/* 2053 */    MCD_OPC_Decode, 254, 16, 126, // Opcode: VRINTMD
-/* 2057 */    MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 2125
-/* 2062 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 2065 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2095
-/* 2070 */    MCD_OPC_CheckPredicate, 69, 230, 1, 0, // Skip to: 2561
-/* 2075 */    MCD_OPC_CheckField, 23, 9, 253, 3, 222, 1, 0, // Skip to: 2561
-/* 2083 */    MCD_OPC_CheckField, 4, 1, 0, 215, 1, 0, // Skip to: 2561
-/* 2090 */    MCD_OPC_Decode, 164, 9, 241, 2, // Opcode: VCVTAUD
-/* 2095 */    MCD_OPC_FilterValue, 1, 205, 1, 0, // Skip to: 2561
-/* 2100 */    MCD_OPC_CheckPredicate, 69, 200, 1, 0, // Skip to: 2561
-/* 2105 */    MCD_OPC_CheckField, 23, 9, 253, 3, 192, 1, 0, // Skip to: 2561
-/* 2113 */    MCD_OPC_CheckField, 4, 1, 0, 185, 1, 0, // Skip to: 2561
-/* 2120 */    MCD_OPC_Decode, 161, 9, 241, 2, // Opcode: VCVTASD
-/* 2125 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 2193
-/* 2130 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 2133 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2163
-/* 2138 */    MCD_OPC_CheckPredicate, 69, 162, 1, 0, // Skip to: 2561
-/* 2143 */    MCD_OPC_CheckField, 23, 9, 253, 3, 154, 1, 0, // Skip to: 2561
-/* 2151 */    MCD_OPC_CheckField, 4, 1, 0, 147, 1, 0, // Skip to: 2561
-/* 2158 */    MCD_OPC_Decode, 197, 9, 241, 2, // Opcode: VCVTNUD
-/* 2163 */    MCD_OPC_FilterValue, 1, 137, 1, 0, // Skip to: 2561
-/* 2168 */    MCD_OPC_CheckPredicate, 69, 132, 1, 0, // Skip to: 2561
-/* 2173 */    MCD_OPC_CheckField, 23, 9, 253, 3, 124, 1, 0, // Skip to: 2561
-/* 2181 */    MCD_OPC_CheckField, 4, 1, 0, 117, 1, 0, // Skip to: 2561
-/* 2188 */    MCD_OPC_Decode, 194, 9, 241, 2, // Opcode: VCVTNSD
-/* 2193 */    MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 2261
-/* 2198 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 2201 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2231
-/* 2206 */    MCD_OPC_CheckPredicate, 69, 94, 1, 0, // Skip to: 2561
-/* 2211 */    MCD_OPC_CheckField, 23, 9, 253, 3, 86, 1, 0, // Skip to: 2561
-/* 2219 */    MCD_OPC_CheckField, 4, 1, 0, 79, 1, 0, // Skip to: 2561
-/* 2226 */    MCD_OPC_Decode, 211, 9, 241, 2, // Opcode: VCVTPUD
-/* 2231 */    MCD_OPC_FilterValue, 1, 69, 1, 0, // Skip to: 2561
-/* 2236 */    MCD_OPC_CheckPredicate, 69, 64, 1, 0, // Skip to: 2561
-/* 2241 */    MCD_OPC_CheckField, 23, 9, 253, 3, 56, 1, 0, // Skip to: 2561
-/* 2249 */    MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2561
-/* 2256 */    MCD_OPC_Decode, 208, 9, 241, 2, // Opcode: VCVTPSD
-/* 2261 */    MCD_OPC_FilterValue, 15, 39, 1, 0, // Skip to: 2561
-/* 2266 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
-/* 2269 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2299
-/* 2274 */    MCD_OPC_CheckPredicate, 69, 26, 1, 0, // Skip to: 2561
-/* 2279 */    MCD_OPC_CheckField, 23, 9, 253, 3, 18, 1, 0, // Skip to: 2561
-/* 2287 */    MCD_OPC_CheckField, 4, 1, 0, 11, 1, 0, // Skip to: 2561
-/* 2294 */    MCD_OPC_Decode, 183, 9, 241, 2, // Opcode: VCVTMUD
-/* 2299 */    MCD_OPC_FilterValue, 1, 1, 1, 0, // Skip to: 2561
-/* 2304 */    MCD_OPC_CheckPredicate, 69, 252, 0, 0, // Skip to: 2561
-/* 2309 */    MCD_OPC_CheckField, 23, 9, 253, 3, 244, 0, 0, // Skip to: 2561
-/* 2317 */    MCD_OPC_CheckField, 4, 1, 0, 237, 0, 0, // Skip to: 2561
-/* 2324 */    MCD_OPC_Decode, 180, 9, 241, 2, // Opcode: VCVTMSD
-/* 2329 */    MCD_OPC_FilterValue, 13, 227, 0, 0, // Skip to: 2561
-/* 2334 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
-/* 2337 */    MCD_OPC_FilterValue, 0, 107, 0, 0, // Skip to: 2449
-/* 2342 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2345 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2397
-/* 2350 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2353 */    MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2375
-/* 2359 */    MCD_OPC_CheckPredicate, 73, 197, 0, 0, // Skip to: 2561
-/* 2364 */    MCD_OPC_CheckField, 20, 2, 2, 190, 0, 0, // Skip to: 2561
-/* 2371 */    MCD_OPC_Decode, 228, 17, 105, // Opcode: VSDOTD
-/* 2375 */    MCD_OPC_FilterValue, 252, 3, 180, 0, 0, // Skip to: 2561
-/* 2381 */    MCD_OPC_CheckPredicate, 73, 175, 0, 0, // Skip to: 2561
-/* 2386 */    MCD_OPC_CheckField, 20, 2, 2, 168, 0, 0, // Skip to: 2561
-/* 2393 */    MCD_OPC_Decode, 229, 17, 113, // Opcode: VSDOTDI
-/* 2397 */    MCD_OPC_FilterValue, 1, 159, 0, 0, // Skip to: 2561
-/* 2402 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2405 */    MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2427
-/* 2411 */    MCD_OPC_CheckPredicate, 73, 145, 0, 0, // Skip to: 2561
-/* 2416 */    MCD_OPC_CheckField, 20, 2, 2, 138, 0, 0, // Skip to: 2561
-/* 2423 */    MCD_OPC_Decode, 230, 17, 106, // Opcode: VSDOTQ
-/* 2427 */    MCD_OPC_FilterValue, 252, 3, 128, 0, 0, // Skip to: 2561
-/* 2433 */    MCD_OPC_CheckPredicate, 73, 123, 0, 0, // Skip to: 2561
-/* 2438 */    MCD_OPC_CheckField, 20, 2, 2, 116, 0, 0, // Skip to: 2561
-/* 2445 */    MCD_OPC_Decode, 231, 17, 114, // Opcode: VSDOTQI
-/* 2449 */    MCD_OPC_FilterValue, 1, 107, 0, 0, // Skip to: 2561
-/* 2454 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2457 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 2509
-/* 2462 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2465 */    MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2487
-/* 2471 */    MCD_OPC_CheckPredicate, 73, 85, 0, 0, // Skip to: 2561
-/* 2476 */    MCD_OPC_CheckField, 20, 2, 2, 78, 0, 0, // Skip to: 2561
-/* 2483 */    MCD_OPC_Decode, 159, 21, 105, // Opcode: VUDOTD
-/* 2487 */    MCD_OPC_FilterValue, 252, 3, 68, 0, 0, // Skip to: 2561
-/* 2493 */    MCD_OPC_CheckPredicate, 73, 63, 0, 0, // Skip to: 2561
-/* 2498 */    MCD_OPC_CheckField, 20, 2, 2, 56, 0, 0, // Skip to: 2561
-/* 2505 */    MCD_OPC_Decode, 160, 21, 113, // Opcode: VUDOTDI
-/* 2509 */    MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 2561
-/* 2514 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 2517 */    MCD_OPC_FilterValue, 248, 3, 16, 0, 0, // Skip to: 2539
-/* 2523 */    MCD_OPC_CheckPredicate, 73, 33, 0, 0, // Skip to: 2561
-/* 2528 */    MCD_OPC_CheckField, 20, 2, 2, 26, 0, 0, // Skip to: 2561
-/* 2535 */    MCD_OPC_Decode, 161, 21, 106, // Opcode: VUDOTQ
-/* 2539 */    MCD_OPC_FilterValue, 252, 3, 16, 0, 0, // Skip to: 2561
-/* 2545 */    MCD_OPC_CheckPredicate, 73, 11, 0, 0, // Skip to: 2561
-/* 2550 */    MCD_OPC_CheckField, 20, 2, 2, 4, 0, 0, // Skip to: 2561
-/* 2557 */    MCD_OPC_Decode, 162, 21, 114, // Opcode: VUDOTQI
-/* 2561 */    MCD_OPC_Fail,
+/* 795 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 824
+/* 800 */     MCD_OPC_CheckPredicate, 94, 127, 9, 0, // Skip to: 3236
+/* 805 */     MCD_OPC_CheckField, 23, 5, 29, 120, 9, 0, // Skip to: 3236
+/* 812 */     MCD_OPC_CheckField, 4, 1, 0, 113, 9, 0, // Skip to: 3236
+/* 819 */     MCD_OPC_Decode, 219, 5, 237, 3, // Opcode: BF16_VCVTB
+/* 824 */     MCD_OPC_FilterValue, 1, 103, 9, 0, // Skip to: 3236
+/* 829 */     MCD_OPC_CheckPredicate, 94, 98, 9, 0, // Skip to: 3236
+/* 834 */     MCD_OPC_CheckField, 23, 5, 29, 91, 9, 0, // Skip to: 3236
+/* 841 */     MCD_OPC_CheckField, 4, 1, 0, 84, 9, 0, // Skip to: 3236
+/* 848 */     MCD_OPC_Decode, 220, 5, 237, 3, // Opcode: BF16_VCVTT
+/* 853 */     MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 890
+/* 858 */     MCD_OPC_CheckPredicate, 77, 69, 9, 0, // Skip to: 3236
+/* 863 */     MCD_OPC_CheckField, 23, 9, 253, 3, 61, 9, 0, // Skip to: 3236
+/* 871 */     MCD_OPC_CheckField, 7, 1, 0, 54, 9, 0, // Skip to: 3236
+/* 878 */     MCD_OPC_CheckField, 4, 1, 0, 47, 9, 0, // Skip to: 3236
+/* 885 */     MCD_OPC_Decode, 230, 25, 139, 4, // Opcode: VRINTAH
+/* 890 */     MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 927
+/* 895 */     MCD_OPC_CheckPredicate, 77, 32, 9, 0, // Skip to: 3236
+/* 900 */     MCD_OPC_CheckField, 23, 9, 253, 3, 24, 9, 0, // Skip to: 3236
+/* 908 */     MCD_OPC_CheckField, 7, 1, 0, 17, 9, 0, // Skip to: 3236
+/* 915 */     MCD_OPC_CheckField, 4, 1, 0, 10, 9, 0, // Skip to: 3236
+/* 922 */     MCD_OPC_Decode, 244, 25, 139, 4, // Opcode: VRINTNH
+/* 927 */     MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 964
+/* 932 */     MCD_OPC_CheckPredicate, 77, 251, 8, 0, // Skip to: 3236
+/* 937 */     MCD_OPC_CheckField, 23, 9, 253, 3, 243, 8, 0, // Skip to: 3236
+/* 945 */     MCD_OPC_CheckField, 7, 1, 0, 236, 8, 0, // Skip to: 3236
+/* 952 */     MCD_OPC_CheckField, 4, 1, 0, 229, 8, 0, // Skip to: 3236
+/* 959 */     MCD_OPC_Decode, 251, 25, 139, 4, // Opcode: VRINTPH
+/* 964 */     MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 1001
+/* 969 */     MCD_OPC_CheckPredicate, 77, 214, 8, 0, // Skip to: 3236
+/* 974 */     MCD_OPC_CheckField, 23, 9, 253, 3, 206, 8, 0, // Skip to: 3236
+/* 982 */     MCD_OPC_CheckField, 7, 1, 0, 199, 8, 0, // Skip to: 3236
+/* 989 */     MCD_OPC_CheckField, 4, 1, 0, 192, 8, 0, // Skip to: 3236
+/* 996 */     MCD_OPC_Decode, 237, 25, 139, 4, // Opcode: VRINTMH
+/* 1001 */    MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 1069
+/* 1006 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1009 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1039
+/* 1014 */    MCD_OPC_CheckPredicate, 77, 169, 8, 0, // Skip to: 3236
+/* 1019 */    MCD_OPC_CheckField, 23, 9, 253, 3, 161, 8, 0, // Skip to: 3236
+/* 1027 */    MCD_OPC_CheckField, 4, 1, 0, 154, 8, 0, // Skip to: 3236
+/* 1034 */    MCD_OPC_Decode, 214, 17, 140, 4, // Opcode: VCVTAUH
+/* 1039 */    MCD_OPC_FilterValue, 1, 144, 8, 0, // Skip to: 3236
+/* 1044 */    MCD_OPC_CheckPredicate, 77, 139, 8, 0, // Skip to: 3236
+/* 1049 */    MCD_OPC_CheckField, 23, 9, 253, 3, 131, 8, 0, // Skip to: 3236
+/* 1057 */    MCD_OPC_CheckField, 4, 1, 0, 124, 8, 0, // Skip to: 3236
+/* 1064 */    MCD_OPC_Decode, 211, 17, 140, 4, // Opcode: VCVTASH
+/* 1069 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1137
+/* 1074 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1077 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1107
+/* 1082 */    MCD_OPC_CheckPredicate, 77, 101, 8, 0, // Skip to: 3236
+/* 1087 */    MCD_OPC_CheckField, 23, 9, 253, 3, 93, 8, 0, // Skip to: 3236
+/* 1095 */    MCD_OPC_CheckField, 4, 1, 0, 86, 8, 0, // Skip to: 3236
+/* 1102 */    MCD_OPC_Decode, 247, 17, 140, 4, // Opcode: VCVTNUH
+/* 1107 */    MCD_OPC_FilterValue, 1, 76, 8, 0, // Skip to: 3236
+/* 1112 */    MCD_OPC_CheckPredicate, 77, 71, 8, 0, // Skip to: 3236
+/* 1117 */    MCD_OPC_CheckField, 23, 9, 253, 3, 63, 8, 0, // Skip to: 3236
+/* 1125 */    MCD_OPC_CheckField, 4, 1, 0, 56, 8, 0, // Skip to: 3236
+/* 1132 */    MCD_OPC_Decode, 244, 17, 140, 4, // Opcode: VCVTNSH
+/* 1137 */    MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 1205
+/* 1142 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1145 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1175
+/* 1150 */    MCD_OPC_CheckPredicate, 77, 33, 8, 0, // Skip to: 3236
+/* 1155 */    MCD_OPC_CheckField, 23, 9, 253, 3, 25, 8, 0, // Skip to: 3236
+/* 1163 */    MCD_OPC_CheckField, 4, 1, 0, 18, 8, 0, // Skip to: 3236
+/* 1170 */    MCD_OPC_Decode, 133, 18, 140, 4, // Opcode: VCVTPUH
+/* 1175 */    MCD_OPC_FilterValue, 1, 8, 8, 0, // Skip to: 3236
+/* 1180 */    MCD_OPC_CheckPredicate, 77, 3, 8, 0, // Skip to: 3236
+/* 1185 */    MCD_OPC_CheckField, 23, 9, 253, 3, 251, 7, 0, // Skip to: 3236
+/* 1193 */    MCD_OPC_CheckField, 4, 1, 0, 244, 7, 0, // Skip to: 3236
+/* 1200 */    MCD_OPC_Decode, 130, 18, 140, 4, // Opcode: VCVTPSH
+/* 1205 */    MCD_OPC_FilterValue, 15, 234, 7, 0, // Skip to: 3236
+/* 1210 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1213 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1243
+/* 1218 */    MCD_OPC_CheckPredicate, 77, 221, 7, 0, // Skip to: 3236
+/* 1223 */    MCD_OPC_CheckField, 23, 9, 253, 3, 213, 7, 0, // Skip to: 3236
+/* 1231 */    MCD_OPC_CheckField, 4, 1, 0, 206, 7, 0, // Skip to: 3236
+/* 1238 */    MCD_OPC_Decode, 233, 17, 140, 4, // Opcode: VCVTMUH
+/* 1243 */    MCD_OPC_FilterValue, 1, 196, 7, 0, // Skip to: 3236
+/* 1248 */    MCD_OPC_CheckPredicate, 77, 191, 7, 0, // Skip to: 3236
+/* 1253 */    MCD_OPC_CheckField, 23, 9, 253, 3, 183, 7, 0, // Skip to: 3236
+/* 1261 */    MCD_OPC_CheckField, 4, 1, 0, 176, 7, 0, // Skip to: 3236
+/* 1268 */    MCD_OPC_Decode, 230, 17, 140, 4, // Opcode: VCVTMSH
+/* 1273 */    MCD_OPC_FilterValue, 10, 191, 2, 0, // Skip to: 1981
+/* 1278 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 1281 */    MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 1373
+/* 1286 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1289 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 1343
+/* 1294 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 1297 */    MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 1320
+/* 1303 */    MCD_OPC_CheckPredicate, 84, 136, 7, 0, // Skip to: 3236
+/* 1308 */    MCD_OPC_CheckField, 4, 1, 0, 129, 7, 0, // Skip to: 3236
+/* 1315 */    MCD_OPC_Decode, 218, 26, 141, 4, // Opcode: VSELEQS
+/* 1320 */    MCD_OPC_FilterValue, 253, 3, 118, 7, 0, // Skip to: 3236
+/* 1326 */    MCD_OPC_CheckPredicate, 84, 113, 7, 0, // Skip to: 3236
+/* 1331 */    MCD_OPC_CheckField, 4, 1, 0, 106, 7, 0, // Skip to: 3236
+/* 1338 */    MCD_OPC_Decode, 228, 18, 141, 4, // Opcode: VFP_VMAXNMS
+/* 1343 */    MCD_OPC_FilterValue, 1, 96, 7, 0, // Skip to: 3236
+/* 1348 */    MCD_OPC_CheckPredicate, 84, 91, 7, 0, // Skip to: 3236
+/* 1353 */    MCD_OPC_CheckField, 23, 9, 253, 3, 83, 7, 0, // Skip to: 3236
+/* 1361 */    MCD_OPC_CheckField, 4, 1, 0, 76, 7, 0, // Skip to: 3236
+/* 1368 */    MCD_OPC_Decode, 231, 18, 141, 4, // Opcode: VFP_VMINNMS
+/* 1373 */    MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 1410
+/* 1378 */    MCD_OPC_CheckPredicate, 84, 61, 7, 0, // Skip to: 3236
+/* 1383 */    MCD_OPC_CheckField, 23, 9, 252, 3, 53, 7, 0, // Skip to: 3236
+/* 1391 */    MCD_OPC_CheckField, 6, 1, 0, 46, 7, 0, // Skip to: 3236
+/* 1398 */    MCD_OPC_CheckField, 4, 1, 0, 39, 7, 0, // Skip to: 3236
+/* 1405 */    MCD_OPC_Decode, 227, 26, 141, 4, // Opcode: VSELVSS
+/* 1410 */    MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 1447
+/* 1415 */    MCD_OPC_CheckPredicate, 84, 24, 7, 0, // Skip to: 3236
+/* 1420 */    MCD_OPC_CheckField, 23, 9, 252, 3, 16, 7, 0, // Skip to: 3236
+/* 1428 */    MCD_OPC_CheckField, 6, 1, 0, 9, 7, 0, // Skip to: 3236
+/* 1435 */    MCD_OPC_CheckField, 4, 1, 0, 2, 7, 0, // Skip to: 3236
+/* 1442 */    MCD_OPC_Decode, 221, 26, 141, 4, // Opcode: VSELGES
+/* 1447 */    MCD_OPC_FilterValue, 3, 248, 6, 0, // Skip to: 3236
+/* 1452 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1455 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1485
+/* 1460 */    MCD_OPC_CheckPredicate, 84, 235, 6, 0, // Skip to: 3236
+/* 1465 */    MCD_OPC_CheckField, 23, 9, 252, 3, 227, 6, 0, // Skip to: 3236
+/* 1473 */    MCD_OPC_CheckField, 4, 1, 0, 220, 6, 0, // Skip to: 3236
+/* 1480 */    MCD_OPC_Decode, 224, 26, 141, 4, // Opcode: VSELGTS
+/* 1485 */    MCD_OPC_FilterValue, 1, 210, 6, 0, // Skip to: 3236
+/* 1490 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 1493 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1561
+/* 1498 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1501 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1531
+/* 1506 */    MCD_OPC_CheckPredicate, 77, 189, 6, 0, // Skip to: 3236
+/* 1511 */    MCD_OPC_CheckField, 23, 9, 253, 3, 181, 6, 0, // Skip to: 3236
+/* 1519 */    MCD_OPC_CheckField, 4, 1, 0, 174, 6, 0, // Skip to: 3236
+/* 1526 */    MCD_OPC_Decode, 238, 22, 142, 4, // Opcode: VMOVH
+/* 1531 */    MCD_OPC_FilterValue, 1, 164, 6, 0, // Skip to: 3236
+/* 1536 */    MCD_OPC_CheckPredicate, 77, 159, 6, 0, // Skip to: 3236
+/* 1541 */    MCD_OPC_CheckField, 23, 9, 253, 3, 151, 6, 0, // Skip to: 3236
+/* 1549 */    MCD_OPC_CheckField, 4, 1, 0, 144, 6, 0, // Skip to: 3236
+/* 1556 */    MCD_OPC_Decode, 133, 19, 143, 4, // Opcode: VINSH
+/* 1561 */    MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 1598
+/* 1566 */    MCD_OPC_CheckPredicate, 84, 129, 6, 0, // Skip to: 3236
+/* 1571 */    MCD_OPC_CheckField, 23, 9, 253, 3, 121, 6, 0, // Skip to: 3236
+/* 1579 */    MCD_OPC_CheckField, 7, 1, 0, 114, 6, 0, // Skip to: 3236
+/* 1586 */    MCD_OPC_CheckField, 4, 1, 0, 107, 6, 0, // Skip to: 3236
+/* 1593 */    MCD_OPC_Decode, 235, 25, 142, 4, // Opcode: VRINTAS
+/* 1598 */    MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 1635
+/* 1603 */    MCD_OPC_CheckPredicate, 84, 92, 6, 0, // Skip to: 3236
+/* 1608 */    MCD_OPC_CheckField, 23, 9, 253, 3, 84, 6, 0, // Skip to: 3236
+/* 1616 */    MCD_OPC_CheckField, 7, 1, 0, 77, 6, 0, // Skip to: 3236
+/* 1623 */    MCD_OPC_CheckField, 4, 1, 0, 70, 6, 0, // Skip to: 3236
+/* 1630 */    MCD_OPC_Decode, 249, 25, 142, 4, // Opcode: VRINTNS
+/* 1635 */    MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 1672
+/* 1640 */    MCD_OPC_CheckPredicate, 84, 55, 6, 0, // Skip to: 3236
+/* 1645 */    MCD_OPC_CheckField, 23, 9, 253, 3, 47, 6, 0, // Skip to: 3236
+/* 1653 */    MCD_OPC_CheckField, 7, 1, 0, 40, 6, 0, // Skip to: 3236
+/* 1660 */    MCD_OPC_CheckField, 4, 1, 0, 33, 6, 0, // Skip to: 3236
+/* 1667 */    MCD_OPC_Decode, 128, 26, 142, 4, // Opcode: VRINTPS
+/* 1672 */    MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 1709
+/* 1677 */    MCD_OPC_CheckPredicate, 84, 18, 6, 0, // Skip to: 3236
+/* 1682 */    MCD_OPC_CheckField, 23, 9, 253, 3, 10, 6, 0, // Skip to: 3236
+/* 1690 */    MCD_OPC_CheckField, 7, 1, 0, 3, 6, 0, // Skip to: 3236
+/* 1697 */    MCD_OPC_CheckField, 4, 1, 0, 252, 5, 0, // Skip to: 3236
+/* 1704 */    MCD_OPC_Decode, 242, 25, 142, 4, // Opcode: VRINTMS
+/* 1709 */    MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 1777
+/* 1714 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1717 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1747
+/* 1722 */    MCD_OPC_CheckPredicate, 84, 229, 5, 0, // Skip to: 3236
+/* 1727 */    MCD_OPC_CheckField, 23, 9, 253, 3, 221, 5, 0, // Skip to: 3236
+/* 1735 */    MCD_OPC_CheckField, 4, 1, 0, 214, 5, 0, // Skip to: 3236
+/* 1742 */    MCD_OPC_Decode, 215, 17, 142, 4, // Opcode: VCVTAUS
+/* 1747 */    MCD_OPC_FilterValue, 1, 204, 5, 0, // Skip to: 3236
+/* 1752 */    MCD_OPC_CheckPredicate, 84, 199, 5, 0, // Skip to: 3236
+/* 1757 */    MCD_OPC_CheckField, 23, 9, 253, 3, 191, 5, 0, // Skip to: 3236
+/* 1765 */    MCD_OPC_CheckField, 4, 1, 0, 184, 5, 0, // Skip to: 3236
+/* 1772 */    MCD_OPC_Decode, 212, 17, 142, 4, // Opcode: VCVTASS
+/* 1777 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 1845
+/* 1782 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1785 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1815
+/* 1790 */    MCD_OPC_CheckPredicate, 84, 161, 5, 0, // Skip to: 3236
+/* 1795 */    MCD_OPC_CheckField, 23, 9, 253, 3, 153, 5, 0, // Skip to: 3236
+/* 1803 */    MCD_OPC_CheckField, 4, 1, 0, 146, 5, 0, // Skip to: 3236
+/* 1810 */    MCD_OPC_Decode, 248, 17, 142, 4, // Opcode: VCVTNUS
+/* 1815 */    MCD_OPC_FilterValue, 1, 136, 5, 0, // Skip to: 3236
+/* 1820 */    MCD_OPC_CheckPredicate, 84, 131, 5, 0, // Skip to: 3236
+/* 1825 */    MCD_OPC_CheckField, 23, 9, 253, 3, 123, 5, 0, // Skip to: 3236
+/* 1833 */    MCD_OPC_CheckField, 4, 1, 0, 116, 5, 0, // Skip to: 3236
+/* 1840 */    MCD_OPC_Decode, 245, 17, 142, 4, // Opcode: VCVTNSS
+/* 1845 */    MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 1913
+/* 1850 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1853 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1883
+/* 1858 */    MCD_OPC_CheckPredicate, 84, 93, 5, 0, // Skip to: 3236
+/* 1863 */    MCD_OPC_CheckField, 23, 9, 253, 3, 85, 5, 0, // Skip to: 3236
+/* 1871 */    MCD_OPC_CheckField, 4, 1, 0, 78, 5, 0, // Skip to: 3236
+/* 1878 */    MCD_OPC_Decode, 134, 18, 142, 4, // Opcode: VCVTPUS
+/* 1883 */    MCD_OPC_FilterValue, 1, 68, 5, 0, // Skip to: 3236
+/* 1888 */    MCD_OPC_CheckPredicate, 84, 63, 5, 0, // Skip to: 3236
+/* 1893 */    MCD_OPC_CheckField, 23, 9, 253, 3, 55, 5, 0, // Skip to: 3236
+/* 1901 */    MCD_OPC_CheckField, 4, 1, 0, 48, 5, 0, // Skip to: 3236
+/* 1908 */    MCD_OPC_Decode, 131, 18, 142, 4, // Opcode: VCVTPSS
+/* 1913 */    MCD_OPC_FilterValue, 15, 38, 5, 0, // Skip to: 3236
+/* 1918 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 1921 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 1951
+/* 1926 */    MCD_OPC_CheckPredicate, 84, 25, 5, 0, // Skip to: 3236
+/* 1931 */    MCD_OPC_CheckField, 23, 9, 253, 3, 17, 5, 0, // Skip to: 3236
+/* 1939 */    MCD_OPC_CheckField, 4, 1, 0, 10, 5, 0, // Skip to: 3236
+/* 1946 */    MCD_OPC_Decode, 234, 17, 142, 4, // Opcode: VCVTMUS
+/* 1951 */    MCD_OPC_FilterValue, 1, 0, 5, 0, // Skip to: 3236
+/* 1956 */    MCD_OPC_CheckPredicate, 84, 251, 4, 0, // Skip to: 3236
+/* 1961 */    MCD_OPC_CheckField, 23, 9, 253, 3, 243, 4, 0, // Skip to: 3236
+/* 1969 */    MCD_OPC_CheckField, 4, 1, 0, 236, 4, 0, // Skip to: 3236
+/* 1976 */    MCD_OPC_Decode, 231, 17, 142, 4, // Opcode: VCVTMSS
+/* 1981 */    MCD_OPC_FilterValue, 11, 123, 2, 0, // Skip to: 2621
+/* 1986 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 1989 */    MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 2081
+/* 1994 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1997 */    MCD_OPC_FilterValue, 0, 49, 0, 0, // Skip to: 2051
+/* 2002 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2005 */    MCD_OPC_FilterValue, 252, 3, 17, 0, 0, // Skip to: 2028
+/* 2011 */    MCD_OPC_CheckPredicate, 89, 196, 4, 0, // Skip to: 3236
+/* 2016 */    MCD_OPC_CheckField, 4, 1, 0, 189, 4, 0, // Skip to: 3236
+/* 2023 */    MCD_OPC_Decode, 216, 26, 202, 1, // Opcode: VSELEQD
+/* 2028 */    MCD_OPC_FilterValue, 253, 3, 178, 4, 0, // Skip to: 3236
+/* 2034 */    MCD_OPC_CheckPredicate, 89, 173, 4, 0, // Skip to: 3236
+/* 2039 */    MCD_OPC_CheckField, 4, 1, 0, 166, 4, 0, // Skip to: 3236
+/* 2046 */    MCD_OPC_Decode, 226, 18, 202, 1, // Opcode: VFP_VMAXNMD
+/* 2051 */    MCD_OPC_FilterValue, 1, 156, 4, 0, // Skip to: 3236
+/* 2056 */    MCD_OPC_CheckPredicate, 89, 151, 4, 0, // Skip to: 3236
+/* 2061 */    MCD_OPC_CheckField, 23, 9, 253, 3, 143, 4, 0, // Skip to: 3236
+/* 2069 */    MCD_OPC_CheckField, 4, 1, 0, 136, 4, 0, // Skip to: 3236
+/* 2076 */    MCD_OPC_Decode, 229, 18, 202, 1, // Opcode: VFP_VMINNMD
+/* 2081 */    MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 2118
+/* 2086 */    MCD_OPC_CheckPredicate, 89, 121, 4, 0, // Skip to: 3236
+/* 2091 */    MCD_OPC_CheckField, 23, 9, 252, 3, 113, 4, 0, // Skip to: 3236
+/* 2099 */    MCD_OPC_CheckField, 6, 1, 0, 106, 4, 0, // Skip to: 3236
+/* 2106 */    MCD_OPC_CheckField, 4, 1, 0, 99, 4, 0, // Skip to: 3236
+/* 2113 */    MCD_OPC_Decode, 225, 26, 202, 1, // Opcode: VSELVSD
+/* 2118 */    MCD_OPC_FilterValue, 2, 32, 0, 0, // Skip to: 2155
+/* 2123 */    MCD_OPC_CheckPredicate, 89, 84, 4, 0, // Skip to: 3236
+/* 2128 */    MCD_OPC_CheckField, 23, 9, 252, 3, 76, 4, 0, // Skip to: 3236
+/* 2136 */    MCD_OPC_CheckField, 6, 1, 0, 69, 4, 0, // Skip to: 3236
+/* 2143 */    MCD_OPC_CheckField, 4, 1, 0, 62, 4, 0, // Skip to: 3236
+/* 2150 */    MCD_OPC_Decode, 219, 26, 202, 1, // Opcode: VSELGED
+/* 2155 */    MCD_OPC_FilterValue, 3, 52, 4, 0, // Skip to: 3236
+/* 2160 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2163 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2193
+/* 2168 */    MCD_OPC_CheckPredicate, 89, 39, 4, 0, // Skip to: 3236
+/* 2173 */    MCD_OPC_CheckField, 23, 9, 252, 3, 31, 4, 0, // Skip to: 3236
+/* 2181 */    MCD_OPC_CheckField, 4, 1, 0, 24, 4, 0, // Skip to: 3236
+/* 2188 */    MCD_OPC_Decode, 222, 26, 202, 1, // Opcode: VSELGTD
+/* 2193 */    MCD_OPC_FilterValue, 1, 14, 4, 0, // Skip to: 3236
+/* 2198 */    MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 2201 */    MCD_OPC_FilterValue, 8, 32, 0, 0, // Skip to: 2238
+/* 2206 */    MCD_OPC_CheckPredicate, 89, 1, 4, 0, // Skip to: 3236
+/* 2211 */    MCD_OPC_CheckField, 23, 9, 253, 3, 249, 3, 0, // Skip to: 3236
+/* 2219 */    MCD_OPC_CheckField, 7, 1, 0, 242, 3, 0, // Skip to: 3236
+/* 2226 */    MCD_OPC_CheckField, 4, 1, 0, 235, 3, 0, // Skip to: 3236
+/* 2233 */    MCD_OPC_Decode, 229, 25, 231, 1, // Opcode: VRINTAD
+/* 2238 */    MCD_OPC_FilterValue, 9, 32, 0, 0, // Skip to: 2275
+/* 2243 */    MCD_OPC_CheckPredicate, 89, 220, 3, 0, // Skip to: 3236
+/* 2248 */    MCD_OPC_CheckField, 23, 9, 253, 3, 212, 3, 0, // Skip to: 3236
+/* 2256 */    MCD_OPC_CheckField, 7, 1, 0, 205, 3, 0, // Skip to: 3236
+/* 2263 */    MCD_OPC_CheckField, 4, 1, 0, 198, 3, 0, // Skip to: 3236
+/* 2270 */    MCD_OPC_Decode, 243, 25, 231, 1, // Opcode: VRINTND
+/* 2275 */    MCD_OPC_FilterValue, 10, 32, 0, 0, // Skip to: 2312
+/* 2280 */    MCD_OPC_CheckPredicate, 89, 183, 3, 0, // Skip to: 3236
+/* 2285 */    MCD_OPC_CheckField, 23, 9, 253, 3, 175, 3, 0, // Skip to: 3236
+/* 2293 */    MCD_OPC_CheckField, 7, 1, 0, 168, 3, 0, // Skip to: 3236
+/* 2300 */    MCD_OPC_CheckField, 4, 1, 0, 161, 3, 0, // Skip to: 3236
+/* 2307 */    MCD_OPC_Decode, 250, 25, 231, 1, // Opcode: VRINTPD
+/* 2312 */    MCD_OPC_FilterValue, 11, 32, 0, 0, // Skip to: 2349
+/* 2317 */    MCD_OPC_CheckPredicate, 89, 146, 3, 0, // Skip to: 3236
+/* 2322 */    MCD_OPC_CheckField, 23, 9, 253, 3, 138, 3, 0, // Skip to: 3236
+/* 2330 */    MCD_OPC_CheckField, 7, 1, 0, 131, 3, 0, // Skip to: 3236
+/* 2337 */    MCD_OPC_CheckField, 4, 1, 0, 124, 3, 0, // Skip to: 3236
+/* 2344 */    MCD_OPC_Decode, 236, 25, 231, 1, // Opcode: VRINTMD
+/* 2349 */    MCD_OPC_FilterValue, 12, 63, 0, 0, // Skip to: 2417
+/* 2354 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2357 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2387
+/* 2362 */    MCD_OPC_CheckPredicate, 89, 101, 3, 0, // Skip to: 3236
+/* 2367 */    MCD_OPC_CheckField, 23, 9, 253, 3, 93, 3, 0, // Skip to: 3236
+/* 2375 */    MCD_OPC_CheckField, 4, 1, 0, 86, 3, 0, // Skip to: 3236
+/* 2382 */    MCD_OPC_Decode, 213, 17, 144, 4, // Opcode: VCVTAUD
+/* 2387 */    MCD_OPC_FilterValue, 1, 76, 3, 0, // Skip to: 3236
+/* 2392 */    MCD_OPC_CheckPredicate, 89, 71, 3, 0, // Skip to: 3236
+/* 2397 */    MCD_OPC_CheckField, 23, 9, 253, 3, 63, 3, 0, // Skip to: 3236
+/* 2405 */    MCD_OPC_CheckField, 4, 1, 0, 56, 3, 0, // Skip to: 3236
+/* 2412 */    MCD_OPC_Decode, 210, 17, 144, 4, // Opcode: VCVTASD
+/* 2417 */    MCD_OPC_FilterValue, 13, 63, 0, 0, // Skip to: 2485
+/* 2422 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2425 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2455
+/* 2430 */    MCD_OPC_CheckPredicate, 89, 33, 3, 0, // Skip to: 3236
+/* 2435 */    MCD_OPC_CheckField, 23, 9, 253, 3, 25, 3, 0, // Skip to: 3236
+/* 2443 */    MCD_OPC_CheckField, 4, 1, 0, 18, 3, 0, // Skip to: 3236
+/* 2450 */    MCD_OPC_Decode, 246, 17, 144, 4, // Opcode: VCVTNUD
+/* 2455 */    MCD_OPC_FilterValue, 1, 8, 3, 0, // Skip to: 3236
+/* 2460 */    MCD_OPC_CheckPredicate, 89, 3, 3, 0, // Skip to: 3236
+/* 2465 */    MCD_OPC_CheckField, 23, 9, 253, 3, 251, 2, 0, // Skip to: 3236
+/* 2473 */    MCD_OPC_CheckField, 4, 1, 0, 244, 2, 0, // Skip to: 3236
+/* 2480 */    MCD_OPC_Decode, 243, 17, 144, 4, // Opcode: VCVTNSD
+/* 2485 */    MCD_OPC_FilterValue, 14, 63, 0, 0, // Skip to: 2553
+/* 2490 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2493 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2523
+/* 2498 */    MCD_OPC_CheckPredicate, 89, 221, 2, 0, // Skip to: 3236
+/* 2503 */    MCD_OPC_CheckField, 23, 9, 253, 3, 213, 2, 0, // Skip to: 3236
+/* 2511 */    MCD_OPC_CheckField, 4, 1, 0, 206, 2, 0, // Skip to: 3236
+/* 2518 */    MCD_OPC_Decode, 132, 18, 144, 4, // Opcode: VCVTPUD
+/* 2523 */    MCD_OPC_FilterValue, 1, 196, 2, 0, // Skip to: 3236
+/* 2528 */    MCD_OPC_CheckPredicate, 89, 191, 2, 0, // Skip to: 3236
+/* 2533 */    MCD_OPC_CheckField, 23, 9, 253, 3, 183, 2, 0, // Skip to: 3236
+/* 2541 */    MCD_OPC_CheckField, 4, 1, 0, 176, 2, 0, // Skip to: 3236
+/* 2548 */    MCD_OPC_Decode, 129, 18, 144, 4, // Opcode: VCVTPSD
+/* 2553 */    MCD_OPC_FilterValue, 15, 166, 2, 0, // Skip to: 3236
+/* 2558 */    MCD_OPC_ExtractField, 7, 1,  // Inst{7} ...
+/* 2561 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2591
+/* 2566 */    MCD_OPC_CheckPredicate, 89, 153, 2, 0, // Skip to: 3236
+/* 2571 */    MCD_OPC_CheckField, 23, 9, 253, 3, 145, 2, 0, // Skip to: 3236
+/* 2579 */    MCD_OPC_CheckField, 4, 1, 0, 138, 2, 0, // Skip to: 3236
+/* 2586 */    MCD_OPC_Decode, 232, 17, 144, 4, // Opcode: VCVTMUD
+/* 2591 */    MCD_OPC_FilterValue, 1, 128, 2, 0, // Skip to: 3236
+/* 2596 */    MCD_OPC_CheckPredicate, 89, 123, 2, 0, // Skip to: 3236
+/* 2601 */    MCD_OPC_CheckField, 23, 9, 253, 3, 115, 2, 0, // Skip to: 3236
+/* 2609 */    MCD_OPC_CheckField, 4, 1, 0, 108, 2, 0, // Skip to: 3236
+/* 2616 */    MCD_OPC_Decode, 229, 17, 144, 4, // Opcode: VCVTMSD
+/* 2621 */    MCD_OPC_FilterValue, 12, 132, 0, 0, // Skip to: 2758
+/* 2626 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 2629 */    MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 2721
+/* 2634 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 2637 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2667
+/* 2642 */    MCD_OPC_CheckPredicate, 31, 77, 2, 0, // Skip to: 3236
+/* 2647 */    MCD_OPC_CheckField, 23, 9, 248, 3, 69, 2, 0, // Skip to: 3236
+/* 2655 */    MCD_OPC_CheckField, 6, 1, 1, 62, 2, 0, // Skip to: 3236
+/* 2662 */    MCD_OPC_Decode, 235, 22, 211, 1, // Opcode: VMMLA
+/* 2667 */    MCD_OPC_FilterValue, 2, 52, 2, 0, // Skip to: 3236
+/* 2672 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2675 */    MCD_OPC_FilterValue, 248, 3, 17, 0, 0, // Skip to: 2698
+/* 2681 */    MCD_OPC_CheckPredicate, 95, 38, 2, 0, // Skip to: 3236
+/* 2686 */    MCD_OPC_CheckField, 6, 1, 1, 31, 2, 0, // Skip to: 3236
+/* 2693 */    MCD_OPC_Decode, 172, 27, 211, 1, // Opcode: VSMMLA
+/* 2698 */    MCD_OPC_FilterValue, 249, 3, 20, 2, 0, // Skip to: 3236
+/* 2704 */    MCD_OPC_CheckPredicate, 95, 15, 2, 0, // Skip to: 3236
+/* 2709 */    MCD_OPC_CheckField, 6, 1, 1, 8, 2, 0, // Skip to: 3236
+/* 2716 */    MCD_OPC_Decode, 202, 30, 211, 1, // Opcode: VUSMMLA
+/* 2721 */    MCD_OPC_FilterValue, 1, 254, 1, 0, // Skip to: 3236
+/* 2726 */    MCD_OPC_CheckPredicate, 95, 249, 1, 0, // Skip to: 3236
+/* 2731 */    MCD_OPC_CheckField, 23, 9, 248, 3, 241, 1, 0, // Skip to: 3236
+/* 2739 */    MCD_OPC_CheckField, 20, 2, 2, 234, 1, 0, // Skip to: 3236
+/* 2746 */    MCD_OPC_CheckField, 6, 1, 1, 227, 1, 0, // Skip to: 3236
+/* 2753 */    MCD_OPC_Decode, 197, 30, 211, 1, // Opcode: VUMMLA
+/* 2758 */    MCD_OPC_FilterValue, 13, 217, 1, 0, // Skip to: 3236
+/* 2763 */    MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 2766 */    MCD_OPC_FilterValue, 248, 3, 139, 0, 0, // Skip to: 2911
+/* 2772 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 2775 */    MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 2859
+/* 2780 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2783 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 2821
+/* 2788 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 2791 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2806
+/* 2796 */    MCD_OPC_CheckPredicate, 31, 179, 1, 0, // Skip to: 3236
+/* 2801 */    MCD_OPC_Decode, 216, 5, 210, 1, // Opcode: BF16VDOTS_VDOTD
+/* 2806 */    MCD_OPC_FilterValue, 2, 169, 1, 0, // Skip to: 3236
+/* 2811 */    MCD_OPC_CheckPredicate, 96, 164, 1, 0, // Skip to: 3236
+/* 2816 */    MCD_OPC_Decode, 212, 26, 210, 1, // Opcode: VSDOTD
+/* 2821 */    MCD_OPC_FilterValue, 1, 154, 1, 0, // Skip to: 3236
+/* 2826 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 2829 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 2844
+/* 2834 */    MCD_OPC_CheckPredicate, 31, 141, 1, 0, // Skip to: 3236
+/* 2839 */    MCD_OPC_Decode, 217, 5, 211, 1, // Opcode: BF16VDOTS_VDOTQ
+/* 2844 */    MCD_OPC_FilterValue, 2, 131, 1, 0, // Skip to: 3236
+/* 2849 */    MCD_OPC_CheckPredicate, 96, 126, 1, 0, // Skip to: 3236
+/* 2854 */    MCD_OPC_Decode, 214, 26, 211, 1, // Opcode: VSDOTQ
+/* 2859 */    MCD_OPC_FilterValue, 1, 116, 1, 0, // Skip to: 3236
+/* 2864 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2867 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 2889
+/* 2872 */    MCD_OPC_CheckPredicate, 96, 103, 1, 0, // Skip to: 3236
+/* 2877 */    MCD_OPC_CheckField, 20, 2, 2, 96, 1, 0, // Skip to: 3236
+/* 2884 */    MCD_OPC_Decode, 184, 30, 210, 1, // Opcode: VUDOTD
+/* 2889 */    MCD_OPC_FilterValue, 1, 86, 1, 0, // Skip to: 3236
+/* 2894 */    MCD_OPC_CheckPredicate, 96, 81, 1, 0, // Skip to: 3236
+/* 2899 */    MCD_OPC_CheckField, 20, 2, 2, 74, 1, 0, // Skip to: 3236
+/* 2906 */    MCD_OPC_Decode, 186, 30, 211, 1, // Opcode: VUDOTQ
+/* 2911 */    MCD_OPC_FilterValue, 249, 3, 61, 0, 0, // Skip to: 2978
+/* 2917 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2920 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2949
+/* 2925 */    MCD_OPC_CheckPredicate, 95, 50, 1, 0, // Skip to: 3236
+/* 2930 */    MCD_OPC_CheckField, 20, 2, 2, 43, 1, 0, // Skip to: 3236
+/* 2937 */    MCD_OPC_CheckField, 4, 1, 0, 36, 1, 0, // Skip to: 3236
+/* 2944 */    MCD_OPC_Decode, 198, 30, 210, 1, // Opcode: VUSDOTD
+/* 2949 */    MCD_OPC_FilterValue, 1, 26, 1, 0, // Skip to: 3236
+/* 2954 */    MCD_OPC_CheckPredicate, 95, 21, 1, 0, // Skip to: 3236
+/* 2959 */    MCD_OPC_CheckField, 20, 2, 2, 14, 1, 0, // Skip to: 3236
+/* 2966 */    MCD_OPC_CheckField, 4, 1, 0, 7, 1, 0, // Skip to: 3236
+/* 2973 */    MCD_OPC_Decode, 200, 30, 211, 1, // Opcode: VUSDOTQ
+/* 2978 */    MCD_OPC_FilterValue, 252, 3, 139, 0, 0, // Skip to: 3123
+/* 2984 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 2987 */    MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 3071
+/* 2992 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2995 */    MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 3033
+/* 3000 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 3003 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3018
+/* 3008 */    MCD_OPC_CheckPredicate, 31, 223, 0, 0, // Skip to: 3236
+/* 3013 */    MCD_OPC_Decode, 214, 5, 218, 1, // Opcode: BF16VDOTI_VDOTD
+/* 3018 */    MCD_OPC_FilterValue, 2, 213, 0, 0, // Skip to: 3236
+/* 3023 */    MCD_OPC_CheckPredicate, 96, 208, 0, 0, // Skip to: 3236
+/* 3028 */    MCD_OPC_Decode, 213, 26, 218, 1, // Opcode: VSDOTDI
+/* 3033 */    MCD_OPC_FilterValue, 1, 198, 0, 0, // Skip to: 3236
+/* 3038 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 3041 */    MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 3056
+/* 3046 */    MCD_OPC_CheckPredicate, 31, 185, 0, 0, // Skip to: 3236
+/* 3051 */    MCD_OPC_Decode, 215, 5, 219, 1, // Opcode: BF16VDOTI_VDOTQ
+/* 3056 */    MCD_OPC_FilterValue, 2, 175, 0, 0, // Skip to: 3236
+/* 3061 */    MCD_OPC_CheckPredicate, 96, 170, 0, 0, // Skip to: 3236
+/* 3066 */    MCD_OPC_Decode, 215, 26, 219, 1, // Opcode: VSDOTQI
+/* 3071 */    MCD_OPC_FilterValue, 1, 160, 0, 0, // Skip to: 3236
+/* 3076 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3079 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3101
+/* 3084 */    MCD_OPC_CheckPredicate, 96, 147, 0, 0, // Skip to: 3236
+/* 3089 */    MCD_OPC_CheckField, 20, 2, 2, 140, 0, 0, // Skip to: 3236
+/* 3096 */    MCD_OPC_Decode, 185, 30, 218, 1, // Opcode: VUDOTDI
+/* 3101 */    MCD_OPC_FilterValue, 1, 130, 0, 0, // Skip to: 3236
+/* 3106 */    MCD_OPC_CheckPredicate, 96, 125, 0, 0, // Skip to: 3236
+/* 3111 */    MCD_OPC_CheckField, 20, 2, 2, 118, 0, 0, // Skip to: 3236
+/* 3118 */    MCD_OPC_Decode, 187, 30, 219, 1, // Opcode: VUDOTQI
+/* 3123 */    MCD_OPC_FilterValue, 253, 3, 107, 0, 0, // Skip to: 3236
+/* 3129 */    MCD_OPC_ExtractField, 4, 1,  // Inst{4} ...
+/* 3132 */    MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 3184
+/* 3137 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3140 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3162
+/* 3145 */    MCD_OPC_CheckPredicate, 95, 86, 0, 0, // Skip to: 3236
+/* 3150 */    MCD_OPC_CheckField, 20, 2, 0, 79, 0, 0, // Skip to: 3236
+/* 3157 */    MCD_OPC_Decode, 199, 30, 218, 1, // Opcode: VUSDOTDI
+/* 3162 */    MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 3236
+/* 3167 */    MCD_OPC_CheckPredicate, 95, 64, 0, 0, // Skip to: 3236
+/* 3172 */    MCD_OPC_CheckField, 20, 2, 0, 57, 0, 0, // Skip to: 3236
+/* 3179 */    MCD_OPC_Decode, 201, 30, 219, 1, // Opcode: VUSDOTQI
+/* 3184 */    MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 3236
+/* 3189 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 3192 */    MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 3214
+/* 3197 */    MCD_OPC_CheckPredicate, 95, 34, 0, 0, // Skip to: 3236
+/* 3202 */    MCD_OPC_CheckField, 20, 2, 0, 27, 0, 0, // Skip to: 3236
+/* 3209 */    MCD_OPC_Decode, 132, 30, 218, 1, // Opcode: VSUDOTDI
+/* 3214 */    MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 3236
+/* 3219 */    MCD_OPC_CheckPredicate, 95, 12, 0, 0, // Skip to: 3236
+/* 3224 */    MCD_OPC_CheckField, 20, 2, 0, 5, 0, 0, // Skip to: 3236
+/* 3231 */    MCD_OPC_Decode, 133, 30, 219, 1, // Opcode: VSUDOTQI
+/* 3236 */    MCD_OPC_Fail,
   0
 };
 
 static const uint8_t DecoderTablev8Crypto32[] = {
 /* 0 */       MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 3 */       MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 83
+/* 3 */       MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 85
 /* 8 */       MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 11 */      MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 47
-/* 17 */      MCD_OPC_CheckPredicate, 24, 12, 2, 0, // Skip to: 546
-/* 22 */      MCD_OPC_CheckField, 8, 4, 12, 5, 2, 0, // Skip to: 546
-/* 29 */      MCD_OPC_CheckField, 6, 1, 1, 254, 1, 0, // Skip to: 546
-/* 36 */      MCD_OPC_CheckField, 4, 1, 0, 247, 1, 0, // Skip to: 546
-/* 43 */      MCD_OPC_Decode, 247, 5, 106, // Opcode: SHA1C
-/* 47 */      MCD_OPC_FilterValue, 230, 3, 237, 1, 0, // Skip to: 546
-/* 53 */      MCD_OPC_CheckPredicate, 24, 232, 1, 0, // Skip to: 546
-/* 58 */      MCD_OPC_CheckField, 8, 4, 12, 225, 1, 0, // Skip to: 546
-/* 65 */      MCD_OPC_CheckField, 6, 1, 1, 218, 1, 0, // Skip to: 546
-/* 72 */      MCD_OPC_CheckField, 4, 1, 0, 211, 1, 0, // Skip to: 546
-/* 79 */      MCD_OPC_Decode, 253, 5, 106, // Opcode: SHA256H
-/* 83 */      MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 163
-/* 88 */      MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 91 */      MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 127
-/* 97 */      MCD_OPC_CheckPredicate, 24, 188, 1, 0, // Skip to: 546
-/* 102 */     MCD_OPC_CheckField, 8, 4, 12, 181, 1, 0, // Skip to: 546
-/* 109 */     MCD_OPC_CheckField, 6, 1, 1, 174, 1, 0, // Skip to: 546
-/* 116 */     MCD_OPC_CheckField, 4, 1, 0, 167, 1, 0, // Skip to: 546
-/* 123 */     MCD_OPC_Decode, 250, 5, 106, // Opcode: SHA1P
-/* 127 */     MCD_OPC_FilterValue, 230, 3, 157, 1, 0, // Skip to: 546
-/* 133 */     MCD_OPC_CheckPredicate, 24, 152, 1, 0, // Skip to: 546
-/* 138 */     MCD_OPC_CheckField, 8, 4, 12, 145, 1, 0, // Skip to: 546
-/* 145 */     MCD_OPC_CheckField, 6, 1, 1, 138, 1, 0, // Skip to: 546
-/* 152 */     MCD_OPC_CheckField, 4, 1, 0, 131, 1, 0, // Skip to: 546
-/* 159 */     MCD_OPC_Decode, 254, 5, 106, // Opcode: SHA256H2
-/* 163 */     MCD_OPC_FilterValue, 2, 75, 0, 0, // Skip to: 243
-/* 168 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
-/* 171 */     MCD_OPC_FilterValue, 228, 3, 30, 0, 0, // Skip to: 207
-/* 177 */     MCD_OPC_CheckPredicate, 24, 108, 1, 0, // Skip to: 546
-/* 182 */     MCD_OPC_CheckField, 8, 4, 12, 101, 1, 0, // Skip to: 546
-/* 189 */     MCD_OPC_CheckField, 6, 1, 1, 94, 1, 0, // Skip to: 546
-/* 196 */     MCD_OPC_CheckField, 4, 1, 0, 87, 1, 0, // Skip to: 546
-/* 203 */     MCD_OPC_Decode, 249, 5, 106, // Opcode: SHA1M
-/* 207 */     MCD_OPC_FilterValue, 230, 3, 77, 1, 0, // Skip to: 546
-/* 213 */     MCD_OPC_CheckPredicate, 24, 72, 1, 0, // Skip to: 546
-/* 218 */     MCD_OPC_CheckField, 8, 4, 12, 65, 1, 0, // Skip to: 546
-/* 225 */     MCD_OPC_CheckField, 6, 1, 1, 58, 1, 0, // Skip to: 546
-/* 232 */     MCD_OPC_CheckField, 4, 1, 0, 51, 1, 0, // Skip to: 546
-/* 239 */     MCD_OPC_Decode, 128, 6, 106, // Opcode: SHA256SU1
-/* 243 */     MCD_OPC_FilterValue, 3, 42, 1, 0, // Skip to: 546
-/* 248 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 251 */     MCD_OPC_FilterValue, 2, 38, 0, 0, // Skip to: 294
-/* 256 */     MCD_OPC_CheckPredicate, 24, 29, 1, 0, // Skip to: 546
-/* 261 */     MCD_OPC_CheckField, 23, 9, 231, 3, 21, 1, 0, // Skip to: 546
-/* 269 */     MCD_OPC_CheckField, 16, 4, 9, 14, 1, 0, // Skip to: 546
-/* 276 */     MCD_OPC_CheckField, 6, 2, 3, 7, 1, 0, // Skip to: 546
-/* 283 */     MCD_OPC_CheckField, 4, 1, 0, 0, 1, 0, // Skip to: 546
-/* 290 */     MCD_OPC_Decode, 248, 5, 127, // Opcode: SHA1H
-/* 294 */     MCD_OPC_FilterValue, 3, 211, 0, 0, // Skip to: 510
-/* 299 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 302 */     MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 339
-/* 307 */     MCD_OPC_CheckPredicate, 24, 234, 0, 0, // Skip to: 546
-/* 312 */     MCD_OPC_CheckField, 23, 9, 231, 3, 226, 0, 0, // Skip to: 546
-/* 320 */     MCD_OPC_CheckField, 16, 4, 0, 219, 0, 0, // Skip to: 546
-/* 327 */     MCD_OPC_CheckField, 4, 1, 0, 212, 0, 0, // Skip to: 546
-/* 334 */     MCD_OPC_Decode, 155, 4, 133, 1, // Opcode: AESE
-/* 339 */     MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 376
-/* 344 */     MCD_OPC_CheckPredicate, 24, 197, 0, 0, // Skip to: 546
-/* 349 */     MCD_OPC_CheckField, 23, 9, 231, 3, 189, 0, 0, // Skip to: 546
-/* 357 */     MCD_OPC_CheckField, 16, 4, 0, 182, 0, 0, // Skip to: 546
-/* 364 */     MCD_OPC_CheckField, 4, 1, 0, 175, 0, 0, // Skip to: 546
-/* 371 */     MCD_OPC_Decode, 154, 4, 133, 1, // Opcode: AESD
-/* 376 */     MCD_OPC_FilterValue, 2, 62, 0, 0, // Skip to: 443
-/* 381 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 384 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 413
-/* 389 */     MCD_OPC_CheckPredicate, 24, 152, 0, 0, // Skip to: 546
-/* 394 */     MCD_OPC_CheckField, 23, 9, 231, 3, 144, 0, 0, // Skip to: 546
-/* 402 */     MCD_OPC_CheckField, 4, 1, 0, 137, 0, 0, // Skip to: 546
-/* 409 */     MCD_OPC_Decode, 157, 4, 127, // Opcode: AESMC
-/* 413 */     MCD_OPC_FilterValue, 10, 128, 0, 0, // Skip to: 546
-/* 418 */     MCD_OPC_CheckPredicate, 24, 123, 0, 0, // Skip to: 546
-/* 423 */     MCD_OPC_CheckField, 23, 9, 231, 3, 115, 0, 0, // Skip to: 546
-/* 431 */     MCD_OPC_CheckField, 4, 1, 0, 108, 0, 0, // Skip to: 546
-/* 438 */     MCD_OPC_Decode, 252, 5, 133, 1, // Opcode: SHA1SU1
-/* 443 */     MCD_OPC_FilterValue, 3, 98, 0, 0, // Skip to: 546
-/* 448 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
-/* 451 */     MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 480
-/* 456 */     MCD_OPC_CheckPredicate, 24, 85, 0, 0, // Skip to: 546
-/* 461 */     MCD_OPC_CheckField, 23, 9, 231, 3, 77, 0, 0, // Skip to: 546
-/* 469 */     MCD_OPC_CheckField, 4, 1, 0, 70, 0, 0, // Skip to: 546
-/* 476 */     MCD_OPC_Decode, 156, 4, 127, // Opcode: AESIMC
-/* 480 */     MCD_OPC_FilterValue, 10, 61, 0, 0, // Skip to: 546
-/* 485 */     MCD_OPC_CheckPredicate, 24, 56, 0, 0, // Skip to: 546
-/* 490 */     MCD_OPC_CheckField, 23, 9, 231, 3, 48, 0, 0, // Skip to: 546
-/* 498 */     MCD_OPC_CheckField, 4, 1, 0, 41, 0, 0, // Skip to: 546
-/* 505 */     MCD_OPC_Decode, 255, 5, 133, 1, // Opcode: SHA256SU0
-/* 510 */     MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 546
-/* 515 */     MCD_OPC_CheckPredicate, 24, 26, 0, 0, // Skip to: 546
-/* 520 */     MCD_OPC_CheckField, 23, 9, 228, 3, 18, 0, 0, // Skip to: 546
-/* 528 */     MCD_OPC_CheckField, 6, 1, 1, 11, 0, 0, // Skip to: 546
-/* 535 */     MCD_OPC_CheckField, 4, 1, 0, 4, 0, 0, // Skip to: 546
-/* 542 */     MCD_OPC_Decode, 251, 5, 106, // Opcode: SHA1SU0
-/* 546 */     MCD_OPC_Fail,
+/* 11 */      MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 48
+/* 17 */      MCD_OPC_CheckPredicate, 97, 22, 2, 0, // Skip to: 556
+/* 22 */      MCD_OPC_CheckField, 8, 4, 12, 15, 2, 0, // Skip to: 556
+/* 29 */      MCD_OPC_CheckField, 6, 1, 1, 8, 2, 0, // Skip to: 556
+/* 36 */      MCD_OPC_CheckField, 4, 1, 0, 1, 2, 0, // Skip to: 556
+/* 43 */      MCD_OPC_Decode, 162, 14, 211, 1, // Opcode: SHA1C
+/* 48 */      MCD_OPC_FilterValue, 230, 3, 246, 1, 0, // Skip to: 556
+/* 54 */      MCD_OPC_CheckPredicate, 97, 241, 1, 0, // Skip to: 556
+/* 59 */      MCD_OPC_CheckField, 8, 4, 12, 234, 1, 0, // Skip to: 556
+/* 66 */      MCD_OPC_CheckField, 6, 1, 1, 227, 1, 0, // Skip to: 556
+/* 73 */      MCD_OPC_CheckField, 4, 1, 0, 220, 1, 0, // Skip to: 556
+/* 80 */      MCD_OPC_Decode, 168, 14, 211, 1, // Opcode: SHA256H
+/* 85 */      MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 167
+/* 90 */      MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 93 */      MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 130
+/* 99 */      MCD_OPC_CheckPredicate, 97, 196, 1, 0, // Skip to: 556
+/* 104 */     MCD_OPC_CheckField, 8, 4, 12, 189, 1, 0, // Skip to: 556
+/* 111 */     MCD_OPC_CheckField, 6, 1, 1, 182, 1, 0, // Skip to: 556
+/* 118 */     MCD_OPC_CheckField, 4, 1, 0, 175, 1, 0, // Skip to: 556
+/* 125 */     MCD_OPC_Decode, 165, 14, 211, 1, // Opcode: SHA1P
+/* 130 */     MCD_OPC_FilterValue, 230, 3, 164, 1, 0, // Skip to: 556
+/* 136 */     MCD_OPC_CheckPredicate, 97, 159, 1, 0, // Skip to: 556
+/* 141 */     MCD_OPC_CheckField, 8, 4, 12, 152, 1, 0, // Skip to: 556
+/* 148 */     MCD_OPC_CheckField, 6, 1, 1, 145, 1, 0, // Skip to: 556
+/* 155 */     MCD_OPC_CheckField, 4, 1, 0, 138, 1, 0, // Skip to: 556
+/* 162 */     MCD_OPC_Decode, 169, 14, 211, 1, // Opcode: SHA256H2
+/* 167 */     MCD_OPC_FilterValue, 2, 77, 0, 0, // Skip to: 249
+/* 172 */     MCD_OPC_ExtractField, 23, 9,  // Inst{31-23} ...
+/* 175 */     MCD_OPC_FilterValue, 228, 3, 31, 0, 0, // Skip to: 212
+/* 181 */     MCD_OPC_CheckPredicate, 97, 114, 1, 0, // Skip to: 556
+/* 186 */     MCD_OPC_CheckField, 8, 4, 12, 107, 1, 0, // Skip to: 556
+/* 193 */     MCD_OPC_CheckField, 6, 1, 1, 100, 1, 0, // Skip to: 556
+/* 200 */     MCD_OPC_CheckField, 4, 1, 0, 93, 1, 0, // Skip to: 556
+/* 207 */     MCD_OPC_Decode, 164, 14, 211, 1, // Opcode: SHA1M
+/* 212 */     MCD_OPC_FilterValue, 230, 3, 82, 1, 0, // Skip to: 556
+/* 218 */     MCD_OPC_CheckPredicate, 97, 77, 1, 0, // Skip to: 556
+/* 223 */     MCD_OPC_CheckField, 8, 4, 12, 70, 1, 0, // Skip to: 556
+/* 230 */     MCD_OPC_CheckField, 6, 1, 1, 63, 1, 0, // Skip to: 556
+/* 237 */     MCD_OPC_CheckField, 4, 1, 0, 56, 1, 0, // Skip to: 556
+/* 244 */     MCD_OPC_Decode, 171, 14, 211, 1, // Opcode: SHA256SU1
+/* 249 */     MCD_OPC_FilterValue, 3, 46, 1, 0, // Skip to: 556
+/* 254 */     MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
+/* 257 */     MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 301
+/* 262 */     MCD_OPC_CheckPredicate, 97, 33, 1, 0, // Skip to: 556
+/* 267 */     MCD_OPC_CheckField, 23, 9, 231, 3, 25, 1, 0, // Skip to: 556
+/* 275 */     MCD_OPC_CheckField, 16, 4, 9, 18, 1, 0, // Skip to: 556
+/* 282 */     MCD_OPC_CheckField, 6, 2, 3, 11, 1, 0, // Skip to: 556
+/* 289 */     MCD_OPC_CheckField, 4, 1, 0, 4, 1, 0, // Skip to: 556
+/* 296 */     MCD_OPC_Decode, 163, 14, 232, 1, // Opcode: SHA1H
+/* 301 */     MCD_OPC_FilterValue, 3, 213, 0, 0, // Skip to: 519
+/* 306 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 309 */     MCD_OPC_FilterValue, 0, 32, 0, 0, // Skip to: 346
+/* 314 */     MCD_OPC_CheckPredicate, 29, 237, 0, 0, // Skip to: 556
+/* 319 */     MCD_OPC_CheckField, 23, 9, 231, 3, 229, 0, 0, // Skip to: 556
+/* 327 */     MCD_OPC_CheckField, 16, 4, 0, 222, 0, 0, // Skip to: 556
+/* 334 */     MCD_OPC_CheckField, 4, 1, 0, 215, 0, 0, // Skip to: 556
+/* 341 */     MCD_OPC_Decode, 207, 5, 238, 1, // Opcode: AESE
+/* 346 */     MCD_OPC_FilterValue, 1, 32, 0, 0, // Skip to: 383
+/* 351 */     MCD_OPC_CheckPredicate, 29, 200, 0, 0, // Skip to: 556
+/* 356 */     MCD_OPC_CheckField, 23, 9, 231, 3, 192, 0, 0, // Skip to: 556
+/* 364 */     MCD_OPC_CheckField, 16, 4, 0, 185, 0, 0, // Skip to: 556
+/* 371 */     MCD_OPC_CheckField, 4, 1, 0, 178, 0, 0, // Skip to: 556
+/* 378 */     MCD_OPC_Decode, 206, 5, 238, 1, // Opcode: AESD
+/* 383 */     MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 451
+/* 388 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 391 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 421
+/* 396 */     MCD_OPC_CheckPredicate, 29, 155, 0, 0, // Skip to: 556
+/* 401 */     MCD_OPC_CheckField, 23, 9, 231, 3, 147, 0, 0, // Skip to: 556
+/* 409 */     MCD_OPC_CheckField, 4, 1, 0, 140, 0, 0, // Skip to: 556
+/* 416 */     MCD_OPC_Decode, 209, 5, 232, 1, // Opcode: AESMC
+/* 421 */     MCD_OPC_FilterValue, 10, 130, 0, 0, // Skip to: 556
+/* 426 */     MCD_OPC_CheckPredicate, 97, 125, 0, 0, // Skip to: 556
+/* 431 */     MCD_OPC_CheckField, 23, 9, 231, 3, 117, 0, 0, // Skip to: 556
+/* 439 */     MCD_OPC_CheckField, 4, 1, 0, 110, 0, 0, // Skip to: 556
+/* 446 */     MCD_OPC_Decode, 167, 14, 238, 1, // Opcode: SHA1SU1
+/* 451 */     MCD_OPC_FilterValue, 3, 100, 0, 0, // Skip to: 556
+/* 456 */     MCD_OPC_ExtractField, 16, 4,  // Inst{19-16} ...
+/* 459 */     MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 489
+/* 464 */     MCD_OPC_CheckPredicate, 29, 87, 0, 0, // Skip to: 556
+/* 469 */     MCD_OPC_CheckField, 23, 9, 231, 3, 79, 0, 0, // Skip to: 556
+/* 477 */     MCD_OPC_CheckField, 4, 1, 0, 72, 0, 0, // Skip to: 556
+/* 484 */     MCD_OPC_Decode, 208, 5, 232, 1, // Opcode: AESIMC
+/* 489 */     MCD_OPC_FilterValue, 10, 62, 0, 0, // Skip to: 556
+/* 494 */     MCD_OPC_CheckPredicate, 97, 57, 0, 0, // Skip to: 556
+/* 499 */     MCD_OPC_CheckField, 23, 9, 231, 3, 49, 0, 0, // Skip to: 556
+/* 507 */     MCD_OPC_CheckField, 4, 1, 0, 42, 0, 0, // Skip to: 556
+/* 514 */     MCD_OPC_Decode, 170, 14, 238, 1, // Opcode: SHA256SU0
+/* 519 */     MCD_OPC_FilterValue, 12, 32, 0, 0, // Skip to: 556
+/* 524 */     MCD_OPC_CheckPredicate, 97, 27, 0, 0, // Skip to: 556
+/* 529 */     MCD_OPC_CheckField, 23, 9, 228, 3, 19, 0, 0, // Skip to: 556
+/* 537 */     MCD_OPC_CheckField, 6, 1, 1, 12, 0, 0, // Skip to: 556
+/* 544 */     MCD_OPC_CheckField, 4, 1, 0, 5, 0, 0, // Skip to: 556
+/* 551 */     MCD_OPC_Decode, 166, 14, 211, 1, // Opcode: SHA1SU0
+/* 556 */     MCD_OPC_Fail,
   0
 };
 
 static const uint8_t DecoderTablev8NEON32[] = {
 /* 0 */       MCD_OPC_ExtractField, 8, 4,  // Inst{11-8} ...
-/* 3 */       MCD_OPC_FilterValue, 0, 11, 1, 0, // Skip to: 275
+/* 3 */       MCD_OPC_FilterValue, 0, 19, 1, 0, // Skip to: 283
 /* 8 */       MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 11 */      MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 77
+/* 11 */      MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 79
 /* 16 */      MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 19 */      MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 48
-/* 24 */      MCD_OPC_CheckPredicate, 74, 110, 8, 0, // Skip to: 2187
-/* 29 */      MCD_OPC_CheckField, 23, 9, 231, 3, 102, 8, 0, // Skip to: 2187
-/* 37 */      MCD_OPC_CheckField, 4, 1, 0, 95, 8, 0, // Skip to: 2187
-/* 44 */      MCD_OPC_Decode, 154, 9, 126, // Opcode: VCVTANSDh
-/* 48 */      MCD_OPC_FilterValue, 59, 86, 8, 0, // Skip to: 2187
-/* 53 */      MCD_OPC_CheckPredicate, 75, 81, 8, 0, // Skip to: 2187
-/* 58 */      MCD_OPC_CheckField, 23, 9, 231, 3, 73, 8, 0, // Skip to: 2187
-/* 66 */      MCD_OPC_CheckField, 4, 1, 0, 66, 8, 0, // Skip to: 2187
-/* 73 */      MCD_OPC_Decode, 153, 9, 126, // Opcode: VCVTANSDf
-/* 77 */      MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 143
-/* 82 */      MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 85 */      MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 114
-/* 90 */      MCD_OPC_CheckPredicate, 74, 44, 8, 0, // Skip to: 2187
-/* 95 */      MCD_OPC_CheckField, 23, 9, 231, 3, 36, 8, 0, // Skip to: 2187
-/* 103 */     MCD_OPC_CheckField, 4, 1, 0, 29, 8, 0, // Skip to: 2187
-/* 110 */     MCD_OPC_Decode, 156, 9, 127, // Opcode: VCVTANSQh
-/* 114 */     MCD_OPC_FilterValue, 59, 20, 8, 0, // Skip to: 2187
-/* 119 */     MCD_OPC_CheckPredicate, 75, 15, 8, 0, // Skip to: 2187
-/* 124 */     MCD_OPC_CheckField, 23, 9, 231, 3, 7, 8, 0, // Skip to: 2187
-/* 132 */     MCD_OPC_CheckField, 4, 1, 0, 0, 8, 0, // Skip to: 2187
-/* 139 */     MCD_OPC_Decode, 155, 9, 127, // Opcode: VCVTANSQf
-/* 143 */     MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 209
-/* 148 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 151 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 180
-/* 156 */     MCD_OPC_CheckPredicate, 74, 234, 7, 0, // Skip to: 2187
-/* 161 */     MCD_OPC_CheckField, 23, 9, 231, 3, 226, 7, 0, // Skip to: 2187
-/* 169 */     MCD_OPC_CheckField, 4, 1, 0, 219, 7, 0, // Skip to: 2187
-/* 176 */     MCD_OPC_Decode, 158, 9, 126, // Opcode: VCVTANUDh
-/* 180 */     MCD_OPC_FilterValue, 59, 210, 7, 0, // Skip to: 2187
-/* 185 */     MCD_OPC_CheckPredicate, 75, 205, 7, 0, // Skip to: 2187
-/* 190 */     MCD_OPC_CheckField, 23, 9, 231, 3, 197, 7, 0, // Skip to: 2187
-/* 198 */     MCD_OPC_CheckField, 4, 1, 0, 190, 7, 0, // Skip to: 2187
-/* 205 */     MCD_OPC_Decode, 157, 9, 126, // Opcode: VCVTANUDf
-/* 209 */     MCD_OPC_FilterValue, 3, 181, 7, 0, // Skip to: 2187
-/* 214 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 217 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 246
-/* 222 */     MCD_OPC_CheckPredicate, 74, 168, 7, 0, // Skip to: 2187
-/* 227 */     MCD_OPC_CheckField, 23, 9, 231, 3, 160, 7, 0, // Skip to: 2187
-/* 235 */     MCD_OPC_CheckField, 4, 1, 0, 153, 7, 0, // Skip to: 2187
-/* 242 */     MCD_OPC_Decode, 160, 9, 127, // Opcode: VCVTANUQh
-/* 246 */     MCD_OPC_FilterValue, 59, 144, 7, 0, // Skip to: 2187
-/* 251 */     MCD_OPC_CheckPredicate, 75, 139, 7, 0, // Skip to: 2187
-/* 256 */     MCD_OPC_CheckField, 23, 9, 231, 3, 131, 7, 0, // Skip to: 2187
-/* 264 */     MCD_OPC_CheckField, 4, 1, 0, 124, 7, 0, // Skip to: 2187
-/* 271 */     MCD_OPC_Decode, 159, 9, 127, // Opcode: VCVTANUQf
-/* 275 */     MCD_OPC_FilterValue, 1, 11, 1, 0, // Skip to: 547
-/* 280 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 283 */     MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 349
-/* 288 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 291 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 320
-/* 296 */     MCD_OPC_CheckPredicate, 74, 94, 7, 0, // Skip to: 2187
-/* 301 */     MCD_OPC_CheckField, 23, 9, 231, 3, 86, 7, 0, // Skip to: 2187
-/* 309 */     MCD_OPC_CheckField, 4, 1, 0, 79, 7, 0, // Skip to: 2187
-/* 316 */     MCD_OPC_Decode, 187, 9, 126, // Opcode: VCVTNNSDh
-/* 320 */     MCD_OPC_FilterValue, 59, 70, 7, 0, // Skip to: 2187
-/* 325 */     MCD_OPC_CheckPredicate, 75, 65, 7, 0, // Skip to: 2187
-/* 330 */     MCD_OPC_CheckField, 23, 9, 231, 3, 57, 7, 0, // Skip to: 2187
-/* 338 */     MCD_OPC_CheckField, 4, 1, 0, 50, 7, 0, // Skip to: 2187
-/* 345 */     MCD_OPC_Decode, 186, 9, 126, // Opcode: VCVTNNSDf
-/* 349 */     MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 415
-/* 354 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 357 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 386
-/* 362 */     MCD_OPC_CheckPredicate, 74, 28, 7, 0, // Skip to: 2187
-/* 367 */     MCD_OPC_CheckField, 23, 9, 231, 3, 20, 7, 0, // Skip to: 2187
-/* 375 */     MCD_OPC_CheckField, 4, 1, 0, 13, 7, 0, // Skip to: 2187
-/* 382 */     MCD_OPC_Decode, 189, 9, 127, // Opcode: VCVTNNSQh
-/* 386 */     MCD_OPC_FilterValue, 59, 4, 7, 0, // Skip to: 2187
-/* 391 */     MCD_OPC_CheckPredicate, 75, 255, 6, 0, // Skip to: 2187
-/* 396 */     MCD_OPC_CheckField, 23, 9, 231, 3, 247, 6, 0, // Skip to: 2187
-/* 404 */     MCD_OPC_CheckField, 4, 1, 0, 240, 6, 0, // Skip to: 2187
-/* 411 */     MCD_OPC_Decode, 188, 9, 127, // Opcode: VCVTNNSQf
-/* 415 */     MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 481
-/* 420 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 423 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 452
-/* 428 */     MCD_OPC_CheckPredicate, 74, 218, 6, 0, // Skip to: 2187
-/* 433 */     MCD_OPC_CheckField, 23, 9, 231, 3, 210, 6, 0, // Skip to: 2187
-/* 441 */     MCD_OPC_CheckField, 4, 1, 0, 203, 6, 0, // Skip to: 2187
-/* 448 */     MCD_OPC_Decode, 191, 9, 126, // Opcode: VCVTNNUDh
-/* 452 */     MCD_OPC_FilterValue, 59, 194, 6, 0, // Skip to: 2187
-/* 457 */     MCD_OPC_CheckPredicate, 75, 189, 6, 0, // Skip to: 2187
-/* 462 */     MCD_OPC_CheckField, 23, 9, 231, 3, 181, 6, 0, // Skip to: 2187
-/* 470 */     MCD_OPC_CheckField, 4, 1, 0, 174, 6, 0, // Skip to: 2187
-/* 477 */     MCD_OPC_Decode, 190, 9, 126, // Opcode: VCVTNNUDf
-/* 481 */     MCD_OPC_FilterValue, 3, 165, 6, 0, // Skip to: 2187
-/* 486 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 489 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 518
-/* 494 */     MCD_OPC_CheckPredicate, 74, 152, 6, 0, // Skip to: 2187
-/* 499 */     MCD_OPC_CheckField, 23, 9, 231, 3, 144, 6, 0, // Skip to: 2187
-/* 507 */     MCD_OPC_CheckField, 4, 1, 0, 137, 6, 0, // Skip to: 2187
-/* 514 */     MCD_OPC_Decode, 193, 9, 127, // Opcode: VCVTNNUQh
-/* 518 */     MCD_OPC_FilterValue, 59, 128, 6, 0, // Skip to: 2187
-/* 523 */     MCD_OPC_CheckPredicate, 75, 123, 6, 0, // Skip to: 2187
-/* 528 */     MCD_OPC_CheckField, 23, 9, 231, 3, 115, 6, 0, // Skip to: 2187
-/* 536 */     MCD_OPC_CheckField, 4, 1, 0, 108, 6, 0, // Skip to: 2187
-/* 543 */     MCD_OPC_Decode, 192, 9, 127, // Opcode: VCVTNNUQf
-/* 547 */     MCD_OPC_FilterValue, 2, 11, 1, 0, // Skip to: 819
-/* 552 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 555 */     MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 621
-/* 560 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 563 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 592
-/* 568 */     MCD_OPC_CheckPredicate, 74, 78, 6, 0, // Skip to: 2187
-/* 573 */     MCD_OPC_CheckField, 23, 9, 231, 3, 70, 6, 0, // Skip to: 2187
-/* 581 */     MCD_OPC_CheckField, 4, 1, 0, 63, 6, 0, // Skip to: 2187
-/* 588 */     MCD_OPC_Decode, 201, 9, 126, // Opcode: VCVTPNSDh
-/* 592 */     MCD_OPC_FilterValue, 59, 54, 6, 0, // Skip to: 2187
-/* 597 */     MCD_OPC_CheckPredicate, 75, 49, 6, 0, // Skip to: 2187
-/* 602 */     MCD_OPC_CheckField, 23, 9, 231, 3, 41, 6, 0, // Skip to: 2187
-/* 610 */     MCD_OPC_CheckField, 4, 1, 0, 34, 6, 0, // Skip to: 2187
-/* 617 */     MCD_OPC_Decode, 200, 9, 126, // Opcode: VCVTPNSDf
-/* 621 */     MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 687
-/* 626 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 629 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 658
-/* 634 */     MCD_OPC_CheckPredicate, 74, 12, 6, 0, // Skip to: 2187
-/* 639 */     MCD_OPC_CheckField, 23, 9, 231, 3, 4, 6, 0, // Skip to: 2187
-/* 647 */     MCD_OPC_CheckField, 4, 1, 0, 253, 5, 0, // Skip to: 2187
-/* 654 */     MCD_OPC_Decode, 203, 9, 127, // Opcode: VCVTPNSQh
-/* 658 */     MCD_OPC_FilterValue, 59, 244, 5, 0, // Skip to: 2187
-/* 663 */     MCD_OPC_CheckPredicate, 75, 239, 5, 0, // Skip to: 2187
-/* 668 */     MCD_OPC_CheckField, 23, 9, 231, 3, 231, 5, 0, // Skip to: 2187
-/* 676 */     MCD_OPC_CheckField, 4, 1, 0, 224, 5, 0, // Skip to: 2187
-/* 683 */     MCD_OPC_Decode, 202, 9, 127, // Opcode: VCVTPNSQf
-/* 687 */     MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 753
-/* 692 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 695 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 724
-/* 700 */     MCD_OPC_CheckPredicate, 74, 202, 5, 0, // Skip to: 2187
-/* 705 */     MCD_OPC_CheckField, 23, 9, 231, 3, 194, 5, 0, // Skip to: 2187
-/* 713 */     MCD_OPC_CheckField, 4, 1, 0, 187, 5, 0, // Skip to: 2187
-/* 720 */     MCD_OPC_Decode, 205, 9, 126, // Opcode: VCVTPNUDh
-/* 724 */     MCD_OPC_FilterValue, 59, 178, 5, 0, // Skip to: 2187
-/* 729 */     MCD_OPC_CheckPredicate, 75, 173, 5, 0, // Skip to: 2187
-/* 734 */     MCD_OPC_CheckField, 23, 9, 231, 3, 165, 5, 0, // Skip to: 2187
-/* 742 */     MCD_OPC_CheckField, 4, 1, 0, 158, 5, 0, // Skip to: 2187
-/* 749 */     MCD_OPC_Decode, 204, 9, 126, // Opcode: VCVTPNUDf
-/* 753 */     MCD_OPC_FilterValue, 3, 149, 5, 0, // Skip to: 2187
-/* 758 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 761 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 790
-/* 766 */     MCD_OPC_CheckPredicate, 74, 136, 5, 0, // Skip to: 2187
-/* 771 */     MCD_OPC_CheckField, 23, 9, 231, 3, 128, 5, 0, // Skip to: 2187
-/* 779 */     MCD_OPC_CheckField, 4, 1, 0, 121, 5, 0, // Skip to: 2187
-/* 786 */     MCD_OPC_Decode, 207, 9, 127, // Opcode: VCVTPNUQh
-/* 790 */     MCD_OPC_FilterValue, 59, 112, 5, 0, // Skip to: 2187
-/* 795 */     MCD_OPC_CheckPredicate, 75, 107, 5, 0, // Skip to: 2187
-/* 800 */     MCD_OPC_CheckField, 23, 9, 231, 3, 99, 5, 0, // Skip to: 2187
-/* 808 */     MCD_OPC_CheckField, 4, 1, 0, 92, 5, 0, // Skip to: 2187
-/* 815 */     MCD_OPC_Decode, 206, 9, 127, // Opcode: VCVTPNUQf
-/* 819 */     MCD_OPC_FilterValue, 3, 11, 1, 0, // Skip to: 1091
-/* 824 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 827 */     MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 893
-/* 832 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 835 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 864
-/* 840 */     MCD_OPC_CheckPredicate, 74, 62, 5, 0, // Skip to: 2187
-/* 845 */     MCD_OPC_CheckField, 23, 9, 231, 3, 54, 5, 0, // Skip to: 2187
-/* 853 */     MCD_OPC_CheckField, 4, 1, 0, 47, 5, 0, // Skip to: 2187
-/* 860 */     MCD_OPC_Decode, 173, 9, 126, // Opcode: VCVTMNSDh
-/* 864 */     MCD_OPC_FilterValue, 59, 38, 5, 0, // Skip to: 2187
-/* 869 */     MCD_OPC_CheckPredicate, 75, 33, 5, 0, // Skip to: 2187
-/* 874 */     MCD_OPC_CheckField, 23, 9, 231, 3, 25, 5, 0, // Skip to: 2187
-/* 882 */     MCD_OPC_CheckField, 4, 1, 0, 18, 5, 0, // Skip to: 2187
-/* 889 */     MCD_OPC_Decode, 172, 9, 126, // Opcode: VCVTMNSDf
-/* 893 */     MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 959
-/* 898 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 901 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 930
-/* 906 */     MCD_OPC_CheckPredicate, 74, 252, 4, 0, // Skip to: 2187
-/* 911 */     MCD_OPC_CheckField, 23, 9, 231, 3, 244, 4, 0, // Skip to: 2187
-/* 919 */     MCD_OPC_CheckField, 4, 1, 0, 237, 4, 0, // Skip to: 2187
-/* 926 */     MCD_OPC_Decode, 175, 9, 127, // Opcode: VCVTMNSQh
-/* 930 */     MCD_OPC_FilterValue, 59, 228, 4, 0, // Skip to: 2187
-/* 935 */     MCD_OPC_CheckPredicate, 75, 223, 4, 0, // Skip to: 2187
-/* 940 */     MCD_OPC_CheckField, 23, 9, 231, 3, 215, 4, 0, // Skip to: 2187
-/* 948 */     MCD_OPC_CheckField, 4, 1, 0, 208, 4, 0, // Skip to: 2187
-/* 955 */     MCD_OPC_Decode, 174, 9, 127, // Opcode: VCVTMNSQf
-/* 959 */     MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1025
-/* 964 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 967 */     MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 996
-/* 972 */     MCD_OPC_CheckPredicate, 74, 186, 4, 0, // Skip to: 2187
-/* 977 */     MCD_OPC_CheckField, 23, 9, 231, 3, 178, 4, 0, // Skip to: 2187
-/* 985 */     MCD_OPC_CheckField, 4, 1, 0, 171, 4, 0, // Skip to: 2187
-/* 992 */     MCD_OPC_Decode, 177, 9, 126, // Opcode: VCVTMNUDh
-/* 996 */     MCD_OPC_FilterValue, 59, 162, 4, 0, // Skip to: 2187
-/* 1001 */    MCD_OPC_CheckPredicate, 75, 157, 4, 0, // Skip to: 2187
-/* 1006 */    MCD_OPC_CheckField, 23, 9, 231, 3, 149, 4, 0, // Skip to: 2187
-/* 1014 */    MCD_OPC_CheckField, 4, 1, 0, 142, 4, 0, // Skip to: 2187
-/* 1021 */    MCD_OPC_Decode, 176, 9, 126, // Opcode: VCVTMNUDf
-/* 1025 */    MCD_OPC_FilterValue, 3, 133, 4, 0, // Skip to: 2187
-/* 1030 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1033 */    MCD_OPC_FilterValue, 55, 24, 0, 0, // Skip to: 1062
-/* 1038 */    MCD_OPC_CheckPredicate, 74, 120, 4, 0, // Skip to: 2187
-/* 1043 */    MCD_OPC_CheckField, 23, 9, 231, 3, 112, 4, 0, // Skip to: 2187
-/* 1051 */    MCD_OPC_CheckField, 4, 1, 0, 105, 4, 0, // Skip to: 2187
-/* 1058 */    MCD_OPC_Decode, 179, 9, 127, // Opcode: VCVTMNUQh
-/* 1062 */    MCD_OPC_FilterValue, 59, 96, 4, 0, // Skip to: 2187
-/* 1067 */    MCD_OPC_CheckPredicate, 75, 91, 4, 0, // Skip to: 2187
-/* 1072 */    MCD_OPC_CheckField, 23, 9, 231, 3, 83, 4, 0, // Skip to: 2187
-/* 1080 */    MCD_OPC_CheckField, 4, 1, 0, 76, 4, 0, // Skip to: 2187
-/* 1087 */    MCD_OPC_Decode, 178, 9, 127, // Opcode: VCVTMNUQf
-/* 1091 */    MCD_OPC_FilterValue, 4, 11, 1, 0, // Skip to: 1363
-/* 1096 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 1099 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1165
-/* 1104 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1107 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1136
-/* 1112 */    MCD_OPC_CheckPredicate, 74, 46, 4, 0, // Skip to: 2187
-/* 1117 */    MCD_OPC_CheckField, 23, 9, 231, 3, 38, 4, 0, // Skip to: 2187
-/* 1125 */    MCD_OPC_CheckField, 4, 1, 0, 31, 4, 0, // Skip to: 2187
-/* 1132 */    MCD_OPC_Decode, 136, 17, 126, // Opcode: VRINTNNDh
-/* 1136 */    MCD_OPC_FilterValue, 58, 22, 4, 0, // Skip to: 2187
-/* 1141 */    MCD_OPC_CheckPredicate, 75, 17, 4, 0, // Skip to: 2187
-/* 1146 */    MCD_OPC_CheckField, 23, 9, 231, 3, 9, 4, 0, // Skip to: 2187
-/* 1154 */    MCD_OPC_CheckField, 4, 1, 0, 2, 4, 0, // Skip to: 2187
-/* 1161 */    MCD_OPC_Decode, 135, 17, 126, // Opcode: VRINTNNDf
-/* 1165 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1231
-/* 1170 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1173 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1202
-/* 1178 */    MCD_OPC_CheckPredicate, 74, 236, 3, 0, // Skip to: 2187
-/* 1183 */    MCD_OPC_CheckField, 23, 9, 231, 3, 228, 3, 0, // Skip to: 2187
-/* 1191 */    MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 2187
-/* 1198 */    MCD_OPC_Decode, 138, 17, 127, // Opcode: VRINTNNQh
-/* 1202 */    MCD_OPC_FilterValue, 58, 212, 3, 0, // Skip to: 2187
-/* 1207 */    MCD_OPC_CheckPredicate, 75, 207, 3, 0, // Skip to: 2187
-/* 1212 */    MCD_OPC_CheckField, 23, 9, 231, 3, 199, 3, 0, // Skip to: 2187
-/* 1220 */    MCD_OPC_CheckField, 4, 1, 0, 192, 3, 0, // Skip to: 2187
-/* 1227 */    MCD_OPC_Decode, 137, 17, 127, // Opcode: VRINTNNQf
-/* 1231 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1297
-/* 1236 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1239 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1268
-/* 1244 */    MCD_OPC_CheckPredicate, 74, 170, 3, 0, // Skip to: 2187
-/* 1249 */    MCD_OPC_CheckField, 23, 9, 231, 3, 162, 3, 0, // Skip to: 2187
-/* 1257 */    MCD_OPC_CheckField, 4, 1, 0, 155, 3, 0, // Skip to: 2187
-/* 1264 */    MCD_OPC_Decode, 153, 17, 126, // Opcode: VRINTXNDh
-/* 1268 */    MCD_OPC_FilterValue, 58, 146, 3, 0, // Skip to: 2187
-/* 1273 */    MCD_OPC_CheckPredicate, 75, 141, 3, 0, // Skip to: 2187
-/* 1278 */    MCD_OPC_CheckField, 23, 9, 231, 3, 133, 3, 0, // Skip to: 2187
-/* 1286 */    MCD_OPC_CheckField, 4, 1, 0, 126, 3, 0, // Skip to: 2187
-/* 1293 */    MCD_OPC_Decode, 152, 17, 126, // Opcode: VRINTXNDf
-/* 1297 */    MCD_OPC_FilterValue, 3, 117, 3, 0, // Skip to: 2187
-/* 1302 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1305 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1334
-/* 1310 */    MCD_OPC_CheckPredicate, 74, 104, 3, 0, // Skip to: 2187
-/* 1315 */    MCD_OPC_CheckField, 23, 9, 231, 3, 96, 3, 0, // Skip to: 2187
-/* 1323 */    MCD_OPC_CheckField, 4, 1, 0, 89, 3, 0, // Skip to: 2187
-/* 1330 */    MCD_OPC_Decode, 155, 17, 127, // Opcode: VRINTXNQh
-/* 1334 */    MCD_OPC_FilterValue, 58, 80, 3, 0, // Skip to: 2187
-/* 1339 */    MCD_OPC_CheckPredicate, 75, 75, 3, 0, // Skip to: 2187
-/* 1344 */    MCD_OPC_CheckField, 23, 9, 231, 3, 67, 3, 0, // Skip to: 2187
-/* 1352 */    MCD_OPC_CheckField, 4, 1, 0, 60, 3, 0, // Skip to: 2187
-/* 1359 */    MCD_OPC_Decode, 154, 17, 127, // Opcode: VRINTXNQf
-/* 1363 */    MCD_OPC_FilterValue, 5, 11, 1, 0, // Skip to: 1635
-/* 1368 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 1371 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1437
-/* 1376 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1379 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1408
-/* 1384 */    MCD_OPC_CheckPredicate, 74, 30, 3, 0, // Skip to: 2187
-/* 1389 */    MCD_OPC_CheckField, 23, 9, 231, 3, 22, 3, 0, // Skip to: 2187
-/* 1397 */    MCD_OPC_CheckField, 4, 1, 0, 15, 3, 0, // Skip to: 2187
-/* 1404 */    MCD_OPC_Decode, 250, 16, 126, // Opcode: VRINTANDh
-/* 1408 */    MCD_OPC_FilterValue, 58, 6, 3, 0, // Skip to: 2187
-/* 1413 */    MCD_OPC_CheckPredicate, 75, 1, 3, 0, // Skip to: 2187
-/* 1418 */    MCD_OPC_CheckField, 23, 9, 231, 3, 249, 2, 0, // Skip to: 2187
-/* 1426 */    MCD_OPC_CheckField, 4, 1, 0, 242, 2, 0, // Skip to: 2187
-/* 1433 */    MCD_OPC_Decode, 249, 16, 126, // Opcode: VRINTANDf
-/* 1437 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 1503
-/* 1442 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1445 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1474
-/* 1450 */    MCD_OPC_CheckPredicate, 74, 220, 2, 0, // Skip to: 2187
-/* 1455 */    MCD_OPC_CheckField, 23, 9, 231, 3, 212, 2, 0, // Skip to: 2187
-/* 1463 */    MCD_OPC_CheckField, 4, 1, 0, 205, 2, 0, // Skip to: 2187
-/* 1470 */    MCD_OPC_Decode, 252, 16, 127, // Opcode: VRINTANQh
-/* 1474 */    MCD_OPC_FilterValue, 58, 196, 2, 0, // Skip to: 2187
-/* 1479 */    MCD_OPC_CheckPredicate, 75, 191, 2, 0, // Skip to: 2187
-/* 1484 */    MCD_OPC_CheckField, 23, 9, 231, 3, 183, 2, 0, // Skip to: 2187
-/* 1492 */    MCD_OPC_CheckField, 4, 1, 0, 176, 2, 0, // Skip to: 2187
-/* 1499 */    MCD_OPC_Decode, 251, 16, 127, // Opcode: VRINTANQf
-/* 1503 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1569
-/* 1508 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1511 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1540
-/* 1516 */    MCD_OPC_CheckPredicate, 74, 154, 2, 0, // Skip to: 2187
-/* 1521 */    MCD_OPC_CheckField, 23, 9, 231, 3, 146, 2, 0, // Skip to: 2187
-/* 1529 */    MCD_OPC_CheckField, 4, 1, 0, 139, 2, 0, // Skip to: 2187
-/* 1536 */    MCD_OPC_Decode, 160, 17, 126, // Opcode: VRINTZNDh
-/* 1540 */    MCD_OPC_FilterValue, 58, 130, 2, 0, // Skip to: 2187
-/* 1545 */    MCD_OPC_CheckPredicate, 75, 125, 2, 0, // Skip to: 2187
-/* 1550 */    MCD_OPC_CheckField, 23, 9, 231, 3, 117, 2, 0, // Skip to: 2187
-/* 1558 */    MCD_OPC_CheckField, 4, 1, 0, 110, 2, 0, // Skip to: 2187
-/* 1565 */    MCD_OPC_Decode, 159, 17, 126, // Opcode: VRINTZNDf
-/* 1569 */    MCD_OPC_FilterValue, 3, 101, 2, 0, // Skip to: 2187
-/* 1574 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1577 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1606
-/* 1582 */    MCD_OPC_CheckPredicate, 74, 88, 2, 0, // Skip to: 2187
-/* 1587 */    MCD_OPC_CheckField, 23, 9, 231, 3, 80, 2, 0, // Skip to: 2187
-/* 1595 */    MCD_OPC_CheckField, 4, 1, 0, 73, 2, 0, // Skip to: 2187
-/* 1602 */    MCD_OPC_Decode, 162, 17, 127, // Opcode: VRINTZNQh
-/* 1606 */    MCD_OPC_FilterValue, 58, 64, 2, 0, // Skip to: 2187
-/* 1611 */    MCD_OPC_CheckPredicate, 75, 59, 2, 0, // Skip to: 2187
-/* 1616 */    MCD_OPC_CheckField, 23, 9, 231, 3, 51, 2, 0, // Skip to: 2187
-/* 1624 */    MCD_OPC_CheckField, 4, 1, 0, 44, 2, 0, // Skip to: 2187
-/* 1631 */    MCD_OPC_Decode, 161, 17, 127, // Opcode: VRINTZNQf
-/* 1635 */    MCD_OPC_FilterValue, 6, 135, 0, 0, // Skip to: 1775
-/* 1640 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 1643 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1709
-/* 1648 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1651 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1680
-/* 1656 */    MCD_OPC_CheckPredicate, 74, 14, 2, 0, // Skip to: 2187
-/* 1661 */    MCD_OPC_CheckField, 23, 9, 231, 3, 6, 2, 0, // Skip to: 2187
-/* 1669 */    MCD_OPC_CheckField, 4, 1, 0, 255, 1, 0, // Skip to: 2187
-/* 1676 */    MCD_OPC_Decode, 129, 17, 126, // Opcode: VRINTMNDh
-/* 1680 */    MCD_OPC_FilterValue, 58, 246, 1, 0, // Skip to: 2187
-/* 1685 */    MCD_OPC_CheckPredicate, 75, 241, 1, 0, // Skip to: 2187
-/* 1690 */    MCD_OPC_CheckField, 23, 9, 231, 3, 233, 1, 0, // Skip to: 2187
-/* 1698 */    MCD_OPC_CheckField, 4, 1, 0, 226, 1, 0, // Skip to: 2187
-/* 1705 */    MCD_OPC_Decode, 128, 17, 126, // Opcode: VRINTMNDf
-/* 1709 */    MCD_OPC_FilterValue, 3, 217, 1, 0, // Skip to: 2187
-/* 1714 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1717 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1746
-/* 1722 */    MCD_OPC_CheckPredicate, 74, 204, 1, 0, // Skip to: 2187
-/* 1727 */    MCD_OPC_CheckField, 23, 9, 231, 3, 196, 1, 0, // Skip to: 2187
-/* 1735 */    MCD_OPC_CheckField, 4, 1, 0, 189, 1, 0, // Skip to: 2187
-/* 1742 */    MCD_OPC_Decode, 131, 17, 127, // Opcode: VRINTMNQh
-/* 1746 */    MCD_OPC_FilterValue, 58, 180, 1, 0, // Skip to: 2187
-/* 1751 */    MCD_OPC_CheckPredicate, 75, 175, 1, 0, // Skip to: 2187
-/* 1756 */    MCD_OPC_CheckField, 23, 9, 231, 3, 167, 1, 0, // Skip to: 2187
-/* 1764 */    MCD_OPC_CheckField, 4, 1, 0, 160, 1, 0, // Skip to: 2187
-/* 1771 */    MCD_OPC_Decode, 130, 17, 127, // Opcode: VRINTMNQf
-/* 1775 */    MCD_OPC_FilterValue, 7, 135, 0, 0, // Skip to: 1915
-/* 1780 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
-/* 1783 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 1849
-/* 1788 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1791 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1820
-/* 1796 */    MCD_OPC_CheckPredicate, 74, 130, 1, 0, // Skip to: 2187
-/* 1801 */    MCD_OPC_CheckField, 23, 9, 231, 3, 122, 1, 0, // Skip to: 2187
-/* 1809 */    MCD_OPC_CheckField, 4, 1, 0, 115, 1, 0, // Skip to: 2187
-/* 1816 */    MCD_OPC_Decode, 143, 17, 126, // Opcode: VRINTPNDh
-/* 1820 */    MCD_OPC_FilterValue, 58, 106, 1, 0, // Skip to: 2187
-/* 1825 */    MCD_OPC_CheckPredicate, 75, 101, 1, 0, // Skip to: 2187
-/* 1830 */    MCD_OPC_CheckField, 23, 9, 231, 3, 93, 1, 0, // Skip to: 2187
-/* 1838 */    MCD_OPC_CheckField, 4, 1, 0, 86, 1, 0, // Skip to: 2187
-/* 1845 */    MCD_OPC_Decode, 142, 17, 126, // Opcode: VRINTPNDf
-/* 1849 */    MCD_OPC_FilterValue, 3, 77, 1, 0, // Skip to: 2187
-/* 1854 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
-/* 1857 */    MCD_OPC_FilterValue, 54, 24, 0, 0, // Skip to: 1886
-/* 1862 */    MCD_OPC_CheckPredicate, 74, 64, 1, 0, // Skip to: 2187
-/* 1867 */    MCD_OPC_CheckField, 23, 9, 231, 3, 56, 1, 0, // Skip to: 2187
-/* 1875 */    MCD_OPC_CheckField, 4, 1, 0, 49, 1, 0, // Skip to: 2187
-/* 1882 */    MCD_OPC_Decode, 145, 17, 127, // Opcode: VRINTPNQh
-/* 1886 */    MCD_OPC_FilterValue, 58, 40, 1, 0, // Skip to: 2187
-/* 1891 */    MCD_OPC_CheckPredicate, 75, 35, 1, 0, // Skip to: 2187
-/* 1896 */    MCD_OPC_CheckField, 23, 9, 231, 3, 27, 1, 0, // Skip to: 2187
-/* 1904 */    MCD_OPC_CheckField, 4, 1, 0, 20, 1, 0, // Skip to: 2187
-/* 1911 */    MCD_OPC_Decode, 144, 17, 127, // Opcode: VRINTPNQf
-/* 1915 */    MCD_OPC_FilterValue, 15, 11, 1, 0, // Skip to: 2187
-/* 1920 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
-/* 1923 */    MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 1989
-/* 1928 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1931 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 1960
-/* 1936 */    MCD_OPC_CheckPredicate, 75, 246, 0, 0, // Skip to: 2187
-/* 1941 */    MCD_OPC_CheckField, 23, 9, 230, 3, 238, 0, 0, // Skip to: 2187
-/* 1949 */    MCD_OPC_CheckField, 4, 1, 1, 231, 0, 0, // Skip to: 2187
-/* 1956 */    MCD_OPC_Decode, 158, 13, 97, // Opcode: VMAXNMNDf
-/* 1960 */    MCD_OPC_FilterValue, 1, 222, 0, 0, // Skip to: 2187
-/* 1965 */    MCD_OPC_CheckPredicate, 75, 217, 0, 0, // Skip to: 2187
-/* 1970 */    MCD_OPC_CheckField, 23, 9, 230, 3, 209, 0, 0, // Skip to: 2187
-/* 1978 */    MCD_OPC_CheckField, 4, 1, 1, 202, 0, 0, // Skip to: 2187
-/* 1985 */    MCD_OPC_Decode, 160, 13, 98, // Opcode: VMAXNMNQf
-/* 1989 */    MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 2055
-/* 1994 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 1997 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2026
-/* 2002 */    MCD_OPC_CheckPredicate, 74, 180, 0, 0, // Skip to: 2187
-/* 2007 */    MCD_OPC_CheckField, 23, 9, 230, 3, 172, 0, 0, // Skip to: 2187
-/* 2015 */    MCD_OPC_CheckField, 4, 1, 1, 165, 0, 0, // Skip to: 2187
-/* 2022 */    MCD_OPC_Decode, 159, 13, 97, // Opcode: VMAXNMNDh
-/* 2026 */    MCD_OPC_FilterValue, 1, 156, 0, 0, // Skip to: 2187
-/* 2031 */    MCD_OPC_CheckPredicate, 74, 151, 0, 0, // Skip to: 2187
-/* 2036 */    MCD_OPC_CheckField, 23, 9, 230, 3, 143, 0, 0, // Skip to: 2187
-/* 2044 */    MCD_OPC_CheckField, 4, 1, 1, 136, 0, 0, // Skip to: 2187
-/* 2051 */    MCD_OPC_Decode, 161, 13, 98, // Opcode: VMAXNMNQh
-/* 2055 */    MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 2121
-/* 2060 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2063 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2092
-/* 2068 */    MCD_OPC_CheckPredicate, 75, 114, 0, 0, // Skip to: 2187
-/* 2073 */    MCD_OPC_CheckField, 23, 9, 230, 3, 106, 0, 0, // Skip to: 2187
-/* 2081 */    MCD_OPC_CheckField, 4, 1, 1, 99, 0, 0, // Skip to: 2187
-/* 2088 */    MCD_OPC_Decode, 181, 13, 97, // Opcode: VMINNMNDf
-/* 2092 */    MCD_OPC_FilterValue, 1, 90, 0, 0, // Skip to: 2187
-/* 2097 */    MCD_OPC_CheckPredicate, 75, 85, 0, 0, // Skip to: 2187
-/* 2102 */    MCD_OPC_CheckField, 23, 9, 230, 3, 77, 0, 0, // Skip to: 2187
-/* 2110 */    MCD_OPC_CheckField, 4, 1, 1, 70, 0, 0, // Skip to: 2187
-/* 2117 */    MCD_OPC_Decode, 183, 13, 98, // Opcode: VMINNMNQf
-/* 2121 */    MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 2187
-/* 2126 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
-/* 2129 */    MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 2158
-/* 2134 */    MCD_OPC_CheckPredicate, 74, 48, 0, 0, // Skip to: 2187
-/* 2139 */    MCD_OPC_CheckField, 23, 9, 230, 3, 40, 0, 0, // Skip to: 2187
-/* 2147 */    MCD_OPC_CheckField, 4, 1, 1, 33, 0, 0, // Skip to: 2187
-/* 2154 */    MCD_OPC_Decode, 182, 13, 97, // Opcode: VMINNMNDh
-/* 2158 */    MCD_OPC_FilterValue, 1, 24, 0, 0, // Skip to: 2187
-/* 2163 */    MCD_OPC_CheckPredicate, 74, 19, 0, 0, // Skip to: 2187
-/* 2168 */    MCD_OPC_CheckField, 23, 9, 230, 3, 11, 0, 0, // Skip to: 2187
-/* 2176 */    MCD_OPC_CheckField, 4, 1, 1, 4, 0, 0, // Skip to: 2187
-/* 2183 */    MCD_OPC_Decode, 184, 13, 98, // Opcode: VMINNMNQh
-/* 2187 */    MCD_OPC_Fail,
+/* 19 */      MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 49
+/* 24 */      MCD_OPC_CheckPredicate, 98, 174, 8, 0, // Skip to: 2251
+/* 29 */      MCD_OPC_CheckField, 23, 9, 231, 3, 166, 8, 0, // Skip to: 2251
+/* 37 */      MCD_OPC_CheckField, 4, 1, 0, 159, 8, 0, // Skip to: 2251
+/* 44 */      MCD_OPC_Decode, 203, 17, 231, 1, // Opcode: VCVTANSDh
+/* 49 */      MCD_OPC_FilterValue, 59, 149, 8, 0, // Skip to: 2251
+/* 54 */      MCD_OPC_CheckPredicate, 99, 144, 8, 0, // Skip to: 2251
+/* 59 */      MCD_OPC_CheckField, 23, 9, 231, 3, 136, 8, 0, // Skip to: 2251
+/* 67 */      MCD_OPC_CheckField, 4, 1, 0, 129, 8, 0, // Skip to: 2251
+/* 74 */      MCD_OPC_Decode, 202, 17, 231, 1, // Opcode: VCVTANSDf
+/* 79 */      MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 147
+/* 84 */      MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 87 */      MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 117
+/* 92 */      MCD_OPC_CheckPredicate, 98, 106, 8, 0, // Skip to: 2251
+/* 97 */      MCD_OPC_CheckField, 23, 9, 231, 3, 98, 8, 0, // Skip to: 2251
+/* 105 */     MCD_OPC_CheckField, 4, 1, 0, 91, 8, 0, // Skip to: 2251
+/* 112 */     MCD_OPC_Decode, 205, 17, 232, 1, // Opcode: VCVTANSQh
+/* 117 */     MCD_OPC_FilterValue, 59, 81, 8, 0, // Skip to: 2251
+/* 122 */     MCD_OPC_CheckPredicate, 99, 76, 8, 0, // Skip to: 2251
+/* 127 */     MCD_OPC_CheckField, 23, 9, 231, 3, 68, 8, 0, // Skip to: 2251
+/* 135 */     MCD_OPC_CheckField, 4, 1, 0, 61, 8, 0, // Skip to: 2251
+/* 142 */     MCD_OPC_Decode, 204, 17, 232, 1, // Opcode: VCVTANSQf
+/* 147 */     MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 215
+/* 152 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 155 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 185
+/* 160 */     MCD_OPC_CheckPredicate, 98, 38, 8, 0, // Skip to: 2251
+/* 165 */     MCD_OPC_CheckField, 23, 9, 231, 3, 30, 8, 0, // Skip to: 2251
+/* 173 */     MCD_OPC_CheckField, 4, 1, 0, 23, 8, 0, // Skip to: 2251
+/* 180 */     MCD_OPC_Decode, 207, 17, 231, 1, // Opcode: VCVTANUDh
+/* 185 */     MCD_OPC_FilterValue, 59, 13, 8, 0, // Skip to: 2251
+/* 190 */     MCD_OPC_CheckPredicate, 99, 8, 8, 0, // Skip to: 2251
+/* 195 */     MCD_OPC_CheckField, 23, 9, 231, 3, 0, 8, 0, // Skip to: 2251
+/* 203 */     MCD_OPC_CheckField, 4, 1, 0, 249, 7, 0, // Skip to: 2251
+/* 210 */     MCD_OPC_Decode, 206, 17, 231, 1, // Opcode: VCVTANUDf
+/* 215 */     MCD_OPC_FilterValue, 3, 239, 7, 0, // Skip to: 2251
+/* 220 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 223 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 253
+/* 228 */     MCD_OPC_CheckPredicate, 98, 226, 7, 0, // Skip to: 2251
+/* 233 */     MCD_OPC_CheckField, 23, 9, 231, 3, 218, 7, 0, // Skip to: 2251
+/* 241 */     MCD_OPC_CheckField, 4, 1, 0, 211, 7, 0, // Skip to: 2251
+/* 248 */     MCD_OPC_Decode, 209, 17, 232, 1, // Opcode: VCVTANUQh
+/* 253 */     MCD_OPC_FilterValue, 59, 201, 7, 0, // Skip to: 2251
+/* 258 */     MCD_OPC_CheckPredicate, 99, 196, 7, 0, // Skip to: 2251
+/* 263 */     MCD_OPC_CheckField, 23, 9, 231, 3, 188, 7, 0, // Skip to: 2251
+/* 271 */     MCD_OPC_CheckField, 4, 1, 0, 181, 7, 0, // Skip to: 2251
+/* 278 */     MCD_OPC_Decode, 208, 17, 232, 1, // Opcode: VCVTANUQf
+/* 283 */     MCD_OPC_FilterValue, 1, 19, 1, 0, // Skip to: 563
+/* 288 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 291 */     MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 359
+/* 296 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 299 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 329
+/* 304 */     MCD_OPC_CheckPredicate, 98, 150, 7, 0, // Skip to: 2251
+/* 309 */     MCD_OPC_CheckField, 23, 9, 231, 3, 142, 7, 0, // Skip to: 2251
+/* 317 */     MCD_OPC_CheckField, 4, 1, 0, 135, 7, 0, // Skip to: 2251
+/* 324 */     MCD_OPC_Decode, 236, 17, 231, 1, // Opcode: VCVTNNSDh
+/* 329 */     MCD_OPC_FilterValue, 59, 125, 7, 0, // Skip to: 2251
+/* 334 */     MCD_OPC_CheckPredicate, 99, 120, 7, 0, // Skip to: 2251
+/* 339 */     MCD_OPC_CheckField, 23, 9, 231, 3, 112, 7, 0, // Skip to: 2251
+/* 347 */     MCD_OPC_CheckField, 4, 1, 0, 105, 7, 0, // Skip to: 2251
+/* 354 */     MCD_OPC_Decode, 235, 17, 231, 1, // Opcode: VCVTNNSDf
+/* 359 */     MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 427
+/* 364 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 367 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 397
+/* 372 */     MCD_OPC_CheckPredicate, 98, 82, 7, 0, // Skip to: 2251
+/* 377 */     MCD_OPC_CheckField, 23, 9, 231, 3, 74, 7, 0, // Skip to: 2251
+/* 385 */     MCD_OPC_CheckField, 4, 1, 0, 67, 7, 0, // Skip to: 2251
+/* 392 */     MCD_OPC_Decode, 238, 17, 232, 1, // Opcode: VCVTNNSQh
+/* 397 */     MCD_OPC_FilterValue, 59, 57, 7, 0, // Skip to: 2251
+/* 402 */     MCD_OPC_CheckPredicate, 99, 52, 7, 0, // Skip to: 2251
+/* 407 */     MCD_OPC_CheckField, 23, 9, 231, 3, 44, 7, 0, // Skip to: 2251
+/* 415 */     MCD_OPC_CheckField, 4, 1, 0, 37, 7, 0, // Skip to: 2251
+/* 422 */     MCD_OPC_Decode, 237, 17, 232, 1, // Opcode: VCVTNNSQf
+/* 427 */     MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 495
+/* 432 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 435 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 465
+/* 440 */     MCD_OPC_CheckPredicate, 98, 14, 7, 0, // Skip to: 2251
+/* 445 */     MCD_OPC_CheckField, 23, 9, 231, 3, 6, 7, 0, // Skip to: 2251
+/* 453 */     MCD_OPC_CheckField, 4, 1, 0, 255, 6, 0, // Skip to: 2251
+/* 460 */     MCD_OPC_Decode, 240, 17, 231, 1, // Opcode: VCVTNNUDh
+/* 465 */     MCD_OPC_FilterValue, 59, 245, 6, 0, // Skip to: 2251
+/* 470 */     MCD_OPC_CheckPredicate, 99, 240, 6, 0, // Skip to: 2251
+/* 475 */     MCD_OPC_CheckField, 23, 9, 231, 3, 232, 6, 0, // Skip to: 2251
+/* 483 */     MCD_OPC_CheckField, 4, 1, 0, 225, 6, 0, // Skip to: 2251
+/* 490 */     MCD_OPC_Decode, 239, 17, 231, 1, // Opcode: VCVTNNUDf
+/* 495 */     MCD_OPC_FilterValue, 3, 215, 6, 0, // Skip to: 2251
+/* 500 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 503 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 533
+/* 508 */     MCD_OPC_CheckPredicate, 98, 202, 6, 0, // Skip to: 2251
+/* 513 */     MCD_OPC_CheckField, 23, 9, 231, 3, 194, 6, 0, // Skip to: 2251
+/* 521 */     MCD_OPC_CheckField, 4, 1, 0, 187, 6, 0, // Skip to: 2251
+/* 528 */     MCD_OPC_Decode, 242, 17, 232, 1, // Opcode: VCVTNNUQh
+/* 533 */     MCD_OPC_FilterValue, 59, 177, 6, 0, // Skip to: 2251
+/* 538 */     MCD_OPC_CheckPredicate, 99, 172, 6, 0, // Skip to: 2251
+/* 543 */     MCD_OPC_CheckField, 23, 9, 231, 3, 164, 6, 0, // Skip to: 2251
+/* 551 */     MCD_OPC_CheckField, 4, 1, 0, 157, 6, 0, // Skip to: 2251
+/* 558 */     MCD_OPC_Decode, 241, 17, 232, 1, // Opcode: VCVTNNUQf
+/* 563 */     MCD_OPC_FilterValue, 2, 19, 1, 0, // Skip to: 843
+/* 568 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 571 */     MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 639
+/* 576 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 579 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 609
+/* 584 */     MCD_OPC_CheckPredicate, 98, 126, 6, 0, // Skip to: 2251
+/* 589 */     MCD_OPC_CheckField, 23, 9, 231, 3, 118, 6, 0, // Skip to: 2251
+/* 597 */     MCD_OPC_CheckField, 4, 1, 0, 111, 6, 0, // Skip to: 2251
+/* 604 */     MCD_OPC_Decode, 250, 17, 231, 1, // Opcode: VCVTPNSDh
+/* 609 */     MCD_OPC_FilterValue, 59, 101, 6, 0, // Skip to: 2251
+/* 614 */     MCD_OPC_CheckPredicate, 99, 96, 6, 0, // Skip to: 2251
+/* 619 */     MCD_OPC_CheckField, 23, 9, 231, 3, 88, 6, 0, // Skip to: 2251
+/* 627 */     MCD_OPC_CheckField, 4, 1, 0, 81, 6, 0, // Skip to: 2251
+/* 634 */     MCD_OPC_Decode, 249, 17, 231, 1, // Opcode: VCVTPNSDf
+/* 639 */     MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 707
+/* 644 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 647 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 677
+/* 652 */     MCD_OPC_CheckPredicate, 98, 58, 6, 0, // Skip to: 2251
+/* 657 */     MCD_OPC_CheckField, 23, 9, 231, 3, 50, 6, 0, // Skip to: 2251
+/* 665 */     MCD_OPC_CheckField, 4, 1, 0, 43, 6, 0, // Skip to: 2251
+/* 672 */     MCD_OPC_Decode, 252, 17, 232, 1, // Opcode: VCVTPNSQh
+/* 677 */     MCD_OPC_FilterValue, 59, 33, 6, 0, // Skip to: 2251
+/* 682 */     MCD_OPC_CheckPredicate, 99, 28, 6, 0, // Skip to: 2251
+/* 687 */     MCD_OPC_CheckField, 23, 9, 231, 3, 20, 6, 0, // Skip to: 2251
+/* 695 */     MCD_OPC_CheckField, 4, 1, 0, 13, 6, 0, // Skip to: 2251
+/* 702 */     MCD_OPC_Decode, 251, 17, 232, 1, // Opcode: VCVTPNSQf
+/* 707 */     MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 775
+/* 712 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 715 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 745
+/* 720 */     MCD_OPC_CheckPredicate, 98, 246, 5, 0, // Skip to: 2251
+/* 725 */     MCD_OPC_CheckField, 23, 9, 231, 3, 238, 5, 0, // Skip to: 2251
+/* 733 */     MCD_OPC_CheckField, 4, 1, 0, 231, 5, 0, // Skip to: 2251
+/* 740 */     MCD_OPC_Decode, 254, 17, 231, 1, // Opcode: VCVTPNUDh
+/* 745 */     MCD_OPC_FilterValue, 59, 221, 5, 0, // Skip to: 2251
+/* 750 */     MCD_OPC_CheckPredicate, 99, 216, 5, 0, // Skip to: 2251
+/* 755 */     MCD_OPC_CheckField, 23, 9, 231, 3, 208, 5, 0, // Skip to: 2251
+/* 763 */     MCD_OPC_CheckField, 4, 1, 0, 201, 5, 0, // Skip to: 2251
+/* 770 */     MCD_OPC_Decode, 253, 17, 231, 1, // Opcode: VCVTPNUDf
+/* 775 */     MCD_OPC_FilterValue, 3, 191, 5, 0, // Skip to: 2251
+/* 780 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 783 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 813
+/* 788 */     MCD_OPC_CheckPredicate, 98, 178, 5, 0, // Skip to: 2251
+/* 793 */     MCD_OPC_CheckField, 23, 9, 231, 3, 170, 5, 0, // Skip to: 2251
+/* 801 */     MCD_OPC_CheckField, 4, 1, 0, 163, 5, 0, // Skip to: 2251
+/* 808 */     MCD_OPC_Decode, 128, 18, 232, 1, // Opcode: VCVTPNUQh
+/* 813 */     MCD_OPC_FilterValue, 59, 153, 5, 0, // Skip to: 2251
+/* 818 */     MCD_OPC_CheckPredicate, 99, 148, 5, 0, // Skip to: 2251
+/* 823 */     MCD_OPC_CheckField, 23, 9, 231, 3, 140, 5, 0, // Skip to: 2251
+/* 831 */     MCD_OPC_CheckField, 4, 1, 0, 133, 5, 0, // Skip to: 2251
+/* 838 */     MCD_OPC_Decode, 255, 17, 232, 1, // Opcode: VCVTPNUQf
+/* 843 */     MCD_OPC_FilterValue, 3, 19, 1, 0, // Skip to: 1123
+/* 848 */     MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 851 */     MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 919
+/* 856 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 859 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 889
+/* 864 */     MCD_OPC_CheckPredicate, 98, 102, 5, 0, // Skip to: 2251
+/* 869 */     MCD_OPC_CheckField, 23, 9, 231, 3, 94, 5, 0, // Skip to: 2251
+/* 877 */     MCD_OPC_CheckField, 4, 1, 0, 87, 5, 0, // Skip to: 2251
+/* 884 */     MCD_OPC_Decode, 222, 17, 231, 1, // Opcode: VCVTMNSDh
+/* 889 */     MCD_OPC_FilterValue, 59, 77, 5, 0, // Skip to: 2251
+/* 894 */     MCD_OPC_CheckPredicate, 99, 72, 5, 0, // Skip to: 2251
+/* 899 */     MCD_OPC_CheckField, 23, 9, 231, 3, 64, 5, 0, // Skip to: 2251
+/* 907 */     MCD_OPC_CheckField, 4, 1, 0, 57, 5, 0, // Skip to: 2251
+/* 914 */     MCD_OPC_Decode, 221, 17, 231, 1, // Opcode: VCVTMNSDf
+/* 919 */     MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 987
+/* 924 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 927 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 957
+/* 932 */     MCD_OPC_CheckPredicate, 98, 34, 5, 0, // Skip to: 2251
+/* 937 */     MCD_OPC_CheckField, 23, 9, 231, 3, 26, 5, 0, // Skip to: 2251
+/* 945 */     MCD_OPC_CheckField, 4, 1, 0, 19, 5, 0, // Skip to: 2251
+/* 952 */     MCD_OPC_Decode, 224, 17, 232, 1, // Opcode: VCVTMNSQh
+/* 957 */     MCD_OPC_FilterValue, 59, 9, 5, 0, // Skip to: 2251
+/* 962 */     MCD_OPC_CheckPredicate, 99, 4, 5, 0, // Skip to: 2251
+/* 967 */     MCD_OPC_CheckField, 23, 9, 231, 3, 252, 4, 0, // Skip to: 2251
+/* 975 */     MCD_OPC_CheckField, 4, 1, 0, 245, 4, 0, // Skip to: 2251
+/* 982 */     MCD_OPC_Decode, 223, 17, 232, 1, // Opcode: VCVTMNSQf
+/* 987 */     MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 1055
+/* 992 */     MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 995 */     MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 1025
+/* 1000 */    MCD_OPC_CheckPredicate, 98, 222, 4, 0, // Skip to: 2251
+/* 1005 */    MCD_OPC_CheckField, 23, 9, 231, 3, 214, 4, 0, // Skip to: 2251
+/* 1013 */    MCD_OPC_CheckField, 4, 1, 0, 207, 4, 0, // Skip to: 2251
+/* 1020 */    MCD_OPC_Decode, 226, 17, 231, 1, // Opcode: VCVTMNUDh
+/* 1025 */    MCD_OPC_FilterValue, 59, 197, 4, 0, // Skip to: 2251
+/* 1030 */    MCD_OPC_CheckPredicate, 99, 192, 4, 0, // Skip to: 2251
+/* 1035 */    MCD_OPC_CheckField, 23, 9, 231, 3, 184, 4, 0, // Skip to: 2251
+/* 1043 */    MCD_OPC_CheckField, 4, 1, 0, 177, 4, 0, // Skip to: 2251
+/* 1050 */    MCD_OPC_Decode, 225, 17, 231, 1, // Opcode: VCVTMNUDf
+/* 1055 */    MCD_OPC_FilterValue, 3, 167, 4, 0, // Skip to: 2251
+/* 1060 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1063 */    MCD_OPC_FilterValue, 55, 25, 0, 0, // Skip to: 1093
+/* 1068 */    MCD_OPC_CheckPredicate, 98, 154, 4, 0, // Skip to: 2251
+/* 1073 */    MCD_OPC_CheckField, 23, 9, 231, 3, 146, 4, 0, // Skip to: 2251
+/* 1081 */    MCD_OPC_CheckField, 4, 1, 0, 139, 4, 0, // Skip to: 2251
+/* 1088 */    MCD_OPC_Decode, 228, 17, 232, 1, // Opcode: VCVTMNUQh
+/* 1093 */    MCD_OPC_FilterValue, 59, 129, 4, 0, // Skip to: 2251
+/* 1098 */    MCD_OPC_CheckPredicate, 99, 124, 4, 0, // Skip to: 2251
+/* 1103 */    MCD_OPC_CheckField, 23, 9, 231, 3, 116, 4, 0, // Skip to: 2251
+/* 1111 */    MCD_OPC_CheckField, 4, 1, 0, 109, 4, 0, // Skip to: 2251
+/* 1118 */    MCD_OPC_Decode, 227, 17, 232, 1, // Opcode: VCVTMNUQf
+/* 1123 */    MCD_OPC_FilterValue, 4, 19, 1, 0, // Skip to: 1403
+/* 1128 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1131 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1199
+/* 1136 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1139 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1169
+/* 1144 */    MCD_OPC_CheckPredicate, 98, 78, 4, 0, // Skip to: 2251
+/* 1149 */    MCD_OPC_CheckField, 23, 9, 231, 3, 70, 4, 0, // Skip to: 2251
+/* 1157 */    MCD_OPC_CheckField, 4, 1, 0, 63, 4, 0, // Skip to: 2251
+/* 1164 */    MCD_OPC_Decode, 246, 25, 231, 1, // Opcode: VRINTNNDh
+/* 1169 */    MCD_OPC_FilterValue, 58, 53, 4, 0, // Skip to: 2251
+/* 1174 */    MCD_OPC_CheckPredicate, 99, 48, 4, 0, // Skip to: 2251
+/* 1179 */    MCD_OPC_CheckField, 23, 9, 231, 3, 40, 4, 0, // Skip to: 2251
+/* 1187 */    MCD_OPC_CheckField, 4, 1, 0, 33, 4, 0, // Skip to: 2251
+/* 1194 */    MCD_OPC_Decode, 245, 25, 231, 1, // Opcode: VRINTNNDf
+/* 1199 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 1267
+/* 1204 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1207 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1237
+/* 1212 */    MCD_OPC_CheckPredicate, 98, 10, 4, 0, // Skip to: 2251
+/* 1217 */    MCD_OPC_CheckField, 23, 9, 231, 3, 2, 4, 0, // Skip to: 2251
+/* 1225 */    MCD_OPC_CheckField, 4, 1, 0, 251, 3, 0, // Skip to: 2251
+/* 1232 */    MCD_OPC_Decode, 248, 25, 232, 1, // Opcode: VRINTNNQh
+/* 1237 */    MCD_OPC_FilterValue, 58, 241, 3, 0, // Skip to: 2251
+/* 1242 */    MCD_OPC_CheckPredicate, 99, 236, 3, 0, // Skip to: 2251
+/* 1247 */    MCD_OPC_CheckField, 23, 9, 231, 3, 228, 3, 0, // Skip to: 2251
+/* 1255 */    MCD_OPC_CheckField, 4, 1, 0, 221, 3, 0, // Skip to: 2251
+/* 1262 */    MCD_OPC_Decode, 247, 25, 232, 1, // Opcode: VRINTNNQf
+/* 1267 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 1335
+/* 1272 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1275 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1305
+/* 1280 */    MCD_OPC_CheckPredicate, 98, 198, 3, 0, // Skip to: 2251
+/* 1285 */    MCD_OPC_CheckField, 23, 9, 231, 3, 190, 3, 0, // Skip to: 2251
+/* 1293 */    MCD_OPC_CheckField, 4, 1, 0, 183, 3, 0, // Skip to: 2251
+/* 1300 */    MCD_OPC_Decode, 135, 26, 231, 1, // Opcode: VRINTXNDh
+/* 1305 */    MCD_OPC_FilterValue, 58, 173, 3, 0, // Skip to: 2251
+/* 1310 */    MCD_OPC_CheckPredicate, 99, 168, 3, 0, // Skip to: 2251
+/* 1315 */    MCD_OPC_CheckField, 23, 9, 231, 3, 160, 3, 0, // Skip to: 2251
+/* 1323 */    MCD_OPC_CheckField, 4, 1, 0, 153, 3, 0, // Skip to: 2251
+/* 1330 */    MCD_OPC_Decode, 134, 26, 231, 1, // Opcode: VRINTXNDf
+/* 1335 */    MCD_OPC_FilterValue, 3, 143, 3, 0, // Skip to: 2251
+/* 1340 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1343 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1373
+/* 1348 */    MCD_OPC_CheckPredicate, 98, 130, 3, 0, // Skip to: 2251
+/* 1353 */    MCD_OPC_CheckField, 23, 9, 231, 3, 122, 3, 0, // Skip to: 2251
+/* 1361 */    MCD_OPC_CheckField, 4, 1, 0, 115, 3, 0, // Skip to: 2251
+/* 1368 */    MCD_OPC_Decode, 137, 26, 232, 1, // Opcode: VRINTXNQh
+/* 1373 */    MCD_OPC_FilterValue, 58, 105, 3, 0, // Skip to: 2251
+/* 1378 */    MCD_OPC_CheckPredicate, 99, 100, 3, 0, // Skip to: 2251
+/* 1383 */    MCD_OPC_CheckField, 23, 9, 231, 3, 92, 3, 0, // Skip to: 2251
+/* 1391 */    MCD_OPC_CheckField, 4, 1, 0, 85, 3, 0, // Skip to: 2251
+/* 1398 */    MCD_OPC_Decode, 136, 26, 232, 1, // Opcode: VRINTXNQf
+/* 1403 */    MCD_OPC_FilterValue, 5, 19, 1, 0, // Skip to: 1683
+/* 1408 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1411 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 1479
+/* 1416 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1419 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1449
+/* 1424 */    MCD_OPC_CheckPredicate, 98, 54, 3, 0, // Skip to: 2251
+/* 1429 */    MCD_OPC_CheckField, 23, 9, 231, 3, 46, 3, 0, // Skip to: 2251
+/* 1437 */    MCD_OPC_CheckField, 4, 1, 0, 39, 3, 0, // Skip to: 2251
+/* 1444 */    MCD_OPC_Decode, 232, 25, 231, 1, // Opcode: VRINTANDh
+/* 1449 */    MCD_OPC_FilterValue, 58, 29, 3, 0, // Skip to: 2251
+/* 1454 */    MCD_OPC_CheckPredicate, 99, 24, 3, 0, // Skip to: 2251
+/* 1459 */    MCD_OPC_CheckField, 23, 9, 231, 3, 16, 3, 0, // Skip to: 2251
+/* 1467 */    MCD_OPC_CheckField, 4, 1, 0, 9, 3, 0, // Skip to: 2251
+/* 1474 */    MCD_OPC_Decode, 231, 25, 231, 1, // Opcode: VRINTANDf
+/* 1479 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 1547
+/* 1484 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1487 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1517
+/* 1492 */    MCD_OPC_CheckPredicate, 98, 242, 2, 0, // Skip to: 2251
+/* 1497 */    MCD_OPC_CheckField, 23, 9, 231, 3, 234, 2, 0, // Skip to: 2251
+/* 1505 */    MCD_OPC_CheckField, 4, 1, 0, 227, 2, 0, // Skip to: 2251
+/* 1512 */    MCD_OPC_Decode, 234, 25, 232, 1, // Opcode: VRINTANQh
+/* 1517 */    MCD_OPC_FilterValue, 58, 217, 2, 0, // Skip to: 2251
+/* 1522 */    MCD_OPC_CheckPredicate, 99, 212, 2, 0, // Skip to: 2251
+/* 1527 */    MCD_OPC_CheckField, 23, 9, 231, 3, 204, 2, 0, // Skip to: 2251
+/* 1535 */    MCD_OPC_CheckField, 4, 1, 0, 197, 2, 0, // Skip to: 2251
+/* 1542 */    MCD_OPC_Decode, 233, 25, 232, 1, // Opcode: VRINTANQf
+/* 1547 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 1615
+/* 1552 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1555 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1585
+/* 1560 */    MCD_OPC_CheckPredicate, 98, 174, 2, 0, // Skip to: 2251
+/* 1565 */    MCD_OPC_CheckField, 23, 9, 231, 3, 166, 2, 0, // Skip to: 2251
+/* 1573 */    MCD_OPC_CheckField, 4, 1, 0, 159, 2, 0, // Skip to: 2251
+/* 1580 */    MCD_OPC_Decode, 142, 26, 231, 1, // Opcode: VRINTZNDh
+/* 1585 */    MCD_OPC_FilterValue, 58, 149, 2, 0, // Skip to: 2251
+/* 1590 */    MCD_OPC_CheckPredicate, 99, 144, 2, 0, // Skip to: 2251
+/* 1595 */    MCD_OPC_CheckField, 23, 9, 231, 3, 136, 2, 0, // Skip to: 2251
+/* 1603 */    MCD_OPC_CheckField, 4, 1, 0, 129, 2, 0, // Skip to: 2251
+/* 1610 */    MCD_OPC_Decode, 141, 26, 231, 1, // Opcode: VRINTZNDf
+/* 1615 */    MCD_OPC_FilterValue, 3, 119, 2, 0, // Skip to: 2251
+/* 1620 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1623 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1653
+/* 1628 */    MCD_OPC_CheckPredicate, 98, 106, 2, 0, // Skip to: 2251
+/* 1633 */    MCD_OPC_CheckField, 23, 9, 231, 3, 98, 2, 0, // Skip to: 2251
+/* 1641 */    MCD_OPC_CheckField, 4, 1, 0, 91, 2, 0, // Skip to: 2251
+/* 1648 */    MCD_OPC_Decode, 144, 26, 232, 1, // Opcode: VRINTZNQh
+/* 1653 */    MCD_OPC_FilterValue, 58, 81, 2, 0, // Skip to: 2251
+/* 1658 */    MCD_OPC_CheckPredicate, 99, 76, 2, 0, // Skip to: 2251
+/* 1663 */    MCD_OPC_CheckField, 23, 9, 231, 3, 68, 2, 0, // Skip to: 2251
+/* 1671 */    MCD_OPC_CheckField, 4, 1, 0, 61, 2, 0, // Skip to: 2251
+/* 1678 */    MCD_OPC_Decode, 143, 26, 232, 1, // Opcode: VRINTZNQf
+/* 1683 */    MCD_OPC_FilterValue, 6, 139, 0, 0, // Skip to: 1827
+/* 1688 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1691 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 1759
+/* 1696 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1699 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1729
+/* 1704 */    MCD_OPC_CheckPredicate, 98, 30, 2, 0, // Skip to: 2251
+/* 1709 */    MCD_OPC_CheckField, 23, 9, 231, 3, 22, 2, 0, // Skip to: 2251
+/* 1717 */    MCD_OPC_CheckField, 4, 1, 0, 15, 2, 0, // Skip to: 2251
+/* 1724 */    MCD_OPC_Decode, 239, 25, 231, 1, // Opcode: VRINTMNDh
+/* 1729 */    MCD_OPC_FilterValue, 58, 5, 2, 0, // Skip to: 2251
+/* 1734 */    MCD_OPC_CheckPredicate, 99, 0, 2, 0, // Skip to: 2251
+/* 1739 */    MCD_OPC_CheckField, 23, 9, 231, 3, 248, 1, 0, // Skip to: 2251
+/* 1747 */    MCD_OPC_CheckField, 4, 1, 0, 241, 1, 0, // Skip to: 2251
+/* 1754 */    MCD_OPC_Decode, 238, 25, 231, 1, // Opcode: VRINTMNDf
+/* 1759 */    MCD_OPC_FilterValue, 3, 231, 1, 0, // Skip to: 2251
+/* 1764 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1767 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1797
+/* 1772 */    MCD_OPC_CheckPredicate, 98, 218, 1, 0, // Skip to: 2251
+/* 1777 */    MCD_OPC_CheckField, 23, 9, 231, 3, 210, 1, 0, // Skip to: 2251
+/* 1785 */    MCD_OPC_CheckField, 4, 1, 0, 203, 1, 0, // Skip to: 2251
+/* 1792 */    MCD_OPC_Decode, 241, 25, 232, 1, // Opcode: VRINTMNQh
+/* 1797 */    MCD_OPC_FilterValue, 58, 193, 1, 0, // Skip to: 2251
+/* 1802 */    MCD_OPC_CheckPredicate, 99, 188, 1, 0, // Skip to: 2251
+/* 1807 */    MCD_OPC_CheckField, 23, 9, 231, 3, 180, 1, 0, // Skip to: 2251
+/* 1815 */    MCD_OPC_CheckField, 4, 1, 0, 173, 1, 0, // Skip to: 2251
+/* 1822 */    MCD_OPC_Decode, 240, 25, 232, 1, // Opcode: VRINTMNQf
+/* 1827 */    MCD_OPC_FilterValue, 7, 139, 0, 0, // Skip to: 1971
+/* 1832 */    MCD_OPC_ExtractField, 6, 2,  // Inst{7-6} ...
+/* 1835 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 1903
+/* 1840 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1843 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1873
+/* 1848 */    MCD_OPC_CheckPredicate, 98, 142, 1, 0, // Skip to: 2251
+/* 1853 */    MCD_OPC_CheckField, 23, 9, 231, 3, 134, 1, 0, // Skip to: 2251
+/* 1861 */    MCD_OPC_CheckField, 4, 1, 0, 127, 1, 0, // Skip to: 2251
+/* 1868 */    MCD_OPC_Decode, 253, 25, 231, 1, // Opcode: VRINTPNDh
+/* 1873 */    MCD_OPC_FilterValue, 58, 117, 1, 0, // Skip to: 2251
+/* 1878 */    MCD_OPC_CheckPredicate, 99, 112, 1, 0, // Skip to: 2251
+/* 1883 */    MCD_OPC_CheckField, 23, 9, 231, 3, 104, 1, 0, // Skip to: 2251
+/* 1891 */    MCD_OPC_CheckField, 4, 1, 0, 97, 1, 0, // Skip to: 2251
+/* 1898 */    MCD_OPC_Decode, 252, 25, 231, 1, // Opcode: VRINTPNDf
+/* 1903 */    MCD_OPC_FilterValue, 3, 87, 1, 0, // Skip to: 2251
+/* 1908 */    MCD_OPC_ExtractField, 16, 6,  // Inst{21-16} ...
+/* 1911 */    MCD_OPC_FilterValue, 54, 25, 0, 0, // Skip to: 1941
+/* 1916 */    MCD_OPC_CheckPredicate, 98, 74, 1, 0, // Skip to: 2251
+/* 1921 */    MCD_OPC_CheckField, 23, 9, 231, 3, 66, 1, 0, // Skip to: 2251
+/* 1929 */    MCD_OPC_CheckField, 4, 1, 0, 59, 1, 0, // Skip to: 2251
+/* 1936 */    MCD_OPC_Decode, 255, 25, 232, 1, // Opcode: VRINTPNQh
+/* 1941 */    MCD_OPC_FilterValue, 58, 49, 1, 0, // Skip to: 2251
+/* 1946 */    MCD_OPC_CheckPredicate, 99, 44, 1, 0, // Skip to: 2251
+/* 1951 */    MCD_OPC_CheckField, 23, 9, 231, 3, 36, 1, 0, // Skip to: 2251
+/* 1959 */    MCD_OPC_CheckField, 4, 1, 0, 29, 1, 0, // Skip to: 2251
+/* 1966 */    MCD_OPC_Decode, 254, 25, 232, 1, // Opcode: VRINTPNQf
+/* 1971 */    MCD_OPC_FilterValue, 15, 19, 1, 0, // Skip to: 2251
+/* 1976 */    MCD_OPC_ExtractField, 20, 2,  // Inst{21-20} ...
+/* 1979 */    MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 2047
+/* 1984 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 1987 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2017
+/* 1992 */    MCD_OPC_CheckPredicate, 99, 254, 0, 0, // Skip to: 2251
+/* 1997 */    MCD_OPC_CheckField, 23, 9, 230, 3, 246, 0, 0, // Skip to: 2251
+/* 2005 */    MCD_OPC_CheckField, 4, 1, 1, 239, 0, 0, // Skip to: 2251
+/* 2012 */    MCD_OPC_Decode, 227, 13, 202, 1, // Opcode: NEON_VMAXNMNDf
+/* 2017 */    MCD_OPC_FilterValue, 1, 229, 0, 0, // Skip to: 2251
+/* 2022 */    MCD_OPC_CheckPredicate, 99, 224, 0, 0, // Skip to: 2251
+/* 2027 */    MCD_OPC_CheckField, 23, 9, 230, 3, 216, 0, 0, // Skip to: 2251
+/* 2035 */    MCD_OPC_CheckField, 4, 1, 1, 209, 0, 0, // Skip to: 2251
+/* 2042 */    MCD_OPC_Decode, 229, 13, 203, 1, // Opcode: NEON_VMAXNMNQf
+/* 2047 */    MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 2115
+/* 2052 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2055 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2085
+/* 2060 */    MCD_OPC_CheckPredicate, 98, 186, 0, 0, // Skip to: 2251
+/* 2065 */    MCD_OPC_CheckField, 23, 9, 230, 3, 178, 0, 0, // Skip to: 2251
+/* 2073 */    MCD_OPC_CheckField, 4, 1, 1, 171, 0, 0, // Skip to: 2251
+/* 2080 */    MCD_OPC_Decode, 228, 13, 202, 1, // Opcode: NEON_VMAXNMNDh
+/* 2085 */    MCD_OPC_FilterValue, 1, 161, 0, 0, // Skip to: 2251
+/* 2090 */    MCD_OPC_CheckPredicate, 98, 156, 0, 0, // Skip to: 2251
+/* 2095 */    MCD_OPC_CheckField, 23, 9, 230, 3, 148, 0, 0, // Skip to: 2251
+/* 2103 */    MCD_OPC_CheckField, 4, 1, 1, 141, 0, 0, // Skip to: 2251
+/* 2110 */    MCD_OPC_Decode, 230, 13, 203, 1, // Opcode: NEON_VMAXNMNQh
+/* 2115 */    MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 2183
+/* 2120 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2123 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2153
+/* 2128 */    MCD_OPC_CheckPredicate, 99, 118, 0, 0, // Skip to: 2251
+/* 2133 */    MCD_OPC_CheckField, 23, 9, 230, 3, 110, 0, 0, // Skip to: 2251
+/* 2141 */    MCD_OPC_CheckField, 4, 1, 1, 103, 0, 0, // Skip to: 2251
+/* 2148 */    MCD_OPC_Decode, 231, 13, 202, 1, // Opcode: NEON_VMINNMNDf
+/* 2153 */    MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 2251
+/* 2158 */    MCD_OPC_CheckPredicate, 99, 88, 0, 0, // Skip to: 2251
+/* 2163 */    MCD_OPC_CheckField, 23, 9, 230, 3, 80, 0, 0, // Skip to: 2251
+/* 2171 */    MCD_OPC_CheckField, 4, 1, 1, 73, 0, 0, // Skip to: 2251
+/* 2178 */    MCD_OPC_Decode, 233, 13, 203, 1, // Opcode: NEON_VMINNMNQf
+/* 2183 */    MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 2251
+/* 2188 */    MCD_OPC_ExtractField, 6, 1,  // Inst{6} ...
+/* 2191 */    MCD_OPC_FilterValue, 0, 25, 0, 0, // Skip to: 2221
+/* 2196 */    MCD_OPC_CheckPredicate, 98, 50, 0, 0, // Skip to: 2251
+/* 2201 */    MCD_OPC_CheckField, 23, 9, 230, 3, 42, 0, 0, // Skip to: 2251
+/* 2209 */    MCD_OPC_CheckField, 4, 1, 1, 35, 0, 0, // Skip to: 2251
+/* 2216 */    MCD_OPC_Decode, 232, 13, 202, 1, // Opcode: NEON_VMINNMNDh
+/* 2221 */    MCD_OPC_FilterValue, 1, 25, 0, 0, // Skip to: 2251
+/* 2226 */    MCD_OPC_CheckPredicate, 98, 20, 0, 0, // Skip to: 2251
+/* 2231 */    MCD_OPC_CheckField, 23, 9, 230, 3, 12, 0, 0, // Skip to: 2251
+/* 2239 */    MCD_OPC_CheckField, 4, 1, 1, 5, 0, 0, // Skip to: 2251
+/* 2246 */    MCD_OPC_Decode, 234, 13, 203, 1, // Opcode: NEON_VMINNMNQh
+/* 2251 */    MCD_OPC_Fail,
   0
 };
 
-static bool checkDecoderPredicate(unsigned Idx, MCInst *MI)
-{
+static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) {
   switch (Idx) {
-  default: /* llvm_unreachable("Invalid index!");*/ 
+  default: /* llvm_unreachable("Invalid index!"); */
   case 0:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb));
   case 1:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6Ops));
   case 2:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureCRC));
   case 3:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TEOps));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TEOps));
   case 4:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops));
   case 5:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops));
   case 6:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps));
   case 7:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVirtualization));
   case 8:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAcquireRelease));
   case 9:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureV7Clrex));
   case 10:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV4TOps));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV4TOps));
   case 11:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TOps));
   case 12:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureTrustZone));
   case 13:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6T2Ops));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6T2Ops));
   case 14:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_4aOps));
   case 15:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops));
   case 16:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP));
   case 17:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6KOps));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6KOps));
   case 18:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDB));
   case 19:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivARM));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureSB));
   case 20:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNaClTrap));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureHWDivARM));
   case 21:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNaClTrap));
   case 22:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasMVEIntegerOps));
   case 23:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasMVEIntegerOps));
   case 24:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCrypto));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasMVEFloatOps));
   case 25:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps));
   case 26:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON));
   case 27:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16));
   case 28:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps));
   case 29:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAES));
   case 30:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP16));
   case 31:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6Ops));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureBF16) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON));
   case 32:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP4_D16_SP));
   case 33:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_1aOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP2_SP));
   case 34:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs));
   case 35:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb));
   case 36:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV6MOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt));
   case 37:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV5TOps) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TOps));
   case 38:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6Ops));
   case 39:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MBaselineOps));
   case 40:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1aOps));
   case 41:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && !ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass));
   case 42:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops));
   case 43:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV6MOps));
   case 44:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV5TOps) && !ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass));
   case 45:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2));
   case 46:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && !ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass));
   case 47:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_4aOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps));
   case 48:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureV7Clrex));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAcquireRelease));
   case 49:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDB));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureV7Clrex));
   case 50:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureAcquireRelease) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureV7Clrex) && !ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass));
   case 51:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVirtualization));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP) && (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)));
   case 52:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureTrustZone));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt));
   case 53:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDSP));
   case 54:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops));
   case 55:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureHWDivThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MBaselineOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_4aOps));
   case 56:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMP));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureV7Clrex));
   case 57:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCRC));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDB));
   case 58:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2) && !ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass));
   case 59:
-    return (!ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureThumb2));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureSB));
   case 60:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVirtualization));
   case 61:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP2) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureTrustZone));
   case 62:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVirtualization));
   case 63:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP4) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMClass));
   case 64:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8MMainlineOps) && ARM_getFeatureBits(MI->csh->mode, ARM_Feature8MSecExt));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureLOB));
   case 65:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops));
   case 66:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)));
   case 67:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFP16));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureHWDivThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MBaselineOps));
   case 68:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFP3) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV7Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMP));
   case 69:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && !ARM_getFeatureBits(MI->csh->mode, ARM_FeatureVFPOnlySP));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureCRC));
   case 70:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFPARMv8) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeaturePACBTI));
   case 71:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasCDEOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs));
   case 72:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_HasV8_3aOps));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasCDEOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasMVEIntegerOps));
   case 73:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDotProd));
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasCDEOps));
   case 74:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureFullFP16));
+    return ((ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)) && !ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops));
   case 75:
-    return (ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureNEON));
+    return (!ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (ARM_getFeatureBits(Inst->csh->mode, ARM_ModeThumb) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureThumb2)));
+  case 76:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs16));
+  case 77:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16));
+  case 78:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt));
+  case 79:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP4_D16_SP));
+  case 80:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8MMainlineOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_Feature8MSecExt));
+  case 81:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs));
+  case 82:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP3_D16_SP));
+  case 83:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP16));
+  case 84:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPARMv8_D16_SP));
+  case 85:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP2_SP) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64));
+  case 86:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP4_D16_SP) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64));
+  case 87:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureVFP3_D16_SP) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64));
+  case 88:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPRegs64));
+  case 89:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPARMv8_D16_SP) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP64));
+  case 90:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFPARMv8_D16_SP) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_3aOps));
+  case 91:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_3aOps) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16));
+  case 92:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_3aOps));
+  case 93:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFP16FML));
+  case 94:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureBF16));
+  case 95:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureMatMulInt8));
+  case 96:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureDotProd));
+  case 97:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureSHA2));
+  case 98:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureFullFP16));
+  case 99:
+    return (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && ARM_getFeatureBits(Inst->csh->mode, ARM_FeatureNEON));
   }
 }
 
@@ -11359,9 +17050,8 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
 		uint64_t Address, bool *Decoder) \
 { \
   InsnType tmp; \
-  /* printf("Idx = %u\n", Idx); */\
   switch (Idx) { \
-  default: /* llvm_unreachable("Invalid index!");*/  \
+  default: /* llvm_unreachable("Invalid index!"); */ \
   case 0: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11379,7 +17069,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 7) << 5; \
     if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11393,7 +17083,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 2) << 5; \
     tmp |= fieldname(insn, 8, 4) << 8; \
@@ -11408,7 +17098,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 2) << 5; \
     tmp |= fieldname(insn, 8, 4) << 8; \
@@ -11494,7 +17184,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 15: \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 8, 12) << 4; \
     MCOperand_CreateImm0(MI, tmp); \
@@ -11505,7 +17195,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 17: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 7) << 5; \
     if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11515,7 +17205,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 18: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 2) << 5; \
     tmp |= fieldname(insn, 8, 4) << 8; \
@@ -11586,7 +17276,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 25: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 8, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 5; \
@@ -11595,7 +17285,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 26: \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11605,7 +17295,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 27: \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 8, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 5; \
@@ -11658,7 +17348,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 33: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 7) << 5; \
     if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11688,7 +17378,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 37: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 2) << 5; \
     tmp |= fieldname(insn, 8, 4) << 8; \
@@ -11755,7 +17445,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 23, 1) << 4; \
     if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11769,7 +17459,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 8, 4) << 4; \
     tmp |= fieldname(insn, 23, 1) << 8; \
@@ -11787,7 +17477,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 8, 4) << 4; \
     tmp |= fieldname(insn, 23, 1) << 8; \
@@ -11810,7 +17500,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 48: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 12) << 0; \
     tmp |= fieldname(insn, 22, 2) << 12; \
     MCOperand_CreateImm0(MI, tmp); \
@@ -11829,12 +17519,13 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 51: \
+    if (!Check(&S, DecodeTSBInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 52: \
     if (!Check(&S, DecodeHINTInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 53: \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11859,7 +17550,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 56: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 12) << 0; \
     tmp |= fieldname(insn, 16, 4) << 13; \
     tmp |= fieldname(insn, 23, 1) << 12; \
@@ -11868,7 +17559,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 57: \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 12) << 0; \
     tmp |= fieldname(insn, 16, 4) << 13; \
     tmp |= fieldname(insn, 23, 1) << 12; \
@@ -11883,7 +17574,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 60: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 12) << 0; \
     tmp |= fieldname(insn, 16, 4) << 13; \
     tmp |= fieldname(insn, 23, 1) << 12; \
@@ -11892,43 +17583,35 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 61: \
-    tmp = fieldname(insn, 0, 4); \
-    if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 62: \
     tmp = fieldname(insn, 0, 4); \
-    if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 63: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 7) << 5; \
-    tmp |= fieldname(insn, 16, 4) << 13; \
-    tmp |= fieldname(insn, 23, 1) << 12; \
-    if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 64: \
-    tmp = 0; \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 7) << 5; \
     tmp |= fieldname(insn, 16, 4) << 13; \
     tmp |= fieldname(insn, 23, 1) << 12; \
     if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 65: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 0, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
+  case 65: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 7) << 5; \
+    tmp |= fieldname(insn, 16, 4) << 13; \
+    tmp |= fieldname(insn, 23, 1) << 12; \
+    if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
   case 66: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -11936,18 +17619,18 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 7, 5); \
-    MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 67: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 7, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
@@ -11958,36 +17641,34 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 69: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 70: \
     tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 10, 2); \
-    MCOperand_CreateImm0(MI, tmp); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 71: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 10, 2); \
@@ -11996,26 +17677,38 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 72: \
-    if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 10, 2); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 73: \
-    if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 74: \
+    if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 75: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 1) << 5; \
     tmp |= fieldname(insn, 7, 5) << 0; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 75: \
+  case 76: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -12025,7 +17718,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 76: \
+  case 77: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
@@ -12037,10 +17730,10 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 77: \
+  case 78: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 7) << 5; \
     tmp |= fieldname(insn, 16, 4) << 13; \
@@ -12049,26 +17742,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 78: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 5) << 0; \
-    tmp |= fieldname(insn, 16, 5) << 5; \
-    if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
   case 79: \
     tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 5) << 0; \
     tmp |= fieldname(insn, 16, 5) << 5; \
     if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12076,6 +17755,20 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 80: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 5) << 0; \
+    tmp |= fieldname(insn, 16, 5) << 5; \
+    if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 81: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
@@ -12083,103 +17776,79 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 16); \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 81: \
+  case 82: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 82: \
+  case 83: \
     if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 83: \
+  case 84: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 85: \
     tmp = fieldname(insn, 0, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 84: \
+  case 86: \
     if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 85: \
-    tmp = 0; \
+  case 87: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 24) << 1; \
     tmp |= fieldname(insn, 24, 1) << 0; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 86: \
+  case 88: \
     if (!Check(&S, DecoderForMRRC2AndMCRR2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 87: \
-    tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 4, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 0, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 88: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 4, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 0, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
   case 89: \
-    tmp = fieldname(insn, 0, 24); \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 4, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 90: \
-    if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 91: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 20, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 12, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 16, 4); \
+    tmp = fieldname(insn, 4, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 4); \
     MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 5, 3); \
-    MCOperand_CreateImm0(MI, tmp); \
-    return S; \
-  case 92: \
-    tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 20, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 12, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 16, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 0, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 5, 3); \
-    MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
+  case 91: \
+    tmp = fieldname(insn, 0, 24); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 92: \
+    if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
   case 93: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 21, 3); \
+    tmp = fieldname(insn, 20, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 4); \
@@ -12190,10 +17859,10 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
   case 94: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 21, 3); \
+    tmp = fieldname(insn, 20, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 4); \
@@ -12204,12 +17873,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 95: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 21, 3); \
     MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 4); \
@@ -12218,12 +17887,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
   case 96: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 21, 3); \
     MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 4); \
@@ -12234,275 +17903,1419 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 97: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 21, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 16, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 0, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 5, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
     return S; \
   case 98: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 21, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 16, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 0, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 5, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 99: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodeMveVCTP(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 100: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodeMVEOverlappingLongShift(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 101: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 102: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 6, 2) << 0; \
+    tmp |= fieldname(insn, 12, 3) << 2; \
+    if (!Check(&S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 103: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 9, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 9, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 6, 2) << 0; \
+    tmp |= fieldname(insn, 12, 3) << 2; \
+    if (!Check(&S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 104: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 24, 1); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
   case 105: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 23, 2); \
+    MCOperand_CreateImm0(MI, tmp); \
     return S; \
   case 106: \
-    tmp = 0; \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 3; \
+    if (!Check(&S, DecodeMveAddrModeRQ(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 107: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 16, 3) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeTAddrModeImm7_0(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 108: \
+    tmp = fieldname(insn, 16, 3); \
+    if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 3); \
+    if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2Imm7_0(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 109: \
+    if (!Check(&S, DecodeMVE_MEM_1_pre_0(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 110: \
+    if (!Check(&S, DecodeMVEVMOVQtoDReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 111: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 16, 3) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeTAddrModeImm7_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 112: \
+    if (!Check(&S, DecodeMVEVMOVDRegtoQ(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 113: \
+    tmp = fieldname(insn, 16, 3); \
+    if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 3); \
+    if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2Imm7_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 114: \
+    if (!Check(&S, DecodeMVE_MEM_1_pre_1(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 115: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 116: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 117: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2AddrModeImm7_0_0(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 118: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 17, 3) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeMveAddrModeQ_2(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 119: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2AddrModeImm7_1_0(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 120: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 121: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 122: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2Imm7_0(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 123: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 124: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 125: \
+    if (!Check(&S, DecodeMVE_MEM_2_pre_0(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 126: \
+    if (!Check(&S, DecodeMVE_MEM_3_pre_2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 127: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2Imm7_1(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 128: \
+    if (!Check(&S, DecodeMVE_MEM_2_pre_1(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 129: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 130: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQQQQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 131: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2AddrModeImm7_2_0(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 132: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 17, 3) << 8; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeMveAddrModeQ_3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 133: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 7) << 0; \
+    tmp |= fieldname(insn, 23, 1) << 7; \
+    if (!Check(&S, DecodeT2Imm7_2(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 134: \
+    if (!Check(&S, DecodeMVE_MEM_2_pre_2(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 135: \
+    if (!Check(&S, DecodeMVE_MEM_3_pre_3(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 136: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 16, 1) << 1; \
+    tmp |= fieldname(insn, 21, 1) << 0; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 137: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 6, 1) << 0; \
+    tmp |= fieldname(insn, 16, 1) << 2; \
+    tmp |= fieldname(insn, 21, 1) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 138: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 5, 2) << 0; \
+    tmp |= fieldname(insn, 16, 1) << 3; \
+    tmp |= fieldname(insn, 21, 1) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 139: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 16, 1) << 1; \
+    tmp |= fieldname(insn, 21, 1) << 0; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 140: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 6, 1) << 0; \
+    tmp |= fieldname(insn, 16, 1) << 2; \
+    tmp |= fieldname(insn, 21, 1) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 141: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 5, 2) << 0; \
+    tmp |= fieldname(insn, 16, 1) << 3; \
+    tmp |= fieldname(insn, 21, 1) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 142: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 143: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 144: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 145: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 146: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 1) << 0; \
+    tmp |= fieldname(insn, 12, 1) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 147: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 148: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 149: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 150: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 1); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 151: \
+    if (!Check(&S, DecodeMVEVCMP_0_DecodeRestrictedIPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 152: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 7, 1); \
+    if (!Check(&S, DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 153: \
+    if (!Check(&S, DecodeMVEVCMP_0_DecodeRestrictedUPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 154: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 7, 1); \
+    if (!Check(&S, DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 155: \
+    if (!Check(&S, DecodeMVEVCMP_0_DecodeRestrictedSPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 156: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 1) << 1; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    if (!Check(&S, DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 157: \
+    if (!Check(&S, DecodeMVEVCMP_1_DecodeRestrictedIPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 158: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 7, 1); \
+    if (!Check(&S, DecodeRestrictedIPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 159: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    if (!Check(&S, DecodePowerTwoOperand_0_3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 160: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    if (!Check(&S, DecodePowerTwoOperand_0_3(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 161: \
+    if (!Check(&S, DecodeMVEVCMP_1_DecodeRestrictedUPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 162: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 7, 1); \
+    if (!Check(&S, DecodeRestrictedUPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 163: \
+    if (!Check(&S, DecodeMVEVCMP_1_DecodeRestrictedSPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 164: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 5, 1) << 1; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    if (!Check(&S, DecodeRestrictedSPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 165: \
+    if (!Check(&S, DecodeMVEVADCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 166: \
+    if (!Check(&S, DecodeMVEVCMP_0_DecodeRestrictedFPPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 167: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 1) << 1; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 12, 1) << 2; \
+    if (!Check(&S, DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 168: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 169: \
+    if (!Check(&S, DecodeMVEVCMP_1_DecodeRestrictedFPPredicateOperand(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 170: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithZRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 5, 1) << 1; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 12, 1) << 2; \
+    if (!Check(&S, DecodeRestrictedFPPredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 171: \
+    if (!Check(&S, DecodeMVEVPNOT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 172: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVPTMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 173: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 174: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 175: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 20, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 176: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 177: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 20, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 20, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 178: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 179: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 180: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 20, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 181: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 182: \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 20, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3) << 1; \
+    if (!Check(&S, DecodetGPREvenRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 20, 3) << 1; \
+    if (!Check(&S, DecodetGPROddRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 183: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 184: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 3); \
+    if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 185: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 186: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 187: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 188: \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 5); \
+    if (!Check(&S, DecodeLongShiftOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 189: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 3; \
+    tmp |= fieldname(insn, 17, 3) << 0; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 190: \
+    if (!Check(&S, DecodeMVEModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 191: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 9, 2) << 9; \
+    tmp |= fieldname(insn, 16, 3) << 4; \
+    tmp |= fieldname(insn, 28, 1) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 192: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 9, 1) << 9; \
+    tmp |= fieldname(insn, 16, 3) << 4; \
+    tmp |= fieldname(insn, 28, 1) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 193: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 3); \
+    if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 194: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 3); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 195: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 196: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 197: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 5); \
+    if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 198: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 5); \
+    if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 199: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 200: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 13, 3) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 3) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 3; \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 5); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 201: \
+    if (!Check(&S, DecodeMVEVCVTt1fp(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 202: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 203: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 107: \
-    tmp = 0; \
+  case 204: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 205: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 206: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 207: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 208: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 209: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 210: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 211: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 212: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 1) << 0; \
     tmp |= fieldname(insn, 5, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 108: \
-    tmp = 0; \
+  case 213: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 1) << 0; \
     tmp |= fieldname(insn, 5, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 109: \
-    tmp = 0; \
+  case 214: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 1) << 0; \
     tmp |= fieldname(insn, 5, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 110: \
-    tmp = 0; \
+  case 215: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 1) << 0; \
     tmp |= fieldname(insn, 5, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 111: \
-    tmp = 0; \
+  case 216: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 1) << 0; \
     tmp |= fieldname(insn, 5, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 112: \
-    tmp = 0; \
+  case 217: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 1) << 0; \
     tmp |= fieldname(insn, 5, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 113: \
-    tmp = 0; \
+  case 218: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12511,16 +19324,16 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 5, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 114: \
-    tmp = 0; \
+  case 219: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12529,16 +19342,16 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 5, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 115: \
-    tmp = 0; \
+  case 220: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12547,12 +19360,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 5, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 116: \
-    tmp = 0; \
+  case 221: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12561,12 +19374,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 5, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 117: \
-    tmp = 0; \
+  case 222: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12575,12 +19388,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 5, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 118: \
-    tmp = 0; \
+  case 223: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -12589,835 +19402,835 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 5, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 119: \
-    tmp = 0; \
+  case 224: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 10, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 120: \
-    tmp = 0; \
+  case 225: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 9, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 121: \
-    tmp = 0; \
+  case 226: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 122: \
-    tmp = 0; \
+  case 227: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 11, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 123: \
-    tmp = 0; \
+  case 228: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 10, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 124: \
-    tmp = 0; \
+  case 229: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 9, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 125: \
-    tmp = 0; \
+  case 230: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 126: \
-    tmp = 0; \
+  case 231: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 127: \
-    tmp = 0; \
+  case 232: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 128: \
-    tmp = 0; \
+  case 233: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 129: \
-    tmp = 0; \
+  case 234: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 130: \
-    tmp = 0; \
+  case 235: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 131: \
+  case 236: \
     if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 132: \
-    tmp = 0; \
+  case 237: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 133: \
-    tmp = 0; \
+  case 238: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 134: \
-    tmp = 0; \
+  case 239: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 135: \
+  case 240: \
     if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 136: \
-    tmp = 0; \
+  case 241: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 19, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 137: \
-    tmp = 0; \
+  case 242: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 18, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 138: \
-    tmp = 0; \
+  case 243: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 17, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 139: \
-    tmp = 0; \
+  case 244: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 19, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 140: \
-    tmp = 0; \
+  case 245: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 18, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 141: \
-    tmp = 0; \
+  case 246: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 17, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 142: \
-    tmp = 0; \
+  case 247: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 143: \
-    tmp = 0; \
+  case 248: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 144: \
-    tmp = 0; \
+  case 249: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 145: \
-    tmp = 0; \
+  case 250: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 146: \
-    tmp = 0; \
+  case 251: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 147: \
-    tmp = 0; \
+  case 252: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 148: \
-    tmp = 0; \
+  case 253: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 149: \
-    tmp = 0; \
+  case 254: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 150: \
-    tmp = 0; \
+  case 255: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 151: \
-    tmp = 0; \
+  case 256: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 152: \
-    tmp = 0; \
+  case 257: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 153: \
-    tmp = 0; \
+  case 258: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 154: \
-    tmp = 0; \
+  case 259: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 155: \
-    tmp = 0; \
+  case 260: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 156: \
-    tmp = 0; \
+  case 261: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 157: \
-    tmp = 0; \
+  case 262: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 158: \
-    tmp = 0; \
+  case 263: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 159: \
-    tmp = 0; \
+  case 264: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 160: \
+  case 265: \
     if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 161: \
-    if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+  case 266: \
+    if (!Check(&S, DecodeVMOVModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 162: \
-    tmp = 0; \
+  case 267: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 163: \
-    tmp = 0; \
+  case 268: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 164: \
-    tmp = 0; \
+  case 269: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 165: \
-    tmp = 0; \
+  case 270: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 166: \
-    tmp = 0; \
+  case 271: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 167: \
-    tmp = 0; \
+  case 272: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 168: \
-    tmp = 0; \
+  case 273: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 169: \
-    tmp = 0; \
+  case 274: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 170: \
-    tmp = 0; \
+  case 275: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 171: \
-    tmp = 0; \
+  case 276: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 172: \
-    tmp = 0; \
+  case 277: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 173: \
-    tmp = 0; \
+  case 278: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 174: \
-    tmp = 0; \
+  case 279: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 175: \
-    tmp = 0; \
+  case 280: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 176: \
-    tmp = 0; \
+  case 281: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 177: \
-    tmp = 0; \
+  case 282: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 178: \
+  case 283: \
     if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 179: \
-    tmp = 0; \
+  case 284: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 180: \
-    tmp = 0; \
+  case 285: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 181: \
-    tmp = 0; \
+  case 286: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 182: \
-    tmp = 0; \
+  case 287: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 6); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 183: \
-    tmp = 0; \
+  case 288: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -13428,10 +20241,10 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 184: \
+  case 289: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -13440,72 +20253,72 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 185: \
-    tmp = 0; \
+  case 290: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 1) << 0; \
     tmp |= fieldname(insn, 21, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 186: \
+  case 291: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 1) << 0; \
     tmp |= fieldname(insn, 21, 1) << 1; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 187: \
-    tmp = 0; \
+  case 292: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 5, 2) << 0; \
     tmp |= fieldname(insn, 21, 1) << 2; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 188: \
+  case 293: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 5, 2) << 0; \
     tmp |= fieldname(insn, 21, 1) << 2; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 189: \
-    tmp = 0; \
+  case 294: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -13514,8 +20327,8 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 190: \
-    tmp = 0; \
+  case 295: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -13524,192 +20337,192 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 191: \
+  case 296: \
     if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 192: \
+  case 297: \
     if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 193: \
+  case 298: \
     if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 194: \
+  case 299: \
     if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 195: \
+  case 300: \
     if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 196: \
+  case 301: \
     if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 197: \
+  case 302: \
     if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 198: \
+  case 303: \
     if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 199: \
+  case 304: \
     if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 200: \
+  case 305: \
     if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 201: \
+  case 306: \
     if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 202: \
+  case 307: \
     if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 203: \
+  case 308: \
     if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 204: \
+  case 309: \
     if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 205: \
+  case 310: \
     if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 206: \
+  case 311: \
     if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 207: \
+  case 312: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 208: \
+  case 313: \
     tmp = fieldname(insn, 8, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 8); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 209: \
+  case 314: \
     if (!Check(&S, DecodeThumbAddSPReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 210: \
-    tmp = 0; \
+  case 315: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 3) << 0; \
     tmp |= fieldname(insn, 7, 1) << 3; \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 3) << 0; \
     tmp |= fieldname(insn, 7, 1) << 3; \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 211: \
-    tmp = 0; \
+  case 316: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 3) << 0; \
     tmp |= fieldname(insn, 7, 1) << 3; \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 212: \
+  case 317: \
     tmp = fieldname(insn, 3, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 213: \
+  case 318: \
     tmp = fieldname(insn, 3, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 214: \
+  case 319: \
     tmp = fieldname(insn, 8, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 8); \
     if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 215: \
+  case 320: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 6); \
     if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 216: \
+  case 321: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 8); \
     if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 217: \
+  case 322: \
     tmp = fieldname(insn, 8, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 8); \
     if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 218: \
+  case 323: \
     if (!Check(&S, DecodeThumbAddSpecialReg(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 219: \
+  case 324: \
     if (!Check(&S, DecodeThumbAddSPImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 220: \
+  case 325: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 3, 5) << 0; \
     tmp |= fieldname(insn, 9, 1) << 5; \
     if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 221: \
-    tmp = 0; \
+  case 326: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 8, 1) << 14; \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 222: \
+  case 327: \
     tmp = fieldname(insn, 3, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 223: \
+  case 328: \
     if (!Check(&S, DecodeThumbCPS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 224: \
+  case 329: \
     tmp = fieldname(insn, 0, 6); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 225: \
-    tmp = 0; \
+  case 330: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 8, 1) << 15; \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 226: \
+  case 331: \
     tmp = fieldname(insn, 0, 8); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 227: \
+  case 332: \
     tmp = fieldname(insn, 4, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 228: \
+  case 333: \
     tmp = fieldname(insn, 8, 3); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 8); \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 229: \
+  case 334: \
     tmp = fieldname(insn, 8, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 8); \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 230: \
+  case 335: \
     tmp = fieldname(insn, 0, 8); \
     if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 231: \
+  case 336: \
     tmp = fieldname(insn, 0, 11); \
     if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 232: \
-    tmp = 0; \
+  case 337: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 1, 10) << 1; \
     tmp |= fieldname(insn, 11, 1) << 21; \
     tmp |= fieldname(insn, 13, 1) << 22; \
@@ -13717,8 +20530,8 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp |= fieldname(insn, 26, 1) << 23; \
     if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 233: \
-    tmp = 0; \
+  case 338: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 11) << 0; \
     tmp |= fieldname(insn, 11, 1) << 21; \
     tmp |= fieldname(insn, 13, 1) << 22; \
@@ -13726,39 +20539,45 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp |= fieldname(insn, 26, 1) << 23; \
     if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 234: \
+  case 339: \
     if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 235: \
+  case 340: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 13) << 0; \
     tmp |= fieldname(insn, 14, 1) << 14; \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 236: \
+  case 341: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 13) << 0; \
+    tmp |= fieldname(insn, 14, 2) << 14; \
+    if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 342: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 16); \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 237: \
+  case 343: \
     tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 238: \
+  case 344: \
     tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 4, 4) << 5; \
     tmp |= fieldname(insn, 12, 3) << 9; \
     if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 239: \
+  case 345: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -13768,12 +20587,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 240: \
+  case 346: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 4, 4) << 5; \
     tmp |= fieldname(insn, 12, 3) << 9; \
@@ -13781,7 +20600,22 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 241: \
+  case 347: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 348: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 4, 4) << 5; \
+    tmp |= fieldname(insn, 12, 3) << 9; \
+    if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 349: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -13791,12 +20625,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 242: \
+  case 350: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 4, 4) << 5; \
     tmp |= fieldname(insn, 12, 3) << 9; \
@@ -13804,17 +20638,17 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 243: \
+  case 351: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 13) << 0; \
     tmp |= fieldname(insn, 14, 1) << 14; \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 244: \
+  case 352: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -13822,23 +20656,23 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 16); \
     if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 245: \
+  case 353: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 246: \
+  case 354: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 16, 4) << 8; \
     if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 247: \
+  case 355: \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
@@ -13846,7 +20680,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 248: \
+  case 356: \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
@@ -13856,24 +20690,24 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 249: \
+  case 357: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 250: \
+  case 358: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 16, 4) << 8; \
     if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 251: \
+  case 359: \
     if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 252: \
+  case 360: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
@@ -13881,18 +20715,18 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 253: \
+  case 361: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 16, 4) << 9; \
     tmp |= fieldname(insn, 23, 1) << 8; \
     if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 254: \
+  case 362: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
@@ -13900,7 +20734,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 255: \
+  case 363: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
@@ -13908,31 +20742,41 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 256: \
+  case 364: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 2) << 0; \
     tmp |= fieldname(insn, 12, 3) << 2; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 257: \
+  case 365: \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithZRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 4, 4); \
+    if (!Check(&S, DecodePredNoALOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 366: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 2) << 0; \
     tmp |= fieldname(insn, 12, 3) << 2; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 258: \
+  case 367: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
@@ -13941,12 +20785,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 23, 1) << 8; \
     if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 259: \
+  case 368: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
@@ -13955,21 +20799,21 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 23, 1) << 8; \
     if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 260: \
+  case 369: \
     if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 261: \
+  case 370: \
     if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 262: \
+  case 371: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 4, 4) << 5; \
     tmp |= fieldname(insn, 12, 3) << 9; \
@@ -13977,21 +20821,21 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 263: \
+  case 372: \
     tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 3) << 8; \
     tmp |= fieldname(insn, 26, 1) << 11; \
     if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 264: \
+  case 373: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 3) << 8; \
     tmp |= fieldname(insn, 26, 1) << 11; \
@@ -13999,10 +20843,10 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 265: \
+  case 374: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 3) << 8; \
     tmp |= fieldname(insn, 26, 1) << 11; \
@@ -14010,12 +20854,24 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 266: \
-    tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+  case 375: \
+    if (!Check(&S, DecodeT2AddSubSPImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 376: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 8) << 0; \
+    tmp |= fieldname(insn, 12, 3) << 8; \
+    tmp |= fieldname(insn, 26, 1) << 11; \
+    if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 377: \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 3) << 8; \
     tmp |= fieldname(insn, 26, 1) << 11; \
@@ -14023,24 +20879,24 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 1); \
     if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 267: \
+  case 378: \
+    if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 379: \
     tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 3) << 8; \
     tmp |= fieldname(insn, 26, 1) << 11; \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 268: \
-    if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 269: \
+  case 380: \
     if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 270: \
+  case 381: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
@@ -14048,80 +20904,93 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 271: \
+  case 382: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 2) << 0; \
     tmp |= fieldname(insn, 12, 3) << 2; \
     tmp |= fieldname(insn, 21, 1) << 5; \
     if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 272: \
+  case 383: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 6, 2) << 0; \
     tmp |= fieldname(insn, 12, 3) << 2; \
     MCOperand_CreateImm0(MI, tmp); \
     tmp = fieldname(insn, 0, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 273: \
+  case 384: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 5) << 5; \
     tmp |= fieldname(insn, 6, 2) << 0; \
     tmp |= fieldname(insn, 12, 3) << 2; \
     if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 274: \
+  case 385: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 5) << 5; \
     tmp |= fieldname(insn, 6, 2) << 0; \
     tmp |= fieldname(insn, 12, 3) << 2; \
     if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 275: \
+  case 386: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 276: \
+  case 387: \
     tmp = fieldname(insn, 0, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 277: \
+  case 388: \
+    if (!Check(&S, DecodeT2HintSpaceInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 389: \
     if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 278: \
+  case 390: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 279: \
-    tmp = 0; \
+  case 391: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 12) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 12; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 392: \
+    tmp = fieldname(insn, 16, 4); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 393: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 8, 4) << 0; \
     tmp |= fieldname(insn, 20, 1) << 4; \
     if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 280: \
-    tmp = 0; \
+  case 394: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 4, 1) << 4; \
     tmp |= fieldname(insn, 8, 4) << 0; \
     tmp |= fieldname(insn, 20, 1) << 5; \
@@ -14129,98 +20998,128 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 281: \
-    tmp = fieldname(insn, 8, 4); \
-    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 4, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    tmp |= fieldname(insn, 20, 1) << 5; \
-    if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 282: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 12) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 12; \
-    MCOperand_CreateImm0(MI, tmp); \
-    return S; \
-  case 283: \
-    tmp = fieldname(insn, 16, 4); \
-    MCOperand_CreateImm0(MI, tmp); \
-    return S; \
-  case 284: \
-    tmp = 0; \
+  case 395: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 10, 2) << 10; \
     if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 285: \
+  case 396: \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    tmp |= fieldname(insn, 20, 1) << 5; \
+    if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 397: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 8); \
     if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 286: \
+  case 398: \
     if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 287: \
+  case 399: \
+    if (!Check(&S, DecodeLOLoop(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 400: \
+    tmp = fieldname(insn, 23, 4); \
+    if (!Check(&S, DecodeBFLabelOperand_0_0_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 10) << 1; \
+    tmp |= fieldname(insn, 11, 1) << 0; \
+    tmp |= fieldname(insn, 16, 7) << 11; \
+    if (!Check(&S, DecodeBFLabelOperand_1_0_1_18(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 401: \
+    tmp = fieldname(insn, 23, 4); \
+    if (!Check(&S, DecodeBFLabelOperand_0_0_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 10) << 1; \
+    tmp |= fieldname(insn, 11, 1) << 0; \
+    tmp |= fieldname(insn, 16, 1) << 11; \
+    if (!Check(&S, DecodeBFLabelOperand_1_0_1_12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 1); \
+    if (!Check(&S, DecodeBFAfterTargetOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 18, 4); \
+    if (!Check(&S, DecodePredNoALOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 402: \
+    tmp = fieldname(insn, 23, 4); \
+    if (!Check(&S, DecodeBFLabelOperand_0_0_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 10) << 1; \
+    tmp |= fieldname(insn, 11, 1) << 0; \
+    tmp |= fieldname(insn, 16, 5) << 11; \
+    if (!Check(&S, DecodeBFLabelOperand_1_0_1_16(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 403: \
+    tmp = fieldname(insn, 23, 4); \
+    if (!Check(&S, DecodeBFLabelOperand_0_0_0_4(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 404: \
     if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 288: \
+  case 405: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 2; \
     tmp |= fieldname(insn, 4, 2) << 0; \
     tmp |= fieldname(insn, 16, 4) << 6; \
     if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 289: \
+  case 406: \
     if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 290: \
+  case 407: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 16, 4) << 9; \
     if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 291: \
+  case 408: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 9, 1) << 8; \
     tmp |= fieldname(insn, 16, 4) << 9; \
     if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 292: \
+  case 409: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x1000; \
     tmp |= fieldname(insn, 0, 12) << 0; \
     tmp |= fieldname(insn, 16, 4) << 13; \
     if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 293: \
+  case 410: \
     if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 294: \
+  case 411: \
     if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 295: \
+  case 412: \
     if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 296: \
+  case 413: \
     if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 297: \
+  case 414: \
     if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 298: \
+  case 415: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -14228,7 +21127,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 299: \
+  case 416: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
@@ -14236,7 +21135,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 4, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 300: \
+  case 417: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -14246,7 +21145,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 4, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 301: \
+  case 418: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 4); \
@@ -14254,15 +21153,15 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 302: \
+  case 419: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 303: \
+  case 420: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -14272,7 +21171,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 304: \
+  case 421: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
@@ -14282,7 +21181,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 305: \
+  case 422: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -14290,33 +21189,33 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 306: \
+  case 423: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 2; \
     tmp |= fieldname(insn, 4, 2) << 0; \
     tmp |= fieldname(insn, 16, 4) << 6; \
     if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 307: \
+  case 424: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 9, 1) << 8; \
     tmp |= fieldname(insn, 16, 4) << 9; \
     if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 308: \
+  case 425: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x1000; \
     tmp |= fieldname(insn, 0, 12) << 0; \
     tmp |= fieldname(insn, 16, 4) << 13; \
     if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 309: \
+  case 426: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 4); \
@@ -14330,7 +21229,517 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 310: \
+  case 427: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 428: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 429: \
+    tmp = fieldname(insn, 8, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 430: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 4) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 431: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    tmp |= fieldname(insn, 16, 4) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 432: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 1; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 20, 2) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 433: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 4) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 434: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    tmp |= fieldname(insn, 16, 4) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 435: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 20, 2) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 436: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 4) << 7; \
+    tmp |= fieldname(insn, 24, 1) << 11; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 437: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    tmp |= fieldname(insn, 16, 4) << 2; \
+    tmp |= fieldname(insn, 24, 1) << 6; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 438: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 20, 2) << 1; \
+    tmp |= fieldname(insn, 24, 1) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeVpredROperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 439: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 6) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 440: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 20, 2) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 441: \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 2) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 2; \
+    tmp |= fieldname(insn, 20, 3) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 442: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 6) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 443: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 20, 2) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 444: \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 2) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 2; \
+    tmp |= fieldname(insn, 20, 3) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 445: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 4) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 446: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    tmp |= fieldname(insn, 16, 4) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 447: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 1; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 20, 2) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 448: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 4) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 449: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    tmp |= fieldname(insn, 16, 4) << 2; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 450: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 20, 2) << 1; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 451: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 4) << 7; \
+    tmp |= fieldname(insn, 24, 1) << 11; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 452: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 1; \
+    tmp |= fieldname(insn, 16, 4) << 2; \
+    tmp |= fieldname(insn, 24, 1) << 6; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 453: \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 13, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 17, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 1, 3); \
+    if (!Check(&S, DecodeMQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 1) << 0; \
+    tmp |= fieldname(insn, 20, 2) << 1; \
+    tmp |= fieldname(insn, 24, 1) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 454: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 6) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 455: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 20, 2) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 456: \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 2) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 2; \
+    tmp |= fieldname(insn, 20, 3) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 457: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 16, 6) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 458: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 6) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 6; \
+    tmp |= fieldname(insn, 20, 2) << 7; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 459: \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 8, 3); \
+    if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 0, 4); \
+    if (!Check(&S, DecodeGPRPairnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRwithAPSR_NZCVnospRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 4, 2) << 0; \
+    tmp |= fieldname(insn, 7, 1) << 2; \
+    tmp |= fieldname(insn, 20, 3) << 3; \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 460: \
     tmp = fieldname(insn, 8, 4); \
     if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 4, 4); \
@@ -14342,7 +21751,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 311: \
+  case 461: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
@@ -14354,7 +21763,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 4); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 312: \
+  case 462: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 3); \
@@ -14362,7 +21771,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 6, 5); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 313: \
+  case 463: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 3); \
@@ -14370,7 +21779,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 6, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 314: \
+  case 464: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 3); \
@@ -14378,7 +21787,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 6, 3); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 315: \
+  case 465: \
     tmp = fieldname(insn, 8, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 8, 3); \
@@ -14386,7 +21795,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 8); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 316: \
+  case 466: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 0, 3); \
@@ -14394,7 +21803,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 3, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 317: \
+  case 467: \
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 3, 3); \
@@ -14402,12 +21811,12 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 0, 3); \
     if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 318: \
-    tmp = 0; \
+  case 468: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 16, 4) << 9; \
     tmp |= fieldname(insn, 23, 1) << 8; \
@@ -14415,72 +21824,166 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 319: \
-    tmp = 0; \
+  case 469: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 1; \
     tmp |= fieldname(insn, 5, 1) << 0; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 320: \
-    tmp = 0; \
+  case 470: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 1; \
     tmp |= fieldname(insn, 5, 1) << 0; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 321: \
-    tmp = 0; \
+  case 471: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 322: \
+  case 472: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 1; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 473: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 4; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 474: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 475: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 476: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 477: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 478: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 479: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 480: \
     if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 323: \
+  case 481: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 4) << 9; \
     tmp |= fieldname(insn, 22, 1) << 8; \
     if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 324: \
-    tmp = 0; \
+  case 482: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 16, 4) << 9; \
     tmp |= fieldname(insn, 23, 1) << 8; \
@@ -14488,44 +21991,44 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 325: \
-    tmp = 0; \
+  case 483: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 1; \
     tmp |= fieldname(insn, 5, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 326: \
-    tmp = 0; \
+  case 484: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 1; \
     tmp |= fieldname(insn, 5, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 327: \
-    tmp = 0; \
+  case 485: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -14534,392 +22037,339 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 328: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 329: \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 1, 7) << 1; \
-    tmp |= fieldname(insn, 12, 4) << 8; \
-    tmp |= fieldname(insn, 22, 1) << 12; \
-    if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 330: \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 1, 7) << 1; \
-    tmp |= fieldname(insn, 12, 4) << 8; \
-    if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 331: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 8) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 9; \
-    tmp |= fieldname(insn, 23, 1) << 8; \
-    if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 332: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 333: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 4; \
-    tmp |= fieldname(insn, 16, 4) << 0; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 334: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 1; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 335: \
+  case 486: \
     if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 336: \
+  case 487: \
+    if (!Check(&S, DecodeVSCCLRM(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 488: \
     tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 337: \
-    tmp = fieldname(insn, 12, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 338: \
+  case 489: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 339: \
+  case 490: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 8) << 0; \
     tmp |= fieldname(insn, 12, 4) << 9; \
     tmp |= fieldname(insn, 22, 1) << 8; \
     if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 340: \
-    tmp = fieldname(insn, 16, 4); \
+  case 491: \
+    if (!Check(&S, DecodeForVMRSandVMSR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 492: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 4; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 493: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 494: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 495: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 496: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 12, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    return S; \
+  case 497: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 1, 7) << 1; \
     tmp |= fieldname(insn, 12, 4) << 8; \
     tmp |= fieldname(insn, 22, 1) << 12; \
     if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 341: \
-    tmp = fieldname(insn, 16, 4); \
-    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+  case 498: \
     tmp = fieldname(insn, 16, 4); \
     if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 1, 7) << 1; \
     tmp |= fieldname(insn, 12, 4) << 8; \
     if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 342: \
-    if (!Check(&S, DecodeForVMRSandVMSR(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 343: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 4; \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 344: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 345: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 346: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 347: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 348: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 349: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 350: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 4; \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 351: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 352: \
-    tmp = 0; \
+  case 499: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 8) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 9; \
+    tmp |= fieldname(insn, 23, 1) << 8; \
+    if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 28, 4); \
     if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 353: \
-    tmp = 0; \
+  case 500: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 4; \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 354: \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 355: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 0; \
-    tmp |= fieldname(insn, 5, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 356: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 357: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    MCOperand_CreateImm0(MI, tmp); \
-    tmp = fieldname(insn, 28, 4); \
-    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 358: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 0; \
-    tmp |= fieldname(insn, 22, 1) << 4; \
-    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 501: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 502: \
+    tmp = fieldname(insn, 12, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 503: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 7) << 1; \
+    tmp |= fieldname(insn, 12, 4) << 8; \
+    tmp |= fieldname(insn, 22, 1) << 12; \
+    if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 504: \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 16, 4); \
+    if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 1, 7) << 1; \
+    tmp |= fieldname(insn, 12, 4) << 8; \
+    if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 505: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 4; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 506: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 507: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 508: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 509: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    MCOperand_CreateImm0(MI, tmp); \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 510: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 0; \
+    tmp |= fieldname(insn, 5, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 28, 4); \
+    if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 511: \
+    if (!Check(&S, DecodeVSTRVLDR_SYSREG_0(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 512: \
+    if (!Check(&S, DecodeVSTRVLDR_SYSREG_1(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 513: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 4; \
+    tmp |= fieldname(insn, 16, 4) << 0; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 24, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 359: \
-    tmp = 0; \
+  case 514: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 23, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 360: \
-    tmp = 0; \
+  case 515: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -14930,55 +22380,55 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 361: \
+  case 516: \
     if (!Check(&S, DecodeNEONComplexLane64Instruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 362: \
-    tmp = 0; \
+  case 517: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 24, 1); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 363: \
-    tmp = 0; \
+  case 518: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     tmp = fieldname(insn, 23, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 364: \
-    tmp = 0; \
+  case 519: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 0; \
     tmp |= fieldname(insn, 22, 1) << 4; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 4; \
     tmp |= fieldname(insn, 16, 4) << 0; \
     if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -14989,60 +22439,114 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
     tmp = fieldname(insn, 20, 2); \
     MCOperand_CreateImm0(MI, tmp); \
     return S; \
-  case 365: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 7, 1) << 0; \
-    tmp |= fieldname(insn, 16, 4) << 1; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 366: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 367: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
-    tmp |= fieldname(insn, 0, 4) << 1; \
-    tmp |= fieldname(insn, 5, 1) << 0; \
-    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    return S; \
-  case 368: \
-    tmp = 0; \
-    tmp |= fieldname(insn, 12, 4) << 1; \
-    tmp |= fieldname(insn, 22, 1) << 0; \
-    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+  case 520: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 7, 1) << 0; \
     tmp |= fieldname(insn, 16, 4) << 1; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 3) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPR_8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = fieldname(insn, 3, 1); \
+    MCOperand_CreateImm0(MI, tmp); \
+    return S; \
+  case 521: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 0; \
+    tmp |= fieldname(insn, 22, 1) << 4; \
+    if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 1; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 1; \
     tmp |= fieldname(insn, 5, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
     return S; \
-  case 369: \
-    tmp = 0; \
+  case 522: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 1; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 523: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 524: \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 12, 4) << 1; \
     tmp |= fieldname(insn, 22, 1) << 0; \
     if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
-    tmp = 0; \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeHPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 525: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 7, 1) << 0; \
+    tmp |= fieldname(insn, 16, 4) << 1; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 526: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 527: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 0, 4) << 1; \
+    tmp |= fieldname(insn, 5, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    return S; \
+  case 528: \
+    tmp = 0x0; \
+    tmp |= fieldname(insn, 12, 4) << 1; \
+    tmp |= fieldname(insn, 22, 1) << 0; \
+    if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
+    tmp = 0x0; \
     tmp |= fieldname(insn, 0, 4) << 0; \
     tmp |= fieldname(insn, 5, 1) << 4; \
     if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \
@@ -15052,32 +22556,28 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
 
 #define DecodeInstruction(fname, fieldname, decoder, InsnType) \
 static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
-		InsnType insn, uint64_t Address) \
-{ \
-  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
-  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
-  bool Pred, Fail, DecodeComplete = true; \
-  uint32_t ExpectedValue; \
+                                      InsnType insn, uint64_t Address) { \
   const uint8_t *Ptr = DecodeTable; \
-  uint32_t CurFieldValue = 0; \
+  uint64_t CurFieldValue = 0; \
   DecodeStatus S = MCDisassembler_Success; \
   while (true) { \
     switch (*Ptr) { \
     default: \
       return MCDisassembler_Fail; \
     case MCD_OPC_ExtractField: { \
-      Start = *++Ptr; \
-      Len = *++Ptr; \
+      unsigned Start = *++Ptr; \
+      unsigned Len = *++Ptr; \
       ++Ptr; \
       CurFieldValue = fieldname(insn, Start, Len); \
       break; \
     } \
     case MCD_OPC_FilterValue: { \
       /* Decode the field value. */ \
-      Val = decodeULEB128(++Ptr, &Len); \
+      unsigned Len; \
+      uint64_t Val = decodeULEB128(++Ptr, &Len); \
       Ptr += Len; \
       /* NumToSkip is a plain 24-bit integer. */ \
-      NumToSkip = *Ptr++; \
+      unsigned NumToSkip = *Ptr++; \
       NumToSkip |= (*Ptr++) << 8; \
       NumToSkip |= (*Ptr++) << 16; \
       /* Perform the filter operation. */ \
@@ -15086,14 +22586,15 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
       break; \
     } \
     case MCD_OPC_CheckField: { \
-      Start = *++Ptr; \
-      Len = *++Ptr; \
-      FieldValue = fieldname(insn, Start, Len); \
+      unsigned Start = *++Ptr; \
+      unsigned Len = *++Ptr; \
+      uint64_t FieldValue = fieldname(insn, Start, Len); \
       /* Decode the field value. */ \
-      ExpectedValue = decodeULEB128(++Ptr, &Len); \
-      Ptr += Len; \
+      unsigned PtrLen = 0; \
+      uint64_t ExpectedValue = decodeULEB128(++Ptr, &PtrLen); \
+      Ptr += PtrLen; \
       /* NumToSkip is a plain 24-bit integer. */ \
-      NumToSkip = *Ptr++; \
+      unsigned NumToSkip = *Ptr++; \
       NumToSkip |= (*Ptr++) << 8; \
       NumToSkip |= (*Ptr++) << 16; \
       /* If the actual and expected values don't match, skip. */ \
@@ -15102,50 +22603,52 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
       break; \
     } \
     case MCD_OPC_CheckPredicate: { \
+      unsigned Len; \
       /* Decode the Predicate Index value. */ \
-      PIdx = decodeULEB128(++Ptr, &Len); \
+      unsigned PIdx = decodeULEB128(++Ptr, &Len); \
       Ptr += Len; \
       /* NumToSkip is a plain 24-bit integer. */ \
-      NumToSkip = *Ptr++; \
+      unsigned NumToSkip = *Ptr++; \
       NumToSkip |= (*Ptr++) << 8; \
       NumToSkip |= (*Ptr++) << 16; \
       /* Check the predicate. */ \
-      if (!(Pred = checkDecoderPredicate(PIdx, MI))) \
+      bool Pred = checkDecoderPredicate(MI, PIdx); \
+      if (!Pred) \
         Ptr += NumToSkip; \
-		/* printf("55 PIdx = %u, Pred = %u\n", PIdx, Pred); */ \
-      (void)Pred; \
       break; \
     } \
     case MCD_OPC_Decode: { \
+      unsigned Len; \
       /* Decode the Opcode value. */ \
-      Opc = decodeULEB128(++Ptr, &Len); \
+      unsigned Opc = decodeULEB128(++Ptr, &Len); \
       Ptr += Len; \
-      DecodeIdx = decodeULEB128(Ptr, &Len); \
+      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
       Ptr += Len; \
       MCInst_clear(MI); \
       MCInst_setOpcode(MI, Opc); \
+      bool DecodeComplete; \
       S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \
-      /* assert(DecodeComplete); */ \
       return S; \
     } \
     case MCD_OPC_TryDecode: { \
+      unsigned Len; \
       /* Decode the Opcode value. */ \
-      Opc = decodeULEB128(++Ptr, &Len); \
+      unsigned Opc = decodeULEB128(++Ptr, &Len); \
       Ptr += Len; \
-      DecodeIdx = decodeULEB128(Ptr, &Len); \
+      unsigned DecodeIdx = decodeULEB128(Ptr, &Len); \
       Ptr += Len; \
       /* NumToSkip is a plain 24-bit integer. */ \
-      NumToSkip = *Ptr++; \
+      unsigned NumToSkip = *Ptr++; \
       NumToSkip |= (*Ptr++) << 8; \
       NumToSkip |= (*Ptr++) << 16; \
       /* Perform the decode operation. */ \
       MCInst_setOpcode(MI, Opc); \
+      bool DecodeComplete; \
       S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \
       if (DecodeComplete) { \
         /* Decoding complete. */ \
         return S; \
       } else { \
-        /* assert(S == MCDisassembler_Fail); */ \
         /* If the decoding was incomplete, skip. */ \
         Ptr += NumToSkip; \
         /* Reset decode status. This also drops a SoftFail status that could be */ \
@@ -15156,11 +22659,12 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
     } \
     case MCD_OPC_SoftFail: { \
       /* Decode the mask values. */ \
-      PositiveMask = decodeULEB128(++Ptr, &Len); \
+      unsigned Len; \
+      uint64_t PositiveMask = decodeULEB128(++Ptr, &Len); \
       Ptr += Len; \
-      NegativeMask = decodeULEB128(Ptr, &Len); \
+      uint64_t NegativeMask = decodeULEB128(Ptr, &Len); \
       Ptr += Len; \
-      Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
+      bool Fail = (insn & PositiveMask) != 0 || (~insn & NegativeMask) != 0; \
       if (Fail) \
         S = MCDisassembler_SoftFail; \
       break; \
@@ -15170,11 +22674,9 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
     } \
     } \
   } \
-  /* llvm_unreachable("bogosity detected in disassembler state machine!");*/  \
+  /* Bogisity detected in disassembler state machine! */ \
 }
 
-
-
 FieldFromInstruction(fieldFromInstruction_2, uint16_t)
 DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint16_t)
 DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2, uint16_t)
@@ -15182,4 +22684,3 @@ DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2,
 FieldFromInstruction(fieldFromInstruction_4, uint32_t)
 DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
 DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
-
diff --git a/arch/ARM/ARMGenInstrInfo.inc b/arch/ARM/ARMGenInstrInfo.inc
index 82178f342..0e1727ce1 100644
--- a/arch/ARM/ARMGenInstrInfo.inc
+++ b/arch/ARM/ARMGenInstrInfo.inc
@@ -1,6632 +1,9468 @@
-
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
-|* Target Instruction Enum Values and Descriptors                             *|
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
 
 #ifdef GET_INSTRINFO_ENUM
 #undef GET_INSTRINFO_ENUM
 
-enum {
-	ARM_PHI	= 0,
-	ARM_INLINEASM	= 1,
-	ARM_CFI_INSTRUCTION	= 2,
-	ARM_EH_LABEL	= 3,
-	ARM_GC_LABEL	= 4,
-	ARM_ANNOTATION_LABEL	= 5,
-	ARM_KILL	= 6,
-	ARM_EXTRACT_SUBREG	= 7,
-	ARM_INSERT_SUBREG	= 8,
-	ARM_IMPLICIT_DEF	= 9,
-	ARM_SUBREG_TO_REG	= 10,
-	ARM_COPY_TO_REGCLASS	= 11,
-	ARM_DBG_VALUE	= 12,
-	ARM_DBG_LABEL	= 13,
-	ARM_REG_SEQUENCE	= 14,
-	ARM_COPY	= 15,
-	ARM_BUNDLE	= 16,
-	ARM_LIFETIME_START	= 17,
-	ARM_LIFETIME_END	= 18,
-	ARM_STACKMAP	= 19,
-	ARM_FENTRY_CALL	= 20,
-	ARM_PATCHPOINT	= 21,
-	ARM_LOAD_STACK_GUARD	= 22,
-	ARM_STATEPOINT	= 23,
-	ARM_LOCAL_ESCAPE	= 24,
-	ARM_FAULTING_OP	= 25,
-	ARM_PATCHABLE_OP	= 26,
-	ARM_PATCHABLE_FUNCTION_ENTER	= 27,
-	ARM_PATCHABLE_RET	= 28,
-	ARM_PATCHABLE_FUNCTION_EXIT	= 29,
-	ARM_PATCHABLE_TAIL_CALL	= 30,
-	ARM_PATCHABLE_EVENT_CALL	= 31,
-	ARM_PATCHABLE_TYPED_EVENT_CALL	= 32,
-	ARM_ICALL_BRANCH_FUNNEL	= 33,
-	ARM_G_ADD	= 34,
-	ARM_G_SUB	= 35,
-	ARM_G_MUL	= 36,
-	ARM_G_SDIV	= 37,
-	ARM_G_UDIV	= 38,
-	ARM_G_SREM	= 39,
-	ARM_G_UREM	= 40,
-	ARM_G_AND	= 41,
-	ARM_G_OR	= 42,
-	ARM_G_XOR	= 43,
-	ARM_G_IMPLICIT_DEF	= 44,
-	ARM_G_PHI	= 45,
-	ARM_G_FRAME_INDEX	= 46,
-	ARM_G_GLOBAL_VALUE	= 47,
-	ARM_G_EXTRACT	= 48,
-	ARM_G_UNMERGE_VALUES	= 49,
-	ARM_G_INSERT	= 50,
-	ARM_G_MERGE_VALUES	= 51,
-	ARM_G_PTRTOINT	= 52,
-	ARM_G_INTTOPTR	= 53,
-	ARM_G_BITCAST	= 54,
-	ARM_G_LOAD	= 55,
-	ARM_G_SEXTLOAD	= 56,
-	ARM_G_ZEXTLOAD	= 57,
-	ARM_G_STORE	= 58,
-	ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 59,
-	ARM_G_ATOMIC_CMPXCHG	= 60,
-	ARM_G_ATOMICRMW_XCHG	= 61,
-	ARM_G_ATOMICRMW_ADD	= 62,
-	ARM_G_ATOMICRMW_SUB	= 63,
-	ARM_G_ATOMICRMW_AND	= 64,
-	ARM_G_ATOMICRMW_NAND	= 65,
-	ARM_G_ATOMICRMW_OR	= 66,
-	ARM_G_ATOMICRMW_XOR	= 67,
-	ARM_G_ATOMICRMW_MAX	= 68,
-	ARM_G_ATOMICRMW_MIN	= 69,
-	ARM_G_ATOMICRMW_UMAX	= 70,
-	ARM_G_ATOMICRMW_UMIN	= 71,
-	ARM_G_BRCOND	= 72,
-	ARM_G_BRINDIRECT	= 73,
-	ARM_G_INTRINSIC	= 74,
-	ARM_G_INTRINSIC_W_SIDE_EFFECTS	= 75,
-	ARM_G_ANYEXT	= 76,
-	ARM_G_TRUNC	= 77,
-	ARM_G_CONSTANT	= 78,
-	ARM_G_FCONSTANT	= 79,
-	ARM_G_VASTART	= 80,
-	ARM_G_VAARG	= 81,
-	ARM_G_SEXT	= 82,
-	ARM_G_ZEXT	= 83,
-	ARM_G_SHL	= 84,
-	ARM_G_LSHR	= 85,
-	ARM_G_ASHR	= 86,
-	ARM_G_ICMP	= 87,
-	ARM_G_FCMP	= 88,
-	ARM_G_SELECT	= 89,
-	ARM_G_UADDE	= 90,
-	ARM_G_USUBE	= 91,
-	ARM_G_SADDO	= 92,
-	ARM_G_SSUBO	= 93,
-	ARM_G_UMULO	= 94,
-	ARM_G_SMULO	= 95,
-	ARM_G_UMULH	= 96,
-	ARM_G_SMULH	= 97,
-	ARM_G_FADD	= 98,
-	ARM_G_FSUB	= 99,
-	ARM_G_FMUL	= 100,
-	ARM_G_FMA	= 101,
-	ARM_G_FDIV	= 102,
-	ARM_G_FREM	= 103,
-	ARM_G_FPOW	= 104,
-	ARM_G_FEXP	= 105,
-	ARM_G_FEXP2	= 106,
-	ARM_G_FLOG	= 107,
-	ARM_G_FLOG2	= 108,
-	ARM_G_FNEG	= 109,
-	ARM_G_FPEXT	= 110,
-	ARM_G_FPTRUNC	= 111,
-	ARM_G_FPTOSI	= 112,
-	ARM_G_FPTOUI	= 113,
-	ARM_G_SITOFP	= 114,
-	ARM_G_UITOFP	= 115,
-	ARM_G_FABS	= 116,
-	ARM_G_GEP	= 117,
-	ARM_G_PTR_MASK	= 118,
-	ARM_G_BR	= 119,
-	ARM_G_INSERT_VECTOR_ELT	= 120,
-	ARM_G_EXTRACT_VECTOR_ELT	= 121,
-	ARM_G_SHUFFLE_VECTOR	= 122,
-	ARM_G_BSWAP	= 123,
-	ARM_G_ADDRSPACE_CAST	= 124,
-	ARM_G_BLOCK_ADDR	= 125,
-	ARM_ABS	= 126,
-	ARM_ADDSri	= 127,
-	ARM_ADDSrr	= 128,
-	ARM_ADDSrsi	= 129,
-	ARM_ADDSrsr	= 130,
-	ARM_ADJCALLSTACKDOWN	= 131,
-	ARM_ADJCALLSTACKUP	= 132,
-	ARM_ASRi	= 133,
-	ARM_ASRr	= 134,
-	ARM_B	= 135,
-	ARM_BCCZi64	= 136,
-	ARM_BCCi64	= 137,
-	ARM_BMOVPCB_CALL	= 138,
-	ARM_BMOVPCRX_CALL	= 139,
-	ARM_BR_JTadd	= 140,
-	ARM_BR_JTm_i12	= 141,
-	ARM_BR_JTm_rs	= 142,
-	ARM_BR_JTr	= 143,
-	ARM_BX_CALL	= 144,
-	ARM_CMP_SWAP_16	= 145,
-	ARM_CMP_SWAP_32	= 146,
-	ARM_CMP_SWAP_64	= 147,
-	ARM_CMP_SWAP_8	= 148,
-	ARM_CONSTPOOL_ENTRY	= 149,
-	ARM_COPY_STRUCT_BYVAL_I32	= 150,
-	ARM_CompilerBarrier	= 151,
-	ARM_ITasm	= 152,
-	ARM_Int_eh_sjlj_dispatchsetup	= 153,
-	ARM_Int_eh_sjlj_setup_dispatch	= 157,
-	ARM_JUMPTABLE_ADDRS	= 158,
-	ARM_JUMPTABLE_INSTS	= 159,
-	ARM_JUMPTABLE_TBB	= 160,
-	ARM_JUMPTABLE_TBH	= 161,
-	ARM_LDMIA_RET	= 162,
-	ARM_LDRBT_POST	= 163,
-	ARM_LDRConstPool	= 164,
-	ARM_LDRLIT_ga_abs	= 165,
-	ARM_LDRLIT_ga_pcrel	= 166,
-	ARM_LDRLIT_ga_pcrel_ldr	= 167,
-	ARM_LDRT_POST	= 168,
-	ARM_LEApcrel	= 169,
-	ARM_LEApcrelJT	= 170,
-	ARM_LSLi	= 171,
-	ARM_LSLr	= 172,
-	ARM_LSRi	= 173,
-	ARM_LSRr	= 174,
-	ARM_MEMCPY	= 175,
-	ARM_MLAv5	= 176,
-	ARM_MOVCCi	= 177,
-	ARM_MOVCCi16	= 178,
-	ARM_MOVCCi32imm	= 179,
-	ARM_MOVCCr	= 180,
-	ARM_MOVCCsi	= 181,
-	ARM_MOVCCsr	= 182,
-	ARM_MOVPCRX	= 183,
-	ARM_MOVTi16_ga_pcrel	= 184,
-	ARM_MOV_ga_pcrel	= 185,
-	ARM_MOV_ga_pcrel_ldr	= 186,
-	ARM_MOVi16_ga_pcrel	= 187,
-	ARM_MOVi32imm	= 188,
-	ARM_MOVsra_flag	= 189,
-	ARM_MOVsrl_flag	= 190,
-	ARM_MULv5	= 191,
-	ARM_MVNCCi	= 192,
-	ARM_PICADD	= 193,
-	ARM_PICLDR	= 194,
-	ARM_PICLDRB	= 195,
-	ARM_PICLDRH	= 196,
-	ARM_PICLDRSB	= 197,
-	ARM_PICLDRSH	= 198,
-	ARM_PICSTR	= 199,
-	ARM_PICSTRB	= 200,
-	ARM_PICSTRH	= 201,
-	ARM_RORi	= 202,
-	ARM_RORr	= 203,
-	ARM_RRX	= 204,
-	ARM_RRXi	= 205,
-	ARM_RSBSri	= 206,
-	ARM_RSBSrsi	= 207,
-	ARM_RSBSrsr	= 208,
-	ARM_SMLALv5	= 209,
-	ARM_SMULLv5	= 210,
-	ARM_SPACE	= 211,
-	ARM_STRBT_POST	= 212,
-	ARM_STRBi_preidx	= 213,
-	ARM_STRBr_preidx	= 214,
-	ARM_STRH_preidx	= 215,
-	ARM_STRT_POST	= 216,
-	ARM_STRi_preidx	= 217,
-	ARM_STRr_preidx	= 218,
-	ARM_SUBS_PC_LR	= 219,
-	ARM_SUBSri	= 220,
-	ARM_SUBSrr	= 221,
-	ARM_SUBSrsi	= 222,
-	ARM_SUBSrsr	= 223,
-	ARM_TAILJMPd	= 224,
-	ARM_TAILJMPr	= 225,
-	ARM_TAILJMPr4	= 226,
-	ARM_TCRETURNdi	= 227,
-	ARM_TCRETURNri	= 228,
-	ARM_TPsoft	= 229,
-	ARM_UMLALv5	= 230,
-	ARM_UMULLv5	= 231,
-	ARM_VLD1LNdAsm_16	= 232,
-	ARM_VLD1LNdAsm_32	= 233,
-	ARM_VLD1LNdAsm_8	= 234,
-	ARM_VLD1LNdWB_fixed_Asm_16	= 235,
-	ARM_VLD1LNdWB_fixed_Asm_32	= 236,
-	ARM_VLD1LNdWB_fixed_Asm_8	= 237,
-	ARM_VLD1LNdWB_register_Asm_16	= 238,
-	ARM_VLD1LNdWB_register_Asm_32	= 239,
-	ARM_VLD1LNdWB_register_Asm_8	= 240,
-	ARM_VLD2LNdAsm_16	= 241,
-	ARM_VLD2LNdAsm_32	= 242,
-	ARM_VLD2LNdAsm_8	= 243,
-	ARM_VLD2LNdWB_fixed_Asm_16	= 244,
-	ARM_VLD2LNdWB_fixed_Asm_32	= 245,
-	ARM_VLD2LNdWB_fixed_Asm_8	= 246,
-	ARM_VLD2LNdWB_register_Asm_16	= 247,
-	ARM_VLD2LNdWB_register_Asm_32	= 248,
-	ARM_VLD2LNdWB_register_Asm_8	= 249,
-	ARM_VLD2LNqAsm_16	= 250,
-	ARM_VLD2LNqAsm_32	= 251,
-	ARM_VLD2LNqWB_fixed_Asm_16	= 252,
-	ARM_VLD2LNqWB_fixed_Asm_32	= 253,
-	ARM_VLD2LNqWB_register_Asm_16	= 254,
-	ARM_VLD2LNqWB_register_Asm_32	= 255,
-	ARM_VLD3DUPdAsm_16	= 256,
-	ARM_VLD3DUPdAsm_32	= 257,
-	ARM_VLD3DUPdAsm_8	= 258,
-	ARM_VLD3DUPdWB_fixed_Asm_16	= 259,
-	ARM_VLD3DUPdWB_fixed_Asm_32	= 260,
-	ARM_VLD3DUPdWB_fixed_Asm_8	= 261,
-	ARM_VLD3DUPdWB_register_Asm_16	= 262,
-	ARM_VLD3DUPdWB_register_Asm_32	= 263,
-	ARM_VLD3DUPdWB_register_Asm_8	= 264,
-	ARM_VLD3DUPqAsm_16	= 265,
-	ARM_VLD3DUPqAsm_32	= 266,
-	ARM_VLD3DUPqAsm_8	= 267,
-	ARM_VLD3DUPqWB_fixed_Asm_16	= 268,
-	ARM_VLD3DUPqWB_fixed_Asm_32	= 269,
-	ARM_VLD3DUPqWB_fixed_Asm_8	= 270,
-	ARM_VLD3DUPqWB_register_Asm_16	= 271,
-	ARM_VLD3DUPqWB_register_Asm_32	= 272,
-	ARM_VLD3DUPqWB_register_Asm_8	= 273,
-	ARM_VLD3LNdAsm_16	= 274,
-	ARM_VLD3LNdAsm_32	= 275,
-	ARM_VLD3LNdAsm_8	= 276,
-	ARM_VLD3LNdWB_fixed_Asm_16	= 277,
-	ARM_VLD3LNdWB_fixed_Asm_32	= 278,
-	ARM_VLD3LNdWB_fixed_Asm_8	= 279,
-	ARM_VLD3LNdWB_register_Asm_16	= 280,
-	ARM_VLD3LNdWB_register_Asm_32	= 281,
-	ARM_VLD3LNdWB_register_Asm_8	= 282,
-	ARM_VLD3LNqAsm_16	= 283,
-	ARM_VLD3LNqAsm_32	= 284,
-	ARM_VLD3LNqWB_fixed_Asm_16	= 285,
-	ARM_VLD3LNqWB_fixed_Asm_32	= 286,
-	ARM_VLD3LNqWB_register_Asm_16	= 287,
-	ARM_VLD3LNqWB_register_Asm_32	= 288,
-	ARM_VLD3dAsm_16	= 289,
-	ARM_VLD3dAsm_32	= 290,
-	ARM_VLD3dAsm_8	= 291,
-	ARM_VLD3dWB_fixed_Asm_16	= 292,
-	ARM_VLD3dWB_fixed_Asm_32	= 293,
-	ARM_VLD3dWB_fixed_Asm_8	= 294,
-	ARM_VLD3dWB_register_Asm_16	= 295,
-	ARM_VLD3dWB_register_Asm_32	= 296,
-	ARM_VLD3dWB_register_Asm_8	= 297,
-	ARM_VLD3qAsm_16	= 298,
-	ARM_VLD3qAsm_32	= 299,
-	ARM_VLD3qAsm_8	= 300,
-	ARM_VLD3qWB_fixed_Asm_16	= 301,
-	ARM_VLD3qWB_fixed_Asm_32	= 302,
-	ARM_VLD3qWB_fixed_Asm_8	= 303,
-	ARM_VLD3qWB_register_Asm_16	= 304,
-	ARM_VLD3qWB_register_Asm_32	= 305,
-	ARM_VLD3qWB_register_Asm_8	= 306,
-	ARM_VLD4DUPdAsm_16	= 307,
-	ARM_VLD4DUPdAsm_32	= 308,
-	ARM_VLD4DUPdAsm_8	= 309,
-	ARM_VLD4DUPdWB_fixed_Asm_16	= 310,
-	ARM_VLD4DUPdWB_fixed_Asm_32	= 311,
-	ARM_VLD4DUPdWB_fixed_Asm_8	= 312,
-	ARM_VLD4DUPdWB_register_Asm_16	= 313,
-	ARM_VLD4DUPdWB_register_Asm_32	= 314,
-	ARM_VLD4DUPdWB_register_Asm_8	= 315,
-	ARM_VLD4DUPqAsm_16	= 316,
-	ARM_VLD4DUPqAsm_32	= 317,
-	ARM_VLD4DUPqAsm_8	= 318,
-	ARM_VLD4DUPqWB_fixed_Asm_16	= 319,
-	ARM_VLD4DUPqWB_fixed_Asm_32	= 320,
-	ARM_VLD4DUPqWB_fixed_Asm_8	= 321,
-	ARM_VLD4DUPqWB_register_Asm_16	= 322,
-	ARM_VLD4DUPqWB_register_Asm_32	= 323,
-	ARM_VLD4DUPqWB_register_Asm_8	= 324,
-	ARM_VLD4LNdAsm_16	= 325,
-	ARM_VLD4LNdAsm_32	= 326,
-	ARM_VLD4LNdAsm_8	= 327,
-	ARM_VLD4LNdWB_fixed_Asm_16	= 328,
-	ARM_VLD4LNdWB_fixed_Asm_32	= 329,
-	ARM_VLD4LNdWB_fixed_Asm_8	= 330,
-	ARM_VLD4LNdWB_register_Asm_16	= 331,
-	ARM_VLD4LNdWB_register_Asm_32	= 332,
-	ARM_VLD4LNdWB_register_Asm_8	= 333,
-	ARM_VLD4LNqAsm_16	= 334,
-	ARM_VLD4LNqAsm_32	= 335,
-	ARM_VLD4LNqWB_fixed_Asm_16	= 336,
-	ARM_VLD4LNqWB_fixed_Asm_32	= 337,
-	ARM_VLD4LNqWB_register_Asm_16	= 338,
-	ARM_VLD4LNqWB_register_Asm_32	= 339,
-	ARM_VLD4dAsm_16	= 340,
-	ARM_VLD4dAsm_32	= 341,
-	ARM_VLD4dAsm_8	= 342,
-	ARM_VLD4dWB_fixed_Asm_16	= 343,
-	ARM_VLD4dWB_fixed_Asm_32	= 344,
-	ARM_VLD4dWB_fixed_Asm_8	= 345,
-	ARM_VLD4dWB_register_Asm_16	= 346,
-	ARM_VLD4dWB_register_Asm_32	= 347,
-	ARM_VLD4dWB_register_Asm_8	= 348,
-	ARM_VLD4qAsm_16	= 349,
-	ARM_VLD4qAsm_32	= 350,
-	ARM_VLD4qAsm_8	= 351,
-	ARM_VLD4qWB_fixed_Asm_16	= 352,
-	ARM_VLD4qWB_fixed_Asm_32	= 353,
-	ARM_VLD4qWB_fixed_Asm_8	= 354,
-	ARM_VLD4qWB_register_Asm_16	= 355,
-	ARM_VLD4qWB_register_Asm_32	= 356,
-	ARM_VLD4qWB_register_Asm_8	= 357,
-	ARM_VMOVD0	= 358,
-	ARM_VMOVDcc	= 359,
-	ARM_VMOVQ0	= 360,
-	ARM_VMOVScc	= 361,
-	ARM_VST1LNdAsm_16	= 362,
-	ARM_VST1LNdAsm_32	= 363,
-	ARM_VST1LNdAsm_8	= 364,
-	ARM_VST1LNdWB_fixed_Asm_16	= 365,
-	ARM_VST1LNdWB_fixed_Asm_32	= 366,
-	ARM_VST1LNdWB_fixed_Asm_8	= 367,
-	ARM_VST1LNdWB_register_Asm_16	= 368,
-	ARM_VST1LNdWB_register_Asm_32	= 369,
-	ARM_VST1LNdWB_register_Asm_8	= 370,
-	ARM_VST2LNdAsm_16	= 371,
-	ARM_VST2LNdAsm_32	= 372,
-	ARM_VST2LNdAsm_8	= 373,
-	ARM_VST2LNdWB_fixed_Asm_16	= 374,
-	ARM_VST2LNdWB_fixed_Asm_32	= 375,
-	ARM_VST2LNdWB_fixed_Asm_8	= 376,
-	ARM_VST2LNdWB_register_Asm_16	= 377,
-	ARM_VST2LNdWB_register_Asm_32	= 378,
-	ARM_VST2LNdWB_register_Asm_8	= 379,
-	ARM_VST2LNqAsm_16	= 380,
-	ARM_VST2LNqAsm_32	= 381,
-	ARM_VST2LNqWB_fixed_Asm_16	= 382,
-	ARM_VST2LNqWB_fixed_Asm_32	= 383,
-	ARM_VST2LNqWB_register_Asm_16	= 384,
-	ARM_VST2LNqWB_register_Asm_32	= 385,
-	ARM_VST3LNdAsm_16	= 386,
-	ARM_VST3LNdAsm_32	= 387,
-	ARM_VST3LNdAsm_8	= 388,
-	ARM_VST3LNdWB_fixed_Asm_16	= 389,
-	ARM_VST3LNdWB_fixed_Asm_32	= 390,
-	ARM_VST3LNdWB_fixed_Asm_8	= 391,
-	ARM_VST3LNdWB_register_Asm_16	= 392,
-	ARM_VST3LNdWB_register_Asm_32	= 393,
-	ARM_VST3LNdWB_register_Asm_8	= 394,
-	ARM_VST3LNqAsm_16	= 395,
-	ARM_VST3LNqAsm_32	= 396,
-	ARM_VST3LNqWB_fixed_Asm_16	= 397,
-	ARM_VST3LNqWB_fixed_Asm_32	= 398,
-	ARM_VST3LNqWB_register_Asm_16	= 399,
-	ARM_VST3LNqWB_register_Asm_32	= 400,
-	ARM_VST3dAsm_16	= 401,
-	ARM_VST3dAsm_32	= 402,
-	ARM_VST3dAsm_8	= 403,
-	ARM_VST3dWB_fixed_Asm_16	= 404,
-	ARM_VST3dWB_fixed_Asm_32	= 405,
-	ARM_VST3dWB_fixed_Asm_8	= 406,
-	ARM_VST3dWB_register_Asm_16	= 407,
-	ARM_VST3dWB_register_Asm_32	= 408,
-	ARM_VST3dWB_register_Asm_8	= 409,
-	ARM_VST3qAsm_16	= 410,
-	ARM_VST3qAsm_32	= 411,
-	ARM_VST3qAsm_8	= 412,
-	ARM_VST3qWB_fixed_Asm_16	= 413,
-	ARM_VST3qWB_fixed_Asm_32	= 414,
-	ARM_VST3qWB_fixed_Asm_8	= 415,
-	ARM_VST3qWB_register_Asm_16	= 416,
-	ARM_VST3qWB_register_Asm_32	= 417,
-	ARM_VST3qWB_register_Asm_8	= 418,
-	ARM_VST4LNdAsm_16	= 419,
-	ARM_VST4LNdAsm_32	= 420,
-	ARM_VST4LNdAsm_8	= 421,
-	ARM_VST4LNdWB_fixed_Asm_16	= 422,
-	ARM_VST4LNdWB_fixed_Asm_32	= 423,
-	ARM_VST4LNdWB_fixed_Asm_8	= 424,
-	ARM_VST4LNdWB_register_Asm_16	= 425,
-	ARM_VST4LNdWB_register_Asm_32	= 426,
-	ARM_VST4LNdWB_register_Asm_8	= 427,
-	ARM_VST4LNqAsm_16	= 428,
-	ARM_VST4LNqAsm_32	= 429,
-	ARM_VST4LNqWB_fixed_Asm_16	= 430,
-	ARM_VST4LNqWB_fixed_Asm_32	= 431,
-	ARM_VST4LNqWB_register_Asm_16	= 432,
-	ARM_VST4LNqWB_register_Asm_32	= 433,
-	ARM_VST4dAsm_16	= 434,
-	ARM_VST4dAsm_32	= 435,
-	ARM_VST4dAsm_8	= 436,
-	ARM_VST4dWB_fixed_Asm_16	= 437,
-	ARM_VST4dWB_fixed_Asm_32	= 438,
-	ARM_VST4dWB_fixed_Asm_8	= 439,
-	ARM_VST4dWB_register_Asm_16	= 440,
-	ARM_VST4dWB_register_Asm_32	= 441,
-	ARM_VST4dWB_register_Asm_8	= 442,
-	ARM_VST4qAsm_16	= 443,
-	ARM_VST4qAsm_32	= 444,
-	ARM_VST4qAsm_8	= 445,
-	ARM_VST4qWB_fixed_Asm_16	= 446,
-	ARM_VST4qWB_fixed_Asm_32	= 447,
-	ARM_VST4qWB_fixed_Asm_8	= 448,
-	ARM_VST4qWB_register_Asm_16	= 449,
-	ARM_VST4qWB_register_Asm_32	= 450,
-	ARM_VST4qWB_register_Asm_8	= 451,
-	ARM_t2ABS	= 454,
-	ARM_t2ADDSri	= 455,
-	ARM_t2ADDSrr	= 456,
-	ARM_t2ADDSrs	= 457,
-	ARM_t2BR_JT	= 458,
-	ARM_t2LDMIA_RET	= 459,
-	ARM_t2LDRBpcrel	= 460,
-	ARM_t2LDRConstPool	= 461,
-	ARM_t2LDRHpcrel	= 462,
-	ARM_t2LDRSBpcrel	= 463,
-	ARM_t2LDRSHpcrel	= 464,
-	ARM_t2LDRpci_pic	= 465,
-	ARM_t2LDRpcrel	= 466,
-	ARM_t2LEApcrel	= 467,
-	ARM_t2LEApcrelJT	= 468,
-	ARM_t2MOVCCasr	= 469,
-	ARM_t2MOVCCi	= 470,
-	ARM_t2MOVCCi16	= 471,
-	ARM_t2MOVCCi32imm	= 472,
-	ARM_t2MOVCClsl	= 473,
-	ARM_t2MOVCClsr	= 474,
-	ARM_t2MOVCCr	= 475,
-	ARM_t2MOVCCror	= 476,
-	ARM_t2MOVSsi	= 477,
-	ARM_t2MOVSsr	= 478,
-	ARM_t2MOVTi16_ga_pcrel	= 479,
-	ARM_t2MOV_ga_pcrel	= 480,
-	ARM_t2MOVi16_ga_pcrel	= 481,
-	ARM_t2MOVi32imm	= 482,
-	ARM_t2MOVsi	= 483,
-	ARM_t2MOVsr	= 484,
-	ARM_t2MVNCCi	= 485,
-	ARM_t2RSBSri	= 486,
-	ARM_t2RSBSrs	= 487,
-	ARM_t2STRB_preidx	= 488,
-	ARM_t2STRH_preidx	= 489,
-	ARM_t2STR_preidx	= 490,
-	ARM_t2SUBSri	= 491,
-	ARM_t2SUBSrr	= 492,
-	ARM_t2SUBSrs	= 493,
-	ARM_t2TBB_JT	= 494,
-	ARM_t2TBH_JT	= 495,
-	ARM_tADCS	= 496,
-	ARM_tADDSi3	= 497,
-	ARM_tADDSi8	= 498,
-	ARM_tADDSrr	= 499,
-	ARM_tADDframe	= 500,
-	ARM_tADJCALLSTACKDOWN	= 501,
-	ARM_tADJCALLSTACKUP	= 502,
-	ARM_tBRIND	= 503,
-	ARM_tBR_JTr	= 504,
-	ARM_tBX_CALL	= 505,
-	ARM_tBX_RET	= 506,
-	ARM_tBX_RET_vararg	= 507,
-	ARM_tBfar	= 508,
-	ARM_tLDMIA_UPD	= 509,
-	ARM_tLDRConstPool	= 510,
-	ARM_tLDRLIT_ga_abs	= 511,
-	ARM_tLDRLIT_ga_pcrel	= 512,
-	ARM_tLDR_postidx	= 513,
-	ARM_tLDRpci_pic	= 514,
-	ARM_tLEApcrel	= 515,
-	ARM_tLEApcrelJT	= 516,
-	ARM_tMOVCCr_pseudo	= 517,
-	ARM_tPOP_RET	= 518,
-	ARM_tSBCS	= 519,
-	ARM_tSUBSi3	= 520,
-	ARM_tSUBSi8	= 521,
-	ARM_tSUBSrr	= 522,
-	ARM_tTAILJMPd	= 523,
-	ARM_tTAILJMPdND	= 524,
-	ARM_tTAILJMPr	= 525,
-	ARM_tTBB_JT	= 526,
-	ARM_tTBH_JT	= 527,
-	ARM_tTPsoft	= 528,
-	ARM_ADCri	= 529,
-	ARM_ADCrr	= 530,
-	ARM_ADCrsi	= 531,
-	ARM_ADCrsr	= 532,
-	ARM_ADDri	= 533,
-	ARM_ADDrr	= 534,
-	ARM_ADDrsi	= 535,
-	ARM_ADDrsr	= 536,
-	ARM_ADR	= 537,
-	ARM_AESD	= 538,
-	ARM_AESE	= 539,
-	ARM_AESIMC	= 540,
-	ARM_AESMC	= 541,
-	ARM_ANDri	= 542,
-	ARM_ANDrr	= 543,
-	ARM_ANDrsi	= 544,
-	ARM_ANDrsr	= 545,
-	ARM_BFC	= 546,
-	ARM_BFI	= 547,
-	ARM_BICri	= 548,
-	ARM_BICrr	= 549,
-	ARM_BICrsi	= 550,
-	ARM_BICrsr	= 551,
-	ARM_BKPT	= 552,
-	ARM_BL	= 553,
-	ARM_BLX	= 554,
-	ARM_BLX_pred	= 555,
-	ARM_BLXi	= 556,
-	ARM_BL_pred	= 557,
-	ARM_BX	= 558,
-	ARM_BXJ	= 559,
-	ARM_BX_RET	= 560,
-	ARM_BX_pred	= 561,
-	ARM_Bcc	= 562,
-	ARM_CDP	= 563,
-	ARM_CDP2	= 564,
-	ARM_CLREX	= 565,
-	ARM_CLZ	= 566,
-	ARM_CMNri	= 567,
-	ARM_CMNzrr	= 568,
-	ARM_CMNzrsi	= 569,
-	ARM_CMNzrsr	= 570,
-	ARM_CMPri	= 571,
-	ARM_CMPrr	= 572,
-	ARM_CMPrsi	= 573,
-	ARM_CMPrsr	= 574,
-	ARM_CPS1p	= 575,
-	ARM_CPS2p	= 576,
-	ARM_CPS3p	= 577,
-	ARM_CRC32B	= 578,
-	ARM_CRC32CB	= 579,
-	ARM_CRC32CH	= 580,
-	ARM_CRC32CW	= 581,
-	ARM_CRC32H	= 582,
-	ARM_CRC32W	= 583,
-	ARM_DBG	= 584,
-	ARM_DMB	= 585,
-	ARM_DSB	= 586,
-	ARM_EORri	= 587,
-	ARM_EORrr	= 588,
-	ARM_EORrsi	= 589,
-	ARM_EORrsr	= 590,
-	ARM_ERET	= 591,
-	ARM_FCONSTD	= 592,
-	ARM_FCONSTH	= 593,
-	ARM_FCONSTS	= 594,
-	ARM_FLDMXDB_UPD	= 595,
-	ARM_FLDMXIA	= 596,
-	ARM_FLDMXIA_UPD	= 597,
-	ARM_FMSTAT	= 598,
-	ARM_FSTMXDB_UPD	= 599,
-	ARM_FSTMXIA	= 600,
-	ARM_FSTMXIA_UPD	= 601,
-	ARM_HINT	= 602,
-	ARM_HLT	= 603,
-	ARM_HVC	= 604,
-	ARM_ISB	= 605,
-	ARM_LDA	= 606,
-	ARM_LDAB	= 607,
-	ARM_LDAEX	= 608,
-	ARM_LDAEXB	= 609,
-	ARM_LDAEXD	= 610,
-	ARM_LDAEXH	= 611,
-	ARM_LDAH	= 612,
-	ARM_LDC2L_OFFSET	= 613,
-	ARM_LDC2L_OPTION	= 614,
-	ARM_LDC2L_POST	= 615,
-	ARM_LDC2L_PRE	= 616,
-	ARM_LDC2_OFFSET	= 617,
-	ARM_LDC2_OPTION	= 618,
-	ARM_LDC2_POST	= 619,
-	ARM_LDC2_PRE	= 620,
-	ARM_LDCL_OFFSET	= 621,
-	ARM_LDCL_OPTION	= 622,
-	ARM_LDCL_POST	= 623,
-	ARM_LDCL_PRE	= 624,
-	ARM_LDC_OFFSET	= 625,
-	ARM_LDC_OPTION	= 626,
-	ARM_LDC_POST	= 627,
-	ARM_LDC_PRE	= 628,
-	ARM_LDMDA	= 629,
-	ARM_LDMDA_UPD	= 630,
-	ARM_LDMDB	= 631,
-	ARM_LDMDB_UPD	= 632,
-	ARM_LDMIA	= 633,
-	ARM_LDMIA_UPD	= 634,
-	ARM_LDMIB	= 635,
-	ARM_LDMIB_UPD	= 636,
-	ARM_LDRBT_POST_IMM	= 637,
-	ARM_LDRBT_POST_REG	= 638,
-	ARM_LDRB_POST_IMM	= 639,
-	ARM_LDRB_POST_REG	= 640,
-	ARM_LDRB_PRE_IMM	= 641,
-	ARM_LDRB_PRE_REG	= 642,
-	ARM_LDRBi12	= 643,
-	ARM_LDRBrs	= 644,
-	ARM_LDRD	= 645,
-	ARM_LDRD_POST	= 646,
-	ARM_LDRD_PRE	= 647,
-	ARM_LDREX	= 648,
-	ARM_LDREXB	= 649,
-	ARM_LDREXD	= 650,
-	ARM_LDREXH	= 651,
-	ARM_LDRH	= 652,
-	ARM_LDRHTi	= 653,
-	ARM_LDRHTr	= 654,
-	ARM_LDRH_POST	= 655,
-	ARM_LDRH_PRE	= 656,
-	ARM_LDRSB	= 657,
-	ARM_LDRSBTi	= 658,
-	ARM_LDRSBTr	= 659,
-	ARM_LDRSB_POST	= 660,
-	ARM_LDRSB_PRE	= 661,
-	ARM_LDRSH	= 662,
-	ARM_LDRSHTi	= 663,
-	ARM_LDRSHTr	= 664,
-	ARM_LDRSH_POST	= 665,
-	ARM_LDRSH_PRE	= 666,
-	ARM_LDRT_POST_IMM	= 667,
-	ARM_LDRT_POST_REG	= 668,
-	ARM_LDR_POST_IMM	= 669,
-	ARM_LDR_POST_REG	= 670,
-	ARM_LDR_PRE_IMM	= 671,
-	ARM_LDR_PRE_REG	= 672,
-	ARM_LDRcp	= 673,
-	ARM_LDRi12	= 674,
-	ARM_LDRrs	= 675,
-	ARM_MCR	= 676,
-	ARM_MCR2	= 677,
-	ARM_MCRR	= 678,
-	ARM_MCRR2	= 679,
-	ARM_MLA	= 680,
-	ARM_MLS	= 681,
-	ARM_MOVPCLR	= 682,
-	ARM_MOVTi16	= 683,
-	ARM_MOVi	= 684,
-	ARM_MOVi16	= 685,
-	ARM_MOVr	= 686,
-	ARM_MOVr_TC	= 687,
-	ARM_MOVsi	= 688,
-	ARM_MOVsr	= 689,
-	ARM_MRC	= 690,
-	ARM_MRC2	= 691,
-	ARM_MRRC	= 692,
-	ARM_MRRC2	= 693,
-	ARM_MRS	= 694,
-	ARM_MRSbanked	= 695,
-	ARM_MRSsys	= 696,
-	ARM_MSR	= 697,
-	ARM_MSRbanked	= 698,
-	ARM_MSRi	= 699,
-	ARM_MUL	= 700,
-	ARM_MVNi	= 701,
-	ARM_MVNr	= 702,
-	ARM_MVNsi	= 703,
-	ARM_MVNsr	= 704,
-	ARM_ORRri	= 705,
-	ARM_ORRrr	= 706,
-	ARM_ORRrsi	= 707,
-	ARM_ORRrsr	= 708,
-	ARM_PKHBT	= 709,
-	ARM_PKHTB	= 710,
-	ARM_PLDWi12	= 711,
-	ARM_PLDWrs	= 712,
-	ARM_PLDi12	= 713,
-	ARM_PLDrs	= 714,
-	ARM_PLIi12	= 715,
-	ARM_PLIrs	= 716,
-	ARM_QADD	= 717,
-	ARM_QADD16	= 718,
-	ARM_QADD8	= 719,
-	ARM_QASX	= 720,
-	ARM_QDADD	= 721,
-	ARM_QDSUB	= 722,
-	ARM_QSAX	= 723,
-	ARM_QSUB	= 724,
-	ARM_QSUB16	= 725,
-	ARM_QSUB8	= 726,
-	ARM_RBIT	= 727,
-	ARM_REV	= 728,
-	ARM_REV16	= 729,
-	ARM_REVSH	= 730,
-	ARM_RFEDA	= 731,
-	ARM_RFEDA_UPD	= 732,
-	ARM_RFEDB	= 733,
-	ARM_RFEDB_UPD	= 734,
-	ARM_RFEIA	= 735,
-	ARM_RFEIA_UPD	= 736,
-	ARM_RFEIB	= 737,
-	ARM_RFEIB_UPD	= 738,
-	ARM_RSBri	= 739,
-	ARM_RSBrr	= 740,
-	ARM_RSBrsi	= 741,
-	ARM_RSBrsr	= 742,
-	ARM_RSCri	= 743,
-	ARM_RSCrr	= 744,
-	ARM_RSCrsi	= 745,
-	ARM_RSCrsr	= 746,
-	ARM_SADD16	= 747,
-	ARM_SADD8	= 748,
-	ARM_SASX	= 749,
-	ARM_SBCri	= 750,
-	ARM_SBCrr	= 751,
-	ARM_SBCrsi	= 752,
-	ARM_SBCrsr	= 753,
-	ARM_SBFX	= 754,
-	ARM_SDIV	= 755,
-	ARM_SEL	= 756,
-	ARM_SETEND	= 757,
-	ARM_SETPAN	= 758,
-	ARM_SHA1C	= 759,
-	ARM_SHA1H	= 760,
-	ARM_SHA1M	= 761,
-	ARM_SHA1P	= 762,
-	ARM_SHA1SU0	= 763,
-	ARM_SHA1SU1	= 764,
-	ARM_SHA256H	= 765,
-	ARM_SHA256H2	= 766,
-	ARM_SHA256SU0	= 767,
-	ARM_SHA256SU1	= 768,
-	ARM_SHADD16	= 769,
-	ARM_SHADD8	= 770,
-	ARM_SHASX	= 771,
-	ARM_SHSAX	= 772,
-	ARM_SHSUB16	= 773,
-	ARM_SHSUB8	= 774,
-	ARM_SMC	= 775,
-	ARM_SMLABB	= 776,
-	ARM_SMLABT	= 777,
-	ARM_SMLAD	= 778,
-	ARM_SMLADX	= 779,
-	ARM_SMLAL	= 780,
-	ARM_SMLALBB	= 781,
-	ARM_SMLALBT	= 782,
-	ARM_SMLALD	= 783,
-	ARM_SMLALDX	= 784,
-	ARM_SMLALTB	= 785,
-	ARM_SMLALTT	= 786,
-	ARM_SMLATB	= 787,
-	ARM_SMLATT	= 788,
-	ARM_SMLAWB	= 789,
-	ARM_SMLAWT	= 790,
-	ARM_SMLSD	= 791,
-	ARM_SMLSDX	= 792,
-	ARM_SMLSLD	= 793,
-	ARM_SMLSLDX	= 794,
-	ARM_SMMLA	= 795,
-	ARM_SMMLAR	= 796,
-	ARM_SMMLS	= 797,
-	ARM_SMMLSR	= 798,
-	ARM_SMMUL	= 799,
-	ARM_SMMULR	= 800,
-	ARM_SMUAD	= 801,
-	ARM_SMUADX	= 802,
-	ARM_SMULBB	= 803,
-	ARM_SMULBT	= 804,
-	ARM_SMULL	= 805,
-	ARM_SMULTB	= 806,
-	ARM_SMULTT	= 807,
-	ARM_SMULWB	= 808,
-	ARM_SMULWT	= 809,
-	ARM_SMUSD	= 810,
-	ARM_SMUSDX	= 811,
-	ARM_SRSDA	= 812,
-	ARM_SRSDA_UPD	= 813,
-	ARM_SRSDB	= 814,
-	ARM_SRSDB_UPD	= 815,
-	ARM_SRSIA	= 816,
-	ARM_SRSIA_UPD	= 817,
-	ARM_SRSIB	= 818,
-	ARM_SRSIB_UPD	= 819,
-	ARM_SSAT	= 820,
-	ARM_SSAT16	= 821,
-	ARM_SSAX	= 822,
-	ARM_SSUB16	= 823,
-	ARM_SSUB8	= 824,
-	ARM_STC2L_OFFSET	= 825,
-	ARM_STC2L_OPTION	= 826,
-	ARM_STC2L_POST	= 827,
-	ARM_STC2L_PRE	= 828,
-	ARM_STC2_OFFSET	= 829,
-	ARM_STC2_OPTION	= 830,
-	ARM_STC2_POST	= 831,
-	ARM_STC2_PRE	= 832,
-	ARM_STCL_OFFSET	= 833,
-	ARM_STCL_OPTION	= 834,
-	ARM_STCL_POST	= 835,
-	ARM_STCL_PRE	= 836,
-	ARM_STC_OFFSET	= 837,
-	ARM_STC_OPTION	= 838,
-	ARM_STC_POST	= 839,
-	ARM_STC_PRE	= 840,
-	ARM_STL	= 841,
-	ARM_STLB	= 842,
-	ARM_STLEX	= 843,
-	ARM_STLEXB	= 844,
-	ARM_STLEXD	= 845,
-	ARM_STLEXH	= 846,
-	ARM_STLH	= 847,
-	ARM_STMDA	= 848,
-	ARM_STMDA_UPD	= 849,
-	ARM_STMDB	= 850,
-	ARM_STMDB_UPD	= 851,
-	ARM_STMIA	= 852,
-	ARM_STMIA_UPD	= 853,
-	ARM_STMIB	= 854,
-	ARM_STMIB_UPD	= 855,
-	ARM_STRBT_POST_IMM	= 856,
-	ARM_STRBT_POST_REG	= 857,
-	ARM_STRB_POST_IMM	= 858,
-	ARM_STRB_POST_REG	= 859,
-	ARM_STRB_PRE_IMM	= 860,
-	ARM_STRB_PRE_REG	= 861,
-	ARM_STRBi12	= 862,
-	ARM_STRBrs	= 863,
-	ARM_STRD	= 864,
-	ARM_STRD_POST	= 865,
-	ARM_STRD_PRE	= 866,
-	ARM_STREX	= 867,
-	ARM_STREXB	= 868,
-	ARM_STREXD	= 869,
-	ARM_STREXH	= 870,
-	ARM_STRH	= 871,
-	ARM_STRHTi	= 872,
-	ARM_STRHTr	= 873,
-	ARM_STRH_POST	= 874,
-	ARM_STRH_PRE	= 875,
-	ARM_STRT_POST_IMM	= 876,
-	ARM_STRT_POST_REG	= 877,
-	ARM_STR_POST_IMM	= 878,
-	ARM_STR_POST_REG	= 879,
-	ARM_STR_PRE_IMM	= 880,
-	ARM_STR_PRE_REG	= 881,
-	ARM_STRi12	= 882,
-	ARM_STRrs	= 883,
-	ARM_SUBri	= 884,
-	ARM_SUBrr	= 885,
-	ARM_SUBrsi	= 886,
-	ARM_SUBrsr	= 887,
-	ARM_SVC	= 888,
-	ARM_SWP	= 889,
-	ARM_SWPB	= 890,
-	ARM_SXTAB	= 891,
-	ARM_SXTAB16	= 892,
-	ARM_SXTAH	= 893,
-	ARM_SXTB	= 894,
-	ARM_SXTB16	= 895,
-	ARM_SXTH	= 896,
-	ARM_TEQri	= 897,
-	ARM_TEQrr	= 898,
-	ARM_TEQrsi	= 899,
-	ARM_TEQrsr	= 900,
-	ARM_TRAP	= 901,
-	ARM_TRAPNaCl	= 902,
-	ARM_TSB	= 903,
-	ARM_TSTri	= 904,
-	ARM_TSTrr	= 905,
-	ARM_TSTrsi	= 906,
-	ARM_TSTrsr	= 907,
-	ARM_UADD16	= 908,
-	ARM_UADD8	= 909,
-	ARM_UASX	= 910,
-	ARM_UBFX	= 911,
-	ARM_UDF	= 912,
-	ARM_UDIV	= 913,
-	ARM_UHADD16	= 914,
-	ARM_UHADD8	= 915,
-	ARM_UHASX	= 916,
-	ARM_UHSAX	= 917,
-	ARM_UHSUB16	= 918,
-	ARM_UHSUB8	= 919,
-	ARM_UMAAL	= 920,
-	ARM_UMLAL	= 921,
-	ARM_UMULL	= 922,
-	ARM_UQADD16	= 923,
-	ARM_UQADD8	= 924,
-	ARM_UQASX	= 925,
-	ARM_UQSAX	= 926,
-	ARM_UQSUB16	= 927,
-	ARM_UQSUB8	= 928,
-	ARM_USAD8	= 929,
-	ARM_USADA8	= 930,
-	ARM_USAT	= 931,
-	ARM_USAT16	= 932,
-	ARM_USAX	= 933,
-	ARM_USUB16	= 934,
-	ARM_USUB8	= 935,
-	ARM_UXTAB	= 936,
-	ARM_UXTAB16	= 937,
-	ARM_UXTAH	= 938,
-	ARM_UXTB	= 939,
-	ARM_UXTB16	= 940,
-	ARM_UXTH	= 941,
-	ARM_VABALsv2i64	= 942,
-	ARM_VABALsv4i32	= 943,
-	ARM_VABALsv8i16	= 944,
-	ARM_VABALuv2i64	= 945,
-	ARM_VABALuv4i32	= 946,
-	ARM_VABALuv8i16	= 947,
-	ARM_VABAsv16i8	= 948,
-	ARM_VABAsv2i32	= 949,
-	ARM_VABAsv4i16	= 950,
-	ARM_VABAsv4i32	= 951,
-	ARM_VABAsv8i16	= 952,
-	ARM_VABAsv8i8	= 953,
-	ARM_VABAuv16i8	= 954,
-	ARM_VABAuv2i32	= 955,
-	ARM_VABAuv4i16	= 956,
-	ARM_VABAuv4i32	= 957,
-	ARM_VABAuv8i16	= 958,
-	ARM_VABAuv8i8	= 959,
-	ARM_VABDLsv2i64	= 960,
-	ARM_VABDLsv4i32	= 961,
-	ARM_VABDLsv8i16	= 962,
-	ARM_VABDLuv2i64	= 963,
-	ARM_VABDLuv4i32	= 964,
-	ARM_VABDLuv8i16	= 965,
-	ARM_VABDfd	= 966,
-	ARM_VABDfq	= 967,
-	ARM_VABDhd	= 968,
-	ARM_VABDhq	= 969,
-	ARM_VABDsv16i8	= 970,
-	ARM_VABDsv2i32	= 971,
-	ARM_VABDsv4i16	= 972,
-	ARM_VABDsv4i32	= 973,
-	ARM_VABDsv8i16	= 974,
-	ARM_VABDsv8i8	= 975,
-	ARM_VABDuv16i8	= 976,
-	ARM_VABDuv2i32	= 977,
-	ARM_VABDuv4i16	= 978,
-	ARM_VABDuv4i32	= 979,
-	ARM_VABDuv8i16	= 980,
-	ARM_VABDuv8i8	= 981,
-	ARM_VABSD	= 982,
-	ARM_VABSH	= 983,
-	ARM_VABSS	= 984,
-	ARM_VABSfd	= 985,
-	ARM_VABSfq	= 986,
-	ARM_VABShd	= 987,
-	ARM_VABShq	= 988,
-	ARM_VABSv16i8	= 989,
-	ARM_VABSv2i32	= 990,
-	ARM_VABSv4i16	= 991,
-	ARM_VABSv4i32	= 992,
-	ARM_VABSv8i16	= 993,
-	ARM_VABSv8i8	= 994,
-	ARM_VACGEfd	= 995,
-	ARM_VACGEfq	= 996,
-	ARM_VACGEhd	= 997,
-	ARM_VACGEhq	= 998,
-	ARM_VACGTfd	= 999,
-	ARM_VACGTfq	= 1000,
-	ARM_VACGThd	= 1001,
-	ARM_VACGThq	= 1002,
-	ARM_VADDD	= 1003,
-	ARM_VADDH	= 1004,
-	ARM_VADDHNv2i32	= 1005,
-	ARM_VADDHNv4i16	= 1006,
-	ARM_VADDHNv8i8	= 1007,
-	ARM_VADDLsv2i64	= 1008,
-	ARM_VADDLsv4i32	= 1009,
-	ARM_VADDLsv8i16	= 1010,
-	ARM_VADDLuv2i64	= 1011,
-	ARM_VADDLuv4i32	= 1012,
-	ARM_VADDLuv8i16	= 1013,
-	ARM_VADDS	= 1014,
-	ARM_VADDWsv2i64	= 1015,
-	ARM_VADDWsv4i32	= 1016,
-	ARM_VADDWsv8i16	= 1017,
-	ARM_VADDWuv2i64	= 1018,
-	ARM_VADDWuv4i32	= 1019,
-	ARM_VADDWuv8i16	= 1020,
-	ARM_VADDfd	= 1021,
-	ARM_VADDfq	= 1022,
-	ARM_VADDhd	= 1023,
-	ARM_VADDhq	= 1024,
-	ARM_VADDv16i8	= 1025,
-	ARM_VADDv1i64	= 1026,
-	ARM_VADDv2i32	= 1027,
-	ARM_VADDv2i64	= 1028,
-	ARM_VADDv4i16	= 1029,
-	ARM_VADDv4i32	= 1030,
-	ARM_VADDv8i16	= 1031,
-	ARM_VADDv8i8	= 1032,
-	ARM_VANDd	= 1033,
-	ARM_VANDq	= 1034,
-	ARM_VBICd	= 1035,
-	ARM_VBICiv2i32	= 1036,
-	ARM_VBICiv4i16	= 1037,
-	ARM_VBICiv4i32	= 1038,
-	ARM_VBICiv8i16	= 1039,
-	ARM_VBICq	= 1040,
-	ARM_VBIFd	= 1041,
-	ARM_VBIFq	= 1042,
-	ARM_VBITd	= 1043,
-	ARM_VBITq	= 1044,
-	ARM_VBSLd	= 1045,
-	ARM_VBSLq	= 1046,
-	ARM_VCADDv2f32	= 1047,
-	ARM_VCADDv4f16	= 1048,
-	ARM_VCADDv4f32	= 1049,
-	ARM_VCADDv8f16	= 1050,
-	ARM_VCEQfd	= 1051,
-	ARM_VCEQfq	= 1052,
-	ARM_VCEQhd	= 1053,
-	ARM_VCEQhq	= 1054,
-	ARM_VCEQv16i8	= 1055,
-	ARM_VCEQv2i32	= 1056,
-	ARM_VCEQv4i16	= 1057,
-	ARM_VCEQv4i32	= 1058,
-	ARM_VCEQv8i16	= 1059,
-	ARM_VCEQv8i8	= 1060,
-	ARM_VCEQzv16i8	= 1061,
-	ARM_VCEQzv2f32	= 1062,
-	ARM_VCEQzv2i32	= 1063,
-	ARM_VCEQzv4f16	= 1064,
-	ARM_VCEQzv4f32	= 1065,
-	ARM_VCEQzv4i16	= 1066,
-	ARM_VCEQzv4i32	= 1067,
-	ARM_VCEQzv8f16	= 1068,
-	ARM_VCEQzv8i16	= 1069,
-	ARM_VCEQzv8i8	= 1070,
-	ARM_VCGEfd	= 1071,
-	ARM_VCGEfq	= 1072,
-	ARM_VCGEhd	= 1073,
-	ARM_VCGEhq	= 1074,
-	ARM_VCGEsv16i8	= 1075,
-	ARM_VCGEsv2i32	= 1076,
-	ARM_VCGEsv4i16	= 1077,
-	ARM_VCGEsv4i32	= 1078,
-	ARM_VCGEsv8i16	= 1079,
-	ARM_VCGEsv8i8	= 1080,
-	ARM_VCGEuv16i8	= 1081,
-	ARM_VCGEuv2i32	= 1082,
-	ARM_VCGEuv4i16	= 1083,
-	ARM_VCGEuv4i32	= 1084,
-	ARM_VCGEuv8i16	= 1085,
-	ARM_VCGEuv8i8	= 1086,
-	ARM_VCGEzv16i8	= 1087,
-	ARM_VCGEzv2f32	= 1088,
-	ARM_VCGEzv2i32	= 1089,
-	ARM_VCGEzv4f16	= 1090,
-	ARM_VCGEzv4f32	= 1091,
-	ARM_VCGEzv4i16	= 1092,
-	ARM_VCGEzv4i32	= 1093,
-	ARM_VCGEzv8f16	= 1094,
-	ARM_VCGEzv8i16	= 1095,
-	ARM_VCGEzv8i8	= 1096,
-	ARM_VCGTfd	= 1097,
-	ARM_VCGTfq	= 1098,
-	ARM_VCGThd	= 1099,
-	ARM_VCGThq	= 1100,
-	ARM_VCGTsv16i8	= 1101,
-	ARM_VCGTsv2i32	= 1102,
-	ARM_VCGTsv4i16	= 1103,
-	ARM_VCGTsv4i32	= 1104,
-	ARM_VCGTsv8i16	= 1105,
-	ARM_VCGTsv8i8	= 1106,
-	ARM_VCGTuv16i8	= 1107,
-	ARM_VCGTuv2i32	= 1108,
-	ARM_VCGTuv4i16	= 1109,
-	ARM_VCGTuv4i32	= 1110,
-	ARM_VCGTuv8i16	= 1111,
-	ARM_VCGTuv8i8	= 1112,
-	ARM_VCGTzv16i8	= 1113,
-	ARM_VCGTzv2f32	= 1114,
-	ARM_VCGTzv2i32	= 1115,
-	ARM_VCGTzv4f16	= 1116,
-	ARM_VCGTzv4f32	= 1117,
-	ARM_VCGTzv4i16	= 1118,
-	ARM_VCGTzv4i32	= 1119,
-	ARM_VCGTzv8f16	= 1120,
-	ARM_VCGTzv8i16	= 1121,
-	ARM_VCGTzv8i8	= 1122,
-	ARM_VCLEzv16i8	= 1123,
-	ARM_VCLEzv2f32	= 1124,
-	ARM_VCLEzv2i32	= 1125,
-	ARM_VCLEzv4f16	= 1126,
-	ARM_VCLEzv4f32	= 1127,
-	ARM_VCLEzv4i16	= 1128,
-	ARM_VCLEzv4i32	= 1129,
-	ARM_VCLEzv8f16	= 1130,
-	ARM_VCLEzv8i16	= 1131,
-	ARM_VCLEzv8i8	= 1132,
-	ARM_VCLSv16i8	= 1133,
-	ARM_VCLSv2i32	= 1134,
-	ARM_VCLSv4i16	= 1135,
-	ARM_VCLSv4i32	= 1136,
-	ARM_VCLSv8i16	= 1137,
-	ARM_VCLSv8i8	= 1138,
-	ARM_VCLTzv16i8	= 1139,
-	ARM_VCLTzv2f32	= 1140,
-	ARM_VCLTzv2i32	= 1141,
-	ARM_VCLTzv4f16	= 1142,
-	ARM_VCLTzv4f32	= 1143,
-	ARM_VCLTzv4i16	= 1144,
-	ARM_VCLTzv4i32	= 1145,
-	ARM_VCLTzv8f16	= 1146,
-	ARM_VCLTzv8i16	= 1147,
-	ARM_VCLTzv8i8	= 1148,
-	ARM_VCLZv16i8	= 1149,
-	ARM_VCLZv2i32	= 1150,
-	ARM_VCLZv4i16	= 1151,
-	ARM_VCLZv4i32	= 1152,
-	ARM_VCLZv8i16	= 1153,
-	ARM_VCLZv8i8	= 1154,
-	ARM_VCMLAv2f32	= 1155,
-	ARM_VCMLAv2f32_indexed	= 1156,
-	ARM_VCMLAv4f16	= 1157,
-	ARM_VCMLAv4f16_indexed	= 1158,
-	ARM_VCMLAv4f32	= 1159,
-	ARM_VCMLAv4f32_indexed	= 1160,
-	ARM_VCMLAv8f16	= 1161,
-	ARM_VCMLAv8f16_indexed	= 1162,
-	ARM_VCMPD	= 1163,
-	ARM_VCMPED	= 1164,
-	ARM_VCMPEH	= 1165,
-	ARM_VCMPES	= 1166,
-	ARM_VCMPEZD	= 1167,
-	ARM_VCMPEZH	= 1168,
-	ARM_VCMPEZS	= 1169,
-	ARM_VCMPH	= 1170,
-	ARM_VCMPS	= 1171,
-	ARM_VCMPZD	= 1172,
-	ARM_VCMPZH	= 1173,
-	ARM_VCMPZS	= 1174,
-	ARM_VCNTd	= 1175,
-	ARM_VCNTq	= 1176,
-	ARM_VCVTANSDf	= 1177,
-	ARM_VCVTANSDh	= 1178,
-	ARM_VCVTANSQf	= 1179,
-	ARM_VCVTANSQh	= 1180,
-	ARM_VCVTANUDf	= 1181,
-	ARM_VCVTANUDh	= 1182,
-	ARM_VCVTANUQf	= 1183,
-	ARM_VCVTANUQh	= 1184,
-	ARM_VCVTASD	= 1185,
-	ARM_VCVTASH	= 1186,
-	ARM_VCVTASS	= 1187,
-	ARM_VCVTAUD	= 1188,
-	ARM_VCVTAUH	= 1189,
-	ARM_VCVTAUS	= 1190,
-	ARM_VCVTBDH	= 1191,
-	ARM_VCVTBHD	= 1192,
-	ARM_VCVTBHS	= 1193,
-	ARM_VCVTBSH	= 1194,
-	ARM_VCVTDS	= 1195,
-	ARM_VCVTMNSDf	= 1196,
-	ARM_VCVTMNSDh	= 1197,
-	ARM_VCVTMNSQf	= 1198,
-	ARM_VCVTMNSQh	= 1199,
-	ARM_VCVTMNUDf	= 1200,
-	ARM_VCVTMNUDh	= 1201,
-	ARM_VCVTMNUQf	= 1202,
-	ARM_VCVTMNUQh	= 1203,
-	ARM_VCVTMSD	= 1204,
-	ARM_VCVTMSH	= 1205,
-	ARM_VCVTMSS	= 1206,
-	ARM_VCVTMUD	= 1207,
-	ARM_VCVTMUH	= 1208,
-	ARM_VCVTMUS	= 1209,
-	ARM_VCVTNNSDf	= 1210,
-	ARM_VCVTNNSDh	= 1211,
-	ARM_VCVTNNSQf	= 1212,
-	ARM_VCVTNNSQh	= 1213,
-	ARM_VCVTNNUDf	= 1214,
-	ARM_VCVTNNUDh	= 1215,
-	ARM_VCVTNNUQf	= 1216,
-	ARM_VCVTNNUQh	= 1217,
-	ARM_VCVTNSD	= 1218,
-	ARM_VCVTNSH	= 1219,
-	ARM_VCVTNSS	= 1220,
-	ARM_VCVTNUD	= 1221,
-	ARM_VCVTNUH	= 1222,
-	ARM_VCVTNUS	= 1223,
-	ARM_VCVTPNSDf	= 1224,
-	ARM_VCVTPNSDh	= 1225,
-	ARM_VCVTPNSQf	= 1226,
-	ARM_VCVTPNSQh	= 1227,
-	ARM_VCVTPNUDf	= 1228,
-	ARM_VCVTPNUDh	= 1229,
-	ARM_VCVTPNUQf	= 1230,
-	ARM_VCVTPNUQh	= 1231,
-	ARM_VCVTPSD	= 1232,
-	ARM_VCVTPSH	= 1233,
-	ARM_VCVTPSS	= 1234,
-	ARM_VCVTPUD	= 1235,
-	ARM_VCVTPUH	= 1236,
-	ARM_VCVTPUS	= 1237,
-	ARM_VCVTSD	= 1238,
-	ARM_VCVTTDH	= 1239,
-	ARM_VCVTTHD	= 1240,
-	ARM_VCVTTHS	= 1241,
-	ARM_VCVTTSH	= 1242,
-	ARM_VCVTf2h	= 1243,
-	ARM_VCVTf2sd	= 1244,
-	ARM_VCVTf2sq	= 1245,
-	ARM_VCVTf2ud	= 1246,
-	ARM_VCVTf2uq	= 1247,
-	ARM_VCVTf2xsd	= 1248,
-	ARM_VCVTf2xsq	= 1249,
-	ARM_VCVTf2xud	= 1250,
-	ARM_VCVTf2xuq	= 1251,
-	ARM_VCVTh2f	= 1252,
-	ARM_VCVTh2sd	= 1253,
-	ARM_VCVTh2sq	= 1254,
-	ARM_VCVTh2ud	= 1255,
-	ARM_VCVTh2uq	= 1256,
-	ARM_VCVTh2xsd	= 1257,
-	ARM_VCVTh2xsq	= 1258,
-	ARM_VCVTh2xud	= 1259,
-	ARM_VCVTh2xuq	= 1260,
-	ARM_VCVTs2fd	= 1261,
-	ARM_VCVTs2fq	= 1262,
-	ARM_VCVTs2hd	= 1263,
-	ARM_VCVTs2hq	= 1264,
-	ARM_VCVTu2fd	= 1265,
-	ARM_VCVTu2fq	= 1266,
-	ARM_VCVTu2hd	= 1267,
-	ARM_VCVTu2hq	= 1268,
-	ARM_VCVTxs2fd	= 1269,
-	ARM_VCVTxs2fq	= 1270,
-	ARM_VCVTxs2hd	= 1271,
-	ARM_VCVTxs2hq	= 1272,
-	ARM_VCVTxu2fd	= 1273,
-	ARM_VCVTxu2fq	= 1274,
-	ARM_VCVTxu2hd	= 1275,
-	ARM_VCVTxu2hq	= 1276,
-	ARM_VDIVD	= 1277,
-	ARM_VDIVH	= 1278,
-	ARM_VDIVS	= 1279,
-	ARM_VDUP16d	= 1280,
-	ARM_VDUP16q	= 1281,
-	ARM_VDUP32d	= 1282,
-	ARM_VDUP32q	= 1283,
-	ARM_VDUP8d	= 1284,
-	ARM_VDUP8q	= 1285,
-	ARM_VDUPLN16d	= 1286,
-	ARM_VDUPLN16q	= 1287,
-	ARM_VDUPLN32d	= 1288,
-	ARM_VDUPLN32q	= 1289,
-	ARM_VDUPLN8d	= 1290,
-	ARM_VDUPLN8q	= 1291,
-	ARM_VEORd	= 1292,
-	ARM_VEORq	= 1293,
-	ARM_VEXTd16	= 1294,
-	ARM_VEXTd32	= 1295,
-	ARM_VEXTd8	= 1296,
-	ARM_VEXTq16	= 1297,
-	ARM_VEXTq32	= 1298,
-	ARM_VEXTq64	= 1299,
-	ARM_VEXTq8	= 1300,
-	ARM_VFMAD	= 1301,
-	ARM_VFMAH	= 1302,
-	ARM_VFMAS	= 1303,
-	ARM_VFMAfd	= 1304,
-	ARM_VFMAfq	= 1305,
-	ARM_VFMAhd	= 1306,
-	ARM_VFMAhq	= 1307,
-	ARM_VFMSD	= 1308,
-	ARM_VFMSH	= 1309,
-	ARM_VFMSS	= 1310,
-	ARM_VFMSfd	= 1311,
-	ARM_VFMSfq	= 1312,
-	ARM_VFMShd	= 1313,
-	ARM_VFMShq	= 1314,
-	ARM_VFNMAD	= 1315,
-	ARM_VFNMAH	= 1316,
-	ARM_VFNMAS	= 1317,
-	ARM_VFNMSD	= 1318,
-	ARM_VFNMSH	= 1319,
-	ARM_VFNMSS	= 1320,
-	ARM_VGETLNi32	= 1321,
-	ARM_VGETLNs16	= 1322,
-	ARM_VGETLNs8	= 1323,
-	ARM_VGETLNu16	= 1324,
-	ARM_VGETLNu8	= 1325,
-	ARM_VHADDsv16i8	= 1326,
-	ARM_VHADDsv2i32	= 1327,
-	ARM_VHADDsv4i16	= 1328,
-	ARM_VHADDsv4i32	= 1329,
-	ARM_VHADDsv8i16	= 1330,
-	ARM_VHADDsv8i8	= 1331,
-	ARM_VHADDuv16i8	= 1332,
-	ARM_VHADDuv2i32	= 1333,
-	ARM_VHADDuv4i16	= 1334,
-	ARM_VHADDuv4i32	= 1335,
-	ARM_VHADDuv8i16	= 1336,
-	ARM_VHADDuv8i8	= 1337,
-	ARM_VHSUBsv16i8	= 1338,
-	ARM_VHSUBsv2i32	= 1339,
-	ARM_VHSUBsv4i16	= 1340,
-	ARM_VHSUBsv4i32	= 1341,
-	ARM_VHSUBsv8i16	= 1342,
-	ARM_VHSUBsv8i8	= 1343,
-	ARM_VHSUBuv16i8	= 1344,
-	ARM_VHSUBuv2i32	= 1345,
-	ARM_VHSUBuv4i16	= 1346,
-	ARM_VHSUBuv4i32	= 1347,
-	ARM_VHSUBuv8i16	= 1348,
-	ARM_VHSUBuv8i8	= 1349,
-	ARM_VINSH	= 1350,
-	ARM_VJCVT	= 1351,
-	ARM_VLD1DUPd16	= 1352,
-	ARM_VLD1DUPd16wb_fixed	= 1353,
-	ARM_VLD1DUPd16wb_register	= 1354,
-	ARM_VLD1DUPd32	= 1355,
-	ARM_VLD1DUPd32wb_fixed	= 1356,
-	ARM_VLD1DUPd32wb_register	= 1357,
-	ARM_VLD1DUPd8	= 1358,
-	ARM_VLD1DUPd8wb_fixed	= 1359,
-	ARM_VLD1DUPd8wb_register	= 1360,
-	ARM_VLD1DUPq16	= 1361,
-	ARM_VLD1DUPq16wb_fixed	= 1362,
-	ARM_VLD1DUPq16wb_register	= 1363,
-	ARM_VLD1DUPq32	= 1364,
-	ARM_VLD1DUPq32wb_fixed	= 1365,
-	ARM_VLD1DUPq32wb_register	= 1366,
-	ARM_VLD1DUPq8	= 1367,
-	ARM_VLD1DUPq8wb_fixed	= 1368,
-	ARM_VLD1DUPq8wb_register	= 1369,
-	ARM_VLD1LNd16	= 1370,
-	ARM_VLD1LNd16_UPD	= 1371,
-	ARM_VLD1LNd32	= 1372,
-	ARM_VLD1LNd32_UPD	= 1373,
-	ARM_VLD1LNd8	= 1374,
-	ARM_VLD1LNd8_UPD	= 1375,
-	ARM_VLD1d16	= 1382,
-	ARM_VLD1d16Q	= 1383,
-	ARM_VLD1d16Qwb_fixed	= 1385,
-	ARM_VLD1d16Qwb_register	= 1386,
-	ARM_VLD1d16T	= 1387,
-	ARM_VLD1d16Twb_fixed	= 1389,
-	ARM_VLD1d16Twb_register	= 1390,
-	ARM_VLD1d16wb_fixed	= 1391,
-	ARM_VLD1d16wb_register	= 1392,
-	ARM_VLD1d32	= 1393,
-	ARM_VLD1d32Q	= 1394,
-	ARM_VLD1d32Qwb_fixed	= 1396,
-	ARM_VLD1d32Qwb_register	= 1397,
-	ARM_VLD1d32T	= 1398,
-	ARM_VLD1d32Twb_fixed	= 1400,
-	ARM_VLD1d32Twb_register	= 1401,
-	ARM_VLD1d32wb_fixed	= 1402,
-	ARM_VLD1d32wb_register	= 1403,
-	ARM_VLD1d64	= 1404,
-	ARM_VLD1d64Q	= 1405,
-	ARM_VLD1d64Qwb_fixed	= 1409,
-	ARM_VLD1d64Qwb_register	= 1410,
-	ARM_VLD1d64T	= 1411,
-	ARM_VLD1d64Twb_fixed	= 1415,
-	ARM_VLD1d64Twb_register	= 1416,
-	ARM_VLD1d64wb_fixed	= 1417,
-	ARM_VLD1d64wb_register	= 1418,
-	ARM_VLD1d8	= 1419,
-	ARM_VLD1d8Q	= 1420,
-	ARM_VLD1d8Qwb_fixed	= 1422,
-	ARM_VLD1d8Qwb_register	= 1423,
-	ARM_VLD1d8T	= 1424,
-	ARM_VLD1d8Twb_fixed	= 1426,
-	ARM_VLD1d8Twb_register	= 1427,
-	ARM_VLD1d8wb_fixed	= 1428,
-	ARM_VLD1d8wb_register	= 1429,
-	ARM_VLD1q16	= 1430,
-	ARM_VLD1q16wb_fixed	= 1435,
-	ARM_VLD1q16wb_register	= 1436,
-	ARM_VLD1q32	= 1437,
-	ARM_VLD1q32wb_fixed	= 1442,
-	ARM_VLD1q32wb_register	= 1443,
-	ARM_VLD1q64	= 1444,
-	ARM_VLD1q64wb_fixed	= 1449,
-	ARM_VLD1q64wb_register	= 1450,
-	ARM_VLD1q8	= 1451,
-	ARM_VLD1q8wb_fixed	= 1456,
-	ARM_VLD1q8wb_register	= 1457,
-	ARM_VLD2DUPd16	= 1458,
-	ARM_VLD2DUPd16wb_fixed	= 1459,
-	ARM_VLD2DUPd16wb_register	= 1460,
-	ARM_VLD2DUPd16x2	= 1461,
-	ARM_VLD2DUPd16x2wb_fixed	= 1462,
-	ARM_VLD2DUPd16x2wb_register	= 1463,
-	ARM_VLD2DUPd32	= 1464,
-	ARM_VLD2DUPd32wb_fixed	= 1465,
-	ARM_VLD2DUPd32wb_register	= 1466,
-	ARM_VLD2DUPd32x2	= 1467,
-	ARM_VLD2DUPd32x2wb_fixed	= 1468,
-	ARM_VLD2DUPd32x2wb_register	= 1469,
-	ARM_VLD2DUPd8	= 1470,
-	ARM_VLD2DUPd8wb_fixed	= 1471,
-	ARM_VLD2DUPd8wb_register	= 1472,
-	ARM_VLD2DUPd8x2	= 1473,
-	ARM_VLD2DUPd8x2wb_fixed	= 1474,
-	ARM_VLD2DUPd8x2wb_register	= 1475,
-	ARM_VLD2LNd16	= 1482,
-	ARM_VLD2LNd16_UPD	= 1485,
-	ARM_VLD2LNd32	= 1486,
-	ARM_VLD2LNd32_UPD	= 1489,
-	ARM_VLD2LNd8	= 1490,
-	ARM_VLD2LNd8_UPD	= 1493,
-	ARM_VLD2LNq16	= 1494,
-	ARM_VLD2LNq16_UPD	= 1497,
-	ARM_VLD2LNq32	= 1498,
-	ARM_VLD2LNq32_UPD	= 1501,
-	ARM_VLD2b16	= 1502,
-	ARM_VLD2b16wb_fixed	= 1503,
-	ARM_VLD2b16wb_register	= 1504,
-	ARM_VLD2b32	= 1505,
-	ARM_VLD2b32wb_fixed	= 1506,
-	ARM_VLD2b32wb_register	= 1507,
-	ARM_VLD2b8	= 1508,
-	ARM_VLD2b8wb_fixed	= 1509,
-	ARM_VLD2b8wb_register	= 1510,
-	ARM_VLD2d16	= 1511,
-	ARM_VLD2d16wb_fixed	= 1512,
-	ARM_VLD2d16wb_register	= 1513,
-	ARM_VLD2d32	= 1514,
-	ARM_VLD2d32wb_fixed	= 1515,
-	ARM_VLD2d32wb_register	= 1516,
-	ARM_VLD2d8	= 1517,
-	ARM_VLD2d8wb_fixed	= 1518,
-	ARM_VLD2d8wb_register	= 1519,
-	ARM_VLD2q16	= 1520,
-	ARM_VLD2q16wb_fixed	= 1524,
-	ARM_VLD2q16wb_register	= 1525,
-	ARM_VLD2q32	= 1526,
-	ARM_VLD2q32wb_fixed	= 1530,
-	ARM_VLD2q32wb_register	= 1531,
-	ARM_VLD2q8	= 1532,
-	ARM_VLD2q8wb_fixed	= 1536,
-	ARM_VLD2q8wb_register	= 1537,
-	ARM_VLD3DUPd16	= 1538,
-	ARM_VLD3DUPd16_UPD	= 1541,
-	ARM_VLD3DUPd32	= 1542,
-	ARM_VLD3DUPd32_UPD	= 1545,
-	ARM_VLD3DUPd8	= 1546,
-	ARM_VLD3DUPd8_UPD	= 1549,
-	ARM_VLD3DUPq16	= 1550,
-	ARM_VLD3DUPq16_UPD	= 1553,
-	ARM_VLD3DUPq32	= 1554,
-	ARM_VLD3DUPq32_UPD	= 1557,
-	ARM_VLD3DUPq8	= 1558,
-	ARM_VLD3DUPq8_UPD	= 1561,
-	ARM_VLD3LNd16	= 1562,
-	ARM_VLD3LNd16_UPD	= 1565,
-	ARM_VLD3LNd32	= 1566,
-	ARM_VLD3LNd32_UPD	= 1569,
-	ARM_VLD3LNd8	= 1570,
-	ARM_VLD3LNd8_UPD	= 1573,
-	ARM_VLD3LNq16	= 1574,
-	ARM_VLD3LNq16_UPD	= 1577,
-	ARM_VLD3LNq32	= 1578,
-	ARM_VLD3LNq32_UPD	= 1581,
-	ARM_VLD3d16	= 1582,
-	ARM_VLD3d16_UPD	= 1585,
-	ARM_VLD3d32	= 1586,
-	ARM_VLD3d32_UPD	= 1589,
-	ARM_VLD3d8	= 1590,
-	ARM_VLD3d8_UPD	= 1593,
-	ARM_VLD3q16	= 1594,
-	ARM_VLD3q16_UPD	= 1596,
-	ARM_VLD3q32	= 1599,
-	ARM_VLD3q32_UPD	= 1601,
-	ARM_VLD3q8	= 1604,
-	ARM_VLD3q8_UPD	= 1606,
-	ARM_VLD4DUPd16	= 1609,
-	ARM_VLD4DUPd16_UPD	= 1612,
-	ARM_VLD4DUPd32	= 1613,
-	ARM_VLD4DUPd32_UPD	= 1616,
-	ARM_VLD4DUPd8	= 1617,
-	ARM_VLD4DUPd8_UPD	= 1620,
-	ARM_VLD4DUPq16	= 1621,
-	ARM_VLD4DUPq16_UPD	= 1624,
-	ARM_VLD4DUPq32	= 1625,
-	ARM_VLD4DUPq32_UPD	= 1628,
-	ARM_VLD4DUPq8	= 1629,
-	ARM_VLD4DUPq8_UPD	= 1632,
-	ARM_VLD4LNd16	= 1633,
-	ARM_VLD4LNd16_UPD	= 1636,
-	ARM_VLD4LNd32	= 1637,
-	ARM_VLD4LNd32_UPD	= 1640,
-	ARM_VLD4LNd8	= 1641,
-	ARM_VLD4LNd8_UPD	= 1644,
-	ARM_VLD4LNq16	= 1645,
-	ARM_VLD4LNq16_UPD	= 1648,
-	ARM_VLD4LNq32	= 1649,
-	ARM_VLD4LNq32_UPD	= 1652,
-	ARM_VLD4d16	= 1653,
-	ARM_VLD4d16_UPD	= 1656,
-	ARM_VLD4d32	= 1657,
-	ARM_VLD4d32_UPD	= 1660,
-	ARM_VLD4d8	= 1661,
-	ARM_VLD4d8_UPD	= 1664,
-	ARM_VLD4q16	= 1665,
-	ARM_VLD4q16_UPD	= 1667,
-	ARM_VLD4q32	= 1670,
-	ARM_VLD4q32_UPD	= 1672,
-	ARM_VLD4q8	= 1675,
-	ARM_VLD4q8_UPD	= 1677,
-	ARM_VLDMDDB_UPD	= 1680,
-	ARM_VLDMDIA	= 1681,
-	ARM_VLDMDIA_UPD	= 1682,
-	ARM_VLDMQIA	= 1683,
-	ARM_VLDMSDB_UPD	= 1684,
-	ARM_VLDMSIA	= 1685,
-	ARM_VLDMSIA_UPD	= 1686,
-	ARM_VLDRD	= 1687,
-	ARM_VLDRH	= 1688,
-	ARM_VLDRS	= 1689,
-	ARM_VLLDM	= 1690,
-	ARM_VLSTM	= 1691,
-	ARM_VMAXNMD	= 1692,
-	ARM_VMAXNMH	= 1693,
-	ARM_VMAXNMNDf	= 1694,
-	ARM_VMAXNMNDh	= 1695,
-	ARM_VMAXNMNQf	= 1696,
-	ARM_VMAXNMNQh	= 1697,
-	ARM_VMAXNMS	= 1698,
-	ARM_VMAXfd	= 1699,
-	ARM_VMAXfq	= 1700,
-	ARM_VMAXhd	= 1701,
-	ARM_VMAXhq	= 1702,
-	ARM_VMAXsv16i8	= 1703,
-	ARM_VMAXsv2i32	= 1704,
-	ARM_VMAXsv4i16	= 1705,
-	ARM_VMAXsv4i32	= 1706,
-	ARM_VMAXsv8i16	= 1707,
-	ARM_VMAXsv8i8	= 1708,
-	ARM_VMAXuv16i8	= 1709,
-	ARM_VMAXuv2i32	= 1710,
-	ARM_VMAXuv4i16	= 1711,
-	ARM_VMAXuv4i32	= 1712,
-	ARM_VMAXuv8i16	= 1713,
-	ARM_VMAXuv8i8	= 1714,
-	ARM_VMINNMD	= 1715,
-	ARM_VMINNMH	= 1716,
-	ARM_VMINNMNDf	= 1717,
-	ARM_VMINNMNDh	= 1718,
-	ARM_VMINNMNQf	= 1719,
-	ARM_VMINNMNQh	= 1720,
-	ARM_VMINNMS	= 1721,
-	ARM_VMINfd	= 1722,
-	ARM_VMINfq	= 1723,
-	ARM_VMINhd	= 1724,
-	ARM_VMINhq	= 1725,
-	ARM_VMINsv16i8	= 1726,
-	ARM_VMINsv2i32	= 1727,
-	ARM_VMINsv4i16	= 1728,
-	ARM_VMINsv4i32	= 1729,
-	ARM_VMINsv8i16	= 1730,
-	ARM_VMINsv8i8	= 1731,
-	ARM_VMINuv16i8	= 1732,
-	ARM_VMINuv2i32	= 1733,
-	ARM_VMINuv4i16	= 1734,
-	ARM_VMINuv4i32	= 1735,
-	ARM_VMINuv8i16	= 1736,
-	ARM_VMINuv8i8	= 1737,
-	ARM_VMLAD	= 1738,
-	ARM_VMLAH	= 1739,
-	ARM_VMLALslsv2i32	= 1740,
-	ARM_VMLALslsv4i16	= 1741,
-	ARM_VMLALsluv2i32	= 1742,
-	ARM_VMLALsluv4i16	= 1743,
-	ARM_VMLALsv2i64	= 1744,
-	ARM_VMLALsv4i32	= 1745,
-	ARM_VMLALsv8i16	= 1746,
-	ARM_VMLALuv2i64	= 1747,
-	ARM_VMLALuv4i32	= 1748,
-	ARM_VMLALuv8i16	= 1749,
-	ARM_VMLAS	= 1750,
-	ARM_VMLAfd	= 1751,
-	ARM_VMLAfq	= 1752,
-	ARM_VMLAhd	= 1753,
-	ARM_VMLAhq	= 1754,
-	ARM_VMLAslfd	= 1755,
-	ARM_VMLAslfq	= 1756,
-	ARM_VMLAslhd	= 1757,
-	ARM_VMLAslhq	= 1758,
-	ARM_VMLAslv2i32	= 1759,
-	ARM_VMLAslv4i16	= 1760,
-	ARM_VMLAslv4i32	= 1761,
-	ARM_VMLAslv8i16	= 1762,
-	ARM_VMLAv16i8	= 1763,
-	ARM_VMLAv2i32	= 1764,
-	ARM_VMLAv4i16	= 1765,
-	ARM_VMLAv4i32	= 1766,
-	ARM_VMLAv8i16	= 1767,
-	ARM_VMLAv8i8	= 1768,
-	ARM_VMLSD	= 1769,
-	ARM_VMLSH	= 1770,
-	ARM_VMLSLslsv2i32	= 1771,
-	ARM_VMLSLslsv4i16	= 1772,
-	ARM_VMLSLsluv2i32	= 1773,
-	ARM_VMLSLsluv4i16	= 1774,
-	ARM_VMLSLsv2i64	= 1775,
-	ARM_VMLSLsv4i32	= 1776,
-	ARM_VMLSLsv8i16	= 1777,
-	ARM_VMLSLuv2i64	= 1778,
-	ARM_VMLSLuv4i32	= 1779,
-	ARM_VMLSLuv8i16	= 1780,
-	ARM_VMLSS	= 1781,
-	ARM_VMLSfd	= 1782,
-	ARM_VMLSfq	= 1783,
-	ARM_VMLShd	= 1784,
-	ARM_VMLShq	= 1785,
-	ARM_VMLSslfd	= 1786,
-	ARM_VMLSslfq	= 1787,
-	ARM_VMLSslhd	= 1788,
-	ARM_VMLSslhq	= 1789,
-	ARM_VMLSslv2i32	= 1790,
-	ARM_VMLSslv4i16	= 1791,
-	ARM_VMLSslv4i32	= 1792,
-	ARM_VMLSslv8i16	= 1793,
-	ARM_VMLSv16i8	= 1794,
-	ARM_VMLSv2i32	= 1795,
-	ARM_VMLSv4i16	= 1796,
-	ARM_VMLSv4i32	= 1797,
-	ARM_VMLSv8i16	= 1798,
-	ARM_VMLSv8i8	= 1799,
-	ARM_VMOVD	= 1800,
-	ARM_VMOVDRR	= 1801,
-	ARM_VMOVH	= 1802,
-	ARM_VMOVHR	= 1803,
-	ARM_VMOVLsv2i64	= 1804,
-	ARM_VMOVLsv4i32	= 1805,
-	ARM_VMOVLsv8i16	= 1806,
-	ARM_VMOVLuv2i64	= 1807,
-	ARM_VMOVLuv4i32	= 1808,
-	ARM_VMOVLuv8i16	= 1809,
-	ARM_VMOVNv2i32	= 1810,
-	ARM_VMOVNv4i16	= 1811,
-	ARM_VMOVNv8i8	= 1812,
-	ARM_VMOVRH	= 1813,
-	ARM_VMOVRRD	= 1814,
-	ARM_VMOVRRS	= 1815,
-	ARM_VMOVRS	= 1816,
-	ARM_VMOVS	= 1817,
-	ARM_VMOVSR	= 1818,
-	ARM_VMOVSRR	= 1819,
-	ARM_VMOVv16i8	= 1820,
-	ARM_VMOVv1i64	= 1821,
-	ARM_VMOVv2f32	= 1822,
-	ARM_VMOVv2i32	= 1823,
-	ARM_VMOVv2i64	= 1824,
-	ARM_VMOVv4f32	= 1825,
-	ARM_VMOVv4i16	= 1826,
-	ARM_VMOVv4i32	= 1827,
-	ARM_VMOVv8i16	= 1828,
-	ARM_VMOVv8i8	= 1829,
-	ARM_VMRS	= 1830,
-	ARM_VMRS_FPEXC	= 1831,
-	ARM_VMRS_FPINST	= 1832,
-	ARM_VMRS_FPINST2	= 1833,
-	ARM_VMRS_FPSID	= 1834,
-	ARM_VMRS_MVFR0	= 1835,
-	ARM_VMRS_MVFR1	= 1836,
-	ARM_VMRS_MVFR2	= 1837,
-	ARM_VMSR	= 1838,
-	ARM_VMSR_FPEXC	= 1839,
-	ARM_VMSR_FPINST	= 1840,
-	ARM_VMSR_FPINST2	= 1841,
-	ARM_VMSR_FPSID	= 1842,
-	ARM_VMULD	= 1843,
-	ARM_VMULH	= 1844,
-	ARM_VMULLp64	= 1845,
-	ARM_VMULLp8	= 1846,
-	ARM_VMULLslsv2i32	= 1847,
-	ARM_VMULLslsv4i16	= 1848,
-	ARM_VMULLsluv2i32	= 1849,
-	ARM_VMULLsluv4i16	= 1850,
-	ARM_VMULLsv2i64	= 1851,
-	ARM_VMULLsv4i32	= 1852,
-	ARM_VMULLsv8i16	= 1853,
-	ARM_VMULLuv2i64	= 1854,
-	ARM_VMULLuv4i32	= 1855,
-	ARM_VMULLuv8i16	= 1856,
-	ARM_VMULS	= 1857,
-	ARM_VMULfd	= 1858,
-	ARM_VMULfq	= 1859,
-	ARM_VMULhd	= 1860,
-	ARM_VMULhq	= 1861,
-	ARM_VMULpd	= 1862,
-	ARM_VMULpq	= 1863,
-	ARM_VMULslfd	= 1864,
-	ARM_VMULslfq	= 1865,
-	ARM_VMULslhd	= 1866,
-	ARM_VMULslhq	= 1867,
-	ARM_VMULslv2i32	= 1868,
-	ARM_VMULslv4i16	= 1869,
-	ARM_VMULslv4i32	= 1870,
-	ARM_VMULslv8i16	= 1871,
-	ARM_VMULv16i8	= 1872,
-	ARM_VMULv2i32	= 1873,
-	ARM_VMULv4i16	= 1874,
-	ARM_VMULv4i32	= 1875,
-	ARM_VMULv8i16	= 1876,
-	ARM_VMULv8i8	= 1877,
-	ARM_VMVNd	= 1878,
-	ARM_VMVNq	= 1879,
-	ARM_VMVNv2i32	= 1880,
-	ARM_VMVNv4i16	= 1881,
-	ARM_VMVNv4i32	= 1882,
-	ARM_VMVNv8i16	= 1883,
-	ARM_VNEGD	= 1884,
-	ARM_VNEGH	= 1885,
-	ARM_VNEGS	= 1886,
-	ARM_VNEGf32q	= 1887,
-	ARM_VNEGfd	= 1888,
-	ARM_VNEGhd	= 1889,
-	ARM_VNEGhq	= 1890,
-	ARM_VNEGs16d	= 1891,
-	ARM_VNEGs16q	= 1892,
-	ARM_VNEGs32d	= 1893,
-	ARM_VNEGs32q	= 1894,
-	ARM_VNEGs8d	= 1895,
-	ARM_VNEGs8q	= 1896,
-	ARM_VNMLAD	= 1897,
-	ARM_VNMLAH	= 1898,
-	ARM_VNMLAS	= 1899,
-	ARM_VNMLSD	= 1900,
-	ARM_VNMLSH	= 1901,
-	ARM_VNMLSS	= 1902,
-	ARM_VNMULD	= 1903,
-	ARM_VNMULH	= 1904,
-	ARM_VNMULS	= 1905,
-	ARM_VORNd	= 1906,
-	ARM_VORNq	= 1907,
-	ARM_VORRd	= 1908,
-	ARM_VORRiv2i32	= 1909,
-	ARM_VORRiv4i16	= 1910,
-	ARM_VORRiv4i32	= 1911,
-	ARM_VORRiv8i16	= 1912,
-	ARM_VORRq	= 1913,
-	ARM_VPADALsv16i8	= 1914,
-	ARM_VPADALsv2i32	= 1915,
-	ARM_VPADALsv4i16	= 1916,
-	ARM_VPADALsv4i32	= 1917,
-	ARM_VPADALsv8i16	= 1918,
-	ARM_VPADALsv8i8	= 1919,
-	ARM_VPADALuv16i8	= 1920,
-	ARM_VPADALuv2i32	= 1921,
-	ARM_VPADALuv4i16	= 1922,
-	ARM_VPADALuv4i32	= 1923,
-	ARM_VPADALuv8i16	= 1924,
-	ARM_VPADALuv8i8	= 1925,
-	ARM_VPADDLsv16i8	= 1926,
-	ARM_VPADDLsv2i32	= 1927,
-	ARM_VPADDLsv4i16	= 1928,
-	ARM_VPADDLsv4i32	= 1929,
-	ARM_VPADDLsv8i16	= 1930,
-	ARM_VPADDLsv8i8	= 1931,
-	ARM_VPADDLuv16i8	= 1932,
-	ARM_VPADDLuv2i32	= 1933,
-	ARM_VPADDLuv4i16	= 1934,
-	ARM_VPADDLuv4i32	= 1935,
-	ARM_VPADDLuv8i16	= 1936,
-	ARM_VPADDLuv8i8	= 1937,
-	ARM_VPADDf	= 1938,
-	ARM_VPADDh	= 1939,
-	ARM_VPADDi16	= 1940,
-	ARM_VPADDi32	= 1941,
-	ARM_VPADDi8	= 1942,
-	ARM_VPMAXf	= 1943,
-	ARM_VPMAXh	= 1944,
-	ARM_VPMAXs16	= 1945,
-	ARM_VPMAXs32	= 1946,
-	ARM_VPMAXs8	= 1947,
-	ARM_VPMAXu16	= 1948,
-	ARM_VPMAXu32	= 1949,
-	ARM_VPMAXu8	= 1950,
-	ARM_VPMINf	= 1951,
-	ARM_VPMINh	= 1952,
-	ARM_VPMINs16	= 1953,
-	ARM_VPMINs32	= 1954,
-	ARM_VPMINs8	= 1955,
-	ARM_VPMINu16	= 1956,
-	ARM_VPMINu32	= 1957,
-	ARM_VPMINu8	= 1958,
-	ARM_VQABSv16i8	= 1959,
-	ARM_VQABSv2i32	= 1960,
-	ARM_VQABSv4i16	= 1961,
-	ARM_VQABSv4i32	= 1962,
-	ARM_VQABSv8i16	= 1963,
-	ARM_VQABSv8i8	= 1964,
-	ARM_VQADDsv16i8	= 1965,
-	ARM_VQADDsv1i64	= 1966,
-	ARM_VQADDsv2i32	= 1967,
-	ARM_VQADDsv2i64	= 1968,
-	ARM_VQADDsv4i16	= 1969,
-	ARM_VQADDsv4i32	= 1970,
-	ARM_VQADDsv8i16	= 1971,
-	ARM_VQADDsv8i8	= 1972,
-	ARM_VQADDuv16i8	= 1973,
-	ARM_VQADDuv1i64	= 1974,
-	ARM_VQADDuv2i32	= 1975,
-	ARM_VQADDuv2i64	= 1976,
-	ARM_VQADDuv4i16	= 1977,
-	ARM_VQADDuv4i32	= 1978,
-	ARM_VQADDuv8i16	= 1979,
-	ARM_VQADDuv8i8	= 1980,
-	ARM_VQDMLALslv2i32	= 1981,
-	ARM_VQDMLALslv4i16	= 1982,
-	ARM_VQDMLALv2i64	= 1983,
-	ARM_VQDMLALv4i32	= 1984,
-	ARM_VQDMLSLslv2i32	= 1985,
-	ARM_VQDMLSLslv4i16	= 1986,
-	ARM_VQDMLSLv2i64	= 1987,
-	ARM_VQDMLSLv4i32	= 1988,
-	ARM_VQDMULHslv2i32	= 1989,
-	ARM_VQDMULHslv4i16	= 1990,
-	ARM_VQDMULHslv4i32	= 1991,
-	ARM_VQDMULHslv8i16	= 1992,
-	ARM_VQDMULHv2i32	= 1993,
-	ARM_VQDMULHv4i16	= 1994,
-	ARM_VQDMULHv4i32	= 1995,
-	ARM_VQDMULHv8i16	= 1996,
-	ARM_VQDMULLslv2i32	= 1997,
-	ARM_VQDMULLslv4i16	= 1998,
-	ARM_VQDMULLv2i64	= 1999,
-	ARM_VQDMULLv4i32	= 2000,
-	ARM_VQMOVNsuv2i32	= 2001,
-	ARM_VQMOVNsuv4i16	= 2002,
-	ARM_VQMOVNsuv8i8	= 2003,
-	ARM_VQMOVNsv2i32	= 2004,
-	ARM_VQMOVNsv4i16	= 2005,
-	ARM_VQMOVNsv8i8	= 2006,
-	ARM_VQMOVNuv2i32	= 2007,
-	ARM_VQMOVNuv4i16	= 2008,
-	ARM_VQMOVNuv8i8	= 2009,
-	ARM_VQNEGv16i8	= 2010,
-	ARM_VQNEGv2i32	= 2011,
-	ARM_VQNEGv4i16	= 2012,
-	ARM_VQNEGv4i32	= 2013,
-	ARM_VQNEGv8i16	= 2014,
-	ARM_VQNEGv8i8	= 2015,
-	ARM_VQRDMLAHslv2i32	= 2016,
-	ARM_VQRDMLAHslv4i16	= 2017,
-	ARM_VQRDMLAHslv4i32	= 2018,
-	ARM_VQRDMLAHslv8i16	= 2019,
-	ARM_VQRDMLAHv2i32	= 2020,
-	ARM_VQRDMLAHv4i16	= 2021,
-	ARM_VQRDMLAHv4i32	= 2022,
-	ARM_VQRDMLAHv8i16	= 2023,
-	ARM_VQRDMLSHslv2i32	= 2024,
-	ARM_VQRDMLSHslv4i16	= 2025,
-	ARM_VQRDMLSHslv4i32	= 2026,
-	ARM_VQRDMLSHslv8i16	= 2027,
-	ARM_VQRDMLSHv2i32	= 2028,
-	ARM_VQRDMLSHv4i16	= 2029,
-	ARM_VQRDMLSHv4i32	= 2030,
-	ARM_VQRDMLSHv8i16	= 2031,
-	ARM_VQRDMULHslv2i32	= 2032,
-	ARM_VQRDMULHslv4i16	= 2033,
-	ARM_VQRDMULHslv4i32	= 2034,
-	ARM_VQRDMULHslv8i16	= 2035,
-	ARM_VQRDMULHv2i32	= 2036,
-	ARM_VQRDMULHv4i16	= 2037,
-	ARM_VQRDMULHv4i32	= 2038,
-	ARM_VQRDMULHv8i16	= 2039,
-	ARM_VQRSHLsv16i8	= 2040,
-	ARM_VQRSHLsv1i64	= 2041,
-	ARM_VQRSHLsv2i32	= 2042,
-	ARM_VQRSHLsv2i64	= 2043,
-	ARM_VQRSHLsv4i16	= 2044,
-	ARM_VQRSHLsv4i32	= 2045,
-	ARM_VQRSHLsv8i16	= 2046,
-	ARM_VQRSHLsv8i8	= 2047,
-	ARM_VQRSHLuv16i8	= 2048,
-	ARM_VQRSHLuv1i64	= 2049,
-	ARM_VQRSHLuv2i32	= 2050,
-	ARM_VQRSHLuv2i64	= 2051,
-	ARM_VQRSHLuv4i16	= 2052,
-	ARM_VQRSHLuv4i32	= 2053,
-	ARM_VQRSHLuv8i16	= 2054,
-	ARM_VQRSHLuv8i8	= 2055,
-	ARM_VQRSHRNsv2i32	= 2056,
-	ARM_VQRSHRNsv4i16	= 2057,
-	ARM_VQRSHRNsv8i8	= 2058,
-	ARM_VQRSHRNuv2i32	= 2059,
-	ARM_VQRSHRNuv4i16	= 2060,
-	ARM_VQRSHRNuv8i8	= 2061,
-	ARM_VQRSHRUNv2i32	= 2062,
-	ARM_VQRSHRUNv4i16	= 2063,
-	ARM_VQRSHRUNv8i8	= 2064,
-	ARM_VQSHLsiv16i8	= 2065,
-	ARM_VQSHLsiv1i64	= 2066,
-	ARM_VQSHLsiv2i32	= 2067,
-	ARM_VQSHLsiv2i64	= 2068,
-	ARM_VQSHLsiv4i16	= 2069,
-	ARM_VQSHLsiv4i32	= 2070,
-	ARM_VQSHLsiv8i16	= 2071,
-	ARM_VQSHLsiv8i8	= 2072,
-	ARM_VQSHLsuv16i8	= 2073,
-	ARM_VQSHLsuv1i64	= 2074,
-	ARM_VQSHLsuv2i32	= 2075,
-	ARM_VQSHLsuv2i64	= 2076,
-	ARM_VQSHLsuv4i16	= 2077,
-	ARM_VQSHLsuv4i32	= 2078,
-	ARM_VQSHLsuv8i16	= 2079,
-	ARM_VQSHLsuv8i8	= 2080,
-	ARM_VQSHLsv16i8	= 2081,
-	ARM_VQSHLsv1i64	= 2082,
-	ARM_VQSHLsv2i32	= 2083,
-	ARM_VQSHLsv2i64	= 2084,
-	ARM_VQSHLsv4i16	= 2085,
-	ARM_VQSHLsv4i32	= 2086,
-	ARM_VQSHLsv8i16	= 2087,
-	ARM_VQSHLsv8i8	= 2088,
-	ARM_VQSHLuiv16i8	= 2089,
-	ARM_VQSHLuiv1i64	= 2090,
-	ARM_VQSHLuiv2i32	= 2091,
-	ARM_VQSHLuiv2i64	= 2092,
-	ARM_VQSHLuiv4i16	= 2093,
-	ARM_VQSHLuiv4i32	= 2094,
-	ARM_VQSHLuiv8i16	= 2095,
-	ARM_VQSHLuiv8i8	= 2096,
-	ARM_VQSHLuv16i8	= 2097,
-	ARM_VQSHLuv1i64	= 2098,
-	ARM_VQSHLuv2i32	= 2099,
-	ARM_VQSHLuv2i64	= 2100,
-	ARM_VQSHLuv4i16	= 2101,
-	ARM_VQSHLuv4i32	= 2102,
-	ARM_VQSHLuv8i16	= 2103,
-	ARM_VQSHLuv8i8	= 2104,
-	ARM_VQSHRNsv2i32	= 2105,
-	ARM_VQSHRNsv4i16	= 2106,
-	ARM_VQSHRNsv8i8	= 2107,
-	ARM_VQSHRNuv2i32	= 2108,
-	ARM_VQSHRNuv4i16	= 2109,
-	ARM_VQSHRNuv8i8	= 2110,
-	ARM_VQSHRUNv2i32	= 2111,
-	ARM_VQSHRUNv4i16	= 2112,
-	ARM_VQSHRUNv8i8	= 2113,
-	ARM_VQSUBsv16i8	= 2114,
-	ARM_VQSUBsv1i64	= 2115,
-	ARM_VQSUBsv2i32	= 2116,
-	ARM_VQSUBsv2i64	= 2117,
-	ARM_VQSUBsv4i16	= 2118,
-	ARM_VQSUBsv4i32	= 2119,
-	ARM_VQSUBsv8i16	= 2120,
-	ARM_VQSUBsv8i8	= 2121,
-	ARM_VQSUBuv16i8	= 2122,
-	ARM_VQSUBuv1i64	= 2123,
-	ARM_VQSUBuv2i32	= 2124,
-	ARM_VQSUBuv2i64	= 2125,
-	ARM_VQSUBuv4i16	= 2126,
-	ARM_VQSUBuv4i32	= 2127,
-	ARM_VQSUBuv8i16	= 2128,
-	ARM_VQSUBuv8i8	= 2129,
-	ARM_VRADDHNv2i32	= 2130,
-	ARM_VRADDHNv4i16	= 2131,
-	ARM_VRADDHNv8i8	= 2132,
-	ARM_VRECPEd	= 2133,
-	ARM_VRECPEfd	= 2134,
-	ARM_VRECPEfq	= 2135,
-	ARM_VRECPEhd	= 2136,
-	ARM_VRECPEhq	= 2137,
-	ARM_VRECPEq	= 2138,
-	ARM_VRECPSfd	= 2139,
-	ARM_VRECPSfq	= 2140,
-	ARM_VRECPShd	= 2141,
-	ARM_VRECPShq	= 2142,
-	ARM_VREV16d8	= 2143,
-	ARM_VREV16q8	= 2144,
-	ARM_VREV32d16	= 2145,
-	ARM_VREV32d8	= 2146,
-	ARM_VREV32q16	= 2147,
-	ARM_VREV32q8	= 2148,
-	ARM_VREV64d16	= 2149,
-	ARM_VREV64d32	= 2150,
-	ARM_VREV64d8	= 2151,
-	ARM_VREV64q16	= 2152,
-	ARM_VREV64q32	= 2153,
-	ARM_VREV64q8	= 2154,
-	ARM_VRHADDsv16i8	= 2155,
-	ARM_VRHADDsv2i32	= 2156,
-	ARM_VRHADDsv4i16	= 2157,
-	ARM_VRHADDsv4i32	= 2158,
-	ARM_VRHADDsv8i16	= 2159,
-	ARM_VRHADDsv8i8	= 2160,
-	ARM_VRHADDuv16i8	= 2161,
-	ARM_VRHADDuv2i32	= 2162,
-	ARM_VRHADDuv4i16	= 2163,
-	ARM_VRHADDuv4i32	= 2164,
-	ARM_VRHADDuv8i16	= 2165,
-	ARM_VRHADDuv8i8	= 2166,
-	ARM_VRINTAD	= 2167,
-	ARM_VRINTAH	= 2168,
-	ARM_VRINTANDf	= 2169,
-	ARM_VRINTANDh	= 2170,
-	ARM_VRINTANQf	= 2171,
-	ARM_VRINTANQh	= 2172,
-	ARM_VRINTAS	= 2173,
-	ARM_VRINTMD	= 2174,
-	ARM_VRINTMH	= 2175,
-	ARM_VRINTMNDf	= 2176,
-	ARM_VRINTMNDh	= 2177,
-	ARM_VRINTMNQf	= 2178,
-	ARM_VRINTMNQh	= 2179,
-	ARM_VRINTMS	= 2180,
-	ARM_VRINTND	= 2181,
-	ARM_VRINTNH	= 2182,
-	ARM_VRINTNNDf	= 2183,
-	ARM_VRINTNNDh	= 2184,
-	ARM_VRINTNNQf	= 2185,
-	ARM_VRINTNNQh	= 2186,
-	ARM_VRINTNS	= 2187,
-	ARM_VRINTPD	= 2188,
-	ARM_VRINTPH	= 2189,
-	ARM_VRINTPNDf	= 2190,
-	ARM_VRINTPNDh	= 2191,
-	ARM_VRINTPNQf	= 2192,
-	ARM_VRINTPNQh	= 2193,
-	ARM_VRINTPS	= 2194,
-	ARM_VRINTRD	= 2195,
-	ARM_VRINTRH	= 2196,
-	ARM_VRINTRS	= 2197,
-	ARM_VRINTXD	= 2198,
-	ARM_VRINTXH	= 2199,
-	ARM_VRINTXNDf	= 2200,
-	ARM_VRINTXNDh	= 2201,
-	ARM_VRINTXNQf	= 2202,
-	ARM_VRINTXNQh	= 2203,
-	ARM_VRINTXS	= 2204,
-	ARM_VRINTZD	= 2205,
-	ARM_VRINTZH	= 2206,
-	ARM_VRINTZNDf	= 2207,
-	ARM_VRINTZNDh	= 2208,
-	ARM_VRINTZNQf	= 2209,
-	ARM_VRINTZNQh	= 2210,
-	ARM_VRINTZS	= 2211,
-	ARM_VRSHLsv16i8	= 2212,
-	ARM_VRSHLsv1i64	= 2213,
-	ARM_VRSHLsv2i32	= 2214,
-	ARM_VRSHLsv2i64	= 2215,
-	ARM_VRSHLsv4i16	= 2216,
-	ARM_VRSHLsv4i32	= 2217,
-	ARM_VRSHLsv8i16	= 2218,
-	ARM_VRSHLsv8i8	= 2219,
-	ARM_VRSHLuv16i8	= 2220,
-	ARM_VRSHLuv1i64	= 2221,
-	ARM_VRSHLuv2i32	= 2222,
-	ARM_VRSHLuv2i64	= 2223,
-	ARM_VRSHLuv4i16	= 2224,
-	ARM_VRSHLuv4i32	= 2225,
-	ARM_VRSHLuv8i16	= 2226,
-	ARM_VRSHLuv8i8	= 2227,
-	ARM_VRSHRNv2i32	= 2228,
-	ARM_VRSHRNv4i16	= 2229,
-	ARM_VRSHRNv8i8	= 2230,
-	ARM_VRSHRsv16i8	= 2231,
-	ARM_VRSHRsv1i64	= 2232,
-	ARM_VRSHRsv2i32	= 2233,
-	ARM_VRSHRsv2i64	= 2234,
-	ARM_VRSHRsv4i16	= 2235,
-	ARM_VRSHRsv4i32	= 2236,
-	ARM_VRSHRsv8i16	= 2237,
-	ARM_VRSHRsv8i8	= 2238,
-	ARM_VRSHRuv16i8	= 2239,
-	ARM_VRSHRuv1i64	= 2240,
-	ARM_VRSHRuv2i32	= 2241,
-	ARM_VRSHRuv2i64	= 2242,
-	ARM_VRSHRuv4i16	= 2243,
-	ARM_VRSHRuv4i32	= 2244,
-	ARM_VRSHRuv8i16	= 2245,
-	ARM_VRSHRuv8i8	= 2246,
-	ARM_VRSQRTEd	= 2247,
-	ARM_VRSQRTEfd	= 2248,
-	ARM_VRSQRTEfq	= 2249,
-	ARM_VRSQRTEhd	= 2250,
-	ARM_VRSQRTEhq	= 2251,
-	ARM_VRSQRTEq	= 2252,
-	ARM_VRSQRTSfd	= 2253,
-	ARM_VRSQRTSfq	= 2254,
-	ARM_VRSQRTShd	= 2255,
-	ARM_VRSQRTShq	= 2256,
-	ARM_VRSRAsv16i8	= 2257,
-	ARM_VRSRAsv1i64	= 2258,
-	ARM_VRSRAsv2i32	= 2259,
-	ARM_VRSRAsv2i64	= 2260,
-	ARM_VRSRAsv4i16	= 2261,
-	ARM_VRSRAsv4i32	= 2262,
-	ARM_VRSRAsv8i16	= 2263,
-	ARM_VRSRAsv8i8	= 2264,
-	ARM_VRSRAuv16i8	= 2265,
-	ARM_VRSRAuv1i64	= 2266,
-	ARM_VRSRAuv2i32	= 2267,
-	ARM_VRSRAuv2i64	= 2268,
-	ARM_VRSRAuv4i16	= 2269,
-	ARM_VRSRAuv4i32	= 2270,
-	ARM_VRSRAuv8i16	= 2271,
-	ARM_VRSRAuv8i8	= 2272,
-	ARM_VRSUBHNv2i32	= 2273,
-	ARM_VRSUBHNv4i16	= 2274,
-	ARM_VRSUBHNv8i8	= 2275,
-	ARM_VSDOTD	= 2276,
-	ARM_VSDOTDI	= 2277,
-	ARM_VSDOTQ	= 2278,
-	ARM_VSDOTQI	= 2279,
-	ARM_VSELEQD	= 2280,
-	ARM_VSELEQH	= 2281,
-	ARM_VSELEQS	= 2282,
-	ARM_VSELGED	= 2283,
-	ARM_VSELGEH	= 2284,
-	ARM_VSELGES	= 2285,
-	ARM_VSELGTD	= 2286,
-	ARM_VSELGTH	= 2287,
-	ARM_VSELGTS	= 2288,
-	ARM_VSELVSD	= 2289,
-	ARM_VSELVSH	= 2290,
-	ARM_VSELVSS	= 2291,
-	ARM_VSETLNi16	= 2292,
-	ARM_VSETLNi32	= 2293,
-	ARM_VSETLNi8	= 2294,
-	ARM_VSHLLi16	= 2295,
-	ARM_VSHLLi32	= 2296,
-	ARM_VSHLLi8	= 2297,
-	ARM_VSHLLsv2i64	= 2298,
-	ARM_VSHLLsv4i32	= 2299,
-	ARM_VSHLLsv8i16	= 2300,
-	ARM_VSHLLuv2i64	= 2301,
-	ARM_VSHLLuv4i32	= 2302,
-	ARM_VSHLLuv8i16	= 2303,
-	ARM_VSHLiv16i8	= 2304,
-	ARM_VSHLiv1i64	= 2305,
-	ARM_VSHLiv2i32	= 2306,
-	ARM_VSHLiv2i64	= 2307,
-	ARM_VSHLiv4i16	= 2308,
-	ARM_VSHLiv4i32	= 2309,
-	ARM_VSHLiv8i16	= 2310,
-	ARM_VSHLiv8i8	= 2311,
-	ARM_VSHLsv16i8	= 2312,
-	ARM_VSHLsv1i64	= 2313,
-	ARM_VSHLsv2i32	= 2314,
-	ARM_VSHLsv2i64	= 2315,
-	ARM_VSHLsv4i16	= 2316,
-	ARM_VSHLsv4i32	= 2317,
-	ARM_VSHLsv8i16	= 2318,
-	ARM_VSHLsv8i8	= 2319,
-	ARM_VSHLuv16i8	= 2320,
-	ARM_VSHLuv1i64	= 2321,
-	ARM_VSHLuv2i32	= 2322,
-	ARM_VSHLuv2i64	= 2323,
-	ARM_VSHLuv4i16	= 2324,
-	ARM_VSHLuv4i32	= 2325,
-	ARM_VSHLuv8i16	= 2326,
-	ARM_VSHLuv8i8	= 2327,
-	ARM_VSHRNv2i32	= 2328,
-	ARM_VSHRNv4i16	= 2329,
-	ARM_VSHRNv8i8	= 2330,
-	ARM_VSHRsv16i8	= 2331,
-	ARM_VSHRsv1i64	= 2332,
-	ARM_VSHRsv2i32	= 2333,
-	ARM_VSHRsv2i64	= 2334,
-	ARM_VSHRsv4i16	= 2335,
-	ARM_VSHRsv4i32	= 2336,
-	ARM_VSHRsv8i16	= 2337,
-	ARM_VSHRsv8i8	= 2338,
-	ARM_VSHRuv16i8	= 2339,
-	ARM_VSHRuv1i64	= 2340,
-	ARM_VSHRuv2i32	= 2341,
-	ARM_VSHRuv2i64	= 2342,
-	ARM_VSHRuv4i16	= 2343,
-	ARM_VSHRuv4i32	= 2344,
-	ARM_VSHRuv8i16	= 2345,
-	ARM_VSHRuv8i8	= 2346,
-	ARM_VSHTOD	= 2347,
-	ARM_VSHTOH	= 2348,
-	ARM_VSHTOS	= 2349,
-	ARM_VSITOD	= 2350,
-	ARM_VSITOH	= 2351,
-	ARM_VSITOS	= 2352,
-	ARM_VSLIv16i8	= 2353,
-	ARM_VSLIv1i64	= 2354,
-	ARM_VSLIv2i32	= 2355,
-	ARM_VSLIv2i64	= 2356,
-	ARM_VSLIv4i16	= 2357,
-	ARM_VSLIv4i32	= 2358,
-	ARM_VSLIv8i16	= 2359,
-	ARM_VSLIv8i8	= 2360,
-	ARM_VSLTOD	= 2361,
-	ARM_VSLTOH	= 2362,
-	ARM_VSLTOS	= 2363,
-	ARM_VSQRTD	= 2364,
-	ARM_VSQRTH	= 2365,
-	ARM_VSQRTS	= 2366,
-	ARM_VSRAsv16i8	= 2367,
-	ARM_VSRAsv1i64	= 2368,
-	ARM_VSRAsv2i32	= 2369,
-	ARM_VSRAsv2i64	= 2370,
-	ARM_VSRAsv4i16	= 2371,
-	ARM_VSRAsv4i32	= 2372,
-	ARM_VSRAsv8i16	= 2373,
-	ARM_VSRAsv8i8	= 2374,
-	ARM_VSRAuv16i8	= 2375,
-	ARM_VSRAuv1i64	= 2376,
-	ARM_VSRAuv2i32	= 2377,
-	ARM_VSRAuv2i64	= 2378,
-	ARM_VSRAuv4i16	= 2379,
-	ARM_VSRAuv4i32	= 2380,
-	ARM_VSRAuv8i16	= 2381,
-	ARM_VSRAuv8i8	= 2382,
-	ARM_VSRIv16i8	= 2383,
-	ARM_VSRIv1i64	= 2384,
-	ARM_VSRIv2i32	= 2385,
-	ARM_VSRIv2i64	= 2386,
-	ARM_VSRIv4i16	= 2387,
-	ARM_VSRIv4i32	= 2388,
-	ARM_VSRIv8i16	= 2389,
-	ARM_VSRIv8i8	= 2390,
-	ARM_VST1LNd16	= 2391,
-	ARM_VST1LNd16_UPD	= 2392,
-	ARM_VST1LNd32	= 2393,
-	ARM_VST1LNd32_UPD	= 2394,
-	ARM_VST1LNd8	= 2395,
-	ARM_VST1LNd8_UPD	= 2396,
-	ARM_VST1d16	= 2403,
-	ARM_VST1d16Q	= 2404,
-	ARM_VST1d16Qwb_fixed	= 2406,
-	ARM_VST1d16Qwb_register	= 2407,
-	ARM_VST1d16T	= 2408,
-	ARM_VST1d16Twb_fixed	= 2410,
-	ARM_VST1d16Twb_register	= 2411,
-	ARM_VST1d16wb_fixed	= 2412,
-	ARM_VST1d16wb_register	= 2413,
-	ARM_VST1d32	= 2414,
-	ARM_VST1d32Q	= 2415,
-	ARM_VST1d32Qwb_fixed	= 2417,
-	ARM_VST1d32Qwb_register	= 2418,
-	ARM_VST1d32T	= 2419,
-	ARM_VST1d32Twb_fixed	= 2421,
-	ARM_VST1d32Twb_register	= 2422,
-	ARM_VST1d32wb_fixed	= 2423,
-	ARM_VST1d32wb_register	= 2424,
-	ARM_VST1d64	= 2425,
-	ARM_VST1d64Q	= 2426,
-	ARM_VST1d64Qwb_fixed	= 2430,
-	ARM_VST1d64Qwb_register	= 2431,
-	ARM_VST1d64T	= 2432,
-	ARM_VST1d64Twb_fixed	= 2436,
-	ARM_VST1d64Twb_register	= 2437,
-	ARM_VST1d64wb_fixed	= 2438,
-	ARM_VST1d64wb_register	= 2439,
-	ARM_VST1d8	= 2440,
-	ARM_VST1d8Q	= 2441,
-	ARM_VST1d8Qwb_fixed	= 2443,
-	ARM_VST1d8Qwb_register	= 2444,
-	ARM_VST1d8T	= 2445,
-	ARM_VST1d8Twb_fixed	= 2447,
-	ARM_VST1d8Twb_register	= 2448,
-	ARM_VST1d8wb_fixed	= 2449,
-	ARM_VST1d8wb_register	= 2450,
-	ARM_VST1q16	= 2451,
-	ARM_VST1q16wb_fixed	= 2456,
-	ARM_VST1q16wb_register	= 2457,
-	ARM_VST1q32	= 2458,
-	ARM_VST1q32wb_fixed	= 2463,
-	ARM_VST1q32wb_register	= 2464,
-	ARM_VST1q64	= 2465,
-	ARM_VST1q64wb_fixed	= 2470,
-	ARM_VST1q64wb_register	= 2471,
-	ARM_VST1q8	= 2472,
-	ARM_VST1q8wb_fixed	= 2477,
-	ARM_VST1q8wb_register	= 2478,
-	ARM_VST2LNd16	= 2479,
-	ARM_VST2LNd16_UPD	= 2482,
-	ARM_VST2LNd32	= 2483,
-	ARM_VST2LNd32_UPD	= 2486,
-	ARM_VST2LNd8	= 2487,
-	ARM_VST2LNd8_UPD	= 2490,
-	ARM_VST2LNq16	= 2491,
-	ARM_VST2LNq16_UPD	= 2494,
-	ARM_VST2LNq32	= 2495,
-	ARM_VST2LNq32_UPD	= 2498,
-	ARM_VST2b16	= 2499,
-	ARM_VST2b16wb_fixed	= 2500,
-	ARM_VST2b16wb_register	= 2501,
-	ARM_VST2b32	= 2502,
-	ARM_VST2b32wb_fixed	= 2503,
-	ARM_VST2b32wb_register	= 2504,
-	ARM_VST2b8	= 2505,
-	ARM_VST2b8wb_fixed	= 2506,
-	ARM_VST2b8wb_register	= 2507,
-	ARM_VST2d16	= 2508,
-	ARM_VST2d16wb_fixed	= 2509,
-	ARM_VST2d16wb_register	= 2510,
-	ARM_VST2d32	= 2511,
-	ARM_VST2d32wb_fixed	= 2512,
-	ARM_VST2d32wb_register	= 2513,
-	ARM_VST2d8	= 2514,
-	ARM_VST2d8wb_fixed	= 2515,
-	ARM_VST2d8wb_register	= 2516,
-	ARM_VST2q16	= 2517,
-	ARM_VST2q16wb_fixed	= 2521,
-	ARM_VST2q16wb_register	= 2522,
-	ARM_VST2q32	= 2523,
-	ARM_VST2q32wb_fixed	= 2527,
-	ARM_VST2q32wb_register	= 2528,
-	ARM_VST2q8	= 2529,
-	ARM_VST2q8wb_fixed	= 2533,
-	ARM_VST2q8wb_register	= 2534,
-	ARM_VST3LNd16	= 2535,
-	ARM_VST3LNd16_UPD	= 2538,
-	ARM_VST3LNd32	= 2539,
-	ARM_VST3LNd32_UPD	= 2542,
-	ARM_VST3LNd8	= 2543,
-	ARM_VST3LNd8_UPD	= 2546,
-	ARM_VST3LNq16	= 2547,
-	ARM_VST3LNq16_UPD	= 2550,
-	ARM_VST3LNq32	= 2551,
-	ARM_VST3LNq32_UPD	= 2554,
-	ARM_VST3d16	= 2555,
-	ARM_VST3d16_UPD	= 2558,
-	ARM_VST3d32	= 2559,
-	ARM_VST3d32_UPD	= 2562,
-	ARM_VST3d8	= 2563,
-	ARM_VST3d8_UPD	= 2566,
-	ARM_VST3q16	= 2567,
-	ARM_VST3q16_UPD	= 2569,
-	ARM_VST3q32	= 2572,
-	ARM_VST3q32_UPD	= 2574,
-	ARM_VST3q8	= 2577,
-	ARM_VST3q8_UPD	= 2579,
-	ARM_VST4LNd16	= 2582,
-	ARM_VST4LNd16_UPD	= 2585,
-	ARM_VST4LNd32	= 2586,
-	ARM_VST4LNd32_UPD	= 2589,
-	ARM_VST4LNd8	= 2590,
-	ARM_VST4LNd8_UPD	= 2593,
-	ARM_VST4LNq16	= 2594,
-	ARM_VST4LNq16_UPD	= 2597,
-	ARM_VST4LNq32	= 2598,
-	ARM_VST4LNq32_UPD	= 2601,
-	ARM_VST4d16	= 2602,
-	ARM_VST4d16_UPD	= 2605,
-	ARM_VST4d32	= 2606,
-	ARM_VST4d32_UPD	= 2609,
-	ARM_VST4d8	= 2610,
-	ARM_VST4d8_UPD	= 2613,
-	ARM_VST4q16	= 2614,
-	ARM_VST4q16_UPD	= 2616,
-	ARM_VST4q32	= 2619,
-	ARM_VST4q32_UPD	= 2621,
-	ARM_VST4q8	= 2624,
-	ARM_VST4q8_UPD	= 2626,
-	ARM_VSTMDDB_UPD	= 2629,
-	ARM_VSTMDIA	= 2630,
-	ARM_VSTMDIA_UPD	= 2631,
-	ARM_VSTMQIA	= 2632,
-	ARM_VSTMSDB_UPD	= 2633,
-	ARM_VSTMSIA	= 2634,
-	ARM_VSTMSIA_UPD	= 2635,
-	ARM_VSTRD	= 2636,
-	ARM_VSTRH	= 2637,
-	ARM_VSTRS	= 2638,
-	ARM_VSUBD	= 2639,
-	ARM_VSUBH	= 2640,
-	ARM_VSUBHNv2i32	= 2641,
-	ARM_VSUBHNv4i16	= 2642,
-	ARM_VSUBHNv8i8	= 2643,
-	ARM_VSUBLsv2i64	= 2644,
-	ARM_VSUBLsv4i32	= 2645,
-	ARM_VSUBLsv8i16	= 2646,
-	ARM_VSUBLuv2i64	= 2647,
-	ARM_VSUBLuv4i32	= 2648,
-	ARM_VSUBLuv8i16	= 2649,
-	ARM_VSUBS	= 2650,
-	ARM_VSUBWsv2i64	= 2651,
-	ARM_VSUBWsv4i32	= 2652,
-	ARM_VSUBWsv8i16	= 2653,
-	ARM_VSUBWuv2i64	= 2654,
-	ARM_VSUBWuv4i32	= 2655,
-	ARM_VSUBWuv8i16	= 2656,
-	ARM_VSUBfd	= 2657,
-	ARM_VSUBfq	= 2658,
-	ARM_VSUBhd	= 2659,
-	ARM_VSUBhq	= 2660,
-	ARM_VSUBv16i8	= 2661,
-	ARM_VSUBv1i64	= 2662,
-	ARM_VSUBv2i32	= 2663,
-	ARM_VSUBv2i64	= 2664,
-	ARM_VSUBv4i16	= 2665,
-	ARM_VSUBv4i32	= 2666,
-	ARM_VSUBv8i16	= 2667,
-	ARM_VSUBv8i8	= 2668,
-	ARM_VSWPd	= 2669,
-	ARM_VSWPq	= 2670,
-	ARM_VTBL1	= 2671,
-	ARM_VTBL2	= 2672,
-	ARM_VTBL3	= 2673,
-	ARM_VTBL4	= 2675,
-	ARM_VTBX1	= 2677,
-	ARM_VTBX2	= 2678,
-	ARM_VTBX3	= 2679,
-	ARM_VTBX4	= 2681,
-	ARM_VTOSHD	= 2683,
-	ARM_VTOSHH	= 2684,
-	ARM_VTOSHS	= 2685,
-	ARM_VTOSIRD	= 2686,
-	ARM_VTOSIRH	= 2687,
-	ARM_VTOSIRS	= 2688,
-	ARM_VTOSIZD	= 2689,
-	ARM_VTOSIZH	= 2690,
-	ARM_VTOSIZS	= 2691,
-	ARM_VTOSLD	= 2692,
-	ARM_VTOSLH	= 2693,
-	ARM_VTOSLS	= 2694,
-	ARM_VTOUHD	= 2695,
-	ARM_VTOUHH	= 2696,
-	ARM_VTOUHS	= 2697,
-	ARM_VTOUIRD	= 2698,
-	ARM_VTOUIRH	= 2699,
-	ARM_VTOUIRS	= 2700,
-	ARM_VTOUIZD	= 2701,
-	ARM_VTOUIZH	= 2702,
-	ARM_VTOUIZS	= 2703,
-	ARM_VTOULD	= 2704,
-	ARM_VTOULH	= 2705,
-	ARM_VTOULS	= 2706,
-	ARM_VTRNd16	= 2707,
-	ARM_VTRNd32	= 2708,
-	ARM_VTRNd8	= 2709,
-	ARM_VTRNq16	= 2710,
-	ARM_VTRNq32	= 2711,
-	ARM_VTRNq8	= 2712,
-	ARM_VTSTv16i8	= 2713,
-	ARM_VTSTv2i32	= 2714,
-	ARM_VTSTv4i16	= 2715,
-	ARM_VTSTv4i32	= 2716,
-	ARM_VTSTv8i16	= 2717,
-	ARM_VTSTv8i8	= 2718,
-	ARM_VUDOTD	= 2719,
-	ARM_VUDOTDI	= 2720,
-	ARM_VUDOTQ	= 2721,
-	ARM_VUDOTQI	= 2722,
-	ARM_VUHTOD	= 2723,
-	ARM_VUHTOH	= 2724,
-	ARM_VUHTOS	= 2725,
-	ARM_VUITOD	= 2726,
-	ARM_VUITOH	= 2727,
-	ARM_VUITOS	= 2728,
-	ARM_VULTOD	= 2729,
-	ARM_VULTOH	= 2730,
-	ARM_VULTOS	= 2731,
-	ARM_VUZPd16	= 2732,
-	ARM_VUZPd8	= 2733,
-	ARM_VUZPq16	= 2734,
-	ARM_VUZPq32	= 2735,
-	ARM_VUZPq8	= 2736,
-	ARM_VZIPd16	= 2737,
-	ARM_VZIPd8	= 2738,
-	ARM_VZIPq16	= 2739,
-	ARM_VZIPq32	= 2740,
-	ARM_VZIPq8	= 2741,
-	ARM_sysLDMDA	= 2742,
-	ARM_sysLDMDA_UPD	= 2743,
-	ARM_sysLDMDB	= 2744,
-	ARM_sysLDMDB_UPD	= 2745,
-	ARM_sysLDMIA	= 2746,
-	ARM_sysLDMIA_UPD	= 2747,
-	ARM_sysLDMIB	= 2748,
-	ARM_sysLDMIB_UPD	= 2749,
-	ARM_sysSTMDA	= 2750,
-	ARM_sysSTMDA_UPD	= 2751,
-	ARM_sysSTMDB	= 2752,
-	ARM_sysSTMDB_UPD	= 2753,
-	ARM_sysSTMIA	= 2754,
-	ARM_sysSTMIA_UPD	= 2755,
-	ARM_sysSTMIB	= 2756,
-	ARM_sysSTMIB_UPD	= 2757,
-	ARM_t2ADCri	= 2758,
-	ARM_t2ADCrr	= 2759,
-	ARM_t2ADCrs	= 2760,
-	ARM_t2ADDri	= 2761,
-	ARM_t2ADDri12	= 2762,
-	ARM_t2ADDrr	= 2763,
-	ARM_t2ADDrs	= 2764,
-	ARM_t2ADR	= 2765,
-	ARM_t2ANDri	= 2766,
-	ARM_t2ANDrr	= 2767,
-	ARM_t2ANDrs	= 2768,
-	ARM_t2ASRri	= 2769,
-	ARM_t2ASRrr	= 2770,
-	ARM_t2B	= 2771,
-	ARM_t2BFC	= 2772,
-	ARM_t2BFI	= 2773,
-	ARM_t2BICri	= 2774,
-	ARM_t2BICrr	= 2775,
-	ARM_t2BICrs	= 2776,
-	ARM_t2BXJ	= 2777,
-	ARM_t2Bcc	= 2778,
-	ARM_t2CDP	= 2779,
-	ARM_t2CDP2	= 2780,
-	ARM_t2CLREX	= 2781,
-	ARM_t2CLZ	= 2782,
-	ARM_t2CMNri	= 2783,
-	ARM_t2CMNzrr	= 2784,
-	ARM_t2CMNzrs	= 2785,
-	ARM_t2CMPri	= 2786,
-	ARM_t2CMPrr	= 2787,
-	ARM_t2CMPrs	= 2788,
-	ARM_t2CPS1p	= 2789,
-	ARM_t2CPS2p	= 2790,
-	ARM_t2CPS3p	= 2791,
-	ARM_t2CRC32B	= 2792,
-	ARM_t2CRC32CB	= 2793,
-	ARM_t2CRC32CH	= 2794,
-	ARM_t2CRC32CW	= 2795,
-	ARM_t2CRC32H	= 2796,
-	ARM_t2CRC32W	= 2797,
-	ARM_t2DBG	= 2798,
-	ARM_t2DCPS1	= 2799,
-	ARM_t2DCPS2	= 2800,
-	ARM_t2DCPS3	= 2801,
-	ARM_t2DMB	= 2802,
-	ARM_t2DSB	= 2803,
-	ARM_t2EORri	= 2804,
-	ARM_t2EORrr	= 2805,
-	ARM_t2EORrs	= 2806,
-	ARM_t2HINT	= 2807,
-	ARM_t2HVC	= 2808,
-	ARM_t2ISB	= 2809,
-	ARM_t2IT	= 2810,
-	ARM_t2LDA	= 2813,
-	ARM_t2LDAB	= 2814,
-	ARM_t2LDAEX	= 2815,
-	ARM_t2LDAEXB	= 2816,
-	ARM_t2LDAEXD	= 2817,
-	ARM_t2LDAEXH	= 2818,
-	ARM_t2LDAH	= 2819,
-	ARM_t2LDC2L_OFFSET	= 2820,
-	ARM_t2LDC2L_OPTION	= 2821,
-	ARM_t2LDC2L_POST	= 2822,
-	ARM_t2LDC2L_PRE	= 2823,
-	ARM_t2LDC2_OFFSET	= 2824,
-	ARM_t2LDC2_OPTION	= 2825,
-	ARM_t2LDC2_POST	= 2826,
-	ARM_t2LDC2_PRE	= 2827,
-	ARM_t2LDCL_OFFSET	= 2828,
-	ARM_t2LDCL_OPTION	= 2829,
-	ARM_t2LDCL_POST	= 2830,
-	ARM_t2LDCL_PRE	= 2831,
-	ARM_t2LDC_OFFSET	= 2832,
-	ARM_t2LDC_OPTION	= 2833,
-	ARM_t2LDC_POST	= 2834,
-	ARM_t2LDC_PRE	= 2835,
-	ARM_t2LDMDB	= 2836,
-	ARM_t2LDMDB_UPD	= 2837,
-	ARM_t2LDMIA	= 2838,
-	ARM_t2LDMIA_UPD	= 2839,
-	ARM_t2LDRBT	= 2840,
-	ARM_t2LDRB_POST	= 2841,
-	ARM_t2LDRB_PRE	= 2842,
-	ARM_t2LDRBi12	= 2843,
-	ARM_t2LDRBi8	= 2844,
-	ARM_t2LDRBpci	= 2845,
-	ARM_t2LDRBs	= 2846,
-	ARM_t2LDRD_POST	= 2847,
-	ARM_t2LDRD_PRE	= 2848,
-	ARM_t2LDRDi8	= 2849,
-	ARM_t2LDREX	= 2850,
-	ARM_t2LDREXB	= 2851,
-	ARM_t2LDREXD	= 2852,
-	ARM_t2LDREXH	= 2853,
-	ARM_t2LDRHT	= 2854,
-	ARM_t2LDRH_POST	= 2855,
-	ARM_t2LDRH_PRE	= 2856,
-	ARM_t2LDRHi12	= 2857,
-	ARM_t2LDRHi8	= 2858,
-	ARM_t2LDRHpci	= 2859,
-	ARM_t2LDRHs	= 2860,
-	ARM_t2LDRSBT	= 2861,
-	ARM_t2LDRSB_POST	= 2862,
-	ARM_t2LDRSB_PRE	= 2863,
-	ARM_t2LDRSBi12	= 2864,
-	ARM_t2LDRSBi8	= 2865,
-	ARM_t2LDRSBpci	= 2866,
-	ARM_t2LDRSBs	= 2867,
-	ARM_t2LDRSHT	= 2868,
-	ARM_t2LDRSH_POST	= 2869,
-	ARM_t2LDRSH_PRE	= 2870,
-	ARM_t2LDRSHi12	= 2871,
-	ARM_t2LDRSHi8	= 2872,
-	ARM_t2LDRSHpci	= 2873,
-	ARM_t2LDRSHs	= 2874,
-	ARM_t2LDRT	= 2875,
-	ARM_t2LDR_POST	= 2876,
-	ARM_t2LDR_PRE	= 2877,
-	ARM_t2LDRi12	= 2878,
-	ARM_t2LDRi8	= 2879,
-	ARM_t2LDRpci	= 2880,
-	ARM_t2LDRs	= 2881,
-	ARM_t2LSLri	= 2882,
-	ARM_t2LSLrr	= 2883,
-	ARM_t2LSRri	= 2884,
-	ARM_t2LSRrr	= 2885,
-	ARM_t2MCR	= 2886,
-	ARM_t2MCR2	= 2887,
-	ARM_t2MCRR	= 2888,
-	ARM_t2MCRR2	= 2889,
-	ARM_t2MLA	= 2890,
-	ARM_t2MLS	= 2891,
-	ARM_t2MOVTi16	= 2892,
-	ARM_t2MOVi	= 2893,
-	ARM_t2MOVi16	= 2894,
-	ARM_t2MOVr	= 2895,
-	ARM_t2MOVsra_flag	= 2896,
-	ARM_t2MOVsrl_flag	= 2897,
-	ARM_t2MRC	= 2898,
-	ARM_t2MRC2	= 2899,
-	ARM_t2MRRC	= 2900,
-	ARM_t2MRRC2	= 2901,
-	ARM_t2MRS_AR	= 2902,
-	ARM_t2MRS_M	= 2903,
-	ARM_t2MRSbanked	= 2904,
-	ARM_t2MRSsys_AR	= 2905,
-	ARM_t2MSR_AR	= 2906,
-	ARM_t2MSR_M	= 2907,
-	ARM_t2MSRbanked	= 2908,
-	ARM_t2MUL	= 2909,
-	ARM_t2MVNi	= 2910,
-	ARM_t2MVNr	= 2911,
-	ARM_t2MVNs	= 2912,
-	ARM_t2ORNri	= 2913,
-	ARM_t2ORNrr	= 2914,
-	ARM_t2ORNrs	= 2915,
-	ARM_t2ORRri	= 2916,
-	ARM_t2ORRrr	= 2917,
-	ARM_t2ORRrs	= 2918,
-	ARM_t2PKHBT	= 2919,
-	ARM_t2PKHTB	= 2920,
-	ARM_t2PLDWi12	= 2921,
-	ARM_t2PLDWi8	= 2922,
-	ARM_t2PLDWs	= 2923,
-	ARM_t2PLDi12	= 2924,
-	ARM_t2PLDi8	= 2925,
-	ARM_t2PLDpci	= 2926,
-	ARM_t2PLDs	= 2927,
-	ARM_t2PLIi12	= 2928,
-	ARM_t2PLIi8	= 2929,
-	ARM_t2PLIpci	= 2930,
-	ARM_t2PLIs	= 2931,
-	ARM_t2QADD	= 2932,
-	ARM_t2QADD16	= 2933,
-	ARM_t2QADD8	= 2934,
-	ARM_t2QASX	= 2935,
-	ARM_t2QDADD	= 2936,
-	ARM_t2QDSUB	= 2937,
-	ARM_t2QSAX	= 2938,
-	ARM_t2QSUB	= 2939,
-	ARM_t2QSUB16	= 2940,
-	ARM_t2QSUB8	= 2941,
-	ARM_t2RBIT	= 2942,
-	ARM_t2REV	= 2943,
-	ARM_t2REV16	= 2944,
-	ARM_t2REVSH	= 2945,
-	ARM_t2RFEDB	= 2946,
-	ARM_t2RFEDBW	= 2947,
-	ARM_t2RFEIA	= 2948,
-	ARM_t2RFEIAW	= 2949,
-	ARM_t2RORri	= 2950,
-	ARM_t2RORrr	= 2951,
-	ARM_t2RRX	= 2952,
-	ARM_t2RSBri	= 2953,
-	ARM_t2RSBrr	= 2954,
-	ARM_t2RSBrs	= 2955,
-	ARM_t2SADD16	= 2956,
-	ARM_t2SADD8	= 2957,
-	ARM_t2SASX	= 2958,
-	ARM_t2SBCri	= 2959,
-	ARM_t2SBCrr	= 2960,
-	ARM_t2SBCrs	= 2961,
-	ARM_t2SBFX	= 2962,
-	ARM_t2SDIV	= 2963,
-	ARM_t2SEL	= 2964,
-	ARM_t2SETPAN	= 2965,
-	ARM_t2SG	= 2966,
-	ARM_t2SHADD16	= 2967,
-	ARM_t2SHADD8	= 2968,
-	ARM_t2SHASX	= 2969,
-	ARM_t2SHSAX	= 2970,
-	ARM_t2SHSUB16	= 2971,
-	ARM_t2SHSUB8	= 2972,
-	ARM_t2SMC	= 2973,
-	ARM_t2SMLABB	= 2974,
-	ARM_t2SMLABT	= 2975,
-	ARM_t2SMLAD	= 2976,
-	ARM_t2SMLADX	= 2977,
-	ARM_t2SMLAL	= 2978,
-	ARM_t2SMLALBB	= 2979,
-	ARM_t2SMLALBT	= 2980,
-	ARM_t2SMLALD	= 2981,
-	ARM_t2SMLALDX	= 2982,
-	ARM_t2SMLALTB	= 2983,
-	ARM_t2SMLALTT	= 2984,
-	ARM_t2SMLATB	= 2985,
-	ARM_t2SMLATT	= 2986,
-	ARM_t2SMLAWB	= 2987,
-	ARM_t2SMLAWT	= 2988,
-	ARM_t2SMLSD	= 2989,
-	ARM_t2SMLSDX	= 2990,
-	ARM_t2SMLSLD	= 2991,
-	ARM_t2SMLSLDX	= 2992,
-	ARM_t2SMMLA	= 2993,
-	ARM_t2SMMLAR	= 2994,
-	ARM_t2SMMLS	= 2995,
-	ARM_t2SMMLSR	= 2996,
-	ARM_t2SMMUL	= 2997,
-	ARM_t2SMMULR	= 2998,
-	ARM_t2SMUAD	= 2999,
-	ARM_t2SMUADX	= 3000,
-	ARM_t2SMULBB	= 3001,
-	ARM_t2SMULBT	= 3002,
-	ARM_t2SMULL	= 3003,
-	ARM_t2SMULTB	= 3004,
-	ARM_t2SMULTT	= 3005,
-	ARM_t2SMULWB	= 3006,
-	ARM_t2SMULWT	= 3007,
-	ARM_t2SMUSD	= 3008,
-	ARM_t2SMUSDX	= 3009,
-	ARM_t2SRSDB	= 3010,
-	ARM_t2SRSDB_UPD	= 3011,
-	ARM_t2SRSIA	= 3012,
-	ARM_t2SRSIA_UPD	= 3013,
-	ARM_t2SSAT	= 3014,
-	ARM_t2SSAT16	= 3015,
-	ARM_t2SSAX	= 3016,
-	ARM_t2SSUB16	= 3017,
-	ARM_t2SSUB8	= 3018,
-	ARM_t2STC2L_OFFSET	= 3019,
-	ARM_t2STC2L_OPTION	= 3020,
-	ARM_t2STC2L_POST	= 3021,
-	ARM_t2STC2L_PRE	= 3022,
-	ARM_t2STC2_OFFSET	= 3023,
-	ARM_t2STC2_OPTION	= 3024,
-	ARM_t2STC2_POST	= 3025,
-	ARM_t2STC2_PRE	= 3026,
-	ARM_t2STCL_OFFSET	= 3027,
-	ARM_t2STCL_OPTION	= 3028,
-	ARM_t2STCL_POST	= 3029,
-	ARM_t2STCL_PRE	= 3030,
-	ARM_t2STC_OFFSET	= 3031,
-	ARM_t2STC_OPTION	= 3032,
-	ARM_t2STC_POST	= 3033,
-	ARM_t2STC_PRE	= 3034,
-	ARM_t2STL	= 3035,
-	ARM_t2STLB	= 3036,
-	ARM_t2STLEX	= 3037,
-	ARM_t2STLEXB	= 3038,
-	ARM_t2STLEXD	= 3039,
-	ARM_t2STLEXH	= 3040,
-	ARM_t2STLH	= 3041,
-	ARM_t2STMDB	= 3042,
-	ARM_t2STMDB_UPD	= 3043,
-	ARM_t2STMIA	= 3044,
-	ARM_t2STMIA_UPD	= 3045,
-	ARM_t2STRBT	= 3046,
-	ARM_t2STRB_POST	= 3047,
-	ARM_t2STRB_PRE	= 3048,
-	ARM_t2STRBi12	= 3049,
-	ARM_t2STRBi8	= 3050,
-	ARM_t2STRBs	= 3051,
-	ARM_t2STRD_POST	= 3052,
-	ARM_t2STRD_PRE	= 3053,
-	ARM_t2STRDi8	= 3054,
-	ARM_t2STREX	= 3055,
-	ARM_t2STREXB	= 3056,
-	ARM_t2STREXD	= 3057,
-	ARM_t2STREXH	= 3058,
-	ARM_t2STRHT	= 3059,
-	ARM_t2STRH_POST	= 3060,
-	ARM_t2STRH_PRE	= 3061,
-	ARM_t2STRHi12	= 3062,
-	ARM_t2STRHi8	= 3063,
-	ARM_t2STRHs	= 3064,
-	ARM_t2STRT	= 3065,
-	ARM_t2STR_POST	= 3066,
-	ARM_t2STR_PRE	= 3067,
-	ARM_t2STRi12	= 3068,
-	ARM_t2STRi8	= 3069,
-	ARM_t2STRs	= 3070,
-	ARM_t2SUBS_PC_LR	= 3071,
-	ARM_t2SUBri	= 3072,
-	ARM_t2SUBri12	= 3073,
-	ARM_t2SUBrr	= 3074,
-	ARM_t2SUBrs	= 3075,
-	ARM_t2SXTAB	= 3076,
-	ARM_t2SXTAB16	= 3077,
-	ARM_t2SXTAH	= 3078,
-	ARM_t2SXTB	= 3079,
-	ARM_t2SXTB16	= 3080,
-	ARM_t2SXTH	= 3081,
-	ARM_t2TBB	= 3082,
-	ARM_t2TBH	= 3083,
-	ARM_t2TEQri	= 3084,
-	ARM_t2TEQrr	= 3085,
-	ARM_t2TEQrs	= 3086,
-	ARM_t2TSB	= 3087,
-	ARM_t2TSTri	= 3088,
-	ARM_t2TSTrr	= 3089,
-	ARM_t2TSTrs	= 3090,
-	ARM_t2TT	= 3091,
-	ARM_t2TTA	= 3092,
-	ARM_t2TTAT	= 3093,
-	ARM_t2TTT	= 3094,
-	ARM_t2UADD16	= 3095,
-	ARM_t2UADD8	= 3096,
-	ARM_t2UASX	= 3097,
-	ARM_t2UBFX	= 3098,
-	ARM_t2UDF	= 3099,
-	ARM_t2UDIV	= 3100,
-	ARM_t2UHADD16	= 3101,
-	ARM_t2UHADD8	= 3102,
-	ARM_t2UHASX	= 3103,
-	ARM_t2UHSAX	= 3104,
-	ARM_t2UHSUB16	= 3105,
-	ARM_t2UHSUB8	= 3106,
-	ARM_t2UMAAL	= 3107,
-	ARM_t2UMLAL	= 3108,
-	ARM_t2UMULL	= 3109,
-	ARM_t2UQADD16	= 3110,
-	ARM_t2UQADD8	= 3111,
-	ARM_t2UQASX	= 3112,
-	ARM_t2UQSAX	= 3113,
-	ARM_t2UQSUB16	= 3114,
-	ARM_t2UQSUB8	= 3115,
-	ARM_t2USAD8	= 3116,
-	ARM_t2USADA8	= 3117,
-	ARM_t2USAT	= 3118,
-	ARM_t2USAT16	= 3119,
-	ARM_t2USAX	= 3120,
-	ARM_t2USUB16	= 3121,
-	ARM_t2USUB8	= 3122,
-	ARM_t2UXTAB	= 3123,
-	ARM_t2UXTAB16	= 3124,
-	ARM_t2UXTAH	= 3125,
-	ARM_t2UXTB	= 3126,
-	ARM_t2UXTB16	= 3127,
-	ARM_t2UXTH	= 3128,
-	ARM_tADC	= 3129,
-	ARM_tADDhirr	= 3130,
-	ARM_tADDi3	= 3131,
-	ARM_tADDi8	= 3132,
-	ARM_tADDrSP	= 3133,
-	ARM_tADDrSPi	= 3134,
-	ARM_tADDrr	= 3135,
-	ARM_tADDspi	= 3136,
-	ARM_tADDspr	= 3137,
-	ARM_tADR	= 3138,
-	ARM_tAND	= 3139,
-	ARM_tASRri	= 3140,
-	ARM_tASRrr	= 3141,
-	ARM_tB	= 3142,
-	ARM_tBIC	= 3143,
-	ARM_tBKPT	= 3144,
-	ARM_tBL	= 3145,
-	ARM_tBLXNSr	= 3146,
-	ARM_tBLXi	= 3147,
-	ARM_tBLXr	= 3148,
-	ARM_tBX	= 3149,
-	ARM_tBXNS	= 3150,
-	ARM_tBcc	= 3151,
-	ARM_tCBNZ	= 3152,
-	ARM_tCBZ	= 3153,
-	ARM_tCMNz	= 3154,
-	ARM_tCMPhir	= 3155,
-	ARM_tCMPi8	= 3156,
-	ARM_tCMPr	= 3157,
-	ARM_tCPS	= 3158,
-	ARM_tEOR	= 3159,
-	ARM_tHINT	= 3160,
-	ARM_tHLT	= 3161,
-	ARM_tLDMIA	= 3165,
-	ARM_tLDRBi	= 3166,
-	ARM_tLDRBr	= 3167,
-	ARM_tLDRHi	= 3168,
-	ARM_tLDRHr	= 3169,
-	ARM_tLDRSB	= 3170,
-	ARM_tLDRSH	= 3171,
-	ARM_tLDRi	= 3172,
-	ARM_tLDRpci	= 3173,
-	ARM_tLDRr	= 3174,
-	ARM_tLDRspi	= 3175,
-	ARM_tLSLri	= 3176,
-	ARM_tLSLrr	= 3177,
-	ARM_tLSRri	= 3178,
-	ARM_tLSRrr	= 3179,
-	ARM_tMOVSr	= 3180,
-	ARM_tMOVi8	= 3181,
-	ARM_tMOVr	= 3182,
-	ARM_tMUL	= 3183,
-	ARM_tMVN	= 3184,
-	ARM_tORR	= 3185,
-	ARM_tPICADD	= 3186,
-	ARM_tPOP	= 3187,
-	ARM_tPUSH	= 3188,
-	ARM_tREV	= 3189,
-	ARM_tREV16	= 3190,
-	ARM_tREVSH	= 3191,
-	ARM_tROR	= 3192,
-	ARM_tRSB	= 3193,
-	ARM_tSBC	= 3194,
-	ARM_tSETEND	= 3195,
-	ARM_tSTMIA_UPD	= 3196,
-	ARM_tSTRBi	= 3197,
-	ARM_tSTRBr	= 3198,
-	ARM_tSTRHi	= 3199,
-	ARM_tSTRHr	= 3200,
-	ARM_tSTRi	= 3201,
-	ARM_tSTRr	= 3202,
-	ARM_tSTRspi	= 3203,
-	ARM_tSUBi3	= 3204,
-	ARM_tSUBi8	= 3205,
-	ARM_tSUBrr	= 3206,
-	ARM_tSUBspi	= 3207,
-	ARM_tSVC	= 3208,
-	ARM_tSXTB	= 3209,
-	ARM_tSXTH	= 3210,
-	ARM_tTRAP	= 3211,
-	ARM_tTST	= 3212,
-	ARM_tUDF	= 3213,
-	ARM_tUXTB	= 3214,
-	ARM_tUXTH	= 3215,
-	ARM_t__brkdiv0	= 3216,
-	ARM_INSTRUCTION_LIST_END = 3217
-};
+  enum {
+    ARM_PHI	= 0,
+    ARM_INLINEASM	= 1,
+    ARM_INLINEASM_BR	= 2,
+    ARM_CFI_INSTRUCTION	= 3,
+    ARM_EH_LABEL	= 4,
+    ARM_GC_LABEL	= 5,
+    ARM_ANNOTATION_LABEL	= 6,
+    ARM_KILL	= 7,
+    ARM_EXTRACT_SUBREG	= 8,
+    ARM_INSERT_SUBREG	= 9,
+    ARM_IMPLICIT_DEF	= 10,
+    ARM_SUBREG_TO_REG	= 11,
+    ARM_COPY_TO_REGCLASS	= 12,
+    ARM_DBG_VALUE	= 13,
+    ARM_DBG_VALUE_LIST	= 14,
+    ARM_DBG_INSTR_REF	= 15,
+    ARM_DBG_PHI	= 16,
+    ARM_DBG_LABEL	= 17,
+    ARM_REG_SEQUENCE	= 18,
+    ARM_COPY	= 19,
+    ARM_BUNDLE	= 20,
+    ARM_LIFETIME_START	= 21,
+    ARM_LIFETIME_END	= 22,
+    ARM_PSEUDO_PROBE	= 23,
+    ARM_ARITH_FENCE	= 24,
+    ARM_STACKMAP	= 25,
+    ARM_FENTRY_CALL	= 26,
+    ARM_PATCHPOINT	= 27,
+    ARM_LOAD_STACK_GUARD	= 28,
+    ARM_PREALLOCATED_SETUP	= 29,
+    ARM_PREALLOCATED_ARG	= 30,
+    ARM_STATEPOINT	= 31,
+    ARM_LOCAL_ESCAPE	= 32,
+    ARM_FAULTING_OP	= 33,
+    ARM_PATCHABLE_OP	= 34,
+    ARM_PATCHABLE_FUNCTION_ENTER	= 35,
+    ARM_PATCHABLE_RET	= 36,
+    ARM_PATCHABLE_FUNCTION_EXIT	= 37,
+    ARM_PATCHABLE_TAIL_CALL	= 38,
+    ARM_PATCHABLE_EVENT_CALL	= 39,
+    ARM_PATCHABLE_TYPED_EVENT_CALL	= 40,
+    ARM_ICALL_BRANCH_FUNNEL	= 41,
+    ARM_MEMBARRIER	= 42,
+    ARM_G_ASSERT_SEXT	= 43,
+    ARM_G_ASSERT_ZEXT	= 44,
+    ARM_G_ASSERT_ALIGN	= 45,
+    ARM_G_ADD	= 46,
+    ARM_G_SUB	= 47,
+    ARM_G_MUL	= 48,
+    ARM_G_SDIV	= 49,
+    ARM_G_UDIV	= 50,
+    ARM_G_SREM	= 51,
+    ARM_G_UREM	= 52,
+    ARM_G_SDIVREM	= 53,
+    ARM_G_UDIVREM	= 54,
+    ARM_G_AND	= 55,
+    ARM_G_OR	= 56,
+    ARM_G_XOR	= 57,
+    ARM_G_IMPLICIT_DEF	= 58,
+    ARM_G_PHI	= 59,
+    ARM_G_FRAME_INDEX	= 60,
+    ARM_G_GLOBAL_VALUE	= 61,
+    ARM_G_EXTRACT	= 62,
+    ARM_G_UNMERGE_VALUES	= 63,
+    ARM_G_INSERT	= 64,
+    ARM_G_MERGE_VALUES	= 65,
+    ARM_G_BUILD_VECTOR	= 66,
+    ARM_G_BUILD_VECTOR_TRUNC	= 67,
+    ARM_G_CONCAT_VECTORS	= 68,
+    ARM_G_PTRTOINT	= 69,
+    ARM_G_INTTOPTR	= 70,
+    ARM_G_BITCAST	= 71,
+    ARM_G_FREEZE	= 72,
+    ARM_G_INTRINSIC_FPTRUNC_ROUND	= 73,
+    ARM_G_INTRINSIC_TRUNC	= 74,
+    ARM_G_INTRINSIC_ROUND	= 75,
+    ARM_G_INTRINSIC_LRINT	= 76,
+    ARM_G_INTRINSIC_ROUNDEVEN	= 77,
+    ARM_G_READCYCLECOUNTER	= 78,
+    ARM_G_LOAD	= 79,
+    ARM_G_SEXTLOAD	= 80,
+    ARM_G_ZEXTLOAD	= 81,
+    ARM_G_INDEXED_LOAD	= 82,
+    ARM_G_INDEXED_SEXTLOAD	= 83,
+    ARM_G_INDEXED_ZEXTLOAD	= 84,
+    ARM_G_STORE	= 85,
+    ARM_G_INDEXED_STORE	= 86,
+    ARM_G_ATOMIC_CMPXCHG_WITH_SUCCESS	= 87,
+    ARM_G_ATOMIC_CMPXCHG	= 88,
+    ARM_G_ATOMICRMW_XCHG	= 89,
+    ARM_G_ATOMICRMW_ADD	= 90,
+    ARM_G_ATOMICRMW_SUB	= 91,
+    ARM_G_ATOMICRMW_AND	= 92,
+    ARM_G_ATOMICRMW_NAND	= 93,
+    ARM_G_ATOMICRMW_OR	= 94,
+    ARM_G_ATOMICRMW_XOR	= 95,
+    ARM_G_ATOMICRMW_MAX	= 96,
+    ARM_G_ATOMICRMW_MIN	= 97,
+    ARM_G_ATOMICRMW_UMAX	= 98,
+    ARM_G_ATOMICRMW_UMIN	= 99,
+    ARM_G_ATOMICRMW_FADD	= 100,
+    ARM_G_ATOMICRMW_FSUB	= 101,
+    ARM_G_ATOMICRMW_FMAX	= 102,
+    ARM_G_ATOMICRMW_FMIN	= 103,
+    ARM_G_ATOMICRMW_UINC_WRAP	= 104,
+    ARM_G_ATOMICRMW_UDEC_WRAP	= 105,
+    ARM_G_FENCE	= 106,
+    ARM_G_BRCOND	= 107,
+    ARM_G_BRINDIRECT	= 108,
+    ARM_G_INVOKE_REGION_START	= 109,
+    ARM_G_INTRINSIC	= 110,
+    ARM_G_INTRINSIC_W_SIDE_EFFECTS	= 111,
+    ARM_G_ANYEXT	= 112,
+    ARM_G_TRUNC	= 113,
+    ARM_G_CONSTANT	= 114,
+    ARM_G_FCONSTANT	= 115,
+    ARM_G_VASTART	= 116,
+    ARM_G_VAARG	= 117,
+    ARM_G_SEXT	= 118,
+    ARM_G_SEXT_INREG	= 119,
+    ARM_G_ZEXT	= 120,
+    ARM_G_SHL	= 121,
+    ARM_G_LSHR	= 122,
+    ARM_G_ASHR	= 123,
+    ARM_G_FSHL	= 124,
+    ARM_G_FSHR	= 125,
+    ARM_G_ROTR	= 126,
+    ARM_G_ROTL	= 127,
+    ARM_G_ICMP	= 128,
+    ARM_G_FCMP	= 129,
+    ARM_G_SELECT	= 130,
+    ARM_G_UADDO	= 131,
+    ARM_G_UADDE	= 132,
+    ARM_G_USUBO	= 133,
+    ARM_G_USUBE	= 134,
+    ARM_G_SADDO	= 135,
+    ARM_G_SADDE	= 136,
+    ARM_G_SSUBO	= 137,
+    ARM_G_SSUBE	= 138,
+    ARM_G_UMULO	= 139,
+    ARM_G_SMULO	= 140,
+    ARM_G_UMULH	= 141,
+    ARM_G_SMULH	= 142,
+    ARM_G_UADDSAT	= 143,
+    ARM_G_SADDSAT	= 144,
+    ARM_G_USUBSAT	= 145,
+    ARM_G_SSUBSAT	= 146,
+    ARM_G_USHLSAT	= 147,
+    ARM_G_SSHLSAT	= 148,
+    ARM_G_SMULFIX	= 149,
+    ARM_G_UMULFIX	= 150,
+    ARM_G_SMULFIXSAT	= 151,
+    ARM_G_UMULFIXSAT	= 152,
+    ARM_G_SDIVFIX	= 153,
+    ARM_G_UDIVFIX	= 154,
+    ARM_G_SDIVFIXSAT	= 155,
+    ARM_G_UDIVFIXSAT	= 156,
+    ARM_G_FADD	= 157,
+    ARM_G_FSUB	= 158,
+    ARM_G_FMUL	= 159,
+    ARM_G_FMA	= 160,
+    ARM_G_FMAD	= 161,
+    ARM_G_FDIV	= 162,
+    ARM_G_FREM	= 163,
+    ARM_G_FPOW	= 164,
+    ARM_G_FPOWI	= 165,
+    ARM_G_FEXP	= 166,
+    ARM_G_FEXP2	= 167,
+    ARM_G_FLOG	= 168,
+    ARM_G_FLOG2	= 169,
+    ARM_G_FLOG10	= 170,
+    ARM_G_FNEG	= 171,
+    ARM_G_FPEXT	= 172,
+    ARM_G_FPTRUNC	= 173,
+    ARM_G_FPTOSI	= 174,
+    ARM_G_FPTOUI	= 175,
+    ARM_G_SITOFP	= 176,
+    ARM_G_UITOFP	= 177,
+    ARM_G_FABS	= 178,
+    ARM_G_FCOPYSIGN	= 179,
+    ARM_G_IS_FPCLASS	= 180,
+    ARM_G_FCANONICALIZE	= 181,
+    ARM_G_FMINNUM	= 182,
+    ARM_G_FMAXNUM	= 183,
+    ARM_G_FMINNUM_IEEE	= 184,
+    ARM_G_FMAXNUM_IEEE	= 185,
+    ARM_G_FMINIMUM	= 186,
+    ARM_G_FMAXIMUM	= 187,
+    ARM_G_PTR_ADD	= 188,
+    ARM_G_PTRMASK	= 189,
+    ARM_G_SMIN	= 190,
+    ARM_G_SMAX	= 191,
+    ARM_G_UMIN	= 192,
+    ARM_G_UMAX	= 193,
+    ARM_G_ABS	= 194,
+    ARM_G_LROUND	= 195,
+    ARM_G_LLROUND	= 196,
+    ARM_G_BR	= 197,
+    ARM_G_BRJT	= 198,
+    ARM_G_INSERT_VECTOR_ELT	= 199,
+    ARM_G_EXTRACT_VECTOR_ELT	= 200,
+    ARM_G_SHUFFLE_VECTOR	= 201,
+    ARM_G_CTTZ	= 202,
+    ARM_G_CTTZ_ZERO_UNDEF	= 203,
+    ARM_G_CTLZ	= 204,
+    ARM_G_CTLZ_ZERO_UNDEF	= 205,
+    ARM_G_CTPOP	= 206,
+    ARM_G_BSWAP	= 207,
+    ARM_G_BITREVERSE	= 208,
+    ARM_G_FCEIL	= 209,
+    ARM_G_FCOS	= 210,
+    ARM_G_FSIN	= 211,
+    ARM_G_FSQRT	= 212,
+    ARM_G_FFLOOR	= 213,
+    ARM_G_FRINT	= 214,
+    ARM_G_FNEARBYINT	= 215,
+    ARM_G_ADDRSPACE_CAST	= 216,
+    ARM_G_BLOCK_ADDR	= 217,
+    ARM_G_JUMP_TABLE	= 218,
+    ARM_G_DYN_STACKALLOC	= 219,
+    ARM_G_STRICT_FADD	= 220,
+    ARM_G_STRICT_FSUB	= 221,
+    ARM_G_STRICT_FMUL	= 222,
+    ARM_G_STRICT_FDIV	= 223,
+    ARM_G_STRICT_FREM	= 224,
+    ARM_G_STRICT_FMA	= 225,
+    ARM_G_STRICT_FSQRT	= 226,
+    ARM_G_READ_REGISTER	= 227,
+    ARM_G_WRITE_REGISTER	= 228,
+    ARM_G_MEMCPY	= 229,
+    ARM_G_MEMCPY_INLINE	= 230,
+    ARM_G_MEMMOVE	= 231,
+    ARM_G_MEMSET	= 232,
+    ARM_G_BZERO	= 233,
+    ARM_G_VECREDUCE_SEQ_FADD	= 234,
+    ARM_G_VECREDUCE_SEQ_FMUL	= 235,
+    ARM_G_VECREDUCE_FADD	= 236,
+    ARM_G_VECREDUCE_FMUL	= 237,
+    ARM_G_VECREDUCE_FMAX	= 238,
+    ARM_G_VECREDUCE_FMIN	= 239,
+    ARM_G_VECREDUCE_ADD	= 240,
+    ARM_G_VECREDUCE_MUL	= 241,
+    ARM_G_VECREDUCE_AND	= 242,
+    ARM_G_VECREDUCE_OR	= 243,
+    ARM_G_VECREDUCE_XOR	= 244,
+    ARM_G_VECREDUCE_SMAX	= 245,
+    ARM_G_VECREDUCE_SMIN	= 246,
+    ARM_G_VECREDUCE_UMAX	= 247,
+    ARM_G_VECREDUCE_UMIN	= 248,
+    ARM_G_SBFX	= 249,
+    ARM_G_UBFX	= 250,
+    ARM_ABS	= 251,
+    ARM_ADDSri	= 252,
+    ARM_ADDSrr	= 253,
+    ARM_ADDSrsi	= 254,
+    ARM_ADDSrsr	= 255,
+    ARM_ADJCALLSTACKDOWN	= 256,
+    ARM_ADJCALLSTACKUP	= 257,
+    ARM_ASRi	= 258,
+    ARM_ASRr	= 259,
+    ARM_B	= 260,
+    ARM_BCCZi64	= 261,
+    ARM_BCCi64	= 262,
+    ARM_BLX_noip	= 263,
+    ARM_BLX_pred_noip	= 264,
+    ARM_BL_PUSHLR	= 265,
+    ARM_BMOVPCB_CALL	= 266,
+    ARM_BMOVPCRX_CALL	= 267,
+    ARM_BR_JTadd	= 268,
+    ARM_BR_JTm_i12	= 269,
+    ARM_BR_JTm_rs	= 270,
+    ARM_BR_JTr	= 271,
+    ARM_BX_CALL	= 272,
+    ARM_CMP_SWAP_16	= 273,
+    ARM_CMP_SWAP_32	= 274,
+    ARM_CMP_SWAP_64	= 275,
+    ARM_CMP_SWAP_8	= 276,
+    ARM_CONSTPOOL_ENTRY	= 277,
+    ARM_COPY_STRUCT_BYVAL_I32	= 278,
+    ARM_ITasm	= 279,
+    ARM_Int_eh_sjlj_dispatchsetup	= 280,
+    ARM_Int_eh_sjlj_longjmp	= 281,
+    ARM_Int_eh_sjlj_setjmp	= 282,
+    ARM_Int_eh_sjlj_setjmp_nofp	= 283,
+    ARM_Int_eh_sjlj_setup_dispatch	= 284,
+    ARM_JUMPTABLE_ADDRS	= 285,
+    ARM_JUMPTABLE_INSTS	= 286,
+    ARM_JUMPTABLE_TBB	= 287,
+    ARM_JUMPTABLE_TBH	= 288,
+    ARM_LDMIA_RET	= 289,
+    ARM_LDRBT_POST	= 290,
+    ARM_LDRConstPool	= 291,
+    ARM_LDRHTii	= 292,
+    ARM_LDRLIT_ga_abs	= 293,
+    ARM_LDRLIT_ga_pcrel	= 294,
+    ARM_LDRLIT_ga_pcrel_ldr	= 295,
+    ARM_LDRSBTii	= 296,
+    ARM_LDRSHTii	= 297,
+    ARM_LDRT_POST	= 298,
+    ARM_LEApcrel	= 299,
+    ARM_LEApcrelJT	= 300,
+    ARM_LOADDUAL	= 301,
+    ARM_LSLi	= 302,
+    ARM_LSLr	= 303,
+    ARM_LSRi	= 304,
+    ARM_LSRr	= 305,
+    ARM_MEMCPY	= 306,
+    ARM_MLAv5	= 307,
+    ARM_MOVCCi	= 308,
+    ARM_MOVCCi16	= 309,
+    ARM_MOVCCi32imm	= 310,
+    ARM_MOVCCr	= 311,
+    ARM_MOVCCsi	= 312,
+    ARM_MOVCCsr	= 313,
+    ARM_MOVPCRX	= 314,
+    ARM_MOVTi16_ga_pcrel	= 315,
+    ARM_MOV_ga_pcrel	= 316,
+    ARM_MOV_ga_pcrel_ldr	= 317,
+    ARM_MOVi16_ga_pcrel	= 318,
+    ARM_MOVi32imm	= 319,
+    ARM_MOVsra_flag	= 320,
+    ARM_MOVsrl_flag	= 321,
+    ARM_MQPRCopy	= 322,
+    ARM_MQQPRLoad	= 323,
+    ARM_MQQPRStore	= 324,
+    ARM_MQQQQPRLoad	= 325,
+    ARM_MQQQQPRStore	= 326,
+    ARM_MULv5	= 327,
+    ARM_MVE_MEMCPYLOOPINST	= 328,
+    ARM_MVE_MEMSETLOOPINST	= 329,
+    ARM_MVNCCi	= 330,
+    ARM_PICADD	= 331,
+    ARM_PICLDR	= 332,
+    ARM_PICLDRB	= 333,
+    ARM_PICLDRH	= 334,
+    ARM_PICLDRSB	= 335,
+    ARM_PICLDRSH	= 336,
+    ARM_PICSTR	= 337,
+    ARM_PICSTRB	= 338,
+    ARM_PICSTRH	= 339,
+    ARM_RORi	= 340,
+    ARM_RORr	= 341,
+    ARM_RRX	= 342,
+    ARM_RRXi	= 343,
+    ARM_RSBSri	= 344,
+    ARM_RSBSrsi	= 345,
+    ARM_RSBSrsr	= 346,
+    ARM_SEH_EpilogEnd	= 347,
+    ARM_SEH_EpilogStart	= 348,
+    ARM_SEH_Nop	= 349,
+    ARM_SEH_Nop_Ret	= 350,
+    ARM_SEH_PrologEnd	= 351,
+    ARM_SEH_SaveFRegs	= 352,
+    ARM_SEH_SaveLR	= 353,
+    ARM_SEH_SaveRegs	= 354,
+    ARM_SEH_SaveRegs_Ret	= 355,
+    ARM_SEH_SaveSP	= 356,
+    ARM_SEH_StackAlloc	= 357,
+    ARM_SMLALv5	= 358,
+    ARM_SMULLv5	= 359,
+    ARM_SPACE	= 360,
+    ARM_STOREDUAL	= 361,
+    ARM_STRBT_POST	= 362,
+    ARM_STRBi_preidx	= 363,
+    ARM_STRBr_preidx	= 364,
+    ARM_STRH_preidx	= 365,
+    ARM_STRT_POST	= 366,
+    ARM_STRi_preidx	= 367,
+    ARM_STRr_preidx	= 368,
+    ARM_SUBS_PC_LR	= 369,
+    ARM_SUBSri	= 370,
+    ARM_SUBSrr	= 371,
+    ARM_SUBSrsi	= 372,
+    ARM_SUBSrsr	= 373,
+    ARM_SpeculationBarrierISBDSBEndBB	= 374,
+    ARM_SpeculationBarrierSBEndBB	= 375,
+    ARM_TAILJMPd	= 376,
+    ARM_TAILJMPr	= 377,
+    ARM_TAILJMPr4	= 378,
+    ARM_TCRETURNdi	= 379,
+    ARM_TCRETURNri	= 380,
+    ARM_TPsoft	= 381,
+    ARM_UMLALv5	= 382,
+    ARM_UMULLv5	= 383,
+    ARM_VLD1LNdAsm_16	= 384,
+    ARM_VLD1LNdAsm_32	= 385,
+    ARM_VLD1LNdAsm_8	= 386,
+    ARM_VLD1LNdWB_fixed_Asm_16	= 387,
+    ARM_VLD1LNdWB_fixed_Asm_32	= 388,
+    ARM_VLD1LNdWB_fixed_Asm_8	= 389,
+    ARM_VLD1LNdWB_register_Asm_16	= 390,
+    ARM_VLD1LNdWB_register_Asm_32	= 391,
+    ARM_VLD1LNdWB_register_Asm_8	= 392,
+    ARM_VLD2LNdAsm_16	= 393,
+    ARM_VLD2LNdAsm_32	= 394,
+    ARM_VLD2LNdAsm_8	= 395,
+    ARM_VLD2LNdWB_fixed_Asm_16	= 396,
+    ARM_VLD2LNdWB_fixed_Asm_32	= 397,
+    ARM_VLD2LNdWB_fixed_Asm_8	= 398,
+    ARM_VLD2LNdWB_register_Asm_16	= 399,
+    ARM_VLD2LNdWB_register_Asm_32	= 400,
+    ARM_VLD2LNdWB_register_Asm_8	= 401,
+    ARM_VLD2LNqAsm_16	= 402,
+    ARM_VLD2LNqAsm_32	= 403,
+    ARM_VLD2LNqWB_fixed_Asm_16	= 404,
+    ARM_VLD2LNqWB_fixed_Asm_32	= 405,
+    ARM_VLD2LNqWB_register_Asm_16	= 406,
+    ARM_VLD2LNqWB_register_Asm_32	= 407,
+    ARM_VLD3DUPdAsm_16	= 408,
+    ARM_VLD3DUPdAsm_32	= 409,
+    ARM_VLD3DUPdAsm_8	= 410,
+    ARM_VLD3DUPdWB_fixed_Asm_16	= 411,
+    ARM_VLD3DUPdWB_fixed_Asm_32	= 412,
+    ARM_VLD3DUPdWB_fixed_Asm_8	= 413,
+    ARM_VLD3DUPdWB_register_Asm_16	= 414,
+    ARM_VLD3DUPdWB_register_Asm_32	= 415,
+    ARM_VLD3DUPdWB_register_Asm_8	= 416,
+    ARM_VLD3DUPqAsm_16	= 417,
+    ARM_VLD3DUPqAsm_32	= 418,
+    ARM_VLD3DUPqAsm_8	= 419,
+    ARM_VLD3DUPqWB_fixed_Asm_16	= 420,
+    ARM_VLD3DUPqWB_fixed_Asm_32	= 421,
+    ARM_VLD3DUPqWB_fixed_Asm_8	= 422,
+    ARM_VLD3DUPqWB_register_Asm_16	= 423,
+    ARM_VLD3DUPqWB_register_Asm_32	= 424,
+    ARM_VLD3DUPqWB_register_Asm_8	= 425,
+    ARM_VLD3LNdAsm_16	= 426,
+    ARM_VLD3LNdAsm_32	= 427,
+    ARM_VLD3LNdAsm_8	= 428,
+    ARM_VLD3LNdWB_fixed_Asm_16	= 429,
+    ARM_VLD3LNdWB_fixed_Asm_32	= 430,
+    ARM_VLD3LNdWB_fixed_Asm_8	= 431,
+    ARM_VLD3LNdWB_register_Asm_16	= 432,
+    ARM_VLD3LNdWB_register_Asm_32	= 433,
+    ARM_VLD3LNdWB_register_Asm_8	= 434,
+    ARM_VLD3LNqAsm_16	= 435,
+    ARM_VLD3LNqAsm_32	= 436,
+    ARM_VLD3LNqWB_fixed_Asm_16	= 437,
+    ARM_VLD3LNqWB_fixed_Asm_32	= 438,
+    ARM_VLD3LNqWB_register_Asm_16	= 439,
+    ARM_VLD3LNqWB_register_Asm_32	= 440,
+    ARM_VLD3dAsm_16	= 441,
+    ARM_VLD3dAsm_32	= 442,
+    ARM_VLD3dAsm_8	= 443,
+    ARM_VLD3dWB_fixed_Asm_16	= 444,
+    ARM_VLD3dWB_fixed_Asm_32	= 445,
+    ARM_VLD3dWB_fixed_Asm_8	= 446,
+    ARM_VLD3dWB_register_Asm_16	= 447,
+    ARM_VLD3dWB_register_Asm_32	= 448,
+    ARM_VLD3dWB_register_Asm_8	= 449,
+    ARM_VLD3qAsm_16	= 450,
+    ARM_VLD3qAsm_32	= 451,
+    ARM_VLD3qAsm_8	= 452,
+    ARM_VLD3qWB_fixed_Asm_16	= 453,
+    ARM_VLD3qWB_fixed_Asm_32	= 454,
+    ARM_VLD3qWB_fixed_Asm_8	= 455,
+    ARM_VLD3qWB_register_Asm_16	= 456,
+    ARM_VLD3qWB_register_Asm_32	= 457,
+    ARM_VLD3qWB_register_Asm_8	= 458,
+    ARM_VLD4DUPdAsm_16	= 459,
+    ARM_VLD4DUPdAsm_32	= 460,
+    ARM_VLD4DUPdAsm_8	= 461,
+    ARM_VLD4DUPdWB_fixed_Asm_16	= 462,
+    ARM_VLD4DUPdWB_fixed_Asm_32	= 463,
+    ARM_VLD4DUPdWB_fixed_Asm_8	= 464,
+    ARM_VLD4DUPdWB_register_Asm_16	= 465,
+    ARM_VLD4DUPdWB_register_Asm_32	= 466,
+    ARM_VLD4DUPdWB_register_Asm_8	= 467,
+    ARM_VLD4DUPqAsm_16	= 468,
+    ARM_VLD4DUPqAsm_32	= 469,
+    ARM_VLD4DUPqAsm_8	= 470,
+    ARM_VLD4DUPqWB_fixed_Asm_16	= 471,
+    ARM_VLD4DUPqWB_fixed_Asm_32	= 472,
+    ARM_VLD4DUPqWB_fixed_Asm_8	= 473,
+    ARM_VLD4DUPqWB_register_Asm_16	= 474,
+    ARM_VLD4DUPqWB_register_Asm_32	= 475,
+    ARM_VLD4DUPqWB_register_Asm_8	= 476,
+    ARM_VLD4LNdAsm_16	= 477,
+    ARM_VLD4LNdAsm_32	= 478,
+    ARM_VLD4LNdAsm_8	= 479,
+    ARM_VLD4LNdWB_fixed_Asm_16	= 480,
+    ARM_VLD4LNdWB_fixed_Asm_32	= 481,
+    ARM_VLD4LNdWB_fixed_Asm_8	= 482,
+    ARM_VLD4LNdWB_register_Asm_16	= 483,
+    ARM_VLD4LNdWB_register_Asm_32	= 484,
+    ARM_VLD4LNdWB_register_Asm_8	= 485,
+    ARM_VLD4LNqAsm_16	= 486,
+    ARM_VLD4LNqAsm_32	= 487,
+    ARM_VLD4LNqWB_fixed_Asm_16	= 488,
+    ARM_VLD4LNqWB_fixed_Asm_32	= 489,
+    ARM_VLD4LNqWB_register_Asm_16	= 490,
+    ARM_VLD4LNqWB_register_Asm_32	= 491,
+    ARM_VLD4dAsm_16	= 492,
+    ARM_VLD4dAsm_32	= 493,
+    ARM_VLD4dAsm_8	= 494,
+    ARM_VLD4dWB_fixed_Asm_16	= 495,
+    ARM_VLD4dWB_fixed_Asm_32	= 496,
+    ARM_VLD4dWB_fixed_Asm_8	= 497,
+    ARM_VLD4dWB_register_Asm_16	= 498,
+    ARM_VLD4dWB_register_Asm_32	= 499,
+    ARM_VLD4dWB_register_Asm_8	= 500,
+    ARM_VLD4qAsm_16	= 501,
+    ARM_VLD4qAsm_32	= 502,
+    ARM_VLD4qAsm_8	= 503,
+    ARM_VLD4qWB_fixed_Asm_16	= 504,
+    ARM_VLD4qWB_fixed_Asm_32	= 505,
+    ARM_VLD4qWB_fixed_Asm_8	= 506,
+    ARM_VLD4qWB_register_Asm_16	= 507,
+    ARM_VLD4qWB_register_Asm_32	= 508,
+    ARM_VLD4qWB_register_Asm_8	= 509,
+    ARM_VMOVD0	= 510,
+    ARM_VMOVDcc	= 511,
+    ARM_VMOVHcc	= 512,
+    ARM_VMOVQ0	= 513,
+    ARM_VMOVScc	= 514,
+    ARM_VST1LNdAsm_16	= 515,
+    ARM_VST1LNdAsm_32	= 516,
+    ARM_VST1LNdAsm_8	= 517,
+    ARM_VST1LNdWB_fixed_Asm_16	= 518,
+    ARM_VST1LNdWB_fixed_Asm_32	= 519,
+    ARM_VST1LNdWB_fixed_Asm_8	= 520,
+    ARM_VST1LNdWB_register_Asm_16	= 521,
+    ARM_VST1LNdWB_register_Asm_32	= 522,
+    ARM_VST1LNdWB_register_Asm_8	= 523,
+    ARM_VST2LNdAsm_16	= 524,
+    ARM_VST2LNdAsm_32	= 525,
+    ARM_VST2LNdAsm_8	= 526,
+    ARM_VST2LNdWB_fixed_Asm_16	= 527,
+    ARM_VST2LNdWB_fixed_Asm_32	= 528,
+    ARM_VST2LNdWB_fixed_Asm_8	= 529,
+    ARM_VST2LNdWB_register_Asm_16	= 530,
+    ARM_VST2LNdWB_register_Asm_32	= 531,
+    ARM_VST2LNdWB_register_Asm_8	= 532,
+    ARM_VST2LNqAsm_16	= 533,
+    ARM_VST2LNqAsm_32	= 534,
+    ARM_VST2LNqWB_fixed_Asm_16	= 535,
+    ARM_VST2LNqWB_fixed_Asm_32	= 536,
+    ARM_VST2LNqWB_register_Asm_16	= 537,
+    ARM_VST2LNqWB_register_Asm_32	= 538,
+    ARM_VST3LNdAsm_16	= 539,
+    ARM_VST3LNdAsm_32	= 540,
+    ARM_VST3LNdAsm_8	= 541,
+    ARM_VST3LNdWB_fixed_Asm_16	= 542,
+    ARM_VST3LNdWB_fixed_Asm_32	= 543,
+    ARM_VST3LNdWB_fixed_Asm_8	= 544,
+    ARM_VST3LNdWB_register_Asm_16	= 545,
+    ARM_VST3LNdWB_register_Asm_32	= 546,
+    ARM_VST3LNdWB_register_Asm_8	= 547,
+    ARM_VST3LNqAsm_16	= 548,
+    ARM_VST3LNqAsm_32	= 549,
+    ARM_VST3LNqWB_fixed_Asm_16	= 550,
+    ARM_VST3LNqWB_fixed_Asm_32	= 551,
+    ARM_VST3LNqWB_register_Asm_16	= 552,
+    ARM_VST3LNqWB_register_Asm_32	= 553,
+    ARM_VST3dAsm_16	= 554,
+    ARM_VST3dAsm_32	= 555,
+    ARM_VST3dAsm_8	= 556,
+    ARM_VST3dWB_fixed_Asm_16	= 557,
+    ARM_VST3dWB_fixed_Asm_32	= 558,
+    ARM_VST3dWB_fixed_Asm_8	= 559,
+    ARM_VST3dWB_register_Asm_16	= 560,
+    ARM_VST3dWB_register_Asm_32	= 561,
+    ARM_VST3dWB_register_Asm_8	= 562,
+    ARM_VST3qAsm_16	= 563,
+    ARM_VST3qAsm_32	= 564,
+    ARM_VST3qAsm_8	= 565,
+    ARM_VST3qWB_fixed_Asm_16	= 566,
+    ARM_VST3qWB_fixed_Asm_32	= 567,
+    ARM_VST3qWB_fixed_Asm_8	= 568,
+    ARM_VST3qWB_register_Asm_16	= 569,
+    ARM_VST3qWB_register_Asm_32	= 570,
+    ARM_VST3qWB_register_Asm_8	= 571,
+    ARM_VST4LNdAsm_16	= 572,
+    ARM_VST4LNdAsm_32	= 573,
+    ARM_VST4LNdAsm_8	= 574,
+    ARM_VST4LNdWB_fixed_Asm_16	= 575,
+    ARM_VST4LNdWB_fixed_Asm_32	= 576,
+    ARM_VST4LNdWB_fixed_Asm_8	= 577,
+    ARM_VST4LNdWB_register_Asm_16	= 578,
+    ARM_VST4LNdWB_register_Asm_32	= 579,
+    ARM_VST4LNdWB_register_Asm_8	= 580,
+    ARM_VST4LNqAsm_16	= 581,
+    ARM_VST4LNqAsm_32	= 582,
+    ARM_VST4LNqWB_fixed_Asm_16	= 583,
+    ARM_VST4LNqWB_fixed_Asm_32	= 584,
+    ARM_VST4LNqWB_register_Asm_16	= 585,
+    ARM_VST4LNqWB_register_Asm_32	= 586,
+    ARM_VST4dAsm_16	= 587,
+    ARM_VST4dAsm_32	= 588,
+    ARM_VST4dAsm_8	= 589,
+    ARM_VST4dWB_fixed_Asm_16	= 590,
+    ARM_VST4dWB_fixed_Asm_32	= 591,
+    ARM_VST4dWB_fixed_Asm_8	= 592,
+    ARM_VST4dWB_register_Asm_16	= 593,
+    ARM_VST4dWB_register_Asm_32	= 594,
+    ARM_VST4dWB_register_Asm_8	= 595,
+    ARM_VST4qAsm_16	= 596,
+    ARM_VST4qAsm_32	= 597,
+    ARM_VST4qAsm_8	= 598,
+    ARM_VST4qWB_fixed_Asm_16	= 599,
+    ARM_VST4qWB_fixed_Asm_32	= 600,
+    ARM_VST4qWB_fixed_Asm_8	= 601,
+    ARM_VST4qWB_register_Asm_16	= 602,
+    ARM_VST4qWB_register_Asm_32	= 603,
+    ARM_VST4qWB_register_Asm_8	= 604,
+    ARM_WIN__CHKSTK	= 605,
+    ARM_WIN__DBZCHK	= 606,
+    ARM_t2ABS	= 607,
+    ARM_t2ADDSri	= 608,
+    ARM_t2ADDSrr	= 609,
+    ARM_t2ADDSrs	= 610,
+    ARM_t2BF_LabelPseudo	= 611,
+    ARM_t2BR_JT	= 612,
+    ARM_t2CALL_BTI	= 613,
+    ARM_t2DoLoopStart	= 614,
+    ARM_t2DoLoopStartTP	= 615,
+    ARM_t2LDMIA_RET	= 616,
+    ARM_t2LDRBpcrel	= 617,
+    ARM_t2LDRConstPool	= 618,
+    ARM_t2LDRHpcrel	= 619,
+    ARM_t2LDRLIT_ga_pcrel	= 620,
+    ARM_t2LDRSBpcrel	= 621,
+    ARM_t2LDRSHpcrel	= 622,
+    ARM_t2LDR_POST_imm	= 623,
+    ARM_t2LDR_PRE_imm	= 624,
+    ARM_t2LDRpci_pic	= 625,
+    ARM_t2LDRpcrel	= 626,
+    ARM_t2LEApcrel	= 627,
+    ARM_t2LEApcrelJT	= 628,
+    ARM_t2LoopDec	= 629,
+    ARM_t2LoopEnd	= 630,
+    ARM_t2LoopEndDec	= 631,
+    ARM_t2MOVCCasr	= 632,
+    ARM_t2MOVCCi	= 633,
+    ARM_t2MOVCCi16	= 634,
+    ARM_t2MOVCCi32imm	= 635,
+    ARM_t2MOVCClsl	= 636,
+    ARM_t2MOVCClsr	= 637,
+    ARM_t2MOVCCr	= 638,
+    ARM_t2MOVCCror	= 639,
+    ARM_t2MOVSsi	= 640,
+    ARM_t2MOVSsr	= 641,
+    ARM_t2MOVTi16_ga_pcrel	= 642,
+    ARM_t2MOV_ga_pcrel	= 643,
+    ARM_t2MOVi16_ga_pcrel	= 644,
+    ARM_t2MOVi32imm	= 645,
+    ARM_t2MOVsi	= 646,
+    ARM_t2MOVsr	= 647,
+    ARM_t2MVNCCi	= 648,
+    ARM_t2RSBSri	= 649,
+    ARM_t2RSBSrs	= 650,
+    ARM_t2STRB_preidx	= 651,
+    ARM_t2STRH_preidx	= 652,
+    ARM_t2STR_POST_imm	= 653,
+    ARM_t2STR_PRE_imm	= 654,
+    ARM_t2STR_preidx	= 655,
+    ARM_t2SUBSri	= 656,
+    ARM_t2SUBSrr	= 657,
+    ARM_t2SUBSrs	= 658,
+    ARM_t2SpeculationBarrierISBDSBEndBB	= 659,
+    ARM_t2SpeculationBarrierSBEndBB	= 660,
+    ARM_t2TBB_JT	= 661,
+    ARM_t2TBH_JT	= 662,
+    ARM_t2WhileLoopSetup	= 663,
+    ARM_t2WhileLoopStart	= 664,
+    ARM_t2WhileLoopStartLR	= 665,
+    ARM_t2WhileLoopStartTP	= 666,
+    ARM_tADCS	= 667,
+    ARM_tADDSi3	= 668,
+    ARM_tADDSi8	= 669,
+    ARM_tADDSrr	= 670,
+    ARM_tADDframe	= 671,
+    ARM_tADJCALLSTACKDOWN	= 672,
+    ARM_tADJCALLSTACKUP	= 673,
+    ARM_tBLXNS_CALL	= 674,
+    ARM_tBLXr_noip	= 675,
+    ARM_tBL_PUSHLR	= 676,
+    ARM_tBRIND	= 677,
+    ARM_tBR_JTr	= 678,
+    ARM_tBXNS_RET	= 679,
+    ARM_tBX_CALL	= 680,
+    ARM_tBX_RET	= 681,
+    ARM_tBX_RET_vararg	= 682,
+    ARM_tBfar	= 683,
+    ARM_tCMP_SWAP_16	= 684,
+    ARM_tCMP_SWAP_32	= 685,
+    ARM_tCMP_SWAP_8	= 686,
+    ARM_tLDMIA_UPD	= 687,
+    ARM_tLDRConstPool	= 688,
+    ARM_tLDRLIT_ga_abs	= 689,
+    ARM_tLDRLIT_ga_pcrel	= 690,
+    ARM_tLDR_postidx	= 691,
+    ARM_tLDRpci_pic	= 692,
+    ARM_tLEApcrel	= 693,
+    ARM_tLEApcrelJT	= 694,
+    ARM_tLSLSri	= 695,
+    ARM_tMOVCCr_pseudo	= 696,
+    ARM_tPOP_RET	= 697,
+    ARM_tRSBS	= 698,
+    ARM_tSBCS	= 699,
+    ARM_tSUBSi3	= 700,
+    ARM_tSUBSi8	= 701,
+    ARM_tSUBSrr	= 702,
+    ARM_tTAILJMPd	= 703,
+    ARM_tTAILJMPdND	= 704,
+    ARM_tTAILJMPr	= 705,
+    ARM_tTBB_JT	= 706,
+    ARM_tTBH_JT	= 707,
+    ARM_tTPsoft	= 708,
+    ARM_ADCri	= 709,
+    ARM_ADCrr	= 710,
+    ARM_ADCrsi	= 711,
+    ARM_ADCrsr	= 712,
+    ARM_ADDri	= 713,
+    ARM_ADDrr	= 714,
+    ARM_ADDrsi	= 715,
+    ARM_ADDrsr	= 716,
+    ARM_ADR	= 717,
+    ARM_AESD	= 718,
+    ARM_AESE	= 719,
+    ARM_AESIMC	= 720,
+    ARM_AESMC	= 721,
+    ARM_ANDri	= 722,
+    ARM_ANDrr	= 723,
+    ARM_ANDrsi	= 724,
+    ARM_ANDrsr	= 725,
+    ARM_BF16VDOTI_VDOTD	= 726,
+    ARM_BF16VDOTI_VDOTQ	= 727,
+    ARM_BF16VDOTS_VDOTD	= 728,
+    ARM_BF16VDOTS_VDOTQ	= 729,
+    ARM_BF16_VCVT	= 730,
+    ARM_BF16_VCVTB	= 731,
+    ARM_BF16_VCVTT	= 732,
+    ARM_BFC	= 733,
+    ARM_BFI	= 734,
+    ARM_BICri	= 735,
+    ARM_BICrr	= 736,
+    ARM_BICrsi	= 737,
+    ARM_BICrsr	= 738,
+    ARM_BKPT	= 739,
+    ARM_BL	= 740,
+    ARM_BLX	= 741,
+    ARM_BLX_pred	= 742,
+    ARM_BLXi	= 743,
+    ARM_BL_pred	= 744,
+    ARM_BX	= 745,
+    ARM_BXJ	= 746,
+    ARM_BX_RET	= 747,
+    ARM_BX_pred	= 748,
+    ARM_Bcc	= 749,
+    ARM_CDE_CX1	= 750,
+    ARM_CDE_CX1A	= 751,
+    ARM_CDE_CX1D	= 752,
+    ARM_CDE_CX1DA	= 753,
+    ARM_CDE_CX2	= 754,
+    ARM_CDE_CX2A	= 755,
+    ARM_CDE_CX2D	= 756,
+    ARM_CDE_CX2DA	= 757,
+    ARM_CDE_CX3	= 758,
+    ARM_CDE_CX3A	= 759,
+    ARM_CDE_CX3D	= 760,
+    ARM_CDE_CX3DA	= 761,
+    ARM_CDE_VCX1A_fpdp	= 762,
+    ARM_CDE_VCX1A_fpsp	= 763,
+    ARM_CDE_VCX1A_vec	= 764,
+    ARM_CDE_VCX1_fpdp	= 765,
+    ARM_CDE_VCX1_fpsp	= 766,
+    ARM_CDE_VCX1_vec	= 767,
+    ARM_CDE_VCX2A_fpdp	= 768,
+    ARM_CDE_VCX2A_fpsp	= 769,
+    ARM_CDE_VCX2A_vec	= 770,
+    ARM_CDE_VCX2_fpdp	= 771,
+    ARM_CDE_VCX2_fpsp	= 772,
+    ARM_CDE_VCX2_vec	= 773,
+    ARM_CDE_VCX3A_fpdp	= 774,
+    ARM_CDE_VCX3A_fpsp	= 775,
+    ARM_CDE_VCX3A_vec	= 776,
+    ARM_CDE_VCX3_fpdp	= 777,
+    ARM_CDE_VCX3_fpsp	= 778,
+    ARM_CDE_VCX3_vec	= 779,
+    ARM_CDP	= 780,
+    ARM_CDP2	= 781,
+    ARM_CLREX	= 782,
+    ARM_CLZ	= 783,
+    ARM_CMNri	= 784,
+    ARM_CMNzrr	= 785,
+    ARM_CMNzrsi	= 786,
+    ARM_CMNzrsr	= 787,
+    ARM_CMPri	= 788,
+    ARM_CMPrr	= 789,
+    ARM_CMPrsi	= 790,
+    ARM_CMPrsr	= 791,
+    ARM_CPS1p	= 792,
+    ARM_CPS2p	= 793,
+    ARM_CPS3p	= 794,
+    ARM_CRC32B	= 795,
+    ARM_CRC32CB	= 796,
+    ARM_CRC32CH	= 797,
+    ARM_CRC32CW	= 798,
+    ARM_CRC32H	= 799,
+    ARM_CRC32W	= 800,
+    ARM_DBG	= 801,
+    ARM_DMB	= 802,
+    ARM_DSB	= 803,
+    ARM_EORri	= 804,
+    ARM_EORrr	= 805,
+    ARM_EORrsi	= 806,
+    ARM_EORrsr	= 807,
+    ARM_ERET	= 808,
+    ARM_FCONSTD	= 809,
+    ARM_FCONSTH	= 810,
+    ARM_FCONSTS	= 811,
+    ARM_FLDMXDB_UPD	= 812,
+    ARM_FLDMXIA	= 813,
+    ARM_FLDMXIA_UPD	= 814,
+    ARM_FMSTAT	= 815,
+    ARM_FSTMXDB_UPD	= 816,
+    ARM_FSTMXIA	= 817,
+    ARM_FSTMXIA_UPD	= 818,
+    ARM_HINT	= 819,
+    ARM_HLT	= 820,
+    ARM_HVC	= 821,
+    ARM_ISB	= 822,
+    ARM_LDA	= 823,
+    ARM_LDAB	= 824,
+    ARM_LDAEX	= 825,
+    ARM_LDAEXB	= 826,
+    ARM_LDAEXD	= 827,
+    ARM_LDAEXH	= 828,
+    ARM_LDAH	= 829,
+    ARM_LDC2L_OFFSET	= 830,
+    ARM_LDC2L_OPTION	= 831,
+    ARM_LDC2L_POST	= 832,
+    ARM_LDC2L_PRE	= 833,
+    ARM_LDC2_OFFSET	= 834,
+    ARM_LDC2_OPTION	= 835,
+    ARM_LDC2_POST	= 836,
+    ARM_LDC2_PRE	= 837,
+    ARM_LDCL_OFFSET	= 838,
+    ARM_LDCL_OPTION	= 839,
+    ARM_LDCL_POST	= 840,
+    ARM_LDCL_PRE	= 841,
+    ARM_LDC_OFFSET	= 842,
+    ARM_LDC_OPTION	= 843,
+    ARM_LDC_POST	= 844,
+    ARM_LDC_PRE	= 845,
+    ARM_LDMDA	= 846,
+    ARM_LDMDA_UPD	= 847,
+    ARM_LDMDB	= 848,
+    ARM_LDMDB_UPD	= 849,
+    ARM_LDMIA	= 850,
+    ARM_LDMIA_UPD	= 851,
+    ARM_LDMIB	= 852,
+    ARM_LDMIB_UPD	= 853,
+    ARM_LDRBT_POST_IMM	= 854,
+    ARM_LDRBT_POST_REG	= 855,
+    ARM_LDRB_POST_IMM	= 856,
+    ARM_LDRB_POST_REG	= 857,
+    ARM_LDRB_PRE_IMM	= 858,
+    ARM_LDRB_PRE_REG	= 859,
+    ARM_LDRBi12	= 860,
+    ARM_LDRBrs	= 861,
+    ARM_LDRD	= 862,
+    ARM_LDRD_POST	= 863,
+    ARM_LDRD_PRE	= 864,
+    ARM_LDREX	= 865,
+    ARM_LDREXB	= 866,
+    ARM_LDREXD	= 867,
+    ARM_LDREXH	= 868,
+    ARM_LDRH	= 869,
+    ARM_LDRHTi	= 870,
+    ARM_LDRHTr	= 871,
+    ARM_LDRH_POST	= 872,
+    ARM_LDRH_PRE	= 873,
+    ARM_LDRSB	= 874,
+    ARM_LDRSBTi	= 875,
+    ARM_LDRSBTr	= 876,
+    ARM_LDRSB_POST	= 877,
+    ARM_LDRSB_PRE	= 878,
+    ARM_LDRSH	= 879,
+    ARM_LDRSHTi	= 880,
+    ARM_LDRSHTr	= 881,
+    ARM_LDRSH_POST	= 882,
+    ARM_LDRSH_PRE	= 883,
+    ARM_LDRT_POST_IMM	= 884,
+    ARM_LDRT_POST_REG	= 885,
+    ARM_LDR_POST_IMM	= 886,
+    ARM_LDR_POST_REG	= 887,
+    ARM_LDR_PRE_IMM	= 888,
+    ARM_LDR_PRE_REG	= 889,
+    ARM_LDRcp	= 890,
+    ARM_LDRi12	= 891,
+    ARM_LDRrs	= 892,
+    ARM_MCR	= 893,
+    ARM_MCR2	= 894,
+    ARM_MCRR	= 895,
+    ARM_MCRR2	= 896,
+    ARM_MLA	= 897,
+    ARM_MLS	= 898,
+    ARM_MOVPCLR	= 899,
+    ARM_MOVTi16	= 900,
+    ARM_MOVi	= 901,
+    ARM_MOVi16	= 902,
+    ARM_MOVr	= 903,
+    ARM_MOVr_TC	= 904,
+    ARM_MOVsi	= 905,
+    ARM_MOVsr	= 906,
+    ARM_MRC	= 907,
+    ARM_MRC2	= 908,
+    ARM_MRRC	= 909,
+    ARM_MRRC2	= 910,
+    ARM_MRS	= 911,
+    ARM_MRSbanked	= 912,
+    ARM_MRSsys	= 913,
+    ARM_MSR	= 914,
+    ARM_MSRbanked	= 915,
+    ARM_MSRi	= 916,
+    ARM_MUL	= 917,
+    ARM_MVE_ASRLi	= 918,
+    ARM_MVE_ASRLr	= 919,
+    ARM_MVE_DLSTP_16	= 920,
+    ARM_MVE_DLSTP_32	= 921,
+    ARM_MVE_DLSTP_64	= 922,
+    ARM_MVE_DLSTP_8	= 923,
+    ARM_MVE_LCTP	= 924,
+    ARM_MVE_LETP	= 925,
+    ARM_MVE_LSLLi	= 926,
+    ARM_MVE_LSLLr	= 927,
+    ARM_MVE_LSRL	= 928,
+    ARM_MVE_SQRSHR	= 929,
+    ARM_MVE_SQRSHRL	= 930,
+    ARM_MVE_SQSHL	= 931,
+    ARM_MVE_SQSHLL	= 932,
+    ARM_MVE_SRSHR	= 933,
+    ARM_MVE_SRSHRL	= 934,
+    ARM_MVE_UQRSHL	= 935,
+    ARM_MVE_UQRSHLL	= 936,
+    ARM_MVE_UQSHL	= 937,
+    ARM_MVE_UQSHLL	= 938,
+    ARM_MVE_URSHR	= 939,
+    ARM_MVE_URSHRL	= 940,
+    ARM_MVE_VABAVs16	= 941,
+    ARM_MVE_VABAVs32	= 942,
+    ARM_MVE_VABAVs8	= 943,
+    ARM_MVE_VABAVu16	= 944,
+    ARM_MVE_VABAVu32	= 945,
+    ARM_MVE_VABAVu8	= 946,
+    ARM_MVE_VABDf16	= 947,
+    ARM_MVE_VABDf32	= 948,
+    ARM_MVE_VABDs16	= 949,
+    ARM_MVE_VABDs32	= 950,
+    ARM_MVE_VABDs8	= 951,
+    ARM_MVE_VABDu16	= 952,
+    ARM_MVE_VABDu32	= 953,
+    ARM_MVE_VABDu8	= 954,
+    ARM_MVE_VABSf16	= 955,
+    ARM_MVE_VABSf32	= 956,
+    ARM_MVE_VABSs16	= 957,
+    ARM_MVE_VABSs32	= 958,
+    ARM_MVE_VABSs8	= 959,
+    ARM_MVE_VADC	= 960,
+    ARM_MVE_VADCI	= 961,
+    ARM_MVE_VADDLVs32acc	= 962,
+    ARM_MVE_VADDLVs32no_acc	= 963,
+    ARM_MVE_VADDLVu32acc	= 964,
+    ARM_MVE_VADDLVu32no_acc	= 965,
+    ARM_MVE_VADDVs16acc	= 966,
+    ARM_MVE_VADDVs16no_acc	= 967,
+    ARM_MVE_VADDVs32acc	= 968,
+    ARM_MVE_VADDVs32no_acc	= 969,
+    ARM_MVE_VADDVs8acc	= 970,
+    ARM_MVE_VADDVs8no_acc	= 971,
+    ARM_MVE_VADDVu16acc	= 972,
+    ARM_MVE_VADDVu16no_acc	= 973,
+    ARM_MVE_VADDVu32acc	= 974,
+    ARM_MVE_VADDVu32no_acc	= 975,
+    ARM_MVE_VADDVu8acc	= 976,
+    ARM_MVE_VADDVu8no_acc	= 977,
+    ARM_MVE_VADD_qr_f16	= 978,
+    ARM_MVE_VADD_qr_f32	= 979,
+    ARM_MVE_VADD_qr_i16	= 980,
+    ARM_MVE_VADD_qr_i32	= 981,
+    ARM_MVE_VADD_qr_i8	= 982,
+    ARM_MVE_VADDf16	= 983,
+    ARM_MVE_VADDf32	= 984,
+    ARM_MVE_VADDi16	= 985,
+    ARM_MVE_VADDi32	= 986,
+    ARM_MVE_VADDi8	= 987,
+    ARM_MVE_VAND	= 988,
+    ARM_MVE_VBIC	= 989,
+    ARM_MVE_VBICimmi16	= 990,
+    ARM_MVE_VBICimmi32	= 991,
+    ARM_MVE_VBRSR16	= 992,
+    ARM_MVE_VBRSR32	= 993,
+    ARM_MVE_VBRSR8	= 994,
+    ARM_MVE_VCADDf16	= 995,
+    ARM_MVE_VCADDf32	= 996,
+    ARM_MVE_VCADDi16	= 997,
+    ARM_MVE_VCADDi32	= 998,
+    ARM_MVE_VCADDi8	= 999,
+    ARM_MVE_VCLSs16	= 1000,
+    ARM_MVE_VCLSs32	= 1001,
+    ARM_MVE_VCLSs8	= 1002,
+    ARM_MVE_VCLZs16	= 1003,
+    ARM_MVE_VCLZs32	= 1004,
+    ARM_MVE_VCLZs8	= 1005,
+    ARM_MVE_VCMLAf16	= 1006,
+    ARM_MVE_VCMLAf32	= 1007,
+    ARM_MVE_VCMPf16	= 1008,
+    ARM_MVE_VCMPf16r	= 1009,
+    ARM_MVE_VCMPf32	= 1010,
+    ARM_MVE_VCMPf32r	= 1011,
+    ARM_MVE_VCMPi16	= 1012,
+    ARM_MVE_VCMPi16r	= 1013,
+    ARM_MVE_VCMPi32	= 1014,
+    ARM_MVE_VCMPi32r	= 1015,
+    ARM_MVE_VCMPi8	= 1016,
+    ARM_MVE_VCMPi8r	= 1017,
+    ARM_MVE_VCMPs16	= 1018,
+    ARM_MVE_VCMPs16r	= 1019,
+    ARM_MVE_VCMPs32	= 1020,
+    ARM_MVE_VCMPs32r	= 1021,
+    ARM_MVE_VCMPs8	= 1022,
+    ARM_MVE_VCMPs8r	= 1023,
+    ARM_MVE_VCMPu16	= 1024,
+    ARM_MVE_VCMPu16r	= 1025,
+    ARM_MVE_VCMPu32	= 1026,
+    ARM_MVE_VCMPu32r	= 1027,
+    ARM_MVE_VCMPu8	= 1028,
+    ARM_MVE_VCMPu8r	= 1029,
+    ARM_MVE_VCMULf16	= 1030,
+    ARM_MVE_VCMULf32	= 1031,
+    ARM_MVE_VCTP16	= 1032,
+    ARM_MVE_VCTP32	= 1033,
+    ARM_MVE_VCTP64	= 1034,
+    ARM_MVE_VCTP8	= 1035,
+    ARM_MVE_VCVTf16f32bh	= 1036,
+    ARM_MVE_VCVTf16f32th	= 1037,
+    ARM_MVE_VCVTf16s16_fix	= 1038,
+    ARM_MVE_VCVTf16s16n	= 1039,
+    ARM_MVE_VCVTf16u16_fix	= 1040,
+    ARM_MVE_VCVTf16u16n	= 1041,
+    ARM_MVE_VCVTf32f16bh	= 1042,
+    ARM_MVE_VCVTf32f16th	= 1043,
+    ARM_MVE_VCVTf32s32_fix	= 1044,
+    ARM_MVE_VCVTf32s32n	= 1045,
+    ARM_MVE_VCVTf32u32_fix	= 1046,
+    ARM_MVE_VCVTf32u32n	= 1047,
+    ARM_MVE_VCVTs16f16_fix	= 1048,
+    ARM_MVE_VCVTs16f16a	= 1049,
+    ARM_MVE_VCVTs16f16m	= 1050,
+    ARM_MVE_VCVTs16f16n	= 1051,
+    ARM_MVE_VCVTs16f16p	= 1052,
+    ARM_MVE_VCVTs16f16z	= 1053,
+    ARM_MVE_VCVTs32f32_fix	= 1054,
+    ARM_MVE_VCVTs32f32a	= 1055,
+    ARM_MVE_VCVTs32f32m	= 1056,
+    ARM_MVE_VCVTs32f32n	= 1057,
+    ARM_MVE_VCVTs32f32p	= 1058,
+    ARM_MVE_VCVTs32f32z	= 1059,
+    ARM_MVE_VCVTu16f16_fix	= 1060,
+    ARM_MVE_VCVTu16f16a	= 1061,
+    ARM_MVE_VCVTu16f16m	= 1062,
+    ARM_MVE_VCVTu16f16n	= 1063,
+    ARM_MVE_VCVTu16f16p	= 1064,
+    ARM_MVE_VCVTu16f16z	= 1065,
+    ARM_MVE_VCVTu32f32_fix	= 1066,
+    ARM_MVE_VCVTu32f32a	= 1067,
+    ARM_MVE_VCVTu32f32m	= 1068,
+    ARM_MVE_VCVTu32f32n	= 1069,
+    ARM_MVE_VCVTu32f32p	= 1070,
+    ARM_MVE_VCVTu32f32z	= 1071,
+    ARM_MVE_VDDUPu16	= 1072,
+    ARM_MVE_VDDUPu32	= 1073,
+    ARM_MVE_VDDUPu8	= 1074,
+    ARM_MVE_VDUP16	= 1075,
+    ARM_MVE_VDUP32	= 1076,
+    ARM_MVE_VDUP8	= 1077,
+    ARM_MVE_VDWDUPu16	= 1078,
+    ARM_MVE_VDWDUPu32	= 1079,
+    ARM_MVE_VDWDUPu8	= 1080,
+    ARM_MVE_VEOR	= 1081,
+    ARM_MVE_VFMA_qr_Sf16	= 1082,
+    ARM_MVE_VFMA_qr_Sf32	= 1083,
+    ARM_MVE_VFMA_qr_f16	= 1084,
+    ARM_MVE_VFMA_qr_f32	= 1085,
+    ARM_MVE_VFMAf16	= 1086,
+    ARM_MVE_VFMAf32	= 1087,
+    ARM_MVE_VFMSf16	= 1088,
+    ARM_MVE_VFMSf32	= 1089,
+    ARM_MVE_VHADD_qr_s16	= 1090,
+    ARM_MVE_VHADD_qr_s32	= 1091,
+    ARM_MVE_VHADD_qr_s8	= 1092,
+    ARM_MVE_VHADD_qr_u16	= 1093,
+    ARM_MVE_VHADD_qr_u32	= 1094,
+    ARM_MVE_VHADD_qr_u8	= 1095,
+    ARM_MVE_VHADDs16	= 1096,
+    ARM_MVE_VHADDs32	= 1097,
+    ARM_MVE_VHADDs8	= 1098,
+    ARM_MVE_VHADDu16	= 1099,
+    ARM_MVE_VHADDu32	= 1100,
+    ARM_MVE_VHADDu8	= 1101,
+    ARM_MVE_VHCADDs16	= 1102,
+    ARM_MVE_VHCADDs32	= 1103,
+    ARM_MVE_VHCADDs8	= 1104,
+    ARM_MVE_VHSUB_qr_s16	= 1105,
+    ARM_MVE_VHSUB_qr_s32	= 1106,
+    ARM_MVE_VHSUB_qr_s8	= 1107,
+    ARM_MVE_VHSUB_qr_u16	= 1108,
+    ARM_MVE_VHSUB_qr_u32	= 1109,
+    ARM_MVE_VHSUB_qr_u8	= 1110,
+    ARM_MVE_VHSUBs16	= 1111,
+    ARM_MVE_VHSUBs32	= 1112,
+    ARM_MVE_VHSUBs8	= 1113,
+    ARM_MVE_VHSUBu16	= 1114,
+    ARM_MVE_VHSUBu32	= 1115,
+    ARM_MVE_VHSUBu8	= 1116,
+    ARM_MVE_VIDUPu16	= 1117,
+    ARM_MVE_VIDUPu32	= 1118,
+    ARM_MVE_VIDUPu8	= 1119,
+    ARM_MVE_VIWDUPu16	= 1120,
+    ARM_MVE_VIWDUPu32	= 1121,
+    ARM_MVE_VIWDUPu8	= 1122,
+    ARM_MVE_VLD20_16	= 1123,
+    ARM_MVE_VLD20_16_wb	= 1124,
+    ARM_MVE_VLD20_32	= 1125,
+    ARM_MVE_VLD20_32_wb	= 1126,
+    ARM_MVE_VLD20_8	= 1127,
+    ARM_MVE_VLD20_8_wb	= 1128,
+    ARM_MVE_VLD21_16	= 1129,
+    ARM_MVE_VLD21_16_wb	= 1130,
+    ARM_MVE_VLD21_32	= 1131,
+    ARM_MVE_VLD21_32_wb	= 1132,
+    ARM_MVE_VLD21_8	= 1133,
+    ARM_MVE_VLD21_8_wb	= 1134,
+    ARM_MVE_VLD40_16	= 1135,
+    ARM_MVE_VLD40_16_wb	= 1136,
+    ARM_MVE_VLD40_32	= 1137,
+    ARM_MVE_VLD40_32_wb	= 1138,
+    ARM_MVE_VLD40_8	= 1139,
+    ARM_MVE_VLD40_8_wb	= 1140,
+    ARM_MVE_VLD41_16	= 1141,
+    ARM_MVE_VLD41_16_wb	= 1142,
+    ARM_MVE_VLD41_32	= 1143,
+    ARM_MVE_VLD41_32_wb	= 1144,
+    ARM_MVE_VLD41_8	= 1145,
+    ARM_MVE_VLD41_8_wb	= 1146,
+    ARM_MVE_VLD42_16	= 1147,
+    ARM_MVE_VLD42_16_wb	= 1148,
+    ARM_MVE_VLD42_32	= 1149,
+    ARM_MVE_VLD42_32_wb	= 1150,
+    ARM_MVE_VLD42_8	= 1151,
+    ARM_MVE_VLD42_8_wb	= 1152,
+    ARM_MVE_VLD43_16	= 1153,
+    ARM_MVE_VLD43_16_wb	= 1154,
+    ARM_MVE_VLD43_32	= 1155,
+    ARM_MVE_VLD43_32_wb	= 1156,
+    ARM_MVE_VLD43_8	= 1157,
+    ARM_MVE_VLD43_8_wb	= 1158,
+    ARM_MVE_VLDRBS16	= 1159,
+    ARM_MVE_VLDRBS16_post	= 1160,
+    ARM_MVE_VLDRBS16_pre	= 1161,
+    ARM_MVE_VLDRBS16_rq	= 1162,
+    ARM_MVE_VLDRBS32	= 1163,
+    ARM_MVE_VLDRBS32_post	= 1164,
+    ARM_MVE_VLDRBS32_pre	= 1165,
+    ARM_MVE_VLDRBS32_rq	= 1166,
+    ARM_MVE_VLDRBU16	= 1167,
+    ARM_MVE_VLDRBU16_post	= 1168,
+    ARM_MVE_VLDRBU16_pre	= 1169,
+    ARM_MVE_VLDRBU16_rq	= 1170,
+    ARM_MVE_VLDRBU32	= 1171,
+    ARM_MVE_VLDRBU32_post	= 1172,
+    ARM_MVE_VLDRBU32_pre	= 1173,
+    ARM_MVE_VLDRBU32_rq	= 1174,
+    ARM_MVE_VLDRBU8	= 1175,
+    ARM_MVE_VLDRBU8_post	= 1176,
+    ARM_MVE_VLDRBU8_pre	= 1177,
+    ARM_MVE_VLDRBU8_rq	= 1178,
+    ARM_MVE_VLDRDU64_qi	= 1179,
+    ARM_MVE_VLDRDU64_qi_pre	= 1180,
+    ARM_MVE_VLDRDU64_rq	= 1181,
+    ARM_MVE_VLDRDU64_rq_u	= 1182,
+    ARM_MVE_VLDRHS32	= 1183,
+    ARM_MVE_VLDRHS32_post	= 1184,
+    ARM_MVE_VLDRHS32_pre	= 1185,
+    ARM_MVE_VLDRHS32_rq	= 1186,
+    ARM_MVE_VLDRHS32_rq_u	= 1187,
+    ARM_MVE_VLDRHU16	= 1188,
+    ARM_MVE_VLDRHU16_post	= 1189,
+    ARM_MVE_VLDRHU16_pre	= 1190,
+    ARM_MVE_VLDRHU16_rq	= 1191,
+    ARM_MVE_VLDRHU16_rq_u	= 1192,
+    ARM_MVE_VLDRHU32	= 1193,
+    ARM_MVE_VLDRHU32_post	= 1194,
+    ARM_MVE_VLDRHU32_pre	= 1195,
+    ARM_MVE_VLDRHU32_rq	= 1196,
+    ARM_MVE_VLDRHU32_rq_u	= 1197,
+    ARM_MVE_VLDRWU32	= 1198,
+    ARM_MVE_VLDRWU32_post	= 1199,
+    ARM_MVE_VLDRWU32_pre	= 1200,
+    ARM_MVE_VLDRWU32_qi	= 1201,
+    ARM_MVE_VLDRWU32_qi_pre	= 1202,
+    ARM_MVE_VLDRWU32_rq	= 1203,
+    ARM_MVE_VLDRWU32_rq_u	= 1204,
+    ARM_MVE_VMAXAVs16	= 1205,
+    ARM_MVE_VMAXAVs32	= 1206,
+    ARM_MVE_VMAXAVs8	= 1207,
+    ARM_MVE_VMAXAs16	= 1208,
+    ARM_MVE_VMAXAs32	= 1209,
+    ARM_MVE_VMAXAs8	= 1210,
+    ARM_MVE_VMAXNMAVf16	= 1211,
+    ARM_MVE_VMAXNMAVf32	= 1212,
+    ARM_MVE_VMAXNMAf16	= 1213,
+    ARM_MVE_VMAXNMAf32	= 1214,
+    ARM_MVE_VMAXNMVf16	= 1215,
+    ARM_MVE_VMAXNMVf32	= 1216,
+    ARM_MVE_VMAXNMf16	= 1217,
+    ARM_MVE_VMAXNMf32	= 1218,
+    ARM_MVE_VMAXVs16	= 1219,
+    ARM_MVE_VMAXVs32	= 1220,
+    ARM_MVE_VMAXVs8	= 1221,
+    ARM_MVE_VMAXVu16	= 1222,
+    ARM_MVE_VMAXVu32	= 1223,
+    ARM_MVE_VMAXVu8	= 1224,
+    ARM_MVE_VMAXs16	= 1225,
+    ARM_MVE_VMAXs32	= 1226,
+    ARM_MVE_VMAXs8	= 1227,
+    ARM_MVE_VMAXu16	= 1228,
+    ARM_MVE_VMAXu32	= 1229,
+    ARM_MVE_VMAXu8	= 1230,
+    ARM_MVE_VMINAVs16	= 1231,
+    ARM_MVE_VMINAVs32	= 1232,
+    ARM_MVE_VMINAVs8	= 1233,
+    ARM_MVE_VMINAs16	= 1234,
+    ARM_MVE_VMINAs32	= 1235,
+    ARM_MVE_VMINAs8	= 1236,
+    ARM_MVE_VMINNMAVf16	= 1237,
+    ARM_MVE_VMINNMAVf32	= 1238,
+    ARM_MVE_VMINNMAf16	= 1239,
+    ARM_MVE_VMINNMAf32	= 1240,
+    ARM_MVE_VMINNMVf16	= 1241,
+    ARM_MVE_VMINNMVf32	= 1242,
+    ARM_MVE_VMINNMf16	= 1243,
+    ARM_MVE_VMINNMf32	= 1244,
+    ARM_MVE_VMINVs16	= 1245,
+    ARM_MVE_VMINVs32	= 1246,
+    ARM_MVE_VMINVs8	= 1247,
+    ARM_MVE_VMINVu16	= 1248,
+    ARM_MVE_VMINVu32	= 1249,
+    ARM_MVE_VMINVu8	= 1250,
+    ARM_MVE_VMINs16	= 1251,
+    ARM_MVE_VMINs32	= 1252,
+    ARM_MVE_VMINs8	= 1253,
+    ARM_MVE_VMINu16	= 1254,
+    ARM_MVE_VMINu32	= 1255,
+    ARM_MVE_VMINu8	= 1256,
+    ARM_MVE_VMLADAVas16	= 1257,
+    ARM_MVE_VMLADAVas32	= 1258,
+    ARM_MVE_VMLADAVas8	= 1259,
+    ARM_MVE_VMLADAVau16	= 1260,
+    ARM_MVE_VMLADAVau32	= 1261,
+    ARM_MVE_VMLADAVau8	= 1262,
+    ARM_MVE_VMLADAVaxs16	= 1263,
+    ARM_MVE_VMLADAVaxs32	= 1264,
+    ARM_MVE_VMLADAVaxs8	= 1265,
+    ARM_MVE_VMLADAVs16	= 1266,
+    ARM_MVE_VMLADAVs32	= 1267,
+    ARM_MVE_VMLADAVs8	= 1268,
+    ARM_MVE_VMLADAVu16	= 1269,
+    ARM_MVE_VMLADAVu32	= 1270,
+    ARM_MVE_VMLADAVu8	= 1271,
+    ARM_MVE_VMLADAVxs16	= 1272,
+    ARM_MVE_VMLADAVxs32	= 1273,
+    ARM_MVE_VMLADAVxs8	= 1274,
+    ARM_MVE_VMLALDAVas16	= 1275,
+    ARM_MVE_VMLALDAVas32	= 1276,
+    ARM_MVE_VMLALDAVau16	= 1277,
+    ARM_MVE_VMLALDAVau32	= 1278,
+    ARM_MVE_VMLALDAVaxs16	= 1279,
+    ARM_MVE_VMLALDAVaxs32	= 1280,
+    ARM_MVE_VMLALDAVs16	= 1281,
+    ARM_MVE_VMLALDAVs32	= 1282,
+    ARM_MVE_VMLALDAVu16	= 1283,
+    ARM_MVE_VMLALDAVu32	= 1284,
+    ARM_MVE_VMLALDAVxs16	= 1285,
+    ARM_MVE_VMLALDAVxs32	= 1286,
+    ARM_MVE_VMLAS_qr_i16	= 1287,
+    ARM_MVE_VMLAS_qr_i32	= 1288,
+    ARM_MVE_VMLAS_qr_i8	= 1289,
+    ARM_MVE_VMLA_qr_i16	= 1290,
+    ARM_MVE_VMLA_qr_i32	= 1291,
+    ARM_MVE_VMLA_qr_i8	= 1292,
+    ARM_MVE_VMLSDAVas16	= 1293,
+    ARM_MVE_VMLSDAVas32	= 1294,
+    ARM_MVE_VMLSDAVas8	= 1295,
+    ARM_MVE_VMLSDAVaxs16	= 1296,
+    ARM_MVE_VMLSDAVaxs32	= 1297,
+    ARM_MVE_VMLSDAVaxs8	= 1298,
+    ARM_MVE_VMLSDAVs16	= 1299,
+    ARM_MVE_VMLSDAVs32	= 1300,
+    ARM_MVE_VMLSDAVs8	= 1301,
+    ARM_MVE_VMLSDAVxs16	= 1302,
+    ARM_MVE_VMLSDAVxs32	= 1303,
+    ARM_MVE_VMLSDAVxs8	= 1304,
+    ARM_MVE_VMLSLDAVas16	= 1305,
+    ARM_MVE_VMLSLDAVas32	= 1306,
+    ARM_MVE_VMLSLDAVaxs16	= 1307,
+    ARM_MVE_VMLSLDAVaxs32	= 1308,
+    ARM_MVE_VMLSLDAVs16	= 1309,
+    ARM_MVE_VMLSLDAVs32	= 1310,
+    ARM_MVE_VMLSLDAVxs16	= 1311,
+    ARM_MVE_VMLSLDAVxs32	= 1312,
+    ARM_MVE_VMOVLs16bh	= 1313,
+    ARM_MVE_VMOVLs16th	= 1314,
+    ARM_MVE_VMOVLs8bh	= 1315,
+    ARM_MVE_VMOVLs8th	= 1316,
+    ARM_MVE_VMOVLu16bh	= 1317,
+    ARM_MVE_VMOVLu16th	= 1318,
+    ARM_MVE_VMOVLu8bh	= 1319,
+    ARM_MVE_VMOVLu8th	= 1320,
+    ARM_MVE_VMOVNi16bh	= 1321,
+    ARM_MVE_VMOVNi16th	= 1322,
+    ARM_MVE_VMOVNi32bh	= 1323,
+    ARM_MVE_VMOVNi32th	= 1324,
+    ARM_MVE_VMOV_from_lane_32	= 1325,
+    ARM_MVE_VMOV_from_lane_s16	= 1326,
+    ARM_MVE_VMOV_from_lane_s8	= 1327,
+    ARM_MVE_VMOV_from_lane_u16	= 1328,
+    ARM_MVE_VMOV_from_lane_u8	= 1329,
+    ARM_MVE_VMOV_q_rr	= 1330,
+    ARM_MVE_VMOV_rr_q	= 1331,
+    ARM_MVE_VMOV_to_lane_16	= 1332,
+    ARM_MVE_VMOV_to_lane_32	= 1333,
+    ARM_MVE_VMOV_to_lane_8	= 1334,
+    ARM_MVE_VMOVimmf32	= 1335,
+    ARM_MVE_VMOVimmi16	= 1336,
+    ARM_MVE_VMOVimmi32	= 1337,
+    ARM_MVE_VMOVimmi64	= 1338,
+    ARM_MVE_VMOVimmi8	= 1339,
+    ARM_MVE_VMULHs16	= 1340,
+    ARM_MVE_VMULHs32	= 1341,
+    ARM_MVE_VMULHs8	= 1342,
+    ARM_MVE_VMULHu16	= 1343,
+    ARM_MVE_VMULHu32	= 1344,
+    ARM_MVE_VMULHu8	= 1345,
+    ARM_MVE_VMULLBp16	= 1346,
+    ARM_MVE_VMULLBp8	= 1347,
+    ARM_MVE_VMULLBs16	= 1348,
+    ARM_MVE_VMULLBs32	= 1349,
+    ARM_MVE_VMULLBs8	= 1350,
+    ARM_MVE_VMULLBu16	= 1351,
+    ARM_MVE_VMULLBu32	= 1352,
+    ARM_MVE_VMULLBu8	= 1353,
+    ARM_MVE_VMULLTp16	= 1354,
+    ARM_MVE_VMULLTp8	= 1355,
+    ARM_MVE_VMULLTs16	= 1356,
+    ARM_MVE_VMULLTs32	= 1357,
+    ARM_MVE_VMULLTs8	= 1358,
+    ARM_MVE_VMULLTu16	= 1359,
+    ARM_MVE_VMULLTu32	= 1360,
+    ARM_MVE_VMULLTu8	= 1361,
+    ARM_MVE_VMUL_qr_f16	= 1362,
+    ARM_MVE_VMUL_qr_f32	= 1363,
+    ARM_MVE_VMUL_qr_i16	= 1364,
+    ARM_MVE_VMUL_qr_i32	= 1365,
+    ARM_MVE_VMUL_qr_i8	= 1366,
+    ARM_MVE_VMULf16	= 1367,
+    ARM_MVE_VMULf32	= 1368,
+    ARM_MVE_VMULi16	= 1369,
+    ARM_MVE_VMULi32	= 1370,
+    ARM_MVE_VMULi8	= 1371,
+    ARM_MVE_VMVN	= 1372,
+    ARM_MVE_VMVNimmi16	= 1373,
+    ARM_MVE_VMVNimmi32	= 1374,
+    ARM_MVE_VNEGf16	= 1375,
+    ARM_MVE_VNEGf32	= 1376,
+    ARM_MVE_VNEGs16	= 1377,
+    ARM_MVE_VNEGs32	= 1378,
+    ARM_MVE_VNEGs8	= 1379,
+    ARM_MVE_VORN	= 1380,
+    ARM_MVE_VORR	= 1381,
+    ARM_MVE_VORRimmi16	= 1382,
+    ARM_MVE_VORRimmi32	= 1383,
+    ARM_MVE_VPNOT	= 1384,
+    ARM_MVE_VPSEL	= 1385,
+    ARM_MVE_VPST	= 1386,
+    ARM_MVE_VPTv16i8	= 1387,
+    ARM_MVE_VPTv16i8r	= 1388,
+    ARM_MVE_VPTv16s8	= 1389,
+    ARM_MVE_VPTv16s8r	= 1390,
+    ARM_MVE_VPTv16u8	= 1391,
+    ARM_MVE_VPTv16u8r	= 1392,
+    ARM_MVE_VPTv4f32	= 1393,
+    ARM_MVE_VPTv4f32r	= 1394,
+    ARM_MVE_VPTv4i32	= 1395,
+    ARM_MVE_VPTv4i32r	= 1396,
+    ARM_MVE_VPTv4s32	= 1397,
+    ARM_MVE_VPTv4s32r	= 1398,
+    ARM_MVE_VPTv4u32	= 1399,
+    ARM_MVE_VPTv4u32r	= 1400,
+    ARM_MVE_VPTv8f16	= 1401,
+    ARM_MVE_VPTv8f16r	= 1402,
+    ARM_MVE_VPTv8i16	= 1403,
+    ARM_MVE_VPTv8i16r	= 1404,
+    ARM_MVE_VPTv8s16	= 1405,
+    ARM_MVE_VPTv8s16r	= 1406,
+    ARM_MVE_VPTv8u16	= 1407,
+    ARM_MVE_VPTv8u16r	= 1408,
+    ARM_MVE_VQABSs16	= 1409,
+    ARM_MVE_VQABSs32	= 1410,
+    ARM_MVE_VQABSs8	= 1411,
+    ARM_MVE_VQADD_qr_s16	= 1412,
+    ARM_MVE_VQADD_qr_s32	= 1413,
+    ARM_MVE_VQADD_qr_s8	= 1414,
+    ARM_MVE_VQADD_qr_u16	= 1415,
+    ARM_MVE_VQADD_qr_u32	= 1416,
+    ARM_MVE_VQADD_qr_u8	= 1417,
+    ARM_MVE_VQADDs16	= 1418,
+    ARM_MVE_VQADDs32	= 1419,
+    ARM_MVE_VQADDs8	= 1420,
+    ARM_MVE_VQADDu16	= 1421,
+    ARM_MVE_VQADDu32	= 1422,
+    ARM_MVE_VQADDu8	= 1423,
+    ARM_MVE_VQDMLADHXs16	= 1424,
+    ARM_MVE_VQDMLADHXs32	= 1425,
+    ARM_MVE_VQDMLADHXs8	= 1426,
+    ARM_MVE_VQDMLADHs16	= 1427,
+    ARM_MVE_VQDMLADHs32	= 1428,
+    ARM_MVE_VQDMLADHs8	= 1429,
+    ARM_MVE_VQDMLAH_qrs16	= 1430,
+    ARM_MVE_VQDMLAH_qrs32	= 1431,
+    ARM_MVE_VQDMLAH_qrs8	= 1432,
+    ARM_MVE_VQDMLASH_qrs16	= 1433,
+    ARM_MVE_VQDMLASH_qrs32	= 1434,
+    ARM_MVE_VQDMLASH_qrs8	= 1435,
+    ARM_MVE_VQDMLSDHXs16	= 1436,
+    ARM_MVE_VQDMLSDHXs32	= 1437,
+    ARM_MVE_VQDMLSDHXs8	= 1438,
+    ARM_MVE_VQDMLSDHs16	= 1439,
+    ARM_MVE_VQDMLSDHs32	= 1440,
+    ARM_MVE_VQDMLSDHs8	= 1441,
+    ARM_MVE_VQDMULH_qr_s16	= 1442,
+    ARM_MVE_VQDMULH_qr_s32	= 1443,
+    ARM_MVE_VQDMULH_qr_s8	= 1444,
+    ARM_MVE_VQDMULHi16	= 1445,
+    ARM_MVE_VQDMULHi32	= 1446,
+    ARM_MVE_VQDMULHi8	= 1447,
+    ARM_MVE_VQDMULL_qr_s16bh	= 1448,
+    ARM_MVE_VQDMULL_qr_s16th	= 1449,
+    ARM_MVE_VQDMULL_qr_s32bh	= 1450,
+    ARM_MVE_VQDMULL_qr_s32th	= 1451,
+    ARM_MVE_VQDMULLs16bh	= 1452,
+    ARM_MVE_VQDMULLs16th	= 1453,
+    ARM_MVE_VQDMULLs32bh	= 1454,
+    ARM_MVE_VQDMULLs32th	= 1455,
+    ARM_MVE_VQMOVNs16bh	= 1456,
+    ARM_MVE_VQMOVNs16th	= 1457,
+    ARM_MVE_VQMOVNs32bh	= 1458,
+    ARM_MVE_VQMOVNs32th	= 1459,
+    ARM_MVE_VQMOVNu16bh	= 1460,
+    ARM_MVE_VQMOVNu16th	= 1461,
+    ARM_MVE_VQMOVNu32bh	= 1462,
+    ARM_MVE_VQMOVNu32th	= 1463,
+    ARM_MVE_VQMOVUNs16bh	= 1464,
+    ARM_MVE_VQMOVUNs16th	= 1465,
+    ARM_MVE_VQMOVUNs32bh	= 1466,
+    ARM_MVE_VQMOVUNs32th	= 1467,
+    ARM_MVE_VQNEGs16	= 1468,
+    ARM_MVE_VQNEGs32	= 1469,
+    ARM_MVE_VQNEGs8	= 1470,
+    ARM_MVE_VQRDMLADHXs16	= 1471,
+    ARM_MVE_VQRDMLADHXs32	= 1472,
+    ARM_MVE_VQRDMLADHXs8	= 1473,
+    ARM_MVE_VQRDMLADHs16	= 1474,
+    ARM_MVE_VQRDMLADHs32	= 1475,
+    ARM_MVE_VQRDMLADHs8	= 1476,
+    ARM_MVE_VQRDMLAH_qrs16	= 1477,
+    ARM_MVE_VQRDMLAH_qrs32	= 1478,
+    ARM_MVE_VQRDMLAH_qrs8	= 1479,
+    ARM_MVE_VQRDMLASH_qrs16	= 1480,
+    ARM_MVE_VQRDMLASH_qrs32	= 1481,
+    ARM_MVE_VQRDMLASH_qrs8	= 1482,
+    ARM_MVE_VQRDMLSDHXs16	= 1483,
+    ARM_MVE_VQRDMLSDHXs32	= 1484,
+    ARM_MVE_VQRDMLSDHXs8	= 1485,
+    ARM_MVE_VQRDMLSDHs16	= 1486,
+    ARM_MVE_VQRDMLSDHs32	= 1487,
+    ARM_MVE_VQRDMLSDHs8	= 1488,
+    ARM_MVE_VQRDMULH_qr_s16	= 1489,
+    ARM_MVE_VQRDMULH_qr_s32	= 1490,
+    ARM_MVE_VQRDMULH_qr_s8	= 1491,
+    ARM_MVE_VQRDMULHi16	= 1492,
+    ARM_MVE_VQRDMULHi32	= 1493,
+    ARM_MVE_VQRDMULHi8	= 1494,
+    ARM_MVE_VQRSHL_by_vecs16	= 1495,
+    ARM_MVE_VQRSHL_by_vecs32	= 1496,
+    ARM_MVE_VQRSHL_by_vecs8	= 1497,
+    ARM_MVE_VQRSHL_by_vecu16	= 1498,
+    ARM_MVE_VQRSHL_by_vecu32	= 1499,
+    ARM_MVE_VQRSHL_by_vecu8	= 1500,
+    ARM_MVE_VQRSHL_qrs16	= 1501,
+    ARM_MVE_VQRSHL_qrs32	= 1502,
+    ARM_MVE_VQRSHL_qrs8	= 1503,
+    ARM_MVE_VQRSHL_qru16	= 1504,
+    ARM_MVE_VQRSHL_qru32	= 1505,
+    ARM_MVE_VQRSHL_qru8	= 1506,
+    ARM_MVE_VQRSHRNbhs16	= 1507,
+    ARM_MVE_VQRSHRNbhs32	= 1508,
+    ARM_MVE_VQRSHRNbhu16	= 1509,
+    ARM_MVE_VQRSHRNbhu32	= 1510,
+    ARM_MVE_VQRSHRNths16	= 1511,
+    ARM_MVE_VQRSHRNths32	= 1512,
+    ARM_MVE_VQRSHRNthu16	= 1513,
+    ARM_MVE_VQRSHRNthu32	= 1514,
+    ARM_MVE_VQRSHRUNs16bh	= 1515,
+    ARM_MVE_VQRSHRUNs16th	= 1516,
+    ARM_MVE_VQRSHRUNs32bh	= 1517,
+    ARM_MVE_VQRSHRUNs32th	= 1518,
+    ARM_MVE_VQSHLU_imms16	= 1519,
+    ARM_MVE_VQSHLU_imms32	= 1520,
+    ARM_MVE_VQSHLU_imms8	= 1521,
+    ARM_MVE_VQSHL_by_vecs16	= 1522,
+    ARM_MVE_VQSHL_by_vecs32	= 1523,
+    ARM_MVE_VQSHL_by_vecs8	= 1524,
+    ARM_MVE_VQSHL_by_vecu16	= 1525,
+    ARM_MVE_VQSHL_by_vecu32	= 1526,
+    ARM_MVE_VQSHL_by_vecu8	= 1527,
+    ARM_MVE_VQSHL_qrs16	= 1528,
+    ARM_MVE_VQSHL_qrs32	= 1529,
+    ARM_MVE_VQSHL_qrs8	= 1530,
+    ARM_MVE_VQSHL_qru16	= 1531,
+    ARM_MVE_VQSHL_qru32	= 1532,
+    ARM_MVE_VQSHL_qru8	= 1533,
+    ARM_MVE_VQSHLimms16	= 1534,
+    ARM_MVE_VQSHLimms32	= 1535,
+    ARM_MVE_VQSHLimms8	= 1536,
+    ARM_MVE_VQSHLimmu16	= 1537,
+    ARM_MVE_VQSHLimmu32	= 1538,
+    ARM_MVE_VQSHLimmu8	= 1539,
+    ARM_MVE_VQSHRNbhs16	= 1540,
+    ARM_MVE_VQSHRNbhs32	= 1541,
+    ARM_MVE_VQSHRNbhu16	= 1542,
+    ARM_MVE_VQSHRNbhu32	= 1543,
+    ARM_MVE_VQSHRNths16	= 1544,
+    ARM_MVE_VQSHRNths32	= 1545,
+    ARM_MVE_VQSHRNthu16	= 1546,
+    ARM_MVE_VQSHRNthu32	= 1547,
+    ARM_MVE_VQSHRUNs16bh	= 1548,
+    ARM_MVE_VQSHRUNs16th	= 1549,
+    ARM_MVE_VQSHRUNs32bh	= 1550,
+    ARM_MVE_VQSHRUNs32th	= 1551,
+    ARM_MVE_VQSUB_qr_s16	= 1552,
+    ARM_MVE_VQSUB_qr_s32	= 1553,
+    ARM_MVE_VQSUB_qr_s8	= 1554,
+    ARM_MVE_VQSUB_qr_u16	= 1555,
+    ARM_MVE_VQSUB_qr_u32	= 1556,
+    ARM_MVE_VQSUB_qr_u8	= 1557,
+    ARM_MVE_VQSUBs16	= 1558,
+    ARM_MVE_VQSUBs32	= 1559,
+    ARM_MVE_VQSUBs8	= 1560,
+    ARM_MVE_VQSUBu16	= 1561,
+    ARM_MVE_VQSUBu32	= 1562,
+    ARM_MVE_VQSUBu8	= 1563,
+    ARM_MVE_VREV16_8	= 1564,
+    ARM_MVE_VREV32_16	= 1565,
+    ARM_MVE_VREV32_8	= 1566,
+    ARM_MVE_VREV64_16	= 1567,
+    ARM_MVE_VREV64_32	= 1568,
+    ARM_MVE_VREV64_8	= 1569,
+    ARM_MVE_VRHADDs16	= 1570,
+    ARM_MVE_VRHADDs32	= 1571,
+    ARM_MVE_VRHADDs8	= 1572,
+    ARM_MVE_VRHADDu16	= 1573,
+    ARM_MVE_VRHADDu32	= 1574,
+    ARM_MVE_VRHADDu8	= 1575,
+    ARM_MVE_VRINTf16A	= 1576,
+    ARM_MVE_VRINTf16M	= 1577,
+    ARM_MVE_VRINTf16N	= 1578,
+    ARM_MVE_VRINTf16P	= 1579,
+    ARM_MVE_VRINTf16X	= 1580,
+    ARM_MVE_VRINTf16Z	= 1581,
+    ARM_MVE_VRINTf32A	= 1582,
+    ARM_MVE_VRINTf32M	= 1583,
+    ARM_MVE_VRINTf32N	= 1584,
+    ARM_MVE_VRINTf32P	= 1585,
+    ARM_MVE_VRINTf32X	= 1586,
+    ARM_MVE_VRINTf32Z	= 1587,
+    ARM_MVE_VRMLALDAVHas32	= 1588,
+    ARM_MVE_VRMLALDAVHau32	= 1589,
+    ARM_MVE_VRMLALDAVHaxs32	= 1590,
+    ARM_MVE_VRMLALDAVHs32	= 1591,
+    ARM_MVE_VRMLALDAVHu32	= 1592,
+    ARM_MVE_VRMLALDAVHxs32	= 1593,
+    ARM_MVE_VRMLSLDAVHas32	= 1594,
+    ARM_MVE_VRMLSLDAVHaxs32	= 1595,
+    ARM_MVE_VRMLSLDAVHs32	= 1596,
+    ARM_MVE_VRMLSLDAVHxs32	= 1597,
+    ARM_MVE_VRMULHs16	= 1598,
+    ARM_MVE_VRMULHs32	= 1599,
+    ARM_MVE_VRMULHs8	= 1600,
+    ARM_MVE_VRMULHu16	= 1601,
+    ARM_MVE_VRMULHu32	= 1602,
+    ARM_MVE_VRMULHu8	= 1603,
+    ARM_MVE_VRSHL_by_vecs16	= 1604,
+    ARM_MVE_VRSHL_by_vecs32	= 1605,
+    ARM_MVE_VRSHL_by_vecs8	= 1606,
+    ARM_MVE_VRSHL_by_vecu16	= 1607,
+    ARM_MVE_VRSHL_by_vecu32	= 1608,
+    ARM_MVE_VRSHL_by_vecu8	= 1609,
+    ARM_MVE_VRSHL_qrs16	= 1610,
+    ARM_MVE_VRSHL_qrs32	= 1611,
+    ARM_MVE_VRSHL_qrs8	= 1612,
+    ARM_MVE_VRSHL_qru16	= 1613,
+    ARM_MVE_VRSHL_qru32	= 1614,
+    ARM_MVE_VRSHL_qru8	= 1615,
+    ARM_MVE_VRSHRNi16bh	= 1616,
+    ARM_MVE_VRSHRNi16th	= 1617,
+    ARM_MVE_VRSHRNi32bh	= 1618,
+    ARM_MVE_VRSHRNi32th	= 1619,
+    ARM_MVE_VRSHR_imms16	= 1620,
+    ARM_MVE_VRSHR_imms32	= 1621,
+    ARM_MVE_VRSHR_imms8	= 1622,
+    ARM_MVE_VRSHR_immu16	= 1623,
+    ARM_MVE_VRSHR_immu32	= 1624,
+    ARM_MVE_VRSHR_immu8	= 1625,
+    ARM_MVE_VSBC	= 1626,
+    ARM_MVE_VSBCI	= 1627,
+    ARM_MVE_VSHLC	= 1628,
+    ARM_MVE_VSHLL_imms16bh	= 1629,
+    ARM_MVE_VSHLL_imms16th	= 1630,
+    ARM_MVE_VSHLL_imms8bh	= 1631,
+    ARM_MVE_VSHLL_imms8th	= 1632,
+    ARM_MVE_VSHLL_immu16bh	= 1633,
+    ARM_MVE_VSHLL_immu16th	= 1634,
+    ARM_MVE_VSHLL_immu8bh	= 1635,
+    ARM_MVE_VSHLL_immu8th	= 1636,
+    ARM_MVE_VSHLL_lws16bh	= 1637,
+    ARM_MVE_VSHLL_lws16th	= 1638,
+    ARM_MVE_VSHLL_lws8bh	= 1639,
+    ARM_MVE_VSHLL_lws8th	= 1640,
+    ARM_MVE_VSHLL_lwu16bh	= 1641,
+    ARM_MVE_VSHLL_lwu16th	= 1642,
+    ARM_MVE_VSHLL_lwu8bh	= 1643,
+    ARM_MVE_VSHLL_lwu8th	= 1644,
+    ARM_MVE_VSHL_by_vecs16	= 1645,
+    ARM_MVE_VSHL_by_vecs32	= 1646,
+    ARM_MVE_VSHL_by_vecs8	= 1647,
+    ARM_MVE_VSHL_by_vecu16	= 1648,
+    ARM_MVE_VSHL_by_vecu32	= 1649,
+    ARM_MVE_VSHL_by_vecu8	= 1650,
+    ARM_MVE_VSHL_immi16	= 1651,
+    ARM_MVE_VSHL_immi32	= 1652,
+    ARM_MVE_VSHL_immi8	= 1653,
+    ARM_MVE_VSHL_qrs16	= 1654,
+    ARM_MVE_VSHL_qrs32	= 1655,
+    ARM_MVE_VSHL_qrs8	= 1656,
+    ARM_MVE_VSHL_qru16	= 1657,
+    ARM_MVE_VSHL_qru32	= 1658,
+    ARM_MVE_VSHL_qru8	= 1659,
+    ARM_MVE_VSHRNi16bh	= 1660,
+    ARM_MVE_VSHRNi16th	= 1661,
+    ARM_MVE_VSHRNi32bh	= 1662,
+    ARM_MVE_VSHRNi32th	= 1663,
+    ARM_MVE_VSHR_imms16	= 1664,
+    ARM_MVE_VSHR_imms32	= 1665,
+    ARM_MVE_VSHR_imms8	= 1666,
+    ARM_MVE_VSHR_immu16	= 1667,
+    ARM_MVE_VSHR_immu32	= 1668,
+    ARM_MVE_VSHR_immu8	= 1669,
+    ARM_MVE_VSLIimm16	= 1670,
+    ARM_MVE_VSLIimm32	= 1671,
+    ARM_MVE_VSLIimm8	= 1672,
+    ARM_MVE_VSRIimm16	= 1673,
+    ARM_MVE_VSRIimm32	= 1674,
+    ARM_MVE_VSRIimm8	= 1675,
+    ARM_MVE_VST20_16	= 1676,
+    ARM_MVE_VST20_16_wb	= 1677,
+    ARM_MVE_VST20_32	= 1678,
+    ARM_MVE_VST20_32_wb	= 1679,
+    ARM_MVE_VST20_8	= 1680,
+    ARM_MVE_VST20_8_wb	= 1681,
+    ARM_MVE_VST21_16	= 1682,
+    ARM_MVE_VST21_16_wb	= 1683,
+    ARM_MVE_VST21_32	= 1684,
+    ARM_MVE_VST21_32_wb	= 1685,
+    ARM_MVE_VST21_8	= 1686,
+    ARM_MVE_VST21_8_wb	= 1687,
+    ARM_MVE_VST40_16	= 1688,
+    ARM_MVE_VST40_16_wb	= 1689,
+    ARM_MVE_VST40_32	= 1690,
+    ARM_MVE_VST40_32_wb	= 1691,
+    ARM_MVE_VST40_8	= 1692,
+    ARM_MVE_VST40_8_wb	= 1693,
+    ARM_MVE_VST41_16	= 1694,
+    ARM_MVE_VST41_16_wb	= 1695,
+    ARM_MVE_VST41_32	= 1696,
+    ARM_MVE_VST41_32_wb	= 1697,
+    ARM_MVE_VST41_8	= 1698,
+    ARM_MVE_VST41_8_wb	= 1699,
+    ARM_MVE_VST42_16	= 1700,
+    ARM_MVE_VST42_16_wb	= 1701,
+    ARM_MVE_VST42_32	= 1702,
+    ARM_MVE_VST42_32_wb	= 1703,
+    ARM_MVE_VST42_8	= 1704,
+    ARM_MVE_VST42_8_wb	= 1705,
+    ARM_MVE_VST43_16	= 1706,
+    ARM_MVE_VST43_16_wb	= 1707,
+    ARM_MVE_VST43_32	= 1708,
+    ARM_MVE_VST43_32_wb	= 1709,
+    ARM_MVE_VST43_8	= 1710,
+    ARM_MVE_VST43_8_wb	= 1711,
+    ARM_MVE_VSTRB16	= 1712,
+    ARM_MVE_VSTRB16_post	= 1713,
+    ARM_MVE_VSTRB16_pre	= 1714,
+    ARM_MVE_VSTRB16_rq	= 1715,
+    ARM_MVE_VSTRB32	= 1716,
+    ARM_MVE_VSTRB32_post	= 1717,
+    ARM_MVE_VSTRB32_pre	= 1718,
+    ARM_MVE_VSTRB32_rq	= 1719,
+    ARM_MVE_VSTRB8_rq	= 1720,
+    ARM_MVE_VSTRBU8	= 1721,
+    ARM_MVE_VSTRBU8_post	= 1722,
+    ARM_MVE_VSTRBU8_pre	= 1723,
+    ARM_MVE_VSTRD64_qi	= 1724,
+    ARM_MVE_VSTRD64_qi_pre	= 1725,
+    ARM_MVE_VSTRD64_rq	= 1726,
+    ARM_MVE_VSTRD64_rq_u	= 1727,
+    ARM_MVE_VSTRH16_rq	= 1728,
+    ARM_MVE_VSTRH16_rq_u	= 1729,
+    ARM_MVE_VSTRH32	= 1730,
+    ARM_MVE_VSTRH32_post	= 1731,
+    ARM_MVE_VSTRH32_pre	= 1732,
+    ARM_MVE_VSTRH32_rq	= 1733,
+    ARM_MVE_VSTRH32_rq_u	= 1734,
+    ARM_MVE_VSTRHU16	= 1735,
+    ARM_MVE_VSTRHU16_post	= 1736,
+    ARM_MVE_VSTRHU16_pre	= 1737,
+    ARM_MVE_VSTRW32_qi	= 1738,
+    ARM_MVE_VSTRW32_qi_pre	= 1739,
+    ARM_MVE_VSTRW32_rq	= 1740,
+    ARM_MVE_VSTRW32_rq_u	= 1741,
+    ARM_MVE_VSTRWU32	= 1742,
+    ARM_MVE_VSTRWU32_post	= 1743,
+    ARM_MVE_VSTRWU32_pre	= 1744,
+    ARM_MVE_VSUB_qr_f16	= 1745,
+    ARM_MVE_VSUB_qr_f32	= 1746,
+    ARM_MVE_VSUB_qr_i16	= 1747,
+    ARM_MVE_VSUB_qr_i32	= 1748,
+    ARM_MVE_VSUB_qr_i8	= 1749,
+    ARM_MVE_VSUBf16	= 1750,
+    ARM_MVE_VSUBf32	= 1751,
+    ARM_MVE_VSUBi16	= 1752,
+    ARM_MVE_VSUBi32	= 1753,
+    ARM_MVE_VSUBi8	= 1754,
+    ARM_MVE_WLSTP_16	= 1755,
+    ARM_MVE_WLSTP_32	= 1756,
+    ARM_MVE_WLSTP_64	= 1757,
+    ARM_MVE_WLSTP_8	= 1758,
+    ARM_MVNi	= 1759,
+    ARM_MVNr	= 1760,
+    ARM_MVNsi	= 1761,
+    ARM_MVNsr	= 1762,
+    ARM_NEON_VMAXNMNDf	= 1763,
+    ARM_NEON_VMAXNMNDh	= 1764,
+    ARM_NEON_VMAXNMNQf	= 1765,
+    ARM_NEON_VMAXNMNQh	= 1766,
+    ARM_NEON_VMINNMNDf	= 1767,
+    ARM_NEON_VMINNMNDh	= 1768,
+    ARM_NEON_VMINNMNQf	= 1769,
+    ARM_NEON_VMINNMNQh	= 1770,
+    ARM_ORRri	= 1771,
+    ARM_ORRrr	= 1772,
+    ARM_ORRrsi	= 1773,
+    ARM_ORRrsr	= 1774,
+    ARM_PKHBT	= 1775,
+    ARM_PKHTB	= 1776,
+    ARM_PLDWi12	= 1777,
+    ARM_PLDWrs	= 1778,
+    ARM_PLDi12	= 1779,
+    ARM_PLDrs	= 1780,
+    ARM_PLIi12	= 1781,
+    ARM_PLIrs	= 1782,
+    ARM_QADD	= 1783,
+    ARM_QADD16	= 1784,
+    ARM_QADD8	= 1785,
+    ARM_QASX	= 1786,
+    ARM_QDADD	= 1787,
+    ARM_QDSUB	= 1788,
+    ARM_QSAX	= 1789,
+    ARM_QSUB	= 1790,
+    ARM_QSUB16	= 1791,
+    ARM_QSUB8	= 1792,
+    ARM_RBIT	= 1793,
+    ARM_REV	= 1794,
+    ARM_REV16	= 1795,
+    ARM_REVSH	= 1796,
+    ARM_RFEDA	= 1797,
+    ARM_RFEDA_UPD	= 1798,
+    ARM_RFEDB	= 1799,
+    ARM_RFEDB_UPD	= 1800,
+    ARM_RFEIA	= 1801,
+    ARM_RFEIA_UPD	= 1802,
+    ARM_RFEIB	= 1803,
+    ARM_RFEIB_UPD	= 1804,
+    ARM_RSBri	= 1805,
+    ARM_RSBrr	= 1806,
+    ARM_RSBrsi	= 1807,
+    ARM_RSBrsr	= 1808,
+    ARM_RSCri	= 1809,
+    ARM_RSCrr	= 1810,
+    ARM_RSCrsi	= 1811,
+    ARM_RSCrsr	= 1812,
+    ARM_SADD16	= 1813,
+    ARM_SADD8	= 1814,
+    ARM_SASX	= 1815,
+    ARM_SB	= 1816,
+    ARM_SBCri	= 1817,
+    ARM_SBCrr	= 1818,
+    ARM_SBCrsi	= 1819,
+    ARM_SBCrsr	= 1820,
+    ARM_SBFX	= 1821,
+    ARM_SDIV	= 1822,
+    ARM_SEL	= 1823,
+    ARM_SETEND	= 1824,
+    ARM_SETPAN	= 1825,
+    ARM_SHA1C	= 1826,
+    ARM_SHA1H	= 1827,
+    ARM_SHA1M	= 1828,
+    ARM_SHA1P	= 1829,
+    ARM_SHA1SU0	= 1830,
+    ARM_SHA1SU1	= 1831,
+    ARM_SHA256H	= 1832,
+    ARM_SHA256H2	= 1833,
+    ARM_SHA256SU0	= 1834,
+    ARM_SHA256SU1	= 1835,
+    ARM_SHADD16	= 1836,
+    ARM_SHADD8	= 1837,
+    ARM_SHASX	= 1838,
+    ARM_SHSAX	= 1839,
+    ARM_SHSUB16	= 1840,
+    ARM_SHSUB8	= 1841,
+    ARM_SMC	= 1842,
+    ARM_SMLABB	= 1843,
+    ARM_SMLABT	= 1844,
+    ARM_SMLAD	= 1845,
+    ARM_SMLADX	= 1846,
+    ARM_SMLAL	= 1847,
+    ARM_SMLALBB	= 1848,
+    ARM_SMLALBT	= 1849,
+    ARM_SMLALD	= 1850,
+    ARM_SMLALDX	= 1851,
+    ARM_SMLALTB	= 1852,
+    ARM_SMLALTT	= 1853,
+    ARM_SMLATB	= 1854,
+    ARM_SMLATT	= 1855,
+    ARM_SMLAWB	= 1856,
+    ARM_SMLAWT	= 1857,
+    ARM_SMLSD	= 1858,
+    ARM_SMLSDX	= 1859,
+    ARM_SMLSLD	= 1860,
+    ARM_SMLSLDX	= 1861,
+    ARM_SMMLA	= 1862,
+    ARM_SMMLAR	= 1863,
+    ARM_SMMLS	= 1864,
+    ARM_SMMLSR	= 1865,
+    ARM_SMMUL	= 1866,
+    ARM_SMMULR	= 1867,
+    ARM_SMUAD	= 1868,
+    ARM_SMUADX	= 1869,
+    ARM_SMULBB	= 1870,
+    ARM_SMULBT	= 1871,
+    ARM_SMULL	= 1872,
+    ARM_SMULTB	= 1873,
+    ARM_SMULTT	= 1874,
+    ARM_SMULWB	= 1875,
+    ARM_SMULWT	= 1876,
+    ARM_SMUSD	= 1877,
+    ARM_SMUSDX	= 1878,
+    ARM_SRSDA	= 1879,
+    ARM_SRSDA_UPD	= 1880,
+    ARM_SRSDB	= 1881,
+    ARM_SRSDB_UPD	= 1882,
+    ARM_SRSIA	= 1883,
+    ARM_SRSIA_UPD	= 1884,
+    ARM_SRSIB	= 1885,
+    ARM_SRSIB_UPD	= 1886,
+    ARM_SSAT	= 1887,
+    ARM_SSAT16	= 1888,
+    ARM_SSAX	= 1889,
+    ARM_SSUB16	= 1890,
+    ARM_SSUB8	= 1891,
+    ARM_STC2L_OFFSET	= 1892,
+    ARM_STC2L_OPTION	= 1893,
+    ARM_STC2L_POST	= 1894,
+    ARM_STC2L_PRE	= 1895,
+    ARM_STC2_OFFSET	= 1896,
+    ARM_STC2_OPTION	= 1897,
+    ARM_STC2_POST	= 1898,
+    ARM_STC2_PRE	= 1899,
+    ARM_STCL_OFFSET	= 1900,
+    ARM_STCL_OPTION	= 1901,
+    ARM_STCL_POST	= 1902,
+    ARM_STCL_PRE	= 1903,
+    ARM_STC_OFFSET	= 1904,
+    ARM_STC_OPTION	= 1905,
+    ARM_STC_POST	= 1906,
+    ARM_STC_PRE	= 1907,
+    ARM_STL	= 1908,
+    ARM_STLB	= 1909,
+    ARM_STLEX	= 1910,
+    ARM_STLEXB	= 1911,
+    ARM_STLEXD	= 1912,
+    ARM_STLEXH	= 1913,
+    ARM_STLH	= 1914,
+    ARM_STMDA	= 1915,
+    ARM_STMDA_UPD	= 1916,
+    ARM_STMDB	= 1917,
+    ARM_STMDB_UPD	= 1918,
+    ARM_STMIA	= 1919,
+    ARM_STMIA_UPD	= 1920,
+    ARM_STMIB	= 1921,
+    ARM_STMIB_UPD	= 1922,
+    ARM_STRBT_POST_IMM	= 1923,
+    ARM_STRBT_POST_REG	= 1924,
+    ARM_STRB_POST_IMM	= 1925,
+    ARM_STRB_POST_REG	= 1926,
+    ARM_STRB_PRE_IMM	= 1927,
+    ARM_STRB_PRE_REG	= 1928,
+    ARM_STRBi12	= 1929,
+    ARM_STRBrs	= 1930,
+    ARM_STRD	= 1931,
+    ARM_STRD_POST	= 1932,
+    ARM_STRD_PRE	= 1933,
+    ARM_STREX	= 1934,
+    ARM_STREXB	= 1935,
+    ARM_STREXD	= 1936,
+    ARM_STREXH	= 1937,
+    ARM_STRH	= 1938,
+    ARM_STRHTi	= 1939,
+    ARM_STRHTr	= 1940,
+    ARM_STRH_POST	= 1941,
+    ARM_STRH_PRE	= 1942,
+    ARM_STRT_POST_IMM	= 1943,
+    ARM_STRT_POST_REG	= 1944,
+    ARM_STR_POST_IMM	= 1945,
+    ARM_STR_POST_REG	= 1946,
+    ARM_STR_PRE_IMM	= 1947,
+    ARM_STR_PRE_REG	= 1948,
+    ARM_STRi12	= 1949,
+    ARM_STRrs	= 1950,
+    ARM_SUBri	= 1951,
+    ARM_SUBrr	= 1952,
+    ARM_SUBrsi	= 1953,
+    ARM_SUBrsr	= 1954,
+    ARM_SVC	= 1955,
+    ARM_SWP	= 1956,
+    ARM_SWPB	= 1957,
+    ARM_SXTAB	= 1958,
+    ARM_SXTAB16	= 1959,
+    ARM_SXTAH	= 1960,
+    ARM_SXTB	= 1961,
+    ARM_SXTB16	= 1962,
+    ARM_SXTH	= 1963,
+    ARM_TEQri	= 1964,
+    ARM_TEQrr	= 1965,
+    ARM_TEQrsi	= 1966,
+    ARM_TEQrsr	= 1967,
+    ARM_TRAP	= 1968,
+    ARM_TRAPNaCl	= 1969,
+    ARM_TSB	= 1970,
+    ARM_TSTri	= 1971,
+    ARM_TSTrr	= 1972,
+    ARM_TSTrsi	= 1973,
+    ARM_TSTrsr	= 1974,
+    ARM_UADD16	= 1975,
+    ARM_UADD8	= 1976,
+    ARM_UASX	= 1977,
+    ARM_UBFX	= 1978,
+    ARM_UDF	= 1979,
+    ARM_UDIV	= 1980,
+    ARM_UHADD16	= 1981,
+    ARM_UHADD8	= 1982,
+    ARM_UHASX	= 1983,
+    ARM_UHSAX	= 1984,
+    ARM_UHSUB16	= 1985,
+    ARM_UHSUB8	= 1986,
+    ARM_UMAAL	= 1987,
+    ARM_UMLAL	= 1988,
+    ARM_UMULL	= 1989,
+    ARM_UQADD16	= 1990,
+    ARM_UQADD8	= 1991,
+    ARM_UQASX	= 1992,
+    ARM_UQSAX	= 1993,
+    ARM_UQSUB16	= 1994,
+    ARM_UQSUB8	= 1995,
+    ARM_USAD8	= 1996,
+    ARM_USADA8	= 1997,
+    ARM_USAT	= 1998,
+    ARM_USAT16	= 1999,
+    ARM_USAX	= 2000,
+    ARM_USUB16	= 2001,
+    ARM_USUB8	= 2002,
+    ARM_UXTAB	= 2003,
+    ARM_UXTAB16	= 2004,
+    ARM_UXTAH	= 2005,
+    ARM_UXTB	= 2006,
+    ARM_UXTB16	= 2007,
+    ARM_UXTH	= 2008,
+    ARM_VABALsv2i64	= 2009,
+    ARM_VABALsv4i32	= 2010,
+    ARM_VABALsv8i16	= 2011,
+    ARM_VABALuv2i64	= 2012,
+    ARM_VABALuv4i32	= 2013,
+    ARM_VABALuv8i16	= 2014,
+    ARM_VABAsv16i8	= 2015,
+    ARM_VABAsv2i32	= 2016,
+    ARM_VABAsv4i16	= 2017,
+    ARM_VABAsv4i32	= 2018,
+    ARM_VABAsv8i16	= 2019,
+    ARM_VABAsv8i8	= 2020,
+    ARM_VABAuv16i8	= 2021,
+    ARM_VABAuv2i32	= 2022,
+    ARM_VABAuv4i16	= 2023,
+    ARM_VABAuv4i32	= 2024,
+    ARM_VABAuv8i16	= 2025,
+    ARM_VABAuv8i8	= 2026,
+    ARM_VABDLsv2i64	= 2027,
+    ARM_VABDLsv4i32	= 2028,
+    ARM_VABDLsv8i16	= 2029,
+    ARM_VABDLuv2i64	= 2030,
+    ARM_VABDLuv4i32	= 2031,
+    ARM_VABDLuv8i16	= 2032,
+    ARM_VABDfd	= 2033,
+    ARM_VABDfq	= 2034,
+    ARM_VABDhd	= 2035,
+    ARM_VABDhq	= 2036,
+    ARM_VABDsv16i8	= 2037,
+    ARM_VABDsv2i32	= 2038,
+    ARM_VABDsv4i16	= 2039,
+    ARM_VABDsv4i32	= 2040,
+    ARM_VABDsv8i16	= 2041,
+    ARM_VABDsv8i8	= 2042,
+    ARM_VABDuv16i8	= 2043,
+    ARM_VABDuv2i32	= 2044,
+    ARM_VABDuv4i16	= 2045,
+    ARM_VABDuv4i32	= 2046,
+    ARM_VABDuv8i16	= 2047,
+    ARM_VABDuv8i8	= 2048,
+    ARM_VABSD	= 2049,
+    ARM_VABSH	= 2050,
+    ARM_VABSS	= 2051,
+    ARM_VABSfd	= 2052,
+    ARM_VABSfq	= 2053,
+    ARM_VABShd	= 2054,
+    ARM_VABShq	= 2055,
+    ARM_VABSv16i8	= 2056,
+    ARM_VABSv2i32	= 2057,
+    ARM_VABSv4i16	= 2058,
+    ARM_VABSv4i32	= 2059,
+    ARM_VABSv8i16	= 2060,
+    ARM_VABSv8i8	= 2061,
+    ARM_VACGEfd	= 2062,
+    ARM_VACGEfq	= 2063,
+    ARM_VACGEhd	= 2064,
+    ARM_VACGEhq	= 2065,
+    ARM_VACGTfd	= 2066,
+    ARM_VACGTfq	= 2067,
+    ARM_VACGThd	= 2068,
+    ARM_VACGThq	= 2069,
+    ARM_VADDD	= 2070,
+    ARM_VADDH	= 2071,
+    ARM_VADDHNv2i32	= 2072,
+    ARM_VADDHNv4i16	= 2073,
+    ARM_VADDHNv8i8	= 2074,
+    ARM_VADDLsv2i64	= 2075,
+    ARM_VADDLsv4i32	= 2076,
+    ARM_VADDLsv8i16	= 2077,
+    ARM_VADDLuv2i64	= 2078,
+    ARM_VADDLuv4i32	= 2079,
+    ARM_VADDLuv8i16	= 2080,
+    ARM_VADDS	= 2081,
+    ARM_VADDWsv2i64	= 2082,
+    ARM_VADDWsv4i32	= 2083,
+    ARM_VADDWsv8i16	= 2084,
+    ARM_VADDWuv2i64	= 2085,
+    ARM_VADDWuv4i32	= 2086,
+    ARM_VADDWuv8i16	= 2087,
+    ARM_VADDfd	= 2088,
+    ARM_VADDfq	= 2089,
+    ARM_VADDhd	= 2090,
+    ARM_VADDhq	= 2091,
+    ARM_VADDv16i8	= 2092,
+    ARM_VADDv1i64	= 2093,
+    ARM_VADDv2i32	= 2094,
+    ARM_VADDv2i64	= 2095,
+    ARM_VADDv4i16	= 2096,
+    ARM_VADDv4i32	= 2097,
+    ARM_VADDv8i16	= 2098,
+    ARM_VADDv8i8	= 2099,
+    ARM_VANDd	= 2100,
+    ARM_VANDq	= 2101,
+    ARM_VBF16MALBQ	= 2102,
+    ARM_VBF16MALBQI	= 2103,
+    ARM_VBF16MALTQ	= 2104,
+    ARM_VBF16MALTQI	= 2105,
+    ARM_VBICd	= 2106,
+    ARM_VBICiv2i32	= 2107,
+    ARM_VBICiv4i16	= 2108,
+    ARM_VBICiv4i32	= 2109,
+    ARM_VBICiv8i16	= 2110,
+    ARM_VBICq	= 2111,
+    ARM_VBIFd	= 2112,
+    ARM_VBIFq	= 2113,
+    ARM_VBITd	= 2114,
+    ARM_VBITq	= 2115,
+    ARM_VBSLd	= 2116,
+    ARM_VBSLq	= 2117,
+    ARM_VBSPd	= 2118,
+    ARM_VBSPq	= 2119,
+    ARM_VCADDv2f32	= 2120,
+    ARM_VCADDv4f16	= 2121,
+    ARM_VCADDv4f32	= 2122,
+    ARM_VCADDv8f16	= 2123,
+    ARM_VCEQfd	= 2124,
+    ARM_VCEQfq	= 2125,
+    ARM_VCEQhd	= 2126,
+    ARM_VCEQhq	= 2127,
+    ARM_VCEQv16i8	= 2128,
+    ARM_VCEQv2i32	= 2129,
+    ARM_VCEQv4i16	= 2130,
+    ARM_VCEQv4i32	= 2131,
+    ARM_VCEQv8i16	= 2132,
+    ARM_VCEQv8i8	= 2133,
+    ARM_VCEQzv16i8	= 2134,
+    ARM_VCEQzv2f32	= 2135,
+    ARM_VCEQzv2i32	= 2136,
+    ARM_VCEQzv4f16	= 2137,
+    ARM_VCEQzv4f32	= 2138,
+    ARM_VCEQzv4i16	= 2139,
+    ARM_VCEQzv4i32	= 2140,
+    ARM_VCEQzv8f16	= 2141,
+    ARM_VCEQzv8i16	= 2142,
+    ARM_VCEQzv8i8	= 2143,
+    ARM_VCGEfd	= 2144,
+    ARM_VCGEfq	= 2145,
+    ARM_VCGEhd	= 2146,
+    ARM_VCGEhq	= 2147,
+    ARM_VCGEsv16i8	= 2148,
+    ARM_VCGEsv2i32	= 2149,
+    ARM_VCGEsv4i16	= 2150,
+    ARM_VCGEsv4i32	= 2151,
+    ARM_VCGEsv8i16	= 2152,
+    ARM_VCGEsv8i8	= 2153,
+    ARM_VCGEuv16i8	= 2154,
+    ARM_VCGEuv2i32	= 2155,
+    ARM_VCGEuv4i16	= 2156,
+    ARM_VCGEuv4i32	= 2157,
+    ARM_VCGEuv8i16	= 2158,
+    ARM_VCGEuv8i8	= 2159,
+    ARM_VCGEzv16i8	= 2160,
+    ARM_VCGEzv2f32	= 2161,
+    ARM_VCGEzv2i32	= 2162,
+    ARM_VCGEzv4f16	= 2163,
+    ARM_VCGEzv4f32	= 2164,
+    ARM_VCGEzv4i16	= 2165,
+    ARM_VCGEzv4i32	= 2166,
+    ARM_VCGEzv8f16	= 2167,
+    ARM_VCGEzv8i16	= 2168,
+    ARM_VCGEzv8i8	= 2169,
+    ARM_VCGTfd	= 2170,
+    ARM_VCGTfq	= 2171,
+    ARM_VCGThd	= 2172,
+    ARM_VCGThq	= 2173,
+    ARM_VCGTsv16i8	= 2174,
+    ARM_VCGTsv2i32	= 2175,
+    ARM_VCGTsv4i16	= 2176,
+    ARM_VCGTsv4i32	= 2177,
+    ARM_VCGTsv8i16	= 2178,
+    ARM_VCGTsv8i8	= 2179,
+    ARM_VCGTuv16i8	= 2180,
+    ARM_VCGTuv2i32	= 2181,
+    ARM_VCGTuv4i16	= 2182,
+    ARM_VCGTuv4i32	= 2183,
+    ARM_VCGTuv8i16	= 2184,
+    ARM_VCGTuv8i8	= 2185,
+    ARM_VCGTzv16i8	= 2186,
+    ARM_VCGTzv2f32	= 2187,
+    ARM_VCGTzv2i32	= 2188,
+    ARM_VCGTzv4f16	= 2189,
+    ARM_VCGTzv4f32	= 2190,
+    ARM_VCGTzv4i16	= 2191,
+    ARM_VCGTzv4i32	= 2192,
+    ARM_VCGTzv8f16	= 2193,
+    ARM_VCGTzv8i16	= 2194,
+    ARM_VCGTzv8i8	= 2195,
+    ARM_VCLEzv16i8	= 2196,
+    ARM_VCLEzv2f32	= 2197,
+    ARM_VCLEzv2i32	= 2198,
+    ARM_VCLEzv4f16	= 2199,
+    ARM_VCLEzv4f32	= 2200,
+    ARM_VCLEzv4i16	= 2201,
+    ARM_VCLEzv4i32	= 2202,
+    ARM_VCLEzv8f16	= 2203,
+    ARM_VCLEzv8i16	= 2204,
+    ARM_VCLEzv8i8	= 2205,
+    ARM_VCLSv16i8	= 2206,
+    ARM_VCLSv2i32	= 2207,
+    ARM_VCLSv4i16	= 2208,
+    ARM_VCLSv4i32	= 2209,
+    ARM_VCLSv8i16	= 2210,
+    ARM_VCLSv8i8	= 2211,
+    ARM_VCLTzv16i8	= 2212,
+    ARM_VCLTzv2f32	= 2213,
+    ARM_VCLTzv2i32	= 2214,
+    ARM_VCLTzv4f16	= 2215,
+    ARM_VCLTzv4f32	= 2216,
+    ARM_VCLTzv4i16	= 2217,
+    ARM_VCLTzv4i32	= 2218,
+    ARM_VCLTzv8f16	= 2219,
+    ARM_VCLTzv8i16	= 2220,
+    ARM_VCLTzv8i8	= 2221,
+    ARM_VCLZv16i8	= 2222,
+    ARM_VCLZv2i32	= 2223,
+    ARM_VCLZv4i16	= 2224,
+    ARM_VCLZv4i32	= 2225,
+    ARM_VCLZv8i16	= 2226,
+    ARM_VCLZv8i8	= 2227,
+    ARM_VCMLAv2f32	= 2228,
+    ARM_VCMLAv2f32_indexed	= 2229,
+    ARM_VCMLAv4f16	= 2230,
+    ARM_VCMLAv4f16_indexed	= 2231,
+    ARM_VCMLAv4f32	= 2232,
+    ARM_VCMLAv4f32_indexed	= 2233,
+    ARM_VCMLAv8f16	= 2234,
+    ARM_VCMLAv8f16_indexed	= 2235,
+    ARM_VCMPD	= 2236,
+    ARM_VCMPED	= 2237,
+    ARM_VCMPEH	= 2238,
+    ARM_VCMPES	= 2239,
+    ARM_VCMPEZD	= 2240,
+    ARM_VCMPEZH	= 2241,
+    ARM_VCMPEZS	= 2242,
+    ARM_VCMPH	= 2243,
+    ARM_VCMPS	= 2244,
+    ARM_VCMPZD	= 2245,
+    ARM_VCMPZH	= 2246,
+    ARM_VCMPZS	= 2247,
+    ARM_VCNTd	= 2248,
+    ARM_VCNTq	= 2249,
+    ARM_VCVTANSDf	= 2250,
+    ARM_VCVTANSDh	= 2251,
+    ARM_VCVTANSQf	= 2252,
+    ARM_VCVTANSQh	= 2253,
+    ARM_VCVTANUDf	= 2254,
+    ARM_VCVTANUDh	= 2255,
+    ARM_VCVTANUQf	= 2256,
+    ARM_VCVTANUQh	= 2257,
+    ARM_VCVTASD	= 2258,
+    ARM_VCVTASH	= 2259,
+    ARM_VCVTASS	= 2260,
+    ARM_VCVTAUD	= 2261,
+    ARM_VCVTAUH	= 2262,
+    ARM_VCVTAUS	= 2263,
+    ARM_VCVTBDH	= 2264,
+    ARM_VCVTBHD	= 2265,
+    ARM_VCVTBHS	= 2266,
+    ARM_VCVTBSH	= 2267,
+    ARM_VCVTDS	= 2268,
+    ARM_VCVTMNSDf	= 2269,
+    ARM_VCVTMNSDh	= 2270,
+    ARM_VCVTMNSQf	= 2271,
+    ARM_VCVTMNSQh	= 2272,
+    ARM_VCVTMNUDf	= 2273,
+    ARM_VCVTMNUDh	= 2274,
+    ARM_VCVTMNUQf	= 2275,
+    ARM_VCVTMNUQh	= 2276,
+    ARM_VCVTMSD	= 2277,
+    ARM_VCVTMSH	= 2278,
+    ARM_VCVTMSS	= 2279,
+    ARM_VCVTMUD	= 2280,
+    ARM_VCVTMUH	= 2281,
+    ARM_VCVTMUS	= 2282,
+    ARM_VCVTNNSDf	= 2283,
+    ARM_VCVTNNSDh	= 2284,
+    ARM_VCVTNNSQf	= 2285,
+    ARM_VCVTNNSQh	= 2286,
+    ARM_VCVTNNUDf	= 2287,
+    ARM_VCVTNNUDh	= 2288,
+    ARM_VCVTNNUQf	= 2289,
+    ARM_VCVTNNUQh	= 2290,
+    ARM_VCVTNSD	= 2291,
+    ARM_VCVTNSH	= 2292,
+    ARM_VCVTNSS	= 2293,
+    ARM_VCVTNUD	= 2294,
+    ARM_VCVTNUH	= 2295,
+    ARM_VCVTNUS	= 2296,
+    ARM_VCVTPNSDf	= 2297,
+    ARM_VCVTPNSDh	= 2298,
+    ARM_VCVTPNSQf	= 2299,
+    ARM_VCVTPNSQh	= 2300,
+    ARM_VCVTPNUDf	= 2301,
+    ARM_VCVTPNUDh	= 2302,
+    ARM_VCVTPNUQf	= 2303,
+    ARM_VCVTPNUQh	= 2304,
+    ARM_VCVTPSD	= 2305,
+    ARM_VCVTPSH	= 2306,
+    ARM_VCVTPSS	= 2307,
+    ARM_VCVTPUD	= 2308,
+    ARM_VCVTPUH	= 2309,
+    ARM_VCVTPUS	= 2310,
+    ARM_VCVTSD	= 2311,
+    ARM_VCVTTDH	= 2312,
+    ARM_VCVTTHD	= 2313,
+    ARM_VCVTTHS	= 2314,
+    ARM_VCVTTSH	= 2315,
+    ARM_VCVTf2h	= 2316,
+    ARM_VCVTf2sd	= 2317,
+    ARM_VCVTf2sq	= 2318,
+    ARM_VCVTf2ud	= 2319,
+    ARM_VCVTf2uq	= 2320,
+    ARM_VCVTf2xsd	= 2321,
+    ARM_VCVTf2xsq	= 2322,
+    ARM_VCVTf2xud	= 2323,
+    ARM_VCVTf2xuq	= 2324,
+    ARM_VCVTh2f	= 2325,
+    ARM_VCVTh2sd	= 2326,
+    ARM_VCVTh2sq	= 2327,
+    ARM_VCVTh2ud	= 2328,
+    ARM_VCVTh2uq	= 2329,
+    ARM_VCVTh2xsd	= 2330,
+    ARM_VCVTh2xsq	= 2331,
+    ARM_VCVTh2xud	= 2332,
+    ARM_VCVTh2xuq	= 2333,
+    ARM_VCVTs2fd	= 2334,
+    ARM_VCVTs2fq	= 2335,
+    ARM_VCVTs2hd	= 2336,
+    ARM_VCVTs2hq	= 2337,
+    ARM_VCVTu2fd	= 2338,
+    ARM_VCVTu2fq	= 2339,
+    ARM_VCVTu2hd	= 2340,
+    ARM_VCVTu2hq	= 2341,
+    ARM_VCVTxs2fd	= 2342,
+    ARM_VCVTxs2fq	= 2343,
+    ARM_VCVTxs2hd	= 2344,
+    ARM_VCVTxs2hq	= 2345,
+    ARM_VCVTxu2fd	= 2346,
+    ARM_VCVTxu2fq	= 2347,
+    ARM_VCVTxu2hd	= 2348,
+    ARM_VCVTxu2hq	= 2349,
+    ARM_VDIVD	= 2350,
+    ARM_VDIVH	= 2351,
+    ARM_VDIVS	= 2352,
+    ARM_VDUP16d	= 2353,
+    ARM_VDUP16q	= 2354,
+    ARM_VDUP32d	= 2355,
+    ARM_VDUP32q	= 2356,
+    ARM_VDUP8d	= 2357,
+    ARM_VDUP8q	= 2358,
+    ARM_VDUPLN16d	= 2359,
+    ARM_VDUPLN16q	= 2360,
+    ARM_VDUPLN32d	= 2361,
+    ARM_VDUPLN32q	= 2362,
+    ARM_VDUPLN8d	= 2363,
+    ARM_VDUPLN8q	= 2364,
+    ARM_VEORd	= 2365,
+    ARM_VEORq	= 2366,
+    ARM_VEXTd16	= 2367,
+    ARM_VEXTd32	= 2368,
+    ARM_VEXTd8	= 2369,
+    ARM_VEXTq16	= 2370,
+    ARM_VEXTq32	= 2371,
+    ARM_VEXTq64	= 2372,
+    ARM_VEXTq8	= 2373,
+    ARM_VFMAD	= 2374,
+    ARM_VFMAH	= 2375,
+    ARM_VFMALD	= 2376,
+    ARM_VFMALDI	= 2377,
+    ARM_VFMALQ	= 2378,
+    ARM_VFMALQI	= 2379,
+    ARM_VFMAS	= 2380,
+    ARM_VFMAfd	= 2381,
+    ARM_VFMAfq	= 2382,
+    ARM_VFMAhd	= 2383,
+    ARM_VFMAhq	= 2384,
+    ARM_VFMSD	= 2385,
+    ARM_VFMSH	= 2386,
+    ARM_VFMSLD	= 2387,
+    ARM_VFMSLDI	= 2388,
+    ARM_VFMSLQ	= 2389,
+    ARM_VFMSLQI	= 2390,
+    ARM_VFMSS	= 2391,
+    ARM_VFMSfd	= 2392,
+    ARM_VFMSfq	= 2393,
+    ARM_VFMShd	= 2394,
+    ARM_VFMShq	= 2395,
+    ARM_VFNMAD	= 2396,
+    ARM_VFNMAH	= 2397,
+    ARM_VFNMAS	= 2398,
+    ARM_VFNMSD	= 2399,
+    ARM_VFNMSH	= 2400,
+    ARM_VFNMSS	= 2401,
+    ARM_VFP_VMAXNMD	= 2402,
+    ARM_VFP_VMAXNMH	= 2403,
+    ARM_VFP_VMAXNMS	= 2404,
+    ARM_VFP_VMINNMD	= 2405,
+    ARM_VFP_VMINNMH	= 2406,
+    ARM_VFP_VMINNMS	= 2407,
+    ARM_VGETLNi32	= 2408,
+    ARM_VGETLNs16	= 2409,
+    ARM_VGETLNs8	= 2410,
+    ARM_VGETLNu16	= 2411,
+    ARM_VGETLNu8	= 2412,
+    ARM_VHADDsv16i8	= 2413,
+    ARM_VHADDsv2i32	= 2414,
+    ARM_VHADDsv4i16	= 2415,
+    ARM_VHADDsv4i32	= 2416,
+    ARM_VHADDsv8i16	= 2417,
+    ARM_VHADDsv8i8	= 2418,
+    ARM_VHADDuv16i8	= 2419,
+    ARM_VHADDuv2i32	= 2420,
+    ARM_VHADDuv4i16	= 2421,
+    ARM_VHADDuv4i32	= 2422,
+    ARM_VHADDuv8i16	= 2423,
+    ARM_VHADDuv8i8	= 2424,
+    ARM_VHSUBsv16i8	= 2425,
+    ARM_VHSUBsv2i32	= 2426,
+    ARM_VHSUBsv4i16	= 2427,
+    ARM_VHSUBsv4i32	= 2428,
+    ARM_VHSUBsv8i16	= 2429,
+    ARM_VHSUBsv8i8	= 2430,
+    ARM_VHSUBuv16i8	= 2431,
+    ARM_VHSUBuv2i32	= 2432,
+    ARM_VHSUBuv4i16	= 2433,
+    ARM_VHSUBuv4i32	= 2434,
+    ARM_VHSUBuv8i16	= 2435,
+    ARM_VHSUBuv8i8	= 2436,
+    ARM_VINSH	= 2437,
+    ARM_VJCVT	= 2438,
+    ARM_VLD1DUPd16	= 2439,
+    ARM_VLD1DUPd16wb_fixed	= 2440,
+    ARM_VLD1DUPd16wb_register	= 2441,
+    ARM_VLD1DUPd32	= 2442,
+    ARM_VLD1DUPd32wb_fixed	= 2443,
+    ARM_VLD1DUPd32wb_register	= 2444,
+    ARM_VLD1DUPd8	= 2445,
+    ARM_VLD1DUPd8wb_fixed	= 2446,
+    ARM_VLD1DUPd8wb_register	= 2447,
+    ARM_VLD1DUPq16	= 2448,
+    ARM_VLD1DUPq16wb_fixed	= 2449,
+    ARM_VLD1DUPq16wb_register	= 2450,
+    ARM_VLD1DUPq32	= 2451,
+    ARM_VLD1DUPq32wb_fixed	= 2452,
+    ARM_VLD1DUPq32wb_register	= 2453,
+    ARM_VLD1DUPq8	= 2454,
+    ARM_VLD1DUPq8wb_fixed	= 2455,
+    ARM_VLD1DUPq8wb_register	= 2456,
+    ARM_VLD1LNd16	= 2457,
+    ARM_VLD1LNd16_UPD	= 2458,
+    ARM_VLD1LNd32	= 2459,
+    ARM_VLD1LNd32_UPD	= 2460,
+    ARM_VLD1LNd8	= 2461,
+    ARM_VLD1LNd8_UPD	= 2462,
+    ARM_VLD1LNq16Pseudo	= 2463,
+    ARM_VLD1LNq16Pseudo_UPD	= 2464,
+    ARM_VLD1LNq32Pseudo	= 2465,
+    ARM_VLD1LNq32Pseudo_UPD	= 2466,
+    ARM_VLD1LNq8Pseudo	= 2467,
+    ARM_VLD1LNq8Pseudo_UPD	= 2468,
+    ARM_VLD1d16	= 2469,
+    ARM_VLD1d16Q	= 2470,
+    ARM_VLD1d16QPseudo	= 2471,
+    ARM_VLD1d16QPseudoWB_fixed	= 2472,
+    ARM_VLD1d16QPseudoWB_register	= 2473,
+    ARM_VLD1d16Qwb_fixed	= 2474,
+    ARM_VLD1d16Qwb_register	= 2475,
+    ARM_VLD1d16T	= 2476,
+    ARM_VLD1d16TPseudo	= 2477,
+    ARM_VLD1d16TPseudoWB_fixed	= 2478,
+    ARM_VLD1d16TPseudoWB_register	= 2479,
+    ARM_VLD1d16Twb_fixed	= 2480,
+    ARM_VLD1d16Twb_register	= 2481,
+    ARM_VLD1d16wb_fixed	= 2482,
+    ARM_VLD1d16wb_register	= 2483,
+    ARM_VLD1d32	= 2484,
+    ARM_VLD1d32Q	= 2485,
+    ARM_VLD1d32QPseudo	= 2486,
+    ARM_VLD1d32QPseudoWB_fixed	= 2487,
+    ARM_VLD1d32QPseudoWB_register	= 2488,
+    ARM_VLD1d32Qwb_fixed	= 2489,
+    ARM_VLD1d32Qwb_register	= 2490,
+    ARM_VLD1d32T	= 2491,
+    ARM_VLD1d32TPseudo	= 2492,
+    ARM_VLD1d32TPseudoWB_fixed	= 2493,
+    ARM_VLD1d32TPseudoWB_register	= 2494,
+    ARM_VLD1d32Twb_fixed	= 2495,
+    ARM_VLD1d32Twb_register	= 2496,
+    ARM_VLD1d32wb_fixed	= 2497,
+    ARM_VLD1d32wb_register	= 2498,
+    ARM_VLD1d64	= 2499,
+    ARM_VLD1d64Q	= 2500,
+    ARM_VLD1d64QPseudo	= 2501,
+    ARM_VLD1d64QPseudoWB_fixed	= 2502,
+    ARM_VLD1d64QPseudoWB_register	= 2503,
+    ARM_VLD1d64Qwb_fixed	= 2504,
+    ARM_VLD1d64Qwb_register	= 2505,
+    ARM_VLD1d64T	= 2506,
+    ARM_VLD1d64TPseudo	= 2507,
+    ARM_VLD1d64TPseudoWB_fixed	= 2508,
+    ARM_VLD1d64TPseudoWB_register	= 2509,
+    ARM_VLD1d64Twb_fixed	= 2510,
+    ARM_VLD1d64Twb_register	= 2511,
+    ARM_VLD1d64wb_fixed	= 2512,
+    ARM_VLD1d64wb_register	= 2513,
+    ARM_VLD1d8	= 2514,
+    ARM_VLD1d8Q	= 2515,
+    ARM_VLD1d8QPseudo	= 2516,
+    ARM_VLD1d8QPseudoWB_fixed	= 2517,
+    ARM_VLD1d8QPseudoWB_register	= 2518,
+    ARM_VLD1d8Qwb_fixed	= 2519,
+    ARM_VLD1d8Qwb_register	= 2520,
+    ARM_VLD1d8T	= 2521,
+    ARM_VLD1d8TPseudo	= 2522,
+    ARM_VLD1d8TPseudoWB_fixed	= 2523,
+    ARM_VLD1d8TPseudoWB_register	= 2524,
+    ARM_VLD1d8Twb_fixed	= 2525,
+    ARM_VLD1d8Twb_register	= 2526,
+    ARM_VLD1d8wb_fixed	= 2527,
+    ARM_VLD1d8wb_register	= 2528,
+    ARM_VLD1q16	= 2529,
+    ARM_VLD1q16HighQPseudo	= 2530,
+    ARM_VLD1q16HighQPseudo_UPD	= 2531,
+    ARM_VLD1q16HighTPseudo	= 2532,
+    ARM_VLD1q16HighTPseudo_UPD	= 2533,
+    ARM_VLD1q16LowQPseudo_UPD	= 2534,
+    ARM_VLD1q16LowTPseudo_UPD	= 2535,
+    ARM_VLD1q16wb_fixed	= 2536,
+    ARM_VLD1q16wb_register	= 2537,
+    ARM_VLD1q32	= 2538,
+    ARM_VLD1q32HighQPseudo	= 2539,
+    ARM_VLD1q32HighQPseudo_UPD	= 2540,
+    ARM_VLD1q32HighTPseudo	= 2541,
+    ARM_VLD1q32HighTPseudo_UPD	= 2542,
+    ARM_VLD1q32LowQPseudo_UPD	= 2543,
+    ARM_VLD1q32LowTPseudo_UPD	= 2544,
+    ARM_VLD1q32wb_fixed	= 2545,
+    ARM_VLD1q32wb_register	= 2546,
+    ARM_VLD1q64	= 2547,
+    ARM_VLD1q64HighQPseudo	= 2548,
+    ARM_VLD1q64HighQPseudo_UPD	= 2549,
+    ARM_VLD1q64HighTPseudo	= 2550,
+    ARM_VLD1q64HighTPseudo_UPD	= 2551,
+    ARM_VLD1q64LowQPseudo_UPD	= 2552,
+    ARM_VLD1q64LowTPseudo_UPD	= 2553,
+    ARM_VLD1q64wb_fixed	= 2554,
+    ARM_VLD1q64wb_register	= 2555,
+    ARM_VLD1q8	= 2556,
+    ARM_VLD1q8HighQPseudo	= 2557,
+    ARM_VLD1q8HighQPseudo_UPD	= 2558,
+    ARM_VLD1q8HighTPseudo	= 2559,
+    ARM_VLD1q8HighTPseudo_UPD	= 2560,
+    ARM_VLD1q8LowQPseudo_UPD	= 2561,
+    ARM_VLD1q8LowTPseudo_UPD	= 2562,
+    ARM_VLD1q8wb_fixed	= 2563,
+    ARM_VLD1q8wb_register	= 2564,
+    ARM_VLD2DUPd16	= 2565,
+    ARM_VLD2DUPd16wb_fixed	= 2566,
+    ARM_VLD2DUPd16wb_register	= 2567,
+    ARM_VLD2DUPd16x2	= 2568,
+    ARM_VLD2DUPd16x2wb_fixed	= 2569,
+    ARM_VLD2DUPd16x2wb_register	= 2570,
+    ARM_VLD2DUPd32	= 2571,
+    ARM_VLD2DUPd32wb_fixed	= 2572,
+    ARM_VLD2DUPd32wb_register	= 2573,
+    ARM_VLD2DUPd32x2	= 2574,
+    ARM_VLD2DUPd32x2wb_fixed	= 2575,
+    ARM_VLD2DUPd32x2wb_register	= 2576,
+    ARM_VLD2DUPd8	= 2577,
+    ARM_VLD2DUPd8wb_fixed	= 2578,
+    ARM_VLD2DUPd8wb_register	= 2579,
+    ARM_VLD2DUPd8x2	= 2580,
+    ARM_VLD2DUPd8x2wb_fixed	= 2581,
+    ARM_VLD2DUPd8x2wb_register	= 2582,
+    ARM_VLD2DUPq16EvenPseudo	= 2583,
+    ARM_VLD2DUPq16OddPseudo	= 2584,
+    ARM_VLD2DUPq16OddPseudoWB_fixed	= 2585,
+    ARM_VLD2DUPq16OddPseudoWB_register	= 2586,
+    ARM_VLD2DUPq32EvenPseudo	= 2587,
+    ARM_VLD2DUPq32OddPseudo	= 2588,
+    ARM_VLD2DUPq32OddPseudoWB_fixed	= 2589,
+    ARM_VLD2DUPq32OddPseudoWB_register	= 2590,
+    ARM_VLD2DUPq8EvenPseudo	= 2591,
+    ARM_VLD2DUPq8OddPseudo	= 2592,
+    ARM_VLD2DUPq8OddPseudoWB_fixed	= 2593,
+    ARM_VLD2DUPq8OddPseudoWB_register	= 2594,
+    ARM_VLD2LNd16	= 2595,
+    ARM_VLD2LNd16Pseudo	= 2596,
+    ARM_VLD2LNd16Pseudo_UPD	= 2597,
+    ARM_VLD2LNd16_UPD	= 2598,
+    ARM_VLD2LNd32	= 2599,
+    ARM_VLD2LNd32Pseudo	= 2600,
+    ARM_VLD2LNd32Pseudo_UPD	= 2601,
+    ARM_VLD2LNd32_UPD	= 2602,
+    ARM_VLD2LNd8	= 2603,
+    ARM_VLD2LNd8Pseudo	= 2604,
+    ARM_VLD2LNd8Pseudo_UPD	= 2605,
+    ARM_VLD2LNd8_UPD	= 2606,
+    ARM_VLD2LNq16	= 2607,
+    ARM_VLD2LNq16Pseudo	= 2608,
+    ARM_VLD2LNq16Pseudo_UPD	= 2609,
+    ARM_VLD2LNq16_UPD	= 2610,
+    ARM_VLD2LNq32	= 2611,
+    ARM_VLD2LNq32Pseudo	= 2612,
+    ARM_VLD2LNq32Pseudo_UPD	= 2613,
+    ARM_VLD2LNq32_UPD	= 2614,
+    ARM_VLD2b16	= 2615,
+    ARM_VLD2b16wb_fixed	= 2616,
+    ARM_VLD2b16wb_register	= 2617,
+    ARM_VLD2b32	= 2618,
+    ARM_VLD2b32wb_fixed	= 2619,
+    ARM_VLD2b32wb_register	= 2620,
+    ARM_VLD2b8	= 2621,
+    ARM_VLD2b8wb_fixed	= 2622,
+    ARM_VLD2b8wb_register	= 2623,
+    ARM_VLD2d16	= 2624,
+    ARM_VLD2d16wb_fixed	= 2625,
+    ARM_VLD2d16wb_register	= 2626,
+    ARM_VLD2d32	= 2627,
+    ARM_VLD2d32wb_fixed	= 2628,
+    ARM_VLD2d32wb_register	= 2629,
+    ARM_VLD2d8	= 2630,
+    ARM_VLD2d8wb_fixed	= 2631,
+    ARM_VLD2d8wb_register	= 2632,
+    ARM_VLD2q16	= 2633,
+    ARM_VLD2q16Pseudo	= 2634,
+    ARM_VLD2q16PseudoWB_fixed	= 2635,
+    ARM_VLD2q16PseudoWB_register	= 2636,
+    ARM_VLD2q16wb_fixed	= 2637,
+    ARM_VLD2q16wb_register	= 2638,
+    ARM_VLD2q32	= 2639,
+    ARM_VLD2q32Pseudo	= 2640,
+    ARM_VLD2q32PseudoWB_fixed	= 2641,
+    ARM_VLD2q32PseudoWB_register	= 2642,
+    ARM_VLD2q32wb_fixed	= 2643,
+    ARM_VLD2q32wb_register	= 2644,
+    ARM_VLD2q8	= 2645,
+    ARM_VLD2q8Pseudo	= 2646,
+    ARM_VLD2q8PseudoWB_fixed	= 2647,
+    ARM_VLD2q8PseudoWB_register	= 2648,
+    ARM_VLD2q8wb_fixed	= 2649,
+    ARM_VLD2q8wb_register	= 2650,
+    ARM_VLD3DUPd16	= 2651,
+    ARM_VLD3DUPd16Pseudo	= 2652,
+    ARM_VLD3DUPd16Pseudo_UPD	= 2653,
+    ARM_VLD3DUPd16_UPD	= 2654,
+    ARM_VLD3DUPd32	= 2655,
+    ARM_VLD3DUPd32Pseudo	= 2656,
+    ARM_VLD3DUPd32Pseudo_UPD	= 2657,
+    ARM_VLD3DUPd32_UPD	= 2658,
+    ARM_VLD3DUPd8	= 2659,
+    ARM_VLD3DUPd8Pseudo	= 2660,
+    ARM_VLD3DUPd8Pseudo_UPD	= 2661,
+    ARM_VLD3DUPd8_UPD	= 2662,
+    ARM_VLD3DUPq16	= 2663,
+    ARM_VLD3DUPq16EvenPseudo	= 2664,
+    ARM_VLD3DUPq16OddPseudo	= 2665,
+    ARM_VLD3DUPq16OddPseudo_UPD	= 2666,
+    ARM_VLD3DUPq16_UPD	= 2667,
+    ARM_VLD3DUPq32	= 2668,
+    ARM_VLD3DUPq32EvenPseudo	= 2669,
+    ARM_VLD3DUPq32OddPseudo	= 2670,
+    ARM_VLD3DUPq32OddPseudo_UPD	= 2671,
+    ARM_VLD3DUPq32_UPD	= 2672,
+    ARM_VLD3DUPq8	= 2673,
+    ARM_VLD3DUPq8EvenPseudo	= 2674,
+    ARM_VLD3DUPq8OddPseudo	= 2675,
+    ARM_VLD3DUPq8OddPseudo_UPD	= 2676,
+    ARM_VLD3DUPq8_UPD	= 2677,
+    ARM_VLD3LNd16	= 2678,
+    ARM_VLD3LNd16Pseudo	= 2679,
+    ARM_VLD3LNd16Pseudo_UPD	= 2680,
+    ARM_VLD3LNd16_UPD	= 2681,
+    ARM_VLD3LNd32	= 2682,
+    ARM_VLD3LNd32Pseudo	= 2683,
+    ARM_VLD3LNd32Pseudo_UPD	= 2684,
+    ARM_VLD3LNd32_UPD	= 2685,
+    ARM_VLD3LNd8	= 2686,
+    ARM_VLD3LNd8Pseudo	= 2687,
+    ARM_VLD3LNd8Pseudo_UPD	= 2688,
+    ARM_VLD3LNd8_UPD	= 2689,
+    ARM_VLD3LNq16	= 2690,
+    ARM_VLD3LNq16Pseudo	= 2691,
+    ARM_VLD3LNq16Pseudo_UPD	= 2692,
+    ARM_VLD3LNq16_UPD	= 2693,
+    ARM_VLD3LNq32	= 2694,
+    ARM_VLD3LNq32Pseudo	= 2695,
+    ARM_VLD3LNq32Pseudo_UPD	= 2696,
+    ARM_VLD3LNq32_UPD	= 2697,
+    ARM_VLD3d16	= 2698,
+    ARM_VLD3d16Pseudo	= 2699,
+    ARM_VLD3d16Pseudo_UPD	= 2700,
+    ARM_VLD3d16_UPD	= 2701,
+    ARM_VLD3d32	= 2702,
+    ARM_VLD3d32Pseudo	= 2703,
+    ARM_VLD3d32Pseudo_UPD	= 2704,
+    ARM_VLD3d32_UPD	= 2705,
+    ARM_VLD3d8	= 2706,
+    ARM_VLD3d8Pseudo	= 2707,
+    ARM_VLD3d8Pseudo_UPD	= 2708,
+    ARM_VLD3d8_UPD	= 2709,
+    ARM_VLD3q16	= 2710,
+    ARM_VLD3q16Pseudo_UPD	= 2711,
+    ARM_VLD3q16_UPD	= 2712,
+    ARM_VLD3q16oddPseudo	= 2713,
+    ARM_VLD3q16oddPseudo_UPD	= 2714,
+    ARM_VLD3q32	= 2715,
+    ARM_VLD3q32Pseudo_UPD	= 2716,
+    ARM_VLD3q32_UPD	= 2717,
+    ARM_VLD3q32oddPseudo	= 2718,
+    ARM_VLD3q32oddPseudo_UPD	= 2719,
+    ARM_VLD3q8	= 2720,
+    ARM_VLD3q8Pseudo_UPD	= 2721,
+    ARM_VLD3q8_UPD	= 2722,
+    ARM_VLD3q8oddPseudo	= 2723,
+    ARM_VLD3q8oddPseudo_UPD	= 2724,
+    ARM_VLD4DUPd16	= 2725,
+    ARM_VLD4DUPd16Pseudo	= 2726,
+    ARM_VLD4DUPd16Pseudo_UPD	= 2727,
+    ARM_VLD4DUPd16_UPD	= 2728,
+    ARM_VLD4DUPd32	= 2729,
+    ARM_VLD4DUPd32Pseudo	= 2730,
+    ARM_VLD4DUPd32Pseudo_UPD	= 2731,
+    ARM_VLD4DUPd32_UPD	= 2732,
+    ARM_VLD4DUPd8	= 2733,
+    ARM_VLD4DUPd8Pseudo	= 2734,
+    ARM_VLD4DUPd8Pseudo_UPD	= 2735,
+    ARM_VLD4DUPd8_UPD	= 2736,
+    ARM_VLD4DUPq16	= 2737,
+    ARM_VLD4DUPq16EvenPseudo	= 2738,
+    ARM_VLD4DUPq16OddPseudo	= 2739,
+    ARM_VLD4DUPq16OddPseudo_UPD	= 2740,
+    ARM_VLD4DUPq16_UPD	= 2741,
+    ARM_VLD4DUPq32	= 2742,
+    ARM_VLD4DUPq32EvenPseudo	= 2743,
+    ARM_VLD4DUPq32OddPseudo	= 2744,
+    ARM_VLD4DUPq32OddPseudo_UPD	= 2745,
+    ARM_VLD4DUPq32_UPD	= 2746,
+    ARM_VLD4DUPq8	= 2747,
+    ARM_VLD4DUPq8EvenPseudo	= 2748,
+    ARM_VLD4DUPq8OddPseudo	= 2749,
+    ARM_VLD4DUPq8OddPseudo_UPD	= 2750,
+    ARM_VLD4DUPq8_UPD	= 2751,
+    ARM_VLD4LNd16	= 2752,
+    ARM_VLD4LNd16Pseudo	= 2753,
+    ARM_VLD4LNd16Pseudo_UPD	= 2754,
+    ARM_VLD4LNd16_UPD	= 2755,
+    ARM_VLD4LNd32	= 2756,
+    ARM_VLD4LNd32Pseudo	= 2757,
+    ARM_VLD4LNd32Pseudo_UPD	= 2758,
+    ARM_VLD4LNd32_UPD	= 2759,
+    ARM_VLD4LNd8	= 2760,
+    ARM_VLD4LNd8Pseudo	= 2761,
+    ARM_VLD4LNd8Pseudo_UPD	= 2762,
+    ARM_VLD4LNd8_UPD	= 2763,
+    ARM_VLD4LNq16	= 2764,
+    ARM_VLD4LNq16Pseudo	= 2765,
+    ARM_VLD4LNq16Pseudo_UPD	= 2766,
+    ARM_VLD4LNq16_UPD	= 2767,
+    ARM_VLD4LNq32	= 2768,
+    ARM_VLD4LNq32Pseudo	= 2769,
+    ARM_VLD4LNq32Pseudo_UPD	= 2770,
+    ARM_VLD4LNq32_UPD	= 2771,
+    ARM_VLD4d16	= 2772,
+    ARM_VLD4d16Pseudo	= 2773,
+    ARM_VLD4d16Pseudo_UPD	= 2774,
+    ARM_VLD4d16_UPD	= 2775,
+    ARM_VLD4d32	= 2776,
+    ARM_VLD4d32Pseudo	= 2777,
+    ARM_VLD4d32Pseudo_UPD	= 2778,
+    ARM_VLD4d32_UPD	= 2779,
+    ARM_VLD4d8	= 2780,
+    ARM_VLD4d8Pseudo	= 2781,
+    ARM_VLD4d8Pseudo_UPD	= 2782,
+    ARM_VLD4d8_UPD	= 2783,
+    ARM_VLD4q16	= 2784,
+    ARM_VLD4q16Pseudo_UPD	= 2785,
+    ARM_VLD4q16_UPD	= 2786,
+    ARM_VLD4q16oddPseudo	= 2787,
+    ARM_VLD4q16oddPseudo_UPD	= 2788,
+    ARM_VLD4q32	= 2789,
+    ARM_VLD4q32Pseudo_UPD	= 2790,
+    ARM_VLD4q32_UPD	= 2791,
+    ARM_VLD4q32oddPseudo	= 2792,
+    ARM_VLD4q32oddPseudo_UPD	= 2793,
+    ARM_VLD4q8	= 2794,
+    ARM_VLD4q8Pseudo_UPD	= 2795,
+    ARM_VLD4q8_UPD	= 2796,
+    ARM_VLD4q8oddPseudo	= 2797,
+    ARM_VLD4q8oddPseudo_UPD	= 2798,
+    ARM_VLDMDDB_UPD	= 2799,
+    ARM_VLDMDIA	= 2800,
+    ARM_VLDMDIA_UPD	= 2801,
+    ARM_VLDMQIA	= 2802,
+    ARM_VLDMSDB_UPD	= 2803,
+    ARM_VLDMSIA	= 2804,
+    ARM_VLDMSIA_UPD	= 2805,
+    ARM_VLDRD	= 2806,
+    ARM_VLDRH	= 2807,
+    ARM_VLDRS	= 2808,
+    ARM_VLDR_FPCXTNS_off	= 2809,
+    ARM_VLDR_FPCXTNS_post	= 2810,
+    ARM_VLDR_FPCXTNS_pre	= 2811,
+    ARM_VLDR_FPCXTS_off	= 2812,
+    ARM_VLDR_FPCXTS_post	= 2813,
+    ARM_VLDR_FPCXTS_pre	= 2814,
+    ARM_VLDR_FPSCR_NZCVQC_off	= 2815,
+    ARM_VLDR_FPSCR_NZCVQC_post	= 2816,
+    ARM_VLDR_FPSCR_NZCVQC_pre	= 2817,
+    ARM_VLDR_FPSCR_off	= 2818,
+    ARM_VLDR_FPSCR_post	= 2819,
+    ARM_VLDR_FPSCR_pre	= 2820,
+    ARM_VLDR_P0_off	= 2821,
+    ARM_VLDR_P0_post	= 2822,
+    ARM_VLDR_P0_pre	= 2823,
+    ARM_VLDR_VPR_off	= 2824,
+    ARM_VLDR_VPR_post	= 2825,
+    ARM_VLDR_VPR_pre	= 2826,
+    ARM_VLLDM	= 2827,
+    ARM_VLSTM	= 2828,
+    ARM_VMAXfd	= 2829,
+    ARM_VMAXfq	= 2830,
+    ARM_VMAXhd	= 2831,
+    ARM_VMAXhq	= 2832,
+    ARM_VMAXsv16i8	= 2833,
+    ARM_VMAXsv2i32	= 2834,
+    ARM_VMAXsv4i16	= 2835,
+    ARM_VMAXsv4i32	= 2836,
+    ARM_VMAXsv8i16	= 2837,
+    ARM_VMAXsv8i8	= 2838,
+    ARM_VMAXuv16i8	= 2839,
+    ARM_VMAXuv2i32	= 2840,
+    ARM_VMAXuv4i16	= 2841,
+    ARM_VMAXuv4i32	= 2842,
+    ARM_VMAXuv8i16	= 2843,
+    ARM_VMAXuv8i8	= 2844,
+    ARM_VMINfd	= 2845,
+    ARM_VMINfq	= 2846,
+    ARM_VMINhd	= 2847,
+    ARM_VMINhq	= 2848,
+    ARM_VMINsv16i8	= 2849,
+    ARM_VMINsv2i32	= 2850,
+    ARM_VMINsv4i16	= 2851,
+    ARM_VMINsv4i32	= 2852,
+    ARM_VMINsv8i16	= 2853,
+    ARM_VMINsv8i8	= 2854,
+    ARM_VMINuv16i8	= 2855,
+    ARM_VMINuv2i32	= 2856,
+    ARM_VMINuv4i16	= 2857,
+    ARM_VMINuv4i32	= 2858,
+    ARM_VMINuv8i16	= 2859,
+    ARM_VMINuv8i8	= 2860,
+    ARM_VMLAD	= 2861,
+    ARM_VMLAH	= 2862,
+    ARM_VMLALslsv2i32	= 2863,
+    ARM_VMLALslsv4i16	= 2864,
+    ARM_VMLALsluv2i32	= 2865,
+    ARM_VMLALsluv4i16	= 2866,
+    ARM_VMLALsv2i64	= 2867,
+    ARM_VMLALsv4i32	= 2868,
+    ARM_VMLALsv8i16	= 2869,
+    ARM_VMLALuv2i64	= 2870,
+    ARM_VMLALuv4i32	= 2871,
+    ARM_VMLALuv8i16	= 2872,
+    ARM_VMLAS	= 2873,
+    ARM_VMLAfd	= 2874,
+    ARM_VMLAfq	= 2875,
+    ARM_VMLAhd	= 2876,
+    ARM_VMLAhq	= 2877,
+    ARM_VMLAslfd	= 2878,
+    ARM_VMLAslfq	= 2879,
+    ARM_VMLAslhd	= 2880,
+    ARM_VMLAslhq	= 2881,
+    ARM_VMLAslv2i32	= 2882,
+    ARM_VMLAslv4i16	= 2883,
+    ARM_VMLAslv4i32	= 2884,
+    ARM_VMLAslv8i16	= 2885,
+    ARM_VMLAv16i8	= 2886,
+    ARM_VMLAv2i32	= 2887,
+    ARM_VMLAv4i16	= 2888,
+    ARM_VMLAv4i32	= 2889,
+    ARM_VMLAv8i16	= 2890,
+    ARM_VMLAv8i8	= 2891,
+    ARM_VMLSD	= 2892,
+    ARM_VMLSH	= 2893,
+    ARM_VMLSLslsv2i32	= 2894,
+    ARM_VMLSLslsv4i16	= 2895,
+    ARM_VMLSLsluv2i32	= 2896,
+    ARM_VMLSLsluv4i16	= 2897,
+    ARM_VMLSLsv2i64	= 2898,
+    ARM_VMLSLsv4i32	= 2899,
+    ARM_VMLSLsv8i16	= 2900,
+    ARM_VMLSLuv2i64	= 2901,
+    ARM_VMLSLuv4i32	= 2902,
+    ARM_VMLSLuv8i16	= 2903,
+    ARM_VMLSS	= 2904,
+    ARM_VMLSfd	= 2905,
+    ARM_VMLSfq	= 2906,
+    ARM_VMLShd	= 2907,
+    ARM_VMLShq	= 2908,
+    ARM_VMLSslfd	= 2909,
+    ARM_VMLSslfq	= 2910,
+    ARM_VMLSslhd	= 2911,
+    ARM_VMLSslhq	= 2912,
+    ARM_VMLSslv2i32	= 2913,
+    ARM_VMLSslv4i16	= 2914,
+    ARM_VMLSslv4i32	= 2915,
+    ARM_VMLSslv8i16	= 2916,
+    ARM_VMLSv16i8	= 2917,
+    ARM_VMLSv2i32	= 2918,
+    ARM_VMLSv4i16	= 2919,
+    ARM_VMLSv4i32	= 2920,
+    ARM_VMLSv8i16	= 2921,
+    ARM_VMLSv8i8	= 2922,
+    ARM_VMMLA	= 2923,
+    ARM_VMOVD	= 2924,
+    ARM_VMOVDRR	= 2925,
+    ARM_VMOVH	= 2926,
+    ARM_VMOVHR	= 2927,
+    ARM_VMOVLsv2i64	= 2928,
+    ARM_VMOVLsv4i32	= 2929,
+    ARM_VMOVLsv8i16	= 2930,
+    ARM_VMOVLuv2i64	= 2931,
+    ARM_VMOVLuv4i32	= 2932,
+    ARM_VMOVLuv8i16	= 2933,
+    ARM_VMOVNv2i32	= 2934,
+    ARM_VMOVNv4i16	= 2935,
+    ARM_VMOVNv8i8	= 2936,
+    ARM_VMOVRH	= 2937,
+    ARM_VMOVRRD	= 2938,
+    ARM_VMOVRRS	= 2939,
+    ARM_VMOVRS	= 2940,
+    ARM_VMOVS	= 2941,
+    ARM_VMOVSR	= 2942,
+    ARM_VMOVSRR	= 2943,
+    ARM_VMOVv16i8	= 2944,
+    ARM_VMOVv1i64	= 2945,
+    ARM_VMOVv2f32	= 2946,
+    ARM_VMOVv2i32	= 2947,
+    ARM_VMOVv2i64	= 2948,
+    ARM_VMOVv4f32	= 2949,
+    ARM_VMOVv4i16	= 2950,
+    ARM_VMOVv4i32	= 2951,
+    ARM_VMOVv8i16	= 2952,
+    ARM_VMOVv8i8	= 2953,
+    ARM_VMRS	= 2954,
+    ARM_VMRS_FPCXTNS	= 2955,
+    ARM_VMRS_FPCXTS	= 2956,
+    ARM_VMRS_FPEXC	= 2957,
+    ARM_VMRS_FPINST	= 2958,
+    ARM_VMRS_FPINST2	= 2959,
+    ARM_VMRS_FPSCR_NZCVQC	= 2960,
+    ARM_VMRS_FPSID	= 2961,
+    ARM_VMRS_MVFR0	= 2962,
+    ARM_VMRS_MVFR1	= 2963,
+    ARM_VMRS_MVFR2	= 2964,
+    ARM_VMRS_P0	= 2965,
+    ARM_VMRS_VPR	= 2966,
+    ARM_VMSR	= 2967,
+    ARM_VMSR_FPCXTNS	= 2968,
+    ARM_VMSR_FPCXTS	= 2969,
+    ARM_VMSR_FPEXC	= 2970,
+    ARM_VMSR_FPINST	= 2971,
+    ARM_VMSR_FPINST2	= 2972,
+    ARM_VMSR_FPSCR_NZCVQC	= 2973,
+    ARM_VMSR_FPSID	= 2974,
+    ARM_VMSR_P0	= 2975,
+    ARM_VMSR_VPR	= 2976,
+    ARM_VMULD	= 2977,
+    ARM_VMULH	= 2978,
+    ARM_VMULLp64	= 2979,
+    ARM_VMULLp8	= 2980,
+    ARM_VMULLslsv2i32	= 2981,
+    ARM_VMULLslsv4i16	= 2982,
+    ARM_VMULLsluv2i32	= 2983,
+    ARM_VMULLsluv4i16	= 2984,
+    ARM_VMULLsv2i64	= 2985,
+    ARM_VMULLsv4i32	= 2986,
+    ARM_VMULLsv8i16	= 2987,
+    ARM_VMULLuv2i64	= 2988,
+    ARM_VMULLuv4i32	= 2989,
+    ARM_VMULLuv8i16	= 2990,
+    ARM_VMULS	= 2991,
+    ARM_VMULfd	= 2992,
+    ARM_VMULfq	= 2993,
+    ARM_VMULhd	= 2994,
+    ARM_VMULhq	= 2995,
+    ARM_VMULpd	= 2996,
+    ARM_VMULpq	= 2997,
+    ARM_VMULslfd	= 2998,
+    ARM_VMULslfq	= 2999,
+    ARM_VMULslhd	= 3000,
+    ARM_VMULslhq	= 3001,
+    ARM_VMULslv2i32	= 3002,
+    ARM_VMULslv4i16	= 3003,
+    ARM_VMULslv4i32	= 3004,
+    ARM_VMULslv8i16	= 3005,
+    ARM_VMULv16i8	= 3006,
+    ARM_VMULv2i32	= 3007,
+    ARM_VMULv4i16	= 3008,
+    ARM_VMULv4i32	= 3009,
+    ARM_VMULv8i16	= 3010,
+    ARM_VMULv8i8	= 3011,
+    ARM_VMVNd	= 3012,
+    ARM_VMVNq	= 3013,
+    ARM_VMVNv2i32	= 3014,
+    ARM_VMVNv4i16	= 3015,
+    ARM_VMVNv4i32	= 3016,
+    ARM_VMVNv8i16	= 3017,
+    ARM_VNEGD	= 3018,
+    ARM_VNEGH	= 3019,
+    ARM_VNEGS	= 3020,
+    ARM_VNEGf32q	= 3021,
+    ARM_VNEGfd	= 3022,
+    ARM_VNEGhd	= 3023,
+    ARM_VNEGhq	= 3024,
+    ARM_VNEGs16d	= 3025,
+    ARM_VNEGs16q	= 3026,
+    ARM_VNEGs32d	= 3027,
+    ARM_VNEGs32q	= 3028,
+    ARM_VNEGs8d	= 3029,
+    ARM_VNEGs8q	= 3030,
+    ARM_VNMLAD	= 3031,
+    ARM_VNMLAH	= 3032,
+    ARM_VNMLAS	= 3033,
+    ARM_VNMLSD	= 3034,
+    ARM_VNMLSH	= 3035,
+    ARM_VNMLSS	= 3036,
+    ARM_VNMULD	= 3037,
+    ARM_VNMULH	= 3038,
+    ARM_VNMULS	= 3039,
+    ARM_VORNd	= 3040,
+    ARM_VORNq	= 3041,
+    ARM_VORRd	= 3042,
+    ARM_VORRiv2i32	= 3043,
+    ARM_VORRiv4i16	= 3044,
+    ARM_VORRiv4i32	= 3045,
+    ARM_VORRiv8i16	= 3046,
+    ARM_VORRq	= 3047,
+    ARM_VPADALsv16i8	= 3048,
+    ARM_VPADALsv2i32	= 3049,
+    ARM_VPADALsv4i16	= 3050,
+    ARM_VPADALsv4i32	= 3051,
+    ARM_VPADALsv8i16	= 3052,
+    ARM_VPADALsv8i8	= 3053,
+    ARM_VPADALuv16i8	= 3054,
+    ARM_VPADALuv2i32	= 3055,
+    ARM_VPADALuv4i16	= 3056,
+    ARM_VPADALuv4i32	= 3057,
+    ARM_VPADALuv8i16	= 3058,
+    ARM_VPADALuv8i8	= 3059,
+    ARM_VPADDLsv16i8	= 3060,
+    ARM_VPADDLsv2i32	= 3061,
+    ARM_VPADDLsv4i16	= 3062,
+    ARM_VPADDLsv4i32	= 3063,
+    ARM_VPADDLsv8i16	= 3064,
+    ARM_VPADDLsv8i8	= 3065,
+    ARM_VPADDLuv16i8	= 3066,
+    ARM_VPADDLuv2i32	= 3067,
+    ARM_VPADDLuv4i16	= 3068,
+    ARM_VPADDLuv4i32	= 3069,
+    ARM_VPADDLuv8i16	= 3070,
+    ARM_VPADDLuv8i8	= 3071,
+    ARM_VPADDf	= 3072,
+    ARM_VPADDh	= 3073,
+    ARM_VPADDi16	= 3074,
+    ARM_VPADDi32	= 3075,
+    ARM_VPADDi8	= 3076,
+    ARM_VPMAXf	= 3077,
+    ARM_VPMAXh	= 3078,
+    ARM_VPMAXs16	= 3079,
+    ARM_VPMAXs32	= 3080,
+    ARM_VPMAXs8	= 3081,
+    ARM_VPMAXu16	= 3082,
+    ARM_VPMAXu32	= 3083,
+    ARM_VPMAXu8	= 3084,
+    ARM_VPMINf	= 3085,
+    ARM_VPMINh	= 3086,
+    ARM_VPMINs16	= 3087,
+    ARM_VPMINs32	= 3088,
+    ARM_VPMINs8	= 3089,
+    ARM_VPMINu16	= 3090,
+    ARM_VPMINu32	= 3091,
+    ARM_VPMINu8	= 3092,
+    ARM_VQABSv16i8	= 3093,
+    ARM_VQABSv2i32	= 3094,
+    ARM_VQABSv4i16	= 3095,
+    ARM_VQABSv4i32	= 3096,
+    ARM_VQABSv8i16	= 3097,
+    ARM_VQABSv8i8	= 3098,
+    ARM_VQADDsv16i8	= 3099,
+    ARM_VQADDsv1i64	= 3100,
+    ARM_VQADDsv2i32	= 3101,
+    ARM_VQADDsv2i64	= 3102,
+    ARM_VQADDsv4i16	= 3103,
+    ARM_VQADDsv4i32	= 3104,
+    ARM_VQADDsv8i16	= 3105,
+    ARM_VQADDsv8i8	= 3106,
+    ARM_VQADDuv16i8	= 3107,
+    ARM_VQADDuv1i64	= 3108,
+    ARM_VQADDuv2i32	= 3109,
+    ARM_VQADDuv2i64	= 3110,
+    ARM_VQADDuv4i16	= 3111,
+    ARM_VQADDuv4i32	= 3112,
+    ARM_VQADDuv8i16	= 3113,
+    ARM_VQADDuv8i8	= 3114,
+    ARM_VQDMLALslv2i32	= 3115,
+    ARM_VQDMLALslv4i16	= 3116,
+    ARM_VQDMLALv2i64	= 3117,
+    ARM_VQDMLALv4i32	= 3118,
+    ARM_VQDMLSLslv2i32	= 3119,
+    ARM_VQDMLSLslv4i16	= 3120,
+    ARM_VQDMLSLv2i64	= 3121,
+    ARM_VQDMLSLv4i32	= 3122,
+    ARM_VQDMULHslv2i32	= 3123,
+    ARM_VQDMULHslv4i16	= 3124,
+    ARM_VQDMULHslv4i32	= 3125,
+    ARM_VQDMULHslv8i16	= 3126,
+    ARM_VQDMULHv2i32	= 3127,
+    ARM_VQDMULHv4i16	= 3128,
+    ARM_VQDMULHv4i32	= 3129,
+    ARM_VQDMULHv8i16	= 3130,
+    ARM_VQDMULLslv2i32	= 3131,
+    ARM_VQDMULLslv4i16	= 3132,
+    ARM_VQDMULLv2i64	= 3133,
+    ARM_VQDMULLv4i32	= 3134,
+    ARM_VQMOVNsuv2i32	= 3135,
+    ARM_VQMOVNsuv4i16	= 3136,
+    ARM_VQMOVNsuv8i8	= 3137,
+    ARM_VQMOVNsv2i32	= 3138,
+    ARM_VQMOVNsv4i16	= 3139,
+    ARM_VQMOVNsv8i8	= 3140,
+    ARM_VQMOVNuv2i32	= 3141,
+    ARM_VQMOVNuv4i16	= 3142,
+    ARM_VQMOVNuv8i8	= 3143,
+    ARM_VQNEGv16i8	= 3144,
+    ARM_VQNEGv2i32	= 3145,
+    ARM_VQNEGv4i16	= 3146,
+    ARM_VQNEGv4i32	= 3147,
+    ARM_VQNEGv8i16	= 3148,
+    ARM_VQNEGv8i8	= 3149,
+    ARM_VQRDMLAHslv2i32	= 3150,
+    ARM_VQRDMLAHslv4i16	= 3151,
+    ARM_VQRDMLAHslv4i32	= 3152,
+    ARM_VQRDMLAHslv8i16	= 3153,
+    ARM_VQRDMLAHv2i32	= 3154,
+    ARM_VQRDMLAHv4i16	= 3155,
+    ARM_VQRDMLAHv4i32	= 3156,
+    ARM_VQRDMLAHv8i16	= 3157,
+    ARM_VQRDMLSHslv2i32	= 3158,
+    ARM_VQRDMLSHslv4i16	= 3159,
+    ARM_VQRDMLSHslv4i32	= 3160,
+    ARM_VQRDMLSHslv8i16	= 3161,
+    ARM_VQRDMLSHv2i32	= 3162,
+    ARM_VQRDMLSHv4i16	= 3163,
+    ARM_VQRDMLSHv4i32	= 3164,
+    ARM_VQRDMLSHv8i16	= 3165,
+    ARM_VQRDMULHslv2i32	= 3166,
+    ARM_VQRDMULHslv4i16	= 3167,
+    ARM_VQRDMULHslv4i32	= 3168,
+    ARM_VQRDMULHslv8i16	= 3169,
+    ARM_VQRDMULHv2i32	= 3170,
+    ARM_VQRDMULHv4i16	= 3171,
+    ARM_VQRDMULHv4i32	= 3172,
+    ARM_VQRDMULHv8i16	= 3173,
+    ARM_VQRSHLsv16i8	= 3174,
+    ARM_VQRSHLsv1i64	= 3175,
+    ARM_VQRSHLsv2i32	= 3176,
+    ARM_VQRSHLsv2i64	= 3177,
+    ARM_VQRSHLsv4i16	= 3178,
+    ARM_VQRSHLsv4i32	= 3179,
+    ARM_VQRSHLsv8i16	= 3180,
+    ARM_VQRSHLsv8i8	= 3181,
+    ARM_VQRSHLuv16i8	= 3182,
+    ARM_VQRSHLuv1i64	= 3183,
+    ARM_VQRSHLuv2i32	= 3184,
+    ARM_VQRSHLuv2i64	= 3185,
+    ARM_VQRSHLuv4i16	= 3186,
+    ARM_VQRSHLuv4i32	= 3187,
+    ARM_VQRSHLuv8i16	= 3188,
+    ARM_VQRSHLuv8i8	= 3189,
+    ARM_VQRSHRNsv2i32	= 3190,
+    ARM_VQRSHRNsv4i16	= 3191,
+    ARM_VQRSHRNsv8i8	= 3192,
+    ARM_VQRSHRNuv2i32	= 3193,
+    ARM_VQRSHRNuv4i16	= 3194,
+    ARM_VQRSHRNuv8i8	= 3195,
+    ARM_VQRSHRUNv2i32	= 3196,
+    ARM_VQRSHRUNv4i16	= 3197,
+    ARM_VQRSHRUNv8i8	= 3198,
+    ARM_VQSHLsiv16i8	= 3199,
+    ARM_VQSHLsiv1i64	= 3200,
+    ARM_VQSHLsiv2i32	= 3201,
+    ARM_VQSHLsiv2i64	= 3202,
+    ARM_VQSHLsiv4i16	= 3203,
+    ARM_VQSHLsiv4i32	= 3204,
+    ARM_VQSHLsiv8i16	= 3205,
+    ARM_VQSHLsiv8i8	= 3206,
+    ARM_VQSHLsuv16i8	= 3207,
+    ARM_VQSHLsuv1i64	= 3208,
+    ARM_VQSHLsuv2i32	= 3209,
+    ARM_VQSHLsuv2i64	= 3210,
+    ARM_VQSHLsuv4i16	= 3211,
+    ARM_VQSHLsuv4i32	= 3212,
+    ARM_VQSHLsuv8i16	= 3213,
+    ARM_VQSHLsuv8i8	= 3214,
+    ARM_VQSHLsv16i8	= 3215,
+    ARM_VQSHLsv1i64	= 3216,
+    ARM_VQSHLsv2i32	= 3217,
+    ARM_VQSHLsv2i64	= 3218,
+    ARM_VQSHLsv4i16	= 3219,
+    ARM_VQSHLsv4i32	= 3220,
+    ARM_VQSHLsv8i16	= 3221,
+    ARM_VQSHLsv8i8	= 3222,
+    ARM_VQSHLuiv16i8	= 3223,
+    ARM_VQSHLuiv1i64	= 3224,
+    ARM_VQSHLuiv2i32	= 3225,
+    ARM_VQSHLuiv2i64	= 3226,
+    ARM_VQSHLuiv4i16	= 3227,
+    ARM_VQSHLuiv4i32	= 3228,
+    ARM_VQSHLuiv8i16	= 3229,
+    ARM_VQSHLuiv8i8	= 3230,
+    ARM_VQSHLuv16i8	= 3231,
+    ARM_VQSHLuv1i64	= 3232,
+    ARM_VQSHLuv2i32	= 3233,
+    ARM_VQSHLuv2i64	= 3234,
+    ARM_VQSHLuv4i16	= 3235,
+    ARM_VQSHLuv4i32	= 3236,
+    ARM_VQSHLuv8i16	= 3237,
+    ARM_VQSHLuv8i8	= 3238,
+    ARM_VQSHRNsv2i32	= 3239,
+    ARM_VQSHRNsv4i16	= 3240,
+    ARM_VQSHRNsv8i8	= 3241,
+    ARM_VQSHRNuv2i32	= 3242,
+    ARM_VQSHRNuv4i16	= 3243,
+    ARM_VQSHRNuv8i8	= 3244,
+    ARM_VQSHRUNv2i32	= 3245,
+    ARM_VQSHRUNv4i16	= 3246,
+    ARM_VQSHRUNv8i8	= 3247,
+    ARM_VQSUBsv16i8	= 3248,
+    ARM_VQSUBsv1i64	= 3249,
+    ARM_VQSUBsv2i32	= 3250,
+    ARM_VQSUBsv2i64	= 3251,
+    ARM_VQSUBsv4i16	= 3252,
+    ARM_VQSUBsv4i32	= 3253,
+    ARM_VQSUBsv8i16	= 3254,
+    ARM_VQSUBsv8i8	= 3255,
+    ARM_VQSUBuv16i8	= 3256,
+    ARM_VQSUBuv1i64	= 3257,
+    ARM_VQSUBuv2i32	= 3258,
+    ARM_VQSUBuv2i64	= 3259,
+    ARM_VQSUBuv4i16	= 3260,
+    ARM_VQSUBuv4i32	= 3261,
+    ARM_VQSUBuv8i16	= 3262,
+    ARM_VQSUBuv8i8	= 3263,
+    ARM_VRADDHNv2i32	= 3264,
+    ARM_VRADDHNv4i16	= 3265,
+    ARM_VRADDHNv8i8	= 3266,
+    ARM_VRECPEd	= 3267,
+    ARM_VRECPEfd	= 3268,
+    ARM_VRECPEfq	= 3269,
+    ARM_VRECPEhd	= 3270,
+    ARM_VRECPEhq	= 3271,
+    ARM_VRECPEq	= 3272,
+    ARM_VRECPSfd	= 3273,
+    ARM_VRECPSfq	= 3274,
+    ARM_VRECPShd	= 3275,
+    ARM_VRECPShq	= 3276,
+    ARM_VREV16d8	= 3277,
+    ARM_VREV16q8	= 3278,
+    ARM_VREV32d16	= 3279,
+    ARM_VREV32d8	= 3280,
+    ARM_VREV32q16	= 3281,
+    ARM_VREV32q8	= 3282,
+    ARM_VREV64d16	= 3283,
+    ARM_VREV64d32	= 3284,
+    ARM_VREV64d8	= 3285,
+    ARM_VREV64q16	= 3286,
+    ARM_VREV64q32	= 3287,
+    ARM_VREV64q8	= 3288,
+    ARM_VRHADDsv16i8	= 3289,
+    ARM_VRHADDsv2i32	= 3290,
+    ARM_VRHADDsv4i16	= 3291,
+    ARM_VRHADDsv4i32	= 3292,
+    ARM_VRHADDsv8i16	= 3293,
+    ARM_VRHADDsv8i8	= 3294,
+    ARM_VRHADDuv16i8	= 3295,
+    ARM_VRHADDuv2i32	= 3296,
+    ARM_VRHADDuv4i16	= 3297,
+    ARM_VRHADDuv4i32	= 3298,
+    ARM_VRHADDuv8i16	= 3299,
+    ARM_VRHADDuv8i8	= 3300,
+    ARM_VRINTAD	= 3301,
+    ARM_VRINTAH	= 3302,
+    ARM_VRINTANDf	= 3303,
+    ARM_VRINTANDh	= 3304,
+    ARM_VRINTANQf	= 3305,
+    ARM_VRINTANQh	= 3306,
+    ARM_VRINTAS	= 3307,
+    ARM_VRINTMD	= 3308,
+    ARM_VRINTMH	= 3309,
+    ARM_VRINTMNDf	= 3310,
+    ARM_VRINTMNDh	= 3311,
+    ARM_VRINTMNQf	= 3312,
+    ARM_VRINTMNQh	= 3313,
+    ARM_VRINTMS	= 3314,
+    ARM_VRINTND	= 3315,
+    ARM_VRINTNH	= 3316,
+    ARM_VRINTNNDf	= 3317,
+    ARM_VRINTNNDh	= 3318,
+    ARM_VRINTNNQf	= 3319,
+    ARM_VRINTNNQh	= 3320,
+    ARM_VRINTNS	= 3321,
+    ARM_VRINTPD	= 3322,
+    ARM_VRINTPH	= 3323,
+    ARM_VRINTPNDf	= 3324,
+    ARM_VRINTPNDh	= 3325,
+    ARM_VRINTPNQf	= 3326,
+    ARM_VRINTPNQh	= 3327,
+    ARM_VRINTPS	= 3328,
+    ARM_VRINTRD	= 3329,
+    ARM_VRINTRH	= 3330,
+    ARM_VRINTRS	= 3331,
+    ARM_VRINTXD	= 3332,
+    ARM_VRINTXH	= 3333,
+    ARM_VRINTXNDf	= 3334,
+    ARM_VRINTXNDh	= 3335,
+    ARM_VRINTXNQf	= 3336,
+    ARM_VRINTXNQh	= 3337,
+    ARM_VRINTXS	= 3338,
+    ARM_VRINTZD	= 3339,
+    ARM_VRINTZH	= 3340,
+    ARM_VRINTZNDf	= 3341,
+    ARM_VRINTZNDh	= 3342,
+    ARM_VRINTZNQf	= 3343,
+    ARM_VRINTZNQh	= 3344,
+    ARM_VRINTZS	= 3345,
+    ARM_VRSHLsv16i8	= 3346,
+    ARM_VRSHLsv1i64	= 3347,
+    ARM_VRSHLsv2i32	= 3348,
+    ARM_VRSHLsv2i64	= 3349,
+    ARM_VRSHLsv4i16	= 3350,
+    ARM_VRSHLsv4i32	= 3351,
+    ARM_VRSHLsv8i16	= 3352,
+    ARM_VRSHLsv8i8	= 3353,
+    ARM_VRSHLuv16i8	= 3354,
+    ARM_VRSHLuv1i64	= 3355,
+    ARM_VRSHLuv2i32	= 3356,
+    ARM_VRSHLuv2i64	= 3357,
+    ARM_VRSHLuv4i16	= 3358,
+    ARM_VRSHLuv4i32	= 3359,
+    ARM_VRSHLuv8i16	= 3360,
+    ARM_VRSHLuv8i8	= 3361,
+    ARM_VRSHRNv2i32	= 3362,
+    ARM_VRSHRNv4i16	= 3363,
+    ARM_VRSHRNv8i8	= 3364,
+    ARM_VRSHRsv16i8	= 3365,
+    ARM_VRSHRsv1i64	= 3366,
+    ARM_VRSHRsv2i32	= 3367,
+    ARM_VRSHRsv2i64	= 3368,
+    ARM_VRSHRsv4i16	= 3369,
+    ARM_VRSHRsv4i32	= 3370,
+    ARM_VRSHRsv8i16	= 3371,
+    ARM_VRSHRsv8i8	= 3372,
+    ARM_VRSHRuv16i8	= 3373,
+    ARM_VRSHRuv1i64	= 3374,
+    ARM_VRSHRuv2i32	= 3375,
+    ARM_VRSHRuv2i64	= 3376,
+    ARM_VRSHRuv4i16	= 3377,
+    ARM_VRSHRuv4i32	= 3378,
+    ARM_VRSHRuv8i16	= 3379,
+    ARM_VRSHRuv8i8	= 3380,
+    ARM_VRSQRTEd	= 3381,
+    ARM_VRSQRTEfd	= 3382,
+    ARM_VRSQRTEfq	= 3383,
+    ARM_VRSQRTEhd	= 3384,
+    ARM_VRSQRTEhq	= 3385,
+    ARM_VRSQRTEq	= 3386,
+    ARM_VRSQRTSfd	= 3387,
+    ARM_VRSQRTSfq	= 3388,
+    ARM_VRSQRTShd	= 3389,
+    ARM_VRSQRTShq	= 3390,
+    ARM_VRSRAsv16i8	= 3391,
+    ARM_VRSRAsv1i64	= 3392,
+    ARM_VRSRAsv2i32	= 3393,
+    ARM_VRSRAsv2i64	= 3394,
+    ARM_VRSRAsv4i16	= 3395,
+    ARM_VRSRAsv4i32	= 3396,
+    ARM_VRSRAsv8i16	= 3397,
+    ARM_VRSRAsv8i8	= 3398,
+    ARM_VRSRAuv16i8	= 3399,
+    ARM_VRSRAuv1i64	= 3400,
+    ARM_VRSRAuv2i32	= 3401,
+    ARM_VRSRAuv2i64	= 3402,
+    ARM_VRSRAuv4i16	= 3403,
+    ARM_VRSRAuv4i32	= 3404,
+    ARM_VRSRAuv8i16	= 3405,
+    ARM_VRSRAuv8i8	= 3406,
+    ARM_VRSUBHNv2i32	= 3407,
+    ARM_VRSUBHNv4i16	= 3408,
+    ARM_VRSUBHNv8i8	= 3409,
+    ARM_VSCCLRMD	= 3410,
+    ARM_VSCCLRMS	= 3411,
+    ARM_VSDOTD	= 3412,
+    ARM_VSDOTDI	= 3413,
+    ARM_VSDOTQ	= 3414,
+    ARM_VSDOTQI	= 3415,
+    ARM_VSELEQD	= 3416,
+    ARM_VSELEQH	= 3417,
+    ARM_VSELEQS	= 3418,
+    ARM_VSELGED	= 3419,
+    ARM_VSELGEH	= 3420,
+    ARM_VSELGES	= 3421,
+    ARM_VSELGTD	= 3422,
+    ARM_VSELGTH	= 3423,
+    ARM_VSELGTS	= 3424,
+    ARM_VSELVSD	= 3425,
+    ARM_VSELVSH	= 3426,
+    ARM_VSELVSS	= 3427,
+    ARM_VSETLNi16	= 3428,
+    ARM_VSETLNi32	= 3429,
+    ARM_VSETLNi8	= 3430,
+    ARM_VSHLLi16	= 3431,
+    ARM_VSHLLi32	= 3432,
+    ARM_VSHLLi8	= 3433,
+    ARM_VSHLLsv2i64	= 3434,
+    ARM_VSHLLsv4i32	= 3435,
+    ARM_VSHLLsv8i16	= 3436,
+    ARM_VSHLLuv2i64	= 3437,
+    ARM_VSHLLuv4i32	= 3438,
+    ARM_VSHLLuv8i16	= 3439,
+    ARM_VSHLiv16i8	= 3440,
+    ARM_VSHLiv1i64	= 3441,
+    ARM_VSHLiv2i32	= 3442,
+    ARM_VSHLiv2i64	= 3443,
+    ARM_VSHLiv4i16	= 3444,
+    ARM_VSHLiv4i32	= 3445,
+    ARM_VSHLiv8i16	= 3446,
+    ARM_VSHLiv8i8	= 3447,
+    ARM_VSHLsv16i8	= 3448,
+    ARM_VSHLsv1i64	= 3449,
+    ARM_VSHLsv2i32	= 3450,
+    ARM_VSHLsv2i64	= 3451,
+    ARM_VSHLsv4i16	= 3452,
+    ARM_VSHLsv4i32	= 3453,
+    ARM_VSHLsv8i16	= 3454,
+    ARM_VSHLsv8i8	= 3455,
+    ARM_VSHLuv16i8	= 3456,
+    ARM_VSHLuv1i64	= 3457,
+    ARM_VSHLuv2i32	= 3458,
+    ARM_VSHLuv2i64	= 3459,
+    ARM_VSHLuv4i16	= 3460,
+    ARM_VSHLuv4i32	= 3461,
+    ARM_VSHLuv8i16	= 3462,
+    ARM_VSHLuv8i8	= 3463,
+    ARM_VSHRNv2i32	= 3464,
+    ARM_VSHRNv4i16	= 3465,
+    ARM_VSHRNv8i8	= 3466,
+    ARM_VSHRsv16i8	= 3467,
+    ARM_VSHRsv1i64	= 3468,
+    ARM_VSHRsv2i32	= 3469,
+    ARM_VSHRsv2i64	= 3470,
+    ARM_VSHRsv4i16	= 3471,
+    ARM_VSHRsv4i32	= 3472,
+    ARM_VSHRsv8i16	= 3473,
+    ARM_VSHRsv8i8	= 3474,
+    ARM_VSHRuv16i8	= 3475,
+    ARM_VSHRuv1i64	= 3476,
+    ARM_VSHRuv2i32	= 3477,
+    ARM_VSHRuv2i64	= 3478,
+    ARM_VSHRuv4i16	= 3479,
+    ARM_VSHRuv4i32	= 3480,
+    ARM_VSHRuv8i16	= 3481,
+    ARM_VSHRuv8i8	= 3482,
+    ARM_VSHTOD	= 3483,
+    ARM_VSHTOH	= 3484,
+    ARM_VSHTOS	= 3485,
+    ARM_VSITOD	= 3486,
+    ARM_VSITOH	= 3487,
+    ARM_VSITOS	= 3488,
+    ARM_VSLIv16i8	= 3489,
+    ARM_VSLIv1i64	= 3490,
+    ARM_VSLIv2i32	= 3491,
+    ARM_VSLIv2i64	= 3492,
+    ARM_VSLIv4i16	= 3493,
+    ARM_VSLIv4i32	= 3494,
+    ARM_VSLIv8i16	= 3495,
+    ARM_VSLIv8i8	= 3496,
+    ARM_VSLTOD	= 3497,
+    ARM_VSLTOH	= 3498,
+    ARM_VSLTOS	= 3499,
+    ARM_VSMMLA	= 3500,
+    ARM_VSQRTD	= 3501,
+    ARM_VSQRTH	= 3502,
+    ARM_VSQRTS	= 3503,
+    ARM_VSRAsv16i8	= 3504,
+    ARM_VSRAsv1i64	= 3505,
+    ARM_VSRAsv2i32	= 3506,
+    ARM_VSRAsv2i64	= 3507,
+    ARM_VSRAsv4i16	= 3508,
+    ARM_VSRAsv4i32	= 3509,
+    ARM_VSRAsv8i16	= 3510,
+    ARM_VSRAsv8i8	= 3511,
+    ARM_VSRAuv16i8	= 3512,
+    ARM_VSRAuv1i64	= 3513,
+    ARM_VSRAuv2i32	= 3514,
+    ARM_VSRAuv2i64	= 3515,
+    ARM_VSRAuv4i16	= 3516,
+    ARM_VSRAuv4i32	= 3517,
+    ARM_VSRAuv8i16	= 3518,
+    ARM_VSRAuv8i8	= 3519,
+    ARM_VSRIv16i8	= 3520,
+    ARM_VSRIv1i64	= 3521,
+    ARM_VSRIv2i32	= 3522,
+    ARM_VSRIv2i64	= 3523,
+    ARM_VSRIv4i16	= 3524,
+    ARM_VSRIv4i32	= 3525,
+    ARM_VSRIv8i16	= 3526,
+    ARM_VSRIv8i8	= 3527,
+    ARM_VST1LNd16	= 3528,
+    ARM_VST1LNd16_UPD	= 3529,
+    ARM_VST1LNd32	= 3530,
+    ARM_VST1LNd32_UPD	= 3531,
+    ARM_VST1LNd8	= 3532,
+    ARM_VST1LNd8_UPD	= 3533,
+    ARM_VST1LNq16Pseudo	= 3534,
+    ARM_VST1LNq16Pseudo_UPD	= 3535,
+    ARM_VST1LNq32Pseudo	= 3536,
+    ARM_VST1LNq32Pseudo_UPD	= 3537,
+    ARM_VST1LNq8Pseudo	= 3538,
+    ARM_VST1LNq8Pseudo_UPD	= 3539,
+    ARM_VST1d16	= 3540,
+    ARM_VST1d16Q	= 3541,
+    ARM_VST1d16QPseudo	= 3542,
+    ARM_VST1d16QPseudoWB_fixed	= 3543,
+    ARM_VST1d16QPseudoWB_register	= 3544,
+    ARM_VST1d16Qwb_fixed	= 3545,
+    ARM_VST1d16Qwb_register	= 3546,
+    ARM_VST1d16T	= 3547,
+    ARM_VST1d16TPseudo	= 3548,
+    ARM_VST1d16TPseudoWB_fixed	= 3549,
+    ARM_VST1d16TPseudoWB_register	= 3550,
+    ARM_VST1d16Twb_fixed	= 3551,
+    ARM_VST1d16Twb_register	= 3552,
+    ARM_VST1d16wb_fixed	= 3553,
+    ARM_VST1d16wb_register	= 3554,
+    ARM_VST1d32	= 3555,
+    ARM_VST1d32Q	= 3556,
+    ARM_VST1d32QPseudo	= 3557,
+    ARM_VST1d32QPseudoWB_fixed	= 3558,
+    ARM_VST1d32QPseudoWB_register	= 3559,
+    ARM_VST1d32Qwb_fixed	= 3560,
+    ARM_VST1d32Qwb_register	= 3561,
+    ARM_VST1d32T	= 3562,
+    ARM_VST1d32TPseudo	= 3563,
+    ARM_VST1d32TPseudoWB_fixed	= 3564,
+    ARM_VST1d32TPseudoWB_register	= 3565,
+    ARM_VST1d32Twb_fixed	= 3566,
+    ARM_VST1d32Twb_register	= 3567,
+    ARM_VST1d32wb_fixed	= 3568,
+    ARM_VST1d32wb_register	= 3569,
+    ARM_VST1d64	= 3570,
+    ARM_VST1d64Q	= 3571,
+    ARM_VST1d64QPseudo	= 3572,
+    ARM_VST1d64QPseudoWB_fixed	= 3573,
+    ARM_VST1d64QPseudoWB_register	= 3574,
+    ARM_VST1d64Qwb_fixed	= 3575,
+    ARM_VST1d64Qwb_register	= 3576,
+    ARM_VST1d64T	= 3577,
+    ARM_VST1d64TPseudo	= 3578,
+    ARM_VST1d64TPseudoWB_fixed	= 3579,
+    ARM_VST1d64TPseudoWB_register	= 3580,
+    ARM_VST1d64Twb_fixed	= 3581,
+    ARM_VST1d64Twb_register	= 3582,
+    ARM_VST1d64wb_fixed	= 3583,
+    ARM_VST1d64wb_register	= 3584,
+    ARM_VST1d8	= 3585,
+    ARM_VST1d8Q	= 3586,
+    ARM_VST1d8QPseudo	= 3587,
+    ARM_VST1d8QPseudoWB_fixed	= 3588,
+    ARM_VST1d8QPseudoWB_register	= 3589,
+    ARM_VST1d8Qwb_fixed	= 3590,
+    ARM_VST1d8Qwb_register	= 3591,
+    ARM_VST1d8T	= 3592,
+    ARM_VST1d8TPseudo	= 3593,
+    ARM_VST1d8TPseudoWB_fixed	= 3594,
+    ARM_VST1d8TPseudoWB_register	= 3595,
+    ARM_VST1d8Twb_fixed	= 3596,
+    ARM_VST1d8Twb_register	= 3597,
+    ARM_VST1d8wb_fixed	= 3598,
+    ARM_VST1d8wb_register	= 3599,
+    ARM_VST1q16	= 3600,
+    ARM_VST1q16HighQPseudo	= 3601,
+    ARM_VST1q16HighQPseudo_UPD	= 3602,
+    ARM_VST1q16HighTPseudo	= 3603,
+    ARM_VST1q16HighTPseudo_UPD	= 3604,
+    ARM_VST1q16LowQPseudo_UPD	= 3605,
+    ARM_VST1q16LowTPseudo_UPD	= 3606,
+    ARM_VST1q16wb_fixed	= 3607,
+    ARM_VST1q16wb_register	= 3608,
+    ARM_VST1q32	= 3609,
+    ARM_VST1q32HighQPseudo	= 3610,
+    ARM_VST1q32HighQPseudo_UPD	= 3611,
+    ARM_VST1q32HighTPseudo	= 3612,
+    ARM_VST1q32HighTPseudo_UPD	= 3613,
+    ARM_VST1q32LowQPseudo_UPD	= 3614,
+    ARM_VST1q32LowTPseudo_UPD	= 3615,
+    ARM_VST1q32wb_fixed	= 3616,
+    ARM_VST1q32wb_register	= 3617,
+    ARM_VST1q64	= 3618,
+    ARM_VST1q64HighQPseudo	= 3619,
+    ARM_VST1q64HighQPseudo_UPD	= 3620,
+    ARM_VST1q64HighTPseudo	= 3621,
+    ARM_VST1q64HighTPseudo_UPD	= 3622,
+    ARM_VST1q64LowQPseudo_UPD	= 3623,
+    ARM_VST1q64LowTPseudo_UPD	= 3624,
+    ARM_VST1q64wb_fixed	= 3625,
+    ARM_VST1q64wb_register	= 3626,
+    ARM_VST1q8	= 3627,
+    ARM_VST1q8HighQPseudo	= 3628,
+    ARM_VST1q8HighQPseudo_UPD	= 3629,
+    ARM_VST1q8HighTPseudo	= 3630,
+    ARM_VST1q8HighTPseudo_UPD	= 3631,
+    ARM_VST1q8LowQPseudo_UPD	= 3632,
+    ARM_VST1q8LowTPseudo_UPD	= 3633,
+    ARM_VST1q8wb_fixed	= 3634,
+    ARM_VST1q8wb_register	= 3635,
+    ARM_VST2LNd16	= 3636,
+    ARM_VST2LNd16Pseudo	= 3637,
+    ARM_VST2LNd16Pseudo_UPD	= 3638,
+    ARM_VST2LNd16_UPD	= 3639,
+    ARM_VST2LNd32	= 3640,
+    ARM_VST2LNd32Pseudo	= 3641,
+    ARM_VST2LNd32Pseudo_UPD	= 3642,
+    ARM_VST2LNd32_UPD	= 3643,
+    ARM_VST2LNd8	= 3644,
+    ARM_VST2LNd8Pseudo	= 3645,
+    ARM_VST2LNd8Pseudo_UPD	= 3646,
+    ARM_VST2LNd8_UPD	= 3647,
+    ARM_VST2LNq16	= 3648,
+    ARM_VST2LNq16Pseudo	= 3649,
+    ARM_VST2LNq16Pseudo_UPD	= 3650,
+    ARM_VST2LNq16_UPD	= 3651,
+    ARM_VST2LNq32	= 3652,
+    ARM_VST2LNq32Pseudo	= 3653,
+    ARM_VST2LNq32Pseudo_UPD	= 3654,
+    ARM_VST2LNq32_UPD	= 3655,
+    ARM_VST2b16	= 3656,
+    ARM_VST2b16wb_fixed	= 3657,
+    ARM_VST2b16wb_register	= 3658,
+    ARM_VST2b32	= 3659,
+    ARM_VST2b32wb_fixed	= 3660,
+    ARM_VST2b32wb_register	= 3661,
+    ARM_VST2b8	= 3662,
+    ARM_VST2b8wb_fixed	= 3663,
+    ARM_VST2b8wb_register	= 3664,
+    ARM_VST2d16	= 3665,
+    ARM_VST2d16wb_fixed	= 3666,
+    ARM_VST2d16wb_register	= 3667,
+    ARM_VST2d32	= 3668,
+    ARM_VST2d32wb_fixed	= 3669,
+    ARM_VST2d32wb_register	= 3670,
+    ARM_VST2d8	= 3671,
+    ARM_VST2d8wb_fixed	= 3672,
+    ARM_VST2d8wb_register	= 3673,
+    ARM_VST2q16	= 3674,
+    ARM_VST2q16Pseudo	= 3675,
+    ARM_VST2q16PseudoWB_fixed	= 3676,
+    ARM_VST2q16PseudoWB_register	= 3677,
+    ARM_VST2q16wb_fixed	= 3678,
+    ARM_VST2q16wb_register	= 3679,
+    ARM_VST2q32	= 3680,
+    ARM_VST2q32Pseudo	= 3681,
+    ARM_VST2q32PseudoWB_fixed	= 3682,
+    ARM_VST2q32PseudoWB_register	= 3683,
+    ARM_VST2q32wb_fixed	= 3684,
+    ARM_VST2q32wb_register	= 3685,
+    ARM_VST2q8	= 3686,
+    ARM_VST2q8Pseudo	= 3687,
+    ARM_VST2q8PseudoWB_fixed	= 3688,
+    ARM_VST2q8PseudoWB_register	= 3689,
+    ARM_VST2q8wb_fixed	= 3690,
+    ARM_VST2q8wb_register	= 3691,
+    ARM_VST3LNd16	= 3692,
+    ARM_VST3LNd16Pseudo	= 3693,
+    ARM_VST3LNd16Pseudo_UPD	= 3694,
+    ARM_VST3LNd16_UPD	= 3695,
+    ARM_VST3LNd32	= 3696,
+    ARM_VST3LNd32Pseudo	= 3697,
+    ARM_VST3LNd32Pseudo_UPD	= 3698,
+    ARM_VST3LNd32_UPD	= 3699,
+    ARM_VST3LNd8	= 3700,
+    ARM_VST3LNd8Pseudo	= 3701,
+    ARM_VST3LNd8Pseudo_UPD	= 3702,
+    ARM_VST3LNd8_UPD	= 3703,
+    ARM_VST3LNq16	= 3704,
+    ARM_VST3LNq16Pseudo	= 3705,
+    ARM_VST3LNq16Pseudo_UPD	= 3706,
+    ARM_VST3LNq16_UPD	= 3707,
+    ARM_VST3LNq32	= 3708,
+    ARM_VST3LNq32Pseudo	= 3709,
+    ARM_VST3LNq32Pseudo_UPD	= 3710,
+    ARM_VST3LNq32_UPD	= 3711,
+    ARM_VST3d16	= 3712,
+    ARM_VST3d16Pseudo	= 3713,
+    ARM_VST3d16Pseudo_UPD	= 3714,
+    ARM_VST3d16_UPD	= 3715,
+    ARM_VST3d32	= 3716,
+    ARM_VST3d32Pseudo	= 3717,
+    ARM_VST3d32Pseudo_UPD	= 3718,
+    ARM_VST3d32_UPD	= 3719,
+    ARM_VST3d8	= 3720,
+    ARM_VST3d8Pseudo	= 3721,
+    ARM_VST3d8Pseudo_UPD	= 3722,
+    ARM_VST3d8_UPD	= 3723,
+    ARM_VST3q16	= 3724,
+    ARM_VST3q16Pseudo_UPD	= 3725,
+    ARM_VST3q16_UPD	= 3726,
+    ARM_VST3q16oddPseudo	= 3727,
+    ARM_VST3q16oddPseudo_UPD	= 3728,
+    ARM_VST3q32	= 3729,
+    ARM_VST3q32Pseudo_UPD	= 3730,
+    ARM_VST3q32_UPD	= 3731,
+    ARM_VST3q32oddPseudo	= 3732,
+    ARM_VST3q32oddPseudo_UPD	= 3733,
+    ARM_VST3q8	= 3734,
+    ARM_VST3q8Pseudo_UPD	= 3735,
+    ARM_VST3q8_UPD	= 3736,
+    ARM_VST3q8oddPseudo	= 3737,
+    ARM_VST3q8oddPseudo_UPD	= 3738,
+    ARM_VST4LNd16	= 3739,
+    ARM_VST4LNd16Pseudo	= 3740,
+    ARM_VST4LNd16Pseudo_UPD	= 3741,
+    ARM_VST4LNd16_UPD	= 3742,
+    ARM_VST4LNd32	= 3743,
+    ARM_VST4LNd32Pseudo	= 3744,
+    ARM_VST4LNd32Pseudo_UPD	= 3745,
+    ARM_VST4LNd32_UPD	= 3746,
+    ARM_VST4LNd8	= 3747,
+    ARM_VST4LNd8Pseudo	= 3748,
+    ARM_VST4LNd8Pseudo_UPD	= 3749,
+    ARM_VST4LNd8_UPD	= 3750,
+    ARM_VST4LNq16	= 3751,
+    ARM_VST4LNq16Pseudo	= 3752,
+    ARM_VST4LNq16Pseudo_UPD	= 3753,
+    ARM_VST4LNq16_UPD	= 3754,
+    ARM_VST4LNq32	= 3755,
+    ARM_VST4LNq32Pseudo	= 3756,
+    ARM_VST4LNq32Pseudo_UPD	= 3757,
+    ARM_VST4LNq32_UPD	= 3758,
+    ARM_VST4d16	= 3759,
+    ARM_VST4d16Pseudo	= 3760,
+    ARM_VST4d16Pseudo_UPD	= 3761,
+    ARM_VST4d16_UPD	= 3762,
+    ARM_VST4d32	= 3763,
+    ARM_VST4d32Pseudo	= 3764,
+    ARM_VST4d32Pseudo_UPD	= 3765,
+    ARM_VST4d32_UPD	= 3766,
+    ARM_VST4d8	= 3767,
+    ARM_VST4d8Pseudo	= 3768,
+    ARM_VST4d8Pseudo_UPD	= 3769,
+    ARM_VST4d8_UPD	= 3770,
+    ARM_VST4q16	= 3771,
+    ARM_VST4q16Pseudo_UPD	= 3772,
+    ARM_VST4q16_UPD	= 3773,
+    ARM_VST4q16oddPseudo	= 3774,
+    ARM_VST4q16oddPseudo_UPD	= 3775,
+    ARM_VST4q32	= 3776,
+    ARM_VST4q32Pseudo_UPD	= 3777,
+    ARM_VST4q32_UPD	= 3778,
+    ARM_VST4q32oddPseudo	= 3779,
+    ARM_VST4q32oddPseudo_UPD	= 3780,
+    ARM_VST4q8	= 3781,
+    ARM_VST4q8Pseudo_UPD	= 3782,
+    ARM_VST4q8_UPD	= 3783,
+    ARM_VST4q8oddPseudo	= 3784,
+    ARM_VST4q8oddPseudo_UPD	= 3785,
+    ARM_VSTMDDB_UPD	= 3786,
+    ARM_VSTMDIA	= 3787,
+    ARM_VSTMDIA_UPD	= 3788,
+    ARM_VSTMQIA	= 3789,
+    ARM_VSTMSDB_UPD	= 3790,
+    ARM_VSTMSIA	= 3791,
+    ARM_VSTMSIA_UPD	= 3792,
+    ARM_VSTRD	= 3793,
+    ARM_VSTRH	= 3794,
+    ARM_VSTRS	= 3795,
+    ARM_VSTR_FPCXTNS_off	= 3796,
+    ARM_VSTR_FPCXTNS_post	= 3797,
+    ARM_VSTR_FPCXTNS_pre	= 3798,
+    ARM_VSTR_FPCXTS_off	= 3799,
+    ARM_VSTR_FPCXTS_post	= 3800,
+    ARM_VSTR_FPCXTS_pre	= 3801,
+    ARM_VSTR_FPSCR_NZCVQC_off	= 3802,
+    ARM_VSTR_FPSCR_NZCVQC_post	= 3803,
+    ARM_VSTR_FPSCR_NZCVQC_pre	= 3804,
+    ARM_VSTR_FPSCR_off	= 3805,
+    ARM_VSTR_FPSCR_post	= 3806,
+    ARM_VSTR_FPSCR_pre	= 3807,
+    ARM_VSTR_P0_off	= 3808,
+    ARM_VSTR_P0_post	= 3809,
+    ARM_VSTR_P0_pre	= 3810,
+    ARM_VSTR_VPR_off	= 3811,
+    ARM_VSTR_VPR_post	= 3812,
+    ARM_VSTR_VPR_pre	= 3813,
+    ARM_VSUBD	= 3814,
+    ARM_VSUBH	= 3815,
+    ARM_VSUBHNv2i32	= 3816,
+    ARM_VSUBHNv4i16	= 3817,
+    ARM_VSUBHNv8i8	= 3818,
+    ARM_VSUBLsv2i64	= 3819,
+    ARM_VSUBLsv4i32	= 3820,
+    ARM_VSUBLsv8i16	= 3821,
+    ARM_VSUBLuv2i64	= 3822,
+    ARM_VSUBLuv4i32	= 3823,
+    ARM_VSUBLuv8i16	= 3824,
+    ARM_VSUBS	= 3825,
+    ARM_VSUBWsv2i64	= 3826,
+    ARM_VSUBWsv4i32	= 3827,
+    ARM_VSUBWsv8i16	= 3828,
+    ARM_VSUBWuv2i64	= 3829,
+    ARM_VSUBWuv4i32	= 3830,
+    ARM_VSUBWuv8i16	= 3831,
+    ARM_VSUBfd	= 3832,
+    ARM_VSUBfq	= 3833,
+    ARM_VSUBhd	= 3834,
+    ARM_VSUBhq	= 3835,
+    ARM_VSUBv16i8	= 3836,
+    ARM_VSUBv1i64	= 3837,
+    ARM_VSUBv2i32	= 3838,
+    ARM_VSUBv2i64	= 3839,
+    ARM_VSUBv4i16	= 3840,
+    ARM_VSUBv4i32	= 3841,
+    ARM_VSUBv8i16	= 3842,
+    ARM_VSUBv8i8	= 3843,
+    ARM_VSUDOTDI	= 3844,
+    ARM_VSUDOTQI	= 3845,
+    ARM_VSWPd	= 3846,
+    ARM_VSWPq	= 3847,
+    ARM_VTBL1	= 3848,
+    ARM_VTBL2	= 3849,
+    ARM_VTBL3	= 3850,
+    ARM_VTBL3Pseudo	= 3851,
+    ARM_VTBL4	= 3852,
+    ARM_VTBL4Pseudo	= 3853,
+    ARM_VTBX1	= 3854,
+    ARM_VTBX2	= 3855,
+    ARM_VTBX3	= 3856,
+    ARM_VTBX3Pseudo	= 3857,
+    ARM_VTBX4	= 3858,
+    ARM_VTBX4Pseudo	= 3859,
+    ARM_VTOSHD	= 3860,
+    ARM_VTOSHH	= 3861,
+    ARM_VTOSHS	= 3862,
+    ARM_VTOSIRD	= 3863,
+    ARM_VTOSIRH	= 3864,
+    ARM_VTOSIRS	= 3865,
+    ARM_VTOSIZD	= 3866,
+    ARM_VTOSIZH	= 3867,
+    ARM_VTOSIZS	= 3868,
+    ARM_VTOSLD	= 3869,
+    ARM_VTOSLH	= 3870,
+    ARM_VTOSLS	= 3871,
+    ARM_VTOUHD	= 3872,
+    ARM_VTOUHH	= 3873,
+    ARM_VTOUHS	= 3874,
+    ARM_VTOUIRD	= 3875,
+    ARM_VTOUIRH	= 3876,
+    ARM_VTOUIRS	= 3877,
+    ARM_VTOUIZD	= 3878,
+    ARM_VTOUIZH	= 3879,
+    ARM_VTOUIZS	= 3880,
+    ARM_VTOULD	= 3881,
+    ARM_VTOULH	= 3882,
+    ARM_VTOULS	= 3883,
+    ARM_VTRNd16	= 3884,
+    ARM_VTRNd32	= 3885,
+    ARM_VTRNd8	= 3886,
+    ARM_VTRNq16	= 3887,
+    ARM_VTRNq32	= 3888,
+    ARM_VTRNq8	= 3889,
+    ARM_VTSTv16i8	= 3890,
+    ARM_VTSTv2i32	= 3891,
+    ARM_VTSTv4i16	= 3892,
+    ARM_VTSTv4i32	= 3893,
+    ARM_VTSTv8i16	= 3894,
+    ARM_VTSTv8i8	= 3895,
+    ARM_VUDOTD	= 3896,
+    ARM_VUDOTDI	= 3897,
+    ARM_VUDOTQ	= 3898,
+    ARM_VUDOTQI	= 3899,
+    ARM_VUHTOD	= 3900,
+    ARM_VUHTOH	= 3901,
+    ARM_VUHTOS	= 3902,
+    ARM_VUITOD	= 3903,
+    ARM_VUITOH	= 3904,
+    ARM_VUITOS	= 3905,
+    ARM_VULTOD	= 3906,
+    ARM_VULTOH	= 3907,
+    ARM_VULTOS	= 3908,
+    ARM_VUMMLA	= 3909,
+    ARM_VUSDOTD	= 3910,
+    ARM_VUSDOTDI	= 3911,
+    ARM_VUSDOTQ	= 3912,
+    ARM_VUSDOTQI	= 3913,
+    ARM_VUSMMLA	= 3914,
+    ARM_VUZPd16	= 3915,
+    ARM_VUZPd8	= 3916,
+    ARM_VUZPq16	= 3917,
+    ARM_VUZPq32	= 3918,
+    ARM_VUZPq8	= 3919,
+    ARM_VZIPd16	= 3920,
+    ARM_VZIPd8	= 3921,
+    ARM_VZIPq16	= 3922,
+    ARM_VZIPq32	= 3923,
+    ARM_VZIPq8	= 3924,
+    ARM_sysLDMDA	= 3925,
+    ARM_sysLDMDA_UPD	= 3926,
+    ARM_sysLDMDB	= 3927,
+    ARM_sysLDMDB_UPD	= 3928,
+    ARM_sysLDMIA	= 3929,
+    ARM_sysLDMIA_UPD	= 3930,
+    ARM_sysLDMIB	= 3931,
+    ARM_sysLDMIB_UPD	= 3932,
+    ARM_sysSTMDA	= 3933,
+    ARM_sysSTMDA_UPD	= 3934,
+    ARM_sysSTMDB	= 3935,
+    ARM_sysSTMDB_UPD	= 3936,
+    ARM_sysSTMIA	= 3937,
+    ARM_sysSTMIA_UPD	= 3938,
+    ARM_sysSTMIB	= 3939,
+    ARM_sysSTMIB_UPD	= 3940,
+    ARM_t2ADCri	= 3941,
+    ARM_t2ADCrr	= 3942,
+    ARM_t2ADCrs	= 3943,
+    ARM_t2ADDri	= 3944,
+    ARM_t2ADDri12	= 3945,
+    ARM_t2ADDrr	= 3946,
+    ARM_t2ADDrs	= 3947,
+    ARM_t2ADDspImm	= 3948,
+    ARM_t2ADDspImm12	= 3949,
+    ARM_t2ADR	= 3950,
+    ARM_t2ANDri	= 3951,
+    ARM_t2ANDrr	= 3952,
+    ARM_t2ANDrs	= 3953,
+    ARM_t2ASRri	= 3954,
+    ARM_t2ASRrr	= 3955,
+    ARM_t2AUT	= 3956,
+    ARM_t2AUTG	= 3957,
+    ARM_t2B	= 3958,
+    ARM_t2BFC	= 3959,
+    ARM_t2BFI	= 3960,
+    ARM_t2BFLi	= 3961,
+    ARM_t2BFLr	= 3962,
+    ARM_t2BFi	= 3963,
+    ARM_t2BFic	= 3964,
+    ARM_t2BFr	= 3965,
+    ARM_t2BICri	= 3966,
+    ARM_t2BICrr	= 3967,
+    ARM_t2BICrs	= 3968,
+    ARM_t2BTI	= 3969,
+    ARM_t2BXAUT	= 3970,
+    ARM_t2BXJ	= 3971,
+    ARM_t2Bcc	= 3972,
+    ARM_t2CDP	= 3973,
+    ARM_t2CDP2	= 3974,
+    ARM_t2CLREX	= 3975,
+    ARM_t2CLRM	= 3976,
+    ARM_t2CLZ	= 3977,
+    ARM_t2CMNri	= 3978,
+    ARM_t2CMNzrr	= 3979,
+    ARM_t2CMNzrs	= 3980,
+    ARM_t2CMPri	= 3981,
+    ARM_t2CMPrr	= 3982,
+    ARM_t2CMPrs	= 3983,
+    ARM_t2CPS1p	= 3984,
+    ARM_t2CPS2p	= 3985,
+    ARM_t2CPS3p	= 3986,
+    ARM_t2CRC32B	= 3987,
+    ARM_t2CRC32CB	= 3988,
+    ARM_t2CRC32CH	= 3989,
+    ARM_t2CRC32CW	= 3990,
+    ARM_t2CRC32H	= 3991,
+    ARM_t2CRC32W	= 3992,
+    ARM_t2CSEL	= 3993,
+    ARM_t2CSINC	= 3994,
+    ARM_t2CSINV	= 3995,
+    ARM_t2CSNEG	= 3996,
+    ARM_t2DBG	= 3997,
+    ARM_t2DCPS1	= 3998,
+    ARM_t2DCPS2	= 3999,
+    ARM_t2DCPS3	= 4000,
+    ARM_t2DLS	= 4001,
+    ARM_t2DMB	= 4002,
+    ARM_t2DSB	= 4003,
+    ARM_t2EORri	= 4004,
+    ARM_t2EORrr	= 4005,
+    ARM_t2EORrs	= 4006,
+    ARM_t2HINT	= 4007,
+    ARM_t2HVC	= 4008,
+    ARM_t2ISB	= 4009,
+    ARM_t2IT	= 4010,
+    ARM_t2Int_eh_sjlj_setjmp	= 4011,
+    ARM_t2Int_eh_sjlj_setjmp_nofp	= 4012,
+    ARM_t2LDA	= 4013,
+    ARM_t2LDAB	= 4014,
+    ARM_t2LDAEX	= 4015,
+    ARM_t2LDAEXB	= 4016,
+    ARM_t2LDAEXD	= 4017,
+    ARM_t2LDAEXH	= 4018,
+    ARM_t2LDAH	= 4019,
+    ARM_t2LDC2L_OFFSET	= 4020,
+    ARM_t2LDC2L_OPTION	= 4021,
+    ARM_t2LDC2L_POST	= 4022,
+    ARM_t2LDC2L_PRE	= 4023,
+    ARM_t2LDC2_OFFSET	= 4024,
+    ARM_t2LDC2_OPTION	= 4025,
+    ARM_t2LDC2_POST	= 4026,
+    ARM_t2LDC2_PRE	= 4027,
+    ARM_t2LDCL_OFFSET	= 4028,
+    ARM_t2LDCL_OPTION	= 4029,
+    ARM_t2LDCL_POST	= 4030,
+    ARM_t2LDCL_PRE	= 4031,
+    ARM_t2LDC_OFFSET	= 4032,
+    ARM_t2LDC_OPTION	= 4033,
+    ARM_t2LDC_POST	= 4034,
+    ARM_t2LDC_PRE	= 4035,
+    ARM_t2LDMDB	= 4036,
+    ARM_t2LDMDB_UPD	= 4037,
+    ARM_t2LDMIA	= 4038,
+    ARM_t2LDMIA_UPD	= 4039,
+    ARM_t2LDRBT	= 4040,
+    ARM_t2LDRB_POST	= 4041,
+    ARM_t2LDRB_PRE	= 4042,
+    ARM_t2LDRBi12	= 4043,
+    ARM_t2LDRBi8	= 4044,
+    ARM_t2LDRBpci	= 4045,
+    ARM_t2LDRBs	= 4046,
+    ARM_t2LDRD_POST	= 4047,
+    ARM_t2LDRD_PRE	= 4048,
+    ARM_t2LDRDi8	= 4049,
+    ARM_t2LDREX	= 4050,
+    ARM_t2LDREXB	= 4051,
+    ARM_t2LDREXD	= 4052,
+    ARM_t2LDREXH	= 4053,
+    ARM_t2LDRHT	= 4054,
+    ARM_t2LDRH_POST	= 4055,
+    ARM_t2LDRH_PRE	= 4056,
+    ARM_t2LDRHi12	= 4057,
+    ARM_t2LDRHi8	= 4058,
+    ARM_t2LDRHpci	= 4059,
+    ARM_t2LDRHs	= 4060,
+    ARM_t2LDRSBT	= 4061,
+    ARM_t2LDRSB_POST	= 4062,
+    ARM_t2LDRSB_PRE	= 4063,
+    ARM_t2LDRSBi12	= 4064,
+    ARM_t2LDRSBi8	= 4065,
+    ARM_t2LDRSBpci	= 4066,
+    ARM_t2LDRSBs	= 4067,
+    ARM_t2LDRSHT	= 4068,
+    ARM_t2LDRSH_POST	= 4069,
+    ARM_t2LDRSH_PRE	= 4070,
+    ARM_t2LDRSHi12	= 4071,
+    ARM_t2LDRSHi8	= 4072,
+    ARM_t2LDRSHpci	= 4073,
+    ARM_t2LDRSHs	= 4074,
+    ARM_t2LDRT	= 4075,
+    ARM_t2LDR_POST	= 4076,
+    ARM_t2LDR_PRE	= 4077,
+    ARM_t2LDRi12	= 4078,
+    ARM_t2LDRi8	= 4079,
+    ARM_t2LDRpci	= 4080,
+    ARM_t2LDRs	= 4081,
+    ARM_t2LE	= 4082,
+    ARM_t2LEUpdate	= 4083,
+    ARM_t2LSLri	= 4084,
+    ARM_t2LSLrr	= 4085,
+    ARM_t2LSRri	= 4086,
+    ARM_t2LSRrr	= 4087,
+    ARM_t2MCR	= 4088,
+    ARM_t2MCR2	= 4089,
+    ARM_t2MCRR	= 4090,
+    ARM_t2MCRR2	= 4091,
+    ARM_t2MLA	= 4092,
+    ARM_t2MLS	= 4093,
+    ARM_t2MOVTi16	= 4094,
+    ARM_t2MOVi	= 4095,
+    ARM_t2MOVi16	= 4096,
+    ARM_t2MOVr	= 4097,
+    ARM_t2MOVsra_flag	= 4098,
+    ARM_t2MOVsrl_flag	= 4099,
+    ARM_t2MRC	= 4100,
+    ARM_t2MRC2	= 4101,
+    ARM_t2MRRC	= 4102,
+    ARM_t2MRRC2	= 4103,
+    ARM_t2MRS_AR	= 4104,
+    ARM_t2MRS_M	= 4105,
+    ARM_t2MRSbanked	= 4106,
+    ARM_t2MRSsys_AR	= 4107,
+    ARM_t2MSR_AR	= 4108,
+    ARM_t2MSR_M	= 4109,
+    ARM_t2MSRbanked	= 4110,
+    ARM_t2MUL	= 4111,
+    ARM_t2MVNi	= 4112,
+    ARM_t2MVNr	= 4113,
+    ARM_t2MVNs	= 4114,
+    ARM_t2ORNri	= 4115,
+    ARM_t2ORNrr	= 4116,
+    ARM_t2ORNrs	= 4117,
+    ARM_t2ORRri	= 4118,
+    ARM_t2ORRrr	= 4119,
+    ARM_t2ORRrs	= 4120,
+    ARM_t2PAC	= 4121,
+    ARM_t2PACBTI	= 4122,
+    ARM_t2PACG	= 4123,
+    ARM_t2PKHBT	= 4124,
+    ARM_t2PKHTB	= 4125,
+    ARM_t2PLDWi12	= 4126,
+    ARM_t2PLDWi8	= 4127,
+    ARM_t2PLDWs	= 4128,
+    ARM_t2PLDi12	= 4129,
+    ARM_t2PLDi8	= 4130,
+    ARM_t2PLDpci	= 4131,
+    ARM_t2PLDs	= 4132,
+    ARM_t2PLIi12	= 4133,
+    ARM_t2PLIi8	= 4134,
+    ARM_t2PLIpci	= 4135,
+    ARM_t2PLIs	= 4136,
+    ARM_t2QADD	= 4137,
+    ARM_t2QADD16	= 4138,
+    ARM_t2QADD8	= 4139,
+    ARM_t2QASX	= 4140,
+    ARM_t2QDADD	= 4141,
+    ARM_t2QDSUB	= 4142,
+    ARM_t2QSAX	= 4143,
+    ARM_t2QSUB	= 4144,
+    ARM_t2QSUB16	= 4145,
+    ARM_t2QSUB8	= 4146,
+    ARM_t2RBIT	= 4147,
+    ARM_t2REV	= 4148,
+    ARM_t2REV16	= 4149,
+    ARM_t2REVSH	= 4150,
+    ARM_t2RFEDB	= 4151,
+    ARM_t2RFEDBW	= 4152,
+    ARM_t2RFEIA	= 4153,
+    ARM_t2RFEIAW	= 4154,
+    ARM_t2RORri	= 4155,
+    ARM_t2RORrr	= 4156,
+    ARM_t2RRX	= 4157,
+    ARM_t2RSBri	= 4158,
+    ARM_t2RSBrr	= 4159,
+    ARM_t2RSBrs	= 4160,
+    ARM_t2SADD16	= 4161,
+    ARM_t2SADD8	= 4162,
+    ARM_t2SASX	= 4163,
+    ARM_t2SB	= 4164,
+    ARM_t2SBCri	= 4165,
+    ARM_t2SBCrr	= 4166,
+    ARM_t2SBCrs	= 4167,
+    ARM_t2SBFX	= 4168,
+    ARM_t2SDIV	= 4169,
+    ARM_t2SEL	= 4170,
+    ARM_t2SETPAN	= 4171,
+    ARM_t2SG	= 4172,
+    ARM_t2SHADD16	= 4173,
+    ARM_t2SHADD8	= 4174,
+    ARM_t2SHASX	= 4175,
+    ARM_t2SHSAX	= 4176,
+    ARM_t2SHSUB16	= 4177,
+    ARM_t2SHSUB8	= 4178,
+    ARM_t2SMC	= 4179,
+    ARM_t2SMLABB	= 4180,
+    ARM_t2SMLABT	= 4181,
+    ARM_t2SMLAD	= 4182,
+    ARM_t2SMLADX	= 4183,
+    ARM_t2SMLAL	= 4184,
+    ARM_t2SMLALBB	= 4185,
+    ARM_t2SMLALBT	= 4186,
+    ARM_t2SMLALD	= 4187,
+    ARM_t2SMLALDX	= 4188,
+    ARM_t2SMLALTB	= 4189,
+    ARM_t2SMLALTT	= 4190,
+    ARM_t2SMLATB	= 4191,
+    ARM_t2SMLATT	= 4192,
+    ARM_t2SMLAWB	= 4193,
+    ARM_t2SMLAWT	= 4194,
+    ARM_t2SMLSD	= 4195,
+    ARM_t2SMLSDX	= 4196,
+    ARM_t2SMLSLD	= 4197,
+    ARM_t2SMLSLDX	= 4198,
+    ARM_t2SMMLA	= 4199,
+    ARM_t2SMMLAR	= 4200,
+    ARM_t2SMMLS	= 4201,
+    ARM_t2SMMLSR	= 4202,
+    ARM_t2SMMUL	= 4203,
+    ARM_t2SMMULR	= 4204,
+    ARM_t2SMUAD	= 4205,
+    ARM_t2SMUADX	= 4206,
+    ARM_t2SMULBB	= 4207,
+    ARM_t2SMULBT	= 4208,
+    ARM_t2SMULL	= 4209,
+    ARM_t2SMULTB	= 4210,
+    ARM_t2SMULTT	= 4211,
+    ARM_t2SMULWB	= 4212,
+    ARM_t2SMULWT	= 4213,
+    ARM_t2SMUSD	= 4214,
+    ARM_t2SMUSDX	= 4215,
+    ARM_t2SRSDB	= 4216,
+    ARM_t2SRSDB_UPD	= 4217,
+    ARM_t2SRSIA	= 4218,
+    ARM_t2SRSIA_UPD	= 4219,
+    ARM_t2SSAT	= 4220,
+    ARM_t2SSAT16	= 4221,
+    ARM_t2SSAX	= 4222,
+    ARM_t2SSUB16	= 4223,
+    ARM_t2SSUB8	= 4224,
+    ARM_t2STC2L_OFFSET	= 4225,
+    ARM_t2STC2L_OPTION	= 4226,
+    ARM_t2STC2L_POST	= 4227,
+    ARM_t2STC2L_PRE	= 4228,
+    ARM_t2STC2_OFFSET	= 4229,
+    ARM_t2STC2_OPTION	= 4230,
+    ARM_t2STC2_POST	= 4231,
+    ARM_t2STC2_PRE	= 4232,
+    ARM_t2STCL_OFFSET	= 4233,
+    ARM_t2STCL_OPTION	= 4234,
+    ARM_t2STCL_POST	= 4235,
+    ARM_t2STCL_PRE	= 4236,
+    ARM_t2STC_OFFSET	= 4237,
+    ARM_t2STC_OPTION	= 4238,
+    ARM_t2STC_POST	= 4239,
+    ARM_t2STC_PRE	= 4240,
+    ARM_t2STL	= 4241,
+    ARM_t2STLB	= 4242,
+    ARM_t2STLEX	= 4243,
+    ARM_t2STLEXB	= 4244,
+    ARM_t2STLEXD	= 4245,
+    ARM_t2STLEXH	= 4246,
+    ARM_t2STLH	= 4247,
+    ARM_t2STMDB	= 4248,
+    ARM_t2STMDB_UPD	= 4249,
+    ARM_t2STMIA	= 4250,
+    ARM_t2STMIA_UPD	= 4251,
+    ARM_t2STRBT	= 4252,
+    ARM_t2STRB_POST	= 4253,
+    ARM_t2STRB_PRE	= 4254,
+    ARM_t2STRBi12	= 4255,
+    ARM_t2STRBi8	= 4256,
+    ARM_t2STRBs	= 4257,
+    ARM_t2STRD_POST	= 4258,
+    ARM_t2STRD_PRE	= 4259,
+    ARM_t2STRDi8	= 4260,
+    ARM_t2STREX	= 4261,
+    ARM_t2STREXB	= 4262,
+    ARM_t2STREXD	= 4263,
+    ARM_t2STREXH	= 4264,
+    ARM_t2STRHT	= 4265,
+    ARM_t2STRH_POST	= 4266,
+    ARM_t2STRH_PRE	= 4267,
+    ARM_t2STRHi12	= 4268,
+    ARM_t2STRHi8	= 4269,
+    ARM_t2STRHs	= 4270,
+    ARM_t2STRT	= 4271,
+    ARM_t2STR_POST	= 4272,
+    ARM_t2STR_PRE	= 4273,
+    ARM_t2STRi12	= 4274,
+    ARM_t2STRi8	= 4275,
+    ARM_t2STRs	= 4276,
+    ARM_t2SUBS_PC_LR	= 4277,
+    ARM_t2SUBri	= 4278,
+    ARM_t2SUBri12	= 4279,
+    ARM_t2SUBrr	= 4280,
+    ARM_t2SUBrs	= 4281,
+    ARM_t2SUBspImm	= 4282,
+    ARM_t2SUBspImm12	= 4283,
+    ARM_t2SXTAB	= 4284,
+    ARM_t2SXTAB16	= 4285,
+    ARM_t2SXTAH	= 4286,
+    ARM_t2SXTB	= 4287,
+    ARM_t2SXTB16	= 4288,
+    ARM_t2SXTH	= 4289,
+    ARM_t2TBB	= 4290,
+    ARM_t2TBH	= 4291,
+    ARM_t2TEQri	= 4292,
+    ARM_t2TEQrr	= 4293,
+    ARM_t2TEQrs	= 4294,
+    ARM_t2TSB	= 4295,
+    ARM_t2TSTri	= 4296,
+    ARM_t2TSTrr	= 4297,
+    ARM_t2TSTrs	= 4298,
+    ARM_t2TT	= 4299,
+    ARM_t2TTA	= 4300,
+    ARM_t2TTAT	= 4301,
+    ARM_t2TTT	= 4302,
+    ARM_t2UADD16	= 4303,
+    ARM_t2UADD8	= 4304,
+    ARM_t2UASX	= 4305,
+    ARM_t2UBFX	= 4306,
+    ARM_t2UDF	= 4307,
+    ARM_t2UDIV	= 4308,
+    ARM_t2UHADD16	= 4309,
+    ARM_t2UHADD8	= 4310,
+    ARM_t2UHASX	= 4311,
+    ARM_t2UHSAX	= 4312,
+    ARM_t2UHSUB16	= 4313,
+    ARM_t2UHSUB8	= 4314,
+    ARM_t2UMAAL	= 4315,
+    ARM_t2UMLAL	= 4316,
+    ARM_t2UMULL	= 4317,
+    ARM_t2UQADD16	= 4318,
+    ARM_t2UQADD8	= 4319,
+    ARM_t2UQASX	= 4320,
+    ARM_t2UQSAX	= 4321,
+    ARM_t2UQSUB16	= 4322,
+    ARM_t2UQSUB8	= 4323,
+    ARM_t2USAD8	= 4324,
+    ARM_t2USADA8	= 4325,
+    ARM_t2USAT	= 4326,
+    ARM_t2USAT16	= 4327,
+    ARM_t2USAX	= 4328,
+    ARM_t2USUB16	= 4329,
+    ARM_t2USUB8	= 4330,
+    ARM_t2UXTAB	= 4331,
+    ARM_t2UXTAB16	= 4332,
+    ARM_t2UXTAH	= 4333,
+    ARM_t2UXTB	= 4334,
+    ARM_t2UXTB16	= 4335,
+    ARM_t2UXTH	= 4336,
+    ARM_t2WLS	= 4337,
+    ARM_tADC	= 4338,
+    ARM_tADDhirr	= 4339,
+    ARM_tADDi3	= 4340,
+    ARM_tADDi8	= 4341,
+    ARM_tADDrSP	= 4342,
+    ARM_tADDrSPi	= 4343,
+    ARM_tADDrr	= 4344,
+    ARM_tADDspi	= 4345,
+    ARM_tADDspr	= 4346,
+    ARM_tADR	= 4347,
+    ARM_tAND	= 4348,
+    ARM_tASRri	= 4349,
+    ARM_tASRrr	= 4350,
+    ARM_tB	= 4351,
+    ARM_tBIC	= 4352,
+    ARM_tBKPT	= 4353,
+    ARM_tBL	= 4354,
+    ARM_tBLXNSr	= 4355,
+    ARM_tBLXi	= 4356,
+    ARM_tBLXr	= 4357,
+    ARM_tBX	= 4358,
+    ARM_tBXNS	= 4359,
+    ARM_tBcc	= 4360,
+    ARM_tCBNZ	= 4361,
+    ARM_tCBZ	= 4362,
+    ARM_tCMNz	= 4363,
+    ARM_tCMPhir	= 4364,
+    ARM_tCMPi8	= 4365,
+    ARM_tCMPr	= 4366,
+    ARM_tCPS	= 4367,
+    ARM_tEOR	= 4368,
+    ARM_tHINT	= 4369,
+    ARM_tHLT	= 4370,
+    ARM_tInt_WIN_eh_sjlj_longjmp	= 4371,
+    ARM_tInt_eh_sjlj_longjmp	= 4372,
+    ARM_tInt_eh_sjlj_setjmp	= 4373,
+    ARM_tLDMIA	= 4374,
+    ARM_tLDRBi	= 4375,
+    ARM_tLDRBr	= 4376,
+    ARM_tLDRHi	= 4377,
+    ARM_tLDRHr	= 4378,
+    ARM_tLDRSB	= 4379,
+    ARM_tLDRSH	= 4380,
+    ARM_tLDRi	= 4381,
+    ARM_tLDRpci	= 4382,
+    ARM_tLDRr	= 4383,
+    ARM_tLDRspi	= 4384,
+    ARM_tLSLri	= 4385,
+    ARM_tLSLrr	= 4386,
+    ARM_tLSRri	= 4387,
+    ARM_tLSRrr	= 4388,
+    ARM_tMOVSr	= 4389,
+    ARM_tMOVi8	= 4390,
+    ARM_tMOVr	= 4391,
+    ARM_tMUL	= 4392,
+    ARM_tMVN	= 4393,
+    ARM_tORR	= 4394,
+    ARM_tPICADD	= 4395,
+    ARM_tPOP	= 4396,
+    ARM_tPUSH	= 4397,
+    ARM_tREV	= 4398,
+    ARM_tREV16	= 4399,
+    ARM_tREVSH	= 4400,
+    ARM_tROR	= 4401,
+    ARM_tRSB	= 4402,
+    ARM_tSBC	= 4403,
+    ARM_tSETEND	= 4404,
+    ARM_tSTMIA_UPD	= 4405,
+    ARM_tSTRBi	= 4406,
+    ARM_tSTRBr	= 4407,
+    ARM_tSTRHi	= 4408,
+    ARM_tSTRHr	= 4409,
+    ARM_tSTRi	= 4410,
+    ARM_tSTRr	= 4411,
+    ARM_tSTRspi	= 4412,
+    ARM_tSUBi3	= 4413,
+    ARM_tSUBi8	= 4414,
+    ARM_tSUBrr	= 4415,
+    ARM_tSUBspi	= 4416,
+    ARM_tSVC	= 4417,
+    ARM_tSXTB	= 4418,
+    ARM_tSXTH	= 4419,
+    ARM_tTRAP	= 4420,
+    ARM_tTST	= 4421,
+    ARM_tUDF	= 4422,
+    ARM_tUXTB	= 4423,
+    ARM_tUXTH	= 4424,
+    ARM_t__brkdiv0	= 4425,
+    INSTRUCTION_LIST_END = 4426
+  };
 
 #endif // GET_INSTRINFO_ENUM
 
 #ifdef GET_INSTRINFO_MC_DESC
 #undef GET_INSTRINFO_MC_DESC
 
-#define nullptr 0
 
 static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
 static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
 static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
 static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
 static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
-static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
-static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
-static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
-static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
-static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
-static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
-static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
-static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
 static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
-static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
-static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
-static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
-static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
-static const MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo38[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
-static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
-static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
-static const MCOperandInfo OperandInfo42[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo48[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo55[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo73[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo74[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo75[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo76[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo77[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo78[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo79[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo80[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo81[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo82[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo83[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo84[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo86[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo87[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo88[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo89[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo90[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo91[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo92[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo93[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo94[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo95[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo96[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo97[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo98[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo100[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo101[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo102[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo103[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo104[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo105[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo106[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo107[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo108[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo110[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo111[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo112[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo113[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
-static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo116[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo118[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo119[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo121[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo122[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo126[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo127[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo128[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo130[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo132[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo133[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo134[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
-static const MCOperandInfo OperandInfo135[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo136[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo137[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo138[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo139[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo140[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo141[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo144[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo145[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo146[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo147[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo148[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo149[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo150[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo152[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo154[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo155[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo156[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo158[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo159[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo160[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo161[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo162[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo163[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo164[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo165[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo166[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo167[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo168[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo169[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
-static const MCOperandInfo OperandInfo170[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
-static const MCOperandInfo OperandInfo171[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo172[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo173[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo174[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo175[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo176[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo177[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo178[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo179[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo180[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo181[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo182[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo183[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo184[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo185[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo186[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo187[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo188[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo189[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo190[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo191[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo193[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo199[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo201[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo203[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo204[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo207[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo208[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo209[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo210[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo211[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo215[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo217[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo218[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo220[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo221[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo222[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo223[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo231[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo232[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo233[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo234[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo235[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo237[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo238[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo239[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo240[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo241[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo242[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo243[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo244[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo245[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo246[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo247[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo248[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo249[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo250[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo251[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo252[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo253[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo254[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo255[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo256[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo257[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo258[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo259[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo263[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo264[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo268[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo269[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo270[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo271[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo272[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo273[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo274[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo275[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo276[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo277[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo278[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo279[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo280[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo281[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo282[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo283[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo284[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo285[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo286[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo287[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo288[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo289[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo290[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo291[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo292[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo293[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo294[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo295[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo296[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo297[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo298[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo299[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo300[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo301[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo302[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo303[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo304[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo305[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo306[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo307[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo308[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo309[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo310[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo312[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo317[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo318[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo320[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo322[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo323[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo332[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo333[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo337[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo338[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo339[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo340[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo341[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo342[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo343[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo344[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo345[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo346[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo348[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo349[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo350[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo351[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo352[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo353[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo354[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo355[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo356[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo357[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo358[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo359[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo360[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo361[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo362[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo363[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo364[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo365[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo366[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo367[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo368[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo369[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo370[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo371[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo372[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo373[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo374[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo375[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo376[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo377[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo378[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo379[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo380[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo381[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo382[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo383[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo384[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo385[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo386[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo387[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo388[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo389[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo390[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo391[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo392[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo393[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo394[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo395[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo396[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo397[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo398[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo399[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo400[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo401[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo402[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo403[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo404[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo405[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo406[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
-static const MCOperandInfo OperandInfo407[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo408[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
-static const MCOperandInfo OperandInfo409[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
-static const MCOperandInfo OperandInfo410[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo411[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo412[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo413[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo414[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo415[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo416[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo417[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo418[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
-static const MCOperandInfo OperandInfo419[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, };
+static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, };
+static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_IMM_0, 0 }, };
+static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI_OPERAND_GENERIC_1, 0 }, };
+static const MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo47[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo48[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo49[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo50[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo52[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo53[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo54[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo56[] = { { ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo57[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo58[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo64[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo70[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo72[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo73[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo74[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo75[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo80[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo81[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo82[] = { { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo83[] = { { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo84[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo85[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo86[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo87[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo88[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo89[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo90[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo91[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo92[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo93[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo95[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo96[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo97[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo98[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo99[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo100[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo101[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo102[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo103[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo104[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo105[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo106[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo107[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo108[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo109[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo110[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo111[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo112[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo113[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo114[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo115[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo116[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo117[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo118[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo119[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo120[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo121[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo122[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo123[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo124[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo125[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo126[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo127[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo128[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo129[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo130[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo131[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo132[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo133[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo134[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo135[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnoipRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo136[] = { { ARM_GPRlrRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo137[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo138[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo139[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo140[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo141[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo142[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo143[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo144[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo145[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo146[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo147[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo148[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo149[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo150[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo151[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo152[] = { { ARM_tGPRwithpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
+static const MCOperandInfo OperandInfo153[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo154[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo155[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo156[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo157[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo158[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo159[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo160[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo162[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo163[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo164[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo165[] = { { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo166[] = { { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo167[] = { { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo168[] = { { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo169[] = { { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo170[] = { { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo171[] = { { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo172[] = { { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo173[] = { { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo174[] = { { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo175[] = { { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo176[] = { { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRPairnospRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithAPSR_NZCVnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo177[] = { { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo178[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo179[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo180[] = { { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo181[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo182[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo183[] = { { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo184[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo185[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo186[] = { { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo187[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo188[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo189[] = { { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo190[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo191[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo192[] = { { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo194[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo195[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo196[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo197[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo198[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo199[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo200[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo201[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo202[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo203[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo204[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo205[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo207[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo208[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo209[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo210[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo211[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo212[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo213[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo214[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo215[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo216[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo217[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo218[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo219[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(2) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo220[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo221[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo222[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo223[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo224[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo225[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo226[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo227[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo228[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo229[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo230[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo232[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo234[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo235[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo236[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo237[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo238[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo239[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo240[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo241[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo242[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo243[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo244[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo245[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo246[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo247[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo248[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo249[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo250[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo251[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo252[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo253[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo254[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo255[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo256[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo257[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo258[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo259[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo260[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo261[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo262[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo263[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo264[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo265[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo266[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo267[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo268[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo269[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo270[] = { { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo271[] = { { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, };
+static const MCOperandInfo OperandInfo272[] = { { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo273[] = { { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, };
+static const MCOperandInfo OperandInfo274[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo275[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo276[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo277[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo278[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo279[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo280[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo282[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo283[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo284[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo285[] = { { ARM_tGPREvenRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPROddRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo287[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo289[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo290[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo291[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo292[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo293[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo294[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo295[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo296[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo297[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo298[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo299[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo300[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, ARM_OP_VPRED_R, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_R, 0 }, { ARM_MQPRRegClassID, 0, ARM_OP_VPRED_R, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo302[] = { { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo304[] = { { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo306[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo307[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo308[] = { { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_MQPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, ARM_OP_VPRED_N, 0 }, { ARM_VCCRRegClassID, 0, ARM_OP_VPRED_N, 0 }, { ARM_GPRlrRegClassID, 0, ARM_OP_VPRED_N, 0 }, };
+static const MCOperandInfo OperandInfo309[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo310[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo311[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo312[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo313[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, };
+static const MCOperandInfo OperandInfo315[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, };
+static const MCOperandInfo OperandInfo317[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo318[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo319[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo320[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo321[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo322[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo323[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo324[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo325[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo326[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo329[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo332[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo333[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo334[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo336[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo337[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo338[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo339[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo340[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo341[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo342[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo343[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo344[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo345[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo346[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo347[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo348[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo349[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo350[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo351[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo352[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo353[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo354[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo355[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo356[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo357[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo358[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo359[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo360[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo361[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo362[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo363[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo364[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo365[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo366[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo367[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo368[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo369[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo370[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo371[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo372[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo373[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo374[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo375[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo376[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo377[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo378[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo379[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo380[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo381[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo382[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo383[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo384[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo385[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo386[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo387[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo388[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo389[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo390[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo391[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo392[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo393[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo394[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo395[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo396[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo397[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo398[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo399[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo400[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo401[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo402[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo403[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo404[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo405[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo406[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo407[] = { { ARM_DPairSpcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo408[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo409[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo410[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo411[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo412[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo413[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo414[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo415[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo416[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo417[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo418[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo419[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo420[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(4) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo421[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo422[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(4) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(2) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(3) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo423[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo424[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo425[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo426[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo427[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo428[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo429[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo430[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo431[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo432[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo433[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo434[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo435[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo436[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo437[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo438[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo439[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo440[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo441[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo442[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo443[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo444[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo445[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo446[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo447[] = { { ARM_cl_FPSCR_NZCVRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo448[] = { { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo449[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo450[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo451[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo452[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo453[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo454[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo455[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo456[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo457[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo458[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo459[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo460[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo461[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo462[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo463[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo464[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo465[] = { { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo466[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo467[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo468[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo469[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo470[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo471[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo472[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo473[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo474[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo475[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo476[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo477[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo478[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo479[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo480[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo481[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo482[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo483[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo484[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo485[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo486[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo487[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo488[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo489[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo490[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo491[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo492[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo493[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo494[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo495[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo496[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo497[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo498[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_VCCRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo499[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo500[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo501[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo502[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo503[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo504[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo505[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_HPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo506[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo507[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo508[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo509[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo510[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo511[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo512[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo513[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo514[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo515[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo516[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo517[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo518[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo519[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo520[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo521[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo522[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo523[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo524[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo525[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRwithZRnospRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo526[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo527[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo528[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo529[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo530[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo531[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(2) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo532[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo533[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo534[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo535[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo536[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo537[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo538[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo539[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo540[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo541[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo542[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo543[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo544[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo545[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo546[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo547[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo548[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo549[] = { { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo550[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo551[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo552[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo553[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo554[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo555[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo556[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo557[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo558[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo559[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo560[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_EARLY_CLOBBER }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo561[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo562[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo563[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo564[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo565[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo566[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo567[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo568[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo569[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo570[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo571[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo572[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo573[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
+static const MCOperandInfo OperandInfo574[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
+static const MCOperandInfo OperandInfo575[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo576[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo577[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo578[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo579[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo580[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0, MCOI_OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo581[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo582[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo583[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
+static const MCOperandInfo OperandInfo584[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, CONSTRAINT_MCOI_TIED_TO(0) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
 
 static const MCInstrDesc ARMInsts[] = {
-  { 1, OperandInfo2 },
-  { 0, nullptr },
-  { 1, OperandInfo3 },
-  { 1, OperandInfo3 },
-  { 1, OperandInfo3 },
-  { 1, OperandInfo3 },
-  { 0, nullptr },
-  { 3, OperandInfo4 },
-  { 4, OperandInfo5 },
-  { 1, OperandInfo2 },
-  { 4, OperandInfo6 },
-  { 3, OperandInfo4 },
-  { 0, nullptr },
-  { 1, OperandInfo2 },
-  { 2, OperandInfo7 },
-  { 2, OperandInfo7 },
-  { 0, nullptr },
-  { 1, OperandInfo3 },
-  { 1, OperandInfo3 },
-  { 2, OperandInfo8 },
-  { 1, OperandInfo2 },
-  { 6, OperandInfo9 },
-  { 1, OperandInfo10 },
-  { 0, nullptr },
-  { 2, OperandInfo11 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 0, nullptr },
-  { 0, nullptr },
-  { 0, nullptr },
-  { 0, nullptr },
-  { 2, OperandInfo11 },
-  { 3, OperandInfo12 },
-  { 1, OperandInfo2 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 1, OperandInfo14 },
-  { 1, OperandInfo14 },
-  { 2, OperandInfo15 },
-  { 2, OperandInfo15 },
-  { 3, OperandInfo16 },
-  { 2, OperandInfo17 },
-  { 4, OperandInfo18 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 5, OperandInfo19 },
-  { 4, OperandInfo20 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 3, OperandInfo21 },
-  { 2, OperandInfo15 },
-  { 1, OperandInfo14 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo15 },
-  { 2, OperandInfo15 },
-  { 1, OperandInfo14 },
-  { 3, OperandInfo16 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 4, OperandInfo22 },
-  { 4, OperandInfo22 },
-  { 4, OperandInfo20 },
-  { 5, OperandInfo23 },
-  { 5, OperandInfo23 },
-  { 4, OperandInfo20 },
-  { 4, OperandInfo20 },
-  { 4, OperandInfo20 },
-  { 4, OperandInfo20 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 4, OperandInfo24 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 3, OperandInfo13 },
-  { 2, OperandInfo25 },
-  { 2, OperandInfo25 },
-  { 2, OperandInfo25 },
-  { 2, OperandInfo25 },
-  { 2, OperandInfo25 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo25 },
-  { 3, OperandInfo26 },
-  { 3, OperandInfo27 },
-  { 1, OperandInfo2 },
-  { 4, OperandInfo28 },
-  { 3, OperandInfo29 },
-  { 4, OperandInfo30 },
-  { 2, OperandInfo25 },
-  { 2, OperandInfo17 },
-  { 2, OperandInfo15 },
-  { 2, OperandInfo31 },
-  { 5, OperandInfo32 },
-  { 5, OperandInfo33 },
-  { 6, OperandInfo34 },
-  { 7, OperandInfo35 },
-  { 4, OperandInfo36 },
-  { 4, OperandInfo36 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo38 },
-  { 1, OperandInfo39 },
-  { 4, OperandInfo40 },
-  { 6, OperandInfo41 },
-  { 1, OperandInfo39 },
-  { 1, OperandInfo42 },
-  { 3, OperandInfo43 },
-  { 3, OperandInfo44 },
-  { 4, OperandInfo45 },
-  { 2, OperandInfo46 },
-  { 1, OperandInfo42 },
-  { 5, OperandInfo47 },
-  { 5, OperandInfo47 },
-  { 5, OperandInfo48 },
-  { 5, OperandInfo47 },
-  { 3, OperandInfo4 },
-  { 4, OperandInfo49 },
-  { 1, OperandInfo3 },
-  { 2, OperandInfo7 },
-  { 0, nullptr },
-  { 2, OperandInfo31 },
-  { 2, OperandInfo31 },
-  { 2, OperandInfo31 },
-  { 0, nullptr },
-  { 3, OperandInfo4 },
-  { 3, OperandInfo4 },
-  { 3, OperandInfo4 },
-  { 3, OperandInfo4 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo52 },
-  { 2, OperandInfo46 },
-  { 2, OperandInfo46 },
-  { 2, OperandInfo46 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo53 },
-  { 4, OperandInfo53 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo38 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo38 },
-  { 5, OperandInfo54 },
-  { 7, OperandInfo55 },
-  { 5, OperandInfo56 },
-  { 5, OperandInfo56 },
-  { 5, OperandInfo57 },
-  { 5, OperandInfo58 },
-  { 6, OperandInfo59 },
-  { 7, OperandInfo60 },
-  { 1, OperandInfo61 },
-  { 4, OperandInfo62 },
-  { 2, OperandInfo46 },
-  { 2, OperandInfo46 },
-  { 3, OperandInfo63 },
-  { 2, OperandInfo46 },
-  { 2, OperandInfo31 },
-  { 2, OperandInfo31 },
-  { 6, OperandInfo64 },
-  { 5, OperandInfo56 },
-  { 5, OperandInfo32 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo38 },
-  { 2, OperandInfo31 },
-  { 5, OperandInfo66 },
-  { 5, OperandInfo32 },
-  { 6, OperandInfo34 },
-  { 7, OperandInfo35 },
-  { 9, OperandInfo67 },
-  { 7, OperandInfo68 },
-  { 3, OperandInfo69 },
-  { 4, OperandInfo51 },
-  { 7, OperandInfo70 },
-  { 7, OperandInfo70 },
-  { 7, OperandInfo71 },
-  { 4, OperandInfo51 },
-  { 7, OperandInfo70 },
-  { 7, OperandInfo70 },
-  { 3, OperandInfo72 },
-  { 5, OperandInfo32 },
-  { 5, OperandInfo33 },
-  { 6, OperandInfo34 },
-  { 7, OperandInfo35 },
-  { 1, OperandInfo39 },
-  { 1, OperandInfo73 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo3 },
-  { 1, OperandInfo73 },
-  { 0, nullptr },
-  { 9, OperandInfo67 },
-  { 7, OperandInfo68 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 1, OperandInfo78 },
-  { 5, OperandInfo79 },
-  { 1, OperandInfo80 },
-  { 5, OperandInfo81 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 6, OperandInfo74 },
-  { 7, OperandInfo75 },
-  { 7, OperandInfo75 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 6, OperandInfo77 },
-  { 0, nullptr },
-  { 1, OperandInfo42 },
-  { 2, OperandInfo82 },
-  { 5, OperandInfo83 },
-  { 5, OperandInfo84 },
-  { 6, OperandInfo85 },
-  { 3, OperandInfo43 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo52 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo86 },
-  { 3, OperandInfo87 },
-  { 4, OperandInfo52 },
-  { 4, OperandInfo88 },
-  { 4, OperandInfo88 },
-  { 6, OperandInfo89 },
-  { 5, OperandInfo90 },
-  { 5, OperandInfo90 },
-  { 5, OperandInfo91 },
-  { 6, OperandInfo89 },
-  { 6, OperandInfo89 },
-  { 5, OperandInfo92 },
-  { 6, OperandInfo89 },
-  { 5, OperandInfo93 },
-  { 6, OperandInfo94 },
-  { 4, OperandInfo95 },
-  { 2, OperandInfo96 },
-  { 3, OperandInfo87 },
-  { 2, OperandInfo96 },
-  { 5, OperandInfo93 },
-  { 6, OperandInfo94 },
-  { 5, OperandInfo90 },
-  { 5, OperandInfo97 },
-  { 6, OperandInfo98 },
-  { 6, OperandInfo99 },
-  { 6, OperandInfo99 },
-  { 6, OperandInfo99 },
-  { 5, OperandInfo83 },
-  { 5, OperandInfo84 },
-  { 6, OperandInfo85 },
-  { 4, OperandInfo49 },
-  { 4, OperandInfo49 },
-  { 3, OperandInfo100 },
-  { 3, OperandInfo101 },
-  { 3, OperandInfo101 },
-  { 3, OperandInfo100 },
-  { 3, OperandInfo102 },
-  { 2, OperandInfo8 },
-  { 2, OperandInfo8 },
-  { 3, OperandInfo103 },
-  { 2, OperandInfo104 },
-  { 1, OperandInfo42 },
-  { 2, OperandInfo105 },
-  { 3, OperandInfo106 },
-  { 3, OperandInfo107 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo108 },
-  { 2, OperandInfo104 },
-  { 2, OperandInfo104 },
-  { 5, OperandInfo109 },
-  { 3, OperandInfo63 },
-  { 4, OperandInfo110 },
-  { 4, OperandInfo110 },
-  { 5, OperandInfo111 },
-  { 3, OperandInfo112 },
-  { 3, OperandInfo100 },
-  { 3, OperandInfo101 },
-  { 3, OperandInfo101 },
-  { 3, OperandInfo100 },
-  { 3, OperandInfo107 },
-  { 3, OperandInfo107 },
-  { 1, OperandInfo73 },
-  { 4, OperandInfo113 },
-  { 4, OperandInfo113 },
-  { 0, nullptr },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo116 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 4, OperandInfo52 },
-  { 3, OperandInfo118 },
-  { 3, OperandInfo118 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 5, OperandInfo56 },
-  { 6, OperandInfo120 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo39 },
-  { 1, OperandInfo61 },
-  { 3, OperandInfo103 },
-  { 1, OperandInfo39 },
-  { 3, OperandInfo107 },
-  { 1, OperandInfo61 },
-  { 3, OperandInfo103 },
-  { 2, OperandInfo105 },
-  { 3, OperandInfo103 },
-  { 3, OperandInfo107 },
-  { 8, OperandInfo121 },
-  { 6, OperandInfo122 },
-  { 0, nullptr },
-  { 4, OperandInfo123 },
-  { 4, OperandInfo52 },
-  { 4, OperandInfo123 },
-  { 5, OperandInfo124 },
-  { 6, OperandInfo125 },
-  { 4, OperandInfo52 },
-  { 4, OperandInfo123 },
-  { 5, OperandInfo124 },
-  { 6, OperandInfo125 },
-  { 1, OperandInfo2 },
-  { 2, OperandInfo7 },
-  { 3, OperandInfo126 },
-  { 3, OperandInfo127 },
-  { 3, OperandInfo127 },
-  { 3, OperandInfo127 },
-  { 3, OperandInfo127 },
-  { 3, OperandInfo127 },
-  { 3, OperandInfo127 },
-  { 3, OperandInfo128 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 2, OperandInfo105 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo130 },
-  { 4, OperandInfo131 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 2, OperandInfo105 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 3, OperandInfo128 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo133 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo135 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo135 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo134 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 7, OperandInfo138 },
-  { 7, OperandInfo138 },
-  { 7, OperandInfo138 },
-  { 7, OperandInfo138 },
-  { 6, OperandInfo139 },
-  { 7, OperandInfo138 },
-  { 5, OperandInfo140 },
-  { 6, OperandInfo141 },
-  { 7, OperandInfo142 },
-  { 8, OperandInfo143 },
-  { 8, OperandInfo143 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo133 },
-  { 4, OperandInfo51 },
-  { 6, OperandInfo144 },
-  { 6, OperandInfo139 },
-  { 7, OperandInfo145 },
-  { 7, OperandInfo146 },
-  { 7, OperandInfo146 },
-  { 6, OperandInfo144 },
-  { 6, OperandInfo139 },
-  { 7, OperandInfo145 },
-  { 7, OperandInfo146 },
-  { 7, OperandInfo146 },
-  { 6, OperandInfo144 },
-  { 6, OperandInfo139 },
-  { 7, OperandInfo145 },
-  { 7, OperandInfo146 },
-  { 7, OperandInfo146 },
-  { 7, OperandInfo138 },
-  { 7, OperandInfo138 },
-  { 7, OperandInfo138 },
-  { 7, OperandInfo138 },
-  { 6, OperandInfo139 },
-  { 7, OperandInfo138 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 6, OperandInfo147 },
-  { 8, OperandInfo148 },
-  { 6, OperandInfo149 },
-  { 7, OperandInfo150 },
-  { 5, OperandInfo151 },
-  { 7, OperandInfo152 },
-  { 6, OperandInfo153 },
-  { 2, OperandInfo105 },
-  { 5, OperandInfo154 },
-  { 5, OperandInfo155 },
-  { 4, OperandInfo52 },
-  { 5, OperandInfo66 },
-  { 5, OperandInfo156 },
-  { 6, OperandInfo157 },
-  { 7, OperandInfo158 },
-  { 8, OperandInfo159 },
-  { 6, OperandInfo160 },
-  { 7, OperandInfo161 },
-  { 5, OperandInfo162 },
-  { 3, OperandInfo163 },
-  { 4, OperandInfo86 },
-  { 3, OperandInfo163 },
-  { 4, OperandInfo164 },
-  { 4, OperandInfo165 },
-  { 4, OperandInfo166 },
-  { 6, OperandInfo38 },
-  { 5, OperandInfo155 },
-  { 5, OperandInfo66 },
-  { 6, OperandInfo157 },
-  { 7, OperandInfo167 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 6, OperandInfo168 },
-  { 6, OperandInfo168 },
-  { 2, OperandInfo169 },
-  { 3, OperandInfo170 },
-  { 2, OperandInfo169 },
-  { 3, OperandInfo170 },
-  { 2, OperandInfo169 },
-  { 3, OperandInfo170 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 4, OperandInfo123 },
-  { 4, OperandInfo123 },
-  { 4, OperandInfo123 },
-  { 4, OperandInfo123 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 1, OperandInfo61 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo116 },
-  { 6, OperandInfo172 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo33 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 4, OperandInfo173 },
-  { 2, OperandInfo119 },
-  { 4, OperandInfo173 },
-  { 4, OperandInfo173 },
-  { 4, OperandInfo173 },
-  { 3, OperandInfo118 },
-  { 4, OperandInfo173 },
-  { 4, OperandInfo173 },
-  { 3, OperandInfo118 },
-  { 4, OperandInfo173 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 3, OperandInfo128 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 9, OperandInfo175 },
-  { 8, OperandInfo176 },
-  { 8, OperandInfo176 },
-  { 8, OperandInfo176 },
-  { 8, OperandInfo176 },
-  { 8, OperandInfo176 },
-  { 8, OperandInfo176 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 6, OperandInfo174 },
-  { 8, OperandInfo176 },
-  { 8, OperandInfo176 },
-  { 6, OperandInfo153 },
-  { 6, OperandInfo153 },
-  { 6, OperandInfo153 },
-  { 6, OperandInfo153 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo33 },
-  { 7, OperandInfo177 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 1, OperandInfo2 },
-  { 6, OperandInfo178 },
-  { 5, OperandInfo179 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo135 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo135 },
-  { 4, OperandInfo134 },
-  { 4, OperandInfo134 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo51 },
-  { 5, OperandInfo180 },
-  { 5, OperandInfo180 },
-  { 5, OperandInfo181 },
-  { 5, OperandInfo180 },
-  { 4, OperandInfo51 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 7, OperandInfo182 },
-  { 7, OperandInfo182 },
-  { 7, OperandInfo183 },
-  { 7, OperandInfo183 },
-  { 6, OperandInfo184 },
-  { 7, OperandInfo183 },
-  { 5, OperandInfo140 },
-  { 6, OperandInfo141 },
-  { 7, OperandInfo142 },
-  { 8, OperandInfo185 },
-  { 8, OperandInfo185 },
-  { 5, OperandInfo180 },
-  { 5, OperandInfo180 },
-  { 5, OperandInfo181 },
-  { 5, OperandInfo180 },
-  { 6, OperandInfo144 },
-  { 6, OperandInfo186 },
-  { 7, OperandInfo182 },
-  { 7, OperandInfo187 },
-  { 7, OperandInfo187 },
-  { 7, OperandInfo182 },
-  { 7, OperandInfo182 },
-  { 7, OperandInfo183 },
-  { 7, OperandInfo183 },
-  { 6, OperandInfo184 },
-  { 7, OperandInfo183 },
-  { 5, OperandInfo65 },
-  { 6, OperandInfo147 },
-  { 6, OperandInfo37 },
-  { 6, OperandInfo114 },
-  { 7, OperandInfo115 },
-  { 8, OperandInfo117 },
-  { 3, OperandInfo128 },
-  { 5, OperandInfo188 },
-  { 5, OperandInfo188 },
-  { 6, OperandInfo189 },
-  { 6, OperandInfo189 },
-  { 6, OperandInfo189 },
-  { 5, OperandInfo190 },
-  { 5, OperandInfo190 },
-  { 5, OperandInfo190 },
-  { 4, OperandInfo52 },
-  { 4, OperandInfo123 },
-  { 5, OperandInfo124 },
-  { 6, OperandInfo125 },
-  { 0, nullptr },
-  { 0, nullptr },
-  { 1, OperandInfo2 },
-  { 4, OperandInfo52 },
-  { 4, OperandInfo123 },
-  { 5, OperandInfo124 },
-  { 6, OperandInfo125 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 6, OperandInfo172 },
-  { 1, OperandInfo2 },
-  { 5, OperandInfo33 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 8, OperandInfo191 },
-  { 9, OperandInfo175 },
-  { 7, OperandInfo177 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo33 },
-  { 6, OperandInfo153 },
-  { 6, OperandInfo178 },
-  { 5, OperandInfo179 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 5, OperandInfo171 },
-  { 6, OperandInfo189 },
-  { 6, OperandInfo189 },
-  { 6, OperandInfo189 },
-  { 5, OperandInfo190 },
-  { 5, OperandInfo190 },
-  { 5, OperandInfo190 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo201 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo203 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo205 },
-  { 5, OperandInfo205 },
-  { 5, OperandInfo206 },
-  { 5, OperandInfo206 },
-  { 5, OperandInfo197 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 4, OperandInfo207 },
-  { 4, OperandInfo207 },
-  { 4, OperandInfo208 },
-  { 4, OperandInfo208 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo209 },
-  { 6, OperandInfo210 },
-  { 5, OperandInfo209 },
-  { 6, OperandInfo211 },
-  { 5, OperandInfo212 },
-  { 6, OperandInfo213 },
-  { 5, OperandInfo212 },
-  { 6, OperandInfo214 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo215 },
-  { 4, OperandInfo199 },
-  { 3, OperandInfo216 },
-  { 3, OperandInfo217 },
-  { 3, OperandInfo218 },
-  { 4, OperandInfo215 },
-  { 4, OperandInfo199 },
-  { 3, OperandInfo216 },
-  { 3, OperandInfo217 },
-  { 3, OperandInfo218 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo224 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo224 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo220 },
-  { 2, OperandInfo221 },
-  { 2, OperandInfo222 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo224 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo201 },
-  { 5, OperandInfo203 },
-  { 4, OperandInfo229 },
-  { 4, OperandInfo230 },
-  { 4, OperandInfo229 },
-  { 4, OperandInfo230 },
-  { 4, OperandInfo229 },
-  { 4, OperandInfo230 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 6, OperandInfo232 },
-  { 6, OperandInfo232 },
-  { 6, OperandInfo232 },
-  { 6, OperandInfo233 },
-  { 6, OperandInfo233 },
-  { 6, OperandInfo233 },
-  { 6, OperandInfo233 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 6, OperandInfo235 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 6, OperandInfo235 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 6, OperandInfo235 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 6, OperandInfo235 },
-  { 5, OperandInfo236 },
-  { 5, OperandInfo236 },
-  { 5, OperandInfo236 },
-  { 5, OperandInfo236 },
-  { 5, OperandInfo236 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 2, OperandInfo222 },
-  { 4, OperandInfo223 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 7, OperandInfo242 },
-  { 9, OperandInfo243 },
-  { 7, OperandInfo242 },
-  { 9, OperandInfo243 },
-  { 7, OperandInfo242 },
-  { 9, OperandInfo243 },
-  { 7, OperandInfo244 },
-  { 9, OperandInfo245 },
-  { 7, OperandInfo244 },
-  { 9, OperandInfo245 },
-  { 7, OperandInfo244 },
-  { 9, OperandInfo245 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo247 },
-  { 7, OperandInfo248 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo247 },
-  { 7, OperandInfo248 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo250 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo250 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo250 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo250 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo251 },
-  { 6, OperandInfo252 },
-  { 7, OperandInfo253 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo251 },
-  { 6, OperandInfo252 },
-  { 7, OperandInfo253 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo251 },
-  { 6, OperandInfo252 },
-  { 7, OperandInfo253 },
-  { 5, OperandInfo246 },
-  { 5, OperandInfo246 },
-  { 5, OperandInfo246 },
-  { 5, OperandInfo246 },
-  { 5, OperandInfo246 },
-  { 5, OperandInfo246 },
-  { 9, OperandInfo254 },
-  { 7, OperandInfo244 },
-  { 9, OperandInfo245 },
-  { 11, OperandInfo255 },
-  { 9, OperandInfo254 },
-  { 7, OperandInfo244 },
-  { 9, OperandInfo245 },
-  { 11, OperandInfo255 },
-  { 9, OperandInfo254 },
-  { 7, OperandInfo244 },
-  { 9, OperandInfo245 },
-  { 11, OperandInfo255 },
-  { 9, OperandInfo254 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 11, OperandInfo255 },
-  { 9, OperandInfo254 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 11, OperandInfo255 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo239 },
-  { 6, OperandInfo240 },
-  { 7, OperandInfo241 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo247 },
-  { 7, OperandInfo248 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo247 },
-  { 7, OperandInfo248 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo246 },
-  { 6, OperandInfo247 },
-  { 7, OperandInfo248 },
-  { 6, OperandInfo237 },
-  { 7, OperandInfo238 },
-  { 7, OperandInfo258 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 9, OperandInfo260 },
-  { 11, OperandInfo261 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 13, OperandInfo262 },
-  { 11, OperandInfo261 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 13, OperandInfo262 },
-  { 11, OperandInfo261 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 13, OperandInfo262 },
-  { 11, OperandInfo261 },
-  { 7, OperandInfo263 },
-  { 9, OperandInfo264 },
-  { 13, OperandInfo262 },
-  { 11, OperandInfo261 },
-  { 7, OperandInfo263 },
-  { 9, OperandInfo264 },
-  { 13, OperandInfo262 },
-  { 7, OperandInfo258 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 9, OperandInfo260 },
-  { 7, OperandInfo258 },
-  { 8, OperandInfo250 },
-  { 9, OperandInfo260 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 7, OperandInfo258 },
-  { 8, OperandInfo250 },
-  { 9, OperandInfo260 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 7, OperandInfo258 },
-  { 8, OperandInfo250 },
-  { 9, OperandInfo260 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo265 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 6, OperandInfo249 },
-  { 6, OperandInfo249 },
-  { 10, OperandInfo266 },
-  { 13, OperandInfo267 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 15, OperandInfo268 },
-  { 13, OperandInfo267 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 15, OperandInfo268 },
-  { 13, OperandInfo267 },
-  { 7, OperandInfo256 },
-  { 9, OperandInfo257 },
-  { 15, OperandInfo268 },
-  { 13, OperandInfo267 },
-  { 7, OperandInfo263 },
-  { 9, OperandInfo264 },
-  { 15, OperandInfo268 },
-  { 13, OperandInfo267 },
-  { 7, OperandInfo263 },
-  { 9, OperandInfo264 },
-  { 15, OperandInfo268 },
-  { 8, OperandInfo265 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 5, OperandInfo246 },
-  { 7, OperandInfo259 },
-  { 10, OperandInfo266 },
-  { 8, OperandInfo265 },
-  { 8, OperandInfo250 },
-  { 10, OperandInfo266 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo265 },
-  { 8, OperandInfo250 },
-  { 10, OperandInfo266 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 8, OperandInfo265 },
-  { 8, OperandInfo250 },
-  { 10, OperandInfo266 },
-  { 6, OperandInfo249 },
-  { 8, OperandInfo250 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo269 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo270 },
-  { 5, OperandInfo271 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo273 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo274 },
-  { 3, OperandInfo274 },
-  { 3, OperandInfo275 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo273 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo274 },
-  { 3, OperandInfo274 },
-  { 3, OperandInfo275 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 7, OperandInfo276 },
-  { 7, OperandInfo277 },
-  { 7, OperandInfo276 },
-  { 7, OperandInfo277 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo235 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 7, OperandInfo278 },
-  { 7, OperandInfo279 },
-  { 7, OperandInfo280 },
-  { 7, OperandInfo281 },
-  { 7, OperandInfo278 },
-  { 7, OperandInfo280 },
-  { 7, OperandInfo279 },
-  { 7, OperandInfo281 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 7, OperandInfo276 },
-  { 7, OperandInfo277 },
-  { 7, OperandInfo276 },
-  { 7, OperandInfo277 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo235 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 7, OperandInfo278 },
-  { 7, OperandInfo279 },
-  { 7, OperandInfo280 },
-  { 7, OperandInfo281 },
-  { 7, OperandInfo278 },
-  { 7, OperandInfo280 },
-  { 7, OperandInfo279 },
-  { 7, OperandInfo281 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo194 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo282 },
-  { 2, OperandInfo222 },
-  { 4, OperandInfo283 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo228 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo284 },
-  { 5, OperandInfo285 },
-  { 6, OperandInfo286 },
-  { 4, OperandInfo287 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo288 },
-  { 6, OperandInfo289 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo129 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo163 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo201 },
-  { 3, OperandInfo291 },
-  { 5, OperandInfo195 },
-  { 6, OperandInfo292 },
-  { 6, OperandInfo293 },
-  { 6, OperandInfo292 },
-  { 6, OperandInfo293 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo203 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 6, OperandInfo294 },
-  { 6, OperandInfo295 },
-  { 6, OperandInfo296 },
-  { 6, OperandInfo297 },
-  { 6, OperandInfo294 },
-  { 6, OperandInfo296 },
-  { 6, OperandInfo295 },
-  { 6, OperandInfo297 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo129 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo290 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo215 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 6, OperandInfo235 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo234 },
-  { 6, OperandInfo235 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo201 },
-  { 5, OperandInfo203 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo205 },
-  { 5, OperandInfo205 },
-  { 5, OperandInfo206 },
-  { 5, OperandInfo206 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo298 },
-  { 5, OperandInfo79 },
-  { 5, OperandInfo79 },
-  { 5, OperandInfo298 },
-  { 5, OperandInfo298 },
-  { 5, OperandInfo79 },
-  { 5, OperandInfo298 },
-  { 5, OperandInfo79 },
-  { 5, OperandInfo79 },
-  { 5, OperandInfo298 },
-  { 5, OperandInfo298 },
-  { 5, OperandInfo79 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 7, OperandInfo276 },
-  { 7, OperandInfo277 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 7, OperandInfo276 },
-  { 7, OperandInfo277 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo192 },
-  { 6, OperandInfo294 },
-  { 6, OperandInfo296 },
-  { 6, OperandInfo295 },
-  { 6, OperandInfo297 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 6, OperandInfo292 },
-  { 6, OperandInfo293 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo225 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 7, OperandInfo278 },
-  { 7, OperandInfo280 },
-  { 7, OperandInfo279 },
-  { 7, OperandInfo281 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo193 },
-  { 7, OperandInfo278 },
-  { 7, OperandInfo280 },
-  { 7, OperandInfo279 },
-  { 7, OperandInfo281 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo193 },
-  { 6, OperandInfo294 },
-  { 6, OperandInfo296 },
-  { 6, OperandInfo295 },
-  { 6, OperandInfo297 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo222 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo222 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo199 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo199 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo219 },
-  { 2, OperandInfo119 },
-  { 2, OperandInfo119 },
-  { 4, OperandInfo199 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo200 },
-  { 4, OperandInfo200 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 4, OperandInfo304 },
-  { 5, OperandInfo305 },
-  { 4, OperandInfo173 },
-  { 5, OperandInfo306 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo273 },
-  { 3, OperandInfo275 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo273 },
-  { 3, OperandInfo275 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo273 },
-  { 3, OperandInfo275 },
-  { 3, OperandInfo272 },
-  { 3, OperandInfo273 },
-  { 3, OperandInfo275 },
-  { 6, OperandInfo307 },
-  { 6, OperandInfo307 },
-  { 6, OperandInfo307 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo231 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo300 },
-  { 5, OperandInfo301 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo299 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo227 },
-  { 5, OperandInfo226 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 4, OperandInfo224 },
-  { 4, OperandInfo310 },
-  { 4, OperandInfo199 },
-  { 6, OperandInfo311 },
-  { 6, OperandInfo312 },
-  { 6, OperandInfo312 },
-  { 6, OperandInfo311 },
-  { 6, OperandInfo312 },
-  { 6, OperandInfo311 },
-  { 6, OperandInfo311 },
-  { 6, OperandInfo312 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 4, OperandInfo198 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo302 },
-  { 6, OperandInfo303 },
-  { 6, OperandInfo313 },
-  { 8, OperandInfo314 },
-  { 6, OperandInfo313 },
-  { 8, OperandInfo314 },
-  { 6, OperandInfo313 },
-  { 8, OperandInfo314 },
-  { 6, OperandInfo315 },
-  { 8, OperandInfo316 },
-  { 6, OperandInfo315 },
-  { 8, OperandInfo316 },
-  { 6, OperandInfo315 },
-  { 8, OperandInfo316 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo321 },
-  { 7, OperandInfo322 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo321 },
-  { 7, OperandInfo322 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo323 },
-  { 5, OperandInfo324 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 7, OperandInfo325 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 5, OperandInfo324 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 7, OperandInfo325 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 5, OperandInfo324 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 7, OperandInfo325 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 5, OperandInfo324 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 7, OperandInfo325 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 7, OperandInfo328 },
-  { 6, OperandInfo315 },
-  { 8, OperandInfo316 },
-  { 9, OperandInfo329 },
-  { 7, OperandInfo328 },
-  { 6, OperandInfo315 },
-  { 8, OperandInfo316 },
-  { 9, OperandInfo329 },
-  { 7, OperandInfo328 },
-  { 6, OperandInfo315 },
-  { 8, OperandInfo316 },
-  { 9, OperandInfo329 },
-  { 7, OperandInfo328 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 9, OperandInfo329 },
-  { 7, OperandInfo328 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 9, OperandInfo329 },
-  { 5, OperandInfo323 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo323 },
-  { 6, OperandInfo326 },
-  { 7, OperandInfo327 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo321 },
-  { 7, OperandInfo332 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo321 },
-  { 7, OperandInfo332 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 5, OperandInfo317 },
-  { 5, OperandInfo318 },
-  { 6, OperandInfo321 },
-  { 7, OperandInfo332 },
-  { 6, OperandInfo319 },
-  { 7, OperandInfo320 },
-  { 8, OperandInfo333 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 10, OperandInfo334 },
-  { 8, OperandInfo333 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 10, OperandInfo334 },
-  { 8, OperandInfo333 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 10, OperandInfo334 },
-  { 8, OperandInfo333 },
-  { 6, OperandInfo335 },
-  { 8, OperandInfo336 },
-  { 10, OperandInfo334 },
-  { 8, OperandInfo333 },
-  { 6, OperandInfo335 },
-  { 8, OperandInfo336 },
-  { 10, OperandInfo334 },
-  { 7, OperandInfo337 },
-  { 5, OperandInfo318 },
-  { 7, OperandInfo322 },
-  { 9, OperandInfo338 },
-  { 7, OperandInfo337 },
-  { 5, OperandInfo318 },
-  { 7, OperandInfo322 },
-  { 9, OperandInfo338 },
-  { 7, OperandInfo337 },
-  { 5, OperandInfo318 },
-  { 7, OperandInfo322 },
-  { 9, OperandInfo338 },
-  { 7, OperandInfo337 },
-  { 7, OperandInfo325 },
-  { 9, OperandInfo338 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 7, OperandInfo337 },
-  { 7, OperandInfo325 },
-  { 9, OperandInfo338 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 7, OperandInfo337 },
-  { 7, OperandInfo325 },
-  { 9, OperandInfo338 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 9, OperandInfo339 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 11, OperandInfo340 },
-  { 9, OperandInfo339 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 11, OperandInfo340 },
-  { 9, OperandInfo339 },
-  { 6, OperandInfo330 },
-  { 8, OperandInfo331 },
-  { 11, OperandInfo340 },
-  { 9, OperandInfo339 },
-  { 6, OperandInfo335 },
-  { 8, OperandInfo336 },
-  { 11, OperandInfo340 },
-  { 9, OperandInfo339 },
-  { 6, OperandInfo335 },
-  { 8, OperandInfo336 },
-  { 11, OperandInfo340 },
-  { 8, OperandInfo341 },
-  { 5, OperandInfo318 },
-  { 7, OperandInfo322 },
-  { 10, OperandInfo342 },
-  { 8, OperandInfo341 },
-  { 5, OperandInfo318 },
-  { 7, OperandInfo322 },
-  { 10, OperandInfo342 },
-  { 8, OperandInfo341 },
-  { 5, OperandInfo318 },
-  { 7, OperandInfo322 },
-  { 10, OperandInfo342 },
-  { 8, OperandInfo341 },
-  { 7, OperandInfo325 },
-  { 10, OperandInfo342 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 8, OperandInfo341 },
-  { 7, OperandInfo325 },
-  { 10, OperandInfo342 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 8, OperandInfo341 },
-  { 7, OperandInfo325 },
-  { 10, OperandInfo342 },
-  { 5, OperandInfo324 },
-  { 7, OperandInfo325 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo269 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 5, OperandInfo76 },
-  { 5, OperandInfo270 },
-  { 5, OperandInfo271 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo201 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo202 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo195 },
-  { 5, OperandInfo203 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo204 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo344 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo345 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo346 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo346 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo347 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo348 },
-  { 6, OperandInfo194 },
-  { 6, OperandInfo348 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo349 },
-  { 4, OperandInfo199 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo199 },
-  { 4, OperandInfo223 },
-  { 4, OperandInfo349 },
-  { 4, OperandInfo199 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo344 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo196 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo197 },
-  { 5, OperandInfo196 },
-  { 4, OperandInfo304 },
-  { 5, OperandInfo305 },
-  { 4, OperandInfo173 },
-  { 5, OperandInfo306 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 4, OperandInfo224 },
-  { 4, OperandInfo310 },
-  { 4, OperandInfo199 },
-  { 5, OperandInfo308 },
-  { 5, OperandInfo309 },
-  { 5, OperandInfo309 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo343 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo344 },
-  { 6, OperandInfo344 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 6, OperandInfo353 },
-  { 5, OperandInfo354 },
-  { 6, OperandInfo355 },
-  { 7, OperandInfo356 },
-  { 4, OperandInfo357 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 3, OperandInfo107 },
-  { 5, OperandInfo90 },
-  { 6, OperandInfo358 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 3, OperandInfo163 },
-  { 3, OperandInfo107 },
-  { 8, OperandInfo121 },
-  { 8, OperandInfo121 },
-  { 2, OperandInfo105 },
-  { 4, OperandInfo359 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo360 },
-  { 5, OperandInfo361 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo360 },
-  { 5, OperandInfo361 },
-  { 1, OperandInfo2 },
-  { 2, OperandInfo7 },
-  { 3, OperandInfo4 },
-  { 3, OperandInfo362 },
-  { 3, OperandInfo362 },
-  { 3, OperandInfo362 },
-  { 3, OperandInfo362 },
-  { 3, OperandInfo362 },
-  { 3, OperandInfo362 },
-  { 3, OperandInfo128 },
-  { 2, OperandInfo105 },
-  { 2, OperandInfo105 },
-  { 2, OperandInfo105 },
-  { 3, OperandInfo128 },
-  { 3, OperandInfo128 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 3, OperandInfo128 },
-  { 1, OperandInfo2 },
-  { 3, OperandInfo128 },
-  { 2, OperandInfo7 },
-  { 2, OperandInfo363 },
-  { 2, OperandInfo363 },
-  { 4, OperandInfo364 },
-  { 4, OperandInfo364 },
-  { 4, OperandInfo364 },
-  { 4, OperandInfo364 },
-  { 5, OperandInfo365 },
-  { 4, OperandInfo364 },
-  { 4, OperandInfo364 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo139 },
-  { 6, OperandInfo139 },
-  { 5, OperandInfo140 },
-  { 5, OperandInfo140 },
-  { 4, OperandInfo86 },
-  { 6, OperandInfo367 },
-  { 7, OperandInfo368 },
-  { 7, OperandInfo368 },
-  { 6, OperandInfo369 },
-  { 5, OperandInfo370 },
-  { 4, OperandInfo364 },
-  { 5, OperandInfo365 },
-  { 4, OperandInfo364 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo139 },
-  { 6, OperandInfo139 },
-  { 5, OperandInfo140 },
-  { 5, OperandInfo140 },
-  { 4, OperandInfo86 },
-  { 6, OperandInfo367 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo139 },
-  { 6, OperandInfo139 },
-  { 5, OperandInfo140 },
-  { 5, OperandInfo140 },
-  { 4, OperandInfo86 },
-  { 6, OperandInfo367 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo139 },
-  { 6, OperandInfo139 },
-  { 5, OperandInfo140 },
-  { 5, OperandInfo140 },
-  { 4, OperandInfo86 },
-  { 6, OperandInfo367 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo139 },
-  { 6, OperandInfo139 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 4, OperandInfo52 },
-  { 6, OperandInfo371 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 8, OperandInfo148 },
-  { 8, OperandInfo148 },
-  { 7, OperandInfo372 },
-  { 7, OperandInfo372 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 5, OperandInfo90 },
-  { 5, OperandInfo374 },
-  { 4, OperandInfo357 },
-  { 5, OperandInfo375 },
-  { 4, OperandInfo359 },
-  { 4, OperandInfo359 },
-  { 8, OperandInfo159 },
-  { 8, OperandInfo159 },
-  { 7, OperandInfo376 },
-  { 7, OperandInfo376 },
-  { 3, OperandInfo103 },
-  { 4, OperandInfo357 },
-  { 4, OperandInfo357 },
-  { 3, OperandInfo103 },
-  { 4, OperandInfo377 },
-  { 4, OperandInfo377 },
-  { 4, OperandInfo377 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo374 },
-  { 5, OperandInfo379 },
-  { 6, OperandInfo380 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 6, OperandInfo381 },
-  { 6, OperandInfo381 },
-  { 4, OperandInfo382 },
-  { 4, OperandInfo382 },
-  { 5, OperandInfo383 },
-  { 4, OperandInfo382 },
-  { 4, OperandInfo382 },
-  { 3, OperandInfo128 },
-  { 5, OperandInfo383 },
-  { 4, OperandInfo382 },
-  { 4, OperandInfo382 },
-  { 3, OperandInfo128 },
-  { 5, OperandInfo383 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 4, OperandInfo359 },
-  { 4, OperandInfo359 },
-  { 4, OperandInfo359 },
-  { 4, OperandInfo359 },
-  { 3, OperandInfo103 },
-  { 3, OperandInfo103 },
-  { 3, OperandInfo103 },
-  { 3, OperandInfo103 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 5, OperandInfo379 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 6, OperandInfo350 },
-  { 6, OperandInfo351 },
-  { 7, OperandInfo352 },
-  { 6, OperandInfo384 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo33 },
-  { 1, OperandInfo2 },
-  { 2, OperandInfo105 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 3, OperandInfo128 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo373 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 6, OperandInfo373 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 3, OperandInfo128 },
-  { 3, OperandInfo128 },
-  { 3, OperandInfo128 },
-  { 3, OperandInfo128 },
-  { 6, OperandInfo386 },
-  { 5, OperandInfo387 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo137 },
-  { 6, OperandInfo136 },
-  { 6, OperandInfo136 },
-  { 4, OperandInfo364 },
-  { 4, OperandInfo364 },
-  { 5, OperandInfo388 },
-  { 5, OperandInfo388 },
-  { 6, OperandInfo389 },
-  { 5, OperandInfo388 },
-  { 4, OperandInfo364 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 4, OperandInfo132 },
-  { 5, OperandInfo50 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo390 },
-  { 6, OperandInfo390 },
-  { 5, OperandInfo366 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo391 },
-  { 7, OperandInfo392 },
-  { 7, OperandInfo392 },
-  { 6, OperandInfo369 },
-  { 6, OperandInfo393 },
-  { 5, OperandInfo388 },
-  { 6, OperandInfo389 },
-  { 5, OperandInfo388 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo390 },
-  { 6, OperandInfo390 },
-  { 5, OperandInfo366 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo391 },
-  { 5, OperandInfo366 },
-  { 6, OperandInfo394 },
-  { 6, OperandInfo394 },
-  { 5, OperandInfo65 },
-  { 5, OperandInfo65 },
-  { 6, OperandInfo371 },
-  { 3, OperandInfo128 },
-  { 6, OperandInfo353 },
-  { 5, OperandInfo354 },
-  { 6, OperandInfo355 },
-  { 7, OperandInfo356 },
-  { 6, OperandInfo381 },
-  { 6, OperandInfo381 },
-  { 6, OperandInfo381 },
-  { 5, OperandInfo97 },
-  { 5, OperandInfo97 },
-  { 5, OperandInfo97 },
-  { 4, OperandInfo395 },
-  { 4, OperandInfo395 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo360 },
-  { 5, OperandInfo361 },
-  { 3, OperandInfo128 },
-  { 4, OperandInfo86 },
-  { 4, OperandInfo360 },
-  { 5, OperandInfo361 },
-  { 4, OperandInfo396 },
-  { 4, OperandInfo396 },
-  { 4, OperandInfo396 },
-  { 4, OperandInfo396 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 6, OperandInfo384 },
-  { 1, OperandInfo2 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 8, OperandInfo385 },
-  { 8, OperandInfo385 },
-  { 6, OperandInfo373 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 6, OperandInfo373 },
-  { 6, OperandInfo386 },
-  { 5, OperandInfo387 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 5, OperandInfo378 },
-  { 6, OperandInfo381 },
-  { 6, OperandInfo381 },
-  { 6, OperandInfo381 },
-  { 5, OperandInfo97 },
-  { 5, OperandInfo97 },
-  { 5, OperandInfo97 },
-  { 6, OperandInfo397 },
-  { 5, OperandInfo58 },
-  { 6, OperandInfo398 },
-  { 6, OperandInfo399 },
-  { 5, OperandInfo400 },
-  { 5, OperandInfo401 },
-  { 6, OperandInfo402 },
-  { 5, OperandInfo403 },
-  { 5, OperandInfo404 },
-  { 4, OperandInfo405 },
-  { 6, OperandInfo397 },
-  { 6, OperandInfo398 },
-  { 6, OperandInfo397 },
-  { 3, OperandInfo107 },
-  { 6, OperandInfo397 },
-  { 1, OperandInfo2 },
-  { 3, OperandInfo406 },
-  { 3, OperandInfo407 },
-  { 3, OperandInfo406 },
-  { 3, OperandInfo408 },
-  { 3, OperandInfo103 },
-  { 3, OperandInfo103 },
-  { 3, OperandInfo107 },
-  { 2, OperandInfo409 },
-  { 2, OperandInfo409 },
-  { 4, OperandInfo410 },
-  { 4, OperandInfo123 },
-  { 4, OperandInfo108 },
-  { 4, OperandInfo410 },
-  { 2, OperandInfo7 },
-  { 6, OperandInfo397 },
-  { 3, OperandInfo128 },
-  { 1, OperandInfo2 },
-  { 2, OperandInfo31 },
-  { 2, OperandInfo31 },
-  { 2, OperandInfo363 },
-  { 4, OperandInfo411 },
-  { 5, OperandInfo412 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo412 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo412 },
-  { 4, OperandInfo405 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo414 },
-  { 6, OperandInfo398 },
-  { 6, OperandInfo397 },
-  { 6, OperandInfo398 },
-  { 6, OperandInfo397 },
-  { 2, OperandInfo363 },
-  { 5, OperandInfo415 },
-  { 4, OperandInfo123 },
-  { 6, OperandInfo416 },
-  { 5, OperandInfo417 },
-  { 6, OperandInfo397 },
-  { 3, OperandInfo418 },
-  { 3, OperandInfo112 },
-  { 3, OperandInfo112 },
-  { 4, OperandInfo410 },
-  { 4, OperandInfo410 },
-  { 4, OperandInfo410 },
-  { 6, OperandInfo397 },
-  { 5, OperandInfo417 },
-  { 6, OperandInfo397 },
-  { 1, OperandInfo2 },
-  { 5, OperandInfo419 },
-  { 5, OperandInfo412 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo412 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo412 },
-  { 5, OperandInfo413 },
-  { 5, OperandInfo414 },
-  { 6, OperandInfo398 },
-  { 6, OperandInfo399 },
-  { 6, OperandInfo402 },
-  { 5, OperandInfo403 },
-  { 3, OperandInfo128 },
-  { 4, OperandInfo410 },
-  { 4, OperandInfo410 },
-  { 0, nullptr },
-  { 4, OperandInfo410 },
-  { 1, OperandInfo2 },
-  { 4, OperandInfo410 },
-  { 4, OperandInfo410 },
-  { 0, nullptr },
+  { 1, OperandInfo2 },  // Inst #0 = PHI
+  { 0, 0 },  // Inst #1 = INLINEASM
+  { 0, 0 },  // Inst #2 = INLINEASM_BR
+  { 1, OperandInfo3 },  // Inst #3 = CFI_INSTRUCTION
+  { 1, OperandInfo3 },  // Inst #4 = EH_LABEL
+  { 1, OperandInfo3 },  // Inst #5 = GC_LABEL
+  { 1, OperandInfo3 },  // Inst #6 = ANNOTATION_LABEL
+  { 0, 0 },  // Inst #7 = KILL
+  { 3, OperandInfo4 },  // Inst #8 = EXTRACT_SUBREG
+  { 4, OperandInfo5 },  // Inst #9 = INSERT_SUBREG
+  { 1, OperandInfo2 },  // Inst #10 = IMPLICIT_DEF
+  { 4, OperandInfo6 },  // Inst #11 = SUBREG_TO_REG
+  { 3, OperandInfo4 },  // Inst #12 = COPY_TO_REGCLASS
+  { 0, 0 },  // Inst #13 = DBG_VALUE
+  { 0, 0 },  // Inst #14 = DBG_VALUE_LIST
+  { 0, 0 },  // Inst #15 = DBG_INSTR_REF
+  { 0, 0 },  // Inst #16 = DBG_PHI
+  { 1, OperandInfo2 },  // Inst #17 = DBG_LABEL
+  { 2, OperandInfo7 },  // Inst #18 = REG_SEQUENCE
+  { 2, OperandInfo7 },  // Inst #19 = COPY
+  { 0, 0 },  // Inst #20 = BUNDLE
+  { 1, OperandInfo3 },  // Inst #21 = LIFETIME_START
+  { 1, OperandInfo3 },  // Inst #22 = LIFETIME_END
+  { 4, OperandInfo8 },  // Inst #23 = PSEUDO_PROBE
+  { 2, OperandInfo9 },  // Inst #24 = ARITH_FENCE
+  { 2, OperandInfo10 },  // Inst #25 = STACKMAP
+  { 0, 0 },  // Inst #26 = FENTRY_CALL
+  { 6, OperandInfo11 },  // Inst #27 = PATCHPOINT
+  { 1, OperandInfo12 },  // Inst #28 = LOAD_STACK_GUARD
+  { 1, OperandInfo3 },  // Inst #29 = PREALLOCATED_SETUP
+  { 3, OperandInfo13 },  // Inst #30 = PREALLOCATED_ARG
+  { 0, 0 },  // Inst #31 = STATEPOINT
+  { 2, OperandInfo14 },  // Inst #32 = LOCAL_ESCAPE
+  { 1, OperandInfo2 },  // Inst #33 = FAULTING_OP
+  { 0, 0 },  // Inst #34 = PATCHABLE_OP
+  { 0, 0 },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
+  { 0, 0 },  // Inst #36 = PATCHABLE_RET
+  { 0, 0 },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
+  { 0, 0 },  // Inst #38 = PATCHABLE_TAIL_CALL
+  { 2, OperandInfo15 },  // Inst #39 = PATCHABLE_EVENT_CALL
+  { 3, OperandInfo16 },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
+  { 0, 0 },  // Inst #41 = ICALL_BRANCH_FUNNEL
+  { 0, 0 },  // Inst #42 = MEMBARRIER
+  { 3, OperandInfo17 },  // Inst #43 = G_ASSERT_SEXT
+  { 3, OperandInfo17 },  // Inst #44 = G_ASSERT_ZEXT
+  { 3, OperandInfo17 },  // Inst #45 = G_ASSERT_ALIGN
+  { 3, OperandInfo18 },  // Inst #46 = G_ADD
+  { 3, OperandInfo18 },  // Inst #47 = G_SUB
+  { 3, OperandInfo18 },  // Inst #48 = G_MUL
+  { 3, OperandInfo18 },  // Inst #49 = G_SDIV
+  { 3, OperandInfo18 },  // Inst #50 = G_UDIV
+  { 3, OperandInfo18 },  // Inst #51 = G_SREM
+  { 3, OperandInfo18 },  // Inst #52 = G_UREM
+  { 4, OperandInfo19 },  // Inst #53 = G_SDIVREM
+  { 4, OperandInfo19 },  // Inst #54 = G_UDIVREM
+  { 3, OperandInfo18 },  // Inst #55 = G_AND
+  { 3, OperandInfo18 },  // Inst #56 = G_OR
+  { 3, OperandInfo18 },  // Inst #57 = G_XOR
+  { 1, OperandInfo20 },  // Inst #58 = G_IMPLICIT_DEF
+  { 1, OperandInfo20 },  // Inst #59 = G_PHI
+  { 2, OperandInfo21 },  // Inst #60 = G_FRAME_INDEX
+  { 2, OperandInfo21 },  // Inst #61 = G_GLOBAL_VALUE
+  { 3, OperandInfo22 },  // Inst #62 = G_EXTRACT
+  { 2, OperandInfo23 },  // Inst #63 = G_UNMERGE_VALUES
+  { 4, OperandInfo24 },  // Inst #64 = G_INSERT
+  { 2, OperandInfo23 },  // Inst #65 = G_MERGE_VALUES
+  { 2, OperandInfo23 },  // Inst #66 = G_BUILD_VECTOR
+  { 2, OperandInfo23 },  // Inst #67 = G_BUILD_VECTOR_TRUNC
+  { 2, OperandInfo23 },  // Inst #68 = G_CONCAT_VECTORS
+  { 2, OperandInfo23 },  // Inst #69 = G_PTRTOINT
+  { 2, OperandInfo23 },  // Inst #70 = G_INTTOPTR
+  { 2, OperandInfo23 },  // Inst #71 = G_BITCAST
+  { 2, OperandInfo25 },  // Inst #72 = G_FREEZE
+  { 3, OperandInfo26 },  // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND
+  { 2, OperandInfo25 },  // Inst #74 = G_INTRINSIC_TRUNC
+  { 2, OperandInfo25 },  // Inst #75 = G_INTRINSIC_ROUND
+  { 2, OperandInfo23 },  // Inst #76 = G_INTRINSIC_LRINT
+  { 2, OperandInfo25 },  // Inst #77 = G_INTRINSIC_ROUNDEVEN
+  { 1, OperandInfo20 },  // Inst #78 = G_READCYCLECOUNTER
+  { 2, OperandInfo23 },  // Inst #79 = G_LOAD
+  { 2, OperandInfo23 },  // Inst #80 = G_SEXTLOAD
+  { 2, OperandInfo23 },  // Inst #81 = G_ZEXTLOAD
+  { 5, OperandInfo27 },  // Inst #82 = G_INDEXED_LOAD
+  { 5, OperandInfo27 },  // Inst #83 = G_INDEXED_SEXTLOAD
+  { 5, OperandInfo27 },  // Inst #84 = G_INDEXED_ZEXTLOAD
+  { 2, OperandInfo23 },  // Inst #85 = G_STORE
+  { 5, OperandInfo28 },  // Inst #86 = G_INDEXED_STORE
+  { 5, OperandInfo29 },  // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
+  { 4, OperandInfo30 },  // Inst #88 = G_ATOMIC_CMPXCHG
+  { 3, OperandInfo31 },  // Inst #89 = G_ATOMICRMW_XCHG
+  { 3, OperandInfo31 },  // Inst #90 = G_ATOMICRMW_ADD
+  { 3, OperandInfo31 },  // Inst #91 = G_ATOMICRMW_SUB
+  { 3, OperandInfo31 },  // Inst #92 = G_ATOMICRMW_AND
+  { 3, OperandInfo31 },  // Inst #93 = G_ATOMICRMW_NAND
+  { 3, OperandInfo31 },  // Inst #94 = G_ATOMICRMW_OR
+  { 3, OperandInfo31 },  // Inst #95 = G_ATOMICRMW_XOR
+  { 3, OperandInfo31 },  // Inst #96 = G_ATOMICRMW_MAX
+  { 3, OperandInfo31 },  // Inst #97 = G_ATOMICRMW_MIN
+  { 3, OperandInfo31 },  // Inst #98 = G_ATOMICRMW_UMAX
+  { 3, OperandInfo31 },  // Inst #99 = G_ATOMICRMW_UMIN
+  { 3, OperandInfo31 },  // Inst #100 = G_ATOMICRMW_FADD
+  { 3, OperandInfo31 },  // Inst #101 = G_ATOMICRMW_FSUB
+  { 3, OperandInfo31 },  // Inst #102 = G_ATOMICRMW_FMAX
+  { 3, OperandInfo31 },  // Inst #103 = G_ATOMICRMW_FMIN
+  { 3, OperandInfo31 },  // Inst #104 = G_ATOMICRMW_UINC_WRAP
+  { 3, OperandInfo31 },  // Inst #105 = G_ATOMICRMW_UDEC_WRAP
+  { 2, OperandInfo10 },  // Inst #106 = G_FENCE
+  { 2, OperandInfo21 },  // Inst #107 = G_BRCOND
+  { 1, OperandInfo20 },  // Inst #108 = G_BRINDIRECT
+  { 0, 0 },  // Inst #109 = G_INVOKE_REGION_START
+  { 1, OperandInfo2 },  // Inst #110 = G_INTRINSIC
+  { 1, OperandInfo2 },  // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS
+  { 2, OperandInfo23 },  // Inst #112 = G_ANYEXT
+  { 2, OperandInfo23 },  // Inst #113 = G_TRUNC
+  { 2, OperandInfo21 },  // Inst #114 = G_CONSTANT
+  { 2, OperandInfo21 },  // Inst #115 = G_FCONSTANT
+  { 1, OperandInfo20 },  // Inst #116 = G_VASTART
+  { 3, OperandInfo32 },  // Inst #117 = G_VAARG
+  { 2, OperandInfo23 },  // Inst #118 = G_SEXT
+  { 3, OperandInfo17 },  // Inst #119 = G_SEXT_INREG
+  { 2, OperandInfo23 },  // Inst #120 = G_ZEXT
+  { 3, OperandInfo33 },  // Inst #121 = G_SHL
+  { 3, OperandInfo33 },  // Inst #122 = G_LSHR
+  { 3, OperandInfo33 },  // Inst #123 = G_ASHR
+  { 4, OperandInfo34 },  // Inst #124 = G_FSHL
+  { 4, OperandInfo34 },  // Inst #125 = G_FSHR
+  { 3, OperandInfo33 },  // Inst #126 = G_ROTR
+  { 3, OperandInfo33 },  // Inst #127 = G_ROTL
+  { 4, OperandInfo35 },  // Inst #128 = G_ICMP
+  { 4, OperandInfo35 },  // Inst #129 = G_FCMP
+  { 4, OperandInfo30 },  // Inst #130 = G_SELECT
+  { 4, OperandInfo30 },  // Inst #131 = G_UADDO
+  { 5, OperandInfo36 },  // Inst #132 = G_UADDE
+  { 4, OperandInfo30 },  // Inst #133 = G_USUBO
+  { 5, OperandInfo36 },  // Inst #134 = G_USUBE
+  { 4, OperandInfo30 },  // Inst #135 = G_SADDO
+  { 5, OperandInfo36 },  // Inst #136 = G_SADDE
+  { 4, OperandInfo30 },  // Inst #137 = G_SSUBO
+  { 5, OperandInfo36 },  // Inst #138 = G_SSUBE
+  { 4, OperandInfo30 },  // Inst #139 = G_UMULO
+  { 4, OperandInfo30 },  // Inst #140 = G_SMULO
+  { 3, OperandInfo18 },  // Inst #141 = G_UMULH
+  { 3, OperandInfo18 },  // Inst #142 = G_SMULH
+  { 3, OperandInfo18 },  // Inst #143 = G_UADDSAT
+  { 3, OperandInfo18 },  // Inst #144 = G_SADDSAT
+  { 3, OperandInfo18 },  // Inst #145 = G_USUBSAT
+  { 3, OperandInfo18 },  // Inst #146 = G_SSUBSAT
+  { 3, OperandInfo33 },  // Inst #147 = G_USHLSAT
+  { 3, OperandInfo33 },  // Inst #148 = G_SSHLSAT
+  { 4, OperandInfo37 },  // Inst #149 = G_SMULFIX
+  { 4, OperandInfo37 },  // Inst #150 = G_UMULFIX
+  { 4, OperandInfo37 },  // Inst #151 = G_SMULFIXSAT
+  { 4, OperandInfo37 },  // Inst #152 = G_UMULFIXSAT
+  { 4, OperandInfo37 },  // Inst #153 = G_SDIVFIX
+  { 4, OperandInfo37 },  // Inst #154 = G_UDIVFIX
+  { 4, OperandInfo37 },  // Inst #155 = G_SDIVFIXSAT
+  { 4, OperandInfo37 },  // Inst #156 = G_UDIVFIXSAT
+  { 3, OperandInfo18 },  // Inst #157 = G_FADD
+  { 3, OperandInfo18 },  // Inst #158 = G_FSUB
+  { 3, OperandInfo18 },  // Inst #159 = G_FMUL
+  { 4, OperandInfo19 },  // Inst #160 = G_FMA
+  { 4, OperandInfo19 },  // Inst #161 = G_FMAD
+  { 3, OperandInfo18 },  // Inst #162 = G_FDIV
+  { 3, OperandInfo18 },  // Inst #163 = G_FREM
+  { 3, OperandInfo18 },  // Inst #164 = G_FPOW
+  { 3, OperandInfo33 },  // Inst #165 = G_FPOWI
+  { 2, OperandInfo25 },  // Inst #166 = G_FEXP
+  { 2, OperandInfo25 },  // Inst #167 = G_FEXP2
+  { 2, OperandInfo25 },  // Inst #168 = G_FLOG
+  { 2, OperandInfo25 },  // Inst #169 = G_FLOG2
+  { 2, OperandInfo25 },  // Inst #170 = G_FLOG10
+  { 2, OperandInfo25 },  // Inst #171 = G_FNEG
+  { 2, OperandInfo23 },  // Inst #172 = G_FPEXT
+  { 2, OperandInfo23 },  // Inst #173 = G_FPTRUNC
+  { 2, OperandInfo23 },  // Inst #174 = G_FPTOSI
+  { 2, OperandInfo23 },  // Inst #175 = G_FPTOUI
+  { 2, OperandInfo23 },  // Inst #176 = G_SITOFP
+  { 2, OperandInfo23 },  // Inst #177 = G_UITOFP
+  { 2, OperandInfo25 },  // Inst #178 = G_FABS
+  { 3, OperandInfo33 },  // Inst #179 = G_FCOPYSIGN
+  { 3, OperandInfo32 },  // Inst #180 = G_IS_FPCLASS
+  { 2, OperandInfo25 },  // Inst #181 = G_FCANONICALIZE
+  { 3, OperandInfo18 },  // Inst #182 = G_FMINNUM
+  { 3, OperandInfo18 },  // Inst #183 = G_FMAXNUM
+  { 3, OperandInfo18 },  // Inst #184 = G_FMINNUM_IEEE
+  { 3, OperandInfo18 },  // Inst #185 = G_FMAXNUM_IEEE
+  { 3, OperandInfo18 },  // Inst #186 = G_FMINIMUM
+  { 3, OperandInfo18 },  // Inst #187 = G_FMAXIMUM
+  { 3, OperandInfo33 },  // Inst #188 = G_PTR_ADD
+  { 3, OperandInfo33 },  // Inst #189 = G_PTRMASK
+  { 3, OperandInfo18 },  // Inst #190 = G_SMIN
+  { 3, OperandInfo18 },  // Inst #191 = G_SMAX
+  { 3, OperandInfo18 },  // Inst #192 = G_UMIN
+  { 3, OperandInfo18 },  // Inst #193 = G_UMAX
+  { 2, OperandInfo25 },  // Inst #194 = G_ABS
+  { 2, OperandInfo23 },  // Inst #195 = G_LROUND
+  { 2, OperandInfo23 },  // Inst #196 = G_LLROUND
+  { 1, OperandInfo2 },  // Inst #197 = G_BR
+  { 3, OperandInfo38 },  // Inst #198 = G_BRJT
+  { 4, OperandInfo39 },  // Inst #199 = G_INSERT_VECTOR_ELT
+  { 3, OperandInfo40 },  // Inst #200 = G_EXTRACT_VECTOR_ELT
+  { 4, OperandInfo41 },  // Inst #201 = G_SHUFFLE_VECTOR
+  { 2, OperandInfo23 },  // Inst #202 = G_CTTZ
+  { 2, OperandInfo23 },  // Inst #203 = G_CTTZ_ZERO_UNDEF
+  { 2, OperandInfo23 },  // Inst #204 = G_CTLZ
+  { 2, OperandInfo23 },  // Inst #205 = G_CTLZ_ZERO_UNDEF
+  { 2, OperandInfo23 },  // Inst #206 = G_CTPOP
+  { 2, OperandInfo25 },  // Inst #207 = G_BSWAP
+  { 2, OperandInfo25 },  // Inst #208 = G_BITREVERSE
+  { 2, OperandInfo25 },  // Inst #209 = G_FCEIL
+  { 2, OperandInfo25 },  // Inst #210 = G_FCOS
+  { 2, OperandInfo25 },  // Inst #211 = G_FSIN
+  { 2, OperandInfo25 },  // Inst #212 = G_FSQRT
+  { 2, OperandInfo25 },  // Inst #213 = G_FFLOOR
+  { 2, OperandInfo25 },  // Inst #214 = G_FRINT
+  { 2, OperandInfo25 },  // Inst #215 = G_FNEARBYINT
+  { 2, OperandInfo23 },  // Inst #216 = G_ADDRSPACE_CAST
+  { 2, OperandInfo21 },  // Inst #217 = G_BLOCK_ADDR
+  { 2, OperandInfo21 },  // Inst #218 = G_JUMP_TABLE
+  { 3, OperandInfo26 },  // Inst #219 = G_DYN_STACKALLOC
+  { 3, OperandInfo18 },  // Inst #220 = G_STRICT_FADD
+  { 3, OperandInfo18 },  // Inst #221 = G_STRICT_FSUB
+  { 3, OperandInfo18 },  // Inst #222 = G_STRICT_FMUL
+  { 3, OperandInfo18 },  // Inst #223 = G_STRICT_FDIV
+  { 3, OperandInfo18 },  // Inst #224 = G_STRICT_FREM
+  { 4, OperandInfo19 },  // Inst #225 = G_STRICT_FMA
+  { 2, OperandInfo25 },  // Inst #226 = G_STRICT_FSQRT
+  { 2, OperandInfo21 },  // Inst #227 = G_READ_REGISTER
+  { 2, OperandInfo42 },  // Inst #228 = G_WRITE_REGISTER
+  { 4, OperandInfo43 },  // Inst #229 = G_MEMCPY
+  { 3, OperandInfo40 },  // Inst #230 = G_MEMCPY_INLINE
+  { 4, OperandInfo43 },  // Inst #231 = G_MEMMOVE
+  { 4, OperandInfo43 },  // Inst #232 = G_MEMSET
+  { 3, OperandInfo22 },  // Inst #233 = G_BZERO
+  { 3, OperandInfo40 },  // Inst #234 = G_VECREDUCE_SEQ_FADD
+  { 3, OperandInfo40 },  // Inst #235 = G_VECREDUCE_SEQ_FMUL
+  { 2, OperandInfo23 },  // Inst #236 = G_VECREDUCE_FADD
+  { 2, OperandInfo23 },  // Inst #237 = G_VECREDUCE_FMUL
+  { 2, OperandInfo23 },  // Inst #238 = G_VECREDUCE_FMAX
+  { 2, OperandInfo23 },  // Inst #239 = G_VECREDUCE_FMIN
+  { 2, OperandInfo23 },  // Inst #240 = G_VECREDUCE_ADD
+  { 2, OperandInfo23 },  // Inst #241 = G_VECREDUCE_MUL
+  { 2, OperandInfo23 },  // Inst #242 = G_VECREDUCE_AND
+  { 2, OperandInfo23 },  // Inst #243 = G_VECREDUCE_OR
+  { 2, OperandInfo23 },  // Inst #244 = G_VECREDUCE_XOR
+  { 2, OperandInfo23 },  // Inst #245 = G_VECREDUCE_SMAX
+  { 2, OperandInfo23 },  // Inst #246 = G_VECREDUCE_SMIN
+  { 2, OperandInfo23 },  // Inst #247 = G_VECREDUCE_UMAX
+  { 2, OperandInfo23 },  // Inst #248 = G_VECREDUCE_UMIN
+  { 4, OperandInfo44 },  // Inst #249 = G_SBFX
+  { 4, OperandInfo44 },  // Inst #250 = G_UBFX
+  { 2, OperandInfo45 },  // Inst #251 = ABS
+  { 5, OperandInfo46 },  // Inst #252 = ADDSri
+  { 5, OperandInfo47 },  // Inst #253 = ADDSrr
+  { 6, OperandInfo48 },  // Inst #254 = ADDSrsi
+  { 7, OperandInfo49 },  // Inst #255 = ADDSrsr
+  { 4, OperandInfo50 },  // Inst #256 = ADJCALLSTACKDOWN
+  { 4, OperandInfo50 },  // Inst #257 = ADJCALLSTACKUP
+  { 6, OperandInfo51 },  // Inst #258 = ASRi
+  { 6, OperandInfo52 },  // Inst #259 = ASRr
+  { 1, OperandInfo53 },  // Inst #260 = B
+  { 4, OperandInfo54 },  // Inst #261 = BCCZi64
+  { 6, OperandInfo55 },  // Inst #262 = BCCi64
+  { 1, OperandInfo56 },  // Inst #263 = BLX_noip
+  { 1, OperandInfo56 },  // Inst #264 = BLX_pred_noip
+  { 2, OperandInfo57 },  // Inst #265 = BL_PUSHLR
+  { 1, OperandInfo53 },  // Inst #266 = BMOVPCB_CALL
+  { 1, OperandInfo58 },  // Inst #267 = BMOVPCRX_CALL
+  { 3, OperandInfo59 },  // Inst #268 = BR_JTadd
+  { 3, OperandInfo60 },  // Inst #269 = BR_JTm_i12
+  { 4, OperandInfo61 },  // Inst #270 = BR_JTm_rs
+  { 2, OperandInfo62 },  // Inst #271 = BR_JTr
+  { 1, OperandInfo58 },  // Inst #272 = BX_CALL
+  { 5, OperandInfo63 },  // Inst #273 = CMP_SWAP_16
+  { 5, OperandInfo63 },  // Inst #274 = CMP_SWAP_32
+  { 5, OperandInfo64 },  // Inst #275 = CMP_SWAP_64
+  { 5, OperandInfo63 },  // Inst #276 = CMP_SWAP_8
+  { 3, OperandInfo4 },  // Inst #277 = CONSTPOOL_ENTRY
+  { 4, OperandInfo65 },  // Inst #278 = COPY_STRUCT_BYVAL_I32
+  { 2, OperandInfo7 },  // Inst #279 = ITasm
+  { 0, 0 },  // Inst #280 = Int_eh_sjlj_dispatchsetup
+  { 2, OperandInfo45 },  // Inst #281 = Int_eh_sjlj_longjmp
+  { 2, OperandInfo45 },  // Inst #282 = Int_eh_sjlj_setjmp
+  { 2, OperandInfo45 },  // Inst #283 = Int_eh_sjlj_setjmp_nofp
+  { 0, 0 },  // Inst #284 = Int_eh_sjlj_setup_dispatch
+  { 3, OperandInfo4 },  // Inst #285 = JUMPTABLE_ADDRS
+  { 3, OperandInfo4 },  // Inst #286 = JUMPTABLE_INSTS
+  { 3, OperandInfo4 },  // Inst #287 = JUMPTABLE_TBB
+  { 3, OperandInfo4 },  // Inst #288 = JUMPTABLE_TBH
+  { 5, OperandInfo66 },  // Inst #289 = LDMIA_RET
+  { 4, OperandInfo67 },  // Inst #290 = LDRBT_POST
+  { 4, OperandInfo68 },  // Inst #291 = LDRConstPool
+  { 4, OperandInfo67 },  // Inst #292 = LDRHTii
+  { 2, OperandInfo62 },  // Inst #293 = LDRLIT_ga_abs
+  { 2, OperandInfo62 },  // Inst #294 = LDRLIT_ga_pcrel
+  { 2, OperandInfo62 },  // Inst #295 = LDRLIT_ga_pcrel_ldr
+  { 4, OperandInfo67 },  // Inst #296 = LDRSBTii
+  { 4, OperandInfo67 },  // Inst #297 = LDRSHTii
+  { 4, OperandInfo67 },  // Inst #298 = LDRT_POST
+  { 4, OperandInfo69 },  // Inst #299 = LEApcrel
+  { 4, OperandInfo69 },  // Inst #300 = LEApcrelJT
+  { 4, OperandInfo70 },  // Inst #301 = LOADDUAL
+  { 6, OperandInfo51 },  // Inst #302 = LSLi
+  { 6, OperandInfo52 },  // Inst #303 = LSLr
+  { 6, OperandInfo51 },  // Inst #304 = LSRi
+  { 6, OperandInfo52 },  // Inst #305 = LSRr
+  { 5, OperandInfo71 },  // Inst #306 = MEMCPY
+  { 7, OperandInfo72 },  // Inst #307 = MLAv5
+  { 5, OperandInfo73 },  // Inst #308 = MOVCCi
+  { 5, OperandInfo73 },  // Inst #309 = MOVCCi16
+  { 5, OperandInfo74 },  // Inst #310 = MOVCCi32imm
+  { 5, OperandInfo75 },  // Inst #311 = MOVCCr
+  { 6, OperandInfo76 },  // Inst #312 = MOVCCsi
+  { 7, OperandInfo77 },  // Inst #313 = MOVCCsr
+  { 1, OperandInfo78 },  // Inst #314 = MOVPCRX
+  { 4, OperandInfo79 },  // Inst #315 = MOVTi16_ga_pcrel
+  { 2, OperandInfo62 },  // Inst #316 = MOV_ga_pcrel
+  { 2, OperandInfo62 },  // Inst #317 = MOV_ga_pcrel_ldr
+  { 3, OperandInfo80 },  // Inst #318 = MOVi16_ga_pcrel
+  { 2, OperandInfo62 },  // Inst #319 = MOVi32imm
+  { 2, OperandInfo45 },  // Inst #320 = MOVsra_flag
+  { 2, OperandInfo45 },  // Inst #321 = MOVsrl_flag
+  { 2, OperandInfo81 },  // Inst #322 = MQPRCopy
+  { 2, OperandInfo82 },  // Inst #323 = MQQPRLoad
+  { 2, OperandInfo82 },  // Inst #324 = MQQPRStore
+  { 2, OperandInfo83 },  // Inst #325 = MQQQQPRLoad
+  { 2, OperandInfo83 },  // Inst #326 = MQQQQPRStore
+  { 6, OperandInfo84 },  // Inst #327 = MULv5
+  { 3, OperandInfo85 },  // Inst #328 = MVE_MEMCPYLOOPINST
+  { 3, OperandInfo86 },  // Inst #329 = MVE_MEMSETLOOPINST
+  { 5, OperandInfo73 },  // Inst #330 = MVNCCi
+  { 5, OperandInfo46 },  // Inst #331 = PICADD
+  { 5, OperandInfo87 },  // Inst #332 = PICLDR
+  { 5, OperandInfo87 },  // Inst #333 = PICLDRB
+  { 5, OperandInfo87 },  // Inst #334 = PICLDRH
+  { 5, OperandInfo87 },  // Inst #335 = PICLDRSB
+  { 5, OperandInfo87 },  // Inst #336 = PICLDRSH
+  { 5, OperandInfo87 },  // Inst #337 = PICSTR
+  { 5, OperandInfo87 },  // Inst #338 = PICSTRB
+  { 5, OperandInfo87 },  // Inst #339 = PICSTRH
+  { 6, OperandInfo51 },  // Inst #340 = RORi
+  { 6, OperandInfo52 },  // Inst #341 = RORr
+  { 2, OperandInfo45 },  // Inst #342 = RRX
+  { 5, OperandInfo88 },  // Inst #343 = RRXi
+  { 5, OperandInfo46 },  // Inst #344 = RSBSri
+  { 6, OperandInfo48 },  // Inst #345 = RSBSrsi
+  { 7, OperandInfo49 },  // Inst #346 = RSBSrsr
+  { 0, 0 },  // Inst #347 = SEH_EpilogEnd
+  { 0, 0 },  // Inst #348 = SEH_EpilogStart
+  { 1, OperandInfo3 },  // Inst #349 = SEH_Nop
+  { 1, OperandInfo3 },  // Inst #350 = SEH_Nop_Ret
+  { 0, 0 },  // Inst #351 = SEH_PrologEnd
+  { 2, OperandInfo10 },  // Inst #352 = SEH_SaveFRegs
+  { 1, OperandInfo3 },  // Inst #353 = SEH_SaveLR
+  { 2, OperandInfo10 },  // Inst #354 = SEH_SaveRegs
+  { 2, OperandInfo10 },  // Inst #355 = SEH_SaveRegs_Ret
+  { 1, OperandInfo3 },  // Inst #356 = SEH_SaveSP
+  { 2, OperandInfo10 },  // Inst #357 = SEH_StackAlloc
+  { 9, OperandInfo89 },  // Inst #358 = SMLALv5
+  { 7, OperandInfo90 },  // Inst #359 = SMULLv5
+  { 3, OperandInfo91 },  // Inst #360 = SPACE
+  { 4, OperandInfo70 },  // Inst #361 = STOREDUAL
+  { 4, OperandInfo67 },  // Inst #362 = STRBT_POST
+  { 7, OperandInfo92 },  // Inst #363 = STRBi_preidx
+  { 7, OperandInfo92 },  // Inst #364 = STRBr_preidx
+  { 7, OperandInfo93 },  // Inst #365 = STRH_preidx
+  { 4, OperandInfo67 },  // Inst #366 = STRT_POST
+  { 7, OperandInfo92 },  // Inst #367 = STRi_preidx
+  { 7, OperandInfo92 },  // Inst #368 = STRr_preidx
+  { 3, OperandInfo94 },  // Inst #369 = SUBS_PC_LR
+  { 5, OperandInfo46 },  // Inst #370 = SUBSri
+  { 5, OperandInfo47 },  // Inst #371 = SUBSrr
+  { 6, OperandInfo48 },  // Inst #372 = SUBSrsi
+  { 7, OperandInfo49 },  // Inst #373 = SUBSrsr
+  { 0, 0 },  // Inst #374 = SpeculationBarrierISBDSBEndBB
+  { 0, 0 },  // Inst #375 = SpeculationBarrierSBEndBB
+  { 1, OperandInfo53 },  // Inst #376 = TAILJMPd
+  { 1, OperandInfo95 },  // Inst #377 = TAILJMPr
+  { 1, OperandInfo78 },  // Inst #378 = TAILJMPr4
+  { 2, OperandInfo10 },  // Inst #379 = TCRETURNdi
+  { 2, OperandInfo96 },  // Inst #380 = TCRETURNri
+  { 0, 0 },  // Inst #381 = TPsoft
+  { 9, OperandInfo89 },  // Inst #382 = UMLALv5
+  { 7, OperandInfo90 },  // Inst #383 = UMULLv5
+  { 6, OperandInfo97 },  // Inst #384 = VLD1LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #385 = VLD1LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #386 = VLD1LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #387 = VLD1LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #388 = VLD1LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #389 = VLD1LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #390 = VLD1LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #391 = VLD1LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #392 = VLD1LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #393 = VLD2LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #394 = VLD2LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #395 = VLD2LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #396 = VLD2LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #397 = VLD2LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #398 = VLD2LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #399 = VLD2LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #400 = VLD2LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #401 = VLD2LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #402 = VLD2LNqAsm_16
+  { 6, OperandInfo97 },  // Inst #403 = VLD2LNqAsm_32
+  { 6, OperandInfo97 },  // Inst #404 = VLD2LNqWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #405 = VLD2LNqWB_fixed_Asm_32
+  { 7, OperandInfo98 },  // Inst #406 = VLD2LNqWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #407 = VLD2LNqWB_register_Asm_32
+  { 5, OperandInfo99 },  // Inst #408 = VLD3DUPdAsm_16
+  { 5, OperandInfo99 },  // Inst #409 = VLD3DUPdAsm_32
+  { 5, OperandInfo99 },  // Inst #410 = VLD3DUPdAsm_8
+  { 5, OperandInfo99 },  // Inst #411 = VLD3DUPdWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #412 = VLD3DUPdWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #413 = VLD3DUPdWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #414 = VLD3DUPdWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #415 = VLD3DUPdWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #416 = VLD3DUPdWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #417 = VLD3DUPqAsm_16
+  { 5, OperandInfo99 },  // Inst #418 = VLD3DUPqAsm_32
+  { 5, OperandInfo99 },  // Inst #419 = VLD3DUPqAsm_8
+  { 5, OperandInfo99 },  // Inst #420 = VLD3DUPqWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #421 = VLD3DUPqWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #422 = VLD3DUPqWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #423 = VLD3DUPqWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #424 = VLD3DUPqWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #425 = VLD3DUPqWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #426 = VLD3LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #427 = VLD3LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #428 = VLD3LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #429 = VLD3LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #430 = VLD3LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #431 = VLD3LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #432 = VLD3LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #433 = VLD3LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #434 = VLD3LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #435 = VLD3LNqAsm_16
+  { 6, OperandInfo97 },  // Inst #436 = VLD3LNqAsm_32
+  { 6, OperandInfo97 },  // Inst #437 = VLD3LNqWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #438 = VLD3LNqWB_fixed_Asm_32
+  { 7, OperandInfo98 },  // Inst #439 = VLD3LNqWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #440 = VLD3LNqWB_register_Asm_32
+  { 5, OperandInfo99 },  // Inst #441 = VLD3dAsm_16
+  { 5, OperandInfo99 },  // Inst #442 = VLD3dAsm_32
+  { 5, OperandInfo99 },  // Inst #443 = VLD3dAsm_8
+  { 5, OperandInfo99 },  // Inst #444 = VLD3dWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #445 = VLD3dWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #446 = VLD3dWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #447 = VLD3dWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #448 = VLD3dWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #449 = VLD3dWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #450 = VLD3qAsm_16
+  { 5, OperandInfo99 },  // Inst #451 = VLD3qAsm_32
+  { 5, OperandInfo99 },  // Inst #452 = VLD3qAsm_8
+  { 5, OperandInfo99 },  // Inst #453 = VLD3qWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #454 = VLD3qWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #455 = VLD3qWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #456 = VLD3qWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #457 = VLD3qWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #458 = VLD3qWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #459 = VLD4DUPdAsm_16
+  { 5, OperandInfo99 },  // Inst #460 = VLD4DUPdAsm_32
+  { 5, OperandInfo99 },  // Inst #461 = VLD4DUPdAsm_8
+  { 5, OperandInfo99 },  // Inst #462 = VLD4DUPdWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #463 = VLD4DUPdWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #464 = VLD4DUPdWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #465 = VLD4DUPdWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #466 = VLD4DUPdWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #467 = VLD4DUPdWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #468 = VLD4DUPqAsm_16
+  { 5, OperandInfo99 },  // Inst #469 = VLD4DUPqAsm_32
+  { 5, OperandInfo99 },  // Inst #470 = VLD4DUPqAsm_8
+  { 5, OperandInfo99 },  // Inst #471 = VLD4DUPqWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #472 = VLD4DUPqWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #473 = VLD4DUPqWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #474 = VLD4DUPqWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #475 = VLD4DUPqWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #476 = VLD4DUPqWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #477 = VLD4LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #478 = VLD4LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #479 = VLD4LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #480 = VLD4LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #481 = VLD4LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #482 = VLD4LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #483 = VLD4LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #484 = VLD4LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #485 = VLD4LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #486 = VLD4LNqAsm_16
+  { 6, OperandInfo97 },  // Inst #487 = VLD4LNqAsm_32
+  { 6, OperandInfo97 },  // Inst #488 = VLD4LNqWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #489 = VLD4LNqWB_fixed_Asm_32
+  { 7, OperandInfo98 },  // Inst #490 = VLD4LNqWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #491 = VLD4LNqWB_register_Asm_32
+  { 5, OperandInfo99 },  // Inst #492 = VLD4dAsm_16
+  { 5, OperandInfo99 },  // Inst #493 = VLD4dAsm_32
+  { 5, OperandInfo99 },  // Inst #494 = VLD4dAsm_8
+  { 5, OperandInfo99 },  // Inst #495 = VLD4dWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #496 = VLD4dWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #497 = VLD4dWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #498 = VLD4dWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #499 = VLD4dWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #500 = VLD4dWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #501 = VLD4qAsm_16
+  { 5, OperandInfo99 },  // Inst #502 = VLD4qAsm_32
+  { 5, OperandInfo99 },  // Inst #503 = VLD4qAsm_8
+  { 5, OperandInfo99 },  // Inst #504 = VLD4qWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #505 = VLD4qWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #506 = VLD4qWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #507 = VLD4qWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #508 = VLD4qWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #509 = VLD4qWB_register_Asm_8
+  { 1, OperandInfo101 },  // Inst #510 = VMOVD0
+  { 5, OperandInfo102 },  // Inst #511 = VMOVDcc
+  { 5, OperandInfo103 },  // Inst #512 = VMOVHcc
+  { 1, OperandInfo104 },  // Inst #513 = VMOVQ0
+  { 5, OperandInfo105 },  // Inst #514 = VMOVScc
+  { 6, OperandInfo97 },  // Inst #515 = VST1LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #516 = VST1LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #517 = VST1LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #518 = VST1LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #519 = VST1LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #520 = VST1LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #521 = VST1LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #522 = VST1LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #523 = VST1LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #524 = VST2LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #525 = VST2LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #526 = VST2LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #527 = VST2LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #528 = VST2LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #529 = VST2LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #530 = VST2LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #531 = VST2LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #532 = VST2LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #533 = VST2LNqAsm_16
+  { 6, OperandInfo97 },  // Inst #534 = VST2LNqAsm_32
+  { 6, OperandInfo97 },  // Inst #535 = VST2LNqWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #536 = VST2LNqWB_fixed_Asm_32
+  { 7, OperandInfo98 },  // Inst #537 = VST2LNqWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #538 = VST2LNqWB_register_Asm_32
+  { 6, OperandInfo97 },  // Inst #539 = VST3LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #540 = VST3LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #541 = VST3LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #542 = VST3LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #543 = VST3LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #544 = VST3LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #545 = VST3LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #546 = VST3LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #547 = VST3LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #548 = VST3LNqAsm_16
+  { 6, OperandInfo97 },  // Inst #549 = VST3LNqAsm_32
+  { 6, OperandInfo97 },  // Inst #550 = VST3LNqWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #551 = VST3LNqWB_fixed_Asm_32
+  { 7, OperandInfo98 },  // Inst #552 = VST3LNqWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #553 = VST3LNqWB_register_Asm_32
+  { 5, OperandInfo99 },  // Inst #554 = VST3dAsm_16
+  { 5, OperandInfo99 },  // Inst #555 = VST3dAsm_32
+  { 5, OperandInfo99 },  // Inst #556 = VST3dAsm_8
+  { 5, OperandInfo99 },  // Inst #557 = VST3dWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #558 = VST3dWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #559 = VST3dWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #560 = VST3dWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #561 = VST3dWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #562 = VST3dWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #563 = VST3qAsm_16
+  { 5, OperandInfo99 },  // Inst #564 = VST3qAsm_32
+  { 5, OperandInfo99 },  // Inst #565 = VST3qAsm_8
+  { 5, OperandInfo99 },  // Inst #566 = VST3qWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #567 = VST3qWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #568 = VST3qWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #569 = VST3qWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #570 = VST3qWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #571 = VST3qWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #572 = VST4LNdAsm_16
+  { 6, OperandInfo97 },  // Inst #573 = VST4LNdAsm_32
+  { 6, OperandInfo97 },  // Inst #574 = VST4LNdAsm_8
+  { 6, OperandInfo97 },  // Inst #575 = VST4LNdWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #576 = VST4LNdWB_fixed_Asm_32
+  { 6, OperandInfo97 },  // Inst #577 = VST4LNdWB_fixed_Asm_8
+  { 7, OperandInfo98 },  // Inst #578 = VST4LNdWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #579 = VST4LNdWB_register_Asm_32
+  { 7, OperandInfo98 },  // Inst #580 = VST4LNdWB_register_Asm_8
+  { 6, OperandInfo97 },  // Inst #581 = VST4LNqAsm_16
+  { 6, OperandInfo97 },  // Inst #582 = VST4LNqAsm_32
+  { 6, OperandInfo97 },  // Inst #583 = VST4LNqWB_fixed_Asm_16
+  { 6, OperandInfo97 },  // Inst #584 = VST4LNqWB_fixed_Asm_32
+  { 7, OperandInfo98 },  // Inst #585 = VST4LNqWB_register_Asm_16
+  { 7, OperandInfo98 },  // Inst #586 = VST4LNqWB_register_Asm_32
+  { 5, OperandInfo99 },  // Inst #587 = VST4dAsm_16
+  { 5, OperandInfo99 },  // Inst #588 = VST4dAsm_32
+  { 5, OperandInfo99 },  // Inst #589 = VST4dAsm_8
+  { 5, OperandInfo99 },  // Inst #590 = VST4dWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #591 = VST4dWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #592 = VST4dWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #593 = VST4dWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #594 = VST4dWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #595 = VST4dWB_register_Asm_8
+  { 5, OperandInfo99 },  // Inst #596 = VST4qAsm_16
+  { 5, OperandInfo99 },  // Inst #597 = VST4qAsm_32
+  { 5, OperandInfo99 },  // Inst #598 = VST4qAsm_8
+  { 5, OperandInfo99 },  // Inst #599 = VST4qWB_fixed_Asm_16
+  { 5, OperandInfo99 },  // Inst #600 = VST4qWB_fixed_Asm_32
+  { 5, OperandInfo99 },  // Inst #601 = VST4qWB_fixed_Asm_8
+  { 6, OperandInfo100 },  // Inst #602 = VST4qWB_register_Asm_16
+  { 6, OperandInfo100 },  // Inst #603 = VST4qWB_register_Asm_32
+  { 6, OperandInfo100 },  // Inst #604 = VST4qWB_register_Asm_8
+  { 0, 0 },  // Inst #605 = WIN__CHKSTK
+  { 1, OperandInfo58 },  // Inst #606 = WIN__DBZCHK
+  { 2, OperandInfo106 },  // Inst #607 = t2ABS
+  { 5, OperandInfo107 },  // Inst #608 = t2ADDSri
+  { 5, OperandInfo108 },  // Inst #609 = t2ADDSrr
+  { 6, OperandInfo109 },  // Inst #610 = t2ADDSrs
+  { 1, OperandInfo2 },  // Inst #611 = t2BF_LabelPseudo
+  { 3, OperandInfo59 },  // Inst #612 = t2BR_JT
+  { 3, OperandInfo110 },  // Inst #613 = t2CALL_BTI
+  { 2, OperandInfo111 },  // Inst #614 = t2DoLoopStart
+  { 3, OperandInfo112 },  // Inst #615 = t2DoLoopStartTP
+  { 5, OperandInfo66 },  // Inst #616 = t2LDMIA_RET
+  { 4, OperandInfo113 },  // Inst #617 = t2LDRBpcrel
+  { 4, OperandInfo68 },  // Inst #618 = t2LDRConstPool
+  { 4, OperandInfo113 },  // Inst #619 = t2LDRHpcrel
+  { 2, OperandInfo114 },  // Inst #620 = t2LDRLIT_ga_pcrel
+  { 4, OperandInfo113 },  // Inst #621 = t2LDRSBpcrel
+  { 4, OperandInfo113 },  // Inst #622 = t2LDRSHpcrel
+  { 5, OperandInfo87 },  // Inst #623 = t2LDR_POST_imm
+  { 5, OperandInfo87 },  // Inst #624 = t2LDR_PRE_imm
+  { 3, OperandInfo115 },  // Inst #625 = t2LDRpci_pic
+  { 4, OperandInfo68 },  // Inst #626 = t2LDRpcrel
+  { 4, OperandInfo116 },  // Inst #627 = t2LEApcrel
+  { 4, OperandInfo116 },  // Inst #628 = t2LEApcrelJT
+  { 3, OperandInfo117 },  // Inst #629 = t2LoopDec
+  { 2, OperandInfo57 },  // Inst #630 = t2LoopEnd
+  { 3, OperandInfo118 },  // Inst #631 = t2LoopEndDec
+  { 6, OperandInfo119 },  // Inst #632 = t2MOVCCasr
+  { 5, OperandInfo120 },  // Inst #633 = t2MOVCCi
+  { 5, OperandInfo120 },  // Inst #634 = t2MOVCCi16
+  { 5, OperandInfo121 },  // Inst #635 = t2MOVCCi32imm
+  { 6, OperandInfo119 },  // Inst #636 = t2MOVCClsl
+  { 6, OperandInfo119 },  // Inst #637 = t2MOVCClsr
+  { 5, OperandInfo122 },  // Inst #638 = t2MOVCCr
+  { 6, OperandInfo119 },  // Inst #639 = t2MOVCCror
+  { 5, OperandInfo123 },  // Inst #640 = t2MOVSsi
+  { 6, OperandInfo124 },  // Inst #641 = t2MOVSsr
+  { 4, OperandInfo125 },  // Inst #642 = t2MOVTi16_ga_pcrel
+  { 2, OperandInfo114 },  // Inst #643 = t2MOV_ga_pcrel
+  { 3, OperandInfo115 },  // Inst #644 = t2MOVi16_ga_pcrel
+  { 2, OperandInfo114 },  // Inst #645 = t2MOVi32imm
+  { 5, OperandInfo123 },  // Inst #646 = t2MOVsi
+  { 6, OperandInfo124 },  // Inst #647 = t2MOVsr
+  { 5, OperandInfo120 },  // Inst #648 = t2MVNCCi
+  { 5, OperandInfo126 },  // Inst #649 = t2RSBSri
+  { 6, OperandInfo127 },  // Inst #650 = t2RSBSrs
+  { 6, OperandInfo128 },  // Inst #651 = t2STRB_preidx
+  { 6, OperandInfo128 },  // Inst #652 = t2STRH_preidx
+  { 5, OperandInfo87 },  // Inst #653 = t2STR_POST_imm
+  { 5, OperandInfo87 },  // Inst #654 = t2STR_PRE_imm
+  { 6, OperandInfo128 },  // Inst #655 = t2STR_preidx
+  { 5, OperandInfo107 },  // Inst #656 = t2SUBSri
+  { 5, OperandInfo108 },  // Inst #657 = t2SUBSrr
+  { 6, OperandInfo109 },  // Inst #658 = t2SUBSrs
+  { 0, 0 },  // Inst #659 = t2SpeculationBarrierISBDSBEndBB
+  { 0, 0 },  // Inst #660 = t2SpeculationBarrierSBEndBB
+  { 4, OperandInfo65 },  // Inst #661 = t2TBB_JT
+  { 4, OperandInfo65 },  // Inst #662 = t2TBH_JT
+  { 2, OperandInfo111 },  // Inst #663 = t2WhileLoopSetup
+  { 2, OperandInfo57 },  // Inst #664 = t2WhileLoopStart
+  { 3, OperandInfo129 },  // Inst #665 = t2WhileLoopStartLR
+  { 4, OperandInfo130 },  // Inst #666 = t2WhileLoopStartTP
+  { 3, OperandInfo131 },  // Inst #667 = tADCS
+  { 3, OperandInfo132 },  // Inst #668 = tADDSi3
+  { 3, OperandInfo132 },  // Inst #669 = tADDSi8
+  { 3, OperandInfo131 },  // Inst #670 = tADDSrr
+  { 3, OperandInfo133 },  // Inst #671 = tADDframe
+  { 2, OperandInfo10 },  // Inst #672 = tADJCALLSTACKDOWN
+  { 2, OperandInfo10 },  // Inst #673 = tADJCALLSTACKUP
+  { 1, OperandInfo134 },  // Inst #674 = tBLXNS_CALL
+  { 3, OperandInfo135 },  // Inst #675 = tBLXr_noip
+  { 4, OperandInfo136 },  // Inst #676 = tBL_PUSHLR
+  { 3, OperandInfo137 },  // Inst #677 = tBRIND
+  { 2, OperandInfo138 },  // Inst #678 = tBR_JTr
+  { 0, 0 },  // Inst #679 = tBXNS_RET
+  { 1, OperandInfo58 },  // Inst #680 = tBX_CALL
+  { 2, OperandInfo139 },  // Inst #681 = tBX_RET
+  { 3, OperandInfo140 },  // Inst #682 = tBX_RET_vararg
+  { 3, OperandInfo141 },  // Inst #683 = tBfar
+  { 5, OperandInfo142 },  // Inst #684 = tCMP_SWAP_16
+  { 5, OperandInfo143 },  // Inst #685 = tCMP_SWAP_32
+  { 5, OperandInfo142 },  // Inst #686 = tCMP_SWAP_8
+  { 5, OperandInfo144 },  // Inst #687 = tLDMIA_UPD
+  { 4, OperandInfo145 },  // Inst #688 = tLDRConstPool
+  { 2, OperandInfo138 },  // Inst #689 = tLDRLIT_ga_abs
+  { 2, OperandInfo138 },  // Inst #690 = tLDRLIT_ga_pcrel
+  { 5, OperandInfo146 },  // Inst #691 = tLDR_postidx
+  { 3, OperandInfo147 },  // Inst #692 = tLDRpci_pic
+  { 4, OperandInfo148 },  // Inst #693 = tLEApcrel
+  { 4, OperandInfo148 },  // Inst #694 = tLEApcrelJT
+  { 3, OperandInfo132 },  // Inst #695 = tLSLSri
+  { 5, OperandInfo149 },  // Inst #696 = tMOVCCr_pseudo
+  { 3, OperandInfo150 },  // Inst #697 = tPOP_RET
+  { 2, OperandInfo151 },  // Inst #698 = tRSBS
+  { 3, OperandInfo131 },  // Inst #699 = tSBCS
+  { 3, OperandInfo132 },  // Inst #700 = tSUBSi3
+  { 3, OperandInfo132 },  // Inst #701 = tSUBSi8
+  { 3, OperandInfo131 },  // Inst #702 = tSUBSrr
+  { 3, OperandInfo141 },  // Inst #703 = tTAILJMPd
+  { 3, OperandInfo141 },  // Inst #704 = tTAILJMPdND
+  { 1, OperandInfo95 },  // Inst #705 = tTAILJMPr
+  { 4, OperandInfo152 },  // Inst #706 = tTBB_JT
+  { 4, OperandInfo152 },  // Inst #707 = tTBH_JT
+  { 0, 0 },  // Inst #708 = tTPsoft
+  { 6, OperandInfo51 },  // Inst #709 = ADCri
+  { 6, OperandInfo153 },  // Inst #710 = ADCrr
+  { 7, OperandInfo154 },  // Inst #711 = ADCrsi
+  { 8, OperandInfo155 },  // Inst #712 = ADCrsr
+  { 6, OperandInfo51 },  // Inst #713 = ADDri
+  { 6, OperandInfo153 },  // Inst #714 = ADDrr
+  { 7, OperandInfo154 },  // Inst #715 = ADDrsi
+  { 8, OperandInfo156 },  // Inst #716 = ADDrsr
+  { 4, OperandInfo68 },  // Inst #717 = ADR
+  { 3, OperandInfo157 },  // Inst #718 = AESD
+  { 3, OperandInfo157 },  // Inst #719 = AESE
+  { 2, OperandInfo158 },  // Inst #720 = AESIMC
+  { 2, OperandInfo158 },  // Inst #721 = AESMC
+  { 6, OperandInfo51 },  // Inst #722 = ANDri
+  { 6, OperandInfo153 },  // Inst #723 = ANDrr
+  { 7, OperandInfo154 },  // Inst #724 = ANDrsi
+  { 8, OperandInfo156 },  // Inst #725 = ANDrsr
+  { 5, OperandInfo159 },  // Inst #726 = BF16VDOTI_VDOTD
+  { 5, OperandInfo160 },  // Inst #727 = BF16VDOTI_VDOTQ
+  { 4, OperandInfo161 },  // Inst #728 = BF16VDOTS_VDOTD
+  { 4, OperandInfo162 },  // Inst #729 = BF16VDOTS_VDOTQ
+  { 4, OperandInfo163 },  // Inst #730 = BF16_VCVT
+  { 5, OperandInfo105 },  // Inst #731 = BF16_VCVTB
+  { 5, OperandInfo105 },  // Inst #732 = BF16_VCVTT
+  { 5, OperandInfo73 },  // Inst #733 = BFC
+  { 6, OperandInfo164 },  // Inst #734 = BFI
+  { 6, OperandInfo51 },  // Inst #735 = BICri
+  { 6, OperandInfo153 },  // Inst #736 = BICrr
+  { 7, OperandInfo154 },  // Inst #737 = BICrsi
+  { 8, OperandInfo156 },  // Inst #738 = BICrsr
+  { 1, OperandInfo2 },  // Inst #739 = BKPT
+  { 1, OperandInfo53 },  // Inst #740 = BL
+  { 1, OperandInfo78 },  // Inst #741 = BLX
+  { 3, OperandInfo137 },  // Inst #742 = BLX_pred
+  { 1, OperandInfo53 },  // Inst #743 = BLXi
+  { 3, OperandInfo141 },  // Inst #744 = BL_pred
+  { 1, OperandInfo78 },  // Inst #745 = BX
+  { 3, OperandInfo137 },  // Inst #746 = BXJ
+  { 2, OperandInfo139 },  // Inst #747 = BX_RET
+  { 3, OperandInfo137 },  // Inst #748 = BX_pred
+  { 3, OperandInfo141 },  // Inst #749 = Bcc
+  { 3, OperandInfo165 },  // Inst #750 = CDE_CX1
+  { 6, OperandInfo166 },  // Inst #751 = CDE_CX1A
+  { 3, OperandInfo167 },  // Inst #752 = CDE_CX1D
+  { 6, OperandInfo168 },  // Inst #753 = CDE_CX1DA
+  { 4, OperandInfo169 },  // Inst #754 = CDE_CX2
+  { 7, OperandInfo170 },  // Inst #755 = CDE_CX2A
+  { 4, OperandInfo171 },  // Inst #756 = CDE_CX2D
+  { 7, OperandInfo172 },  // Inst #757 = CDE_CX2DA
+  { 5, OperandInfo173 },  // Inst #758 = CDE_CX3
+  { 8, OperandInfo174 },  // Inst #759 = CDE_CX3A
+  { 5, OperandInfo175 },  // Inst #760 = CDE_CX3D
+  { 8, OperandInfo176 },  // Inst #761 = CDE_CX3DA
+  { 4, OperandInfo177 },  // Inst #762 = CDE_VCX1A_fpdp
+  { 4, OperandInfo178 },  // Inst #763 = CDE_VCX1A_fpsp
+  { 7, OperandInfo179 },  // Inst #764 = CDE_VCX1A_vec
+  { 3, OperandInfo180 },  // Inst #765 = CDE_VCX1_fpdp
+  { 3, OperandInfo181 },  // Inst #766 = CDE_VCX1_fpsp
+  { 7, OperandInfo182 },  // Inst #767 = CDE_VCX1_vec
+  { 5, OperandInfo183 },  // Inst #768 = CDE_VCX2A_fpdp
+  { 5, OperandInfo184 },  // Inst #769 = CDE_VCX2A_fpsp
+  { 8, OperandInfo185 },  // Inst #770 = CDE_VCX2A_vec
+  { 4, OperandInfo186 },  // Inst #771 = CDE_VCX2_fpdp
+  { 4, OperandInfo187 },  // Inst #772 = CDE_VCX2_fpsp
+  { 8, OperandInfo188 },  // Inst #773 = CDE_VCX2_vec
+  { 6, OperandInfo189 },  // Inst #774 = CDE_VCX3A_fpdp
+  { 6, OperandInfo190 },  // Inst #775 = CDE_VCX3A_fpsp
+  { 9, OperandInfo191 },  // Inst #776 = CDE_VCX3A_vec
+  { 5, OperandInfo192 },  // Inst #777 = CDE_VCX3_fpdp
+  { 5, OperandInfo193 },  // Inst #778 = CDE_VCX3_fpsp
+  { 9, OperandInfo194 },  // Inst #779 = CDE_VCX3_vec
+  { 8, OperandInfo195 },  // Inst #780 = CDP
+  { 6, OperandInfo196 },  // Inst #781 = CDP2
+  { 0, 0 },  // Inst #782 = CLREX
+  { 4, OperandInfo197 },  // Inst #783 = CLZ
+  { 4, OperandInfo68 },  // Inst #784 = CMNri
+  { 4, OperandInfo197 },  // Inst #785 = CMNzrr
+  { 5, OperandInfo198 },  // Inst #786 = CMNzrsi
+  { 6, OperandInfo199 },  // Inst #787 = CMNzrsr
+  { 4, OperandInfo68 },  // Inst #788 = CMPri
+  { 4, OperandInfo197 },  // Inst #789 = CMPrr
+  { 5, OperandInfo198 },  // Inst #790 = CMPrsi
+  { 6, OperandInfo199 },  // Inst #791 = CMPrsr
+  { 1, OperandInfo2 },  // Inst #792 = CPS1p
+  { 2, OperandInfo7 },  // Inst #793 = CPS2p
+  { 3, OperandInfo200 },  // Inst #794 = CPS3p
+  { 3, OperandInfo201 },  // Inst #795 = CRC32B
+  { 3, OperandInfo201 },  // Inst #796 = CRC32CB
+  { 3, OperandInfo201 },  // Inst #797 = CRC32CH
+  { 3, OperandInfo201 },  // Inst #798 = CRC32CW
+  { 3, OperandInfo201 },  // Inst #799 = CRC32H
+  { 3, OperandInfo201 },  // Inst #800 = CRC32W
+  { 3, OperandInfo202 },  // Inst #801 = DBG
+  { 1, OperandInfo2 },  // Inst #802 = DMB
+  { 1, OperandInfo2 },  // Inst #803 = DSB
+  { 6, OperandInfo51 },  // Inst #804 = EORri
+  { 6, OperandInfo153 },  // Inst #805 = EORrr
+  { 7, OperandInfo154 },  // Inst #806 = EORrsi
+  { 8, OperandInfo156 },  // Inst #807 = EORrsr
+  { 2, OperandInfo139 },  // Inst #808 = ERET
+  { 4, OperandInfo203 },  // Inst #809 = FCONSTD
+  { 4, OperandInfo204 },  // Inst #810 = FCONSTH
+  { 4, OperandInfo205 },  // Inst #811 = FCONSTS
+  { 5, OperandInfo66 },  // Inst #812 = FLDMXDB_UPD
+  { 4, OperandInfo206 },  // Inst #813 = FLDMXIA
+  { 5, OperandInfo66 },  // Inst #814 = FLDMXIA_UPD
+  { 2, OperandInfo139 },  // Inst #815 = FMSTAT
+  { 5, OperandInfo66 },  // Inst #816 = FSTMXDB_UPD
+  { 4, OperandInfo206 },  // Inst #817 = FSTMXIA
+  { 5, OperandInfo66 },  // Inst #818 = FSTMXIA_UPD
+  { 3, OperandInfo202 },  // Inst #819 = HINT
+  { 1, OperandInfo2 },  // Inst #820 = HLT
+  { 1, OperandInfo2 },  // Inst #821 = HVC
+  { 1, OperandInfo2 },  // Inst #822 = ISB
+  { 4, OperandInfo67 },  // Inst #823 = LDA
+  { 4, OperandInfo67 },  // Inst #824 = LDAB
+  { 4, OperandInfo67 },  // Inst #825 = LDAEX
+  { 4, OperandInfo67 },  // Inst #826 = LDAEXB
+  { 4, OperandInfo207 },  // Inst #827 = LDAEXD
+  { 4, OperandInfo67 },  // Inst #828 = LDAEXH
+  { 4, OperandInfo67 },  // Inst #829 = LDAH
+  { 4, OperandInfo208 },  // Inst #830 = LDC2L_OFFSET
+  { 4, OperandInfo209 },  // Inst #831 = LDC2L_OPTION
+  { 4, OperandInfo208 },  // Inst #832 = LDC2L_POST
+  { 5, OperandInfo210 },  // Inst #833 = LDC2L_PRE
+  { 4, OperandInfo208 },  // Inst #834 = LDC2_OFFSET
+  { 4, OperandInfo209 },  // Inst #835 = LDC2_OPTION
+  { 4, OperandInfo208 },  // Inst #836 = LDC2_POST
+  { 5, OperandInfo210 },  // Inst #837 = LDC2_PRE
+  { 6, OperandInfo211 },  // Inst #838 = LDCL_OFFSET
+  { 6, OperandInfo212 },  // Inst #839 = LDCL_OPTION
+  { 6, OperandInfo211 },  // Inst #840 = LDCL_POST
+  { 7, OperandInfo213 },  // Inst #841 = LDCL_PRE
+  { 6, OperandInfo211 },  // Inst #842 = LDC_OFFSET
+  { 6, OperandInfo212 },  // Inst #843 = LDC_OPTION
+  { 6, OperandInfo211 },  // Inst #844 = LDC_POST
+  { 7, OperandInfo213 },  // Inst #845 = LDC_PRE
+  { 4, OperandInfo206 },  // Inst #846 = LDMDA
+  { 5, OperandInfo66 },  // Inst #847 = LDMDA_UPD
+  { 4, OperandInfo206 },  // Inst #848 = LDMDB
+  { 5, OperandInfo66 },  // Inst #849 = LDMDB_UPD
+  { 4, OperandInfo206 },  // Inst #850 = LDMIA
+  { 5, OperandInfo66 },  // Inst #851 = LDMIA_UPD
+  { 4, OperandInfo206 },  // Inst #852 = LDMIB
+  { 5, OperandInfo66 },  // Inst #853 = LDMIB_UPD
+  { 7, OperandInfo214 },  // Inst #854 = LDRBT_POST_IMM
+  { 7, OperandInfo214 },  // Inst #855 = LDRBT_POST_REG
+  { 7, OperandInfo214 },  // Inst #856 = LDRB_POST_IMM
+  { 7, OperandInfo214 },  // Inst #857 = LDRB_POST_REG
+  { 6, OperandInfo215 },  // Inst #858 = LDRB_PRE_IMM
+  { 7, OperandInfo214 },  // Inst #859 = LDRB_PRE_REG
+  { 5, OperandInfo216 },  // Inst #860 = LDRBi12
+  { 6, OperandInfo217 },  // Inst #861 = LDRBrs
+  { 7, OperandInfo218 },  // Inst #862 = LDRD
+  { 8, OperandInfo219 },  // Inst #863 = LDRD_POST
+  { 8, OperandInfo219 },  // Inst #864 = LDRD_PRE
+  { 4, OperandInfo67 },  // Inst #865 = LDREX
+  { 4, OperandInfo67 },  // Inst #866 = LDREXB
+  { 4, OperandInfo207 },  // Inst #867 = LDREXD
+  { 4, OperandInfo67 },  // Inst #868 = LDREXH
+  { 6, OperandInfo220 },  // Inst #869 = LDRH
+  { 6, OperandInfo215 },  // Inst #870 = LDRHTi
+  { 7, OperandInfo221 },  // Inst #871 = LDRHTr
+  { 7, OperandInfo222 },  // Inst #872 = LDRH_POST
+  { 7, OperandInfo222 },  // Inst #873 = LDRH_PRE
+  { 6, OperandInfo220 },  // Inst #874 = LDRSB
+  { 6, OperandInfo215 },  // Inst #875 = LDRSBTi
+  { 7, OperandInfo221 },  // Inst #876 = LDRSBTr
+  { 7, OperandInfo222 },  // Inst #877 = LDRSB_POST
+  { 7, OperandInfo222 },  // Inst #878 = LDRSB_PRE
+  { 6, OperandInfo220 },  // Inst #879 = LDRSH
+  { 6, OperandInfo215 },  // Inst #880 = LDRSHTi
+  { 7, OperandInfo221 },  // Inst #881 = LDRSHTr
+  { 7, OperandInfo222 },  // Inst #882 = LDRSH_POST
+  { 7, OperandInfo222 },  // Inst #883 = LDRSH_PRE
+  { 7, OperandInfo214 },  // Inst #884 = LDRT_POST_IMM
+  { 7, OperandInfo214 },  // Inst #885 = LDRT_POST_REG
+  { 7, OperandInfo214 },  // Inst #886 = LDR_POST_IMM
+  { 7, OperandInfo214 },  // Inst #887 = LDR_POST_REG
+  { 6, OperandInfo215 },  // Inst #888 = LDR_PRE_IMM
+  { 7, OperandInfo214 },  // Inst #889 = LDR_PRE_REG
+  { 5, OperandInfo87 },  // Inst #890 = LDRcp
+  { 5, OperandInfo87 },  // Inst #891 = LDRi12
+  { 6, OperandInfo223 },  // Inst #892 = LDRrs
+  { 8, OperandInfo224 },  // Inst #893 = MCR
+  { 6, OperandInfo225 },  // Inst #894 = MCR2
+  { 7, OperandInfo226 },  // Inst #895 = MCRR
+  { 5, OperandInfo227 },  // Inst #896 = MCRR2
+  { 7, OperandInfo228 },  // Inst #897 = MLA
+  { 6, OperandInfo229 },  // Inst #898 = MLS
+  { 2, OperandInfo139 },  // Inst #899 = MOVPCLR
+  { 5, OperandInfo230 },  // Inst #900 = MOVTi16
+  { 5, OperandInfo231 },  // Inst #901 = MOVi
+  { 4, OperandInfo68 },  // Inst #902 = MOVi16
+  { 5, OperandInfo88 },  // Inst #903 = MOVr
+  { 5, OperandInfo232 },  // Inst #904 = MOVr_TC
+  { 6, OperandInfo233 },  // Inst #905 = MOVsi
+  { 7, OperandInfo234 },  // Inst #906 = MOVsr
+  { 8, OperandInfo235 },  // Inst #907 = MRC
+  { 6, OperandInfo236 },  // Inst #908 = MRC2
+  { 7, OperandInfo237 },  // Inst #909 = MRRC
+  { 5, OperandInfo238 },  // Inst #910 = MRRC2
+  { 3, OperandInfo239 },  // Inst #911 = MRS
+  { 4, OperandInfo113 },  // Inst #912 = MRSbanked
+  { 3, OperandInfo239 },  // Inst #913 = MRSsys
+  { 4, OperandInfo240 },  // Inst #914 = MSR
+  { 4, OperandInfo241 },  // Inst #915 = MSRbanked
+  { 4, OperandInfo242 },  // Inst #916 = MSRi
+  { 6, OperandInfo52 },  // Inst #917 = MUL
+  { 7, OperandInfo243 },  // Inst #918 = MVE_ASRLi
+  { 7, OperandInfo244 },  // Inst #919 = MVE_ASRLr
+  { 2, OperandInfo111 },  // Inst #920 = MVE_DLSTP_16
+  { 2, OperandInfo111 },  // Inst #921 = MVE_DLSTP_32
+  { 2, OperandInfo111 },  // Inst #922 = MVE_DLSTP_64
+  { 2, OperandInfo111 },  // Inst #923 = MVE_DLSTP_8
+  { 2, OperandInfo139 },  // Inst #924 = MVE_LCTP
+  { 3, OperandInfo118 },  // Inst #925 = MVE_LETP
+  { 7, OperandInfo243 },  // Inst #926 = MVE_LSLLi
+  { 7, OperandInfo244 },  // Inst #927 = MVE_LSLLr
+  { 7, OperandInfo243 },  // Inst #928 = MVE_LSRL
+  { 5, OperandInfo122 },  // Inst #929 = MVE_SQRSHR
+  { 8, OperandInfo245 },  // Inst #930 = MVE_SQRSHRL
+  { 5, OperandInfo120 },  // Inst #931 = MVE_SQSHL
+  { 7, OperandInfo243 },  // Inst #932 = MVE_SQSHLL
+  { 5, OperandInfo120 },  // Inst #933 = MVE_SRSHR
+  { 7, OperandInfo243 },  // Inst #934 = MVE_SRSHRL
+  { 5, OperandInfo122 },  // Inst #935 = MVE_UQRSHL
+  { 8, OperandInfo245 },  // Inst #936 = MVE_UQRSHLL
+  { 5, OperandInfo120 },  // Inst #937 = MVE_UQSHL
+  { 7, OperandInfo243 },  // Inst #938 = MVE_UQSHLL
+  { 5, OperandInfo120 },  // Inst #939 = MVE_URSHR
+  { 7, OperandInfo243 },  // Inst #940 = MVE_URSHRL
+  { 7, OperandInfo246 },  // Inst #941 = MVE_VABAVs16
+  { 7, OperandInfo246 },  // Inst #942 = MVE_VABAVs32
+  { 7, OperandInfo246 },  // Inst #943 = MVE_VABAVs8
+  { 7, OperandInfo246 },  // Inst #944 = MVE_VABAVu16
+  { 7, OperandInfo246 },  // Inst #945 = MVE_VABAVu32
+  { 7, OperandInfo246 },  // Inst #946 = MVE_VABAVu8
+  { 7, OperandInfo247 },  // Inst #947 = MVE_VABDf16
+  { 7, OperandInfo247 },  // Inst #948 = MVE_VABDf32
+  { 7, OperandInfo247 },  // Inst #949 = MVE_VABDs16
+  { 7, OperandInfo247 },  // Inst #950 = MVE_VABDs32
+  { 7, OperandInfo247 },  // Inst #951 = MVE_VABDs8
+  { 7, OperandInfo247 },  // Inst #952 = MVE_VABDu16
+  { 7, OperandInfo247 },  // Inst #953 = MVE_VABDu32
+  { 7, OperandInfo247 },  // Inst #954 = MVE_VABDu8
+  { 6, OperandInfo248 },  // Inst #955 = MVE_VABSf16
+  { 6, OperandInfo248 },  // Inst #956 = MVE_VABSf32
+  { 6, OperandInfo248 },  // Inst #957 = MVE_VABSs16
+  { 6, OperandInfo248 },  // Inst #958 = MVE_VABSs32
+  { 6, OperandInfo248 },  // Inst #959 = MVE_VABSs8
+  { 9, OperandInfo249 },  // Inst #960 = MVE_VADC
+  { 8, OperandInfo250 },  // Inst #961 = MVE_VADCI
+  { 8, OperandInfo251 },  // Inst #962 = MVE_VADDLVs32acc
+  { 6, OperandInfo252 },  // Inst #963 = MVE_VADDLVs32no_acc
+  { 8, OperandInfo251 },  // Inst #964 = MVE_VADDLVu32acc
+  { 6, OperandInfo252 },  // Inst #965 = MVE_VADDLVu32no_acc
+  { 6, OperandInfo253 },  // Inst #966 = MVE_VADDVs16acc
+  { 5, OperandInfo254 },  // Inst #967 = MVE_VADDVs16no_acc
+  { 6, OperandInfo253 },  // Inst #968 = MVE_VADDVs32acc
+  { 5, OperandInfo254 },  // Inst #969 = MVE_VADDVs32no_acc
+  { 6, OperandInfo253 },  // Inst #970 = MVE_VADDVs8acc
+  { 5, OperandInfo254 },  // Inst #971 = MVE_VADDVs8no_acc
+  { 6, OperandInfo253 },  // Inst #972 = MVE_VADDVu16acc
+  { 5, OperandInfo254 },  // Inst #973 = MVE_VADDVu16no_acc
+  { 6, OperandInfo253 },  // Inst #974 = MVE_VADDVu32acc
+  { 5, OperandInfo254 },  // Inst #975 = MVE_VADDVu32no_acc
+  { 6, OperandInfo253 },  // Inst #976 = MVE_VADDVu8acc
+  { 5, OperandInfo254 },  // Inst #977 = MVE_VADDVu8no_acc
+  { 7, OperandInfo255 },  // Inst #978 = MVE_VADD_qr_f16
+  { 7, OperandInfo255 },  // Inst #979 = MVE_VADD_qr_f32
+  { 7, OperandInfo255 },  // Inst #980 = MVE_VADD_qr_i16
+  { 7, OperandInfo255 },  // Inst #981 = MVE_VADD_qr_i32
+  { 7, OperandInfo255 },  // Inst #982 = MVE_VADD_qr_i8
+  { 7, OperandInfo247 },  // Inst #983 = MVE_VADDf16
+  { 7, OperandInfo247 },  // Inst #984 = MVE_VADDf32
+  { 7, OperandInfo247 },  // Inst #985 = MVE_VADDi16
+  { 7, OperandInfo247 },  // Inst #986 = MVE_VADDi32
+  { 7, OperandInfo247 },  // Inst #987 = MVE_VADDi8
+  { 7, OperandInfo247 },  // Inst #988 = MVE_VAND
+  { 7, OperandInfo247 },  // Inst #989 = MVE_VBIC
+  { 6, OperandInfo256 },  // Inst #990 = MVE_VBICimmi16
+  { 6, OperandInfo256 },  // Inst #991 = MVE_VBICimmi32
+  { 7, OperandInfo255 },  // Inst #992 = MVE_VBRSR16
+  { 7, OperandInfo255 },  // Inst #993 = MVE_VBRSR32
+  { 7, OperandInfo255 },  // Inst #994 = MVE_VBRSR8
+  { 8, OperandInfo257 },  // Inst #995 = MVE_VCADDf16
+  { 8, OperandInfo258 },  // Inst #996 = MVE_VCADDf32
+  { 8, OperandInfo257 },  // Inst #997 = MVE_VCADDi16
+  { 8, OperandInfo258 },  // Inst #998 = MVE_VCADDi32
+  { 8, OperandInfo257 },  // Inst #999 = MVE_VCADDi8
+  { 6, OperandInfo248 },  // Inst #1000 = MVE_VCLSs16
+  { 6, OperandInfo248 },  // Inst #1001 = MVE_VCLSs32
+  { 6, OperandInfo248 },  // Inst #1002 = MVE_VCLSs8
+  { 6, OperandInfo248 },  // Inst #1003 = MVE_VCLZs16
+  { 6, OperandInfo248 },  // Inst #1004 = MVE_VCLZs32
+  { 6, OperandInfo248 },  // Inst #1005 = MVE_VCLZs8
+  { 8, OperandInfo259 },  // Inst #1006 = MVE_VCMLAf16
+  { 8, OperandInfo259 },  // Inst #1007 = MVE_VCMLAf32
+  { 7, OperandInfo260 },  // Inst #1008 = MVE_VCMPf16
+  { 7, OperandInfo261 },  // Inst #1009 = MVE_VCMPf16r
+  { 7, OperandInfo260 },  // Inst #1010 = MVE_VCMPf32
+  { 7, OperandInfo261 },  // Inst #1011 = MVE_VCMPf32r
+  { 7, OperandInfo260 },  // Inst #1012 = MVE_VCMPi16
+  { 7, OperandInfo261 },  // Inst #1013 = MVE_VCMPi16r
+  { 7, OperandInfo260 },  // Inst #1014 = MVE_VCMPi32
+  { 7, OperandInfo261 },  // Inst #1015 = MVE_VCMPi32r
+  { 7, OperandInfo260 },  // Inst #1016 = MVE_VCMPi8
+  { 7, OperandInfo261 },  // Inst #1017 = MVE_VCMPi8r
+  { 7, OperandInfo260 },  // Inst #1018 = MVE_VCMPs16
+  { 7, OperandInfo261 },  // Inst #1019 = MVE_VCMPs16r
+  { 7, OperandInfo260 },  // Inst #1020 = MVE_VCMPs32
+  { 7, OperandInfo261 },  // Inst #1021 = MVE_VCMPs32r
+  { 7, OperandInfo260 },  // Inst #1022 = MVE_VCMPs8
+  { 7, OperandInfo261 },  // Inst #1023 = MVE_VCMPs8r
+  { 7, OperandInfo260 },  // Inst #1024 = MVE_VCMPu16
+  { 7, OperandInfo261 },  // Inst #1025 = MVE_VCMPu16r
+  { 7, OperandInfo260 },  // Inst #1026 = MVE_VCMPu32
+  { 7, OperandInfo261 },  // Inst #1027 = MVE_VCMPu32r
+  { 7, OperandInfo260 },  // Inst #1028 = MVE_VCMPu8
+  { 7, OperandInfo261 },  // Inst #1029 = MVE_VCMPu8r
+  { 8, OperandInfo257 },  // Inst #1030 = MVE_VCMULf16
+  { 8, OperandInfo258 },  // Inst #1031 = MVE_VCMULf32
+  { 5, OperandInfo262 },  // Inst #1032 = MVE_VCTP16
+  { 5, OperandInfo262 },  // Inst #1033 = MVE_VCTP32
+  { 5, OperandInfo262 },  // Inst #1034 = MVE_VCTP64
+  { 5, OperandInfo262 },  // Inst #1035 = MVE_VCTP8
+  { 6, OperandInfo263 },  // Inst #1036 = MVE_VCVTf16f32bh
+  { 6, OperandInfo263 },  // Inst #1037 = MVE_VCVTf16f32th
+  { 7, OperandInfo264 },  // Inst #1038 = MVE_VCVTf16s16_fix
+  { 6, OperandInfo248 },  // Inst #1039 = MVE_VCVTf16s16n
+  { 7, OperandInfo264 },  // Inst #1040 = MVE_VCVTf16u16_fix
+  { 6, OperandInfo248 },  // Inst #1041 = MVE_VCVTf16u16n
+  { 6, OperandInfo248 },  // Inst #1042 = MVE_VCVTf32f16bh
+  { 6, OperandInfo248 },  // Inst #1043 = MVE_VCVTf32f16th
+  { 7, OperandInfo264 },  // Inst #1044 = MVE_VCVTf32s32_fix
+  { 6, OperandInfo248 },  // Inst #1045 = MVE_VCVTf32s32n
+  { 7, OperandInfo264 },  // Inst #1046 = MVE_VCVTf32u32_fix
+  { 6, OperandInfo248 },  // Inst #1047 = MVE_VCVTf32u32n
+  { 7, OperandInfo264 },  // Inst #1048 = MVE_VCVTs16f16_fix
+  { 6, OperandInfo248 },  // Inst #1049 = MVE_VCVTs16f16a
+  { 6, OperandInfo248 },  // Inst #1050 = MVE_VCVTs16f16m
+  { 6, OperandInfo248 },  // Inst #1051 = MVE_VCVTs16f16n
+  { 6, OperandInfo248 },  // Inst #1052 = MVE_VCVTs16f16p
+  { 6, OperandInfo248 },  // Inst #1053 = MVE_VCVTs16f16z
+  { 7, OperandInfo264 },  // Inst #1054 = MVE_VCVTs32f32_fix
+  { 6, OperandInfo248 },  // Inst #1055 = MVE_VCVTs32f32a
+  { 6, OperandInfo248 },  // Inst #1056 = MVE_VCVTs32f32m
+  { 6, OperandInfo248 },  // Inst #1057 = MVE_VCVTs32f32n
+  { 6, OperandInfo248 },  // Inst #1058 = MVE_VCVTs32f32p
+  { 6, OperandInfo248 },  // Inst #1059 = MVE_VCVTs32f32z
+  { 7, OperandInfo264 },  // Inst #1060 = MVE_VCVTu16f16_fix
+  { 6, OperandInfo248 },  // Inst #1061 = MVE_VCVTu16f16a
+  { 6, OperandInfo248 },  // Inst #1062 = MVE_VCVTu16f16m
+  { 6, OperandInfo248 },  // Inst #1063 = MVE_VCVTu16f16n
+  { 6, OperandInfo248 },  // Inst #1064 = MVE_VCVTu16f16p
+  { 6, OperandInfo248 },  // Inst #1065 = MVE_VCVTu16f16z
+  { 7, OperandInfo264 },  // Inst #1066 = MVE_VCVTu32f32_fix
+  { 6, OperandInfo248 },  // Inst #1067 = MVE_VCVTu32f32a
+  { 6, OperandInfo248 },  // Inst #1068 = MVE_VCVTu32f32m
+  { 6, OperandInfo248 },  // Inst #1069 = MVE_VCVTu32f32n
+  { 6, OperandInfo248 },  // Inst #1070 = MVE_VCVTu32f32p
+  { 6, OperandInfo248 },  // Inst #1071 = MVE_VCVTu32f32z
+  { 8, OperandInfo265 },  // Inst #1072 = MVE_VDDUPu16
+  { 8, OperandInfo265 },  // Inst #1073 = MVE_VDDUPu32
+  { 8, OperandInfo265 },  // Inst #1074 = MVE_VDDUPu8
+  { 6, OperandInfo266 },  // Inst #1075 = MVE_VDUP16
+  { 6, OperandInfo266 },  // Inst #1076 = MVE_VDUP32
+  { 6, OperandInfo266 },  // Inst #1077 = MVE_VDUP8
+  { 9, OperandInfo267 },  // Inst #1078 = MVE_VDWDUPu16
+  { 9, OperandInfo267 },  // Inst #1079 = MVE_VDWDUPu32
+  { 9, OperandInfo267 },  // Inst #1080 = MVE_VDWDUPu8
+  { 7, OperandInfo247 },  // Inst #1081 = MVE_VEOR
+  { 7, OperandInfo268 },  // Inst #1082 = MVE_VFMA_qr_Sf16
+  { 7, OperandInfo268 },  // Inst #1083 = MVE_VFMA_qr_Sf32
+  { 7, OperandInfo268 },  // Inst #1084 = MVE_VFMA_qr_f16
+  { 7, OperandInfo268 },  // Inst #1085 = MVE_VFMA_qr_f32
+  { 7, OperandInfo269 },  // Inst #1086 = MVE_VFMAf16
+  { 7, OperandInfo269 },  // Inst #1087 = MVE_VFMAf32
+  { 7, OperandInfo269 },  // Inst #1088 = MVE_VFMSf16
+  { 7, OperandInfo269 },  // Inst #1089 = MVE_VFMSf32
+  { 7, OperandInfo255 },  // Inst #1090 = MVE_VHADD_qr_s16
+  { 7, OperandInfo255 },  // Inst #1091 = MVE_VHADD_qr_s32
+  { 7, OperandInfo255 },  // Inst #1092 = MVE_VHADD_qr_s8
+  { 7, OperandInfo255 },  // Inst #1093 = MVE_VHADD_qr_u16
+  { 7, OperandInfo255 },  // Inst #1094 = MVE_VHADD_qr_u32
+  { 7, OperandInfo255 },  // Inst #1095 = MVE_VHADD_qr_u8
+  { 7, OperandInfo247 },  // Inst #1096 = MVE_VHADDs16
+  { 7, OperandInfo247 },  // Inst #1097 = MVE_VHADDs32
+  { 7, OperandInfo247 },  // Inst #1098 = MVE_VHADDs8
+  { 7, OperandInfo247 },  // Inst #1099 = MVE_VHADDu16
+  { 7, OperandInfo247 },  // Inst #1100 = MVE_VHADDu32
+  { 7, OperandInfo247 },  // Inst #1101 = MVE_VHADDu8
+  { 8, OperandInfo257 },  // Inst #1102 = MVE_VHCADDs16
+  { 8, OperandInfo258 },  // Inst #1103 = MVE_VHCADDs32
+  { 8, OperandInfo257 },  // Inst #1104 = MVE_VHCADDs8
+  { 7, OperandInfo255 },  // Inst #1105 = MVE_VHSUB_qr_s16
+  { 7, OperandInfo255 },  // Inst #1106 = MVE_VHSUB_qr_s32
+  { 7, OperandInfo255 },  // Inst #1107 = MVE_VHSUB_qr_s8
+  { 7, OperandInfo255 },  // Inst #1108 = MVE_VHSUB_qr_u16
+  { 7, OperandInfo255 },  // Inst #1109 = MVE_VHSUB_qr_u32
+  { 7, OperandInfo255 },  // Inst #1110 = MVE_VHSUB_qr_u8
+  { 7, OperandInfo247 },  // Inst #1111 = MVE_VHSUBs16
+  { 7, OperandInfo247 },  // Inst #1112 = MVE_VHSUBs32
+  { 7, OperandInfo247 },  // Inst #1113 = MVE_VHSUBs8
+  { 7, OperandInfo247 },  // Inst #1114 = MVE_VHSUBu16
+  { 7, OperandInfo247 },  // Inst #1115 = MVE_VHSUBu32
+  { 7, OperandInfo247 },  // Inst #1116 = MVE_VHSUBu8
+  { 8, OperandInfo265 },  // Inst #1117 = MVE_VIDUPu16
+  { 8, OperandInfo265 },  // Inst #1118 = MVE_VIDUPu32
+  { 8, OperandInfo265 },  // Inst #1119 = MVE_VIDUPu8
+  { 9, OperandInfo267 },  // Inst #1120 = MVE_VIWDUPu16
+  { 9, OperandInfo267 },  // Inst #1121 = MVE_VIWDUPu32
+  { 9, OperandInfo267 },  // Inst #1122 = MVE_VIWDUPu8
+  { 3, OperandInfo270 },  // Inst #1123 = MVE_VLD20_16
+  { 4, OperandInfo271 },  // Inst #1124 = MVE_VLD20_16_wb
+  { 3, OperandInfo270 },  // Inst #1125 = MVE_VLD20_32
+  { 4, OperandInfo271 },  // Inst #1126 = MVE_VLD20_32_wb
+  { 3, OperandInfo270 },  // Inst #1127 = MVE_VLD20_8
+  { 4, OperandInfo271 },  // Inst #1128 = MVE_VLD20_8_wb
+  { 3, OperandInfo270 },  // Inst #1129 = MVE_VLD21_16
+  { 4, OperandInfo271 },  // Inst #1130 = MVE_VLD21_16_wb
+  { 3, OperandInfo270 },  // Inst #1131 = MVE_VLD21_32
+  { 4, OperandInfo271 },  // Inst #1132 = MVE_VLD21_32_wb
+  { 3, OperandInfo270 },  // Inst #1133 = MVE_VLD21_8
+  { 4, OperandInfo271 },  // Inst #1134 = MVE_VLD21_8_wb
+  { 3, OperandInfo272 },  // Inst #1135 = MVE_VLD40_16
+  { 4, OperandInfo273 },  // Inst #1136 = MVE_VLD40_16_wb
+  { 3, OperandInfo272 },  // Inst #1137 = MVE_VLD40_32
+  { 4, OperandInfo273 },  // Inst #1138 = MVE_VLD40_32_wb
+  { 3, OperandInfo272 },  // Inst #1139 = MVE_VLD40_8
+  { 4, OperandInfo273 },  // Inst #1140 = MVE_VLD40_8_wb
+  { 3, OperandInfo272 },  // Inst #1141 = MVE_VLD41_16
+  { 4, OperandInfo273 },  // Inst #1142 = MVE_VLD41_16_wb
+  { 3, OperandInfo272 },  // Inst #1143 = MVE_VLD41_32
+  { 4, OperandInfo273 },  // Inst #1144 = MVE_VLD41_32_wb
+  { 3, OperandInfo272 },  // Inst #1145 = MVE_VLD41_8
+  { 4, OperandInfo273 },  // Inst #1146 = MVE_VLD41_8_wb
+  { 3, OperandInfo272 },  // Inst #1147 = MVE_VLD42_16
+  { 4, OperandInfo273 },  // Inst #1148 = MVE_VLD42_16_wb
+  { 3, OperandInfo272 },  // Inst #1149 = MVE_VLD42_32
+  { 4, OperandInfo273 },  // Inst #1150 = MVE_VLD42_32_wb
+  { 3, OperandInfo272 },  // Inst #1151 = MVE_VLD42_8
+  { 4, OperandInfo273 },  // Inst #1152 = MVE_VLD42_8_wb
+  { 3, OperandInfo272 },  // Inst #1153 = MVE_VLD43_16
+  { 4, OperandInfo273 },  // Inst #1154 = MVE_VLD43_16_wb
+  { 3, OperandInfo272 },  // Inst #1155 = MVE_VLD43_32
+  { 4, OperandInfo273 },  // Inst #1156 = MVE_VLD43_32_wb
+  { 3, OperandInfo272 },  // Inst #1157 = MVE_VLD43_8
+  { 4, OperandInfo273 },  // Inst #1158 = MVE_VLD43_8_wb
+  { 6, OperandInfo274 },  // Inst #1159 = MVE_VLDRBS16
+  { 7, OperandInfo275 },  // Inst #1160 = MVE_VLDRBS16_post
+  { 7, OperandInfo275 },  // Inst #1161 = MVE_VLDRBS16_pre
+  { 6, OperandInfo276 },  // Inst #1162 = MVE_VLDRBS16_rq
+  { 6, OperandInfo274 },  // Inst #1163 = MVE_VLDRBS32
+  { 7, OperandInfo275 },  // Inst #1164 = MVE_VLDRBS32_post
+  { 7, OperandInfo275 },  // Inst #1165 = MVE_VLDRBS32_pre
+  { 6, OperandInfo276 },  // Inst #1166 = MVE_VLDRBS32_rq
+  { 6, OperandInfo274 },  // Inst #1167 = MVE_VLDRBU16
+  { 7, OperandInfo275 },  // Inst #1168 = MVE_VLDRBU16_post
+  { 7, OperandInfo275 },  // Inst #1169 = MVE_VLDRBU16_pre
+  { 6, OperandInfo276 },  // Inst #1170 = MVE_VLDRBU16_rq
+  { 6, OperandInfo274 },  // Inst #1171 = MVE_VLDRBU32
+  { 7, OperandInfo275 },  // Inst #1172 = MVE_VLDRBU32_post
+  { 7, OperandInfo275 },  // Inst #1173 = MVE_VLDRBU32_pre
+  { 6, OperandInfo276 },  // Inst #1174 = MVE_VLDRBU32_rq
+  { 6, OperandInfo277 },  // Inst #1175 = MVE_VLDRBU8
+  { 7, OperandInfo278 },  // Inst #1176 = MVE_VLDRBU8_post
+  { 7, OperandInfo278 },  // Inst #1177 = MVE_VLDRBU8_pre
+  { 6, OperandInfo276 },  // Inst #1178 = MVE_VLDRBU8_rq
+  { 6, OperandInfo279 },  // Inst #1179 = MVE_VLDRDU64_qi
+  { 7, OperandInfo280 },  // Inst #1180 = MVE_VLDRDU64_qi_pre
+  { 6, OperandInfo276 },  // Inst #1181 = MVE_VLDRDU64_rq
+  { 6, OperandInfo276 },  // Inst #1182 = MVE_VLDRDU64_rq_u
+  { 6, OperandInfo274 },  // Inst #1183 = MVE_VLDRHS32
+  { 7, OperandInfo275 },  // Inst #1184 = MVE_VLDRHS32_post
+  { 7, OperandInfo275 },  // Inst #1185 = MVE_VLDRHS32_pre
+  { 6, OperandInfo276 },  // Inst #1186 = MVE_VLDRHS32_rq
+  { 6, OperandInfo276 },  // Inst #1187 = MVE_VLDRHS32_rq_u
+  { 6, OperandInfo277 },  // Inst #1188 = MVE_VLDRHU16
+  { 7, OperandInfo278 },  // Inst #1189 = MVE_VLDRHU16_post
+  { 7, OperandInfo278 },  // Inst #1190 = MVE_VLDRHU16_pre
+  { 6, OperandInfo276 },  // Inst #1191 = MVE_VLDRHU16_rq
+  { 6, OperandInfo276 },  // Inst #1192 = MVE_VLDRHU16_rq_u
+  { 6, OperandInfo274 },  // Inst #1193 = MVE_VLDRHU32
+  { 7, OperandInfo275 },  // Inst #1194 = MVE_VLDRHU32_post
+  { 7, OperandInfo275 },  // Inst #1195 = MVE_VLDRHU32_pre
+  { 6, OperandInfo276 },  // Inst #1196 = MVE_VLDRHU32_rq
+  { 6, OperandInfo276 },  // Inst #1197 = MVE_VLDRHU32_rq_u
+  { 6, OperandInfo277 },  // Inst #1198 = MVE_VLDRWU32
+  { 7, OperandInfo278 },  // Inst #1199 = MVE_VLDRWU32_post
+  { 7, OperandInfo278 },  // Inst #1200 = MVE_VLDRWU32_pre
+  { 6, OperandInfo279 },  // Inst #1201 = MVE_VLDRWU32_qi
+  { 7, OperandInfo280 },  // Inst #1202 = MVE_VLDRWU32_qi_pre
+  { 6, OperandInfo276 },  // Inst #1203 = MVE_VLDRWU32_rq
+  { 6, OperandInfo276 },  // Inst #1204 = MVE_VLDRWU32_rq_u
+  { 6, OperandInfo281 },  // Inst #1205 = MVE_VMAXAVs16
+  { 6, OperandInfo281 },  // Inst #1206 = MVE_VMAXAVs32
+  { 6, OperandInfo281 },  // Inst #1207 = MVE_VMAXAVs8
+  { 6, OperandInfo263 },  // Inst #1208 = MVE_VMAXAs16
+  { 6, OperandInfo263 },  // Inst #1209 = MVE_VMAXAs32
+  { 6, OperandInfo263 },  // Inst #1210 = MVE_VMAXAs8
+  { 6, OperandInfo281 },  // Inst #1211 = MVE_VMAXNMAVf16
+  { 6, OperandInfo281 },  // Inst #1212 = MVE_VMAXNMAVf32
+  { 6, OperandInfo263 },  // Inst #1213 = MVE_VMAXNMAf16
+  { 6, OperandInfo263 },  // Inst #1214 = MVE_VMAXNMAf32
+  { 6, OperandInfo281 },  // Inst #1215 = MVE_VMAXNMVf16
+  { 6, OperandInfo281 },  // Inst #1216 = MVE_VMAXNMVf32
+  { 7, OperandInfo247 },  // Inst #1217 = MVE_VMAXNMf16
+  { 7, OperandInfo247 },  // Inst #1218 = MVE_VMAXNMf32
+  { 6, OperandInfo281 },  // Inst #1219 = MVE_VMAXVs16
+  { 6, OperandInfo281 },  // Inst #1220 = MVE_VMAXVs32
+  { 6, OperandInfo281 },  // Inst #1221 = MVE_VMAXVs8
+  { 6, OperandInfo281 },  // Inst #1222 = MVE_VMAXVu16
+  { 6, OperandInfo281 },  // Inst #1223 = MVE_VMAXVu32
+  { 6, OperandInfo281 },  // Inst #1224 = MVE_VMAXVu8
+  { 7, OperandInfo247 },  // Inst #1225 = MVE_VMAXs16
+  { 7, OperandInfo247 },  // Inst #1226 = MVE_VMAXs32
+  { 7, OperandInfo247 },  // Inst #1227 = MVE_VMAXs8
+  { 7, OperandInfo247 },  // Inst #1228 = MVE_VMAXu16
+  { 7, OperandInfo247 },  // Inst #1229 = MVE_VMAXu32
+  { 7, OperandInfo247 },  // Inst #1230 = MVE_VMAXu8
+  { 6, OperandInfo281 },  // Inst #1231 = MVE_VMINAVs16
+  { 6, OperandInfo281 },  // Inst #1232 = MVE_VMINAVs32
+  { 6, OperandInfo281 },  // Inst #1233 = MVE_VMINAVs8
+  { 6, OperandInfo263 },  // Inst #1234 = MVE_VMINAs16
+  { 6, OperandInfo263 },  // Inst #1235 = MVE_VMINAs32
+  { 6, OperandInfo263 },  // Inst #1236 = MVE_VMINAs8
+  { 6, OperandInfo281 },  // Inst #1237 = MVE_VMINNMAVf16
+  { 6, OperandInfo281 },  // Inst #1238 = MVE_VMINNMAVf32
+  { 6, OperandInfo263 },  // Inst #1239 = MVE_VMINNMAf16
+  { 6, OperandInfo263 },  // Inst #1240 = MVE_VMINNMAf32
+  { 6, OperandInfo281 },  // Inst #1241 = MVE_VMINNMVf16
+  { 6, OperandInfo281 },  // Inst #1242 = MVE_VMINNMVf32
+  { 7, OperandInfo247 },  // Inst #1243 = MVE_VMINNMf16
+  { 7, OperandInfo247 },  // Inst #1244 = MVE_VMINNMf32
+  { 6, OperandInfo281 },  // Inst #1245 = MVE_VMINVs16
+  { 6, OperandInfo281 },  // Inst #1246 = MVE_VMINVs32
+  { 6, OperandInfo281 },  // Inst #1247 = MVE_VMINVs8
+  { 6, OperandInfo281 },  // Inst #1248 = MVE_VMINVu16
+  { 6, OperandInfo281 },  // Inst #1249 = MVE_VMINVu32
+  { 6, OperandInfo281 },  // Inst #1250 = MVE_VMINVu8
+  { 7, OperandInfo247 },  // Inst #1251 = MVE_VMINs16
+  { 7, OperandInfo247 },  // Inst #1252 = MVE_VMINs32
+  { 7, OperandInfo247 },  // Inst #1253 = MVE_VMINs8
+  { 7, OperandInfo247 },  // Inst #1254 = MVE_VMINu16
+  { 7, OperandInfo247 },  // Inst #1255 = MVE_VMINu32
+  { 7, OperandInfo247 },  // Inst #1256 = MVE_VMINu8
+  { 7, OperandInfo282 },  // Inst #1257 = MVE_VMLADAVas16
+  { 7, OperandInfo282 },  // Inst #1258 = MVE_VMLADAVas32
+  { 7, OperandInfo282 },  // Inst #1259 = MVE_VMLADAVas8
+  { 7, OperandInfo282 },  // Inst #1260 = MVE_VMLADAVau16
+  { 7, OperandInfo282 },  // Inst #1261 = MVE_VMLADAVau32
+  { 7, OperandInfo282 },  // Inst #1262 = MVE_VMLADAVau8
+  { 7, OperandInfo282 },  // Inst #1263 = MVE_VMLADAVaxs16
+  { 7, OperandInfo282 },  // Inst #1264 = MVE_VMLADAVaxs32
+  { 7, OperandInfo282 },  // Inst #1265 = MVE_VMLADAVaxs8
+  { 6, OperandInfo283 },  // Inst #1266 = MVE_VMLADAVs16
+  { 6, OperandInfo283 },  // Inst #1267 = MVE_VMLADAVs32
+  { 6, OperandInfo283 },  // Inst #1268 = MVE_VMLADAVs8
+  { 6, OperandInfo283 },  // Inst #1269 = MVE_VMLADAVu16
+  { 6, OperandInfo283 },  // Inst #1270 = MVE_VMLADAVu32
+  { 6, OperandInfo283 },  // Inst #1271 = MVE_VMLADAVu8
+  { 6, OperandInfo283 },  // Inst #1272 = MVE_VMLADAVxs16
+  { 6, OperandInfo283 },  // Inst #1273 = MVE_VMLADAVxs32
+  { 6, OperandInfo283 },  // Inst #1274 = MVE_VMLADAVxs8
+  { 9, OperandInfo284 },  // Inst #1275 = MVE_VMLALDAVas16
+  { 9, OperandInfo284 },  // Inst #1276 = MVE_VMLALDAVas32
+  { 9, OperandInfo284 },  // Inst #1277 = MVE_VMLALDAVau16
+  { 9, OperandInfo284 },  // Inst #1278 = MVE_VMLALDAVau32
+  { 9, OperandInfo284 },  // Inst #1279 = MVE_VMLALDAVaxs16
+  { 9, OperandInfo284 },  // Inst #1280 = MVE_VMLALDAVaxs32
+  { 7, OperandInfo285 },  // Inst #1281 = MVE_VMLALDAVs16
+  { 7, OperandInfo285 },  // Inst #1282 = MVE_VMLALDAVs32
+  { 7, OperandInfo285 },  // Inst #1283 = MVE_VMLALDAVu16
+  { 7, OperandInfo285 },  // Inst #1284 = MVE_VMLALDAVu32
+  { 7, OperandInfo285 },  // Inst #1285 = MVE_VMLALDAVxs16
+  { 7, OperandInfo285 },  // Inst #1286 = MVE_VMLALDAVxs32
+  { 7, OperandInfo268 },  // Inst #1287 = MVE_VMLAS_qr_i16
+  { 7, OperandInfo268 },  // Inst #1288 = MVE_VMLAS_qr_i32
+  { 7, OperandInfo268 },  // Inst #1289 = MVE_VMLAS_qr_i8
+  { 7, OperandInfo268 },  // Inst #1290 = MVE_VMLA_qr_i16
+  { 7, OperandInfo268 },  // Inst #1291 = MVE_VMLA_qr_i32
+  { 7, OperandInfo268 },  // Inst #1292 = MVE_VMLA_qr_i8
+  { 7, OperandInfo282 },  // Inst #1293 = MVE_VMLSDAVas16
+  { 7, OperandInfo282 },  // Inst #1294 = MVE_VMLSDAVas32
+  { 7, OperandInfo282 },  // Inst #1295 = MVE_VMLSDAVas8
+  { 7, OperandInfo282 },  // Inst #1296 = MVE_VMLSDAVaxs16
+  { 7, OperandInfo282 },  // Inst #1297 = MVE_VMLSDAVaxs32
+  { 7, OperandInfo282 },  // Inst #1298 = MVE_VMLSDAVaxs8
+  { 6, OperandInfo283 },  // Inst #1299 = MVE_VMLSDAVs16
+  { 6, OperandInfo283 },  // Inst #1300 = MVE_VMLSDAVs32
+  { 6, OperandInfo283 },  // Inst #1301 = MVE_VMLSDAVs8
+  { 6, OperandInfo283 },  // Inst #1302 = MVE_VMLSDAVxs16
+  { 6, OperandInfo283 },  // Inst #1303 = MVE_VMLSDAVxs32
+  { 6, OperandInfo283 },  // Inst #1304 = MVE_VMLSDAVxs8
+  { 9, OperandInfo284 },  // Inst #1305 = MVE_VMLSLDAVas16
+  { 9, OperandInfo284 },  // Inst #1306 = MVE_VMLSLDAVas32
+  { 9, OperandInfo284 },  // Inst #1307 = MVE_VMLSLDAVaxs16
+  { 9, OperandInfo284 },  // Inst #1308 = MVE_VMLSLDAVaxs32
+  { 7, OperandInfo285 },  // Inst #1309 = MVE_VMLSLDAVs16
+  { 7, OperandInfo285 },  // Inst #1310 = MVE_VMLSLDAVs32
+  { 7, OperandInfo285 },  // Inst #1311 = MVE_VMLSLDAVxs16
+  { 7, OperandInfo285 },  // Inst #1312 = MVE_VMLSLDAVxs32
+  { 6, OperandInfo248 },  // Inst #1313 = MVE_VMOVLs16bh
+  { 6, OperandInfo248 },  // Inst #1314 = MVE_VMOVLs16th
+  { 6, OperandInfo248 },  // Inst #1315 = MVE_VMOVLs8bh
+  { 6, OperandInfo248 },  // Inst #1316 = MVE_VMOVLs8th
+  { 6, OperandInfo248 },  // Inst #1317 = MVE_VMOVLu16bh
+  { 6, OperandInfo248 },  // Inst #1318 = MVE_VMOVLu16th
+  { 6, OperandInfo248 },  // Inst #1319 = MVE_VMOVLu8bh
+  { 6, OperandInfo248 },  // Inst #1320 = MVE_VMOVLu8th
+  { 6, OperandInfo263 },  // Inst #1321 = MVE_VMOVNi16bh
+  { 6, OperandInfo263 },  // Inst #1322 = MVE_VMOVNi16th
+  { 6, OperandInfo263 },  // Inst #1323 = MVE_VMOVNi32bh
+  { 6, OperandInfo263 },  // Inst #1324 = MVE_VMOVNi32th
+  { 5, OperandInfo286 },  // Inst #1325 = MVE_VMOV_from_lane_32
+  { 5, OperandInfo286 },  // Inst #1326 = MVE_VMOV_from_lane_s16
+  { 5, OperandInfo286 },  // Inst #1327 = MVE_VMOV_from_lane_s8
+  { 5, OperandInfo286 },  // Inst #1328 = MVE_VMOV_from_lane_u16
+  { 5, OperandInfo286 },  // Inst #1329 = MVE_VMOV_from_lane_u8
+  { 8, OperandInfo287 },  // Inst #1330 = MVE_VMOV_q_rr
+  { 7, OperandInfo288 },  // Inst #1331 = MVE_VMOV_rr_q
+  { 6, OperandInfo289 },  // Inst #1332 = MVE_VMOV_to_lane_16
+  { 6, OperandInfo289 },  // Inst #1333 = MVE_VMOV_to_lane_32
+  { 6, OperandInfo289 },  // Inst #1334 = MVE_VMOV_to_lane_8
+  { 6, OperandInfo290 },  // Inst #1335 = MVE_VMOVimmf32
+  { 6, OperandInfo290 },  // Inst #1336 = MVE_VMOVimmi16
+  { 6, OperandInfo290 },  // Inst #1337 = MVE_VMOVimmi32
+  { 6, OperandInfo290 },  // Inst #1338 = MVE_VMOVimmi64
+  { 6, OperandInfo290 },  // Inst #1339 = MVE_VMOVimmi8
+  { 7, OperandInfo247 },  // Inst #1340 = MVE_VMULHs16
+  { 7, OperandInfo247 },  // Inst #1341 = MVE_VMULHs32
+  { 7, OperandInfo247 },  // Inst #1342 = MVE_VMULHs8
+  { 7, OperandInfo247 },  // Inst #1343 = MVE_VMULHu16
+  { 7, OperandInfo247 },  // Inst #1344 = MVE_VMULHu32
+  { 7, OperandInfo247 },  // Inst #1345 = MVE_VMULHu8
+  { 7, OperandInfo247 },  // Inst #1346 = MVE_VMULLBp16
+  { 7, OperandInfo247 },  // Inst #1347 = MVE_VMULLBp8
+  { 7, OperandInfo247 },  // Inst #1348 = MVE_VMULLBs16
+  { 7, OperandInfo291 },  // Inst #1349 = MVE_VMULLBs32
+  { 7, OperandInfo247 },  // Inst #1350 = MVE_VMULLBs8
+  { 7, OperandInfo247 },  // Inst #1351 = MVE_VMULLBu16
+  { 7, OperandInfo291 },  // Inst #1352 = MVE_VMULLBu32
+  { 7, OperandInfo247 },  // Inst #1353 = MVE_VMULLBu8
+  { 7, OperandInfo247 },  // Inst #1354 = MVE_VMULLTp16
+  { 7, OperandInfo247 },  // Inst #1355 = MVE_VMULLTp8
+  { 7, OperandInfo247 },  // Inst #1356 = MVE_VMULLTs16
+  { 7, OperandInfo291 },  // Inst #1357 = MVE_VMULLTs32
+  { 7, OperandInfo247 },  // Inst #1358 = MVE_VMULLTs8
+  { 7, OperandInfo247 },  // Inst #1359 = MVE_VMULLTu16
+  { 7, OperandInfo291 },  // Inst #1360 = MVE_VMULLTu32
+  { 7, OperandInfo247 },  // Inst #1361 = MVE_VMULLTu8
+  { 7, OperandInfo255 },  // Inst #1362 = MVE_VMUL_qr_f16
+  { 7, OperandInfo255 },  // Inst #1363 = MVE_VMUL_qr_f32
+  { 7, OperandInfo255 },  // Inst #1364 = MVE_VMUL_qr_i16
+  { 7, OperandInfo255 },  // Inst #1365 = MVE_VMUL_qr_i32
+  { 7, OperandInfo255 },  // Inst #1366 = MVE_VMUL_qr_i8
+  { 7, OperandInfo247 },  // Inst #1367 = MVE_VMULf16
+  { 7, OperandInfo247 },  // Inst #1368 = MVE_VMULf32
+  { 7, OperandInfo247 },  // Inst #1369 = MVE_VMULi16
+  { 7, OperandInfo247 },  // Inst #1370 = MVE_VMULi32
+  { 7, OperandInfo247 },  // Inst #1371 = MVE_VMULi8
+  { 6, OperandInfo248 },  // Inst #1372 = MVE_VMVN
+  { 6, OperandInfo290 },  // Inst #1373 = MVE_VMVNimmi16
+  { 6, OperandInfo290 },  // Inst #1374 = MVE_VMVNimmi32
+  { 6, OperandInfo248 },  // Inst #1375 = MVE_VNEGf16
+  { 6, OperandInfo248 },  // Inst #1376 = MVE_VNEGf32
+  { 6, OperandInfo248 },  // Inst #1377 = MVE_VNEGs16
+  { 6, OperandInfo248 },  // Inst #1378 = MVE_VNEGs32
+  { 6, OperandInfo248 },  // Inst #1379 = MVE_VNEGs8
+  { 7, OperandInfo247 },  // Inst #1380 = MVE_VORN
+  { 7, OperandInfo247 },  // Inst #1381 = MVE_VORR
+  { 6, OperandInfo256 },  // Inst #1382 = MVE_VORRimmi16
+  { 6, OperandInfo256 },  // Inst #1383 = MVE_VORRimmi32
+  { 5, OperandInfo292 },  // Inst #1384 = MVE_VPNOT
+  { 6, OperandInfo293 },  // Inst #1385 = MVE_VPSEL
+  { 1, OperandInfo2 },  // Inst #1386 = MVE_VPST
+  { 4, OperandInfo294 },  // Inst #1387 = MVE_VPTv16i8
+  { 4, OperandInfo295 },  // Inst #1388 = MVE_VPTv16i8r
+  { 4, OperandInfo294 },  // Inst #1389 = MVE_VPTv16s8
+  { 4, OperandInfo295 },  // Inst #1390 = MVE_VPTv16s8r
+  { 4, OperandInfo294 },  // Inst #1391 = MVE_VPTv16u8
+  { 4, OperandInfo295 },  // Inst #1392 = MVE_VPTv16u8r
+  { 4, OperandInfo294 },  // Inst #1393 = MVE_VPTv4f32
+  { 4, OperandInfo295 },  // Inst #1394 = MVE_VPTv4f32r
+  { 4, OperandInfo294 },  // Inst #1395 = MVE_VPTv4i32
+  { 4, OperandInfo295 },  // Inst #1396 = MVE_VPTv4i32r
+  { 4, OperandInfo294 },  // Inst #1397 = MVE_VPTv4s32
+  { 4, OperandInfo295 },  // Inst #1398 = MVE_VPTv4s32r
+  { 4, OperandInfo294 },  // Inst #1399 = MVE_VPTv4u32
+  { 4, OperandInfo295 },  // Inst #1400 = MVE_VPTv4u32r
+  { 4, OperandInfo294 },  // Inst #1401 = MVE_VPTv8f16
+  { 4, OperandInfo295 },  // Inst #1402 = MVE_VPTv8f16r
+  { 4, OperandInfo294 },  // Inst #1403 = MVE_VPTv8i16
+  { 4, OperandInfo295 },  // Inst #1404 = MVE_VPTv8i16r
+  { 4, OperandInfo294 },  // Inst #1405 = MVE_VPTv8s16
+  { 4, OperandInfo295 },  // Inst #1406 = MVE_VPTv8s16r
+  { 4, OperandInfo294 },  // Inst #1407 = MVE_VPTv8u16
+  { 4, OperandInfo295 },  // Inst #1408 = MVE_VPTv8u16r
+  { 6, OperandInfo248 },  // Inst #1409 = MVE_VQABSs16
+  { 6, OperandInfo248 },  // Inst #1410 = MVE_VQABSs32
+  { 6, OperandInfo248 },  // Inst #1411 = MVE_VQABSs8
+  { 7, OperandInfo255 },  // Inst #1412 = MVE_VQADD_qr_s16
+  { 7, OperandInfo255 },  // Inst #1413 = MVE_VQADD_qr_s32
+  { 7, OperandInfo255 },  // Inst #1414 = MVE_VQADD_qr_s8
+  { 7, OperandInfo255 },  // Inst #1415 = MVE_VQADD_qr_u16
+  { 7, OperandInfo255 },  // Inst #1416 = MVE_VQADD_qr_u32
+  { 7, OperandInfo255 },  // Inst #1417 = MVE_VQADD_qr_u8
+  { 7, OperandInfo247 },  // Inst #1418 = MVE_VQADDs16
+  { 7, OperandInfo247 },  // Inst #1419 = MVE_VQADDs32
+  { 7, OperandInfo247 },  // Inst #1420 = MVE_VQADDs8
+  { 7, OperandInfo247 },  // Inst #1421 = MVE_VQADDu16
+  { 7, OperandInfo247 },  // Inst #1422 = MVE_VQADDu32
+  { 7, OperandInfo247 },  // Inst #1423 = MVE_VQADDu8
+  { 7, OperandInfo269 },  // Inst #1424 = MVE_VQDMLADHXs16
+  { 7, OperandInfo296 },  // Inst #1425 = MVE_VQDMLADHXs32
+  { 7, OperandInfo269 },  // Inst #1426 = MVE_VQDMLADHXs8
+  { 7, OperandInfo269 },  // Inst #1427 = MVE_VQDMLADHs16
+  { 7, OperandInfo296 },  // Inst #1428 = MVE_VQDMLADHs32
+  { 7, OperandInfo269 },  // Inst #1429 = MVE_VQDMLADHs8
+  { 7, OperandInfo268 },  // Inst #1430 = MVE_VQDMLAH_qrs16
+  { 7, OperandInfo268 },  // Inst #1431 = MVE_VQDMLAH_qrs32
+  { 7, OperandInfo268 },  // Inst #1432 = MVE_VQDMLAH_qrs8
+  { 7, OperandInfo268 },  // Inst #1433 = MVE_VQDMLASH_qrs16
+  { 7, OperandInfo268 },  // Inst #1434 = MVE_VQDMLASH_qrs32
+  { 7, OperandInfo268 },  // Inst #1435 = MVE_VQDMLASH_qrs8
+  { 7, OperandInfo269 },  // Inst #1436 = MVE_VQDMLSDHXs16
+  { 7, OperandInfo296 },  // Inst #1437 = MVE_VQDMLSDHXs32
+  { 7, OperandInfo269 },  // Inst #1438 = MVE_VQDMLSDHXs8
+  { 7, OperandInfo269 },  // Inst #1439 = MVE_VQDMLSDHs16
+  { 7, OperandInfo296 },  // Inst #1440 = MVE_VQDMLSDHs32
+  { 7, OperandInfo269 },  // Inst #1441 = MVE_VQDMLSDHs8
+  { 7, OperandInfo255 },  // Inst #1442 = MVE_VQDMULH_qr_s16
+  { 7, OperandInfo255 },  // Inst #1443 = MVE_VQDMULH_qr_s32
+  { 7, OperandInfo255 },  // Inst #1444 = MVE_VQDMULH_qr_s8
+  { 7, OperandInfo247 },  // Inst #1445 = MVE_VQDMULHi16
+  { 7, OperandInfo247 },  // Inst #1446 = MVE_VQDMULHi32
+  { 7, OperandInfo247 },  // Inst #1447 = MVE_VQDMULHi8
+  { 7, OperandInfo255 },  // Inst #1448 = MVE_VQDMULL_qr_s16bh
+  { 7, OperandInfo255 },  // Inst #1449 = MVE_VQDMULL_qr_s16th
+  { 7, OperandInfo297 },  // Inst #1450 = MVE_VQDMULL_qr_s32bh
+  { 7, OperandInfo297 },  // Inst #1451 = MVE_VQDMULL_qr_s32th
+  { 7, OperandInfo247 },  // Inst #1452 = MVE_VQDMULLs16bh
+  { 7, OperandInfo247 },  // Inst #1453 = MVE_VQDMULLs16th
+  { 7, OperandInfo291 },  // Inst #1454 = MVE_VQDMULLs32bh
+  { 7, OperandInfo291 },  // Inst #1455 = MVE_VQDMULLs32th
+  { 6, OperandInfo263 },  // Inst #1456 = MVE_VQMOVNs16bh
+  { 6, OperandInfo263 },  // Inst #1457 = MVE_VQMOVNs16th
+  { 6, OperandInfo263 },  // Inst #1458 = MVE_VQMOVNs32bh
+  { 6, OperandInfo263 },  // Inst #1459 = MVE_VQMOVNs32th
+  { 6, OperandInfo263 },  // Inst #1460 = MVE_VQMOVNu16bh
+  { 6, OperandInfo263 },  // Inst #1461 = MVE_VQMOVNu16th
+  { 6, OperandInfo263 },  // Inst #1462 = MVE_VQMOVNu32bh
+  { 6, OperandInfo263 },  // Inst #1463 = MVE_VQMOVNu32th
+  { 6, OperandInfo263 },  // Inst #1464 = MVE_VQMOVUNs16bh
+  { 6, OperandInfo263 },  // Inst #1465 = MVE_VQMOVUNs16th
+  { 6, OperandInfo263 },  // Inst #1466 = MVE_VQMOVUNs32bh
+  { 6, OperandInfo263 },  // Inst #1467 = MVE_VQMOVUNs32th
+  { 6, OperandInfo248 },  // Inst #1468 = MVE_VQNEGs16
+  { 6, OperandInfo248 },  // Inst #1469 = MVE_VQNEGs32
+  { 6, OperandInfo248 },  // Inst #1470 = MVE_VQNEGs8
+  { 7, OperandInfo269 },  // Inst #1471 = MVE_VQRDMLADHXs16
+  { 7, OperandInfo296 },  // Inst #1472 = MVE_VQRDMLADHXs32
+  { 7, OperandInfo269 },  // Inst #1473 = MVE_VQRDMLADHXs8
+  { 7, OperandInfo269 },  // Inst #1474 = MVE_VQRDMLADHs16
+  { 7, OperandInfo296 },  // Inst #1475 = MVE_VQRDMLADHs32
+  { 7, OperandInfo269 },  // Inst #1476 = MVE_VQRDMLADHs8
+  { 7, OperandInfo268 },  // Inst #1477 = MVE_VQRDMLAH_qrs16
+  { 7, OperandInfo268 },  // Inst #1478 = MVE_VQRDMLAH_qrs32
+  { 7, OperandInfo268 },  // Inst #1479 = MVE_VQRDMLAH_qrs8
+  { 7, OperandInfo268 },  // Inst #1480 = MVE_VQRDMLASH_qrs16
+  { 7, OperandInfo268 },  // Inst #1481 = MVE_VQRDMLASH_qrs32
+  { 7, OperandInfo268 },  // Inst #1482 = MVE_VQRDMLASH_qrs8
+  { 7, OperandInfo269 },  // Inst #1483 = MVE_VQRDMLSDHXs16
+  { 7, OperandInfo296 },  // Inst #1484 = MVE_VQRDMLSDHXs32
+  { 7, OperandInfo269 },  // Inst #1485 = MVE_VQRDMLSDHXs8
+  { 7, OperandInfo269 },  // Inst #1486 = MVE_VQRDMLSDHs16
+  { 7, OperandInfo296 },  // Inst #1487 = MVE_VQRDMLSDHs32
+  { 7, OperandInfo269 },  // Inst #1488 = MVE_VQRDMLSDHs8
+  { 7, OperandInfo255 },  // Inst #1489 = MVE_VQRDMULH_qr_s16
+  { 7, OperandInfo255 },  // Inst #1490 = MVE_VQRDMULH_qr_s32
+  { 7, OperandInfo255 },  // Inst #1491 = MVE_VQRDMULH_qr_s8
+  { 7, OperandInfo247 },  // Inst #1492 = MVE_VQRDMULHi16
+  { 7, OperandInfo247 },  // Inst #1493 = MVE_VQRDMULHi32
+  { 7, OperandInfo247 },  // Inst #1494 = MVE_VQRDMULHi8
+  { 7, OperandInfo247 },  // Inst #1495 = MVE_VQRSHL_by_vecs16
+  { 7, OperandInfo247 },  // Inst #1496 = MVE_VQRSHL_by_vecs32
+  { 7, OperandInfo247 },  // Inst #1497 = MVE_VQRSHL_by_vecs8
+  { 7, OperandInfo247 },  // Inst #1498 = MVE_VQRSHL_by_vecu16
+  { 7, OperandInfo247 },  // Inst #1499 = MVE_VQRSHL_by_vecu32
+  { 7, OperandInfo247 },  // Inst #1500 = MVE_VQRSHL_by_vecu8
+  { 6, OperandInfo298 },  // Inst #1501 = MVE_VQRSHL_qrs16
+  { 6, OperandInfo298 },  // Inst #1502 = MVE_VQRSHL_qrs32
+  { 6, OperandInfo298 },  // Inst #1503 = MVE_VQRSHL_qrs8
+  { 6, OperandInfo298 },  // Inst #1504 = MVE_VQRSHL_qru16
+  { 6, OperandInfo298 },  // Inst #1505 = MVE_VQRSHL_qru32
+  { 6, OperandInfo298 },  // Inst #1506 = MVE_VQRSHL_qru8
+  { 7, OperandInfo299 },  // Inst #1507 = MVE_VQRSHRNbhs16
+  { 7, OperandInfo299 },  // Inst #1508 = MVE_VQRSHRNbhs32
+  { 7, OperandInfo299 },  // Inst #1509 = MVE_VQRSHRNbhu16
+  { 7, OperandInfo299 },  // Inst #1510 = MVE_VQRSHRNbhu32
+  { 7, OperandInfo299 },  // Inst #1511 = MVE_VQRSHRNths16
+  { 7, OperandInfo299 },  // Inst #1512 = MVE_VQRSHRNths32
+  { 7, OperandInfo299 },  // Inst #1513 = MVE_VQRSHRNthu16
+  { 7, OperandInfo299 },  // Inst #1514 = MVE_VQRSHRNthu32
+  { 7, OperandInfo299 },  // Inst #1515 = MVE_VQRSHRUNs16bh
+  { 7, OperandInfo299 },  // Inst #1516 = MVE_VQRSHRUNs16th
+  { 7, OperandInfo299 },  // Inst #1517 = MVE_VQRSHRUNs32bh
+  { 7, OperandInfo299 },  // Inst #1518 = MVE_VQRSHRUNs32th
+  { 7, OperandInfo264 },  // Inst #1519 = MVE_VQSHLU_imms16
+  { 7, OperandInfo264 },  // Inst #1520 = MVE_VQSHLU_imms32
+  { 7, OperandInfo264 },  // Inst #1521 = MVE_VQSHLU_imms8
+  { 7, OperandInfo247 },  // Inst #1522 = MVE_VQSHL_by_vecs16
+  { 7, OperandInfo247 },  // Inst #1523 = MVE_VQSHL_by_vecs32
+  { 7, OperandInfo247 },  // Inst #1524 = MVE_VQSHL_by_vecs8
+  { 7, OperandInfo247 },  // Inst #1525 = MVE_VQSHL_by_vecu16
+  { 7, OperandInfo247 },  // Inst #1526 = MVE_VQSHL_by_vecu32
+  { 7, OperandInfo247 },  // Inst #1527 = MVE_VQSHL_by_vecu8
+  { 6, OperandInfo298 },  // Inst #1528 = MVE_VQSHL_qrs16
+  { 6, OperandInfo298 },  // Inst #1529 = MVE_VQSHL_qrs32
+  { 6, OperandInfo298 },  // Inst #1530 = MVE_VQSHL_qrs8
+  { 6, OperandInfo298 },  // Inst #1531 = MVE_VQSHL_qru16
+  { 6, OperandInfo298 },  // Inst #1532 = MVE_VQSHL_qru32
+  { 6, OperandInfo298 },  // Inst #1533 = MVE_VQSHL_qru8
+  { 7, OperandInfo264 },  // Inst #1534 = MVE_VQSHLimms16
+  { 7, OperandInfo264 },  // Inst #1535 = MVE_VQSHLimms32
+  { 7, OperandInfo264 },  // Inst #1536 = MVE_VQSHLimms8
+  { 7, OperandInfo264 },  // Inst #1537 = MVE_VQSHLimmu16
+  { 7, OperandInfo264 },  // Inst #1538 = MVE_VQSHLimmu32
+  { 7, OperandInfo264 },  // Inst #1539 = MVE_VQSHLimmu8
+  { 7, OperandInfo299 },  // Inst #1540 = MVE_VQSHRNbhs16
+  { 7, OperandInfo299 },  // Inst #1541 = MVE_VQSHRNbhs32
+  { 7, OperandInfo299 },  // Inst #1542 = MVE_VQSHRNbhu16
+  { 7, OperandInfo299 },  // Inst #1543 = MVE_VQSHRNbhu32
+  { 7, OperandInfo299 },  // Inst #1544 = MVE_VQSHRNths16
+  { 7, OperandInfo299 },  // Inst #1545 = MVE_VQSHRNths32
+  { 7, OperandInfo299 },  // Inst #1546 = MVE_VQSHRNthu16
+  { 7, OperandInfo299 },  // Inst #1547 = MVE_VQSHRNthu32
+  { 7, OperandInfo299 },  // Inst #1548 = MVE_VQSHRUNs16bh
+  { 7, OperandInfo299 },  // Inst #1549 = MVE_VQSHRUNs16th
+  { 7, OperandInfo299 },  // Inst #1550 = MVE_VQSHRUNs32bh
+  { 7, OperandInfo299 },  // Inst #1551 = MVE_VQSHRUNs32th
+  { 7, OperandInfo255 },  // Inst #1552 = MVE_VQSUB_qr_s16
+  { 7, OperandInfo255 },  // Inst #1553 = MVE_VQSUB_qr_s32
+  { 7, OperandInfo255 },  // Inst #1554 = MVE_VQSUB_qr_s8
+  { 7, OperandInfo255 },  // Inst #1555 = MVE_VQSUB_qr_u16
+  { 7, OperandInfo255 },  // Inst #1556 = MVE_VQSUB_qr_u32
+  { 7, OperandInfo255 },  // Inst #1557 = MVE_VQSUB_qr_u8
+  { 7, OperandInfo247 },  // Inst #1558 = MVE_VQSUBs16
+  { 7, OperandInfo247 },  // Inst #1559 = MVE_VQSUBs32
+  { 7, OperandInfo247 },  // Inst #1560 = MVE_VQSUBs8
+  { 7, OperandInfo247 },  // Inst #1561 = MVE_VQSUBu16
+  { 7, OperandInfo247 },  // Inst #1562 = MVE_VQSUBu32
+  { 7, OperandInfo247 },  // Inst #1563 = MVE_VQSUBu8
+  { 6, OperandInfo248 },  // Inst #1564 = MVE_VREV16_8
+  { 6, OperandInfo248 },  // Inst #1565 = MVE_VREV32_16
+  { 6, OperandInfo248 },  // Inst #1566 = MVE_VREV32_8
+  { 6, OperandInfo300 },  // Inst #1567 = MVE_VREV64_16
+  { 6, OperandInfo300 },  // Inst #1568 = MVE_VREV64_32
+  { 6, OperandInfo300 },  // Inst #1569 = MVE_VREV64_8
+  { 7, OperandInfo247 },  // Inst #1570 = MVE_VRHADDs16
+  { 7, OperandInfo247 },  // Inst #1571 = MVE_VRHADDs32
+  { 7, OperandInfo247 },  // Inst #1572 = MVE_VRHADDs8
+  { 7, OperandInfo247 },  // Inst #1573 = MVE_VRHADDu16
+  { 7, OperandInfo247 },  // Inst #1574 = MVE_VRHADDu32
+  { 7, OperandInfo247 },  // Inst #1575 = MVE_VRHADDu8
+  { 6, OperandInfo248 },  // Inst #1576 = MVE_VRINTf16A
+  { 6, OperandInfo248 },  // Inst #1577 = MVE_VRINTf16M
+  { 6, OperandInfo248 },  // Inst #1578 = MVE_VRINTf16N
+  { 6, OperandInfo248 },  // Inst #1579 = MVE_VRINTf16P
+  { 6, OperandInfo248 },  // Inst #1580 = MVE_VRINTf16X
+  { 6, OperandInfo248 },  // Inst #1581 = MVE_VRINTf16Z
+  { 6, OperandInfo248 },  // Inst #1582 = MVE_VRINTf32A
+  { 6, OperandInfo248 },  // Inst #1583 = MVE_VRINTf32M
+  { 6, OperandInfo248 },  // Inst #1584 = MVE_VRINTf32N
+  { 6, OperandInfo248 },  // Inst #1585 = MVE_VRINTf32P
+  { 6, OperandInfo248 },  // Inst #1586 = MVE_VRINTf32X
+  { 6, OperandInfo248 },  // Inst #1587 = MVE_VRINTf32Z
+  { 9, OperandInfo284 },  // Inst #1588 = MVE_VRMLALDAVHas32
+  { 9, OperandInfo284 },  // Inst #1589 = MVE_VRMLALDAVHau32
+  { 9, OperandInfo284 },  // Inst #1590 = MVE_VRMLALDAVHaxs32
+  { 7, OperandInfo285 },  // Inst #1591 = MVE_VRMLALDAVHs32
+  { 7, OperandInfo285 },  // Inst #1592 = MVE_VRMLALDAVHu32
+  { 7, OperandInfo285 },  // Inst #1593 = MVE_VRMLALDAVHxs32
+  { 9, OperandInfo284 },  // Inst #1594 = MVE_VRMLSLDAVHas32
+  { 9, OperandInfo284 },  // Inst #1595 = MVE_VRMLSLDAVHaxs32
+  { 7, OperandInfo285 },  // Inst #1596 = MVE_VRMLSLDAVHs32
+  { 7, OperandInfo285 },  // Inst #1597 = MVE_VRMLSLDAVHxs32
+  { 7, OperandInfo247 },  // Inst #1598 = MVE_VRMULHs16
+  { 7, OperandInfo247 },  // Inst #1599 = MVE_VRMULHs32
+  { 7, OperandInfo247 },  // Inst #1600 = MVE_VRMULHs8
+  { 7, OperandInfo247 },  // Inst #1601 = MVE_VRMULHu16
+  { 7, OperandInfo247 },  // Inst #1602 = MVE_VRMULHu32
+  { 7, OperandInfo247 },  // Inst #1603 = MVE_VRMULHu8
+  { 7, OperandInfo247 },  // Inst #1604 = MVE_VRSHL_by_vecs16
+  { 7, OperandInfo247 },  // Inst #1605 = MVE_VRSHL_by_vecs32
+  { 7, OperandInfo247 },  // Inst #1606 = MVE_VRSHL_by_vecs8
+  { 7, OperandInfo247 },  // Inst #1607 = MVE_VRSHL_by_vecu16
+  { 7, OperandInfo247 },  // Inst #1608 = MVE_VRSHL_by_vecu32
+  { 7, OperandInfo247 },  // Inst #1609 = MVE_VRSHL_by_vecu8
+  { 6, OperandInfo298 },  // Inst #1610 = MVE_VRSHL_qrs16
+  { 6, OperandInfo298 },  // Inst #1611 = MVE_VRSHL_qrs32
+  { 6, OperandInfo298 },  // Inst #1612 = MVE_VRSHL_qrs8
+  { 6, OperandInfo298 },  // Inst #1613 = MVE_VRSHL_qru16
+  { 6, OperandInfo298 },  // Inst #1614 = MVE_VRSHL_qru32
+  { 6, OperandInfo298 },  // Inst #1615 = MVE_VRSHL_qru8
+  { 7, OperandInfo299 },  // Inst #1616 = MVE_VRSHRNi16bh
+  { 7, OperandInfo299 },  // Inst #1617 = MVE_VRSHRNi16th
+  { 7, OperandInfo299 },  // Inst #1618 = MVE_VRSHRNi32bh
+  { 7, OperandInfo299 },  // Inst #1619 = MVE_VRSHRNi32th
+  { 7, OperandInfo264 },  // Inst #1620 = MVE_VRSHR_imms16
+  { 7, OperandInfo264 },  // Inst #1621 = MVE_VRSHR_imms32
+  { 7, OperandInfo264 },  // Inst #1622 = MVE_VRSHR_imms8
+  { 7, OperandInfo264 },  // Inst #1623 = MVE_VRSHR_immu16
+  { 7, OperandInfo264 },  // Inst #1624 = MVE_VRSHR_immu32
+  { 7, OperandInfo264 },  // Inst #1625 = MVE_VRSHR_immu8
+  { 9, OperandInfo249 },  // Inst #1626 = MVE_VSBC
+  { 8, OperandInfo250 },  // Inst #1627 = MVE_VSBCI
+  { 8, OperandInfo301 },  // Inst #1628 = MVE_VSHLC
+  { 7, OperandInfo264 },  // Inst #1629 = MVE_VSHLL_imms16bh
+  { 7, OperandInfo264 },  // Inst #1630 = MVE_VSHLL_imms16th
+  { 7, OperandInfo264 },  // Inst #1631 = MVE_VSHLL_imms8bh
+  { 7, OperandInfo264 },  // Inst #1632 = MVE_VSHLL_imms8th
+  { 7, OperandInfo264 },  // Inst #1633 = MVE_VSHLL_immu16bh
+  { 7, OperandInfo264 },  // Inst #1634 = MVE_VSHLL_immu16th
+  { 7, OperandInfo264 },  // Inst #1635 = MVE_VSHLL_immu8bh
+  { 7, OperandInfo264 },  // Inst #1636 = MVE_VSHLL_immu8th
+  { 6, OperandInfo248 },  // Inst #1637 = MVE_VSHLL_lws16bh
+  { 6, OperandInfo248 },  // Inst #1638 = MVE_VSHLL_lws16th
+  { 6, OperandInfo248 },  // Inst #1639 = MVE_VSHLL_lws8bh
+  { 6, OperandInfo248 },  // Inst #1640 = MVE_VSHLL_lws8th
+  { 6, OperandInfo248 },  // Inst #1641 = MVE_VSHLL_lwu16bh
+  { 6, OperandInfo248 },  // Inst #1642 = MVE_VSHLL_lwu16th
+  { 6, OperandInfo248 },  // Inst #1643 = MVE_VSHLL_lwu8bh
+  { 6, OperandInfo248 },  // Inst #1644 = MVE_VSHLL_lwu8th
+  { 7, OperandInfo247 },  // Inst #1645 = MVE_VSHL_by_vecs16
+  { 7, OperandInfo247 },  // Inst #1646 = MVE_VSHL_by_vecs32
+  { 7, OperandInfo247 },  // Inst #1647 = MVE_VSHL_by_vecs8
+  { 7, OperandInfo247 },  // Inst #1648 = MVE_VSHL_by_vecu16
+  { 7, OperandInfo247 },  // Inst #1649 = MVE_VSHL_by_vecu32
+  { 7, OperandInfo247 },  // Inst #1650 = MVE_VSHL_by_vecu8
+  { 7, OperandInfo264 },  // Inst #1651 = MVE_VSHL_immi16
+  { 7, OperandInfo264 },  // Inst #1652 = MVE_VSHL_immi32
+  { 7, OperandInfo264 },  // Inst #1653 = MVE_VSHL_immi8
+  { 6, OperandInfo298 },  // Inst #1654 = MVE_VSHL_qrs16
+  { 6, OperandInfo298 },  // Inst #1655 = MVE_VSHL_qrs32
+  { 6, OperandInfo298 },  // Inst #1656 = MVE_VSHL_qrs8
+  { 6, OperandInfo298 },  // Inst #1657 = MVE_VSHL_qru16
+  { 6, OperandInfo298 },  // Inst #1658 = MVE_VSHL_qru32
+  { 6, OperandInfo298 },  // Inst #1659 = MVE_VSHL_qru8
+  { 7, OperandInfo299 },  // Inst #1660 = MVE_VSHRNi16bh
+  { 7, OperandInfo299 },  // Inst #1661 = MVE_VSHRNi16th
+  { 7, OperandInfo299 },  // Inst #1662 = MVE_VSHRNi32bh
+  { 7, OperandInfo299 },  // Inst #1663 = MVE_VSHRNi32th
+  { 7, OperandInfo264 },  // Inst #1664 = MVE_VSHR_imms16
+  { 7, OperandInfo264 },  // Inst #1665 = MVE_VSHR_imms32
+  { 7, OperandInfo264 },  // Inst #1666 = MVE_VSHR_imms8
+  { 7, OperandInfo264 },  // Inst #1667 = MVE_VSHR_immu16
+  { 7, OperandInfo264 },  // Inst #1668 = MVE_VSHR_immu32
+  { 7, OperandInfo264 },  // Inst #1669 = MVE_VSHR_immu8
+  { 7, OperandInfo299 },  // Inst #1670 = MVE_VSLIimm16
+  { 7, OperandInfo299 },  // Inst #1671 = MVE_VSLIimm32
+  { 7, OperandInfo299 },  // Inst #1672 = MVE_VSLIimm8
+  { 7, OperandInfo299 },  // Inst #1673 = MVE_VSRIimm16
+  { 7, OperandInfo299 },  // Inst #1674 = MVE_VSRIimm32
+  { 7, OperandInfo299 },  // Inst #1675 = MVE_VSRIimm8
+  { 2, OperandInfo302 },  // Inst #1676 = MVE_VST20_16
+  { 3, OperandInfo303 },  // Inst #1677 = MVE_VST20_16_wb
+  { 2, OperandInfo302 },  // Inst #1678 = MVE_VST20_32
+  { 3, OperandInfo303 },  // Inst #1679 = MVE_VST20_32_wb
+  { 2, OperandInfo302 },  // Inst #1680 = MVE_VST20_8
+  { 3, OperandInfo303 },  // Inst #1681 = MVE_VST20_8_wb
+  { 2, OperandInfo302 },  // Inst #1682 = MVE_VST21_16
+  { 3, OperandInfo303 },  // Inst #1683 = MVE_VST21_16_wb
+  { 2, OperandInfo302 },  // Inst #1684 = MVE_VST21_32
+  { 3, OperandInfo303 },  // Inst #1685 = MVE_VST21_32_wb
+  { 2, OperandInfo302 },  // Inst #1686 = MVE_VST21_8
+  { 3, OperandInfo303 },  // Inst #1687 = MVE_VST21_8_wb
+  { 2, OperandInfo304 },  // Inst #1688 = MVE_VST40_16
+  { 3, OperandInfo305 },  // Inst #1689 = MVE_VST40_16_wb
+  { 2, OperandInfo304 },  // Inst #1690 = MVE_VST40_32
+  { 3, OperandInfo305 },  // Inst #1691 = MVE_VST40_32_wb
+  { 2, OperandInfo304 },  // Inst #1692 = MVE_VST40_8
+  { 3, OperandInfo305 },  // Inst #1693 = MVE_VST40_8_wb
+  { 2, OperandInfo304 },  // Inst #1694 = MVE_VST41_16
+  { 3, OperandInfo305 },  // Inst #1695 = MVE_VST41_16_wb
+  { 2, OperandInfo304 },  // Inst #1696 = MVE_VST41_32
+  { 3, OperandInfo305 },  // Inst #1697 = MVE_VST41_32_wb
+  { 2, OperandInfo304 },  // Inst #1698 = MVE_VST41_8
+  { 3, OperandInfo305 },  // Inst #1699 = MVE_VST41_8_wb
+  { 2, OperandInfo304 },  // Inst #1700 = MVE_VST42_16
+  { 3, OperandInfo305 },  // Inst #1701 = MVE_VST42_16_wb
+  { 2, OperandInfo304 },  // Inst #1702 = MVE_VST42_32
+  { 3, OperandInfo305 },  // Inst #1703 = MVE_VST42_32_wb
+  { 2, OperandInfo304 },  // Inst #1704 = MVE_VST42_8
+  { 3, OperandInfo305 },  // Inst #1705 = MVE_VST42_8_wb
+  { 2, OperandInfo304 },  // Inst #1706 = MVE_VST43_16
+  { 3, OperandInfo305 },  // Inst #1707 = MVE_VST43_16_wb
+  { 2, OperandInfo304 },  // Inst #1708 = MVE_VST43_32
+  { 3, OperandInfo305 },  // Inst #1709 = MVE_VST43_32_wb
+  { 2, OperandInfo304 },  // Inst #1710 = MVE_VST43_8
+  { 3, OperandInfo305 },  // Inst #1711 = MVE_VST43_8_wb
+  { 6, OperandInfo274 },  // Inst #1712 = MVE_VSTRB16
+  { 7, OperandInfo275 },  // Inst #1713 = MVE_VSTRB16_post
+  { 7, OperandInfo275 },  // Inst #1714 = MVE_VSTRB16_pre
+  { 6, OperandInfo306 },  // Inst #1715 = MVE_VSTRB16_rq
+  { 6, OperandInfo274 },  // Inst #1716 = MVE_VSTRB32
+  { 7, OperandInfo275 },  // Inst #1717 = MVE_VSTRB32_post
+  { 7, OperandInfo275 },  // Inst #1718 = MVE_VSTRB32_pre
+  { 6, OperandInfo306 },  // Inst #1719 = MVE_VSTRB32_rq
+  { 6, OperandInfo306 },  // Inst #1720 = MVE_VSTRB8_rq
+  { 6, OperandInfo277 },  // Inst #1721 = MVE_VSTRBU8
+  { 7, OperandInfo278 },  // Inst #1722 = MVE_VSTRBU8_post
+  { 7, OperandInfo278 },  // Inst #1723 = MVE_VSTRBU8_pre
+  { 6, OperandInfo307 },  // Inst #1724 = MVE_VSTRD64_qi
+  { 7, OperandInfo308 },  // Inst #1725 = MVE_VSTRD64_qi_pre
+  { 6, OperandInfo306 },  // Inst #1726 = MVE_VSTRD64_rq
+  { 6, OperandInfo306 },  // Inst #1727 = MVE_VSTRD64_rq_u
+  { 6, OperandInfo306 },  // Inst #1728 = MVE_VSTRH16_rq
+  { 6, OperandInfo306 },  // Inst #1729 = MVE_VSTRH16_rq_u
+  { 6, OperandInfo274 },  // Inst #1730 = MVE_VSTRH32
+  { 7, OperandInfo275 },  // Inst #1731 = MVE_VSTRH32_post
+  { 7, OperandInfo275 },  // Inst #1732 = MVE_VSTRH32_pre
+  { 6, OperandInfo306 },  // Inst #1733 = MVE_VSTRH32_rq
+  { 6, OperandInfo306 },  // Inst #1734 = MVE_VSTRH32_rq_u
+  { 6, OperandInfo277 },  // Inst #1735 = MVE_VSTRHU16
+  { 7, OperandInfo278 },  // Inst #1736 = MVE_VSTRHU16_post
+  { 7, OperandInfo278 },  // Inst #1737 = MVE_VSTRHU16_pre
+  { 6, OperandInfo307 },  // Inst #1738 = MVE_VSTRW32_qi
+  { 7, OperandInfo308 },  // Inst #1739 = MVE_VSTRW32_qi_pre
+  { 6, OperandInfo306 },  // Inst #1740 = MVE_VSTRW32_rq
+  { 6, OperandInfo306 },  // Inst #1741 = MVE_VSTRW32_rq_u
+  { 6, OperandInfo277 },  // Inst #1742 = MVE_VSTRWU32
+  { 7, OperandInfo278 },  // Inst #1743 = MVE_VSTRWU32_post
+  { 7, OperandInfo278 },  // Inst #1744 = MVE_VSTRWU32_pre
+  { 7, OperandInfo255 },  // Inst #1745 = MVE_VSUB_qr_f16
+  { 7, OperandInfo255 },  // Inst #1746 = MVE_VSUB_qr_f32
+  { 7, OperandInfo255 },  // Inst #1747 = MVE_VSUB_qr_i16
+  { 7, OperandInfo255 },  // Inst #1748 = MVE_VSUB_qr_i32
+  { 7, OperandInfo255 },  // Inst #1749 = MVE_VSUB_qr_i8
+  { 7, OperandInfo247 },  // Inst #1750 = MVE_VSUBf16
+  { 7, OperandInfo247 },  // Inst #1751 = MVE_VSUBf32
+  { 7, OperandInfo247 },  // Inst #1752 = MVE_VSUBi16
+  { 7, OperandInfo247 },  // Inst #1753 = MVE_VSUBi32
+  { 7, OperandInfo247 },  // Inst #1754 = MVE_VSUBi8
+  { 3, OperandInfo129 },  // Inst #1755 = MVE_WLSTP_16
+  { 3, OperandInfo129 },  // Inst #1756 = MVE_WLSTP_32
+  { 3, OperandInfo129 },  // Inst #1757 = MVE_WLSTP_64
+  { 3, OperandInfo129 },  // Inst #1758 = MVE_WLSTP_8
+  { 5, OperandInfo231 },  // Inst #1759 = MVNi
+  { 5, OperandInfo88 },  // Inst #1760 = MVNr
+  { 6, OperandInfo233 },  // Inst #1761 = MVNsi
+  { 7, OperandInfo309 },  // Inst #1762 = MVNsr
+  { 3, OperandInfo310 },  // Inst #1763 = NEON_VMAXNMNDf
+  { 3, OperandInfo310 },  // Inst #1764 = NEON_VMAXNMNDh
+  { 3, OperandInfo311 },  // Inst #1765 = NEON_VMAXNMNQf
+  { 3, OperandInfo311 },  // Inst #1766 = NEON_VMAXNMNQh
+  { 3, OperandInfo310 },  // Inst #1767 = NEON_VMINNMNDf
+  { 3, OperandInfo310 },  // Inst #1768 = NEON_VMINNMNDh
+  { 3, OperandInfo311 },  // Inst #1769 = NEON_VMINNMNQf
+  { 3, OperandInfo311 },  // Inst #1770 = NEON_VMINNMNQh
+  { 6, OperandInfo51 },  // Inst #1771 = ORRri
+  { 6, OperandInfo153 },  // Inst #1772 = ORRrr
+  { 7, OperandInfo154 },  // Inst #1773 = ORRrsi
+  { 8, OperandInfo156 },  // Inst #1774 = ORRrsr
+  { 6, OperandInfo312 },  // Inst #1775 = PKHBT
+  { 6, OperandInfo312 },  // Inst #1776 = PKHTB
+  { 2, OperandInfo313 },  // Inst #1777 = PLDWi12
+  { 3, OperandInfo314 },  // Inst #1778 = PLDWrs
+  { 2, OperandInfo313 },  // Inst #1779 = PLDi12
+  { 3, OperandInfo314 },  // Inst #1780 = PLDrs
+  { 2, OperandInfo313 },  // Inst #1781 = PLIi12
+  { 3, OperandInfo314 },  // Inst #1782 = PLIrs
+  { 5, OperandInfo315 },  // Inst #1783 = QADD
+  { 5, OperandInfo315 },  // Inst #1784 = QADD16
+  { 5, OperandInfo315 },  // Inst #1785 = QADD8
+  { 5, OperandInfo315 },  // Inst #1786 = QASX
+  { 5, OperandInfo315 },  // Inst #1787 = QDADD
+  { 5, OperandInfo315 },  // Inst #1788 = QDSUB
+  { 5, OperandInfo315 },  // Inst #1789 = QSAX
+  { 5, OperandInfo315 },  // Inst #1790 = QSUB
+  { 5, OperandInfo315 },  // Inst #1791 = QSUB16
+  { 5, OperandInfo315 },  // Inst #1792 = QSUB8
+  { 4, OperandInfo197 },  // Inst #1793 = RBIT
+  { 4, OperandInfo197 },  // Inst #1794 = REV
+  { 4, OperandInfo197 },  // Inst #1795 = REV16
+  { 4, OperandInfo197 },  // Inst #1796 = REVSH
+  { 1, OperandInfo78 },  // Inst #1797 = RFEDA
+  { 2, OperandInfo316 },  // Inst #1798 = RFEDA_UPD
+  { 1, OperandInfo78 },  // Inst #1799 = RFEDB
+  { 2, OperandInfo316 },  // Inst #1800 = RFEDB_UPD
+  { 1, OperandInfo78 },  // Inst #1801 = RFEIA
+  { 2, OperandInfo316 },  // Inst #1802 = RFEIA_UPD
+  { 1, OperandInfo78 },  // Inst #1803 = RFEIB
+  { 2, OperandInfo316 },  // Inst #1804 = RFEIB_UPD
+  { 6, OperandInfo51 },  // Inst #1805 = RSBri
+  { 6, OperandInfo153 },  // Inst #1806 = RSBrr
+  { 7, OperandInfo154 },  // Inst #1807 = RSBrsi
+  { 8, OperandInfo156 },  // Inst #1808 = RSBrsr
+  { 6, OperandInfo51 },  // Inst #1809 = RSCri
+  { 6, OperandInfo153 },  // Inst #1810 = RSCrr
+  { 7, OperandInfo154 },  // Inst #1811 = RSCrsi
+  { 8, OperandInfo156 },  // Inst #1812 = RSCrsr
+  { 5, OperandInfo315 },  // Inst #1813 = SADD16
+  { 5, OperandInfo315 },  // Inst #1814 = SADD8
+  { 5, OperandInfo315 },  // Inst #1815 = SASX
+  { 0, 0 },  // Inst #1816 = SB
+  { 6, OperandInfo51 },  // Inst #1817 = SBCri
+  { 6, OperandInfo153 },  // Inst #1818 = SBCrr
+  { 7, OperandInfo154 },  // Inst #1819 = SBCrsi
+  { 8, OperandInfo155 },  // Inst #1820 = SBCrsr
+  { 6, OperandInfo317 },  // Inst #1821 = SBFX
+  { 5, OperandInfo47 },  // Inst #1822 = SDIV
+  { 5, OperandInfo47 },  // Inst #1823 = SEL
+  { 1, OperandInfo2 },  // Inst #1824 = SETEND
+  { 1, OperandInfo2 },  // Inst #1825 = SETPAN
+  { 4, OperandInfo162 },  // Inst #1826 = SHA1C
+  { 2, OperandInfo158 },  // Inst #1827 = SHA1H
+  { 4, OperandInfo162 },  // Inst #1828 = SHA1M
+  { 4, OperandInfo162 },  // Inst #1829 = SHA1P
+  { 4, OperandInfo162 },  // Inst #1830 = SHA1SU0
+  { 3, OperandInfo157 },  // Inst #1831 = SHA1SU1
+  { 4, OperandInfo162 },  // Inst #1832 = SHA256H
+  { 4, OperandInfo162 },  // Inst #1833 = SHA256H2
+  { 3, OperandInfo157 },  // Inst #1834 = SHA256SU0
+  { 4, OperandInfo162 },  // Inst #1835 = SHA256SU1
+  { 5, OperandInfo315 },  // Inst #1836 = SHADD16
+  { 5, OperandInfo315 },  // Inst #1837 = SHADD8
+  { 5, OperandInfo315 },  // Inst #1838 = SHASX
+  { 5, OperandInfo315 },  // Inst #1839 = SHSAX
+  { 5, OperandInfo315 },  // Inst #1840 = SHSUB16
+  { 5, OperandInfo315 },  // Inst #1841 = SHSUB8
+  { 3, OperandInfo202 },  // Inst #1842 = SMC
+  { 6, OperandInfo318 },  // Inst #1843 = SMLABB
+  { 6, OperandInfo318 },  // Inst #1844 = SMLABT
+  { 6, OperandInfo318 },  // Inst #1845 = SMLAD
+  { 6, OperandInfo318 },  // Inst #1846 = SMLADX
+  { 9, OperandInfo319 },  // Inst #1847 = SMLAL
+  { 8, OperandInfo320 },  // Inst #1848 = SMLALBB
+  { 8, OperandInfo320 },  // Inst #1849 = SMLALBT
+  { 8, OperandInfo320 },  // Inst #1850 = SMLALD
+  { 8, OperandInfo320 },  // Inst #1851 = SMLALDX
+  { 8, OperandInfo320 },  // Inst #1852 = SMLALTB
+  { 8, OperandInfo320 },  // Inst #1853 = SMLALTT
+  { 6, OperandInfo318 },  // Inst #1854 = SMLATB
+  { 6, OperandInfo318 },  // Inst #1855 = SMLATT
+  { 6, OperandInfo318 },  // Inst #1856 = SMLAWB
+  { 6, OperandInfo318 },  // Inst #1857 = SMLAWT
+  { 6, OperandInfo318 },  // Inst #1858 = SMLSD
+  { 6, OperandInfo318 },  // Inst #1859 = SMLSDX
+  { 8, OperandInfo320 },  // Inst #1860 = SMLSLD
+  { 8, OperandInfo320 },  // Inst #1861 = SMLSLDX
+  { 6, OperandInfo229 },  // Inst #1862 = SMMLA
+  { 6, OperandInfo229 },  // Inst #1863 = SMMLAR
+  { 6, OperandInfo229 },  // Inst #1864 = SMMLS
+  { 6, OperandInfo229 },  // Inst #1865 = SMMLSR
+  { 5, OperandInfo47 },  // Inst #1866 = SMMUL
+  { 5, OperandInfo47 },  // Inst #1867 = SMMULR
+  { 5, OperandInfo315 },  // Inst #1868 = SMUAD
+  { 5, OperandInfo315 },  // Inst #1869 = SMUADX
+  { 5, OperandInfo47 },  // Inst #1870 = SMULBB
+  { 5, OperandInfo47 },  // Inst #1871 = SMULBT
+  { 7, OperandInfo321 },  // Inst #1872 = SMULL
+  { 5, OperandInfo47 },  // Inst #1873 = SMULTB
+  { 5, OperandInfo47 },  // Inst #1874 = SMULTT
+  { 5, OperandInfo47 },  // Inst #1875 = SMULWB
+  { 5, OperandInfo47 },  // Inst #1876 = SMULWT
+  { 5, OperandInfo315 },  // Inst #1877 = SMUSD
+  { 5, OperandInfo315 },  // Inst #1878 = SMUSDX
+  { 1, OperandInfo2 },  // Inst #1879 = SRSDA
+  { 1, OperandInfo2 },  // Inst #1880 = SRSDA_UPD
+  { 1, OperandInfo2 },  // Inst #1881 = SRSDB
+  { 1, OperandInfo2 },  // Inst #1882 = SRSDB_UPD
+  { 1, OperandInfo2 },  // Inst #1883 = SRSIA
+  { 1, OperandInfo2 },  // Inst #1884 = SRSIA_UPD
+  { 1, OperandInfo2 },  // Inst #1885 = SRSIB
+  { 1, OperandInfo2 },  // Inst #1886 = SRSIB_UPD
+  { 6, OperandInfo322 },  // Inst #1887 = SSAT
+  { 5, OperandInfo323 },  // Inst #1888 = SSAT16
+  { 5, OperandInfo315 },  // Inst #1889 = SSAX
+  { 5, OperandInfo315 },  // Inst #1890 = SSUB16
+  { 5, OperandInfo315 },  // Inst #1891 = SSUB8
+  { 4, OperandInfo208 },  // Inst #1892 = STC2L_OFFSET
+  { 4, OperandInfo209 },  // Inst #1893 = STC2L_OPTION
+  { 4, OperandInfo208 },  // Inst #1894 = STC2L_POST
+  { 5, OperandInfo210 },  // Inst #1895 = STC2L_PRE
+  { 4, OperandInfo208 },  // Inst #1896 = STC2_OFFSET
+  { 4, OperandInfo209 },  // Inst #1897 = STC2_OPTION
+  { 4, OperandInfo208 },  // Inst #1898 = STC2_POST
+  { 5, OperandInfo210 },  // Inst #1899 = STC2_PRE
+  { 6, OperandInfo211 },  // Inst #1900 = STCL_OFFSET
+  { 6, OperandInfo212 },  // Inst #1901 = STCL_OPTION
+  { 6, OperandInfo211 },  // Inst #1902 = STCL_POST
+  { 7, OperandInfo213 },  // Inst #1903 = STCL_PRE
+  { 6, OperandInfo211 },  // Inst #1904 = STC_OFFSET
+  { 6, OperandInfo212 },  // Inst #1905 = STC_OPTION
+  { 6, OperandInfo211 },  // Inst #1906 = STC_POST
+  { 7, OperandInfo213 },  // Inst #1907 = STC_PRE
+  { 4, OperandInfo67 },  // Inst #1908 = STL
+  { 4, OperandInfo67 },  // Inst #1909 = STLB
+  { 5, OperandInfo324 },  // Inst #1910 = STLEX
+  { 5, OperandInfo324 },  // Inst #1911 = STLEXB
+  { 5, OperandInfo325 },  // Inst #1912 = STLEXD
+  { 5, OperandInfo324 },  // Inst #1913 = STLEXH
+  { 4, OperandInfo67 },  // Inst #1914 = STLH
+  { 4, OperandInfo206 },  // Inst #1915 = STMDA
+  { 5, OperandInfo66 },  // Inst #1916 = STMDA_UPD
+  { 4, OperandInfo206 },  // Inst #1917 = STMDB
+  { 5, OperandInfo66 },  // Inst #1918 = STMDB_UPD
+  { 4, OperandInfo206 },  // Inst #1919 = STMIA
+  { 5, OperandInfo66 },  // Inst #1920 = STMIA_UPD
+  { 4, OperandInfo206 },  // Inst #1921 = STMIB
+  { 5, OperandInfo66 },  // Inst #1922 = STMIB_UPD
+  { 7, OperandInfo326 },  // Inst #1923 = STRBT_POST_IMM
+  { 7, OperandInfo326 },  // Inst #1924 = STRBT_POST_REG
+  { 7, OperandInfo327 },  // Inst #1925 = STRB_POST_IMM
+  { 7, OperandInfo327 },  // Inst #1926 = STRB_POST_REG
+  { 6, OperandInfo328 },  // Inst #1927 = STRB_PRE_IMM
+  { 7, OperandInfo327 },  // Inst #1928 = STRB_PRE_REG
+  { 5, OperandInfo216 },  // Inst #1929 = STRBi12
+  { 6, OperandInfo217 },  // Inst #1930 = STRBrs
+  { 7, OperandInfo218 },  // Inst #1931 = STRD
+  { 8, OperandInfo329 },  // Inst #1932 = STRD_POST
+  { 8, OperandInfo329 },  // Inst #1933 = STRD_PRE
+  { 5, OperandInfo324 },  // Inst #1934 = STREX
+  { 5, OperandInfo324 },  // Inst #1935 = STREXB
+  { 5, OperandInfo325 },  // Inst #1936 = STREXD
+  { 5, OperandInfo324 },  // Inst #1937 = STREXH
+  { 6, OperandInfo220 },  // Inst #1938 = STRH
+  { 6, OperandInfo330 },  // Inst #1939 = STRHTi
+  { 7, OperandInfo326 },  // Inst #1940 = STRHTr
+  { 7, OperandInfo331 },  // Inst #1941 = STRH_POST
+  { 7, OperandInfo331 },  // Inst #1942 = STRH_PRE
+  { 7, OperandInfo326 },  // Inst #1943 = STRT_POST_IMM
+  { 7, OperandInfo326 },  // Inst #1944 = STRT_POST_REG
+  { 7, OperandInfo327 },  // Inst #1945 = STR_POST_IMM
+  { 7, OperandInfo327 },  // Inst #1946 = STR_POST_REG
+  { 6, OperandInfo328 },  // Inst #1947 = STR_PRE_IMM
+  { 7, OperandInfo327 },  // Inst #1948 = STR_PRE_REG
+  { 5, OperandInfo87 },  // Inst #1949 = STRi12
+  { 6, OperandInfo223 },  // Inst #1950 = STRrs
+  { 6, OperandInfo51 },  // Inst #1951 = SUBri
+  { 6, OperandInfo153 },  // Inst #1952 = SUBrr
+  { 7, OperandInfo154 },  // Inst #1953 = SUBrsi
+  { 8, OperandInfo156 },  // Inst #1954 = SUBrsr
+  { 3, OperandInfo202 },  // Inst #1955 = SVC
+  { 5, OperandInfo332 },  // Inst #1956 = SWP
+  { 5, OperandInfo332 },  // Inst #1957 = SWPB
+  { 6, OperandInfo333 },  // Inst #1958 = SXTAB
+  { 6, OperandInfo333 },  // Inst #1959 = SXTAB16
+  { 6, OperandInfo333 },  // Inst #1960 = SXTAH
+  { 5, OperandInfo334 },  // Inst #1961 = SXTB
+  { 5, OperandInfo334 },  // Inst #1962 = SXTB16
+  { 5, OperandInfo334 },  // Inst #1963 = SXTH
+  { 4, OperandInfo68 },  // Inst #1964 = TEQri
+  { 4, OperandInfo197 },  // Inst #1965 = TEQrr
+  { 5, OperandInfo198 },  // Inst #1966 = TEQrsi
+  { 6, OperandInfo199 },  // Inst #1967 = TEQrsr
+  { 0, 0 },  // Inst #1968 = TRAP
+  { 0, 0 },  // Inst #1969 = TRAPNaCl
+  { 1, OperandInfo2 },  // Inst #1970 = TSB
+  { 4, OperandInfo68 },  // Inst #1971 = TSTri
+  { 4, OperandInfo197 },  // Inst #1972 = TSTrr
+  { 5, OperandInfo198 },  // Inst #1973 = TSTrsi
+  { 6, OperandInfo199 },  // Inst #1974 = TSTrsr
+  { 5, OperandInfo315 },  // Inst #1975 = UADD16
+  { 5, OperandInfo315 },  // Inst #1976 = UADD8
+  { 5, OperandInfo315 },  // Inst #1977 = UASX
+  { 6, OperandInfo317 },  // Inst #1978 = UBFX
+  { 1, OperandInfo2 },  // Inst #1979 = UDF
+  { 5, OperandInfo47 },  // Inst #1980 = UDIV
+  { 5, OperandInfo315 },  // Inst #1981 = UHADD16
+  { 5, OperandInfo315 },  // Inst #1982 = UHADD8
+  { 5, OperandInfo315 },  // Inst #1983 = UHASX
+  { 5, OperandInfo315 },  // Inst #1984 = UHSAX
+  { 5, OperandInfo315 },  // Inst #1985 = UHSUB16
+  { 5, OperandInfo315 },  // Inst #1986 = UHSUB8
+  { 8, OperandInfo335 },  // Inst #1987 = UMAAL
+  { 9, OperandInfo319 },  // Inst #1988 = UMLAL
+  { 7, OperandInfo321 },  // Inst #1989 = UMULL
+  { 5, OperandInfo315 },  // Inst #1990 = UQADD16
+  { 5, OperandInfo315 },  // Inst #1991 = UQADD8
+  { 5, OperandInfo315 },  // Inst #1992 = UQASX
+  { 5, OperandInfo315 },  // Inst #1993 = UQSAX
+  { 5, OperandInfo315 },  // Inst #1994 = UQSUB16
+  { 5, OperandInfo315 },  // Inst #1995 = UQSUB8
+  { 5, OperandInfo47 },  // Inst #1996 = USAD8
+  { 6, OperandInfo229 },  // Inst #1997 = USADA8
+  { 6, OperandInfo322 },  // Inst #1998 = USAT
+  { 5, OperandInfo323 },  // Inst #1999 = USAT16
+  { 5, OperandInfo315 },  // Inst #2000 = USAX
+  { 5, OperandInfo315 },  // Inst #2001 = USUB16
+  { 5, OperandInfo315 },  // Inst #2002 = USUB8
+  { 6, OperandInfo333 },  // Inst #2003 = UXTAB
+  { 6, OperandInfo333 },  // Inst #2004 = UXTAB16
+  { 6, OperandInfo333 },  // Inst #2005 = UXTAH
+  { 5, OperandInfo334 },  // Inst #2006 = UXTB
+  { 5, OperandInfo334 },  // Inst #2007 = UXTB16
+  { 5, OperandInfo334 },  // Inst #2008 = UXTH
+  { 6, OperandInfo336 },  // Inst #2009 = VABALsv2i64
+  { 6, OperandInfo336 },  // Inst #2010 = VABALsv4i32
+  { 6, OperandInfo336 },  // Inst #2011 = VABALsv8i16
+  { 6, OperandInfo336 },  // Inst #2012 = VABALuv2i64
+  { 6, OperandInfo336 },  // Inst #2013 = VABALuv4i32
+  { 6, OperandInfo336 },  // Inst #2014 = VABALuv8i16
+  { 6, OperandInfo337 },  // Inst #2015 = VABAsv16i8
+  { 6, OperandInfo338 },  // Inst #2016 = VABAsv2i32
+  { 6, OperandInfo338 },  // Inst #2017 = VABAsv4i16
+  { 6, OperandInfo337 },  // Inst #2018 = VABAsv4i32
+  { 6, OperandInfo337 },  // Inst #2019 = VABAsv8i16
+  { 6, OperandInfo338 },  // Inst #2020 = VABAsv8i8
+  { 6, OperandInfo337 },  // Inst #2021 = VABAuv16i8
+  { 6, OperandInfo338 },  // Inst #2022 = VABAuv2i32
+  { 6, OperandInfo338 },  // Inst #2023 = VABAuv4i16
+  { 6, OperandInfo337 },  // Inst #2024 = VABAuv4i32
+  { 6, OperandInfo337 },  // Inst #2025 = VABAuv8i16
+  { 6, OperandInfo338 },  // Inst #2026 = VABAuv8i8
+  { 5, OperandInfo339 },  // Inst #2027 = VABDLsv2i64
+  { 5, OperandInfo339 },  // Inst #2028 = VABDLsv4i32
+  { 5, OperandInfo339 },  // Inst #2029 = VABDLsv8i16
+  { 5, OperandInfo339 },  // Inst #2030 = VABDLuv2i64
+  { 5, OperandInfo339 },  // Inst #2031 = VABDLuv4i32
+  { 5, OperandInfo339 },  // Inst #2032 = VABDLuv8i16
+  { 5, OperandInfo340 },  // Inst #2033 = VABDfd
+  { 5, OperandInfo341 },  // Inst #2034 = VABDfq
+  { 5, OperandInfo340 },  // Inst #2035 = VABDhd
+  { 5, OperandInfo341 },  // Inst #2036 = VABDhq
+  { 5, OperandInfo341 },  // Inst #2037 = VABDsv16i8
+  { 5, OperandInfo340 },  // Inst #2038 = VABDsv2i32
+  { 5, OperandInfo340 },  // Inst #2039 = VABDsv4i16
+  { 5, OperandInfo341 },  // Inst #2040 = VABDsv4i32
+  { 5, OperandInfo341 },  // Inst #2041 = VABDsv8i16
+  { 5, OperandInfo340 },  // Inst #2042 = VABDsv8i8
+  { 5, OperandInfo341 },  // Inst #2043 = VABDuv16i8
+  { 5, OperandInfo340 },  // Inst #2044 = VABDuv2i32
+  { 5, OperandInfo340 },  // Inst #2045 = VABDuv4i16
+  { 5, OperandInfo341 },  // Inst #2046 = VABDuv4i32
+  { 5, OperandInfo341 },  // Inst #2047 = VABDuv8i16
+  { 5, OperandInfo340 },  // Inst #2048 = VABDuv8i8
+  { 4, OperandInfo342 },  // Inst #2049 = VABSD
+  { 4, OperandInfo343 },  // Inst #2050 = VABSH
+  { 4, OperandInfo344 },  // Inst #2051 = VABSS
+  { 4, OperandInfo342 },  // Inst #2052 = VABSfd
+  { 4, OperandInfo345 },  // Inst #2053 = VABSfq
+  { 4, OperandInfo342 },  // Inst #2054 = VABShd
+  { 4, OperandInfo345 },  // Inst #2055 = VABShq
+  { 4, OperandInfo345 },  // Inst #2056 = VABSv16i8
+  { 4, OperandInfo342 },  // Inst #2057 = VABSv2i32
+  { 4, OperandInfo342 },  // Inst #2058 = VABSv4i16
+  { 4, OperandInfo345 },  // Inst #2059 = VABSv4i32
+  { 4, OperandInfo345 },  // Inst #2060 = VABSv8i16
+  { 4, OperandInfo342 },  // Inst #2061 = VABSv8i8
+  { 5, OperandInfo340 },  // Inst #2062 = VACGEfd
+  { 5, OperandInfo341 },  // Inst #2063 = VACGEfq
+  { 5, OperandInfo340 },  // Inst #2064 = VACGEhd
+  { 5, OperandInfo341 },  // Inst #2065 = VACGEhq
+  { 5, OperandInfo340 },  // Inst #2066 = VACGTfd
+  { 5, OperandInfo341 },  // Inst #2067 = VACGTfq
+  { 5, OperandInfo340 },  // Inst #2068 = VACGThd
+  { 5, OperandInfo341 },  // Inst #2069 = VACGThq
+  { 5, OperandInfo340 },  // Inst #2070 = VADDD
+  { 5, OperandInfo346 },  // Inst #2071 = VADDH
+  { 5, OperandInfo347 },  // Inst #2072 = VADDHNv2i32
+  { 5, OperandInfo347 },  // Inst #2073 = VADDHNv4i16
+  { 5, OperandInfo347 },  // Inst #2074 = VADDHNv8i8
+  { 5, OperandInfo339 },  // Inst #2075 = VADDLsv2i64
+  { 5, OperandInfo339 },  // Inst #2076 = VADDLsv4i32
+  { 5, OperandInfo339 },  // Inst #2077 = VADDLsv8i16
+  { 5, OperandInfo339 },  // Inst #2078 = VADDLuv2i64
+  { 5, OperandInfo339 },  // Inst #2079 = VADDLuv4i32
+  { 5, OperandInfo339 },  // Inst #2080 = VADDLuv8i16
+  { 5, OperandInfo348 },  // Inst #2081 = VADDS
+  { 5, OperandInfo349 },  // Inst #2082 = VADDWsv2i64
+  { 5, OperandInfo349 },  // Inst #2083 = VADDWsv4i32
+  { 5, OperandInfo349 },  // Inst #2084 = VADDWsv8i16
+  { 5, OperandInfo349 },  // Inst #2085 = VADDWuv2i64
+  { 5, OperandInfo349 },  // Inst #2086 = VADDWuv4i32
+  { 5, OperandInfo349 },  // Inst #2087 = VADDWuv8i16
+  { 5, OperandInfo340 },  // Inst #2088 = VADDfd
+  { 5, OperandInfo341 },  // Inst #2089 = VADDfq
+  { 5, OperandInfo340 },  // Inst #2090 = VADDhd
+  { 5, OperandInfo341 },  // Inst #2091 = VADDhq
+  { 5, OperandInfo341 },  // Inst #2092 = VADDv16i8
+  { 5, OperandInfo340 },  // Inst #2093 = VADDv1i64
+  { 5, OperandInfo340 },  // Inst #2094 = VADDv2i32
+  { 5, OperandInfo341 },  // Inst #2095 = VADDv2i64
+  { 5, OperandInfo340 },  // Inst #2096 = VADDv4i16
+  { 5, OperandInfo341 },  // Inst #2097 = VADDv4i32
+  { 5, OperandInfo341 },  // Inst #2098 = VADDv8i16
+  { 5, OperandInfo340 },  // Inst #2099 = VADDv8i8
+  { 5, OperandInfo340 },  // Inst #2100 = VANDd
+  { 5, OperandInfo341 },  // Inst #2101 = VANDq
+  { 4, OperandInfo162 },  // Inst #2102 = VBF16MALBQ
+  { 5, OperandInfo350 },  // Inst #2103 = VBF16MALBQI
+  { 4, OperandInfo162 },  // Inst #2104 = VBF16MALTQ
+  { 5, OperandInfo350 },  // Inst #2105 = VBF16MALTQI
+  { 5, OperandInfo340 },  // Inst #2106 = VBICd
+  { 5, OperandInfo351 },  // Inst #2107 = VBICiv2i32
+  { 5, OperandInfo351 },  // Inst #2108 = VBICiv4i16
+  { 5, OperandInfo352 },  // Inst #2109 = VBICiv4i32
+  { 5, OperandInfo352 },  // Inst #2110 = VBICiv8i16
+  { 5, OperandInfo341 },  // Inst #2111 = VBICq
+  { 6, OperandInfo338 },  // Inst #2112 = VBIFd
+  { 6, OperandInfo337 },  // Inst #2113 = VBIFq
+  { 6, OperandInfo338 },  // Inst #2114 = VBITd
+  { 6, OperandInfo337 },  // Inst #2115 = VBITq
+  { 6, OperandInfo338 },  // Inst #2116 = VBSLd
+  { 6, OperandInfo337 },  // Inst #2117 = VBSLq
+  { 6, OperandInfo353 },  // Inst #2118 = VBSPd
+  { 6, OperandInfo354 },  // Inst #2119 = VBSPq
+  { 4, OperandInfo355 },  // Inst #2120 = VCADDv2f32
+  { 4, OperandInfo355 },  // Inst #2121 = VCADDv4f16
+  { 4, OperandInfo356 },  // Inst #2122 = VCADDv4f32
+  { 4, OperandInfo356 },  // Inst #2123 = VCADDv8f16
+  { 5, OperandInfo340 },  // Inst #2124 = VCEQfd
+  { 5, OperandInfo341 },  // Inst #2125 = VCEQfq
+  { 5, OperandInfo340 },  // Inst #2126 = VCEQhd
+  { 5, OperandInfo341 },  // Inst #2127 = VCEQhq
+  { 5, OperandInfo341 },  // Inst #2128 = VCEQv16i8
+  { 5, OperandInfo340 },  // Inst #2129 = VCEQv2i32
+  { 5, OperandInfo340 },  // Inst #2130 = VCEQv4i16
+  { 5, OperandInfo341 },  // Inst #2131 = VCEQv4i32
+  { 5, OperandInfo341 },  // Inst #2132 = VCEQv8i16
+  { 5, OperandInfo340 },  // Inst #2133 = VCEQv8i8
+  { 4, OperandInfo345 },  // Inst #2134 = VCEQzv16i8
+  { 4, OperandInfo342 },  // Inst #2135 = VCEQzv2f32
+  { 4, OperandInfo342 },  // Inst #2136 = VCEQzv2i32
+  { 4, OperandInfo342 },  // Inst #2137 = VCEQzv4f16
+  { 4, OperandInfo345 },  // Inst #2138 = VCEQzv4f32
+  { 4, OperandInfo342 },  // Inst #2139 = VCEQzv4i16
+  { 4, OperandInfo345 },  // Inst #2140 = VCEQzv4i32
+  { 4, OperandInfo345 },  // Inst #2141 = VCEQzv8f16
+  { 4, OperandInfo345 },  // Inst #2142 = VCEQzv8i16
+  { 4, OperandInfo342 },  // Inst #2143 = VCEQzv8i8
+  { 5, OperandInfo340 },  // Inst #2144 = VCGEfd
+  { 5, OperandInfo341 },  // Inst #2145 = VCGEfq
+  { 5, OperandInfo340 },  // Inst #2146 = VCGEhd
+  { 5, OperandInfo341 },  // Inst #2147 = VCGEhq
+  { 5, OperandInfo341 },  // Inst #2148 = VCGEsv16i8
+  { 5, OperandInfo340 },  // Inst #2149 = VCGEsv2i32
+  { 5, OperandInfo340 },  // Inst #2150 = VCGEsv4i16
+  { 5, OperandInfo341 },  // Inst #2151 = VCGEsv4i32
+  { 5, OperandInfo341 },  // Inst #2152 = VCGEsv8i16
+  { 5, OperandInfo340 },  // Inst #2153 = VCGEsv8i8
+  { 5, OperandInfo341 },  // Inst #2154 = VCGEuv16i8
+  { 5, OperandInfo340 },  // Inst #2155 = VCGEuv2i32
+  { 5, OperandInfo340 },  // Inst #2156 = VCGEuv4i16
+  { 5, OperandInfo341 },  // Inst #2157 = VCGEuv4i32
+  { 5, OperandInfo341 },  // Inst #2158 = VCGEuv8i16
+  { 5, OperandInfo340 },  // Inst #2159 = VCGEuv8i8
+  { 4, OperandInfo345 },  // Inst #2160 = VCGEzv16i8
+  { 4, OperandInfo342 },  // Inst #2161 = VCGEzv2f32
+  { 4, OperandInfo342 },  // Inst #2162 = VCGEzv2i32
+  { 4, OperandInfo342 },  // Inst #2163 = VCGEzv4f16
+  { 4, OperandInfo345 },  // Inst #2164 = VCGEzv4f32
+  { 4, OperandInfo342 },  // Inst #2165 = VCGEzv4i16
+  { 4, OperandInfo345 },  // Inst #2166 = VCGEzv4i32
+  { 4, OperandInfo345 },  // Inst #2167 = VCGEzv8f16
+  { 4, OperandInfo345 },  // Inst #2168 = VCGEzv8i16
+  { 4, OperandInfo342 },  // Inst #2169 = VCGEzv8i8
+  { 5, OperandInfo340 },  // Inst #2170 = VCGTfd
+  { 5, OperandInfo341 },  // Inst #2171 = VCGTfq
+  { 5, OperandInfo340 },  // Inst #2172 = VCGThd
+  { 5, OperandInfo341 },  // Inst #2173 = VCGThq
+  { 5, OperandInfo341 },  // Inst #2174 = VCGTsv16i8
+  { 5, OperandInfo340 },  // Inst #2175 = VCGTsv2i32
+  { 5, OperandInfo340 },  // Inst #2176 = VCGTsv4i16
+  { 5, OperandInfo341 },  // Inst #2177 = VCGTsv4i32
+  { 5, OperandInfo341 },  // Inst #2178 = VCGTsv8i16
+  { 5, OperandInfo340 },  // Inst #2179 = VCGTsv8i8
+  { 5, OperandInfo341 },  // Inst #2180 = VCGTuv16i8
+  { 5, OperandInfo340 },  // Inst #2181 = VCGTuv2i32
+  { 5, OperandInfo340 },  // Inst #2182 = VCGTuv4i16
+  { 5, OperandInfo341 },  // Inst #2183 = VCGTuv4i32
+  { 5, OperandInfo341 },  // Inst #2184 = VCGTuv8i16
+  { 5, OperandInfo340 },  // Inst #2185 = VCGTuv8i8
+  { 4, OperandInfo345 },  // Inst #2186 = VCGTzv16i8
+  { 4, OperandInfo342 },  // Inst #2187 = VCGTzv2f32
+  { 4, OperandInfo342 },  // Inst #2188 = VCGTzv2i32
+  { 4, OperandInfo342 },  // Inst #2189 = VCGTzv4f16
+  { 4, OperandInfo345 },  // Inst #2190 = VCGTzv4f32
+  { 4, OperandInfo342 },  // Inst #2191 = VCGTzv4i16
+  { 4, OperandInfo345 },  // Inst #2192 = VCGTzv4i32
+  { 4, OperandInfo345 },  // Inst #2193 = VCGTzv8f16
+  { 4, OperandInfo345 },  // Inst #2194 = VCGTzv8i16
+  { 4, OperandInfo342 },  // Inst #2195 = VCGTzv8i8
+  { 4, OperandInfo345 },  // Inst #2196 = VCLEzv16i8
+  { 4, OperandInfo342 },  // Inst #2197 = VCLEzv2f32
+  { 4, OperandInfo342 },  // Inst #2198 = VCLEzv2i32
+  { 4, OperandInfo342 },  // Inst #2199 = VCLEzv4f16
+  { 4, OperandInfo345 },  // Inst #2200 = VCLEzv4f32
+  { 4, OperandInfo342 },  // Inst #2201 = VCLEzv4i16
+  { 4, OperandInfo345 },  // Inst #2202 = VCLEzv4i32
+  { 4, OperandInfo345 },  // Inst #2203 = VCLEzv8f16
+  { 4, OperandInfo345 },  // Inst #2204 = VCLEzv8i16
+  { 4, OperandInfo342 },  // Inst #2205 = VCLEzv8i8
+  { 4, OperandInfo345 },  // Inst #2206 = VCLSv16i8
+  { 4, OperandInfo342 },  // Inst #2207 = VCLSv2i32
+  { 4, OperandInfo342 },  // Inst #2208 = VCLSv4i16
+  { 4, OperandInfo345 },  // Inst #2209 = VCLSv4i32
+  { 4, OperandInfo345 },  // Inst #2210 = VCLSv8i16
+  { 4, OperandInfo342 },  // Inst #2211 = VCLSv8i8
+  { 4, OperandInfo345 },  // Inst #2212 = VCLTzv16i8
+  { 4, OperandInfo342 },  // Inst #2213 = VCLTzv2f32
+  { 4, OperandInfo342 },  // Inst #2214 = VCLTzv2i32
+  { 4, OperandInfo342 },  // Inst #2215 = VCLTzv4f16
+  { 4, OperandInfo345 },  // Inst #2216 = VCLTzv4f32
+  { 4, OperandInfo342 },  // Inst #2217 = VCLTzv4i16
+  { 4, OperandInfo345 },  // Inst #2218 = VCLTzv4i32
+  { 4, OperandInfo345 },  // Inst #2219 = VCLTzv8f16
+  { 4, OperandInfo345 },  // Inst #2220 = VCLTzv8i16
+  { 4, OperandInfo342 },  // Inst #2221 = VCLTzv8i8
+  { 4, OperandInfo345 },  // Inst #2222 = VCLZv16i8
+  { 4, OperandInfo342 },  // Inst #2223 = VCLZv2i32
+  { 4, OperandInfo342 },  // Inst #2224 = VCLZv4i16
+  { 4, OperandInfo345 },  // Inst #2225 = VCLZv4i32
+  { 4, OperandInfo345 },  // Inst #2226 = VCLZv8i16
+  { 4, OperandInfo342 },  // Inst #2227 = VCLZv8i8
+  { 5, OperandInfo357 },  // Inst #2228 = VCMLAv2f32
+  { 6, OperandInfo358 },  // Inst #2229 = VCMLAv2f32_indexed
+  { 5, OperandInfo357 },  // Inst #2230 = VCMLAv4f16
+  { 6, OperandInfo359 },  // Inst #2231 = VCMLAv4f16_indexed
+  { 5, OperandInfo360 },  // Inst #2232 = VCMLAv4f32
+  { 6, OperandInfo361 },  // Inst #2233 = VCMLAv4f32_indexed
+  { 5, OperandInfo360 },  // Inst #2234 = VCMLAv8f16
+  { 6, OperandInfo362 },  // Inst #2235 = VCMLAv8f16_indexed
+  { 4, OperandInfo342 },  // Inst #2236 = VCMPD
+  { 4, OperandInfo342 },  // Inst #2237 = VCMPED
+  { 4, OperandInfo343 },  // Inst #2238 = VCMPEH
+  { 4, OperandInfo344 },  // Inst #2239 = VCMPES
+  { 3, OperandInfo363 },  // Inst #2240 = VCMPEZD
+  { 3, OperandInfo364 },  // Inst #2241 = VCMPEZH
+  { 3, OperandInfo365 },  // Inst #2242 = VCMPEZS
+  { 4, OperandInfo343 },  // Inst #2243 = VCMPH
+  { 4, OperandInfo344 },  // Inst #2244 = VCMPS
+  { 3, OperandInfo363 },  // Inst #2245 = VCMPZD
+  { 3, OperandInfo364 },  // Inst #2246 = VCMPZH
+  { 3, OperandInfo365 },  // Inst #2247 = VCMPZS
+  { 4, OperandInfo342 },  // Inst #2248 = VCNTd
+  { 4, OperandInfo345 },  // Inst #2249 = VCNTq
+  { 2, OperandInfo366 },  // Inst #2250 = VCVTANSDf
+  { 2, OperandInfo366 },  // Inst #2251 = VCVTANSDh
+  { 2, OperandInfo158 },  // Inst #2252 = VCVTANSQf
+  { 2, OperandInfo158 },  // Inst #2253 = VCVTANSQh
+  { 2, OperandInfo366 },  // Inst #2254 = VCVTANUDf
+  { 2, OperandInfo366 },  // Inst #2255 = VCVTANUDh
+  { 2, OperandInfo158 },  // Inst #2256 = VCVTANUQf
+  { 2, OperandInfo158 },  // Inst #2257 = VCVTANUQh
+  { 2, OperandInfo367 },  // Inst #2258 = VCVTASD
+  { 2, OperandInfo368 },  // Inst #2259 = VCVTASH
+  { 2, OperandInfo369 },  // Inst #2260 = VCVTASS
+  { 2, OperandInfo367 },  // Inst #2261 = VCVTAUD
+  { 2, OperandInfo368 },  // Inst #2262 = VCVTAUH
+  { 2, OperandInfo369 },  // Inst #2263 = VCVTAUS
+  { 5, OperandInfo370 },  // Inst #2264 = VCVTBDH
+  { 4, OperandInfo371 },  // Inst #2265 = VCVTBHD
+  { 4, OperandInfo344 },  // Inst #2266 = VCVTBHS
+  { 5, OperandInfo105 },  // Inst #2267 = VCVTBSH
+  { 4, OperandInfo371 },  // Inst #2268 = VCVTDS
+  { 2, OperandInfo366 },  // Inst #2269 = VCVTMNSDf
+  { 2, OperandInfo366 },  // Inst #2270 = VCVTMNSDh
+  { 2, OperandInfo158 },  // Inst #2271 = VCVTMNSQf
+  { 2, OperandInfo158 },  // Inst #2272 = VCVTMNSQh
+  { 2, OperandInfo366 },  // Inst #2273 = VCVTMNUDf
+  { 2, OperandInfo366 },  // Inst #2274 = VCVTMNUDh
+  { 2, OperandInfo158 },  // Inst #2275 = VCVTMNUQf
+  { 2, OperandInfo158 },  // Inst #2276 = VCVTMNUQh
+  { 2, OperandInfo367 },  // Inst #2277 = VCVTMSD
+  { 2, OperandInfo368 },  // Inst #2278 = VCVTMSH
+  { 2, OperandInfo369 },  // Inst #2279 = VCVTMSS
+  { 2, OperandInfo367 },  // Inst #2280 = VCVTMUD
+  { 2, OperandInfo368 },  // Inst #2281 = VCVTMUH
+  { 2, OperandInfo369 },  // Inst #2282 = VCVTMUS
+  { 2, OperandInfo366 },  // Inst #2283 = VCVTNNSDf
+  { 2, OperandInfo366 },  // Inst #2284 = VCVTNNSDh
+  { 2, OperandInfo158 },  // Inst #2285 = VCVTNNSQf
+  { 2, OperandInfo158 },  // Inst #2286 = VCVTNNSQh
+  { 2, OperandInfo366 },  // Inst #2287 = VCVTNNUDf
+  { 2, OperandInfo366 },  // Inst #2288 = VCVTNNUDh
+  { 2, OperandInfo158 },  // Inst #2289 = VCVTNNUQf
+  { 2, OperandInfo158 },  // Inst #2290 = VCVTNNUQh
+  { 2, OperandInfo367 },  // Inst #2291 = VCVTNSD
+  { 2, OperandInfo368 },  // Inst #2292 = VCVTNSH
+  { 2, OperandInfo369 },  // Inst #2293 = VCVTNSS
+  { 2, OperandInfo367 },  // Inst #2294 = VCVTNUD
+  { 2, OperandInfo368 },  // Inst #2295 = VCVTNUH
+  { 2, OperandInfo369 },  // Inst #2296 = VCVTNUS
+  { 2, OperandInfo366 },  // Inst #2297 = VCVTPNSDf
+  { 2, OperandInfo366 },  // Inst #2298 = VCVTPNSDh
+  { 2, OperandInfo158 },  // Inst #2299 = VCVTPNSQf
+  { 2, OperandInfo158 },  // Inst #2300 = VCVTPNSQh
+  { 2, OperandInfo366 },  // Inst #2301 = VCVTPNUDf
+  { 2, OperandInfo366 },  // Inst #2302 = VCVTPNUDh
+  { 2, OperandInfo158 },  // Inst #2303 = VCVTPNUQf
+  { 2, OperandInfo158 },  // Inst #2304 = VCVTPNUQh
+  { 2, OperandInfo367 },  // Inst #2305 = VCVTPSD
+  { 2, OperandInfo368 },  // Inst #2306 = VCVTPSH
+  { 2, OperandInfo369 },  // Inst #2307 = VCVTPSS
+  { 2, OperandInfo367 },  // Inst #2308 = VCVTPUD
+  { 2, OperandInfo368 },  // Inst #2309 = VCVTPUH
+  { 2, OperandInfo369 },  // Inst #2310 = VCVTPUS
+  { 4, OperandInfo372 },  // Inst #2311 = VCVTSD
+  { 5, OperandInfo370 },  // Inst #2312 = VCVTTDH
+  { 4, OperandInfo371 },  // Inst #2313 = VCVTTHD
+  { 4, OperandInfo344 },  // Inst #2314 = VCVTTHS
+  { 5, OperandInfo105 },  // Inst #2315 = VCVTTSH
+  { 4, OperandInfo163 },  // Inst #2316 = VCVTf2h
+  { 4, OperandInfo342 },  // Inst #2317 = VCVTf2sd
+  { 4, OperandInfo345 },  // Inst #2318 = VCVTf2sq
+  { 4, OperandInfo342 },  // Inst #2319 = VCVTf2ud
+  { 4, OperandInfo345 },  // Inst #2320 = VCVTf2uq
+  { 5, OperandInfo373 },  // Inst #2321 = VCVTf2xsd
+  { 5, OperandInfo374 },  // Inst #2322 = VCVTf2xsq
+  { 5, OperandInfo373 },  // Inst #2323 = VCVTf2xud
+  { 5, OperandInfo374 },  // Inst #2324 = VCVTf2xuq
+  { 4, OperandInfo375 },  // Inst #2325 = VCVTh2f
+  { 4, OperandInfo342 },  // Inst #2326 = VCVTh2sd
+  { 4, OperandInfo345 },  // Inst #2327 = VCVTh2sq
+  { 4, OperandInfo342 },  // Inst #2328 = VCVTh2ud
+  { 4, OperandInfo345 },  // Inst #2329 = VCVTh2uq
+  { 5, OperandInfo373 },  // Inst #2330 = VCVTh2xsd
+  { 5, OperandInfo374 },  // Inst #2331 = VCVTh2xsq
+  { 5, OperandInfo373 },  // Inst #2332 = VCVTh2xud
+  { 5, OperandInfo374 },  // Inst #2333 = VCVTh2xuq
+  { 4, OperandInfo342 },  // Inst #2334 = VCVTs2fd
+  { 4, OperandInfo345 },  // Inst #2335 = VCVTs2fq
+  { 4, OperandInfo342 },  // Inst #2336 = VCVTs2hd
+  { 4, OperandInfo345 },  // Inst #2337 = VCVTs2hq
+  { 4, OperandInfo342 },  // Inst #2338 = VCVTu2fd
+  { 4, OperandInfo345 },  // Inst #2339 = VCVTu2fq
+  { 4, OperandInfo342 },  // Inst #2340 = VCVTu2hd
+  { 4, OperandInfo345 },  // Inst #2341 = VCVTu2hq
+  { 5, OperandInfo373 },  // Inst #2342 = VCVTxs2fd
+  { 5, OperandInfo374 },  // Inst #2343 = VCVTxs2fq
+  { 5, OperandInfo373 },  // Inst #2344 = VCVTxs2hd
+  { 5, OperandInfo374 },  // Inst #2345 = VCVTxs2hq
+  { 5, OperandInfo373 },  // Inst #2346 = VCVTxu2fd
+  { 5, OperandInfo374 },  // Inst #2347 = VCVTxu2fq
+  { 5, OperandInfo373 },  // Inst #2348 = VCVTxu2hd
+  { 5, OperandInfo374 },  // Inst #2349 = VCVTxu2hq
+  { 5, OperandInfo340 },  // Inst #2350 = VDIVD
+  { 5, OperandInfo346 },  // Inst #2351 = VDIVH
+  { 5, OperandInfo348 },  // Inst #2352 = VDIVS
+  { 4, OperandInfo376 },  // Inst #2353 = VDUP16d
+  { 4, OperandInfo377 },  // Inst #2354 = VDUP16q
+  { 4, OperandInfo376 },  // Inst #2355 = VDUP32d
+  { 4, OperandInfo377 },  // Inst #2356 = VDUP32q
+  { 4, OperandInfo376 },  // Inst #2357 = VDUP8d
+  { 4, OperandInfo377 },  // Inst #2358 = VDUP8q
+  { 5, OperandInfo373 },  // Inst #2359 = VDUPLN16d
+  { 5, OperandInfo378 },  // Inst #2360 = VDUPLN16q
+  { 5, OperandInfo373 },  // Inst #2361 = VDUPLN32d
+  { 5, OperandInfo378 },  // Inst #2362 = VDUPLN32q
+  { 5, OperandInfo373 },  // Inst #2363 = VDUPLN8d
+  { 5, OperandInfo378 },  // Inst #2364 = VDUPLN8q
+  { 5, OperandInfo340 },  // Inst #2365 = VEORd
+  { 5, OperandInfo341 },  // Inst #2366 = VEORq
+  { 6, OperandInfo379 },  // Inst #2367 = VEXTd16
+  { 6, OperandInfo379 },  // Inst #2368 = VEXTd32
+  { 6, OperandInfo379 },  // Inst #2369 = VEXTd8
+  { 6, OperandInfo380 },  // Inst #2370 = VEXTq16
+  { 6, OperandInfo380 },  // Inst #2371 = VEXTq32
+  { 6, OperandInfo380 },  // Inst #2372 = VEXTq64
+  { 6, OperandInfo380 },  // Inst #2373 = VEXTq8
+  { 6, OperandInfo338 },  // Inst #2374 = VFMAD
+  { 6, OperandInfo381 },  // Inst #2375 = VFMAH
+  { 3, OperandInfo382 },  // Inst #2376 = VFMALD
+  { 4, OperandInfo383 },  // Inst #2377 = VFMALDI
+  { 3, OperandInfo384 },  // Inst #2378 = VFMALQ
+  { 4, OperandInfo385 },  // Inst #2379 = VFMALQI
+  { 6, OperandInfo386 },  // Inst #2380 = VFMAS
+  { 6, OperandInfo338 },  // Inst #2381 = VFMAfd
+  { 6, OperandInfo337 },  // Inst #2382 = VFMAfq
+  { 6, OperandInfo338 },  // Inst #2383 = VFMAhd
+  { 6, OperandInfo337 },  // Inst #2384 = VFMAhq
+  { 6, OperandInfo338 },  // Inst #2385 = VFMSD
+  { 6, OperandInfo381 },  // Inst #2386 = VFMSH
+  { 3, OperandInfo382 },  // Inst #2387 = VFMSLD
+  { 4, OperandInfo383 },  // Inst #2388 = VFMSLDI
+  { 3, OperandInfo384 },  // Inst #2389 = VFMSLQ
+  { 4, OperandInfo385 },  // Inst #2390 = VFMSLQI
+  { 6, OperandInfo386 },  // Inst #2391 = VFMSS
+  { 6, OperandInfo338 },  // Inst #2392 = VFMSfd
+  { 6, OperandInfo337 },  // Inst #2393 = VFMSfq
+  { 6, OperandInfo338 },  // Inst #2394 = VFMShd
+  { 6, OperandInfo337 },  // Inst #2395 = VFMShq
+  { 6, OperandInfo338 },  // Inst #2396 = VFNMAD
+  { 6, OperandInfo381 },  // Inst #2397 = VFNMAH
+  { 6, OperandInfo386 },  // Inst #2398 = VFNMAS
+  { 6, OperandInfo338 },  // Inst #2399 = VFNMSD
+  { 6, OperandInfo381 },  // Inst #2400 = VFNMSH
+  { 6, OperandInfo386 },  // Inst #2401 = VFNMSS
+  { 3, OperandInfo310 },  // Inst #2402 = VFP_VMAXNMD
+  { 3, OperandInfo387 },  // Inst #2403 = VFP_VMAXNMH
+  { 3, OperandInfo388 },  // Inst #2404 = VFP_VMAXNMS
+  { 3, OperandInfo310 },  // Inst #2405 = VFP_VMINNMD
+  { 3, OperandInfo387 },  // Inst #2406 = VFP_VMINNMH
+  { 3, OperandInfo388 },  // Inst #2407 = VFP_VMINNMS
+  { 5, OperandInfo389 },  // Inst #2408 = VGETLNi32
+  { 5, OperandInfo389 },  // Inst #2409 = VGETLNs16
+  { 5, OperandInfo389 },  // Inst #2410 = VGETLNs8
+  { 5, OperandInfo389 },  // Inst #2411 = VGETLNu16
+  { 5, OperandInfo389 },  // Inst #2412 = VGETLNu8
+  { 5, OperandInfo341 },  // Inst #2413 = VHADDsv16i8
+  { 5, OperandInfo340 },  // Inst #2414 = VHADDsv2i32
+  { 5, OperandInfo340 },  // Inst #2415 = VHADDsv4i16
+  { 5, OperandInfo341 },  // Inst #2416 = VHADDsv4i32
+  { 5, OperandInfo341 },  // Inst #2417 = VHADDsv8i16
+  { 5, OperandInfo340 },  // Inst #2418 = VHADDsv8i8
+  { 5, OperandInfo341 },  // Inst #2419 = VHADDuv16i8
+  { 5, OperandInfo340 },  // Inst #2420 = VHADDuv2i32
+  { 5, OperandInfo340 },  // Inst #2421 = VHADDuv4i16
+  { 5, OperandInfo341 },  // Inst #2422 = VHADDuv4i32
+  { 5, OperandInfo341 },  // Inst #2423 = VHADDuv8i16
+  { 5, OperandInfo340 },  // Inst #2424 = VHADDuv8i8
+  { 5, OperandInfo341 },  // Inst #2425 = VHSUBsv16i8
+  { 5, OperandInfo340 },  // Inst #2426 = VHSUBsv2i32
+  { 5, OperandInfo340 },  // Inst #2427 = VHSUBsv4i16
+  { 5, OperandInfo341 },  // Inst #2428 = VHSUBsv4i32
+  { 5, OperandInfo341 },  // Inst #2429 = VHSUBsv8i16
+  { 5, OperandInfo340 },  // Inst #2430 = VHSUBsv8i8
+  { 5, OperandInfo341 },  // Inst #2431 = VHSUBuv16i8
+  { 5, OperandInfo340 },  // Inst #2432 = VHSUBuv2i32
+  { 5, OperandInfo340 },  // Inst #2433 = VHSUBuv4i16
+  { 5, OperandInfo341 },  // Inst #2434 = VHSUBuv4i32
+  { 5, OperandInfo341 },  // Inst #2435 = VHSUBuv8i16
+  { 5, OperandInfo340 },  // Inst #2436 = VHSUBuv8i8
+  { 3, OperandInfo390 },  // Inst #2437 = VINSH
+  { 4, OperandInfo372 },  // Inst #2438 = VJCVT
+  { 5, OperandInfo99 },  // Inst #2439 = VLD1DUPd16
+  { 6, OperandInfo391 },  // Inst #2440 = VLD1DUPd16wb_fixed
+  { 7, OperandInfo392 },  // Inst #2441 = VLD1DUPd16wb_register
+  { 5, OperandInfo99 },  // Inst #2442 = VLD1DUPd32
+  { 6, OperandInfo391 },  // Inst #2443 = VLD1DUPd32wb_fixed
+  { 7, OperandInfo392 },  // Inst #2444 = VLD1DUPd32wb_register
+  { 5, OperandInfo99 },  // Inst #2445 = VLD1DUPd8
+  { 6, OperandInfo391 },  // Inst #2446 = VLD1DUPd8wb_fixed
+  { 7, OperandInfo392 },  // Inst #2447 = VLD1DUPd8wb_register
+  { 5, OperandInfo393 },  // Inst #2448 = VLD1DUPq16
+  { 6, OperandInfo394 },  // Inst #2449 = VLD1DUPq16wb_fixed
+  { 7, OperandInfo395 },  // Inst #2450 = VLD1DUPq16wb_register
+  { 5, OperandInfo393 },  // Inst #2451 = VLD1DUPq32
+  { 6, OperandInfo394 },  // Inst #2452 = VLD1DUPq32wb_fixed
+  { 7, OperandInfo395 },  // Inst #2453 = VLD1DUPq32wb_register
+  { 5, OperandInfo393 },  // Inst #2454 = VLD1DUPq8
+  { 6, OperandInfo394 },  // Inst #2455 = VLD1DUPq8wb_fixed
+  { 7, OperandInfo395 },  // Inst #2456 = VLD1DUPq8wb_register
+  { 7, OperandInfo396 },  // Inst #2457 = VLD1LNd16
+  { 9, OperandInfo397 },  // Inst #2458 = VLD1LNd16_UPD
+  { 7, OperandInfo396 },  // Inst #2459 = VLD1LNd32
+  { 9, OperandInfo397 },  // Inst #2460 = VLD1LNd32_UPD
+  { 7, OperandInfo396 },  // Inst #2461 = VLD1LNd8
+  { 9, OperandInfo397 },  // Inst #2462 = VLD1LNd8_UPD
+  { 7, OperandInfo398 },  // Inst #2463 = VLD1LNq16Pseudo
+  { 9, OperandInfo399 },  // Inst #2464 = VLD1LNq16Pseudo_UPD
+  { 7, OperandInfo398 },  // Inst #2465 = VLD1LNq32Pseudo
+  { 9, OperandInfo399 },  // Inst #2466 = VLD1LNq32Pseudo_UPD
+  { 7, OperandInfo398 },  // Inst #2467 = VLD1LNq8Pseudo
+  { 9, OperandInfo399 },  // Inst #2468 = VLD1LNq8Pseudo_UPD
+  { 5, OperandInfo99 },  // Inst #2469 = VLD1d16
+  { 5, OperandInfo99 },  // Inst #2470 = VLD1d16Q
+  { 5, OperandInfo400 },  // Inst #2471 = VLD1d16QPseudo
+  { 6, OperandInfo401 },  // Inst #2472 = VLD1d16QPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2473 = VLD1d16QPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2474 = VLD1d16Qwb_fixed
+  { 7, OperandInfo392 },  // Inst #2475 = VLD1d16Qwb_register
+  { 5, OperandInfo99 },  // Inst #2476 = VLD1d16T
+  { 5, OperandInfo400 },  // Inst #2477 = VLD1d16TPseudo
+  { 6, OperandInfo401 },  // Inst #2478 = VLD1d16TPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2479 = VLD1d16TPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2480 = VLD1d16Twb_fixed
+  { 7, OperandInfo392 },  // Inst #2481 = VLD1d16Twb_register
+  { 6, OperandInfo391 },  // Inst #2482 = VLD1d16wb_fixed
+  { 7, OperandInfo392 },  // Inst #2483 = VLD1d16wb_register
+  { 5, OperandInfo99 },  // Inst #2484 = VLD1d32
+  { 5, OperandInfo99 },  // Inst #2485 = VLD1d32Q
+  { 5, OperandInfo400 },  // Inst #2486 = VLD1d32QPseudo
+  { 6, OperandInfo401 },  // Inst #2487 = VLD1d32QPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2488 = VLD1d32QPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2489 = VLD1d32Qwb_fixed
+  { 7, OperandInfo392 },  // Inst #2490 = VLD1d32Qwb_register
+  { 5, OperandInfo99 },  // Inst #2491 = VLD1d32T
+  { 5, OperandInfo400 },  // Inst #2492 = VLD1d32TPseudo
+  { 6, OperandInfo401 },  // Inst #2493 = VLD1d32TPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2494 = VLD1d32TPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2495 = VLD1d32Twb_fixed
+  { 7, OperandInfo392 },  // Inst #2496 = VLD1d32Twb_register
+  { 6, OperandInfo391 },  // Inst #2497 = VLD1d32wb_fixed
+  { 7, OperandInfo392 },  // Inst #2498 = VLD1d32wb_register
+  { 5, OperandInfo99 },  // Inst #2499 = VLD1d64
+  { 5, OperandInfo99 },  // Inst #2500 = VLD1d64Q
+  { 5, OperandInfo400 },  // Inst #2501 = VLD1d64QPseudo
+  { 6, OperandInfo401 },  // Inst #2502 = VLD1d64QPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2503 = VLD1d64QPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2504 = VLD1d64Qwb_fixed
+  { 7, OperandInfo392 },  // Inst #2505 = VLD1d64Qwb_register
+  { 5, OperandInfo99 },  // Inst #2506 = VLD1d64T
+  { 5, OperandInfo400 },  // Inst #2507 = VLD1d64TPseudo
+  { 6, OperandInfo401 },  // Inst #2508 = VLD1d64TPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2509 = VLD1d64TPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2510 = VLD1d64Twb_fixed
+  { 7, OperandInfo392 },  // Inst #2511 = VLD1d64Twb_register
+  { 6, OperandInfo391 },  // Inst #2512 = VLD1d64wb_fixed
+  { 7, OperandInfo392 },  // Inst #2513 = VLD1d64wb_register
+  { 5, OperandInfo99 },  // Inst #2514 = VLD1d8
+  { 5, OperandInfo99 },  // Inst #2515 = VLD1d8Q
+  { 5, OperandInfo400 },  // Inst #2516 = VLD1d8QPseudo
+  { 6, OperandInfo401 },  // Inst #2517 = VLD1d8QPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2518 = VLD1d8QPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2519 = VLD1d8Qwb_fixed
+  { 7, OperandInfo392 },  // Inst #2520 = VLD1d8Qwb_register
+  { 5, OperandInfo99 },  // Inst #2521 = VLD1d8T
+  { 5, OperandInfo400 },  // Inst #2522 = VLD1d8TPseudo
+  { 6, OperandInfo401 },  // Inst #2523 = VLD1d8TPseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2524 = VLD1d8TPseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2525 = VLD1d8Twb_fixed
+  { 7, OperandInfo392 },  // Inst #2526 = VLD1d8Twb_register
+  { 6, OperandInfo391 },  // Inst #2527 = VLD1d8wb_fixed
+  { 7, OperandInfo392 },  // Inst #2528 = VLD1d8wb_register
+  { 5, OperandInfo393 },  // Inst #2529 = VLD1q16
+  { 6, OperandInfo403 },  // Inst #2530 = VLD1q16HighQPseudo
+  { 8, OperandInfo404 },  // Inst #2531 = VLD1q16HighQPseudo_UPD
+  { 6, OperandInfo403 },  // Inst #2532 = VLD1q16HighTPseudo
+  { 8, OperandInfo404 },  // Inst #2533 = VLD1q16HighTPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2534 = VLD1q16LowQPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2535 = VLD1q16LowTPseudo_UPD
+  { 6, OperandInfo394 },  // Inst #2536 = VLD1q16wb_fixed
+  { 7, OperandInfo395 },  // Inst #2537 = VLD1q16wb_register
+  { 5, OperandInfo393 },  // Inst #2538 = VLD1q32
+  { 6, OperandInfo403 },  // Inst #2539 = VLD1q32HighQPseudo
+  { 8, OperandInfo404 },  // Inst #2540 = VLD1q32HighQPseudo_UPD
+  { 6, OperandInfo403 },  // Inst #2541 = VLD1q32HighTPseudo
+  { 8, OperandInfo404 },  // Inst #2542 = VLD1q32HighTPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2543 = VLD1q32LowQPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2544 = VLD1q32LowTPseudo_UPD
+  { 6, OperandInfo394 },  // Inst #2545 = VLD1q32wb_fixed
+  { 7, OperandInfo395 },  // Inst #2546 = VLD1q32wb_register
+  { 5, OperandInfo393 },  // Inst #2547 = VLD1q64
+  { 6, OperandInfo403 },  // Inst #2548 = VLD1q64HighQPseudo
+  { 8, OperandInfo404 },  // Inst #2549 = VLD1q64HighQPseudo_UPD
+  { 6, OperandInfo403 },  // Inst #2550 = VLD1q64HighTPseudo
+  { 8, OperandInfo404 },  // Inst #2551 = VLD1q64HighTPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2552 = VLD1q64LowQPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2553 = VLD1q64LowTPseudo_UPD
+  { 6, OperandInfo394 },  // Inst #2554 = VLD1q64wb_fixed
+  { 7, OperandInfo395 },  // Inst #2555 = VLD1q64wb_register
+  { 5, OperandInfo393 },  // Inst #2556 = VLD1q8
+  { 6, OperandInfo403 },  // Inst #2557 = VLD1q8HighQPseudo
+  { 8, OperandInfo404 },  // Inst #2558 = VLD1q8HighQPseudo_UPD
+  { 6, OperandInfo403 },  // Inst #2559 = VLD1q8HighTPseudo
+  { 8, OperandInfo404 },  // Inst #2560 = VLD1q8HighTPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2561 = VLD1q8LowQPseudo_UPD
+  { 8, OperandInfo404 },  // Inst #2562 = VLD1q8LowTPseudo_UPD
+  { 6, OperandInfo394 },  // Inst #2563 = VLD1q8wb_fixed
+  { 7, OperandInfo395 },  // Inst #2564 = VLD1q8wb_register
+  { 5, OperandInfo393 },  // Inst #2565 = VLD2DUPd16
+  { 6, OperandInfo394 },  // Inst #2566 = VLD2DUPd16wb_fixed
+  { 7, OperandInfo395 },  // Inst #2567 = VLD2DUPd16wb_register
+  { 5, OperandInfo405 },  // Inst #2568 = VLD2DUPd16x2
+  { 6, OperandInfo406 },  // Inst #2569 = VLD2DUPd16x2wb_fixed
+  { 7, OperandInfo407 },  // Inst #2570 = VLD2DUPd16x2wb_register
+  { 5, OperandInfo393 },  // Inst #2571 = VLD2DUPd32
+  { 6, OperandInfo394 },  // Inst #2572 = VLD2DUPd32wb_fixed
+  { 7, OperandInfo395 },  // Inst #2573 = VLD2DUPd32wb_register
+  { 5, OperandInfo405 },  // Inst #2574 = VLD2DUPd32x2
+  { 6, OperandInfo406 },  // Inst #2575 = VLD2DUPd32x2wb_fixed
+  { 7, OperandInfo407 },  // Inst #2576 = VLD2DUPd32x2wb_register
+  { 5, OperandInfo393 },  // Inst #2577 = VLD2DUPd8
+  { 6, OperandInfo394 },  // Inst #2578 = VLD2DUPd8wb_fixed
+  { 7, OperandInfo395 },  // Inst #2579 = VLD2DUPd8wb_register
+  { 5, OperandInfo405 },  // Inst #2580 = VLD2DUPd8x2
+  { 6, OperandInfo406 },  // Inst #2581 = VLD2DUPd8x2wb_fixed
+  { 7, OperandInfo407 },  // Inst #2582 = VLD2DUPd8x2wb_register
+  { 5, OperandInfo400 },  // Inst #2583 = VLD2DUPq16EvenPseudo
+  { 5, OperandInfo400 },  // Inst #2584 = VLD2DUPq16OddPseudo
+  { 6, OperandInfo401 },  // Inst #2585 = VLD2DUPq16OddPseudoWB_fixed
+  { 7, OperandInfo408 },  // Inst #2586 = VLD2DUPq16OddPseudoWB_register
+  { 5, OperandInfo400 },  // Inst #2587 = VLD2DUPq32EvenPseudo
+  { 5, OperandInfo400 },  // Inst #2588 = VLD2DUPq32OddPseudo
+  { 6, OperandInfo401 },  // Inst #2589 = VLD2DUPq32OddPseudoWB_fixed
+  { 7, OperandInfo408 },  // Inst #2590 = VLD2DUPq32OddPseudoWB_register
+  { 5, OperandInfo400 },  // Inst #2591 = VLD2DUPq8EvenPseudo
+  { 5, OperandInfo400 },  // Inst #2592 = VLD2DUPq8OddPseudo
+  { 6, OperandInfo401 },  // Inst #2593 = VLD2DUPq8OddPseudoWB_fixed
+  { 7, OperandInfo408 },  // Inst #2594 = VLD2DUPq8OddPseudoWB_register
+  { 9, OperandInfo409 },  // Inst #2595 = VLD2LNd16
+  { 7, OperandInfo398 },  // Inst #2596 = VLD2LNd16Pseudo
+  { 9, OperandInfo399 },  // Inst #2597 = VLD2LNd16Pseudo_UPD
+  { 11, OperandInfo410 },  // Inst #2598 = VLD2LNd16_UPD
+  { 9, OperandInfo409 },  // Inst #2599 = VLD2LNd32
+  { 7, OperandInfo398 },  // Inst #2600 = VLD2LNd32Pseudo
+  { 9, OperandInfo399 },  // Inst #2601 = VLD2LNd32Pseudo_UPD
+  { 11, OperandInfo410 },  // Inst #2602 = VLD2LNd32_UPD
+  { 9, OperandInfo409 },  // Inst #2603 = VLD2LNd8
+  { 7, OperandInfo398 },  // Inst #2604 = VLD2LNd8Pseudo
+  { 9, OperandInfo399 },  // Inst #2605 = VLD2LNd8Pseudo_UPD
+  { 11, OperandInfo410 },  // Inst #2606 = VLD2LNd8_UPD
+  { 9, OperandInfo409 },  // Inst #2607 = VLD2LNq16
+  { 7, OperandInfo411 },  // Inst #2608 = VLD2LNq16Pseudo
+  { 9, OperandInfo412 },  // Inst #2609 = VLD2LNq16Pseudo_UPD
+  { 11, OperandInfo410 },  // Inst #2610 = VLD2LNq16_UPD
+  { 9, OperandInfo409 },  // Inst #2611 = VLD2LNq32
+  { 7, OperandInfo411 },  // Inst #2612 = VLD2LNq32Pseudo
+  { 9, OperandInfo412 },  // Inst #2613 = VLD2LNq32Pseudo_UPD
+  { 11, OperandInfo410 },  // Inst #2614 = VLD2LNq32_UPD
+  { 5, OperandInfo393 },  // Inst #2615 = VLD2b16
+  { 6, OperandInfo394 },  // Inst #2616 = VLD2b16wb_fixed
+  { 7, OperandInfo395 },  // Inst #2617 = VLD2b16wb_register
+  { 5, OperandInfo393 },  // Inst #2618 = VLD2b32
+  { 6, OperandInfo394 },  // Inst #2619 = VLD2b32wb_fixed
+  { 7, OperandInfo395 },  // Inst #2620 = VLD2b32wb_register
+  { 5, OperandInfo393 },  // Inst #2621 = VLD2b8
+  { 6, OperandInfo394 },  // Inst #2622 = VLD2b8wb_fixed
+  { 7, OperandInfo395 },  // Inst #2623 = VLD2b8wb_register
+  { 5, OperandInfo393 },  // Inst #2624 = VLD2d16
+  { 6, OperandInfo394 },  // Inst #2625 = VLD2d16wb_fixed
+  { 7, OperandInfo395 },  // Inst #2626 = VLD2d16wb_register
+  { 5, OperandInfo393 },  // Inst #2627 = VLD2d32
+  { 6, OperandInfo394 },  // Inst #2628 = VLD2d32wb_fixed
+  { 7, OperandInfo395 },  // Inst #2629 = VLD2d32wb_register
+  { 5, OperandInfo393 },  // Inst #2630 = VLD2d8
+  { 6, OperandInfo394 },  // Inst #2631 = VLD2d8wb_fixed
+  { 7, OperandInfo395 },  // Inst #2632 = VLD2d8wb_register
+  { 5, OperandInfo99 },  // Inst #2633 = VLD2q16
+  { 5, OperandInfo400 },  // Inst #2634 = VLD2q16Pseudo
+  { 6, OperandInfo401 },  // Inst #2635 = VLD2q16PseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2636 = VLD2q16PseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2637 = VLD2q16wb_fixed
+  { 7, OperandInfo392 },  // Inst #2638 = VLD2q16wb_register
+  { 5, OperandInfo99 },  // Inst #2639 = VLD2q32
+  { 5, OperandInfo400 },  // Inst #2640 = VLD2q32Pseudo
+  { 6, OperandInfo401 },  // Inst #2641 = VLD2q32PseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2642 = VLD2q32PseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2643 = VLD2q32wb_fixed
+  { 7, OperandInfo392 },  // Inst #2644 = VLD2q32wb_register
+  { 5, OperandInfo99 },  // Inst #2645 = VLD2q8
+  { 5, OperandInfo400 },  // Inst #2646 = VLD2q8Pseudo
+  { 6, OperandInfo401 },  // Inst #2647 = VLD2q8PseudoWB_fixed
+  { 7, OperandInfo402 },  // Inst #2648 = VLD2q8PseudoWB_register
+  { 6, OperandInfo391 },  // Inst #2649 = VLD2q8wb_fixed
+  { 7, OperandInfo392 },  // Inst #2650 = VLD2q8wb_register
+  { 7, OperandInfo413 },  // Inst #2651 = VLD3DUPd16
+  { 5, OperandInfo400 },  // Inst #2652 = VLD3DUPd16Pseudo
+  { 7, OperandInfo408 },  // Inst #2653 = VLD3DUPd16Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2654 = VLD3DUPd16_UPD
+  { 7, OperandInfo413 },  // Inst #2655 = VLD3DUPd32
+  { 5, OperandInfo400 },  // Inst #2656 = VLD3DUPd32Pseudo
+  { 7, OperandInfo408 },  // Inst #2657 = VLD3DUPd32Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2658 = VLD3DUPd32_UPD
+  { 7, OperandInfo413 },  // Inst #2659 = VLD3DUPd8
+  { 5, OperandInfo400 },  // Inst #2660 = VLD3DUPd8Pseudo
+  { 7, OperandInfo408 },  // Inst #2661 = VLD3DUPd8Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2662 = VLD3DUPd8_UPD
+  { 7, OperandInfo413 },  // Inst #2663 = VLD3DUPq16
+  { 6, OperandInfo403 },  // Inst #2664 = VLD3DUPq16EvenPseudo
+  { 6, OperandInfo403 },  // Inst #2665 = VLD3DUPq16OddPseudo
+  { 8, OperandInfo404 },  // Inst #2666 = VLD3DUPq16OddPseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2667 = VLD3DUPq16_UPD
+  { 7, OperandInfo413 },  // Inst #2668 = VLD3DUPq32
+  { 6, OperandInfo403 },  // Inst #2669 = VLD3DUPq32EvenPseudo
+  { 6, OperandInfo403 },  // Inst #2670 = VLD3DUPq32OddPseudo
+  { 8, OperandInfo404 },  // Inst #2671 = VLD3DUPq32OddPseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2672 = VLD3DUPq32_UPD
+  { 7, OperandInfo413 },  // Inst #2673 = VLD3DUPq8
+  { 6, OperandInfo403 },  // Inst #2674 = VLD3DUPq8EvenPseudo
+  { 6, OperandInfo403 },  // Inst #2675 = VLD3DUPq8OddPseudo
+  { 8, OperandInfo404 },  // Inst #2676 = VLD3DUPq8OddPseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2677 = VLD3DUPq8_UPD
+  { 11, OperandInfo415 },  // Inst #2678 = VLD3LNd16
+  { 7, OperandInfo411 },  // Inst #2679 = VLD3LNd16Pseudo
+  { 9, OperandInfo412 },  // Inst #2680 = VLD3LNd16Pseudo_UPD
+  { 13, OperandInfo416 },  // Inst #2681 = VLD3LNd16_UPD
+  { 11, OperandInfo415 },  // Inst #2682 = VLD3LNd32
+  { 7, OperandInfo411 },  // Inst #2683 = VLD3LNd32Pseudo
+  { 9, OperandInfo412 },  // Inst #2684 = VLD3LNd32Pseudo_UPD
+  { 13, OperandInfo416 },  // Inst #2685 = VLD3LNd32_UPD
+  { 11, OperandInfo415 },  // Inst #2686 = VLD3LNd8
+  { 7, OperandInfo411 },  // Inst #2687 = VLD3LNd8Pseudo
+  { 9, OperandInfo412 },  // Inst #2688 = VLD3LNd8Pseudo_UPD
+  { 13, OperandInfo416 },  // Inst #2689 = VLD3LNd8_UPD
+  { 11, OperandInfo415 },  // Inst #2690 = VLD3LNq16
+  { 7, OperandInfo417 },  // Inst #2691 = VLD3LNq16Pseudo
+  { 9, OperandInfo418 },  // Inst #2692 = VLD3LNq16Pseudo_UPD
+  { 13, OperandInfo416 },  // Inst #2693 = VLD3LNq16_UPD
+  { 11, OperandInfo415 },  // Inst #2694 = VLD3LNq32
+  { 7, OperandInfo417 },  // Inst #2695 = VLD3LNq32Pseudo
+  { 9, OperandInfo418 },  // Inst #2696 = VLD3LNq32Pseudo_UPD
+  { 13, OperandInfo416 },  // Inst #2697 = VLD3LNq32_UPD
+  { 7, OperandInfo413 },  // Inst #2698 = VLD3d16
+  { 5, OperandInfo400 },  // Inst #2699 = VLD3d16Pseudo
+  { 7, OperandInfo408 },  // Inst #2700 = VLD3d16Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2701 = VLD3d16_UPD
+  { 7, OperandInfo413 },  // Inst #2702 = VLD3d32
+  { 5, OperandInfo400 },  // Inst #2703 = VLD3d32Pseudo
+  { 7, OperandInfo408 },  // Inst #2704 = VLD3d32Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2705 = VLD3d32_UPD
+  { 7, OperandInfo413 },  // Inst #2706 = VLD3d8
+  { 5, OperandInfo400 },  // Inst #2707 = VLD3d8Pseudo
+  { 7, OperandInfo408 },  // Inst #2708 = VLD3d8Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2709 = VLD3d8_UPD
+  { 7, OperandInfo413 },  // Inst #2710 = VLD3q16
+  { 8, OperandInfo404 },  // Inst #2711 = VLD3q16Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2712 = VLD3q16_UPD
+  { 6, OperandInfo403 },  // Inst #2713 = VLD3q16oddPseudo
+  { 8, OperandInfo404 },  // Inst #2714 = VLD3q16oddPseudo_UPD
+  { 7, OperandInfo413 },  // Inst #2715 = VLD3q32
+  { 8, OperandInfo404 },  // Inst #2716 = VLD3q32Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2717 = VLD3q32_UPD
+  { 6, OperandInfo403 },  // Inst #2718 = VLD3q32oddPseudo
+  { 8, OperandInfo404 },  // Inst #2719 = VLD3q32oddPseudo_UPD
+  { 7, OperandInfo413 },  // Inst #2720 = VLD3q8
+  { 8, OperandInfo404 },  // Inst #2721 = VLD3q8Pseudo_UPD
+  { 9, OperandInfo414 },  // Inst #2722 = VLD3q8_UPD
+  { 6, OperandInfo403 },  // Inst #2723 = VLD3q8oddPseudo
+  { 8, OperandInfo404 },  // Inst #2724 = VLD3q8oddPseudo_UPD
+  { 8, OperandInfo419 },  // Inst #2725 = VLD4DUPd16
+  { 5, OperandInfo400 },  // Inst #2726 = VLD4DUPd16Pseudo
+  { 7, OperandInfo408 },  // Inst #2727 = VLD4DUPd16Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2728 = VLD4DUPd16_UPD
+  { 8, OperandInfo419 },  // Inst #2729 = VLD4DUPd32
+  { 5, OperandInfo400 },  // Inst #2730 = VLD4DUPd32Pseudo
+  { 7, OperandInfo408 },  // Inst #2731 = VLD4DUPd32Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2732 = VLD4DUPd32_UPD
+  { 8, OperandInfo419 },  // Inst #2733 = VLD4DUPd8
+  { 5, OperandInfo400 },  // Inst #2734 = VLD4DUPd8Pseudo
+  { 7, OperandInfo408 },  // Inst #2735 = VLD4DUPd8Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2736 = VLD4DUPd8_UPD
+  { 8, OperandInfo419 },  // Inst #2737 = VLD4DUPq16
+  { 6, OperandInfo403 },  // Inst #2738 = VLD4DUPq16EvenPseudo
+  { 6, OperandInfo403 },  // Inst #2739 = VLD4DUPq16OddPseudo
+  { 8, OperandInfo404 },  // Inst #2740 = VLD4DUPq16OddPseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2741 = VLD4DUPq16_UPD
+  { 8, OperandInfo419 },  // Inst #2742 = VLD4DUPq32
+  { 6, OperandInfo403 },  // Inst #2743 = VLD4DUPq32EvenPseudo
+  { 6, OperandInfo403 },  // Inst #2744 = VLD4DUPq32OddPseudo
+  { 8, OperandInfo404 },  // Inst #2745 = VLD4DUPq32OddPseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2746 = VLD4DUPq32_UPD
+  { 8, OperandInfo419 },  // Inst #2747 = VLD4DUPq8
+  { 6, OperandInfo403 },  // Inst #2748 = VLD4DUPq8EvenPseudo
+  { 6, OperandInfo403 },  // Inst #2749 = VLD4DUPq8OddPseudo
+  { 8, OperandInfo404 },  // Inst #2750 = VLD4DUPq8OddPseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2751 = VLD4DUPq8_UPD
+  { 13, OperandInfo421 },  // Inst #2752 = VLD4LNd16
+  { 7, OperandInfo411 },  // Inst #2753 = VLD4LNd16Pseudo
+  { 9, OperandInfo412 },  // Inst #2754 = VLD4LNd16Pseudo_UPD
+  { 15, OperandInfo422 },  // Inst #2755 = VLD4LNd16_UPD
+  { 13, OperandInfo421 },  // Inst #2756 = VLD4LNd32
+  { 7, OperandInfo411 },  // Inst #2757 = VLD4LNd32Pseudo
+  { 9, OperandInfo412 },  // Inst #2758 = VLD4LNd32Pseudo_UPD
+  { 15, OperandInfo422 },  // Inst #2759 = VLD4LNd32_UPD
+  { 13, OperandInfo421 },  // Inst #2760 = VLD4LNd8
+  { 7, OperandInfo411 },  // Inst #2761 = VLD4LNd8Pseudo
+  { 9, OperandInfo412 },  // Inst #2762 = VLD4LNd8Pseudo_UPD
+  { 15, OperandInfo422 },  // Inst #2763 = VLD4LNd8_UPD
+  { 13, OperandInfo421 },  // Inst #2764 = VLD4LNq16
+  { 7, OperandInfo417 },  // Inst #2765 = VLD4LNq16Pseudo
+  { 9, OperandInfo418 },  // Inst #2766 = VLD4LNq16Pseudo_UPD
+  { 15, OperandInfo422 },  // Inst #2767 = VLD4LNq16_UPD
+  { 13, OperandInfo421 },  // Inst #2768 = VLD4LNq32
+  { 7, OperandInfo417 },  // Inst #2769 = VLD4LNq32Pseudo
+  { 9, OperandInfo418 },  // Inst #2770 = VLD4LNq32Pseudo_UPD
+  { 15, OperandInfo422 },  // Inst #2771 = VLD4LNq32_UPD
+  { 8, OperandInfo419 },  // Inst #2772 = VLD4d16
+  { 5, OperandInfo400 },  // Inst #2773 = VLD4d16Pseudo
+  { 7, OperandInfo408 },  // Inst #2774 = VLD4d16Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2775 = VLD4d16_UPD
+  { 8, OperandInfo419 },  // Inst #2776 = VLD4d32
+  { 5, OperandInfo400 },  // Inst #2777 = VLD4d32Pseudo
+  { 7, OperandInfo408 },  // Inst #2778 = VLD4d32Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2779 = VLD4d32_UPD
+  { 8, OperandInfo419 },  // Inst #2780 = VLD4d8
+  { 5, OperandInfo400 },  // Inst #2781 = VLD4d8Pseudo
+  { 7, OperandInfo408 },  // Inst #2782 = VLD4d8Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2783 = VLD4d8_UPD
+  { 8, OperandInfo419 },  // Inst #2784 = VLD4q16
+  { 8, OperandInfo404 },  // Inst #2785 = VLD4q16Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2786 = VLD4q16_UPD
+  { 6, OperandInfo403 },  // Inst #2787 = VLD4q16oddPseudo
+  { 8, OperandInfo404 },  // Inst #2788 = VLD4q16oddPseudo_UPD
+  { 8, OperandInfo419 },  // Inst #2789 = VLD4q32
+  { 8, OperandInfo404 },  // Inst #2790 = VLD4q32Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2791 = VLD4q32_UPD
+  { 6, OperandInfo403 },  // Inst #2792 = VLD4q32oddPseudo
+  { 8, OperandInfo404 },  // Inst #2793 = VLD4q32oddPseudo_UPD
+  { 8, OperandInfo419 },  // Inst #2794 = VLD4q8
+  { 8, OperandInfo404 },  // Inst #2795 = VLD4q8Pseudo_UPD
+  { 10, OperandInfo420 },  // Inst #2796 = VLD4q8_UPD
+  { 6, OperandInfo403 },  // Inst #2797 = VLD4q8oddPseudo
+  { 8, OperandInfo404 },  // Inst #2798 = VLD4q8oddPseudo_UPD
+  { 5, OperandInfo66 },  // Inst #2799 = VLDMDDB_UPD
+  { 4, OperandInfo206 },  // Inst #2800 = VLDMDIA
+  { 5, OperandInfo66 },  // Inst #2801 = VLDMDIA_UPD
+  { 4, OperandInfo423 },  // Inst #2802 = VLDMQIA
+  { 5, OperandInfo66 },  // Inst #2803 = VLDMSDB_UPD
+  { 4, OperandInfo206 },  // Inst #2804 = VLDMSIA
+  { 5, OperandInfo66 },  // Inst #2805 = VLDMSIA_UPD
+  { 5, OperandInfo99 },  // Inst #2806 = VLDRD
+  { 5, OperandInfo424 },  // Inst #2807 = VLDRH
+  { 5, OperandInfo425 },  // Inst #2808 = VLDRS
+  { 4, OperandInfo426 },  // Inst #2809 = VLDR_FPCXTNS_off
+  { 5, OperandInfo427 },  // Inst #2810 = VLDR_FPCXTNS_post
+  { 5, OperandInfo427 },  // Inst #2811 = VLDR_FPCXTNS_pre
+  { 4, OperandInfo426 },  // Inst #2812 = VLDR_FPCXTS_off
+  { 5, OperandInfo427 },  // Inst #2813 = VLDR_FPCXTS_post
+  { 5, OperandInfo427 },  // Inst #2814 = VLDR_FPCXTS_pre
+  { 4, OperandInfo426 },  // Inst #2815 = VLDR_FPSCR_NZCVQC_off
+  { 5, OperandInfo427 },  // Inst #2816 = VLDR_FPSCR_NZCVQC_post
+  { 5, OperandInfo427 },  // Inst #2817 = VLDR_FPSCR_NZCVQC_pre
+  { 4, OperandInfo426 },  // Inst #2818 = VLDR_FPSCR_off
+  { 5, OperandInfo427 },  // Inst #2819 = VLDR_FPSCR_post
+  { 5, OperandInfo427 },  // Inst #2820 = VLDR_FPSCR_pre
+  { 5, OperandInfo428 },  // Inst #2821 = VLDR_P0_off
+  { 6, OperandInfo429 },  // Inst #2822 = VLDR_P0_post
+  { 6, OperandInfo429 },  // Inst #2823 = VLDR_P0_pre
+  { 4, OperandInfo426 },  // Inst #2824 = VLDR_VPR_off
+  { 5, OperandInfo427 },  // Inst #2825 = VLDR_VPR_post
+  { 5, OperandInfo427 },  // Inst #2826 = VLDR_VPR_pre
+  { 3, OperandInfo239 },  // Inst #2827 = VLLDM
+  { 3, OperandInfo239 },  // Inst #2828 = VLSTM
+  { 5, OperandInfo340 },  // Inst #2829 = VMAXfd
+  { 5, OperandInfo341 },  // Inst #2830 = VMAXfq
+  { 5, OperandInfo340 },  // Inst #2831 = VMAXhd
+  { 5, OperandInfo341 },  // Inst #2832 = VMAXhq
+  { 5, OperandInfo341 },  // Inst #2833 = VMAXsv16i8
+  { 5, OperandInfo340 },  // Inst #2834 = VMAXsv2i32
+  { 5, OperandInfo340 },  // Inst #2835 = VMAXsv4i16
+  { 5, OperandInfo341 },  // Inst #2836 = VMAXsv4i32
+  { 5, OperandInfo341 },  // Inst #2837 = VMAXsv8i16
+  { 5, OperandInfo340 },  // Inst #2838 = VMAXsv8i8
+  { 5, OperandInfo341 },  // Inst #2839 = VMAXuv16i8
+  { 5, OperandInfo340 },  // Inst #2840 = VMAXuv2i32
+  { 5, OperandInfo340 },  // Inst #2841 = VMAXuv4i16
+  { 5, OperandInfo341 },  // Inst #2842 = VMAXuv4i32
+  { 5, OperandInfo341 },  // Inst #2843 = VMAXuv8i16
+  { 5, OperandInfo340 },  // Inst #2844 = VMAXuv8i8
+  { 5, OperandInfo340 },  // Inst #2845 = VMINfd
+  { 5, OperandInfo341 },  // Inst #2846 = VMINfq
+  { 5, OperandInfo340 },  // Inst #2847 = VMINhd
+  { 5, OperandInfo341 },  // Inst #2848 = VMINhq
+  { 5, OperandInfo341 },  // Inst #2849 = VMINsv16i8
+  { 5, OperandInfo340 },  // Inst #2850 = VMINsv2i32
+  { 5, OperandInfo340 },  // Inst #2851 = VMINsv4i16
+  { 5, OperandInfo341 },  // Inst #2852 = VMINsv4i32
+  { 5, OperandInfo341 },  // Inst #2853 = VMINsv8i16
+  { 5, OperandInfo340 },  // Inst #2854 = VMINsv8i8
+  { 5, OperandInfo341 },  // Inst #2855 = VMINuv16i8
+  { 5, OperandInfo340 },  // Inst #2856 = VMINuv2i32
+  { 5, OperandInfo340 },  // Inst #2857 = VMINuv4i16
+  { 5, OperandInfo341 },  // Inst #2858 = VMINuv4i32
+  { 5, OperandInfo341 },  // Inst #2859 = VMINuv8i16
+  { 5, OperandInfo340 },  // Inst #2860 = VMINuv8i8
+  { 6, OperandInfo338 },  // Inst #2861 = VMLAD
+  { 6, OperandInfo381 },  // Inst #2862 = VMLAH
+  { 7, OperandInfo430 },  // Inst #2863 = VMLALslsv2i32
+  { 7, OperandInfo431 },  // Inst #2864 = VMLALslsv4i16
+  { 7, OperandInfo430 },  // Inst #2865 = VMLALsluv2i32
+  { 7, OperandInfo431 },  // Inst #2866 = VMLALsluv4i16
+  { 6, OperandInfo336 },  // Inst #2867 = VMLALsv2i64
+  { 6, OperandInfo336 },  // Inst #2868 = VMLALsv4i32
+  { 6, OperandInfo336 },  // Inst #2869 = VMLALsv8i16
+  { 6, OperandInfo336 },  // Inst #2870 = VMLALuv2i64
+  { 6, OperandInfo336 },  // Inst #2871 = VMLALuv4i32
+  { 6, OperandInfo336 },  // Inst #2872 = VMLALuv8i16
+  { 6, OperandInfo386 },  // Inst #2873 = VMLAS
+  { 6, OperandInfo338 },  // Inst #2874 = VMLAfd
+  { 6, OperandInfo337 },  // Inst #2875 = VMLAfq
+  { 6, OperandInfo338 },  // Inst #2876 = VMLAhd
+  { 6, OperandInfo337 },  // Inst #2877 = VMLAhq
+  { 7, OperandInfo432 },  // Inst #2878 = VMLAslfd
+  { 7, OperandInfo433 },  // Inst #2879 = VMLAslfq
+  { 7, OperandInfo434 },  // Inst #2880 = VMLAslhd
+  { 7, OperandInfo435 },  // Inst #2881 = VMLAslhq
+  { 7, OperandInfo432 },  // Inst #2882 = VMLAslv2i32
+  { 7, OperandInfo434 },  // Inst #2883 = VMLAslv4i16
+  { 7, OperandInfo433 },  // Inst #2884 = VMLAslv4i32
+  { 7, OperandInfo435 },  // Inst #2885 = VMLAslv8i16
+  { 6, OperandInfo337 },  // Inst #2886 = VMLAv16i8
+  { 6, OperandInfo338 },  // Inst #2887 = VMLAv2i32
+  { 6, OperandInfo338 },  // Inst #2888 = VMLAv4i16
+  { 6, OperandInfo337 },  // Inst #2889 = VMLAv4i32
+  { 6, OperandInfo337 },  // Inst #2890 = VMLAv8i16
+  { 6, OperandInfo338 },  // Inst #2891 = VMLAv8i8
+  { 6, OperandInfo338 },  // Inst #2892 = VMLSD
+  { 6, OperandInfo381 },  // Inst #2893 = VMLSH
+  { 7, OperandInfo430 },  // Inst #2894 = VMLSLslsv2i32
+  { 7, OperandInfo431 },  // Inst #2895 = VMLSLslsv4i16
+  { 7, OperandInfo430 },  // Inst #2896 = VMLSLsluv2i32
+  { 7, OperandInfo431 },  // Inst #2897 = VMLSLsluv4i16
+  { 6, OperandInfo336 },  // Inst #2898 = VMLSLsv2i64
+  { 6, OperandInfo336 },  // Inst #2899 = VMLSLsv4i32
+  { 6, OperandInfo336 },  // Inst #2900 = VMLSLsv8i16
+  { 6, OperandInfo336 },  // Inst #2901 = VMLSLuv2i64
+  { 6, OperandInfo336 },  // Inst #2902 = VMLSLuv4i32
+  { 6, OperandInfo336 },  // Inst #2903 = VMLSLuv8i16
+  { 6, OperandInfo386 },  // Inst #2904 = VMLSS
+  { 6, OperandInfo338 },  // Inst #2905 = VMLSfd
+  { 6, OperandInfo337 },  // Inst #2906 = VMLSfq
+  { 6, OperandInfo338 },  // Inst #2907 = VMLShd
+  { 6, OperandInfo337 },  // Inst #2908 = VMLShq
+  { 7, OperandInfo432 },  // Inst #2909 = VMLSslfd
+  { 7, OperandInfo433 },  // Inst #2910 = VMLSslfq
+  { 7, OperandInfo434 },  // Inst #2911 = VMLSslhd
+  { 7, OperandInfo435 },  // Inst #2912 = VMLSslhq
+  { 7, OperandInfo432 },  // Inst #2913 = VMLSslv2i32
+  { 7, OperandInfo434 },  // Inst #2914 = VMLSslv4i16
+  { 7, OperandInfo433 },  // Inst #2915 = VMLSslv4i32
+  { 7, OperandInfo435 },  // Inst #2916 = VMLSslv8i16
+  { 6, OperandInfo337 },  // Inst #2917 = VMLSv16i8
+  { 6, OperandInfo338 },  // Inst #2918 = VMLSv2i32
+  { 6, OperandInfo338 },  // Inst #2919 = VMLSv4i16
+  { 6, OperandInfo337 },  // Inst #2920 = VMLSv4i32
+  { 6, OperandInfo337 },  // Inst #2921 = VMLSv8i16
+  { 6, OperandInfo338 },  // Inst #2922 = VMLSv8i8
+  { 4, OperandInfo162 },  // Inst #2923 = VMMLA
+  { 4, OperandInfo342 },  // Inst #2924 = VMOVD
+  { 5, OperandInfo436 },  // Inst #2925 = VMOVDRR
+  { 2, OperandInfo369 },  // Inst #2926 = VMOVH
+  { 4, OperandInfo437 },  // Inst #2927 = VMOVHR
+  { 4, OperandInfo375 },  // Inst #2928 = VMOVLsv2i64
+  { 4, OperandInfo375 },  // Inst #2929 = VMOVLsv4i32
+  { 4, OperandInfo375 },  // Inst #2930 = VMOVLsv8i16
+  { 4, OperandInfo375 },  // Inst #2931 = VMOVLuv2i64
+  { 4, OperandInfo375 },  // Inst #2932 = VMOVLuv4i32
+  { 4, OperandInfo375 },  // Inst #2933 = VMOVLuv8i16
+  { 4, OperandInfo163 },  // Inst #2934 = VMOVNv2i32
+  { 4, OperandInfo163 },  // Inst #2935 = VMOVNv4i16
+  { 4, OperandInfo163 },  // Inst #2936 = VMOVNv8i8
+  { 4, OperandInfo438 },  // Inst #2937 = VMOVRH
+  { 5, OperandInfo439 },  // Inst #2938 = VMOVRRD
+  { 6, OperandInfo440 },  // Inst #2939 = VMOVRRS
+  { 4, OperandInfo441 },  // Inst #2940 = VMOVRS
+  { 4, OperandInfo344 },  // Inst #2941 = VMOVS
+  { 4, OperandInfo442 },  // Inst #2942 = VMOVSR
+  { 6, OperandInfo443 },  // Inst #2943 = VMOVSRR
+  { 4, OperandInfo444 },  // Inst #2944 = VMOVv16i8
+  { 4, OperandInfo203 },  // Inst #2945 = VMOVv1i64
+  { 4, OperandInfo203 },  // Inst #2946 = VMOVv2f32
+  { 4, OperandInfo203 },  // Inst #2947 = VMOVv2i32
+  { 4, OperandInfo444 },  // Inst #2948 = VMOVv2i64
+  { 4, OperandInfo444 },  // Inst #2949 = VMOVv4f32
+  { 4, OperandInfo203 },  // Inst #2950 = VMOVv4i16
+  { 4, OperandInfo444 },  // Inst #2951 = VMOVv4i32
+  { 4, OperandInfo444 },  // Inst #2952 = VMOVv8i16
+  { 4, OperandInfo203 },  // Inst #2953 = VMOVv8i8
+  { 3, OperandInfo239 },  // Inst #2954 = VMRS
+  { 3, OperandInfo137 },  // Inst #2955 = VMRS_FPCXTNS
+  { 3, OperandInfo137 },  // Inst #2956 = VMRS_FPCXTS
+  { 3, OperandInfo239 },  // Inst #2957 = VMRS_FPEXC
+  { 3, OperandInfo239 },  // Inst #2958 = VMRS_FPINST
+  { 3, OperandInfo239 },  // Inst #2959 = VMRS_FPINST2
+  { 4, OperandInfo445 },  // Inst #2960 = VMRS_FPSCR_NZCVQC
+  { 3, OperandInfo239 },  // Inst #2961 = VMRS_FPSID
+  { 3, OperandInfo239 },  // Inst #2962 = VMRS_MVFR0
+  { 3, OperandInfo239 },  // Inst #2963 = VMRS_MVFR1
+  { 3, OperandInfo239 },  // Inst #2964 = VMRS_MVFR2
+  { 4, OperandInfo446 },  // Inst #2965 = VMRS_P0
+  { 3, OperandInfo137 },  // Inst #2966 = VMRS_VPR
+  { 3, OperandInfo239 },  // Inst #2967 = VMSR
+  { 3, OperandInfo137 },  // Inst #2968 = VMSR_FPCXTNS
+  { 3, OperandInfo137 },  // Inst #2969 = VMSR_FPCXTS
+  { 3, OperandInfo239 },  // Inst #2970 = VMSR_FPEXC
+  { 3, OperandInfo239 },  // Inst #2971 = VMSR_FPINST
+  { 3, OperandInfo239 },  // Inst #2972 = VMSR_FPINST2
+  { 4, OperandInfo447 },  // Inst #2973 = VMSR_FPSCR_NZCVQC
+  { 3, OperandInfo239 },  // Inst #2974 = VMSR_FPSID
+  { 4, OperandInfo448 },  // Inst #2975 = VMSR_P0
+  { 3, OperandInfo137 },  // Inst #2976 = VMSR_VPR
+  { 5, OperandInfo340 },  // Inst #2977 = VMULD
+  { 5, OperandInfo346 },  // Inst #2978 = VMULH
+  { 3, OperandInfo384 },  // Inst #2979 = VMULLp64
+  { 5, OperandInfo339 },  // Inst #2980 = VMULLp8
+  { 6, OperandInfo449 },  // Inst #2981 = VMULLslsv2i32
+  { 6, OperandInfo450 },  // Inst #2982 = VMULLslsv4i16
+  { 6, OperandInfo449 },  // Inst #2983 = VMULLsluv2i32
+  { 6, OperandInfo450 },  // Inst #2984 = VMULLsluv4i16
+  { 5, OperandInfo339 },  // Inst #2985 = VMULLsv2i64
+  { 5, OperandInfo339 },  // Inst #2986 = VMULLsv4i32
+  { 5, OperandInfo339 },  // Inst #2987 = VMULLsv8i16
+  { 5, OperandInfo339 },  // Inst #2988 = VMULLuv2i64
+  { 5, OperandInfo339 },  // Inst #2989 = VMULLuv4i32
+  { 5, OperandInfo339 },  // Inst #2990 = VMULLuv8i16
+  { 5, OperandInfo348 },  // Inst #2991 = VMULS
+  { 5, OperandInfo340 },  // Inst #2992 = VMULfd
+  { 5, OperandInfo341 },  // Inst #2993 = VMULfq
+  { 5, OperandInfo340 },  // Inst #2994 = VMULhd
+  { 5, OperandInfo341 },  // Inst #2995 = VMULhq
+  { 5, OperandInfo340 },  // Inst #2996 = VMULpd
+  { 5, OperandInfo341 },  // Inst #2997 = VMULpq
+  { 6, OperandInfo451 },  // Inst #2998 = VMULslfd
+  { 6, OperandInfo452 },  // Inst #2999 = VMULslfq
+  { 6, OperandInfo453 },  // Inst #3000 = VMULslhd
+  { 6, OperandInfo454 },  // Inst #3001 = VMULslhq
+  { 6, OperandInfo451 },  // Inst #3002 = VMULslv2i32
+  { 6, OperandInfo453 },  // Inst #3003 = VMULslv4i16
+  { 6, OperandInfo452 },  // Inst #3004 = VMULslv4i32
+  { 6, OperandInfo454 },  // Inst #3005 = VMULslv8i16
+  { 5, OperandInfo341 },  // Inst #3006 = VMULv16i8
+  { 5, OperandInfo340 },  // Inst #3007 = VMULv2i32
+  { 5, OperandInfo340 },  // Inst #3008 = VMULv4i16
+  { 5, OperandInfo341 },  // Inst #3009 = VMULv4i32
+  { 5, OperandInfo341 },  // Inst #3010 = VMULv8i16
+  { 5, OperandInfo340 },  // Inst #3011 = VMULv8i8
+  { 4, OperandInfo342 },  // Inst #3012 = VMVNd
+  { 4, OperandInfo345 },  // Inst #3013 = VMVNq
+  { 4, OperandInfo203 },  // Inst #3014 = VMVNv2i32
+  { 4, OperandInfo203 },  // Inst #3015 = VMVNv4i16
+  { 4, OperandInfo444 },  // Inst #3016 = VMVNv4i32
+  { 4, OperandInfo444 },  // Inst #3017 = VMVNv8i16
+  { 4, OperandInfo342 },  // Inst #3018 = VNEGD
+  { 4, OperandInfo343 },  // Inst #3019 = VNEGH
+  { 4, OperandInfo344 },  // Inst #3020 = VNEGS
+  { 4, OperandInfo345 },  // Inst #3021 = VNEGf32q
+  { 4, OperandInfo342 },  // Inst #3022 = VNEGfd
+  { 4, OperandInfo342 },  // Inst #3023 = VNEGhd
+  { 4, OperandInfo345 },  // Inst #3024 = VNEGhq
+  { 4, OperandInfo342 },  // Inst #3025 = VNEGs16d
+  { 4, OperandInfo345 },  // Inst #3026 = VNEGs16q
+  { 4, OperandInfo342 },  // Inst #3027 = VNEGs32d
+  { 4, OperandInfo345 },  // Inst #3028 = VNEGs32q
+  { 4, OperandInfo342 },  // Inst #3029 = VNEGs8d
+  { 4, OperandInfo345 },  // Inst #3030 = VNEGs8q
+  { 6, OperandInfo338 },  // Inst #3031 = VNMLAD
+  { 6, OperandInfo381 },  // Inst #3032 = VNMLAH
+  { 6, OperandInfo386 },  // Inst #3033 = VNMLAS
+  { 6, OperandInfo338 },  // Inst #3034 = VNMLSD
+  { 6, OperandInfo381 },  // Inst #3035 = VNMLSH
+  { 6, OperandInfo386 },  // Inst #3036 = VNMLSS
+  { 5, OperandInfo340 },  // Inst #3037 = VNMULD
+  { 5, OperandInfo346 },  // Inst #3038 = VNMULH
+  { 5, OperandInfo348 },  // Inst #3039 = VNMULS
+  { 5, OperandInfo340 },  // Inst #3040 = VORNd
+  { 5, OperandInfo341 },  // Inst #3041 = VORNq
+  { 5, OperandInfo340 },  // Inst #3042 = VORRd
+  { 5, OperandInfo351 },  // Inst #3043 = VORRiv2i32
+  { 5, OperandInfo351 },  // Inst #3044 = VORRiv4i16
+  { 5, OperandInfo352 },  // Inst #3045 = VORRiv4i32
+  { 5, OperandInfo352 },  // Inst #3046 = VORRiv8i16
+  { 5, OperandInfo341 },  // Inst #3047 = VORRq
+  { 5, OperandInfo455 },  // Inst #3048 = VPADALsv16i8
+  { 5, OperandInfo102 },  // Inst #3049 = VPADALsv2i32
+  { 5, OperandInfo102 },  // Inst #3050 = VPADALsv4i16
+  { 5, OperandInfo455 },  // Inst #3051 = VPADALsv4i32
+  { 5, OperandInfo455 },  // Inst #3052 = VPADALsv8i16
+  { 5, OperandInfo102 },  // Inst #3053 = VPADALsv8i8
+  { 5, OperandInfo455 },  // Inst #3054 = VPADALuv16i8
+  { 5, OperandInfo102 },  // Inst #3055 = VPADALuv2i32
+  { 5, OperandInfo102 },  // Inst #3056 = VPADALuv4i16
+  { 5, OperandInfo455 },  // Inst #3057 = VPADALuv4i32
+  { 5, OperandInfo455 },  // Inst #3058 = VPADALuv8i16
+  { 5, OperandInfo102 },  // Inst #3059 = VPADALuv8i8
+  { 4, OperandInfo345 },  // Inst #3060 = VPADDLsv16i8
+  { 4, OperandInfo342 },  // Inst #3061 = VPADDLsv2i32
+  { 4, OperandInfo342 },  // Inst #3062 = VPADDLsv4i16
+  { 4, OperandInfo345 },  // Inst #3063 = VPADDLsv4i32
+  { 4, OperandInfo345 },  // Inst #3064 = VPADDLsv8i16
+  { 4, OperandInfo342 },  // Inst #3065 = VPADDLsv8i8
+  { 4, OperandInfo345 },  // Inst #3066 = VPADDLuv16i8
+  { 4, OperandInfo342 },  // Inst #3067 = VPADDLuv2i32
+  { 4, OperandInfo342 },  // Inst #3068 = VPADDLuv4i16
+  { 4, OperandInfo345 },  // Inst #3069 = VPADDLuv4i32
+  { 4, OperandInfo345 },  // Inst #3070 = VPADDLuv8i16
+  { 4, OperandInfo342 },  // Inst #3071 = VPADDLuv8i8
+  { 5, OperandInfo340 },  // Inst #3072 = VPADDf
+  { 5, OperandInfo340 },  // Inst #3073 = VPADDh
+  { 5, OperandInfo340 },  // Inst #3074 = VPADDi16
+  { 5, OperandInfo340 },  // Inst #3075 = VPADDi32
+  { 5, OperandInfo340 },  // Inst #3076 = VPADDi8
+  { 5, OperandInfo340 },  // Inst #3077 = VPMAXf
+  { 5, OperandInfo340 },  // Inst #3078 = VPMAXh
+  { 5, OperandInfo340 },  // Inst #3079 = VPMAXs16
+  { 5, OperandInfo340 },  // Inst #3080 = VPMAXs32
+  { 5, OperandInfo340 },  // Inst #3081 = VPMAXs8
+  { 5, OperandInfo340 },  // Inst #3082 = VPMAXu16
+  { 5, OperandInfo340 },  // Inst #3083 = VPMAXu32
+  { 5, OperandInfo340 },  // Inst #3084 = VPMAXu8
+  { 5, OperandInfo340 },  // Inst #3085 = VPMINf
+  { 5, OperandInfo340 },  // Inst #3086 = VPMINh
+  { 5, OperandInfo340 },  // Inst #3087 = VPMINs16
+  { 5, OperandInfo340 },  // Inst #3088 = VPMINs32
+  { 5, OperandInfo340 },  // Inst #3089 = VPMINs8
+  { 5, OperandInfo340 },  // Inst #3090 = VPMINu16
+  { 5, OperandInfo340 },  // Inst #3091 = VPMINu32
+  { 5, OperandInfo340 },  // Inst #3092 = VPMINu8
+  { 4, OperandInfo345 },  // Inst #3093 = VQABSv16i8
+  { 4, OperandInfo342 },  // Inst #3094 = VQABSv2i32
+  { 4, OperandInfo342 },  // Inst #3095 = VQABSv4i16
+  { 4, OperandInfo345 },  // Inst #3096 = VQABSv4i32
+  { 4, OperandInfo345 },  // Inst #3097 = VQABSv8i16
+  { 4, OperandInfo342 },  // Inst #3098 = VQABSv8i8
+  { 5, OperandInfo341 },  // Inst #3099 = VQADDsv16i8
+  { 5, OperandInfo340 },  // Inst #3100 = VQADDsv1i64
+  { 5, OperandInfo340 },  // Inst #3101 = VQADDsv2i32
+  { 5, OperandInfo341 },  // Inst #3102 = VQADDsv2i64
+  { 5, OperandInfo340 },  // Inst #3103 = VQADDsv4i16
+  { 5, OperandInfo341 },  // Inst #3104 = VQADDsv4i32
+  { 5, OperandInfo341 },  // Inst #3105 = VQADDsv8i16
+  { 5, OperandInfo340 },  // Inst #3106 = VQADDsv8i8
+  { 5, OperandInfo341 },  // Inst #3107 = VQADDuv16i8
+  { 5, OperandInfo340 },  // Inst #3108 = VQADDuv1i64
+  { 5, OperandInfo340 },  // Inst #3109 = VQADDuv2i32
+  { 5, OperandInfo341 },  // Inst #3110 = VQADDuv2i64
+  { 5, OperandInfo340 },  // Inst #3111 = VQADDuv4i16
+  { 5, OperandInfo341 },  // Inst #3112 = VQADDuv4i32
+  { 5, OperandInfo341 },  // Inst #3113 = VQADDuv8i16
+  { 5, OperandInfo340 },  // Inst #3114 = VQADDuv8i8
+  { 7, OperandInfo430 },  // Inst #3115 = VQDMLALslv2i32
+  { 7, OperandInfo431 },  // Inst #3116 = VQDMLALslv4i16
+  { 6, OperandInfo336 },  // Inst #3117 = VQDMLALv2i64
+  { 6, OperandInfo336 },  // Inst #3118 = VQDMLALv4i32
+  { 7, OperandInfo430 },  // Inst #3119 = VQDMLSLslv2i32
+  { 7, OperandInfo431 },  // Inst #3120 = VQDMLSLslv4i16
+  { 6, OperandInfo336 },  // Inst #3121 = VQDMLSLv2i64
+  { 6, OperandInfo336 },  // Inst #3122 = VQDMLSLv4i32
+  { 6, OperandInfo451 },  // Inst #3123 = VQDMULHslv2i32
+  { 6, OperandInfo453 },  // Inst #3124 = VQDMULHslv4i16
+  { 6, OperandInfo452 },  // Inst #3125 = VQDMULHslv4i32
+  { 6, OperandInfo454 },  // Inst #3126 = VQDMULHslv8i16
+  { 5, OperandInfo340 },  // Inst #3127 = VQDMULHv2i32
+  { 5, OperandInfo340 },  // Inst #3128 = VQDMULHv4i16
+  { 5, OperandInfo341 },  // Inst #3129 = VQDMULHv4i32
+  { 5, OperandInfo341 },  // Inst #3130 = VQDMULHv8i16
+  { 6, OperandInfo449 },  // Inst #3131 = VQDMULLslv2i32
+  { 6, OperandInfo450 },  // Inst #3132 = VQDMULLslv4i16
+  { 5, OperandInfo339 },  // Inst #3133 = VQDMULLv2i64
+  { 5, OperandInfo339 },  // Inst #3134 = VQDMULLv4i32
+  { 4, OperandInfo163 },  // Inst #3135 = VQMOVNsuv2i32
+  { 4, OperandInfo163 },  // Inst #3136 = VQMOVNsuv4i16
+  { 4, OperandInfo163 },  // Inst #3137 = VQMOVNsuv8i8
+  { 4, OperandInfo163 },  // Inst #3138 = VQMOVNsv2i32
+  { 4, OperandInfo163 },  // Inst #3139 = VQMOVNsv4i16
+  { 4, OperandInfo163 },  // Inst #3140 = VQMOVNsv8i8
+  { 4, OperandInfo163 },  // Inst #3141 = VQMOVNuv2i32
+  { 4, OperandInfo163 },  // Inst #3142 = VQMOVNuv4i16
+  { 4, OperandInfo163 },  // Inst #3143 = VQMOVNuv8i8
+  { 4, OperandInfo345 },  // Inst #3144 = VQNEGv16i8
+  { 4, OperandInfo342 },  // Inst #3145 = VQNEGv2i32
+  { 4, OperandInfo342 },  // Inst #3146 = VQNEGv4i16
+  { 4, OperandInfo345 },  // Inst #3147 = VQNEGv4i32
+  { 4, OperandInfo345 },  // Inst #3148 = VQNEGv8i16
+  { 4, OperandInfo342 },  // Inst #3149 = VQNEGv8i8
+  { 7, OperandInfo432 },  // Inst #3150 = VQRDMLAHslv2i32
+  { 7, OperandInfo434 },  // Inst #3151 = VQRDMLAHslv4i16
+  { 7, OperandInfo433 },  // Inst #3152 = VQRDMLAHslv4i32
+  { 7, OperandInfo435 },  // Inst #3153 = VQRDMLAHslv8i16
+  { 6, OperandInfo338 },  // Inst #3154 = VQRDMLAHv2i32
+  { 6, OperandInfo338 },  // Inst #3155 = VQRDMLAHv4i16
+  { 6, OperandInfo337 },  // Inst #3156 = VQRDMLAHv4i32
+  { 6, OperandInfo337 },  // Inst #3157 = VQRDMLAHv8i16
+  { 7, OperandInfo432 },  // Inst #3158 = VQRDMLSHslv2i32
+  { 7, OperandInfo434 },  // Inst #3159 = VQRDMLSHslv4i16
+  { 7, OperandInfo433 },  // Inst #3160 = VQRDMLSHslv4i32
+  { 7, OperandInfo435 },  // Inst #3161 = VQRDMLSHslv8i16
+  { 6, OperandInfo338 },  // Inst #3162 = VQRDMLSHv2i32
+  { 6, OperandInfo338 },  // Inst #3163 = VQRDMLSHv4i16
+  { 6, OperandInfo337 },  // Inst #3164 = VQRDMLSHv4i32
+  { 6, OperandInfo337 },  // Inst #3165 = VQRDMLSHv8i16
+  { 6, OperandInfo451 },  // Inst #3166 = VQRDMULHslv2i32
+  { 6, OperandInfo453 },  // Inst #3167 = VQRDMULHslv4i16
+  { 6, OperandInfo452 },  // Inst #3168 = VQRDMULHslv4i32
+  { 6, OperandInfo454 },  // Inst #3169 = VQRDMULHslv8i16
+  { 5, OperandInfo340 },  // Inst #3170 = VQRDMULHv2i32
+  { 5, OperandInfo340 },  // Inst #3171 = VQRDMULHv4i16
+  { 5, OperandInfo341 },  // Inst #3172 = VQRDMULHv4i32
+  { 5, OperandInfo341 },  // Inst #3173 = VQRDMULHv8i16
+  { 5, OperandInfo341 },  // Inst #3174 = VQRSHLsv16i8
+  { 5, OperandInfo340 },  // Inst #3175 = VQRSHLsv1i64
+  { 5, OperandInfo340 },  // Inst #3176 = VQRSHLsv2i32
+  { 5, OperandInfo341 },  // Inst #3177 = VQRSHLsv2i64
+  { 5, OperandInfo340 },  // Inst #3178 = VQRSHLsv4i16
+  { 5, OperandInfo341 },  // Inst #3179 = VQRSHLsv4i32
+  { 5, OperandInfo341 },  // Inst #3180 = VQRSHLsv8i16
+  { 5, OperandInfo340 },  // Inst #3181 = VQRSHLsv8i8
+  { 5, OperandInfo341 },  // Inst #3182 = VQRSHLuv16i8
+  { 5, OperandInfo340 },  // Inst #3183 = VQRSHLuv1i64
+  { 5, OperandInfo340 },  // Inst #3184 = VQRSHLuv2i32
+  { 5, OperandInfo341 },  // Inst #3185 = VQRSHLuv2i64
+  { 5, OperandInfo340 },  // Inst #3186 = VQRSHLuv4i16
+  { 5, OperandInfo341 },  // Inst #3187 = VQRSHLuv4i32
+  { 5, OperandInfo341 },  // Inst #3188 = VQRSHLuv8i16
+  { 5, OperandInfo340 },  // Inst #3189 = VQRSHLuv8i8
+  { 5, OperandInfo456 },  // Inst #3190 = VQRSHRNsv2i32
+  { 5, OperandInfo456 },  // Inst #3191 = VQRSHRNsv4i16
+  { 5, OperandInfo456 },  // Inst #3192 = VQRSHRNsv8i8
+  { 5, OperandInfo456 },  // Inst #3193 = VQRSHRNuv2i32
+  { 5, OperandInfo456 },  // Inst #3194 = VQRSHRNuv4i16
+  { 5, OperandInfo456 },  // Inst #3195 = VQRSHRNuv8i8
+  { 5, OperandInfo456 },  // Inst #3196 = VQRSHRUNv2i32
+  { 5, OperandInfo456 },  // Inst #3197 = VQRSHRUNv4i16
+  { 5, OperandInfo456 },  // Inst #3198 = VQRSHRUNv8i8
+  { 5, OperandInfo457 },  // Inst #3199 = VQSHLsiv16i8
+  { 5, OperandInfo458 },  // Inst #3200 = VQSHLsiv1i64
+  { 5, OperandInfo458 },  // Inst #3201 = VQSHLsiv2i32
+  { 5, OperandInfo457 },  // Inst #3202 = VQSHLsiv2i64
+  { 5, OperandInfo458 },  // Inst #3203 = VQSHLsiv4i16
+  { 5, OperandInfo457 },  // Inst #3204 = VQSHLsiv4i32
+  { 5, OperandInfo457 },  // Inst #3205 = VQSHLsiv8i16
+  { 5, OperandInfo458 },  // Inst #3206 = VQSHLsiv8i8
+  { 5, OperandInfo457 },  // Inst #3207 = VQSHLsuv16i8
+  { 5, OperandInfo458 },  // Inst #3208 = VQSHLsuv1i64
+  { 5, OperandInfo458 },  // Inst #3209 = VQSHLsuv2i32
+  { 5, OperandInfo457 },  // Inst #3210 = VQSHLsuv2i64
+  { 5, OperandInfo458 },  // Inst #3211 = VQSHLsuv4i16
+  { 5, OperandInfo457 },  // Inst #3212 = VQSHLsuv4i32
+  { 5, OperandInfo457 },  // Inst #3213 = VQSHLsuv8i16
+  { 5, OperandInfo458 },  // Inst #3214 = VQSHLsuv8i8
+  { 5, OperandInfo341 },  // Inst #3215 = VQSHLsv16i8
+  { 5, OperandInfo340 },  // Inst #3216 = VQSHLsv1i64
+  { 5, OperandInfo340 },  // Inst #3217 = VQSHLsv2i32
+  { 5, OperandInfo341 },  // Inst #3218 = VQSHLsv2i64
+  { 5, OperandInfo340 },  // Inst #3219 = VQSHLsv4i16
+  { 5, OperandInfo341 },  // Inst #3220 = VQSHLsv4i32
+  { 5, OperandInfo341 },  // Inst #3221 = VQSHLsv8i16
+  { 5, OperandInfo340 },  // Inst #3222 = VQSHLsv8i8
+  { 5, OperandInfo457 },  // Inst #3223 = VQSHLuiv16i8
+  { 5, OperandInfo458 },  // Inst #3224 = VQSHLuiv1i64
+  { 5, OperandInfo458 },  // Inst #3225 = VQSHLuiv2i32
+  { 5, OperandInfo457 },  // Inst #3226 = VQSHLuiv2i64
+  { 5, OperandInfo458 },  // Inst #3227 = VQSHLuiv4i16
+  { 5, OperandInfo457 },  // Inst #3228 = VQSHLuiv4i32
+  { 5, OperandInfo457 },  // Inst #3229 = VQSHLuiv8i16
+  { 5, OperandInfo458 },  // Inst #3230 = VQSHLuiv8i8
+  { 5, OperandInfo341 },  // Inst #3231 = VQSHLuv16i8
+  { 5, OperandInfo340 },  // Inst #3232 = VQSHLuv1i64
+  { 5, OperandInfo340 },  // Inst #3233 = VQSHLuv2i32
+  { 5, OperandInfo341 },  // Inst #3234 = VQSHLuv2i64
+  { 5, OperandInfo340 },  // Inst #3235 = VQSHLuv4i16
+  { 5, OperandInfo341 },  // Inst #3236 = VQSHLuv4i32
+  { 5, OperandInfo341 },  // Inst #3237 = VQSHLuv8i16
+  { 5, OperandInfo340 },  // Inst #3238 = VQSHLuv8i8
+  { 5, OperandInfo456 },  // Inst #3239 = VQSHRNsv2i32
+  { 5, OperandInfo456 },  // Inst #3240 = VQSHRNsv4i16
+  { 5, OperandInfo456 },  // Inst #3241 = VQSHRNsv8i8
+  { 5, OperandInfo456 },  // Inst #3242 = VQSHRNuv2i32
+  { 5, OperandInfo456 },  // Inst #3243 = VQSHRNuv4i16
+  { 5, OperandInfo456 },  // Inst #3244 = VQSHRNuv8i8
+  { 5, OperandInfo456 },  // Inst #3245 = VQSHRUNv2i32
+  { 5, OperandInfo456 },  // Inst #3246 = VQSHRUNv4i16
+  { 5, OperandInfo456 },  // Inst #3247 = VQSHRUNv8i8
+  { 5, OperandInfo341 },  // Inst #3248 = VQSUBsv16i8
+  { 5, OperandInfo340 },  // Inst #3249 = VQSUBsv1i64
+  { 5, OperandInfo340 },  // Inst #3250 = VQSUBsv2i32
+  { 5, OperandInfo341 },  // Inst #3251 = VQSUBsv2i64
+  { 5, OperandInfo340 },  // Inst #3252 = VQSUBsv4i16
+  { 5, OperandInfo341 },  // Inst #3253 = VQSUBsv4i32
+  { 5, OperandInfo341 },  // Inst #3254 = VQSUBsv8i16
+  { 5, OperandInfo340 },  // Inst #3255 = VQSUBsv8i8
+  { 5, OperandInfo341 },  // Inst #3256 = VQSUBuv16i8
+  { 5, OperandInfo340 },  // Inst #3257 = VQSUBuv1i64
+  { 5, OperandInfo340 },  // Inst #3258 = VQSUBuv2i32
+  { 5, OperandInfo341 },  // Inst #3259 = VQSUBuv2i64
+  { 5, OperandInfo340 },  // Inst #3260 = VQSUBuv4i16
+  { 5, OperandInfo341 },  // Inst #3261 = VQSUBuv4i32
+  { 5, OperandInfo341 },  // Inst #3262 = VQSUBuv8i16
+  { 5, OperandInfo340 },  // Inst #3263 = VQSUBuv8i8
+  { 5, OperandInfo347 },  // Inst #3264 = VRADDHNv2i32
+  { 5, OperandInfo347 },  // Inst #3265 = VRADDHNv4i16
+  { 5, OperandInfo347 },  // Inst #3266 = VRADDHNv8i8
+  { 4, OperandInfo342 },  // Inst #3267 = VRECPEd
+  { 4, OperandInfo342 },  // Inst #3268 = VRECPEfd
+  { 4, OperandInfo345 },  // Inst #3269 = VRECPEfq
+  { 4, OperandInfo342 },  // Inst #3270 = VRECPEhd
+  { 4, OperandInfo345 },  // Inst #3271 = VRECPEhq
+  { 4, OperandInfo345 },  // Inst #3272 = VRECPEq
+  { 5, OperandInfo340 },  // Inst #3273 = VRECPSfd
+  { 5, OperandInfo341 },  // Inst #3274 = VRECPSfq
+  { 5, OperandInfo340 },  // Inst #3275 = VRECPShd
+  { 5, OperandInfo341 },  // Inst #3276 = VRECPShq
+  { 4, OperandInfo342 },  // Inst #3277 = VREV16d8
+  { 4, OperandInfo345 },  // Inst #3278 = VREV16q8
+  { 4, OperandInfo342 },  // Inst #3279 = VREV32d16
+  { 4, OperandInfo342 },  // Inst #3280 = VREV32d8
+  { 4, OperandInfo345 },  // Inst #3281 = VREV32q16
+  { 4, OperandInfo345 },  // Inst #3282 = VREV32q8
+  { 4, OperandInfo342 },  // Inst #3283 = VREV64d16
+  { 4, OperandInfo342 },  // Inst #3284 = VREV64d32
+  { 4, OperandInfo342 },  // Inst #3285 = VREV64d8
+  { 4, OperandInfo345 },  // Inst #3286 = VREV64q16
+  { 4, OperandInfo345 },  // Inst #3287 = VREV64q32
+  { 4, OperandInfo345 },  // Inst #3288 = VREV64q8
+  { 5, OperandInfo341 },  // Inst #3289 = VRHADDsv16i8
+  { 5, OperandInfo340 },  // Inst #3290 = VRHADDsv2i32
+  { 5, OperandInfo340 },  // Inst #3291 = VRHADDsv4i16
+  { 5, OperandInfo341 },  // Inst #3292 = VRHADDsv4i32
+  { 5, OperandInfo341 },  // Inst #3293 = VRHADDsv8i16
+  { 5, OperandInfo340 },  // Inst #3294 = VRHADDsv8i8
+  { 5, OperandInfo341 },  // Inst #3295 = VRHADDuv16i8
+  { 5, OperandInfo340 },  // Inst #3296 = VRHADDuv2i32
+  { 5, OperandInfo340 },  // Inst #3297 = VRHADDuv4i16
+  { 5, OperandInfo341 },  // Inst #3298 = VRHADDuv4i32
+  { 5, OperandInfo341 },  // Inst #3299 = VRHADDuv8i16
+  { 5, OperandInfo340 },  // Inst #3300 = VRHADDuv8i8
+  { 2, OperandInfo366 },  // Inst #3301 = VRINTAD
+  { 2, OperandInfo459 },  // Inst #3302 = VRINTAH
+  { 2, OperandInfo366 },  // Inst #3303 = VRINTANDf
+  { 2, OperandInfo366 },  // Inst #3304 = VRINTANDh
+  { 2, OperandInfo158 },  // Inst #3305 = VRINTANQf
+  { 2, OperandInfo158 },  // Inst #3306 = VRINTANQh
+  { 2, OperandInfo369 },  // Inst #3307 = VRINTAS
+  { 2, OperandInfo366 },  // Inst #3308 = VRINTMD
+  { 2, OperandInfo459 },  // Inst #3309 = VRINTMH
+  { 2, OperandInfo366 },  // Inst #3310 = VRINTMNDf
+  { 2, OperandInfo366 },  // Inst #3311 = VRINTMNDh
+  { 2, OperandInfo158 },  // Inst #3312 = VRINTMNQf
+  { 2, OperandInfo158 },  // Inst #3313 = VRINTMNQh
+  { 2, OperandInfo369 },  // Inst #3314 = VRINTMS
+  { 2, OperandInfo366 },  // Inst #3315 = VRINTND
+  { 2, OperandInfo459 },  // Inst #3316 = VRINTNH
+  { 2, OperandInfo366 },  // Inst #3317 = VRINTNNDf
+  { 2, OperandInfo366 },  // Inst #3318 = VRINTNNDh
+  { 2, OperandInfo158 },  // Inst #3319 = VRINTNNQf
+  { 2, OperandInfo158 },  // Inst #3320 = VRINTNNQh
+  { 2, OperandInfo369 },  // Inst #3321 = VRINTNS
+  { 2, OperandInfo366 },  // Inst #3322 = VRINTPD
+  { 2, OperandInfo459 },  // Inst #3323 = VRINTPH
+  { 2, OperandInfo366 },  // Inst #3324 = VRINTPNDf
+  { 2, OperandInfo366 },  // Inst #3325 = VRINTPNDh
+  { 2, OperandInfo158 },  // Inst #3326 = VRINTPNQf
+  { 2, OperandInfo158 },  // Inst #3327 = VRINTPNQh
+  { 2, OperandInfo369 },  // Inst #3328 = VRINTPS
+  { 4, OperandInfo342 },  // Inst #3329 = VRINTRD
+  { 4, OperandInfo343 },  // Inst #3330 = VRINTRH
+  { 4, OperandInfo344 },  // Inst #3331 = VRINTRS
+  { 4, OperandInfo342 },  // Inst #3332 = VRINTXD
+  { 4, OperandInfo343 },  // Inst #3333 = VRINTXH
+  { 2, OperandInfo366 },  // Inst #3334 = VRINTXNDf
+  { 2, OperandInfo366 },  // Inst #3335 = VRINTXNDh
+  { 2, OperandInfo158 },  // Inst #3336 = VRINTXNQf
+  { 2, OperandInfo158 },  // Inst #3337 = VRINTXNQh
+  { 4, OperandInfo344 },  // Inst #3338 = VRINTXS
+  { 4, OperandInfo342 },  // Inst #3339 = VRINTZD
+  { 4, OperandInfo343 },  // Inst #3340 = VRINTZH
+  { 2, OperandInfo366 },  // Inst #3341 = VRINTZNDf
+  { 2, OperandInfo366 },  // Inst #3342 = VRINTZNDh
+  { 2, OperandInfo158 },  // Inst #3343 = VRINTZNQf
+  { 2, OperandInfo158 },  // Inst #3344 = VRINTZNQh
+  { 4, OperandInfo344 },  // Inst #3345 = VRINTZS
+  { 5, OperandInfo341 },  // Inst #3346 = VRSHLsv16i8
+  { 5, OperandInfo340 },  // Inst #3347 = VRSHLsv1i64
+  { 5, OperandInfo340 },  // Inst #3348 = VRSHLsv2i32
+  { 5, OperandInfo341 },  // Inst #3349 = VRSHLsv2i64
+  { 5, OperandInfo340 },  // Inst #3350 = VRSHLsv4i16
+  { 5, OperandInfo341 },  // Inst #3351 = VRSHLsv4i32
+  { 5, OperandInfo341 },  // Inst #3352 = VRSHLsv8i16
+  { 5, OperandInfo340 },  // Inst #3353 = VRSHLsv8i8
+  { 5, OperandInfo341 },  // Inst #3354 = VRSHLuv16i8
+  { 5, OperandInfo340 },  // Inst #3355 = VRSHLuv1i64
+  { 5, OperandInfo340 },  // Inst #3356 = VRSHLuv2i32
+  { 5, OperandInfo341 },  // Inst #3357 = VRSHLuv2i64
+  { 5, OperandInfo340 },  // Inst #3358 = VRSHLuv4i16
+  { 5, OperandInfo341 },  // Inst #3359 = VRSHLuv4i32
+  { 5, OperandInfo341 },  // Inst #3360 = VRSHLuv8i16
+  { 5, OperandInfo340 },  // Inst #3361 = VRSHLuv8i8
+  { 5, OperandInfo456 },  // Inst #3362 = VRSHRNv2i32
+  { 5, OperandInfo456 },  // Inst #3363 = VRSHRNv4i16
+  { 5, OperandInfo456 },  // Inst #3364 = VRSHRNv8i8
+  { 5, OperandInfo374 },  // Inst #3365 = VRSHRsv16i8
+  { 5, OperandInfo373 },  // Inst #3366 = VRSHRsv1i64
+  { 5, OperandInfo373 },  // Inst #3367 = VRSHRsv2i32
+  { 5, OperandInfo374 },  // Inst #3368 = VRSHRsv2i64
+  { 5, OperandInfo373 },  // Inst #3369 = VRSHRsv4i16
+  { 5, OperandInfo374 },  // Inst #3370 = VRSHRsv4i32
+  { 5, OperandInfo374 },  // Inst #3371 = VRSHRsv8i16
+  { 5, OperandInfo373 },  // Inst #3372 = VRSHRsv8i8
+  { 5, OperandInfo374 },  // Inst #3373 = VRSHRuv16i8
+  { 5, OperandInfo373 },  // Inst #3374 = VRSHRuv1i64
+  { 5, OperandInfo373 },  // Inst #3375 = VRSHRuv2i32
+  { 5, OperandInfo374 },  // Inst #3376 = VRSHRuv2i64
+  { 5, OperandInfo373 },  // Inst #3377 = VRSHRuv4i16
+  { 5, OperandInfo374 },  // Inst #3378 = VRSHRuv4i32
+  { 5, OperandInfo374 },  // Inst #3379 = VRSHRuv8i16
+  { 5, OperandInfo373 },  // Inst #3380 = VRSHRuv8i8
+  { 4, OperandInfo342 },  // Inst #3381 = VRSQRTEd
+  { 4, OperandInfo342 },  // Inst #3382 = VRSQRTEfd
+  { 4, OperandInfo345 },  // Inst #3383 = VRSQRTEfq
+  { 4, OperandInfo342 },  // Inst #3384 = VRSQRTEhd
+  { 4, OperandInfo345 },  // Inst #3385 = VRSQRTEhq
+  { 4, OperandInfo345 },  // Inst #3386 = VRSQRTEq
+  { 5, OperandInfo340 },  // Inst #3387 = VRSQRTSfd
+  { 5, OperandInfo341 },  // Inst #3388 = VRSQRTSfq
+  { 5, OperandInfo340 },  // Inst #3389 = VRSQRTShd
+  { 5, OperandInfo341 },  // Inst #3390 = VRSQRTShq
+  { 6, OperandInfo460 },  // Inst #3391 = VRSRAsv16i8
+  { 6, OperandInfo461 },  // Inst #3392 = VRSRAsv1i64
+  { 6, OperandInfo461 },  // Inst #3393 = VRSRAsv2i32
+  { 6, OperandInfo460 },  // Inst #3394 = VRSRAsv2i64
+  { 6, OperandInfo461 },  // Inst #3395 = VRSRAsv4i16
+  { 6, OperandInfo460 },  // Inst #3396 = VRSRAsv4i32
+  { 6, OperandInfo460 },  // Inst #3397 = VRSRAsv8i16
+  { 6, OperandInfo461 },  // Inst #3398 = VRSRAsv8i8
+  { 6, OperandInfo460 },  // Inst #3399 = VRSRAuv16i8
+  { 6, OperandInfo461 },  // Inst #3400 = VRSRAuv1i64
+  { 6, OperandInfo461 },  // Inst #3401 = VRSRAuv2i32
+  { 6, OperandInfo460 },  // Inst #3402 = VRSRAuv2i64
+  { 6, OperandInfo461 },  // Inst #3403 = VRSRAuv4i16
+  { 6, OperandInfo460 },  // Inst #3404 = VRSRAuv4i32
+  { 6, OperandInfo460 },  // Inst #3405 = VRSRAuv8i16
+  { 6, OperandInfo461 },  // Inst #3406 = VRSRAuv8i8
+  { 5, OperandInfo347 },  // Inst #3407 = VRSUBHNv2i32
+  { 5, OperandInfo347 },  // Inst #3408 = VRSUBHNv4i16
+  { 5, OperandInfo347 },  // Inst #3409 = VRSUBHNv8i8
+  { 3, OperandInfo150 },  // Inst #3410 = VSCCLRMD
+  { 3, OperandInfo150 },  // Inst #3411 = VSCCLRMS
+  { 4, OperandInfo161 },  // Inst #3412 = VSDOTD
+  { 5, OperandInfo159 },  // Inst #3413 = VSDOTDI
+  { 4, OperandInfo162 },  // Inst #3414 = VSDOTQ
+  { 5, OperandInfo160 },  // Inst #3415 = VSDOTQI
+  { 3, OperandInfo310 },  // Inst #3416 = VSELEQD
+  { 3, OperandInfo387 },  // Inst #3417 = VSELEQH
+  { 3, OperandInfo388 },  // Inst #3418 = VSELEQS
+  { 3, OperandInfo310 },  // Inst #3419 = VSELGED
+  { 3, OperandInfo387 },  // Inst #3420 = VSELGEH
+  { 3, OperandInfo388 },  // Inst #3421 = VSELGES
+  { 3, OperandInfo310 },  // Inst #3422 = VSELGTD
+  { 3, OperandInfo387 },  // Inst #3423 = VSELGTH
+  { 3, OperandInfo388 },  // Inst #3424 = VSELGTS
+  { 3, OperandInfo310 },  // Inst #3425 = VSELVSD
+  { 3, OperandInfo387 },  // Inst #3426 = VSELVSH
+  { 3, OperandInfo388 },  // Inst #3427 = VSELVSS
+  { 6, OperandInfo462 },  // Inst #3428 = VSETLNi16
+  { 6, OperandInfo462 },  // Inst #3429 = VSETLNi32
+  { 6, OperandInfo462 },  // Inst #3430 = VSETLNi8
+  { 5, OperandInfo378 },  // Inst #3431 = VSHLLi16
+  { 5, OperandInfo378 },  // Inst #3432 = VSHLLi32
+  { 5, OperandInfo378 },  // Inst #3433 = VSHLLi8
+  { 5, OperandInfo378 },  // Inst #3434 = VSHLLsv2i64
+  { 5, OperandInfo378 },  // Inst #3435 = VSHLLsv4i32
+  { 5, OperandInfo378 },  // Inst #3436 = VSHLLsv8i16
+  { 5, OperandInfo378 },  // Inst #3437 = VSHLLuv2i64
+  { 5, OperandInfo378 },  // Inst #3438 = VSHLLuv4i32
+  { 5, OperandInfo378 },  // Inst #3439 = VSHLLuv8i16
+  { 5, OperandInfo457 },  // Inst #3440 = VSHLiv16i8
+  { 5, OperandInfo458 },  // Inst #3441 = VSHLiv1i64
+  { 5, OperandInfo458 },  // Inst #3442 = VSHLiv2i32
+  { 5, OperandInfo457 },  // Inst #3443 = VSHLiv2i64
+  { 5, OperandInfo458 },  // Inst #3444 = VSHLiv4i16
+  { 5, OperandInfo457 },  // Inst #3445 = VSHLiv4i32
+  { 5, OperandInfo457 },  // Inst #3446 = VSHLiv8i16
+  { 5, OperandInfo458 },  // Inst #3447 = VSHLiv8i8
+  { 5, OperandInfo341 },  // Inst #3448 = VSHLsv16i8
+  { 5, OperandInfo340 },  // Inst #3449 = VSHLsv1i64
+  { 5, OperandInfo340 },  // Inst #3450 = VSHLsv2i32
+  { 5, OperandInfo341 },  // Inst #3451 = VSHLsv2i64
+  { 5, OperandInfo340 },  // Inst #3452 = VSHLsv4i16
+  { 5, OperandInfo341 },  // Inst #3453 = VSHLsv4i32
+  { 5, OperandInfo341 },  // Inst #3454 = VSHLsv8i16
+  { 5, OperandInfo340 },  // Inst #3455 = VSHLsv8i8
+  { 5, OperandInfo341 },  // Inst #3456 = VSHLuv16i8
+  { 5, OperandInfo340 },  // Inst #3457 = VSHLuv1i64
+  { 5, OperandInfo340 },  // Inst #3458 = VSHLuv2i32
+  { 5, OperandInfo341 },  // Inst #3459 = VSHLuv2i64
+  { 5, OperandInfo340 },  // Inst #3460 = VSHLuv4i16
+  { 5, OperandInfo341 },  // Inst #3461 = VSHLuv4i32
+  { 5, OperandInfo341 },  // Inst #3462 = VSHLuv8i16
+  { 5, OperandInfo340 },  // Inst #3463 = VSHLuv8i8
+  { 5, OperandInfo456 },  // Inst #3464 = VSHRNv2i32
+  { 5, OperandInfo456 },  // Inst #3465 = VSHRNv4i16
+  { 5, OperandInfo456 },  // Inst #3466 = VSHRNv8i8
+  { 5, OperandInfo374 },  // Inst #3467 = VSHRsv16i8
+  { 5, OperandInfo373 },  // Inst #3468 = VSHRsv1i64
+  { 5, OperandInfo373 },  // Inst #3469 = VSHRsv2i32
+  { 5, OperandInfo374 },  // Inst #3470 = VSHRsv2i64
+  { 5, OperandInfo373 },  // Inst #3471 = VSHRsv4i16
+  { 5, OperandInfo374 },  // Inst #3472 = VSHRsv4i32
+  { 5, OperandInfo374 },  // Inst #3473 = VSHRsv8i16
+  { 5, OperandInfo373 },  // Inst #3474 = VSHRsv8i8
+  { 5, OperandInfo374 },  // Inst #3475 = VSHRuv16i8
+  { 5, OperandInfo373 },  // Inst #3476 = VSHRuv1i64
+  { 5, OperandInfo373 },  // Inst #3477 = VSHRuv2i32
+  { 5, OperandInfo374 },  // Inst #3478 = VSHRuv2i64
+  { 5, OperandInfo373 },  // Inst #3479 = VSHRuv4i16
+  { 5, OperandInfo374 },  // Inst #3480 = VSHRuv4i32
+  { 5, OperandInfo374 },  // Inst #3481 = VSHRuv8i16
+  { 5, OperandInfo373 },  // Inst #3482 = VSHRuv8i8
+  { 5, OperandInfo463 },  // Inst #3483 = VSHTOD
+  { 5, OperandInfo464 },  // Inst #3484 = VSHTOH
+  { 5, OperandInfo464 },  // Inst #3485 = VSHTOS
+  { 4, OperandInfo371 },  // Inst #3486 = VSITOD
+  { 4, OperandInfo465 },  // Inst #3487 = VSITOH
+  { 4, OperandInfo344 },  // Inst #3488 = VSITOS
+  { 6, OperandInfo466 },  // Inst #3489 = VSLIv16i8
+  { 6, OperandInfo467 },  // Inst #3490 = VSLIv1i64
+  { 6, OperandInfo467 },  // Inst #3491 = VSLIv2i32
+  { 6, OperandInfo466 },  // Inst #3492 = VSLIv2i64
+  { 6, OperandInfo467 },  // Inst #3493 = VSLIv4i16
+  { 6, OperandInfo466 },  // Inst #3494 = VSLIv4i32
+  { 6, OperandInfo466 },  // Inst #3495 = VSLIv8i16
+  { 6, OperandInfo467 },  // Inst #3496 = VSLIv8i8
+  { 5, OperandInfo463 },  // Inst #3497 = VSLTOD
+  { 5, OperandInfo464 },  // Inst #3498 = VSLTOH
+  { 5, OperandInfo464 },  // Inst #3499 = VSLTOS
+  { 4, OperandInfo162 },  // Inst #3500 = VSMMLA
+  { 4, OperandInfo342 },  // Inst #3501 = VSQRTD
+  { 4, OperandInfo343 },  // Inst #3502 = VSQRTH
+  { 4, OperandInfo344 },  // Inst #3503 = VSQRTS
+  { 6, OperandInfo460 },  // Inst #3504 = VSRAsv16i8
+  { 6, OperandInfo461 },  // Inst #3505 = VSRAsv1i64
+  { 6, OperandInfo461 },  // Inst #3506 = VSRAsv2i32
+  { 6, OperandInfo460 },  // Inst #3507 = VSRAsv2i64
+  { 6, OperandInfo461 },  // Inst #3508 = VSRAsv4i16
+  { 6, OperandInfo460 },  // Inst #3509 = VSRAsv4i32
+  { 6, OperandInfo460 },  // Inst #3510 = VSRAsv8i16
+  { 6, OperandInfo461 },  // Inst #3511 = VSRAsv8i8
+  { 6, OperandInfo460 },  // Inst #3512 = VSRAuv16i8
+  { 6, OperandInfo461 },  // Inst #3513 = VSRAuv1i64
+  { 6, OperandInfo461 },  // Inst #3514 = VSRAuv2i32
+  { 6, OperandInfo460 },  // Inst #3515 = VSRAuv2i64
+  { 6, OperandInfo461 },  // Inst #3516 = VSRAuv4i16
+  { 6, OperandInfo460 },  // Inst #3517 = VSRAuv4i32
+  { 6, OperandInfo460 },  // Inst #3518 = VSRAuv8i16
+  { 6, OperandInfo461 },  // Inst #3519 = VSRAuv8i8
+  { 6, OperandInfo460 },  // Inst #3520 = VSRIv16i8
+  { 6, OperandInfo461 },  // Inst #3521 = VSRIv1i64
+  { 6, OperandInfo461 },  // Inst #3522 = VSRIv2i32
+  { 6, OperandInfo460 },  // Inst #3523 = VSRIv2i64
+  { 6, OperandInfo461 },  // Inst #3524 = VSRIv4i16
+  { 6, OperandInfo460 },  // Inst #3525 = VSRIv4i32
+  { 6, OperandInfo460 },  // Inst #3526 = VSRIv8i16
+  { 6, OperandInfo461 },  // Inst #3527 = VSRIv8i8
+  { 6, OperandInfo468 },  // Inst #3528 = VST1LNd16
+  { 8, OperandInfo469 },  // Inst #3529 = VST1LNd16_UPD
+  { 6, OperandInfo468 },  // Inst #3530 = VST1LNd32
+  { 8, OperandInfo469 },  // Inst #3531 = VST1LNd32_UPD
+  { 6, OperandInfo468 },  // Inst #3532 = VST1LNd8
+  { 8, OperandInfo469 },  // Inst #3533 = VST1LNd8_UPD
+  { 6, OperandInfo470 },  // Inst #3534 = VST1LNq16Pseudo
+  { 8, OperandInfo471 },  // Inst #3535 = VST1LNq16Pseudo_UPD
+  { 6, OperandInfo470 },  // Inst #3536 = VST1LNq32Pseudo
+  { 8, OperandInfo471 },  // Inst #3537 = VST1LNq32Pseudo_UPD
+  { 6, OperandInfo470 },  // Inst #3538 = VST1LNq8Pseudo
+  { 8, OperandInfo471 },  // Inst #3539 = VST1LNq8Pseudo_UPD
+  { 5, OperandInfo472 },  // Inst #3540 = VST1d16
+  { 5, OperandInfo472 },  // Inst #3541 = VST1d16Q
+  { 5, OperandInfo473 },  // Inst #3542 = VST1d16QPseudo
+  { 6, OperandInfo474 },  // Inst #3543 = VST1d16QPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3544 = VST1d16QPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3545 = VST1d16Qwb_fixed
+  { 7, OperandInfo477 },  // Inst #3546 = VST1d16Qwb_register
+  { 5, OperandInfo472 },  // Inst #3547 = VST1d16T
+  { 5, OperandInfo473 },  // Inst #3548 = VST1d16TPseudo
+  { 6, OperandInfo474 },  // Inst #3549 = VST1d16TPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3550 = VST1d16TPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3551 = VST1d16Twb_fixed
+  { 7, OperandInfo477 },  // Inst #3552 = VST1d16Twb_register
+  { 6, OperandInfo476 },  // Inst #3553 = VST1d16wb_fixed
+  { 7, OperandInfo477 },  // Inst #3554 = VST1d16wb_register
+  { 5, OperandInfo472 },  // Inst #3555 = VST1d32
+  { 5, OperandInfo472 },  // Inst #3556 = VST1d32Q
+  { 5, OperandInfo473 },  // Inst #3557 = VST1d32QPseudo
+  { 6, OperandInfo474 },  // Inst #3558 = VST1d32QPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3559 = VST1d32QPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3560 = VST1d32Qwb_fixed
+  { 7, OperandInfo477 },  // Inst #3561 = VST1d32Qwb_register
+  { 5, OperandInfo472 },  // Inst #3562 = VST1d32T
+  { 5, OperandInfo473 },  // Inst #3563 = VST1d32TPseudo
+  { 6, OperandInfo474 },  // Inst #3564 = VST1d32TPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3565 = VST1d32TPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3566 = VST1d32Twb_fixed
+  { 7, OperandInfo477 },  // Inst #3567 = VST1d32Twb_register
+  { 6, OperandInfo476 },  // Inst #3568 = VST1d32wb_fixed
+  { 7, OperandInfo477 },  // Inst #3569 = VST1d32wb_register
+  { 5, OperandInfo472 },  // Inst #3570 = VST1d64
+  { 5, OperandInfo472 },  // Inst #3571 = VST1d64Q
+  { 5, OperandInfo473 },  // Inst #3572 = VST1d64QPseudo
+  { 6, OperandInfo474 },  // Inst #3573 = VST1d64QPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3574 = VST1d64QPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3575 = VST1d64Qwb_fixed
+  { 7, OperandInfo477 },  // Inst #3576 = VST1d64Qwb_register
+  { 5, OperandInfo472 },  // Inst #3577 = VST1d64T
+  { 5, OperandInfo473 },  // Inst #3578 = VST1d64TPseudo
+  { 6, OperandInfo474 },  // Inst #3579 = VST1d64TPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3580 = VST1d64TPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3581 = VST1d64Twb_fixed
+  { 7, OperandInfo477 },  // Inst #3582 = VST1d64Twb_register
+  { 6, OperandInfo476 },  // Inst #3583 = VST1d64wb_fixed
+  { 7, OperandInfo477 },  // Inst #3584 = VST1d64wb_register
+  { 5, OperandInfo472 },  // Inst #3585 = VST1d8
+  { 5, OperandInfo472 },  // Inst #3586 = VST1d8Q
+  { 5, OperandInfo473 },  // Inst #3587 = VST1d8QPseudo
+  { 6, OperandInfo474 },  // Inst #3588 = VST1d8QPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3589 = VST1d8QPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3590 = VST1d8Qwb_fixed
+  { 7, OperandInfo477 },  // Inst #3591 = VST1d8Qwb_register
+  { 5, OperandInfo472 },  // Inst #3592 = VST1d8T
+  { 5, OperandInfo473 },  // Inst #3593 = VST1d8TPseudo
+  { 6, OperandInfo474 },  // Inst #3594 = VST1d8TPseudoWB_fixed
+  { 7, OperandInfo475 },  // Inst #3595 = VST1d8TPseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3596 = VST1d8Twb_fixed
+  { 7, OperandInfo477 },  // Inst #3597 = VST1d8Twb_register
+  { 6, OperandInfo476 },  // Inst #3598 = VST1d8wb_fixed
+  { 7, OperandInfo477 },  // Inst #3599 = VST1d8wb_register
+  { 5, OperandInfo478 },  // Inst #3600 = VST1q16
+  { 5, OperandInfo479 },  // Inst #3601 = VST1q16HighQPseudo
+  { 7, OperandInfo480 },  // Inst #3602 = VST1q16HighQPseudo_UPD
+  { 5, OperandInfo479 },  // Inst #3603 = VST1q16HighTPseudo
+  { 7, OperandInfo480 },  // Inst #3604 = VST1q16HighTPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3605 = VST1q16LowQPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3606 = VST1q16LowTPseudo_UPD
+  { 6, OperandInfo481 },  // Inst #3607 = VST1q16wb_fixed
+  { 7, OperandInfo482 },  // Inst #3608 = VST1q16wb_register
+  { 5, OperandInfo478 },  // Inst #3609 = VST1q32
+  { 5, OperandInfo479 },  // Inst #3610 = VST1q32HighQPseudo
+  { 7, OperandInfo480 },  // Inst #3611 = VST1q32HighQPseudo_UPD
+  { 5, OperandInfo479 },  // Inst #3612 = VST1q32HighTPseudo
+  { 7, OperandInfo480 },  // Inst #3613 = VST1q32HighTPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3614 = VST1q32LowQPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3615 = VST1q32LowTPseudo_UPD
+  { 6, OperandInfo481 },  // Inst #3616 = VST1q32wb_fixed
+  { 7, OperandInfo482 },  // Inst #3617 = VST1q32wb_register
+  { 5, OperandInfo478 },  // Inst #3618 = VST1q64
+  { 5, OperandInfo479 },  // Inst #3619 = VST1q64HighQPseudo
+  { 7, OperandInfo480 },  // Inst #3620 = VST1q64HighQPseudo_UPD
+  { 5, OperandInfo479 },  // Inst #3621 = VST1q64HighTPseudo
+  { 7, OperandInfo480 },  // Inst #3622 = VST1q64HighTPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3623 = VST1q64LowQPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3624 = VST1q64LowTPseudo_UPD
+  { 6, OperandInfo481 },  // Inst #3625 = VST1q64wb_fixed
+  { 7, OperandInfo482 },  // Inst #3626 = VST1q64wb_register
+  { 5, OperandInfo478 },  // Inst #3627 = VST1q8
+  { 5, OperandInfo479 },  // Inst #3628 = VST1q8HighQPseudo
+  { 7, OperandInfo480 },  // Inst #3629 = VST1q8HighQPseudo_UPD
+  { 5, OperandInfo479 },  // Inst #3630 = VST1q8HighTPseudo
+  { 7, OperandInfo480 },  // Inst #3631 = VST1q8HighTPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3632 = VST1q8LowQPseudo_UPD
+  { 7, OperandInfo480 },  // Inst #3633 = VST1q8LowTPseudo_UPD
+  { 6, OperandInfo481 },  // Inst #3634 = VST1q8wb_fixed
+  { 7, OperandInfo482 },  // Inst #3635 = VST1q8wb_register
+  { 7, OperandInfo483 },  // Inst #3636 = VST2LNd16
+  { 6, OperandInfo470 },  // Inst #3637 = VST2LNd16Pseudo
+  { 8, OperandInfo471 },  // Inst #3638 = VST2LNd16Pseudo_UPD
+  { 9, OperandInfo484 },  // Inst #3639 = VST2LNd16_UPD
+  { 7, OperandInfo483 },  // Inst #3640 = VST2LNd32
+  { 6, OperandInfo470 },  // Inst #3641 = VST2LNd32Pseudo
+  { 8, OperandInfo471 },  // Inst #3642 = VST2LNd32Pseudo_UPD
+  { 9, OperandInfo484 },  // Inst #3643 = VST2LNd32_UPD
+  { 7, OperandInfo483 },  // Inst #3644 = VST2LNd8
+  { 6, OperandInfo470 },  // Inst #3645 = VST2LNd8Pseudo
+  { 8, OperandInfo471 },  // Inst #3646 = VST2LNd8Pseudo_UPD
+  { 9, OperandInfo484 },  // Inst #3647 = VST2LNd8_UPD
+  { 7, OperandInfo483 },  // Inst #3648 = VST2LNq16
+  { 6, OperandInfo485 },  // Inst #3649 = VST2LNq16Pseudo
+  { 8, OperandInfo486 },  // Inst #3650 = VST2LNq16Pseudo_UPD
+  { 9, OperandInfo484 },  // Inst #3651 = VST2LNq16_UPD
+  { 7, OperandInfo483 },  // Inst #3652 = VST2LNq32
+  { 6, OperandInfo485 },  // Inst #3653 = VST2LNq32Pseudo
+  { 8, OperandInfo486 },  // Inst #3654 = VST2LNq32Pseudo_UPD
+  { 9, OperandInfo484 },  // Inst #3655 = VST2LNq32_UPD
+  { 5, OperandInfo478 },  // Inst #3656 = VST2b16
+  { 6, OperandInfo481 },  // Inst #3657 = VST2b16wb_fixed
+  { 7, OperandInfo482 },  // Inst #3658 = VST2b16wb_register
+  { 5, OperandInfo478 },  // Inst #3659 = VST2b32
+  { 6, OperandInfo481 },  // Inst #3660 = VST2b32wb_fixed
+  { 7, OperandInfo482 },  // Inst #3661 = VST2b32wb_register
+  { 5, OperandInfo478 },  // Inst #3662 = VST2b8
+  { 6, OperandInfo481 },  // Inst #3663 = VST2b8wb_fixed
+  { 7, OperandInfo482 },  // Inst #3664 = VST2b8wb_register
+  { 5, OperandInfo478 },  // Inst #3665 = VST2d16
+  { 6, OperandInfo481 },  // Inst #3666 = VST2d16wb_fixed
+  { 7, OperandInfo482 },  // Inst #3667 = VST2d16wb_register
+  { 5, OperandInfo478 },  // Inst #3668 = VST2d32
+  { 6, OperandInfo481 },  // Inst #3669 = VST2d32wb_fixed
+  { 7, OperandInfo482 },  // Inst #3670 = VST2d32wb_register
+  { 5, OperandInfo478 },  // Inst #3671 = VST2d8
+  { 6, OperandInfo481 },  // Inst #3672 = VST2d8wb_fixed
+  { 7, OperandInfo482 },  // Inst #3673 = VST2d8wb_register
+  { 5, OperandInfo472 },  // Inst #3674 = VST2q16
+  { 5, OperandInfo473 },  // Inst #3675 = VST2q16Pseudo
+  { 6, OperandInfo474 },  // Inst #3676 = VST2q16PseudoWB_fixed
+  { 7, OperandInfo487 },  // Inst #3677 = VST2q16PseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3678 = VST2q16wb_fixed
+  { 7, OperandInfo477 },  // Inst #3679 = VST2q16wb_register
+  { 5, OperandInfo472 },  // Inst #3680 = VST2q32
+  { 5, OperandInfo473 },  // Inst #3681 = VST2q32Pseudo
+  { 6, OperandInfo474 },  // Inst #3682 = VST2q32PseudoWB_fixed
+  { 7, OperandInfo487 },  // Inst #3683 = VST2q32PseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3684 = VST2q32wb_fixed
+  { 7, OperandInfo477 },  // Inst #3685 = VST2q32wb_register
+  { 5, OperandInfo472 },  // Inst #3686 = VST2q8
+  { 5, OperandInfo473 },  // Inst #3687 = VST2q8Pseudo
+  { 6, OperandInfo474 },  // Inst #3688 = VST2q8PseudoWB_fixed
+  { 7, OperandInfo487 },  // Inst #3689 = VST2q8PseudoWB_register
+  { 6, OperandInfo476 },  // Inst #3690 = VST2q8wb_fixed
+  { 7, OperandInfo477 },  // Inst #3691 = VST2q8wb_register
+  { 8, OperandInfo488 },  // Inst #3692 = VST3LNd16
+  { 6, OperandInfo485 },  // Inst #3693 = VST3LNd16Pseudo
+  { 8, OperandInfo486 },  // Inst #3694 = VST3LNd16Pseudo_UPD
+  { 10, OperandInfo489 },  // Inst #3695 = VST3LNd16_UPD
+  { 8, OperandInfo488 },  // Inst #3696 = VST3LNd32
+  { 6, OperandInfo485 },  // Inst #3697 = VST3LNd32Pseudo
+  { 8, OperandInfo486 },  // Inst #3698 = VST3LNd32Pseudo_UPD
+  { 10, OperandInfo489 },  // Inst #3699 = VST3LNd32_UPD
+  { 8, OperandInfo488 },  // Inst #3700 = VST3LNd8
+  { 6, OperandInfo485 },  // Inst #3701 = VST3LNd8Pseudo
+  { 8, OperandInfo486 },  // Inst #3702 = VST3LNd8Pseudo_UPD
+  { 10, OperandInfo489 },  // Inst #3703 = VST3LNd8_UPD
+  { 8, OperandInfo488 },  // Inst #3704 = VST3LNq16
+  { 6, OperandInfo490 },  // Inst #3705 = VST3LNq16Pseudo
+  { 8, OperandInfo491 },  // Inst #3706 = VST3LNq16Pseudo_UPD
+  { 10, OperandInfo489 },  // Inst #3707 = VST3LNq16_UPD
+  { 8, OperandInfo488 },  // Inst #3708 = VST3LNq32
+  { 6, OperandInfo490 },  // Inst #3709 = VST3LNq32Pseudo
+  { 8, OperandInfo491 },  // Inst #3710 = VST3LNq32Pseudo_UPD
+  { 10, OperandInfo489 },  // Inst #3711 = VST3LNq32_UPD
+  { 7, OperandInfo492 },  // Inst #3712 = VST3d16
+  { 5, OperandInfo473 },  // Inst #3713 = VST3d16Pseudo
+  { 7, OperandInfo475 },  // Inst #3714 = VST3d16Pseudo_UPD
+  { 9, OperandInfo493 },  // Inst #3715 = VST3d16_UPD
+  { 7, OperandInfo492 },  // Inst #3716 = VST3d32
+  { 5, OperandInfo473 },  // Inst #3717 = VST3d32Pseudo
+  { 7, OperandInfo475 },  // Inst #3718 = VST3d32Pseudo_UPD
+  { 9, OperandInfo493 },  // Inst #3719 = VST3d32_UPD
+  { 7, OperandInfo492 },  // Inst #3720 = VST3d8
+  { 5, OperandInfo473 },  // Inst #3721 = VST3d8Pseudo
+  { 7, OperandInfo475 },  // Inst #3722 = VST3d8Pseudo_UPD
+  { 9, OperandInfo493 },  // Inst #3723 = VST3d8_UPD
+  { 7, OperandInfo492 },  // Inst #3724 = VST3q16
+  { 7, OperandInfo480 },  // Inst #3725 = VST3q16Pseudo_UPD
+  { 9, OperandInfo493 },  // Inst #3726 = VST3q16_UPD
+  { 5, OperandInfo479 },  // Inst #3727 = VST3q16oddPseudo
+  { 7, OperandInfo480 },  // Inst #3728 = VST3q16oddPseudo_UPD
+  { 7, OperandInfo492 },  // Inst #3729 = VST3q32
+  { 7, OperandInfo480 },  // Inst #3730 = VST3q32Pseudo_UPD
+  { 9, OperandInfo493 },  // Inst #3731 = VST3q32_UPD
+  { 5, OperandInfo479 },  // Inst #3732 = VST3q32oddPseudo
+  { 7, OperandInfo480 },  // Inst #3733 = VST3q32oddPseudo_UPD
+  { 7, OperandInfo492 },  // Inst #3734 = VST3q8
+  { 7, OperandInfo480 },  // Inst #3735 = VST3q8Pseudo_UPD
+  { 9, OperandInfo493 },  // Inst #3736 = VST3q8_UPD
+  { 5, OperandInfo479 },  // Inst #3737 = VST3q8oddPseudo
+  { 7, OperandInfo480 },  // Inst #3738 = VST3q8oddPseudo_UPD
+  { 9, OperandInfo494 },  // Inst #3739 = VST4LNd16
+  { 6, OperandInfo485 },  // Inst #3740 = VST4LNd16Pseudo
+  { 8, OperandInfo486 },  // Inst #3741 = VST4LNd16Pseudo_UPD
+  { 11, OperandInfo495 },  // Inst #3742 = VST4LNd16_UPD
+  { 9, OperandInfo494 },  // Inst #3743 = VST4LNd32
+  { 6, OperandInfo485 },  // Inst #3744 = VST4LNd32Pseudo
+  { 8, OperandInfo486 },  // Inst #3745 = VST4LNd32Pseudo_UPD
+  { 11, OperandInfo495 },  // Inst #3746 = VST4LNd32_UPD
+  { 9, OperandInfo494 },  // Inst #3747 = VST4LNd8
+  { 6, OperandInfo485 },  // Inst #3748 = VST4LNd8Pseudo
+  { 8, OperandInfo486 },  // Inst #3749 = VST4LNd8Pseudo_UPD
+  { 11, OperandInfo495 },  // Inst #3750 = VST4LNd8_UPD
+  { 9, OperandInfo494 },  // Inst #3751 = VST4LNq16
+  { 6, OperandInfo490 },  // Inst #3752 = VST4LNq16Pseudo
+  { 8, OperandInfo491 },  // Inst #3753 = VST4LNq16Pseudo_UPD
+  { 11, OperandInfo495 },  // Inst #3754 = VST4LNq16_UPD
+  { 9, OperandInfo494 },  // Inst #3755 = VST4LNq32
+  { 6, OperandInfo490 },  // Inst #3756 = VST4LNq32Pseudo
+  { 8, OperandInfo491 },  // Inst #3757 = VST4LNq32Pseudo_UPD
+  { 11, OperandInfo495 },  // Inst #3758 = VST4LNq32_UPD
+  { 8, OperandInfo496 },  // Inst #3759 = VST4d16
+  { 5, OperandInfo473 },  // Inst #3760 = VST4d16Pseudo
+  { 7, OperandInfo475 },  // Inst #3761 = VST4d16Pseudo_UPD
+  { 10, OperandInfo497 },  // Inst #3762 = VST4d16_UPD
+  { 8, OperandInfo496 },  // Inst #3763 = VST4d32
+  { 5, OperandInfo473 },  // Inst #3764 = VST4d32Pseudo
+  { 7, OperandInfo475 },  // Inst #3765 = VST4d32Pseudo_UPD
+  { 10, OperandInfo497 },  // Inst #3766 = VST4d32_UPD
+  { 8, OperandInfo496 },  // Inst #3767 = VST4d8
+  { 5, OperandInfo473 },  // Inst #3768 = VST4d8Pseudo
+  { 7, OperandInfo475 },  // Inst #3769 = VST4d8Pseudo_UPD
+  { 10, OperandInfo497 },  // Inst #3770 = VST4d8_UPD
+  { 8, OperandInfo496 },  // Inst #3771 = VST4q16
+  { 7, OperandInfo480 },  // Inst #3772 = VST4q16Pseudo_UPD
+  { 10, OperandInfo497 },  // Inst #3773 = VST4q16_UPD
+  { 5, OperandInfo479 },  // Inst #3774 = VST4q16oddPseudo
+  { 7, OperandInfo480 },  // Inst #3775 = VST4q16oddPseudo_UPD
+  { 8, OperandInfo496 },  // Inst #3776 = VST4q32
+  { 7, OperandInfo480 },  // Inst #3777 = VST4q32Pseudo_UPD
+  { 10, OperandInfo497 },  // Inst #3778 = VST4q32_UPD
+  { 5, OperandInfo479 },  // Inst #3779 = VST4q32oddPseudo
+  { 7, OperandInfo480 },  // Inst #3780 = VST4q32oddPseudo_UPD
+  { 8, OperandInfo496 },  // Inst #3781 = VST4q8
+  { 7, OperandInfo480 },  // Inst #3782 = VST4q8Pseudo_UPD
+  { 10, OperandInfo497 },  // Inst #3783 = VST4q8_UPD
+  { 5, OperandInfo479 },  // Inst #3784 = VST4q8oddPseudo
+  { 7, OperandInfo480 },  // Inst #3785 = VST4q8oddPseudo_UPD
+  { 5, OperandInfo66 },  // Inst #3786 = VSTMDDB_UPD
+  { 4, OperandInfo206 },  // Inst #3787 = VSTMDIA
+  { 5, OperandInfo66 },  // Inst #3788 = VSTMDIA_UPD
+  { 4, OperandInfo423 },  // Inst #3789 = VSTMQIA
+  { 5, OperandInfo66 },  // Inst #3790 = VSTMSDB_UPD
+  { 4, OperandInfo206 },  // Inst #3791 = VSTMSIA
+  { 5, OperandInfo66 },  // Inst #3792 = VSTMSIA_UPD
+  { 5, OperandInfo99 },  // Inst #3793 = VSTRD
+  { 5, OperandInfo424 },  // Inst #3794 = VSTRH
+  { 5, OperandInfo425 },  // Inst #3795 = VSTRS
+  { 4, OperandInfo426 },  // Inst #3796 = VSTR_FPCXTNS_off
+  { 5, OperandInfo427 },  // Inst #3797 = VSTR_FPCXTNS_post
+  { 5, OperandInfo427 },  // Inst #3798 = VSTR_FPCXTNS_pre
+  { 4, OperandInfo426 },  // Inst #3799 = VSTR_FPCXTS_off
+  { 5, OperandInfo427 },  // Inst #3800 = VSTR_FPCXTS_post
+  { 5, OperandInfo427 },  // Inst #3801 = VSTR_FPCXTS_pre
+  { 4, OperandInfo426 },  // Inst #3802 = VSTR_FPSCR_NZCVQC_off
+  { 5, OperandInfo427 },  // Inst #3803 = VSTR_FPSCR_NZCVQC_post
+  { 5, OperandInfo427 },  // Inst #3804 = VSTR_FPSCR_NZCVQC_pre
+  { 4, OperandInfo426 },  // Inst #3805 = VSTR_FPSCR_off
+  { 5, OperandInfo427 },  // Inst #3806 = VSTR_FPSCR_post
+  { 5, OperandInfo427 },  // Inst #3807 = VSTR_FPSCR_pre
+  { 5, OperandInfo428 },  // Inst #3808 = VSTR_P0_off
+  { 6, OperandInfo498 },  // Inst #3809 = VSTR_P0_post
+  { 6, OperandInfo498 },  // Inst #3810 = VSTR_P0_pre
+  { 4, OperandInfo426 },  // Inst #3811 = VSTR_VPR_off
+  { 5, OperandInfo427 },  // Inst #3812 = VSTR_VPR_post
+  { 5, OperandInfo427 },  // Inst #3813 = VSTR_VPR_pre
+  { 5, OperandInfo340 },  // Inst #3814 = VSUBD
+  { 5, OperandInfo346 },  // Inst #3815 = VSUBH
+  { 5, OperandInfo347 },  // Inst #3816 = VSUBHNv2i32
+  { 5, OperandInfo347 },  // Inst #3817 = VSUBHNv4i16
+  { 5, OperandInfo347 },  // Inst #3818 = VSUBHNv8i8
+  { 5, OperandInfo339 },  // Inst #3819 = VSUBLsv2i64
+  { 5, OperandInfo339 },  // Inst #3820 = VSUBLsv4i32
+  { 5, OperandInfo339 },  // Inst #3821 = VSUBLsv8i16
+  { 5, OperandInfo339 },  // Inst #3822 = VSUBLuv2i64
+  { 5, OperandInfo339 },  // Inst #3823 = VSUBLuv4i32
+  { 5, OperandInfo339 },  // Inst #3824 = VSUBLuv8i16
+  { 5, OperandInfo348 },  // Inst #3825 = VSUBS
+  { 5, OperandInfo349 },  // Inst #3826 = VSUBWsv2i64
+  { 5, OperandInfo349 },  // Inst #3827 = VSUBWsv4i32
+  { 5, OperandInfo349 },  // Inst #3828 = VSUBWsv8i16
+  { 5, OperandInfo349 },  // Inst #3829 = VSUBWuv2i64
+  { 5, OperandInfo349 },  // Inst #3830 = VSUBWuv4i32
+  { 5, OperandInfo349 },  // Inst #3831 = VSUBWuv8i16
+  { 5, OperandInfo340 },  // Inst #3832 = VSUBfd
+  { 5, OperandInfo341 },  // Inst #3833 = VSUBfq
+  { 5, OperandInfo340 },  // Inst #3834 = VSUBhd
+  { 5, OperandInfo341 },  // Inst #3835 = VSUBhq
+  { 5, OperandInfo341 },  // Inst #3836 = VSUBv16i8
+  { 5, OperandInfo340 },  // Inst #3837 = VSUBv1i64
+  { 5, OperandInfo340 },  // Inst #3838 = VSUBv2i32
+  { 5, OperandInfo341 },  // Inst #3839 = VSUBv2i64
+  { 5, OperandInfo340 },  // Inst #3840 = VSUBv4i16
+  { 5, OperandInfo341 },  // Inst #3841 = VSUBv4i32
+  { 5, OperandInfo341 },  // Inst #3842 = VSUBv8i16
+  { 5, OperandInfo340 },  // Inst #3843 = VSUBv8i8
+  { 5, OperandInfo159 },  // Inst #3844 = VSUDOTDI
+  { 5, OperandInfo160 },  // Inst #3845 = VSUDOTQI
+  { 6, OperandInfo499 },  // Inst #3846 = VSWPd
+  { 6, OperandInfo500 },  // Inst #3847 = VSWPq
+  { 5, OperandInfo340 },  // Inst #3848 = VTBL1
+  { 5, OperandInfo501 },  // Inst #3849 = VTBL2
+  { 5, OperandInfo340 },  // Inst #3850 = VTBL3
+  { 5, OperandInfo502 },  // Inst #3851 = VTBL3Pseudo
+  { 5, OperandInfo340 },  // Inst #3852 = VTBL4
+  { 5, OperandInfo502 },  // Inst #3853 = VTBL4Pseudo
+  { 6, OperandInfo338 },  // Inst #3854 = VTBX1
+  { 6, OperandInfo503 },  // Inst #3855 = VTBX2
+  { 6, OperandInfo338 },  // Inst #3856 = VTBX3
+  { 6, OperandInfo504 },  // Inst #3857 = VTBX3Pseudo
+  { 6, OperandInfo338 },  // Inst #3858 = VTBX4
+  { 6, OperandInfo504 },  // Inst #3859 = VTBX4Pseudo
+  { 5, OperandInfo463 },  // Inst #3860 = VTOSHD
+  { 5, OperandInfo464 },  // Inst #3861 = VTOSHH
+  { 5, OperandInfo464 },  // Inst #3862 = VTOSHS
+  { 4, OperandInfo372 },  // Inst #3863 = VTOSIRD
+  { 4, OperandInfo344 },  // Inst #3864 = VTOSIRH
+  { 4, OperandInfo344 },  // Inst #3865 = VTOSIRS
+  { 4, OperandInfo372 },  // Inst #3866 = VTOSIZD
+  { 4, OperandInfo505 },  // Inst #3867 = VTOSIZH
+  { 4, OperandInfo344 },  // Inst #3868 = VTOSIZS
+  { 5, OperandInfo463 },  // Inst #3869 = VTOSLD
+  { 5, OperandInfo464 },  // Inst #3870 = VTOSLH
+  { 5, OperandInfo464 },  // Inst #3871 = VTOSLS
+  { 5, OperandInfo463 },  // Inst #3872 = VTOUHD
+  { 5, OperandInfo464 },  // Inst #3873 = VTOUHH
+  { 5, OperandInfo464 },  // Inst #3874 = VTOUHS
+  { 4, OperandInfo372 },  // Inst #3875 = VTOUIRD
+  { 4, OperandInfo344 },  // Inst #3876 = VTOUIRH
+  { 4, OperandInfo344 },  // Inst #3877 = VTOUIRS
+  { 4, OperandInfo372 },  // Inst #3878 = VTOUIZD
+  { 4, OperandInfo505 },  // Inst #3879 = VTOUIZH
+  { 4, OperandInfo344 },  // Inst #3880 = VTOUIZS
+  { 5, OperandInfo463 },  // Inst #3881 = VTOULD
+  { 5, OperandInfo464 },  // Inst #3882 = VTOULH
+  { 5, OperandInfo464 },  // Inst #3883 = VTOULS
+  { 6, OperandInfo499 },  // Inst #3884 = VTRNd16
+  { 6, OperandInfo499 },  // Inst #3885 = VTRNd32
+  { 6, OperandInfo499 },  // Inst #3886 = VTRNd8
+  { 6, OperandInfo500 },  // Inst #3887 = VTRNq16
+  { 6, OperandInfo500 },  // Inst #3888 = VTRNq32
+  { 6, OperandInfo500 },  // Inst #3889 = VTRNq8
+  { 5, OperandInfo341 },  // Inst #3890 = VTSTv16i8
+  { 5, OperandInfo340 },  // Inst #3891 = VTSTv2i32
+  { 5, OperandInfo340 },  // Inst #3892 = VTSTv4i16
+  { 5, OperandInfo341 },  // Inst #3893 = VTSTv4i32
+  { 5, OperandInfo341 },  // Inst #3894 = VTSTv8i16
+  { 5, OperandInfo340 },  // Inst #3895 = VTSTv8i8
+  { 4, OperandInfo161 },  // Inst #3896 = VUDOTD
+  { 5, OperandInfo159 },  // Inst #3897 = VUDOTDI
+  { 4, OperandInfo162 },  // Inst #3898 = VUDOTQ
+  { 5, OperandInfo160 },  // Inst #3899 = VUDOTQI
+  { 5, OperandInfo463 },  // Inst #3900 = VUHTOD
+  { 5, OperandInfo464 },  // Inst #3901 = VUHTOH
+  { 5, OperandInfo464 },  // Inst #3902 = VUHTOS
+  { 4, OperandInfo371 },  // Inst #3903 = VUITOD
+  { 4, OperandInfo465 },  // Inst #3904 = VUITOH
+  { 4, OperandInfo344 },  // Inst #3905 = VUITOS
+  { 5, OperandInfo463 },  // Inst #3906 = VULTOD
+  { 5, OperandInfo464 },  // Inst #3907 = VULTOH
+  { 5, OperandInfo464 },  // Inst #3908 = VULTOS
+  { 4, OperandInfo162 },  // Inst #3909 = VUMMLA
+  { 4, OperandInfo161 },  // Inst #3910 = VUSDOTD
+  { 5, OperandInfo159 },  // Inst #3911 = VUSDOTDI
+  { 4, OperandInfo162 },  // Inst #3912 = VUSDOTQ
+  { 5, OperandInfo160 },  // Inst #3913 = VUSDOTQI
+  { 4, OperandInfo162 },  // Inst #3914 = VUSMMLA
+  { 6, OperandInfo499 },  // Inst #3915 = VUZPd16
+  { 6, OperandInfo499 },  // Inst #3916 = VUZPd8
+  { 6, OperandInfo500 },  // Inst #3917 = VUZPq16
+  { 6, OperandInfo500 },  // Inst #3918 = VUZPq32
+  { 6, OperandInfo500 },  // Inst #3919 = VUZPq8
+  { 6, OperandInfo499 },  // Inst #3920 = VZIPd16
+  { 6, OperandInfo499 },  // Inst #3921 = VZIPd8
+  { 6, OperandInfo500 },  // Inst #3922 = VZIPq16
+  { 6, OperandInfo500 },  // Inst #3923 = VZIPq32
+  { 6, OperandInfo500 },  // Inst #3924 = VZIPq8
+  { 4, OperandInfo206 },  // Inst #3925 = sysLDMDA
+  { 5, OperandInfo66 },  // Inst #3926 = sysLDMDA_UPD
+  { 4, OperandInfo206 },  // Inst #3927 = sysLDMDB
+  { 5, OperandInfo66 },  // Inst #3928 = sysLDMDB_UPD
+  { 4, OperandInfo206 },  // Inst #3929 = sysLDMIA
+  { 5, OperandInfo66 },  // Inst #3930 = sysLDMIA_UPD
+  { 4, OperandInfo206 },  // Inst #3931 = sysLDMIB
+  { 5, OperandInfo66 },  // Inst #3932 = sysLDMIB_UPD
+  { 4, OperandInfo206 },  // Inst #3933 = sysSTMDA
+  { 5, OperandInfo66 },  // Inst #3934 = sysSTMDA_UPD
+  { 4, OperandInfo206 },  // Inst #3935 = sysSTMDB
+  { 5, OperandInfo66 },  // Inst #3936 = sysSTMDB_UPD
+  { 4, OperandInfo206 },  // Inst #3937 = sysSTMIA
+  { 5, OperandInfo66 },  // Inst #3938 = sysSTMIA_UPD
+  { 4, OperandInfo206 },  // Inst #3939 = sysSTMIB
+  { 5, OperandInfo66 },  // Inst #3940 = sysSTMIB_UPD
+  { 6, OperandInfo506 },  // Inst #3941 = t2ADCri
+  { 6, OperandInfo507 },  // Inst #3942 = t2ADCrr
+  { 7, OperandInfo508 },  // Inst #3943 = t2ADCrs
+  { 6, OperandInfo509 },  // Inst #3944 = t2ADDri
+  { 5, OperandInfo510 },  // Inst #3945 = t2ADDri12
+  { 6, OperandInfo511 },  // Inst #3946 = t2ADDrr
+  { 7, OperandInfo512 },  // Inst #3947 = t2ADDrs
+  { 6, OperandInfo513 },  // Inst #3948 = t2ADDspImm
+  { 5, OperandInfo514 },  // Inst #3949 = t2ADDspImm12
+  { 4, OperandInfo515 },  // Inst #3950 = t2ADR
+  { 6, OperandInfo506 },  // Inst #3951 = t2ANDri
+  { 6, OperandInfo507 },  // Inst #3952 = t2ANDrr
+  { 7, OperandInfo508 },  // Inst #3953 = t2ANDrs
+  { 6, OperandInfo506 },  // Inst #3954 = t2ASRri
+  { 6, OperandInfo507 },  // Inst #3955 = t2ASRrr
+  { 0, 0 },  // Inst #3956 = t2AUT
+  { 5, OperandInfo516 },  // Inst #3957 = t2AUTG
+  { 3, OperandInfo141 },  // Inst #3958 = t2B
+  { 5, OperandInfo120 },  // Inst #3959 = t2BFC
+  { 6, OperandInfo517 },  // Inst #3960 = t2BFI
+  { 4, OperandInfo518 },  // Inst #3961 = t2BFLi
+  { 4, OperandInfo519 },  // Inst #3962 = t2BFLr
+  { 4, OperandInfo518 },  // Inst #3963 = t2BFi
+  { 4, OperandInfo520 },  // Inst #3964 = t2BFic
+  { 4, OperandInfo519 },  // Inst #3965 = t2BFr
+  { 6, OperandInfo506 },  // Inst #3966 = t2BICri
+  { 6, OperandInfo507 },  // Inst #3967 = t2BICrr
+  { 7, OperandInfo508 },  // Inst #3968 = t2BICrs
+  { 0, 0 },  // Inst #3969 = t2BTI
+  { 5, OperandInfo521 },  // Inst #3970 = t2BXAUT
+  { 3, OperandInfo239 },  // Inst #3971 = t2BXJ
+  { 3, OperandInfo141 },  // Inst #3972 = t2Bcc
+  { 8, OperandInfo195 },  // Inst #3973 = t2CDP
+  { 8, OperandInfo195 },  // Inst #3974 = t2CDP2
+  { 2, OperandInfo139 },  // Inst #3975 = t2CLREX
+  { 3, OperandInfo150 },  // Inst #3976 = t2CLRM
+  { 4, OperandInfo522 },  // Inst #3977 = t2CLZ
+  { 4, OperandInfo113 },  // Inst #3978 = t2CMNri
+  { 4, OperandInfo523 },  // Inst #3979 = t2CMNzrr
+  { 5, OperandInfo524 },  // Inst #3980 = t2CMNzrs
+  { 4, OperandInfo113 },  // Inst #3981 = t2CMPri
+  { 4, OperandInfo523 },  // Inst #3982 = t2CMPrr
+  { 5, OperandInfo524 },  // Inst #3983 = t2CMPrs
+  { 1, OperandInfo2 },  // Inst #3984 = t2CPS1p
+  { 2, OperandInfo7 },  // Inst #3985 = t2CPS2p
+  { 3, OperandInfo4 },  // Inst #3986 = t2CPS3p
+  { 3, OperandInfo85 },  // Inst #3987 = t2CRC32B
+  { 3, OperandInfo85 },  // Inst #3988 = t2CRC32CB
+  { 3, OperandInfo85 },  // Inst #3989 = t2CRC32CH
+  { 3, OperandInfo85 },  // Inst #3990 = t2CRC32CW
+  { 3, OperandInfo85 },  // Inst #3991 = t2CRC32H
+  { 3, OperandInfo85 },  // Inst #3992 = t2CRC32W
+  { 4, OperandInfo525 },  // Inst #3993 = t2CSEL
+  { 4, OperandInfo525 },  // Inst #3994 = t2CSINC
+  { 4, OperandInfo525 },  // Inst #3995 = t2CSINV
+  { 4, OperandInfo525 },  // Inst #3996 = t2CSNEG
+  { 3, OperandInfo202 },  // Inst #3997 = t2DBG
+  { 2, OperandInfo139 },  // Inst #3998 = t2DCPS1
+  { 2, OperandInfo139 },  // Inst #3999 = t2DCPS2
+  { 2, OperandInfo139 },  // Inst #4000 = t2DCPS3
+  { 2, OperandInfo111 },  // Inst #4001 = t2DLS
+  { 3, OperandInfo202 },  // Inst #4002 = t2DMB
+  { 3, OperandInfo202 },  // Inst #4003 = t2DSB
+  { 6, OperandInfo506 },  // Inst #4004 = t2EORri
+  { 6, OperandInfo507 },  // Inst #4005 = t2EORrr
+  { 7, OperandInfo508 },  // Inst #4006 = t2EORrs
+  { 3, OperandInfo202 },  // Inst #4007 = t2HINT
+  { 1, OperandInfo2 },  // Inst #4008 = t2HVC
+  { 3, OperandInfo202 },  // Inst #4009 = t2ISB
+  { 2, OperandInfo7 },  // Inst #4010 = t2IT
+  { 2, OperandInfo151 },  // Inst #4011 = t2Int_eh_sjlj_setjmp
+  { 2, OperandInfo151 },  // Inst #4012 = t2Int_eh_sjlj_setjmp_nofp
+  { 4, OperandInfo526 },  // Inst #4013 = t2LDA
+  { 4, OperandInfo526 },  // Inst #4014 = t2LDAB
+  { 4, OperandInfo526 },  // Inst #4015 = t2LDAEX
+  { 4, OperandInfo526 },  // Inst #4016 = t2LDAEXB
+  { 5, OperandInfo527 },  // Inst #4017 = t2LDAEXD
+  { 4, OperandInfo526 },  // Inst #4018 = t2LDAEXH
+  { 4, OperandInfo526 },  // Inst #4019 = t2LDAH
+  { 6, OperandInfo211 },  // Inst #4020 = t2LDC2L_OFFSET
+  { 6, OperandInfo212 },  // Inst #4021 = t2LDC2L_OPTION
+  { 6, OperandInfo211 },  // Inst #4022 = t2LDC2L_POST
+  { 7, OperandInfo213 },  // Inst #4023 = t2LDC2L_PRE
+  { 6, OperandInfo211 },  // Inst #4024 = t2LDC2_OFFSET
+  { 6, OperandInfo212 },  // Inst #4025 = t2LDC2_OPTION
+  { 6, OperandInfo211 },  // Inst #4026 = t2LDC2_POST
+  { 7, OperandInfo213 },  // Inst #4027 = t2LDC2_PRE
+  { 6, OperandInfo211 },  // Inst #4028 = t2LDCL_OFFSET
+  { 6, OperandInfo212 },  // Inst #4029 = t2LDCL_OPTION
+  { 6, OperandInfo211 },  // Inst #4030 = t2LDCL_POST
+  { 7, OperandInfo213 },  // Inst #4031 = t2LDCL_PRE
+  { 6, OperandInfo211 },  // Inst #4032 = t2LDC_OFFSET
+  { 6, OperandInfo212 },  // Inst #4033 = t2LDC_OPTION
+  { 6, OperandInfo211 },  // Inst #4034 = t2LDC_POST
+  { 7, OperandInfo213 },  // Inst #4035 = t2LDC_PRE
+  { 4, OperandInfo206 },  // Inst #4036 = t2LDMDB
+  { 5, OperandInfo66 },  // Inst #4037 = t2LDMDB_UPD
+  { 4, OperandInfo206 },  // Inst #4038 = t2LDMIA
+  { 5, OperandInfo66 },  // Inst #4039 = t2LDMIA_UPD
+  { 5, OperandInfo528 },  // Inst #4040 = t2LDRBT
+  { 6, OperandInfo215 },  // Inst #4041 = t2LDRB_POST
+  { 6, OperandInfo215 },  // Inst #4042 = t2LDRB_PRE
+  { 5, OperandInfo216 },  // Inst #4043 = t2LDRBi12
+  { 5, OperandInfo216 },  // Inst #4044 = t2LDRBi8
+  { 4, OperandInfo529 },  // Inst #4045 = t2LDRBpci
+  { 6, OperandInfo530 },  // Inst #4046 = t2LDRBs
+  { 7, OperandInfo531 },  // Inst #4047 = t2LDRD_POST
+  { 7, OperandInfo531 },  // Inst #4048 = t2LDRD_PRE
+  { 6, OperandInfo532 },  // Inst #4049 = t2LDRDi8
+  { 5, OperandInfo533 },  // Inst #4050 = t2LDREX
+  { 4, OperandInfo526 },  // Inst #4051 = t2LDREXB
+  { 5, OperandInfo527 },  // Inst #4052 = t2LDREXD
+  { 4, OperandInfo526 },  // Inst #4053 = t2LDREXH
+  { 5, OperandInfo528 },  // Inst #4054 = t2LDRHT
+  { 6, OperandInfo215 },  // Inst #4055 = t2LDRH_POST
+  { 6, OperandInfo215 },  // Inst #4056 = t2LDRH_PRE
+  { 5, OperandInfo216 },  // Inst #4057 = t2LDRHi12
+  { 5, OperandInfo216 },  // Inst #4058 = t2LDRHi8
+  { 4, OperandInfo529 },  // Inst #4059 = t2LDRHpci
+  { 6, OperandInfo530 },  // Inst #4060 = t2LDRHs
+  { 5, OperandInfo528 },  // Inst #4061 = t2LDRSBT
+  { 6, OperandInfo215 },  // Inst #4062 = t2LDRSB_POST
+  { 6, OperandInfo215 },  // Inst #4063 = t2LDRSB_PRE
+  { 5, OperandInfo216 },  // Inst #4064 = t2LDRSBi12
+  { 5, OperandInfo216 },  // Inst #4065 = t2LDRSBi8
+  { 4, OperandInfo529 },  // Inst #4066 = t2LDRSBpci
+  { 6, OperandInfo530 },  // Inst #4067 = t2LDRSBs
+  { 5, OperandInfo528 },  // Inst #4068 = t2LDRSHT
+  { 6, OperandInfo215 },  // Inst #4069 = t2LDRSH_POST
+  { 6, OperandInfo215 },  // Inst #4070 = t2LDRSH_PRE
+  { 5, OperandInfo216 },  // Inst #4071 = t2LDRSHi12
+  { 5, OperandInfo216 },  // Inst #4072 = t2LDRSHi8
+  { 4, OperandInfo529 },  // Inst #4073 = t2LDRSHpci
+  { 6, OperandInfo530 },  // Inst #4074 = t2LDRSHs
+  { 5, OperandInfo528 },  // Inst #4075 = t2LDRT
+  { 6, OperandInfo215 },  // Inst #4076 = t2LDR_POST
+  { 6, OperandInfo215 },  // Inst #4077 = t2LDR_PRE
+  { 5, OperandInfo87 },  // Inst #4078 = t2LDRi12
+  { 5, OperandInfo87 },  // Inst #4079 = t2LDRi8
+  { 4, OperandInfo534 },  // Inst #4080 = t2LDRpci
+  { 6, OperandInfo535 },  // Inst #4081 = t2LDRs
+  { 1, OperandInfo53 },  // Inst #4082 = t2LE
+  { 3, OperandInfo118 },  // Inst #4083 = t2LEUpdate
+  { 6, OperandInfo506 },  // Inst #4084 = t2LSLri
+  { 6, OperandInfo507 },  // Inst #4085 = t2LSLrr
+  { 6, OperandInfo506 },  // Inst #4086 = t2LSRri
+  { 6, OperandInfo507 },  // Inst #4087 = t2LSRrr
+  { 8, OperandInfo224 },  // Inst #4088 = t2MCR
+  { 8, OperandInfo224 },  // Inst #4089 = t2MCR2
+  { 7, OperandInfo536 },  // Inst #4090 = t2MCRR
+  { 7, OperandInfo536 },  // Inst #4091 = t2MCRR2
+  { 6, OperandInfo537 },  // Inst #4092 = t2MLA
+  { 6, OperandInfo537 },  // Inst #4093 = t2MLS
+  { 5, OperandInfo120 },  // Inst #4094 = t2MOVTi16
+  { 5, OperandInfo538 },  // Inst #4095 = t2MOVi
+  { 4, OperandInfo515 },  // Inst #4096 = t2MOVi16
+  { 5, OperandInfo539 },  // Inst #4097 = t2MOVr
+  { 4, OperandInfo522 },  // Inst #4098 = t2MOVsra_flag
+  { 4, OperandInfo522 },  // Inst #4099 = t2MOVsrl_flag
+  { 8, OperandInfo235 },  // Inst #4100 = t2MRC
+  { 8, OperandInfo235 },  // Inst #4101 = t2MRC2
+  { 7, OperandInfo540 },  // Inst #4102 = t2MRRC
+  { 7, OperandInfo540 },  // Inst #4103 = t2MRRC2
+  { 3, OperandInfo137 },  // Inst #4104 = t2MRS_AR
+  { 4, OperandInfo515 },  // Inst #4105 = t2MRS_M
+  { 4, OperandInfo515 },  // Inst #4106 = t2MRSbanked
+  { 3, OperandInfo137 },  // Inst #4107 = t2MRSsys_AR
+  { 4, OperandInfo541 },  // Inst #4108 = t2MSR_AR
+  { 4, OperandInfo541 },  // Inst #4109 = t2MSR_M
+  { 4, OperandInfo541 },  // Inst #4110 = t2MSRbanked
+  { 5, OperandInfo542 },  // Inst #4111 = t2MUL
+  { 5, OperandInfo538 },  // Inst #4112 = t2MVNi
+  { 5, OperandInfo543 },  // Inst #4113 = t2MVNr
+  { 6, OperandInfo544 },  // Inst #4114 = t2MVNs
+  { 6, OperandInfo506 },  // Inst #4115 = t2ORNri
+  { 6, OperandInfo507 },  // Inst #4116 = t2ORNrr
+  { 7, OperandInfo508 },  // Inst #4117 = t2ORNrs
+  { 6, OperandInfo506 },  // Inst #4118 = t2ORRri
+  { 6, OperandInfo507 },  // Inst #4119 = t2ORRrr
+  { 7, OperandInfo508 },  // Inst #4120 = t2ORRrs
+  { 0, 0 },  // Inst #4121 = t2PAC
+  { 0, 0 },  // Inst #4122 = t2PACBTI
+  { 5, OperandInfo545 },  // Inst #4123 = t2PACG
+  { 6, OperandInfo546 },  // Inst #4124 = t2PKHBT
+  { 6, OperandInfo546 },  // Inst #4125 = t2PKHTB
+  { 4, OperandInfo547 },  // Inst #4126 = t2PLDWi12
+  { 4, OperandInfo547 },  // Inst #4127 = t2PLDWi8
+  { 5, OperandInfo548 },  // Inst #4128 = t2PLDWs
+  { 4, OperandInfo547 },  // Inst #4129 = t2PLDi12
+  { 4, OperandInfo547 },  // Inst #4130 = t2PLDi8
+  { 3, OperandInfo549 },  // Inst #4131 = t2PLDpci
+  { 5, OperandInfo548 },  // Inst #4132 = t2PLDs
+  { 4, OperandInfo547 },  // Inst #4133 = t2PLIi12
+  { 4, OperandInfo547 },  // Inst #4134 = t2PLIi8
+  { 3, OperandInfo549 },  // Inst #4135 = t2PLIpci
+  { 5, OperandInfo548 },  // Inst #4136 = t2PLIs
+  { 5, OperandInfo542 },  // Inst #4137 = t2QADD
+  { 5, OperandInfo542 },  // Inst #4138 = t2QADD16
+  { 5, OperandInfo542 },  // Inst #4139 = t2QADD8
+  { 5, OperandInfo542 },  // Inst #4140 = t2QASX
+  { 5, OperandInfo542 },  // Inst #4141 = t2QDADD
+  { 5, OperandInfo542 },  // Inst #4142 = t2QDSUB
+  { 5, OperandInfo542 },  // Inst #4143 = t2QSAX
+  { 5, OperandInfo542 },  // Inst #4144 = t2QSUB
+  { 5, OperandInfo542 },  // Inst #4145 = t2QSUB16
+  { 5, OperandInfo542 },  // Inst #4146 = t2QSUB8
+  { 4, OperandInfo522 },  // Inst #4147 = t2RBIT
+  { 4, OperandInfo522 },  // Inst #4148 = t2REV
+  { 4, OperandInfo522 },  // Inst #4149 = t2REV16
+  { 4, OperandInfo522 },  // Inst #4150 = t2REVSH
+  { 3, OperandInfo137 },  // Inst #4151 = t2RFEDB
+  { 3, OperandInfo137 },  // Inst #4152 = t2RFEDBW
+  { 3, OperandInfo137 },  // Inst #4153 = t2RFEIA
+  { 3, OperandInfo137 },  // Inst #4154 = t2RFEIAW
+  { 6, OperandInfo506 },  // Inst #4155 = t2RORri
+  { 6, OperandInfo507 },  // Inst #4156 = t2RORrr
+  { 5, OperandInfo543 },  // Inst #4157 = t2RRX
+  { 6, OperandInfo506 },  // Inst #4158 = t2RSBri
+  { 6, OperandInfo507 },  // Inst #4159 = t2RSBrr
+  { 7, OperandInfo508 },  // Inst #4160 = t2RSBrs
+  { 5, OperandInfo542 },  // Inst #4161 = t2SADD16
+  { 5, OperandInfo542 },  // Inst #4162 = t2SADD8
+  { 5, OperandInfo542 },  // Inst #4163 = t2SASX
+  { 0, 0 },  // Inst #4164 = t2SB
+  { 6, OperandInfo506 },  // Inst #4165 = t2SBCri
+  { 6, OperandInfo507 },  // Inst #4166 = t2SBCrr
+  { 7, OperandInfo508 },  // Inst #4167 = t2SBCrs
+  { 6, OperandInfo550 },  // Inst #4168 = t2SBFX
+  { 5, OperandInfo542 },  // Inst #4169 = t2SDIV
+  { 5, OperandInfo47 },  // Inst #4170 = t2SEL
+  { 1, OperandInfo2 },  // Inst #4171 = t2SETPAN
+  { 2, OperandInfo139 },  // Inst #4172 = t2SG
+  { 5, OperandInfo542 },  // Inst #4173 = t2SHADD16
+  { 5, OperandInfo542 },  // Inst #4174 = t2SHADD8
+  { 5, OperandInfo542 },  // Inst #4175 = t2SHASX
+  { 5, OperandInfo542 },  // Inst #4176 = t2SHSAX
+  { 5, OperandInfo542 },  // Inst #4177 = t2SHSUB16
+  { 5, OperandInfo542 },  // Inst #4178 = t2SHSUB8
+  { 3, OperandInfo202 },  // Inst #4179 = t2SMC
+  { 6, OperandInfo537 },  // Inst #4180 = t2SMLABB
+  { 6, OperandInfo537 },  // Inst #4181 = t2SMLABT
+  { 6, OperandInfo537 },  // Inst #4182 = t2SMLAD
+  { 6, OperandInfo537 },  // Inst #4183 = t2SMLADX
+  { 8, OperandInfo551 },  // Inst #4184 = t2SMLAL
+  { 8, OperandInfo551 },  // Inst #4185 = t2SMLALBB
+  { 8, OperandInfo551 },  // Inst #4186 = t2SMLALBT
+  { 8, OperandInfo551 },  // Inst #4187 = t2SMLALD
+  { 8, OperandInfo551 },  // Inst #4188 = t2SMLALDX
+  { 8, OperandInfo551 },  // Inst #4189 = t2SMLALTB
+  { 8, OperandInfo551 },  // Inst #4190 = t2SMLALTT
+  { 6, OperandInfo537 },  // Inst #4191 = t2SMLATB
+  { 6, OperandInfo537 },  // Inst #4192 = t2SMLATT
+  { 6, OperandInfo537 },  // Inst #4193 = t2SMLAWB
+  { 6, OperandInfo537 },  // Inst #4194 = t2SMLAWT
+  { 6, OperandInfo537 },  // Inst #4195 = t2SMLSD
+  { 6, OperandInfo537 },  // Inst #4196 = t2SMLSDX
+  { 8, OperandInfo551 },  // Inst #4197 = t2SMLSLD
+  { 8, OperandInfo551 },  // Inst #4198 = t2SMLSLDX
+  { 6, OperandInfo537 },  // Inst #4199 = t2SMMLA
+  { 6, OperandInfo537 },  // Inst #4200 = t2SMMLAR
+  { 6, OperandInfo537 },  // Inst #4201 = t2SMMLS
+  { 6, OperandInfo537 },  // Inst #4202 = t2SMMLSR
+  { 5, OperandInfo542 },  // Inst #4203 = t2SMMUL
+  { 5, OperandInfo542 },  // Inst #4204 = t2SMMULR
+  { 5, OperandInfo542 },  // Inst #4205 = t2SMUAD
+  { 5, OperandInfo542 },  // Inst #4206 = t2SMUADX
+  { 5, OperandInfo542 },  // Inst #4207 = t2SMULBB
+  { 5, OperandInfo542 },  // Inst #4208 = t2SMULBT
+  { 6, OperandInfo537 },  // Inst #4209 = t2SMULL
+  { 5, OperandInfo542 },  // Inst #4210 = t2SMULTB
+  { 5, OperandInfo542 },  // Inst #4211 = t2SMULTT
+  { 5, OperandInfo542 },  // Inst #4212 = t2SMULWB
+  { 5, OperandInfo542 },  // Inst #4213 = t2SMULWT
+  { 5, OperandInfo542 },  // Inst #4214 = t2SMUSD
+  { 5, OperandInfo542 },  // Inst #4215 = t2SMUSDX
+  { 3, OperandInfo202 },  // Inst #4216 = t2SRSDB
+  { 3, OperandInfo202 },  // Inst #4217 = t2SRSDB_UPD
+  { 3, OperandInfo202 },  // Inst #4218 = t2SRSIA
+  { 3, OperandInfo202 },  // Inst #4219 = t2SRSIA_UPD
+  { 6, OperandInfo552 },  // Inst #4220 = t2SSAT
+  { 5, OperandInfo553 },  // Inst #4221 = t2SSAT16
+  { 5, OperandInfo542 },  // Inst #4222 = t2SSAX
+  { 5, OperandInfo542 },  // Inst #4223 = t2SSUB16
+  { 5, OperandInfo542 },  // Inst #4224 = t2SSUB8
+  { 6, OperandInfo211 },  // Inst #4225 = t2STC2L_OFFSET
+  { 6, OperandInfo212 },  // Inst #4226 = t2STC2L_OPTION
+  { 6, OperandInfo211 },  // Inst #4227 = t2STC2L_POST
+  { 7, OperandInfo213 },  // Inst #4228 = t2STC2L_PRE
+  { 6, OperandInfo211 },  // Inst #4229 = t2STC2_OFFSET
+  { 6, OperandInfo212 },  // Inst #4230 = t2STC2_OPTION
+  { 6, OperandInfo211 },  // Inst #4231 = t2STC2_POST
+  { 7, OperandInfo213 },  // Inst #4232 = t2STC2_PRE
+  { 6, OperandInfo211 },  // Inst #4233 = t2STCL_OFFSET
+  { 6, OperandInfo212 },  // Inst #4234 = t2STCL_OPTION
+  { 6, OperandInfo211 },  // Inst #4235 = t2STCL_POST
+  { 7, OperandInfo213 },  // Inst #4236 = t2STCL_PRE
+  { 6, OperandInfo211 },  // Inst #4237 = t2STC_OFFSET
+  { 6, OperandInfo212 },  // Inst #4238 = t2STC_OPTION
+  { 6, OperandInfo211 },  // Inst #4239 = t2STC_POST
+  { 7, OperandInfo213 },  // Inst #4240 = t2STC_PRE
+  { 4, OperandInfo526 },  // Inst #4241 = t2STL
+  { 4, OperandInfo526 },  // Inst #4242 = t2STLB
+  { 5, OperandInfo554 },  // Inst #4243 = t2STLEX
+  { 5, OperandInfo554 },  // Inst #4244 = t2STLEXB
+  { 6, OperandInfo555 },  // Inst #4245 = t2STLEXD
+  { 5, OperandInfo554 },  // Inst #4246 = t2STLEXH
+  { 4, OperandInfo526 },  // Inst #4247 = t2STLH
+  { 4, OperandInfo206 },  // Inst #4248 = t2STMDB
+  { 5, OperandInfo66 },  // Inst #4249 = t2STMDB_UPD
+  { 4, OperandInfo206 },  // Inst #4250 = t2STMIA
+  { 5, OperandInfo66 },  // Inst #4251 = t2STMIA_UPD
+  { 5, OperandInfo528 },  // Inst #4252 = t2STRBT
+  { 6, OperandInfo556 },  // Inst #4253 = t2STRB_POST
+  { 6, OperandInfo556 },  // Inst #4254 = t2STRB_PRE
+  { 5, OperandInfo528 },  // Inst #4255 = t2STRBi12
+  { 5, OperandInfo528 },  // Inst #4256 = t2STRBi8
+  { 6, OperandInfo557 },  // Inst #4257 = t2STRBs
+  { 7, OperandInfo558 },  // Inst #4258 = t2STRD_POST
+  { 7, OperandInfo558 },  // Inst #4259 = t2STRD_PRE
+  { 6, OperandInfo532 },  // Inst #4260 = t2STRDi8
+  { 6, OperandInfo559 },  // Inst #4261 = t2STREX
+  { 5, OperandInfo554 },  // Inst #4262 = t2STREXB
+  { 6, OperandInfo555 },  // Inst #4263 = t2STREXD
+  { 5, OperandInfo554 },  // Inst #4264 = t2STREXH
+  { 5, OperandInfo528 },  // Inst #4265 = t2STRHT
+  { 6, OperandInfo556 },  // Inst #4266 = t2STRH_POST
+  { 6, OperandInfo556 },  // Inst #4267 = t2STRH_PRE
+  { 5, OperandInfo528 },  // Inst #4268 = t2STRHi12
+  { 5, OperandInfo528 },  // Inst #4269 = t2STRHi8
+  { 6, OperandInfo557 },  // Inst #4270 = t2STRHs
+  { 5, OperandInfo528 },  // Inst #4271 = t2STRT
+  { 6, OperandInfo560 },  // Inst #4272 = t2STR_POST
+  { 6, OperandInfo560 },  // Inst #4273 = t2STR_PRE
+  { 5, OperandInfo87 },  // Inst #4274 = t2STRi12
+  { 5, OperandInfo87 },  // Inst #4275 = t2STRi8
+  { 6, OperandInfo535 },  // Inst #4276 = t2STRs
+  { 3, OperandInfo202 },  // Inst #4277 = t2SUBS_PC_LR
+  { 6, OperandInfo509 },  // Inst #4278 = t2SUBri
+  { 5, OperandInfo510 },  // Inst #4279 = t2SUBri12
+  { 6, OperandInfo511 },  // Inst #4280 = t2SUBrr
+  { 7, OperandInfo512 },  // Inst #4281 = t2SUBrs
+  { 6, OperandInfo513 },  // Inst #4282 = t2SUBspImm
+  { 5, OperandInfo514 },  // Inst #4283 = t2SUBspImm12
+  { 6, OperandInfo546 },  // Inst #4284 = t2SXTAB
+  { 6, OperandInfo546 },  // Inst #4285 = t2SXTAB16
+  { 6, OperandInfo546 },  // Inst #4286 = t2SXTAH
+  { 5, OperandInfo126 },  // Inst #4287 = t2SXTB
+  { 5, OperandInfo126 },  // Inst #4288 = t2SXTB16
+  { 5, OperandInfo126 },  // Inst #4289 = t2SXTH
+  { 4, OperandInfo561 },  // Inst #4290 = t2TBB
+  { 4, OperandInfo561 },  // Inst #4291 = t2TBH
+  { 4, OperandInfo515 },  // Inst #4292 = t2TEQri
+  { 4, OperandInfo522 },  // Inst #4293 = t2TEQrr
+  { 5, OperandInfo123 },  // Inst #4294 = t2TEQrs
+  { 3, OperandInfo202 },  // Inst #4295 = t2TSB
+  { 4, OperandInfo515 },  // Inst #4296 = t2TSTri
+  { 4, OperandInfo522 },  // Inst #4297 = t2TSTrr
+  { 5, OperandInfo123 },  // Inst #4298 = t2TSTrs
+  { 4, OperandInfo562 },  // Inst #4299 = t2TT
+  { 4, OperandInfo562 },  // Inst #4300 = t2TTA
+  { 4, OperandInfo562 },  // Inst #4301 = t2TTAT
+  { 4, OperandInfo562 },  // Inst #4302 = t2TTT
+  { 5, OperandInfo542 },  // Inst #4303 = t2UADD16
+  { 5, OperandInfo542 },  // Inst #4304 = t2UADD8
+  { 5, OperandInfo542 },  // Inst #4305 = t2UASX
+  { 6, OperandInfo550 },  // Inst #4306 = t2UBFX
+  { 1, OperandInfo2 },  // Inst #4307 = t2UDF
+  { 5, OperandInfo542 },  // Inst #4308 = t2UDIV
+  { 5, OperandInfo542 },  // Inst #4309 = t2UHADD16
+  { 5, OperandInfo542 },  // Inst #4310 = t2UHADD8
+  { 5, OperandInfo542 },  // Inst #4311 = t2UHASX
+  { 5, OperandInfo542 },  // Inst #4312 = t2UHSAX
+  { 5, OperandInfo542 },  // Inst #4313 = t2UHSUB16
+  { 5, OperandInfo542 },  // Inst #4314 = t2UHSUB8
+  { 8, OperandInfo551 },  // Inst #4315 = t2UMAAL
+  { 8, OperandInfo551 },  // Inst #4316 = t2UMLAL
+  { 6, OperandInfo537 },  // Inst #4317 = t2UMULL
+  { 5, OperandInfo542 },  // Inst #4318 = t2UQADD16
+  { 5, OperandInfo542 },  // Inst #4319 = t2UQADD8
+  { 5, OperandInfo542 },  // Inst #4320 = t2UQASX
+  { 5, OperandInfo542 },  // Inst #4321 = t2UQSAX
+  { 5, OperandInfo542 },  // Inst #4322 = t2UQSUB16
+  { 5, OperandInfo542 },  // Inst #4323 = t2UQSUB8
+  { 5, OperandInfo542 },  // Inst #4324 = t2USAD8
+  { 6, OperandInfo537 },  // Inst #4325 = t2USADA8
+  { 6, OperandInfo552 },  // Inst #4326 = t2USAT
+  { 5, OperandInfo553 },  // Inst #4327 = t2USAT16
+  { 5, OperandInfo542 },  // Inst #4328 = t2USAX
+  { 5, OperandInfo542 },  // Inst #4329 = t2USUB16
+  { 5, OperandInfo542 },  // Inst #4330 = t2USUB8
+  { 6, OperandInfo546 },  // Inst #4331 = t2UXTAB
+  { 6, OperandInfo546 },  // Inst #4332 = t2UXTAB16
+  { 6, OperandInfo546 },  // Inst #4333 = t2UXTAH
+  { 5, OperandInfo126 },  // Inst #4334 = t2UXTB
+  { 5, OperandInfo126 },  // Inst #4335 = t2UXTB16
+  { 5, OperandInfo126 },  // Inst #4336 = t2UXTH
+  { 3, OperandInfo129 },  // Inst #4337 = t2WLS
+  { 6, OperandInfo563 },  // Inst #4338 = tADC
+  { 5, OperandInfo75 },  // Inst #4339 = tADDhirr
+  { 6, OperandInfo564 },  // Inst #4340 = tADDi3
+  { 6, OperandInfo565 },  // Inst #4341 = tADDi8
+  { 5, OperandInfo566 },  // Inst #4342 = tADDrSP
+  { 5, OperandInfo567 },  // Inst #4343 = tADDrSPi
+  { 6, OperandInfo568 },  // Inst #4344 = tADDrr
+  { 5, OperandInfo569 },  // Inst #4345 = tADDspi
+  { 5, OperandInfo570 },  // Inst #4346 = tADDspr
+  { 4, OperandInfo571 },  // Inst #4347 = tADR
+  { 6, OperandInfo563 },  // Inst #4348 = tAND
+  { 6, OperandInfo564 },  // Inst #4349 = tASRri
+  { 6, OperandInfo563 },  // Inst #4350 = tASRrr
+  { 3, OperandInfo141 },  // Inst #4351 = tB
+  { 6, OperandInfo563 },  // Inst #4352 = tBIC
+  { 1, OperandInfo2 },  // Inst #4353 = tBKPT
+  { 3, OperandInfo110 },  // Inst #4354 = tBL
+  { 3, OperandInfo572 },  // Inst #4355 = tBLXNSr
+  { 3, OperandInfo110 },  // Inst #4356 = tBLXi
+  { 3, OperandInfo573 },  // Inst #4357 = tBLXr
+  { 3, OperandInfo137 },  // Inst #4358 = tBX
+  { 3, OperandInfo137 },  // Inst #4359 = tBXNS
+  { 3, OperandInfo141 },  // Inst #4360 = tBcc
+  { 2, OperandInfo574 },  // Inst #4361 = tCBNZ
+  { 2, OperandInfo574 },  // Inst #4362 = tCBZ
+  { 4, OperandInfo575 },  // Inst #4363 = tCMNz
+  { 4, OperandInfo197 },  // Inst #4364 = tCMPhir
+  { 4, OperandInfo145 },  // Inst #4365 = tCMPi8
+  { 4, OperandInfo575 },  // Inst #4366 = tCMPr
+  { 2, OperandInfo7 },  // Inst #4367 = tCPS
+  { 6, OperandInfo563 },  // Inst #4368 = tEOR
+  { 3, OperandInfo202 },  // Inst #4369 = tHINT
+  { 1, OperandInfo2 },  // Inst #4370 = tHLT
+  { 2, OperandInfo45 },  // Inst #4371 = tInt_WIN_eh_sjlj_longjmp
+  { 2, OperandInfo151 },  // Inst #4372 = tInt_eh_sjlj_longjmp
+  { 2, OperandInfo151 },  // Inst #4373 = tInt_eh_sjlj_setjmp
+  { 4, OperandInfo576 },  // Inst #4374 = tLDMIA
+  { 5, OperandInfo577 },  // Inst #4375 = tLDRBi
+  { 5, OperandInfo578 },  // Inst #4376 = tLDRBr
+  { 5, OperandInfo577 },  // Inst #4377 = tLDRHi
+  { 5, OperandInfo578 },  // Inst #4378 = tLDRHr
+  { 5, OperandInfo578 },  // Inst #4379 = tLDRSB
+  { 5, OperandInfo578 },  // Inst #4380 = tLDRSH
+  { 5, OperandInfo577 },  // Inst #4381 = tLDRi
+  { 4, OperandInfo579 },  // Inst #4382 = tLDRpci
+  { 5, OperandInfo578 },  // Inst #4383 = tLDRr
+  { 5, OperandInfo580 },  // Inst #4384 = tLDRspi
+  { 6, OperandInfo564 },  // Inst #4385 = tLSLri
+  { 6, OperandInfo563 },  // Inst #4386 = tLSLrr
+  { 6, OperandInfo564 },  // Inst #4387 = tLSRri
+  { 6, OperandInfo563 },  // Inst #4388 = tLSRrr
+  { 2, OperandInfo151 },  // Inst #4389 = tMOVSr
+  { 5, OperandInfo581 },  // Inst #4390 = tMOVi8
+  { 4, OperandInfo197 },  // Inst #4391 = tMOVr
+  { 6, OperandInfo582 },  // Inst #4392 = tMUL
+  { 5, OperandInfo583 },  // Inst #4393 = tMVN
+  { 6, OperandInfo563 },  // Inst #4394 = tORR
+  { 3, OperandInfo584 },  // Inst #4395 = tPICADD
+  { 3, OperandInfo150 },  // Inst #4396 = tPOP
+  { 3, OperandInfo150 },  // Inst #4397 = tPUSH
+  { 4, OperandInfo575 },  // Inst #4398 = tREV
+  { 4, OperandInfo575 },  // Inst #4399 = tREV16
+  { 4, OperandInfo575 },  // Inst #4400 = tREVSH
+  { 6, OperandInfo563 },  // Inst #4401 = tROR
+  { 5, OperandInfo583 },  // Inst #4402 = tRSB
+  { 6, OperandInfo563 },  // Inst #4403 = tSBC
+  { 1, OperandInfo2 },  // Inst #4404 = tSETEND
+  { 5, OperandInfo144 },  // Inst #4405 = tSTMIA_UPD
+  { 5, OperandInfo577 },  // Inst #4406 = tSTRBi
+  { 5, OperandInfo578 },  // Inst #4407 = tSTRBr
+  { 5, OperandInfo577 },  // Inst #4408 = tSTRHi
+  { 5, OperandInfo578 },  // Inst #4409 = tSTRHr
+  { 5, OperandInfo577 },  // Inst #4410 = tSTRi
+  { 5, OperandInfo578 },  // Inst #4411 = tSTRr
+  { 5, OperandInfo580 },  // Inst #4412 = tSTRspi
+  { 6, OperandInfo564 },  // Inst #4413 = tSUBi3
+  { 6, OperandInfo565 },  // Inst #4414 = tSUBi8
+  { 6, OperandInfo568 },  // Inst #4415 = tSUBrr
+  { 5, OperandInfo569 },  // Inst #4416 = tSUBspi
+  { 3, OperandInfo202 },  // Inst #4417 = tSVC
+  { 4, OperandInfo575 },  // Inst #4418 = tSXTB
+  { 4, OperandInfo575 },  // Inst #4419 = tSXTH
+  { 0, 0 },  // Inst #4420 = tTRAP
+  { 4, OperandInfo575 },  // Inst #4421 = tTST
+  { 1, OperandInfo2 },  // Inst #4422 = tUDF
+  { 4, OperandInfo575 },  // Inst #4423 = tUXTB
+  { 4, OperandInfo575 },  // Inst #4424 = tUXTH
+  { 0, 0 },  // Inst #4425 = t__brkdiv0
 };
 
 #endif // GET_INSTRINFO_MC_DESC
+
+
diff --git a/arch/ARM/ARMGenRegisterInfo.inc b/arch/ARM/ARMGenRegisterInfo.inc
index 5463e06d3..d0fbeadd1 100644
--- a/arch/ARM/ARMGenRegisterInfo.inc
+++ b/arch/ARM/ARMGenRegisterInfo.inc
@@ -1,14 +1,15 @@
-
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
-|*                                                                            *|
-|* Target Register Enum Values                                                *|
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
 
 #ifdef GET_REGINFO_ENUM
 #undef GET_REGINFO_ENUM
@@ -18,402 +19,453 @@ enum {
   ARM_APSR = 1,
   ARM_APSR_NZCV = 2,
   ARM_CPSR = 3,
-  ARM_FPEXC = 4,
-  ARM_FPINST = 5,
-  ARM_FPSCR = 6,
-  ARM_FPSCR_NZCV = 7,
-  ARM_FPSID = 8,
-  ARM_ITSTATE = 9,
-  ARM_LR = 10,
-  ARM_PC = 11,
-  ARM_SP = 12,
-  ARM_SPSR = 13,
-  ARM_D0 = 14,
-  ARM_D1 = 15,
-  ARM_D2 = 16,
-  ARM_D3 = 17,
-  ARM_D4 = 18,
-  ARM_D5 = 19,
-  ARM_D6 = 20,
-  ARM_D7 = 21,
-  ARM_D8 = 22,
-  ARM_D9 = 23,
-  ARM_D10 = 24,
-  ARM_D11 = 25,
-  ARM_D12 = 26,
-  ARM_D13 = 27,
-  ARM_D14 = 28,
-  ARM_D15 = 29,
-  ARM_D16 = 30,
-  ARM_D17 = 31,
-  ARM_D18 = 32,
-  ARM_D19 = 33,
-  ARM_D20 = 34,
-  ARM_D21 = 35,
-  ARM_D22 = 36,
-  ARM_D23 = 37,
-  ARM_D24 = 38,
-  ARM_D25 = 39,
-  ARM_D26 = 40,
-  ARM_D27 = 41,
-  ARM_D28 = 42,
-  ARM_D29 = 43,
-  ARM_D30 = 44,
-  ARM_D31 = 45,
-  ARM_FPINST2 = 46,
-  ARM_MVFR0 = 47,
-  ARM_MVFR1 = 48,
-  ARM_MVFR2 = 49,
-  ARM_Q0 = 50,
-  ARM_Q1 = 51,
-  ARM_Q2 = 52,
-  ARM_Q3 = 53,
-  ARM_Q4 = 54,
-  ARM_Q5 = 55,
-  ARM_Q6 = 56,
-  ARM_Q7 = 57,
-  ARM_Q8 = 58,
-  ARM_Q9 = 59,
-  ARM_Q10 = 60,
-  ARM_Q11 = 61,
-  ARM_Q12 = 62,
-  ARM_Q13 = 63,
-  ARM_Q14 = 64,
-  ARM_Q15 = 65,
-  ARM_R0 = 66,
-  ARM_R1 = 67,
-  ARM_R2 = 68,
-  ARM_R3 = 69,
-  ARM_R4 = 70,
-  ARM_R5 = 71,
-  ARM_R6 = 72,
-  ARM_R7 = 73,
-  ARM_R8 = 74,
-  ARM_R9 = 75,
-  ARM_R10 = 76,
-  ARM_R11 = 77,
-  ARM_R12 = 78,
-  ARM_S0 = 79,
-  ARM_S1 = 80,
-  ARM_S2 = 81,
-  ARM_S3 = 82,
-  ARM_S4 = 83,
-  ARM_S5 = 84,
-  ARM_S6 = 85,
-  ARM_S7 = 86,
-  ARM_S8 = 87,
-  ARM_S9 = 88,
-  ARM_S10 = 89,
-  ARM_S11 = 90,
-  ARM_S12 = 91,
-  ARM_S13 = 92,
-  ARM_S14 = 93,
-  ARM_S15 = 94,
-  ARM_S16 = 95,
-  ARM_S17 = 96,
-  ARM_S18 = 97,
-  ARM_S19 = 98,
-  ARM_S20 = 99,
-  ARM_S21 = 100,
-  ARM_S22 = 101,
-  ARM_S23 = 102,
-  ARM_S24 = 103,
-  ARM_S25 = 104,
-  ARM_S26 = 105,
-  ARM_S27 = 106,
-  ARM_S28 = 107,
-  ARM_S29 = 108,
-  ARM_S30 = 109,
-  ARM_S31 = 110,
-  ARM_D0_D2 = 111,
-  ARM_D1_D3 = 112,
-  ARM_D2_D4 = 113,
-  ARM_D3_D5 = 114,
-  ARM_D4_D6 = 115,
-  ARM_D5_D7 = 116,
-  ARM_D6_D8 = 117,
-  ARM_D7_D9 = 118,
-  ARM_D8_D10 = 119,
-  ARM_D9_D11 = 120,
-  ARM_D10_D12 = 121,
-  ARM_D11_D13 = 122,
-  ARM_D12_D14 = 123,
-  ARM_D13_D15 = 124,
-  ARM_D14_D16 = 125,
-  ARM_D15_D17 = 126,
-  ARM_D16_D18 = 127,
-  ARM_D17_D19 = 128,
-  ARM_D18_D20 = 129,
-  ARM_D19_D21 = 130,
-  ARM_D20_D22 = 131,
-  ARM_D21_D23 = 132,
-  ARM_D22_D24 = 133,
-  ARM_D23_D25 = 134,
-  ARM_D24_D26 = 135,
-  ARM_D25_D27 = 136,
-  ARM_D26_D28 = 137,
-  ARM_D27_D29 = 138,
-  ARM_D28_D30 = 139,
-  ARM_D29_D31 = 140,
-  ARM_Q0_Q1 = 141,
-  ARM_Q1_Q2 = 142,
-  ARM_Q2_Q3 = 143,
-  ARM_Q3_Q4 = 144,
-  ARM_Q4_Q5 = 145,
-  ARM_Q5_Q6 = 146,
-  ARM_Q6_Q7 = 147,
-  ARM_Q7_Q8 = 148,
-  ARM_Q8_Q9 = 149,
-  ARM_Q9_Q10 = 150,
-  ARM_Q10_Q11 = 151,
-  ARM_Q11_Q12 = 152,
-  ARM_Q12_Q13 = 153,
-  ARM_Q13_Q14 = 154,
-  ARM_Q14_Q15 = 155,
-  ARM_Q0_Q1_Q2_Q3 = 156,
-  ARM_Q1_Q2_Q3_Q4 = 157,
-  ARM_Q2_Q3_Q4_Q5 = 158,
-  ARM_Q3_Q4_Q5_Q6 = 159,
-  ARM_Q4_Q5_Q6_Q7 = 160,
-  ARM_Q5_Q6_Q7_Q8 = 161,
-  ARM_Q6_Q7_Q8_Q9 = 162,
-  ARM_Q7_Q8_Q9_Q10 = 163,
-  ARM_Q8_Q9_Q10_Q11 = 164,
-  ARM_Q9_Q10_Q11_Q12 = 165,
-  ARM_Q10_Q11_Q12_Q13 = 166,
-  ARM_Q11_Q12_Q13_Q14 = 167,
-  ARM_Q12_Q13_Q14_Q15 = 168,
-  ARM_R12_SP = 169,
-  ARM_R0_R1 = 170,
-  ARM_R2_R3 = 171,
-  ARM_R4_R5 = 172,
-  ARM_R6_R7 = 173,
-  ARM_R8_R9 = 174,
-  ARM_R10_R11 = 175,
-  ARM_D0_D1_D2 = 176,
-  ARM_D1_D2_D3 = 177,
-  ARM_D2_D3_D4 = 178,
-  ARM_D3_D4_D5 = 179,
-  ARM_D4_D5_D6 = 180,
-  ARM_D5_D6_D7 = 181,
-  ARM_D6_D7_D8 = 182,
-  ARM_D7_D8_D9 = 183,
-  ARM_D8_D9_D10 = 184,
-  ARM_D9_D10_D11 = 185,
-  ARM_D10_D11_D12 = 186,
-  ARM_D11_D12_D13 = 187,
-  ARM_D12_D13_D14 = 188,
-  ARM_D13_D14_D15 = 189,
-  ARM_D14_D15_D16 = 190,
-  ARM_D15_D16_D17 = 191,
-  ARM_D16_D17_D18 = 192,
-  ARM_D17_D18_D19 = 193,
-  ARM_D18_D19_D20 = 194,
-  ARM_D19_D20_D21 = 195,
-  ARM_D20_D21_D22 = 196,
-  ARM_D21_D22_D23 = 197,
-  ARM_D22_D23_D24 = 198,
-  ARM_D23_D24_D25 = 199,
-  ARM_D24_D25_D26 = 200,
-  ARM_D25_D26_D27 = 201,
-  ARM_D26_D27_D28 = 202,
-  ARM_D27_D28_D29 = 203,
-  ARM_D28_D29_D30 = 204,
-  ARM_D29_D30_D31 = 205,
-  ARM_D0_D2_D4 = 206,
-  ARM_D1_D3_D5 = 207,
-  ARM_D2_D4_D6 = 208,
-  ARM_D3_D5_D7 = 209,
-  ARM_D4_D6_D8 = 210,
-  ARM_D5_D7_D9 = 211,
-  ARM_D6_D8_D10 = 212,
-  ARM_D7_D9_D11 = 213,
-  ARM_D8_D10_D12 = 214,
-  ARM_D9_D11_D13 = 215,
-  ARM_D10_D12_D14 = 216,
-  ARM_D11_D13_D15 = 217,
-  ARM_D12_D14_D16 = 218,
-  ARM_D13_D15_D17 = 219,
-  ARM_D14_D16_D18 = 220,
-  ARM_D15_D17_D19 = 221,
-  ARM_D16_D18_D20 = 222,
-  ARM_D17_D19_D21 = 223,
-  ARM_D18_D20_D22 = 224,
-  ARM_D19_D21_D23 = 225,
-  ARM_D20_D22_D24 = 226,
-  ARM_D21_D23_D25 = 227,
-  ARM_D22_D24_D26 = 228,
-  ARM_D23_D25_D27 = 229,
-  ARM_D24_D26_D28 = 230,
-  ARM_D25_D27_D29 = 231,
-  ARM_D26_D28_D30 = 232,
-  ARM_D27_D29_D31 = 233,
-  ARM_D0_D2_D4_D6 = 234,
-  ARM_D1_D3_D5_D7 = 235,
-  ARM_D2_D4_D6_D8 = 236,
-  ARM_D3_D5_D7_D9 = 237,
-  ARM_D4_D6_D8_D10 = 238,
-  ARM_D5_D7_D9_D11 = 239,
-  ARM_D6_D8_D10_D12 = 240,
-  ARM_D7_D9_D11_D13 = 241,
-  ARM_D8_D10_D12_D14 = 242,
-  ARM_D9_D11_D13_D15 = 243,
-  ARM_D10_D12_D14_D16 = 244,
-  ARM_D11_D13_D15_D17 = 245,
-  ARM_D12_D14_D16_D18 = 246,
-  ARM_D13_D15_D17_D19 = 247,
-  ARM_D14_D16_D18_D20 = 248,
-  ARM_D15_D17_D19_D21 = 249,
-  ARM_D16_D18_D20_D22 = 250,
-  ARM_D17_D19_D21_D23 = 251,
-  ARM_D18_D20_D22_D24 = 252,
-  ARM_D19_D21_D23_D25 = 253,
-  ARM_D20_D22_D24_D26 = 254,
-  ARM_D21_D23_D25_D27 = 255,
-  ARM_D22_D24_D26_D28 = 256,
-  ARM_D23_D25_D27_D29 = 257,
-  ARM_D24_D26_D28_D30 = 258,
-  ARM_D25_D27_D29_D31 = 259,
-  ARM_D1_D2 = 260,
-  ARM_D3_D4 = 261,
-  ARM_D5_D6 = 262,
-  ARM_D7_D8 = 263,
-  ARM_D9_D10 = 264,
-  ARM_D11_D12 = 265,
-  ARM_D13_D14 = 266,
-  ARM_D15_D16 = 267,
-  ARM_D17_D18 = 268,
-  ARM_D19_D20 = 269,
-  ARM_D21_D22 = 270,
-  ARM_D23_D24 = 271,
-  ARM_D25_D26 = 272,
-  ARM_D27_D28 = 273,
-  ARM_D29_D30 = 274,
-  ARM_D1_D2_D3_D4 = 275,
-  ARM_D3_D4_D5_D6 = 276,
-  ARM_D5_D6_D7_D8 = 277,
-  ARM_D7_D8_D9_D10 = 278,
-  ARM_D9_D10_D11_D12 = 279,
-  ARM_D11_D12_D13_D14 = 280,
-  ARM_D13_D14_D15_D16 = 281,
-  ARM_D15_D16_D17_D18 = 282,
-  ARM_D17_D18_D19_D20 = 283,
-  ARM_D19_D20_D21_D22 = 284,
-  ARM_D21_D22_D23_D24 = 285,
-  ARM_D23_D24_D25_D26 = 286,
-  ARM_D25_D26_D27_D28 = 287,
-  ARM_D27_D28_D29_D30 = 288,
-  ARM_NUM_TARGET_REGS 	// 289
+  ARM_FPCXTNS = 4,
+  ARM_FPCXTS = 5,
+  ARM_FPEXC = 6,
+  ARM_FPINST = 7,
+  ARM_FPSCR = 8,
+  ARM_FPSCR_NZCV = 9,
+  ARM_FPSCR_NZCVQC = 10,
+  ARM_FPSID = 11,
+  ARM_ITSTATE = 12,
+  ARM_LR = 13,
+  ARM_PC = 14,
+  ARM_RA_AUTH_CODE = 15,
+  ARM_SP = 16,
+  ARM_SPSR = 17,
+  ARM_VPR = 18,
+  ARM_ZR = 19,
+  ARM_D0 = 20,
+  ARM_D1 = 21,
+  ARM_D2 = 22,
+  ARM_D3 = 23,
+  ARM_D4 = 24,
+  ARM_D5 = 25,
+  ARM_D6 = 26,
+  ARM_D7 = 27,
+  ARM_D8 = 28,
+  ARM_D9 = 29,
+  ARM_D10 = 30,
+  ARM_D11 = 31,
+  ARM_D12 = 32,
+  ARM_D13 = 33,
+  ARM_D14 = 34,
+  ARM_D15 = 35,
+  ARM_D16 = 36,
+  ARM_D17 = 37,
+  ARM_D18 = 38,
+  ARM_D19 = 39,
+  ARM_D20 = 40,
+  ARM_D21 = 41,
+  ARM_D22 = 42,
+  ARM_D23 = 43,
+  ARM_D24 = 44,
+  ARM_D25 = 45,
+  ARM_D26 = 46,
+  ARM_D27 = 47,
+  ARM_D28 = 48,
+  ARM_D29 = 49,
+  ARM_D30 = 50,
+  ARM_D31 = 51,
+  ARM_FPINST2 = 52,
+  ARM_MVFR0 = 53,
+  ARM_MVFR1 = 54,
+  ARM_MVFR2 = 55,
+  ARM_P0 = 56,
+  ARM_Q0 = 57,
+  ARM_Q1 = 58,
+  ARM_Q2 = 59,
+  ARM_Q3 = 60,
+  ARM_Q4 = 61,
+  ARM_Q5 = 62,
+  ARM_Q6 = 63,
+  ARM_Q7 = 64,
+  ARM_Q8 = 65,
+  ARM_Q9 = 66,
+  ARM_Q10 = 67,
+  ARM_Q11 = 68,
+  ARM_Q12 = 69,
+  ARM_Q13 = 70,
+  ARM_Q14 = 71,
+  ARM_Q15 = 72,
+  ARM_R0 = 73,
+  ARM_R1 = 74,
+  ARM_R2 = 75,
+  ARM_R3 = 76,
+  ARM_R4 = 77,
+  ARM_R5 = 78,
+  ARM_R6 = 79,
+  ARM_R7 = 80,
+  ARM_R8 = 81,
+  ARM_R9 = 82,
+  ARM_R10 = 83,
+  ARM_R11 = 84,
+  ARM_R12 = 85,
+  ARM_S0 = 86,
+  ARM_S1 = 87,
+  ARM_S2 = 88,
+  ARM_S3 = 89,
+  ARM_S4 = 90,
+  ARM_S5 = 91,
+  ARM_S6 = 92,
+  ARM_S7 = 93,
+  ARM_S8 = 94,
+  ARM_S9 = 95,
+  ARM_S10 = 96,
+  ARM_S11 = 97,
+  ARM_S12 = 98,
+  ARM_S13 = 99,
+  ARM_S14 = 100,
+  ARM_S15 = 101,
+  ARM_S16 = 102,
+  ARM_S17 = 103,
+  ARM_S18 = 104,
+  ARM_S19 = 105,
+  ARM_S20 = 106,
+  ARM_S21 = 107,
+  ARM_S22 = 108,
+  ARM_S23 = 109,
+  ARM_S24 = 110,
+  ARM_S25 = 111,
+  ARM_S26 = 112,
+  ARM_S27 = 113,
+  ARM_S28 = 114,
+  ARM_S29 = 115,
+  ARM_S30 = 116,
+  ARM_S31 = 117,
+  ARM_D0_D2 = 118,
+  ARM_D1_D3 = 119,
+  ARM_D2_D4 = 120,
+  ARM_D3_D5 = 121,
+  ARM_D4_D6 = 122,
+  ARM_D5_D7 = 123,
+  ARM_D6_D8 = 124,
+  ARM_D7_D9 = 125,
+  ARM_D8_D10 = 126,
+  ARM_D9_D11 = 127,
+  ARM_D10_D12 = 128,
+  ARM_D11_D13 = 129,
+  ARM_D12_D14 = 130,
+  ARM_D13_D15 = 131,
+  ARM_D14_D16 = 132,
+  ARM_D15_D17 = 133,
+  ARM_D16_D18 = 134,
+  ARM_D17_D19 = 135,
+  ARM_D18_D20 = 136,
+  ARM_D19_D21 = 137,
+  ARM_D20_D22 = 138,
+  ARM_D21_D23 = 139,
+  ARM_D22_D24 = 140,
+  ARM_D23_D25 = 141,
+  ARM_D24_D26 = 142,
+  ARM_D25_D27 = 143,
+  ARM_D26_D28 = 144,
+  ARM_D27_D29 = 145,
+  ARM_D28_D30 = 146,
+  ARM_D29_D31 = 147,
+  ARM_Q0_Q1 = 148,
+  ARM_Q1_Q2 = 149,
+  ARM_Q2_Q3 = 150,
+  ARM_Q3_Q4 = 151,
+  ARM_Q4_Q5 = 152,
+  ARM_Q5_Q6 = 153,
+  ARM_Q6_Q7 = 154,
+  ARM_Q7_Q8 = 155,
+  ARM_Q8_Q9 = 156,
+  ARM_Q9_Q10 = 157,
+  ARM_Q10_Q11 = 158,
+  ARM_Q11_Q12 = 159,
+  ARM_Q12_Q13 = 160,
+  ARM_Q13_Q14 = 161,
+  ARM_Q14_Q15 = 162,
+  ARM_Q0_Q1_Q2_Q3 = 163,
+  ARM_Q1_Q2_Q3_Q4 = 164,
+  ARM_Q2_Q3_Q4_Q5 = 165,
+  ARM_Q3_Q4_Q5_Q6 = 166,
+  ARM_Q4_Q5_Q6_Q7 = 167,
+  ARM_Q5_Q6_Q7_Q8 = 168,
+  ARM_Q6_Q7_Q8_Q9 = 169,
+  ARM_Q7_Q8_Q9_Q10 = 170,
+  ARM_Q8_Q9_Q10_Q11 = 171,
+  ARM_Q9_Q10_Q11_Q12 = 172,
+  ARM_Q10_Q11_Q12_Q13 = 173,
+  ARM_Q11_Q12_Q13_Q14 = 174,
+  ARM_Q12_Q13_Q14_Q15 = 175,
+  ARM_R0_R1 = 176,
+  ARM_R2_R3 = 177,
+  ARM_R4_R5 = 178,
+  ARM_R6_R7 = 179,
+  ARM_R8_R9 = 180,
+  ARM_R10_R11 = 181,
+  ARM_R12_SP = 182,
+  ARM_D0_D1_D2 = 183,
+  ARM_D1_D2_D3 = 184,
+  ARM_D2_D3_D4 = 185,
+  ARM_D3_D4_D5 = 186,
+  ARM_D4_D5_D6 = 187,
+  ARM_D5_D6_D7 = 188,
+  ARM_D6_D7_D8 = 189,
+  ARM_D7_D8_D9 = 190,
+  ARM_D8_D9_D10 = 191,
+  ARM_D9_D10_D11 = 192,
+  ARM_D10_D11_D12 = 193,
+  ARM_D11_D12_D13 = 194,
+  ARM_D12_D13_D14 = 195,
+  ARM_D13_D14_D15 = 196,
+  ARM_D14_D15_D16 = 197,
+  ARM_D15_D16_D17 = 198,
+  ARM_D16_D17_D18 = 199,
+  ARM_D17_D18_D19 = 200,
+  ARM_D18_D19_D20 = 201,
+  ARM_D19_D20_D21 = 202,
+  ARM_D20_D21_D22 = 203,
+  ARM_D21_D22_D23 = 204,
+  ARM_D22_D23_D24 = 205,
+  ARM_D23_D24_D25 = 206,
+  ARM_D24_D25_D26 = 207,
+  ARM_D25_D26_D27 = 208,
+  ARM_D26_D27_D28 = 209,
+  ARM_D27_D28_D29 = 210,
+  ARM_D28_D29_D30 = 211,
+  ARM_D29_D30_D31 = 212,
+  ARM_D0_D2_D4 = 213,
+  ARM_D1_D3_D5 = 214,
+  ARM_D2_D4_D6 = 215,
+  ARM_D3_D5_D7 = 216,
+  ARM_D4_D6_D8 = 217,
+  ARM_D5_D7_D9 = 218,
+  ARM_D6_D8_D10 = 219,
+  ARM_D7_D9_D11 = 220,
+  ARM_D8_D10_D12 = 221,
+  ARM_D9_D11_D13 = 222,
+  ARM_D10_D12_D14 = 223,
+  ARM_D11_D13_D15 = 224,
+  ARM_D12_D14_D16 = 225,
+  ARM_D13_D15_D17 = 226,
+  ARM_D14_D16_D18 = 227,
+  ARM_D15_D17_D19 = 228,
+  ARM_D16_D18_D20 = 229,
+  ARM_D17_D19_D21 = 230,
+  ARM_D18_D20_D22 = 231,
+  ARM_D19_D21_D23 = 232,
+  ARM_D20_D22_D24 = 233,
+  ARM_D21_D23_D25 = 234,
+  ARM_D22_D24_D26 = 235,
+  ARM_D23_D25_D27 = 236,
+  ARM_D24_D26_D28 = 237,
+  ARM_D25_D27_D29 = 238,
+  ARM_D26_D28_D30 = 239,
+  ARM_D27_D29_D31 = 240,
+  ARM_D0_D2_D4_D6 = 241,
+  ARM_D1_D3_D5_D7 = 242,
+  ARM_D2_D4_D6_D8 = 243,
+  ARM_D3_D5_D7_D9 = 244,
+  ARM_D4_D6_D8_D10 = 245,
+  ARM_D5_D7_D9_D11 = 246,
+  ARM_D6_D8_D10_D12 = 247,
+  ARM_D7_D9_D11_D13 = 248,
+  ARM_D8_D10_D12_D14 = 249,
+  ARM_D9_D11_D13_D15 = 250,
+  ARM_D10_D12_D14_D16 = 251,
+  ARM_D11_D13_D15_D17 = 252,
+  ARM_D12_D14_D16_D18 = 253,
+  ARM_D13_D15_D17_D19 = 254,
+  ARM_D14_D16_D18_D20 = 255,
+  ARM_D15_D17_D19_D21 = 256,
+  ARM_D16_D18_D20_D22 = 257,
+  ARM_D17_D19_D21_D23 = 258,
+  ARM_D18_D20_D22_D24 = 259,
+  ARM_D19_D21_D23_D25 = 260,
+  ARM_D20_D22_D24_D26 = 261,
+  ARM_D21_D23_D25_D27 = 262,
+  ARM_D22_D24_D26_D28 = 263,
+  ARM_D23_D25_D27_D29 = 264,
+  ARM_D24_D26_D28_D30 = 265,
+  ARM_D25_D27_D29_D31 = 266,
+  ARM_D1_D2 = 267,
+  ARM_D3_D4 = 268,
+  ARM_D5_D6 = 269,
+  ARM_D7_D8 = 270,
+  ARM_D9_D10 = 271,
+  ARM_D11_D12 = 272,
+  ARM_D13_D14 = 273,
+  ARM_D15_D16 = 274,
+  ARM_D17_D18 = 275,
+  ARM_D19_D20 = 276,
+  ARM_D21_D22 = 277,
+  ARM_D23_D24 = 278,
+  ARM_D25_D26 = 279,
+  ARM_D27_D28 = 280,
+  ARM_D29_D30 = 281,
+  ARM_D1_D2_D3_D4 = 282,
+  ARM_D3_D4_D5_D6 = 283,
+  ARM_D5_D6_D7_D8 = 284,
+  ARM_D7_D8_D9_D10 = 285,
+  ARM_D9_D10_D11_D12 = 286,
+  ARM_D11_D12_D13_D14 = 287,
+  ARM_D13_D14_D15_D16 = 288,
+  ARM_D15_D16_D17_D18 = 289,
+  ARM_D17_D18_D19_D20 = 290,
+  ARM_D19_D20_D21_D22 = 291,
+  ARM_D21_D22_D23_D24 = 292,
+  ARM_D23_D24_D25_D26 = 293,
+  ARM_D25_D26_D27_D28 = 294,
+  ARM_D27_D28_D29_D30 = 295,
+  NUM_TARGET_REGS // 296
 };
 
 // Register classes
+
 enum {
   ARM_HPRRegClassID = 0,
-  ARM_SPRRegClassID = 1,
-  ARM_GPRRegClassID = 2,
-  ARM_GPRwithAPSRRegClassID = 3,
-  ARM_SPR_8RegClassID = 4,
-  ARM_GPRnopcRegClassID = 5,
-  ARM_rGPRRegClassID = 6,
-  ARM_tGPRwithpcRegClassID = 7,
-  ARM_hGPRRegClassID = 8,
-  ARM_tGPRRegClassID = 9,
-  ARM_GPRnopc_and_hGPRRegClassID = 10,
-  ARM_hGPR_and_rGPRRegClassID = 11,
-  ARM_tcGPRRegClassID = 12,
-  ARM_tGPR_and_tcGPRRegClassID = 13,
-  ARM_CCRRegClassID = 14,
-  ARM_GPRspRegClassID = 15,
-  ARM_hGPR_and_tGPRwithpcRegClassID = 16,
-  ARM_hGPR_and_tcGPRRegClassID = 17,
-  ARM_DPRRegClassID = 18,
-  ARM_DPR_VFP2RegClassID = 19,
-  ARM_DPR_8RegClassID = 20,
-  ARM_GPRPairRegClassID = 21,
-  ARM_GPRPair_with_gsub_1_in_rGPRRegClassID = 22,
-  ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 23,
-  ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 24,
-  ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 25,
-  ARM_GPRPair_with_gsub_1_in_hGPR_and_rGPRRegClassID = 26,
-  ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 27,
-  ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 28,
-  ARM_DPairSpcRegClassID = 29,
-  ARM_DPairSpc_with_ssub_0RegClassID = 30,
-  ARM_DPairSpc_with_ssub_4RegClassID = 31,
-  ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 32,
-  ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 33,
-  ARM_DPairRegClassID = 34,
-  ARM_DPair_with_ssub_0RegClassID = 35,
-  ARM_QPRRegClassID = 36,
-  ARM_DPair_with_ssub_2RegClassID = 37,
-  ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 38,
-  ARM_QPR_VFP2RegClassID = 39,
-  ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 40,
-  ARM_QPR_8RegClassID = 41,
-  ARM_DTripleRegClassID = 42,
-  ARM_DTripleSpcRegClassID = 43,
-  ARM_DTripleSpc_with_ssub_0RegClassID = 44,
-  ARM_DTriple_with_ssub_0RegClassID = 45,
-  ARM_DTriple_with_qsub_0_in_QPRRegClassID = 46,
-  ARM_DTriple_with_ssub_2RegClassID = 47,
-  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 48,
-  ARM_DTripleSpc_with_ssub_4RegClassID = 49,
-  ARM_DTriple_with_ssub_4RegClassID = 50,
-  ARM_DTripleSpc_with_ssub_8RegClassID = 51,
-  ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 52,
-  ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 53,
-  ARM_DTriple_with_qsub_0_in_QPR_VFP2RegClassID = 54,
-  ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 55,
-  ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 56,
-  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 57,
-  ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRRegClassID = 58,
-  ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 59,
-  ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 60,
-  ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 61,
-  ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 62,
-  ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 63,
-  ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRRegClassID = 64,
-  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 65,
-  ARM_DQuadSpcRegClassID = 66,
-  ARM_DQuadSpc_with_ssub_0RegClassID = 67,
-  ARM_DQuadSpc_with_ssub_4RegClassID = 68,
-  ARM_DQuadSpc_with_ssub_8RegClassID = 69,
-  ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 70,
-  ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 71,
-  ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 72,
-  ARM_DQuadRegClassID = 73,
-  ARM_DQuad_with_ssub_0RegClassID = 74,
-  ARM_DQuad_with_ssub_2RegClassID = 75,
-  ARM_QQPRRegClassID = 76,
-  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 77,
-  ARM_DQuad_with_ssub_4RegClassID = 78,
-  ARM_DQuad_with_ssub_6RegClassID = 79,
-  ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 80,
-  ARM_DQuad_with_qsub_0_in_QPR_VFP2RegClassID = 81,
-  ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 82,
-  ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 83,
-  ARM_DQuad_with_qsub_1_in_QPR_VFP2RegClassID = 84,
-  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2RegClassID = 85,
-  ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 86,
-  ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 87,
-  ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 88,
-  ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 89,
-  ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 90,
-  ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 91,
-  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 92,
-  ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 93,
-  ARM_QQQQPRRegClassID = 94,
-  ARM_QQQQPR_with_ssub_0RegClassID = 95,
-  ARM_QQQQPR_with_ssub_4RegClassID = 96,
-  ARM_QQQQPR_with_ssub_8RegClassID = 97,
-  ARM_QQQQPR_with_ssub_12RegClassID = 98,
-  ARM_QQQQPR_with_dsub_0_in_DPR_8RegClassID = 99,
-  ARM_QQQQPR_with_dsub_2_in_DPR_8RegClassID = 100,
-  ARM_QQQQPR_with_dsub_4_in_DPR_8RegClassID = 101,
-  ARM_QQQQPR_with_dsub_6_in_DPR_8RegClassID = 102,
+  ARM_FPWithVPRRegClassID = 1,
+  ARM_SPRRegClassID = 2,
+  ARM_FPWithVPR_with_ssub_0RegClassID = 3,
+  ARM_GPRRegClassID = 4,
+  ARM_GPRwithAPSRRegClassID = 5,
+  ARM_GPRwithZRRegClassID = 6,
+  ARM_SPR_8RegClassID = 7,
+  ARM_GPRnopcRegClassID = 8,
+  ARM_GPRnospRegClassID = 9,
+  ARM_GPRwithAPSR_NZCVnospRegClassID = 10,
+  ARM_GPRwithAPSRnospRegClassID = 11,
+  ARM_GPRwithZRnospRegClassID = 12,
+  ARM_GPRnoipRegClassID = 13,
+  ARM_rGPRRegClassID = 14,
+  ARM_GPRnoip_and_GPRnopcRegClassID = 15,
+  ARM_GPRnoip_and_GPRnospRegClassID = 16,
+  ARM_GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17,
+  ARM_tGPRwithpcRegClassID = 18,
+  ARM_FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19,
+  ARM_hGPRRegClassID = 20,
+  ARM_tGPRRegClassID = 21,
+  ARM_tGPREvenRegClassID = 22,
+  ARM_GPRnopc_and_hGPRRegClassID = 23,
+  ARM_GPRnosp_and_hGPRRegClassID = 24,
+  ARM_GPRnoip_and_hGPRRegClassID = 25,
+  ARM_GPRnoip_and_tGPREvenRegClassID = 26,
+  ARM_GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27,
+  ARM_tGPROddRegClassID = 28,
+  ARM_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29,
+  ARM_GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30,
+  ARM_tcGPRRegClassID = 31,
+  ARM_GPRnoip_and_tcGPRRegClassID = 32,
+  ARM_GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 33,
+  ARM_hGPR_and_tGPREvenRegClassID = 34,
+  ARM_tGPR_and_tGPREvenRegClassID = 35,
+  ARM_tGPR_and_tGPROddRegClassID = 36,
+  ARM_tGPREven_and_tcGPRRegClassID = 37,
+  ARM_hGPR_and_GPRnoip_and_tGPREvenRegClassID = 38,
+  ARM_hGPR_and_tGPROddRegClassID = 39,
+  ARM_tGPREven_and_GPRnoip_and_tcGPRRegClassID = 40,
+  ARM_tGPROdd_and_tcGPRRegClassID = 41,
+  ARM_CCRRegClassID = 42,
+  ARM_FPCXTRegsRegClassID = 43,
+  ARM_GPRlrRegClassID = 44,
+  ARM_GPRspRegClassID = 45,
+  ARM_VCCRRegClassID = 46,
+  ARM_cl_FPSCR_NZCVRegClassID = 47,
+  ARM_hGPR_and_tGPRwithpcRegClassID = 48,
+  ARM_hGPR_and_tcGPRRegClassID = 49,
+  ARM_DPRRegClassID = 50,
+  ARM_DPR_VFP2RegClassID = 51,
+  ARM_DPR_8RegClassID = 52,
+  ARM_GPRPairRegClassID = 53,
+  ARM_GPRPairnospRegClassID = 54,
+  ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 55,
+  ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 56,
+  ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 57,
+  ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 58,
+  ARM_GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 59,
+  ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 60,
+  ARM_DPairSpcRegClassID = 61,
+  ARM_DPairSpc_with_ssub_0RegClassID = 62,
+  ARM_DPairSpc_with_ssub_4RegClassID = 63,
+  ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 64,
+  ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 65,
+  ARM_DPairRegClassID = 66,
+  ARM_DPair_with_ssub_0RegClassID = 67,
+  ARM_QPRRegClassID = 68,
+  ARM_DPair_with_ssub_2RegClassID = 69,
+  ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 70,
+  ARM_MQPRRegClassID = 71,
+  ARM_QPR_VFP2RegClassID = 72,
+  ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 73,
+  ARM_QPR_8RegClassID = 74,
+  ARM_DTripleRegClassID = 75,
+  ARM_DTripleSpcRegClassID = 76,
+  ARM_DTripleSpc_with_ssub_0RegClassID = 77,
+  ARM_DTriple_with_ssub_0RegClassID = 78,
+  ARM_DTriple_with_qsub_0_in_QPRRegClassID = 79,
+  ARM_DTriple_with_ssub_2RegClassID = 80,
+  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 81,
+  ARM_DTripleSpc_with_ssub_4RegClassID = 82,
+  ARM_DTriple_with_ssub_4RegClassID = 83,
+  ARM_DTripleSpc_with_ssub_8RegClassID = 84,
+  ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 85,
+  ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 86,
+  ARM_DTriple_with_qsub_0_in_MQPRRegClassID = 87,
+  ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 88,
+  ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 89,
+  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 90,
+  ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 91,
+  ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 92,
+  ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 93,
+  ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 94,
+  ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 95,
+  ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 96,
+  ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID = 97,
+  ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 98,
+  ARM_DQuadSpcRegClassID = 99,
+  ARM_DQuadSpc_with_ssub_0RegClassID = 100,
+  ARM_DQuadSpc_with_ssub_4RegClassID = 101,
+  ARM_DQuadSpc_with_ssub_8RegClassID = 102,
+  ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 103,
+  ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 104,
+  ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 105,
+  ARM_DQuadRegClassID = 106,
+  ARM_DQuad_with_ssub_0RegClassID = 107,
+  ARM_DQuad_with_ssub_2RegClassID = 108,
+  ARM_QQPRRegClassID = 109,
+  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 110,
+  ARM_DQuad_with_ssub_4RegClassID = 111,
+  ARM_DQuad_with_ssub_6RegClassID = 112,
+  ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 113,
+  ARM_DQuad_with_qsub_0_in_MQPRRegClassID = 114,
+  ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 115,
+  ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 116,
+  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 117,
+  ARM_MQQPRRegClassID = 118,
+  ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 119,
+  ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 120,
+  ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 121,
+  ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 122,
+  ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 123,
+  ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 124,
+  ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125,
+  ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 126,
+  ARM_QQQQPRRegClassID = 127,
+  ARM_QQQQPR_with_ssub_0RegClassID = 128,
+  ARM_QQQQPR_with_ssub_4RegClassID = 129,
+  ARM_QQQQPR_with_ssub_8RegClassID = 130,
+  ARM_MQQQQPRRegClassID = 131,
+  ARM_MQQQQPR_with_dsub_0_in_DPR_8RegClassID = 132,
+  ARM_MQQQQPR_with_dsub_2_in_DPR_8RegClassID = 133,
+  ARM_MQQQQPR_with_dsub_4_in_DPR_8RegClassID = 134,
+  ARM_MQQQQPR_with_dsub_6_in_DPR_8RegClassID = 135,
+
+};
+
+// Register alternate name indices
+
+enum {
+  ARM_NoRegAltName,	// 0
+  ARM_RegNamesRaw,	// 1
+  NUM_TARGET_REG_ALT_NAMES = 2
 };
 
 // Subregister indices
+
 enum {
   ARM_NoSubRegister,
   ARM_dsub_0,	// 1
@@ -446,8 +498,8 @@ enum {
   ARM_ssub_11,	// 28
   ARM_ssub_12,	// 29
   ARM_ssub_13,	// 30
-  ARM_dsub_7_then_ssub_0,	// 31
-  ARM_dsub_7_then_ssub_1,	// 32
+  ARM_ssub_14,	// 31
+  ARM_ssub_15,	// 32
   ARM_ssub_0_ssub_1_ssub_4_ssub_5,	// 33
   ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5,	// 34
   ARM_ssub_2_ssub_3_ssub_6_ssub_7,	// 35
@@ -474,34 +526,32 @@ enum {
   ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2,	// 56
   ARM_NUM_TARGET_SUBREGS
 };
-
 #endif // GET_REGINFO_ENUM
 
 #ifdef GET_REGINFO_MC_DESC
 #undef GET_REGINFO_MC_DESC
 
-
 static const MCPhysReg ARMRegDiffLists[] = {
-  /* 0 */ 64924, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 17 */ 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 32 */ 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 45 */ 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 56 */ 64450, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 65 */ 64984, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 74 */ 65252, 1, 1, 1, 1, 1, 1, 1, 0,
-  /* 83 */ 38, 1, 1, 1, 1, 1, 1, 0,
-  /* 91 */ 40, 1, 1, 1, 1, 1, 0,
-  /* 98 */ 65196, 1, 1, 1, 1, 1, 0,
-  /* 105 */ 40, 1, 1, 1, 1, 0,
-  /* 111 */ 42, 1, 1, 1, 1, 0,
-  /* 117 */ 42, 1, 1, 1, 0,
-  /* 122 */ 64510, 1, 1, 1, 0,
-  /* 127 */ 65015, 1, 1, 1, 0,
-  /* 132 */ 65282, 1, 1, 1, 0,
-  /* 137 */ 65348, 1, 1, 1, 0,
+  /* 0 */ 64902, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 17 */ 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 32 */ 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 45 */ 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 56 */ 64428, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 65 */ 64962, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 74 */ 65244, 1, 1, 1, 1, 1, 1, 1, 0,
+  /* 83 */ 44, 1, 1, 1, 1, 1, 1, 0,
+  /* 91 */ 46, 1, 1, 1, 1, 1, 0,
+  /* 98 */ 65188, 1, 1, 1, 1, 1, 0,
+  /* 105 */ 46, 1, 1, 1, 1, 0,
+  /* 111 */ 48, 1, 1, 1, 1, 0,
+  /* 117 */ 48, 1, 1, 1, 0,
+  /* 122 */ 64488, 1, 1, 1, 0,
+  /* 127 */ 65007, 1, 1, 1, 0,
+  /* 132 */ 65274, 1, 1, 1, 0,
+  /* 137 */ 65326, 1, 1, 1, 0,
   /* 142 */ 13, 1, 1, 0,
-  /* 146 */ 42, 1, 1, 0,
-  /* 150 */ 65388, 1, 1, 0,
+  /* 146 */ 48, 1, 1, 0,
+  /* 150 */ 65387, 1, 1, 0,
   /* 154 */ 137, 65489, 48, 65489, 12, 121, 65416, 1, 1, 0,
   /* 164 */ 136, 65490, 47, 65490, 12, 121, 65416, 1, 1, 0,
   /* 174 */ 135, 65491, 46, 65491, 12, 121, 65416, 1, 1, 0,
@@ -523,50 +573,50 @@ static const MCPhysReg ARMRegDiffLists[] = {
   /* 302 */ 65497, 133, 65416, 1, 1, 0,
   /* 308 */ 65498, 133, 65416, 1, 1, 0,
   /* 314 */ 127, 65499, 38, 65499, 133, 65416, 1, 1, 0,
-  /* 323 */ 65080, 1, 3, 1, 3, 1, 3, 1, 0,
-  /* 332 */ 65136, 1, 3, 1, 3, 1, 0,
-  /* 339 */ 65326, 1, 3, 1, 0,
+  /* 323 */ 65072, 1, 3, 1, 3, 1, 3, 1, 0,
+  /* 332 */ 65128, 1, 3, 1, 3, 1, 0,
+  /* 339 */ 65318, 1, 3, 1, 0,
   /* 344 */ 13, 1, 0,
   /* 347 */ 14, 1, 0,
-  /* 350 */ 65, 1, 0,
-  /* 353 */ 65500, 65, 1, 65471, 66, 1, 0,
-  /* 360 */ 65291, 66, 1, 65470, 67, 1, 0,
-  /* 367 */ 65439, 65, 1, 65472, 67, 1, 0,
-  /* 374 */ 65501, 67, 1, 65469, 68, 1, 0,
-  /* 381 */ 65439, 66, 1, 65471, 68, 1, 0,
-  /* 388 */ 65292, 68, 1, 65468, 69, 1, 0,
-  /* 395 */ 65439, 67, 1, 65470, 69, 1, 0,
-  /* 402 */ 65502, 69, 1, 65467, 70, 1, 0,
-  /* 409 */ 65439, 68, 1, 65469, 70, 1, 0,
-  /* 416 */ 65293, 70, 1, 65466, 71, 1, 0,
-  /* 423 */ 65439, 69, 1, 65468, 71, 1, 0,
-  /* 430 */ 65503, 71, 1, 65465, 72, 1, 0,
-  /* 437 */ 65439, 70, 1, 65467, 72, 1, 0,
-  /* 444 */ 65294, 72, 1, 65464, 73, 1, 0,
-  /* 451 */ 65439, 71, 1, 65466, 73, 1, 0,
-  /* 458 */ 65504, 73, 1, 65463, 74, 1, 0,
-  /* 465 */ 65439, 72, 1, 65465, 74, 1, 0,
-  /* 472 */ 65295, 74, 1, 65462, 75, 1, 0,
-  /* 479 */ 65439, 73, 1, 65464, 75, 1, 0,
-  /* 486 */ 65505, 75, 1, 65461, 76, 1, 0,
-  /* 493 */ 65439, 74, 1, 65463, 76, 1, 0,
-  /* 500 */ 65296, 76, 1, 65460, 77, 1, 0,
-  /* 507 */ 65439, 75, 1, 65462, 77, 1, 0,
-  /* 514 */ 65506, 77, 1, 65459, 78, 1, 0,
-  /* 521 */ 65439, 76, 1, 65461, 78, 1, 0,
-  /* 528 */ 65297, 78, 1, 65458, 79, 1, 0,
-  /* 535 */ 65439, 77, 1, 65460, 79, 1, 0,
-  /* 542 */ 65507, 79, 1, 65457, 80, 1, 0,
-  /* 549 */ 65439, 78, 1, 65459, 80, 1, 0,
-  /* 556 */ 65045, 1, 0,
-  /* 559 */ 65260, 1, 0,
-  /* 562 */ 65299, 1, 0,
-  /* 565 */ 65300, 1, 0,
-  /* 568 */ 65301, 1, 0,
-  /* 571 */ 65302, 1, 0,
-  /* 574 */ 65303, 1, 0,
-  /* 577 */ 65304, 1, 0,
-  /* 580 */ 65305, 1, 0,
+  /* 350 */ 66, 1, 0,
+  /* 353 */ 65499, 66, 1, 65470, 67, 1, 0,
+  /* 360 */ 65290, 67, 1, 65469, 68, 1, 0,
+  /* 367 */ 65438, 66, 1, 65471, 68, 1, 0,
+  /* 374 */ 65500, 68, 1, 65468, 69, 1, 0,
+  /* 381 */ 65438, 67, 1, 65470, 69, 1, 0,
+  /* 388 */ 65291, 69, 1, 65467, 70, 1, 0,
+  /* 395 */ 65438, 68, 1, 65469, 70, 1, 0,
+  /* 402 */ 65501, 70, 1, 65466, 71, 1, 0,
+  /* 409 */ 65438, 69, 1, 65468, 71, 1, 0,
+  /* 416 */ 65292, 71, 1, 65465, 72, 1, 0,
+  /* 423 */ 65438, 70, 1, 65467, 72, 1, 0,
+  /* 430 */ 65502, 72, 1, 65464, 73, 1, 0,
+  /* 437 */ 65438, 71, 1, 65466, 73, 1, 0,
+  /* 444 */ 65293, 73, 1, 65463, 74, 1, 0,
+  /* 451 */ 65438, 72, 1, 65465, 74, 1, 0,
+  /* 458 */ 65503, 74, 1, 65462, 75, 1, 0,
+  /* 465 */ 65438, 73, 1, 65464, 75, 1, 0,
+  /* 472 */ 65294, 75, 1, 65461, 76, 1, 0,
+  /* 479 */ 65438, 74, 1, 65463, 76, 1, 0,
+  /* 486 */ 65504, 76, 1, 65460, 77, 1, 0,
+  /* 493 */ 65438, 75, 1, 65462, 77, 1, 0,
+  /* 500 */ 65295, 77, 1, 65459, 78, 1, 0,
+  /* 507 */ 65438, 76, 1, 65461, 78, 1, 0,
+  /* 514 */ 65505, 78, 1, 65458, 79, 1, 0,
+  /* 521 */ 65438, 77, 1, 65460, 79, 1, 0,
+  /* 528 */ 65296, 79, 1, 65457, 80, 1, 0,
+  /* 535 */ 65438, 78, 1, 65459, 80, 1, 0,
+  /* 542 */ 65506, 80, 1, 65456, 81, 1, 0,
+  /* 549 */ 65438, 79, 1, 65458, 81, 1, 0,
+  /* 556 */ 65037, 1, 0,
+  /* 559 */ 65255, 1, 0,
+  /* 562 */ 65298, 1, 0,
+  /* 565 */ 65299, 1, 0,
+  /* 568 */ 65300, 1, 0,
+  /* 571 */ 65301, 1, 0,
+  /* 574 */ 65302, 1, 0,
+  /* 577 */ 65303, 1, 0,
+  /* 580 */ 65304, 1, 0,
   /* 583 */ 65453, 1, 65499, 133, 1, 65416, 1, 0,
   /* 591 */ 138, 65488, 49, 65488, 12, 121, 65416, 1, 0,
   /* 600 */ 65488, 13, 121, 65416, 1, 0,
@@ -594,249 +644,247 @@ static const MCPhysReg ARMRegDiffLists[] = {
   /* 765 */ 65488, 133, 65416, 1, 0,
   /* 770 */ 65499, 134, 65416, 1, 0,
   /* 775 */ 126, 65500, 37, 65500, 133, 65417, 1, 0,
-  /* 783 */ 65432, 1, 0,
-  /* 786 */ 65433, 1, 0,
-  /* 789 */ 65434, 1, 0,
-  /* 792 */ 65435, 1, 0,
-  /* 795 */ 65436, 1, 0,
-  /* 798 */ 65437, 1, 0,
-  /* 801 */ 65464, 1, 0,
-  /* 804 */ 65508, 1, 0,
-  /* 807 */ 65509, 1, 0,
-  /* 810 */ 65510, 1, 0,
-  /* 813 */ 65511, 1, 0,
-  /* 816 */ 65512, 1, 0,
-  /* 819 */ 65513, 1, 0,
-  /* 822 */ 65514, 1, 0,
-  /* 825 */ 65515, 1, 0,
-  /* 828 */ 65520, 1, 0,
-  /* 831 */ 65080, 1, 3, 1, 3, 1, 2, 0,
-  /* 839 */ 65136, 1, 3, 1, 2, 0,
-  /* 845 */ 65326, 1, 2, 0,
-  /* 849 */ 65080, 1, 3, 1, 2, 2, 0,
-  /* 856 */ 65136, 1, 2, 2, 0,
-  /* 861 */ 65080, 1, 2, 2, 2, 0,
-  /* 867 */ 65330, 2, 2, 2, 0,
-  /* 872 */ 65080, 1, 3, 2, 2, 0,
-  /* 878 */ 65358, 2, 2, 0,
-  /* 882 */ 65080, 1, 3, 1, 3, 2, 0,
-  /* 889 */ 65136, 1, 3, 2, 0,
-  /* 894 */ 65344, 76, 1, 65461, 78, 1, 65459, 80, 1, 12, 2, 0,
-  /* 906 */ 65344, 75, 1, 65462, 77, 1, 65460, 79, 1, 13, 2, 0,
-  /* 918 */ 65344, 74, 1, 65463, 76, 1, 65461, 78, 1, 14, 2, 0,
-  /* 930 */ 65344, 73, 1, 65464, 75, 1, 65462, 77, 1, 15, 2, 0,
-  /* 942 */ 65344, 72, 1, 65465, 74, 1, 65463, 76, 1, 16, 2, 0,
-  /* 954 */ 65344, 71, 1, 65466, 73, 1, 65464, 75, 1, 17, 2, 0,
-  /* 966 */ 65344, 70, 1, 65467, 72, 1, 65465, 74, 1, 18, 2, 0,
-  /* 978 */ 65344, 69, 1, 65468, 71, 1, 65466, 73, 1, 19, 2, 0,
-  /* 990 */ 65344, 68, 1, 65469, 70, 1, 65467, 72, 1, 20, 2, 0,
-  /* 1002 */ 65344, 67, 1, 65470, 69, 1, 65468, 71, 1, 21, 2, 0,
-  /* 1014 */ 65344, 66, 1, 65471, 68, 1, 65469, 70, 1, 22, 2, 0,
-  /* 1026 */ 65344, 65, 1, 65472, 67, 1, 65470, 69, 1, 23, 2, 0,
-  /* 1038 */ 65344, 2, 2, 93, 2, 0,
-  /* 1044 */ 65344, 80, 1, 65457, 2, 93, 2, 0,
-  /* 1052 */ 65344, 79, 1, 65458, 2, 93, 2, 0,
-  /* 1060 */ 65344, 78, 1, 65459, 80, 1, 65457, 93, 2, 0,
-  /* 1070 */ 65344, 77, 1, 65460, 79, 1, 65458, 93, 2, 0,
-  /* 1080 */ 65439, 2, 0,
-  /* 1083 */ 65453, 2, 0,
-  /* 1086 */ 65080, 1, 3, 1, 3, 1, 3, 0,
-  /* 1094 */ 65136, 1, 3, 1, 3, 0,
-  /* 1100 */ 65326, 1, 3, 0,
-  /* 1104 */ 5, 0,
-  /* 1106 */ 140, 65486, 13, 0,
-  /* 1110 */ 14, 0,
-  /* 1112 */ 126, 65501, 15, 0,
-  /* 1116 */ 10, 66, 0,
-  /* 1119 */ 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 0,
-  /* 1131 */ 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 0,
-  /* 1143 */ 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 0,
-  /* 1155 */ 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 0,
-  /* 1167 */ 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 0,
-  /* 1179 */ 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 0,
-  /* 1191 */ 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 0,
-  /* 1203 */ 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 0,
-  /* 1219 */ 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 0,
-  /* 1239 */ 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 0,
-  /* 1259 */ 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 0,
-  /* 1279 */ 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 0,
-  /* 1299 */ 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 0,
-  /* 1319 */ 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 0,
-  /* 1339 */ 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 0,
-  /* 1359 */ 91, 0,
-  /* 1361 */ 98, 0,
-  /* 1363 */ 99, 0,
-  /* 1365 */ 100, 0,
-  /* 1367 */ 101, 0,
-  /* 1369 */ 102, 0,
-  /* 1371 */ 103, 0,
-  /* 1373 */ 104, 0,
-  /* 1375 */ 65374, 1, 1, 20, 75, 135, 0,
-  /* 1382 */ 65374, 1, 1, 21, 74, 136, 0,
-  /* 1389 */ 65374, 1, 1, 22, 73, 137, 0,
-  /* 1396 */ 65374, 1, 1, 23, 72, 138, 0,
-  /* 1403 */ 65374, 1, 1, 24, 71, 139, 0,
-  /* 1410 */ 65374, 1, 1, 25, 70, 140, 0,
-  /* 1417 */ 65374, 1, 1, 26, 69, 141, 0,
-  /* 1424 */ 65374, 79, 1, 65457, 80, 1, 65456, 27, 68, 142, 0,
-  /* 1435 */ 65374, 77, 1, 65459, 78, 1, 65458, 79, 1, 65484, 67, 143, 0,
-  /* 1448 */ 65374, 75, 1, 65461, 76, 1, 65460, 77, 1, 65487, 66, 144, 0,
-  /* 1461 */ 65374, 73, 1, 65463, 74, 1, 65462, 75, 1, 65490, 65, 145, 0,
-  /* 1474 */ 65374, 71, 1, 65465, 72, 1, 65464, 73, 1, 65493, 64, 146, 0,
-  /* 1487 */ 65374, 69, 1, 65467, 70, 1, 65466, 71, 1, 65496, 63, 147, 0,
-  /* 1500 */ 65374, 67, 1, 65469, 68, 1, 65468, 69, 1, 65499, 62, 148, 0,
-  /* 1513 */ 65374, 65, 1, 65471, 66, 1, 65470, 67, 1, 65502, 61, 149, 0,
-  /* 1526 */ 157, 0,
-  /* 1528 */ 65289, 1, 1, 1, 229, 1, 65400, 65, 65472, 65, 65396, 0,
-  /* 1540 */ 65288, 1, 1, 1, 230, 1, 65399, 65, 65472, 65, 65397, 0,
-  /* 1552 */ 65287, 1, 1, 1, 231, 1, 65398, 65, 65472, 65, 65398, 0,
-  /* 1564 */ 65286, 1, 1, 1, 232, 1, 65397, 65, 65472, 65, 65399, 0,
-  /* 1576 */ 65285, 1, 1, 1, 233, 1, 65396, 65, 65472, 65, 65400, 0,
-  /* 1588 */ 65284, 1, 1, 1, 234, 1, 65395, 65, 65472, 65, 65401, 0,
-  /* 1600 */ 65521, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65419, 65445, 65514, 1, 22, 65515, 1, 94, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
-  /* 1639 */ 65521, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65419, 65445, 65513, 1, 23, 65514, 1, 94, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
-  /* 1678 */ 65521, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65419, 65445, 65512, 1, 24, 65513, 1, 94, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
-  /* 1717 */ 65521, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65419, 65445, 65511, 1, 25, 65512, 1, 94, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
-  /* 1756 */ 65521, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65419, 65445, 65510, 1, 26, 65511, 1, 94, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
-  /* 1795 */ 65521, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65419, 65445, 65509, 1, 27, 65510, 1, 94, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
-  /* 1838 */ 65521, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65508, 1, 28, 65509, 1, 94, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
-  /* 1885 */ 65521, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65507, 79, 1, 65457, 80, 1, 65484, 65508, 1, 94, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
-  /* 1936 */ 65521, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65506, 77, 1, 65459, 78, 1, 65487, 65507, 79, 1, 65457, 80, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
-  /* 1991 */ 65521, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65505, 75, 1, 65461, 76, 1, 65490, 65506, 77, 1, 65459, 78, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
-  /* 2046 */ 65521, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65504, 73, 1, 65463, 74, 1, 65493, 65505, 75, 1, 65461, 76, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
-  /* 2101 */ 65521, 65445, 65501, 67, 1, 65469, 68, 1, 65502, 65502, 69, 1, 65467, 70, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65503, 71, 1, 65465, 72, 1, 65496, 65504, 73, 1, 65463, 74, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
-  /* 2156 */ 65521, 65445, 65500, 65, 1, 65471, 66, 1, 65505, 65501, 67, 1, 65469, 68, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65502, 69, 1, 65467, 70, 1, 65499, 65503, 71, 1, 65465, 72, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
-  /* 2211 */ 65283, 80, 1, 65456, 1, 1, 235, 1, 65394, 65, 65472, 65, 65402, 0,
-  /* 2225 */ 65282, 78, 1, 65458, 79, 1, 65457, 80, 1, 65456, 236, 1, 65393, 65, 65472, 65, 65403, 0,
-  /* 2243 */ 65281, 76, 1, 65460, 77, 1, 65459, 78, 1, 65458, 79, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
-  /* 2263 */ 65280, 74, 1, 65462, 75, 1, 65461, 76, 1, 65460, 77, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
-  /* 2283 */ 65279, 72, 1, 65464, 73, 1, 65463, 74, 1, 65462, 75, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
-  /* 2303 */ 65278, 70, 1, 65466, 71, 1, 65465, 72, 1, 65464, 73, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
-  /* 2323 */ 65277, 68, 1, 65468, 69, 1, 65467, 70, 1, 65466, 71, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
-  /* 2343 */ 65276, 66, 1, 65470, 67, 1, 65469, 68, 1, 65468, 69, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
-  /* 2363 */ 22, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
-  /* 2384 */ 21, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
-  /* 2401 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
-  /* 2411 */ 22, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
-  /* 2429 */ 21, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
-  /* 2440 */ 65, 65487, 77, 26, 30, 65416, 0,
-  /* 2447 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
-  /* 2455 */ 65487, 13, 121, 65416, 0,
-  /* 2460 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
-  /* 2468 */ 65466, 1, 65486, 133, 65416, 0,
-  /* 2474 */ 65487, 133, 65416, 0,
-  /* 2478 */ 65469, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
-  /* 2490 */ 65470, 35, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
-  /* 2502 */ 65, 65500, 66, 28, 40, 65417, 0,
-  /* 2509 */ 65452, 1, 65500, 134, 65417, 0,
-  /* 2515 */ 65316, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 10, 95, 65443, 95, 65443, 0,
-  /* 2533 */ 65316, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 11, 95, 65443, 95, 65443, 0,
-  /* 2551 */ 65316, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 12, 95, 65443, 95, 65443, 0,
-  /* 2569 */ 65316, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 13, 95, 65443, 95, 65443, 0,
-  /* 2587 */ 65316, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 14, 95, 65443, 95, 65443, 0,
-  /* 2605 */ 65316, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 15, 95, 65443, 95, 65443, 0,
-  /* 2623 */ 65316, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 16, 95, 65443, 95, 65443, 0,
-  /* 2641 */ 65316, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 17, 95, 65443, 95, 65443, 0,
-  /* 2659 */ 65316, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 18, 95, 65443, 95, 65443, 0,
-  /* 2677 */ 65316, 65, 1, 65472, 67, 1, 65470, 69, 1, 65468, 71, 1, 19, 95, 65443, 95, 65443, 0,
-  /* 2695 */ 65316, 2, 2, 2, 91, 95, 65443, 95, 65443, 0,
-  /* 2705 */ 65316, 80, 1, 65457, 2, 2, 91, 95, 65443, 95, 65443, 0,
-  /* 2717 */ 65316, 79, 1, 65458, 2, 2, 91, 95, 65443, 95, 65443, 0,
-  /* 2729 */ 65316, 78, 1, 65459, 80, 1, 65457, 2, 91, 95, 65443, 95, 65443, 0,
-  /* 2743 */ 65316, 77, 1, 65460, 79, 1, 65458, 2, 91, 95, 65443, 95, 65443, 0,
-  /* 2757 */ 65316, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 91, 95, 65443, 95, 65443, 0,
-  /* 2773 */ 65316, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 91, 95, 65443, 95, 65443, 0,
-  /* 2789 */ 20, 75, 65, 65486, 78, 26, 65445, 0,
-  /* 2797 */ 23, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
-  /* 2820 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
-  /* 2832 */ 26, 65446, 92, 65445, 0,
-  /* 2837 */ 23, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
-  /* 2858 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
-  /* 2868 */ 24, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
-  /* 2891 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
-  /* 2903 */ 24, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
-  /* 2926 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
-  /* 2938 */ 25, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
-  /* 2961 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
-  /* 2973 */ 25, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
-  /* 2996 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
-  /* 3008 */ 26, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
-  /* 3031 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
-  /* 3043 */ 26, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
-  /* 3066 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
-  /* 3078 */ 27, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
-  /* 3101 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
-  /* 3113 */ 27, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
-  /* 3136 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
-  /* 3148 */ 65455, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
-  /* 3172 */ 65456, 28, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
-  /* 3196 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
-  /* 3208 */ 28, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
-  /* 3231 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
-  /* 3243 */ 65457, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
-  /* 3267 */ 65458, 29, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
-  /* 3291 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
-  /* 3303 */ 65456, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
-  /* 3327 */ 65457, 29, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
-  /* 3351 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
-  /* 3363 */ 65459, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
-  /* 3387 */ 65460, 30, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
-  /* 3411 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
-  /* 3423 */ 65458, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
-  /* 3447 */ 65459, 30, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
-  /* 3471 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
-  /* 3483 */ 65461, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
-  /* 3507 */ 65462, 31, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
-  /* 3531 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
-  /* 3543 */ 65460, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
-  /* 3567 */ 65461, 31, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
-  /* 3591 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
-  /* 3603 */ 65463, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
-  /* 3627 */ 65464, 32, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
-  /* 3651 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
-  /* 3663 */ 65462, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
-  /* 3687 */ 65463, 32, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
-  /* 3711 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
-  /* 3723 */ 65465, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
-  /* 3745 */ 65466, 33, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
+  /* 783 */ 65433, 1, 0,
+  /* 786 */ 65434, 1, 0,
+  /* 789 */ 65435, 1, 0,
+  /* 792 */ 65436, 1, 0,
+  /* 795 */ 65437, 1, 0,
+  /* 798 */ 65438, 1, 0,
+  /* 801 */ 65456, 1, 0,
+  /* 804 */ 65507, 1, 0,
+  /* 807 */ 65508, 1, 0,
+  /* 810 */ 65509, 1, 0,
+  /* 813 */ 65510, 1, 0,
+  /* 816 */ 65511, 1, 0,
+  /* 819 */ 65512, 1, 0,
+  /* 822 */ 65513, 1, 0,
+  /* 825 */ 65514, 1, 0,
+  /* 828 */ 65072, 1, 3, 1, 3, 1, 2, 0,
+  /* 836 */ 65128, 1, 3, 1, 2, 0,
+  /* 842 */ 65318, 1, 2, 0,
+  /* 846 */ 65072, 1, 3, 1, 2, 2, 0,
+  /* 853 */ 65128, 1, 2, 2, 0,
+  /* 858 */ 65072, 1, 2, 2, 2, 0,
+  /* 864 */ 65329, 2, 2, 2, 0,
+  /* 869 */ 65072, 1, 3, 2, 2, 0,
+  /* 875 */ 65357, 2, 2, 0,
+  /* 879 */ 65072, 1, 3, 1, 3, 2, 0,
+  /* 886 */ 65128, 1, 3, 2, 0,
+  /* 891 */ 65343, 77, 1, 65460, 79, 1, 65458, 81, 1, 12, 2, 0,
+  /* 903 */ 65343, 76, 1, 65461, 78, 1, 65459, 80, 1, 13, 2, 0,
+  /* 915 */ 65343, 75, 1, 65462, 77, 1, 65460, 79, 1, 14, 2, 0,
+  /* 927 */ 65343, 74, 1, 65463, 76, 1, 65461, 78, 1, 15, 2, 0,
+  /* 939 */ 65343, 73, 1, 65464, 75, 1, 65462, 77, 1, 16, 2, 0,
+  /* 951 */ 65343, 72, 1, 65465, 74, 1, 65463, 76, 1, 17, 2, 0,
+  /* 963 */ 65343, 71, 1, 65466, 73, 1, 65464, 75, 1, 18, 2, 0,
+  /* 975 */ 65343, 70, 1, 65467, 72, 1, 65465, 74, 1, 19, 2, 0,
+  /* 987 */ 65343, 69, 1, 65468, 71, 1, 65466, 73, 1, 20, 2, 0,
+  /* 999 */ 65343, 68, 1, 65469, 70, 1, 65467, 72, 1, 21, 2, 0,
+  /* 1011 */ 65343, 67, 1, 65470, 69, 1, 65468, 71, 1, 22, 2, 0,
+  /* 1023 */ 65343, 66, 1, 65471, 68, 1, 65469, 70, 1, 23, 2, 0,
+  /* 1035 */ 65343, 2, 2, 94, 2, 0,
+  /* 1041 */ 65343, 81, 1, 65456, 2, 94, 2, 0,
+  /* 1049 */ 65343, 80, 1, 65457, 2, 94, 2, 0,
+  /* 1057 */ 65343, 79, 1, 65458, 81, 1, 65456, 94, 2, 0,
+  /* 1067 */ 65343, 78, 1, 65459, 80, 1, 65457, 94, 2, 0,
+  /* 1077 */ 65438, 2, 0,
+  /* 1080 */ 65452, 2, 0,
+  /* 1083 */ 65072, 1, 3, 1, 3, 1, 3, 0,
+  /* 1091 */ 65128, 1, 3, 1, 3, 0,
+  /* 1097 */ 65318, 1, 3, 0,
+  /* 1101 */ 7, 0,
+  /* 1103 */ 140, 65486, 13, 0,
+  /* 1107 */ 14, 0,
+  /* 1109 */ 126, 65501, 15, 0,
+  /* 1113 */ 14, 69, 0,
+  /* 1116 */ 65445, 65513, 1, 23, 65514, 1, 95, 65, 65472, 65, 69, 0,
+  /* 1128 */ 65445, 65512, 1, 24, 65513, 1, 95, 65, 65472, 65, 70, 0,
+  /* 1140 */ 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 0,
+  /* 1152 */ 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 0,
+  /* 1164 */ 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 0,
+  /* 1176 */ 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 0,
+  /* 1188 */ 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 0,
+  /* 1200 */ 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 0,
+  /* 1216 */ 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 0,
+  /* 1236 */ 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 0,
+  /* 1256 */ 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 0,
+  /* 1276 */ 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 0,
+  /* 1296 */ 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 0,
+  /* 1316 */ 65445, 65500, 68, 1, 65468, 69, 1, 65502, 65501, 70, 1, 65466, 71, 1, 23, 65, 65472, 65, 82, 0,
+  /* 1336 */ 65445, 65499, 66, 1, 65470, 67, 1, 65505, 65500, 68, 1, 65468, 69, 1, 25, 65, 65472, 65, 83, 0,
+  /* 1356 */ 97, 0,
+  /* 1358 */ 98, 0,
+  /* 1360 */ 99, 0,
+  /* 1362 */ 100, 0,
+  /* 1364 */ 101, 0,
+  /* 1366 */ 102, 0,
+  /* 1368 */ 103, 0,
+  /* 1370 */ 65373, 1, 1, 21, 75, 135, 0,
+  /* 1377 */ 65373, 1, 1, 22, 74, 136, 0,
+  /* 1384 */ 65373, 1, 1, 23, 73, 137, 0,
+  /* 1391 */ 65373, 1, 1, 24, 72, 138, 0,
+  /* 1398 */ 65373, 1, 1, 25, 71, 139, 0,
+  /* 1405 */ 65373, 1, 1, 26, 70, 140, 0,
+  /* 1412 */ 65373, 1, 1, 27, 69, 141, 0,
+  /* 1419 */ 65373, 80, 1, 65456, 81, 1, 65455, 28, 68, 142, 0,
+  /* 1430 */ 65373, 78, 1, 65458, 79, 1, 65457, 80, 1, 65484, 67, 143, 0,
+  /* 1443 */ 65373, 76, 1, 65460, 77, 1, 65459, 78, 1, 65487, 66, 144, 0,
+  /* 1456 */ 65373, 74, 1, 65462, 75, 1, 65461, 76, 1, 65490, 65, 145, 0,
+  /* 1469 */ 65373, 72, 1, 65464, 73, 1, 65463, 74, 1, 65493, 64, 146, 0,
+  /* 1482 */ 65373, 70, 1, 65466, 71, 1, 65465, 72, 1, 65496, 63, 147, 0,
+  /* 1495 */ 65373, 68, 1, 65468, 69, 1, 65467, 70, 1, 65499, 62, 148, 0,
+  /* 1508 */ 65373, 66, 1, 65470, 67, 1, 65469, 68, 1, 65502, 61, 149, 0,
+  /* 1521 */ 166, 0,
+  /* 1523 */ 65288, 1, 1, 1, 230, 1, 65400, 65, 65472, 65, 65396, 0,
+  /* 1535 */ 65287, 1, 1, 1, 231, 1, 65399, 65, 65472, 65, 65397, 0,
+  /* 1547 */ 65286, 1, 1, 1, 232, 1, 65398, 65, 65472, 65, 65398, 0,
+  /* 1559 */ 65285, 1, 1, 1, 233, 1, 65397, 65, 65472, 65, 65399, 0,
+  /* 1571 */ 65284, 1, 1, 1, 234, 1, 65396, 65, 65472, 65, 65400, 0,
+  /* 1583 */ 65283, 1, 1, 1, 235, 1, 65395, 65, 65472, 65, 65401, 0,
+  /* 1595 */ 65521, 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 65419, 65445, 65513, 1, 23, 65514, 1, 95, 65, 65472, 65, 69, 65492, 28, 65509, 28, 28, 65386, 65, 30, 65442, 65, 30, 40, 15, 65402, 0,
+  /* 1634 */ 65521, 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 65419, 65445, 65512, 1, 24, 65513, 1, 95, 65, 65472, 65, 70, 65491, 28, 65509, 28, 29, 65385, 65, 30, 65442, 65, 30, 41, 15, 65402, 0,
+  /* 1673 */ 65521, 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 65419, 65445, 65511, 1, 25, 65512, 1, 95, 65, 65472, 65, 71, 65490, 28, 65509, 28, 30, 65384, 65, 30, 65442, 65, 30, 42, 15, 65402, 0,
+  /* 1712 */ 65521, 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 65419, 65445, 65510, 1, 26, 65511, 1, 95, 65, 65472, 65, 72, 65489, 28, 65509, 28, 31, 65383, 65, 30, 65442, 65, 30, 43, 15, 65402, 0,
+  /* 1751 */ 65521, 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 65419, 65445, 65509, 1, 27, 65510, 1, 95, 65, 65472, 65, 73, 65488, 28, 65509, 28, 32, 65382, 65, 30, 65442, 65, 30, 44, 15, 65402, 0,
+  /* 1790 */ 65521, 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 65419, 65445, 65508, 1, 28, 65509, 1, 95, 65, 65472, 65, 74, 65487, 28, 65509, 28, 33, 65381, 65, 30, 65442, 65, 30, 45, 15, 65402, 0,
+  /* 1833 */ 65521, 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 65419, 65445, 65507, 1, 29, 65508, 1, 95, 65, 65472, 65, 75, 65486, 28, 65509, 28, 34, 65380, 65, 30, 65442, 65, 30, 46, 15, 65402, 0,
+  /* 1880 */ 65521, 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 65419, 65445, 65506, 80, 1, 65456, 81, 1, 65484, 65507, 1, 95, 65, 65472, 65, 76, 65485, 28, 65509, 28, 35, 65379, 65, 30, 65442, 65, 30, 47, 15, 65402, 0,
+  /* 1931 */ 65521, 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 65419, 65445, 65505, 78, 1, 65458, 79, 1, 65487, 65506, 80, 1, 65456, 81, 1, 13, 65, 65472, 65, 77, 65484, 28, 65509, 28, 36, 65378, 65, 30, 65442, 65, 30, 48, 15, 65402, 0,
+  /* 1986 */ 65521, 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 65419, 65445, 65504, 76, 1, 65460, 77, 1, 65490, 65505, 78, 1, 65458, 79, 1, 15, 65, 65472, 65, 78, 65483, 28, 65509, 28, 37, 65377, 65, 30, 65442, 65, 30, 49, 15, 65402, 0,
+  /* 2041 */ 65521, 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 65419, 65445, 65503, 74, 1, 65462, 75, 1, 65493, 65504, 76, 1, 65460, 77, 1, 17, 65, 65472, 65, 79, 65482, 28, 65509, 28, 38, 65376, 65, 30, 65442, 65, 30, 50, 15, 65402, 0,
+  /* 2096 */ 65521, 65445, 65500, 68, 1, 65468, 69, 1, 65502, 65501, 70, 1, 65466, 71, 1, 23, 65, 65472, 65, 82, 65419, 65445, 65502, 72, 1, 65464, 73, 1, 65496, 65503, 74, 1, 65462, 75, 1, 19, 65, 65472, 65, 80, 65481, 28, 65509, 28, 39, 65375, 65, 30, 65442, 65, 30, 51, 15, 65402, 0,
+  /* 2151 */ 65521, 65445, 65499, 66, 1, 65470, 67, 1, 65505, 65500, 68, 1, 65468, 69, 1, 25, 65, 65472, 65, 83, 65419, 65445, 65501, 70, 1, 65466, 71, 1, 65499, 65502, 72, 1, 65464, 73, 1, 21, 65, 65472, 65, 81, 65480, 28, 65509, 28, 40, 65374, 65, 30, 65442, 65, 30, 52, 15, 65402, 0,
+  /* 2206 */ 65282, 81, 1, 65455, 1, 1, 236, 1, 65394, 65, 65472, 65, 65402, 0,
+  /* 2220 */ 65281, 79, 1, 65457, 80, 1, 65456, 81, 1, 65455, 237, 1, 65393, 65, 65472, 65, 65403, 0,
+  /* 2238 */ 65280, 77, 1, 65459, 78, 1, 65458, 79, 1, 65457, 80, 1, 157, 1, 65392, 65, 65472, 65, 65404, 0,
+  /* 2258 */ 65279, 75, 1, 65461, 76, 1, 65460, 77, 1, 65459, 78, 1, 160, 1, 65391, 65, 65472, 65, 65405, 0,
+  /* 2278 */ 65278, 73, 1, 65463, 74, 1, 65462, 75, 1, 65461, 76, 1, 163, 1, 65390, 65, 65472, 65, 65406, 0,
+  /* 2298 */ 65277, 71, 1, 65465, 72, 1, 65464, 73, 1, 65463, 74, 1, 166, 1, 65389, 65, 65472, 65, 65407, 0,
+  /* 2318 */ 65276, 69, 1, 65467, 70, 1, 65466, 71, 1, 65465, 72, 1, 169, 1, 65388, 65, 65472, 65, 65408, 0,
+  /* 2338 */ 65275, 67, 1, 65469, 68, 1, 65468, 69, 1, 65467, 70, 1, 172, 1, 65387, 65, 65472, 65, 65409, 0,
+  /* 2358 */ 23, 73, 2, 63, 65488, 120, 65465, 1, 65487, 75, 26, 65447, 65, 26, 30, 65416, 66, 26, 29, 65416, 0,
+  /* 2379 */ 22, 74, 2, 63, 65487, 120, 65466, 1, 65486, 76, 26, 65446, 66, 26, 29, 65416, 0,
+  /* 2396 */ 65, 65487, 77, 26, 65446, 66, 26, 29, 65416, 0,
+  /* 2406 */ 23, 73, 2, 134, 65465, 1, 65487, 50, 65487, 75, 26, 31, 65416, 65, 26, 30, 65416, 0,
+  /* 2424 */ 22, 74, 135, 65466, 1, 65486, 77, 26, 30, 65416, 0,
+  /* 2435 */ 65, 65487, 77, 26, 30, 65416, 0,
+  /* 2442 */ 139, 65487, 50, 65487, 12, 121, 65416, 0,
+  /* 2450 */ 65487, 13, 121, 65416, 0,
+  /* 2455 */ 65465, 1, 65487, 133, 65416, 121, 65416, 0,
+  /* 2463 */ 65466, 1, 65486, 133, 65416, 0,
+  /* 2469 */ 65487, 133, 65416, 0,
+  /* 2473 */ 65468, 36, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
+  /* 2485 */ 65469, 36, 62, 148, 65452, 1, 65500, 66, 28, 40, 65417, 0,
+  /* 2497 */ 65, 65500, 66, 28, 40, 65417, 0,
+  /* 2504 */ 65452, 1, 65500, 134, 65417, 0,
+  /* 2510 */ 65315, 75, 1, 65462, 77, 1, 65460, 79, 1, 65458, 81, 1, 10, 95, 65443, 95, 65443, 0,
+  /* 2528 */ 65315, 74, 1, 65463, 76, 1, 65461, 78, 1, 65459, 80, 1, 11, 95, 65443, 95, 65443, 0,
+  /* 2546 */ 65315, 73, 1, 65464, 75, 1, 65462, 77, 1, 65460, 79, 1, 12, 95, 65443, 95, 65443, 0,
+  /* 2564 */ 65315, 72, 1, 65465, 74, 1, 65463, 76, 1, 65461, 78, 1, 13, 95, 65443, 95, 65443, 0,
+  /* 2582 */ 65315, 71, 1, 65466, 73, 1, 65464, 75, 1, 65462, 77, 1, 14, 95, 65443, 95, 65443, 0,
+  /* 2600 */ 65315, 70, 1, 65467, 72, 1, 65465, 74, 1, 65463, 76, 1, 15, 95, 65443, 95, 65443, 0,
+  /* 2618 */ 65315, 69, 1, 65468, 71, 1, 65466, 73, 1, 65464, 75, 1, 16, 95, 65443, 95, 65443, 0,
+  /* 2636 */ 65315, 68, 1, 65469, 70, 1, 65467, 72, 1, 65465, 74, 1, 17, 95, 65443, 95, 65443, 0,
+  /* 2654 */ 65315, 67, 1, 65470, 69, 1, 65468, 71, 1, 65466, 73, 1, 18, 95, 65443, 95, 65443, 0,
+  /* 2672 */ 65315, 66, 1, 65471, 68, 1, 65469, 70, 1, 65467, 72, 1, 19, 95, 65443, 95, 65443, 0,
+  /* 2690 */ 65315, 2, 2, 2, 92, 95, 65443, 95, 65443, 0,
+  /* 2700 */ 65315, 81, 1, 65456, 2, 2, 92, 95, 65443, 95, 65443, 0,
+  /* 2712 */ 65315, 80, 1, 65457, 2, 2, 92, 95, 65443, 95, 65443, 0,
+  /* 2724 */ 65315, 79, 1, 65458, 81, 1, 65456, 2, 92, 95, 65443, 95, 65443, 0,
+  /* 2738 */ 65315, 78, 1, 65459, 80, 1, 65457, 2, 92, 95, 65443, 95, 65443, 0,
+  /* 2752 */ 65315, 77, 1, 65460, 79, 1, 65458, 81, 1, 65456, 92, 95, 65443, 95, 65443, 0,
+  /* 2768 */ 65315, 76, 1, 65461, 78, 1, 65459, 80, 1, 65457, 92, 95, 65443, 95, 65443, 0,
+  /* 2784 */ 21, 75, 65, 65486, 78, 26, 65445, 0,
+  /* 2792 */ 24, 72, 2, 63, 65489, 120, 65464, 1, 65488, 74, 26, 65448, 64, 26, 31, 65416, 65, 26, 30, 65416, 92, 65445, 0,
+  /* 2815 */ 65, 65488, 76, 26, 65447, 65, 26, 30, 65416, 92, 65445, 0,
+  /* 2827 */ 26, 65446, 92, 65445, 0,
+  /* 2832 */ 24, 72, 2, 135, 65464, 1, 65488, 49, 65488, 74, 26, 32, 65416, 64, 26, 31, 65416, 65, 26, 65446, 0,
+  /* 2853 */ 65, 65488, 76, 26, 31, 65416, 65, 26, 65446, 0,
+  /* 2863 */ 25, 71, 2, 63, 65490, 120, 65463, 1, 65489, 73, 26, 65449, 63, 26, 32, 65416, 64, 26, 31, 65416, 91, 65446, 0,
+  /* 2886 */ 65, 65489, 75, 26, 65448, 64, 26, 31, 65416, 91, 65446, 0,
+  /* 2898 */ 25, 71, 2, 136, 65463, 1, 65489, 48, 65489, 73, 26, 33, 65416, 63, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
+  /* 2921 */ 65, 65489, 75, 26, 32, 65416, 64, 26, 65447, 91, 65446, 0,
+  /* 2933 */ 26, 70, 2, 63, 65491, 120, 65462, 1, 65490, 72, 26, 65450, 62, 26, 33, 65416, 63, 26, 32, 65416, 90, 65447, 0,
+  /* 2956 */ 65, 65490, 74, 26, 65449, 63, 26, 32, 65416, 90, 65447, 0,
+  /* 2968 */ 26, 70, 2, 137, 65462, 1, 65490, 47, 65490, 72, 26, 34, 65416, 62, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
+  /* 2991 */ 65, 65490, 74, 26, 33, 65416, 63, 26, 65448, 90, 65447, 0,
+  /* 3003 */ 27, 69, 2, 63, 65492, 120, 65461, 1, 65491, 71, 26, 65451, 61, 26, 34, 65416, 62, 26, 33, 65416, 89, 65448, 0,
+  /* 3026 */ 65, 65491, 73, 26, 65450, 62, 26, 33, 65416, 89, 65448, 0,
+  /* 3038 */ 27, 69, 2, 138, 65461, 1, 65491, 46, 65491, 71, 26, 35, 65416, 61, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
+  /* 3061 */ 65, 65491, 73, 26, 34, 65416, 62, 26, 65449, 89, 65448, 0,
+  /* 3073 */ 28, 68, 2, 63, 65493, 120, 65460, 1, 65492, 70, 26, 65452, 60, 26, 35, 65416, 61, 26, 34, 65416, 88, 65449, 0,
+  /* 3096 */ 65, 65492, 72, 26, 65451, 61, 26, 34, 65416, 88, 65449, 0,
+  /* 3108 */ 28, 68, 2, 139, 65460, 1, 65492, 45, 65492, 70, 26, 36, 65416, 60, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
+  /* 3131 */ 65, 65492, 72, 26, 35, 65416, 61, 26, 65450, 88, 65449, 0,
+  /* 3143 */ 65454, 29, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
+  /* 3167 */ 65455, 29, 67, 2, 63, 65494, 120, 65459, 1, 65493, 69, 26, 65453, 59, 26, 36, 65416, 60, 26, 35, 65416, 87, 65450, 0,
+  /* 3191 */ 65, 65493, 71, 26, 65452, 60, 26, 35, 65416, 87, 65450, 0,
+  /* 3203 */ 29, 67, 2, 140, 65459, 1, 65493, 44, 65493, 69, 26, 37, 65416, 59, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
+  /* 3226 */ 65, 65493, 71, 26, 36, 65416, 60, 26, 65451, 87, 65450, 0,
+  /* 3238 */ 65456, 30, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
+  /* 3262 */ 65457, 30, 66, 2, 63, 65495, 120, 65458, 1, 65494, 68, 26, 65454, 58, 26, 37, 65416, 59, 26, 36, 65416, 86, 65451, 0,
+  /* 3286 */ 65, 65494, 70, 26, 65453, 59, 26, 36, 65416, 86, 65451, 0,
+  /* 3298 */ 65455, 30, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
+  /* 3322 */ 65456, 30, 66, 2, 141, 65458, 1, 65494, 43, 65494, 68, 26, 38, 65416, 58, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
+  /* 3346 */ 65, 65494, 70, 26, 37, 65416, 59, 26, 65452, 86, 65451, 0,
+  /* 3358 */ 65458, 31, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
+  /* 3382 */ 65459, 31, 65, 2, 63, 65496, 120, 65457, 1, 65495, 67, 26, 65455, 57, 26, 38, 65416, 58, 26, 37, 65416, 85, 65452, 0,
+  /* 3406 */ 65, 65495, 69, 26, 65454, 58, 26, 37, 65416, 85, 65452, 0,
+  /* 3418 */ 65457, 31, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
+  /* 3442 */ 65458, 31, 65, 2, 142, 65457, 1, 65495, 42, 65495, 67, 26, 39, 65416, 57, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
+  /* 3466 */ 65, 65495, 69, 26, 38, 65416, 58, 26, 65453, 85, 65452, 0,
+  /* 3478 */ 65460, 32, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
+  /* 3502 */ 65461, 32, 64, 2, 63, 65497, 120, 65456, 1, 65496, 66, 26, 65456, 56, 26, 39, 65416, 57, 26, 38, 65416, 84, 65453, 0,
+  /* 3526 */ 65, 65496, 68, 26, 65455, 57, 26, 38, 65416, 84, 65453, 0,
+  /* 3538 */ 65459, 32, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
+  /* 3562 */ 65460, 32, 64, 2, 143, 65456, 1, 65496, 41, 65496, 66, 26, 40, 65416, 56, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
+  /* 3586 */ 65, 65496, 68, 26, 39, 65416, 57, 26, 65454, 84, 65453, 0,
+  /* 3598 */ 65462, 33, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
+  /* 3622 */ 65463, 33, 63, 2, 63, 65498, 120, 65455, 1, 65497, 65, 26, 65457, 55, 26, 40, 65416, 56, 26, 39, 65416, 83, 65454, 0,
+  /* 3646 */ 65, 65497, 67, 26, 65456, 56, 26, 39, 65416, 83, 65454, 0,
+  /* 3658 */ 65461, 33, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
+  /* 3682 */ 65462, 33, 63, 2, 144, 65455, 1, 65497, 40, 65497, 65, 26, 41, 65416, 55, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
+  /* 3706 */ 65, 65497, 67, 26, 40, 65416, 56, 26, 65455, 83, 65454, 0,
+  /* 3718 */ 65297, 81, 1, 65455, 0,
+  /* 3723 */ 65464, 34, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
+  /* 3745 */ 65465, 34, 62, 2, 63, 65499, 120, 65454, 1, 65498, 64, 2, 26, 41, 65416, 55, 26, 40, 65416, 82, 65455, 0,
   /* 3767 */ 65, 65498, 66, 26, 65457, 55, 26, 40, 65416, 82, 65455, 0,
-  /* 3779 */ 65464, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
-  /* 3803 */ 65465, 33, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
+  /* 3779 */ 65463, 34, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
+  /* 3803 */ 65464, 34, 62, 2, 145, 65454, 1, 65498, 39, 65498, 64, 26, 42, 65416, 54, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
   /* 3827 */ 65, 65498, 66, 26, 41, 65416, 55, 26, 65456, 82, 65455, 0,
-  /* 3839 */ 65298, 80, 1, 65456, 0,
-  /* 3844 */ 65467, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
-  /* 3863 */ 65468, 34, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
+  /* 3839 */ 65438, 81, 1, 65456, 0,
+  /* 3844 */ 65466, 35, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
+  /* 3863 */ 65467, 35, 61, 2, 63, 65500, 120, 65453, 1, 65499, 65, 2, 26, 40, 1, 65416, 81, 65456, 0,
   /* 3882 */ 65, 65499, 65, 2, 26, 41, 65416, 81, 65456, 0,
-  /* 3892 */ 65466, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
-  /* 3914 */ 65467, 34, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
+  /* 3892 */ 65465, 35, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
+  /* 3914 */ 65466, 35, 61, 2, 146, 65453, 1, 65499, 38, 65499, 63, 2, 26, 41, 1, 65416, 54, 26, 65457, 81, 65456, 0,
   /* 3936 */ 65, 65499, 65, 26, 42, 65416, 54, 26, 65457, 81, 65456, 0,
-  /* 3948 */ 65439, 80, 1, 65457, 0,
+  /* 3948 */ 65438, 80, 1, 65457, 0,
   /* 3953 */ 28, 65457, 0,
-  /* 3956 */ 65468, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
-  /* 3974 */ 65469, 35, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
+  /* 3956 */ 65467, 36, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
+  /* 3974 */ 65468, 36, 60, 2, 147, 65452, 1, 65500, 37, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
   /* 3992 */ 65, 65500, 64, 2, 26, 41, 65417, 80, 65457, 0,
   /* 4002 */ 26, 65458, 80, 65457, 0,
-  /* 4007 */ 65439, 79, 1, 65458, 0,
-  /* 4012 */ 65470, 36, 61, 65, 65501, 65, 28, 65458, 0,
-  /* 4021 */ 65471, 36, 61, 65, 65501, 65, 28, 65458, 0,
-  /* 4030 */ 65374, 1, 1, 229, 65402, 65461, 0,
-  /* 4037 */ 65374, 1, 1, 230, 65401, 65462, 0,
-  /* 4044 */ 65374, 1, 1, 231, 65400, 65463, 0,
-  /* 4051 */ 65374, 1, 1, 232, 65399, 65464, 0,
-  /* 4058 */ 65374, 1, 1, 233, 65398, 65465, 0,
-  /* 4065 */ 65374, 1, 1, 234, 65397, 65466, 0,
-  /* 4072 */ 65374, 1, 1, 235, 65396, 65467, 0,
-  /* 4079 */ 65374, 80, 1, 65456, 1, 236, 65395, 65468, 0,
-  /* 4088 */ 65374, 78, 1, 65458, 79, 1, 65457, 80, 1, 156, 65394, 65469, 0,
-  /* 4101 */ 65374, 76, 1, 65460, 77, 1, 65459, 78, 1, 159, 65393, 65470, 0,
-  /* 4114 */ 65445, 65470, 0,
-  /* 4117 */ 65374, 74, 1, 65462, 75, 1, 65461, 76, 1, 162, 65392, 65471, 0,
-  /* 4130 */ 65374, 72, 1, 65464, 73, 1, 65463, 74, 1, 165, 65391, 65472, 0,
-  /* 4143 */ 65374, 70, 1, 65466, 71, 1, 65465, 72, 1, 168, 65390, 65473, 0,
-  /* 4156 */ 65374, 68, 1, 65468, 69, 1, 65467, 70, 1, 171, 65389, 65474, 0,
-  /* 4169 */ 65374, 66, 1, 65470, 67, 1, 65469, 68, 1, 174, 65388, 65475, 0,
-  /* 4182 */ 65534, 0,
-  /* 4184 */ 65535, 0,
+  /* 4007 */ 65469, 37, 61, 65, 65501, 65, 28, 65458, 0,
+  /* 4016 */ 65470, 37, 61, 65, 65501, 65, 28, 65458, 0,
+  /* 4025 */ 65373, 1, 1, 230, 65402, 65461, 0,
+  /* 4032 */ 65373, 1, 1, 231, 65401, 65462, 0,
+  /* 4039 */ 65373, 1, 1, 232, 65400, 65463, 0,
+  /* 4046 */ 65373, 1, 1, 233, 65399, 65464, 0,
+  /* 4053 */ 65373, 1, 1, 234, 65398, 65465, 0,
+  /* 4060 */ 65373, 1, 1, 235, 65397, 65466, 0,
+  /* 4067 */ 65373, 1, 1, 236, 65396, 65467, 0,
+  /* 4074 */ 65439, 65467, 0,
+  /* 4077 */ 65373, 81, 1, 65455, 1, 237, 65395, 65468, 0,
+  /* 4086 */ 65373, 79, 1, 65457, 80, 1, 65456, 81, 1, 156, 65394, 65469, 0,
+  /* 4099 */ 65373, 77, 1, 65459, 78, 1, 65458, 79, 1, 159, 65393, 65470, 0,
+  /* 4112 */ 65373, 75, 1, 65461, 76, 1, 65460, 77, 1, 162, 65392, 65471, 0,
+  /* 4125 */ 65373, 73, 1, 65463, 74, 1, 65462, 75, 1, 165, 65391, 65472, 0,
+  /* 4138 */ 65373, 71, 1, 65465, 72, 1, 65464, 73, 1, 168, 65390, 65473, 0,
+  /* 4151 */ 65373, 69, 1, 65467, 70, 1, 65466, 71, 1, 171, 65389, 65474, 0,
+  /* 4164 */ 65373, 67, 1, 65469, 68, 1, 65468, 69, 1, 174, 65388, 65475, 0,
+  /* 4177 */ 65534, 0,
+  /* 4179 */ 65535, 0,
 };
 
 static const uint16_t ARMSubRegIdxLists[] = {
@@ -875,1153 +923,1726 @@ static const uint16_t ARMSubRegIdxLists[] = {
   /* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
 };
 
-static const MCRegisterDesc ARMRegDesc[] = {
+static const MCRegisterDesc ARMRegDesc[] = { // Descriptors
   { 12, 0, 0, 0, 0, 0 },
-  { 1235, 16, 16, 2, 66945, 0 },
-  { 1268, 16, 16, 2, 66945, 0 },
-  { 1240, 16, 16, 2, 66945, 0 },
-  { 1199, 16, 16, 2, 66945, 0 },
-  { 1250, 16, 16, 2, 66945, 0 },
-  { 1226, 16, 16, 2, 17664, 0 },
-  { 1257, 16, 16, 2, 17664, 0 },
-  { 1205, 16, 16, 2, 66913, 0 },
-  { 1211, 16, 16, 2, 66913, 0 },
-  { 1232, 16, 16, 2, 66913, 0 },
-  { 1196, 16, 16, 2, 66913, 0 },
-  { 1223, 16, 1526, 2, 66913, 0 },
-  { 1245, 16, 16, 2, 66913, 0 },
-  { 119, 350, 4013, 19, 13250, 8 },
-  { 248, 357, 2479, 19, 13250, 8 },
-  { 363, 364, 3957, 19, 13250, 8 },
-  { 479, 378, 3845, 19, 13250, 8 },
-  { 605, 392, 3893, 19, 13250, 8 },
-  { 723, 406, 3724, 19, 13250, 8 },
-  { 837, 420, 3780, 19, 13250, 8 },
-  { 943, 434, 3604, 19, 13250, 8 },
-  { 1057, 448, 3664, 19, 13250, 8 },
-  { 1163, 462, 3484, 19, 13250, 8 },
-  { 9, 476, 3544, 19, 13250, 8 },
-  { 141, 490, 3364, 19, 13250, 8 },
-  { 282, 504, 3424, 19, 13250, 8 },
-  { 408, 518, 3244, 19, 13250, 8 },
-  { 523, 532, 3304, 19, 13250, 8 },
-  { 649, 546, 3149, 19, 13250, 8 },
-  { 768, 16, 3208, 2, 17761, 0 },
-  { 882, 16, 3078, 2, 17761, 0 },
-  { 988, 16, 3113, 2, 17761, 0 },
-  { 1102, 16, 3008, 2, 17761, 0 },
-  { 59, 16, 3043, 2, 17761, 0 },
-  { 192, 16, 2938, 2, 17761, 0 },
-  { 336, 16, 2973, 2, 17761, 0 },
-  { 456, 16, 2868, 2, 17761, 0 },
-  { 575, 16, 2903, 2, 17761, 0 },
-  { 697, 16, 2797, 2, 17761, 0 },
-  { 804, 16, 2837, 2, 17761, 0 },
-  { 914, 16, 2363, 2, 17761, 0 },
-  { 1024, 16, 2411, 2, 17761, 0 },
-  { 1134, 16, 2384, 2, 17761, 0 },
-  { 95, 16, 2429, 2, 17761, 0 },
-  { 224, 16, 2789, 2, 17761, 0 },
-  { 390, 16, 16, 2, 17761, 0 },
-  { 125, 16, 16, 2, 17761, 0 },
-  { 257, 16, 16, 2, 17761, 0 },
-  { 381, 16, 16, 2, 17761, 0 },
-  { 122, 353, 1112, 22, 2196, 11 },
-  { 254, 374, 775, 22, 2196, 11 },
-  { 378, 402, 314, 22, 2196, 11 },
-  { 500, 430, 244, 22, 2196, 11 },
-  { 629, 458, 234, 22, 2196, 11 },
-  { 744, 486, 224, 22, 2196, 11 },
-  { 861, 514, 214, 22, 2196, 11 },
-  { 964, 542, 204, 22, 2196, 11 },
-  { 1081, 804, 194, 0, 12818, 20 },
-  { 1184, 807, 184, 0, 12818, 20 },
+  { 1268, 16, 16, 2, 66865, 0 },
+  { 1319, 16, 16, 2, 66865, 0 },
+  { 1273, 16, 16, 2, 66865, 0 },
+  { 1286, 16, 16, 2, 66865, 0 },
+  { 1294, 16, 16, 2, 66865, 0 },
+  { 1215, 16, 16, 2, 66865, 0 },
+  { 1301, 16, 16, 2, 66865, 0 },
+  { 1255, 16, 16, 2, 17616, 0 },
+  { 1308, 16, 16, 2, 17616, 0 },
+  { 1202, 16, 16, 2, 66833, 0 },
+  { 1221, 16, 16, 2, 66833, 0 },
+  { 1240, 16, 16, 2, 66833, 0 },
+  { 1261, 16, 16, 2, 66833, 0 },
+  { 1199, 16, 16, 2, 66833, 0 },
+  { 1227, 16, 16, 2, 66833, 0 },
+  { 1252, 16, 1521, 2, 66833, 0 },
+  { 1278, 16, 16, 2, 66833, 0 },
+  { 1264, 16, 16, 2, 66833, 0 },
+  { 1283, 16, 16, 2, 66833, 0 },
+  { 119, 350, 4008, 19, 13202, 8 },
+  { 251, 357, 2474, 19, 13202, 8 },
+  { 366, 364, 3957, 19, 13202, 8 },
+  { 482, 378, 3845, 19, 13202, 8 },
+  { 608, 392, 3893, 19, 13202, 8 },
+  { 726, 406, 3724, 19, 13202, 8 },
+  { 840, 420, 3780, 19, 13202, 8 },
+  { 946, 434, 3599, 19, 13202, 8 },
+  { 1060, 448, 3659, 19, 13202, 8 },
+  { 1166, 462, 3479, 19, 13202, 8 },
+  { 9, 476, 3539, 19, 13202, 8 },
+  { 144, 490, 3359, 19, 13202, 8 },
+  { 285, 504, 3419, 19, 13202, 8 },
+  { 411, 518, 3239, 19, 13202, 8 },
+  { 526, 532, 3299, 19, 13202, 8 },
+  { 652, 546, 3144, 19, 13202, 8 },
+  { 771, 16, 3203, 2, 17713, 0 },
+  { 885, 16, 3073, 2, 17713, 0 },
+  { 991, 16, 3108, 2, 17713, 0 },
+  { 1105, 16, 3003, 2, 17713, 0 },
+  { 59, 16, 3038, 2, 17713, 0 },
+  { 195, 16, 2933, 2, 17713, 0 },
+  { 339, 16, 2968, 2, 17713, 0 },
+  { 459, 16, 2863, 2, 17713, 0 },
+  { 578, 16, 2898, 2, 17713, 0 },
+  { 700, 16, 2792, 2, 17713, 0 },
+  { 807, 16, 2832, 2, 17713, 0 },
+  { 917, 16, 2358, 2, 17713, 0 },
+  { 1027, 16, 2406, 2, 17713, 0 },
+  { 1137, 16, 2379, 2, 17713, 0 },
+  { 95, 16, 2424, 2, 17713, 0 },
+  { 227, 16, 2784, 2, 17713, 0 },
+  { 393, 16, 16, 2, 17713, 0 },
+  { 128, 16, 16, 2, 17713, 0 },
+  { 260, 16, 16, 2, 17713, 0 },
+  { 384, 16, 16, 2, 17713, 0 },
+  { 122, 16, 16, 2, 17713, 0 },
+  { 125, 353, 1109, 22, 2196, 11 },
+  { 257, 374, 775, 22, 2196, 11 },
+  { 381, 402, 314, 22, 2196, 11 },
+  { 503, 430, 244, 22, 2196, 11 },
+  { 632, 458, 234, 22, 2196, 11 },
+  { 747, 486, 224, 22, 2196, 11 },
+  { 864, 514, 214, 22, 2196, 11 },
+  { 967, 542, 204, 22, 2196, 11 },
+  { 1084, 804, 194, 0, 12818, 20 },
+  { 1187, 807, 184, 0, 12818, 20 },
   { 35, 810, 174, 0, 12818, 20 },
-  { 168, 813, 164, 0, 12818, 20 },
-  { 312, 816, 154, 0, 12818, 20 },
-  { 436, 819, 591, 0, 12818, 20 },
-  { 555, 822, 2447, 0, 12818, 20 },
-  { 677, 825, 1106, 0, 12818, 20 },
-  { 128, 16, 1373, 2, 66913, 0 },
-  { 260, 16, 1371, 2, 66913, 0 },
-  { 384, 16, 1371, 2, 66913, 0 },
-  { 506, 16, 1369, 2, 66913, 0 },
-  { 632, 16, 1369, 2, 66913, 0 },
-  { 750, 16, 1367, 2, 66913, 0 },
-  { 864, 16, 1367, 2, 66913, 0 },
-  { 970, 16, 1365, 2, 66913, 0 },
-  { 1084, 16, 1365, 2, 66913, 0 },
-  { 1190, 16, 1363, 2, 66913, 0 },
-  { 39, 16, 1363, 2, 66913, 0 },
-  { 176, 16, 1361, 2, 66913, 0 },
-  { 316, 16, 1359, 2, 66913, 0 },
-  { 131, 16, 4021, 2, 65585, 0 },
-  { 269, 16, 4012, 2, 65585, 0 },
-  { 387, 16, 2490, 2, 65585, 0 },
-  { 509, 16, 2478, 2, 65585, 0 },
-  { 635, 16, 3974, 2, 65585, 0 },
-  { 753, 16, 3956, 2, 65585, 0 },
-  { 867, 16, 3863, 2, 65585, 0 },
-  { 973, 16, 3844, 2, 65585, 0 },
-  { 1087, 16, 3914, 2, 65585, 0 },
-  { 1193, 16, 3892, 2, 65585, 0 },
-  { 43, 16, 3745, 2, 65585, 0 },
-  { 180, 16, 3723, 2, 65585, 0 },
-  { 320, 16, 3803, 2, 65585, 0 },
-  { 440, 16, 3779, 2, 65585, 0 },
-  { 559, 16, 3627, 2, 65585, 0 },
-  { 681, 16, 3603, 2, 65585, 0 },
-  { 788, 16, 3687, 2, 65585, 0 },
-  { 898, 16, 3663, 2, 65585, 0 },
-  { 1008, 16, 3507, 2, 65585, 0 },
-  { 1118, 16, 3483, 2, 65585, 0 },
-  { 79, 16, 3567, 2, 65585, 0 },
-  { 212, 16, 3543, 2, 65585, 0 },
-  { 356, 16, 3387, 2, 65585, 0 },
-  { 472, 16, 3363, 2, 65585, 0 },
-  { 595, 16, 3447, 2, 65585, 0 },
-  { 713, 16, 3423, 2, 65585, 0 },
-  { 824, 16, 3267, 2, 65585, 0 },
-  { 930, 16, 3243, 2, 65585, 0 },
-  { 1044, 16, 3327, 2, 65585, 0 },
-  { 1150, 16, 3303, 2, 65585, 0 },
-  { 115, 16, 3172, 2, 65585, 0 },
-  { 244, 16, 3148, 2, 65585, 0 },
-  { 360, 367, 4015, 29, 5426, 23 },
-  { 476, 381, 2502, 29, 5426, 23 },
-  { 602, 395, 3992, 29, 5426, 23 },
-  { 720, 409, 3882, 29, 5426, 23 },
-  { 834, 423, 3936, 29, 5426, 23 },
-  { 940, 437, 3767, 29, 5426, 23 },
-  { 1054, 451, 3827, 29, 5426, 23 },
-  { 1160, 465, 3651, 29, 5426, 23 },
-  { 6, 479, 3711, 29, 5426, 23 },
-  { 151, 493, 3531, 29, 5426, 23 },
-  { 278, 507, 3591, 29, 5426, 23 },
-  { 404, 521, 3411, 29, 5426, 23 },
-  { 519, 535, 3471, 29, 5426, 23 },
-  { 645, 549, 3291, 29, 5426, 23 },
-  { 764, 4007, 3351, 11, 17602, 35 },
-  { 878, 3948, 3196, 11, 13522, 35 },
-  { 984, 1080, 3231, 8, 17329, 39 },
-  { 1098, 1080, 3101, 8, 17329, 39 },
-  { 55, 1080, 3136, 8, 17329, 39 },
-  { 204, 1080, 3031, 8, 17329, 39 },
-  { 332, 1080, 3066, 8, 17329, 39 },
-  { 452, 1080, 2961, 8, 17329, 39 },
-  { 571, 1080, 2996, 8, 17329, 39 },
-  { 693, 1080, 2891, 8, 17329, 39 },
-  { 800, 1080, 2926, 8, 17329, 39 },
-  { 910, 1080, 2820, 8, 17329, 39 },
-  { 1020, 1080, 2858, 8, 17329, 39 },
-  { 1130, 1080, 2401, 8, 17329, 39 },
-  { 91, 1080, 2440, 8, 17329, 39 },
-  { 236, 1080, 2791, 8, 17329, 39 },
-  { 251, 1339, 1114, 168, 1044, 57 },
-  { 375, 1319, 347, 168, 1044, 57 },
-  { 497, 1299, 142, 168, 1044, 57 },
-  { 626, 1279, 142, 168, 1044, 57 },
-  { 741, 1259, 142, 168, 1044, 57 },
-  { 858, 1239, 142, 168, 1044, 57 },
-  { 961, 1219, 142, 168, 1044, 57 },
-  { 1078, 1203, 142, 88, 1456, 74 },
-  { 1181, 1191, 142, 76, 2114, 87 },
-  { 32, 1179, 142, 76, 2114, 87 },
-  { 164, 1167, 142, 76, 2114, 87 },
-  { 308, 1155, 142, 76, 2114, 87 },
-  { 432, 1143, 142, 76, 2114, 87 },
-  { 551, 1131, 344, 76, 2114, 87 },
-  { 673, 1119, 1108, 76, 2114, 87 },
-  { 491, 2156, 16, 474, 4, 149 },
-  { 620, 2101, 16, 474, 4, 149 },
-  { 735, 2046, 16, 474, 4, 149 },
-  { 852, 1991, 16, 474, 4, 149 },
-  { 955, 1936, 16, 474, 4, 149 },
-  { 1072, 1885, 16, 423, 272, 166 },
-  { 1175, 1838, 16, 376, 512, 181 },
-  { 26, 1795, 16, 333, 720, 194 },
-  { 158, 1756, 16, 294, 1186, 205 },
-  { 301, 1717, 16, 294, 1186, 205 },
-  { 424, 1678, 16, 294, 1186, 205 },
-  { 543, 1639, 16, 294, 1186, 205 },
-  { 665, 1600, 16, 294, 1186, 205 },
-  { 1219, 4114, 16, 16, 17856, 2 },
-  { 263, 783, 16, 16, 8946, 5 },
-  { 503, 786, 16, 16, 8946, 5 },
-  { 747, 789, 16, 16, 8946, 5 },
-  { 967, 792, 16, 16, 8946, 5 },
-  { 1187, 795, 16, 16, 8946, 5 },
-  { 172, 798, 16, 16, 8946, 5 },
-  { 366, 1513, 1113, 63, 1570, 28 },
-  { 482, 4169, 2511, 63, 1570, 28 },
-  { 611, 1500, 778, 63, 1570, 28 },
-  { 726, 4156, 770, 63, 1570, 28 },
-  { 843, 1487, 317, 63, 1570, 28 },
-  { 946, 4143, 660, 63, 1570, 28 },
-  { 1063, 1474, 308, 63, 1570, 28 },
-  { 1166, 4130, 654, 63, 1570, 28 },
-  { 16, 1461, 302, 63, 1570, 28 },
-  { 134, 4117, 648, 63, 1570, 28 },
-  { 289, 1448, 296, 63, 1570, 28 },
-  { 412, 4101, 642, 63, 1570, 28 },
-  { 531, 1435, 290, 63, 1570, 28 },
-  { 653, 4088, 636, 63, 1570, 28 },
-  { 776, 1424, 284, 52, 1680, 42 },
-  { 886, 4079, 630, 43, 1872, 48 },
-  { 996, 1417, 278, 36, 2401, 53 },
-  { 1106, 4072, 624, 36, 2401, 53 },
-  { 67, 1410, 272, 36, 2401, 53 },
-  { 184, 4065, 618, 36, 2401, 53 },
-  { 344, 1403, 266, 36, 2401, 53 },
-  { 460, 4058, 612, 36, 2401, 53 },
-  { 583, 1396, 260, 36, 2401, 53 },
-  { 701, 4051, 606, 36, 2401, 53 },
-  { 812, 1389, 254, 36, 2401, 53 },
-  { 918, 4044, 600, 36, 2401, 53 },
-  { 1032, 1382, 765, 36, 2401, 53 },
-  { 1138, 4037, 2455, 36, 2401, 53 },
-  { 103, 1375, 2474, 36, 2401, 53 },
-  { 216, 4030, 1107, 36, 2401, 53 },
-  { 599, 1026, 4018, 212, 5314, 92 },
-  { 717, 1014, 3953, 212, 5314, 92 },
-  { 831, 1002, 4002, 212, 5314, 92 },
-  { 937, 990, 3909, 212, 5314, 92 },
-  { 1051, 978, 3909, 212, 5314, 92 },
-  { 1157, 966, 3798, 212, 5314, 92 },
-  { 3, 954, 3798, 212, 5314, 92 },
-  { 148, 942, 3682, 212, 5314, 92 },
-  { 275, 930, 3682, 212, 5314, 92 },
-  { 401, 918, 3562, 212, 5314, 92 },
-  { 515, 906, 3562, 212, 5314, 92 },
-  { 641, 894, 3442, 212, 5314, 92 },
-  { 760, 1070, 3442, 202, 17506, 99 },
-  { 874, 1060, 3322, 202, 13426, 99 },
-  { 980, 1052, 3322, 194, 14226, 105 },
-  { 1094, 1044, 3226, 194, 13698, 105 },
-  { 51, 1038, 3226, 188, 14049, 110 },
-  { 200, 1038, 3131, 188, 14049, 110 },
-  { 328, 1038, 3131, 188, 14049, 110 },
-  { 448, 1038, 3061, 188, 14049, 110 },
-  { 567, 1038, 3061, 188, 14049, 110 },
-  { 689, 1038, 2991, 188, 14049, 110 },
-  { 796, 1038, 2991, 188, 14049, 110 },
-  { 906, 1038, 2921, 188, 14049, 110 },
-  { 1016, 1038, 2921, 188, 14049, 110 },
-  { 1126, 1038, 2832, 188, 14049, 110 },
-  { 87, 1038, 2855, 188, 14049, 110 },
-  { 232, 1038, 2794, 188, 14049, 110 },
-  { 828, 2677, 4010, 276, 5170, 114 },
-  { 934, 2659, 3951, 276, 5170, 114 },
-  { 1048, 2641, 3951, 276, 5170, 114 },
-  { 1154, 2623, 3842, 276, 5170, 114 },
-  { 0, 2605, 3842, 276, 5170, 114 },
-  { 145, 2587, 3743, 276, 5170, 114 },
-  { 272, 2569, 3743, 276, 5170, 114 },
-  { 398, 2551, 3625, 276, 5170, 114 },
-  { 512, 2533, 3625, 276, 5170, 114 },
-  { 638, 2515, 3505, 276, 5170, 114 },
-  { 756, 2773, 3505, 260, 17378, 123 },
-  { 870, 2757, 3385, 260, 13298, 123 },
-  { 976, 2743, 3385, 246, 14114, 131 },
-  { 1090, 2729, 3265, 246, 13586, 131 },
-  { 47, 2717, 3265, 234, 13954, 138 },
-  { 196, 2705, 3170, 234, 13778, 138 },
-  { 324, 2695, 3170, 224, 13873, 144 },
-  { 444, 2695, 3099, 224, 13873, 144 },
-  { 563, 2695, 3099, 224, 13873, 144 },
-  { 685, 2695, 3029, 224, 13873, 144 },
-  { 792, 2695, 3029, 224, 13873, 144 },
-  { 902, 2695, 2959, 224, 13873, 144 },
-  { 1012, 2695, 2959, 224, 13873, 144 },
-  { 1122, 2695, 2856, 224, 13873, 144 },
-  { 83, 2695, 2856, 224, 13873, 144 },
-  { 228, 2695, 2795, 224, 13873, 144 },
-  { 369, 360, 2509, 22, 1956, 11 },
-  { 614, 388, 583, 22, 1956, 11 },
-  { 846, 416, 756, 22, 1956, 11 },
-  { 1066, 444, 747, 22, 1956, 11 },
+  { 171, 813, 164, 0, 12818, 20 },
+  { 315, 816, 154, 0, 12818, 20 },
+  { 439, 819, 591, 0, 12818, 20 },
+  { 558, 822, 2442, 0, 12818, 20 },
+  { 680, 825, 1103, 0, 12818, 20 },
+  { 131, 16, 1368, 2, 66833, 0 },
+  { 263, 16, 1366, 2, 66833, 0 },
+  { 387, 16, 1366, 2, 66833, 0 },
+  { 509, 16, 1364, 2, 66833, 0 },
+  { 635, 16, 1364, 2, 66833, 0 },
+  { 753, 16, 1362, 2, 66833, 0 },
+  { 867, 16, 1362, 2, 66833, 0 },
+  { 973, 16, 1360, 2, 66833, 0 },
+  { 1087, 16, 1360, 2, 66833, 0 },
+  { 1193, 16, 1358, 2, 66833, 0 },
+  { 39, 16, 1358, 2, 66833, 0 },
+  { 179, 16, 1356, 2, 66833, 0 },
+  { 319, 16, 1356, 2, 66833, 0 },
+  { 134, 16, 4016, 2, 65345, 0 },
+  { 272, 16, 4007, 2, 65345, 0 },
+  { 390, 16, 2485, 2, 65345, 0 },
+  { 512, 16, 2473, 2, 65345, 0 },
+  { 638, 16, 3974, 2, 65345, 0 },
+  { 756, 16, 3956, 2, 65345, 0 },
+  { 870, 16, 3863, 2, 65345, 0 },
+  { 976, 16, 3844, 2, 65345, 0 },
+  { 1090, 16, 3914, 2, 65345, 0 },
+  { 1196, 16, 3892, 2, 65345, 0 },
+  { 43, 16, 3745, 2, 65345, 0 },
+  { 183, 16, 3723, 2, 65345, 0 },
+  { 323, 16, 3803, 2, 65345, 0 },
+  { 443, 16, 3779, 2, 65345, 0 },
+  { 562, 16, 3622, 2, 65345, 0 },
+  { 684, 16, 3598, 2, 65345, 0 },
+  { 791, 16, 3682, 2, 65345, 0 },
+  { 901, 16, 3658, 2, 65345, 0 },
+  { 1011, 16, 3502, 2, 65345, 0 },
+  { 1121, 16, 3478, 2, 65345, 0 },
+  { 79, 16, 3562, 2, 65345, 0 },
+  { 215, 16, 3538, 2, 65345, 0 },
+  { 359, 16, 3382, 2, 65345, 0 },
+  { 475, 16, 3358, 2, 65345, 0 },
+  { 598, 16, 3442, 2, 65345, 0 },
+  { 716, 16, 3418, 2, 65345, 0 },
+  { 827, 16, 3262, 2, 65345, 0 },
+  { 933, 16, 3238, 2, 65345, 0 },
+  { 1047, 16, 3322, 2, 65345, 0 },
+  { 1153, 16, 3298, 2, 65345, 0 },
+  { 115, 16, 3167, 2, 65345, 0 },
+  { 247, 16, 3143, 2, 65345, 0 },
+  { 363, 367, 4010, 29, 5426, 23 },
+  { 479, 381, 2497, 29, 5426, 23 },
+  { 605, 395, 3992, 29, 5426, 23 },
+  { 723, 409, 3882, 29, 5426, 23 },
+  { 837, 423, 3936, 29, 5426, 23 },
+  { 943, 437, 3767, 29, 5426, 23 },
+  { 1057, 451, 3827, 29, 5426, 23 },
+  { 1163, 465, 3646, 29, 5426, 23 },
+  { 6, 479, 3706, 29, 5426, 23 },
+  { 154, 493, 3526, 29, 5426, 23 },
+  { 281, 507, 3586, 29, 5426, 23 },
+  { 407, 521, 3406, 29, 5426, 23 },
+  { 522, 535, 3466, 29, 5426, 23 },
+  { 648, 549, 3286, 29, 5426, 23 },
+  { 767, 3948, 3346, 11, 17554, 35 },
+  { 881, 3839, 3191, 11, 13474, 35 },
+  { 987, 1077, 3226, 8, 17281, 39 },
+  { 1101, 1077, 3096, 8, 17281, 39 },
+  { 55, 1077, 3131, 8, 17281, 39 },
+  { 207, 1077, 3026, 8, 17281, 39 },
+  { 335, 1077, 3061, 8, 17281, 39 },
+  { 455, 1077, 2956, 8, 17281, 39 },
+  { 574, 1077, 2991, 8, 17281, 39 },
+  { 696, 1077, 2886, 8, 17281, 39 },
+  { 803, 1077, 2921, 8, 17281, 39 },
+  { 913, 1077, 2815, 8, 17281, 39 },
+  { 1023, 1077, 2853, 8, 17281, 39 },
+  { 1133, 1077, 2396, 8, 17281, 39 },
+  { 91, 1077, 2435, 8, 17281, 39 },
+  { 239, 1077, 2786, 8, 17281, 39 },
+  { 254, 1336, 1111, 168, 1044, 57 },
+  { 378, 1316, 347, 168, 1044, 57 },
+  { 500, 1296, 142, 168, 1044, 57 },
+  { 629, 1276, 142, 168, 1044, 57 },
+  { 744, 1256, 142, 168, 1044, 57 },
+  { 861, 1236, 142, 168, 1044, 57 },
+  { 964, 1216, 142, 168, 1044, 57 },
+  { 1081, 1200, 142, 88, 1456, 74 },
+  { 1184, 1188, 142, 76, 2114, 87 },
+  { 32, 1176, 142, 76, 2114, 87 },
+  { 167, 1164, 142, 76, 2114, 87 },
+  { 311, 1152, 142, 76, 2114, 87 },
+  { 435, 1140, 142, 76, 2114, 87 },
+  { 554, 1128, 344, 76, 2114, 87 },
+  { 676, 1116, 1105, 76, 2114, 87 },
+  { 494, 2151, 16, 474, 4, 149 },
+  { 623, 2096, 16, 474, 4, 149 },
+  { 738, 2041, 16, 474, 4, 149 },
+  { 855, 1986, 16, 474, 4, 149 },
+  { 958, 1931, 16, 474, 4, 149 },
+  { 1075, 1880, 16, 423, 272, 166 },
+  { 1178, 1833, 16, 376, 512, 181 },
+  { 26, 1790, 16, 333, 720, 194 },
+  { 161, 1751, 16, 294, 1186, 205 },
+  { 304, 1712, 16, 294, 1186, 205 },
+  { 427, 1673, 16, 294, 1186, 205 },
+  { 546, 1634, 16, 294, 1186, 205 },
+  { 668, 1595, 16, 294, 1186, 205 },
+  { 266, 783, 16, 16, 8946, 5 },
+  { 506, 786, 16, 16, 8946, 5 },
+  { 750, 789, 16, 16, 8946, 5 },
+  { 970, 792, 16, 16, 8946, 5 },
+  { 1190, 795, 16, 16, 8946, 5 },
+  { 175, 798, 16, 16, 8946, 5 },
+  { 1248, 4074, 16, 16, 17808, 2 },
+  { 369, 1508, 1110, 63, 1570, 28 },
+  { 485, 4164, 2506, 63, 1570, 28 },
+  { 614, 1495, 778, 63, 1570, 28 },
+  { 729, 4151, 770, 63, 1570, 28 },
+  { 846, 1482, 317, 63, 1570, 28 },
+  { 949, 4138, 660, 63, 1570, 28 },
+  { 1066, 1469, 308, 63, 1570, 28 },
+  { 1169, 4125, 654, 63, 1570, 28 },
+  { 16, 1456, 302, 63, 1570, 28 },
+  { 137, 4112, 648, 63, 1570, 28 },
+  { 292, 1443, 296, 63, 1570, 28 },
+  { 415, 4099, 642, 63, 1570, 28 },
+  { 534, 1430, 290, 63, 1570, 28 },
+  { 656, 4086, 636, 63, 1570, 28 },
+  { 779, 1419, 284, 52, 1680, 42 },
+  { 889, 4077, 630, 43, 1872, 48 },
+  { 999, 1412, 278, 36, 2401, 53 },
+  { 1109, 4067, 624, 36, 2401, 53 },
+  { 67, 1405, 272, 36, 2401, 53 },
+  { 187, 4060, 618, 36, 2401, 53 },
+  { 347, 1398, 266, 36, 2401, 53 },
+  { 463, 4053, 612, 36, 2401, 53 },
+  { 586, 1391, 260, 36, 2401, 53 },
+  { 704, 4046, 606, 36, 2401, 53 },
+  { 815, 1384, 254, 36, 2401, 53 },
+  { 921, 4039, 600, 36, 2401, 53 },
+  { 1035, 1377, 765, 36, 2401, 53 },
+  { 1141, 4032, 2450, 36, 2401, 53 },
+  { 103, 1370, 2469, 36, 2401, 53 },
+  { 219, 4025, 1104, 36, 2401, 53 },
+  { 602, 1023, 4013, 212, 5314, 92 },
+  { 720, 1011, 3953, 212, 5314, 92 },
+  { 834, 999, 4002, 212, 5314, 92 },
+  { 940, 987, 3909, 212, 5314, 92 },
+  { 1054, 975, 3909, 212, 5314, 92 },
+  { 1160, 963, 3798, 212, 5314, 92 },
+  { 3, 951, 3798, 212, 5314, 92 },
+  { 151, 939, 3677, 212, 5314, 92 },
+  { 278, 927, 3677, 212, 5314, 92 },
+  { 404, 915, 3557, 212, 5314, 92 },
+  { 518, 903, 3557, 212, 5314, 92 },
+  { 644, 891, 3437, 212, 5314, 92 },
+  { 763, 1067, 3437, 202, 17458, 99 },
+  { 877, 1057, 3317, 202, 13378, 99 },
+  { 983, 1049, 3317, 194, 14178, 105 },
+  { 1097, 1041, 3221, 194, 13650, 105 },
+  { 51, 1035, 3221, 188, 14001, 110 },
+  { 203, 1035, 3126, 188, 14001, 110 },
+  { 331, 1035, 3126, 188, 14001, 110 },
+  { 451, 1035, 3056, 188, 14001, 110 },
+  { 570, 1035, 3056, 188, 14001, 110 },
+  { 692, 1035, 2986, 188, 14001, 110 },
+  { 799, 1035, 2986, 188, 14001, 110 },
+  { 909, 1035, 2916, 188, 14001, 110 },
+  { 1019, 1035, 2916, 188, 14001, 110 },
+  { 1129, 1035, 2827, 188, 14001, 110 },
+  { 87, 1035, 2850, 188, 14001, 110 },
+  { 235, 1035, 2789, 188, 14001, 110 },
+  { 831, 2672, 4014, 276, 5170, 114 },
+  { 937, 2654, 3951, 276, 5170, 114 },
+  { 1051, 2636, 3951, 276, 5170, 114 },
+  { 1157, 2618, 3842, 276, 5170, 114 },
+  { 0, 2600, 3842, 276, 5170, 114 },
+  { 148, 2582, 3721, 276, 5170, 114 },
+  { 275, 2564, 3721, 276, 5170, 114 },
+  { 401, 2546, 3620, 276, 5170, 114 },
+  { 515, 2528, 3620, 276, 5170, 114 },
+  { 641, 2510, 3500, 276, 5170, 114 },
+  { 759, 2768, 3500, 260, 17330, 123 },
+  { 873, 2752, 3380, 260, 13250, 123 },
+  { 979, 2738, 3380, 246, 14066, 131 },
+  { 1093, 2724, 3260, 246, 13538, 131 },
+  { 47, 2712, 3260, 234, 13906, 138 },
+  { 199, 2700, 3165, 234, 13730, 138 },
+  { 327, 2690, 3165, 224, 13825, 144 },
+  { 447, 2690, 3094, 224, 13825, 144 },
+  { 566, 2690, 3094, 224, 13825, 144 },
+  { 688, 2690, 3024, 224, 13825, 144 },
+  { 795, 2690, 3024, 224, 13825, 144 },
+  { 905, 2690, 2954, 224, 13825, 144 },
+  { 1015, 2690, 2954, 224, 13825, 144 },
+  { 1125, 2690, 2851, 224, 13825, 144 },
+  { 83, 2690, 2851, 224, 13825, 144 },
+  { 231, 2690, 2790, 224, 13825, 144 },
+  { 372, 360, 2504, 22, 1956, 11 },
+  { 617, 388, 583, 22, 1956, 11 },
+  { 849, 416, 756, 22, 1956, 11 },
+  { 1069, 444, 747, 22, 1956, 11 },
   { 19, 472, 738, 22, 1956, 11 },
-  { 293, 500, 729, 22, 1956, 11 },
-  { 535, 528, 720, 22, 1956, 11 },
-  { 780, 3839, 711, 3, 2336, 16 },
-  { 1000, 562, 702, 0, 8898, 20 },
+  { 296, 500, 729, 22, 1956, 11 },
+  { 538, 528, 720, 22, 1956, 11 },
+  { 783, 3718, 711, 3, 2336, 16 },
+  { 1003, 562, 702, 0, 8898, 20 },
   { 71, 565, 693, 0, 8898, 20 },
-  { 348, 568, 684, 0, 8898, 20 },
-  { 587, 571, 675, 0, 8898, 20 },
-  { 816, 574, 666, 0, 8898, 20 },
-  { 1036, 577, 2460, 0, 8898, 20 },
-  { 107, 580, 2468, 0, 8898, 20 },
-  { 608, 2343, 2488, 148, 900, 57 },
-  { 840, 2323, 588, 148, 900, 57 },
-  { 1060, 2303, 588, 148, 900, 57 },
-  { 13, 2283, 588, 148, 900, 57 },
-  { 286, 2263, 588, 148, 900, 57 },
-  { 527, 2243, 588, 148, 900, 57 },
-  { 772, 2225, 588, 130, 1328, 66 },
-  { 992, 2211, 588, 116, 1776, 81 },
-  { 63, 1588, 588, 104, 2034, 87 },
-  { 340, 1576, 588, 104, 2034, 87 },
-  { 579, 1564, 588, 104, 2034, 87 },
-  { 808, 1552, 588, 104, 2034, 87 },
-  { 1028, 1540, 588, 104, 2034, 87 },
-  { 99, 1528, 2382, 104, 2034, 87 },
+  { 351, 568, 684, 0, 8898, 20 },
+  { 590, 571, 675, 0, 8898, 20 },
+  { 819, 574, 666, 0, 8898, 20 },
+  { 1039, 577, 2455, 0, 8898, 20 },
+  { 107, 580, 2463, 0, 8898, 20 },
+  { 611, 2338, 2483, 148, 900, 57 },
+  { 843, 2318, 588, 148, 900, 57 },
+  { 1063, 2298, 588, 148, 900, 57 },
+  { 13, 2278, 588, 148, 900, 57 },
+  { 289, 2258, 588, 148, 900, 57 },
+  { 530, 2238, 588, 148, 900, 57 },
+  { 775, 2220, 588, 130, 1328, 66 },
+  { 995, 2206, 588, 116, 1776, 81 },
+  { 63, 1583, 588, 104, 2034, 87 },
+  { 343, 1571, 588, 104, 2034, 87 },
+  { 582, 1559, 588, 104, 2034, 87 },
+  { 811, 1547, 588, 104, 2034, 87 },
+  { 1031, 1535, 588, 104, 2034, 87 },
+  { 99, 1523, 2377, 104, 2034, 87 },
 };
 
   // HPR Register Class...
   static const MCPhysReg HPR[] = {
-    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31,
-  };
-  // HPR Bit set.
-  static const uint8_t HPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
-  };
-  // SPR Register Class...
-  static const MCPhysReg SPR[] = {
-    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31,
-  };
-  // SPR Bit set.
-  static const uint8_t SPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
-  };
-  // GPR Register Class...
-  static const MCPhysReg GPR[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
-  };
-  // GPR Bit set.
-  static const uint8_t GPRBits[] = {
-    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
-  };
-  // GPRwithAPSR Register Class...
-  static const MCPhysReg GPRwithAPSR[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV,
-  };
-  // GPRwithAPSR Bit set.
-  static const uint8_t GPRwithAPSRBits[] = {
-    0x04, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
-  };
-  // SPR_8 Register Class...
-  static const MCPhysReg SPR_8[] = {
-    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15,
-  };
-  // SPR_8 Bit set.
-  static const uint8_t SPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
-  };
-  // GPRnopc Register Class...
-  static const MCPhysReg GPRnopc[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
-  };
-  // GPRnopc Bit set.
-  static const uint8_t GPRnopcBits[] = {
-    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
-  };
-  // rGPR Register Class...
-  static const MCPhysReg rGPR[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR,
-  };
-  // rGPR Bit set.
-  static const uint8_t rGPRBits[] = {
-    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f,
-  };
-  // tGPRwithpc Register Class...
-  static const MCPhysReg tGPRwithpc[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC,
-  };
-  // tGPRwithpc Bit set.
-  static const uint8_t tGPRwithpcBits[] = {
-    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
-  };
-  // hGPR Register Class...
-  static const MCPhysReg hGPR[] = {
-    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
-  };
-  // hGPR Bit set.
-  static const uint8_t hGPRBits[] = {
-    0x00, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
-  };
-  // tGPR Register Class...
-  static const MCPhysReg tGPR[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7,
-  };
-  // tGPR Bit set.
-  static const uint8_t tGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
-  };
-  // GPRnopc_and_hGPR Register Class...
-  static const MCPhysReg GPRnopc_and_hGPR[] = {
-    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
-  };
-  // GPRnopc_and_hGPR Bit set.
-  static const uint8_t GPRnopc_and_hGPRBits[] = {
-    0x00, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
-  };
-  // hGPR_and_rGPR Register Class...
-  static const MCPhysReg hGPR_and_rGPR[] = {
-    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR,
-  };
-  // hGPR_and_rGPR Bit set.
-  static const uint8_t hGPR_and_rGPRBits[] = {
-    0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c,
-  };
-  // tcGPR Register Class...
-  static const MCPhysReg tcGPR[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12,
-  };
-  // tcGPR Bit set.
-  static const uint8_t tcGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x40,
-  };
-  // tGPR_and_tcGPR Register Class...
-  static const MCPhysReg tGPR_and_tcGPR[] = {
-    ARM_R0, ARM_R1, ARM_R2, ARM_R3,
-  };
-  // tGPR_and_tcGPR Bit set.
-  static const uint8_t tGPR_and_tcGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
-  };
-  // CCR Register Class...
-  static const MCPhysReg CCR[] = {
-    ARM_CPSR,
-  };
-  // CCR Bit set.
-  static const uint8_t CCRBits[] = {
-    0x08,
-  };
-  // GPRsp Register Class...
-  static const MCPhysReg GPRsp[] = {
-    ARM_SP,
-  };
-  // GPRsp Bit set.
-  static const uint8_t GPRspBits[] = {
-    0x00, 0x10,
-  };
-  // hGPR_and_tGPRwithpc Register Class...
-  static const MCPhysReg hGPR_and_tGPRwithpc[] = {
-    ARM_PC,
-  };
-  // hGPR_and_tGPRwithpc Bit set.
-  static const uint8_t hGPR_and_tGPRwithpcBits[] = {
-    0x00, 0x08,
-  };
-  // hGPR_and_tcGPR Register Class...
-  static const MCPhysReg hGPR_and_tcGPR[] = {
-    ARM_R12,
-  };
-  // hGPR_and_tcGPR Bit set.
-  static const uint8_t hGPR_and_tcGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
-  };
-  // DPR Register Class...
-  static const MCPhysReg DPR[] = {
-    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31,
-  };
-  // DPR Bit set.
-  static const uint8_t DPRBits[] = {
-    0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
-  };
-  // DPR_VFP2 Register Class...
-  static const MCPhysReg DPR_VFP2[] = {
-    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15,
-  };
-  // DPR_VFP2 Bit set.
-  static const uint8_t DPR_VFP2Bits[] = {
-    0x00, 0xc0, 0xff, 0x3f,
-  };
-  // DPR_8 Register Class...
-  static const MCPhysReg DPR_8[] = {
-    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7,
-  };
-  // DPR_8 Bit set.
-  static const uint8_t DPR_8Bits[] = {
-    0x00, 0xc0, 0x3f,
-  };
-  // GPRPair Register Class...
-  static const MCPhysReg GPRPair[] = {
-    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP,
-  };
-  // GPRPair Bit set.
-  static const uint8_t GPRPairBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
-  };
-  // GPRPair_with_gsub_1_in_rGPR Register Class...
-  static const MCPhysReg GPRPair_with_gsub_1_in_rGPR[] = {
-    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11,
-  };
-  // GPRPair_with_gsub_1_in_rGPR Bit set.
-  static const uint8_t GPRPair_with_gsub_1_in_rGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
-  };
-  // GPRPair_with_gsub_0_in_tGPR Register Class...
-  static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
-    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7,
-  };
-  // GPRPair_with_gsub_0_in_tGPR Bit set.
-  static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
-  };
-  // GPRPair_with_gsub_0_in_hGPR Register Class...
-  static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
-    ARM_R8_R9, ARM_R10_R11, ARM_R12_SP,
-  };
-  // GPRPair_with_gsub_0_in_hGPR Bit set.
-  static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc2,
-  };
-  // GPRPair_with_gsub_0_in_tcGPR Register Class...
-  static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
-    ARM_R0_R1, ARM_R2_R3, ARM_R12_SP,
-  };
-  // GPRPair_with_gsub_0_in_tcGPR Bit set.
-  static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
-  };
-  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Register Class...
-  static const MCPhysReg GPRPair_with_gsub_1_in_hGPR_and_rGPR[] = {
-    ARM_R8_R9, ARM_R10_R11,
-  };
-  // GPRPair_with_gsub_1_in_hGPR_and_rGPR Bit set.
-  static const uint8_t GPRPair_with_gsub_1_in_hGPR_and_rGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0,
-  };
-  // GPRPair_with_gsub_1_in_tcGPR Register Class...
-  static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
-    ARM_R0_R1, ARM_R2_R3,
-  };
-  // GPRPair_with_gsub_1_in_tcGPR Bit set.
-  static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
-  };
-  // GPRPair_with_gsub_1_in_GPRsp Register Class...
-  static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
-    ARM_R12_SP,
-  };
-  // GPRPair_with_gsub_1_in_GPRsp Bit set.
-  static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
-  };
-  // DPairSpc Register Class...
-  static const MCPhysReg DPairSpc[] = {
-    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31,
-  };
-  // DPairSpc Bit set.
-  static const uint8_t DPairSpcBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
-  };
-  // DPairSpc_with_ssub_0 Register Class...
-  static const MCPhysReg DPairSpc_with_ssub_0[] = {
-    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
-  };
-  // DPairSpc_with_ssub_0 Bit set.
-  static const uint8_t DPairSpc_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
-  };
-  // DPairSpc_with_ssub_4 Register Class...
-  static const MCPhysReg DPairSpc_with_ssub_4[] = {
-    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15,
-  };
-  // DPairSpc_with_ssub_4 Bit set.
-  static const uint8_t DPairSpc_with_ssub_4Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
-  };
-  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
-    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9,
-  };
-  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
-  };
-  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
-  static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
-    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7,
-  };
-  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
-  static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
-  };
-  // DPair Register Class...
-  static const MCPhysReg DPair[] = {
-    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15,
-  };
-  // DPair Bit set.
-  static const uint8_t DPairBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
-  };
-  // DPair_with_ssub_0 Register Class...
-  static const MCPhysReg DPair_with_ssub_0[] = {
-    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16,
-  };
-  // DPair_with_ssub_0 Bit set.
-  static const uint8_t DPair_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
-  };
-  // QPR Register Class...
-  static const MCPhysReg QPR[] = {
-    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15,
-  };
-  // QPR Bit set.
-  static const uint8_t QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
-  };
-  // DPair_with_ssub_2 Register Class...
-  static const MCPhysReg DPair_with_ssub_2[] = {
-    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7,
-  };
-  // DPair_with_ssub_2 Bit set.
-  static const uint8_t DPair_with_ssub_2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
-  };
-  // DPair_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
-    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8,
-  };
-  // DPair_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
-  };
-  // QPR_VFP2 Register Class...
-  static const MCPhysReg QPR_VFP2[] = {
-    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
-  };
-  // QPR_VFP2 Bit set.
-  static const uint8_t QPR_VFP2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
-  };
-  // DPair_with_dsub_1_in_DPR_8 Register Class...
-  static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
-    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3,
-  };
-  // DPair_with_dsub_1_in_DPR_8 Bit set.
-  static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
-  };
-  // QPR_8 Register Class...
-  static const MCPhysReg QPR_8[] = {
-    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3,
-  };
-  // QPR_8 Bit set.
-  static const uint8_t QPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
-  };
-  // DTriple Register Class...
-  static const MCPhysReg DTriple[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31,
-  };
-  // DTriple Bit set.
-  static const uint8_t DTripleBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x3f,
-  };
-  // DTripleSpc Register Class...
-  static const MCPhysReg DTripleSpc[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31,
-  };
-  // DTripleSpc Bit set.
-  static const uint8_t DTripleSpcBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
-  };
-  // DTripleSpc_with_ssub_0 Register Class...
-  static const MCPhysReg DTripleSpc_with_ssub_0[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19,
-  };
-  // DTripleSpc_with_ssub_0 Bit set.
-  static const uint8_t DTripleSpc_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
-  };
-  // DTriple_with_ssub_0 Register Class...
-  static const MCPhysReg DTriple_with_ssub_0[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17,
-  };
-  // DTriple_with_ssub_0 Bit set.
-  static const uint8_t DTriple_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
-  };
-  // DTriple_with_qsub_0_in_QPR Register Class...
-  static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
-    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30,
-  };
-  // DTriple_with_qsub_0_in_QPR Bit set.
-  static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
-  };
-  // DTriple_with_ssub_2 Register Class...
-  static const MCPhysReg DTriple_with_ssub_2[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16,
-  };
-  // DTriple_with_ssub_2 Bit set.
-  static const uint8_t DTriple_with_ssub_2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x7f,
-  };
-  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31,
-  };
-  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0x2a,
-  };
-  // DTripleSpc_with_ssub_4 Register Class...
-  static const MCPhysReg DTripleSpc_with_ssub_4[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17,
-  };
-  // DTripleSpc_with_ssub_4 Bit set.
-  static const uint8_t DTripleSpc_with_ssub_4Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
-  };
-  // DTriple_with_ssub_4 Register Class...
-  static const MCPhysReg DTriple_with_ssub_4[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15,
-  };
-  // DTriple_with_ssub_4 Bit set.
-  static const uint8_t DTriple_with_ssub_4Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f,
-  };
-  // DTripleSpc_with_ssub_8 Register Class...
-  static const MCPhysReg DTripleSpc_with_ssub_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15,
-  };
-  // DTripleSpc_with_ssub_8 Bit set.
-  static const uint8_t DTripleSpc_with_ssub_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
-  };
-  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11,
-  };
-  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
-  };
-  // DTriple_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9,
-  };
-  // DTriple_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
-  };
-  // DTriple_with_qsub_0_in_QPR_VFP2 Register Class...
-  static const MCPhysReg DTriple_with_qsub_0_in_QPR_VFP2[] = {
-    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16,
-  };
-  // DTriple_with_qsub_0_in_QPR_VFP2 Bit set.
-  static const uint8_t DTriple_with_qsub_0_in_QPR_VFP2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
-  };
-  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17,
-  };
-  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
-  };
-  // DTriple_with_dsub_1_in_DPR_8 Register Class...
-  static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8,
-  };
-  // DTriple_with_dsub_1_in_DPR_8 Bit set.
-  static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
-  };
-  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
-  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
-    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15,
-  };
-  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
-  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
-  };
-  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Register Class...
-  static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR[] = {
-    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14,
-  };
-  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR Bit set.
-  static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
-  };
-  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
-  static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9,
-  };
-  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
-  static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
-  };
-  // DTriple_with_dsub_2_in_DPR_8 Register Class...
-  static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
-    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7,
-  };
-  // DTriple_with_dsub_2_in_DPR_8 Bit set.
-  static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
-  };
-  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
-  static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7,
-  };
-  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
-  static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
-  };
-  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9,
-  };
-  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
-  };
-  // DTriple_with_qsub_0_in_QPR_8 Register Class...
-  static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
-    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8,
-  };
-  // DTriple_with_qsub_0_in_QPR_8 Bit set.
-  static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
-  };
-  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Register Class...
-  static const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR[] = {
-    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6,
-  };
-  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR Bit set.
-  static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
-  };
-  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
-  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
-    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7,
-  };
-  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
-  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
-  };
-  // DQuadSpc Register Class...
-  static const MCPhysReg DQuadSpc[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31,
-  };
-  // DQuadSpc Bit set.
-  static const uint8_t DQuadSpcBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x03,
-  };
-  // DQuadSpc_with_ssub_0 Register Class...
-  static const MCPhysReg DQuadSpc_with_ssub_0[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19,
-  };
-  // DQuadSpc_with_ssub_0 Bit set.
-  static const uint8_t DQuadSpc_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
-  };
-  // DQuadSpc_with_ssub_4 Register Class...
-  static const MCPhysReg DQuadSpc_with_ssub_4[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17,
-  };
-  // DQuadSpc_with_ssub_4 Bit set.
-  static const uint8_t DQuadSpc_with_ssub_4Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
-  };
-  // DQuadSpc_with_ssub_8 Register Class...
-  static const MCPhysReg DQuadSpc_with_ssub_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15,
-  };
-  // DQuadSpc_with_ssub_8 Bit set.
-  static const uint8_t DQuadSpc_with_ssub_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03,
-  };
-  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11,
-  };
-  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
-  };
-  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
-  static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9,
-  };
-  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
-  static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
-  };
-  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
-  static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
-    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7,
-  };
-  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
-  static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03,
-  };
-  // DQuad Register Class...
-  static const MCPhysReg DQuad[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15,
-  };
-  // DQuad Bit set.
-  static const uint8_t DQuadBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
-  };
-  // DQuad_with_ssub_0 Register Class...
-  static const MCPhysReg DQuad_with_ssub_0[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18,
-  };
-  // DQuad_with_ssub_0 Bit set.
-  static const uint8_t DQuad_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
-  };
-  // DQuad_with_ssub_2 Register Class...
-  static const MCPhysReg DQuad_with_ssub_2[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8,
-  };
-  // DQuad_with_ssub_2 Bit set.
-  static const uint8_t DQuad_with_ssub_2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
-  };
-  // QQPR Register Class...
-  static const MCPhysReg QQPR[] = {
-    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15,
-  };
-  // QQPR Bit set.
-  static const uint8_t QQPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
-  };
-  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30,
-  };
-  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
-  };
-  // DQuad_with_ssub_4 Register Class...
-  static const MCPhysReg DQuad_with_ssub_4[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16,
-  };
-  // DQuad_with_ssub_4 Bit set.
-  static const uint8_t DQuad_with_ssub_4Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
-  };
-  // DQuad_with_ssub_6 Register Class...
-  static const MCPhysReg DQuad_with_ssub_6[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7,
-  };
-  // DQuad_with_ssub_6 Bit set.
-  static const uint8_t DQuad_with_ssub_6Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
-  };
-  // DQuad_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10,
-  };
-  // DQuad_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
-  };
-  // DQuad_with_qsub_0_in_QPR_VFP2 Register Class...
-  static const MCPhysReg DQuad_with_qsub_0_in_QPR_VFP2[] = {
-    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8,
-  };
-  // DQuad_with_qsub_0_in_QPR_VFP2 Bit set.
-  static const uint8_t DQuad_with_qsub_0_in_QPR_VFP2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
-  };
-  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18,
-  };
-  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
-  };
-  // DQuad_with_dsub_1_in_DPR_8 Register Class...
-  static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4,
-  };
-  // DQuad_with_dsub_1_in_DPR_8 Bit set.
-  static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
-  };
-  // DQuad_with_qsub_1_in_QPR_VFP2 Register Class...
-  static const MCPhysReg DQuad_with_qsub_1_in_QPR_VFP2[] = {
-    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7,
-  };
-  // DQuad_with_qsub_1_in_QPR_VFP2 Bit set.
-  static const uint8_t DQuad_with_qsub_1_in_QPR_VFP2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f,
-  };
-  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Register Class...
-  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16,
-  };
-  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2 Bit set.
-  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
-  };
-  // DQuad_with_dsub_2_in_DPR_8 Register Class...
-  static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8,
-  };
-  // DQuad_with_dsub_2_in_DPR_8 Bit set.
-  static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
-  };
-  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14,
-  };
-  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
-  };
-  // DQuad_with_dsub_3_in_DPR_8 Register Class...
-  static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
-    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3,
-  };
-  // DQuad_with_dsub_3_in_DPR_8 Bit set.
-  static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
-  };
-  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10,
-  };
-  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
-  };
-  // DQuad_with_qsub_0_in_QPR_8 Register Class...
-  static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
-    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4,
-  };
-  // DQuad_with_qsub_0_in_QPR_8 Bit set.
-  static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
-  };
-  // DQuad_with_qsub_1_in_QPR_8 Register Class...
-  static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
-    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3,
-  };
-  // DQuad_with_qsub_1_in_QPR_8 Bit set.
-  static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
-  };
-  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
-  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8,
-  };
-  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
-  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
-  };
-  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
-  static const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
-    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6,
-  };
-  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
-  static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
-  };
-  // QQQQPR Register Class...
-  static const MCPhysReg QQQQPR[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15,
-  };
-  // QQQQPR Bit set.
-  static const uint8_t QQQQPRBits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
-  };
-  // QQQQPR_with_ssub_0 Register Class...
-  static const MCPhysReg QQQQPR_with_ssub_0[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10,
-  };
-  // QQQQPR_with_ssub_0 Bit set.
-  static const uint8_t QQQQPR_with_ssub_0Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
-  };
-  // QQQQPR_with_ssub_4 Register Class...
-  static const MCPhysReg QQQQPR_with_ssub_4[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9,
-  };
-  // QQQQPR_with_ssub_4 Bit set.
-  static const uint8_t QQQQPR_with_ssub_4Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
-  };
-  // QQQQPR_with_ssub_8 Register Class...
-  static const MCPhysReg QQQQPR_with_ssub_8[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8,
-  };
-  // QQQQPR_with_ssub_8 Bit set.
-  static const uint8_t QQQQPR_with_ssub_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03,
-  };
-  // QQQQPR_with_ssub_12 Register Class...
-  static const MCPhysReg QQQQPR_with_ssub_12[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7,
-  };
-  // QQQQPR_with_ssub_12 Bit set.
-  static const uint8_t QQQQPR_with_ssub_12Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x01,
-  };
-  // QQQQPR_with_dsub_0_in_DPR_8 Register Class...
-  static const MCPhysReg QQQQPR_with_dsub_0_in_DPR_8[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6,
-  };
-  // QQQQPR_with_dsub_0_in_DPR_8 Bit set.
-  static const uint8_t QQQQPR_with_dsub_0_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
-  };
-  // QQQQPR_with_dsub_2_in_DPR_8 Register Class...
-  static const MCPhysReg QQQQPR_with_dsub_2_in_DPR_8[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5,
-  };
-  // QQQQPR_with_dsub_2_in_DPR_8 Bit set.
-  static const uint8_t QQQQPR_with_dsub_2_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
-  };
-  // QQQQPR_with_dsub_4_in_DPR_8 Register Class...
-  static const MCPhysReg QQQQPR_with_dsub_4_in_DPR_8[] = {
-    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4,
-  };
-  // QQQQPR_with_dsub_4_in_DPR_8 Bit set.
-  static const uint8_t QQQQPR_with_dsub_4_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
-  };
-  // QQQQPR_with_dsub_6_in_DPR_8 Register Class...
-  static const MCPhysReg QQQQPR_with_dsub_6_in_DPR_8[] = {
-    ARM_Q0_Q1_Q2_Q3,
-  };
-  // QQQQPR_with_dsub_6_in_DPR_8 Bit set.
-  static const uint8_t QQQQPR_with_dsub_6_in_DPR_8Bits[] = {
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, 
   };
 
+  // HPR Bit set.
+  static const uint8_t HPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // FPWithVPR Register Class...
+  static const MCPhysReg FPWithVPR[] = {
+    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, ARM_VPR, 
+  };
+
+  // FPWithVPR Bit set.
+  static const uint8_t FPWithVPRBits[] = {
+    0x00, 0x00, 0xf4, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // SPR Register Class...
+  static const MCPhysReg SPR[] = {
+    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, 
+  };
+
+  // SPR Bit set.
+  static const uint8_t SPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
+  };
+
+  // FPWithVPR_with_ssub_0 Register Class...
+  static const MCPhysReg FPWithVPR_with_ssub_0[] = {
+    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, 
+  };
+
+  // FPWithVPR_with_ssub_0 Bit set.
+  static const uint8_t FPWithVPR_with_ssub_0Bits[] = {
+    0x00, 0x00, 0xf0, 0xff, 0x0f, 
+  };
+
+  // GPR Register Class...
+  static const MCPhysReg GPR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, 
+  };
+
+  // GPR Bit set.
+  static const uint8_t GPRBits[] = {
+    0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRwithAPSR Register Class...
+  static const MCPhysReg GPRwithAPSR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV, 
+  };
+
+  // GPRwithAPSR Bit set.
+  static const uint8_t GPRwithAPSRBits[] = {
+    0x04, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRwithZR Register Class...
+  static const MCPhysReg GPRwithZR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_ZR, 
+  };
+
+  // GPRwithZR Bit set.
+  static const uint8_t GPRwithZRBits[] = {
+    0x00, 0x20, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // SPR_8 Register Class...
+  static const MCPhysReg SPR_8[] = {
+    ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, 
+  };
+
+  // SPR_8 Bit set.
+  static const uint8_t SPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
+  };
+
+  // GPRnopc Register Class...
+  static const MCPhysReg GPRnopc[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, 
+  };
+
+  // GPRnopc Bit set.
+  static const uint8_t GPRnopcBits[] = {
+    0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRnosp Register Class...
+  static const MCPhysReg GPRnosp[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_PC, 
+  };
+
+  // GPRnosp Bit set.
+  static const uint8_t GPRnospBits[] = {
+    0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRwithAPSR_NZCVnosp Register Class...
+  static const MCPhysReg GPRwithAPSR_NZCVnosp[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR_NZCV, 
+  };
+
+  // GPRwithAPSR_NZCVnosp Bit set.
+  static const uint8_t GPRwithAPSR_NZCVnospBits[] = {
+    0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRwithAPSRnosp Register Class...
+  static const MCPhysReg GPRwithAPSRnosp[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR, 
+  };
+
+  // GPRwithAPSRnosp Bit set.
+  static const uint8_t GPRwithAPSRnospBits[] = {
+    0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRwithZRnosp Register Class...
+  static const MCPhysReg GPRwithZRnosp[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_ZR, 
+  };
+
+  // GPRwithZRnosp Bit set.
+  static const uint8_t GPRwithZRnospBits[] = {
+    0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRnoip Register Class...
+  static const MCPhysReg GPRnoip[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC, 
+  };
+
+  // GPRnoip Bit set.
+  static const uint8_t GPRnoipBits[] = {
+    0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, 
+  };
+
+  // rGPR Register Class...
+  static const MCPhysReg rGPR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, 
+  };
+
+  // rGPR Bit set.
+  static const uint8_t rGPRBits[] = {
+    0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
+  };
+
+  // GPRnoip_and_GPRnopc Register Class...
+  static const MCPhysReg GPRnoip_and_GPRnopc[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, 
+  };
+
+  // GPRnoip_and_GPRnopc Bit set.
+  static const uint8_t GPRnoip_and_GPRnopcBits[] = {
+    0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, 
+  };
+
+  // GPRnoip_and_GPRnosp Register Class...
+  static const MCPhysReg GPRnoip_and_GPRnosp[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_PC, 
+  };
+
+  // GPRnoip_and_GPRnosp Bit set.
+  static const uint8_t GPRnoip_and_GPRnospBits[] = {
+    0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, 
+  };
+
+  // GPRnoip_and_GPRwithAPSR_NZCVnosp Register Class...
+  static const MCPhysReg GPRnoip_and_GPRwithAPSR_NZCVnosp[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, 
+  };
+
+  // GPRnoip_and_GPRwithAPSR_NZCVnosp Bit set.
+  static const uint8_t GPRnoip_and_GPRwithAPSR_NZCVnospBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, 
+  };
+
+  // tGPRwithpc Register Class...
+  static const MCPhysReg tGPRwithpc[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC, 
+  };
+
+  // tGPRwithpc Bit set.
+  static const uint8_t tGPRwithpcBits[] = {
+    0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
+  };
+
+  // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class...
+  static const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = {
+    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, 
+  };
+
+  // FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set.
+  static const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = {
+    0x00, 0x00, 0xf0, 0x0f, 
+  };
+
+  // hGPR Register Class...
+  static const MCPhysReg hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC, 
+  };
+
+  // hGPR Bit set.
+  static const uint8_t hGPRBits[] = {
+    0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 
+  };
+
+  // tGPR Register Class...
+  static const MCPhysReg tGPR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, 
+  };
+
+  // tGPR Bit set.
+  static const uint8_t tGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
+  };
+
+  // tGPREven Register Class...
+  static const MCPhysReg tGPREven[] = {
+    ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, ARM_R12, ARM_LR, 
+  };
+
+  // tGPREven Bit set.
+  static const uint8_t tGPREvenBits[] = {
+    0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a, 
+  };
+
+  // GPRnopc_and_hGPR Register Class...
+  static const MCPhysReg GPRnopc_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, 
+  };
+
+  // GPRnopc_and_hGPR Bit set.
+  static const uint8_t GPRnopc_and_hGPRBits[] = {
+    0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 
+  };
+
+  // GPRnosp_and_hGPR Register Class...
+  static const MCPhysReg GPRnosp_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_PC, 
+  };
+
+  // GPRnosp_and_hGPR Bit set.
+  static const uint8_t GPRnosp_and_hGPRBits[] = {
+    0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 
+  };
+
+  // GPRnoip_and_hGPR Register Class...
+  static const MCPhysReg GPRnoip_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC, 
+  };
+
+  // GPRnoip_and_hGPR Bit set.
+  static const uint8_t GPRnoip_and_hGPRBits[] = {
+    0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // GPRnoip_and_tGPREven Register Class...
+  static const MCPhysReg GPRnoip_and_tGPREven[] = {
+    ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, 
+  };
+
+  // GPRnoip_and_tGPREven Bit set.
+  static const uint8_t GPRnoip_and_tGPREvenBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x0a, 
+  };
+
+  // GPRnosp_and_GPRnopc_and_hGPR Register Class...
+  static const MCPhysReg GPRnosp_and_GPRnopc_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, 
+  };
+
+  // GPRnosp_and_GPRnopc_and_hGPR Bit set.
+  static const uint8_t GPRnosp_and_GPRnopc_and_hGPRBits[] = {
+    0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 
+  };
+
+  // tGPROdd Register Class...
+  static const MCPhysReg tGPROdd[] = {
+    ARM_R1, ARM_R3, ARM_R5, ARM_R7, ARM_R9, ARM_R11, 
+  };
+
+  // tGPROdd Bit set.
+  static const uint8_t tGPROddBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x15, 
+  };
+
+  // GPRnopc_and_GPRnoip_and_hGPR Register Class...
+  static const MCPhysReg GPRnopc_and_GPRnoip_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, 
+  };
+
+  // GPRnopc_and_GPRnoip_and_hGPR Bit set.
+  static const uint8_t GPRnopc_and_GPRnoip_and_hGPRBits[] = {
+    0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // GPRnosp_and_GPRnoip_and_hGPR Register Class...
+  static const MCPhysReg GPRnosp_and_GPRnoip_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_PC, 
+  };
+
+  // GPRnosp_and_GPRnoip_and_hGPR Bit set.
+  static const uint8_t GPRnosp_and_GPRnoip_and_hGPRBits[] = {
+    0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // tcGPR Register Class...
+  static const MCPhysReg tcGPR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12, 
+  };
+
+  // tcGPR Bit set.
+  static const uint8_t tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x20, 
+  };
+
+  // GPRnoip_and_tcGPR Register Class...
+  static const MCPhysReg GPRnoip_and_tcGPR[] = {
+    ARM_R0, ARM_R1, ARM_R2, ARM_R3, 
+  };
+
+  // GPRnoip_and_tcGPR Bit set.
+  static const uint8_t GPRnoip_and_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Register Class...
+  static const MCPhysReg GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR[] = {
+    ARM_R8, ARM_R9, ARM_R10, ARM_R11, 
+  };
+
+  // GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Bit set.
+  static const uint8_t GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // hGPR_and_tGPREven Register Class...
+  static const MCPhysReg hGPR_and_tGPREven[] = {
+    ARM_R8, ARM_R10, ARM_R12, ARM_LR, 
+  };
+
+  // hGPR_and_tGPREven Bit set.
+  static const uint8_t hGPR_and_tGPREvenBits[] = {
+    0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a, 
+  };
+
+  // tGPR_and_tGPREven Register Class...
+  static const MCPhysReg tGPR_and_tGPREven[] = {
+    ARM_R0, ARM_R2, ARM_R4, ARM_R6, 
+  };
+
+  // tGPR_and_tGPREven Bit set.
+  static const uint8_t tGPR_and_tGPREvenBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
+  };
+
+  // tGPR_and_tGPROdd Register Class...
+  static const MCPhysReg tGPR_and_tGPROdd[] = {
+    ARM_R1, ARM_R3, ARM_R5, ARM_R7, 
+  };
+
+  // tGPR_and_tGPROdd Bit set.
+  static const uint8_t tGPR_and_tGPROddBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01, 
+  };
+
+  // tGPREven_and_tcGPR Register Class...
+  static const MCPhysReg tGPREven_and_tcGPR[] = {
+    ARM_R0, ARM_R2, ARM_R12, 
+  };
+
+  // tGPREven_and_tcGPR Bit set.
+  static const uint8_t tGPREven_and_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x20, 
+  };
+
+  // hGPR_and_GPRnoip_and_tGPREven Register Class...
+  static const MCPhysReg hGPR_and_GPRnoip_and_tGPREven[] = {
+    ARM_R8, ARM_R10, 
+  };
+
+  // hGPR_and_GPRnoip_and_tGPREven Bit set.
+  static const uint8_t hGPR_and_GPRnoip_and_tGPREvenBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 
+  };
+
+  // hGPR_and_tGPROdd Register Class...
+  static const MCPhysReg hGPR_and_tGPROdd[] = {
+    ARM_R9, ARM_R11, 
+  };
+
+  // hGPR_and_tGPROdd Bit set.
+  static const uint8_t hGPR_and_tGPROddBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 
+  };
+
+  // tGPREven_and_GPRnoip_and_tcGPR Register Class...
+  static const MCPhysReg tGPREven_and_GPRnoip_and_tcGPR[] = {
+    ARM_R0, ARM_R2, 
+  };
+
+  // tGPREven_and_GPRnoip_and_tcGPR Bit set.
+  static const uint8_t tGPREven_and_GPRnoip_and_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 
+  };
+
+  // tGPROdd_and_tcGPR Register Class...
+  static const MCPhysReg tGPROdd_and_tcGPR[] = {
+    ARM_R1, ARM_R3, 
+  };
+
+  // tGPROdd_and_tcGPR Bit set.
+  static const uint8_t tGPROdd_and_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 
+  };
+
+  // CCR Register Class...
+  static const MCPhysReg CCR[] = {
+    ARM_CPSR, 
+  };
+
+  // CCR Bit set.
+  static const uint8_t CCRBits[] = {
+    0x08, 
+  };
+
+  // FPCXTRegs Register Class...
+  static const MCPhysReg FPCXTRegs[] = {
+    ARM_FPCXTNS, 
+  };
+
+  // FPCXTRegs Bit set.
+  static const uint8_t FPCXTRegsBits[] = {
+    0x10, 
+  };
+
+  // GPRlr Register Class...
+  static const MCPhysReg GPRlr[] = {
+    ARM_LR, 
+  };
+
+  // GPRlr Bit set.
+  static const uint8_t GPRlrBits[] = {
+    0x00, 0x20, 
+  };
+
+  // GPRsp Register Class...
+  static const MCPhysReg GPRsp[] = {
+    ARM_SP, 
+  };
+
+  // GPRsp Bit set.
+  static const uint8_t GPRspBits[] = {
+    0x00, 0x00, 0x01, 
+  };
+
+  // VCCR Register Class...
+  static const MCPhysReg VCCR[] = {
+    ARM_VPR, 
+  };
+
+  // VCCR Bit set.
+  static const uint8_t VCCRBits[] = {
+    0x00, 0x00, 0x04, 
+  };
+
+  // cl_FPSCR_NZCV Register Class...
+  static const MCPhysReg cl_FPSCR_NZCV[] = {
+    ARM_FPSCR_NZCV, 
+  };
+
+  // cl_FPSCR_NZCV Bit set.
+  static const uint8_t cl_FPSCR_NZCVBits[] = {
+    0x00, 0x02, 
+  };
+
+  // hGPR_and_tGPRwithpc Register Class...
+  static const MCPhysReg hGPR_and_tGPRwithpc[] = {
+    ARM_PC, 
+  };
+
+  // hGPR_and_tGPRwithpc Bit set.
+  static const uint8_t hGPR_and_tGPRwithpcBits[] = {
+    0x00, 0x40, 
+  };
+
+  // hGPR_and_tcGPR Register Class...
+  static const MCPhysReg hGPR_and_tcGPR[] = {
+    ARM_R12, 
+  };
+
+  // hGPR_and_tcGPR Bit set.
+  static const uint8_t hGPR_and_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
+  };
+
+  // DPR Register Class...
+  static const MCPhysReg DPR[] = {
+    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, 
+  };
+
+  // DPR Bit set.
+  static const uint8_t DPRBits[] = {
+    0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
+  };
+
+  // DPR_VFP2 Register Class...
+  static const MCPhysReg DPR_VFP2[] = {
+    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, 
+  };
+
+  // DPR_VFP2 Bit set.
+  static const uint8_t DPR_VFP2Bits[] = {
+    0x00, 0x00, 0xf0, 0xff, 0x0f, 
+  };
+
+  // DPR_8 Register Class...
+  static const MCPhysReg DPR_8[] = {
+    ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, 
+  };
+
+  // DPR_8 Bit set.
+  static const uint8_t DPR_8Bits[] = {
+    0x00, 0x00, 0xf0, 0x0f, 
+  };
+
+  // GPRPair Register Class...
+  static const MCPhysReg GPRPair[] = {
+    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, 
+  };
+
+  // GPRPair Bit set.
+  static const uint8_t GPRPairBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f, 
+  };
+
+  // GPRPairnosp Register Class...
+  static const MCPhysReg GPRPairnosp[] = {
+    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, 
+  };
+
+  // GPRPairnosp Bit set.
+  static const uint8_t GPRPairnospBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 
+  };
+
+  // GPRPair_with_gsub_0_in_tGPR Register Class...
+  static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
+    ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, 
+  };
+
+  // GPRPair_with_gsub_0_in_tGPR Bit set.
+  static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 
+  };
+
+  // GPRPair_with_gsub_0_in_hGPR Register Class...
+  static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
+    ARM_R8_R9, ARM_R10_R11, ARM_R12_SP, 
+  };
+
+  // GPRPair_with_gsub_0_in_hGPR Bit set.
+  static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
+  };
+
+  // GPRPair_with_gsub_0_in_tcGPR Register Class...
+  static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
+    ARM_R0_R1, ARM_R2_R3, ARM_R12_SP, 
+  };
+
+  // GPRPair_with_gsub_0_in_tcGPR Bit set.
+  static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43, 
+  };
+
+  // GPRPair_with_gsub_1_in_tcGPR Register Class...
+  static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
+    ARM_R0_R1, ARM_R2_R3, 
+  };
+
+  // GPRPair_with_gsub_1_in_tcGPR Bit set.
+  static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  };
+
+  // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class...
+  static const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = {
+    ARM_R8_R9, ARM_R10_R11, 
+  };
+
+  // GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set.
+  static const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
+  };
+
+  // GPRPair_with_gsub_1_in_GPRsp Register Class...
+  static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
+    ARM_R12_SP, 
+  };
+
+  // GPRPair_with_gsub_1_in_GPRsp Bit set.
+  static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
+  };
+
+  // DPairSpc Register Class...
+  static const MCPhysReg DPairSpc[] = {
+    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31, 
+  };
+
+  // DPairSpc Bit set.
+  static const uint8_t DPairSpcBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, 
+  };
+
+  // DPairSpc_with_ssub_0 Register Class...
+  static const MCPhysReg DPairSpc_with_ssub_0[] = {
+    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, 
+  };
+
+  // DPairSpc_with_ssub_0 Bit set.
+  static const uint8_t DPairSpc_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
+  };
+
+  // DPairSpc_with_ssub_4 Register Class...
+  static const MCPhysReg DPairSpc_with_ssub_4[] = {
+    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, 
+  };
+
+  // DPairSpc_with_ssub_4 Bit set.
+  static const uint8_t DPairSpc_with_ssub_4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 
+  };
+
+  // DPairSpc_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
+    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, 
+  };
+
+  // DPairSpc_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
+  };
+
+  // DPairSpc_with_dsub_2_in_DPR_8 Register Class...
+  static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
+    ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, 
+  };
+
+  // DPairSpc_with_dsub_2_in_DPR_8 Bit set.
+  static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 
+  };
+
+  // DPair Register Class...
+  static const MCPhysReg DPair[] = {
+    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15, 
+  };
+
+  // DPair Bit set.
+  static const uint8_t DPairBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, 
+  };
+
+  // DPair_with_ssub_0 Register Class...
+  static const MCPhysReg DPair_with_ssub_0[] = {
+    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, 
+  };
+
+  // DPair_with_ssub_0 Bit set.
+  static const uint8_t DPair_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
+  };
+
+  // QPR Register Class...
+  static const MCPhysReg QPR[] = {
+    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 
+  };
+
+  // QPR Bit set.
+  static const uint8_t QPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 
+  };
+
+  // DPair_with_ssub_2 Register Class...
+  static const MCPhysReg DPair_with_ssub_2[] = {
+    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, 
+  };
+
+  // DPair_with_ssub_2 Bit set.
+  static const uint8_t DPair_with_ssub_2Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
+  };
+
+  // DPair_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
+    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, 
+  };
+
+  // DPair_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
+  };
+
+  // MQPR Register Class...
+  static const MCPhysReg MQPR[] = {
+    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, 
+  };
+
+  // MQPR Bit set.
+  static const uint8_t MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
+  };
+
+  // QPR_VFP2 Register Class...
+  static const MCPhysReg QPR_VFP2[] = {
+    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, 
+  };
+
+  // QPR_VFP2 Bit set.
+  static const uint8_t QPR_VFP2Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
+  };
+
+  // DPair_with_dsub_1_in_DPR_8 Register Class...
+  static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
+    ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, 
+  };
+
+  // DPair_with_dsub_1_in_DPR_8 Bit set.
+  static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
+  };
+
+  // QPR_8 Register Class...
+  static const MCPhysReg QPR_8[] = {
+    ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, 
+  };
+
+  // QPR_8 Bit set.
+  static const uint8_t QPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
+  };
+
+  // DTriple Register Class...
+  static const MCPhysReg DTriple[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31, 
+  };
+
+  // DTriple Bit set.
+  static const uint8_t DTripleBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, 
+  };
+
+  // DTripleSpc Register Class...
+  static const MCPhysReg DTripleSpc[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, 
+  };
+
+  // DTripleSpc Bit set.
+  static const uint8_t DTripleSpcBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // DTripleSpc_with_ssub_0 Register Class...
+  static const MCPhysReg DTripleSpc_with_ssub_0[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, 
+  };
+
+  // DTripleSpc_with_ssub_0 Bit set.
+  static const uint8_t DTripleSpc_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
+  };
+
+  // DTriple_with_ssub_0 Register Class...
+  static const MCPhysReg DTriple_with_ssub_0[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, 
+  };
+
+  // DTriple_with_ssub_0 Bit set.
+  static const uint8_t DTriple_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
+  };
+
+  // DTriple_with_qsub_0_in_QPR Register Class...
+  static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
+    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30, 
+  };
+
+  // DTriple_with_qsub_0_in_QPR Bit set.
+  static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x0a, 
+  };
+
+  // DTriple_with_ssub_2 Register Class...
+  static const MCPhysReg DTriple_with_ssub_2[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, 
+  };
+
+  // DTriple_with_ssub_2 Bit set.
+  static const uint8_t DTriple_with_ssub_2Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, 
+  };
+
+  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
+  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
+    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31, 
+  };
+
+  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
+  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15, 
+  };
+
+  // DTripleSpc_with_ssub_4 Register Class...
+  static const MCPhysReg DTripleSpc_with_ssub_4[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, 
+  };
+
+  // DTripleSpc_with_ssub_4 Bit set.
+  static const uint8_t DTripleSpc_with_ssub_4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
+  };
+
+  // DTriple_with_ssub_4 Register Class...
+  static const MCPhysReg DTriple_with_ssub_4[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, 
+  };
+
+  // DTriple_with_ssub_4 Bit set.
+  static const uint8_t DTriple_with_ssub_4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f, 
+  };
+
+  // DTripleSpc_with_ssub_8 Register Class...
+  static const MCPhysReg DTripleSpc_with_ssub_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, 
+  };
+
+  // DTripleSpc_with_ssub_8 Bit set.
+  static const uint8_t DTripleSpc_with_ssub_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01, 
+  };
+
+  // DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, 
+  };
+
+  // DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+  // DTriple_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, 
+  };
+
+  // DTriple_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 
+  };
+
+  // DTriple_with_qsub_0_in_MQPR Register Class...
+  static const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = {
+    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, 
+  };
+
+  // DTriple_with_qsub_0_in_MQPR Bit set.
+  static const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a, 
+  };
+
+  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
+  static const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
+    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, 
+  };
+
+  // DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
+  static const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 
+  };
+
+  // DTriple_with_dsub_1_in_DPR_8 Register Class...
+  static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, 
+  };
+
+  // DTriple_with_dsub_1_in_DPR_8 Bit set.
+  static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 
+  };
+
+  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
+  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
+    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, 
+  };
+
+  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
+  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15, 
+  };
+
+  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class...
+  static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = {
+    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, 
+  };
+
+  // DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set.
+  static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a, 
+  };
+
+  // DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
+  static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, 
+  };
+
+  // DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
+  static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
+  };
+
+  // DTriple_with_dsub_2_in_DPR_8 Register Class...
+  static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
+    ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, 
+  };
+
+  // DTriple_with_dsub_2_in_DPR_8 Bit set.
+  static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 
+  };
+
+  // DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
+  static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, 
+  };
+
+  // DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
+  static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
+  };
+
+  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
+  static const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
+    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, 
+  };
+
+  // DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
+  static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 
+  };
+
+  // DTriple_with_qsub_0_in_QPR_8 Register Class...
+  static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
+    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, 
+  };
+
+  // DTriple_with_qsub_0_in_QPR_8 Bit set.
+  static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a, 
+  };
+
+  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Register Class...
+  static const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = {
+    ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, 
+  };
+
+  // DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Bit set.
+  static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, 
+  };
+
+  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
+  static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
+    ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, 
+  };
+
+  // DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
+  static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 
+  };
+
+  // DQuadSpc Register Class...
+  static const MCPhysReg DQuadSpc[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31, 
+  };
+
+  // DQuadSpc Bit set.
+  static const uint8_t DQuadSpcBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01, 
+  };
+
+  // DQuadSpc_with_ssub_0 Register Class...
+  static const MCPhysReg DQuadSpc_with_ssub_0[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, 
+  };
+
+  // DQuadSpc_with_ssub_0 Bit set.
+  static const uint8_t DQuadSpc_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, 
+  };
+
+  // DQuadSpc_with_ssub_4 Register Class...
+  static const MCPhysReg DQuadSpc_with_ssub_4[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, 
+  };
+
+  // DQuadSpc_with_ssub_4 Bit set.
+  static const uint8_t DQuadSpc_with_ssub_4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
+  };
+
+  // DQuadSpc_with_ssub_8 Register Class...
+  static const MCPhysReg DQuadSpc_with_ssub_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, 
+  };
+
+  // DQuadSpc_with_ssub_8 Bit set.
+  static const uint8_t DQuadSpc_with_ssub_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01, 
+  };
+
+  // DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, 
+  };
+
+  // DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, 
+  };
+
+  // DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
+  static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, 
+  };
+
+  // DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
+  static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 
+  };
+
+  // DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
+  static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
+    ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, 
+  };
+
+  // DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
+  static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
+  };
+
+  // DQuad Register Class...
+  static const MCPhysReg DQuad[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15, 
+  };
+
+  // DQuad Bit set.
+  static const uint8_t DQuadBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 
+  };
+
+  // DQuad_with_ssub_0 Register Class...
+  static const MCPhysReg DQuad_with_ssub_0[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, 
+  };
+
+  // DQuad_with_ssub_0 Bit set.
+  static const uint8_t DQuad_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
+  };
+
+  // DQuad_with_ssub_2 Register Class...
+  static const MCPhysReg DQuad_with_ssub_2[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, 
+  };
+
+  // DQuad_with_ssub_2 Bit set.
+  static const uint8_t DQuad_with_ssub_2Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 
+  };
+
+  // QQPR Register Class...
+  static const MCPhysReg QQPR[] = {
+    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15, 
+  };
+
+  // QQPR Bit set.
+  static const uint8_t QQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
+  };
+
+  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
+  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30, 
+  };
+
+  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
+  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 
+  };
+
+  // DQuad_with_ssub_4 Register Class...
+  static const MCPhysReg DQuad_with_ssub_4[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, 
+  };
+
+  // DQuad_with_ssub_4 Bit set.
+  static const uint8_t DQuad_with_ssub_4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 
+  };
+
+  // DQuad_with_ssub_6 Register Class...
+  static const MCPhysReg DQuad_with_ssub_6[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, 
+  };
+
+  // DQuad_with_ssub_6 Bit set.
+  static const uint8_t DQuad_with_ssub_6Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
+  };
+
+  // DQuad_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, 
+  };
+
+  // DQuad_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
+  };
+
+  // DQuad_with_qsub_0_in_MQPR Register Class...
+  static const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = {
+    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, 
+  };
+
+  // DQuad_with_qsub_0_in_MQPR Bit set.
+  static const uint8_t DQuad_with_qsub_0_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 
+  };
+
+  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
+  static const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, 
+  };
+
+  // DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
+  static const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
+  };
+
+  // DQuad_with_dsub_1_in_DPR_8 Register Class...
+  static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, 
+  };
+
+  // DQuad_with_dsub_1_in_DPR_8 Bit set.
+  static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
+  };
+
+  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
+  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, 
+  };
+
+  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
+  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 
+  };
+
+  // MQQPR Register Class...
+  static const MCPhysReg MQQPR[] = {
+    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, 
+  };
+
+  // MQQPR Bit set.
+  static const uint8_t MQQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
+  };
+
+  // DQuad_with_dsub_2_in_DPR_8 Register Class...
+  static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, 
+  };
+
+  // DQuad_with_dsub_2_in_DPR_8 Bit set.
+  static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
+  };
+
+  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
+  static const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, 
+  };
+
+  // DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
+  static const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 
+  };
+
+  // DQuad_with_dsub_3_in_DPR_8 Register Class...
+  static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
+    ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, 
+  };
+
+  // DQuad_with_dsub_3_in_DPR_8 Bit set.
+  static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
+  };
+
+  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
+  static const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, 
+  };
+
+  // DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
+  static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
+  };
+
+  // DQuad_with_qsub_0_in_QPR_8 Register Class...
+  static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
+    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, 
+  };
+
+  // DQuad_with_qsub_0_in_QPR_8 Bit set.
+  static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 
+  };
+
+  // DQuad_with_qsub_1_in_QPR_8 Register Class...
+  static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
+    ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, 
+  };
+
+  // DQuad_with_qsub_1_in_QPR_8 Bit set.
+  static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
+  };
+
+  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
+  static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, 
+  };
+
+  // DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
+  static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
+  };
+
+  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
+  static const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
+    ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, 
+  };
+
+  // DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
+  static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
+  };
+
+  // QQQQPR Register Class...
+  static const MCPhysReg QQQQPR[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15, 
+  };
+
+  // QQQQPR Bit set.
+  static const uint8_t QQQQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 
+  };
+
+  // QQQQPR_with_ssub_0 Register Class...
+  static const MCPhysReg QQQQPR_with_ssub_0[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, 
+  };
+
+  // QQQQPR_with_ssub_0 Bit set.
+  static const uint8_t QQQQPR_with_ssub_0Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
+  };
+
+  // QQQQPR_with_ssub_4 Register Class...
+  static const MCPhysReg QQQQPR_with_ssub_4[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, 
+  };
+
+  // QQQQPR_with_ssub_4 Bit set.
+  static const uint8_t QQQQPR_with_ssub_4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
+  };
+
+  // QQQQPR_with_ssub_8 Register Class...
+  static const MCPhysReg QQQQPR_with_ssub_8[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, 
+  };
+
+  // QQQQPR_with_ssub_8 Bit set.
+  static const uint8_t QQQQPR_with_ssub_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01, 
+  };
+
+  // MQQQQPR Register Class...
+  static const MCPhysReg MQQQQPR[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, 
+  };
+
+  // MQQQQPR Bit set.
+  static const uint8_t MQQQQPRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 
+  };
+
+  // MQQQQPR_with_dsub_0_in_DPR_8 Register Class...
+  static const MCPhysReg MQQQQPR_with_dsub_0_in_DPR_8[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, 
+  };
+
+  // MQQQQPR_with_dsub_0_in_DPR_8 Bit set.
+  static const uint8_t MQQQQPR_with_dsub_0_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
+  };
+
+  // MQQQQPR_with_dsub_2_in_DPR_8 Register Class...
+  static const MCPhysReg MQQQQPR_with_dsub_2_in_DPR_8[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, 
+  };
+
+  // MQQQQPR_with_dsub_2_in_DPR_8 Bit set.
+  static const uint8_t MQQQQPR_with_dsub_2_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
+  };
+
+  // MQQQQPR_with_dsub_4_in_DPR_8 Register Class...
+  static const MCPhysReg MQQQQPR_with_dsub_4_in_DPR_8[] = {
+    ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, 
+  };
+
+  // MQQQQPR_with_dsub_4_in_DPR_8 Bit set.
+  static const uint8_t MQQQQPR_with_dsub_4_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
+  };
+
+  // MQQQQPR_with_dsub_6_in_DPR_8 Register Class...
+  static const MCPhysReg MQQQQPR_with_dsub_6_in_DPR_8[] = {
+    ARM_Q0_Q1_Q2_Q3, 
+  };
+
+  // MQQQQPR_with_dsub_6_in_DPR_8 Bit set.
+  static const uint8_t MQQQQPR_with_dsub_6_in_DPR_8Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
+  };
 
 static const MCRegisterClass ARMMCRegisterClasses[] = {
   { HPR, HPRBits, sizeof(HPRBits) },
+  { FPWithVPR, FPWithVPRBits, sizeof(FPWithVPRBits) },
   { SPR, SPRBits, sizeof(SPRBits) },
+  { FPWithVPR_with_ssub_0, FPWithVPR_with_ssub_0Bits, sizeof(FPWithVPR_with_ssub_0Bits) },
   { GPR, GPRBits, sizeof(GPRBits) },
   { GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits) },
+  { GPRwithZR, GPRwithZRBits, sizeof(GPRwithZRBits) },
   { SPR_8, SPR_8Bits, sizeof(SPR_8Bits) },
   { GPRnopc, GPRnopcBits, sizeof(GPRnopcBits) },
+  { GPRnosp, GPRnospBits, sizeof(GPRnospBits) },
+  { GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnospBits, sizeof(GPRwithAPSR_NZCVnospBits) },
+  { GPRwithAPSRnosp, GPRwithAPSRnospBits, sizeof(GPRwithAPSRnospBits) },
+  { GPRwithZRnosp, GPRwithZRnospBits, sizeof(GPRwithZRnospBits) },
+  { GPRnoip, GPRnoipBits, sizeof(GPRnoipBits) },
   { rGPR, rGPRBits, sizeof(rGPRBits) },
+  { GPRnoip_and_GPRnopc, GPRnoip_and_GPRnopcBits, sizeof(GPRnoip_and_GPRnopcBits) },
+  { GPRnoip_and_GPRnosp, GPRnoip_and_GPRnospBits, sizeof(GPRnoip_and_GPRnospBits) },
+  { GPRnoip_and_GPRwithAPSR_NZCVnosp, GPRnoip_and_GPRwithAPSR_NZCVnospBits, sizeof(GPRnoip_and_GPRwithAPSR_NZCVnospBits) },
   { tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits) },
+  { FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits) },
   { hGPR, hGPRBits, sizeof(hGPRBits) },
   { tGPR, tGPRBits, sizeof(tGPRBits) },
+  { tGPREven, tGPREvenBits, sizeof(tGPREvenBits) },
   { GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, sizeof(GPRnopc_and_hGPRBits) },
-  { hGPR_and_rGPR, hGPR_and_rGPRBits, sizeof(hGPR_and_rGPRBits) },
+  { GPRnosp_and_hGPR, GPRnosp_and_hGPRBits, sizeof(GPRnosp_and_hGPRBits) },
+  { GPRnoip_and_hGPR, GPRnoip_and_hGPRBits, sizeof(GPRnoip_and_hGPRBits) },
+  { GPRnoip_and_tGPREven, GPRnoip_and_tGPREvenBits, sizeof(GPRnoip_and_tGPREvenBits) },
+  { GPRnosp_and_GPRnopc_and_hGPR, GPRnosp_and_GPRnopc_and_hGPRBits, sizeof(GPRnosp_and_GPRnopc_and_hGPRBits) },
+  { tGPROdd, tGPROddBits, sizeof(tGPROddBits) },
+  { GPRnopc_and_GPRnoip_and_hGPR, GPRnopc_and_GPRnoip_and_hGPRBits, sizeof(GPRnopc_and_GPRnoip_and_hGPRBits) },
+  { GPRnosp_and_GPRnoip_and_hGPR, GPRnosp_and_GPRnoip_and_hGPRBits, sizeof(GPRnosp_and_GPRnoip_and_hGPRBits) },
   { tcGPR, tcGPRBits, sizeof(tcGPRBits) },
-  { tGPR_and_tcGPR, tGPR_and_tcGPRBits, sizeof(tGPR_and_tcGPRBits) },
+  { GPRnoip_and_tcGPR, GPRnoip_and_tcGPRBits, sizeof(GPRnoip_and_tcGPRBits) },
+  { GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR, GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits, sizeof(GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits) },
+  { hGPR_and_tGPREven, hGPR_and_tGPREvenBits, sizeof(hGPR_and_tGPREvenBits) },
+  { tGPR_and_tGPREven, tGPR_and_tGPREvenBits, sizeof(tGPR_and_tGPREvenBits) },
+  { tGPR_and_tGPROdd, tGPR_and_tGPROddBits, sizeof(tGPR_and_tGPROddBits) },
+  { tGPREven_and_tcGPR, tGPREven_and_tcGPRBits, sizeof(tGPREven_and_tcGPRBits) },
+  { hGPR_and_GPRnoip_and_tGPREven, hGPR_and_GPRnoip_and_tGPREvenBits, sizeof(hGPR_and_GPRnoip_and_tGPREvenBits) },
+  { hGPR_and_tGPROdd, hGPR_and_tGPROddBits, sizeof(hGPR_and_tGPROddBits) },
+  { tGPREven_and_GPRnoip_and_tcGPR, tGPREven_and_GPRnoip_and_tcGPRBits, sizeof(tGPREven_and_GPRnoip_and_tcGPRBits) },
+  { tGPROdd_and_tcGPR, tGPROdd_and_tcGPRBits, sizeof(tGPROdd_and_tcGPRBits) },
   { CCR, CCRBits, sizeof(CCRBits) },
+  { FPCXTRegs, FPCXTRegsBits, sizeof(FPCXTRegsBits) },
+  { GPRlr, GPRlrBits, sizeof(GPRlrBits) },
   { GPRsp, GPRspBits, sizeof(GPRspBits) },
+  { VCCR, VCCRBits, sizeof(VCCRBits) },
+  { cl_FPSCR_NZCV, cl_FPSCR_NZCVBits, sizeof(cl_FPSCR_NZCVBits) },
   { hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, sizeof(hGPR_and_tGPRwithpcBits) },
   { hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits) },
   { DPR, DPRBits, sizeof(DPRBits) },
   { DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits) },
   { DPR_8, DPR_8Bits, sizeof(DPR_8Bits) },
   { GPRPair, GPRPairBits, sizeof(GPRPairBits) },
-  { GPRPair_with_gsub_1_in_rGPR, GPRPair_with_gsub_1_in_rGPRBits, sizeof(GPRPair_with_gsub_1_in_rGPRBits) },
+  { GPRPairnosp, GPRPairnospBits, sizeof(GPRPairnospBits) },
   { GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, sizeof(GPRPair_with_gsub_0_in_tGPRBits) },
   { GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPair_with_gsub_0_in_hGPRBits) },
   { GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, sizeof(GPRPair_with_gsub_0_in_tcGPRBits) },
-  { GPRPair_with_gsub_1_in_hGPR_and_rGPR, GPRPair_with_gsub_1_in_hGPR_and_rGPRBits, sizeof(GPRPair_with_gsub_1_in_hGPR_and_rGPRBits) },
   { GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, sizeof(GPRPair_with_gsub_1_in_tcGPRBits) },
+  { GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits) },
   { GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, sizeof(GPRPair_with_gsub_1_in_GPRspBits) },
   { DPairSpc, DPairSpcBits, sizeof(DPairSpcBits) },
   { DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, sizeof(DPairSpc_with_ssub_0Bits) },
@@ -2033,6 +2654,7 @@ static const MCRegisterClass ARMMCRegisterClasses[] = {
   { QPR, QPRBits, sizeof(QPRBits) },
   { DPair_with_ssub_2, DPair_with_ssub_2Bits, sizeof(DPair_with_ssub_2Bits) },
   { DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, sizeof(DPair_with_dsub_0_in_DPR_8Bits) },
+  { MQPR, MQPRBits, sizeof(MQPRBits) },
   { QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits) },
   { DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, sizeof(DPair_with_dsub_1_in_DPR_8Bits) },
   { QPR_8, QPR_8Bits, sizeof(QPR_8Bits) },
@@ -2048,17 +2670,17 @@ static const MCRegisterClass ARMMCRegisterClasses[] = {
   { DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, sizeof(DTripleSpc_with_ssub_8Bits) },
   { DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits) },
   { DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, sizeof(DTriple_with_dsub_0_in_DPR_8Bits) },
-  { DTriple_with_qsub_0_in_QPR_VFP2, DTriple_with_qsub_0_in_QPR_VFP2Bits, sizeof(DTriple_with_qsub_0_in_QPR_VFP2Bits) },
+  { DTriple_with_qsub_0_in_MQPR, DTriple_with_qsub_0_in_MQPRBits, sizeof(DTriple_with_qsub_0_in_MQPRBits) },
   { DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
   { DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, sizeof(DTriple_with_dsub_1_in_DPR_8Bits) },
-  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) },
-  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_QPRBits) },
+  { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
+  { DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits) },
   { DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits) },
   { DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, sizeof(DTriple_with_dsub_2_in_DPR_8Bits) },
   { DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits) },
-  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
+  { DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
   { DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, sizeof(DTriple_with_qsub_0_in_QPR_8Bits) },
-  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_QPRBits) },
+  { DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits) },
   { DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) },
   { DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits) },
   { DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, sizeof(DQuadSpc_with_ssub_0Bits) },
@@ -2075,28 +2697,31 @@ static const MCRegisterClass ARMMCRegisterClasses[] = {
   { DQuad_with_ssub_4, DQuad_with_ssub_4Bits, sizeof(DQuad_with_ssub_4Bits) },
   { DQuad_with_ssub_6, DQuad_with_ssub_6Bits, sizeof(DQuad_with_ssub_6Bits) },
   { DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, sizeof(DQuad_with_dsub_0_in_DPR_8Bits) },
-  { DQuad_with_qsub_0_in_QPR_VFP2, DQuad_with_qsub_0_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_0_in_QPR_VFP2Bits) },
+  { DQuad_with_qsub_0_in_MQPR, DQuad_with_qsub_0_in_MQPRBits, sizeof(DQuad_with_qsub_0_in_MQPRBits) },
   { DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
   { DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, sizeof(DQuad_with_dsub_1_in_DPR_8Bits) },
-  { DQuad_with_qsub_1_in_QPR_VFP2, DQuad_with_qsub_1_in_QPR_VFP2Bits, sizeof(DQuad_with_qsub_1_in_QPR_VFP2Bits) },
-  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_VFP2Bits) },
+  { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
+  { MQQPR, MQQPRBits, sizeof(MQQPRBits) },
   { DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, sizeof(DQuad_with_dsub_2_in_DPR_8Bits) },
-  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
+  { DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
   { DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, sizeof(DQuad_with_dsub_3_in_DPR_8Bits) },
-  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
+  { DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
   { DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, sizeof(DQuad_with_qsub_0_in_QPR_8Bits) },
   { DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, sizeof(DQuad_with_qsub_1_in_QPR_8Bits) },
   { DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) },
-  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
+  { DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
   { QQQQPR, QQQQPRBits, sizeof(QQQQPRBits) },
   { QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, sizeof(QQQQPR_with_ssub_0Bits) },
   { QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, sizeof(QQQQPR_with_ssub_4Bits) },
   { QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, sizeof(QQQQPR_with_ssub_8Bits) },
-  { QQQQPR_with_ssub_12, QQQQPR_with_ssub_12Bits, sizeof(QQQQPR_with_ssub_12Bits) },
-  { QQQQPR_with_dsub_0_in_DPR_8, QQQQPR_with_dsub_0_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_0_in_DPR_8Bits) },
-  { QQQQPR_with_dsub_2_in_DPR_8, QQQQPR_with_dsub_2_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_2_in_DPR_8Bits) },
-  { QQQQPR_with_dsub_4_in_DPR_8, QQQQPR_with_dsub_4_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_4_in_DPR_8Bits) },
-  { QQQQPR_with_dsub_6_in_DPR_8, QQQQPR_with_dsub_6_in_DPR_8Bits, sizeof(QQQQPR_with_dsub_6_in_DPR_8Bits) },
+  { MQQQQPR, MQQQQPRBits, sizeof(MQQQQPRBits) },
+  { MQQQQPR_with_dsub_0_in_DPR_8, MQQQQPR_with_dsub_0_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_0_in_DPR_8Bits) },
+  { MQQQQPR_with_dsub_2_in_DPR_8, MQQQQPR_with_dsub_2_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_2_in_DPR_8Bits) },
+  { MQQQQPR_with_dsub_4_in_DPR_8, MQQQQPR_with_dsub_4_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_4_in_DPR_8Bits) },
+  { MQQQQPR_with_dsub_6_in_DPR_8, MQQQQPR_with_dsub_6_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_6_in_DPR_8Bits) },
 };
 
 #endif // GET_REGINFO_MC_DESC
+
+
+
diff --git a/arch/ARM/ARMGenRegisterName.inc b/arch/ARM/ARMGenRegisterName.inc
deleted file mode 100644
index 22c7d05fb..000000000
--- a/arch/ARM/ARMGenRegisterName.inc
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-/// getRegisterName - This method is automatically generated by tblgen
-/// from the register set description.  This returns the assembler name
-/// for the specified register.
-static const char *getRegisterName(unsigned RegNo)
-{
-
-#ifndef CAPSTONE_DIET
-  static const char AsmStrs[] = {
-  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
-  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
-  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
-  /* 39 */ 'd', '1', '0', 0,
-  /* 43 */ 'q', '1', '0', 0,
-  /* 47 */ 's', '1', '0', 0,
-  /* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
-  /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
-  /* 83 */ 'd', '2', '0', 0,
-  /* 87 */ 's', '2', '0', 0,
-  /* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
-  /* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
-  /* 123 */ 'd', '3', '0', 0,
-  /* 127 */ 's', '3', '0', 0,
-  /* 131 */ 'd', '0', 0,
-  /* 134 */ 'q', '0', 0,
-  /* 137 */ 'm', 'v', 'f', 'r', '0', 0,
-  /* 143 */ 's', '0', 0,
-  /* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
-  /* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
-  /* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
-  /* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
-  /* 192 */ 'd', '1', '1', 0,
-  /* 196 */ 'q', '1', '1', 0,
-  /* 200 */ 's', '1', '1', 0,
-  /* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
-  /* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
-  /* 232 */ 'd', '2', '1', 0,
-  /* 236 */ 's', '2', '1', 0,
-  /* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
-  /* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
-  /* 268 */ 'd', '3', '1', 0,
-  /* 272 */ 's', '3', '1', 0,
-  /* 276 */ 'Q', '0', '_', 'Q', '1', 0,
-  /* 282 */ 'R', '0', '_', 'R', '1', 0,
-  /* 288 */ 'd', '1', 0,
-  /* 291 */ 'q', '1', 0,
-  /* 294 */ 'm', 'v', 'f', 'r', '1', 0,
-  /* 300 */ 's', '1', 0,
-  /* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
-  /* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
-  /* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
-  /* 347 */ 'd', '1', '2', 0,
-  /* 351 */ 'q', '1', '2', 0,
-  /* 355 */ 's', '1', '2', 0,
-  /* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
-  /* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
-  /* 391 */ 'd', '2', '2', 0,
-  /* 395 */ 's', '2', '2', 0,
-  /* 399 */ 'D', '0', '_', 'D', '2', 0,
-  /* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
-  /* 414 */ 'Q', '1', '_', 'Q', '2', 0,
-  /* 420 */ 'd', '2', 0,
-  /* 423 */ 'q', '2', 0,
-  /* 426 */ 'm', 'v', 'f', 'r', '2', 0,
-  /* 432 */ 's', '2', 0,
-  /* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
-  /* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
-  /* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
-  /* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
-  /* 485 */ 'd', '1', '3', 0,
-  /* 489 */ 'q', '1', '3', 0,
-  /* 493 */ 's', '1', '3', 0,
-  /* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
-  /* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
-  /* 525 */ 'd', '2', '3', 0,
-  /* 529 */ 's', '2', '3', 0,
-  /* 533 */ 'D', '1', '_', 'D', '3', 0,
-  /* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
-  /* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
-  /* 560 */ 'R', '2', '_', 'R', '3', 0,
-  /* 566 */ 'd', '3', 0,
-  /* 569 */ 'q', '3', 0,
-  /* 572 */ 'r', '3', 0,
-  /* 575 */ 's', '3', 0,
-  /* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
-  /* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
-  /* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
-  /* 625 */ 'd', '1', '4', 0,
-  /* 629 */ 'q', '1', '4', 0,
-  /* 633 */ 's', '1', '4', 0,
-  /* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
-  /* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
-  /* 669 */ 'd', '2', '4', 0,
-  /* 673 */ 's', '2', '4', 0,
-  /* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
-  /* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
-  /* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
-  /* 710 */ 'd', '4', 0,
-  /* 713 */ 'q', '4', 0,
-  /* 716 */ 'r', '4', 0,
-  /* 719 */ 's', '4', 0,
-  /* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
-  /* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
-  /* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
-  /* 765 */ 'd', '1', '5', 0,
-  /* 769 */ 'q', '1', '5', 0,
-  /* 773 */ 's', '1', '5', 0,
-  /* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
-  /* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
-  /* 805 */ 'd', '2', '5', 0,
-  /* 809 */ 's', '2', '5', 0,
-  /* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
-  /* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
-  /* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
-  /* 843 */ 'R', '4', '_', 'R', '5', 0,
-  /* 849 */ 'd', '5', 0,
-  /* 852 */ 'q', '5', 0,
-  /* 855 */ 'r', '5', 0,
-  /* 858 */ 's', '5', 0,
-  /* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
-  /* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
-  /* 893 */ 'd', '1', '6', 0,
-  /* 897 */ 's', '1', '6', 0,
-  /* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
-  /* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
-  /* 933 */ 'd', '2', '6', 0,
-  /* 937 */ 's', '2', '6', 0,
-  /* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
-  /* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
-  /* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
-  /* 977 */ 'd', '6', 0,
-  /* 980 */ 'q', '6', 0,
-  /* 983 */ 'r', '6', 0,
-  /* 986 */ 's', '6', 0,
-  /* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
-  /* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
-  /* 1017 */ 'd', '1', '7', 0,
-  /* 1021 */ 's', '1', '7', 0,
-  /* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
-  /* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
-  /* 1053 */ 'd', '2', '7', 0,
-  /* 1057 */ 's', '2', '7', 0,
-  /* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
-  /* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
-  /* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
-  /* 1094 */ 'R', '6', '_', 'R', '7', 0,
-  /* 1100 */ 'd', '7', 0,
-  /* 1103 */ 'q', '7', 0,
-  /* 1106 */ 'r', '7', 0,
-  /* 1109 */ 's', '7', 0,
-  /* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
-  /* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
-  /* 1144 */ 'd', '1', '8', 0,
-  /* 1148 */ 's', '1', '8', 0,
-  /* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
-  /* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
-  /* 1184 */ 'd', '2', '8', 0,
-  /* 1188 */ 's', '2', '8', 0,
-  /* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
-  /* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
-  /* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
-  /* 1228 */ 'd', '8', 0,
-  /* 1231 */ 'q', '8', 0,
-  /* 1234 */ 'r', '8', 0,
-  /* 1237 */ 's', '8', 0,
-  /* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
-  /* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
-  /* 1268 */ 'd', '1', '9', 0,
-  /* 1272 */ 's', '1', '9', 0,
-  /* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
-  /* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
-  /* 1304 */ 'd', '2', '9', 0,
-  /* 1308 */ 's', '2', '9', 0,
-  /* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
-  /* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
-  /* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
-  /* 1345 */ 'R', '8', '_', 'R', '9', 0,
-  /* 1351 */ 'd', '9', 0,
-  /* 1354 */ 'q', '9', 0,
-  /* 1357 */ 's', '9', 0,
-  /* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0,
-  /* 1367 */ 's', 'b', 0,
-  /* 1370 */ 'p', 'c', 0,
-  /* 1373 */ 'f', 'p', 'e', 'x', 'c', 0,
-  /* 1379 */ 'f', 'p', 's', 'i', 'd', 0,
-  /* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
-  /* 1393 */ 's', 'l', 0,
-  /* 1396 */ 'f', 'p', 0,
-  /* 1399 */ 'i', 'p', 0,
-  /* 1402 */ 's', 'p', 0,
-  /* 1405 */ 'f', 'p', 's', 'c', 'r', 0,
-  /* 1411 */ 'l', 'r', 0,
-  /* 1414 */ 'a', 'p', 's', 'r', 0,
-  /* 1419 */ 'c', 'p', 's', 'r', 0,
-  /* 1424 */ 's', 'p', 's', 'r', 0,
-  /* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0,
-  /* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  /* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  };
-
-  static const uint16_t RegAsmOffset[] = {
-    1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131,
-    288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625,
-    765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184,
-    1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980,
-    1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716,
-    855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858,
-    986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272,
-    87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533,
-    680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997,
-    1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260,
-    276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617,
-    757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749,
-    1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207,
-    1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379,
-    513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195,
-    1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363,
-    501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0,
-    157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637,
-    777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601,
-    885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593,
-    877, 1128, 67, 375, 653, 917, 1168, 107,
-  };
-
-  return AsmStrs+RegAsmOffset[RegNo-1];
-#else
-  return NULL;
-#endif
-}
diff --git a/arch/ARM/ARMGenRegisterName_digit.inc b/arch/ARM/ARMGenRegisterName_digit.inc
deleted file mode 100644
index c45010301..000000000
--- a/arch/ARM/ARMGenRegisterName_digit.inc
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-/// getRegisterName - This method is automatically generated by tblgen
-/// from the register set description.  This returns the assembler name
-/// for the specified register.
-static const char *getRegisterName_digit(unsigned RegNo)
-{
-
-#ifndef CAPSTONE_DIET
-  static const char AsmStrs[] = {
-  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
-  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
-  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
-  /* 39 */ 'd', '1', '0', 0,
-  /* 43 */ 'q', '1', '0', 0,
-  /* 47 */ 'r', '1', '0', 0,
-  /* 51 */ 's', '1', '0', 0,
-  /* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
-  /* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
-  /* 87 */ 'd', '2', '0', 0,
-  /* 91 */ 's', '2', '0', 0,
-  /* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
-  /* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
-  /* 127 */ 'd', '3', '0', 0,
-  /* 131 */ 's', '3', '0', 0,
-  /* 135 */ 'd', '0', 0,
-  /* 138 */ 'q', '0', 0,
-  /* 141 */ 'm', 'v', 'f', 'r', '0', 0,
-  /* 147 */ 's', '0', 0,
-  /* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
-  /* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
-  /* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
-  /* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
-  /* 196 */ 'd', '1', '1', 0,
-  /* 200 */ 'q', '1', '1', 0,
-  /* 204 */ 'r', '1', '1', 0,
-  /* 208 */ 's', '1', '1', 0,
-  /* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
-  /* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
-  /* 240 */ 'd', '2', '1', 0,
-  /* 244 */ 's', '2', '1', 0,
-  /* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
-  /* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
-  /* 276 */ 'd', '3', '1', 0,
-  /* 280 */ 's', '3', '1', 0,
-  /* 284 */ 'Q', '0', '_', 'Q', '1', 0,
-  /* 290 */ 'R', '0', '_', 'R', '1', 0,
-  /* 296 */ 'd', '1', 0,
-  /* 299 */ 'q', '1', 0,
-  /* 302 */ 'm', 'v', 'f', 'r', '1', 0,
-  /* 308 */ 's', '1', 0,
-  /* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
-  /* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
-  /* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
-  /* 355 */ 'd', '1', '2', 0,
-  /* 359 */ 'q', '1', '2', 0,
-  /* 363 */ 'r', '1', '2', 0,
-  /* 367 */ 's', '1', '2', 0,
-  /* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
-  /* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
-  /* 403 */ 'd', '2', '2', 0,
-  /* 407 */ 's', '2', '2', 0,
-  /* 411 */ 'D', '0', '_', 'D', '2', 0,
-  /* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
-  /* 426 */ 'Q', '1', '_', 'Q', '2', 0,
-  /* 432 */ 'd', '2', 0,
-  /* 435 */ 'q', '2', 0,
-  /* 438 */ 'm', 'v', 'f', 'r', '2', 0,
-  /* 444 */ 's', '2', 0,
-  /* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
-  /* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
-  /* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
-  /* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
-  /* 497 */ 'd', '1', '3', 0,
-  /* 501 */ 'q', '1', '3', 0,
-  /* 505 */ 'r', '1', '3', 0,
-  /* 509 */ 's', '1', '3', 0,
-  /* 513 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
-  /* 529 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
-  /* 541 */ 'd', '2', '3', 0,
-  /* 545 */ 's', '2', '3', 0,
-  /* 549 */ 'D', '1', '_', 'D', '3', 0,
-  /* 555 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
-  /* 564 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
-  /* 576 */ 'R', '2', '_', 'R', '3', 0,
-  /* 582 */ 'd', '3', 0,
-  /* 585 */ 'q', '3', 0,
-  /* 588 */ 'r', '3', 0,
-  /* 591 */ 's', '3', 0,
-  /* 594 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
-  /* 609 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
-  /* 625 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
-  /* 641 */ 'd', '1', '4', 0,
-  /* 645 */ 'q', '1', '4', 0,
-  /* 649 */ 'r', '1', '4', 0,
-  /* 653 */ 's', '1', '4', 0,
-  /* 657 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
-  /* 673 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
-  /* 689 */ 'd', '2', '4', 0,
-  /* 693 */ 's', '2', '4', 0,
-  /* 697 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
-  /* 706 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
-  /* 718 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
-  /* 730 */ 'd', '4', 0,
-  /* 733 */ 'q', '4', 0,
-  /* 736 */ 'r', '4', 0,
-  /* 739 */ 's', '4', 0,
-  /* 742 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
-  /* 757 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
-  /* 769 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
-  /* 785 */ 'd', '1', '5', 0,
-  /* 789 */ 'q', '1', '5', 0,
-  /* 793 */ 's', '1', '5', 0,
-  /* 797 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
-  /* 813 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
-  /* 825 */ 'd', '2', '5', 0,
-  /* 829 */ 's', '2', '5', 0,
-  /* 833 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
-  /* 842 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
-  /* 851 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
-  /* 863 */ 'R', '4', '_', 'R', '5', 0,
-  /* 869 */ 'd', '5', 0,
-  /* 872 */ 'q', '5', 0,
-  /* 875 */ 'r', '5', 0,
-  /* 878 */ 's', '5', 0,
-  /* 881 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
-  /* 897 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
-  /* 913 */ 'd', '1', '6', 0,
-  /* 917 */ 's', '1', '6', 0,
-  /* 921 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
-  /* 937 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
-  /* 953 */ 'd', '2', '6', 0,
-  /* 957 */ 's', '2', '6', 0,
-  /* 961 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
-  /* 973 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
-  /* 985 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
-  /* 997 */ 'd', '6', 0,
-  /* 1000 */ 'q', '6', 0,
-  /* 1003 */ 'r', '6', 0,
-  /* 1006 */ 's', '6', 0,
-  /* 1009 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
-  /* 1025 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
-  /* 1037 */ 'd', '1', '7', 0,
-  /* 1041 */ 's', '1', '7', 0,
-  /* 1045 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
-  /* 1061 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
-  /* 1073 */ 'd', '2', '7', 0,
-  /* 1077 */ 's', '2', '7', 0,
-  /* 1081 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
-  /* 1093 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
-  /* 1102 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
-  /* 1114 */ 'R', '6', '_', 'R', '7', 0,
-  /* 1120 */ 'd', '7', 0,
-  /* 1123 */ 'q', '7', 0,
-  /* 1126 */ 'r', '7', 0,
-  /* 1129 */ 's', '7', 0,
-  /* 1132 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
-  /* 1148 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
-  /* 1164 */ 'd', '1', '8', 0,
-  /* 1168 */ 's', '1', '8', 0,
-  /* 1172 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
-  /* 1188 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
-  /* 1204 */ 'd', '2', '8', 0,
-  /* 1208 */ 's', '2', '8', 0,
-  /* 1212 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
-  /* 1224 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
-  /* 1236 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
-  /* 1248 */ 'd', '8', 0,
-  /* 1251 */ 'q', '8', 0,
-  /* 1254 */ 'r', '8', 0,
-  /* 1257 */ 's', '8', 0,
-  /* 1260 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
-  /* 1276 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
-  /* 1288 */ 'd', '1', '9', 0,
-  /* 1292 */ 's', '1', '9', 0,
-  /* 1296 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
-  /* 1312 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
-  /* 1324 */ 'd', '2', '9', 0,
-  /* 1328 */ 's', '2', '9', 0,
-  /* 1332 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
-  /* 1344 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
-  /* 1353 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
-  /* 1365 */ 'R', '8', '_', 'R', '9', 0,
-  /* 1371 */ 'd', '9', 0,
-  /* 1374 */ 'q', '9', 0,
-  /* 1377 */ 'r', '9', 0,
-  /* 1380 */ 's', '9', 0,
-  /* 1383 */ 'R', '1', '2', '_', 'S', 'P', 0,
-  /* 1390 */ 'p', 'c', 0,
-  /* 1393 */ 'f', 'p', 'e', 'x', 'c', 0,
-  /* 1399 */ 'f', 'p', 's', 'i', 'd', 0,
-  /* 1405 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
-  /* 1413 */ 'f', 'p', 's', 'c', 'r', 0,
-  /* 1419 */ 'a', 'p', 's', 'r', 0,
-  /* 1424 */ 'c', 'p', 's', 'r', 0,
-  /* 1429 */ 's', 'p', 's', 'r', 0,
-  /* 1434 */ 'f', 'p', 'i', 'n', 's', 't', 0,
-  /* 1441 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  /* 1452 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  };
-
-  static const uint16_t RegAsmOffset[] = {
-    1419, 1452, 1424, 1393, 1434, 1413, 1441, 1399, 1405, 649, 1390, 505, 1429, 135,
-    296, 432, 582, 730, 869, 997, 1120, 1248, 1371, 39, 196, 355, 497, 641,
-    785, 913, 1037, 1164, 1288, 87, 240, 403, 541, 689, 825, 953, 1073, 1204,
-    1324, 127, 276, 447, 141, 302, 438, 138, 299, 435, 585, 733, 872, 1000,
-    1123, 1251, 1374, 43, 200, 359, 501, 645, 789, 144, 305, 441, 588, 736,
-    875, 1003, 1126, 1254, 1377, 47, 204, 363, 147, 308, 444, 591, 739, 878,
-    1006, 1129, 1257, 1380, 51, 208, 367, 509, 653, 793, 917, 1041, 1168, 1292,
-    91, 244, 407, 545, 693, 829, 957, 1077, 1208, 1328, 131, 280, 411, 549,
-    700, 836, 967, 1087, 1218, 1338, 6, 167, 317, 461, 601, 749, 889, 1017,
-    1140, 1268, 63, 232, 379, 521, 665, 805, 929, 1053, 1180, 1304, 103, 268,
-    284, 426, 570, 724, 857, 991, 1108, 1242, 1359, 32, 180, 347, 489, 633,
-    777, 564, 718, 851, 985, 1102, 1236, 1353, 26, 174, 340, 481, 625, 769,
-    1383, 290, 576, 863, 1114, 1365, 188, 417, 555, 709, 842, 976, 1093, 1227,
-    1344, 16, 150, 328, 469, 613, 757, 901, 1025, 1152, 1276, 75, 212, 391,
-    529, 677, 813, 941, 1061, 1192, 1312, 115, 248, 697, 833, 964, 1084, 1215,
-    1335, 3, 164, 314, 458, 597, 745, 885, 1013, 1136, 1264, 59, 228, 375,
-    517, 661, 801, 925, 1049, 1176, 1300, 99, 264, 961, 1081, 1212, 1332, 0,
-    161, 311, 455, 594, 742, 881, 1009, 1132, 1260, 55, 224, 371, 513, 657,
-    797, 921, 1045, 1172, 1296, 95, 260, 420, 712, 979, 1230, 19, 332, 617,
-    905, 1156, 79, 395, 681, 945, 1196, 119, 706, 973, 1224, 13, 325, 609,
-    897, 1148, 71, 387, 673, 937, 1188, 111,
-  };
-
-  return AsmStrs+RegAsmOffset[RegNo-1];
-#else
-  return NULL;
-#endif
-}
diff --git a/arch/ARM/ARMGenSubtargetInfo.inc b/arch/ARM/ARMGenSubtargetInfo.inc
index 45bfad856..97a9feea0 100644
--- a/arch/ARM/ARMGenSubtargetInfo.inc
+++ b/arch/ARM/ARMGenSubtargetInfo.inc
@@ -1,162 +1,244 @@
-
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
-|* Subtarget Enumeration Source Fragment                                      *|
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
 
 enum {
-  ARM_ARMv2 = 0,
-  ARM_ARMv2a = 1,
-  ARM_ARMv3 = 2,
-  ARM_ARMv3m = 3,
-  ARM_ARMv4 = 4,
-  ARM_ARMv4t = 5,
-  ARM_ARMv5t = 6,
-  ARM_ARMv5te = 7,
-  ARM_ARMv5tej = 8,
-  ARM_ARMv6 = 9,
-  ARM_ARMv6j = 10,
-  ARM_ARMv6k = 11,
-  ARM_ARMv6kz = 12,
-  ARM_ARMv6m = 13,
-  ARM_ARMv6sm = 14,
-  ARM_ARMv6t2 = 15,
-  ARM_ARMv7a = 16,
-  ARM_ARMv7em = 17,
-  ARM_ARMv7k = 18,
-  ARM_ARMv7m = 19,
-  ARM_ARMv7r = 20,
-  ARM_ARMv7s = 21,
-  ARM_ARMv7ve = 22,
-  ARM_ARMv8a = 23,
-  ARM_ARMv8mBaseline = 24,
-  ARM_ARMv8mMainline = 25,
-  ARM_ARMv8r = 26,
-  ARM_ARMv81a = 27,
-  ARM_ARMv82a = 28,
-  ARM_ARMv83a = 29,
-  ARM_ARMv84a = 30,
-  ARM_Feature8MSecExt = 31,
-  ARM_FeatureAClass = 32,
-  ARM_FeatureAES = 33,
-  ARM_FeatureAcquireRelease = 34,
-  ARM_FeatureAvoidMOVsShOp = 35,
-  ARM_FeatureAvoidPartialCPSR = 36,
-  ARM_FeatureCRC = 37,
-  ARM_FeatureCheapPredicableCPSR = 38,
-  ARM_FeatureCheckVLDnAlign = 39,
-  ARM_FeatureCrypto = 40,
-  ARM_FeatureD16 = 41,
-  ARM_FeatureDB = 42,
-  ARM_FeatureDFB = 43,
-  ARM_FeatureDSP = 44,
-  ARM_FeatureDontWidenVMOVS = 45,
-  ARM_FeatureDotProd = 46,
-  ARM_FeatureExecuteOnly = 47,
-  ARM_FeatureExpandMLx = 48,
-  ARM_FeatureFP16 = 49,
-  ARM_FeatureFPAO = 50,
-  ARM_FeatureFPARMv8 = 51,
-  ARM_FeatureFullFP16 = 52,
-  ARM_FeatureFuseAES = 53,
-  ARM_FeatureFuseLiterals = 54,
-  ARM_FeatureHWDivARM = 55,
-  ARM_FeatureHWDivThumb = 56,
-  ARM_FeatureHasNoBranchPredictor = 57,
-  ARM_FeatureHasRetAddrStack = 58,
-  ARM_FeatureHasSlowFPVMLx = 59,
-  ARM_FeatureHasVMLxHazards = 60,
-  ARM_FeatureLongCalls = 61,
-  ARM_FeatureMClass = 62,
-  ARM_FeatureMP = 63,
-  ARM_FeatureMuxedUnits = 64,
-  ARM_FeatureNEON = 65,
-  ARM_FeatureNEONForFP = 66,
-  ARM_FeatureNEONForFPMovs = 67,
-  ARM_FeatureNaClTrap = 68,
-  ARM_FeatureNoARM = 69,
-  ARM_FeatureNoMovt = 70,
-  ARM_FeatureNoNegativeImmediates = 71,
-  ARM_FeatureNoPostRASched = 72,
-  ARM_FeatureNonpipelinedVFP = 73,
-  ARM_FeaturePerfMon = 74,
-  ARM_FeaturePref32BitThumb = 75,
-  ARM_FeaturePrefISHSTBarrier = 76,
-  ARM_FeaturePreferVMOVSR = 77,
-  ARM_FeatureProfUnpredicate = 78,
-  ARM_FeatureRAS = 79,
-  ARM_FeatureRClass = 80,
-  ARM_FeatureReadTp = 81,
-  ARM_FeatureReserveR9 = 82,
-  ARM_FeatureSHA2 = 83,
-  ARM_FeatureSlowFPBrcc = 84,
-  ARM_FeatureSlowLoadDSubreg = 85,
-  ARM_FeatureSlowOddRegister = 86,
-  ARM_FeatureSlowVDUP32 = 87,
-  ARM_FeatureSlowVGETLNi32 = 88,
-  ARM_FeatureSplatVFPToNeon = 89,
-  ARM_FeatureStrictAlign = 90,
-  ARM_FeatureThumb2 = 91,
-  ARM_FeatureTrustZone = 92,
-  ARM_FeatureUseAA = 93,
-  ARM_FeatureUseMISched = 94,
-  ARM_FeatureV7Clrex = 95,
-  ARM_FeatureVFP2 = 96,
-  ARM_FeatureVFP3 = 97,
-  ARM_FeatureVFP4 = 98,
-  ARM_FeatureVFPOnlySP = 99,
-  ARM_FeatureVMLxForwarding = 100,
-  ARM_FeatureVirtualization = 101,
-  ARM_FeatureZCZeroing = 102,
-  ARM_HasV4TOps = 103,
-  ARM_HasV5TEOps = 104,
-  ARM_HasV5TOps = 105,
-  ARM_HasV6KOps = 106,
-  ARM_HasV6MOps = 107,
-  ARM_HasV6Ops = 108,
-  ARM_HasV6T2Ops = 109,
-  ARM_HasV7Ops = 110,
-  ARM_HasV8MBaselineOps = 111,
-  ARM_HasV8MMainlineOps = 112,
-  ARM_HasV8Ops = 113,
-  ARM_HasV8_1aOps = 114,
-  ARM_HasV8_2aOps = 115,
-  ARM_HasV8_3aOps = 116,
-  ARM_HasV8_4aOps = 117,
-  ARM_IWMMXT = 118,
-  ARM_IWMMXT2 = 119,
-  ARM_ModeSoftFloat = 120,
-  ARM_ModeThumb = 121,
-  ARM_ProcA5 = 122,
-  ARM_ProcA7 = 123,
-  ARM_ProcA8 = 124,
-  ARM_ProcA9 = 125,
-  ARM_ProcA12 = 126,
-  ARM_ProcA15 = 127,
-  ARM_ProcA17 = 128,
-  ARM_ProcA32 = 129,
-  ARM_ProcA35 = 130,
-  ARM_ProcA53 = 131,
-  ARM_ProcA55 = 132,
-  ARM_ProcA57 = 133,
-  ARM_ProcA72 = 134,
-  ARM_ProcA73 = 135,
-  ARM_ProcA75 = 136,
-  ARM_ProcExynosM1 = 137,
-  ARM_ProcKrait = 138,
-  ARM_ProcKryo = 139,
-  ARM_ProcM3 = 140,
-  ARM_ProcR4 = 141,
-  ARM_ProcR5 = 142,
-  ARM_ProcR7 = 143,
-  ARM_ProcR52 = 144,
-  ARM_ProcSwift = 145,
-  ARM_XScale = 146,
+  ARM_ARMv4 = 0,
+  ARM_ARMv4t = 1,
+  ARM_ARMv5t = 2,
+  ARM_ARMv5te = 3,
+  ARM_ARMv5tej = 4,
+  ARM_ARMv6 = 5,
+  ARM_ARMv6j = 6,
+  ARM_ARMv6k = 7,
+  ARM_ARMv6kz = 8,
+  ARM_ARMv6m = 9,
+  ARM_ARMv6sm = 10,
+  ARM_ARMv6t2 = 11,
+  ARM_ARMv7a = 12,
+  ARM_ARMv7em = 13,
+  ARM_ARMv7k = 14,
+  ARM_ARMv7m = 15,
+  ARM_ARMv7r = 16,
+  ARM_ARMv7s = 17,
+  ARM_ARMv7ve = 18,
+  ARM_ARMv8a = 19,
+  ARM_ARMv8mBaseline = 20,
+  ARM_ARMv8mMainline = 21,
+  ARM_ARMv8r = 22,
+  ARM_ARMv9a = 23,
+  ARM_ARMv81a = 24,
+  ARM_ARMv81mMainline = 25,
+  ARM_ARMv82a = 26,
+  ARM_ARMv83a = 27,
+  ARM_ARMv84a = 28,
+  ARM_ARMv85a = 29,
+  ARM_ARMv86a = 30,
+  ARM_ARMv87a = 31,
+  ARM_ARMv88a = 32,
+  ARM_ARMv89a = 33,
+  ARM_ARMv91a = 34,
+  ARM_ARMv92a = 35,
+  ARM_ARMv93a = 36,
+  ARM_ARMv94a = 37,
+  ARM_Feature8MSecExt = 38,
+  ARM_FeatureAAPCSFrameChain = 39,
+  ARM_FeatureAAPCSFrameChainLeaf = 40,
+  ARM_FeatureAClass = 41,
+  ARM_FeatureAES = 42,
+  ARM_FeatureAcquireRelease = 43,
+  ARM_FeatureAtomics32 = 44,
+  ARM_FeatureAvoidMOVsShOp = 45,
+  ARM_FeatureAvoidPartialCPSR = 46,
+  ARM_FeatureBF16 = 47,
+  ARM_FeatureCLRBHB = 48,
+  ARM_FeatureCRC = 49,
+  ARM_FeatureCheapPredicableCPSR = 50,
+  ARM_FeatureCheckVLDnAlign = 51,
+  ARM_FeatureCoprocCDE0 = 52,
+  ARM_FeatureCoprocCDE1 = 53,
+  ARM_FeatureCoprocCDE2 = 54,
+  ARM_FeatureCoprocCDE3 = 55,
+  ARM_FeatureCoprocCDE4 = 56,
+  ARM_FeatureCoprocCDE5 = 57,
+  ARM_FeatureCoprocCDE6 = 58,
+  ARM_FeatureCoprocCDE7 = 59,
+  ARM_FeatureCrypto = 60,
+  ARM_FeatureD32 = 61,
+  ARM_FeatureDB = 62,
+  ARM_FeatureDFB = 63,
+  ARM_FeatureDSP = 64,
+  ARM_FeatureDontWidenVMOVS = 65,
+  ARM_FeatureDotProd = 66,
+  ARM_FeatureExecuteOnly = 67,
+  ARM_FeatureExpandMLx = 68,
+  ARM_FeatureFP16 = 69,
+  ARM_FeatureFP16FML = 70,
+  ARM_FeatureFP64 = 71,
+  ARM_FeatureFPAO = 72,
+  ARM_FeatureFPARMv8 = 73,
+  ARM_FeatureFPARMv8_D16 = 74,
+  ARM_FeatureFPARMv8_D16_SP = 75,
+  ARM_FeatureFPARMv8_SP = 76,
+  ARM_FeatureFPRegs = 77,
+  ARM_FeatureFPRegs16 = 78,
+  ARM_FeatureFPRegs64 = 79,
+  ARM_FeatureFixCMSE_CVE_2021_35465 = 80,
+  ARM_FeatureFixCortexA57AES1742098 = 81,
+  ARM_FeatureFullFP16 = 82,
+  ARM_FeatureFuseAES = 83,
+  ARM_FeatureFuseLiterals = 84,
+  ARM_FeatureHWDivARM = 85,
+  ARM_FeatureHWDivThumb = 86,
+  ARM_FeatureHardenSlsBlr = 87,
+  ARM_FeatureHardenSlsNoComdat = 88,
+  ARM_FeatureHardenSlsRetBr = 89,
+  ARM_FeatureHasNoBranchPredictor = 90,
+  ARM_FeatureHasRetAddrStack = 91,
+  ARM_FeatureHasSlowFPVFMx = 92,
+  ARM_FeatureHasSlowFPVMLx = 93,
+  ARM_FeatureHasVMLxHazards = 94,
+  ARM_FeatureLOB = 95,
+  ARM_FeatureLongCalls = 96,
+  ARM_FeatureMClass = 97,
+  ARM_FeatureMP = 98,
+  ARM_FeatureMVEVectorCostFactor1 = 99,
+  ARM_FeatureMVEVectorCostFactor2 = 100,
+  ARM_FeatureMVEVectorCostFactor4 = 101,
+  ARM_FeatureMatMulInt8 = 102,
+  ARM_FeatureMuxedUnits = 103,
+  ARM_FeatureNEON = 104,
+  ARM_FeatureNEONForFP = 105,
+  ARM_FeatureNEONForFPMovs = 106,
+  ARM_FeatureNaClTrap = 107,
+  ARM_FeatureNoARM = 108,
+  ARM_FeatureNoBTIAtReturnTwice = 109,
+  ARM_FeatureNoMovt = 110,
+  ARM_FeatureNoNegativeImmediates = 111,
+  ARM_FeatureNoPostRASched = 112,
+  ARM_FeatureNonpipelinedVFP = 113,
+  ARM_FeaturePACBTI = 114,
+  ARM_FeaturePerfMon = 115,
+  ARM_FeaturePref32BitThumb = 116,
+  ARM_FeaturePrefISHSTBarrier = 117,
+  ARM_FeaturePrefLoopAlign32 = 118,
+  ARM_FeaturePreferVMOVSR = 119,
+  ARM_FeatureProfUnpredicate = 120,
+  ARM_FeatureRAS = 121,
+  ARM_FeatureRClass = 122,
+  ARM_FeatureReadTp = 123,
+  ARM_FeatureReserveR9 = 124,
+  ARM_FeatureSB = 125,
+  ARM_FeatureSHA2 = 126,
+  ARM_FeatureSlowFPBrcc = 127,
+  ARM_FeatureSlowLoadDSubreg = 128,
+  ARM_FeatureSlowOddRegister = 129,
+  ARM_FeatureSlowVDUP32 = 130,
+  ARM_FeatureSlowVGETLNi32 = 131,
+  ARM_FeatureSplatVFPToNeon = 132,
+  ARM_FeatureStrictAlign = 133,
+  ARM_FeatureThumb2 = 134,
+  ARM_FeatureTrustZone = 135,
+  ARM_FeatureUseMIPipeliner = 136,
+  ARM_FeatureUseMISched = 137,
+  ARM_FeatureUseWideStrideVFP = 138,
+  ARM_FeatureV7Clrex = 139,
+  ARM_FeatureVFP2 = 140,
+  ARM_FeatureVFP2_SP = 141,
+  ARM_FeatureVFP3 = 142,
+  ARM_FeatureVFP3_D16 = 143,
+  ARM_FeatureVFP3_D16_SP = 144,
+  ARM_FeatureVFP3_SP = 145,
+  ARM_FeatureVFP4 = 146,
+  ARM_FeatureVFP4_D16 = 147,
+  ARM_FeatureVFP4_D16_SP = 148,
+  ARM_FeatureVFP4_SP = 149,
+  ARM_FeatureVMLxForwarding = 150,
+  ARM_FeatureVirtualization = 151,
+  ARM_FeatureZCZeroing = 152,
+  ARM_HasCDEOps = 153,
+  ARM_HasMVEFloatOps = 154,
+  ARM_HasMVEIntegerOps = 155,
+  ARM_HasV4TOps = 156,
+  ARM_HasV5TEOps = 157,
+  ARM_HasV5TOps = 158,
+  ARM_HasV6KOps = 159,
+  ARM_HasV6MOps = 160,
+  ARM_HasV6Ops = 161,
+  ARM_HasV6T2Ops = 162,
+  ARM_HasV7Ops = 163,
+  ARM_HasV8MBaselineOps = 164,
+  ARM_HasV8MMainlineOps = 165,
+  ARM_HasV8Ops = 166,
+  ARM_HasV8_1MMainlineOps = 167,
+  ARM_HasV8_1aOps = 168,
+  ARM_HasV8_2aOps = 169,
+  ARM_HasV8_3aOps = 170,
+  ARM_HasV8_4aOps = 171,
+  ARM_HasV8_5aOps = 172,
+  ARM_HasV8_6aOps = 173,
+  ARM_HasV8_7aOps = 174,
+  ARM_HasV8_8aOps = 175,
+  ARM_HasV8_9aOps = 176,
+  ARM_HasV9_0aOps = 177,
+  ARM_HasV9_1aOps = 178,
+  ARM_HasV9_2aOps = 179,
+  ARM_HasV9_3aOps = 180,
+  ARM_HasV9_4aOps = 181,
+  ARM_IWMMXT = 182,
+  ARM_IWMMXT2 = 183,
+  ARM_ModeBigEndianInstructions = 184,
+  ARM_ModeSoftFloat = 185,
+  ARM_ModeThumb = 186,
+  ARM_ProcA5 = 187,
+  ARM_ProcA7 = 188,
+  ARM_ProcA8 = 189,
+  ARM_ProcA9 = 190,
+  ARM_ProcA12 = 191,
+  ARM_ProcA15 = 192,
+  ARM_ProcA17 = 193,
+  ARM_ProcA32 = 194,
+  ARM_ProcA35 = 195,
+  ARM_ProcA53 = 196,
+  ARM_ProcA55 = 197,
+  ARM_ProcA57 = 198,
+  ARM_ProcA72 = 199,
+  ARM_ProcA73 = 200,
+  ARM_ProcA75 = 201,
+  ARM_ProcA76 = 202,
+  ARM_ProcA77 = 203,
+  ARM_ProcA78 = 204,
+  ARM_ProcA78C = 205,
+  ARM_ProcA710 = 206,
+  ARM_ProcExynos = 207,
+  ARM_ProcKrait = 208,
+  ARM_ProcKryo = 209,
+  ARM_ProcM3 = 210,
+  ARM_ProcM7 = 211,
+  ARM_ProcR4 = 212,
+  ARM_ProcR5 = 213,
+  ARM_ProcR7 = 214,
+  ARM_ProcR52 = 215,
+  ARM_ProcSwift = 216,
+  ARM_ProcV1 = 217,
+  ARM_ProcX1 = 218,
+  ARM_ProcX1C = 219,
+  ARM_XScale = 220,
+  ARM_NumSubtargetFeatures = 221
 };
+#endif // GET_SUBTARGETINFO_ENUM
+
+
 
diff --git a/arch/ARM/ARMGenSystemRegister.inc b/arch/ARM/ARMGenSystemRegister.inc
index 4c5ce124d..bc5e67caf 100644
--- a/arch/ARM/ARMGenSystemRegister.inc
+++ b/arch/ARM/ARMGenSystemRegister.inc
@@ -1,270 +1,475 @@
-
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
-|* GenSystemRegister Source Fragment                                          *|
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
 
+/* Do not edit. */
 
-enum BankedRegValues {
-	elr_hyp = 0,
-	lr_abt = 1,
-	lr_fiq = 2,
-	lr_irq = 3,
-	lr_mon = 4,
-	lr_svc = 5,
-	lr_und = 6,
-	lr_usr = 7,
-	r10_fiq = 8,
-	r10_usr = 9,
-	r11_fiq = 10,
-	r11_usr = 11,
-	r12_fiq = 12,
-	r12_usr = 13,
-	r8_fiq = 14,
-	r8_usr = 15,
-	r9_fiq = 16,
-	r9_usr = 17,
-	sp_abt = 18,
-	sp_fiq = 19,
-	sp_hyp = 20,
-	sp_irq = 21,
-	sp_mon = 22,
-	sp_svc = 23,
-	sp_und = 24,
-	sp_usr = 25,
-	spsr_abt = 26,
-	spsr_fiq = 27,
-	spsr_hyp = 28,
-	spsr_irq = 29,
-	spsr_mon = 30,
-	spsr_svc = 31,
-	spsr_und = 32,
-};
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
 
-static const MClassSysReg MClassSysRegsList[] = {
-  { "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 0
-  { "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 1
-  { "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 2
-  { "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 3
-  { "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 4
-  { "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 5
-  { "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 6
-  { "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 7
-  { "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800,  { 0 }  }, // 8
-  { "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800,  { 0 }  }, // 9
-  { "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801,  { 0 }  }, // 10
-  { "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801,  { 0 }  }, // 11
-  { "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802,  { 0 }  }, // 12
-  { "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802,  { 0 }  }, // 13
-  { "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803,  { 0 }  }, // 14
-  { "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803,  { 0 }  }, // 15
-  { "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805,  { 0 }  }, // 16
-  { "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806,  { 0 }  }, // 17
-  { "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807,  { 0 }  }, // 18
-  { "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808,  { 0 }  }, // 19
-  { "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809,  { 0 }  }, // 20
-  { "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 21
-  { "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 22
-  { "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810,  { 0 }  }, // 23
-  { "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 24
-  { "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 25
-  { "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 26
-  { "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814,  { 0 }  }, // 27
-  { "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 28
-  { "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 29
-  { "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 30
-  { "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 31
-  { "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890,  { 0 }  }, // 32
-  { "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 33
-  { "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 34
-  { "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 35
-  { "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 36
-};
+#ifdef GET_BANKEDREG_DECL
+#endif
 
-static const BankedReg BankedRegsList[] = {
-  { "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
-  { "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
-  { "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
-  { "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3
-  { "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4
-  { "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5
-  { "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6
-  { "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7
-  { "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8
-  { "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9
-  { "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10
-  { "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11
-  { "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12
-  { "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13
-  { "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14
-  { "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15
-  { "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16
-  { "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17
-  { "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18
-  { "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19
-  { "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20
-  { "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21
-  { "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22
-  { "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23
-  { "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24
-  { "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25
-  { "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26
-  { "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27
-  { "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28
-  { "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29
-  { "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30
-  { "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31
-  { "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
-};
+#ifdef GET_MCLASSSYSREG_DECL
+#endif
 
-const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
-{
-  unsigned int i;
-  static const struct IndexType Index[] = {
-    { 0x0, 0 },
-    { 0x1, 2 },
-    { 0x2, 4 },
-    { 0x3, 6 },
-    { 0x100, 8 },
-    { 0x101, 10 },
-    { 0x102, 12 },
-    { 0x103, 14 },
-    { 0x105, 16 },
-    { 0x106, 17 },
-    { 0x107, 18 },
-    { 0x108, 19 },
-    { 0x109, 20 },
-    { 0x10A, 21 },
-    { 0x10B, 22 },
-    { 0x110, 23 },
-    { 0x111, 24 },
-    { 0x112, 25 },
-    { 0x113, 26 },
-    { 0x114, 27 },
-    { 0x188, 28 },
-    { 0x189, 29 },
-    { 0x18A, 30 },
-    { 0x18B, 31 },
-    { 0x190, 32 },
-    { 0x191, 33 },
-    { 0x193, 34 },
-    { 0x194, 35 },
-    { 0x198, 36 },
-    { 0x200, 9 },
-    { 0x201, 11 },
-    { 0x202, 13 },
-    { 0x203, 15 },
-    { 0x300, 1 },
-    { 0x301, 3 },
-    { 0x302, 5 },
-    { 0x303, 7 },
+#ifdef GET_BANKEDREG_DECL
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name);
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
+#endif
+
+#ifdef GET_MCLASSSYSREG_DECL
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8);
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
+#endif
+
+#ifdef GET_BANKEDREG_IMPL
+static const ARMBankedReg_BankedReg BankedRegsList[] = {
+  { "elr_hyp", { ARM_BANKEDREG_ELR_HYP }, 0x1E }, // 0
+  { "lr_abt", { ARM_BANKEDREG_LR_ABT }, 0x14 }, // 1
+  { "lr_fiq", { ARM_BANKEDREG_LR_FIQ }, 0xE }, // 2
+  { "lr_irq", { ARM_BANKEDREG_LR_IRQ }, 0x10 }, // 3
+  { "lr_mon", { ARM_BANKEDREG_LR_MON }, 0x1C }, // 4
+  { "lr_svc", { ARM_BANKEDREG_LR_SVC }, 0x12 }, // 5
+  { "lr_und", { ARM_BANKEDREG_LR_UND }, 0x16 }, // 6
+  { "lr_usr", { ARM_BANKEDREG_LR_USR }, 0x6 }, // 7
+  { "r10_fiq", { ARM_BANKEDREG_R10_FIQ }, 0xA }, // 8
+  { "r10_usr", { ARM_BANKEDREG_R10_USR }, 0x2 }, // 9
+  { "r11_fiq", { ARM_BANKEDREG_R11_FIQ }, 0xB }, // 10
+  { "r11_usr", { ARM_BANKEDREG_R11_USR }, 0x3 }, // 11
+  { "r12_fiq", { ARM_BANKEDREG_R12_FIQ }, 0xC }, // 12
+  { "r12_usr", { ARM_BANKEDREG_R12_USR }, 0x4 }, // 13
+  { "r8_fiq", { ARM_BANKEDREG_R8_FIQ }, 0x8 }, // 14
+  { "r8_usr", { ARM_BANKEDREG_R8_USR }, 0x0 }, // 15
+  { "r9_fiq", { ARM_BANKEDREG_R9_FIQ }, 0x9 }, // 16
+  { "r9_usr", { ARM_BANKEDREG_R9_USR }, 0x1 }, // 17
+  { "spsr_abt", { ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18
+  { "spsr_fiq", { ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19
+  { "spsr_hyp", { ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20
+  { "spsr_irq", { ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21
+  { "spsr_mon", { ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22
+  { "spsr_svc", { ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23
+  { "spsr_und", { ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24
+  { "sp_abt", { ARM_BANKEDREG_SP_ABT }, 0x15 }, // 25
+  { "sp_fiq", { ARM_BANKEDREG_SP_FIQ }, 0xD }, // 26
+  { "sp_hyp", { ARM_BANKEDREG_SP_HYP }, 0x1F }, // 27
+  { "sp_irq", { ARM_BANKEDREG_SP_IRQ }, 0x11 }, // 28
+  { "sp_mon", { ARM_BANKEDREG_SP_MON }, 0x1D }, // 29
+  { "sp_svc", { ARM_BANKEDREG_SP_SVC }, 0x13 }, // 30
+  { "sp_und", { ARM_BANKEDREG_SP_UND }, 0x17 }, // 31
+  { "sp_usr", { ARM_BANKEDREG_SP_USR }, 0x5 }, // 32
   };
 
-  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
-  if (i == -1)
-    return NULL;
-  else
-    return &MClassSysRegsList[Index[i].index];
-}
-
-const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
-{
-  unsigned int i;
-  static const struct IndexType Index[] = {
-    { 0x400, 0 },
-    { 0x401, 2 },
-    { 0x402, 4 },
-    { 0x403, 6 },
-    { 0x800, 8 },
-    { 0x801, 10 },
-    { 0x802, 12 },
-    { 0x803, 14 },
-    { 0x805, 16 },
-    { 0x806, 17 },
-    { 0x807, 18 },
-    { 0x808, 19 },
-    { 0x809, 20 },
-    { 0x80A, 21 },
-    { 0x80B, 22 },
-    { 0x810, 23 },
-    { 0x811, 24 },
-    { 0x812, 25 },
-    { 0x813, 26 },
-    { 0x814, 27 },
-    { 0x888, 28 },
-    { 0x889, 29 },
-    { 0x88A, 30 },
-    { 0x88B, 31 },
-    { 0x890, 32 },
-    { 0x891, 33 },
-    { 0x893, 34 },
-    { 0x894, 35 },
-    { 0x898, 36 },
-    { 0xC00, 1 },
-    { 0xC01, 3 },
-    { 0xC02, 5 },
-    { 0xC03, 7 },
-    { 0x1800, 9 },
-    { 0x1801, 11 },
-    { 0x1802, 13 },
-    { 0x1803, 15 },
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name) {
+  static const struct IndexTypeStr Index[] = {
+    { "ELR_HYP", 0 },
+    { "LR_ABT", 1 },
+    { "LR_FIQ", 2 },
+    { "LR_IRQ", 3 },
+    { "LR_MON", 4 },
+    { "LR_SVC", 5 },
+    { "LR_UND", 6 },
+    { "LR_USR", 7 },
+    { "R10_FIQ", 8 },
+    { "R10_USR", 9 },
+    { "R11_FIQ", 10 },
+    { "R11_USR", 11 },
+    { "R12_FIQ", 12 },
+    { "R12_USR", 13 },
+    { "R8_FIQ", 14 },
+    { "R8_USR", 15 },
+    { "R9_FIQ", 16 },
+    { "R9_USR", 17 },
+    { "SPSR_ABT", 18 },
+    { "SPSR_FIQ", 19 },
+    { "SPSR_HYP", 20 },
+    { "SPSR_IRQ", 21 },
+    { "SPSR_MON", 22 },
+    { "SPSR_SVC", 23 },
+    { "SPSR_UND", 24 },
+    { "SP_ABT", 25 },
+    { "SP_FIQ", 26 },
+    { "SP_HYP", 27 },
+    { "SP_IRQ", 28 },
+    { "SP_MON", 29 },
+    { "SP_SVC", 30 },
+    { "SP_UND", 31 },
+    { "SP_USR", 32 },
   };
 
-  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
-  if (i == -1)
-    return NULL;
-  else
-    return &MClassSysRegsList[Index[i].index];
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   if (i == -1)
+      return NULL;
+   else
+      return &BankedRegsList[Index[i].index];
 }
 
-const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
-{
-  unsigned int i;
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding) {
   static const struct IndexType Index[] = {
-    { 0x0, 0 },
-    { 0x1, 1 },
-    { 0x2, 2 },
-    { 0x3, 3 },
-    { 0x4, 4 },
-    { 0x5, 5 },
-    { 0x6, 6 },
-    { 0x8, 7 },
-    { 0x9, 8 },
-    { 0xA, 9 },
+    { 0x0, 15 },
+    { 0x1, 17 },
+    { 0x2, 9 },
+    { 0x3, 11 },
+    { 0x4, 13 },
+    { 0x5, 32 },
+    { 0x6, 7 },
+    { 0x8, 14 },
+    { 0x9, 16 },
+    { 0xA, 8 },
     { 0xB, 10 },
-    { 0xC, 11 },
-    { 0xD, 12 },
-    { 0xE, 13 },
-    { 0x10, 14 },
-    { 0x11, 15 },
-    { 0x12, 16 },
-    { 0x13, 17 },
-    { 0x14, 18 },
-    { 0x15, 19 },
-    { 0x16, 20 },
-    { 0x17, 21 },
-    { 0x1C, 22 },
-    { 0x1D, 23 },
-    { 0x1E, 24 },
-    { 0x1F, 25 },
-    { 0x2E, 26 },
-    { 0x30, 27 },
-    { 0x32, 28 },
-    { 0x34, 29 },
-    { 0x36, 30 },
-    { 0x3C, 31 },
-    { 0x3E, 32 },
+    { 0xC, 12 },
+    { 0xD, 26 },
+    { 0xE, 2 },
+    { 0x10, 3 },
+    { 0x11, 28 },
+    { 0x12, 5 },
+    { 0x13, 30 },
+    { 0x14, 1 },
+    { 0x15, 25 },
+    { 0x16, 6 },
+    { 0x17, 31 },
+    { 0x1C, 4 },
+    { 0x1D, 29 },
+    { 0x1E, 0 },
+    { 0x1F, 27 },
+    { 0x2E, 19 },
+    { 0x30, 21 },
+    { 0x32, 23 },
+    { 0x34, 18 },
+    { 0x36, 24 },
+    { 0x3C, 22 },
+    { 0x3E, 20 },
   };
 
-  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
-  if (i == -1)
-    return NULL;
-  else
-    return &BankedRegsList[Index[i].index];
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   if (i == -1)
+      return NULL;
+   else
+      return &BankedRegsList[Index[i].index];
 }
 
+#endif
+
+#ifdef GET_MCLASSSYSREG_IMPL
+static const ARMSysReg_MClassSysReg MClassSysRegsList[] = {
+  { "apsr", { ARM_MCLASSSYSREG_APSR }, 0x800, 0x100, 0x800,  {0}  }, // 0
+  { "apsr_g", { ARM_MCLASSSYSREG_APSR_G }, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 1
+  { "apsr_nzcvq", { ARM_MCLASSSYSREG_APSR_NZCVQ }, 0x1800, 0x200, 0x800,  {0}  }, // 2
+  { "apsr_nzcvqg", { ARM_MCLASSSYSREG_APSR_NZCVQG }, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 3
+  { "basepri", { ARM_MCLASSSYSREG_BASEPRI }, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 4
+  { "basepri_max", { ARM_MCLASSSYSREG_BASEPRI_MAX }, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 5
+  { "basepri_ns", { ARM_MCLASSSYSREG_BASEPRI_NS }, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 6
+  { "control", { ARM_MCLASSSYSREG_CONTROL }, 0x814, 0x114, 0x814,  {0}  }, // 7
+  { "control_ns", { ARM_MCLASSSYSREG_CONTROL_NS }, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 8
+  { "eapsr", { ARM_MCLASSSYSREG_EAPSR }, 0x802, 0x102, 0x802,  {0}  }, // 9
+  { "eapsr_g", { ARM_MCLASSSYSREG_EAPSR_G }, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 10
+  { "eapsr_nzcvq", { ARM_MCLASSSYSREG_EAPSR_NZCVQ }, 0x1802, 0x202, 0x802,  {0}  }, // 11
+  { "eapsr_nzcvqg", { ARM_MCLASSSYSREG_EAPSR_NZCVQG }, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 12
+  { "epsr", { ARM_MCLASSSYSREG_EPSR }, 0x806, 0x106, 0x806,  {0}  }, // 13
+  { "faultmask", { ARM_MCLASSSYSREG_FAULTMASK }, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 14
+  { "faultmask_ns", { ARM_MCLASSSYSREG_FAULTMASK_NS }, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 15
+  { "iapsr", { ARM_MCLASSSYSREG_IAPSR }, 0x801, 0x101, 0x801,  {0}  }, // 16
+  { "iapsr_g", { ARM_MCLASSSYSREG_IAPSR_G }, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 17
+  { "iapsr_nzcvq", { ARM_MCLASSSYSREG_IAPSR_NZCVQ }, 0x1801, 0x201, 0x801,  {0}  }, // 18
+  { "iapsr_nzcvqg", { ARM_MCLASSSYSREG_IAPSR_NZCVQG }, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 19
+  { "iepsr", { ARM_MCLASSSYSREG_IEPSR }, 0x807, 0x107, 0x807,  {0}  }, // 20
+  { "ipsr", { ARM_MCLASSSYSREG_IPSR }, 0x805, 0x105, 0x805,  {0}  }, // 21
+  { "msp", { ARM_MCLASSSYSREG_MSP }, 0x808, 0x108, 0x808,  {0}  }, // 22
+  { "msplim", { ARM_MCLASSSYSREG_MSPLIM }, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 23
+  { "msplim_ns", { ARM_MCLASSSYSREG_MSPLIM_NS }, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 24
+  { "msp_ns", { ARM_MCLASSSYSREG_MSP_NS }, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 25
+  { "pac_key_p_0", { ARM_MCLASSSYSREG_PAC_KEY_P_0 }, 0x820, 0x120, 0x820,  {ARM_FeaturePACBTI}  }, // 26
+  { "pac_key_p_0_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_0_NS }, 0x8A0, 0x1A0, 0x8A0,  {ARM_FeaturePACBTI}  }, // 27
+  { "pac_key_p_1", { ARM_MCLASSSYSREG_PAC_KEY_P_1 }, 0x821, 0x121, 0x821,  {ARM_FeaturePACBTI}  }, // 28
+  { "pac_key_p_1_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_1_NS }, 0x8A1, 0x1A1, 0x8A1,  {ARM_FeaturePACBTI}  }, // 29
+  { "pac_key_p_2", { ARM_MCLASSSYSREG_PAC_KEY_P_2 }, 0x822, 0x122, 0x822,  {ARM_FeaturePACBTI}  }, // 30
+  { "pac_key_p_2_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_2_NS }, 0x8A2, 0x1A2, 0x8A2,  {ARM_FeaturePACBTI}  }, // 31
+  { "pac_key_p_3", { ARM_MCLASSSYSREG_PAC_KEY_P_3 }, 0x823, 0x123, 0x823,  {ARM_FeaturePACBTI}  }, // 32
+  { "pac_key_p_3_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_3_NS }, 0x8A3, 0x1A3, 0x8A3,  {ARM_FeaturePACBTI}  }, // 33
+  { "pac_key_u_0", { ARM_MCLASSSYSREG_PAC_KEY_U_0 }, 0x824, 0x124, 0x824,  {ARM_FeaturePACBTI}  }, // 34
+  { "pac_key_u_0_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_0_NS }, 0x8A4, 0x1A4, 0x8A4,  {ARM_FeaturePACBTI}  }, // 35
+  { "pac_key_u_1", { ARM_MCLASSSYSREG_PAC_KEY_U_1 }, 0x825, 0x125, 0x825,  {ARM_FeaturePACBTI}  }, // 36
+  { "pac_key_u_1_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_1_NS }, 0x8A5, 0x1A5, 0x8A5,  {ARM_FeaturePACBTI}  }, // 37
+  { "pac_key_u_2", { ARM_MCLASSSYSREG_PAC_KEY_U_2 }, 0x826, 0x126, 0x826,  {ARM_FeaturePACBTI}  }, // 38
+  { "pac_key_u_2_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_2_NS }, 0x8A6, 0x1A6, 0x8A6,  {ARM_FeaturePACBTI}  }, // 39
+  { "pac_key_u_3", { ARM_MCLASSSYSREG_PAC_KEY_U_3 }, 0x827, 0x127, 0x827,  {ARM_FeaturePACBTI}  }, // 40
+  { "pac_key_u_3_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_3_NS }, 0x8A7, 0x1A7, 0x8A7,  {ARM_FeaturePACBTI}  }, // 41
+  { "primask", { ARM_MCLASSSYSREG_PRIMASK }, 0x810, 0x110, 0x810,  {0}  }, // 42
+  { "primask_ns", { ARM_MCLASSSYSREG_PRIMASK_NS }, 0x890, 0x190, 0x890,  {0}  }, // 43
+  { "psp", { ARM_MCLASSSYSREG_PSP }, 0x809, 0x109, 0x809,  {0}  }, // 44
+  { "psplim", { ARM_MCLASSSYSREG_PSPLIM }, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 45
+  { "psplim_ns", { ARM_MCLASSSYSREG_PSPLIM_NS }, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 46
+  { "psp_ns", { ARM_MCLASSSYSREG_PSP_NS }, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 47
+  { "sp_ns", { ARM_MCLASSSYSREG_SP_NS }, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 48
+  { "xpsr", { ARM_MCLASSSYSREG_XPSR }, 0x803, 0x103, 0x803,  {0}  }, // 49
+  { "xpsr_g", { ARM_MCLASSSYSREG_XPSR_G }, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 50
+  { "xpsr_nzcvq", { ARM_MCLASSSYSREG_XPSR_NZCVQ }, 0x1803, 0x203, 0x803,  {0}  }, // 51
+  { "xpsr_nzcvqg", { ARM_MCLASSSYSREG_XPSR_NZCVQG }, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 52
+  };
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name) {
+  static const struct IndexTypeStr Index[] = {
+    { "APSR", 0 },
+    { "APSR_G", 1 },
+    { "APSR_NZCVQ", 2 },
+    { "APSR_NZCVQG", 3 },
+    { "BASEPRI", 4 },
+    { "BASEPRI_MAX", 5 },
+    { "BASEPRI_NS", 6 },
+    { "CONTROL", 7 },
+    { "CONTROL_NS", 8 },
+    { "EAPSR", 9 },
+    { "EAPSR_G", 10 },
+    { "EAPSR_NZCVQ", 11 },
+    { "EAPSR_NZCVQG", 12 },
+    { "EPSR", 13 },
+    { "FAULTMASK", 14 },
+    { "FAULTMASK_NS", 15 },
+    { "IAPSR", 16 },
+    { "IAPSR_G", 17 },
+    { "IAPSR_NZCVQ", 18 },
+    { "IAPSR_NZCVQG", 19 },
+    { "IEPSR", 20 },
+    { "IPSR", 21 },
+    { "MSP", 22 },
+    { "MSPLIM", 23 },
+    { "MSPLIM_NS", 24 },
+    { "MSP_NS", 25 },
+    { "PAC_KEY_P_0", 26 },
+    { "PAC_KEY_P_0_NS", 27 },
+    { "PAC_KEY_P_1", 28 },
+    { "PAC_KEY_P_1_NS", 29 },
+    { "PAC_KEY_P_2", 30 },
+    { "PAC_KEY_P_2_NS", 31 },
+    { "PAC_KEY_P_3", 32 },
+    { "PAC_KEY_P_3_NS", 33 },
+    { "PAC_KEY_U_0", 34 },
+    { "PAC_KEY_U_0_NS", 35 },
+    { "PAC_KEY_U_1", 36 },
+    { "PAC_KEY_U_1_NS", 37 },
+    { "PAC_KEY_U_2", 38 },
+    { "PAC_KEY_U_2_NS", 39 },
+    { "PAC_KEY_U_3", 40 },
+    { "PAC_KEY_U_3_NS", 41 },
+    { "PRIMASK", 42 },
+    { "PRIMASK_NS", 43 },
+    { "PSP", 44 },
+    { "PSPLIM", 45 },
+    { "PSPLIM_NS", 46 },
+    { "PSP_NS", 47 },
+    { "SP_NS", 48 },
+    { "XPSR", 49 },
+    { "XPSR_G", 50 },
+    { "XPSR_NZCVQ", 51 },
+    { "XPSR_NZCVQG", 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) {
+  static const struct IndexType Index[] = {
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x801, 16 },
+    { 0x802, 9 },
+    { 0x803, 49 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+    { 0x1800, 2 },
+    { 0x1801, 18 },
+    { 0x1802, 11 },
+    { 0x1803, 51 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M1Encoding12);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) {
+  static const struct IndexType Index[] = {
+    { 0x0, 1 },
+    { 0x1, 17 },
+    { 0x2, 10 },
+    { 0x3, 50 },
+    { 0x100, 0 },
+    { 0x101, 16 },
+    { 0x102, 9 },
+    { 0x103, 49 },
+    { 0x105, 21 },
+    { 0x106, 13 },
+    { 0x107, 20 },
+    { 0x108, 22 },
+    { 0x109, 44 },
+    { 0x10A, 23 },
+    { 0x10B, 45 },
+    { 0x110, 42 },
+    { 0x111, 4 },
+    { 0x112, 5 },
+    { 0x113, 14 },
+    { 0x114, 7 },
+    { 0x120, 26 },
+    { 0x121, 28 },
+    { 0x122, 30 },
+    { 0x123, 32 },
+    { 0x124, 34 },
+    { 0x125, 36 },
+    { 0x126, 38 },
+    { 0x127, 40 },
+    { 0x188, 25 },
+    { 0x189, 47 },
+    { 0x18A, 24 },
+    { 0x18B, 46 },
+    { 0x190, 43 },
+    { 0x191, 6 },
+    { 0x193, 15 },
+    { 0x194, 8 },
+    { 0x198, 48 },
+    { 0x1A0, 27 },
+    { 0x1A1, 29 },
+    { 0x1A2, 31 },
+    { 0x1A3, 33 },
+    { 0x1A4, 35 },
+    { 0x1A5, 37 },
+    { 0x1A6, 39 },
+    { 0x1A7, 41 },
+    { 0x200, 2 },
+    { 0x201, 18 },
+    { 0x202, 11 },
+    { 0x203, 51 },
+    { 0x300, 3 },
+    { 0x301, 19 },
+    { 0x302, 12 },
+    { 0x303, 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M2M3Encoding8);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding) {
+  static const struct IndexType Index[] = {
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x800, 2 },
+    { 0x801, 16 },
+    { 0x801, 18 },
+    { 0x802, 9 },
+    { 0x802, 11 },
+    { 0x803, 49 },
+    { 0x803, 51 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+#endif
+
+#undef GET_BANKEDREG_DECL
+#undef GET_MCLASSSYSREG_DECL
diff --git a/arch/ARM/ARMInsnEnum.inc b/arch/ARM/ARMInsnEnum.inc
new file mode 100644
index 000000000..6a5fb62cc
--- /dev/null
+++ b/arch/ARM/ARMInsnEnum.inc
@@ -0,0 +1,682 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+/* Auto generated file. Do not edit. */
+/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+  ARM_INS___BRKDIV0,
+  ARM_INS_ADC,
+  ARM_INS_ADD,
+  ARM_INS_ADDW,
+  ARM_INS_ADR,
+  ARM_INS_AESD,
+  ARM_INS_AESE,
+  ARM_INS_AESIMC,
+  ARM_INS_AESMC,
+  ARM_INS_AND,
+  ARM_INS_ASR,
+  ARM_INS_ASRL,
+  ARM_INS_AUT,
+  ARM_INS_AUTG,
+  ARM_INS_B,
+  ARM_INS_BF,
+  ARM_INS_BFC,
+  ARM_INS_BFCSEL,
+  ARM_INS_BFI,
+  ARM_INS_BFL,
+  ARM_INS_BFLX,
+  ARM_INS_BFX,
+  ARM_INS_BIC,
+  ARM_INS_BKPT,
+  ARM_INS_BL,
+  ARM_INS_BLX,
+  ARM_INS_BLXNS,
+  ARM_INS_BTI,
+  ARM_INS_BX,
+  ARM_INS_BXAUT,
+  ARM_INS_BXJ,
+  ARM_INS_BXNS,
+  ARM_INS_CBNZ,
+  ARM_INS_CBZ,
+  ARM_INS_CDP,
+  ARM_INS_CDP2,
+  ARM_INS_CINC,
+  ARM_INS_CINV,
+  ARM_INS_CLRBHB,
+  ARM_INS_CLREX,
+  ARM_INS_CLRM,
+  ARM_INS_CLZ,
+  ARM_INS_CMN,
+  ARM_INS_CMP,
+  ARM_INS_CNEG,
+  ARM_INS_CPS,
+  ARM_INS_CRC32B,
+  ARM_INS_CRC32CB,
+  ARM_INS_CRC32CH,
+  ARM_INS_CRC32CW,
+  ARM_INS_CRC32H,
+  ARM_INS_CRC32W,
+  ARM_INS_CSDB,
+  ARM_INS_CSEL,
+  ARM_INS_CSET,
+  ARM_INS_CSETM,
+  ARM_INS_CSINC,
+  ARM_INS_CSINV,
+  ARM_INS_CSNEG,
+  ARM_INS_CX1,
+  ARM_INS_CX1A,
+  ARM_INS_CX1D,
+  ARM_INS_CX1DA,
+  ARM_INS_CX2,
+  ARM_INS_CX2A,
+  ARM_INS_CX2D,
+  ARM_INS_CX2DA,
+  ARM_INS_CX3,
+  ARM_INS_CX3A,
+  ARM_INS_CX3D,
+  ARM_INS_CX3DA,
+  ARM_INS_DBG,
+  ARM_INS_DCPS1,
+  ARM_INS_DCPS2,
+  ARM_INS_DCPS3,
+  ARM_INS_DFB,
+  ARM_INS_DLS,
+  ARM_INS_DLSTP,
+  ARM_INS_DMB,
+  ARM_INS_DSB,
+  ARM_INS_EOR,
+  ARM_INS_ERET,
+  ARM_INS_ESB,
+  ARM_INS_FADDD,
+  ARM_INS_FADDS,
+  ARM_INS_FCMPZD,
+  ARM_INS_FCMPZS,
+  ARM_INS_FCONSTD,
+  ARM_INS_FCONSTS,
+  ARM_INS_FLDMDBX,
+  ARM_INS_FLDMIAX,
+  ARM_INS_FMDHR,
+  ARM_INS_FMDLR,
+  ARM_INS_FMSTAT,
+  ARM_INS_FSTMDBX,
+  ARM_INS_FSTMIAX,
+  ARM_INS_FSUBD,
+  ARM_INS_FSUBS,
+  ARM_INS_HINT,
+  ARM_INS_HLT,
+  ARM_INS_HVC,
+  ARM_INS_ISB,
+  ARM_INS_IT,
+  ARM_INS_LCTP,
+  ARM_INS_LDA,
+  ARM_INS_LDAB,
+  ARM_INS_LDAEX,
+  ARM_INS_LDAEXB,
+  ARM_INS_LDAEXD,
+  ARM_INS_LDAEXH,
+  ARM_INS_LDAH,
+  ARM_INS_LDC,
+  ARM_INS_LDC2,
+  ARM_INS_LDC2L,
+  ARM_INS_LDCL,
+  ARM_INS_LDM,
+  ARM_INS_LDMDA,
+  ARM_INS_LDMDB,
+  ARM_INS_LDMIB,
+  ARM_INS_LDR,
+  ARM_INS_LDRB,
+  ARM_INS_LDRBT,
+  ARM_INS_LDRD,
+  ARM_INS_LDREX,
+  ARM_INS_LDREXB,
+  ARM_INS_LDREXD,
+  ARM_INS_LDREXH,
+  ARM_INS_LDRH,
+  ARM_INS_LDRHT,
+  ARM_INS_LDRSB,
+  ARM_INS_LDRSBT,
+  ARM_INS_LDRSH,
+  ARM_INS_LDRSHT,
+  ARM_INS_LDRT,
+  ARM_INS_LE,
+  ARM_INS_LETP,
+  ARM_INS_LSL,
+  ARM_INS_LSLL,
+  ARM_INS_LSR,
+  ARM_INS_LSRL,
+  ARM_INS_MCR,
+  ARM_INS_MCR2,
+  ARM_INS_MCRR,
+  ARM_INS_MCRR2,
+  ARM_INS_MLA,
+  ARM_INS_MLS,
+  ARM_INS_MOV,
+  ARM_INS_MOVS,
+  ARM_INS_MOVT,
+  ARM_INS_MOVW,
+  ARM_INS_MRC,
+  ARM_INS_MRC2,
+  ARM_INS_MRRC,
+  ARM_INS_MRRC2,
+  ARM_INS_MRS,
+  ARM_INS_MSR,
+  ARM_INS_MUL,
+  ARM_INS_MVN,
+  ARM_INS_NEG,
+  ARM_INS_NOP,
+  ARM_INS_ORN,
+  ARM_INS_ORR,
+  ARM_INS_PAC,
+  ARM_INS_PACBTI,
+  ARM_INS_PACG,
+  ARM_INS_PKHBT,
+  ARM_INS_PKHTB,
+  ARM_INS_PLD,
+  ARM_INS_PLDW,
+  ARM_INS_PLI,
+  ARM_INS_POP,
+  ARM_INS_PSSBB,
+  ARM_INS_PUSH,
+  ARM_INS_QADD,
+  ARM_INS_QADD16,
+  ARM_INS_QADD8,
+  ARM_INS_QASX,
+  ARM_INS_QDADD,
+  ARM_INS_QDSUB,
+  ARM_INS_QSAX,
+  ARM_INS_QSUB,
+  ARM_INS_QSUB16,
+  ARM_INS_QSUB8,
+  ARM_INS_RBIT,
+  ARM_INS_REV,
+  ARM_INS_REV16,
+  ARM_INS_REVSH,
+  ARM_INS_RFEDA,
+  ARM_INS_RFEDB,
+  ARM_INS_RFEIA,
+  ARM_INS_RFEIB,
+  ARM_INS_ROR,
+  ARM_INS_RRX,
+  ARM_INS_RSB,
+  ARM_INS_RSC,
+  ARM_INS_SADD16,
+  ARM_INS_SADD8,
+  ARM_INS_SASX,
+  ARM_INS_SB,
+  ARM_INS_SBC,
+  ARM_INS_SBFX,
+  ARM_INS_SDIV,
+  ARM_INS_SEL,
+  ARM_INS_SETEND,
+  ARM_INS_SETPAN,
+  ARM_INS_SEV,
+  ARM_INS_SEVL,
+  ARM_INS_SG,
+  ARM_INS_SHA1C,
+  ARM_INS_SHA1H,
+  ARM_INS_SHA1M,
+  ARM_INS_SHA1P,
+  ARM_INS_SHA1SU0,
+  ARM_INS_SHA1SU1,
+  ARM_INS_SHA256H,
+  ARM_INS_SHA256H2,
+  ARM_INS_SHA256SU0,
+  ARM_INS_SHA256SU1,
+  ARM_INS_SHADD16,
+  ARM_INS_SHADD8,
+  ARM_INS_SHASX,
+  ARM_INS_SHSAX,
+  ARM_INS_SHSUB16,
+  ARM_INS_SHSUB8,
+  ARM_INS_SMC,
+  ARM_INS_SMLABB,
+  ARM_INS_SMLABT,
+  ARM_INS_SMLAD,
+  ARM_INS_SMLADX,
+  ARM_INS_SMLAL,
+  ARM_INS_SMLALBB,
+  ARM_INS_SMLALBT,
+  ARM_INS_SMLALD,
+  ARM_INS_SMLALDX,
+  ARM_INS_SMLALTB,
+  ARM_INS_SMLALTT,
+  ARM_INS_SMLATB,
+  ARM_INS_SMLATT,
+  ARM_INS_SMLAWB,
+  ARM_INS_SMLAWT,
+  ARM_INS_SMLSD,
+  ARM_INS_SMLSDX,
+  ARM_INS_SMLSLD,
+  ARM_INS_SMLSLDX,
+  ARM_INS_SMMLA,
+  ARM_INS_SMMLAR,
+  ARM_INS_SMMLS,
+  ARM_INS_SMMLSR,
+  ARM_INS_SMMUL,
+  ARM_INS_SMMULR,
+  ARM_INS_SMUAD,
+  ARM_INS_SMUADX,
+  ARM_INS_SMULBB,
+  ARM_INS_SMULBT,
+  ARM_INS_SMULL,
+  ARM_INS_SMULTB,
+  ARM_INS_SMULTT,
+  ARM_INS_SMULWB,
+  ARM_INS_SMULWT,
+  ARM_INS_SMUSD,
+  ARM_INS_SMUSDX,
+  ARM_INS_SQRSHR,
+  ARM_INS_SQRSHRL,
+  ARM_INS_SQSHL,
+  ARM_INS_SQSHLL,
+  ARM_INS_SRSDA,
+  ARM_INS_SRSDB,
+  ARM_INS_SRSHR,
+  ARM_INS_SRSHRL,
+  ARM_INS_SRSIA,
+  ARM_INS_SRSIB,
+  ARM_INS_SSAT,
+  ARM_INS_SSAT16,
+  ARM_INS_SSAX,
+  ARM_INS_SSBB,
+  ARM_INS_SSUB16,
+  ARM_INS_SSUB8,
+  ARM_INS_STC,
+  ARM_INS_STC2,
+  ARM_INS_STC2L,
+  ARM_INS_STCL,
+  ARM_INS_STL,
+  ARM_INS_STLB,
+  ARM_INS_STLEX,
+  ARM_INS_STLEXB,
+  ARM_INS_STLEXD,
+  ARM_INS_STLEXH,
+  ARM_INS_STLH,
+  ARM_INS_STM,
+  ARM_INS_STMDA,
+  ARM_INS_STMDB,
+  ARM_INS_STMIB,
+  ARM_INS_STR,
+  ARM_INS_STRB,
+  ARM_INS_STRBT,
+  ARM_INS_STRD,
+  ARM_INS_STREX,
+  ARM_INS_STREXB,
+  ARM_INS_STREXD,
+  ARM_INS_STREXH,
+  ARM_INS_STRH,
+  ARM_INS_STRHT,
+  ARM_INS_STRT,
+  ARM_INS_SUB,
+  ARM_INS_SUBS,
+  ARM_INS_SUBW,
+  ARM_INS_SVC,
+  ARM_INS_SWP,
+  ARM_INS_SWPB,
+  ARM_INS_SXTAB,
+  ARM_INS_SXTAB16,
+  ARM_INS_SXTAH,
+  ARM_INS_SXTB,
+  ARM_INS_SXTB16,
+  ARM_INS_SXTH,
+  ARM_INS_TBB,
+  ARM_INS_TBH,
+  ARM_INS_TEQ,
+  ARM_INS_TRAP,
+  ARM_INS_TSB,
+  ARM_INS_TST,
+  ARM_INS_TT,
+  ARM_INS_TTA,
+  ARM_INS_TTAT,
+  ARM_INS_TTT,
+  ARM_INS_UADD16,
+  ARM_INS_UADD8,
+  ARM_INS_UASX,
+  ARM_INS_UBFX,
+  ARM_INS_UDF,
+  ARM_INS_UDIV,
+  ARM_INS_UHADD16,
+  ARM_INS_UHADD8,
+  ARM_INS_UHASX,
+  ARM_INS_UHSAX,
+  ARM_INS_UHSUB16,
+  ARM_INS_UHSUB8,
+  ARM_INS_UMAAL,
+  ARM_INS_UMLAL,
+  ARM_INS_UMULL,
+  ARM_INS_UQADD16,
+  ARM_INS_UQADD8,
+  ARM_INS_UQASX,
+  ARM_INS_UQRSHL,
+  ARM_INS_UQRSHLL,
+  ARM_INS_UQSAX,
+  ARM_INS_UQSHL,
+  ARM_INS_UQSHLL,
+  ARM_INS_UQSUB16,
+  ARM_INS_UQSUB8,
+  ARM_INS_URSHR,
+  ARM_INS_URSHRL,
+  ARM_INS_USAD8,
+  ARM_INS_USADA8,
+  ARM_INS_USAT,
+  ARM_INS_USAT16,
+  ARM_INS_USAX,
+  ARM_INS_USUB16,
+  ARM_INS_USUB8,
+  ARM_INS_UXTAB,
+  ARM_INS_UXTAB16,
+  ARM_INS_UXTAH,
+  ARM_INS_UXTB,
+  ARM_INS_UXTB16,
+  ARM_INS_UXTH,
+  ARM_INS_VABA,
+  ARM_INS_VABAL,
+  ARM_INS_VABAV,
+  ARM_INS_VABD,
+  ARM_INS_VABDL,
+  ARM_INS_VABS,
+  ARM_INS_VACGE,
+  ARM_INS_VACGT,
+  ARM_INS_VACLE,
+  ARM_INS_VACLT,
+  ARM_INS_VADC,
+  ARM_INS_VADCI,
+  ARM_INS_VADD,
+  ARM_INS_VADDHN,
+  ARM_INS_VADDL,
+  ARM_INS_VADDLV,
+  ARM_INS_VADDLVA,
+  ARM_INS_VADDV,
+  ARM_INS_VADDVA,
+  ARM_INS_VADDW,
+  ARM_INS_VAND,
+  ARM_INS_VBIC,
+  ARM_INS_VBIF,
+  ARM_INS_VBIT,
+  ARM_INS_VBRSR,
+  ARM_INS_VBSL,
+  ARM_INS_VCADD,
+  ARM_INS_VCEQ,
+  ARM_INS_VCGE,
+  ARM_INS_VCGT,
+  ARM_INS_VCLE,
+  ARM_INS_VCLS,
+  ARM_INS_VCLT,
+  ARM_INS_VCLZ,
+  ARM_INS_VCMLA,
+  ARM_INS_VCMP,
+  ARM_INS_VCMPE,
+  ARM_INS_VCMUL,
+  ARM_INS_VCNT,
+  ARM_INS_VCTP,
+  ARM_INS_VCVT,
+  ARM_INS_VCVTA,
+  ARM_INS_VCVTB,
+  ARM_INS_VCVTM,
+  ARM_INS_VCVTN,
+  ARM_INS_VCVTP,
+  ARM_INS_VCVTR,
+  ARM_INS_VCVTT,
+  ARM_INS_VCX1,
+  ARM_INS_VCX1A,
+  ARM_INS_VCX2,
+  ARM_INS_VCX2A,
+  ARM_INS_VCX3,
+  ARM_INS_VCX3A,
+  ARM_INS_VDDUP,
+  ARM_INS_VDIV,
+  ARM_INS_VDOT,
+  ARM_INS_VDUP,
+  ARM_INS_VDWDUP,
+  ARM_INS_VEOR,
+  ARM_INS_VEXT,
+  ARM_INS_VFMA,
+  ARM_INS_VFMAB,
+  ARM_INS_VFMAL,
+  ARM_INS_VFMAS,
+  ARM_INS_VFMAT,
+  ARM_INS_VFMS,
+  ARM_INS_VFMSL,
+  ARM_INS_VFNMA,
+  ARM_INS_VFNMS,
+  ARM_INS_VHADD,
+  ARM_INS_VHCADD,
+  ARM_INS_VHSUB,
+  ARM_INS_VIDUP,
+  ARM_INS_VINS,
+  ARM_INS_VIWDUP,
+  ARM_INS_VJCVT,
+  ARM_INS_VLD1,
+  ARM_INS_VLD2,
+  ARM_INS_VLD20,
+  ARM_INS_VLD21,
+  ARM_INS_VLD3,
+  ARM_INS_VLD4,
+  ARM_INS_VLD40,
+  ARM_INS_VLD41,
+  ARM_INS_VLD42,
+  ARM_INS_VLD43,
+  ARM_INS_VLDMDB,
+  ARM_INS_VLDMIA,
+  ARM_INS_VLDR,
+  ARM_INS_VLDRB,
+  ARM_INS_VLDRD,
+  ARM_INS_VLDRH,
+  ARM_INS_VLDRW,
+  ARM_INS_VLLDM,
+  ARM_INS_VLSTM,
+  ARM_INS_VMAX,
+  ARM_INS_VMAXA,
+  ARM_INS_VMAXAV,
+  ARM_INS_VMAXNM,
+  ARM_INS_VMAXNMA,
+  ARM_INS_VMAXNMAV,
+  ARM_INS_VMAXNMV,
+  ARM_INS_VMAXV,
+  ARM_INS_VMIN,
+  ARM_INS_VMINA,
+  ARM_INS_VMINAV,
+  ARM_INS_VMINNM,
+  ARM_INS_VMINNMA,
+  ARM_INS_VMINNMAV,
+  ARM_INS_VMINNMV,
+  ARM_INS_VMINV,
+  ARM_INS_VMLA,
+  ARM_INS_VMLADAV,
+  ARM_INS_VMLADAVA,
+  ARM_INS_VMLADAVAX,
+  ARM_INS_VMLADAVX,
+  ARM_INS_VMLAL,
+  ARM_INS_VMLALDAV,
+  ARM_INS_VMLALDAVA,
+  ARM_INS_VMLALDAVAX,
+  ARM_INS_VMLALDAVX,
+  ARM_INS_VMLALV,
+  ARM_INS_VMLALVA,
+  ARM_INS_VMLAS,
+  ARM_INS_VMLAV,
+  ARM_INS_VMLAVA,
+  ARM_INS_VMLS,
+  ARM_INS_VMLSDAV,
+  ARM_INS_VMLSDAVA,
+  ARM_INS_VMLSDAVAX,
+  ARM_INS_VMLSDAVX,
+  ARM_INS_VMLSL,
+  ARM_INS_VMLSLDAV,
+  ARM_INS_VMLSLDAVA,
+  ARM_INS_VMLSLDAVAX,
+  ARM_INS_VMLSLDAVX,
+  ARM_INS_VMMLA,
+  ARM_INS_VMOV,
+  ARM_INS_VMOVL,
+  ARM_INS_VMOVLB,
+  ARM_INS_VMOVLT,
+  ARM_INS_VMOVN,
+  ARM_INS_VMOVNB,
+  ARM_INS_VMOVNT,
+  ARM_INS_VMOVX,
+  ARM_INS_VMRS,
+  ARM_INS_VMSR,
+  ARM_INS_VMUL,
+  ARM_INS_VMULH,
+  ARM_INS_VMULL,
+  ARM_INS_VMULLB,
+  ARM_INS_VMULLT,
+  ARM_INS_VMVN,
+  ARM_INS_VNEG,
+  ARM_INS_VNMLA,
+  ARM_INS_VNMLS,
+  ARM_INS_VNMUL,
+  ARM_INS_VORN,
+  ARM_INS_VORR,
+  ARM_INS_VPADAL,
+  ARM_INS_VPADD,
+  ARM_INS_VPADDL,
+  ARM_INS_VPMAX,
+  ARM_INS_VPMIN,
+  ARM_INS_VPNOT,
+  ARM_INS_VPOP,
+  ARM_INS_VPSEL,
+  ARM_INS_VPST,
+  ARM_INS_VPT,
+  ARM_INS_VPUSH,
+  ARM_INS_VQABS,
+  ARM_INS_VQADD,
+  ARM_INS_VQDMLADH,
+  ARM_INS_VQDMLADHX,
+  ARM_INS_VQDMLAH,
+  ARM_INS_VQDMLAL,
+  ARM_INS_VQDMLASH,
+  ARM_INS_VQDMLSDH,
+  ARM_INS_VQDMLSDHX,
+  ARM_INS_VQDMLSL,
+  ARM_INS_VQDMULH,
+  ARM_INS_VQDMULL,
+  ARM_INS_VQDMULLB,
+  ARM_INS_VQDMULLT,
+  ARM_INS_VQMOVN,
+  ARM_INS_VQMOVNB,
+  ARM_INS_VQMOVNT,
+  ARM_INS_VQMOVUN,
+  ARM_INS_VQMOVUNB,
+  ARM_INS_VQMOVUNT,
+  ARM_INS_VQNEG,
+  ARM_INS_VQRDMLADH,
+  ARM_INS_VQRDMLADHX,
+  ARM_INS_VQRDMLAH,
+  ARM_INS_VQRDMLASH,
+  ARM_INS_VQRDMLSDH,
+  ARM_INS_VQRDMLSDHX,
+  ARM_INS_VQRDMLSH,
+  ARM_INS_VQRDMULH,
+  ARM_INS_VQRSHL,
+  ARM_INS_VQRSHRN,
+  ARM_INS_VQRSHRNB,
+  ARM_INS_VQRSHRNT,
+  ARM_INS_VQRSHRUN,
+  ARM_INS_VQRSHRUNB,
+  ARM_INS_VQRSHRUNT,
+  ARM_INS_VQSHL,
+  ARM_INS_VQSHLU,
+  ARM_INS_VQSHRN,
+  ARM_INS_VQSHRNB,
+  ARM_INS_VQSHRNT,
+  ARM_INS_VQSHRUN,
+  ARM_INS_VQSHRUNB,
+  ARM_INS_VQSHRUNT,
+  ARM_INS_VQSUB,
+  ARM_INS_VRADDHN,
+  ARM_INS_VRECPE,
+  ARM_INS_VRECPS,
+  ARM_INS_VREV16,
+  ARM_INS_VREV32,
+  ARM_INS_VREV64,
+  ARM_INS_VRHADD,
+  ARM_INS_VRINTA,
+  ARM_INS_VRINTM,
+  ARM_INS_VRINTN,
+  ARM_INS_VRINTP,
+  ARM_INS_VRINTR,
+  ARM_INS_VRINTX,
+  ARM_INS_VRINTZ,
+  ARM_INS_VRMLALDAVH,
+  ARM_INS_VRMLALDAVHA,
+  ARM_INS_VRMLALDAVHAX,
+  ARM_INS_VRMLALDAVHX,
+  ARM_INS_VRMLALVH,
+  ARM_INS_VRMLALVHA,
+  ARM_INS_VRMLSLDAVH,
+  ARM_INS_VRMLSLDAVHA,
+  ARM_INS_VRMLSLDAVHAX,
+  ARM_INS_VRMLSLDAVHX,
+  ARM_INS_VRMULH,
+  ARM_INS_VRSHL,
+  ARM_INS_VRSHR,
+  ARM_INS_VRSHRN,
+  ARM_INS_VRSHRNB,
+  ARM_INS_VRSHRNT,
+  ARM_INS_VRSQRTE,
+  ARM_INS_VRSQRTS,
+  ARM_INS_VRSRA,
+  ARM_INS_VRSUBHN,
+  ARM_INS_VSBC,
+  ARM_INS_VSBCI,
+  ARM_INS_VSCCLRM,
+  ARM_INS_VSDOT,
+  ARM_INS_VSELEQ,
+  ARM_INS_VSELGE,
+  ARM_INS_VSELGT,
+  ARM_INS_VSELVS,
+  ARM_INS_VSHL,
+  ARM_INS_VSHLC,
+  ARM_INS_VSHLL,
+  ARM_INS_VSHLLB,
+  ARM_INS_VSHLLT,
+  ARM_INS_VSHR,
+  ARM_INS_VSHRN,
+  ARM_INS_VSHRNB,
+  ARM_INS_VSHRNT,
+  ARM_INS_VSLI,
+  ARM_INS_VSMMLA,
+  ARM_INS_VSQRT,
+  ARM_INS_VSRA,
+  ARM_INS_VSRI,
+  ARM_INS_VST1,
+  ARM_INS_VST2,
+  ARM_INS_VST20,
+  ARM_INS_VST21,
+  ARM_INS_VST3,
+  ARM_INS_VST4,
+  ARM_INS_VST40,
+  ARM_INS_VST41,
+  ARM_INS_VST42,
+  ARM_INS_VST43,
+  ARM_INS_VSTMDB,
+  ARM_INS_VSTMIA,
+  ARM_INS_VSTR,
+  ARM_INS_VSTRB,
+  ARM_INS_VSTRD,
+  ARM_INS_VSTRH,
+  ARM_INS_VSTRW,
+  ARM_INS_VSUB,
+  ARM_INS_VSUBHN,
+  ARM_INS_VSUBL,
+  ARM_INS_VSUBW,
+  ARM_INS_VSUDOT,
+  ARM_INS_VSWP,
+  ARM_INS_VTBL,
+  ARM_INS_VTBX,
+  ARM_INS_VTRN,
+  ARM_INS_VTST,
+  ARM_INS_VUDOT,
+  ARM_INS_VUMMLA,
+  ARM_INS_VUSDOT,
+  ARM_INS_VUSMMLA,
+  ARM_INS_VUZP,
+  ARM_INS_VZIP,
+  ARM_INS_WFE,
+  ARM_INS_WFI,
+  ARM_INS_WLS,
+  ARM_INS_WLSTP,
+  ARM_INS_YIELD,
diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c
index 1db66ebff..5bc1e150a 100644
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
@@ -1,9 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
@@ -11,934 +24,396 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifdef CAPSTONE_HAS_ARM
-
-#include <stdio.h>	// DEBUG
+#include <capstone/platform.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
-#include <capstone/platform.h>
 
-#include "ARMInstPrinter.h"
+#include "../../Mapping.h"
+#include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "../../utils.h"
 #include "ARMAddressingModes.h"
 #include "ARMBaseInfo.h"
-#include "ARMDisassembler.h"
-#include "../../MCInst.h"
-#include "../../SStream.h"
-#include "../../MCRegisterInfo.h"
-#include "../../utils.h"
+#include "ARMDisassemblerExtension.h"
+#include "ARMInstPrinter.h"
+#include "ARMLinkage.h"
 #include "ARMMapping.h"
 
-#define GET_SUBTARGETINFO_ENUM
-#include "ARMGenSubtargetInfo.inc"
-
+#define GET_BANKEDREG_IMPL
 #include "ARMGenSystemRegister.inc"
 
-static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo);
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
 
-// Autogenerated by tblgen.
-static void printInstruction(MCInst *MI, SStream *O);
+#define DEBUG_TYPE "asm-printer"
+
+// Static function declarations. These are functions which have the same identifiers
+// over all architectures. Therefor they need to be static.
+static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
+							 unsigned PrintMethodIdx, SStream *O);
 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
-static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-
-static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
-static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O, bool AlwaysPrintImm0);
-static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
-static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-
-static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
-static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
-static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned);
-static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale);
-static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
-static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
-static void printT2AddrModeImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O, bool);
-static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
-static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
-static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
 static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
-static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
-static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
-static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
-static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
-static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
-static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
-static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
-static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
-static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-
-static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
-static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
-static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder);
-static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
-
-
-#ifndef CAPSTONE_DIET
-// copy & normalize access info
-static uint8_t get_op_access(cs_struct *h, unsigned int id, unsigned int index)
-{
-	const uint8_t *arr = ARM_get_op_access(h, id);
-
-	if (!arr || arr[index] == CS_AC_IGNORE)
-		return 0;
-
-	return arr[index];
-}
-#endif
-
-static void set_mem_access(MCInst *MI, bool status)
-{
-	if (MI->csh->detail != CS_OPT_ON)
-		return;
-
-	MI->csh->doing_mem = status;
-	if (status) {
-#ifndef CAPSTONE_DIET
-		uint8_t access;
-#endif
-
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_INVALID;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
-
-#ifndef CAPSTONE_DIET
-		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-		MI->ac_idx++;
-#endif
-	} else {
-		// done, create the next operand slot
-		MI->flat_insn->detail->arm.op_count++;
-	}
-}
-
-static void op_addImm(MCInst *MI, int v)
-{
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
-		MI->flat_insn->detail->arm.op_count++;
-	}
-}
-
-#define GET_INSTRINFO_ENUM
-#include "ARMGenInstrInfo.inc"
-
-static void printCustomAliasOperand(MCInst *MI,
-		unsigned OpIdx, unsigned PrintMethodIdx, SStream *OS);
+static void printRegName(SStream *OS, unsigned RegNo);
+static void printInst(MCInst *MI, SStream *O, void *info);
 
 #define PRINT_ALIAS_INSTR
 #include "ARMGenAsmWriter.inc"
-#include "ARMGenRegisterName.inc"
-#include "ARMGenRegisterName_digit.inc"
-
-void ARM_getRegName(cs_struct *handle, int value)
-{
-	if (value == CS_OPT_SYNTAX_NOREGNAME) {
-		handle->get_regname = getRegisterName_digit;
-		handle->reg_name = ARM_reg_name2;
-	} else {
-		handle->get_regname = getRegisterName;
-		handle->reg_name = ARM_reg_name;
-	}
-}
 
 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
 ///
 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
-static unsigned translateShiftImm(unsigned imm)
+unsigned translateShiftImm(unsigned imm)
 {
 	// lsr #32 and asr #32 exist, but should be encoded as a 0.
-	//assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
+
 	if (imm == 0)
 		return 32;
 	return imm;
 }
 
 /// Prints the shift value with an immediate value.
-static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm)
+static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc,
+							 unsigned ShImm, bool UseMarkup)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_RegImmShift, ShOpc, ShImm);
 	if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
 		return;
-
 	SStream_concat0(O, ", ");
 
-	//assert (!(ShOpc == ARM_AM_ror && !ShImm) && "Cannot have ror #0");
 	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
 
-	if (MI->csh->detail) {
-		if (MI->csh->doing_mem)
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)ShOpc;
-		else
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = (arm_shifter)ShOpc;
-	}
-
 	if (ShOpc != ARM_AM_rrx) {
 		SStream_concat0(O, " ");
-		SStream_concat(O, "#%u", translateShiftImm(ShImm));
-		if (MI->csh->detail) {
-			if (MI->csh->doing_mem)
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = translateShiftImm(ShImm);
-			else
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = translateShiftImm(ShImm);
-		}
+		if (getUseMarkup())
+			SStream_concat0(O, "<imm:");
+		SStream_concat(O, "%s%d", "#", translateShiftImm(ShImm));
+		if (getUseMarkup())
+			SStream_concat0(O, ">");
 	}
 }
 
-static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo)
+static void printRegName(SStream *OS, unsigned RegNo)
 {
-#ifndef CAPSTONE_DIET
-	SStream_concat0(OS, h->get_regname(RegNo));
-#endif
+	SStream_concat(OS, "%s%s", markup("<reg:"),
+				   getRegisterName(RegNo, ARM_NoRegAltName));
+	SStream_concat0(OS, markup(">"));
 }
 
-// TODO
-static const name_map insn_update_flgs[] = {
-	{ ARM_INS_CMN, "cmn" },
-	{ ARM_INS_CMP, "cmp" },
-	{ ARM_INS_TEQ, "teq" },
-	{ ARM_INS_TST, "tst" },
-
-	{ ARM_INS_ADC, "adcs" },
-	{ ARM_INS_ADD, "adds" },
-	{ ARM_INS_AND, "ands" },
-	{ ARM_INS_ASR, "asrs" },
-	{ ARM_INS_BIC, "bics" },
-	{ ARM_INS_EOR, "eors" },
-	{ ARM_INS_LSL, "lsls" },
-	{ ARM_INS_LSR, "lsrs" },
-	{ ARM_INS_MLA, "mlas" },
-	{ ARM_INS_MOV, "movs" },
-	{ ARM_INS_MUL, "muls" },
-	{ ARM_INS_MVN, "mvns" },
-	{ ARM_INS_ORN, "orns" },
-	{ ARM_INS_ORR, "orrs" },
-	{ ARM_INS_ROR, "rors" },
-	{ ARM_INS_RRX, "rrxs" },
-	{ ARM_INS_RSB, "rsbs" },
-	{ ARM_INS_RSC, "rscs" },
-	{ ARM_INS_SBC, "sbcs" },
-	{ ARM_INS_SMLAL, "smlals" },
-	{ ARM_INS_SMULL, "smulls" },
-	{ ARM_INS_SUB, "subs" },
-	{ ARM_INS_UMLAL, "umlals" },
-	{ ARM_INS_UMULL, "umulls" },
-
-	{ ARM_INS_UADD8, "uadd8" },
-};
-
-void ARM_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
+static void printInst(MCInst *MI, SStream *O, void *info)
 {
-	if (((cs_struct *)ud)->detail != CS_OPT_ON)
-		return;
-
-	// check if this insn requests write-back
-	if (mci->writeback || (strrchr(insn_asm, '!')) != NULL) {
-		insn->detail->arm.writeback = true;
-	} else if (mci->csh->mode & CS_MODE_THUMB) {
-		// handle some special instructions with writeback
-        //printf(">> Opcode = %u\n", mci->Opcode);
-		switch(mci->Opcode) {
-			default:
-				break;
-			case ARM_t2LDC2L_PRE:
-			case ARM_t2LDC2_PRE:
-			case ARM_t2LDCL_PRE:
-			case ARM_t2LDC_PRE:
-
-			case ARM_t2LDRB_PRE:
-			case ARM_t2LDRD_PRE:
-			case ARM_t2LDRH_PRE:
-			case ARM_t2LDRSB_PRE:
-			case ARM_t2LDRSH_PRE:
-			case ARM_t2LDR_PRE:
-
-			case ARM_t2STC2L_PRE:
-			case ARM_t2STC2_PRE:
-			case ARM_t2STCL_PRE:
-			case ARM_t2STC_PRE:
-
-			case ARM_t2STRB_PRE:
-			case ARM_t2STRD_PRE:
-			case ARM_t2STRH_PRE:
-			case ARM_t2STR_PRE:
-				insn->detail->arm.writeback = true;
-				break;
-			case ARM_t2LDC2L_POST:
-			case ARM_t2LDC2_POST:
-			case ARM_t2LDCL_POST:
-			case ARM_t2LDC_POST:
-
-			case ARM_t2LDRB_POST:
-			case ARM_t2LDRD_POST:
-			case ARM_t2LDRH_POST:
-			case ARM_t2LDRSB_POST:
-			case ARM_t2LDRSH_POST:
-			case ARM_t2LDR_POST:
-
-			case ARM_t2STC2L_POST:
-			case ARM_t2STC2_POST:
-			case ARM_t2STCL_POST:
-			case ARM_t2STC_POST:
-
-			case ARM_t2STRB_POST:
-			case ARM_t2STRD_POST:
-			case ARM_t2STRH_POST:
-			case ARM_t2STR_POST:
-				insn->detail->arm.writeback = true;
-				insn->detail->arm.post_index = true;
-				break;
-		}
-	} else {	// ARM mode
-		// handle some special instructions with writeback
-        //printf(">> Opcode = %u\n", mci->Opcode);
-		switch(mci->Opcode) {
-			default:
-				break;
-			case ARM_LDC2L_PRE:
-			case ARM_LDC2_PRE:
-			case ARM_LDCL_PRE:
-			case ARM_LDC_PRE:
-
-			case ARM_LDRD_PRE:
-			case ARM_LDRH_PRE:
-			case ARM_LDRSB_PRE:
-			case ARM_LDRSH_PRE:
-
-			case ARM_STC2L_PRE:
-			case ARM_STC2_PRE:
-			case ARM_STCL_PRE:
-			case ARM_STC_PRE:
-
-			case ARM_STRD_PRE:
-			case ARM_STRH_PRE:
-				insn->detail->arm.writeback = true;
-				break;
-			case ARM_LDC2L_POST:
-			case ARM_LDC2_POST:
-			case ARM_LDCL_POST:
-			case ARM_LDC_POST:
-
-			case ARM_LDRBT_POST:
-			case ARM_LDRD_POST:
-			case ARM_LDRH_POST:
-			case ARM_LDRSB_POST:
-			case ARM_LDRSH_POST:
-
-			case ARM_STC2L_POST:
-			case ARM_STC2_POST:
-			case ARM_STCL_POST:
-			case ARM_STC_POST:
-
-			case ARM_STRBT_POST:
-			case ARM_STRD_POST:
-			case ARM_STRH_POST:
-
-			case ARM_LDRB_POST_IMM:
-			case ARM_LDR_POST_IMM:
-			case ARM_LDR_POST_REG:
-			case ARM_STRB_POST_IMM:
-
-			case ARM_STR_POST_IMM:
-			case ARM_STR_POST_REG:
-				insn->detail->arm.writeback = true;
-				insn->detail->arm.post_index = true;
-				break;
-		}
-	}
-
-	// check if this insn requests update flags
-	if (insn->detail->arm.update_flags == false) {
-		// some insn still update flags, regardless of tabgen info
-		unsigned int i, j;
-
-		for (i = 0; i < ARR_SIZE(insn_update_flgs); i++) {
-			if (insn->id == insn_update_flgs[i].id &&
-					!strncmp(insn_asm, insn_update_flgs[i].name,
-						strlen(insn_update_flgs[i].name))) {
-				insn->detail->arm.update_flags = true;
-				// we have to update regs_write array as well
-				for (j = 0; j < ARR_SIZE(insn->detail->regs_write); j++) {
-					if (insn->detail->regs_write[j] == 0) {
-						insn->detail->regs_write[j] = ARM_REG_CPSR;
-						break;
-					}
-				}
-				break;
-			}
-		}
-	}
-
-	// instruction should not have invalid CC
-	if (insn->detail->arm.cc == ARM_CC_INVALID) {
-		insn->detail->arm.cc = ARM_CC_AL;
-	}
-
-	// manual fix for some special instructions
-	// printf(">>> id: %u, mcid: %u\n", insn->id, mci->Opcode);
-	switch(mci->Opcode) {
-		default:
-			break;
-		case ARM_MOVPCLR:
-			insn->detail->arm.operands[0].type = ARM_OP_REG;
-			insn->detail->arm.operands[0].reg = ARM_REG_PC;
-			insn->detail->arm.operands[0].access = CS_AC_WRITE;
-			insn->detail->arm.operands[1].type = ARM_OP_REG;
-			insn->detail->arm.operands[1].reg = ARM_REG_LR;
-			insn->detail->arm.operands[1].access = CS_AC_READ;
-			insn->detail->arm.op_count = 2;
-			break;
-	}
-}
-
-void ARM_printInst(MCInst *MI, SStream *O, void *Info)
-{
-	MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
-	unsigned Opcode = MCInst_getOpcode(MI), tmp, i;
-
-	//printf(">>> Opcode = %u\n", Opcode);
-	switch (Opcode) {
-		// Check for MOVs and print canonical forms, instead.
-		case ARM_MOVsr: {
-			// FIXME: Thumb variants?
-			unsigned int opc;
-			MCOperand *Dst = MCInst_getOperand(MI, 0);
-			MCOperand *MO1 = MCInst_getOperand(MI, 1);
-			MCOperand *MO2 = MCInst_getOperand(MI, 2);
-			MCOperand *MO3 = MCInst_getOperand(MI, 3);
-
-			opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
-			SStream_concat0(O, ARM_AM_getShiftOpcStr(opc));
-
-			switch (opc) {
-				default: break;
-				case ARM_AM_asr:
-					 MCInst_setOpcodePub(MI, ARM_INS_ASR);
-					 break;
-				case ARM_AM_lsl:
-					 MCInst_setOpcodePub(MI, ARM_INS_LSL);
-					 break;
-				case ARM_AM_lsr:
-					 MCInst_setOpcodePub(MI, ARM_INS_LSR);
-					 break;
-				case ARM_AM_ror:
-					 MCInst_setOpcodePub(MI, ARM_INS_ROR);
-					 break;
-				case ARM_AM_rrx:
-					 MCInst_setOpcodePub(MI, ARM_INS_RRX);
-					 break;
-			}
-
-			printSBitModifierOperand(MI, 6, O);
-			printPredicateOperand(MI, 4, O);
-
-			SStream_concat0(O, "\t");
-			printRegName(MI->csh, O, MCOperand_getReg(Dst));
-
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
-				MI->flat_insn->detail->arm.op_count++;
-			}
-
-			SStream_concat0(O, ", ");
-			printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-				MI->flat_insn->detail->arm.op_count++;
-			}
-
-			SStream_concat0(O, ", ");
-			printRegName(MI->csh, O, MCOperand_getReg(MO2));
-
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-				MI->flat_insn->detail->arm.op_count++;
-			}
-
-			return;
-		}
-
-		case ARM_MOVsi: {
-			// FIXME: Thumb variants?
-			unsigned int opc;
-			MCOperand *Dst = MCInst_getOperand(MI, 0);
-			MCOperand *MO1 = MCInst_getOperand(MI, 1);
-			MCOperand *MO2 = MCInst_getOperand(MI, 2);
-
-			opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
-			SStream_concat0(O, ARM_AM_getShiftOpcStr(opc));
-
-			switch(opc) {
-				default:
-					break;
-				case ARM_AM_asr:
-					MCInst_setOpcodePub(MI, ARM_INS_ASR);
-					break;
-				case ARM_AM_lsl:
-					MCInst_setOpcodePub(MI, ARM_INS_LSL);
-					break;
-				case ARM_AM_lsr:
-					MCInst_setOpcodePub(MI, ARM_INS_LSR);
-					break;
-				case ARM_AM_ror:
-					MCInst_setOpcodePub(MI, ARM_INS_ROR);
-					break;
-				case ARM_AM_rrx:
-					MCInst_setOpcodePub(MI, ARM_INS_RRX);
-					break;
-			}
-
-			printSBitModifierOperand(MI, 5, O);
-			printPredicateOperand(MI, 3, O);
-
-			SStream_concat0(O, "\t");
-			printRegName(MI->csh, O, MCOperand_getReg(Dst));
-
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(Dst);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
-				MI->flat_insn->detail->arm.op_count++;
-			}
-
-			SStream_concat0(O, ", ");
-			printRegName(MI->csh, O, MCOperand_getReg(MO1));
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-				MI->flat_insn->detail->arm.op_count++;
-			}
-
-			if (opc == ARM_AM_rrx) {
-				//printAnnotation(O, Annot);
-				return;
-			}
-
-			SStream_concat0(O, ", ");
-			tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
-			printUInt32Bang(O, tmp);
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type =
-					(arm_shifter)opc;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
-			}
-
-			return;
-		}
-
-		// A8.6.123 PUSH
-		case ARM_STMDB_UPD:
-		case ARM_t2STMDB_UPD:
-			if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
-						MCInst_getNumOperands(MI) > 5) {
-				// Should only print PUSH if there are at least two registers in the list.
-				SStream_concat0(O, "push");
-				MCInst_setOpcodePub(MI, ARM_INS_PUSH);
-				printPredicateOperand(MI, 2, O);
-
-				if (Opcode == ARM_t2STMDB_UPD)
-					SStream_concat0(O, ".w");
-
-				SStream_concat0(O, "\t");
-
-				if (MI->csh->detail) {
-					MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
-					MI->flat_insn->detail->regs_read_count++;
-					MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
-					MI->flat_insn->detail->regs_write_count++;
-				}
-
-				printRegisterList(MI, 4, O);
-				return;
-			} else
-				break;
-
-		case ARM_STR_PRE_IMM:
-			if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP &&
-					MCOperand_getImm(MCInst_getOperand(MI, 3)) == -4) {
-				SStream_concat0(O, "push");
-				MCInst_setOpcodePub(MI, ARM_INS_PUSH);
-
-				printPredicateOperand(MI, 4, O);
-
-				SStream_concat0(O, "\t{");
-
-				printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
-
-				if (MI->csh->detail) {
-#ifndef CAPSTONE_DIET
-					uint8_t access;
-#endif
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
-#ifndef CAPSTONE_DIET
-					access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-					MI->ac_idx++;
-#endif
-					MI->flat_insn->detail->arm.op_count++;
-				}
-
-				SStream_concat0(O, "}");
-
-				return;
-			} else
-				break;
-
-		// A8.6.122 POP
-		case ARM_LDMIA_UPD:
-		case ARM_t2LDMIA_UPD:
-			if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP &&
-					MCInst_getNumOperands(MI) > 5) {
-				// Should only print POP if there are at least two registers in the list.
-				SStream_concat0(O, "pop");
-				MCInst_setOpcodePub(MI, ARM_INS_POP);
-
-				printPredicateOperand(MI, 2, O);
-				if (Opcode == ARM_t2LDMIA_UPD)
-					SStream_concat0(O, ".w");
-
-				SStream_concat0(O, "\t");
-
-				// unlike LDM, POP only write to registers, so skip the 1st access code
-				MI->ac_idx = 1;
-				if (MI->csh->detail) {
-					MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
-					MI->flat_insn->detail->regs_read_count++;
-					MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
-					MI->flat_insn->detail->regs_write_count++;
-				}
-
-				printRegisterList(MI, 4, O);
-
-				return;
-			}
-			break;
-
-		case ARM_LDR_POST_IMM:
-			if (MCOperand_getReg(MCInst_getOperand(MI, 2)) == ARM_SP) {
-				MCOperand *MO2 = MCInst_getOperand(MI, 4);
-
-				if (getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) {
-					SStream_concat0(O, "pop");
-					MCInst_setOpcodePub(MI, ARM_INS_POP);
-					printPredicateOperand(MI, 5, O);
-					SStream_concat0(O, "\t{");
-
-					printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
-
-					if (MI->csh->detail) {
-						MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-						MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
-						MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_WRITE;
-						MI->flat_insn->detail->arm.op_count++;
-                        // this instruction implicitly read/write SP register
-                        MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
-                        MI->flat_insn->detail->regs_read_count++;
-                        MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
-                        MI->flat_insn->detail->regs_write_count++;
-					}
-					SStream_concat0(O, "}");
-					return;
-				}
-			}
-			break;
-
-		// A8.6.355 VPUSH
-		case ARM_VSTMSDB_UPD:
-		case ARM_VSTMDDB_UPD:
-			if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
-				SStream_concat0(O, "vpush");
-				MCInst_setOpcodePub(MI, ARM_INS_VPUSH);
-				printPredicateOperand(MI, 2, O);
-				SStream_concat0(O, "\t");
-				printRegisterList(MI, 4, O);
-				return;
-			}
-			break;
-
-		// A8.6.354 VPOP
-		case ARM_VLDMSIA_UPD:
-		case ARM_VLDMDIA_UPD:
-			if (MCOperand_getReg(MCInst_getOperand(MI, 0)) == ARM_SP) {
-				SStream_concat0(O, "vpop");
-				MCInst_setOpcodePub(MI, ARM_INS_VPOP);
-				printPredicateOperand(MI, 2, O);
-				SStream_concat0(O, "\t");
-				printRegisterList(MI, 4, O);
-				return;
-			}
-			break;
-
-		case ARM_tLDMIA: {
-				bool Writeback = true;
-				unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, 0));
-				unsigned i;
-
-				for (i = 3; i < MCInst_getNumOperands(MI); ++i) {
-					if (MCOperand_getReg(MCInst_getOperand(MI, i)) == BaseReg)
-						Writeback = false;
-				}
-
-				SStream_concat0(O, "ldm");
-				MCInst_setOpcodePub(MI, ARM_INS_LDM);
-
-				printPredicateOperand(MI, 1, O);
-				SStream_concat0(O, "\t");
-				printRegName(MI->csh, O, BaseReg);
-				if (MI->csh->detail) {
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = BaseReg;
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ | CS_AC_WRITE;
-					MI->flat_insn->detail->arm.op_count++;
-				}
-
-				if (Writeback) {
-					MI->writeback = true;
-					SStream_concat0(O, "!");
-				}
-
-				SStream_concat0(O, ", ");
-				printRegisterList(MI, 3, O);
-				return;
-			}
-
-		// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
-		// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
-		// a single GPRPair reg operand is used in the .td file to replace the two
-		// GPRs. However, when decoding them, the two GRPs cannot be automatically
-		// expressed as a GPRPair, so we have to manually merge them.
-		// FIXME: We would really like to be able to tablegen'erate this.
-		case ARM_LDREXD:
-		case ARM_STREXD:
-		case ARM_LDAEXD:
-		case ARM_STLEXD: {
-			const MCRegisterClass *MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
-			bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
-			unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
-
-			if (MCRegisterClass_contains(MRC, Reg)) {
-			    MCInst NewMI;
-
-			    MCInst_Init(&NewMI);
-			    MCInst_setOpcode(&NewMI, Opcode);
-
-			    if (isStore)
-					MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
-
-			    MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, ARM_gsub_0,
-							MCRegisterInfo_getRegClass(MRI, ARM_GPRPairRegClassID)));
-
-			    // Copy the rest operands into NewMI.
-			    for(i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI); ++i)
-					MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
-
-			    printInstruction(&NewMI, O);
-			    return;
-			}
-			break;
-		}
-
-		case ARM_TSB:
-		case ARM_t2TSB:
-			SStream_concat0(O, "tsb\tcsync");
-			MCInst_setOpcodePub(MI, ARM_INS_TSB);
-			// TODO: add csync to operands[]?
-			return;
-	}
-
+	unsigned Opcode = MCInst_getOpcode(MI);
+	MCRegisterInfo *MRI = (MCRegisterInfo *)info;
 	MI->MRI = MRI;
+	uint64_t Address = MI->address;
 
-	if (!printAliasInstr(MI, O)) {
-		printInstruction(MI, O);
+	switch (Opcode) {
+	// Check for MOVs and print canonical forms, instead.
+	case ARM_MOVsr: {
+		// FIXME: Thumb variants?
+		MCOperand *MO3 = MCInst_getOperand(MI, (3));
+
+		SStream_concat1(O, ' ');
+		SStream_concat0(O, ARM_AM_getShiftOpcStr(
+							   ARM_AM_getSORegShOp(MCOperand_getImm(MO3))));
+		printSBitModifierOperand(MI, 6, O);
+		printPredicateOperand(MI, 4, O);
+
+		SStream_concat0(O, " ");
+
+		printOperand(MI, 0, O);
+		SStream_concat0(O, ", ");
+		printOperand(MI, 1, O);
+
+		SStream_concat0(O, ", ");
+		printOperand(MI, 2, O);
+
+		;
+		return;
 	}
+
+	case ARM_MOVsi: {
+		// FIXME: Thumb variants?
+		MCOperand *MO2 = MCInst_getOperand(MI, (2));
+
+		SStream_concat0(O, ARM_AM_getShiftOpcStr(
+							   ARM_AM_getSORegShOp(MCOperand_getImm(MO2))));
+		printSBitModifierOperand(MI, 5, O);
+		printPredicateOperand(MI, 3, O);
+
+		SStream_concat0(O, " ");
+
+		printOperand(MI, 0, O);
+		SStream_concat0(O, ", ");
+		printOperand(MI, 1, O);
+
+		if (ARM_AM_getSORegShOp(MCOperand_getImm(MO2)) == ARM_AM_rrx) {
+			return;
+		}
+
+		SStream_concat(O, "%s%s%s%d", ", ", markup("<imm:"), "#",
+				translateShiftImm(ARM_AM_getSORegOffset(MCOperand_getImm(MO2))));
+		SStream_concat0(O, markup(">"));
+		;
+		return;
+	}
+
+	// A8.6.123 PUSH
+	case ARM_STMDB_UPD:
+	case ARM_t2STMDB_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP &&
+			MCInst_getNumOperands(MI) > 5) {
+			// Should only print PUSH if there are at least two registers in the
+			// list.
+			SStream_concat0(O, "push");
+			printPredicateOperand(MI, 2, O);
+			if (Opcode == ARM_t2STMDB_UPD)
+				SStream_concat0(O, ".w");
+			SStream_concat0(O, " ");
+
+			printRegisterList(MI, 4, O);
+			return;
+		} else
+			break;
+
+	case ARM_STR_PRE_IMM:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP &&
+			MCOperand_getImm(MCInst_getOperand(MI, (3))) == -4) {
+			SStream_concat1(O, ' ');
+			SStream_concat0(O, "push");
+			printPredicateOperand(MI, 4, O);
+			SStream_concat0(O, " {");
+			printOperand(MI, 1, O);
+			SStream_concat0(O, "}");
+			return;
+		} else
+			break;
+
+	// A8.6.122 POP
+	case ARM_LDMIA_UPD:
+	case ARM_t2LDMIA_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP &&
+			MCInst_getNumOperands(MI) > 5) {
+			// Should only print POP if there are at least two registers in the
+			// list.
+			SStream_concat0(O, "pop");
+			printPredicateOperand(MI, 2, O);
+			if (Opcode == ARM_t2LDMIA_UPD)
+				SStream_concat0(O, ".w");
+			SStream_concat0(O, " ");
+
+			printRegisterList(MI, 4, O);
+			return;
+		} else
+			break;
+
+	case ARM_LDR_POST_IMM:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP &&
+			ARM_AM_getAM2Offset(MCOperand_getImm(MCInst_getOperand(MI, (4)))) == 4) {
+			SStream_concat0(O, "pop");
+			printPredicateOperand(MI, 5, O);
+			SStream_concat0(O, " {");
+			printOperand(MI, 0, O);
+			SStream_concat0(O, "}");
+			return;
+		} else
+			break;
+
+	// A8.6.355 VPUSH
+	case ARM_VSTMSDB_UPD:
+	case ARM_VSTMDDB_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP) {
+			SStream_concat0(O, "vpush");
+			printPredicateOperand(MI, 2, O);
+			SStream_concat0(O, " ");
+
+			printRegisterList(MI, 4, O);
+			return;
+		} else
+			break;
+
+	// A8.6.354 VPOP
+	case ARM_VLDMSIA_UPD:
+	case ARM_VLDMDIA_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP) {
+			SStream_concat1(O, ' ');
+			SStream_concat0(O, "vpop");
+			printPredicateOperand(MI, 2, O);
+			SStream_concat0(O, " ");
+
+			printRegisterList(MI, 4, O);
+			return;
+		} else
+			break;
+
+	case ARM_tLDMIA: {
+		bool Writeback = true;
+		unsigned BaseReg = MCOperand_getReg(MCInst_getOperand(MI, (0)));
+		for (unsigned i = 3; i < MCInst_getNumOperands(MI); ++i) {
+			if (MCOperand_getReg(MCInst_getOperand(MI, (i))) == BaseReg)
+				Writeback = false;
+		}
+
+		SStream_concat0(O, " ldm");
+
+		printPredicateOperand(MI, 1, O);
+		SStream_concat0(O, " ");
+
+		printOperand(MI, 0, O);
+		if (Writeback) {
+			SStream_concat0(O, "!");
+			// TODO: Do this in a static function called by ARMMapping.c::ARM_printer().
+			if (MI->flat_insn->detail) {
+				ARM_get_detail_op(MI, -1)->access |= CS_AC_WRITE;
+				MI->flat_insn->detail->writeback = true;
+			}
+		}
+		SStream_concat0(O, ", ");
+		printRegisterList(MI, 3, O);
+		// TODO: Do this in a static function called by ARMMapping.c::ARM_printer().
+		MI->flat_insn->id = ARM_INS_VPOP;
+		return;
+	}
+
+	// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
+	// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
+	// a single GPRPair reg operand is used in the .td file to replace the two
+	// GPRs. However, when decoding them, the two GRPs cannot be automatically
+	// expressed as a GPRPair, so we have to manually merge them.
+	// FIXME: We would really like to be able to tablegen'erate this.
+	case ARM_LDREXD:
+	case ARM_STREXD:
+	case ARM_LDAEXD:
+	case ARM_STLEXD: {
+		const MCRegisterClass *MRC =
+			MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
+		bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
+		unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
+
+		if (MCRegisterClass_contains(MRC, Reg)) {
+			MCInst NewMI;
+
+			MCInst_Init(&NewMI);
+			MCInst_setOpcode(&NewMI, Opcode);
+
+			if (isStore)
+				MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
+
+			MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(
+											 MRI, Reg, ARM_gsub_0,
+											 MCRegisterInfo_getRegClass(
+												 MRI, ARM_GPRPairRegClassID)));
+
+			// Copy the rest operands into NewMI.
+			for (unsigned i = isStore ? 3 : 2; i < MCInst_getNumOperands(MI);
+				 ++i)
+				MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
+
+			printInstruction(&NewMI, Address, O);
+			return;
+		}
+		break;
+	}
+	case ARM_TSB:
+	case ARM_t2TSB:
+		SStream_concat0(O, " tsb csync");
+		return;
+	case ARM_t2DSB:
+		switch (MCOperand_getImm(MCInst_getOperand(MI, (0)))) {
+		default:
+			if (!printAliasInstr(MI, Address, O))
+				printInstruction(MI, Address, O);
+			break;
+		case 0:
+			SStream_concat0(O, " ssbb");
+			break;
+		case 4:
+			SStream_concat0(O, " pssbb");
+			break;
+		};
+		return;
+	}
+
+	if (!printAliasInstr(MI, Address, O))
+		printInstruction(MI, Address, O);
+
+	;
 }
 
 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
 {
-	int32_t imm;
-	MCOperand *Op = MCInst_getOperand(MI, OpNo);
-
+	add_cs_detail(MI, ARM_OP_GROUP_Operand, OpNo);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNo));
 	if (MCOperand_isReg(Op)) {
 		unsigned Reg = MCOperand_getReg(Op);
-
-		printRegName(MI->csh, O, Reg);
-
-		if (MI->csh->detail) {
-			if (MI->csh->doing_mem) {
-				if (MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base == ARM_REG_INVALID)
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = Reg;
-				else
-					MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = Reg;
-			} else {
-#ifndef CAPSTONE_DIET
-				uint8_t access;
-#endif
-
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
-#ifndef CAPSTONE_DIET
-				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-				MI->ac_idx++;
-#endif
-				MI->flat_insn->detail->arm.op_count++;
-			}
-		}
+		printRegName(O, Reg);
 	} else if (MCOperand_isImm(Op)) {
-		unsigned int opc = MCInst_getOpcode(MI);
-
-		imm = (int32_t)MCOperand_getImm(Op);
-
-		// relative branch only has relative offset, so we have to update it
-		// to reflect absolute address. 
-		// Note: in ARM, PC is always 2 instructions ahead, so we have to
-		// add 8 in ARM mode, or 4 in Thumb mode
-		// printf(">> opcode: %u\n", MCInst_getOpcode(MI));
-		if (ARM_rel_branch(MI->csh, opc)) {
-			uint32_t address;
-
-			// only do this for relative branch
-			if (MI->csh->mode & CS_MODE_THUMB) {
-				address = (uint32_t)MI->address + 4;
-				if (ARM_blx_to_arm_mode(MI->csh, opc)) {
-					// here need to align down to the nearest 4-byte address
-#define _ALIGN_DOWN(v, align_width) ((v/align_width)*align_width)
-					address = _ALIGN_DOWN(address, 4);
-#undef _ALIGN_DOWN
-				}
-			} else {
-				address = (uint32_t)MI->address + 8;
-			}
-
-			imm += address;
-			printUInt32Bang(O, imm);
-		} else {
-			switch(MI->flat_insn->id) {
-				default:
-					if (MI->csh->imm_unsigned)
-						printUInt32Bang(O, imm);
-					else
-						printInt32Bang(O, imm);
-					break;
-				case ARM_INS_AND:
-				case ARM_INS_ORR:
-				case ARM_INS_EOR:
-				case ARM_INS_BIC:
-				case ARM_INS_MVN:
-					// do not print number in negative form
-					printUInt32Bang(O, imm);
-					break;
-			}
-		}
-
-		if (MI->csh->detail) {
-			if (MI->csh->doing_mem)
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
-			else {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
-				MI->flat_insn->detail->arm.op_count++;
-			}
-		}
+		SStream_concat(O, "%s", markup("<imm:"));
+		SStream_concat1(O, '#');
+		printInt64(O, MCOperand_getImm(Op));
+		SStream_concat0(O, markup(">"));
+	} else {
+		assert(0 && "Expressions are not supported.");
 	}
 }
 
-static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	int32_t OffImm;
-	bool isSub;
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	if (!MCOperand_isImm(Op) || MI->csh->PrintBranchImmNotAsAddress ||
+		getUseMarkup())
+		return printOperand(MI, OpNum, O);
+	int64_t Imm = MCOperand_getImm(Op);
+	// For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
+	// is 4 bytes.
+	uint64_t Offset = ARM_getFeatureBits(MI->csh->mode, ARM_ModeThumb) ? 4 : 8;
+
+	// A Thumb instruction BLX(i) can be 16-bit aligned while targets Arm code
+	// which is 32-bit aligned. The target address for the case is calculated as
+	//   targetAddress = Align(PC,4) + imm32;
+	// where
+	//   Align(x, y) = y * (x DIV y);
+	if (MCInst_getOpcode(MI) == ARM_tBLXi)
+		Address &= ~0x3;
+
+	uint64_t Target = Address + Imm + Offset;
+
+	Target &= 0xffffffff;
+	ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Target);
+	printUInt64(O, Target);
+}
+
+void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_isExpr(MO1)) {
+		// MO1.getExpr()->print(O, &MAI);
+		return;
+	}
+
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[pc, ");
 
-	OffImm = (int32_t)MCOperand_getImm(MO1);
-	isSub = OffImm < 0;
+	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
+	bool isSub = OffImm < 0;
 
 	// Special value for #-0. All others are normal.
 	if (OffImm == INT32_MIN)
 		OffImm = 0;
-
 	if (isSub) {
-		SStream_concat(O, "#-0x%x", -OffImm);
+		SStream_concat(O, "%s", markup("<imm:"));
+		printInt32Bang(O, OffImm);
+		SStream_concat0(O, markup(">"));
 	} else {
-		printUInt32Bang(O, OffImm);
-	}
-
-	SStream_concat0(O, "]");
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = ARM_REG_PC;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-		MI->flat_insn->detail->arm.op_count++;
+		SStream_concat(O, "%s", markup("<imm:"));
+		printInt32Bang(O, OffImm);
+		SStream_concat0(O, markup(">"));
 	}
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
@@ -946,1158 +421,848 @@ static void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O)
 //    REG 0   0           - e.g. R5
 //    REG REG 0,SH_OPC    - e.g. R5, ROR R3
 //    REG 0   IMM,SH_OPC  - e.g. R5, LSL #3
-static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	MCOperand *MO3 = MCInst_getOperand(MI, OpNum + 2);
-	ARM_AM_ShiftOpc ShOpc;
+	add_cs_detail(MI, ARM_OP_GROUP_SORegRegOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
+	MCOperand *MO3 = MCInst_getOperand(MI, (OpNum + 2));
 
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (MCOperand_getImm(MO3) & 7) + ARM_SFT_ASR_REG - 1;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	printRegName(O, MCOperand_getReg(MO1));
 
 	// Print the shift opc.
-	ShOpc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO3));
-	SStream_concat0(O, ", ");
+	ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp(MCOperand_getImm(MO3));
+	SStream_concat(O, "%s", ", ");
 	SStream_concat0(O, ARM_AM_getShiftOpcStr(ShOpc));
 	if (ShOpc == ARM_AM_rrx)
 		return;
 
 	SStream_concat0(O, " ");
 
-	printRegName(MI->csh, O, MCOperand_getReg(MO2));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
+	printRegName(O, MCOperand_getReg(MO2));
 }
 
-static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
+	add_cs_detail(MI, ARM_OP_GROUP_SORegImmOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
 
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	printRegName(O, MCOperand_getReg(MO1));
 
 	// Print the shift opc.
-	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
-			getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
+	printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)),
+					 ARM_AM_getSORegOffset(MCOperand_getImm(MO2)),
+					 getUseMarkup());
 }
 
 //===--------------------------------------------------------------------===//
 // Addressing Mode #2
 //===--------------------------------------------------------------------===//
 
-static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
+void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
-	MCOperand *MO3 = MCInst_getOperand(MI, Op + 2);
-	unsigned int imm3 = (unsigned int)MCOperand_getImm(MO3);
-	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO3));
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
+	MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1));
+	MCOperand *MO3 = MCInst_getOperand(MI, (Op + 2));
 
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-	}
+	printRegName(O, MCOperand_getReg(MO1));
 
 	if (!MCOperand_getReg(MO2)) {
-		unsigned tmp = getAM2Offset(imm3);
-		if (tmp) { // Don't print +0.
-			subtracted = getAM2Op(imm3);
-
-			SStream_concat0(O, ", ");
-			if (tmp > HEX_THRESHOLD)
-				SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), tmp);
-			else
-				SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), tmp);
-			if (MI->csh->detail) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = (arm_shifter)getAM2Op(imm3);
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = tmp;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
-			}
+		if (ARM_AM_getAM2Offset(MCOperand_getImm(MO3))) { // Don't print +0.
+			SStream_concat(
+				O, "%s%s%s", ", ", markup("<imm:"), "#",
+				ARM_AM_getAddrOpcStr(ARM_AM_getAM2Op(MCOperand_getImm(MO3))),
+				ARM_AM_getAM2Offset(MCOperand_getImm(MO3)));
+			SStream_concat0(O, markup(">"));
 		}
-
-		SStream_concat0(O, "]");
-		set_mem_access(MI, false);
-
+		SStream_concat(O, "%s", "]");
+		SStream_concat0(O, markup(">"));
 		return;
 	}
 
 	SStream_concat0(O, ", ");
-	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
-	printRegName(MI->csh, O, MCOperand_getReg(MO2));
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
-	}
+	SStream_concat0(
+		O, ARM_AM_getAddrOpcStr(ARM_AM_getAM2Op(MCOperand_getImm(MO3))));
+	printRegName(O, MCOperand_getReg(MO2));
 
-	printRegImmShift(MI, O, getAM2ShiftOpc(imm3), getAM2Offset(imm3));
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	printRegImmShift(MI, O, ARM_AM_getAM2ShiftOpc(MCOperand_getImm(MO3)),
+					 ARM_AM_getAM2Offset(MCOperand_getImm(MO3)),
+					 getUseMarkup());
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O)
+void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
-
+	add_cs_detail(MI, ARM_OP_GROUP_AddrModeTBB, Op);
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
+	MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1));
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
+	printRegName(O, MCOperand_getReg(MO1));
 	SStream_concat0(O, ", ");
-	printRegName(MI->csh, O, MCOperand_getReg(MO2));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	printRegName(O, MCOperand_getReg(MO2));
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
+void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
-
+	add_cs_detail(MI, ARM_OP_GROUP_AddrModeTBH, Op);
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
+	MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1));
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
+	printRegName(O, MCOperand_getReg(MO1));
 	SStream_concat0(O, ", ");
-	printRegName(MI->csh, O, MCOperand_getReg(MO2));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
-
-	SStream_concat0(O, ", lsl #1]");
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = 1;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.lshift = 1;
-	}
-
-	set_mem_access(MI, false);
+	printRegName(O, MCOperand_getReg(MO2));
+	SStream_concat(O, "%s%s%s%s%s", ", lsl ", markup("<imm:"), "#1",
+				   markup(">"), "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O)
+void printAddrMode2Operand(MCInst *MI, unsigned Op, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
+	add_cs_detail(MI, ARM_OP_GROUP_AddrMode2Operand, Op);
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
 
-	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
+	if (!MCOperand_isReg(
+			MO1)) { // FIXME: This is for CP entries, but isn't right.
 		printOperand(MI, Op, O);
 		return;
 	}
 
-//#ifndef NDEBUG
-//  const MCOperand &MO3 = MI->getOperand(Op + 2);
-//  unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
-//  assert(IdxMode != ARMII::IndexModePost && "Should be pre or offset index op");
-//#endif
-
 	printAM2PreOrOffsetIndexOp(MI, Op, O);
 }
 
-static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	ARM_AM_AddrOpc subtracted = getAM2Op((unsigned int)MCOperand_getImm(MO2));
+	add_cs_detail(MI, ARM_OP_GROUP_AddrMode2OffsetOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
 
 	if (!MCOperand_getReg(MO1)) {
-		unsigned ImmOffs = getAM2Offset((unsigned int)MCOperand_getImm(MO2));
-		if (ImmOffs > HEX_THRESHOLD)
-			SStream_concat(O, "#%s0x%x",
-					ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
-		else
-			SStream_concat(O, "#%s%u",
-					ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
-			MI->flat_insn->detail->arm.op_count++;
-		}
+		unsigned ImmOffs = ARM_AM_getAM2Offset(MCOperand_getImm(MO2));
+		SStream_concat(O, "%s", markup("<imm:"));
+		SStream_concat1(O, '#');
+		SStream_concat(
+			O, "%s",
+			ARM_AM_getAddrOpcStr(ARM_AM_getAM2Op(MCOperand_getImm(MO2))));
+		printUInt32(O, ImmOffs);
+		SStream_concat0(O, markup(">"));
 		return;
 	}
 
-	SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
+	SStream_concat0(
+		O, ARM_AM_getAddrOpcStr(ARM_AM_getAM2Op(MCOperand_getImm(MO2))));
+	printRegName(O, MCOperand_getReg(MO1));
 
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
-	printRegImmShift(MI, O, getAM2ShiftOpc((unsigned int)MCOperand_getImm(MO2)),
-			getAM2Offset((unsigned int)MCOperand_getImm(MO2)));
+	printRegImmShift(MI, O, ARM_AM_getAM2ShiftOpc(MCOperand_getImm(MO2)),
+					 ARM_AM_getAM2Offset(MCOperand_getImm(MO2)),
+					 getUseMarkup());
 }
 
 //===--------------------------------------------------------------------===//
 // Addressing Mode #3
 //===--------------------------------------------------------------------===//
 
-static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
-		bool AlwaysPrintImm0)
+void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
+								bool AlwaysPrintImm0)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-	MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
-	MCOperand *MO3 = MCInst_getOperand(MI, Op+2);
-	ARM_AM_AddrOpc sign = getAM3Op((unsigned int)MCOperand_getImm(MO3));
-	unsigned ImmOffs;
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
+	MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1));
+	MCOperand *MO3 = MCInst_getOperand(MI, (Op + 2));
 
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
 
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
+	printRegName(O, MCOperand_getReg(MO1));
 
 	if (MCOperand_getReg(MO2)) {
-		SStream_concat0(O, ", ");
-		SStream_concat0(O, ARM_AM_getAddrOpcStr(sign));
-
-		printRegName(MI->csh, O, MCOperand_getReg(MO2));
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
-			if (sign == ARM_AM_sub) {
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = -1;
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
-			}
-		}
-
-		SStream_concat0(O, "]");
-		set_mem_access(MI, false);
-
+		SStream_concat(O, "%s", ", ");
+		SStream_concat0(
+			O, ARM_AM_getAddrOpcStr(ARM_AM_getAM3Op(MCOperand_getImm(MO3))));
+		printRegName(O, MCOperand_getReg(MO2));
+		SStream_concat1(O, ']');
+		SStream_concat0(O, markup(">"));
 		return;
 	}
 
 	// If the op is sub we have to print the immediate even if it is 0
-	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO3));
+	unsigned ImmOffs = ARM_AM_getAM3Offset(MCOperand_getImm(MO3));
+	ARM_AM_AddrOpc op = ARM_AM_getAM3Op(MCOperand_getImm(MO3));
 
-	if (AlwaysPrintImm0 || ImmOffs || (sign == ARM_AM_sub)) {
-		if (ImmOffs > HEX_THRESHOLD)
-			SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(sign), ImmOffs);
-		else
-			SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(sign), ImmOffs);
+	if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM_sub)) {
+		SStream_concat(O, "%s%s%s%s", ", ", markup("<imm:"), "#",
+					   ARM_AM_getAddrOpcStr(op));
+		printUInt32(O, ImmOffs);
+		SStream_concat0(O, markup(">"));
 	}
-
-	if (MI->csh->detail) {
-		if (sign == ARM_AM_sub) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = true;
-		} else
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = (int)ImmOffs;
-	}
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	SStream_concat1(O, ']');
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrMode3Operand(MCInst *MI, unsigned Op, SStream *O,
-		bool AlwaysPrintImm0)
-{
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-
-	if (!MCOperand_isReg(MO1)) {   // For label symbolic references.
-		printOperand(MI, Op, O);
-		return;
+#define DEFINE_printAddrMode3Operand(AlwaysPrintImm0)                          \
+	void CONCAT(printAddrMode3Operand,                                         \
+				AlwaysPrintImm0)(MCInst * MI, unsigned Op, SStream *O)         \
+	{                                                                          \
+		add_cs_detail(MI,                                                      \
+					  CONCAT(ARM_OP_GROUP_AddrMode3Operand, AlwaysPrintImm0),  \
+					  Op, AlwaysPrintImm0);                                    \
+		MCOperand *MO1 = MCInst_getOperand(MI, (Op));                          \
+		if (!MCOperand_isReg(MO1)) {                                           \
+			printOperand(MI, Op, O);                                           \
+			return;                                                            \
+		}                                                                      \
+                                                                               \
+		printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);                \
 	}
+DEFINE_printAddrMode3Operand(false) DEFINE_printAddrMode3Operand(true)
 
-	printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
-}
-
-static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
+	void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	ARM_AM_AddrOpc subtracted = getAM3Op((unsigned int)MCOperand_getImm(MO2));
-	unsigned ImmOffs;
+	add_cs_detail(MI, ARM_OP_GROUP_AddrMode3OffsetOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
 
 	if (MCOperand_getReg(MO1)) {
-		SStream_concat0(O, ARM_AM_getAddrOpcStr(subtracted));
-		printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-
+		SStream_concat0(
+			O, ARM_AM_getAddrOpcStr(ARM_AM_getAM3Op(MCOperand_getImm(MO2))));
+		printRegName(O, MCOperand_getReg(MO1));
 		return;
 	}
 
-	ImmOffs = getAM3Offset((unsigned int)MCOperand_getImm(MO2));
-	if (ImmOffs > HEX_THRESHOLD)
-		SStream_concat(O, "#%s0x%x", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
-	else
-		SStream_concat(O, "#%s%u", ARM_AM_getAddrOpcStr(subtracted), ImmOffs);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].subtracted = subtracted == ARM_AM_sub;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	unsigned ImmOffs = ARM_AM_getAM3Offset(MCOperand_getImm(MO2));
+	SStream_concat(O, "%s", markup("<imm:"));
+	SStream_concat1(O, '#');
+	SStream_concat(
+		O, "%s", ARM_AM_getAddrOpcStr(ARM_AM_getAM3Op(MCOperand_getImm(MO2))));
+	printUInt32(O, ImmOffs);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
+void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-	unsigned Imm = (unsigned int)MCOperand_getImm(MO);
-
-	if ((Imm & 0xff) > HEX_THRESHOLD)
-		SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
-	else
-		SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_PostIdxImm8Operand, OpNum);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	unsigned Imm = MCOperand_getImm(MO);
+	SStream_concat(O, "%s", markup("<imm:"));
+	SStream_concat1(O, '#');
+	SStream_concat(O, "%s", ((Imm & 256) ? "" : "-"));
+	printUInt32(O, (Imm & 0xff));
+	SStream_concat0(O, markup(">"));
 }
 
-static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
+	add_cs_detail(MI, ARM_OP_GROUP_PostIdxRegOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
 
 	SStream_concat0(O, (MCOperand_getImm(MO2) ? "" : "-"));
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	printRegName(O, MCOperand_getReg(MO1));
 }
 
-static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
+void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-	int Imm = (int)MCOperand_getImm(MO);
-
-	if (((Imm & 0xff) << 2) > HEX_THRESHOLD) {
-		SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
-	} else {
-		SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
-	}
-
-	if (MI->csh->detail) {
-		int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_PostIdxImm8s4Operand, OpNum);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	unsigned Imm = MCOperand_getImm(MO);
+	SStream_concat(O, "%s", markup("<imm:"));
+	SStream_concat1(O, '#');
+	SStream_concat(O, "%s", ((Imm & 256) ? "" : "-"));
+	printUInt32(O, (Imm & 0xff) << 2);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
-		bool AlwaysPrintImm0)
-{
-	unsigned ImmOffs;
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	ARM_AM_AddrOpc Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
-
-	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
-		printOperand(MI, OpNum, O);
-		return;
+#define DEFINE_printMveAddrModeRQOperand(shift)                                \
+	void CONCAT(printMveAddrModeRQOperand, shift)(MCInst * MI, unsigned OpNum, \
+												  SStream *O)                  \
+	{                                                                          \
+		add_cs_detail(MI, CONCAT(ARM_OP_GROUP_MveAddrModeRQOperand, shift),    \
+					  OpNum, shift);                                           \
+		MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));                       \
+		MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));                   \
+                                                                               \
+		SStream_concat(O, "%s", markup("<mem:"));                              \
+		SStream_concat0(O, "[");                                               \
+		printRegName(O, MCOperand_getReg(MO1));                                \
+		SStream_concat0(O, ", ");                                              \
+		printRegName(O, MCOperand_getReg(MO2));                                \
+                                                                               \
+		if (shift > 0)                                                         \
+			printRegImmShift(MI, O, ARM_AM_uxtw, shift, getUseMarkup());       \
+                                                                               \
+		SStream_concat(O, "%s", "]");                                          \
+		SStream_concat0(O, markup(">"));                                       \
 	}
+DEFINE_printMveAddrModeRQOperand(0) DEFINE_printMveAddrModeRQOperand(3)
+	DEFINE_printMveAddrModeRQOperand(1) DEFINE_printMveAddrModeRQOperand(2)
 
+		void printLdStmModeOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_LdStmModeOperand, OpNum);
+	ARM_AM_SubMode Mode =
+		ARM_AM_getAM4SubMode(MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
+	SStream_concat0(O, ARM_AM_getAMSubModeStr(Mode));
+}
+
+#define DEFINE_printAddrMode5Operand(AlwaysPrintImm0)                          \
+	void CONCAT(printAddrMode5Operand,                                         \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O)      \
+	{                                                                          \
+		add_cs_detail(MI,                                                      \
+					  CONCAT(ARM_OP_GROUP_AddrMode5Operand, AlwaysPrintImm0),  \
+					  OpNum, AlwaysPrintImm0);                                 \
+		MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));                       \
+		MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));                   \
+                                                                               \
+		SStream_concat(O, "%s", markup("<mem:"));                              \
+		SStream_concat0(O, "[");                                               \
+		printRegName(O, MCOperand_getReg(MO1));                                \
+                                                                               \
+		unsigned ImmOffs = ARM_AM_getAM5Offset(MCOperand_getImm(MO2));         \
+		ARM_AM_AddrOpc Op = ARM_AM_getAM5Op(MCOperand_getImm(MO2));            \
+		if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {                  \
+			SStream_concat(O, "%s%s%s%s", ", ", markup("<imm:"), "#",          \
+						   ARM_AM_getAddrOpcStr(Op));                          \
+			printUInt32(O, ImmOffs * 4);                                       \
+			SStream_concat0(O, markup(">"));                                   \
+		}                                                                      \
+		SStream_concat(O, "%s", "]");                                          \
+		SStream_concat0(O, markup(">"));                                       \
+	}
+DEFINE_printAddrMode5Operand(false) DEFINE_printAddrMode5Operand(true)
+
+#define DEFINE_printAddrMode5FP16Operand(AlwaysPrintImm0)                      \
+	void CONCAT(printAddrMode5FP16Operand,                                     \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O)      \
+	{                                                                          \
+		add_cs_detail(                                                         \
+			MI, CONCAT(ARM_OP_GROUP_AddrMode5FP16Operand, AlwaysPrintImm0),    \
+			OpNum, AlwaysPrintImm0);                                           \
+		MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));                       \
+		MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));                   \
+                                                                               \
+		if (!MCOperand_isReg(MO1)) {                                           \
+			printOperand(MI, OpNum, O);                                        \
+			return;                                                            \
+		}                                                                      \
+                                                                               \
+		SStream_concat(O, "%s", markup("<mem:"));                              \
+		SStream_concat0(O, "[");                                               \
+		printRegName(O, MCOperand_getReg(MO1));                                \
+                                                                               \
+		unsigned ImmOffs = ARM_AM_getAM5FP16Offset(MCOperand_getImm(MO2));     \
+		unsigned Op = ARM_AM_getAM5FP16Op(MCOperand_getImm(MO2));              \
+		if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {                  \
+			SStream_concat(O, "%s%s%s%s", ", ", markup("<imm:"), "#",          \
+						   ARM_AM_getAddrOpcStr(                               \
+							   ARM_AM_getAM5FP16Op(MCOperand_getImm(MO2))));   \
+			printUInt32(O, ImmOffs * 2);                                       \
+			SStream_concat0(O, markup(">"));                                   \
+		}                                                                      \
+		SStream_concat(O, "%s", "]");                                          \
+		SStream_concat0(O, markup(">"));                                       \
+	}
+	DEFINE_printAddrMode5FP16Operand(false)
+
+		void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_AddrMode6Operand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
+
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-	}
-
-	ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
-	if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
-		if (ImmOffs * 4 > HEX_THRESHOLD)
-			SStream_concat(O, ", #%s0x%x",
-					ARM_AM_getAddrOpcStr(Op),
-					ImmOffs * 4);
-		else
-			SStream_concat(O, ", #%s%u",
-					ARM_AM_getAddrOpcStr(Op),
-					ImmOffs * 4);
-
-		if (MI->csh->detail) {
-			if (Op)
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 4;
-			else
-				MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 4;
-		}
-	}
-
-	SStream_concat0(O, "]");
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.op_count++;
+	printRegName(O, MCOperand_getReg(MO1));
+	if (MCOperand_getImm(MO2)) {
+		SStream_concat(O, "%s", ":");
+		printInt64(O, ((int32_t)MCOperand_getImm(MO2)) << 3);
 	}
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrMode5FP16Operand(MCInst *MI, unsigned OpNum, SStream *O,
-		bool AlwaysPrintImm0)
+void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-  MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-  MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-  unsigned ImmOffs = getAM5FP16Offset((unsigned)MCOperand_getImm(MO2));
-  unsigned Op = getAM5FP16Op((unsigned)MCOperand_getImm(MO2));
-
-  if (!MCOperand_isReg(MO1)) {  // FIXME: This is for CP entries, but isn't right.
-	  printOperand(MI, OpNum, O);
-	  return;
-  }
-
-  SStream_concat0(O, "[");
-  printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-  if (MI->csh->detail) {
-	  MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_MEM;
-	  MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-	  MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = ARM_REG_INVALID;
-	  MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.scale = 1;
-	  MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = 0;
-	  MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-  }
-
-  if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM_sub) {
-	if (ImmOffs * 2 > HEX_THRESHOLD)
-		SStream_concat(O, ", #%s0x%x", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2);
-	else
-		SStream_concat(O, ", #%s%u", ARM_AM_getAddrOpcStr(Op), ImmOffs * 2);
-
-	if (MI->csh->detail) {
-		if (Op)
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = ImmOffs * 2;
-		else
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = -(int)ImmOffs * 2;
-	}
-  }
-
-  SStream_concat0(O, "]");
-
-  if (MI->csh->detail) {
-	  MI->flat_insn->detail->arm.op_count++;
-  }
-}
-
-static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	unsigned tmp;
-
+	add_cs_detail(MI, ARM_OP_GROUP_AddrMode7Operand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	tmp = (unsigned int)MCOperand_getImm(MO2);
-	if (tmp) {
-		if (tmp << 3 > HEX_THRESHOLD)
-			SStream_concat(O, ":0x%x", (tmp << 3));
-		else
-			SStream_concat(O, ":%u", (tmp << 3));
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp << 3;
-	}
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	printRegName(O, MCOperand_getReg(MO1));
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O)
+void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-
-	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
-}
-
-static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-
-	if (MCOperand_getReg(MO) == 0) {
-		MI->writeback = true;
+	add_cs_detail(MI, ARM_OP_GROUP_AddrMode6OffsetOperand, OpNum);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_getReg(MO) == 0)
 		SStream_concat0(O, "!");
-	} else {
+	else {
 		SStream_concat0(O, ", ");
-		printRegName(MI->csh, O, MCOperand_getReg(MO));
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO);
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-			MI->flat_insn->detail->arm.op_count++;
-		}
+		printRegName(O, MCOperand_getReg(MO));
 	}
 }
 
-static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-	uint32_t v = ~(uint32_t)MCOperand_getImm(MO);
+	add_cs_detail(MI, ARM_OP_GROUP_BitfieldInvMaskImmOperand, OpNum);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	uint32_t v = ~MCOperand_getImm(MO);
 	int32_t lsb = CountTrailingZeros_32(v);
-	int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
+	int32_t width = (32 - countLeadingZeros(v)) - lsb;
 
-	//assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
-	printUInt32Bang(O, lsb);
-
-	if (width > HEX_THRESHOLD)
-		SStream_concat(O, ", #0x%x", width);
-	else
-		SStream_concat(O, ", #%u", width);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
-		MI->flat_insn->detail->arm.op_count++;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	SStream_concat(O, "%s", markup("<imm:"));
+	SStream_concat1(O, '#');
+	printInt32(O, lsb);
+	SStream_concat(O, "%s%s%s", markup(">"), ", ", markup("<imm:"));
+	printInt32Bang(O, width);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
+void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-	SStream_concat0(O, ARM_MB_MemBOptToString(val,
-				ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.mem_barrier = (arm_mem_barrier)(val + 1);
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_MemBOption, OpNum);
+	unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	SStream_concat0(O,
+					ARM_MB_MemBOptToString(
+						val, ARM_getFeatureBits(MI->csh->mode, ARM_HasV8Ops)));
 }
 
-static void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
+void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_InstSyncBOption, OpNum);
+	unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val));
 }
 
-static void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
+void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_TraceSyncBOption, OpNum);
+	unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val));
-	// TODO: add to detail?
 }
 
-static void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned ShiftOp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_ShiftImmOperand, OpNum);
+	unsigned ShiftOp = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	bool isASR = (ShiftOp & (1 << 5)) != 0;
 	unsigned Amt = ShiftOp & 0x1f;
-
 	if (isASR) {
-		unsigned tmp = Amt == 0 ? 32 : Amt;
-		if (tmp > HEX_THRESHOLD)
-			SStream_concat(O, ", asr #0x%x", tmp);
-		else
-			SStream_concat(O, ", asr #%u", tmp);
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = tmp;
-		}
+		SStream_concat(O, "%s%s%s", ", asr ", markup("<imm:"), "#");
+		printUInt32(O, Amt == 0 ? 32 : Amt);
+		SStream_concat0(O, markup(">"));
 	} else if (Amt) {
-		if (Amt > HEX_THRESHOLD)
-			SStream_concat(O, ", lsl #0x%x", Amt);
-		else
-			SStream_concat(O, ", lsl #%u", Amt);
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Amt;
-		}
+		SStream_concat(O, "%s%s%s", ", lsl ", markup("<imm:"), "#");
+		printUInt32(O, Amt);
+		SStream_concat0(O, markup(">"));
 	}
 }
 
-static void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
+void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
+	add_cs_detail(MI, ARM_OP_GROUP_PKHLSLShiftImm, OpNum);
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	if (Imm == 0)
 		return;
 
-	//assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
-	if (Imm > HEX_THRESHOLD)
-		SStream_concat(O, ", lsl #0x%x", Imm);
-	else
-		SStream_concat(O, ", lsl #%u", Imm);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_LSL;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
-	}
+	SStream_concat(O, "%s%s%s", ", lsl ", markup("<imm:"), "#");
+	printUInt32(O, Imm);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
+void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
+	add_cs_detail(MI, ARM_OP_GROUP_PKHASRShiftImm, OpNum);
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	// A shift amount of 32 is encoded as 0.
 	if (Imm == 0)
 		Imm = 32;
 
-	//assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
-	if (Imm > HEX_THRESHOLD)
-		SStream_concat(O, ", asr #0x%x", Imm);
-	else
-		SStream_concat(O, ", asr #%u", Imm);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ASR;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
-	}
+	SStream_concat(O, "%s%s%s", ", asr ", markup("<imm:"), "#");
+	printUInt32(O, Imm);
+	SStream_concat0(O, markup(">"));
 }
 
-// FIXME: push {r1, r2, r3, ...} can exceed the number of operands in MCInst struct
-static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
+void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned i, e;
-#ifndef CAPSTONE_DIET
-	uint8_t access = 0;
-#endif
+	add_cs_detail(MI, ARM_OP_GROUP_RegisterList, OpNum);
+	if (MCInst_getOpcode(MI) != ARM_t2CLRM) {
+	}
 
 	SStream_concat0(O, "{");
-
-#ifndef CAPSTONE_DIET
-	if (MI->csh->detail) {
-		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-	}
-#endif
-
-	for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
+	for (unsigned i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
 		if (i != OpNum)
 			SStream_concat0(O, ", ");
-
-		printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
-#ifndef CAPSTONE_DIET
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-			MI->flat_insn->detail->arm.op_count++;
-		}
+		printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (i))));
 	}
-
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	if (MI->csh->detail) {
-		MI->ac_idx++;
-	}
-#endif
 }
 
-static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-
-	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0);
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	add_cs_detail(MI, ARM_OP_GROUP_GPRPairOperand, OpNum);
+	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
+	printRegName(O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0));
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1);
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	printRegName(O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1));
 }
 
-// SETEND BE/LE
-static void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *Op = MCInst_getOperand(MI, OpNum);
-
-	if (MCOperand_getImm(Op)) {
+	add_cs_detail(MI, ARM_OP_GROUP_SetendOperand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_getImm(Op))
 		SStream_concat0(O, "be");
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_BE;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-	} else {
+	else
 		SStream_concat0(O, "le");
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SETEND;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].setend = ARM_SETEND_LE;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-	}
 }
 
-static void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
+void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *Op = MCInst_getOperand(MI, OpNum);
-	unsigned int mode = (unsigned int)MCOperand_getImm(Op);
-
-	SStream_concat0(O, ARM_PROC_IModToString(mode));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.cps_mode = mode;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_CPSIMod, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	SStream_concat0(O, ARM_PROC_IModToString(MCOperand_getImm(Op)));
 }
 
-static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
+void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *Op = MCInst_getOperand(MI, OpNum);
-	unsigned IFlags = (unsigned int)MCOperand_getImm(Op);
-	int i;
-
-	for (i = 2; i >= 0; --i)
-		if (IFlags & (1 << i)) {
+	add_cs_detail(MI, ARM_OP_GROUP_CPSIFlag, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+	unsigned IFlags = MCOperand_getImm(Op);
+	for (int i = 2; i >= 0; --i)
+		if (IFlags & (1 << i))
 			SStream_concat0(O, ARM_PROC_IFlagsToString(1 << i));
-		}
 
-	if (IFlags == 0) {
+	if (IFlags == 0)
 		SStream_concat0(O, "none");
-		IFlags = ARM_CPSFLAG_NONE;
-	}
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.cps_flag = IFlags;
-	}
 }
 
-static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *Op = MCInst_getOperand(MI, OpNum);
-	unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
-	unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf;
-	unsigned reg;
+	add_cs_detail(MI, ARM_OP_GROUP_MSRMaskOperand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
 
 	if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) {
-		const MClassSysReg *TheReg;
-		unsigned SYSm = (unsigned)MCOperand_getImm(Op) & 0xFFF;  // 12-bit SYMm
+
+		unsigned SYSm = MCOperand_getImm(Op) & 0xFFF; // 12-bit SYSm
 		unsigned Opcode = MCInst_getOpcode(MI);
 
-		if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) {
-			TheReg = lookupMClassSysRegBy12bitSYSmValue(SYSm);
-			if (TheReg && MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) {
+		// For writes, handle extended mask bits if the DSP extension is
+		// present.
+		if (Opcode == ARM_t2MSR_M &&
+			ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) {
+			const ARMSysReg_MClassSysReg *TheReg =
+				ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(SYSm);
+			if (TheReg &&
+				MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) {
 				SStream_concat0(O, TheReg->Name);
-				ARM_addSysReg(MI, TheReg->sysreg);
 				return;
 			}
 		}
 
 		// Handle the basic 8-bit mask.
 		SYSm &= 0xff;
-		if (Opcode == ARM_t2MSR_M && ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) {
-			// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
-			// alias for MSR APSR_nzcvq.
-			TheReg = lookupMClassSysRegAPSRNonDeprecated(SYSm);
+		if (Opcode == ARM_t2MSR_M &&
+			ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) {
+			// ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as
+			// an alias for MSR APSR_nzcvq.
+			const ARMSysReg_MClassSysReg *TheReg =
+				ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(SYSm);
 			if (TheReg) {
 				SStream_concat0(O, TheReg->Name);
-				ARM_addSysReg(MI, TheReg->sysreg);
 				return;
 			}
 		}
 
-		TheReg = lookupMClassSysRegBy8bitSYSmValue(SYSm);
+		const ARMSysReg_MClassSysReg *TheReg = ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(SYSm);
 		if (TheReg) {
 			SStream_concat0(O, TheReg->Name);
-			ARM_addSysReg(MI, TheReg->sysreg);
 			return;
 		}
 
-		if (SYSm > HEX_THRESHOLD)
-			SStream_concat(O, "%x", SYSm);
-		else
-			SStream_concat(O, "%u", SYSm);
-
-		if (MI->csh->detail)
-			MCOperand_CreateImm0(MI, SYSm);
+		printUInt32(O, SYSm);
 
 		return;
 	}
 
 	// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
 	// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
+	unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
+	unsigned Mask = MCOperand_getImm(Op) & 0xf;
+
 	if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
 		SStream_concat0(O, "apsr_");
 		switch (Mask) {
-			default: // llvm_unreachable("Unexpected mask value!");
-			case 4:  SStream_concat0(O, "g"); ARM_addSysReg(MI, ARM_SYSREG_APSR_G); return;
-			case 8:  SStream_concat0(O, "nzcvq"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQ); return;
-			case 12: SStream_concat0(O, "nzcvqg"); ARM_addSysReg(MI, ARM_SYSREG_APSR_NZCVQG); return;
+		default:
+			assert(0 && "Unexpected mask value!");
+		case 4:
+			SStream_concat0(O, "g");
+			return;
+		case 8:
+			SStream_concat0(O, "nzcvq");
+			return;
+		case 12:
+			SStream_concat0(O, "nzcvqg");
+			return;
 		}
 	}
 
-	if (SpecRegRBit) {
+	if (SpecRegRBit)
 		SStream_concat0(O, "spsr");
-	} else {
+	else
 		SStream_concat0(O, "cpsr");
-	}
 
-	reg = 0;
 	if (Mask) {
 		SStream_concat0(O, "_");
 
-		if (Mask & 8) {
+		if (Mask & 8)
 			SStream_concat0(O, "f");
-			reg += ARM_SYSREG_SPSR_F;
-		}
 
-		if (Mask & 4) {
+		if (Mask & 4)
 			SStream_concat0(O, "s");
-			reg += ARM_SYSREG_SPSR_S;
-		}
 
-		if (Mask & 2) {
+		if (Mask & 2)
 			SStream_concat0(O, "x");
-			reg += ARM_SYSREG_SPSR_X;
-		}
 
-		if (Mask & 1) {
+		if (Mask & 1)
 			SStream_concat0(O, "c");
-			reg += ARM_SYSREG_SPSR_C;
-		}
-
-		ARM_addSysReg(MI, reg);
 	}
 }
 
-static void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	uint32_t Banked = (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-	const BankedReg *TheReg = lookupBankedRegByEncoding(Banked);
+	add_cs_detail(MI, ARM_OP_GROUP_BankedRegOperand, OpNum);
+	uint32_t Banked = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	const ARMBankedReg_BankedReg *TheReg = ARMBankedReg_lookupBankedRegByEncoding(Banked);
 
-	SStream_concat0(O, TheReg->Name);
-	ARM_addSysReg(MI, TheReg->sysreg);
+	const char *Name = TheReg->Name;
+
+	// uint32_t isSPSR = (Banked & 0x20) >> 5;
+	// if (isSPSR)
+	// 	Name.replace(0, 4, "SPSR"); // convert 'spsr_' to 'SPSR_'
+	SStream_concat0(O, Name);
 }
 
 static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_PredicateOperand, OpNum);
+	ARMCC_CondCodes CC =
+		(ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	// Handle the undefined 15 CC value here for printing so we don't abort().
-	if ((unsigned)CC == 15) {
+	if ((unsigned)CC == 15)
 		SStream_concat0(O, "<und>");
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.cc = ARM_CC_INVALID;
-	} else {
-		if (CC != ARMCC_AL) {
-			SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
-		}
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.cc = CC + 1;
-	}
+	else if (CC != ARMCC_AL)
+		SStream_concat0(O, ARMCondCodeToString(CC));
 }
 
-static void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum,
+											  SStream *O)
 {
-	ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-	SStream_concat0(O, ARMCC_ARMCondCodeToString(CC));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.cc = CC + 1;
-}
-
-static void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	if (MCOperand_getReg(MCInst_getOperand(MI, OpNum))) {
-		//assert(MCOperand_getReg(MCInst_getOperand(MI, OpNum)) == ARM_CPSR &&
-		//       "Expect ARM CPSR register!");
-		SStream_concat0(O, "s");
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.update_flags = true;
-	}
-}
-
-static void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
-	printUInt32(O, tmp);
-
-	if (MI->csh->detail) {
-		if (MI->csh->doing_mem) {
-			MI->flat_insn->detail->arm.op_count--;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].neon_lane = (int8_t)tmp;
-			MI->ac_idx--;	// consecutive operands share the same access right
-		} else {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-	}
-}
-
-static void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
-	SStream_concat(O, "p%u", imm);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_PIMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
-		MI->flat_insn->detail->arm.op_count++;
-	}
-}
-
-static void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
-	SStream_concat(O, "c%u", imm);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_CIMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
-		MI->flat_insn->detail->arm.op_count++;
-	}
-}
-
-static void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-	if (tmp > HEX_THRESHOLD)
-		SStream_concat(O, "{0x%x}", tmp);
+	add_cs_detail(MI, ARM_OP_GROUP_MandatoryRestrictedPredicateOperand, OpNum);
+	if ((ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) ==
+		ARMCC_HS)
+		SStream_concat0(O, "cs");
 	else
-		SStream_concat(O, "{%u}", tmp);
+		printMandatoryPredicateOperand(MI, OpNum, O);
+}
 
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-		MI->flat_insn->detail->arm.op_count++;
+void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_MandatoryPredicateOperand, OpNum);
+	ARMCC_CondCodes CC =
+		(ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	SStream_concat0(O, ARMCondCodeToString(CC));
+}
+
+void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum,
+											SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_MandatoryInvertedPredicateOperand, OpNum);
+	ARMCC_CondCodes CC =
+		(ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	SStream_concat0(O, ARMCondCodeToString(ARMCC_getOppositeCondition(CC)));
+}
+
+void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_SBitModifierOperand, OpNum);
+	if (MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))) {
+
+		SStream_concat0(O, "s");
 	}
 }
 
-static void printAdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O, unsigned scale)
+void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-
-	int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;
-
-	if (OffImm == INT32_MIN) {
-		SStream_concat0(O, "#-0");
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-	} else {
-		if (OffImm < 0)
-			SStream_concat(O, "#-0x%x", -OffImm);
-		else {
-			if (OffImm > HEX_THRESHOLD)
-				SStream_concat(O, "#0x%x", OffImm);
-			else
-				SStream_concat(O, "#%u", OffImm);
-		}
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_NoHashImmediate, OpNum);
+	printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
 }
 
-static void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)) * 4;
-
-	printUInt32Bang(O, tmp);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_PImmediate, OpNum);
+	SStream_concat(O, "%s%d", "p",
+				   MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
 }
 
-static void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
+void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-	unsigned tmp = Imm == 0 ? 32 : Imm;
-
-	printUInt32Bang(O, tmp);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_CImmediate, OpNum);
+	SStream_concat(O, "%s%d", "c",
+				   MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
 }
 
-static void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
+void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_CoprocOptionImm, OpNum);
+	SStream_concat(O, "%s", "{");
+	printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
+	SStream_concat0(O, "}");
+}
+
+void printPCLabel(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	// add_cs_detail(MI, ARM_OP_GROUP_PCLabel, OpNum);
+	assert(0 && "Unhandled PC-relative pseudo-instruction!");
+}
+
+#define DEFINE_printAdrLabelOperand(scale)                                     \
+	void CONCAT(printAdrLabelOperand, scale)(MCInst * MI, unsigned OpNum,      \
+											 SStream *O)                       \
+	{                                                                          \
+		add_cs_detail(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), OpNum,  \
+					  scale);                                                  \
+		MCOperand *MO = MCInst_getOperand(MI, (OpNum));                        \
+                                                                               \
+		if (MCOperand_isExpr(MO)) {                                            \
+			return;                                                            \
+		}                                                                      \
+                                                                               \
+		int32_t OffImm = (int32_t)MCOperand_getImm(MO) << scale;               \
+                                                                               \
+		SStream_concat0(O, markup("<imm:"));                                   \
+		if (OffImm == INT32_MIN)                                               \
+			SStream_concat0(O, "#-0");                                         \
+		else if (OffImm < 0) {                                                 \
+			printInt32Bang(O, OffImm);                                         \
+		} else {                                                               \
+			printInt32Bang(O, OffImm);                                         \
+		}                                                                      \
+		SStream_concat0(O, markup(">"));                                       \
+	}
+DEFINE_printAdrLabelOperand(0) DEFINE_printAdrLabelOperand(2)
+
+	void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbS4ImmOperand, OpNum);
+	SStream_concat(O, "%s", markup("<imm:"));
+	printInt64Bang(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) * 4);
+	SStream_concat0(O, markup(">"));
+}
+
+void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbSRImm, OpNum);
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	SStream_concat(O, "%s", markup("<imm:"));
+	printUInt32Bang(O, (Imm == 0 ? 32 : Imm));
+	SStream_concat0(O, markup(">"));
+}
+
+void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbITMask, OpNum);
 	// (3 - the number of trailing zeros) is the number of then / else.
-	unsigned Mask = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-	unsigned Firstcond = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum - 1));
-	unsigned CondBit0 = Firstcond & 1;
+	unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	unsigned NumTZ = CountTrailingZeros_32(Mask);
-	//assert(NumTZ <= 3 && "Invalid IT mask!");
-	unsigned Pos, e;
 
-	for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
-		bool T = ((Mask >> Pos) & 1) == CondBit0;
-		if (T)
-			SStream_concat0(O, "t");
-		else
+	for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
+		if ((Mask >> Pos) & 1)
 			SStream_concat0(O, "e");
-		// TODO: detail for this t/e
+
+		else
+			SStream_concat0(O, "t");
 	}
 }
 
-static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
+void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
-	unsigned RegNum;
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeRROperand, Op);
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
+	MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1));
 
-	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
+	if (!MCOperand_isReg(
+			MO1)) { // FIXME: This is for CP entries, but isn't right.
 		printOperand(MI, Op, O);
 		return;
 	}
 
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	RegNum = MCOperand_getReg(MO2);
+	printRegName(O, MCOperand_getReg(MO1));
+	unsigned RegNum = MCOperand_getReg(MO2);
 	if (RegNum) {
 		SStream_concat0(O, ", ");
-		printRegName(MI->csh, O, RegNum);
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = RegNum;
+		printRegName(O, RegNum);
 	}
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
-		unsigned Scale)
+void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
+									unsigned Scale)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, Op);
-	MCOperand *MO2 = MCInst_getOperand(MI, Op + 1);
-	unsigned ImmOffs, tmp;
+	MCOperand *MO1 = MCInst_getOperand(MI, (Op));
+	MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1));
 
-	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
+	if (!MCOperand_isReg(
+			MO1)) { // FIXME: This is for CP entries, but isn't right.
 		printOperand(MI, Op, O);
 		return;
 	}
 
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	ImmOffs = (unsigned int)MCOperand_getImm(MO2);
+	printRegName(O, MCOperand_getReg(MO1));
+	unsigned ImmOffs = MCOperand_getImm(MO2);
 	if (ImmOffs) {
-		tmp = ImmOffs * Scale;
-		SStream_concat0(O, ", ");
-		printUInt32Bang(O, tmp);
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
+		SStream_concat(O, "%s%s", ", ", markup("<imm:"));
+		printUInt32Bang(O, ImmOffs * Scale);
+		SStream_concat0(O, markup(">"));
 	}
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O)
+void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned Op, SStream *O)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeImm5S1Operand, Op);
 	printThumbAddrModeImm5SOperand(MI, Op, O, 1);
 }
 
-static void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O)
+void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned Op, SStream *O)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeImm5S2Operand, Op);
 	printThumbAddrModeImm5SOperand(MI, Op, O, 2);
 }
 
-static void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O)
+void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned Op, SStream *O)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeImm5S4Operand, Op);
 	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
 }
 
-static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O)
+void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_ThumbAddrModeSPOperand, Op);
 	printThumbAddrModeImm5SOperand(MI, Op, O, 4);
 }
 
@@ -2105,1260 +1270,586 @@ static void printThumbAddrModeSPOperand(MCInst *MI, unsigned Op, SStream *O)
 // register with shift forms.
 // REG 0   0           - e.g. R5
 // REG IMM, SH_OPC     - e.g. R5, LSL #3
-static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
+	add_cs_detail(MI, ARM_OP_GROUP_T2SOOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
+
 	unsigned Reg = MCOperand_getReg(MO1);
-
-	printRegName(MI->csh, O, Reg);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = CS_AC_READ;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	printRegName(O, Reg);
 
 	// Print the shift opc.
-	//assert(MO2.isImm() && "Not a valid t2_so_reg value!");
-	printRegImmShift(MI, O, ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)),
-			getSORegOffset((unsigned int)MCOperand_getImm(MO2)));
+
+	printRegImmShift(MI, O, ARM_AM_getSORegShOp(MCOperand_getImm(MO2)),
+					 ARM_AM_getSORegOffset(MCOperand_getImm(MO2)),
+					 getUseMarkup());
 }
 
-static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
-		SStream *O, bool AlwaysPrintImm0)
+#define DEFINE_printAddrModeImm12Operand(AlwaysPrintImm0)                      \
+	void CONCAT(printAddrModeImm12Operand,                                     \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O)      \
+	{                                                                          \
+		add_cs_detail(                                                         \
+			MI, CONCAT(ARM_OP_GROUP_AddrModeImm12Operand, AlwaysPrintImm0),    \
+			OpNum, AlwaysPrintImm0);                                           \
+		MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));                       \
+		MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));                   \
+                                                                               \
+		if (!MCOperand_isReg(MO1)) {                                           \
+			printOperand(MI, OpNum, O);                                        \
+			return;                                                            \
+		}                                                                      \
+                                                                               \
+		SStream_concat(O, "%s", markup("<mem:"));                              \
+		SStream_concat0(O, "[");                                               \
+		printRegName(O, MCOperand_getReg(MO1));                                \
+                                                                               \
+		int32_t OffImm = (int32_t)MCOperand_getImm(MO2);                       \
+		bool isSub = OffImm < 0;                                               \
+                                                                               \
+		if (OffImm == INT32_MIN)                                               \
+			OffImm = 0;                                                        \
+		if (isSub) {                                                           \
+			SStream_concat(O, "%s%s", ", ", markup("<imm:"));                  \
+			printInt32Bang(O, OffImm);                                         \
+			SStream_concat0(O, markup(">"));                                   \
+		} else if (AlwaysPrintImm0 || OffImm > 0) {                            \
+			SStream_concat(O, "%s%s", ", ", markup("<imm:"));                  \
+			printInt32Bang(O, OffImm);                                         \
+			SStream_concat0(O, markup(">"));                                   \
+		}                                                                      \
+		SStream_concat(O, "%s", "]");                                          \
+		SStream_concat0(O, markup(">"));                                       \
+	}
+DEFINE_printAddrModeImm12Operand(false) DEFINE_printAddrModeImm12Operand(true)
+
+#define DEFINE_printT2AddrModeImm8Operand(AlwaysPrintImm0)                     \
+	void CONCAT(printT2AddrModeImm8Operand,                                    \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O)      \
+	{                                                                          \
+		add_cs_detail(                                                         \
+			MI, CONCAT(ARM_OP_GROUP_T2AddrModeImm8Operand, AlwaysPrintImm0),   \
+			OpNum, AlwaysPrintImm0);                                           \
+		MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));                       \
+		MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));                   \
+                                                                               \
+		SStream_concat(O, "%s", markup("<mem:"));                              \
+		SStream_concat0(O, "[");                                               \
+		printRegName(O, MCOperand_getReg(MO1));                                \
+                                                                               \
+		int32_t OffImm = (int32_t)MCOperand_getImm(MO2);                       \
+		bool isSub = OffImm < 0;                                               \
+                                                                               \
+		if (OffImm == INT32_MIN)                                               \
+			OffImm = 0;                                                        \
+		if (isSub) {                                                           \
+			SStream_concat(O, "%s%s", ", ", markup("<imm:"));                  \
+			printInt32Bang(O, OffImm);                                        \
+			SStream_concat0(O, markup(">"));                                   \
+		} else if (AlwaysPrintImm0 || OffImm > 0) {                            \
+			SStream_concat(O, "%s%s", ", ", markup("<imm:"));                  \
+			printInt32Bang(O, OffImm);                                         \
+			SStream_concat0(O, markup(">"));                                   \
+		}                                                                      \
+		SStream_concat(O, "%s", "]");                                          \
+		SStream_concat0(O, markup(">"));                                       \
+	}
+	DEFINE_printT2AddrModeImm8Operand(true)
+		DEFINE_printT2AddrModeImm8Operand(false)
+
+#define DEFINE_printT2AddrModeImm8s4Operand(AlwaysPrintImm0)                   \
+	void CONCAT(printT2AddrModeImm8s4Operand,                                  \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O)      \
+	{                                                                          \
+		add_cs_detail(                                                         \
+			MI, CONCAT(ARM_OP_GROUP_T2AddrModeImm8s4Operand, AlwaysPrintImm0), \
+			OpNum, AlwaysPrintImm0);                                           \
+		MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));                       \
+		MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));                   \
+                                                                               \
+		if (!MCOperand_isReg(MO1)) {                                           \
+			printOperand(MI, OpNum, O);                                        \
+			return;                                                            \
+		}                                                                      \
+                                                                               \
+		SStream_concat(O, "%s", markup("<mem:"));                              \
+		SStream_concat0(O, "[");                                               \
+		printRegName(O, MCOperand_getReg(MO1));                                \
+                                                                               \
+		int32_t OffImm = (int32_t)MCOperand_getImm(MO2);                       \
+		bool isSub = OffImm < 0;                                               \
+                                                                               \
+		if (OffImm == INT32_MIN)                                               \
+			OffImm = 0;                                                        \
+		if (isSub) {                                                           \
+			SStream_concat(O, "%s%s", ", ", markup("<imm:"));                  \
+			printInt32Bang(O, OffImm);                                         \
+			SStream_concat0(O, markup(">"));                                   \
+		} else if (AlwaysPrintImm0 || OffImm > 0) {                            \
+			SStream_concat(O, "%s%s", ", ", markup("<imm:"));                  \
+			printInt32Bang(O, OffImm);                                         \
+			SStream_concat0(O, markup(">"));                                   \
+		}                                                                      \
+		SStream_concat(O, "%s", "]");                                          \
+		SStream_concat0(O, markup(">"));                                       \
+	}
+			DEFINE_printT2AddrModeImm8s4Operand(false)
+				DEFINE_printT2AddrModeImm8s4Operand(true)
+
+					void printT2AddrModeImm0_1020s4Operand(MCInst *MI,
+														   unsigned OpNum,
+														   SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
-	int32_t OffImm;
-	bool isSub;
-
-	if (!MCOperand_isReg(MO1)) {   // FIXME: This is for CP entries, but isn't right.
-		printOperand(MI, OpNum, O);
-		return;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
 
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	OffImm = (int32_t)MCOperand_getImm(MO2);
-	isSub = OffImm < 0;
-
-	// Special value for #-0. All others are normal.
-	if (OffImm == INT32_MIN)
-		OffImm = 0;
-
-	if (isSub) {
-		if (OffImm < -HEX_THRESHOLD)
-			SStream_concat(O, ", #-0x%x", -OffImm);
-		else
-			SStream_concat(O, ", #-%u", -OffImm);
-	} else if (AlwaysPrintImm0 || OffImm > 0) {
-		if (OffImm >= 0) {
-			if (OffImm > HEX_THRESHOLD)
-				SStream_concat(O, ", #0x%x", OffImm);
-			else
-				SStream_concat(O, ", #%u", OffImm);
-		} else {
-			if (OffImm < -HEX_THRESHOLD)
-				SStream_concat(O, ", #-0x%x", -OffImm);
-			else
-				SStream_concat(O, ", #-%u", -OffImm);
-		}
-	}
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
-}
-
-static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
-		bool AlwaysPrintImm0)
-{
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
-	int32_t OffImm;
-	bool isSub;
-
-	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	OffImm = (int32_t)MCOperand_getImm(MO2);
-	isSub = OffImm < 0;
-
-	// Don't print +0.
-	if (OffImm == INT32_MIN)
-		OffImm = 0;
-
-	if (isSub)
-		SStream_concat(O, ", #-0x%x", -OffImm);
-	else if (AlwaysPrintImm0 || OffImm > 0) {
-		if (OffImm > HEX_THRESHOLD)
-			SStream_concat(O, ", #0x%x", OffImm);
-		else
-			SStream_concat(O, ", #%u", OffImm);
-	}
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
-}
-
-static void printT2AddrModeImm8s4Operand(MCInst *MI,
-		unsigned OpNum, SStream *O, bool AlwaysPrintImm0)
-{
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	int32_t OffImm;
-	bool isSub;
-
-	if (!MCOperand_isReg(MO1)) {   //  For label symbolic references.
-		printOperand(MI, OpNum, O);
-		return;
-	}
-
-	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	OffImm = (int32_t)MCOperand_getImm(MO2);
-	isSub = OffImm < 0;
-
-	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
-
-	// Don't print +0.
-	if (OffImm == INT32_MIN)
-		OffImm = 0;
-
-	if (isSub) {
-		SStream_concat(O, ", #-0x%x", -OffImm);
-	} else if (AlwaysPrintImm0 || OffImm > 0) {
-		if (OffImm > HEX_THRESHOLD)
-			SStream_concat(O, ", #0x%x", OffImm);
-		else
-			SStream_concat(O, ", #%u", OffImm);
-	}
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = OffImm;
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
-}
-
-static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
-{
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
-	unsigned tmp;
-
-	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
-
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
+	printRegName(O, MCOperand_getReg(MO1));
 	if (MCOperand_getImm(MO2)) {
-		SStream_concat0(O, ", ");
-		tmp = (unsigned int)MCOperand_getImm(MO2) * 4;
-		printUInt32Bang(O, tmp);
-
-		if (MI->csh->detail)
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = tmp;
+		SStream_concat(O, "%s%s", ", ", markup("<imm:"));
+		printInt64Bang(O, (int32_t)(MCOperand_getImm(MO2) * 4));
+		SStream_concat0(O, markup(">"));
 	}
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printT2AddrModeImm8OffsetOperand(MCInst *MI,
-		unsigned OpNum, SStream *O)
+void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+	add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeImm8OffsetOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
 	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
-
-	SStream_concat0(O, ", ");
-	if (OffImm == INT32_MIN) {
+	SStream_concat(O, "%s", ", ");
+	SStream_concat0(O, markup("<imm:"));
+	if (OffImm == INT32_MIN)
 		SStream_concat0(O, "#-0");
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
-			MI->flat_insn->detail->arm.op_count++;
-		}
+	else if (OffImm < 0) {
+		printInt32Bang(O, OffImm);
 	} else {
 		printInt32Bang(O, OffImm);
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
-			MI->flat_insn->detail->arm.op_count++;
-		}
 	}
+	SStream_concat0(O, markup(">"));
 }
 
-static void printT2AddrModeImm8s4OffsetOperand(MCInst *MI,
-		unsigned OpNum, SStream *O)
+void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+	add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
 	int32_t OffImm = (int32_t)MCOperand_getImm(MO1);
 
-	//assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
-
-	SStream_concat0(O, ", ");
-
-	if (OffImm == INT32_MIN) {
+	SStream_concat(O, "%s", ", ");
+	SStream_concat0(O, markup("<imm:"));
+	if (OffImm == INT32_MIN)
 		SStream_concat0(O, "#-0");
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
-			MI->flat_insn->detail->arm.op_count++;
-		}
+	else if (OffImm < 0) {
+		printInt32Bang(O, OffImm);
 	} else {
 		printInt32Bang(O, OffImm);
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
-			MI->flat_insn->detail->arm.op_count++;
-		}
 	}
+	SStream_concat0(O, markup(">"));
 }
 
-static void printT2AddrModeSoRegOperand(MCInst *MI,
-		unsigned OpNum, SStream *O)
+void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
-	MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
-	MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
-	unsigned ShAmt;
+	add_cs_detail(MI, ARM_OP_GROUP_T2AddrModeSoRegOperand, OpNum);
+	MCOperand *MO1 = MCInst_getOperand(MI, (OpNum));
+	MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1));
+	MCOperand *MO3 = MCInst_getOperand(MI, (OpNum + 2));
 
+	SStream_concat(O, "%s", markup("<mem:"));
 	SStream_concat0(O, "[");
-	set_mem_access(MI, true);
+	printRegName(O, MCOperand_getReg(MO1));
 
-	printRegName(MI->csh, O, MCOperand_getReg(MO1));
-
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.base = MCOperand_getReg(MO1);
-
-	//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
 	SStream_concat0(O, ", ");
-	printRegName(MI->csh, O, MCOperand_getReg(MO2));
+	printRegName(O, MCOperand_getReg(MO2));
 
-	if (MI->csh->detail)
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.index = MCOperand_getReg(MO2);
-
-	ShAmt = (unsigned int)MCOperand_getImm(MO3);
+	unsigned ShAmt = MCOperand_getImm(MO3);
 	if (ShAmt) {
-		//assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
-		SStream_concat0(O, ", lsl ");
-		SStream_concat(O, "#%u", ShAmt);
 
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.type = ARM_SFT_LSL;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].shift.value = ShAmt;
-		}
+		SStream_concat(O, "%s%s%s", ", lsl ", markup("<imm:"), "#");
+		printUInt32(O, ShAmt);
+		SStream_concat0(O, markup(">"));
 	}
-
-	SStream_concat0(O, "]");
-	set_mem_access(MI, false);
+	SStream_concat(O, "%s", "]");
+	SStream_concat0(O, markup(">"));
 }
 
-static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *MO = MCInst_getOperand(MI, OpNum);
-
-#if defined(_KERNEL_MODE)
-	// Issue #681: Windows kernel does not support formatting float point
-	SStream_concat(O, "#<float_point_unsupported>");
-#else
-	SStream_concat(O, "#%e", getFPImmFloat((unsigned int)MCOperand_getImm(MO)));
-#endif
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_FP;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].fp = getFPImmFloat((unsigned int)MCOperand_getImm(MO));
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_FPImmOperand, OpNum);
+	MCOperand *MO = MCInst_getOperand(MI, (OpNum));
+	SStream_concat(O, "%s", markup("<imm:"));
+	printFloatBang(O, ARM_AM_getFPImmFloat(MCOperand_getImm(MO)));
+	SStream_concat0(O, markup(">"));
 }
 
-static void printNEONModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned EncodedImm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_VMOVModImmOperand, OpNum);
+	unsigned EncodedImm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	unsigned EltBits;
-	uint64_t Val = ARM_AM_decodeNEONModImm(EncodedImm, &EltBits);
-
-	if (Val > HEX_THRESHOLD)
-		SStream_concat(O, "#0x%"PRIx64, Val);
-	else
-		SStream_concat(O, "#%"PRIu64, Val);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	uint64_t Val = ARM_AM_decodeVMOVModImm(EncodedImm, &EltBits);
+	SStream_concat(O, "%s", markup("<imm:"));
+	printUInt64Bang(O, Val);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
+	add_cs_detail(MI, ARM_OP_GROUP_ImmPlusOneOperand, OpNum);
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	SStream_concat(O, "%s", markup("<imm:"));
 	printUInt32Bang(O, Imm + 1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	SStream_concat0(O, markup(">"));
 }
 
-static void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
+	add_cs_detail(MI, ARM_OP_GROUP_RotImmOperand, OpNum);
+	unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
 	if (Imm == 0)
 		return;
 
-	SStream_concat0(O, ", ror #");
-
-	switch (Imm) {
-		default: //assert (0 && "illegal ror immediate!");
-		case 1: SStream_concat0(O, "8"); break;
-		case 2: SStream_concat0(O, "16"); break;
-		case 3: SStream_concat0(O, "24"); break;
-	}
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.type = ARM_SFT_ROR;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
-	}
+	SStream_concat(O, "%s%s%s%d", ", ror ", markup("<imm:"), "#", 8 * Imm);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
+void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	MCOperand *Op = MCInst_getOperand(MI, OpNum);
+	add_cs_detail(MI, ARM_OP_GROUP_ModImmOperand, OpNum);
+	MCOperand *Op = MCInst_getOperand(MI, (OpNum));
+
+	// Support for fixups (MCFixup)
+	if (MCOperand_isExpr(Op))
+		return printOperand(MI, OpNum, O);
+
 	unsigned Bits = MCOperand_getImm(Op) & 0xFF;
 	unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7;
-	int32_t Rotated;
-	bool  PrintUnsigned = false;
 
+	bool PrintUnsigned = false;
 	switch (MCInst_getOpcode(MI)) {
-		case ARM_MOVi:
-			// Movs to PC should be treated unsigned
-			PrintUnsigned = (MCOperand_getReg(MCInst_getOperand(MI, OpNum - 1)) == ARM_PC);
-			break;
-		case ARM_MSRi:
-			// Movs to special registers should be treated unsigned
-			PrintUnsigned = true;
-			break;
+	case ARM_MOVi:
+		// Movs to PC should be treated unsigned
+		PrintUnsigned =
+			(MCOperand_getReg(MCInst_getOperand(MI, (OpNum - 1))) == ARM_PC);
+		break;
+	case ARM_MSRi:
+		// Movs to special registers should be treated unsigned
+		PrintUnsigned = true;
+		break;
 	}
 
-	Rotated = rotr32(Bits, Rot);
-	if (getSOImmVal(Rotated) == MCOperand_getImm(Op)) {
+	int32_t Rotated = ARM_AM_rotr32(Bits, Rot);
+	if (ARM_AM_getSOImmVal(Rotated) == MCOperand_getImm(Op)) {
 		// #rot has the least possible value
-		if (PrintUnsigned) {
-			if (Rotated > HEX_THRESHOLD || Rotated < -HEX_THRESHOLD)
-				SStream_concat(O, "#0x%x", Rotated);
-			else
-				SStream_concat(O, "#%u", Rotated);
-		} else if (Rotated >= 0) {
-			if (Rotated > HEX_THRESHOLD)
-				SStream_concat(O, "#0x%x", Rotated);
-			else
-				SStream_concat(O, "#%u", Rotated);
-		} else {
-			SStream_concat(O, "#0x%x", Rotated);
-		}
-
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-			MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rotated;
-			MI->flat_insn->detail->arm.op_count++;
-		}
-
+		SStream_concat(O, "%s", "#");
+		SStream_concat0(O, markup("<imm:"));
+		if (PrintUnsigned)
+			printUInt32(O, (uint32_t)(Rotated));
+		else
+			printInt32(O, Rotated);
+		SStream_concat0(O, markup(">"));
 		return;
 	}
 
 	// Explicit #bits, #rot implied
-	SStream_concat(O, "#%u, #%u", Bits, Rot);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Bits;
-		MI->flat_insn->detail->arm.op_count++;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Rot;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	SStream_concat(O, "%s%s%u", "#", markup("<imm:"), Bits);
+	SStream_concat(O, "%s%s%s%u", markup(">"), ", #", markup("<imm:"), Rot);
+	SStream_concat0(O, markup(">"));
 }
 
-static void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
+void printFBits16(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned tmp;
-
-	tmp = 16 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
-	printUInt32Bang(O, tmp);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_FBits16, OpNum);
+	SStream_concat(O, "%s%s", markup("<imm:"), "#");
+	SStream_concat(O, "%d", 16 - MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
+	SStream_concat0(O, markup(">"));
 }
 
-static void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
+void printFBits32(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned tmp;
-
-	tmp = 32 - (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
-	printUInt32Bang(O, tmp);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_FBits32, OpNum);
+	SStream_concat(O, "%s%s", markup("<imm:"), "#");
+	printInt64(O, 32 - MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
+	SStream_concat0(O, markup(">"));
 }
 
-static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	unsigned tmp = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
-
-	if (tmp > HEX_THRESHOLD)
-		SStream_concat(O, "[0x%x]", tmp);
-	else
-		SStream_concat(O, "[%u]", tmp);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].vector_index = tmp;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_VectorIndex, OpNum);
+	SStream_concat(O, "%s", "[");
+	printInt64(O, (int32_t) MCOperand_getImm(MCInst_getOperand(MI, (OpNum))));
+	SStream_concat0(O, "]");
 }
 
-static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
 {
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListOne, OpNum);
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-#ifndef CAPSTONE_DIET
-		uint8_t access;
-
-		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, "}");
 }
 
-static void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-#endif
-	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListTwo, OpNum);
+	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
 	unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
 	unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1);
-
-#ifndef CAPSTONE_DIET
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, Reg0);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg0);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, Reg1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg1);
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-#endif
-	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoSpaced, OpNum);
+	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
 	unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
 	unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2);
-
-#ifndef CAPSTONE_DIET
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, Reg0);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg0);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, Reg1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg1);
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListThree, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListFour, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 3);
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListOneAllLanes, OpNum);
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-#endif
-	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoAllLanes, OpNum);
+	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
 	unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
 	unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1);
-
-#ifndef CAPSTONE_DIET
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, Reg0);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg0);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, Reg1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg1);
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeAllLanes, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListFourAllLanes, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 1);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 3);
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-#endif
-	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoSpacedAllLanes, OpNum);
+	unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
 	unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0);
 	unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2);
-
-#ifndef CAPSTONE_DIET
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, Reg0);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg0;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg0);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, Reg1);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = Reg1;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, Reg1);
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListThreeSpacedAllLanes(MCInst *MI,
-		unsigned OpNum, SStream *O)
+void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeSpacedAllLanes, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4);
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListFourSpacedAllLanes(MCInst *MI,
-		unsigned OpNum, SStream *O)
+void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListFourSpacedAllLanes, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4);
 	SStream_concat0(O, "[], ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 6);
 	SStream_concat0(O, "[]}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeSpaced, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4);
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
+void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
 {
-#ifndef CAPSTONE_DIET
-	uint8_t access;
-
-	access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
-#endif
-
+	add_cs_detail(MI, ARM_OP_GROUP_VectorListFourSpaced, OpNum);
 	// Normally, it's not safe to use register enum values directly with
 	// addition to get the next register, but for VFP registers, the
 	// sort order is guaranteed because they're all of the form D<n>.
 	SStream_concat0(O, "{");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))));
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 2);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 4);
 	SStream_concat0(O, ", ");
-
-	printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
-
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
-#ifndef CAPSTONE_DIET
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].access = access;
-#endif
-		MI->flat_insn->detail->arm.op_count++;
-	}
-
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))) + 6);
 	SStream_concat0(O, "}");
-
-#ifndef CAPSTONE_DIET
-	MI->ac_idx++;
-#endif
 }
 
-static void printComplexRotationOp(MCInst *MI, unsigned OpNo, SStream *O, int64_t Angle, int64_t Remainder)
-{
-	unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
-	unsigned tmp = (unsigned)((Val * Angle) + Remainder);
+#define DEFINE_printMVEVectorList(NumRegs)                                     \
+	void CONCAT(printMVEVectorList, NumRegs)(MCInst * MI, unsigned OpNum,      \
+											 SStream *O)                       \
+	{                                                                          \
+		add_cs_detail(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), OpNum,  \
+					  NumRegs);                                                \
+		unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));       \
+		const char *Prefix = "{";                                              \
+		for (unsigned i = 0; i < NumRegs; i++) {                               \
+			SStream_concat0(O, Prefix);                                        \
+			printRegName(                                                      \
+				O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_qsub_0 + i));    \
+			Prefix = ", ";                                                     \
+		}                                                                      \
+		SStream_concat0(O, "}");                                               \
+	}
+DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4)
 
-	printUInt32Bang(O, tmp);
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
-		MI->flat_insn->detail->arm.op_count++;
+#define DEFINE_printComplexRotationOp(Angle, Remainder)                        \
+	void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))(             \
+		MCInst * MI, unsigned OpNo, SStream *O)                                \
+	{                                                                          \
+		add_cs_detail(                                                         \
+			MI,                                                                \
+			CONCAT(CONCAT(ARM_OP_GROUP_ComplexRotationOp, Angle), Remainder),  \
+			OpNo, Angle, Remainder);                                           \
+		unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNo)));        \
+		SStream_concat(O, "#%d", (Val * Angle) + Remainder);                   \
+	}
+	DEFINE_printComplexRotationOp(90, 0) DEFINE_printComplexRotationOp(180, 90)
+
+		void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_VPTPredicateOperand, OpNum);
+	ARMVCC_VPTCodes CC =
+		(ARMVCC_VPTCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	if (CC != ARMVCC_None)
+		SStream_concat0(O, ARMVPTPredToString(CC));
+}
+
+void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O)
+{
+	add_cs_detail(MI, ARM_OP_GROUP_VPTMask, OpNum);
+	// (3 - the number of trailing zeroes) is the number of them / else.
+	unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+	unsigned NumTZ = CountTrailingZeros_32(Mask);
+
+	for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
+		bool T = ((Mask >> Pos) & 1) == 0;
+		if (T)
+			SStream_concat0(O, "t");
+
+		else
+			SStream_concat0(O, "e");
 	}
 }
 
-void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd)
+void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O)
 {
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.vector_data = vd;
-	}
+	add_cs_detail(MI, ARM_OP_GROUP_MveSaturateOp, OpNum);
+	uint32_t Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+
+	printUInt32Bang(O, (Val == 1 ? 48 : 64));
 }
 
-void ARM_addVectorDataSize(MCInst *MI, int size)
-{
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.vector_size = size;
-	}
+const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx) {
+	return getRegisterName(RegNo, AltIdx);
 }
 
-void ARM_addReg(MCInst *MI, int reg)
-{
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
-		MI->flat_insn->detail->arm.op_count++;
-	}
+void ARM_LLVM_printInstruction(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) {
+	printInst(MI, O, info);
 }
-
-void ARM_addUserMode(MCInst *MI)
-{
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.usermode = true;
-	}
-}
-
-void ARM_addSysReg(MCInst *MI, arm_sysreg reg)
-{
-	if (MI->csh->detail) {
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_SYSREG;
-		MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = reg;
-		MI->flat_insn->detail->arm.op_count++;
-	}
-}
-
-#endif
diff --git a/arch/ARM/ARMInstPrinter.h b/arch/ARM/ARMInstPrinter.h
index 4332d1a91..0e4738545 100644
--- a/arch/ARM/ARMInstPrinter.h
+++ b/arch/ARM/ARMInstPrinter.h
@@ -1,9 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
 //===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
@@ -11,33 +24,175 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+#ifndef CS_ARM_INSTPRINTER_H
+#define CS_ARM_INSTPRINTER_H
 
-#ifndef CS_ARMINSTPRINTER_H
-#define CS_ARMINSTPRINTER_H
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
 #include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
 #include "../../MCRegisterInfo.h"
 #include "../../SStream.h"
+#include "../../utils.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
 
-void ARM_printInst(MCInst *MI, SStream *O, void *Info);
-void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci);
+bool applyTargetSpecificCLOption(const char *Opt);
+// Autogenerated by tblgen.
+void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
+void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAM2PostIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAddrMode3Operand(AlwaysPrintImm0)                         \
+	void CONCAT(printAddrMode3Operand,                                         \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printAddrMode3Operand(false) DECLARE_printAddrMode3Operand(true)
 
-// setup handle->get_regname
-void ARM_getRegName(cs_struct *handle, int value);
+	void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
+								bool AlwaysPrintImm0);
+void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printLdStmModeOperand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAddrMode5Operand(AlwaysPrintImm0)                         \
+	void CONCAT(printAddrMode5Operand,                                         \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printAddrMode5Operand(false) DECLARE_printAddrMode5Operand(true)
 
-// specify vector data type for vector instructions
-void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd);
+#define DECLARE_printAddrMode5FP16Operand(AlwaysPrintImm0)                     \
+	void CONCAT(printAddrMode5FP16Operand,                                     \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+	DECLARE_printAddrMode5FP16Operand(false)
 
-void ARM_addVectorDataSize(MCInst *MI, int size);
+		void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
+void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAdrLabelOperand(scale)                                    \
+	void CONCAT(printAdrLabelOperand, scale)(MCInst * MI, unsigned OpNum,      \
+											 SStream *O);
+DECLARE_printAdrLabelOperand(0) DECLARE_printAdrLabelOperand(2)
 
-void ARM_addReg(MCInst *MI, int reg);
+#define DEFINE_printAdrLabelOperandAddr(scale)                                 \
+	static inline void CONCAT(printAdrLabelOperandAddr, scale)(                \
+		MCInst * MI, uint64_t Address, unsigned OpNum, SStream *O)             \
+	{                                                                          \
+		CONCAT(printAdrLabelOperand, scale)(MI, OpNum, O);                     \
+	}
+	DEFINE_printAdrLabelOperandAddr(0) DEFINE_printAdrLabelOperandAddr(2)
 
-// load usermode registers (LDM, STM)
-void ARM_addUserMode(MCInst *MI);
+		void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O,
+									unsigned Scale);
+void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAddrModeImm12Operand(AlwaysPrintImm0)                     \
+	void CONCAT(printAddrModeImm12Operand,                                     \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printAddrModeImm12Operand(false) DECLARE_printAddrModeImm12Operand(true)
 
-// sysreg for MRS/MSR
-void ARM_addSysReg(MCInst *MI, arm_sysreg reg);
+#define DECLARE_printT2AddrModeImm8Operand(AlwaysPrintImm0)                    \
+	void CONCAT(printT2AddrModeImm8Operand,                                    \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+	DECLARE_printT2AddrModeImm8Operand(true)
+		DECLARE_printT2AddrModeImm8Operand(false)
 
-#endif
+#define DECLARE_printT2AddrModeImm8s4Operand(AlwaysPrintImm0)                  \
+	void CONCAT(printT2AddrModeImm8s4Operand,                                  \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+			DECLARE_printT2AddrModeImm8s4Operand(false)
+				DECLARE_printT2AddrModeImm8s4Operand(true)
+
+					void printT2AddrModeImm0_1020s4Operand(MCInst *MI,
+														   unsigned OpNum,
+														   SStream *O);
+void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
+void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
+void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum,
+											  SStream *O);
+void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum,
+											SStream *O);
+void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
+void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
+void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
+void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
+void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
+void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPCLabel(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
+void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMVEVectorList(NumRegs)                                    \
+	void CONCAT(printMVEVectorList, NumRegs)(MCInst * MI, unsigned OpNum,      \
+											 SStream *O);
+DECLARE_printMVEVectorList(2) DECLARE_printMVEVectorList(4)
+
+#define DECLARE_printComplexRotationOp(Angle, Remainder)                       \
+	void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))(             \
+		MCInst * MI, unsigned OpNum, SStream *O);
+	DECLARE_printComplexRotationOp(90, 0)
+		DECLARE_printComplexRotationOp(180, 90)
+
+	// MVE
+	void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMveAddrModeRQOperand(shift)                               \
+	void CONCAT(printMveAddrModeRQOperand, shift)(MCInst * MI, unsigned OpNum, \
+												  SStream *O);
+DECLARE_printMveAddrModeRQOperand(0) DECLARE_printMveAddrModeRQOperand(3)
+	DECLARE_printMveAddrModeRQOperand(1) DECLARE_printMveAddrModeRQOperand(2)
+
+		void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O);
+
+unsigned translateShiftImm(unsigned imm);
+
+#endif // CS_ARM_INSTPRINTER_H
diff --git a/arch/ARM/ARMLinkage.h b/arch/ARM/ARMLinkage.h
new file mode 100644
index 000000000..0cdedc0da
--- /dev/null
+++ b/arch/ARM/ARMLinkage.h
@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_ARM_LINKAGE_H
+#define CS_ARM_LINKAGE_H
+
+// Function defintions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
+							MCInst *MI, uint16_t *Size, uint64_t Address,
+							void *Info);
+const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void ARM_LLVM_printInstruction(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
+
+#endif // CS_ARM_LINKAGE_H
diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c
index a8d8698c0..36c882e82 100644
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
@@ -1,356 +1,402 @@
 /* Capstone Disassembly Engine */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
 
 #ifdef CAPSTONE_HAS_ARM
 
-#include <stdio.h>	// debug
+#include <stdio.h>
 #include <string.h>
 
-#include "../../cs_priv.h"
+#include "capstone/arm.h"
+#include "capstone/capstone.h"
 
+#include "../../Mapping.h"
+#include "../../MCDisassembler.h"
+#include "../../cs_priv.h"
+#include "../../cs_simple_types.h"
+
+#include "ARMAddressingModes.h"
+#include "ARMDisassemblerExtension.h"
+#include "ARMBaseInfo.h"
+#include "ARMLinkage.h"
+#include "ARMInstPrinter.h"
 #include "ARMMapping.h"
 
-#define GET_INSTRINFO_ENUM
-#include "ARMGenInstrInfo.inc"
-
-#ifndef CAPSTONE_DIET
-static const name_map reg_name_maps[] = {
-	{ ARM_REG_INVALID, NULL },
-	{ ARM_REG_APSR, "apsr"},
-	{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
-	{ ARM_REG_CPSR, "cpsr"},
-	{ ARM_REG_FPEXC, "fpexc"},
-	{ ARM_REG_FPINST, "fpinst"},
-	{ ARM_REG_FPSCR, "fpscr"},
-	{ ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
-	{ ARM_REG_FPSID, "fpsid"},
-	{ ARM_REG_ITSTATE, "itstate"},
-	{ ARM_REG_LR, "lr"},
-	{ ARM_REG_PC, "pc"},
-	{ ARM_REG_SP, "sp"},
-	{ ARM_REG_SPSR, "spsr"},
-	{ ARM_REG_D0, "d0"},
-	{ ARM_REG_D1, "d1"},
-	{ ARM_REG_D2, "d2"},
-	{ ARM_REG_D3, "d3"},
-	{ ARM_REG_D4, "d4"},
-	{ ARM_REG_D5, "d5"},
-	{ ARM_REG_D6, "d6"},
-	{ ARM_REG_D7, "d7"},
-	{ ARM_REG_D8, "d8"},
-	{ ARM_REG_D9, "d9"},
-	{ ARM_REG_D10, "d10"},
-	{ ARM_REG_D11, "d11"},
-	{ ARM_REG_D12, "d12"},
-	{ ARM_REG_D13, "d13"},
-	{ ARM_REG_D14, "d14"},
-	{ ARM_REG_D15, "d15"},
-	{ ARM_REG_D16, "d16"},
-	{ ARM_REG_D17, "d17"},
-	{ ARM_REG_D18, "d18"},
-	{ ARM_REG_D19, "d19"},
-	{ ARM_REG_D20, "d20"},
-	{ ARM_REG_D21, "d21"},
-	{ ARM_REG_D22, "d22"},
-	{ ARM_REG_D23, "d23"},
-	{ ARM_REG_D24, "d24"},
-	{ ARM_REG_D25, "d25"},
-	{ ARM_REG_D26, "d26"},
-	{ ARM_REG_D27, "d27"},
-	{ ARM_REG_D28, "d28"},
-	{ ARM_REG_D29, "d29"},
-	{ ARM_REG_D30, "d30"},
-	{ ARM_REG_D31, "d31"},
-	{ ARM_REG_FPINST2, "fpinst2"},
-	{ ARM_REG_MVFR0, "mvfr0"},
-	{ ARM_REG_MVFR1, "mvfr1"},
-	{ ARM_REG_MVFR2, "mvfr2"},
-	{ ARM_REG_Q0, "q0"},
-	{ ARM_REG_Q1, "q1"},
-	{ ARM_REG_Q2, "q2"},
-	{ ARM_REG_Q3, "q3"},
-	{ ARM_REG_Q4, "q4"},
-	{ ARM_REG_Q5, "q5"},
-	{ ARM_REG_Q6, "q6"},
-	{ ARM_REG_Q7, "q7"},
-	{ ARM_REG_Q8, "q8"},
-	{ ARM_REG_Q9, "q9"},
-	{ ARM_REG_Q10, "q10"},
-	{ ARM_REG_Q11, "q11"},
-	{ ARM_REG_Q12, "q12"},
-	{ ARM_REG_Q13, "q13"},
-	{ ARM_REG_Q14, "q14"},
-	{ ARM_REG_Q15, "q15"},
-	{ ARM_REG_R0, "r0"},
-	{ ARM_REG_R1, "r1"},
-	{ ARM_REG_R2, "r2"},
-	{ ARM_REG_R3, "r3"},
-	{ ARM_REG_R4, "r4"},
-	{ ARM_REG_R5, "r5"},
-	{ ARM_REG_R6, "r6"},
-	{ ARM_REG_R7, "r7"},
-	{ ARM_REG_R8, "r8"},
-	{ ARM_REG_R9, "sb"},
-	{ ARM_REG_R10, "sl"},
-	{ ARM_REG_R11, "fp"},
-	{ ARM_REG_R12, "ip"},
-	{ ARM_REG_S0, "s0"},
-	{ ARM_REG_S1, "s1"},
-	{ ARM_REG_S2, "s2"},
-	{ ARM_REG_S3, "s3"},
-	{ ARM_REG_S4, "s4"},
-	{ ARM_REG_S5, "s5"},
-	{ ARM_REG_S6, "s6"},
-	{ ARM_REG_S7, "s7"},
-	{ ARM_REG_S8, "s8"},
-	{ ARM_REG_S9, "s9"},
-	{ ARM_REG_S10, "s10"},
-	{ ARM_REG_S11, "s11"},
-	{ ARM_REG_S12, "s12"},
-	{ ARM_REG_S13, "s13"},
-	{ ARM_REG_S14, "s14"},
-	{ ARM_REG_S15, "s15"},
-	{ ARM_REG_S16, "s16"},
-	{ ARM_REG_S17, "s17"},
-	{ ARM_REG_S18, "s18"},
-	{ ARM_REG_S19, "s19"},
-	{ ARM_REG_S20, "s20"},
-	{ ARM_REG_S21, "s21"},
-	{ ARM_REG_S22, "s22"},
-	{ ARM_REG_S23, "s23"},
-	{ ARM_REG_S24, "s24"},
-	{ ARM_REG_S25, "s25"},
-	{ ARM_REG_S26, "s26"},
-	{ ARM_REG_S27, "s27"},
-	{ ARM_REG_S28, "s28"},
-	{ ARM_REG_S29, "s29"},
-	{ ARM_REG_S30, "s30"},
-	{ ARM_REG_S31, "s31"},
-};
-static const name_map reg_name_maps2[] = {
-	{ ARM_REG_INVALID, NULL },
-	{ ARM_REG_APSR, "apsr"},
-	{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
-	{ ARM_REG_CPSR, "cpsr"},
-	{ ARM_REG_FPEXC, "fpexc"},
-	{ ARM_REG_FPINST, "fpinst"},
-	{ ARM_REG_FPSCR, "fpscr"},
-	{ ARM_REG_FPSCR_NZCV, "fpscr_nzcv"},
-	{ ARM_REG_FPSID, "fpsid"},
-	{ ARM_REG_ITSTATE, "itstate"},
-	{ ARM_REG_LR, "lr"},
-	{ ARM_REG_PC, "pc"},
-	{ ARM_REG_SP, "sp"},
-	{ ARM_REG_SPSR, "spsr"},
-	{ ARM_REG_D0, "d0"},
-	{ ARM_REG_D1, "d1"},
-	{ ARM_REG_D2, "d2"},
-	{ ARM_REG_D3, "d3"},
-	{ ARM_REG_D4, "d4"},
-	{ ARM_REG_D5, "d5"},
-	{ ARM_REG_D6, "d6"},
-	{ ARM_REG_D7, "d7"},
-	{ ARM_REG_D8, "d8"},
-	{ ARM_REG_D9, "d9"},
-	{ ARM_REG_D10, "d10"},
-	{ ARM_REG_D11, "d11"},
-	{ ARM_REG_D12, "d12"},
-	{ ARM_REG_D13, "d13"},
-	{ ARM_REG_D14, "d14"},
-	{ ARM_REG_D15, "d15"},
-	{ ARM_REG_D16, "d16"},
-	{ ARM_REG_D17, "d17"},
-	{ ARM_REG_D18, "d18"},
-	{ ARM_REG_D19, "d19"},
-	{ ARM_REG_D20, "d20"},
-	{ ARM_REG_D21, "d21"},
-	{ ARM_REG_D22, "d22"},
-	{ ARM_REG_D23, "d23"},
-	{ ARM_REG_D24, "d24"},
-	{ ARM_REG_D25, "d25"},
-	{ ARM_REG_D26, "d26"},
-	{ ARM_REG_D27, "d27"},
-	{ ARM_REG_D28, "d28"},
-	{ ARM_REG_D29, "d29"},
-	{ ARM_REG_D30, "d30"},
-	{ ARM_REG_D31, "d31"},
-	{ ARM_REG_FPINST2, "fpinst2"},
-	{ ARM_REG_MVFR0, "mvfr0"},
-	{ ARM_REG_MVFR1, "mvfr1"},
-	{ ARM_REG_MVFR2, "mvfr2"},
-	{ ARM_REG_Q0, "q0"},
-	{ ARM_REG_Q1, "q1"},
-	{ ARM_REG_Q2, "q2"},
-	{ ARM_REG_Q3, "q3"},
-	{ ARM_REG_Q4, "q4"},
-	{ ARM_REG_Q5, "q5"},
-	{ ARM_REG_Q6, "q6"},
-	{ ARM_REG_Q7, "q7"},
-	{ ARM_REG_Q8, "q8"},
-	{ ARM_REG_Q9, "q9"},
-	{ ARM_REG_Q10, "q10"},
-	{ ARM_REG_Q11, "q11"},
-	{ ARM_REG_Q12, "q12"},
-	{ ARM_REG_Q13, "q13"},
-	{ ARM_REG_Q14, "q14"},
-	{ ARM_REG_Q15, "q15"},
-	{ ARM_REG_R0, "r0"},
-	{ ARM_REG_R1, "r1"},
-	{ ARM_REG_R2, "r2"},
-	{ ARM_REG_R3, "r3"},
-	{ ARM_REG_R4, "r4"},
-	{ ARM_REG_R5, "r5"},
-	{ ARM_REG_R6, "r6"},
-	{ ARM_REG_R7, "r7"},
-	{ ARM_REG_R8, "r8"},
-	{ ARM_REG_R9, "r9"},
-	{ ARM_REG_R10, "r10"},
-	{ ARM_REG_R11, "r11"},
-	{ ARM_REG_R12, "r12"},
-	{ ARM_REG_S0, "s0"},
-	{ ARM_REG_S1, "s1"},
-	{ ARM_REG_S2, "s2"},
-	{ ARM_REG_S3, "s3"},
-	{ ARM_REG_S4, "s4"},
-	{ ARM_REG_S5, "s5"},
-	{ ARM_REG_S6, "s6"},
-	{ ARM_REG_S7, "s7"},
-	{ ARM_REG_S8, "s8"},
-	{ ARM_REG_S9, "s9"},
-	{ ARM_REG_S10, "s10"},
-	{ ARM_REG_S11, "s11"},
-	{ ARM_REG_S12, "s12"},
-	{ ARM_REG_S13, "s13"},
-	{ ARM_REG_S14, "s14"},
-	{ ARM_REG_S15, "s15"},
-	{ ARM_REG_S16, "s16"},
-	{ ARM_REG_S17, "s17"},
-	{ ARM_REG_S18, "s18"},
-	{ ARM_REG_S19, "s19"},
-	{ ARM_REG_S20, "s20"},
-	{ ARM_REG_S21, "s21"},
-	{ ARM_REG_S22, "s22"},
-	{ ARM_REG_S23, "s23"},
-	{ ARM_REG_S24, "s24"},
-	{ ARM_REG_S25, "s25"},
-	{ ARM_REG_S26, "s26"},
-	{ ARM_REG_S27, "s27"},
-	{ ARM_REG_S28, "s28"},
-	{ ARM_REG_S29, "s29"},
-	{ ARM_REG_S30, "s30"},
-	{ ARM_REG_S31, "s31"},
-};
-#endif
+static const char *get_custom_reg_alias(unsigned reg) {
+	switch(reg) {
+	case ARM_REG_R9:
+		return "sb";
+	case ARM_REG_R10:
+		return "sl";
+	case ARM_REG_R11:
+		return "fp";
+	case ARM_REG_R12:
+		return "ip";
+	case ARM_REG_R13:
+		return "sp";
+	case ARM_REG_R14:
+		return "lr";
+	case ARM_REG_R15:
+		return "pc";
+	}
+	return NULL;
+}
 
 const char *ARM_reg_name(csh handle, unsigned int reg)
 {
-#ifndef CAPSTONE_DIET
-	if (reg >= ARR_SIZE(reg_name_maps))
-		return NULL;
+	int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
+	const char *alias = get_custom_reg_alias(reg);
+	if ((syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS) && alias)
+		return alias;
 
-	return reg_name_maps[reg].name;
-#else
-	return NULL;
-#endif
-}
-
-const char *ARM_reg_name2(csh handle, unsigned int reg)
-{
-#ifndef CAPSTONE_DIET
-	if (reg >= ARR_SIZE(reg_name_maps2))
-		return NULL;
-
-	return reg_name_maps2[reg].name;
-#else
-	return NULL;
-#endif
-}
-
-static const insn_map insns[] = {
-	// dummy item
-	{
-		0, 0,
-#ifndef CAPSTONE_DIET
-		{ 0 }, { 0 }, { 0 }, 0, 0
-#endif
-	},
-#include "ARMMappingInsn.inc"
-};
-
-// look for @id in @insns
-// return -1 if not found
-static unsigned int find_insn(unsigned int id)
-{
-	// binary searching since the IDs are sorted in order
-	unsigned int left, right, m;
-	unsigned int max = ARR_SIZE(insns);
-
-	right = max - 1;
-
-	if (id < insns[0].id || id > insns[right].id)
-		// not found
-		return -1;
-
-	left = 0;
-
-	while(left <= right) {
-		m = (left + right) / 2;
-		if (id == insns[m].id) {
-			return m;
-		}
-
-		if (id < insns[m].id)
-			right = m - 1;
-		else
-			left = m + 1;
+	if (reg == ARM_REG_INVALID || reg >= ARM_REG_ENDING) {
+		// This might be a system register encoding.
+		const ARMBankedReg_BankedReg *banked_reg = ARMBankedReg_lookupBankedRegByEncoding(reg);
+		if (banked_reg)
+			return banked_reg->Name;
+		const ARMSysReg_MClassSysReg *sys_reg = ARMSysReg_lookupMClassSysRegByEncoding(reg);
+		if (sys_reg)
+			return sys_reg->Name;
 	}
 
-	// not found
-	// printf("NOT FOUNDDDDDDDDDDDDDDD id = %u\n", id);
-	return -1;
+	if (syntax_opt & CS_OPT_SYNTAX_NOREGNAME) {
+		return ARM_LLVM_getRegisterName(reg, ARM_NoRegAltName);
+	}
+	return ARM_LLVM_getRegisterName(reg, ARM_RegNamesRaw);
 }
 
+const insn_map arm_insns[] = {
+#include "ARMGenCSMappingInsn.inc"
+};
+
 void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
 {
-	unsigned int i = find_insn(id);
-	if (i != -1) {
-		insn->id = insns[i].mapid;
+	// Not used by ARM. Information is set after disassembly.
+}
 
-		// printf("id = %u, mapid = %u\n", id, insn->id);
-
-		if (h->detail) {
-#ifndef CAPSTONE_DIET
-			cs_struct handle;
-			handle.detail = h->detail;
-
-			memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
-			insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
-
-			memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
-			insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
-
-			memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
-			insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
-
-			insn->detail->arm.update_flags = cs_reg_write((csh)&handle, insn, ARM_REG_CPSR);
-
-			if (insns[i].branch || insns[i].indirect_branch) {
-				// this insn also belongs to JUMP group. add JUMP group
-				insn->detail->groups[insn->detail->groups_count] = ARM_GRP_JUMP;
-				insn->detail->groups_count++;
-			}
-#endif
-		}
+/// Patches the register names with Capstone specific alias.
+/// Those are common alias for registers (e.g. r15 = pc)
+/// which are not set in LLVM.
+static void patch_cs_reg_alias(char *asm_str) {
+	char *r9 = strstr(asm_str, "r9");
+	while (r9) {
+		r9[0] = 's';
+		r9[1] = 'b';
+		r9 = strstr(asm_str, "r9");
+	}
+	char *r10 = strstr(asm_str, "r10");
+	while (r10) {
+		r10[0] = 's';
+		r10[1] = 'l';
+		memmove(r10+2, r10+3, strlen(r10+3));
+		asm_str[strlen(asm_str) - 1] = '\0';
+		r10 = strstr(asm_str, "r10");
+	}
+	char *r11 = strstr(asm_str, "r11");
+	while (r11) {
+		r11[0] = 'f';
+		r11[1] = 'p';
+		memmove(r11+2, r11+3, strlen(r11+3));
+		asm_str[strlen(asm_str) - 1] = '\0';
+		r11 = strstr(asm_str, "r11");
+	}
+	char *r12 = strstr(asm_str, "r12");
+	while (r12) {
+		r12[0] = 'i';
+		r12[1] = 'p';
+		memmove(r12+2, r12+3, strlen(r12+3));
+		asm_str[strlen(asm_str) - 1] = '\0';
+		r12 = strstr(asm_str, "r12");
+	}
+	char *r13 = strstr(asm_str, "r13");
+	while (r13) {
+		r13[0] = 's';
+		r13[1] = 'p';
+		memmove(r13+2, r13+3, strlen(r13+3));
+		asm_str[strlen(asm_str) - 1] = '\0';
+		r13 = strstr(asm_str, "r13");
+	}
+	char *r14 = strstr(asm_str, "r14");
+	while (r14) {
+		r14[0] = 'l';
+		r14[1] = 'r';
+		memmove(r14+2, r14+3, strlen(r14+3));
+		asm_str[strlen(asm_str) - 1] = '\0';
+		r14 = strstr(asm_str, "r14");
+	}
+	char *r15 = strstr(asm_str, "r15");
+	while (r15) {
+		r15[0] = 'p';
+		r15[1] = 'c';
+		memmove(r15+2, r15+3, strlen(r15+3));
+		asm_str[strlen(asm_str) - 1] = '\0';
+		r15 = strstr(asm_str, "r15");
 	}
 }
 
+/// Adds group to the instruction which are not defined in LLVM.
+static void ARM_add_cs_groups(MCInst *MI) {
+	unsigned Opcode = MI->flat_insn->id;
+	switch (Opcode) {
+	default:
+		return;
+	case ARM_INS_SVC:
+		add_group(MI, ARM_GRP_INT);
+		break;
+	case ARM_INS_CDP:
+	case ARM_INS_CDP2:
+	case ARM_INS_MCR:
+	case ARM_INS_MCR2:
+	case ARM_INS_MCRR:
+	case ARM_INS_MCRR2:
+	case ARM_INS_MRC:
+	case ARM_INS_MRC2:
+	case ARM_INS_SMC:
+		add_group(MI, ARM_GRP_PRIVILEGE);
+		break;
+	}
+}
+
+/// Some instructions have their operands not defined but
+/// hardcoded as string.
+/// Here we add those oprands to detail.
+static void ARM_add_not_defined_ops(MCInst *MI) {
+	unsigned Opcode = MCInst_getOpcode(MI);
+	switch (Opcode) {
+	default:
+		return;
+	case ARM_BX_RET:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_LR, CS_AC_READ);
+		break;
+	case ARM_MOVPCLR:
+	case ARM_t2SUBS_PC_LR:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_PC, CS_AC_WRITE);
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_LR, CS_AC_READ);
+		break;
+	case ARM_FMSTAT:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_APSR_NZCV, CS_AC_WRITE);
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR, CS_AC_READ);
+		break;
+	case ARM_VLDR_FPCXTNS_off:
+	case ARM_VLDR_FPCXTNS_post:
+	case ARM_VLDR_FPCXTNS_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTNS, CS_AC_WRITE);
+		break;
+	case ARM_VSTR_FPCXTNS_off:
+	case ARM_VSTR_FPCXTNS_post:
+	case ARM_VSTR_FPCXTNS_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTNS, CS_AC_READ);
+		break;
+	case ARM_VLDR_FPCXTS_off:
+	case ARM_VLDR_FPCXTS_post:
+	case ARM_VLDR_FPCXTS_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTS, CS_AC_WRITE);
+		break;
+	case ARM_VSTR_FPCXTS_off:
+	case ARM_VSTR_FPCXTS_post:
+	case ARM_VSTR_FPCXTS_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPCXTS, CS_AC_READ);
+		break;
+	case ARM_VLDR_FPSCR_NZCVQC_off:
+	case ARM_VLDR_FPSCR_NZCVQC_post:
+	case ARM_VLDR_FPSCR_NZCVQC_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR_NZCVQC, CS_AC_WRITE);
+		break;
+	case ARM_VSTR_FPSCR_NZCVQC_off:
+	case ARM_VSTR_FPSCR_NZCVQC_post:
+	case ARM_VSTR_FPSCR_NZCVQC_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR_NZCVQC, CS_AC_READ);
+		break;
+	case ARM_VMSR:
+	case ARM_VLDR_FPSCR_off:
+	case ARM_VLDR_FPSCR_post:
+	case ARM_VLDR_FPSCR_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR, CS_AC_WRITE);
+		break;
+	case ARM_VSTR_FPSCR_off:
+	case ARM_VSTR_FPSCR_post:
+	case ARM_VSTR_FPSCR_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSCR, CS_AC_READ);
+		break;
+	case ARM_VLDR_P0_off:
+	case ARM_VLDR_P0_post:
+	case ARM_VLDR_P0_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_P0, CS_AC_WRITE);
+		break;
+	case ARM_VSTR_P0_off:
+	case ARM_VSTR_P0_post:
+	case ARM_VSTR_P0_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_P0, CS_AC_READ);
+		break;
+	case ARM_VLDR_VPR_off:
+	case ARM_VLDR_VPR_post:
+	case ARM_VLDR_VPR_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_VPR, CS_AC_WRITE);
+		break;
+	case ARM_VSTR_VPR_off:
+	case ARM_VSTR_VPR_post:
+	case ARM_VSTR_VPR_pre:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_VPR, CS_AC_READ);
+		break;
+	case ARM_VMSR_FPEXC:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPEXC, CS_AC_WRITE);
+		break;
+	case ARM_VMSR_FPINST:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPINST, CS_AC_WRITE);
+		break;
+	case ARM_VMSR_FPINST2:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPINST2, CS_AC_WRITE);
+		break;
+	case ARM_VMSR_FPSID:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_FPSID, CS_AC_WRITE);
+		break;
+	case ARM_t2SRSDB:
+	case ARM_t2SRSIA:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_SP, CS_AC_WRITE);
+		break;
+	case ARM_t2SRSDB_UPD:
+	case ARM_t2SRSIA_UPD:
+		ARM_insert_detail_op_reg_at(MI, 0, ARM_REG_SP, CS_AC_READ | CS_AC_WRITE);
+		break;
+	case ARM_MRSsys:
+	case ARM_t2MRSsys_AR:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_SPSR, CS_AC_READ);
+		break;
+	case ARM_MRS:
+	case ARM_t2MRS_AR:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_APSR, CS_AC_READ);
+		break;
+	case ARM_VMRS:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPCXTNS:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPCXTNS, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPCXTS:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPCXTS, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPEXC:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPEXC, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPINST:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPINST, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPINST2:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPINST2, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPSCR_NZCVQC:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSCR_NZCVQC, CS_AC_READ);
+		break;
+	case ARM_VMRS_FPSID:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_FPSID, CS_AC_READ);
+		break;
+	case ARM_VMRS_MVFR0:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR0, CS_AC_READ);
+		break;
+	case ARM_VMRS_MVFR1:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR1, CS_AC_READ);
+		break;
+	case ARM_VMRS_MVFR2:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_MVFR2, CS_AC_READ);
+		break;
+	case ARM_VMRS_P0:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_P0, CS_AC_READ);
+		break;
+	case ARM_VMRS_VPR:
+		ARM_insert_detail_op_reg_at(MI, 1, ARM_REG_VPR, CS_AC_READ);
+		break;
+	case ARM_MOVsr:
+		// Add shift information
+		ARM_get_detail(MI)->operands[1].shift.type = (arm_shifter) ARM_AM_getSORegShOp(MCInst_getOpVal(MI, 3)) + ARM_SFT_ASR_REG - 1;
+		ARM_get_detail(MI)->operands[1].shift.value = MCInst_getOpVal(MI, 2);
+		break;
+	case ARM_MOVsi:
+		if (ARM_AM_getSORegShOp(MCInst_getOpVal(MI, 2)) == ARM_AM_rrx) {
+			ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_RRX;
+			ARM_get_detail_op(MI, -1)->shift.value = translateShiftImm(ARM_AM_getSORegOffset(MCInst_getOpVal(MI, 2)));
+			return;
+		}
+
+		ARM_get_detail_op(MI, -1)->shift.type = (arm_shifter) ARM_AM_getSORegShOp(MCInst_getOpVal(MI, 2));
+		ARM_get_detail_op(MI, -1)->shift.value = translateShiftImm(ARM_AM_getSORegOffset(MCInst_getOpVal(MI, 2)));
+		break;
+	case ARM_STMDB_UPD:
+	case ARM_t2STMDB_UPD:
+		if (MCInst_getOpVal(MI, 0) == ARM_SP &&
+			MCInst_getNumOperands(MI) > 5)
+			MI->flat_insn->id = ARM_INS_PUSH;
+		break;
+	case ARM_STR_PRE_IMM:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP &&
+			MCOperand_getImm(MCInst_getOperand(MI, (3))) == -4)
+			MI->flat_insn->id = ARM_INS_PUSH;
+		break;
+	case ARM_LDMIA_UPD:
+	case ARM_t2LDMIA_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP &&
+			MCInst_getNumOperands(MI) > 5)
+			MI->flat_insn->id = ARM_INS_POP;
+		break;
+	case ARM_LDR_POST_IMM:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (2))) == ARM_SP &&
+			ARM_AM_getAM2Offset(MCOperand_getImm(MCInst_getOperand(MI, (4)))) == 4)
+			MI->flat_insn->id = ARM_INS_POP;
+		break;
+	case ARM_VSTMSDB_UPD:
+	case ARM_VSTMDDB_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP)
+			MI->flat_insn->id = ARM_INS_VPUSH;
+		break;
+	case ARM_VLDMSIA_UPD:
+	case ARM_VLDMDIA_UPD:
+		if (MCOperand_getReg(MCInst_getOperand(MI, (0))) == ARM_SP)
+			MI->flat_insn->id = ARM_INS_VPOP;
+		break;
+	case ARM_tLDMIA: {
+		bool Writeback = true;
+		unsigned BaseReg = MCInst_getOpVal(MI, 0);
+		for (unsigned i = 3; i < MCInst_getNumOperands(MI); ++i) {
+			if (MCInst_getOpVal(MI, i) == BaseReg)
+				Writeback = false;
+		}
+		if (Writeback && detail_is_set(MI)) {
+			ARM_get_detail(MI)->operands[0].access |= CS_AC_WRITE;
+			MI->flat_insn->detail->writeback = true;
+		}
+	}
+	}
+}
+
+/// Decodes the asm string for a given instruction
+/// and fills the detail information about the instruction and its operands.
+void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info) {
+	ARM_LLVM_printInstruction(MI, O, info);
+	ARM_add_not_defined_ops(MI);
+	ARM_add_cs_groups(MI);
+	int syntax_opt = MI->csh->syntax;
+	if (syntax_opt & CS_OPT_SYNTAX_CS_REG_ALIAS)
+		patch_cs_reg_alias(O->buffer);
+
+}
+
 #ifndef CAPSTONE_DIET
-static const char * const insn_name_maps[] = {
-	NULL, // ARM_INS_INVALID
-#include "ARMMappingInsnName.inc"
+static const char *const insn_name_maps[] = {
+#include "ARMGenCSMappingInsnName.inc"
+	// Hard coded alias in LLVM, not defined as alias or instruction.
+	// We give them a unique ID for convenience.
+	"vpop",
+	"vpush",
 };
 #endif
 
+#ifndef CAPSTONE_DIET
+static arm_reg arm_flag_regs[] = {
+	ARM_REG_APSR,		ARM_REG_APSR_NZCV,	  ARM_REG_CPSR,	  ARM_REG_FPCXTNS,
+	ARM_REG_FPCXTS,		ARM_REG_FPEXC,		  ARM_REG_FPINST, ARM_REG_FPSCR,
+	ARM_REG_FPSCR_NZCV, ARM_REG_FPSCR_NZCVQC,
+};
+#endif // CAPSTONE_DIET
+
 const char *ARM_insn_name(csh handle, unsigned int id)
 {
 #ifndef CAPSTONE_DIET
@@ -366,46 +412,15 @@ const char *ARM_insn_name(csh handle, unsigned int id)
 #ifndef CAPSTONE_DIET
 static const name_map group_name_maps[] = {
 	// generic groups
-	{ ARM_GRP_INVALID, NULL },
-	{ ARM_GRP_JUMP,	"jump" },
-	{ ARM_GRP_CALL,	"call" },
-	{ ARM_GRP_INT,	"int" },
-	{ ARM_GRP_PRIVILEGE, "privilege" },
-	{ ARM_GRP_BRANCH_RELATIVE, "branch_relative" },
+	{ARM_GRP_INVALID, NULL},
+	{ARM_GRP_JUMP, "jump"},
+	{ARM_GRP_CALL, "call"},
+	{ARM_GRP_INT, "int"},
+	{ARM_GRP_PRIVILEGE, "privilege"},
+	{ARM_GRP_BRANCH_RELATIVE, "branch_relative"},
 
-	// architecture-specific groups
-	{ ARM_GRP_CRYPTO, "crypto" },
-	{ ARM_GRP_DATABARRIER, "databarrier" },
-	{ ARM_GRP_DIVIDE, "divide" },
-	{ ARM_GRP_FPARMV8, "fparmv8" },
-	{ ARM_GRP_MULTPRO, "multpro" },
-	{ ARM_GRP_NEON, "neon" },
-	{ ARM_GRP_T2EXTRACTPACK, "T2EXTRACTPACK" },
-	{ ARM_GRP_THUMB2DSP, "THUMB2DSP" },
-	{ ARM_GRP_TRUSTZONE, "TRUSTZONE" },
-	{ ARM_GRP_V4T, "v4t" },
-	{ ARM_GRP_V5T, "v5t" },
-	{ ARM_GRP_V5TE, "v5te" },
-	{ ARM_GRP_V6, "v6" },
-	{ ARM_GRP_V6T2, "v6t2" },
-	{ ARM_GRP_V7, "v7" },
-	{ ARM_GRP_V8, "v8" },
-	{ ARM_GRP_VFP2, "vfp2" },
-	{ ARM_GRP_VFP3, "vfp3" },
-	{ ARM_GRP_VFP4, "vfp4" },
-	{ ARM_GRP_ARM, "arm" },
-	{ ARM_GRP_MCLASS, "mclass" },
-	{ ARM_GRP_NOTMCLASS, "notmclass" },
-	{ ARM_GRP_THUMB, "thumb" },
-	{ ARM_GRP_THUMB1ONLY, "thumb1only" },
-	{ ARM_GRP_THUMB2, "thumb2" },
-	{ ARM_GRP_PREV8, "prev8" },
-	{ ARM_GRP_FPVMLX, "fpvmlx" },
-	{ ARM_GRP_MULOPS, "mulops" },
-	{ ARM_GRP_CRC, "crc" },
-	{ ARM_GRP_DPVFP, "dpvfp" },
-	{ ARM_GRP_V6M, "v6m" },
-	{ ARM_GRP_VIRTUALIZATION, "virtualization" },
+// architecture-specific groups
+#include "ARMGenCSFeatureName.inc"
 };
 #endif
 
@@ -421,26 +436,11 @@ const char *ARM_group_name(csh handle, unsigned int id)
 // list all relative branch instructions
 // ie: insns[i].branch && !insns[i].indirect_branch
 static const unsigned int insn_rel[] = {
-	ARM_BL,
-	ARM_BLX_pred,
-	ARM_Bcc,
-	ARM_t2B,
-	ARM_t2Bcc,
-	ARM_tB,
-	ARM_tBcc,
-	ARM_tCBNZ,
-	ARM_tCBZ,
-	ARM_BL_pred,
-	ARM_BLXi,
-	ARM_tBL,
-	ARM_tBLXi,
-	0
-};
+	ARM_BL,	  ARM_BLX_pred, ARM_Bcc,   ARM_t2B,	 ARM_t2Bcc,
+	ARM_tB,	  ARM_tBcc,		ARM_tCBNZ, ARM_tCBZ, ARM_BL_pred,
+	ARM_BLXi, ARM_tBL,		ARM_tBLXi, 0};
 
-static const unsigned int insn_blx_rel_to_arm[] = {
-	ARM_tBLXi,
-	0
-};
+static const unsigned int insn_blx_rel_to_arm[] = {ARM_tBLXi, 0};
 
 // check if this insn is relative branch
 bool ARM_rel_branch(cs_struct *h, unsigned int id)
@@ -457,7 +457,8 @@ bool ARM_rel_branch(cs_struct *h, unsigned int id)
 	return false;
 }
 
-bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
+bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id)
+{
 	int i;
 
 	for (i = 0; insn_blx_rel_to_arm[i]; i++)
@@ -466,38 +467,65 @@ bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int id) {
 
 	// not found
 	return false;
-
 }
 
+void ARM_check_updates_flags(MCInst *MI)
+{
 #ifndef CAPSTONE_DIET
-// map instruction to its characteristics
-typedef struct insn_op {
-	uint8_t access[7];
-} insn_op;
+	if (!detail_is_set(MI))
+		return;
+	cs_detail *detail = get_detail(MI);
+	for (int i = 0; i < detail->regs_write_count; ++i) {
+		if (detail->regs_write[i] == 0)
+			return;
+		for (int j = 0; j < ARR_SIZE(arm_flag_regs); ++j) {
+			if (detail->regs_write[i] == arm_flag_regs[j]) {
+				detail->arm.update_flags = true;
+				return;
+			}
+		}
+	}
+#endif // CAPSTONE_DIET
+}
 
-static const insn_op insn_ops[] = {
-	{
-		// NULL item
-		{ 0 }
-	},
+void ARM_set_instr_map_data(MCInst *MI)
+{
+	map_cs_id(MI, arm_insns, ARR_SIZE(arm_insns));
+	map_implicit_reads(MI, arm_insns);
+	map_implicit_writes(MI, arm_insns);
+	ARM_check_updates_flags(MI);
+	map_groups(MI, arm_insns);
+}
 
-#include "ARMMappingInsnOp.inc"
+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+						MCInst *instr, uint16_t *size, uint64_t address,
+						void *info)
+{
+	ARM_init_cs_detail(instr);
+	bool Result = ARM_LLVM_getInstruction(handle, code, code_len, instr, size, address,
+								 info) != MCDisassembler_Fail;
+	ARM_set_instr_map_data(instr);
+	return Result;
+}
+
+#define GET_REGINFO_MC_DESC
+#include "ARMGenRegisterInfo.inc"
+
+void ARM_init_mri(MCRegisterInfo *MRI)
+{
+	MCRegisterInfo_InitMCRegisterInfo(
+		MRI, ARMRegDesc, 289, 0, 0, ARMMCRegisterClasses, 103, 0, 0,
+		ARMRegDiffLists, 0, ARMSubRegIdxLists, 57, 0);
+}
+
+static const map_insn_ops insn_operands[] = {
+#include "ARMGenCSMappingInsnOp.inc"
 };
 
-// given internal insn id, return operand access info
-const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id)
-{
-	int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
-	if (i != 0) {
-		return insn_ops[i].access;
-	}
-
-	return NULL;
-}
-
-void ARM_reg_access(const cs_insn *insn,
-		cs_regs regs_read, uint8_t *regs_read_count,
-		cs_regs regs_write, uint8_t *regs_write_count)
+#ifndef CAPSTONE_DIET
+void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,
+					uint8_t *regs_read_count, cs_regs regs_write,
+					uint8_t *regs_write_count)
 {
 	uint8_t i;
 	uint8_t read_count, write_count;
@@ -507,39 +535,47 @@ void ARM_reg_access(const cs_insn *insn,
 	write_count = insn->detail->regs_write_count;
 
 	// implicit registers
-	memcpy(regs_read, insn->detail->regs_read, read_count * sizeof(insn->detail->regs_read[0]));
-	memcpy(regs_write, insn->detail->regs_write, write_count * sizeof(insn->detail->regs_write[0]));
+	memcpy(regs_read, insn->detail->regs_read,
+		   read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+		   write_count * sizeof(insn->detail->regs_write[0]));
 
 	// explicit registers
 	for (i = 0; i < arm->op_count; i++) {
 		cs_arm_op *op = &(arm->operands[i]);
-		switch((int)op->type) {
-			case ARM_OP_REG:
-				if ((op->access & CS_AC_READ) && !arr_exist(regs_read, read_count, op->reg)) {
-					regs_read[read_count] = (uint16_t)op->reg;
-					read_count++;
-				}
-				if ((op->access & CS_AC_WRITE) && !arr_exist(regs_write, write_count, op->reg)) {
-					regs_write[write_count] = (uint16_t)op->reg;
-					write_count++;
-				}
-				break;
-			case ARM_OP_MEM:
-				// registers appeared in memory references always being read
-				if ((op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.base)) {
-					regs_read[read_count] = (uint16_t)op->mem.base;
-					read_count++;
-				}
-				if ((op->mem.index != ARM_REG_INVALID) && !arr_exist(regs_read, read_count, op->mem.index)) {
-					regs_read[read_count] = (uint16_t)op->mem.index;
-					read_count++;
-				}
-				if ((arm->writeback) && (op->mem.base != ARM_REG_INVALID) && !arr_exist(regs_write, write_count, op->mem.base)) {
-					regs_write[write_count] = (uint16_t)op->mem.base;
-					write_count++;
-				}
-			default:
-				break;
+		switch ((int)op->type) {
+		case ARM_OP_REG:
+			if ((op->access & CS_AC_READ) &&
+				!arr_exist(regs_read, read_count, op->reg)) {
+				regs_read[read_count] = (uint16_t)op->reg;
+				read_count++;
+			}
+			if ((op->access & CS_AC_WRITE) &&
+				!arr_exist(regs_write, write_count, op->reg)) {
+				regs_write[write_count] = (uint16_t)op->reg;
+				write_count++;
+			}
+			break;
+		case ARM_OP_MEM:
+			// registers appeared in memory references always being read
+			if ((op->mem.base != ARM_REG_INVALID) &&
+				!arr_exist(regs_read, read_count, op->mem.base)) {
+				regs_read[read_count] = (uint16_t)op->mem.base;
+				read_count++;
+			}
+			if ((op->mem.index != ARM_REG_INVALID) &&
+				!arr_exist(regs_read, read_count, op->mem.index)) {
+				regs_read[read_count] = (uint16_t)op->mem.index;
+				read_count++;
+			}
+			if ((insn->detail->writeback) &&
+				(op->mem.base != ARM_REG_INVALID) &&
+				!arr_exist(regs_write, write_count, op->mem.base)) {
+				regs_write[write_count] = (uint16_t)op->mem.base;
+				write_count++;
+			}
+		default:
+			break;
 		}
 	}
 
@@ -548,4 +584,1165 @@ void ARM_reg_access(const cs_insn *insn,
 }
 #endif
 
+void ARM_setup_op(cs_arm_op *op) {
+	memset(op, 0, sizeof(cs_arm_op));
+	op->type = ARM_OP_INVALID;
+	op->vector_index = -1;
+	op->neon_lane = -1;
+}
+
+
+void ARM_init_cs_detail(MCInst *MI)
+{
+	if (detail_is_set(MI)) {
+		unsigned int i;
+
+		memset(get_detail(MI), 0,
+			   offsetof(cs_detail, arm) + sizeof(cs_arm));
+
+		for (i = 0; i < ARR_SIZE(ARM_get_detail(MI)->operands); i++)
+			ARM_setup_op(&ARM_get_detail(MI)->operands[i]);
+		ARM_get_detail(MI)->cc = ARMCC_UNDEF;
+		ARM_get_detail(MI)->vcc = ARMVCC_None;
+	}
+}
+
+static uint64_t t_add_pc(MCInst *MI, uint64_t v)
+{
+	int32_t imm = (int32_t)v;
+	if (ARM_rel_branch(MI->csh, MI->Opcode)) {
+		uint32_t address;
+
+		// only do this for relative branch
+		if (MI->csh->mode & CS_MODE_THUMB) {
+			address = (uint32_t)MI->address + 4;
+			if (ARM_blx_to_arm_mode(MI->csh, MI->Opcode)) {
+				// here need to align down to the nearest 4-byte address
+#define _ALIGN_DOWN(v, align_width) ((v / align_width) * align_width)
+				address = _ALIGN_DOWN(address, 4);
+#undef _ALIGN_DOWN
+			}
+		} else {
+			address = (uint32_t)MI->address + 8;
+		}
+
+		imm += address;
+		return imm;
+	}
+	return v;
+}
+
+/// Transform a Qs register to its corresponding Ds + Offset register.
+static uint64_t t_qpr_to_dpr_list(MCInst *MI, unsigned OpNum, uint8_t offset)
+{
+	uint64_t v = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
+	if (v >= ARM_REG_Q0 && v <= ARM_REG_Q15)
+		return ARM_REG_D0 + offset + (v - ARM_REG_Q0) * 2;
+	return v + offset;
+}
+
+static uint64_t t_mod_imm_rotate(uint64_t v)
+{
+	unsigned Bits = v & 0xFF;
+	unsigned Rot = (v & 0xF00) >> 7;
+	int32_t Rotated = ARM_AM_rotr32(Bits, Rot);
+	return Rotated;
+}
+
+inline static uint64_t t_mod_imm_bits(uint64_t v)
+{
+	unsigned Bits = v & 0xFF;
+	return Bits;
+}
+
+inline static uint64_t t_mod_imm_rot(uint64_t v)
+{
+	unsigned Rot = (v & 0xF00) >> 7;
+	return Rot;
+}
+
+static uint64_t t_vmov_mod_imm(uint64_t v)
+{
+	unsigned EltBits;
+	uint64_t Val = ARM_AM_decodeVMOVModImm(v, &EltBits);
+	return Val;
+}
+
+/// Initializes or finishes a memory operand of Capstone (depending on \p
+/// status). A memory operand in Capstone can be assembled by two LLVM operands.
+/// E.g. the base register and the immediate disponent.
+static void ARM_set_mem_access(MCInst *MI, bool status)
+{
+	if (!detail_is_set(MI))
+		return;
+	set_doing_mem(MI, status);
+	if (status) {
+		ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM;
+		ARM_get_detail_op(MI, 0)->mem.base = ARM_REG_INVALID;
+		ARM_get_detail_op(MI, 0)->mem.index = ARM_REG_INVALID;
+		ARM_get_detail_op(MI, 0)->mem.scale = 1;
+		ARM_get_detail_op(MI, 0)->mem.disp = 0;
+
+#ifndef CAPSTONE_DIET
+		uint8_t access =
+			map_get_op_access(MI, ARM_get_detail(MI)->op_count);
+		ARM_get_detail_op(MI, 0)->access = access;
+#endif
+	} else {
+		// done, select the next operand slot
+		ARM_inc_op_count(MI);
+	}
+}
+
+/// Fills cs_detail with operand shift information for the last added operand.
+static void add_cs_detail_RegImmShift(MCInst *MI, ARM_AM_ShiftOpc ShOpc,
+									  unsigned ShImm)
+{
+	if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
+		return;
+
+	if (!MI->csh->detail)
+		return;
+
+	if (doing_mem(MI))
+		ARM_get_detail_op(MI, 0)->shift.type = (arm_shifter)ShOpc;
+	else
+		ARM_get_detail_op(MI, -1)->shift.type = (arm_shifter)ShOpc;
+
+	if (ShOpc != ARM_AM_rrx) {
+		if (doing_mem(MI))
+			ARM_get_detail_op(MI, 0)->shift.value = translateShiftImm(ShImm);
+		else
+			ARM_get_detail_op(MI, -1)->shift.value = translateShiftImm(ShImm);
+	}
+}
+
+/// Fills cs_detail with the data of the operand.
+/// This function handles operands which's original printer function has no
+/// specialities.
+static void add_cs_detail_general(MCInst *MI, arm_op_group op_group,
+								  unsigned OpNum)
+{
+	if (!MI->csh->detail)
+		return;
+	cs_op_type op_type = map_get_op_type(MI, OpNum);
+
+	// Fill cs_detail
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		assert(0);
+	case ARM_OP_GROUP_PredicateOperand:
+	case ARM_OP_GROUP_MandatoryPredicateOperand:
+	case ARM_OP_GROUP_MandatoryInvertedPredicateOperand:
+	case ARM_OP_GROUP_MandatoryRestrictedPredicateOperand: {
+		ARMCC_CondCodes CC =
+			(ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+		if ((unsigned)CC == 15 && op_group == ARM_OP_GROUP_PredicateOperand) {
+			ARM_get_detail(MI)->cc = ARMCC_UNDEF;
+			return;
+		}
+		if (CC == ARMCC_HS &&
+			op_group == ARM_OP_GROUP_MandatoryRestrictedPredicateOperand) {
+			ARM_get_detail(MI)->cc = ARMCC_HS;
+			return;
+		}
+		ARM_get_detail(MI)->cc = CC;
+		break;
+	}
+	case ARM_OP_GROUP_VPTPredicateOperand: {
+		ARMVCC_VPTCodes VCC =
+			(ARMVCC_VPTCodes)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+		assert(VCC <= ARMVCC_Else);
+		if (VCC != ARMVCC_None)
+			ARM_get_detail(MI)->vcc = VCC;
+		break;
+	}
+	case ARM_OP_GROUP_Operand:
+		if (op_type == CS_OP_IMM) {
+			if (doing_mem(MI)) {
+				ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+									  MCInst_getOpVal(MI, OpNum));
+			} else {
+				ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
+									  t_add_pc(MI, MCInst_getOpVal(MI, OpNum)));
+			}
+		} else if (op_type == CS_OP_REG)
+			if (doing_mem(MI)) {
+				bool is_index_reg = map_get_op_type(MI, OpNum) & CS_OP_MEM;
+				ARM_set_detail_op_mem(MI, OpNum, is_index_reg, 0, 0,
+									  MCInst_getOpVal(MI, OpNum));
+			} else {
+				ARM_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
+			}
+		else
+			assert(0 && "Op type not handled.");
+		break;
+	case ARM_OP_GROUP_PImmediate:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_PIMM,
+							  MCInst_getOpVal(MI, OpNum));
+		break;
+	case ARM_OP_GROUP_CImmediate:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_CIMM,
+							  MCInst_getOpVal(MI, OpNum));
+		break;
+	case ARM_OP_GROUP_AddrMode6Operand:
+		if(!doing_mem(MI))
+			ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, true, 0, 0, MCInst_getOpVal(MI, OpNum));
+		ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum + 1) << 3);
+		ARM_set_mem_access(MI, false);
+		break;
+	case ARM_OP_GROUP_AddrMode6OffsetOperand: {
+		arm_reg reg = MCInst_getOpVal(MI, OpNum);
+		if (reg != 0) {
+			ARM_set_detail_op_mem_offset(MI, OpNum, reg, false);
+		}
+		break;
+	}
+	case ARM_OP_GROUP_AddrMode7Operand:
+		if(!doing_mem(MI))
+			ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, MCInst_getOpVal(MI, OpNum));
+		ARM_set_mem_access(MI, false);
+		break;
+	case ARM_OP_GROUP_SBitModifierOperand: {
+		unsigned SBit = MCInst_getOpVal(MI, OpNum);
+
+		if (SBit == 0) {
+			// Does not edit set flags.
+			map_remove_implicit_write(MI, ARM_CPSR);
+			ARM_get_detail(MI)->update_flags = false;
+			break;
+		}
+		// Add the implicit write again. Some instruction miss it.
+		map_add_implicit_write(MI, ARM_CPSR);
+		ARM_get_detail(MI)->update_flags = true;
+		break;
+	}
+	case ARM_OP_GROUP_VectorListOne:
+	case ARM_OP_GROUP_VectorListOneAllLanes:
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 0));
+		break;
+	case ARM_OP_GROUP_VectorListTwo:
+	case ARM_OP_GROUP_VectorListTwoAllLanes: {
+		unsigned Reg = MCInst_getOpVal(MI, OpNum);
+		ARM_set_detail_op_reg(
+			MI, OpNum, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0));
+		ARM_set_detail_op_reg(
+			MI, OpNum, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1));
+		break;
+	}
+	case ARM_OP_GROUP_VectorListTwoSpacedAllLanes:
+	case ARM_OP_GROUP_VectorListTwoSpaced: {
+		unsigned Reg = MCInst_getOpVal(MI, OpNum);
+		ARM_set_detail_op_reg(
+			MI, OpNum, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0));
+		ARM_set_detail_op_reg(
+			MI, OpNum, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2));
+		break;
+	}
+	case ARM_OP_GROUP_VectorListThree:
+	case ARM_OP_GROUP_VectorListThreeAllLanes:
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 0));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 1));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 2));
+		break;
+	case ARM_OP_GROUP_VectorListThreeSpacedAllLanes:
+	case ARM_OP_GROUP_VectorListThreeSpaced:
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 0));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 2));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 4));
+		break;
+	case ARM_OP_GROUP_VectorListFour:
+	case ARM_OP_GROUP_VectorListFourAllLanes:
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 0));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 1));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 2));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 3));
+		break;
+	case ARM_OP_GROUP_VectorListFourSpacedAllLanes:
+	case ARM_OP_GROUP_VectorListFourSpaced:
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 0));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 2));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 4));
+		ARM_set_detail_op_reg(MI, OpNum, t_qpr_to_dpr_list(MI, OpNum, 6));
+		break;
+	case ARM_OP_GROUP_NoHashImmediate:
+		ARM_set_detail_op_neon_lane(MI, OpNum);
+		break;
+	case ARM_OP_GROUP_RegisterList: {
+		// All operands n MI from OpNum on are registers.
+		// But the MappingInsnOps.inc has only a single entry for the whole
+		// list. So all registers in the list share those attributes.
+		unsigned access = map_get_op_access(MI, OpNum);
+		for (unsigned i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
+			unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, i));
+
+			ARM_get_detail_op(MI, 0)->type = ARM_OP_REG;
+			ARM_get_detail_op(MI, 0)->reg = Reg;
+			ARM_get_detail_op(MI, 0)->access = access;
+			ARM_inc_op_count(MI);
+		}
+		break;
+	}
+	case ARM_OP_GROUP_ThumbITMask: {
+		unsigned Mask = MCInst_getOpVal(MI, OpNum);
+		unsigned Firstcond = MCInst_getOpVal(MI, OpNum - 1);
+		unsigned CondBit0 = Firstcond & 1;
+		unsigned NumTZ = CountTrailingZeros_32(Mask);
+		unsigned Pos, e;
+		ARM_PredBlockMask PredMask = 0;
+
+		// Check the documentation of ARM_PredBlockMask how the bits are set.
+		for (Pos = 3, e = NumTZ; Pos > e; --Pos) {
+			bool Then = ((Mask >> Pos) & 1) == CondBit0;
+			if (Then)
+				PredMask <<= 1;
+			else {
+				PredMask |= 1;
+				PredMask <<= 1;
+			}
+		}
+		PredMask |= 1;
+		ARM_get_detail(MI)->pred_mask = PredMask;
+		break;
+	}
+	case ARM_OP_GROUP_VPTMask: {
+		unsigned Mask = MCInst_getOpVal(MI, OpNum);
+		unsigned NumTZ = CountTrailingZeros_32(Mask);
+		ARM_PredBlockMask PredMask = 0;
+
+		// Check the documentation of ARM_PredBlockMask how the bits are set.
+		for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
+			bool T = ((Mask >> Pos) & 1) == 0;
+			if (T)
+				PredMask <<= 1;
+			else {
+				PredMask |= 1;
+				PredMask <<= 1;
+			}
+		}
+		PredMask |= 1;
+		ARM_get_detail(MI)->pred_mask = PredMask;
+		break;
+	}
+	case ARM_OP_GROUP_MSRMaskOperand: {
+		MCOperand *Op = MCInst_getOperand(MI, OpNum);
+		unsigned SpecRegRBit = (unsigned)MCOperand_getImm(Op) >> 4;
+		unsigned Mask = (unsigned)MCOperand_getImm(Op) & 0xf;
+		unsigned reg;
+		bool IsOutReg = OpNum == 0;
+
+		if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) {
+			const ARMSysReg_MClassSysReg *TheReg;
+			unsigned SYSm =
+				(unsigned)MCOperand_getImm(Op) & 0xFFF; // 12-bit SYMm
+			unsigned Opcode = MCInst_getOpcode(MI);
+
+			if (Opcode == ARM_t2MSR_M &&
+				ARM_getFeatureBits(MI->csh->mode, ARM_FeatureDSP)) {
+				TheReg = ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(SYSm);
+				if (TheReg &&
+					MClassSysReg_isInRequiredFeatures(TheReg, ARM_FeatureDSP)) {
+					ARM_set_detail_op_sysreg(MI, TheReg->sysreg.sysreg, IsOutReg);
+					return;
+				}
+			}
+
+			SYSm &= 0xff;
+			if (Opcode == ARM_t2MSR_M &&
+				ARM_getFeatureBits(MI->csh->mode, ARM_HasV7Ops)) {
+				TheReg = ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(SYSm);
+				if (TheReg) {
+					ARM_set_detail_op_sysreg(MI, TheReg->sysreg.sysreg, IsOutReg);
+					return;
+				}
+			}
+
+			TheReg = ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(SYSm);
+			if (TheReg) {
+				ARM_set_detail_op_sysreg(MI, TheReg->sysreg.sysreg, IsOutReg);
+				return;
+			}
+
+			if (MI->csh->detail)
+				MCOperand_CreateImm0(MI, SYSm);
+
+			return;
+		}
+
+		if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
+			switch (Mask) {
+			default:
+				assert(0 && "Unexpected mask value!");
+			case 4:
+				ARM_set_detail_op_sysreg(MI, ARM_MCLASSSYSREG_APSR_G, IsOutReg);
+				return;
+			case 8:
+				ARM_set_detail_op_sysreg(MI, ARM_MCLASSSYSREG_APSR_NZCVQ, IsOutReg);
+				return;
+			case 12:
+				ARM_set_detail_op_sysreg(MI, ARM_MCLASSSYSREG_APSR_NZCVQG, IsOutReg);
+				return;
+			}
+		}
+
+		reg = 0;
+		if (Mask) {
+			if (Mask & 8)
+				reg += ARM_SYSREG_SPSR_F;
+			if (Mask & 4)
+				reg += ARM_SYSREG_SPSR_S;
+			if (Mask & 2)
+				reg += ARM_SYSREG_SPSR_X;
+			if (Mask & 1)
+				reg += ARM_SYSREG_SPSR_C;
+
+			ARM_set_detail_op_sysreg(MI, reg, IsOutReg);
+		}
+		break;
+	}
+	case ARM_OP_GROUP_SORegRegOperand: {
+		int64_t imm = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2));
+		ARM_get_detail_op(MI, 0)->shift.type = (imm & 7) + ARM_SFT_ASR_REG - 1;
+		if (ARM_AM_getSORegShOp(imm) != ARM_AM_rrx)
+			ARM_get_detail_op(MI, 0)->shift.value =
+				MCInst_getOpVal(MI, OpNum + 1);
+
+		ARM_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
+		break;
+	}
+	case ARM_OP_GROUP_ModImmOperand: {
+		int64_t imm = MCInst_getOpVal(MI, OpNum);
+		int32_t Rotated = t_mod_imm_rotate(imm);
+		if (ARM_AM_getSOImmVal(Rotated) == imm) {
+			ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, t_mod_imm_rotate(imm));
+			return;
+		}
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, t_mod_imm_bits(imm));
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, t_mod_imm_rot(imm));
+		break;
+	}
+	case ARM_OP_GROUP_VMOVModImmOperand:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
+							  t_vmov_mod_imm(MCInst_getOpVal(MI, OpNum)));
+		break;
+	case ARM_OP_GROUP_FPImmOperand:
+		ARM_set_detail_op_float(MI, OpNum, MCInst_getOpVal(MI, OpNum));
+		break;
+	case ARM_OP_GROUP_ImmPlusOneOperand:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
+							  MCInst_getOpVal(MI, OpNum) + 1);
+		break;
+	case ARM_OP_GROUP_RotImmOperand: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		if (Imm == 0)
+			return;
+		ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ROR;
+		ARM_get_detail_op(MI, -1)->shift.value = Imm * 8;
+		break;
+	}
+	case ARM_OP_GROUP_FBits16:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
+							  16 - MCInst_getOpVal(MI, OpNum));
+		break;
+	case ARM_OP_GROUP_FBits32:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
+							  32 - MCInst_getOpVal(MI, OpNum));
+		break;
+	case ARM_OP_GROUP_T2SOOperand:
+	case ARM_OP_GROUP_SORegImmOperand:
+		ARM_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
+		uint64_t imm = MCInst_getOpVal(MI, OpNum + 1);
+		ARM_AM_ShiftOpc ShOpc = ARM_AM_getSORegShOp(imm);
+		unsigned ShImm = ARM_AM_getSORegOffset(imm);
+		if (op_group == ARM_OP_GROUP_SORegImmOperand) {
+			if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm))
+				return;
+		}
+		add_cs_detail_RegImmShift(MI, ShOpc, ShImm);
+		break;
+	case ARM_OP_GROUP_PostIdxRegOperand: {
+		bool sub = MCInst_getOpVal(MI, OpNum + 1) ? false : true;
+		ARM_set_detail_op_mem_offset(MI, OpNum, MCInst_getOpVal(MI, OpNum), sub);
+		ARM_get_detail(MI)->post_index = true;
+		break;
+	}
+	case ARM_OP_GROUP_PostIdxImm8Operand: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		bool sub = !(Imm & 256);
+		ARM_set_detail_op_mem_offset(MI, OpNum, (Imm & 0xff), sub);
+		ARM_get_detail(MI)->post_index = true;
+		break;
+	}
+	case ARM_OP_GROUP_PostIdxImm8s4Operand: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		bool sub = !(Imm & 256);
+		ARM_set_detail_op_mem_offset(MI, OpNum, (Imm & 0xff) << 2, sub);
+		ARM_get_detail(MI)->post_index = true;
+		break;
+	}
+	case ARM_OP_GROUP_AddrModeTBB:
+	case ARM_OP_GROUP_AddrModeTBH:
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0,
+							  MCInst_getOpVal(MI, OpNum + 1));
+		if (op_group == ARM_OP_GROUP_AddrModeTBH) {
+			ARM_get_detail_op(MI, 0)->shift.type = ARM_SFT_LSL;
+			ARM_get_detail_op(MI, 0)->shift.value = 1;
+			ARM_get_detail_op(MI, 0)->mem.lshift = 1;
+		}
+		ARM_set_mem_access(MI, false);
+		break;
+	case ARM_OP_GROUP_AddrMode2Operand: {
+		MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+		if (!MCOperand_isReg(MO1))
+			// Handled in printOperand
+			break;
+
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		unsigned int imm3 = MCInst_getOpVal(MI, OpNum + 2);
+		unsigned ShOff = ARM_AM_getAM2Offset(imm3);
+		ARM_AM_AddrOpc subtracted = ARM_AM_getAM2Op(imm3);
+		if (!MCOperand_getReg(MCInst_getOperand(MI, OpNum + 2)) && ShOff) {
+			ARM_get_detail_op(MI, 0)->shift.type = (arm_shifter)subtracted;
+			ARM_get_detail_op(MI, 0)->shift.value = ShOff;
+			ARM_get_detail_op(MI, 0)->subtracted = subtracted == ARM_AM_sub;
+			ARM_set_mem_access(MI, false);
+			break;
+		}
+		ARM_get_detail_op(MI, 0)->shift.type = subtracted == ARM_AM_sub;
+		ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0,
+							  MCInst_getOpVal(MI, OpNum + 1));
+		add_cs_detail_RegImmShift(MI, ARM_AM_getAM2ShiftOpc(imm3),
+								  ARM_AM_getAM2Offset(imm3));
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_AddrMode2OffsetOperand: {
+		uint64_t imm2 = MCInst_getOpVal(MI, OpNum + 1);
+		ARM_AM_AddrOpc subtracted = ARM_AM_getAM2Op(imm2);
+		if (!MCInst_getOpVal(MI, OpNum)) {
+			ARM_set_detail_op_mem_offset(MI, OpNum + 1,
+										 ARM_AM_getAM2Offset(imm2),
+										 subtracted == ARM_AM_sub);
+			ARM_get_detail(MI)->post_index = true;
+			return;
+		}
+		ARM_set_detail_op_mem_offset(MI, OpNum, MCInst_getOpVal(MI, OpNum),
+									 subtracted == ARM_AM_sub);
+		ARM_get_detail(MI)->post_index = true;
+		add_cs_detail_RegImmShift(MI, ARM_AM_getAM2ShiftOpc(imm2),
+								  ARM_AM_getAM2Offset(imm2));
+		break;
+	}
+	case ARM_OP_GROUP_AddrMode3OffsetOperand: {
+		MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+		MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
+		ARM_AM_AddrOpc subtracted = ARM_AM_getAM3Op(MCOperand_getImm(MO2));
+		if (MCOperand_getReg(MO1)) {
+			ARM_set_detail_op_mem_offset(MI, OpNum, MCInst_getOpVal(MI, OpNum),
+										 subtracted == ARM_AM_sub);
+			ARM_get_detail(MI)->post_index = true;
+			return;
+		}
+		ARM_set_detail_op_mem_offset(
+			MI, OpNum + 1, ARM_AM_getAM3Offset(MCInst_getOpVal(MI, OpNum + 1)),
+			subtracted == ARM_AM_sub);
+		ARM_get_detail(MI)->post_index = true;
+		break;
+	}
+	case ARM_OP_GROUP_ThumbAddrModeSPOperand:
+	case ARM_OP_GROUP_ThumbAddrModeImm5S1Operand:
+	case ARM_OP_GROUP_ThumbAddrModeImm5S2Operand:
+	case ARM_OP_GROUP_ThumbAddrModeImm5S4Operand: {
+		MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+		if (!MCOperand_isReg(MO1))
+			// Handled in printOperand
+			break;
+
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		unsigned ImmOffs = MCInst_getOpVal(MI, OpNum + 1);
+		if (ImmOffs) {
+			unsigned Scale = 0;
+			switch (op_group) {
+			default:
+				assert(0 &&
+					   "Cannot determine scale. Operand group not handled.");
+			case ARM_OP_GROUP_ThumbAddrModeImm5S1Operand:
+				Scale = 1;
+				break;
+			case ARM_OP_GROUP_ThumbAddrModeImm5S2Operand:
+				Scale = 2;
+				break;
+			case ARM_OP_GROUP_ThumbAddrModeImm5S4Operand:
+			case ARM_OP_GROUP_ThumbAddrModeSPOperand:
+				Scale = 4;
+				break;
+			}
+			ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, ImmOffs * Scale);
+		}
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_ThumbAddrModeRROperand: {
+		MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+		if (!MCOperand_isReg(MO1))
+			// Handled in printOperand
+			break;
+
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		arm_reg RegNum = MCInst_getOpVal(MI, OpNum + 1);
+		if (RegNum)
+			ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0, RegNum);
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_T2AddrModeImm8OffsetOperand:
+	case ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand: {
+		int32_t OffImm = MCInst_getOpVal(MI, OpNum);
+		if (OffImm == INT32_MIN)
+			ARM_set_detail_op_mem_offset(MI, OpNum, 0, false);
+		else {
+			bool sub = OffImm < 0;
+			OffImm = OffImm < 0 ? OffImm * -1 : OffImm;
+			ARM_set_detail_op_mem_offset(MI, OpNum, OffImm, sub);
+		}
+		ARM_get_detail(MI)->post_index = true;
+		break;
+	}
+	case ARM_OP_GROUP_T2AddrModeSoRegOperand: {
+		if(!doing_mem(MI))
+			ARM_set_mem_access(MI, true);
+
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0,
+							  MCInst_getOpVal(MI, OpNum + 1));
+		unsigned ShAmt = MCInst_getOpVal(MI, OpNum);
+		if (ShAmt) {
+			ARM_get_detail_op(MI, 2)->shift.type = ARM_SFT_LSL;
+			ARM_get_detail_op(MI, 2)->shift.value = ShAmt;
+		}
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand:
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		int64_t Imm = MCInst_getOpVal(MI, OpNum + 1);
+		if (Imm)
+			ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm * 4);
+		ARM_set_mem_access(MI, false);
+		break;
+	case ARM_OP_GROUP_PKHLSLShiftImm: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		if (Imm == 0)
+			return;
+		ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_LSL;
+		ARM_get_detail_op(MI, -1)->shift.value = Imm;
+		break;
+	}
+	case ARM_OP_GROUP_PKHASRShiftImm: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		if (Imm == 0)
+			Imm = 32;
+		ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ASR;
+		ARM_get_detail_op(MI, -1)->shift.value = Imm;
+		break;
+	}
+	case ARM_OP_GROUP_ThumbS4ImmOperand:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM,
+							  MCInst_getOpVal(MI, OpNum) * 4);
+		break;
+	case ARM_OP_GROUP_ThumbSRImm: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Imm == 0 ? 32 : Imm);
+		break;
+	}
+	case ARM_OP_GROUP_BitfieldInvMaskImmOperand: {
+		uint32_t v = ~MCInst_getOpVal(MI, OpNum);
+		int32_t lsb = CountTrailingZeros_32(v);
+		int32_t width = (32 - countLeadingZeros(v)) - lsb;
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, lsb);
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, width);
+		break;
+	}
+	case ARM_OP_GROUP_CPSIMod: {
+		unsigned Imm = MCInst_getOpVal(MI, OpNum);
+		ARM_get_detail(MI)->cps_mode = Imm;
+		break;
+	}
+	case ARM_OP_GROUP_CPSIFlag: {
+		unsigned IFlags = MCInst_getOpVal(MI, OpNum);
+		ARM_get_detail(MI)->cps_flag =
+			IFlags == 0 ? ARM_CPSFLAG_NONE : IFlags;
+		break;
+	}
+	case ARM_OP_GROUP_GPRPairOperand: {
+		unsigned Reg = MCInst_getOpVal(MI, OpNum);
+		ARM_set_detail_op_reg(
+			MI, OpNum, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0));
+		ARM_set_detail_op_reg(
+			MI, OpNum, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_1));
+		break;
+	}
+	case ARM_OP_GROUP_MemBOption:
+	case ARM_OP_GROUP_InstSyncBOption:
+	case ARM_OP_GROUP_TraceSyncBOption:
+		ARM_get_detail(MI)->mem_barrier = MCInst_getOpVal(MI, OpNum);
+		break;
+	case ARM_OP_GROUP_ShiftImmOperand: {
+		unsigned ShiftOp = MCInst_getOpVal(MI, OpNum);
+		bool isASR = (ShiftOp & (1 << 5)) != 0;
+		unsigned Amt = ShiftOp & 0x1f;
+		if (isASR) {
+			unsigned tmp = Amt == 0 ? 32 : Amt;
+			ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ASR;
+			ARM_get_detail_op(MI, -1)->shift.value = tmp;
+		} else if (Amt) {
+			ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_LSL;
+			ARM_get_detail_op(MI, -1)->shift.value = Amt;
+		}
+		break;
+	}
+	case ARM_OP_GROUP_VectorIndex:
+		ARM_get_detail_op(MI, -1)->vector_index = MCInst_getOpVal(MI, OpNum);
+		break;
+	case ARM_OP_GROUP_CoprocOptionImm:
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, MCInst_getOpVal(MI, OpNum));
+		break;
+	case ARM_OP_GROUP_ThumbLdrLabelOperand: {
+		int32_t OffImm = MCInst_getOpVal(MI, OpNum);
+		if (OffImm == INT32_MIN)
+			OffImm = 0;
+		ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM;
+		ARM_get_detail_op(MI, 0)->mem.base = ARM_REG_PC;
+		ARM_get_detail_op(MI, 0)->mem.index = ARM_REG_INVALID;
+		ARM_get_detail_op(MI, 0)->mem.scale = 1;
+		ARM_get_detail_op(MI, 0)->mem.disp = OffImm;
+		ARM_get_detail_op(MI, 0)->access = CS_AC_READ;
+		ARM_inc_op_count(MI);
+		break;
+	}
+	case ARM_OP_GROUP_BankedRegOperand: {
+		uint32_t Banked = MCInst_getOpVal(MI, OpNum);
+		const ARMBankedReg_BankedReg *TheReg = ARMBankedReg_lookupBankedRegByEncoding(Banked);
+		bool IsOutReg = OpNum == 0;
+		ARM_set_detail_op_sysreg(MI, TheReg->sysreg.banked_reg, IsOutReg);
+		break;
+	}
+	case ARM_OP_GROUP_SetendOperand: {
+		bool be = MCInst_getOpVal(MI, OpNum) != 0;
+		if (be) {
+			ARM_get_detail_op(MI, 0)->type = ARM_OP_SETEND;
+			ARM_get_detail_op(MI, 0)->setend = ARM_SETEND_BE;
+		} else {
+			ARM_get_detail_op(MI, 0)->type = ARM_OP_SETEND;
+			ARM_get_detail_op(MI, 0)->setend = ARM_SETEND_LE;
+		}
+		ARM_inc_op_count(MI);
+		break;
+	}
+	case ARM_OP_GROUP_MveSaturateOp: {
+		uint32_t Val = MCInst_getOpVal(MI, OpNum);
+		Val = Val == 1 ? 48 : 64;
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Val);
+		break;
+	}
+	}
+}
+
+/// Fills cs_detail with the data of the operand.
+/// This function handles operands which original printer function is a template
+/// with one argument.
+static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group,
+									 unsigned OpNum, uint64_t temp_arg_0)
+{
+	if (!detail_is_set(MI))
+		return;
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		assert(0);
+	case ARM_OP_GROUP_AddrModeImm12Operand_0:
+	case ARM_OP_GROUP_AddrModeImm12Operand_1:
+	case ARM_OP_GROUP_T2AddrModeImm8s4Operand_0:
+	case ARM_OP_GROUP_T2AddrModeImm8s4Operand_1: {
+		MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+		if (!MCOperand_isReg(MO1))
+			// Handled in printOperand
+			return;
+	}
+	// fallthrough
+	case ARM_OP_GROUP_T2AddrModeImm8Operand_0:
+	case ARM_OP_GROUP_T2AddrModeImm8Operand_1: {
+		bool AlwaysPrintImm0 = temp_arg_0;
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		int32_t Imm = MCInst_getOpVal(MI, OpNum + 1);
+		if (Imm == INT32_MIN)
+			Imm = 0;
+		ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm);
+		if (AlwaysPrintImm0)
+			map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));
+
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_AdrLabelOperand_0:
+	case ARM_OP_GROUP_AdrLabelOperand_2: {
+		unsigned Scale = temp_arg_0;
+		int32_t OffImm = MCInst_getOpVal(MI, OpNum) << Scale;
+		if (OffImm == INT32_MIN)
+			OffImm = 0;
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, OffImm);
+		break;
+	}
+	case ARM_OP_GROUP_AddrMode3Operand_0:
+	case ARM_OP_GROUP_AddrMode3Operand_1: {
+		bool AlwaysPrintImm0 = temp_arg_0;
+		MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
+		if (!MCOperand_isReg(MO1))
+			// Handled in printOperand
+			break;
+
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+
+		MCOperand *MO2 = MCInst_getOperand(MI, OpNum + 1);
+		ARM_AM_AddrOpc Sign = ARM_AM_getAM3Op(MCInst_getOpVal(MI, OpNum + 2));
+
+		if (MCOperand_getReg(MO2)) {
+			ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0,
+								  MCInst_getOpVal(MI, OpNum + 1));
+			ARM_get_detail_op(MI, 0)->subtracted = Sign == ARM_AM_sub;
+			ARM_set_mem_access(MI, false);
+			break;
+		}
+		unsigned ImmOffs = ARM_AM_getAM3Offset(MCOperand_getImm(MCInst_getOperand(MI, OpNum + 2)));
+
+		if (AlwaysPrintImm0 || ImmOffs || Sign == ARM_AM_sub) {
+			ARM_set_detail_op_mem(MI, OpNum + 2, false, 0, 0,
+						MCInst_getOpVal(MI, OpNum + 2));
+			ARM_get_detail_op(MI, 0)->subtracted = Sign == ARM_AM_sub;
+		}
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_AddrMode5Operand_0:
+	case ARM_OP_GROUP_AddrMode5Operand_1:
+	case ARM_OP_GROUP_AddrMode5FP16Operand_0: {
+		bool AlwaysPrintImm0 = temp_arg_0;
+
+		if (AlwaysPrintImm0)
+			map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));
+
+		cs_arm_op *Op = ARM_get_detail_op(MI, 0);
+		Op->type = ARM_OP_MEM;
+		Op->mem.base = MCInst_getOpVal(MI, OpNum);
+		Op->mem.index = ARM_REG_INVALID;
+		Op->mem.scale = 1;
+		Op->mem.disp = 0;
+		Op->access = CS_AC_READ;
+
+		ARM_AM_AddrOpc SubFlag = ARM_AM_getAM5Op(MCInst_getOpVal(MI, OpNum + 1));
+		unsigned ImmOffs = ARM_AM_getAM5Offset(MCInst_getOpVal(MI, OpNum + 1));
+
+		if (AlwaysPrintImm0 || ImmOffs || SubFlag == ARM_AM_sub) {
+			if (op_group == ARM_OP_GROUP_AddrMode5FP16Operand_0) {
+				Op->mem.disp = ImmOffs * 2;
+			} else {
+				Op->mem.disp = ImmOffs * 4;
+			}
+			Op->subtracted = SubFlag == ARM_AM_sub;
+		}
+		ARM_inc_op_count(MI);
+		break;
+	}
+	case ARM_OP_GROUP_MveAddrModeRQOperand_0:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_1:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_2:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_3: {
+		unsigned Shift = temp_arg_0;
+		ARM_set_mem_access(MI, true);
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0,
+							  MCInst_getOpVal(MI, OpNum));
+		ARM_set_detail_op_mem(MI, OpNum + 1, true, 0, 0,
+							  MCInst_getOpVal(MI, OpNum + 1));
+		if (Shift > 0) {
+			add_cs_detail_RegImmShift(MI, ARM_AM_uxtw, Shift);
+		}
+		ARM_set_mem_access(MI, false);
+		break;
+	}
+	case ARM_OP_GROUP_MVEVectorList_2:
+	case ARM_OP_GROUP_MVEVectorList_4: {
+		unsigned NumRegs = temp_arg_0;
+		arm_reg Reg = MCInst_getOpVal(MI, OpNum);
+		for (unsigned i = 0; i < NumRegs; ++i) {
+			arm_reg SubReg =
+				MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_qsub_0 + i);
+			ARM_set_detail_op_reg(MI, OpNum, SubReg);
+		}
+		break;
+	}
+	}
+}
+
+/// Fills cs_detail with the data of the operand.
+/// This function handles operands which's original printer function is a
+/// template with two arguments.
+static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group,
+									 unsigned OpNum, uint64_t temp_arg_0,
+									 uint64_t temp_arg_1)
+{
+	if (!detail_is_set(MI))
+		return;
+	switch (op_group) {
+	default:
+		printf("ERROR: Operand group %d not handled!\n", op_group);
+		assert(0);
+	case ARM_OP_GROUP_ComplexRotationOp_90_0:
+	case ARM_OP_GROUP_ComplexRotationOp_180_90: {
+		unsigned Angle = temp_arg_0;
+		unsigned Remainder = temp_arg_1;
+		unsigned Imm = (MCInst_getOpVal(MI, OpNum) * Angle) + Remainder;
+		ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Imm);
+		break;
+	}
+	}
+}
+
+/// Fills cs_detail with the data of the operand.
+/// Calls to this function are should not be added by hand! Please checkout the
+/// patch `AddCSDetail` of the CppTranslator.
+void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+					   va_list args)
+{
+	if (!detail_is_set(MI))
+		return;
+	switch (op_group) {
+	case ARM_OP_GROUP_RegImmShift: {
+		ARM_AM_ShiftOpc shift_opc = va_arg(args, ARM_AM_ShiftOpc);
+		unsigned shift_imm = va_arg(args, unsigned);
+		add_cs_detail_RegImmShift(MI, shift_opc, shift_imm);
+		return;
+	}
+	case ARM_OP_GROUP_AdrLabelOperand_0:
+	case ARM_OP_GROUP_AdrLabelOperand_2:
+	case ARM_OP_GROUP_AddrMode3Operand_0:
+	case ARM_OP_GROUP_AddrMode3Operand_1:
+	case ARM_OP_GROUP_AddrMode5Operand_0:
+	case ARM_OP_GROUP_AddrMode5Operand_1:
+	case ARM_OP_GROUP_AddrModeImm12Operand_0:
+	case ARM_OP_GROUP_AddrModeImm12Operand_1:
+	case ARM_OP_GROUP_T2AddrModeImm8Operand_0:
+	case ARM_OP_GROUP_T2AddrModeImm8Operand_1:
+	case ARM_OP_GROUP_T2AddrModeImm8s4Operand_0:
+	case ARM_OP_GROUP_T2AddrModeImm8s4Operand_1:
+	case ARM_OP_GROUP_MVEVectorList_2:
+	case ARM_OP_GROUP_MVEVectorList_4:
+	case ARM_OP_GROUP_AddrMode5FP16Operand_0:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_0:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_3:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_1:
+	case ARM_OP_GROUP_MveAddrModeRQOperand_2: {
+		unsigned op_num = va_arg(args, unsigned);
+		uint64_t templ_arg_0 = va_arg(args, uint64_t);
+		add_cs_detail_template_1(MI, op_group, op_num, templ_arg_0);
+		return;
+	}
+	case ARM_OP_GROUP_ComplexRotationOp_180_90:
+	case ARM_OP_GROUP_ComplexRotationOp_90_0: {
+		unsigned op_num = va_arg(args, unsigned);
+		uint64_t templ_arg_0 = va_arg(args, uint64_t);
+		uint64_t templ_arg_1 = va_arg(args, uint64_t);
+		add_cs_detail_template_2(MI, op_group, op_num, templ_arg_0,
+								 templ_arg_1);
+		return;
+	}
+	}
+	unsigned op_num = va_arg(args, unsigned);
+	add_cs_detail_general(MI, op_group, op_num);
+}
+
+/// Inserts a register to the detail operands at @index.
+/// Already present operands are moved.
+void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, cs_ac_type access)
+{
+	if (!detail_is_set(MI))
+		return;
+
+	assert(ARM_get_detail(MI)->op_count < MAX_ARM_OPS);
+
+	cs_arm_op op;
+	ARM_setup_op(&op);
+	op.type = ARM_OP_REG;
+	op.reg = Reg;
+	op.access = access;
+
+	cs_arm_op *ops = ARM_get_detail(MI)->operands;
+	int i = ARM_get_detail(MI)->op_count - 1;
+	for (; i >= 0; --i) {
+		ops[i + 1] = ops[i];
+		if (i == index)
+			break;
+	}
+	ops[index] = op ;
+	ARM_inc_op_count(MI);
+}
+
+/// Adds a register ARM operand at position OpNum and increases the op_count by
+/// one.
+void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
+
+	ARM_get_detail_op(MI, 0)->type = ARM_OP_REG;
+	ARM_get_detail_op(MI, 0)->reg = Reg;
+	ARM_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	ARM_inc_op_count(MI);
+}
+
+/// Adds an immediate ARM operand at position OpNum and increases the op_count
+/// by one.
+void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType,
+						   int64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
+	assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
+	assert(ImmType == ARM_OP_IMM || ImmType == ARM_OP_PIMM ||
+		   ImmType == ARM_OP_CIMM);
+
+	ARM_get_detail_op(MI, 0)->type = ImmType;
+	ARM_get_detail_op(MI, 0)->imm = Imm;
+	ARM_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+	ARM_inc_op_count(MI);
+}
+
+/// Adds the operand as to the previously added memory operand.
+void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val,
+								  bool subtracted)
+{
+	assert(map_get_op_type(MI, OpNum) & CS_OP_MEM);
+
+	if (!doing_mem(MI)) {
+		assert((ARM_get_detail_op(MI, -1) != NULL) &&
+			   (ARM_get_detail_op(MI, -1)->type == ARM_OP_MEM));
+		ARM_dec_op_count(MI);
+	}
+
+	if ((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM)
+		ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, Val);
+	else if ((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG)
+		ARM_set_detail_op_mem(MI, OpNum, true, 0, 0, Val);
+	else
+		assert(0 && "Memory type incorrect.");
+	ARM_get_detail_op(MI, 0)->subtracted = subtracted;
+
+	if (!doing_mem(MI))
+		ARM_inc_op_count(MI);
+}
+
+/// Adds a memory ARM operand at position OpNum. op_count is *not* increased by
+/// one. This is done by ARM_set_mem_access().
+void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg,
+						   int scale, int lshift, uint64_t Val)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(map_get_op_type(MI, OpNum) & CS_OP_MEM);
+	cs_op_type secondary_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
+	switch (secondary_type) {
+	default:
+		assert(0 && "Secondary type not supported yet.");
+	case CS_OP_REG: {
+		assert(secondary_type == CS_OP_REG);
+		if (!is_index_reg)
+			ARM_get_detail_op(MI, 0)->mem.base = Val;
+		else {
+			ARM_get_detail_op(MI, 0)->mem.index = Val;
+			ARM_get_detail_op(MI, 0)->mem.scale = scale;
+			ARM_get_detail_op(MI, 0)->mem.lshift = lshift;
+		}
+
+		if (MCInst_opIsTying(MI, OpNum)) {
+			// Especially base registers can be writeback registers.
+			// For this they tie an MC operand which has write
+			// access. But this one is never processed in the printer
+			// (because it is never emitted). Therefor it is never
+			// added to the modified list.
+			// Here we check for this case and add the memory register
+			// to the modified list.
+			map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum));
+		}
+		break;
+	}
+	case CS_OP_IMM: {
+		assert(secondary_type == CS_OP_IMM);
+		if (((int32_t) Val) < 0)
+			ARM_get_detail_op(MI, 0)->subtracted = true;
+		ARM_get_detail_op(MI, 0)->mem.disp = ((int64_t) Val < 0) ? -Val : Val;
+		break;
+	}
+	}
+
+	ARM_get_detail_op(MI, 0)->type = ARM_OP_MEM;
+	ARM_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
+}
+
+/// Sets the neon_lane in the previous operand to the value of
+/// MI->operands[OpNum] Decrements op_count by 1.
+void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum)
+{
+	if (!detail_is_set(MI))
+		return;
+	assert(map_get_op_type(MI, OpNum) == CS_OP_IMM);
+	unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum));
+
+	ARM_dec_op_count(MI);
+	ARM_get_detail_op(MI, 0)->neon_lane = Val;
+}
+
+/// Adds a System Register and increments op_count by one.
+void ARM_set_detail_op_sysreg(MCInst *MI, int SysReg, bool IsOutReg)
+{
+	if (!detail_is_set(MI))
+		return;
+	ARM_get_detail_op(MI, 0)->type = ARM_OP_SYSREG;
+	ARM_get_detail_op(MI, 0)->reg = SysReg;
+	ARM_get_detail_op(MI, 0)->access = IsOutReg ? CS_AC_WRITE : CS_AC_READ;
+	ARM_inc_op_count(MI);
+}
+
+/// Transforms the immediate of the operand to a float and stores it.
+/// Increments the op_counter by one.
+void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm)
+{
+	if (!detail_is_set(MI))
+		return;
+	ARM_get_detail_op(MI, 0)->type = ARM_OP_FP;
+	ARM_get_detail_op(MI, 0)->fp = ARM_AM_getFPImmFloat(Imm);
+	ARM_inc_op_count(MI);
+}
+
 #endif
diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h
index 1f413d0ce..4edd8cb76 100644
--- a/arch/ARM/ARMMapping.h
+++ b/arch/ARM/ARMMapping.h
@@ -1,15 +1,24 @@
 /* Capstone Disassembly Engine */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
 
-#ifndef CS_ARM_MAP_H
-#define CS_ARM_MAP_H
+#ifndef CS_ARM_MAPPING_H
+#define CS_ARM_MAPPING_H
 
 #include "../../include/capstone/capstone.h"
 #include "../../utils.h"
+#include "ARMBaseInfo.h"
+
+typedef enum {
+#include "ARMGenCSOpGroup.inc"
+} arm_op_group;
+
+extern const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
+extern const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
 
 // return name of regiser in friendly string
 const char *ARM_reg_name(csh handle, unsigned int reg);
-const char *ARM_reg_name2(csh handle, unsigned int reg);
+
+void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */info);
 
 // given internal insn id, return public instruction ID
 void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
@@ -23,18 +32,48 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
 
 bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
 
-const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
+void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,
+					uint8_t *regs_read_count, cs_regs regs_write,
+					uint8_t *regs_write_count);
 
-void ARM_reg_access(const cs_insn *insn,
-		cs_regs regs_read, uint8_t *regs_read_count,
-		cs_regs regs_write, uint8_t *regs_write_count);
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t encoding);
 
-typedef struct BankedReg {
-	const char *Name;
-	arm_sysreg sysreg;
-	uint16_t Encoding;
-} BankedReg;
+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
+						MCInst *instr, uint16_t *size, uint64_t address,
+						void *info);
+void ARM_set_instr_map_data(MCInst *MI);
 
-const BankedReg *lookupBankedRegByEncoding(uint8_t encoding);
+void ARM_init_mri(MCRegisterInfo *MRI);
 
-#endif
+// cs_detail related functions
+void ARM_init_cs_detail(MCInst *MI);
+void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+					   va_list args);
+static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+								 ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	ARM_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, cs_ac_type access);
+void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg);
+void ARM_set_detail_op_sysreg(MCInst *MI, int SysReg, bool IsOutReg);
+void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType,
+						   int64_t Imm);
+void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm);
+void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg,
+						   int scale, int lshift, uint64_t Val);
+void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val,
+								  bool subtracted);
+void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum);
+
+void ARM_check_updates_flags(MCInst *MI);
+
+void ARM_setup_op(cs_arm_op *op);
+
+#endif // CS_ARM_MAPPING_H
diff --git a/arch/ARM/ARMModule.c b/arch/ARM/ARMModule.c
index 0ecadd802..4fe40422b 100644
--- a/arch/ARM/ARMModule.c
+++ b/arch/ARM/ARMModule.c
@@ -1,60 +1,49 @@
 /* Capstone Disassembly Engine */
 /* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
 
+#include "capstone/capstone.h"
 #ifdef CAPSTONE_HAS_ARM
 
-#include "../../cs_priv.h"
+#include "ARMModule.h"
 #include "../../MCRegisterInfo.h"
-#include "ARMDisassembler.h"
+#include "../../cs_priv.h"
 #include "ARMInstPrinter.h"
 #include "ARMMapping.h"
-#include "ARMModule.h"
 
 cs_err ARM_global_init(cs_struct *ud)
 {
 	MCRegisterInfo *mri;
 	mri = cs_mem_malloc(sizeof(*mri));
 
-	ARM_init(mri);
-	ARM_getRegName(ud, 0);	// use default get_regname
+	ARM_init_mri(mri);
 
-	ud->printer = ARM_printInst;
+	ud->printer = ARM_printer;
 	ud->printer_info = mri;
 	ud->reg_name = ARM_reg_name;
 	ud->insn_id = ARM_get_insn_id;
 	ud->insn_name = ARM_insn_name;
 	ud->group_name = ARM_group_name;
-	ud->post_printer = ARM_post_printer;
+	ud->post_printer = NULL;
 #ifndef CAPSTONE_DIET
 	ud->reg_access = ARM_reg_access;
 #endif
 
-	if (ud->mode & CS_MODE_THUMB)
-		ud->disasm = Thumb_getInstruction;
-	else
-		ud->disasm = ARM_getInstruction;
+	ud->disasm = ARM_getInstruction;
 
 	return CS_ERR_OK;
 }
 
 cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value)
 {
-	switch(type) {
-		case CS_OPT_MODE:
-			if (value & CS_MODE_THUMB)
-				handle->disasm = Thumb_getInstruction;
-			else
-				handle->disasm = ARM_getInstruction;
-
-			handle->mode = (cs_mode)value;
-
-			break;
-		case CS_OPT_SYNTAX:
-			ARM_getRegName(handle, (int)value);
-			handle->syntax = (int)value;
-			break;
-		default:
-			break;
+	switch (type) {
+	case CS_OPT_MODE:
+		handle->mode = (cs_mode)value;
+		break;
+	case CS_OPT_SYNTAX:
+		handle->syntax |= (int)value;
+		break;
+	default:
+		break;
 	}
 
 	return CS_ERR_OK;
diff --git a/arch/BPF/BPFMapping.c b/arch/BPF/BPFMapping.c
index fc804dad6..3ba6e93cf 100644
--- a/arch/BPF/BPFMapping.c
+++ b/arch/BPF/BPFMapping.c
@@ -5,6 +5,7 @@
 
 #include "BPFConstants.h"
 #include "BPFMapping.h"
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #ifndef CAPSTONE_DIET
diff --git a/arch/EVM/EVMMapping.c b/arch/EVM/EVMMapping.c
index bbd8d41c3..200358174 100644
--- a/arch/EVM/EVMMapping.c
+++ b/arch/EVM/EVMMapping.c
@@ -6,6 +6,7 @@
 #include <string.h>
 
 #include "../../cs_priv.h"
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "EVMMapping.h"
diff --git a/arch/M680X/M680XInstPrinter.c b/arch/M680X/M680XInstPrinter.c
index 45b6fbc1d..829c3ca7b 100644
--- a/arch/M680X/M680XInstPrinter.c
+++ b/arch/M680X/M680XInstPrinter.c
@@ -11,6 +11,8 @@
 #include "../../MCInst.h"
 #include "../../SStream.h"
 #include "../../MCRegisterInfo.h"
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
 #include "../../utils.h"
 #include "M680XInstPrinter.h"
 #include "M680XDisassembler.h"
diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c
index d42359647..c50c05f10 100644
--- a/arch/M68K/M68KInstPrinter.c
+++ b/arch/M68K/M68KInstPrinter.c
@@ -21,6 +21,7 @@
 #include "M68KDisassembler.h"
 
 #include "../../cs_priv.h"
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "../../MCInst.h"
diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c
index c8a159d80..062031674 100644
--- a/arch/Mips/MipsMapping.c
+++ b/arch/Mips/MipsMapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "MipsMapping.h"
diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c
index ce3532db4..60dd2da6b 100644
--- a/arch/PowerPC/PPCMapping.c
+++ b/arch/PowerPC/PPCMapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "PPCMapping.h"
diff --git a/arch/RISCV/RISCVMapping.c b/arch/RISCV/RISCVMapping.c
index d60b45f5a..6c0613a54 100644
--- a/arch/RISCV/RISCVMapping.c
+++ b/arch/RISCV/RISCVMapping.c
@@ -4,6 +4,7 @@
 #include <stdio.h>		// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "RISCVMapping.h"
diff --git a/arch/SH/SHInstPrinter.c b/arch/SH/SHInstPrinter.c
index b9759198d..207083540 100644
--- a/arch/SH/SHInstPrinter.c
+++ b/arch/SH/SHInstPrinter.c
@@ -2,6 +2,8 @@
 /* By Yoshinori Sato, 2022 */
 
 #include <string.h>
+
+#include "../../Mapping.h"
 #include "SHInstPrinter.h"
 
 
diff --git a/arch/Sparc/SparcMapping.c b/arch/Sparc/SparcMapping.c
index f86fb33eb..b7b65719f 100644
--- a/arch/Sparc/SparcMapping.c
+++ b/arch/Sparc/SparcMapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "SparcMapping.h"
diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c
index 90b4ff3fc..4e5d7e3e2 100644
--- a/arch/SystemZ/SystemZMapping.c
+++ b/arch/SystemZ/SystemZMapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "SystemZMapping.h"
diff --git a/arch/TMS320C64x/TMS320C64xMapping.c b/arch/TMS320C64x/TMS320C64xMapping.c
index 19f3cc19f..885244cce 100644
--- a/arch/TMS320C64x/TMS320C64xMapping.c
+++ b/arch/TMS320C64x/TMS320C64xMapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "TMS320C64xMapping.h"
diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c
index eadf2eef2..a15b962df 100644
--- a/arch/TriCore/TriCoreInstPrinter.c
+++ b/arch/TriCore/TriCoreInstPrinter.c
@@ -23,6 +23,7 @@
 
 #include "../../MCInst.h"
 #include "../../MCRegisterInfo.h"
+#include "../../Mapping.h"
 #include "../../MathExtras.h"
 #include "../../SStream.h"
 #include "../../utils.h"
diff --git a/arch/TriCore/TriCoreMapping.c b/arch/TriCore/TriCoreMapping.c
index 63cd5150d..b193a5a69 100644
--- a/arch/TriCore/TriCoreMapping.c
+++ b/arch/TriCore/TriCoreMapping.c
@@ -7,6 +7,7 @@
 #include <string.h>
 #include <assert.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 #include "../../cs_simple_types.h"
 
@@ -136,7 +137,7 @@ typedef struct {
 	insn_op ops[16]; ///< NULL terminated array of operands.
 } insn_ops;
 
-const insn_ops insn_operands[] = {
+static const insn_ops insn_operands[] = {
 #include "TriCoreGenCSMappingInsnOp.inc"
 };
 #endif
diff --git a/arch/WASM/WASMMapping.c b/arch/WASM/WASMMapping.c
index 88a6f513b..b81a95413 100644
--- a/arch/WASM/WASMMapping.c
+++ b/arch/WASM/WASMMapping.c
@@ -8,6 +8,7 @@
 #include "../../cs_priv.h"
 #include "../../utils.h"
 
+#include "../../Mapping.h"
 #include "WASMMapping.h"
 
 // fill in details
diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c
index 2a3d67ea1..54c5ac8d7 100644
--- a/arch/X86/X86Mapping.c
+++ b/arch/X86/X86Mapping.c
@@ -12,6 +12,8 @@
 #include <stdlib.h>
 #endif
 
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
 #include "X86Mapping.h"
 #include "X86DisassemblerDecoder.h"
 
diff --git a/arch/XCore/XCoreMapping.c b/arch/XCore/XCoreMapping.c
index 2a07e1224..c718364c7 100644
--- a/arch/XCore/XCoreMapping.c
+++ b/arch/XCore/XCoreMapping.c
@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "XCoreMapping.h"
diff --git a/cs.c b/cs.c
index c69e4b1e5..5d0f23bf5 100644
--- a/cs.c
+++ b/cs.c
@@ -815,6 +815,10 @@ cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
 				return CS_ERR_OPTION;
 			}
 			break;
+		case CS_OPT_NO_BRANCH_OFFSET:
+			if (handle->PrintBranchImmNotAsAddress)
+				return CS_ERR_OK;
+			break;
 	}
 
 	return arch_configs[handle->arch].arch_option(handle, type, value);
@@ -883,10 +887,6 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
 
 	handle->errnum = CS_ERR_OK;
 
-	// reset IT block of ARM structure
-	if (handle->arch == CS_ARCH_ARM)
-		handle->ITBlock.size = 0;
-
 #ifdef CAPSTONE_USE_SYS_DYN_MEM
 	if (count > 0 && count <= INSN_CACHE_SIZE)
 		cache_size = (unsigned int) count;
diff --git a/cs_operand.h b/cs_operand.h
new file mode 100644
index 000000000..b0701a5f5
--- /dev/null
+++ b/cs_operand.h
@@ -0,0 +1,38 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_OPERAND_H
+#define CS_OPERAND_H
+
+/// Common instruction operand types - to be consistent across all architectures.
+typedef enum cs_op_type {
+	CS_OP_INVALID = 0,  ///< uninitialized/invalid operand.
+	CS_OP_REG = 1,          ///< Register operand.
+	CS_OP_IMM = 2,          ///< Immediate operand.
+	CS_OP_FP = 3,           ///< Floating-Point operand.
+	CS_OP_PRED = 4,				  ///< Predicate operand.
+	CS_OP_RESERVED_5 = 5,
+	CS_OP_RESERVED_6 = 6,
+	CS_OP_RESERVED_7 = 7,
+	CS_OP_RESERVED_8 = 8,
+	CS_OP_RESERVED_9 = 9,
+	CS_OP_RESERVED_10 = 10,
+	CS_OP_RESERVED_11 = 11,
+	CS_OP_RESERVED_12 = 12,
+	CS_OP_RESERVED_13 = 13,
+	CS_OP_RESERVED_14 = 14,
+	CS_OP_RESERVED_15 = 15,
+	CS_OP_SPECIAL = 0x10, ///< Special operands from archs
+	CS_OP_MEM = 0x80,   ///< Memory operand. Can be ORed with another operand type.
+} cs_op_type;
+
+/// Common instruction operand access types - to be consistent across all architectures.
+/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
+typedef enum cs_ac_type {
+	CS_AC_INVALID = 0,        ///< Uninitialized/invalid access type.
+	CS_AC_READ    = 1 << 0,   ///< Operand read from memory or register.
+	CS_AC_WRITE   = 1 << 1,   ///< Operand write to memory or register.
+} cs_ac_type;
+
+#endif // CS_OPERAND_H
diff --git a/cs_priv.h b/cs_priv.h
index e473b7143..b5abd67e1 100644
--- a/cs_priv.h
+++ b/cs_priv.h
@@ -24,19 +24,21 @@ typedef const char *(*GetName_t)(csh handle, unsigned int id);
 
 typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
 
-// return register name, given register ID
-typedef const char *(*GetRegisterName_t)(unsigned RegNo);
-
 // return registers accessed by instruction
 typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
 		cs_regs regs_read, uint8_t *regs_read_count,
 		cs_regs regs_write, uint8_t *regs_write_count);
 
 // for ARM only
-typedef struct ARM_ITStatus {
+typedef struct ARM_ITBlock {
 	unsigned char ITStates[8];
 	unsigned int size;
-} ARM_ITStatus;
+} ARM_ITBlock;
+
+typedef struct ARM_VPTBlock {
+	unsigned char VPTStates[8];
+	unsigned int size;
+} ARM_VPTBlock;
 
 // Customize mnemonic for instructions with alternative name.
 struct customized_mnem {
@@ -64,13 +66,14 @@ struct cs_struct {
 	GetID_t insn_id;
 	PostPrinter_t post_printer;
 	cs_err errnum;
-	ARM_ITStatus ITBlock;	// for Arm only
+	ARM_ITBlock ITBlock;	// for Arm only
+	ARM_VPTBlock VPTBlock;  // for ARM only
+	bool PrintBranchImmNotAsAddress;
 	cs_opt_value detail, imm_unsigned;
 	int syntax;	// asm syntax for simple printer such as ARM, Mips & PPC
 	bool doing_mem;	// handling memory operand in InstPrinter code
 	bool doing_SME_Index; // handling a SME instruction that has index
 	unsigned short *insn_cache;	// index caching for mapping.c
-	GetRegisterName_t get_regname;
 	bool skipdata;	// set this to True if we skip data when disassembling
 	uint8_t skipdata_size;	// how many bytes to skip
 	cs_opt_skipdata skipdata_setup;	// user-defined skipdata setup
diff --git a/cstool/cstool.c b/cstool/cstool.c
index de1205c84..f21ab14e1 100644
--- a/cstool/cstool.c
+++ b/cstool/cstool.c
@@ -26,6 +26,7 @@ static struct {
 	{ "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
 	{ "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
 	{ "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS },
+	{ "cortexv8m", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 },
 	{ "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
 	{ "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
 	{ "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
@@ -195,6 +196,7 @@ static void usage(char *prog)
 		printf("        thumb       thumb mode\n");
 		printf("        thumbbe     thumb + big endian\n");
 		printf("        cortexm     thumb + cortex-m extensions\n");
+		printf("        cortexv8m   thumb + cortex-m extensions + v8\n");
 		printf("        armv8       arm v8\n");
 		printf("        thumbv8     thumb v8\n");
 		printf("        armv8be     arm v8 + big endian\n");
@@ -387,7 +389,7 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
 		default: break;
 	}
 
-	if (ins->detail->groups_count) {
+	if (ins->detail && ins->detail->groups_count) {
 		int j;
 
 		printf("\tGroups: ");
@@ -415,10 +417,14 @@ int main(int argc, char **argv)
 	bool detail_flag = false;
 	bool unsigned_flag = false;
 	bool skipdata = false;
+	bool custom_reg_alias = false;
 	int args_left;
 
-	while ((c = getopt (argc, argv, "sudhv")) != -1) {
+	while ((c = getopt (argc, argv, "asudhv")) != -1) {
 		switch (c) {
+			case 'a':
+				custom_reg_alias = true;
+				break;
 			case 's':
 				skipdata = true;
 				break;
@@ -583,6 +589,10 @@ int main(int argc, char **argv)
 		cs_option(handle, CS_OPT_UNSIGNED, CS_OPT_ON);
 	}
 
+	if (custom_reg_alias) {
+		cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS);
+	}
+
 	count = cs_disasm(handle, assembly, size, address, 0, &insn);
 	if (count > 0) {
 		size_t i;
diff --git a/cstool/cstool_arm.c b/cstool/cstool_arm.c
index 9ec6b4337..cad8f5569 100644
--- a/cstool/cstool_arm.c
+++ b/cstool/cstool_arm.c
@@ -28,8 +28,16 @@ void print_insn_detail_arm(csh handle, cs_insn *ins)
 			case ARM_OP_REG:
 				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
 				break;
-			case ARM_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
+			case ARM_OP_IMM: {
+				bool neg_imm = op->imm < 0;
+				if (neg_imm)
+					printf("\t\toperands[%u].type: IMM = -0x%lx\n", i, -(op->imm));
+				else
+					printf("\t\toperands[%u].type: IMM = 0x%lx\n", i, op->imm);
+				break;
+			}
+			case ARM_OP_PRED:
+				printf("\t\toperands[%u].type: PRED = %d\n", i, op->pred);
 				break;
 			case ARM_OP_FP:
 #if defined(_KERNEL_MODE)
@@ -105,14 +113,19 @@ void print_insn_detail_arm(csh handle, cs_insn *ins)
 			printf("\t\tSubtracted: True\n");
 	}
 
-	if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
+	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF)
 		printf("\tCode condition: %u\n", arm->cc);
 
+	if (arm->vcc != ARMVCC_None)
+		printf("\tVector code condition: %u\n", arm->vcc);
+
 	if (arm->update_flags)
 		printf("\tUpdate-flags: True\n");
 
-	if (arm->writeback)
+	if (ins->detail->writeback) {
 		printf("\tWrite-back: True\n");
+		printf("\tPost index: %s\n", arm->post_index ? "true" : "false");
+	}
 
 	if (arm->cps_mode)
 		printf("\tCPSI-mode: %u\n", arm->cps_mode);
@@ -132,6 +145,9 @@ void print_insn_detail_arm(csh handle, cs_insn *ins)
 	if (arm->mem_barrier)
 		printf("\tMemory-barrier: %u\n", arm->mem_barrier);
 
+	if (arm->pred_mask)
+		printf("\tPredicate Mask: 0x%x\n", arm->pred_mask);
+
 	// Print out all registers accessed by this instruction (either implicit or explicit)
 	if (!cs_regs_access(handle, ins,
 				regs_read, &regs_read_count,
diff --git a/docs/ARCHITECTURE.md b/docs/ARCHITECTURE.md
new file mode 100644
index 000000000..eefa86773
--- /dev/null
+++ b/docs/ARCHITECTURE.md
@@ -0,0 +1,118 @@
+# Capstone Architecture overview
+
+## Architecture of Capstone
+
+TODO
+
+## Architecture of a Module
+
+An architecture module is split into two components.
+
+1. The disassembler logic, which decodes bytes to instructions.
+2. The mapping logic, which maps the result from component 1 to
+a Capstone internal representation and adds additional detail.
+
+### Component 1 - Disassembler logic
+
+The disassembler logic consists exclusively of code from LLVM.
+It uses:
+
+- Generated state machines, enums and the like for instruction decoding.
+- Handwritten disassembler logic for decoding instruction operands
+and controlling the decoding procedure.
+
+### Component 2 - Mapping logic
+
+The mapping component has three different task:
+
+1. Serving as programmable interface for the Capstone core to the LLVM code.
+2. Mapping LLVM decoded instructions to a Capstone instruction.
+3. Adding additional detail to the Capstone instructions
+(e.g. operand `read/write` attributes etc.).
+
+### Instruction representation
+
+There exist two structs which represent an instruction:
+
+- `MCInst`: The LLVM representation of an instruction.
+- `cs_insn`: The Capstone representation of an instruction.
+
+The `MCInst` is used by the disassembler component for storing the decoded instruction.
+The mapping component on the other hand, uses the `MCInst` to populate the `cs_insn`.
+
+The `cs_insn` is meant to be used by the Capstone core.
+It is distinct from the `MCInst`. It uses different instruction identifiers, other operand representation
+and holds more details about an instruction.
+
+### Disassembling process
+
+There are two steps in disassembling an instruction.
+
+1. Decoding bytes to a `MCInst`.
+2. Decoding the assembler string for the `MCInst` AND mapping it to a `cs_insn` in the same step.
+
+Here is a boiled down explanation about these steps.
+
+**Step 1**
+
+```
+                                                             Forward to               
+                                     getInstr(bytes)    ┌───┐LLVM code     ┌─────────┐            ┌──────────┐
+                                    ┌──────────────────►│ A ├────────────► │         ├───────────►│          ├────┐
+                                    │                   │ R │              │ LLVM    │            │ LLVM     │    │ Decode
+                                    │                   │ C │              │         │            │          │    │ Instr.
+                                    │                   │ H │              │         │decode(Op0) │          │◄───┘
+┌────────┐ disasm(bytes) ┌──────────┴──┐                │   │              │ Disass- │ ◄──────────┤ Decoder  │
+│CS Core ├──────────────►│ ARCH Module │                │   │              │ embler  ├──────────► │ State    │
+└────────┘               └─────────────┘                │ M │              │         │            │ Machine  │
+                                    ▲                   │ A │              │         │decode(Op1) │          │
+                                    │                   │ P │              │         │ ◄──────────┤          │
+                                    │                   │ P │              │         ├──────────► │          │
+                                    │                   │ I │              │         │            │          │
+                                    │                   │ N │              │         │            │          │
+                                    └───────────────────┤ G │◄─────────────┤         │◄───────────┤          │
+                                                        └───┘              └─────────┘            └──────────┘
+```
+
+In the first decoding step the instruction bytes get forwarded to the
+decoder state machine.
+After the instruction was identified, the state machine calls decoder functions
+for each operand to extract the operand values from the bytes.
+
+The disassembler and the state machine are equivalent to what `llvm-objdump` uses
+(in fact they use the same files, except we translated them from C++ to C).
+
+**Step 2**
+
+```
+                                                        printInst(
+                                                               MCInst,
+                                                   ┌───┐       asm_buf) ┌────────┐            ┌──────────┐
+                                      ┌───────────►│ A ├──────────────► │        ├───────────►│          ├──────┐
+                                      │            │ R │                │ LLVM   │            │ LLVM     │      │ Decode
+                                      │            │ C │ add_cs_detail  │        │            │          │      │ Mnemonic
+                                      │            │ H │ (Op0)          │        │ print(Op0) │          │◄─────┘
+                                      │            │   │ ◄──────────────┤        │ ◄──────────┤          │
+           printer(MCInst,            │            │   ├──────────────► │        ├──────────► │ Asm-     │
+┌────────┐         asm_buf)┌──────────┴──┐         │   │                │ Inst   │            │ Writer   │
+│CS Core ├────────────────►│ ARCH Module │         │   │                │ Printer│            │ State    │
+└────────┘                 └─────────────┘         │ M │ add_cs_detail  │        │            │ Machine  │
+                                      ▲            │ A │ (Op1)          │        │ print(Op1) │          │
+                                      │            │ P │ ◄──────────────┤        │ ◄──────────┤          │
+                                      │            │ P ├──────────────► │        ├──────────► │          │
+                                      │            │ I │                │        │            │          │
+                                      │            │ N │                │        │            │          │
+                                      └────────────┤ G │◄───────────────┤        │◄───────────┤          │
+                                                   └───┘                └────────┘            └──────────┘
+```
+
+The second decoding step passes the `MCInst` and a buffer to the printer.
+
+After determining the mnemonic, each operand is printed by using
+functions defined in the `InstPrinter`.
+
+Each time an operand is printed, the mapping component is called
+to populate the `cs_insn` with the operand information and details.
+
+Again the `InstPrinter` and `AsmWriter` are translated code from LLVM,
+and with that mirror the behavior of `llvm-objdump`.
diff --git a/docs/AutoSync.md b/docs/AutoSync.md
new file mode 100644
index 000000000..209df4fbb
--- /dev/null
+++ b/docs/AutoSync.md
@@ -0,0 +1,198 @@
+# Auto-Sync
+
+`auto-sync` is the architecture update tool for Capstone.
+Because the architecture modules of Capstone use mostly code from LLVM,
+we need to update this part with every LLVM release. `auto-sync` helps
+with this synchronization between LLVM and Capstone's modules by
+automating most of it.
+
+You can find it in `suite/auto-sync`.
+
+This document is split into four parts.
+
+1. An overview of the update process and which subcomponents of `auto-sync` do what.
+2. The instructions how to update an architecture which already supports `auto-sync`.
+3. Instructions how to refactor an architecture to use `auto-sync`.
+4. Notes about how to add a new architecture to Capstone with `auto-sync`.
+
+Please read the section about architecture module design in
+[ARCHITECTURE.md](ARCHITECTURE.md) before proceeding.
+The architectural understanding is important for the following.
+
+## Update procedure
+
+As already described in the `ARCHITECTURE` document, Capstone uses translated
+and generated source code from LLVM.
+
+Because LLVM is written in C++ and Capstone in C the update process is
+internally complicated but almost completely automated.
+
+`auto-sync` categorizes source files of a module into three groups. Each group is updated differently.
+
+| File type                         | Update method | Edits by hand |
+|-----------------------------------|----------------------|------------------------|
+| Generated files | Generated by patched LLVM backends | Never/Not allowed |
+| Translated LLVM C++ files         | `CppTranslater` and `Differ` | Only changes which are too complicated for automation. |
+| Capstone files                    | By hand | all |
+
+Let's look at the update procedure for each group in detail.
+
+**Note**: The only exception to touch generated files is via git patches. This is the last resort
+if something is broken in LLVM, and we cannot generate correct files.
+
+**Generated files**
+
+Generated files always have the file extension `.inc`.
+
+There are generated files for the LLVM code and for Capstone. They can be distinguished by their names:
+
+- For Capstone: `<ARCH>GenCS<NAME>.inc`.
+- For LLVM code: `<ARCH>Gen<NAME>.inc`.
+
+The files are generated by refactored [LLVM TableGen emitter backends](https://github.com/capstone-engine/llvm-capstone/tree/dev/llvm/utils/TableGen).
+
+The procedure looks roughly like this:
+
+```
+                                                                   ┌──────────┐
+    1               2                 3                4           │CS .inc   │
+┌───────┐     ┌───────────┐     ┌───────────┐     ┌──────────┐  ┌─►│files     │
+│ .td   │     │           │     │           │     │ Code-    │  │  └──────────┘
+│ files ├────►│ TableGen  ├────►│  CodeGen  ├────►│ Emitter  ├──┤
+└───────┘     └──────┬────┘     └───────────┘     └──────────┘  │  ┌──────────┐
+                     │                                 ▲        └─►│LLVM .inc │
+                     └─────────────────────────────────┘           │files     │
+                                                                   └──────────┘
+```
+
+
+1. LLVM architectures are defined in `.td` files. They describe instructions, operands,
+features and other properties of an architecture.
+
+2. [LLVM TableGen](https://llvm.org/docs/TableGen/index.html) parses these files
+and converts them to an internal representation.
+
+3. In the second step a TableGen component called [CodeGen](https://llvm.org/docs/CodeGenerator.html)
+abstracts the these properties even further.
+The result is a representation which is _not_ specific to any architecture
+(e.g. the `CodeGenInstruction` class can represent a machine instruction of any architecture).
+
+4. The `Code-Emitter` uses the abstract representation of the architecture (provided from `CodeGen`) to
+generated state machines for instruction decoding.
+Architecture specific information (think of register names, operand properties etc.)
+is taken from `TableGen's` internal representation.
+
+The result is emitted to `.inc` files. Those are included in the translated C++ files or Capstone code where necessary.
+
+**Translation of LLVM C++ files**
+
+We use two tools to translate C++ to C files.
+
+First the `CppTranslator` and afterward the `Differ`.
+
+The `CppTranslator` parses the C++ files and patches C++ syntax
+with its equivalent C syntax.
+
+_Note_: For details about this checkout `suite/auto-sync/CppTranslator/README.md`.
+
+Because the result of the `CppTranslator` is not perfect,
+we still have many syntax problems left.
+
+Those need to be fixed by hand.
+In order to ease this process we run the `Differ` after the `CppTranslator`.
+
+The `Differ` parses each _translated_ file and the corresponding source file _currently_ used in Capstone.
+It then compares specific nodes from the just translated file to the equivalent nodes in the old file.
+
+The user can choose if she accepts the version from the translated file or the old file.
+This decision is saved for every node.
+If there exists a saved decision for a node, the previous decision automatically applied again.
+
+Every other syntax error must be solved manually.
+
+## Update an architecture
+
+To update an architecture do the following:
+
+Rebase `llvm-capstone` onto the new LLVM release (if not already done).
+```
+# 1. Clone Capstone's LLVM
+git clone https://github.com/capstone-engine/llvm-capstone
+
+# 2. Rebase onto the new LLVM release and resolve the conflicts.
+
+# 3. Build tblgen
+mkdir build
+cd build
+cmake -G Ninja -DLLVM_TARGETS_TO_BUILD=<ARCH> -DCMAKE_BUILD_TYPE=Debug ../llvm
+cmake --build . --target llvm-tblgen --config Debug
+
+# 4. Run git log and copy the hash of the release commit for the next step.
+git log
+
+# 5. Run the updater
+cd ../../suite/auto-sync/
+mkdir build
+cd build
+../Update-Arch.sh <ARCH> <PATH-TO-LLVM> <LLVM-RELEASE_HASH>
+```
+
+The update script will execute the steps described above and copy the new files to their directories.
+
+Afterward try to build Capstone and fix any build errors left.
+
+If new instructions or operands were added, add test cases for those
+(recession tests for instructions are located in `suite/MC/`).
+
+TODO: Operand and detail tests
+<!--
+TODO: Wait until `cstest` is rewritten and add description about operand testing.
+Issue: https://github.com/capstone-engine/capstone/issues/1984
+-->
+
+## Refactor an architecture for `auto-sync`
+
+To refactor an architecture to use `auto-sync`, you need to add it to the configuration.
+
+1. Add the architecture to the supported architectures list in `Update-Arch.sh`.
+2. Configure the `CppTranslator` for your architecture (`suite/auto-sync/CppTranslator/arch_config.json`)
+
+Now, manually run the update commands within `Update-Arch.sh` but *skip* the `Differ` step.
+
+The task after this is to:
+
+- Replace leftover C++ syntax with its C equivalent.
+- Implement the `add_cs_detail()` handler in `<ARCH>Mapping` for each operand type.
+- Add any missing logic to the translated files.
+- Make it build and write tests.
+- Run the Differ again and always select the old nodes.
+
+**Notes:**
+
+- If you find yourself fixing the same syntax error multiple times,
+please consider adding a `Patch` to the `CppTranslator` for this case.
+
+- Please check out the implementation of ARM's `add_cs_detail()` before implementing your own.
+
+- Running the `Differ` after everything is done, preserves your version of syntax corrections, and the next user can auto-apply them.
+
+- Sometimes the LLVM code uses a single function from a larger source file.
+It is not worth it to translate the whole file just for this function.
+Bundle those lonely functions in `<ARCH>DisassemblerExtension.c`.
+
+- Some generated enums must be included in the `include/capstone/<ARCH>.h` header.
+At the position where the enum should be inserted, add a comment like this (don't remove the `<>` brackets):
+
+    ```
+    // generate content <FILENAME.inc> begin
+    // generate content <FILENAME.inc> end
+    ```
+
+The update script will insert the content of the `.inc` file at this place.
+
+## Adding a new architecture
+
+Adding a new architecture follows the same steps as above. With the exception that you need
+to implement all the Capstone files from scratch.
+
+Check out an `auto-sync` supporting architectures for guidance and open an issue if you need help.
diff --git a/include/capstone/arm.h b/include/capstone/arm.h
index 37675a7f3..bb63400a9 100644
--- a/include/capstone/arm.h
+++ b/include/capstone/arm.h
@@ -3,17 +3,250 @@
 
 /* Capstone Disassembly Engine */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#include <assert.h>
+#include <string.h>
+
+#include "../../cs_operand.h"
 #include "platform.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
 #endif
 
+// Enums corresponding to ARM condition codes
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+typedef enum CondCodes {
+  // Meaning (integer)          Meaning (floating-point)
+  ARMCC_EQ, // Equal                      Equal
+  ARMCC_NE, // Not equal                  Not equal, or unordered
+  ARMCC_HS, // Carry set                  >, ==, or unordered
+  ARMCC_LO, // Carry clear                Less than
+  ARMCC_MI, // Minus, negative            Less than
+  ARMCC_PL, // Plus, positive or zero     >, ==, or unordered
+  ARMCC_VS, // Overflow                   Unordered
+  ARMCC_VC, // No overflow                Not unordered
+  ARMCC_HI, // Unsigned higher            Greater than, or unordered
+  ARMCC_LS, // Unsigned lower or same     Less than or equal
+  ARMCC_GE, // Greater than or equal      Greater than or equal
+  ARMCC_LT, // Less than                  Less than, or unordered
+  ARMCC_GT, // Greater than               Greater than
+  ARMCC_LE, // Less than or equal         <, ==, or unordered
+  ARMCC_AL, // Always (unconditional)     Always (unconditional)
+  ARMCC_UNDEF = 15, // Undefined
+} ARMCC_CondCodes;
+
+inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
+{
+  switch (CC) {
+  default:
+    // llvm_unreachable("Unknown condition code");
+    assert(0);
+  case ARMCC_EQ:
+    return ARMCC_NE;
+  case ARMCC_NE:
+    return ARMCC_EQ;
+  case ARMCC_HS:
+    return ARMCC_LO;
+  case ARMCC_LO:
+    return ARMCC_HS;
+  case ARMCC_MI:
+    return ARMCC_PL;
+  case ARMCC_PL:
+    return ARMCC_MI;
+  case ARMCC_VS:
+    return ARMCC_VC;
+  case ARMCC_VC:
+    return ARMCC_VS;
+  case ARMCC_HI:
+    return ARMCC_LS;
+  case ARMCC_LS:
+    return ARMCC_HI;
+  case ARMCC_GE:
+    return ARMCC_LT;
+  case ARMCC_LT:
+    return ARMCC_GE;
+  case ARMCC_GT:
+    return ARMCC_LE;
+  case ARMCC_LE:
+    return ARMCC_GT;
+  }
+}
+
+/// getSwappedCondition - assume the flags are set by MI(a,b), return
+/// the condition code if we modify the instructions such that flags are
+/// set by MI(b,a).
+inline static ARMCC_CondCodes ARMCC_getSwappedCondition(ARMCC_CondCodes CC)
+{
+  switch (CC) {
+  default:
+    return ARMCC_AL;
+  case ARMCC_EQ:
+    return ARMCC_EQ;
+  case ARMCC_NE:
+    return ARMCC_NE;
+  case ARMCC_HS:
+    return ARMCC_LS;
+  case ARMCC_LO:
+    return ARMCC_HI;
+  case ARMCC_HI:
+    return ARMCC_LO;
+  case ARMCC_LS:
+    return ARMCC_HS;
+  case ARMCC_GE:
+    return ARMCC_LE;
+  case ARMCC_LT:
+    return ARMCC_GT;
+  case ARMCC_GT:
+    return ARMCC_LT;
+  case ARMCC_LE:
+    return ARMCC_GE;
+  }
+}
+
+typedef enum VPTCodes {
+  ARMVCC_None = 0,
+  ARMVCC_Then,
+  ARMVCC_Else
+} ARMVCC_VPTCodes;
+
+/// Mask values for IT and VPT Blocks, to be used by MCOperands.
+/// Note that this is different from the "real" encoding used by the
+/// instructions. In this encoding, the lowest set bit indicates the end of
+/// the encoding, and above that, "1" indicates an else, while "0" indicates
+/// a then.
+///   Tx = x100
+///   Txy = xy10
+///   Txyz = xyz1
+typedef enum PredBlockMask {
+  ARM_T = 0b1000,
+  ARM_TT = 0b0100,
+  ARM_TE = 0b1100,
+  ARM_TTT = 0b0010,
+  ARM_TTE = 0b0110,
+  ARM_TEE = 0b1110,
+  ARM_TET = 0b1010,
+  ARM_TTTT = 0b0001,
+  ARM_TTTE = 0b0011,
+  ARM_TTEE = 0b0111,
+  ARM_TTET = 0b0101,
+  ARM_TEEE = 0b1111,
+  ARM_TEET = 0b1101,
+  ARM_TETT = 0b1001,
+  ARM_TETE = 0b1011
+} ARM_PredBlockMask;
+
+// Expands a PredBlockMask by adding an E or a T at the end, depending on Kind.
+// e.g ExpandPredBlockMask(T, Then) = TT, ExpandPredBlockMask(TT, Else) = TTE,
+// and so on.
+inline static const char *ARMVPTPredToString(ARMVCC_VPTCodes CC)
+{
+  switch (CC) {
+  case ARMVCC_None:
+    return "none";
+  case ARMVCC_Then:
+    return "t";
+  case ARMVCC_Else:
+    return "e";
+  }
+  assert(0 && "Unknown VPT code");
+}
+
+inline static unsigned ARMVectorCondCodeFromString(const char CC)
+{
+  switch (CC) {
+  default:
+    return ~0U;
+  case 't':
+    return ARMVCC_Then;
+  case 'e':
+    return ARMVCC_Else;
+  }
+}
+
+inline static const char *ARMCondCodeToString(ARMCC_CondCodes CC)
+{
+  switch (CC) {
+  default:
+    assert(0 && "Unknown condition code");
+  case ARMCC_EQ:
+    return "eq";
+  case ARMCC_NE:
+    return "ne";
+  case ARMCC_HS:
+    return "hs";
+  case ARMCC_LO:
+    return "lo";
+  case ARMCC_MI:
+    return "mi";
+  case ARMCC_PL:
+    return "pl";
+  case ARMCC_VS:
+    return "vs";
+  case ARMCC_VC:
+    return "vc";
+  case ARMCC_HI:
+    return "hi";
+  case ARMCC_LS:
+    return "ls";
+  case ARMCC_GE:
+    return "ge";
+  case ARMCC_LT:
+    return "lt";
+  case ARMCC_GT:
+    return "gt";
+  case ARMCC_LE:
+    return "le";
+  case ARMCC_AL:
+    return "al";
+  }
+}
+
+inline static unsigned ARMCondCodeFromString(const char *CC)
+{
+  if (strcmp("eq", CC) == 0)
+    return ARMCC_EQ;
+  else if (strcmp("ne", CC) == 0)
+    return ARMCC_NE;
+  else if (strcmp("hs", CC) == 0)
+    return ARMCC_HS;
+  else if (strcmp("cs", CC) == 0)
+    return ARMCC_HS;
+  else if (strcmp("lo", CC) == 0)
+    return ARMCC_LO;
+  else if (strcmp("cc", CC) == 0)
+    return ARMCC_LO;
+  else if (strcmp("mi", CC) == 0)
+    return ARMCC_MI;
+  else if (strcmp("pl", CC) == 0)
+    return ARMCC_PL;
+  else if (strcmp("vs", CC) == 0)
+    return ARMCC_VS;
+  else if (strcmp("vc", CC) == 0)
+    return ARMCC_VC;
+  else if (strcmp("hi", CC) == 0)
+    return ARMCC_HI;
+  else if (strcmp("ls", CC) == 0)
+    return ARMCC_LS;
+  else if (strcmp("ge", CC) == 0)
+    return ARMCC_GE;
+  else if (strcmp("lt", CC) == 0)
+    return ARMCC_LT;
+  else if (strcmp("gt", CC) == 0)
+    return ARMCC_GT;
+  else if (strcmp("le", CC) == 0)
+    return ARMCC_LE;
+  else if (strcmp("al", CC) == 0)
+    return ARMCC_AL;
+  return (~0U);
+}
+
 /// ARM shift type
 typedef enum arm_shifter {
 	ARM_SFT_INVALID = 0,
@@ -29,127 +262,9 @@ typedef enum arm_shifter {
 	ARM_SFT_RRX_REG,	///< shift with register
 } arm_shifter;
 
-/// ARM condition code
-typedef enum arm_cc {
-	ARM_CC_INVALID = 0,
-	ARM_CC_EQ,            ///< Equal                      Equal
-	ARM_CC_NE,            ///< Not equal                  Not equal, or unordered
-	ARM_CC_HS,            ///< Carry set                  >, ==, or unordered
-	ARM_CC_LO,            ///< Carry clear                Less than
-	ARM_CC_MI,            ///< Minus, negative            Less than
-	ARM_CC_PL,            ///< Plus, positive or zero     >, ==, or unordered
-	ARM_CC_VS,            ///< Overflow                   Unordered
-	ARM_CC_VC,            ///< No overflow                Not unordered
-	ARM_CC_HI,            ///< Unsigned higher            Greater than, or unordered
-	ARM_CC_LS,            ///< Unsigned lower or same     Less than or equal
-	ARM_CC_GE,            ///< Greater than or equal      Greater than or equal
-	ARM_CC_LT,            ///< Less than                  Less than, or unordered
-	ARM_CC_GT,            ///< Greater than               Greater than
-	ARM_CC_LE,            ///< Less than or equal         <, ==, or unordered
-	ARM_CC_AL             ///< Always (unconditional)     Always (unconditional)
-} arm_cc;
-
-typedef enum arm_sysreg {
-	/// Special registers for MSR
-	ARM_SYSREG_INVALID = 0,
-
-	// SPSR* registers can be OR combined
-	ARM_SYSREG_SPSR_C = 1,
-	ARM_SYSREG_SPSR_X = 2,
-	ARM_SYSREG_SPSR_S = 4,
-	ARM_SYSREG_SPSR_F = 8,
-
-	// CPSR* registers can be OR combined
-	ARM_SYSREG_CPSR_C = 16,
-	ARM_SYSREG_CPSR_X = 32,
-	ARM_SYSREG_CPSR_S = 64,
-	ARM_SYSREG_CPSR_F = 128,
-
-	// independent registers
-	ARM_SYSREG_APSR = 256,
-	ARM_SYSREG_APSR_G,
-	ARM_SYSREG_APSR_NZCVQ,
-	ARM_SYSREG_APSR_NZCVQG,
-
-	ARM_SYSREG_IAPSR,
-	ARM_SYSREG_IAPSR_G,
-	ARM_SYSREG_IAPSR_NZCVQG,
-	ARM_SYSREG_IAPSR_NZCVQ,
-
-	ARM_SYSREG_EAPSR,
-	ARM_SYSREG_EAPSR_G,
-	ARM_SYSREG_EAPSR_NZCVQG,
-	ARM_SYSREG_EAPSR_NZCVQ,
-
-	ARM_SYSREG_XPSR,
-	ARM_SYSREG_XPSR_G,
-	ARM_SYSREG_XPSR_NZCVQG,
-	ARM_SYSREG_XPSR_NZCVQ,
-
-	ARM_SYSREG_IPSR,
-	ARM_SYSREG_EPSR,
-	ARM_SYSREG_IEPSR,
-
-	ARM_SYSREG_MSP,
-	ARM_SYSREG_PSP,
-	ARM_SYSREG_PRIMASK,
-	ARM_SYSREG_BASEPRI,
-	ARM_SYSREG_BASEPRI_MAX,
-	ARM_SYSREG_FAULTMASK,
-	ARM_SYSREG_CONTROL,
-	ARM_SYSREG_MSPLIM,
-	ARM_SYSREG_PSPLIM,
-	ARM_SYSREG_MSP_NS,
-	ARM_SYSREG_PSP_NS,
-	ARM_SYSREG_MSPLIM_NS,
-	ARM_SYSREG_PSPLIM_NS,
-	ARM_SYSREG_PRIMASK_NS,
-	ARM_SYSREG_BASEPRI_NS,
-	ARM_SYSREG_FAULTMASK_NS,
-	ARM_SYSREG_CONTROL_NS,
-	ARM_SYSREG_SP_NS,
-
-	// Banked Registers
-	ARM_SYSREG_R8_USR,
-	ARM_SYSREG_R9_USR,
-	ARM_SYSREG_R10_USR,
-	ARM_SYSREG_R11_USR,
-	ARM_SYSREG_R12_USR,
-	ARM_SYSREG_SP_USR,
-	ARM_SYSREG_LR_USR,
-	ARM_SYSREG_R8_FIQ,
-	ARM_SYSREG_R9_FIQ,
-	ARM_SYSREG_R10_FIQ,
-	ARM_SYSREG_R11_FIQ,
-	ARM_SYSREG_R12_FIQ,
-	ARM_SYSREG_SP_FIQ,
-	ARM_SYSREG_LR_FIQ,
-	ARM_SYSREG_LR_IRQ,
-	ARM_SYSREG_SP_IRQ,
-	ARM_SYSREG_LR_SVC,
-	ARM_SYSREG_SP_SVC,
-	ARM_SYSREG_LR_ABT,
-	ARM_SYSREG_SP_ABT,
-	ARM_SYSREG_LR_UND,
-	ARM_SYSREG_SP_UND,
-	ARM_SYSREG_LR_MON,
-	ARM_SYSREG_SP_MON,
-	ARM_SYSREG_ELR_HYP,
-	ARM_SYSREG_SP_HYP,
-
-	ARM_SYSREG_SPSR_FIQ,
-	ARM_SYSREG_SPSR_IRQ,
-	ARM_SYSREG_SPSR_SVC,
-	ARM_SYSREG_SPSR_ABT,
-	ARM_SYSREG_SPSR_UND,
-	ARM_SYSREG_SPSR_MON,
-	ARM_SYSREG_SPSR_HYP,
-} arm_sysreg;
-
 /// The memory barrier constants map directly to the 4-bit encoding of
 /// the option field for Memory Barrier operations.
-typedef enum arm_mem_barrier {
-	ARM_MB_INVALID = 0,
+typedef enum MemBOpt {
 	ARM_MB_RESERVED_0,
 	ARM_MB_OSHLD,
 	ARM_MB_OSHST,
@@ -166,19 +281,148 @@ typedef enum arm_mem_barrier {
 	ARM_MB_LD,
 	ARM_MB_ST,
 	ARM_MB_SY,
-} arm_mem_barrier;
+} arm_mem_bo_opt;
+
+typedef enum {
+	/// Special registers for MSR
+	ARM_SYSREG_INVALID = 0,
+
+	// SPSR* registers can be OR combined
+	ARM_SYSREG_SPSR_C = 1,
+	ARM_SYSREG_SPSR_X = 2,
+	ARM_SYSREG_SPSR_S = 4,
+	ARM_SYSREG_SPSR_F = 8,
+
+	// CPSR* registers can be OR combined
+	ARM_SYSREG_CPSR_C = 16,
+	ARM_SYSREG_CPSR_X = 32,
+	ARM_SYSREG_CPSR_S = 64,
+	ARM_SYSREG_CPSR_F = 128,
+} arm_sysreg_bits;
+
+typedef enum {
+	// generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_BankedReg> begin
+	// clang-format off
+
+	ARM_BANKEDREG_ELR_HYP = 0x1e,
+	ARM_BANKEDREG_LR_ABT = 0x14,
+	ARM_BANKEDREG_LR_FIQ = 0xe,
+	ARM_BANKEDREG_LR_IRQ = 0x10,
+	ARM_BANKEDREG_LR_MON = 0x1c,
+	ARM_BANKEDREG_LR_SVC = 0x12,
+	ARM_BANKEDREG_LR_UND = 0x16,
+	ARM_BANKEDREG_LR_USR = 0x6,
+	ARM_BANKEDREG_R10_FIQ = 0xa,
+	ARM_BANKEDREG_R10_USR = 0x2,
+	ARM_BANKEDREG_R11_FIQ = 0xb,
+	ARM_BANKEDREG_R11_USR = 0x3,
+	ARM_BANKEDREG_R12_FIQ = 0xc,
+	ARM_BANKEDREG_R12_USR = 0x4,
+	ARM_BANKEDREG_R8_FIQ = 0x8,
+	ARM_BANKEDREG_R8_USR = 0x0,
+	ARM_BANKEDREG_R9_FIQ = 0x9,
+	ARM_BANKEDREG_R9_USR = 0x1,
+	ARM_BANKEDREG_SPSR_ABT = 0x34,
+	ARM_BANKEDREG_SPSR_FIQ = 0x2e,
+	ARM_BANKEDREG_SPSR_HYP = 0x3e,
+	ARM_BANKEDREG_SPSR_IRQ = 0x30,
+	ARM_BANKEDREG_SPSR_MON = 0x3c,
+	ARM_BANKEDREG_SPSR_SVC = 0x32,
+	ARM_BANKEDREG_SPSR_UND = 0x36,
+	ARM_BANKEDREG_SP_ABT = 0x15,
+	ARM_BANKEDREG_SP_FIQ = 0xd,
+	ARM_BANKEDREG_SP_HYP = 0x1f,
+	ARM_BANKEDREG_SP_IRQ = 0x11,
+	ARM_BANKEDREG_SP_MON = 0x1d,
+	ARM_BANKEDREG_SP_SVC = 0x13,
+	ARM_BANKEDREG_SP_UND = 0x17,
+	ARM_BANKEDREG_SP_USR = 0x5,
+
+	// clang-format on
+	// generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_BankedReg> end
+} arm_banked_reg;
+
+typedef enum {
+	// generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_MClassSysReg> begin
+	// clang-format off
+
+	ARM_MCLASSSYSREG_APSR = 0x800,
+	ARM_MCLASSSYSREG_APSR_G = 0x400,
+	ARM_MCLASSSYSREG_APSR_NZCVQ = 0x800,
+	ARM_MCLASSSYSREG_APSR_NZCVQG = 0xc00,
+	ARM_MCLASSSYSREG_BASEPRI = 0x811,
+	ARM_MCLASSSYSREG_BASEPRI_MAX = 0x812,
+	ARM_MCLASSSYSREG_BASEPRI_NS = 0x891,
+	ARM_MCLASSSYSREG_CONTROL = 0x814,
+	ARM_MCLASSSYSREG_CONTROL_NS = 0x894,
+	ARM_MCLASSSYSREG_EAPSR = 0x802,
+	ARM_MCLASSSYSREG_EAPSR_G = 0x402,
+	ARM_MCLASSSYSREG_EAPSR_NZCVQ = 0x802,
+	ARM_MCLASSSYSREG_EAPSR_NZCVQG = 0xc02,
+	ARM_MCLASSSYSREG_EPSR = 0x806,
+	ARM_MCLASSSYSREG_FAULTMASK = 0x813,
+	ARM_MCLASSSYSREG_FAULTMASK_NS = 0x893,
+	ARM_MCLASSSYSREG_IAPSR = 0x801,
+	ARM_MCLASSSYSREG_IAPSR_G = 0x401,
+	ARM_MCLASSSYSREG_IAPSR_NZCVQ = 0x801,
+	ARM_MCLASSSYSREG_IAPSR_NZCVQG = 0xc01,
+	ARM_MCLASSSYSREG_IEPSR = 0x807,
+	ARM_MCLASSSYSREG_IPSR = 0x805,
+	ARM_MCLASSSYSREG_MSP = 0x808,
+	ARM_MCLASSSYSREG_MSPLIM = 0x80a,
+	ARM_MCLASSSYSREG_MSPLIM_NS = 0x88a,
+	ARM_MCLASSSYSREG_MSP_NS = 0x888,
+	ARM_MCLASSSYSREG_PAC_KEY_P_0 = 0x820,
+	ARM_MCLASSSYSREG_PAC_KEY_P_0_NS = 0x8a0,
+	ARM_MCLASSSYSREG_PAC_KEY_P_1 = 0x821,
+	ARM_MCLASSSYSREG_PAC_KEY_P_1_NS = 0x8a1,
+	ARM_MCLASSSYSREG_PAC_KEY_P_2 = 0x822,
+	ARM_MCLASSSYSREG_PAC_KEY_P_2_NS = 0x8a2,
+	ARM_MCLASSSYSREG_PAC_KEY_P_3 = 0x823,
+	ARM_MCLASSSYSREG_PAC_KEY_P_3_NS = 0x8a3,
+	ARM_MCLASSSYSREG_PAC_KEY_U_0 = 0x824,
+	ARM_MCLASSSYSREG_PAC_KEY_U_0_NS = 0x8a4,
+	ARM_MCLASSSYSREG_PAC_KEY_U_1 = 0x825,
+	ARM_MCLASSSYSREG_PAC_KEY_U_1_NS = 0x8a5,
+	ARM_MCLASSSYSREG_PAC_KEY_U_2 = 0x826,
+	ARM_MCLASSSYSREG_PAC_KEY_U_2_NS = 0x8a6,
+	ARM_MCLASSSYSREG_PAC_KEY_U_3 = 0x827,
+	ARM_MCLASSSYSREG_PAC_KEY_U_3_NS = 0x8a7,
+	ARM_MCLASSSYSREG_PRIMASK = 0x810,
+	ARM_MCLASSSYSREG_PRIMASK_NS = 0x890,
+	ARM_MCLASSSYSREG_PSP = 0x809,
+	ARM_MCLASSSYSREG_PSPLIM = 0x80b,
+	ARM_MCLASSSYSREG_PSPLIM_NS = 0x88b,
+	ARM_MCLASSSYSREG_PSP_NS = 0x889,
+	ARM_MCLASSSYSREG_SP_NS = 0x898,
+	ARM_MCLASSSYSREG_XPSR = 0x803,
+	ARM_MCLASSSYSREG_XPSR_G = 0x403,
+	ARM_MCLASSSYSREG_XPSR_NZCVQ = 0x803,
+	ARM_MCLASSSYSREG_XPSR_NZCVQG = 0xc03,
+
+	// clang-format on
+	// generated content <ARMGenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_MClassSysReg> end
+} arm_sysreg;
+
+typedef union {
+  arm_sysreg sysreg;
+  arm_banked_reg banked_reg;
+} arm_sysop_reg;
 
 /// Operand type for instruction's operands
 typedef enum arm_op_type {
-	ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	ARM_OP_REG, ///< = CS_OP_REG (Register operand).
-	ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand).
-	ARM_OP_FP,  ///< = CS_OP_FP (Floating-Point operand).
-	ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers)
-	ARM_OP_PIMM, ///< P-Immediate (coprocessor registers)
-	ARM_OP_SETEND,	///< operand for SETEND instruction
-	ARM_OP_SYSREG,	///< MSR/MRS special register operand
+	ARM_OP_INVALID = CS_OP_INVALID, ///< Invalid
+	ARM_OP_REG = CS_OP_REG, ///< Register operand
+	ARM_OP_IMM = CS_OP_IMM, ///< Immediate operand
+	ARM_OP_FP = CS_OP_FP,  ///< Floating-Point operand
+	ARM_OP_PRED = CS_OP_PRED, ///< Predicate
+	ARM_OP_CIMM = CS_OP_SPECIAL + 0, ///< C-Immediate (coprocessor registers)
+	ARM_OP_PIMM = CS_OP_SPECIAL + 1, ///< P-Immediate (coprocessor registers)
+	ARM_OP_SETEND = CS_OP_SPECIAL + 2,	///< operand for SETEND instruction
+	ARM_OP_SYSREG = CS_OP_SPECIAL + 3,	///< MSR/MRS special register operand
+	ARM_OP_VPRED_R = CS_OP_SPECIAL + 4, ///< Vector predicate. Leaves inactive lanes of output vector register unchanged.
+	ARM_OP_VPRED_N = CS_OP_SPECIAL + 5, ///< Vector predicate. Don't preserved inactive lanes of output register.
+	ARM_OP_MEM = CS_OP_MEM, ///< Memory operand
 } arm_op_type;
 
 /// Operand type for SETEND instruction
@@ -266,119 +510,309 @@ typedef enum arm_vectordata_type {
 
 /// ARM registers
 typedef enum arm_reg {
-	ARM_REG_INVALID = 0,
-	ARM_REG_APSR,
-	ARM_REG_APSR_NZCV,
-	ARM_REG_CPSR,
-	ARM_REG_FPEXC,
-	ARM_REG_FPINST,
-	ARM_REG_FPSCR,
-	ARM_REG_FPSCR_NZCV,
-	ARM_REG_FPSID,
-	ARM_REG_ITSTATE,
-	ARM_REG_LR,
-	ARM_REG_PC,
-	ARM_REG_SP,
-	ARM_REG_SPSR,
-	ARM_REG_D0,
-	ARM_REG_D1,
-	ARM_REG_D2,
-	ARM_REG_D3,
-	ARM_REG_D4,
-	ARM_REG_D5,
-	ARM_REG_D6,
-	ARM_REG_D7,
-	ARM_REG_D8,
-	ARM_REG_D9,
-	ARM_REG_D10,
-	ARM_REG_D11,
-	ARM_REG_D12,
-	ARM_REG_D13,
-	ARM_REG_D14,
-	ARM_REG_D15,
-	ARM_REG_D16,
-	ARM_REG_D17,
-	ARM_REG_D18,
-	ARM_REG_D19,
-	ARM_REG_D20,
-	ARM_REG_D21,
-	ARM_REG_D22,
-	ARM_REG_D23,
-	ARM_REG_D24,
-	ARM_REG_D25,
-	ARM_REG_D26,
-	ARM_REG_D27,
-	ARM_REG_D28,
-	ARM_REG_D29,
-	ARM_REG_D30,
-	ARM_REG_D31,
-	ARM_REG_FPINST2,
-	ARM_REG_MVFR0,
-	ARM_REG_MVFR1,
-	ARM_REG_MVFR2,
-	ARM_REG_Q0,
-	ARM_REG_Q1,
-	ARM_REG_Q2,
-	ARM_REG_Q3,
-	ARM_REG_Q4,
-	ARM_REG_Q5,
-	ARM_REG_Q6,
-	ARM_REG_Q7,
-	ARM_REG_Q8,
-	ARM_REG_Q9,
-	ARM_REG_Q10,
-	ARM_REG_Q11,
-	ARM_REG_Q12,
-	ARM_REG_Q13,
-	ARM_REG_Q14,
-	ARM_REG_Q15,
-	ARM_REG_R0,
-	ARM_REG_R1,
-	ARM_REG_R2,
-	ARM_REG_R3,
-	ARM_REG_R4,
-	ARM_REG_R5,
-	ARM_REG_R6,
-	ARM_REG_R7,
-	ARM_REG_R8,
-	ARM_REG_R9,
-	ARM_REG_R10,
-	ARM_REG_R11,
-	ARM_REG_R12,
-	ARM_REG_S0,
-	ARM_REG_S1,
-	ARM_REG_S2,
-	ARM_REG_S3,
-	ARM_REG_S4,
-	ARM_REG_S5,
-	ARM_REG_S6,
-	ARM_REG_S7,
-	ARM_REG_S8,
-	ARM_REG_S9,
-	ARM_REG_S10,
-	ARM_REG_S11,
-	ARM_REG_S12,
-	ARM_REG_S13,
-	ARM_REG_S14,
-	ARM_REG_S15,
-	ARM_REG_S16,
-	ARM_REG_S17,
-	ARM_REG_S18,
-	ARM_REG_S19,
-	ARM_REG_S20,
-	ARM_REG_S21,
-	ARM_REG_S22,
-	ARM_REG_S23,
-	ARM_REG_S24,
-	ARM_REG_S25,
-	ARM_REG_S26,
-	ARM_REG_S27,
-	ARM_REG_S28,
-	ARM_REG_S29,
-	ARM_REG_S30,
-	ARM_REG_S31,
+	// generated content <ARMGenCSRegEnum.inc> begin
+	// clang-format off
 
-	ARM_REG_ENDING,		// <-- mark the end of the list or registers
+	ARM_REG_INVALID = 0,
+	ARM_REG_APSR = 1,
+	ARM_REG_APSR_NZCV = 2,
+	ARM_REG_CPSR = 3,
+	ARM_REG_FPCXTNS = 4,
+	ARM_REG_FPCXTS = 5,
+	ARM_REG_FPEXC = 6,
+	ARM_REG_FPINST = 7,
+	ARM_REG_FPSCR = 8,
+	ARM_REG_FPSCR_NZCV = 9,
+	ARM_REG_FPSCR_NZCVQC = 10,
+	ARM_REG_FPSID = 11,
+	ARM_REG_ITSTATE = 12,
+	ARM_REG_LR = 13,
+	ARM_REG_PC = 14,
+	ARM_REG_RA_AUTH_CODE = 15,
+	ARM_REG_SP = 16,
+	ARM_REG_SPSR = 17,
+	ARM_REG_VPR = 18,
+	ARM_REG_ZR = 19,
+	ARM_REG_D0 = 20,
+	ARM_REG_D1 = 21,
+	ARM_REG_D2 = 22,
+	ARM_REG_D3 = 23,
+	ARM_REG_D4 = 24,
+	ARM_REG_D5 = 25,
+	ARM_REG_D6 = 26,
+	ARM_REG_D7 = 27,
+	ARM_REG_D8 = 28,
+	ARM_REG_D9 = 29,
+	ARM_REG_D10 = 30,
+	ARM_REG_D11 = 31,
+	ARM_REG_D12 = 32,
+	ARM_REG_D13 = 33,
+	ARM_REG_D14 = 34,
+	ARM_REG_D15 = 35,
+	ARM_REG_D16 = 36,
+	ARM_REG_D17 = 37,
+	ARM_REG_D18 = 38,
+	ARM_REG_D19 = 39,
+	ARM_REG_D20 = 40,
+	ARM_REG_D21 = 41,
+	ARM_REG_D22 = 42,
+	ARM_REG_D23 = 43,
+	ARM_REG_D24 = 44,
+	ARM_REG_D25 = 45,
+	ARM_REG_D26 = 46,
+	ARM_REG_D27 = 47,
+	ARM_REG_D28 = 48,
+	ARM_REG_D29 = 49,
+	ARM_REG_D30 = 50,
+	ARM_REG_D31 = 51,
+	ARM_REG_FPINST2 = 52,
+	ARM_REG_MVFR0 = 53,
+	ARM_REG_MVFR1 = 54,
+	ARM_REG_MVFR2 = 55,
+	ARM_REG_P0 = 56,
+	ARM_REG_Q0 = 57,
+	ARM_REG_Q1 = 58,
+	ARM_REG_Q2 = 59,
+	ARM_REG_Q3 = 60,
+	ARM_REG_Q4 = 61,
+	ARM_REG_Q5 = 62,
+	ARM_REG_Q6 = 63,
+	ARM_REG_Q7 = 64,
+	ARM_REG_Q8 = 65,
+	ARM_REG_Q9 = 66,
+	ARM_REG_Q10 = 67,
+	ARM_REG_Q11 = 68,
+	ARM_REG_Q12 = 69,
+	ARM_REG_Q13 = 70,
+	ARM_REG_Q14 = 71,
+	ARM_REG_Q15 = 72,
+	ARM_REG_R0 = 73,
+	ARM_REG_R1 = 74,
+	ARM_REG_R2 = 75,
+	ARM_REG_R3 = 76,
+	ARM_REG_R4 = 77,
+	ARM_REG_R5 = 78,
+	ARM_REG_R6 = 79,
+	ARM_REG_R7 = 80,
+	ARM_REG_R8 = 81,
+	ARM_REG_R9 = 82,
+	ARM_REG_R10 = 83,
+	ARM_REG_R11 = 84,
+	ARM_REG_R12 = 85,
+	ARM_REG_S0 = 86,
+	ARM_REG_S1 = 87,
+	ARM_REG_S2 = 88,
+	ARM_REG_S3 = 89,
+	ARM_REG_S4 = 90,
+	ARM_REG_S5 = 91,
+	ARM_REG_S6 = 92,
+	ARM_REG_S7 = 93,
+	ARM_REG_S8 = 94,
+	ARM_REG_S9 = 95,
+	ARM_REG_S10 = 96,
+	ARM_REG_S11 = 97,
+	ARM_REG_S12 = 98,
+	ARM_REG_S13 = 99,
+	ARM_REG_S14 = 100,
+	ARM_REG_S15 = 101,
+	ARM_REG_S16 = 102,
+	ARM_REG_S17 = 103,
+	ARM_REG_S18 = 104,
+	ARM_REG_S19 = 105,
+	ARM_REG_S20 = 106,
+	ARM_REG_S21 = 107,
+	ARM_REG_S22 = 108,
+	ARM_REG_S23 = 109,
+	ARM_REG_S24 = 110,
+	ARM_REG_S25 = 111,
+	ARM_REG_S26 = 112,
+	ARM_REG_S27 = 113,
+	ARM_REG_S28 = 114,
+	ARM_REG_S29 = 115,
+	ARM_REG_S30 = 116,
+	ARM_REG_S31 = 117,
+	ARM_REG_D0_D2 = 118,
+	ARM_REG_D1_D3 = 119,
+	ARM_REG_D2_D4 = 120,
+	ARM_REG_D3_D5 = 121,
+	ARM_REG_D4_D6 = 122,
+	ARM_REG_D5_D7 = 123,
+	ARM_REG_D6_D8 = 124,
+	ARM_REG_D7_D9 = 125,
+	ARM_REG_D8_D10 = 126,
+	ARM_REG_D9_D11 = 127,
+	ARM_REG_D10_D12 = 128,
+	ARM_REG_D11_D13 = 129,
+	ARM_REG_D12_D14 = 130,
+	ARM_REG_D13_D15 = 131,
+	ARM_REG_D14_D16 = 132,
+	ARM_REG_D15_D17 = 133,
+	ARM_REG_D16_D18 = 134,
+	ARM_REG_D17_D19 = 135,
+	ARM_REG_D18_D20 = 136,
+	ARM_REG_D19_D21 = 137,
+	ARM_REG_D20_D22 = 138,
+	ARM_REG_D21_D23 = 139,
+	ARM_REG_D22_D24 = 140,
+	ARM_REG_D23_D25 = 141,
+	ARM_REG_D24_D26 = 142,
+	ARM_REG_D25_D27 = 143,
+	ARM_REG_D26_D28 = 144,
+	ARM_REG_D27_D29 = 145,
+	ARM_REG_D28_D30 = 146,
+	ARM_REG_D29_D31 = 147,
+	ARM_REG_Q0_Q1 = 148,
+	ARM_REG_Q1_Q2 = 149,
+	ARM_REG_Q2_Q3 = 150,
+	ARM_REG_Q3_Q4 = 151,
+	ARM_REG_Q4_Q5 = 152,
+	ARM_REG_Q5_Q6 = 153,
+	ARM_REG_Q6_Q7 = 154,
+	ARM_REG_Q7_Q8 = 155,
+	ARM_REG_Q8_Q9 = 156,
+	ARM_REG_Q9_Q10 = 157,
+	ARM_REG_Q10_Q11 = 158,
+	ARM_REG_Q11_Q12 = 159,
+	ARM_REG_Q12_Q13 = 160,
+	ARM_REG_Q13_Q14 = 161,
+	ARM_REG_Q14_Q15 = 162,
+	ARM_REG_Q0_Q1_Q2_Q3 = 163,
+	ARM_REG_Q1_Q2_Q3_Q4 = 164,
+	ARM_REG_Q2_Q3_Q4_Q5 = 165,
+	ARM_REG_Q3_Q4_Q5_Q6 = 166,
+	ARM_REG_Q4_Q5_Q6_Q7 = 167,
+	ARM_REG_Q5_Q6_Q7_Q8 = 168,
+	ARM_REG_Q6_Q7_Q8_Q9 = 169,
+	ARM_REG_Q7_Q8_Q9_Q10 = 170,
+	ARM_REG_Q8_Q9_Q10_Q11 = 171,
+	ARM_REG_Q9_Q10_Q11_Q12 = 172,
+	ARM_REG_Q10_Q11_Q12_Q13 = 173,
+	ARM_REG_Q11_Q12_Q13_Q14 = 174,
+	ARM_REG_Q12_Q13_Q14_Q15 = 175,
+	ARM_REG_R0_R1 = 176,
+	ARM_REG_R2_R3 = 177,
+	ARM_REG_R4_R5 = 178,
+	ARM_REG_R6_R7 = 179,
+	ARM_REG_R8_R9 = 180,
+	ARM_REG_R10_R11 = 181,
+	ARM_REG_R12_SP = 182,
+	ARM_REG_D0_D1_D2 = 183,
+	ARM_REG_D1_D2_D3 = 184,
+	ARM_REG_D2_D3_D4 = 185,
+	ARM_REG_D3_D4_D5 = 186,
+	ARM_REG_D4_D5_D6 = 187,
+	ARM_REG_D5_D6_D7 = 188,
+	ARM_REG_D6_D7_D8 = 189,
+	ARM_REG_D7_D8_D9 = 190,
+	ARM_REG_D8_D9_D10 = 191,
+	ARM_REG_D9_D10_D11 = 192,
+	ARM_REG_D10_D11_D12 = 193,
+	ARM_REG_D11_D12_D13 = 194,
+	ARM_REG_D12_D13_D14 = 195,
+	ARM_REG_D13_D14_D15 = 196,
+	ARM_REG_D14_D15_D16 = 197,
+	ARM_REG_D15_D16_D17 = 198,
+	ARM_REG_D16_D17_D18 = 199,
+	ARM_REG_D17_D18_D19 = 200,
+	ARM_REG_D18_D19_D20 = 201,
+	ARM_REG_D19_D20_D21 = 202,
+	ARM_REG_D20_D21_D22 = 203,
+	ARM_REG_D21_D22_D23 = 204,
+	ARM_REG_D22_D23_D24 = 205,
+	ARM_REG_D23_D24_D25 = 206,
+	ARM_REG_D24_D25_D26 = 207,
+	ARM_REG_D25_D26_D27 = 208,
+	ARM_REG_D26_D27_D28 = 209,
+	ARM_REG_D27_D28_D29 = 210,
+	ARM_REG_D28_D29_D30 = 211,
+	ARM_REG_D29_D30_D31 = 212,
+	ARM_REG_D0_D2_D4 = 213,
+	ARM_REG_D1_D3_D5 = 214,
+	ARM_REG_D2_D4_D6 = 215,
+	ARM_REG_D3_D5_D7 = 216,
+	ARM_REG_D4_D6_D8 = 217,
+	ARM_REG_D5_D7_D9 = 218,
+	ARM_REG_D6_D8_D10 = 219,
+	ARM_REG_D7_D9_D11 = 220,
+	ARM_REG_D8_D10_D12 = 221,
+	ARM_REG_D9_D11_D13 = 222,
+	ARM_REG_D10_D12_D14 = 223,
+	ARM_REG_D11_D13_D15 = 224,
+	ARM_REG_D12_D14_D16 = 225,
+	ARM_REG_D13_D15_D17 = 226,
+	ARM_REG_D14_D16_D18 = 227,
+	ARM_REG_D15_D17_D19 = 228,
+	ARM_REG_D16_D18_D20 = 229,
+	ARM_REG_D17_D19_D21 = 230,
+	ARM_REG_D18_D20_D22 = 231,
+	ARM_REG_D19_D21_D23 = 232,
+	ARM_REG_D20_D22_D24 = 233,
+	ARM_REG_D21_D23_D25 = 234,
+	ARM_REG_D22_D24_D26 = 235,
+	ARM_REG_D23_D25_D27 = 236,
+	ARM_REG_D24_D26_D28 = 237,
+	ARM_REG_D25_D27_D29 = 238,
+	ARM_REG_D26_D28_D30 = 239,
+	ARM_REG_D27_D29_D31 = 240,
+	ARM_REG_D0_D2_D4_D6 = 241,
+	ARM_REG_D1_D3_D5_D7 = 242,
+	ARM_REG_D2_D4_D6_D8 = 243,
+	ARM_REG_D3_D5_D7_D9 = 244,
+	ARM_REG_D4_D6_D8_D10 = 245,
+	ARM_REG_D5_D7_D9_D11 = 246,
+	ARM_REG_D6_D8_D10_D12 = 247,
+	ARM_REG_D7_D9_D11_D13 = 248,
+	ARM_REG_D8_D10_D12_D14 = 249,
+	ARM_REG_D9_D11_D13_D15 = 250,
+	ARM_REG_D10_D12_D14_D16 = 251,
+	ARM_REG_D11_D13_D15_D17 = 252,
+	ARM_REG_D12_D14_D16_D18 = 253,
+	ARM_REG_D13_D15_D17_D19 = 254,
+	ARM_REG_D14_D16_D18_D20 = 255,
+	ARM_REG_D15_D17_D19_D21 = 256,
+	ARM_REG_D16_D18_D20_D22 = 257,
+	ARM_REG_D17_D19_D21_D23 = 258,
+	ARM_REG_D18_D20_D22_D24 = 259,
+	ARM_REG_D19_D21_D23_D25 = 260,
+	ARM_REG_D20_D22_D24_D26 = 261,
+	ARM_REG_D21_D23_D25_D27 = 262,
+	ARM_REG_D22_D24_D26_D28 = 263,
+	ARM_REG_D23_D25_D27_D29 = 264,
+	ARM_REG_D24_D26_D28_D30 = 265,
+	ARM_REG_D25_D27_D29_D31 = 266,
+	ARM_REG_D1_D2 = 267,
+	ARM_REG_D3_D4 = 268,
+	ARM_REG_D5_D6 = 269,
+	ARM_REG_D7_D8 = 270,
+	ARM_REG_D9_D10 = 271,
+	ARM_REG_D11_D12 = 272,
+	ARM_REG_D13_D14 = 273,
+	ARM_REG_D15_D16 = 274,
+	ARM_REG_D17_D18 = 275,
+	ARM_REG_D19_D20 = 276,
+	ARM_REG_D21_D22 = 277,
+	ARM_REG_D23_D24 = 278,
+	ARM_REG_D25_D26 = 279,
+	ARM_REG_D27_D28 = 280,
+	ARM_REG_D29_D30 = 281,
+	ARM_REG_D1_D2_D3_D4 = 282,
+	ARM_REG_D3_D4_D5_D6 = 283,
+	ARM_REG_D5_D6_D7_D8 = 284,
+	ARM_REG_D7_D8_D9_D10 = 285,
+	ARM_REG_D9_D10_D11_D12 = 286,
+	ARM_REG_D11_D12_D13_D14 = 287,
+	ARM_REG_D13_D14_D15_D16 = 288,
+	ARM_REG_D15_D16_D17_D18 = 289,
+	ARM_REG_D17_D18_D19_D20 = 290,
+	ARM_REG_D19_D20_D21_D22 = 291,
+	ARM_REG_D21_D22_D23_D24 = 292,
+	ARM_REG_D23_D24_D25_D26 = 293,
+	ARM_REG_D25_D26_D27_D28 = 294,
+	ARM_REG_D27_D28_D29_D30 = 295,
+	ARM_REG_ENDING, // 296
+
+	// clang-format on
+	// generated content <ARMGenCSRegEnum.inc> end
 
 	// alias registers
 	ARM_REG_R13 = ARM_REG_SP,
@@ -416,7 +850,8 @@ typedef struct cs_arm_op {
 
 	union {
 		int reg;	///< register value for REG/SYSREG operand
-		int32_t imm;			///< immediate value for C-IMM, P-IMM or IMM operand
+		int64_t imm;			///< immediate value for C-IMM, P-IMM or IMM operand
+		int pred;			///< Predicate operand value.
 		double fp;			///< floating point value for FP operand
 		arm_op_mem mem;		///< base/index/scale/disp value for MEM operand
 		arm_setend_type setend; ///< SETEND instruction's operand type
@@ -436,6 +871,8 @@ typedef struct cs_arm_op {
 	int8_t neon_lane;
 } cs_arm_op;
 
+#define MAX_ARM_OPS 36
+
 /// Instruction structure
 typedef struct cs_arm {
 	bool usermode;	///< User-mode registers to be loaded (for LDM/STM instructions)
@@ -443,46 +880,94 @@ typedef struct cs_arm {
 	arm_vectordata_type vector_data; ///< Data type for elements of vector instructions
 	arm_cpsmode_type cps_mode;	///< CPS mode for CPS instruction
 	arm_cpsflag_type cps_flag;	///< CPS mode for CPS instruction
-	arm_cc cc;			///< conditional code for this insn
+	ARMCC_CondCodes cc;		///< conditional code for this insn
+	ARMVCC_VPTCodes vcc;	///< Vector conditional code for this instruction.
 	bool update_flags;	///< does this insn update flags?
-	bool writeback;		///< does this insn write-back?
 	bool post_index;	///< only set if writeback is 'True', if 'False' pre-index, otherwise post.
-	arm_mem_barrier mem_barrier;	///< Option for some memory barrier instructions
-
+	int /* arm_mem_bo_opt */ mem_barrier;	///< Option for some memory barrier instructions
+	// Check ARM_PredBlockMask for encoding details.
+	uint8_t /* ARM_PredBlockMask */ pred_mask;	///< Used by IT/VPT block instructions.
 	/// Number of operands of this instruction,
 	/// or 0 when instruction has no operand.
 	uint8_t op_count;
 
-	cs_arm_op operands[36];	///< operands for this instruction.
+	cs_arm_op operands[MAX_ARM_OPS];	///< operands for this instruction.
 } cs_arm;
 
 /// ARM instruction
 typedef enum arm_insn {
-	ARM_INS_INVALID = 0,
+	// generated content <ARMGenCSInsnEnum.inc> begin
+	// clang-format off
 
+	ARM_INS_INVALID,
+	ARM_INS_ASR,
+	ARM_INS_IT,
+	ARM_INS_LDRBT,
+	ARM_INS_LDR,
+	ARM_INS_LDRHT,
+	ARM_INS_LDRSBT,
+	ARM_INS_LDRSHT,
+	ARM_INS_LDRT,
+	ARM_INS_LSL,
+	ARM_INS_LSR,
+	ARM_INS_ROR,
+	ARM_INS_RRX,
+	ARM_INS_STRBT,
+	ARM_INS_STRT,
+	ARM_INS_VLD1,
+	ARM_INS_VLD2,
+	ARM_INS_VLD3,
+	ARM_INS_VLD4,
+	ARM_INS_VST1,
+	ARM_INS_VST2,
+	ARM_INS_VST3,
+	ARM_INS_VST4,
+	ARM_INS_LDRB,
+	ARM_INS_LDRH,
+	ARM_INS_LDRSB,
+	ARM_INS_LDRSH,
+	ARM_INS_MOVS,
+	ARM_INS_MOV,
+	ARM_INS_STR,
 	ARM_INS_ADC,
 	ARM_INS_ADD,
-	ARM_INS_ADDW,
 	ARM_INS_ADR,
 	ARM_INS_AESD,
 	ARM_INS_AESE,
 	ARM_INS_AESIMC,
 	ARM_INS_AESMC,
 	ARM_INS_AND,
-	ARM_INS_ASR,
-	ARM_INS_B,
+	ARM_INS_VDOT,
+	ARM_INS_VCVT,
+	ARM_INS_VCVTB,
+	ARM_INS_VCVTT,
 	ARM_INS_BFC,
 	ARM_INS_BFI,
 	ARM_INS_BIC,
 	ARM_INS_BKPT,
 	ARM_INS_BL,
 	ARM_INS_BLX,
-	ARM_INS_BLXNS,
 	ARM_INS_BX,
 	ARM_INS_BXJ,
-	ARM_INS_BXNS,
-	ARM_INS_CBNZ,
-	ARM_INS_CBZ,
+	ARM_INS_B,
+	ARM_INS_CX1,
+	ARM_INS_CX1A,
+	ARM_INS_CX1D,
+	ARM_INS_CX1DA,
+	ARM_INS_CX2,
+	ARM_INS_CX2A,
+	ARM_INS_CX2D,
+	ARM_INS_CX2DA,
+	ARM_INS_CX3,
+	ARM_INS_CX3A,
+	ARM_INS_CX3D,
+	ARM_INS_CX3DA,
+	ARM_INS_VCX1A,
+	ARM_INS_VCX1,
+	ARM_INS_VCX2A,
+	ARM_INS_VCX2,
+	ARM_INS_VCX3A,
+	ARM_INS_VCX3,
 	ARM_INS_CDP,
 	ARM_INS_CDP2,
 	ARM_INS_CLREX,
@@ -496,37 +981,21 @@ typedef enum arm_insn {
 	ARM_INS_CRC32CW,
 	ARM_INS_CRC32H,
 	ARM_INS_CRC32W,
-	ARM_INS_CSDB,
 	ARM_INS_DBG,
-	ARM_INS_DCPS1,
-	ARM_INS_DCPS2,
-	ARM_INS_DCPS3,
-	ARM_INS_DFB,
 	ARM_INS_DMB,
 	ARM_INS_DSB,
 	ARM_INS_EOR,
 	ARM_INS_ERET,
-	ARM_INS_ESB,
-	ARM_INS_FADDD,
-	ARM_INS_FADDS,
-	ARM_INS_FCMPZD,
-	ARM_INS_FCMPZS,
-	ARM_INS_FCONSTD,
-	ARM_INS_FCONSTS,
+	ARM_INS_VMOV,
 	ARM_INS_FLDMDBX,
 	ARM_INS_FLDMIAX,
-	ARM_INS_FMDHR,
-	ARM_INS_FMDLR,
-	ARM_INS_FMSTAT,
+	ARM_INS_VMRS,
 	ARM_INS_FSTMDBX,
 	ARM_INS_FSTMIAX,
-	ARM_INS_FSUBD,
-	ARM_INS_FSUBS,
 	ARM_INS_HINT,
 	ARM_INS_HLT,
 	ARM_INS_HVC,
 	ARM_INS_ISB,
-	ARM_INS_IT,
 	ARM_INS_LDA,
 	ARM_INS_LDAB,
 	ARM_INS_LDAEX,
@@ -534,39 +1003,25 @@ typedef enum arm_insn {
 	ARM_INS_LDAEXD,
 	ARM_INS_LDAEXH,
 	ARM_INS_LDAH,
-	ARM_INS_LDC,
-	ARM_INS_LDC2,
 	ARM_INS_LDC2L,
+	ARM_INS_LDC2,
 	ARM_INS_LDCL,
-	ARM_INS_LDM,
+	ARM_INS_LDC,
 	ARM_INS_LDMDA,
 	ARM_INS_LDMDB,
+	ARM_INS_LDM,
 	ARM_INS_LDMIB,
-	ARM_INS_LDR,
-	ARM_INS_LDRB,
-	ARM_INS_LDRBT,
 	ARM_INS_LDRD,
 	ARM_INS_LDREX,
 	ARM_INS_LDREXB,
 	ARM_INS_LDREXD,
 	ARM_INS_LDREXH,
-	ARM_INS_LDRH,
-	ARM_INS_LDRHT,
-	ARM_INS_LDRSB,
-	ARM_INS_LDRSBT,
-	ARM_INS_LDRSH,
-	ARM_INS_LDRSHT,
-	ARM_INS_LDRT,
-	ARM_INS_LSL,
-	ARM_INS_LSR,
 	ARM_INS_MCR,
 	ARM_INS_MCR2,
 	ARM_INS_MCRR,
 	ARM_INS_MCRR2,
 	ARM_INS_MLA,
 	ARM_INS_MLS,
-	ARM_INS_MOV,
-	ARM_INS_MOVS,
 	ARM_INS_MOVT,
 	ARM_INS_MOVW,
 	ARM_INS_MRC,
@@ -576,18 +1031,208 @@ typedef enum arm_insn {
 	ARM_INS_MRS,
 	ARM_INS_MSR,
 	ARM_INS_MUL,
+	ARM_INS_ASRL,
+	ARM_INS_DLSTP,
+	ARM_INS_LCTP,
+	ARM_INS_LETP,
+	ARM_INS_LSLL,
+	ARM_INS_LSRL,
+	ARM_INS_SQRSHR,
+	ARM_INS_SQRSHRL,
+	ARM_INS_SQSHL,
+	ARM_INS_SQSHLL,
+	ARM_INS_SRSHR,
+	ARM_INS_SRSHRL,
+	ARM_INS_UQRSHL,
+	ARM_INS_UQRSHLL,
+	ARM_INS_UQSHL,
+	ARM_INS_UQSHLL,
+	ARM_INS_URSHR,
+	ARM_INS_URSHRL,
+	ARM_INS_VABAV,
+	ARM_INS_VABD,
+	ARM_INS_VABS,
+	ARM_INS_VADC,
+	ARM_INS_VADCI,
+	ARM_INS_VADDLVA,
+	ARM_INS_VADDLV,
+	ARM_INS_VADDVA,
+	ARM_INS_VADDV,
+	ARM_INS_VADD,
+	ARM_INS_VAND,
+	ARM_INS_VBIC,
+	ARM_INS_VBRSR,
+	ARM_INS_VCADD,
+	ARM_INS_VCLS,
+	ARM_INS_VCLZ,
+	ARM_INS_VCMLA,
+	ARM_INS_VCMP,
+	ARM_INS_VCMUL,
+	ARM_INS_VCTP,
+	ARM_INS_VCVTA,
+	ARM_INS_VCVTM,
+	ARM_INS_VCVTN,
+	ARM_INS_VCVTP,
+	ARM_INS_VDDUP,
+	ARM_INS_VDUP,
+	ARM_INS_VDWDUP,
+	ARM_INS_VEOR,
+	ARM_INS_VFMAS,
+	ARM_INS_VFMA,
+	ARM_INS_VFMS,
+	ARM_INS_VHADD,
+	ARM_INS_VHCADD,
+	ARM_INS_VHSUB,
+	ARM_INS_VIDUP,
+	ARM_INS_VIWDUP,
+	ARM_INS_VLD20,
+	ARM_INS_VLD21,
+	ARM_INS_VLD40,
+	ARM_INS_VLD41,
+	ARM_INS_VLD42,
+	ARM_INS_VLD43,
+	ARM_INS_VLDRB,
+	ARM_INS_VLDRD,
+	ARM_INS_VLDRH,
+	ARM_INS_VLDRW,
+	ARM_INS_VMAXAV,
+	ARM_INS_VMAXA,
+	ARM_INS_VMAXNMAV,
+	ARM_INS_VMAXNMA,
+	ARM_INS_VMAXNMV,
+	ARM_INS_VMAXNM,
+	ARM_INS_VMAXV,
+	ARM_INS_VMAX,
+	ARM_INS_VMINAV,
+	ARM_INS_VMINA,
+	ARM_INS_VMINNMAV,
+	ARM_INS_VMINNMA,
+	ARM_INS_VMINNMV,
+	ARM_INS_VMINNM,
+	ARM_INS_VMINV,
+	ARM_INS_VMIN,
+	ARM_INS_VMLADAVA,
+	ARM_INS_VMLADAVAX,
+	ARM_INS_VMLADAV,
+	ARM_INS_VMLADAVX,
+	ARM_INS_VMLALDAVA,
+	ARM_INS_VMLALDAVAX,
+	ARM_INS_VMLALDAV,
+	ARM_INS_VMLALDAVX,
+	ARM_INS_VMLAS,
+	ARM_INS_VMLA,
+	ARM_INS_VMLSDAVA,
+	ARM_INS_VMLSDAVAX,
+	ARM_INS_VMLSDAV,
+	ARM_INS_VMLSDAVX,
+	ARM_INS_VMLSLDAVA,
+	ARM_INS_VMLSLDAVAX,
+	ARM_INS_VMLSLDAV,
+	ARM_INS_VMLSLDAVX,
+	ARM_INS_VMOVLB,
+	ARM_INS_VMOVLT,
+	ARM_INS_VMOVNB,
+	ARM_INS_VMOVNT,
+	ARM_INS_VMULH,
+	ARM_INS_VMULLB,
+	ARM_INS_VMULLT,
+	ARM_INS_VMUL,
+	ARM_INS_VMVN,
+	ARM_INS_VNEG,
+	ARM_INS_VORN,
+	ARM_INS_VORR,
+	ARM_INS_VPNOT,
+	ARM_INS_VPSEL,
+	ARM_INS_VPST,
+	ARM_INS_VPT,
+	ARM_INS_VQABS,
+	ARM_INS_VQADD,
+	ARM_INS_VQDMLADHX,
+	ARM_INS_VQDMLADH,
+	ARM_INS_VQDMLAH,
+	ARM_INS_VQDMLASH,
+	ARM_INS_VQDMLSDHX,
+	ARM_INS_VQDMLSDH,
+	ARM_INS_VQDMULH,
+	ARM_INS_VQDMULLB,
+	ARM_INS_VQDMULLT,
+	ARM_INS_VQMOVNB,
+	ARM_INS_VQMOVNT,
+	ARM_INS_VQMOVUNB,
+	ARM_INS_VQMOVUNT,
+	ARM_INS_VQNEG,
+	ARM_INS_VQRDMLADHX,
+	ARM_INS_VQRDMLADH,
+	ARM_INS_VQRDMLAH,
+	ARM_INS_VQRDMLASH,
+	ARM_INS_VQRDMLSDHX,
+	ARM_INS_VQRDMLSDH,
+	ARM_INS_VQRDMULH,
+	ARM_INS_VQRSHL,
+	ARM_INS_VQRSHRNB,
+	ARM_INS_VQRSHRNT,
+	ARM_INS_VQRSHRUNB,
+	ARM_INS_VQRSHRUNT,
+	ARM_INS_VQSHLU,
+	ARM_INS_VQSHL,
+	ARM_INS_VQSHRNB,
+	ARM_INS_VQSHRNT,
+	ARM_INS_VQSHRUNB,
+	ARM_INS_VQSHRUNT,
+	ARM_INS_VQSUB,
+	ARM_INS_VREV16,
+	ARM_INS_VREV32,
+	ARM_INS_VREV64,
+	ARM_INS_VRHADD,
+	ARM_INS_VRINTA,
+	ARM_INS_VRINTM,
+	ARM_INS_VRINTN,
+	ARM_INS_VRINTP,
+	ARM_INS_VRINTX,
+	ARM_INS_VRINTZ,
+	ARM_INS_VRMLALDAVHA,
+	ARM_INS_VRMLALDAVHAX,
+	ARM_INS_VRMLALDAVH,
+	ARM_INS_VRMLALDAVHX,
+	ARM_INS_VRMLSLDAVHA,
+	ARM_INS_VRMLSLDAVHAX,
+	ARM_INS_VRMLSLDAVH,
+	ARM_INS_VRMLSLDAVHX,
+	ARM_INS_VRMULH,
+	ARM_INS_VRSHL,
+	ARM_INS_VRSHRNB,
+	ARM_INS_VRSHRNT,
+	ARM_INS_VRSHR,
+	ARM_INS_VSBC,
+	ARM_INS_VSBCI,
+	ARM_INS_VSHLC,
+	ARM_INS_VSHLLB,
+	ARM_INS_VSHLLT,
+	ARM_INS_VSHL,
+	ARM_INS_VSHRNB,
+	ARM_INS_VSHRNT,
+	ARM_INS_VSHR,
+	ARM_INS_VSLI,
+	ARM_INS_VSRI,
+	ARM_INS_VST20,
+	ARM_INS_VST21,
+	ARM_INS_VST40,
+	ARM_INS_VST41,
+	ARM_INS_VST42,
+	ARM_INS_VST43,
+	ARM_INS_VSTRB,
+	ARM_INS_VSTRD,
+	ARM_INS_VSTRH,
+	ARM_INS_VSTRW,
+	ARM_INS_VSUB,
+	ARM_INS_WLSTP,
 	ARM_INS_MVN,
-	ARM_INS_NEG,
-	ARM_INS_NOP,
-	ARM_INS_ORN,
 	ARM_INS_ORR,
 	ARM_INS_PKHBT,
 	ARM_INS_PKHTB,
-	ARM_INS_PLD,
 	ARM_INS_PLDW,
+	ARM_INS_PLD,
 	ARM_INS_PLI,
-	ARM_INS_POP,
-	ARM_INS_PUSH,
 	ARM_INS_QADD,
 	ARM_INS_QADD16,
 	ARM_INS_QADD8,
@@ -606,22 +1251,18 @@ typedef enum arm_insn {
 	ARM_INS_RFEDB,
 	ARM_INS_RFEIA,
 	ARM_INS_RFEIB,
-	ARM_INS_ROR,
-	ARM_INS_RRX,
 	ARM_INS_RSB,
 	ARM_INS_RSC,
 	ARM_INS_SADD16,
 	ARM_INS_SADD8,
 	ARM_INS_SASX,
+	ARM_INS_SB,
 	ARM_INS_SBC,
 	ARM_INS_SBFX,
 	ARM_INS_SDIV,
 	ARM_INS_SEL,
 	ARM_INS_SETEND,
 	ARM_INS_SETPAN,
-	ARM_INS_SEV,
-	ARM_INS_SEVL,
-	ARM_INS_SG,
 	ARM_INS_SHA1C,
 	ARM_INS_SHA1H,
 	ARM_INS_SHA1M,
@@ -684,10 +1325,10 @@ typedef enum arm_insn {
 	ARM_INS_SSAX,
 	ARM_INS_SSUB16,
 	ARM_INS_SSUB8,
-	ARM_INS_STC,
-	ARM_INS_STC2,
 	ARM_INS_STC2L,
+	ARM_INS_STC2,
 	ARM_INS_STCL,
+	ARM_INS_STC,
 	ARM_INS_STL,
 	ARM_INS_STLB,
 	ARM_INS_STLEX,
@@ -695,13 +1336,11 @@ typedef enum arm_insn {
 	ARM_INS_STLEXD,
 	ARM_INS_STLEXH,
 	ARM_INS_STLH,
-	ARM_INS_STM,
 	ARM_INS_STMDA,
 	ARM_INS_STMDB,
+	ARM_INS_STM,
 	ARM_INS_STMIB,
-	ARM_INS_STR,
 	ARM_INS_STRB,
-	ARM_INS_STRBT,
 	ARM_INS_STRD,
 	ARM_INS_STREX,
 	ARM_INS_STREXB,
@@ -709,10 +1348,7 @@ typedef enum arm_insn {
 	ARM_INS_STREXH,
 	ARM_INS_STRH,
 	ARM_INS_STRHT,
-	ARM_INS_STRT,
 	ARM_INS_SUB,
-	ARM_INS_SUBS,
-	ARM_INS_SUBW,
 	ARM_INS_SVC,
 	ARM_INS_SWP,
 	ARM_INS_SWPB,
@@ -722,16 +1358,10 @@ typedef enum arm_insn {
 	ARM_INS_SXTB,
 	ARM_INS_SXTB16,
 	ARM_INS_SXTH,
-	ARM_INS_TBB,
-	ARM_INS_TBH,
 	ARM_INS_TEQ,
 	ARM_INS_TRAP,
 	ARM_INS_TSB,
 	ARM_INS_TST,
-	ARM_INS_TT,
-	ARM_INS_TTA,
-	ARM_INS_TTAT,
-	ARM_INS_TTT,
 	ARM_INS_UADD16,
 	ARM_INS_UADD8,
 	ARM_INS_UASX,
@@ -766,173 +1396,159 @@ typedef enum arm_insn {
 	ARM_INS_UXTB,
 	ARM_INS_UXTB16,
 	ARM_INS_UXTH,
-	ARM_INS_VABA,
 	ARM_INS_VABAL,
-	ARM_INS_VABD,
+	ARM_INS_VABA,
 	ARM_INS_VABDL,
-	ARM_INS_VABS,
 	ARM_INS_VACGE,
 	ARM_INS_VACGT,
-	ARM_INS_VACLE,
-	ARM_INS_VACLT,
-	ARM_INS_VADD,
 	ARM_INS_VADDHN,
 	ARM_INS_VADDL,
 	ARM_INS_VADDW,
-	ARM_INS_VAND,
-	ARM_INS_VBIC,
+	ARM_INS_VFMAB,
+	ARM_INS_VFMAT,
 	ARM_INS_VBIF,
 	ARM_INS_VBIT,
 	ARM_INS_VBSL,
-	ARM_INS_VCADD,
 	ARM_INS_VCEQ,
 	ARM_INS_VCGE,
 	ARM_INS_VCGT,
 	ARM_INS_VCLE,
-	ARM_INS_VCLS,
 	ARM_INS_VCLT,
-	ARM_INS_VCLZ,
-	ARM_INS_VCMLA,
-	ARM_INS_VCMP,
 	ARM_INS_VCMPE,
 	ARM_INS_VCNT,
-	ARM_INS_VCVT,
-	ARM_INS_VCVTA,
-	ARM_INS_VCVTB,
-	ARM_INS_VCVTM,
-	ARM_INS_VCVTN,
-	ARM_INS_VCVTP,
-	ARM_INS_VCVTR,
-	ARM_INS_VCVTT,
 	ARM_INS_VDIV,
-	ARM_INS_VDUP,
-	ARM_INS_VEOR,
 	ARM_INS_VEXT,
-	ARM_INS_VFMA,
-	ARM_INS_VFMS,
+	ARM_INS_VFMAL,
+	ARM_INS_VFMSL,
 	ARM_INS_VFNMA,
 	ARM_INS_VFNMS,
-	ARM_INS_VHADD,
-	ARM_INS_VHSUB,
 	ARM_INS_VINS,
 	ARM_INS_VJCVT,
-	ARM_INS_VLD1,
-	ARM_INS_VLD2,
-	ARM_INS_VLD3,
-	ARM_INS_VLD4,
 	ARM_INS_VLDMDB,
 	ARM_INS_VLDMIA,
 	ARM_INS_VLDR,
 	ARM_INS_VLLDM,
 	ARM_INS_VLSTM,
-	ARM_INS_VMAX,
-	ARM_INS_VMAXNM,
-	ARM_INS_VMIN,
-	ARM_INS_VMINNM,
-	ARM_INS_VMLA,
 	ARM_INS_VMLAL,
 	ARM_INS_VMLS,
 	ARM_INS_VMLSL,
-	ARM_INS_VMOV,
+	ARM_INS_VMMLA,
+	ARM_INS_VMOVX,
 	ARM_INS_VMOVL,
 	ARM_INS_VMOVN,
-	ARM_INS_VMOVX,
-	ARM_INS_VMRS,
 	ARM_INS_VMSR,
-	ARM_INS_VMUL,
 	ARM_INS_VMULL,
-	ARM_INS_VMVN,
-	ARM_INS_VNEG,
 	ARM_INS_VNMLA,
 	ARM_INS_VNMLS,
 	ARM_INS_VNMUL,
-	ARM_INS_VORN,
-	ARM_INS_VORR,
 	ARM_INS_VPADAL,
-	ARM_INS_VPADD,
 	ARM_INS_VPADDL,
+	ARM_INS_VPADD,
 	ARM_INS_VPMAX,
 	ARM_INS_VPMIN,
-	ARM_INS_VPOP,
-	ARM_INS_VPUSH,
-	ARM_INS_VQABS,
-	ARM_INS_VQADD,
 	ARM_INS_VQDMLAL,
 	ARM_INS_VQDMLSL,
-	ARM_INS_VQDMULH,
 	ARM_INS_VQDMULL,
-	ARM_INS_VQMOVN,
 	ARM_INS_VQMOVUN,
-	ARM_INS_VQNEG,
-	ARM_INS_VQRDMLAH,
+	ARM_INS_VQMOVN,
 	ARM_INS_VQRDMLSH,
-	ARM_INS_VQRDMULH,
-	ARM_INS_VQRSHL,
 	ARM_INS_VQRSHRN,
 	ARM_INS_VQRSHRUN,
-	ARM_INS_VQSHL,
-	ARM_INS_VQSHLU,
 	ARM_INS_VQSHRN,
 	ARM_INS_VQSHRUN,
-	ARM_INS_VQSUB,
 	ARM_INS_VRADDHN,
 	ARM_INS_VRECPE,
 	ARM_INS_VRECPS,
-	ARM_INS_VREV16,
-	ARM_INS_VREV32,
-	ARM_INS_VREV64,
-	ARM_INS_VRHADD,
-	ARM_INS_VRINTA,
-	ARM_INS_VRINTM,
-	ARM_INS_VRINTN,
-	ARM_INS_VRINTP,
 	ARM_INS_VRINTR,
-	ARM_INS_VRINTX,
-	ARM_INS_VRINTZ,
-	ARM_INS_VRSHL,
-	ARM_INS_VRSHR,
 	ARM_INS_VRSHRN,
 	ARM_INS_VRSQRTE,
 	ARM_INS_VRSQRTS,
 	ARM_INS_VRSRA,
 	ARM_INS_VRSUBHN,
+	ARM_INS_VSCCLRM,
 	ARM_INS_VSDOT,
 	ARM_INS_VSELEQ,
 	ARM_INS_VSELGE,
 	ARM_INS_VSELGT,
 	ARM_INS_VSELVS,
-	ARM_INS_VSHL,
 	ARM_INS_VSHLL,
-	ARM_INS_VSHR,
 	ARM_INS_VSHRN,
-	ARM_INS_VSLI,
+	ARM_INS_VSMMLA,
 	ARM_INS_VSQRT,
 	ARM_INS_VSRA,
-	ARM_INS_VSRI,
-	ARM_INS_VST1,
-	ARM_INS_VST2,
-	ARM_INS_VST3,
-	ARM_INS_VST4,
 	ARM_INS_VSTMDB,
 	ARM_INS_VSTMIA,
 	ARM_INS_VSTR,
-	ARM_INS_VSUB,
 	ARM_INS_VSUBHN,
 	ARM_INS_VSUBL,
 	ARM_INS_VSUBW,
+	ARM_INS_VSUDOT,
 	ARM_INS_VSWP,
 	ARM_INS_VTBL,
 	ARM_INS_VTBX,
+	ARM_INS_VCVTR,
 	ARM_INS_VTRN,
 	ARM_INS_VTST,
 	ARM_INS_VUDOT,
+	ARM_INS_VUMMLA,
+	ARM_INS_VUSDOT,
+	ARM_INS_VUSMMLA,
 	ARM_INS_VUZP,
 	ARM_INS_VZIP,
-	ARM_INS_WFE,
-	ARM_INS_WFI,
-	ARM_INS_YIELD,
+	ARM_INS_ADDW,
+	ARM_INS_AUT,
+	ARM_INS_AUTG,
+	ARM_INS_BFL,
+	ARM_INS_BFLX,
+	ARM_INS_BF,
+	ARM_INS_BFCSEL,
+	ARM_INS_BFX,
+	ARM_INS_BTI,
+	ARM_INS_BXAUT,
+	ARM_INS_CLRM,
+	ARM_INS_CSEL,
+	ARM_INS_CSINC,
+	ARM_INS_CSINV,
+	ARM_INS_CSNEG,
+	ARM_INS_DCPS1,
+	ARM_INS_DCPS2,
+	ARM_INS_DCPS3,
+	ARM_INS_DLS,
+	ARM_INS_LE,
+	ARM_INS_ORN,
+	ARM_INS_PAC,
+	ARM_INS_PACBTI,
+	ARM_INS_PACG,
+	ARM_INS_SG,
+	ARM_INS_SUBS,
+	ARM_INS_SUBW,
+	ARM_INS_TBB,
+	ARM_INS_TBH,
+	ARM_INS_TT,
+	ARM_INS_TTA,
+	ARM_INS_TTAT,
+	ARM_INS_TTT,
+	ARM_INS_WLS,
+	ARM_INS_BLXNS,
+	ARM_INS_BXNS,
+	ARM_INS_CBNZ,
+	ARM_INS_CBZ,
+	ARM_INS_POP,
+	ARM_INS_PUSH,
+	ARM_INS___BRKDIV0,
+
+	// clang-format on
+	// generated content <ARMGenCSInsnEnum.inc> end
+
+	// Hard coded alias in LLVM, not defined as alias or instruction.
+	// We give them a unique ID for convenience.
+	ARM_INS_VPOP,
+	ARM_INS_VPUSH,
 
 	ARM_INS_ENDING,	// <-- mark the end of the list of instructions
+
+  // Alias
+  ARM_INS_NOP = ARM_INS_HINT,
 } arm_insn;
 
 /// Group of ARM instructions
@@ -948,38 +1564,69 @@ typedef enum arm_insn_group {
 	ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
 
 	// Architecture-specific groups
-	ARM_GRP_CRYPTO = 128,
-	ARM_GRP_DATABARRIER,
-	ARM_GRP_DIVIDE,
-	ARM_GRP_FPARMV8,
-	ARM_GRP_MULTPRO,
-	ARM_GRP_NEON,
-	ARM_GRP_T2EXTRACTPACK,
-	ARM_GRP_THUMB2DSP,
-	ARM_GRP_TRUSTZONE,
-	ARM_GRP_V4T,
-	ARM_GRP_V5T,
-	ARM_GRP_V5TE,
-	ARM_GRP_V6,
-	ARM_GRP_V6T2,
-	ARM_GRP_V7,
-	ARM_GRP_V8,
-	ARM_GRP_VFP2,
-	ARM_GRP_VFP3,
-	ARM_GRP_VFP4,
-	ARM_GRP_ARM,
-	ARM_GRP_MCLASS,
-	ARM_GRP_NOTMCLASS,
-	ARM_GRP_THUMB,
-	ARM_GRP_THUMB1ONLY,
-	ARM_GRP_THUMB2,
-	ARM_GRP_PREV8,
-	ARM_GRP_FPVMLX,
-	ARM_GRP_MULOPS,
-	ARM_GRP_CRC,
-	ARM_GRP_DPVFP,
-	ARM_GRP_V6M,
-	ARM_GRP_VIRTUALIZATION,
+	// generated content <ARMGenCSFeatureEnum.inc> begin
+	// clang-format off
+
+	ARM_FEATURE_IsARM = 128,
+	ARM_FEATURE_HasV5T,
+	ARM_FEATURE_HasV4T,
+	ARM_FEATURE_HasVFP2,
+	ARM_FEATURE_HasV5TE,
+	ARM_FEATURE_HasV6T2,
+	ARM_FEATURE_HasMVEInt,
+	ARM_FEATURE_HasNEON,
+	ARM_FEATURE_HasFPRegs64,
+	ARM_FEATURE_HasFPRegs,
+	ARM_FEATURE_IsThumb2,
+	ARM_FEATURE_HasV8_1MMainline,
+	ARM_FEATURE_HasLOB,
+	ARM_FEATURE_IsThumb,
+	ARM_FEATURE_HasV8MBaseline,
+	ARM_FEATURE_Has8MSecExt,
+	ARM_FEATURE_HasV8,
+	ARM_FEATURE_HasAES,
+	ARM_FEATURE_HasBF16,
+	ARM_FEATURE_HasCDE,
+	ARM_FEATURE_PreV8,
+	ARM_FEATURE_HasV6K,
+	ARM_FEATURE_HasCRC,
+	ARM_FEATURE_HasV7,
+	ARM_FEATURE_HasDB,
+	ARM_FEATURE_HasVirtualization,
+	ARM_FEATURE_HasVFP3,
+	ARM_FEATURE_HasDPVFP,
+	ARM_FEATURE_HasFullFP16,
+	ARM_FEATURE_HasV6,
+	ARM_FEATURE_HasAcquireRelease,
+	ARM_FEATURE_HasV7Clrex,
+	ARM_FEATURE_HasMVEFloat,
+	ARM_FEATURE_HasFPRegsV8_1M,
+	ARM_FEATURE_HasMP,
+	ARM_FEATURE_HasSB,
+	ARM_FEATURE_HasDivideInARM,
+	ARM_FEATURE_HasV8_1a,
+	ARM_FEATURE_HasSHA2,
+	ARM_FEATURE_HasTrustZone,
+	ARM_FEATURE_UseNaClTrap,
+	ARM_FEATURE_HasV8_4a,
+	ARM_FEATURE_HasV8_3a,
+	ARM_FEATURE_HasFPARMv8,
+	ARM_FEATURE_HasFP16,
+	ARM_FEATURE_HasVFP4,
+	ARM_FEATURE_HasFP16FML,
+	ARM_FEATURE_HasFPRegs16,
+	ARM_FEATURE_HasV8MMainline,
+	ARM_FEATURE_HasDotProd,
+	ARM_FEATURE_HasMatMulInt8,
+	ARM_FEATURE_IsMClass,
+	ARM_FEATURE_HasPACBTI,
+	ARM_FEATURE_IsNotMClass,
+	ARM_FEATURE_HasDSP,
+	ARM_FEATURE_HasDivideInThumb,
+	ARM_FEATURE_HasV6M,
+
+	// clang-format on
+	// generated content <ARMGenCSFeatureEnum.inc> end
 
 	ARM_GRP_ENDING,
 } arm_insn_group;
diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
index d028fb574..40e40783a 100644
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@@ -17,6 +17,7 @@ extern "C" {
 #include <stdio.h>
 #endif
 
+#include "../../cs_operand.h"
 #include "platform.h"
 
 #ifdef _MSC_VER
@@ -216,33 +217,16 @@ typedef enum cs_opt_type {
 /// Runtime option value (associated with option type above)
 typedef enum cs_opt_value {
 	CS_OPT_OFF = 0,  ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
-	CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
-	CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_ATT,   ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)
-	CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix
+	CS_OPT_ON = 1 << 0, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
+	CS_OPT_SYNTAX_DEFAULT = 1 << 1, ///< Default asm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_INTEL = 1 << 2, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_ATT = 1 << 3,   ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_NOREGNAME = 1 << 4, ///< Prints register name with only number (CS_OPT_SYNTAX)
+	CS_OPT_SYNTAX_MASM = 1 << 5, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
+	CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
 } cs_opt_value;
 
-/// Common instruction operand types - to be consistent across all architectures.
-typedef enum cs_op_type {
-	CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
-	CS_OP_REG,	   ///< Register operand.
-	CS_OP_IMM,	   ///< Immediate operand.
-	CS_OP_FP,	   ///< Floating-Point operand.
-	CS_OP_MEM =
-		0x80, ///< Memory operand. Can be ORed with another operand type.
-} cs_op_type;
-
-/// Common instruction operand access types - to be consistent across all architectures.
-/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
-typedef enum cs_ac_type {
-	CS_AC_INVALID = 0,        ///< Uninitialized/invalid access type.
-	CS_AC_READ    = 1 << 0,   ///< Operand read from memory or register.
-	CS_AC_WRITE   = 1 << 1,   ///< Operand write to memory or register.
-} cs_ac_type;
-
 /// Common instruction groups - to be consistent across all architectures.
 typedef enum cs_group_type {
 	CS_GRP_INVALID = 0,  ///< uninitialized/invalid group.
diff --git a/include/capstone/tricore.h b/include/capstone/tricore.h
index 4c9ee0039..e9f2426b1 100644
--- a/include/capstone/tricore.h
+++ b/include/capstone/tricore.h
@@ -12,6 +12,7 @@ extern "C" {
 #include <stdint.h>
 #endif
 
+#include "../../cs_operand.h"
 #include "platform.h"
 
 #ifdef _MSC_VER
diff --git a/suite/MC/ARM/arm-arithmetic-aliases.s.cs b/suite/MC/ARM/arm-arithmetic-aliases.s.cs
index 75139c63f..56a459f78 100644
--- a/suite/MC/ARM/arm-arithmetic-aliases.s.cs
+++ b/suite/MC/ARM/arm-arithmetic-aliases.s.cs
@@ -47,4 +47,4 @@
 0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6
 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3
 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3
-0x7b,0x00,0x8f,0xe2 = add r0, pc, #123
+0x7b,0x00,0x8f,0xe2 = add r0, pc, #0x7b
diff --git a/suite/MC/ARM/arm-branches.s.cs b/suite/MC/ARM/arm-branches.s.cs
new file mode 100644
index 000000000..0b12a6fba
--- /dev/null
+++ b/suite/MC/ARM/arm-branches.s.cs
@@ -0,0 +1,6 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x01,0x00,0x00,0xea = b #4
+0x01,0x00,0x00,0xeb = bl #4
+0x01,0x00,0x00,0x0a = beq #4
+0x00,0x00,0x00,0xfb = blx #2
+0x01,0x00,0x00,0xea = b #4
diff --git a/suite/MC/ARM/arm-memory-instructions.s.cs b/suite/MC/ARM/arm-memory-instructions.s.cs
index 8951802c9..db0e870ed 100644
--- a/suite/MC/ARM/arm-memory-instructions.s.cs
+++ b/suite/MC/ARM/arm-memory-instructions.s.cs
@@ -1,9 +1,9 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
 0x00,0x50,0x97,0xe5 = ldr r5, [r7]
-0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #63]
-0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #4095]!
-0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #30
-0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-30
+0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #0x3f]
+0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #0xfff]!
+0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #0x1e
+0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-0x1e
 0x00,0x90,0x12,0xe4 = ldr r9, [r2], #-0
 0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1]
 0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3]
@@ -12,28 +12,28 @@
 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
 0x02,0x50,0x99,0xe6 = ldr r5, [r9], r2
 0x06,0x40,0x13,0xe6 = ldr r4, [r3], -r6
-0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #15]
-0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #15
+0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #0xf]
+0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #0xf
 0x00,0x30,0xd8,0xe5 = ldrb r3, [r8]
-0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #63]
-0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #4095]!
-0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #22
-0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-19
+0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #0x3f]
+0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #0xfff]!
+0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #0x16
+0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-0x13
 0x05,0x90,0xd8,0xe7 = ldrb r9, [r8, r5]
 0x01,0x10,0x55,0xe7 = ldrb r1, [r5, -r1]
 0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]!
 0x03,0x60,0x79,0xe7 = ldrb r6, [r9, -r3]!
 0x04,0x20,0xd1,0xe6 = ldrb r2, [r1], r4
 0x05,0x80,0x54,0xe6 = ldrb r8, [r4], -r5
-0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #15]
-0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #15
+0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #0xf]
+0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #0xf
 0x04,0x30,0xf1,0xe4 = ldrbt r3, [r1], #4
 0x08,0x20,0x78,0xe4 = ldrbt r2, [r8], #-8
 0x06,0x80,0xf7,0xe6 = ldrbt r8, [r7], r6
-0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #12
+0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #0xc
 0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5]
-0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #15]
-0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #32]!
+0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #0xf]
+0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #0x20]!
 0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8
 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
@@ -44,48 +44,51 @@
 0xdc,0x00,0x08,0xe0 = ldrd r0, r1, [r8], -r12
 0xb0,0x30,0xd4,0xe1 = ldrh r3, [r4]
 0xb4,0x20,0xd7,0xe1 = ldrh r2, [r7, #4]
-0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #64]!
-0xb4,0xc0,0xdd,0xe0 = ldrh ip, [sp], #4
+0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #0x40]!
+0xb4,0xc0,0xdd,0xe0 = ldrh r12, [sp], #4
 0xb4,0x60,0x95,0xe1 = ldrh r6, [r5, r4]
 0xbb,0x30,0xb8,0xe1 = ldrh r3, [r8, r11]!
 0xb1,0x10,0x32,0xe1 = ldrh r1, [r2, -r1]!
 0xb2,0x90,0x97,0xe0 = ldrh r9, [r7], r2
 0xb2,0x40,0x13,0xe0 = ldrh r4, [r3], -r2
-0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #128
-0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-75
+0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #0x80
+0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-0x4b
+0xb0,0x40,0xf3,0xe0 = ldrht r4, [r3], #0
 0xb2,0x90,0xb7,0xe0 = ldrht r9, [r7], r2
 0xb2,0x40,0x33,0xe0 = ldrht r4, [r3], -r2
 0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4]
-0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #17]
-0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #255]!
-0xd9,0xc0,0xdd,0xe0 = ldrsb ip, [sp], #9
+0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #0x11]
+0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #0xff]!
+0xd9,0xc0,0xdd,0xe0 = ldrsb r12, [sp], #0x9
 0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4]
 0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]!
 0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]!
 0xd2,0x90,0x97,0xe0 = ldrsb r9, [r7], r2
 0xd2,0x40,0x13,0xe0 = ldrsb r4, [r3], -r2
 0xd1,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #1
-0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-12
+0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-0xc
+0xd0,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #0
 0xd5,0x80,0xb9,0xe0 = ldrsbt r8, [r9], r5
 0xd4,0x20,0x31,0xe0 = ldrsbt r2, [r1], -r4
 0xf0,0x50,0xd9,0xe1 = ldrsh r5, [r9]
 0xf7,0x40,0xd5,0xe1 = ldrsh r4, [r5, #7]
-0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #55]!
-0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-9
+0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #0x37]!
+0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-0x9
 0xf5,0x30,0x91,0xe1 = ldrsh r3, [r1, r5]
 0xf1,0x40,0xb6,0xe1 = ldrsh r4, [r6, r1]!
 0xf6,0x50,0x33,0xe1 = ldrsh r5, [r3, -r6]!
 0xf8,0x60,0x99,0xe0 = ldrsh r6, [r9], r8
 0xf3,0x70,0x18,0xe0 = ldrsh r7, [r8], -r3
 0xf1,0x50,0xf6,0xe0 = ldrsht r5, [r6], #1
-0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-12
+0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-0xc
+0xf0,0x50,0xf6,0xe0 = ldrsht r5, [r6], #0
 0xf5,0x80,0xb9,0xe0 = ldrsht r8, [r9], r5
 0xf4,0x20,0x31,0xe0 = ldrsht r2, [r1], -r4
 0x00,0x80,0x8c,0xe5 = str r8, [r12]
-0x0c,0x70,0x81,0xe5 = str r7, [r1, #12]
-0x28,0x30,0xa5,0xe5 = str r3, [r5, #40]!
-0xff,0x9f,0x8d,0xe4 = str sb, [sp], #4095
-0x80,0x10,0x07,0xe4 = str r1, [r7], #-128
+0x0c,0x70,0x81,0xe5 = str r7, [r1, #0xc]
+0x28,0x30,0xa5,0xe5 = str r3, [r5, #0x28]!
+0xff,0x9f,0x8d,0xe4 = str r9, [sp], #0xfff
+0x80,0x10,0x07,0xe4 = str r1, [r7], #-0x80
 0x00,0x10,0x00,0xe4 = str r1, [r0], #-0
 0x03,0x90,0x86,0xe7 = str r9, [r6, r3]
 0x02,0x80,0x00,0xe7 = str r8, [r0, -r2]
@@ -94,11 +97,11 @@
 0x09,0x50,0x83,0xe6 = str r5, [r3], r9
 0x05,0x40,0x02,0xe6 = str r4, [r2], -r5
 0x02,0x31,0x04,0xe7 = str r3, [r4, -r2, lsl #2]
-0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #24
+0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #0x18
 0x00,0x90,0xc2,0xe5 = strb r9, [r2]
 0x03,0x70,0xc1,0xe5 = strb r7, [r1, #3]
-0x95,0x61,0xe4,0xe5 = strb r6, [r4, #405]!
-0x48,0x50,0xc7,0xe4 = strb r5, [r7], #72
+0x95,0x61,0xe4,0xe5 = strb r6, [r4, #0x195]!
+0x48,0x50,0xc7,0xe4 = strb r5, [r7], #0x48
 0x01,0x10,0x4d,0xe4 = strb r1, [sp], #-1
 0x09,0x10,0xc2,0xe7 = strb r1, [r2, r9]
 0x08,0x20,0x43,0xe7 = strb r2, [r3, -r8]
@@ -107,32 +110,34 @@
 0x05,0x50,0xc6,0xe6 = strb r5, [r6], r5
 0x04,0x60,0x42,0xe6 = strb r6, [r2], -r4
 0x83,0x72,0x4c,0xe7 = strb r7, [r12, -r3, lsl #5]
-0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #12
-0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #12
-0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-13
+0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #0xc
+0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #0xc
+0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-0xd
 0x05,0x40,0xe9,0xe6 = strbt r4, [r9], r5
 0x82,0x31,0x68,0xe6 = strbt r3, [r8], -r2, lsl #3
-0xf0,0x10,0xc4,0xe1 = strd r1, r2, [r4]
+0xf0,0x20,0xc4,0xe1 = strd r2, r3, [r4]
 0xf1,0x20,0xc6,0xe1 = strd r2, r3, [r6, #1]
-0xf6,0x31,0xe7,0xe1 = strd r3, r4, [r7, #22]!
+0xf6,0x01,0xe7,0xe1 = strd r0, r1, [r7, #0x16]!
 0xf7,0x40,0xc8,0xe0 = strd r4, r5, [r8], #7
-0xf0,0x50,0xcd,0xe0 = strd r5, r6, [sp], #0
+0xf0,0x40,0xcd,0xe0 = strd r4, r5, [sp], #0
 0xf0,0x60,0xce,0xe0 = strd r6, r7, [lr], #0
-0xf0,0x70,0x49,0xe0 = strd r7, r8, [r9], #-0
+0xf0,0xa0,0x49,0xe0 = strd r10, r11, [r9], #-0
 0xf1,0x80,0x84,0xe1 = strd r8, r9, [r4, r1]
-0xf9,0x70,0xa3,0xe1 = strd r7, r8, [r3, r9]!
+0xf9,0x60,0xa3,0xe1 = strd r6, r7, [r3, r9]!
 0xf8,0x60,0x85,0xe0 = strd r6, r7, [r5], r8
-0xfa,0x50,0x0c,0xe0 = strd r5, r6, [r12], -r10
+0xfa,0x40,0x0c,0xe0 = strd r4, r5, [r12], -r10
 0xb0,0x30,0xc4,0xe1 = strh r3, [r4]
 0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4]
-0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #64]!
-0xb4,0xc0,0xcd,0xe0 = strh ip, [sp], #4
+0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #0x40]!
+0xb4,0xc0,0xcd,0xe0 = strh r12, [sp], #4
 0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4]
 0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]!
 0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]!
 0xb2,0x90,0x87,0xe0 = strh r9, [r7], r2
 0xb2,0x40,0x03,0xe0 = strh r4, [r3], -r2
-0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #76
-0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-25
+0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #0x4c
+0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-0x19
 0xb4,0x50,0xa3,0xe0 = strht r5, [r3], r4
 0xb0,0x60,0x28,0xe0 = strht r6, [r8], -r0
+0xd0,0x00,0xcd,0xe1 = ldrd r0, r1, [sp]
+0xf0,0x00,0xcd,0xe1 = strd r0, r1, [sp]
diff --git a/suite/MC/ARM/arm-shift-encoding.s.cs b/suite/MC/ARM/arm-shift-encoding.s.cs
index 130b773aa..13a7cc65a 100644
--- a/suite/MC/ARM/arm-shift-encoding.s.cs
+++ b/suite/MC/ARM/arm-shift-encoding.s.cs
@@ -1,50 +1,50 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
-0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
-0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
+0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #0x20]
+0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #0x10]
 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
-0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16]
-0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
-0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
+0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #0x10]
+0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #0x20]
+0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #0x10]
 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
-0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16]
+0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #0x10]
 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
-0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #32]
-0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #16]
+0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #0x20]
+0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #0x10]
 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
-0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #16]
-0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #32]
-0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #16]
+0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #0x10]
+0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #0x20]
+0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #0x10]
 0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx]
-0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #16]
+0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #0x10]
 0x00,0x00,0x80,0xe7 = str r0, [r0, r0]
-0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #32]
-0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #16]
+0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #0x20]
+0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #0x10]
 0x00,0x00,0x80,0xe7 = str r0, [r0, r0]
-0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #16]
-0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #32]
-0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #16]
+0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #0x10]
+0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #0x20]
+0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #0x10]
 0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx]
-0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #16]
+0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #0x10]
 0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx
 0x05,0x30,0x94,0xe6 = ldr r3, [r4], r5
 0x08,0x60,0x87,0xe6 = str r6, [r7], r8
 0x0b,0x90,0x8a,0xe6 = str r9, [r10], r11
 0x0f,0xd0,0xae,0xe0 = adc sp, lr, pc
-0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #32
-0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #16
+0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #0x20
+0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #0x10
 0x0a,0x30,0xa6,0xe0 = adc r3, r6, r10
-0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #16
-0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #32
-0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #16
+0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #0x10
+0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #0x20
+0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #0x10
 0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx
-0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #16
+0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #0x10
 0x0e,0x00,0x5d,0xe1 = cmp sp, lr
-0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #32
-0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #16
+0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #0x20
+0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #0x10
 0x06,0x00,0x53,0xe1 = cmp r3, r6
-0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #16
-0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #32
-0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #16
+0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #0x10
+0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #0x20
+0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #0x10
 0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx
-0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #16
+0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #0x10
diff --git a/suite/MC/ARM/arm_addrmode2.s.cs b/suite/MC/ARM/arm_addrmode2.s.cs
index 4479254e0..082f798b6 100644
--- a/suite/MC/ARM/arm_addrmode2.s.cs
+++ b/suite/MC/ARM/arm_addrmode2.s.cs
@@ -2,14 +2,18 @@
 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2
 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3
 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4
+0x00,0x10,0xb0,0xe4 = ldrt r1, [r0], #0
 0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2
 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3
 0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4
+0x00,0x10,0xf0,0xe4 = ldrbt r1, [r0], #0
 0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2
 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3
 0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4
+0x00,0x10,0xa0,0xe4 = strt r1, [r0], #0
 0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2
 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3
 0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4
+0x00,0x10,0xe0,0xe4 = strbt r1, [r0], #0
 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]!
diff --git a/suite/MC/ARM/arm_instructions.s.cs b/suite/MC/ARM/arm_instructions.s.cs
index ec8aeaa5b..5602e999e 100644
--- a/suite/MC/ARM/arm_instructions.s.cs
+++ b/suite/MC/ARM/arm_instructions.s.cs
@@ -1,6 +1,4 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
-0x1e,0xff,0x2f,0xe1 = bx lr
-0xa0,0x0d,0xe1,0xf2 = vqdmull.s32 q8, d17, d16
 0x03,0x10,0x02,0xe0 = and r1, r2, r3
 0x03,0x10,0x12,0xe0 = ands r1, r2, r3
 0x03,0x10,0x22,0xe0 = eor r1, r2, r3
@@ -16,7 +14,7 @@
 0x02,0x10,0xe0,0xe1 = mvn r1, r2
 0x02,0x10,0xf0,0xe1 = mvns r1, r2
 0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7
-0x7a,0x00,0x20,0xe1 = bkpt #10
+0x7a,0x00,0x20,0xe1 = bkpt #0xa
 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4
 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4
 0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4
diff --git a/suite/MC/ARM/armv8.1m-pacbti.s.cs b/suite/MC/ARM/armv8.1m-pacbti.s.cs
new file mode 100644
index 000000000..1bde3617d
--- /dev/null
+++ b/suite/MC/ARM/armv8.1m-pacbti.s.cs
@@ -0,0 +1,6 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xaf,0xf3,0x2d,0x80 = aut r12, lr, sp
+0xaf,0xf3,0x0f,0x80 = bti
+0xaf,0xf3,0x0f,0x80 = bti
+0xaf,0xf3,0x1d,0x80 = pac r12, lr, sp
+0xaf,0xf3,0x0d,0x80 = pacbti r12, lr, sp
diff --git a/suite/MC/ARM/armv8.2a-dotprod-a32.s.cs b/suite/MC/ARM/armv8.2a-dotprod-a32.s.cs
new file mode 100644
index 000000000..72eaecd71
--- /dev/null
+++ b/suite/MC/ARM/armv8.2a-dotprod-a32.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x12,0x0d,0x21,0xfc = vudot.u8 d0, d1, d2
+0x02,0x0d,0x21,0xfc = vsdot.s8 d0, d1, d2
+0x58,0x0d,0x22,0xfc = vudot.u8 q0, q1, q4
+0x48,0x0d,0x22,0xfc = vsdot.s8 q0, q1, q4
+0x12,0x0d,0x21,0xfe = vudot.u8 d0, d1, d2[0]
+0x22,0x0d,0x21,0xfe = vsdot.s8 d0, d1, d2[1]
+0x54,0x0d,0x22,0xfe = vudot.u8 q0, q1, d4[0]
+0x64,0x0d,0x22,0xfe = vsdot.s8 q0, q1, d4[1]
diff --git a/suite/MC/ARM/armv8.2a-dotprod-t32.s.cs b/suite/MC/ARM/armv8.2a-dotprod-t32.s.cs
new file mode 100644
index 000000000..2a2879c4d
--- /dev/null
+++ b/suite/MC/ARM/armv8.2a-dotprod-t32.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x21,0xfc,0x12,0x0d = vudot.u8 d0, d1, d2
+0x21,0xfc,0x02,0x0d = vsdot.s8 d0, d1, d2
+0x22,0xfc,0x58,0x0d = vudot.u8 q0, q1, q4
+0x22,0xfc,0x48,0x0d = vsdot.s8 q0, q1, q4
+0x21,0xfe,0x12,0x0d = vudot.u8 d0, d1, d2[0]
+0x21,0xfe,0x22,0x0d = vsdot.s8 d0, d1, d2[1]
+0x22,0xfe,0x54,0x0d = vudot.u8 q0, q1, d4[0]
+0x22,0xfe,0x64,0x0d = vsdot.s8 q0, q1, d4[1]
diff --git a/suite/MC/ARM/armv8.5a-sb.s.cs b/suite/MC/ARM/armv8.5a-sb.s.cs
new file mode 100644
index 000000000..a6a3ceea0
--- /dev/null
+++ b/suite/MC/ARM/armv8.5a-sb.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x70,0xf0,0x7f,0xf5 = sb
diff --git a/suite/MC/ARM/armv8a-fpmul.s.cs b/suite/MC/ARM/armv8a-fpmul.s.cs
new file mode 100644
index 000000000..d2125000c
--- /dev/null
+++ b/suite/MC/ARM/armv8a-fpmul.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x91,0x08,0x20,0xfc = vfmal.f16 d0, s1, s2
+0x91,0x08,0xa0,0xfc = vfmsl.f16 d0, s1, s2
+0x52,0x08,0x21,0xfc = vfmal.f16 q0, d1, d2
+0x52,0x08,0xa1,0xfc = vfmsl.f16 q0, d1, d2
+0x99,0x08,0x00,0xfe = vfmal.f16 d0, s1, s2[1]
+0x99,0x08,0x10,0xfe = vfmsl.f16 d0, s1, s2[1]
+0x7a,0x08,0x01,0xfe = vfmal.f16 q0, d1, d2[3]
+0x7a,0x08,0x11,0xfe = vfmsl.f16 q0, d1, d2[3]
diff --git a/suite/MC/ARM/basic-arm-instructions.s.cs b/suite/MC/ARM/basic-arm-instructions.s.cs
index 9a486d71e..e25f2a90f 100644
--- a/suite/MC/ARM/basic-arm-instructions.s.cs
+++ b/suite/MC/ARM/basic-arm-instructions.s.cs
@@ -1,27 +1,37 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
-0x0f,0x10,0xa2,0xe2 = adc r1, r2, #15
-0xf0,0x10,0xa2,0xe2 = adc r1, r2, #240
-0x0f,0x1c,0xa2,0xe2 = adc r1, r2, #3840
-0x0f,0x1a,0xa2,0xe2 = adc r1, r2, #61440
-0x0f,0x18,0xa2,0xe2 = adc r1, r2, #983040
-0x0f,0x16,0xa2,0xe2 = adc r1, r2, #15728640
-0x0f,0x14,0xa2,0xe2 = adc r1, r2, #251658240
-0x0f,0x12,0xa2,0xe2 = adc r1, r2, #4026531840
-0xff,0x12,0xa2,0xe2 = adc r1, r2, #4026531855
-0x0f,0x1c,0xb2,0xe2 = adcs r1, r2, #3840
-0x0f,0x1c,0xb2,0x02 = adcseq r1, r2, #3840
-0x0f,0x1c,0xa2,0x02 = adceq r1, r2, #3840
+0x0f,0x10,0xa2,0xe2 = adc r1, r2, #0xf
+0x0f,0x10,0xa2,0xe2 = adc r1, r2, #0xf
+0x0f,0x10,0xa2,0xe2 = adc r1, r2, #0xf
+0xff,0x78,0xa8,0xe2 = adc r7, r8, #0xff0000
+0x2a,0x71,0xa8,0xe2 = adc r7, r8, #-0x7ffffff6
+0x2a,0x71,0xa8,0xe2 = adc r7, r8, #-0x7ffffff6
+0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2
+0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2
+0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2
+0x28,0x71,0xa8,0xe2 = adc r7, r8, #0x28, #2
+0xf0,0x10,0xa2,0xe2 = adc r1, r2, #0xf0
+0x0f,0x1c,0xa2,0xe2 = adc r1, r2, #0xf00
+0x0f,0x1a,0xa2,0xe2 = adc r1, r2, #0xf000
+0x0f,0x18,0xa2,0xe2 = adc r1, r2, #0xf0000
+0x0f,0x16,0xa2,0xe2 = adc r1, r2, #0xf00000
+0x0f,0x14,0xa2,0xe2 = adc r1, r2, #0xf000000
+0x0f,0x12,0xa2,0xe2 = adc r1, r2, #-0x10000000
+0xff,0x12,0xa2,0xe2 = adc r1, r2, #-0xffffff1
+0x0f,0x1c,0xb2,0xe2 = adcs r1, r2, #0xf00
+0x28,0x71,0xb8,0xe2 = adcs r7, r8, #0x28, #2
+0x0f,0x1c,0xb2,0x02 = adcseq r1, r2, #0xf00
+0x0f,0x1c,0xa2,0x02 = adceq r1, r2, #0xf00
 0x06,0x40,0xa5,0xe0 = adc r4, r5, r6
 0x86,0x40,0xa5,0xe0 = adc r4, r5, r6, lsl #1
-0x86,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsl #31
+0x86,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsl #0x1f
 0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1
-0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #31
-0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #32
+0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #0x1f
+0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #0x20
 0xc6,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #1
-0xc6,0x4f,0xa5,0xe0 = adc r4, r5, r6, asr #31
-0x46,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #32
+0xc6,0x4f,0xa5,0xe0 = adc r4, r5, r6, asr #0x1f
+0x46,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #0x20
 0xe6,0x40,0xa5,0xe0 = adc r4, r5, r6, ror #1
-0xe6,0x4f,0xa5,0xe0 = adc r4, r5, r6, ror #31
+0xe6,0x4f,0xa5,0xe0 = adc r4, r5, r6, ror #0x1f
 0x18,0x69,0xa7,0xe0 = adc r6, r7, r8, lsl r9
 0x38,0x69,0xa7,0xe0 = adc r6, r7, r8, lsr r9
 0x58,0x69,0xa7,0xe0 = adc r6, r7, r8, asr r9
@@ -29,22 +39,39 @@
 0x66,0x40,0xa5,0xe0 = adc r4, r5, r6, rrx
 0x06,0x50,0xa5,0xe0 = adc r5, r5, r6
 0x85,0x40,0xa4,0xe0 = adc r4, r4, r5, lsl #1
-0x85,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsl #31
+0x85,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsl #0x1f
 0xa5,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #1
-0xa5,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsr #31
-0x25,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #32
+0xa5,0x4f,0xa4,0xe0 = adc r4, r4, r5, lsr #0x1f
+0x25,0x40,0xa4,0xe0 = adc r4, r4, r5, lsr #0x20
 0xc5,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #1
-0xc5,0x4f,0xa4,0xe0 = adc r4, r4, r5, asr #31
-0x45,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #32
+0xc5,0x4f,0xa4,0xe0 = adc r4, r4, r5, asr #0x1f
+0x45,0x40,0xa4,0xe0 = adc r4, r4, r5, asr #0x20
 0xe5,0x40,0xa4,0xe0 = adc r4, r4, r5, ror #1
-0xe5,0x4f,0xa4,0xe0 = adc r4, r4, r5, ror #31
+0xe5,0x4f,0xa4,0xe0 = adc r4, r4, r5, ror #0x1f
 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx
 0x17,0x69,0xa6,0xe0 = adc r6, r6, r7, lsl r9
 0x37,0x69,0xa6,0xe0 = adc r6, r6, r7, lsr r9
 0x57,0x69,0xa6,0xe0 = adc r6, r6, r7, asr r9
 0x77,0x69,0xa6,0xe0 = adc r6, r6, r7, ror r9
 0x65,0x40,0xa4,0xe0 = adc r4, r4, r5, rrx
-0x0f,0x4a,0x85,0xe2 = add r4, r5, #61440
+0x03,0x20,0x8f,0xe2 = add r2, pc, #3
+0x03,0x20,0x4f,0xe2 = sub r2, pc, #3
+0x00,0x10,0x4f,0xe2 = sub r1, pc, #0
+0x12,0x14,0x4f,0xe2 = sub r1, pc, #301989888
+0x06,0x11,0x4f,0xe2 = sub r1, pc, #-2147483647
+0x12,0x14,0x8f,0xe2 = add r1, pc, #301989888
+0x06,0x11,0x8f,0xe2 = add r1, pc, #-2147483647
+0x0f,0x4a,0x85,0xe2 = add r4, r5, #0xf000
+0x0f,0x4a,0x85,0xe2 = add r4, r5, #0xf000
+0x0f,0x4a,0x85,0xe2 = add r4, r5, #0xf000
+0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000
+0xff,0x78,0x88,0xe2 = add r7, r8, #0xff0000
+0x2a,0x71,0x88,0xe2 = add r7, r8, #-0x7ffffff6
+0x2a,0x71,0x88,0xe2 = add r7, r8, #-0x7ffffff6
+0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2
+0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2
+0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2
+0x28,0x71,0x88,0xe2 = add r7, r8, #0x28, #2
 0x06,0x40,0x85,0xe0 = add r4, r5, r6
 0x86,0x42,0x85,0xe0 = add r4, r5, r6, lsl #5
 0xa6,0x42,0x85,0xe0 = add r4, r5, r6, lsr #5
@@ -57,7 +84,17 @@
 0x58,0x69,0x87,0xe0 = add r6, r7, r8, asr r9
 0x78,0x69,0x87,0xe0 = add r6, r7, r8, ror r9
 0x66,0x40,0x85,0xe0 = add r4, r5, r6, rrx
-0x0f,0x5a,0x85,0xe2 = add r5, r5, #61440
+0x0f,0x5a,0x85,0xe2 = add r5, r5, #0xf000
+0x0f,0x5a,0x85,0xe2 = add r5, r5, #0xf000
+0x0f,0x5a,0x85,0xe2 = add r5, r5, #0xf000
+0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000
+0xff,0x78,0x87,0xe2 = add r7, r7, #0xff0000
+0x2a,0x71,0x87,0xe2 = add r7, r7, #-0x7ffffff6
+0x2a,0x71,0x87,0xe2 = add r7, r7, #-0x7ffffff6
+0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2
+0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2
+0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2
+0x28,0x71,0x87,0xe2 = add r7, r7, #0x28, #2
 0x05,0x40,0x84,0xe0 = add r4, r4, r5
 0x85,0x42,0x84,0xe0 = add r4, r4, r5, lsl #5
 0xa5,0x42,0x84,0xe0 = add r4, r4, r5, lsr #5
@@ -70,75 +107,131 @@
 0x77,0x69,0x86,0xe0 = add r6, r6, r7, ror r9
 0x65,0x40,0x84,0xe0 = add r4, r4, r5, rrx
 0x04,0x00,0x40,0xe2 = sub r0, r0, #4
-0x15,0x40,0x45,0xe2 = sub r4, r5, #21
-0x22,0x30,0x81,0xe0 = add r3, r1, r2, lsr #32
-0x42,0x30,0x81,0xe0 = add r3, r1, r2, asr #32
-0x0f,0xa0,0x01,0xe2 = and r10, r1, #15
+0x15,0x40,0x45,0xe2 = sub r4, r5, #0x15
+0x03,0x01,0x8f,0xe2 = add r0, pc, #-1073741824
+0x03,0x01,0x9f,0x02 = addseq r0, pc, #-0x40000000
+0x22,0x30,0x81,0xe0 = add r3, r1, r2, lsr #0x20
+0x42,0x30,0x81,0xe0 = add r3, r1, r2, asr #0x20
+0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000
+0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000
+0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000
+0xff,0x78,0x98,0xe2 = adds r7, r8, #0xff0000
+0x2a,0x71,0x98,0xe2 = adds r7, r8, #-0x7ffffff6
+0x2a,0x71,0x98,0xe2 = adds r7, r8, #-0x7ffffff6
+0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2
+0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2
+0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2
+0x28,0x71,0x98,0xe2 = adds r7, r8, #0x28, #2
+0x0f,0xa0,0x01,0xe2 = and r10, r1, #0xf
+0x0f,0xa0,0x01,0xe2 = and r10, r1, #0xf
+0x0f,0xa0,0x01,0xe2 = and r10, r1, #0xf
+0x0e,0xa0,0xc1,0xe3 = bic r10, r1, #0xe
+0xff,0x78,0x08,0xe2 = and r7, r8, #0xff0000
+0x2a,0x71,0x08,0xe2 = and r7, r8, #-0x7ffffff6
+0x2a,0x71,0x08,0xe2 = and r7, r8, #-0x7ffffff6
+0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2
+0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2
+0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2
+0x28,0x71,0x08,0xe2 = and r7, r8, #0x28, #2
 0x06,0xa0,0x01,0xe0 = and r10, r1, r6
-0x06,0xa5,0x01,0xe0 = and r10, r1, r6, lsl #10
-0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #10
-0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #10
-0x46,0xa5,0x01,0xe0 = and r10, r1, r6, asr #10
-0x66,0xa5,0x01,0xe0 = and r10, r1, r6, ror #10
+0x06,0xa5,0x01,0xe0 = and r10, r1, r6, lsl #0xa
+0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #0xa
+0x26,0xa5,0x01,0xe0 = and r10, r1, r6, lsr #0xa
+0x46,0xa5,0x01,0xe0 = and r10, r1, r6, asr #0xa
+0x66,0xa5,0x01,0xe0 = and r10, r1, r6, ror #0xa
 0x18,0x62,0x07,0xe0 = and r6, r7, r8, lsl r2
 0x38,0x62,0x07,0xe0 = and r6, r7, r8, lsr r2
 0x58,0x62,0x07,0xe0 = and r6, r7, r8, asr r2
 0x78,0x62,0x07,0xe0 = and r6, r7, r8, ror r2
 0x66,0xa0,0x01,0xe0 = and r10, r1, r6, rrx
-0x02,0x21,0xc3,0xe3 = bic r2, r3, #-2147483648
-0x0f,0x10,0x01,0xe2 = and r1, r1, #15
+0x02,0x21,0xc3,0xe3 = bic r2, r3, #-0x80000000
+0x02,0xd1,0xcd,0xe3 = bic sp, sp, #-0x80000000
+0x02,0xf1,0xcf,0xe3 = bic pc, pc, #-0x80000000
+0x0f,0x10,0x01,0xe2 = and r1, r1, #0xf
+0x0f,0x10,0x01,0xe2 = and r1, r1, #0xf
+0x0f,0x10,0x01,0xe2 = and r1, r1, #0xf
+0x0e,0x10,0xc1,0xe3 = bic r1, r1, #0xe
+0xff,0x78,0x07,0xe2 = and r7, r7, #0xff0000
+0x2a,0x71,0x07,0xe2 = and r7, r7, #-0x7ffffff6
+0x2a,0x71,0x07,0xe2 = and r7, r7, #-0x7ffffff6
+0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2
+0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2
+0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2
+0x28,0x71,0x07,0xe2 = and r7, r7, #0x28, #2
 0x01,0xa0,0x0a,0xe0 = and r10, r10, r1
-0x01,0xa5,0x0a,0xe0 = and r10, r10, r1, lsl #10
-0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #10
-0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #10
-0x41,0xa5,0x0a,0xe0 = and r10, r10, r1, asr #10
-0x61,0xa5,0x0a,0xe0 = and r10, r10, r1, ror #10
+0x01,0xa5,0x0a,0xe0 = and r10, r10, r1, lsl #0xa
+0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #0xa
+0x21,0xa5,0x0a,0xe0 = and r10, r10, r1, lsr #0xa
+0x41,0xa5,0x0a,0xe0 = and r10, r10, r1, asr #0xa
+0x61,0xa5,0x0a,0xe0 = and r10, r10, r1, ror #0xa
 0x17,0x62,0x06,0xe0 = and r6, r6, r7, lsl r2
 0x37,0x62,0x06,0xe0 = and r6, r6, r7, lsr r2
 0x57,0x62,0x06,0xe0 = and r6, r6, r7, asr r2
 0x77,0x62,0x06,0xe0 = and r6, r6, r7, ror r2
 0x61,0xa0,0x0a,0xe0 = and r10, r10, r1, rrx
-0x22,0x30,0x01,0xe0 = and r3, r1, r2, lsr #32
-0x42,0x30,0x01,0xe0 = and r3, r1, r2, asr #32
-0x44,0x20,0xa0,0xe1 = asr r2, r4, #32
+0x22,0x30,0x01,0xe0 = and r3, r1, r2, lsr #0x20
+0x42,0x30,0x01,0xe0 = and r3, r1, r2, asr #0x20
+0x44,0x20,0xa0,0xe1 = asr r2, r4, #0x20
 0x44,0x21,0xa0,0xe1 = asr r2, r4, #2
 0x04,0x20,0xa0,0xe1 = mov r2, r4
 0x44,0x41,0xa0,0xe1 = asr r4, r4, #2
-0x9f,0x51,0xd3,0xe7 = bfc r5, #3, #17
-0x9f,0x51,0xd3,0x37 = bfclo r5, #3, #17
-0x92,0x51,0xd3,0xe7 = bfi r5, r2, #3, #17
-0x92,0x51,0xd3,0x17 = bfine r5, r2, #3, #17
-0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #15
+0x9f,0x51,0xd3,0xe7 = bfc r5, #3, #0x11
+0x9f,0x51,0xd3,0x37 = bfclo r5, #3, #0x11
+0x92,0x51,0xd3,0xe7 = bfi r5, r2, #3, #0x11
+0x92,0x51,0xd3,0x17 = bfine r5, r2, #3, #0x11
+0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #0xf
+0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #0xf
+0x0f,0xa0,0xc1,0xe3 = bic r10, r1, #0xf
+0x0e,0xa0,0x01,0xe2 = and r10, r1, #0xe
+0xff,0x78,0xc8,0xe3 = bic r7, r8, #0xff0000
+0x2a,0x71,0xc8,0xe3 = bic r7, r8, #-0x7ffffff6
+0x2a,0x71,0xc8,0xe3 = bic r7, r8, #-0x7ffffff6
+0x28,0x71,0xc8,0xe3 = bic r7, r8, #0x28, #2
+0x28,0x71,0xc8,0xe3 = bic r7, r8, #0x28, #2
+0x28,0x71,0xc8,0xe3 = bic r7, r8, #0x28, #2
 0x06,0xa0,0xc1,0xe1 = bic r10, r1, r6
-0x06,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsl #10
-0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #10
-0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #10
-0x46,0xa5,0xc1,0xe1 = bic r10, r1, r6, asr #10
-0x66,0xa5,0xc1,0xe1 = bic r10, r1, r6, ror #10
+0x06,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsl #0xa
+0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #0xa
+0x26,0xa5,0xc1,0xe1 = bic r10, r1, r6, lsr #0xa
+0x46,0xa5,0xc1,0xe1 = bic r10, r1, r6, asr #0xa
+0x66,0xa5,0xc1,0xe1 = bic r10, r1, r6, ror #0xa
 0x18,0x62,0xc7,0xe1 = bic r6, r7, r8, lsl r2
 0x38,0x62,0xc7,0xe1 = bic r6, r7, r8, lsr r2
 0x58,0x62,0xc7,0xe1 = bic r6, r7, r8, asr r2
 0x78,0x62,0xc7,0xe1 = bic r6, r7, r8, ror r2
 0x66,0xa0,0xc1,0xe1 = bic r10, r1, r6, rrx
-0x0f,0x10,0xc1,0xe3 = bic r1, r1, #15
+0x02,0x21,0x03,0xe2 = and r2, r3, #-0x80000000
+0x02,0xd1,0x0d,0xe2 = and sp, sp, #-0x80000000
+0x02,0xf1,0x0f,0xe2 = and pc, pc, #-0x80000000
+0x0f,0x10,0xc1,0xe3 = bic r1, r1, #0xf
+0x0f,0x10,0xc1,0xe3 = bic r1, r1, #0xf
+0x0f,0x10,0xc1,0xe3 = bic r1, r1, #0xf
+0x0e,0x10,0x01,0xe2 = and r1, r1, #0xe
+0xff,0x78,0xc7,0xe3 = bic r7, r7, #0xff0000
+0x2a,0x71,0xc7,0xe3 = bic r7, r7, #-0x7ffffff6
+0x2a,0x71,0xc7,0xe3 = bic r7, r7, #-0x7ffffff6
+0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2
+0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2
+0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2
+0x28,0x71,0xc7,0xe3 = bic r7, r7, #0x28, #2
 0x01,0xa0,0xca,0xe1 = bic r10, r10, r1
-0x01,0xa5,0xca,0xe1 = bic r10, r10, r1, lsl #10
-0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #10
-0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #10
-0x41,0xa5,0xca,0xe1 = bic r10, r10, r1, asr #10
-0x61,0xa5,0xca,0xe1 = bic r10, r10, r1, ror #10
+0x01,0xa5,0xca,0xe1 = bic r10, r10, r1, lsl #0xa
+0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #0xa
+0x21,0xa5,0xca,0xe1 = bic r10, r10, r1, lsr #0xa
+0x41,0xa5,0xca,0xe1 = bic r10, r10, r1, asr #0xa
+0x61,0xa5,0xca,0xe1 = bic r10, r10, r1, ror #0xa
 0x17,0x62,0xc6,0xe1 = bic r6, r6, r7, lsl r2
 0x37,0x62,0xc6,0xe1 = bic r6, r6, r7, lsr r2
 0x57,0x62,0xc6,0xe1 = bic r6, r6, r7, asr r2
 0x77,0x62,0xc6,0xe1 = bic r6, r6, r7, ror r2
 0x61,0xa0,0xca,0xe1 = bic r10, r10, r1, rrx
-0x22,0x30,0xc1,0xe1 = bic r3, r1, r2, lsr #32
-0x42,0x30,0xc1,0xe1 = bic r3, r1, r2, asr #32
-0x7a,0x00,0x20,0xe1 = bkpt #10
-0x7f,0xff,0x2f,0xe1 = bkpt #65535
-0x27,0x3b,0x6d,0x9b = blls #28634276
-0xa0,0xb0,0x7b,0xfa = blx #32424584
-0x50,0xd8,0x3d,0xfa = blx #16212296
+0x22,0x30,0xc1,0xe1 = bic r3, r1, r2, lsr #0x20
+0x42,0x30,0xc1,0xe1 = bic r3, r1, r2, asr #0x20
+0x7a,0x00,0x20,0xe1 = bkpt #0xa
+0x7f,0xff,0x2f,0xe1 = bkpt #0xffff
+0x27,0x3b,0x6d,0x9b = blls #0x1b4ec9c
+0xa0,0xb0,0x7b,0xfa = blx #0x1eec280
+0x50,0xd8,0x3d,0xfa = blx #0xf76140
 0x32,0xff,0x2f,0xe1 = blx r2
 0x32,0xff,0x2f,0x11 = blxne r2
 0x12,0xff,0x2f,0xe1 = bx r2
@@ -149,28 +242,48 @@
 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4
 0xe0,0x6c,0x0c,0xfe = cdp2 p12, #0, c6, c12, c0, #7
 0x81,0x17,0x11,0x1e = cdpne p7, #1, c1, c1, c1, #4
-0x1f,0xf0,0x7f,0xf5 = clrex 
+0x1f,0xf0,0x7f,0xf5 = clrex
 0x12,0x1f,0x6f,0xe1 = clz r1, r2
 0x12,0x1f,0x6f,0x01 = clzeq r1, r2
-0x0f,0x00,0x71,0xe3 = cmn r1, #15
+0x0f,0x00,0x71,0xe3 = cmn r1, #0xf
+0x0f,0x00,0x71,0xe3 = cmn r1, #0xf
+0x0f,0x00,0x71,0xe3 = cmn r1, #0xf
+0x0f,0x00,0x51,0xe3 = cmp r1, #0xf
+0xff,0x08,0x77,0xe3 = cmn r7, #0xff0000
+0x2a,0x01,0x77,0xe3 = cmn r7, #-0x7ffffff6
+0x2a,0x01,0x77,0xe3 = cmn r7, #-0x7ffffff6
+0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2
+0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2
+0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2
+0x28,0x01,0x77,0xe3 = cmn r7, #0x28, #2
 0x06,0x00,0x71,0xe1 = cmn r1, r6
-0x06,0x05,0x71,0xe1 = cmn r1, r6, lsl #10
-0x26,0x05,0x71,0xe1 = cmn r1, r6, lsr #10
-0x26,0x05,0x7d,0xe1 = cmn sp, r6, lsr #10
-0x46,0x05,0x71,0xe1 = cmn r1, r6, asr #10
-0x66,0x05,0x71,0xe1 = cmn r1, r6, ror #10
+0x06,0x05,0x71,0xe1 = cmn r1, r6, lsl #0xa
+0x26,0x05,0x71,0xe1 = cmn r1, r6, lsr #0xa
+0x26,0x05,0x7d,0xe1 = cmn sp, r6, lsr #0xa
+0x46,0x05,0x71,0xe1 = cmn r1, r6, asr #0xa
+0x66,0x05,0x71,0xe1 = cmn r1, r6, ror #0xa
 0x18,0x02,0x77,0xe1 = cmn r7, r8, lsl r2
 0x38,0x02,0x7d,0xe1 = cmn sp, r8, lsr r2
 0x58,0x02,0x77,0xe1 = cmn r7, r8, asr r2
 0x78,0x02,0x77,0xe1 = cmn r7, r8, ror r2
 0x66,0x00,0x71,0xe1 = cmn r1, r6, rrx
-0x0f,0x00,0x51,0xe3 = cmp r1, #15
+0x0f,0x00,0x51,0xe3 = cmp r1, #0xf
+0x0f,0x00,0x51,0xe3 = cmp r1, #0xf
+0x0f,0x00,0x51,0xe3 = cmp r1, #0xf
+0x0f,0x00,0x71,0xe3 = cmn r1, #0xf
+0xff,0x08,0x57,0xe3 = cmp r7, #0xff0000
+0x2a,0x01,0x57,0xe3 = cmp r7, #-0x7ffffff6
+0x2a,0x01,0x57,0xe3 = cmp r7, #-0x7ffffff6
+0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2
+0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2
+0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2
+0x28,0x01,0x57,0xe3 = cmp r7, #0x28, #2
 0x06,0x00,0x51,0xe1 = cmp r1, r6
-0x06,0x05,0x51,0xe1 = cmp r1, r6, lsl #10
-0x26,0x05,0x51,0xe1 = cmp r1, r6, lsr #10
-0x26,0x05,0x5d,0xe1 = cmp sp, r6, lsr #10
-0x46,0x05,0x51,0xe1 = cmp r1, r6, asr #10
-0x66,0x05,0x51,0xe1 = cmp r1, r6, ror #10
+0x06,0x05,0x51,0xe1 = cmp r1, r6, lsl #0xa
+0x26,0x05,0x51,0xe1 = cmp r1, r6, lsr #0xa
+0x26,0x05,0x5d,0xe1 = cmp sp, r6, lsr #0xa
+0x46,0x05,0x51,0xe1 = cmp r1, r6, asr #0xa
+0x66,0x05,0x51,0xe1 = cmp r1, r6, ror #0xa
 0x18,0x02,0x57,0xe1 = cmp r7, r8, lsl r2
 0x38,0x02,0x5d,0xe1 = cmp sp, r8, lsr r2
 0x58,0x02,0x57,0xe1 = cmp r7, r8, asr r2
@@ -179,11 +292,12 @@
 0x02,0x00,0x70,0xe3 = cmn r0, #2
 0x00,0x00,0x5e,0xe3 = cmp lr, #0
 0xc0,0x01,0x08,0xf1 = cpsie aif
-0x0f,0x00,0x02,0xf1 = cps #15
-0xca,0x00,0x0e,0xf1 = cpsid if, #10
+0xc0,0x01,0x08,0xf1 = cpsie aif
+0x0f,0x00,0x02,0xf1 = cps #0xf
+0xca,0x00,0x0e,0xf1 = cpsid if, #0xa
 0xf0,0xf0,0x20,0xe3 = dbg #0
 0xf5,0xf0,0x20,0xe3 = dbg #5
-0xff,0xf0,0x20,0xe3 = dbg #15
+0xff,0xf0,0x20,0xe3 = dbg #0xf
 0x5f,0xf0,0x7f,0xf5 = dmb sy
 0x5e,0xf0,0x7f,0xf5 = dmb st
 0x5d,0xf0,0x7f,0xf5 = dmb #0xd
@@ -216,6 +330,7 @@
 0x4f,0xf0,0x7f,0xf5 = dsb sy
 0x4e,0xf0,0x7f,0xf5 = dsb st
 0x4d,0xf0,0x7f,0xf5 = dsb #0xd
+0x4c,0xf0,0x7f,0xf5 = dsb #0xc
 0x4b,0xf0,0x7f,0xf5 = dsb ish
 0x4a,0xf0,0x7f,0xf5 = dsb ishst
 0x49,0xf0,0x7f,0xf5 = dsb #0x9
@@ -223,11 +338,11 @@
 0x47,0xf0,0x7f,0xf5 = dsb nsh
 0x46,0xf0,0x7f,0xf5 = dsb nshst
 0x45,0xf0,0x7f,0xf5 = dsb #0x5
-0x44,0xf0,0x7f,0xf5 = dsb #0x4
+0x44,0xf0,0x7f,0xf5 = pssbb
 0x43,0xf0,0x7f,0xf5 = dsb osh
 0x42,0xf0,0x7f,0xf5 = dsb oshst
 0x41,0xf0,0x7f,0xf5 = dsb #0x1
-0x40,0xf0,0x7f,0xf5 = dsb #0x0
+0x40,0xf0,0x7f,0xf5 = ssbb
 0x48,0xf0,0x7f,0xf5 = dsb #0x8
 0x47,0xf0,0x7f,0xf5 = dsb nsh
 0x4f,0xf0,0x7f,0xf5 = dsb sy
@@ -245,7 +360,16 @@
 0x4f,0xf0,0x7f,0xf5 = dsb sy
 0x4f,0xf0,0x7f,0xf5 = dsb sy
 0x42,0xf0,0x7f,0xf5 = dsb oshst
-0x0f,0x4a,0x25,0xe2 = eor r4, r5, #61440
+0x0f,0x4a,0x25,0xe2 = eor r4, r5, #0xf000
+0x0f,0x4a,0x25,0xe2 = eor r4, r5, #0xf000
+0x0f,0x4a,0x25,0xe2 = eor r4, r5, #0xf000
+0xff,0x78,0x28,0xe2 = eor r7, r8, #0xff0000
+0x2a,0x71,0x28,0xe2 = eor r7, r8, #-0x7ffffff6
+0x2a,0x71,0x28,0xe2 = eor r7, r8, #-0x7ffffff6
+0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2
+0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2
+0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2
+0x28,0x71,0x28,0xe2 = eor r7, r8, #0x28, #2
 0x06,0x40,0x25,0xe0 = eor r4, r5, r6
 0x86,0x42,0x25,0xe0 = eor r4, r5, r6, lsl #5
 0xa6,0x42,0x25,0xe0 = eor r4, r5, r6, lsr #5
@@ -257,7 +381,16 @@
 0x58,0x69,0x27,0xe0 = eor r6, r7, r8, asr r9
 0x78,0x69,0x27,0xe0 = eor r6, r7, r8, ror r9
 0x66,0x40,0x25,0xe0 = eor r4, r5, r6, rrx
-0x0f,0x5a,0x25,0xe2 = eor r5, r5, #61440
+0x0f,0x5a,0x25,0xe2 = eor r5, r5, #0xf000
+0x0f,0x5a,0x25,0xe2 = eor r5, r5, #0xf000
+0x0f,0x5a,0x25,0xe2 = eor r5, r5, #0xf000
+0xff,0x78,0x27,0xe2 = eor r7, r7, #0xff0000
+0x2a,0x71,0x27,0xe2 = eor r7, r7, #-0x7ffffff6
+0x2a,0x71,0x27,0xe2 = eor r7, r7, #-0x7ffffff6
+0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2
+0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2
+0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2
+0x28,0x71,0x27,0xe2 = eor r7, r7, #0x28, #2
 0x05,0x40,0x24,0xe0 = eor r4, r4, r5
 0x85,0x42,0x24,0xe0 = eor r4, r4, r5, lsl #5
 0xa5,0x42,0x24,0xe0 = eor r4, r4, r5, lsr #5
@@ -269,48 +402,48 @@
 0x57,0x69,0x26,0xe0 = eor r6, r6, r7, asr r9
 0x77,0x69,0x26,0xe0 = eor r6, r6, r7, ror r9
 0x65,0x40,0x24,0xe0 = eor r4, r4, r5, rrx
-0x22,0x30,0x21,0xe0 = eor r3, r1, r2, lsr #32
-0x42,0x30,0x21,0xe0 = eor r3, r1, r2, asr #32
+0x22,0x30,0x21,0xe0 = eor r3, r1, r2, lsr #0x20
+0x42,0x30,0x21,0xe0 = eor r3, r1, r2, asr #0x20
 0x6f,0xf0,0x7f,0xf5 = isb sy
 0x6f,0xf0,0x7f,0xf5 = isb sy
 0x6f,0xf0,0x7f,0xf5 = isb sy
 0x61,0xf0,0x7f,0xf5 = isb #0x1
 0x01,0x80,0x91,0xfd = ldc2 p0, c8, [r1, #4]
 0x00,0x71,0x92,0xfd = ldc2 p1, c7, [r2]
-0x38,0x62,0x13,0xfd = ldc2 p2, c6, [r3, #-224]
-0x1e,0x53,0x34,0xfd = ldc2 p3, c5, [r4, #-120]!
-0x04,0x44,0xb5,0xfc = ldc2 p4, c4, [r5], #16
-0x12,0x35,0x36,0xfc = ldc2 p5, c3, [r6], #-72
+0x38,0x62,0x13,0xfd = ldc2 p2, c6, [r3, #-0xe0]
+0x1e,0x53,0x34,0xfd = ldc2 p3, c5, [r4, #-0x78]!
+0x04,0x44,0xb5,0xfc = ldc2 p4, c4, [r5], #0x10
+0x12,0x35,0x36,0xfc = ldc2 p5, c3, [r6], #-0x48
 0x01,0x26,0xd7,0xfd = ldc2l p6, c2, [r7, #4]
 0x00,0x17,0xd8,0xfd = ldc2l p7, c1, [r8]
-0x38,0x08,0x59,0xfd = ldc2l p8, c0, [r9, #-224]
-0x1e,0x19,0x7a,0xfd = ldc2l p9, c1, [r10, #-120]!
-0x04,0x20,0xfb,0xfc = ldc2l p0, c2, [r11], #16
-0x12,0x31,0x7c,0xfc = ldc2l p1, c3, [r12], #-72
+0x38,0x08,0x59,0xfd = ldc2l p8, c0, [r9, #-0xe0]
+0x1e,0x19,0x7a,0xfd = ldc2l p9, c1, [r10, #-0x78]!
+0x04,0x20,0xfb,0xfc = ldc2l p0, c2, [r11], #0x10
+0x12,0x31,0x7c,0xfc = ldc2l p1, c3, [r12], #-0x48
 0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4]
 0x00,0x5d,0x91,0xed = ldc p13, c5, [r1]
-0x38,0x6e,0x12,0xed = ldc p14, c6, [r2, #-224]
-0x1e,0x7f,0x33,0xed = ldc p15, c7, [r3, #-120]!
-0x04,0x85,0xb4,0xec = ldc p5, c8, [r4], #16
-0x12,0x94,0x35,0xec = ldc p4, c9, [r5], #-72
+0x38,0x6e,0x12,0xed = ldc p14, c6, [r2, #-0xe0]
+0x1e,0x7f,0x33,0xed = ldc p15, c7, [r3, #-0x78]!
+0x04,0x85,0xb4,0xec = ldc p5, c8, [r4], #0x10
+0x12,0x94,0x35,0xec = ldc p4, c9, [r5], #-0x48
 0x01,0xa3,0xd6,0xed = ldcl p3, c10, [r6, #4]
 0x00,0xb2,0xd7,0xed = ldcl p2, c11, [r7]
-0x38,0xc1,0x58,0xed = ldcl p1, c12, [r8, #-224]
-0x1e,0xd0,0x79,0xed = ldcl p0, c13, [r9, #-120]!
-0x04,0xe6,0xfa,0xec = ldcl p6, c14, [r10], #16
-0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-72
+0x38,0xc1,0x58,0xed = ldcl p1, c12, [r8, #-0xe0]
+0x1e,0xd0,0x79,0xed = ldcl p0, c13, [r9, #-0x78]!
+0x04,0xe6,0xfa,0xec = ldcl p6, c14, [r10], #0x10
+0x12,0xf7,0x7b,0xec = ldcl p7, c15, [r11], #-0x48
 0x01,0x4c,0x90,0x3d = ldclo p12, c4, [r0, #4]
 0x00,0x5d,0x91,0x8d = ldchi p13, c5, [r1]
-0x38,0x6e,0x12,0x2d = ldchs p14, c6, [r2, #-224]
-0x1e,0x7f,0x33,0x3d = ldclo p15, c7, [r3, #-120]!
-0x04,0x85,0xb4,0x0c = ldceq p5, c8, [r4], #16
-0x12,0x94,0x35,0xcc = ldcgt p4, c9, [r5], #-72
+0x38,0x6e,0x12,0x2d = ldchs p14, c6, [r2, #-0xe0]
+0x1e,0x7f,0x33,0x3d = ldclo p15, c7, [r3, #-0x78]!
+0x04,0x85,0xb4,0x0c = ldceq p5, c8, [r4], #0x10
+0x12,0x94,0x35,0xcc = ldcgt p4, c9, [r5], #-0x48
 0x01,0xa3,0xd6,0xbd = ldcllt p3, c10, [r6, #4]
 0x00,0xb2,0xd7,0xad = ldclge p2, c11, [r7]
-0x38,0xc1,0x58,0xdd = ldclle p1, c12, [r8, #-224]
-0x1e,0xd0,0x79,0x1d = ldclne p0, c13, [r9, #-120]!
-0x04,0xe6,0xfa,0x0c = ldcleq p6, c14, [r10], #16
-0x12,0xf7,0x7b,0x8c = ldclhi p7, c15, [r11], #-72
+0x38,0xc1,0x58,0xdd = ldclle p1, c12, [r8, #-0xe0]
+0x1e,0xd0,0x79,0x1d = ldclne p0, c13, [r9, #-0x78]!
+0x04,0xe6,0xfa,0x0c = ldcleq p6, c14, [r10], #0x10
+0x12,0xf7,0x7b,0x8c = ldclhi p7, c15, [r11], #-0x48
 0x19,0x82,0x91,0xfc = ldc2 p2, c8, [r1], {25}
 0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp}
 0x7a,0x20,0x92,0xe8 = ldm r2, {r1, r3, r4, r5, r6, sp}
@@ -330,20 +463,26 @@
 0x9f,0x6f,0xb8,0xe1 = ldrexd r6, r7, [r8]
 0xb0,0x80,0x7b,0x80 = ldrhthi r8, [r11], #-0
 0xb0,0x80,0xfb,0x80 = ldrhthi r8, [r11], #0
-0x84,0x2f,0xa0,0xe1 = lsl r2, r4, #31
+0x84,0x2f,0xa0,0xe1 = lsl r2, r4, #0x1f
 0x84,0x20,0xa0,0xe1 = lsl r2, r4, #1
 0x04,0x20,0xa0,0xe1 = mov r2, r4
 0x84,0x40,0xa0,0xe1 = lsl r4, r4, #1
-0x24,0x20,0xa0,0xe1 = lsr r2, r4, #32
+0x24,0x20,0xa0,0xe1 = lsr r2, r4, #0x20
 0x24,0x21,0xa0,0xe1 = lsr r2, r4, #2
 0x04,0x20,0xa0,0xe1 = mov r2, r4
 0x24,0x41,0xa0,0xe1 = lsr r4, r4, #2
 0x91,0x57,0x21,0xee = mcr p7, #1, r5, c1, c1, #4
 0x91,0x57,0x21,0xfe = mcr2 p7, #1, r5, c1, c1, #4
+0x91,0x57,0x21,0xee = mcr p7, #1, r5, c1, c1, #4
+0x91,0x57,0x21,0xfe = mcr2 p7, #1, r5, c1, c1, #4
 0x91,0x57,0x21,0x9e = mcrls p7, #1, r5, c1, c1, #4
-0xf1,0x57,0x44,0xec = mcrr p7, #15, r5, r4, c1
-0xf1,0x57,0x44,0xfc = mcrr2 p7, #15, r5, r4, c1
-0xf1,0x57,0x44,0xcc = mcrrgt p7, #15, r5, r4, c1
+0x91,0x57,0x21,0x9e = mcrls p7, #1, r5, c1, c1, #4
+0xf1,0x57,0x44,0xec = mcrr p7, #0xf, r5, r4, c1
+0xf1,0x57,0x44,0xfc = mcrr2 p7, #0xf, r5, r4, c1
+0xf1,0x57,0x44,0xec = mcrr p7, #0xf, r5, r4, c1
+0xf1,0x57,0x44,0xfc = mcrr2 p7, #0xf, r5, r4, c1
+0xf1,0x57,0x44,0xcc = mcrrgt p7, #0xf, r5, r4, c1
+0xf1,0x57,0x44,0xcc = mcrrgt p7, #0xf, r5, r4, c1
 0x92,0x43,0x21,0xe0 = mla r1, r2, r3, r4
 0x92,0x43,0x31,0xe0 = mlas r1, r2, r3, r4
 0x92,0x43,0x21,0x10 = mlane r1, r2, r3, r4
@@ -351,13 +490,28 @@
 0x95,0x36,0x62,0xe0 = mls r2, r5, r6, r3
 0x95,0x36,0x62,0x10 = mlsne r2, r5, r6, r3
 0x07,0x30,0xa0,0xe3 = mov r3, #7
-0xff,0x4e,0xa0,0xe3 = mov r4, #4080
-0xff,0x58,0xa0,0xe3 = mov r5, #16711680
-0xff,0x6f,0x0f,0xe3 = movw r6, #65535
-0xff,0x9f,0x0f,0xe3 = movw r9, #65535
+0x07,0x30,0xa0,0xe3 = mov r3, #7
+0x07,0x30,0xa0,0xe3 = mov r3, #7
+0x06,0x30,0xe0,0xe3 = mvn r3, #6
+0xff,0x4e,0xa0,0xe3 = mov r4, #0xff0
+0xff,0x58,0xa0,0xe3 = mov r5, #0xff0000
+0x2a,0x70,0xa0,0xe3 = mov r7, #0x2a
+0x2a,0x75,0xa0,0xe3 = mov r7, #0xa800000
+0xff,0x78,0xa0,0xe3 = mov r7, #0xff0000
+0x2a,0x71,0xa0,0xe3 = mov r7, #-0x7ffffff6
+0x2a,0x71,0xa0,0xe3 = mov r7, #-0x7ffffff6
+0x2a,0xf1,0xa0,0xe3 = mov pc, #0x8000000a
+0x00,0x71,0xa0,0xe3 = mov r7, #0, #2
+0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2
+0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2
+0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2
+0x28,0x71,0xa0,0xe3 = mov r7, #0x28, #2
+0x2a,0x7f,0xa0,0xe3 = mov r7, #0x2a, #0x1e
+0xff,0x6f,0x0f,0xe3 = movw r6, #0xffff
+0xff,0x9f,0x0f,0xe3 = movw r9, #0xffff
 0x07,0x30,0xb0,0xe3 = movs r3, #7
-0xff,0x4e,0xa0,0x03 = moveq r4, #4080
-0xff,0x58,0xb0,0x03 = movseq r5, #16711680
+0xff,0x4e,0xa0,0x03 = moveq r4, #0xff0
+0xff,0x58,0xb0,0x03 = movseq r5, #0xff0000
 0x03,0x20,0xa0,0xe1 = mov r2, r3
 0x03,0x20,0xb0,0xe1 = movs r2, r3
 0x03,0x20,0xa0,0x01 = moveq r2, r3
@@ -371,75 +525,112 @@
 0x08,0xc0,0xa0,0xe1 = mov r12, r8
 0x03,0x20,0xa0,0xe1 = mov r2, r3
 0x07,0x30,0x40,0xe3 = movt r3, #7
-0xff,0x6f,0x4f,0xe3 = movt r6, #65535
-0xf0,0x4f,0x40,0x03 = movteq r4, #4080
+0xff,0x6f,0x4f,0xe3 = movt r6, #0xffff
+0xf0,0x4f,0x40,0x03 = movteq r4, #0xff0
+0x92,0x1e,0x11,0xee = mrc p14, #0, r1, c1, c2, #4
+0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6
+0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4
+0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1
 0x92,0x1e,0x11,0xee = mrc p14, #0, r1, c1, c2, #4
 0xd6,0xff,0xff,0xee = mrc p15, #7, apsr_nzcv, c15, c6, #6
 0x92,0x1e,0x11,0xfe = mrc2 p14, #0, r1, c1, c2, #4
 0x30,0xf9,0xff,0xfe = mrc2 p9, #7, apsr_nzcv, c15, c0, #1
 0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6
+0xd6,0xff,0xff,0x0e = mrceq p15, #7, apsr_nzcv, c15, c6, #6
 0x11,0x57,0x54,0xec = mrrc p7, #1, r5, r4, c1
 0x11,0x57,0x54,0xfc = mrrc2 p7, #1, r5, r4, c1
+0x11,0x57,0x54,0xec = mrrc p7, #1, r5, r4, c1
+0x11,0x57,0x54,0xfc = mrrc2 p7, #1, r5, r4, c1
+0x11,0x57,0x54,0x3c = mrrclo p7, #1, r5, r4, c1
 0x11,0x57,0x54,0x3c = mrrclo p7, #1, r5, r4, c1
 0x00,0x80,0x0f,0xe1 = mrs r8, apsr
 0x00,0x80,0x0f,0xe1 = mrs r8, apsr
 0x00,0x80,0x4f,0xe1 = mrs r8, spsr
-0x05,0xf0,0x28,0xe3 = msr apsr_nzcvq, #5
-0x05,0xf0,0x24,0xe3 = msr apsr_g, #5
-0x05,0xf0,0x28,0xe3 = msr apsr_nzcvq, #5
-0x05,0xf0,0x28,0xe3 = msr apsr_nzcvq, #5
-0x05,0xf0,0x2c,0xe3 = msr apsr_nzcvqg, #5
-0x05,0xf0,0x29,0xe3 = msr cpsr_fc, #5
-0x05,0xf0,0x21,0xe3 = msr cpsr_c, #5
-0x05,0xf0,0x22,0xe3 = msr cpsr_x, #5
-0x05,0xf0,0x29,0xe3 = msr cpsr_fc, #5
-0x05,0xf0,0x29,0xe3 = msr cpsr_fc, #5
-0x05,0xf0,0x2e,0xe3 = msr cpsr_fsx, #5
-0x05,0xf0,0x69,0xe3 = msr spsr_fc, #5
-0x05,0xf0,0x6f,0xe3 = msr spsr_fsxc, #5
-0x05,0xf0,0x2f,0xe3 = msr cpsr_fsxc, #5
-0x00,0xf0,0x28,0xe1 = msr apsr_nzcvq, r0
-0x00,0xf0,0x24,0xe1 = msr apsr_g, r0
-0x00,0xf0,0x28,0xe1 = msr apsr_nzcvq, r0
-0x00,0xf0,0x28,0xe1 = msr apsr_nzcvq, r0
-0x00,0xf0,0x2c,0xe1 = msr apsr_nzcvqg, r0
-0x00,0xf0,0x29,0xe1 = msr cpsr_fc, r0
-0x00,0xf0,0x21,0xe1 = msr cpsr_c, r0
-0x00,0xf0,0x22,0xe1 = msr cpsr_x, r0
-0x00,0xf0,0x29,0xe1 = msr cpsr_fc, r0
-0x00,0xf0,0x29,0xe1 = msr cpsr_fc, r0
-0x00,0xf0,0x2e,0xe1 = msr cpsr_fsx, r0
-0x00,0xf0,0x69,0xe1 = msr spsr_fc, r0
-0x00,0xf0,0x6f,0xe1 = msr spsr_fsxc, r0
-0x00,0xf0,0x2f,0xe1 = msr cpsr_fsxc, r0
+0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
+0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
+0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
+0x05,0xf0,0x24,0xe3 = msr APSR_g, #5
+0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
+0x05,0xf0,0x28,0xe3 = msr APSR_nzcvq, #5
+0x05,0xf0,0x2c,0xe3 = msr APSR_nzcvqg, #5
+0x05,0xf0,0x29,0xe3 = msr CPSR_fc, #5
+0x05,0xf0,0x21,0xe3 = msr CPSR_c, #5
+0x05,0xf0,0x22,0xe3 = msr CPSR_x, #5
+0x05,0xf0,0x29,0xe3 = msr CPSR_fc, #5
+0x05,0xf0,0x29,0xe3 = msr CPSR_fc, #5
+0x05,0xf0,0x2e,0xe3 = msr CPSR_fsx, #5
+0x05,0xf0,0x69,0xe3 = msr SPSR_fc, #5
+0x05,0xf0,0x6f,0xe3 = msr SPSR_fsxc, #5
+0x05,0xf0,0x2f,0xe3 = msr CPSR_fsxc, #5
+0xff,0xf8,0x2c,0xe3 = msr APSR_nzcvqg, #0xff0000
+0x2a,0xf1,0x28,0xe3 = msr APSR_nzcvq, #0x8000000a
+0x2a,0xf1,0x2c,0xe3 = msr APSR_nzcvqg, #0x8000000a
+0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2
+0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2
+0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2
+0x28,0xf1,0x6f,0xe3 = msr SPSR_fsxc, #0x28, #2
+0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0
+0x00,0xf0,0x24,0xe1 = msr APSR_g, r0
+0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0
+0x00,0xf0,0x28,0xe1 = msr APSR_nzcvq, r0
+0x00,0xf0,0x2c,0xe1 = msr APSR_nzcvqg, r0
+0x00,0xf0,0x29,0xe1 = msr CPSR_fc, r0
+0x00,0xf0,0x21,0xe1 = msr CPSR_c, r0
+0x00,0xf0,0x22,0xe1 = msr CPSR_x, r0
+0x00,0xf0,0x29,0xe1 = msr CPSR_fc, r0
+0x00,0xf0,0x29,0xe1 = msr CPSR_fc, r0
+0x00,0xf0,0x2e,0xe1 = msr CPSR_fsx, r0
+0x00,0xf0,0x69,0xe1 = msr SPSR_fc, r0
+0x00,0xf0,0x6f,0xe1 = msr SPSR_fsxc, r0
+0x00,0xf0,0x2f,0xe1 = msr CPSR_fsxc, r0
 0x96,0x07,0x05,0xe0 = mul r5, r6, r7
 0x96,0x07,0x15,0xe0 = muls r5, r6, r7
 0x96,0x07,0x05,0xc0 = mulgt r5, r6, r7
 0x96,0x07,0x15,0xd0 = mulsle r5, r6, r7
 0x07,0x30,0xe0,0xe3 = mvn r3, #7
-0xff,0x4e,0xe0,0xe3 = mvn r4, #4080
-0xff,0x58,0xe0,0xe3 = mvn r5, #16711680
+0x07,0x30,0xe0,0xe3 = mvn r3, #7
+0x07,0x30,0xe0,0xe3 = mvn r3, #7
+0x06,0x30,0xa0,0xe3 = mov r3, #6
+0xff,0x70,0xe0,0xe3 = mvn r7, #0xff
+0xff,0x4e,0xe0,0xe3 = mvn r4, #0xff0
+0xff,0x58,0xe0,0xe3 = mvn r5, #0xff0000
+0xff,0x78,0xe0,0xe3 = mvn r7, #0xff0000
+0x2a,0x71,0xe0,0xe3 = mvn r7, #-0x7ffffff6
+0x2a,0x71,0xe0,0xe3 = mvn r7, #-0x7ffffff6
+0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2
+0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2
+0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2
+0x28,0x71,0xe0,0xe3 = mvn r7, #0x28, #2
 0x07,0x30,0xf0,0xe3 = mvns r3, #7
-0xff,0x4e,0xe0,0x03 = mvneq r4, #4080
-0xff,0x58,0xf0,0x03 = mvnseq r5, #16711680
+0xff,0x4e,0xe0,0x03 = mvneq r4, #0xff0
+0xff,0x58,0xf0,0x03 = mvnseq r5, #0xff0000
 0x03,0x20,0xe0,0xe1 = mvn r2, r3
 0x03,0x20,0xf0,0xe1 = mvns r2, r3
-0x86,0x59,0xe0,0xe1 = mvn r5, r6, lsl #19
-0xa6,0x54,0xe0,0xe1 = mvn r5, r6, lsr #9
+0x86,0x59,0xe0,0xe1 = mvn r5, r6, lsl #0x13
+0xa6,0x54,0xe0,0xe1 = mvn r5, r6, lsr #0x9
 0x46,0x52,0xe0,0xe1 = mvn r5, r6, asr #4
 0x66,0x53,0xe0,0xe1 = mvn r5, r6, ror #6
 0x66,0x50,0xe0,0xe1 = mvn r5, r6, rrx
 0x03,0x20,0xe0,0x01 = mvneq r2, r3
-0x03,0x25,0xf0,0x01 = mvnseq r2, r3, lsl #10
+0x03,0x25,0xf0,0x01 = mvnseq r2, r3, lsl #0xa
 0x16,0x57,0xe0,0xe1 = mvn r5, r6, lsl r7
 0x36,0x57,0xf0,0xe1 = mvns r5, r6, lsr r7
 0x56,0x57,0xe0,0xc1 = mvngt r5, r6, asr r7
 0x76,0x57,0xf0,0xb1 = mvnslt r5, r6, ror r7
 0x00,0x50,0x68,0xe2 = rsb r5, r8, #0
-0x00,0xf0,0x20,0xe3 = nop 
-0x00,0xf0,0x20,0xe3 = nop 
-0x00,0xf0,0x20,0xc3 = nopgt 
-0x0f,0x4a,0x85,0xe3 = orr r4, r5, #61440
+0x00,0xf0,0x20,0xe3 = nop
+0x00,0xf0,0x20,0xe3 = nop
+0x00,0xf0,0x20,0xc3 = nopgt
+0x0f,0x4a,0x85,0xe3 = orr r4, r5, #0xf000
+0x0f,0x4a,0x85,0xe3 = orr r4, r5, #0xf000
+0x0f,0x4a,0x85,0xe3 = orr r4, r5, #0xf000
+0xff,0x78,0x88,0xe3 = orr r7, r8, #0xff0000
+0x2a,0x71,0x88,0xe3 = orr r7, r8, #-0x7ffffff6
+0x2a,0x71,0x88,0xe3 = orr r7, r8, #-0x7ffffff6
+0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2
+0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2
+0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2
+0x28,0x71,0x88,0xe3 = orr r7, r8, #0x28, #2
 0x06,0x40,0x85,0xe1 = orr r4, r5, r6
 0x86,0x42,0x85,0xe1 = orr r4, r5, r6, lsl #5
 0xa6,0x42,0x85,0xe1 = orr r4, r5, r6, lsr #5
@@ -451,7 +642,16 @@
 0x58,0x69,0x87,0xe1 = orr r6, r7, r8, asr r9
 0x78,0x69,0x87,0xe1 = orr r6, r7, r8, ror r9
 0x66,0x40,0x85,0xe1 = orr r4, r5, r6, rrx
-0x0f,0x5a,0x85,0xe3 = orr r5, r5, #61440
+0x0f,0x5a,0x85,0xe3 = orr r5, r5, #0xf000
+0x0f,0x5a,0x85,0xe3 = orr r5, r5, #0xf000
+0x0f,0x5a,0x85,0xe3 = orr r5, r5, #0xf000
+0xff,0x78,0x87,0xe3 = orr r7, r7, #0xff0000
+0x2a,0x71,0x87,0xe3 = orr r7, r7, #-0x7ffffff6
+0x2a,0x71,0x87,0xe3 = orr r7, r7, #-0x7ffffff6
+0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2
+0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2
+0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2
+0x28,0x71,0x87,0xe3 = orr r7, r7, #0x28, #2
 0x05,0x40,0x84,0xe1 = orr r4, r4, r5
 0x85,0x42,0x84,0xe1 = orr r4, r4, r5, lsl #5
 0xa5,0x42,0x84,0xe1 = orr r4, r4, r5, lsr #5
@@ -463,28 +663,28 @@
 0x57,0x69,0x86,0xe1 = orr r6, r6, r7, asr r9
 0x77,0x69,0x86,0xe1 = orr r6, r6, r7, ror r9
 0x65,0x40,0x84,0xe1 = orr r4, r4, r5, rrx
-0x0f,0x4a,0x95,0x03 = orrseq r4, r5, #61440
+0x0f,0x4a,0x95,0x03 = orrseq r4, r5, #0xf000
 0x06,0x40,0x85,0x11 = orrne r4, r5, r6
 0x86,0x42,0x95,0x01 = orrseq r4, r5, r6, lsl #5
 0x78,0x69,0x87,0x31 = orrlo r6, r7, r8, ror r9
 0x66,0x40,0x95,0x81 = orrshi r4, r5, r6, rrx
-0x0f,0x5a,0x85,0x23 = orrhs r5, r5, #61440
+0x0f,0x5a,0x85,0x23 = orrhs r5, r5, #0xf000
 0x05,0x40,0x94,0x01 = orrseq r4, r4, r5
 0x57,0x69,0x86,0x11 = orrne r6, r6, r7, asr r9
 0x77,0x69,0x96,0xb1 = orrslt r6, r6, r7, ror r9
 0x65,0x40,0x94,0xc1 = orrsgt r4, r4, r5, rrx
-0x22,0x30,0x81,0xe1 = orr r3, r1, r2, lsr #32
-0x42,0x30,0x81,0xe1 = orr r3, r1, r2, asr #32
+0x22,0x30,0x81,0xe1 = orr r3, r1, r2, lsr #0x20
+0x42,0x30,0x81,0xe1 = orr r3, r1, r2, asr #0x20
 0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3
-0x93,0x2f,0x82,0xe6 = pkhbt r2, r2, r3, lsl #31
+0x93,0x2f,0x82,0xe6 = pkhbt r2, r2, r3, lsl #0x1f
 0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3
-0x93,0x27,0x82,0xe6 = pkhbt r2, r2, r3, lsl #15
-0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3
-0xd3,0x2f,0x82,0xe6 = pkhtb r2, r2, r3, asr #31
-0xd3,0x27,0x82,0xe6 = pkhtb r2, r2, r3, asr #15
-// 0x04,0x70,0x9d,0xe4 = pop {r7}
+0x93,0x27,0x82,0xe6 = pkhbt r2, r2, r3, lsl #0xf
+0x12,0x20,0x83,0xe6 = pkhbt r2, r3, r2
+0xd3,0x2f,0x82,0xe6 = pkhtb r2, r2, r3, asr #0x1f
+0xd3,0x27,0x82,0xe6 = pkhtb r2, r2, r3, asr #0xf
+0x04,0x70,0x9d,0xe4 = ldr r7, [sp], #4
 0x80,0x07,0xbd,0xe8 = pop {r7, r8, r9, r10}
-#0x04,0x70,0x2d,0xe5 = push {r7}
+0x04,0x70,0x2d,0xe5 = str r7, [sp, #-0x4]!
 0x80,0x07,0x2d,0xe9 = push {r7, r8, r9, r10}
 0x52,0x10,0x03,0xe1 = qadd r1, r2, r3
 0x52,0x10,0x03,0x11 = qaddne r1, r2, r3
@@ -530,11 +730,20 @@
 0x00,0x0a,0xb8,0xf9 = rfeib r8!
 0x00,0x0a,0x91,0xf8 = rfeia r1
 0x00,0x0a,0xb1,0xf8 = rfeia r1!
-0xe4,0x2f,0xa0,0xe1 = ror r2, r4, #31
+0xe4,0x2f,0xa0,0xe1 = ror r2, r4, #0x1f
 0xe4,0x20,0xa0,0xe1 = ror r2, r4, #1
 0x04,0x20,0xa0,0xe1 = mov r2, r4
 0xe4,0x40,0xa0,0xe1 = ror r4, r4, #1
-0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #61440
+0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #0xf000
+0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #0xf000
+0x0f,0x4a,0x65,0xe2 = rsb r4, r5, #0xf000
+0xff,0x78,0x68,0xe2 = rsb r7, r8, #0xff0000
+0x2a,0x71,0x68,0xe2 = rsb r7, r8, #-0x7ffffff6
+0x2a,0x71,0x68,0xe2 = rsb r7, r8, #-0x7ffffff6
+0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2
+0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2
+0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2
+0x28,0x71,0x68,0xe2 = rsb r7, r8, #0x28, #2
 0x06,0x40,0x65,0xe0 = rsb r4, r5, r6
 0x86,0x42,0x65,0xe0 = rsb r4, r5, r6, lsl #5
 0xa6,0x42,0x65,0x30 = rsblo r4, r5, r6, lsr #5
@@ -546,7 +755,16 @@
 0x58,0x69,0x67,0xe0 = rsb r6, r7, r8, asr r9
 0x78,0x69,0x67,0xd0 = rsble r6, r7, r8, ror r9
 0x66,0x40,0x65,0xe0 = rsb r4, r5, r6, rrx
-0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #61440
+0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #0xf000
+0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #0xf000
+0x0f,0x5a,0x65,0xe2 = rsb r5, r5, #0xf000
+0xff,0x78,0x67,0xe2 = rsb r7, r7, #0xff0000
+0x2a,0x71,0x67,0xe2 = rsb r7, r7, #-0x7ffffff6
+0x2a,0x71,0x67,0xe2 = rsb r7, r7, #-0x7ffffff6
+0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2
+0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2
+0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2
+0x28,0x71,0x67,0xe2 = rsb r7, r7, #0x28, #2
 0x05,0x40,0x64,0xe0 = rsb r4, r4, r5
 0x85,0x42,0x64,0xe0 = rsb r4, r4, r5, lsl #5
 0xa5,0x42,0x64,0xe0 = rsb r4, r4, r5, lsr #5
@@ -558,7 +776,26 @@
 0x57,0x69,0x66,0xe0 = rsb r6, r6, r7, asr r9
 0x77,0x69,0x66,0xe0 = rsb r6, r6, r7, ror r9
 0x65,0x40,0x64,0xe0 = rsb r4, r4, r5, rrx
-0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #61440
+0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000
+0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000
+0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000
+0xff,0x78,0x77,0xe2 = rsbs r7, r7, #0xff0000
+0x2a,0x71,0x78,0xe2 = rsbs r7, r8, #-0x7ffffff6
+0x2a,0x71,0x78,0xe2 = rsbs r7, r8, #-0x7ffffff6
+0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2
+0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2
+0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2
+0x28,0x71,0x78,0xe2 = rsbs r7, r8, #0x28, #2
+0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #0xf000
+0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #0xf000
+0x0f,0x4a,0xe5,0xe2 = rsc r4, r5, #0xf000
+0xff,0x78,0xe8,0xe2 = rsc r7, r8, #0xff0000
+0x2a,0x71,0xe8,0xe2 = rsc r7, r8, #-0x7ffffff6
+0x2a,0x71,0xe8,0xe2 = rsc r7, r8, #-0x7ffffff6
+0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2
+0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2
+0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2
+0x28,0x71,0xe8,0xe2 = rsc r7, r8, #0x28, #2
 0x06,0x40,0xe5,0xe0 = rsc r4, r5, r6
 0x86,0x42,0xe5,0xe0 = rsc r4, r5, r6, lsl #5
 0xa6,0x42,0xe5,0x30 = rsclo r4, r5, r6, lsr #5
@@ -569,8 +806,17 @@
 0x38,0x69,0xe7,0xe0 = rsc r6, r7, r8, lsr r9
 0x58,0x69,0xe7,0xe0 = rsc r6, r7, r8, asr r9
 0x78,0x69,0xe7,0xd0 = rscle r6, r7, r8, ror r9
-0xfe,0x1e,0xf8,0xe2 = rscs r1, r8, #4064
-0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #61440
+0xfe,0x1e,0xf8,0xe2 = rscs r1, r8, #0xfe0
+0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #0xf000
+0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #0xf000
+0x0f,0x5a,0xe5,0xe2 = rsc r5, r5, #0xf000
+0xff,0x78,0xe7,0xe2 = rsc r7, r7, #0xff0000
+0x2a,0x71,0xe7,0xe2 = rsc r7, r7, #-0x7ffffff6
+0x2a,0x71,0xe7,0xe2 = rsc r7, r7, #-0x7ffffff6
+0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2
+0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2
+0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2
+0x28,0x71,0xe7,0xe2 = rsc r7, r7, #0x28, #2
 0x05,0x40,0xe4,0xe0 = rsc r4, r4, r5
 0x85,0x42,0xe4,0xe0 = rsc r4, r4, r5, lsl #5
 0xa5,0x42,0xe4,0xe0 = rsc r4, r4, r5, lsr #5
@@ -595,7 +841,16 @@
 0x93,0x1f,0x12,0xd6 = sadd8le r1, r2, r3
 0x30,0x9f,0x1c,0xe6 = sasx r9, r12, r0
 0x30,0x9f,0x1c,0x06 = sasxeq r9, r12, r0
-0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #61440
+0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #0xf000
+0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #0xf000
+0x0f,0x4a,0xc5,0xe2 = sbc r4, r5, #0xf000
+0xff,0x78,0xc8,0xe2 = sbc r7, r8, #0xff0000
+0x2a,0x71,0xc8,0xe2 = sbc r7, r8, #-0x7ffffff6
+0x2a,0x71,0xc8,0xe2 = sbc r7, r8, #-0x7ffffff6
+0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2
+0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2
+0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2
+0x28,0x71,0xc8,0xe2 = sbc r7, r8, #0x28, #2
 0x06,0x40,0xc5,0xe0 = sbc r4, r5, r6
 0x86,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsl #5
 0xa6,0x42,0xc5,0xe0 = sbc r4, r5, r6, lsr #5
@@ -606,7 +861,16 @@
 0x38,0x69,0xc7,0xe0 = sbc r6, r7, r8, lsr r9
 0x58,0x69,0xc7,0xe0 = sbc r6, r7, r8, asr r9
 0x78,0x69,0xc7,0xe0 = sbc r6, r7, r8, ror r9
-0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #61440
+0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #0xf000
+0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #0xf000
+0x0f,0x5a,0xc5,0xe2 = sbc r5, r5, #0xf000
+0xff,0x78,0xc7,0xe2 = sbc r7, r7, #0xff0000
+0x2a,0x71,0xc7,0xe2 = sbc r7, r7, #-0x7ffffff6
+0x2a,0x71,0xc7,0xe2 = sbc r7, r7, #-0x7ffffff6
+0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2
+0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2
+0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2
+0x28,0x71,0xc7,0xe2 = sbc r7, r7, #0x28, #2
 0x05,0x40,0xc4,0xe0 = sbc r4, r4, r5
 0x85,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsl #5
 0xa5,0x42,0xc4,0xe0 = sbc r4, r4, r5, lsr #5
@@ -617,16 +881,16 @@
 0x37,0x69,0xc6,0xe0 = sbc r6, r6, r7, lsr r9
 0x57,0x69,0xc6,0xe0 = sbc r6, r6, r7, asr r9
 0x77,0x69,0xc6,0xe0 = sbc r6, r6, r7, ror r9
-0x55,0x48,0xa0,0xe7 = sbfx r4, r5, #16, #1
-0x55,0x48,0xaf,0xc7 = sbfxgt r4, r5, #16, #16
+0x55,0x48,0xa0,0xe7 = sbfx r4, r5, #0x10, #1
+0x55,0x48,0xaf,0xc7 = sbfxgt r4, r5, #0x10, #0x10
 0xb1,0x9f,0x82,0xe6 = sel r9, r2, r1
 0xb1,0x9f,0x82,0x16 = selne r9, r2, r1
 0x00,0x02,0x01,0xf1 = setend be
 0x00,0x02,0x01,0xf1 = setend be
 0x00,0x00,0x01,0xf1 = setend le
 0x00,0x00,0x01,0xf1 = setend le
-0x04,0xf0,0x20,0xe3 = sev 
-0x04,0xf0,0x20,0x03 = seveq 
+0x04,0xf0,0x20,0xe3 = sev
+0x04,0xf0,0x20,0x03 = seveq
 0x12,0x4f,0x38,0xe6 = shadd16 r4, r8, r2
 0x12,0x4f,0x38,0xc6 = shadd16gt r4, r8, r2
 0x92,0x4f,0x38,0xe6 = shadd8 r4, r8, r2
@@ -714,14 +978,14 @@
 0x05,0x05,0x4d,0xf8 = srsda sp, #5
 0x01,0x05,0x4d,0xf9 = srsdb sp, #1
 0x00,0x05,0xcd,0xf8 = srsia sp, #0
-0x0f,0x05,0xcd,0xf9 = srsib sp, #15
-0x1f,0x05,0x6d,0xf8 = srsda sp!, #31
-0x13,0x05,0x6d,0xf9 = srsdb sp!, #19
+0x0f,0x05,0xcd,0xf9 = srsib sp, #0xf
+0x1f,0x05,0x6d,0xf8 = srsda sp!, #0x1f
+0x13,0x05,0x6d,0xf9 = srsdb sp!, #0x13
 0x02,0x05,0xed,0xf8 = srsia sp!, #2
-0x0e,0x05,0xed,0xf9 = srsib sp!, #14
-0x0b,0x05,0xcd,0xf9 = srsib sp, #11
-0x0a,0x05,0xcd,0xf8 = srsia sp, #10
-0x09,0x05,0x4d,0xf9 = srsdb sp, #9
+0x0e,0x05,0xed,0xf9 = srsib sp!, #0xe
+0x0b,0x05,0xcd,0xf9 = srsib sp, #0xb
+0x0a,0x05,0xcd,0xf8 = srsia sp, #0xa
+0x09,0x05,0x4d,0xf9 = srsdb sp, #0x9
 0x05,0x05,0x4d,0xf8 = srsda sp, #5
 0x05,0x05,0xed,0xf9 = srsib sp!, #5
 0x05,0x05,0xed,0xf8 = srsia sp!, #5
@@ -732,14 +996,14 @@
 0x05,0x05,0x4d,0xf8 = srsda sp, #5
 0x01,0x05,0x4d,0xf9 = srsdb sp, #1
 0x00,0x05,0xcd,0xf8 = srsia sp, #0
-0x0f,0x05,0xcd,0xf9 = srsib sp, #15
-0x1f,0x05,0x6d,0xf8 = srsda sp!, #31
-0x13,0x05,0x6d,0xf9 = srsdb sp!, #19
+0x0f,0x05,0xcd,0xf9 = srsib sp, #0xf
+0x1f,0x05,0x6d,0xf8 = srsda sp!, #0x1f
+0x13,0x05,0x6d,0xf9 = srsdb sp!, #0x13
 0x02,0x05,0xed,0xf8 = srsia sp!, #2
-0x0e,0x05,0xed,0xf9 = srsib sp!, #14
-0x0b,0x05,0xcd,0xf9 = srsib sp, #11
-0x0a,0x05,0xcd,0xf8 = srsia sp, #10
-0x09,0x05,0x4d,0xf9 = srsdb sp, #9
+0x0e,0x05,0xed,0xf9 = srsib sp!, #0xe
+0x0b,0x05,0xcd,0xf9 = srsib sp, #0xb
+0x0a,0x05,0xcd,0xf8 = srsia sp, #0xa
+0x09,0x05,0x4d,0xf9 = srsdb sp, #0x9
 0x05,0x05,0x4d,0xf8 = srsda sp, #5
 0x05,0x05,0xed,0xf9 = srsib sp!, #5
 0x05,0x05,0xed,0xf8 = srsia sp!, #5
@@ -749,11 +1013,11 @@
 0x05,0x05,0xed,0xf8 = srsia sp!, #5
 0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10
 0x1a,0x80,0xa0,0xe6 = ssat r8, #1, r10
-0x9a,0x8f,0xa0,0xe6 = ssat r8, #1, r10, lsl #31
-0x5a,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #32
+0x9a,0x8f,0xa0,0xe6 = ssat r8, #1, r10, lsl #0x1f
+0x5a,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #0x20
 0xda,0x80,0xa0,0xe6 = ssat r8, #1, r10, asr #1
 0x37,0x2f,0xa0,0xe6 = ssat16 r2, #1, r7
-0x35,0x3f,0xaf,0xe6 = ssat16 r3, #16, r5
+0x35,0x3f,0xaf,0xe6 = ssat16 r3, #0x10, r5
 0x54,0x2f,0x13,0xe6 = ssax r2, r3, r4
 0x54,0x2f,0x13,0xb6 = ssaxlt r2, r3, r4
 0x76,0x1f,0x10,0xe6 = ssub16 r1, r0, r6
@@ -762,40 +1026,40 @@
 0xf2,0x5f,0x11,0x06 = ssub8eq r5, r1, r2
 0x01,0x80,0x81,0xfd = stc2 p0, c8, [r1, #4]
 0x00,0x71,0x82,0xfd = stc2 p1, c7, [r2]
-0x38,0x62,0x03,0xfd = stc2 p2, c6, [r3, #-224]
-0x1e,0x53,0x24,0xfd = stc2 p3, c5, [r4, #-120]!
-0x04,0x44,0xa5,0xfc = stc2 p4, c4, [r5], #16
-0x12,0x35,0x26,0xfc = stc2 p5, c3, [r6], #-72
+0x38,0x62,0x03,0xfd = stc2 p2, c6, [r3, #-0xe0]
+0x1e,0x53,0x24,0xfd = stc2 p3, c5, [r4, #-0x78]!
+0x04,0x44,0xa5,0xfc = stc2 p4, c4, [r5], #0x10
+0x12,0x35,0x26,0xfc = stc2 p5, c3, [r6], #-0x48
 0x01,0x26,0xc7,0xfd = stc2l p6, c2, [r7, #4]
 0x00,0x17,0xc8,0xfd = stc2l p7, c1, [r8]
-0x38,0x08,0x49,0xfd = stc2l p8, c0, [r9, #-224]
-0x1e,0x19,0x6a,0xfd = stc2l p9, c1, [r10, #-120]!
-0x04,0x20,0xeb,0xfc = stc2l p0, c2, [r11], #16
-0x12,0x31,0x6c,0xfc = stc2l p1, c3, [r12], #-72
+0x38,0x08,0x49,0xfd = stc2l p8, c0, [r9, #-0xe0]
+0x1e,0x19,0x6a,0xfd = stc2l p9, c1, [r10, #-0x78]!
+0x04,0x20,0xeb,0xfc = stc2l p0, c2, [r11], #0x10
+0x12,0x31,0x6c,0xfc = stc2l p1, c3, [r12], #-0x48
 0x01,0x4c,0x80,0xed = stc p12, c4, [r0, #4]
 0x00,0x5d,0x81,0xed = stc p13, c5, [r1]
-0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-224]
-0x1e,0x7f,0x23,0xed = stc p15, c7, [r3, #-120]!
-0x04,0x85,0xa4,0xec = stc p5, c8, [r4], #16
-0x12,0x94,0x25,0xec = stc p4, c9, [r5], #-72
+0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0]
+0x1e,0x7f,0x23,0xed = stc p15, c7, [r3, #-0x78]!
+0x04,0x85,0xa4,0xec = stc p5, c8, [r4], #0x10
+0x12,0x94,0x25,0xec = stc p4, c9, [r5], #-0x48
 0x01,0xa3,0xc6,0xed = stcl p3, c10, [r6, #4]
 0x00,0xb2,0xc7,0xed = stcl p2, c11, [r7]
-0x38,0xc1,0x48,0xed = stcl p1, c12, [r8, #-224]
-0x1e,0xd0,0x69,0xed = stcl p0, c13, [r9, #-120]!
-0x04,0xe6,0xea,0xec = stcl p6, c14, [r10], #16
-0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-72
+0x38,0xc1,0x48,0xed = stcl p1, c12, [r8, #-0xe0]
+0x1e,0xd0,0x69,0xed = stcl p0, c13, [r9, #-0x78]!
+0x04,0xe6,0xea,0xec = stcl p6, c14, [r10], #0x10
+0x12,0xf7,0x6b,0xec = stcl p7, c15, [r11], #-0x48
 0x01,0x4c,0x80,0x3d = stclo p12, c4, [r0, #4]
 0x00,0x5d,0x81,0x8d = stchi p13, c5, [r1]
-0x38,0x6e,0x02,0x2d = stchs p14, c6, [r2, #-224]
-0x1e,0x7f,0x23,0x3d = stclo p15, c7, [r3, #-120]!
-0x04,0x85,0xa4,0x0c = stceq p5, c8, [r4], #16
-0x12,0x94,0x25,0xcc = stcgt p4, c9, [r5], #-72
+0x38,0x6e,0x02,0x2d = stchs p14, c6, [r2, #-0xe0]
+0x1e,0x7f,0x23,0x3d = stclo p15, c7, [r3, #-0x78]!
+0x04,0x85,0xa4,0x0c = stceq p5, c8, [r4], #0x10
+0x12,0x94,0x25,0xcc = stcgt p4, c9, [r5], #-0x48
 0x01,0xa3,0xc6,0xbd = stcllt p3, c10, [r6, #4]
 0x00,0xb2,0xc7,0xad = stclge p2, c11, [r7]
-0x38,0xc1,0x48,0xdd = stclle p1, c12, [r8, #-224]
-0x1e,0xd0,0x69,0x1d = stclne p0, c13, [r9, #-120]!
-0x04,0xe6,0xea,0x0c = stcleq p6, c14, [r10], #16
-0x12,0xf7,0x6b,0x8c = stclhi p7, c15, [r11], #-72
+0x38,0xc1,0x48,0xdd = stclle p1, c12, [r8, #-0xe0]
+0x1e,0xd0,0x69,0x1d = stclne p0, c13, [r9, #-0x78]!
+0x04,0xe6,0xea,0x0c = stcleq p6, c14, [r10], #0x10
+0x12,0xf7,0x6b,0x8c = stclhi p7, c15, [r11], #-0x48
 0x19,0x82,0x81,0xfc = stc2 p2, c8, [r1], {25}
 0x7a,0x20,0x82,0xe8 = stm r2, {r1, r3, r4, r5, r6, sp}
 0x7a,0x40,0x83,0xe8 = stm r3, {r1, r3, r4, r5, r6, lr}
@@ -804,7 +1068,7 @@
 0x7a,0x01,0x06,0xe9 = stmdb r6, {r1, r3, r4, r5, r6, r8}
 0x7a,0x20,0x0d,0xe9 = stmdb sp, {r1, r3, r4, r5, r6, sp}
 0x7a,0x20,0xa8,0xe8 = stm r8!, {r1, r3, r4, r5, r6, sp}
-0x7a,0x20,0xa9,0xe9 = stmib sb!, {r1, r3, r4, r5, r6, sp}
+0x7a,0x20,0xa9,0xe9 = stmib r9!, {r1, r3, r4, r5, r6, sp}
 0x7a,0x00,0x2d,0xe8 = stmda sp!, {r1, r3, r4, r5, r6}
 0xa2,0x20,0x20,0xe9 = stmdb r0!, {r1, r5, r7, sp}
 0x93,0x1f,0xc4,0xe1 = strexb r1, r3, [r4]
@@ -813,7 +1077,16 @@
 0x92,0x6f,0xa8,0xe1 = strexd r6, r2, r3, [r8]
 0x00,0x30,0x2a,0x55 = strpl r3, [r10, #-0]!
 0x00,0x30,0xaa,0x55 = strpl r3, [r10, #0]!
-0x0f,0x4a,0x45,0xe2 = sub r4, r5, #61440
+0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000
+0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000
+0x0f,0x4a,0x45,0xe2 = sub r4, r5, #0xf000
+0xff,0x78,0x48,0xe2 = sub r7, r8, #0xff0000
+0x2a,0x71,0x48,0xe2 = sub r7, r8, #-0x7ffffff6
+0x2a,0x71,0x48,0xe2 = sub r7, r8, #-0x7ffffff6
+0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2
+0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2
+0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2
+0x28,0x71,0x48,0xe2 = sub r7, r8, #0x28, #2
 0x06,0x40,0x45,0xe0 = sub r4, r5, r6
 0x86,0x42,0x45,0xe0 = sub r4, r5, r6, lsl #5
 0xa6,0x42,0x45,0xe0 = sub r4, r5, r6, lsr #5
@@ -824,7 +1097,15 @@
 0x38,0x69,0x47,0xe0 = sub r6, r7, r8, lsr r9
 0x58,0x69,0x47,0xe0 = sub r6, r7, r8, asr r9
 0x78,0x69,0x47,0xe0 = sub r6, r7, r8, ror r9
-0x0f,0x5a,0x45,0xe2 = sub r5, r5, #61440
+0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000
+0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000
+0x0f,0x5a,0x45,0xe2 = sub r5, r5, #0xf000
+0xff,0x78,0x47,0xe2 = sub r7, r7, #0xff0000
+0x2a,0x71,0x47,0xe2 = sub r7, r7, #-0x7ffffff6
+0x2a,0x71,0x47,0xe2 = sub r7, r7, #-0x7ffffff6
+0x28,0x71,0x47,0xe2 = sub r7, r7, #0x28, #2
+0x28,0x71,0x47,0xe2 = sub r7, r7, #0x28, #2
+0x28,0x71,0x47,0xe2 = sub r7, r7, #0x28, #2
 0x05,0x40,0x44,0xe0 = sub r4, r4, r5
 0x85,0x42,0x44,0xe0 = sub r4, r4, r5, lsl #5
 0xa5,0x42,0x44,0xe0 = sub r4, r4, r5, lsr #5
@@ -835,45 +1116,64 @@
 0x37,0x69,0x46,0xe0 = sub r6, r6, r7, lsr r9
 0x57,0x69,0x46,0xe0 = sub r6, r6, r7, asr r9
 0x77,0x69,0x46,0xe0 = sub r6, r6, r7, ror r9
-0x22,0x30,0x41,0xe0 = sub r3, r1, r2, lsr #32
-0x42,0x30,0x41,0xe0 = sub r3, r1, r2, asr #32
-0x10,0x00,0x00,0xef = svc #16
+0x22,0x30,0x41,0xe0 = sub r3, r1, r2, lsr #0x20
+0x42,0x30,0x41,0xe0 = sub r3, r1, r2, asr #0x20
+0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000
+0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000
+0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000
+0xff,0x78,0x58,0xe2 = subs r7, r8, #0xff0000
+0x2a,0x71,0x58,0xe2 = subs r7, r8, #-0x7ffffff6
+0x2a,0x71,0x58,0xe2 = subs r7, r8, #-0x7ffffff6
+0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2
+0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2
+0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2
+0x28,0x71,0x58,0xe2 = subs r7, r8, #0x28, #2
+0x10,0x00,0x00,0xef = svc #0x10
 0x00,0x00,0x00,0xef = svc #0
-0xff,0xff,0xff,0xef = svc #16777215
+0xff,0xff,0xff,0xef = svc #0xffffff
 0x92,0x10,0x03,0xe1 = swp r1, r2, [r3]
 0x94,0x40,0x06,0xe1 = swp r4, r4, [r6]
 0x91,0x50,0x49,0xe1 = swpb r5, r1, [r9]
 0x74,0x20,0xa3,0xe6 = sxtab r2, r3, r4
 0x76,0x40,0xa5,0xe6 = sxtab r4, r5, r6
 0x79,0x64,0xa2,0xb6 = sxtablt r6, r2, r9, ror #8
-0x74,0x58,0xa1,0xe6 = sxtab r5, r1, r4, ror #16
-0x73,0x7c,0xa8,0xe6 = sxtab r7, r8, r3, ror #24
+0x74,0x58,0xa1,0xe6 = sxtab r5, r1, r4, ror #0x10
+0x73,0x7c,0xa8,0xe6 = sxtab r7, r8, r3, ror #0x18
 0x74,0x00,0x81,0xa6 = sxtab16ge r0, r1, r4
 0x77,0x60,0x82,0xe6 = sxtab16 r6, r2, r7
 0x78,0x34,0x85,0xe6 = sxtab16 r3, r5, r8, ror #8
-0x71,0x38,0x82,0xe6 = sxtab16 r3, r2, r1, ror #16
-0x73,0x1c,0x82,0x06 = sxtab16eq r1, r2, r3, ror #24
+0x71,0x38,0x82,0xe6 = sxtab16 r3, r2, r1, ror #0x10
+0x73,0x1c,0x82,0x06 = sxtab16eq r1, r2, r3, ror #0x18
 0x79,0x10,0xb3,0xe6 = sxtah r1, r3, r9
 0x76,0x60,0xb1,0x86 = sxtahhi r6, r1, r6
 0x73,0x34,0xb8,0xe6 = sxtah r3, r8, r3, ror #8
-0x74,0x28,0xb2,0x36 = sxtahlo r2, r2, r4, ror #16
-0x73,0x9c,0xb3,0xe6 = sxtah r9, r3, r3, ror #24
+0x74,0x28,0xb2,0x36 = sxtahlo r2, r2, r4, ror #0x10
+0x73,0x9c,0xb3,0xe6 = sxtah r9, r3, r3, ror #0x18
 0x74,0x20,0xaf,0xa6 = sxtbge r2, r4
 0x76,0x50,0xaf,0xe6 = sxtb r5, r6
 0x79,0x64,0xaf,0xe6 = sxtb r6, r9, ror #8
-0x71,0x58,0xaf,0x36 = sxtblo r5, r1, ror #16
-0x73,0x8c,0xaf,0xe6 = sxtb r8, r3, ror #24
+0x71,0x58,0xaf,0x36 = sxtblo r5, r1, ror #0x10
+0x73,0x8c,0xaf,0xe6 = sxtb r8, r3, ror #0x18
 0x74,0x10,0x8f,0xe6 = sxtb16 r1, r4
 0x77,0x60,0x8f,0xe6 = sxtb16 r6, r7
 0x75,0x34,0x8f,0x26 = sxtb16hs r3, r5, ror #8
-0x71,0x38,0x8f,0xe6 = sxtb16 r3, r1, ror #16
-0x73,0x2c,0x8f,0xa6 = sxtb16ge r2, r3, ror #24
+0x71,0x38,0x8f,0xe6 = sxtb16 r3, r1, ror #0x10
+0x73,0x2c,0x8f,0xa6 = sxtb16ge r2, r3, ror #0x18
 0x79,0x30,0xbf,0x16 = sxthne r3, r9
 0x76,0x10,0xbf,0xe6 = sxth r1, r6
 0x78,0x34,0xbf,0xe6 = sxth r3, r8, ror #8
-0x72,0x28,0xbf,0xd6 = sxthle r2, r2, ror #16
-0x73,0x9c,0xbf,0xe6 = sxth r9, r3, ror #24
-0x0f,0x0a,0x35,0xe3 = teq r5, #61440
+0x72,0x28,0xbf,0xd6 = sxthle r2, r2, ror #0x10
+0x73,0x9c,0xbf,0xe6 = sxth r9, r3, ror #0x18
+0x0f,0x0a,0x35,0xe3 = teq r5, #0xf000
+0x0f,0x0a,0x35,0xe3 = teq r5, #0xf000
+0x0f,0x0a,0x35,0xe3 = teq r5, #0xf000
+0xff,0x08,0x37,0xe3 = teq r7, #0xff0000
+0x2a,0x01,0x37,0xe3 = teq r7, #-0x7ffffff6
+0x2a,0x01,0x37,0xe3 = teq r7, #-0x7ffffff6
+0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2
+0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2
+0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2
+0x28,0x01,0x37,0xe3 = teq r7, #0x28, #2
 0x05,0x00,0x34,0xe1 = teq r4, r5
 0x85,0x02,0x34,0xe1 = teq r4, r5, lsl #5
 0xa5,0x02,0x34,0xe1 = teq r4, r5, lsr #5
@@ -884,7 +1184,16 @@
 0x37,0x09,0x36,0xe1 = teq r6, r7, lsr r9
 0x57,0x09,0x36,0xe1 = teq r6, r7, asr r9
 0x77,0x09,0x36,0xe1 = teq r6, r7, ror r9
-0x0f,0x0a,0x15,0xe3 = tst r5, #61440
+0x0f,0x0a,0x15,0xe3 = tst r5, #0xf000
+0x0f,0x0a,0x15,0xe3 = tst r5, #0xf000
+0x0f,0x0a,0x15,0xe3 = tst r5, #0xf000
+0xff,0x08,0x17,0xe3 = tst r7, #0xff0000
+0x2a,0x01,0x17,0xe3 = tst r7, #-0x7ffffff6
+0x2a,0x01,0x17,0xe3 = tst r7, #-0x7ffffff6
+0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2
+0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2
+0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2
+0x28,0x01,0x17,0xe3 = tst r7, #0x28, #2
 0x05,0x00,0x14,0xe1 = tst r4, r5
 0x85,0x02,0x14,0xe1 = tst r4, r5, lsl #5
 0xa5,0x02,0x14,0xe1 = tst r4, r5, lsr #5
@@ -901,8 +1210,8 @@
 0x93,0x1f,0x52,0xd6 = uadd8le r1, r2, r3
 0x30,0x9f,0x5c,0xe6 = uasx r9, r12, r0
 0x30,0x9f,0x5c,0x06 = uasxeq r9, r12, r0
-0x55,0x48,0xe0,0xe7 = ubfx r4, r5, #16, #1
-0x55,0x48,0xef,0xc7 = ubfxgt r4, r5, #16, #16
+0x55,0x48,0xe0,0xe7 = ubfx r4, r5, #0x10, #1
+0x55,0x48,0xef,0xc7 = ubfxgt r4, r5, #0x10, #0x10
 0x12,0x4f,0x78,0xe6 = uhadd16 r4, r8, r2
 0x12,0x4f,0x78,0xc6 = uhadd16gt r4, r8, r2
 0x92,0x4f,0x78,0xe6 = uhadd8 r4, r8, r2
@@ -941,11 +1250,11 @@
 0x12,0x15,0x83,0xc7 = usada8gt r3, r2, r5, r1
 0x1a,0x80,0xe1,0xe6 = usat r8, #1, r10
 0x1a,0x80,0xe4,0xe6 = usat r8, #4, r10
-0x9a,0x8f,0xe5,0xe6 = usat r8, #5, r10, lsl #31
-0x5a,0x80,0xff,0xe6 = usat r8, #31, r10, asr #32
-0xda,0x80,0xf0,0xe6 = usat r8, #16, r10, asr #1
+0x9a,0x8f,0xe5,0xe6 = usat r8, #5, r10, lsl #0x1f
+0x5a,0x80,0xff,0xe6 = usat r8, #0x1f, r10, asr #0x20
+0xda,0x80,0xf0,0xe6 = usat r8, #0x10, r10, asr #1
 0x37,0x2f,0xe2,0xe6 = usat16 r2, #2, r7
-0x35,0x3f,0xef,0xe6 = usat16 r3, #15, r5
+0x35,0x3f,0xef,0xe6 = usat16 r3, #0xf, r5
 0x54,0x2f,0x53,0xe6 = usax r2, r3, r4
 0x54,0x2f,0x53,0x16 = usaxne r2, r3, r4
 0x77,0x4f,0x52,0xe6 = usub16 r4, r2, r7
@@ -955,42 +1264,42 @@
 0x74,0x20,0xe3,0xe6 = uxtab r2, r3, r4
 0x76,0x40,0xe5,0xe6 = uxtab r4, r5, r6
 0x79,0x64,0xe2,0xb6 = uxtablt r6, r2, r9, ror #8
-0x74,0x58,0xe1,0xe6 = uxtab r5, r1, r4, ror #16
-0x73,0x7c,0xe8,0xe6 = uxtab r7, r8, r3, ror #24
+0x74,0x58,0xe1,0xe6 = uxtab r5, r1, r4, ror #0x10
+0x73,0x7c,0xe8,0xe6 = uxtab r7, r8, r3, ror #0x18
 0x74,0x00,0xc1,0xa6 = uxtab16ge r0, r1, r4
 0x77,0x60,0xc2,0xe6 = uxtab16 r6, r2, r7
 0x78,0x34,0xc5,0xe6 = uxtab16 r3, r5, r8, ror #8
-0x71,0x38,0xc2,0xe6 = uxtab16 r3, r2, r1, ror #16
-0x73,0x1c,0xc2,0x06 = uxtab16eq r1, r2, r3, ror #24
+0x71,0x38,0xc2,0xe6 = uxtab16 r3, r2, r1, ror #0x10
+0x73,0x1c,0xc2,0x06 = uxtab16eq r1, r2, r3, ror #0x18
 0x79,0x10,0xf3,0xe6 = uxtah r1, r3, r9
 0x76,0x60,0xf1,0x86 = uxtahhi r6, r1, r6
 0x73,0x34,0xf8,0xe6 = uxtah r3, r8, r3, ror #8
-0x74,0x28,0xf2,0x36 = uxtahlo r2, r2, r4, ror #16
-0x73,0x9c,0xf3,0xe6 = uxtah r9, r3, r3, ror #24
+0x74,0x28,0xf2,0x36 = uxtahlo r2, r2, r4, ror #0x10
+0x73,0x9c,0xf3,0xe6 = uxtah r9, r3, r3, ror #0x18
 0x74,0x20,0xef,0xa6 = uxtbge r2, r4
 0x76,0x50,0xef,0xe6 = uxtb r5, r6
 0x79,0x64,0xef,0xe6 = uxtb r6, r9, ror #8
-0x71,0x58,0xef,0x36 = uxtblo r5, r1, ror #16
-0x73,0x8c,0xef,0xe6 = uxtb r8, r3, ror #24
+0x71,0x58,0xef,0x36 = uxtblo r5, r1, ror #0x10
+0x73,0x8c,0xef,0xe6 = uxtb r8, r3, ror #0x18
 0x74,0x10,0xcf,0xe6 = uxtb16 r1, r4
 0x77,0x60,0xcf,0xe6 = uxtb16 r6, r7
 0x75,0x34,0xcf,0x26 = uxtb16hs r3, r5, ror #8
-0x71,0x38,0xcf,0xe6 = uxtb16 r3, r1, ror #16
-0x73,0x2c,0xcf,0xa6 = uxtb16ge r2, r3, ror #24
+0x71,0x38,0xcf,0xe6 = uxtb16 r3, r1, ror #0x10
+0x73,0x2c,0xcf,0xa6 = uxtb16ge r2, r3, ror #0x18
 0x79,0x30,0xff,0x16 = uxthne r3, r9
 0x76,0x10,0xff,0xe6 = uxth r1, r6
 0x78,0x34,0xff,0xe6 = uxth r3, r8, ror #8
-0x72,0x28,0xff,0xd6 = uxthle r2, r2, ror #16
-0x73,0x9c,0xff,0xe6 = uxth r9, r3, ror #24
-0x02,0xf0,0x20,0xe3 = wfe 
-0x02,0xf0,0x20,0x83 = wfehi 
-0x03,0xf0,0x20,0xe3 = wfi 
-0x03,0xf0,0x20,0xb3 = wfilt 
-0x01,0xf0,0x20,0xe3 = yield 
-0x01,0xf0,0x20,0x13 = yieldne 
-0x04,0xf0,0x20,0xe3 = sev 
-0x03,0xf0,0x20,0xe3 = wfi 
-0x02,0xf0,0x20,0xe3 = wfe 
-0x01,0xf0,0x20,0xe3 = yield 
-0x00,0xf0,0x20,0xe3 = nop 
-0xef,0xf0,0x20,0xc3 = hintgt #239
+0x72,0x28,0xff,0xd6 = uxthle r2, r2, ror #0x10
+0x73,0x9c,0xff,0xe6 = uxth r9, r3, ror #0x18
+0x02,0xf0,0x20,0xe3 = wfe
+0x02,0xf0,0x20,0x83 = wfehi
+0x03,0xf0,0x20,0xe3 = wfi
+0x03,0xf0,0x20,0xb3 = wfilt
+0x01,0xf0,0x20,0xe3 = yield
+0x01,0xf0,0x20,0x13 = yieldne
+0x04,0xf0,0x20,0xe3 = sev
+0x03,0xf0,0x20,0xe3 = wfi
+0x02,0xf0,0x20,0xe3 = wfe
+0x01,0xf0,0x20,0xe3 = yield
+0x00,0xf0,0x20,0xe3 = nop
+0xef,0xf0,0x20,0xc3 = hintgt #0xef
diff --git a/suite/MC/ARM/basic-thumb-instructions.s.cs b/suite/MC/ARM/basic-thumb-instructions.s.cs
index b43241fd8..bb3d8a8f2 100644
--- a/suite/MC/ARM/basic-thumb-instructions.s.cs
+++ b/suite/MC/ARM/basic-thumb-instructions.s.cs
@@ -6,37 +6,37 @@
 0xd1,0x18 = adds r1, r2, r3
 0x42,0x44 = add r2, r8
 0x01,0xb0 = add sp, #4
-0x7f,0xb0 = add sp, #508
+0x7f,0xb0 = add sp, #0x1fc
 0x01,0xb0 = add sp, #4
 0x02,0xaa = add r2, sp, #8
-0xff,0xaa = add r2, sp, #1020
+0xff,0xaa = add r2, sp, #0x3fc
 0x82,0xb0 = sub sp, #8
 0x82,0xb0 = sub sp, #8
 0x9d,0x44 = add sp, r3
 0x6a,0x44 = add r2, sp, r2
 0x00,0xa5 = adr r5, #0
 0x01,0xa2 = adr r2, #4
-0xff,0xa3 = adr r3, #1020
-0x1a,0x10 = asrs r2, r3, #32
+0xff,0xa3 = adr r3, #0x3fc
+0x1a,0x10 = asrs r2, r3, #0x20
 0x5a,0x11 = asrs r2, r3, #5
 0x5a,0x10 = asrs r2, r3, #1
-0x6d,0x15 = asrs r5, r5, #21
-0x6d,0x15 = asrs r5, r5, #21
-0x6b,0x15 = asrs r3, r5, #21
+0x6d,0x15 = asrs r5, r5, #0x15
+0x6d,0x15 = asrs r5, r5, #0x15
+0x6b,0x15 = asrs r3, r5, #0x15
 0x15,0x41 = asrs r5, r2
-0x97,0xe3 = b #1842
-0x2e,0xe7 = b #-416
-0x80,0xd0 = beq #-252
-0x50,0xd0 = beq #164
-0xd8,0xf0,0x20,0xe8 = blx #884804
-0xb0,0xf1,0x40,0xe8 = blx #1769604
+0x97,0xe3 = b #0x72e
+0x2e,0xe7 = b #-0x1a4
+0x80,0xd0 = beq #-0x100
+0x50,0xd0 = beq #0xa0
+0xd8,0xf0,0x20,0xe8 = blx #0xd8040
+0xb0,0xf1,0x40,0xe8 = blx #0x1b0080
 0xb1,0x43 = bics r1, r6
 0x00,0xbe = bkpt #0
-0xff,0xbe = bkpt #255
+0xff,0xbe = bkpt #0xff
 0xa0,0x47 = blx r4
 0x10,0x47 = bx r2
 0xcd,0x42 = cmn r5, r1
-0x20,0x2e = cmp r6, #32
+0x20,0x2e = cmp r6, #0x20
 0xa3,0x42 = cmp r3, r4
 0x88,0x45 = cmp r8, r1
 0x61,0xb6 = cpsie f
@@ -46,39 +46,39 @@
 0xba,0xca = ldm r2!, {r1, r3, r4, r5, r7}
 0x02,0xc9 = ldm r1, {r1}
 0x29,0x68 = ldr r1, [r5]
-0x32,0x6a = ldr r2, [r6, #32]
-0xfb,0x6f = ldr r3, [r7, #124]
+0x32,0x6a = ldr r2, [r6, #0x20]
+0xfb,0x6f = ldr r3, [r7, #0x7c]
 0x00,0x99 = ldr r1, [sp]
-0x06,0x9a = ldr r2, [sp, #24]
-0xff,0x9b = ldr r3, [sp, #1020]
-0x97,0x4b = ldr r3, [pc, #604]
-0x5c,0x4b = ldr r3, [pc, #368]
+0x06,0x9a = ldr r2, [sp, #0x18]
+0xff,0x9b = ldr r3, [sp, #0x3fc]
+0x97,0x4b = ldr r3, [pc, #0x25c]
+0x5c,0x4b = ldr r3, [pc, #0x170]
 0xd1,0x58 = ldr r1, [r2, r3]
 0x1c,0x78 = ldrb r4, [r3]
 0x35,0x78 = ldrb r5, [r6]
-0xfe,0x7f = ldrb r6, [r7, #31]
+0xfe,0x7f = ldrb r6, [r7, #0x1f]
 0x66,0x5d = ldrb r6, [r4, r5]
 0x1b,0x88 = ldrh r3, [r3]
 0x74,0x88 = ldrh r4, [r6, #2]
-0xfd,0x8f = ldrh r5, [r7, #62]
+0xfd,0x8f = ldrh r5, [r7, #0x3e]
 0x96,0x5b = ldrh r6, [r2, r6]
 0x96,0x57 = ldrsb r6, [r2, r6]
 0x7b,0x5e = ldrsh r3, [r7, r1]
-// 0x2c,0x00 = lsls r4, r5, #0
+0x2c,0x00 = movs r4, r5
 0x2c,0x01 = lsls r4, r5, #4
-0x1b,0x03 = lsls r3, r3, #12
-0x1b,0x03 = lsls r3, r3, #12
-0x19,0x03 = lsls r1, r3, #12
+0x1b,0x03 = lsls r3, r3, #0xc
+0x1b,0x03 = lsls r3, r3, #0xc
+0x19,0x03 = lsls r1, r3, #0xc
 0xb2,0x40 = lsls r2, r6
 0x59,0x08 = lsrs r1, r3, #1
-0x19,0x08 = lsrs r1, r3, #32
-0x24,0x0d = lsrs r4, r4, #20
-0x24,0x0d = lsrs r4, r4, #20
-0x22,0x0d = lsrs r2, r4, #20
+0x19,0x08 = lsrs r1, r3, #0x20
+0x24,0x0d = lsrs r4, r4, #0x14
+0x24,0x0d = lsrs r4, r4, #0x14
+0x22,0x0d = lsrs r2, r4, #0x14
 0xf2,0x40 = lsrs r2, r6
 0x00,0x22 = movs r2, #0
-0xff,0x22 = movs r2, #255
-0x17,0x22 = movs r2, #23
+0xff,0x22 = movs r2, #0xff
+0x17,0x22 = movs r2, #0x17
 0x23,0x46 = mov r3, r4
 0x19,0x00 = movs r1, r3
 0x51,0x43 = muls r1, r2, r1
@@ -101,28 +101,28 @@
 0x3a,0x60 = str r2, [r7]
 0x3a,0x60 = str r2, [r7]
 0x4d,0x60 = str r5, [r1, #4]
-0xfb,0x67 = str r3, [r7, #124]
+0xfb,0x67 = str r3, [r7, #0x7c]
 0x00,0x92 = str r2, [sp]
 0x00,0x93 = str r3, [sp]
-0x05,0x94 = str r4, [sp, #20]
-0xff,0x95 = str r5, [sp, #1020]
+0x05,0x94 = str r4, [sp, #0x14]
+0xff,0x95 = str r5, [sp, #0x3fc]
 0xfa,0x50 = str r2, [r7, r3]
 0x1c,0x70 = strb r4, [r3]
 0x35,0x70 = strb r5, [r6]
-0xfe,0x77 = strb r6, [r7, #31]
+0xfe,0x77 = strb r6, [r7, #0x1f]
 0x66,0x55 = strb r6, [r4, r5]
 0x1b,0x80 = strh r3, [r3]
 0x74,0x80 = strh r4, [r6, #2]
-0xfd,0x87 = strh r5, [r7, #62]
+0xfd,0x87 = strh r5, [r7, #0x3e]
 0x96,0x53 = strh r6, [r2, r6]
 0xd1,0x1e = subs r1, r2, #3
 0x03,0x3a = subs r2, #3
 0x08,0x3a = subs r2, #8
-0x83,0xb0 = sub sp, #12
-0xff,0xb0 = sub sp, #508
+0x83,0xb0 = sub sp, #0xc
+0xff,0xb0 = sub sp, #0x1fc
 0xd1,0x1a = subs r1, r2, r3
 0x00,0xdf = svc #0
-0xff,0xdf = svc #255
+0xff,0xdf = svc #0xff
 0x6b,0xb2 = sxtb r3, r5
 0x2b,0xb2 = sxth r3, r5
 0x0e,0x42 = tst r6, r1
diff --git a/suite/MC/ARM/basic-thumb2-instructions.s.cs b/suite/MC/ARM/basic-thumb2-instructions.s.cs
index 87175459e..542b7603c 100644
--- a/suite/MC/ARM/basic-thumb2-instructions.s.cs
+++ b/suite/MC/ARM/basic-thumb2-instructions.s.cs
@@ -1,129 +1,162 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
 0x41,0xf1,0x04,0x00 = adc r0, r1, #4
 0x51,0xf1,0x00,0x00 = adcs r0, r1, #0
-0x42,0xf1,0xff,0x01 = adc r1, r2, #255
-0x47,0xf1,0x55,0x13 = adc r3, r7, #5570645
-0x4c,0xf1,0xaa,0x28 = adc r8, r12, #2852170240
-0x47,0xf1,0xa5,0x39 = adc r9, r7, #2779096485
-0x43,0xf1,0x07,0x45 = adc r5, r3, #2264924160
-0x42,0xf1,0xff,0x44 = adc r4, r2, #2139095040
-0x42,0xf5,0xd0,0x64 = adc r4, r2, #1664
+0x42,0xf1,0xff,0x01 = adc r1, r2, #0xff
+0x47,0xf1,0x55,0x13 = adc r3, r7, #0x550055
+0x4c,0xf1,0xaa,0x28 = adc r8, r12, #0xaa00aa00
+0x47,0xf1,0xa5,0x39 = adc r9, r7, #0xa5a5a5a5
+0x43,0xf1,0x07,0x45 = adc r5, r3, #0x87000000
+0x42,0xf1,0xff,0x44 = adc r4, r2, #0x7f800000
+0x42,0xf5,0xd0,0x64 = adc r4, r2, #0x680
 0x45,0xeb,0x06,0x04 = adc.w r4, r5, r6
 0x55,0xeb,0x06,0x04 = adcs.w r4, r5, r6
 0x41,0xeb,0x03,0x09 = adc.w r9, r1, r3
 0x51,0xeb,0x03,0x09 = adcs.w r9, r1, r3
 0x41,0xeb,0x33,0x10 = adc.w r0, r1, r3, ror #4
 0x51,0xeb,0xc3,0x10 = adcs.w r0, r1, r3, lsl #7
-0x41,0xeb,0xd3,0x70 = adc.w r0, r1, r3, lsr #31
-0x51,0xeb,0x23,0x00 = adcs.w r0, r1, r3, asr #32
-0x0d,0xeb,0x0c,0x02 = add.w r2, sp, ip
+0x41,0xeb,0xd3,0x70 = adc.w r0, r1, r3, lsr #0x1f
+0x51,0xeb,0x23,0x00 = adcs.w r0, r1, r3, asr #0x20
 0x0a,0xbf = itet eq
-// 0x03,0xf2,0xff,0x35 = addwne r5, r3, #1023
-// 0x05,0xf2,0x25,0x14 = addweq r4, r5, #293
-0x0d,0xf5,0x80,0x62 = add.w r2, sp, #1024
-0x08,0xf5,0x7f,0x42 = add.w r2, r8, #65280
-0x03,0xf2,0x01,0x12 = addw r2, r3, #257
-0x03,0xf2,0x01,0x12 = addw r2, r3, #257
-0x06,0xf5,0x80,0x7c = add.w r12, r6, #256
-0x06,0xf2,0x00,0x1c = addw r12, r6, #256
-0x12,0xf5,0xf8,0x71 = adds.w r1, r2, #496
+0x11,0x1d = addeq r1, r2, #4
+0x03,0xf2,0xff,0x35 = addwne r5, r3, #0x3ff
+0x05,0xf2,0x25,0x14 = addweq r4, r5, #0x125
+0x0d,0xf5,0x80,0x62 = add.w r2, sp, #0x400
+0x08,0xf5,0x7f,0x42 = add.w r2, r8, #0xff00
+0x03,0xf2,0x01,0x12 = addw r2, r3, #0x101
+0x03,0xf2,0x01,0x12 = addw r2, r3, #0x101
+0x06,0xf5,0x80,0x7c = add.w r12, r6, #0x100
+0x06,0xf2,0x00,0x1c = addw r12, r6, #0x100
+0x12,0xf5,0xf8,0x71 = adds.w r1, r2, #0x1f0
 0x02,0xf1,0x01,0x02 = add.w r2, r2, #1
-0x00,0xf1,0x20,0x00 = add.w r0, r0, #32
-0x38,0x32 = adds r2, #56
-0x38,0x32 = adds r2, #56
-0x07,0xf1,0xcb,0x31 = add.w r1, r7, #3419130827
-0x0d,0xf1,0xff,0x7d = add.w sp, sp, #33423360
-0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #16
-0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #16
-0xa2,0xf2,0x10,0x02 = subw r2, r2, #16
-0xa2,0xf2,0x10,0x02 = subw r2, r2, #16
-0xa2,0xf2,0x10,0x02 = subw r2, r2, #16
+0x00,0xf1,0x20,0x00 = add.w r0, r0, #0x20
+0x38,0x32 = adds r2, #0x38
+0x38,0x32 = adds r2, #0x38
+0x07,0xf1,0xcb,0x31 = add.w r1, r7, #0xcbcbcbcb
+0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #0x10
+0xb2,0xf1,0x10,0x02 = subs.w r2, r2, #0x10
+0xa2,0xf2,0x10,0x02 = subw r2, r2, #0x10
+0xa2,0xf2,0x10,0x02 = subw r2, r2, #0x10
+0xa2,0xf2,0x10,0x02 = subw r2, r2, #0x10
 0x02,0xeb,0x08,0x01 = add.w r1, r2, r8
-0x09,0xeb,0x22,0x05 = add.w r5, r9, r2, asr #32
-0x13,0xeb,0xc1,0x77 = adds.w r7, r3, r1, lsl #31
-0x13,0xeb,0x56,0x60 = adds.w r0, r3, r6, lsr #25
-0x08,0xeb,0x31,0x34 = add.w r4, r8, r1, ror #12
+0x09,0xeb,0x22,0x05 = add.w r5, r9, r2, asr #0x20
+0x13,0xeb,0xc1,0x77 = adds.w r7, r3, r1, lsl #0x1f
+0x13,0xeb,0x56,0x60 = adds.w r0, r3, r6, lsr #0x19
+0x08,0xeb,0x31,0x34 = add.w r4, r8, r1, ror #0xc
+0xc9,0x19 = adds r1, r1, r7
+0x08,0xbf = it eq
+0x59,0x19 = addeq r1, r3, r5
+0x08,0xbf = it eq
+0x49,0x19 = addeq r1, r1, r5
+0x08,0xbf = it eq
+0x13,0xeb,0x05,0x01 = addseq.w r1, r3, r5
+0x08,0xbf = it eq
+0x11,0xeb,0x05,0x01 = addseq.w r1, r1, r5
 0xc2,0x44 = add r10, r8
 0xc2,0x44 = add r10, r8
-0xaf,0xf6,0xc6,0x4b = subw r11, pc, #3270
-// 0x0f,0xf2,0x03,0x02 = adr.w r2, #3
-// 0xaf,0xf2,0x3a,0x3b = adr.w r11, #-826
-// 0xaf,0xf2,0x00,0x01 = adr.w r1, #-0
-0x05,0xf4,0x7f,0x22 = and r2, r5, #1044480
-0x1c,0xf0,0x0f,0x03 = ands r3, r12, #15
-0x01,0xf0,0xff,0x01 = and r1, r1, #255
-0x01,0xf0,0xff,0x01 = and r1, r1, #255
-0x04,0xf0,0xff,0x35 = and r5, r4, #4294967295
-0x19,0xf0,0xff,0x31 = ands r1, r9, #4294967295
+0x08,0xbf = it eq
+0x51,0x44 = addeq r1, r10
+0x08,0xbf = it eq
+0x11,0xeb,0x0a,0x01 = addseq.w r1, r1, r10
+0x08,0xbf = it eq
+0xff,0xaf = addeq r7, sp, #0x3fc
+0x08,0xbf = it eq
+0x7f,0xb0 = addeq sp, #0x1fc
+0x0d,0xf1,0x0f,0x07 = add.w r7, sp, #0xf
+0x1d,0xf1,0x10,0x07 = adds.w r7, sp, #0x10
+0x0d,0xf1,0x10,0x08 = add.w r8, sp, #0x10
+0x0d,0xf2,0xfc,0x36 = addw r6, sp, #0x3fc
+0x0d,0xf2,0xfb,0x36 = addw r6, sp, #0x3fb
+0x08,0xbf = it eq
+0xe8,0x44 = addeq r8, sp, r8
+0x08,0xbf = it eq
+0xcd,0x44 = addeq sp, r9
+0x0d,0xeb,0x0c,0x02 = add.w r2, sp, r12
+0x08,0xbf = it eq
+0x0d,0xeb,0x0c,0x02 = addeq.w r2, sp, r12
+0xaf,0xf6,0xc6,0x4b = adr.w r11, #4294964026
+0x0f,0xf2,0x03,0x02 = adr.w r2, #3
+0xaf,0xf2,0x3a,0x3b = adr.w r11, #-0x33a
+0xaf,0xf2,0x00,0x01 = subw r1, pc, #0
+0x05,0xf4,0x7f,0x22 = and r2, r5, #0xff000
+0x1c,0xf0,0x0f,0x03 = ands r3, r12, #0xf
+0x01,0xf0,0xff,0x01 = and r1, r1, #0xff
+0x01,0xf0,0xff,0x01 = and r1, r1, #0xff
+0x04,0xf0,0xff,0x35 = and r5, r4, #0xffffffff
+0x19,0xf0,0xff,0x31 = ands r1, r9, #0xffffffff
 0x09,0xea,0x08,0x04 = and.w r4, r9, r8
 0x04,0xea,0xe8,0x01 = and.w r1, r4, r8, asr #3
 0x11,0xea,0x47,0x02 = ands.w r2, r1, r7, lsl #1
-0x15,0xea,0x12,0x54 = ands.w r4, r5, r2, lsr #20
-0x0c,0xea,0x71,0x49 = and.w r9, r12, r1, ror #17
-0x4f,0xea,0x23,0x32 = asr.w r2, r3, #12
-0x5f,0xea,0x23,0x08 = asrs.w r8, r3, #32
+0x15,0xea,0x12,0x54 = ands.w r4, r5, r2, lsr #0x14
+0x0c,0xea,0x71,0x49 = and.w r9, r12, r1, ror #0x11
+0x4f,0xea,0x23,0x32 = asr.w r2, r3, #0xc
+0x5f,0xea,0x23,0x08 = asrs.w r8, r3, #0x20
 0x5f,0xea,0x63,0x02 = asrs.w r2, r3, #1
 0x4f,0xea,0x23,0x12 = asr.w r2, r3, #4
-0x5f,0xea,0xec,0x32 = asrs.w r2, r12, #15
-0x4f,0xea,0xe3,0x43 = asr.w r3, r3, #19
+0x5f,0xea,0xec,0x32 = asrs.w r2, r12, #0xf
+0x4f,0xea,0xe3,0x43 = asr.w r3, r3, #0x13
 0x5f,0xea,0xa8,0x08 = asrs.w r8, r8, #2
 0x5f,0xea,0x67,0x17 = asrs.w r7, r7, #5
-0x4f,0xea,0x6c,0x5c = asr.w r12, r12, #21
+0x4f,0xea,0x6c,0x5c = asr.w r12, r12, #0x15
+0x51,0x10 = asrs r1, r2, #1
+0x04,0xbf = itt eq
+0x5f,0xea,0x62,0x01 = asrseq.w r1, r2, #1
+0x51,0x10 = asreq r1, r2, #1
 0x44,0xfa,0x02,0xf3 = asr.w r3, r4, r2
 0x41,0xfa,0x02,0xf1 = asr.w r1, r1, r2
 0x54,0xfa,0x08,0xf3 = asrs.w r3, r4, r8
 0x08,0xbf = it eq
-0x13,0xf5,0xce,0xa9 = bmi.w #-183392
-// 0x6f,0xf3,0xd3,0x05 = bfc r5, #3, #17
+0x13,0xf5,0xce,0xa9 = beq.w #-0x2cc64
+0x6f,0xf3,0xd3,0x05 = bfc r5, #3, #0x11
 0x38,0xbf = it lo
-// 0x6f,0xf3,0xd3,0x05 = bfclo r5, #3, #17
-// 0x62,0xf3,0xd3,0x05 = bfi r5, r2, #3, #17
+0x6f,0xf3,0xd3,0x05 = bfclo r5, #3, #0x11
+0x62,0xf3,0xd3,0x05 = bfi r5, r2, #3, #0x11
 0x18,0xbf = it ne
-// 0x62,0xf3,0xd3,0x05 = bfine r5, r2, #3, #17
-0x21,0xf0,0x0f,0x0a = bic r10, r1, #15
-0x22,0xf0,0xff,0x35 = bic r5, r2, #4294967295
-0x3a,0xf0,0xff,0x3b = bics r11, r10, #4294967295
+0x62,0xf3,0xd3,0x05 = bfine r5, r2, #3, #0x11
+0x21,0xf0,0x0f,0x0a = bic r10, r1, #0xf
+0x22,0xf0,0xff,0x35 = bic r5, r2, #0xffffffff
+0x3a,0xf0,0xff,0x3b = bics r11, r10, #0xffffffff
 0x23,0xea,0x06,0x0c = bic.w r12, r3, r6
-0x22,0xea,0x06,0x3b = bic.w r11, r2, r6, lsl #12
-0x24,0xea,0xd1,0x28 = bic.w r8, r4, r1, lsr #11
-0x25,0xea,0xd7,0x37 = bic.w r7, r5, r7, lsr #15
-0x27,0xea,0x29,0x06 = bic.w r6, r7, r9, asr #32
+0x22,0xea,0x06,0x3b = bic.w r11, r2, r6, lsl #0xc
+0x24,0xea,0xd1,0x28 = bic.w r8, r4, r1, lsr #0xb
+0x25,0xea,0xd7,0x37 = bic.w r7, r5, r7, lsr #0xf
+0x27,0xea,0x29,0x06 = bic.w r6, r7, r9, asr #0x20
 0x26,0xea,0x78,0x05 = bic.w r5, r6, r8, ror #1
-0x21,0xf0,0x0f,0x01 = bic r1, r1, #15
+0x21,0xf0,0x0f,0x01 = bic r1, r1, #0xf
 0x21,0xea,0x01,0x01 = bic.w r1, r1, r1
-0x24,0xea,0xc2,0x74 = bic.w r4, r4, r2, lsl #31
-0x26,0xea,0x13,0x36 = bic.w r6, r6, r3, lsr #12
+0x24,0xea,0xc2,0x74 = bic.w r4, r4, r2, lsl #0x1f
+0x26,0xea,0x13,0x36 = bic.w r6, r6, r3, lsr #0xc
 0x27,0xea,0xd4,0x17 = bic.w r7, r7, r4, lsr #7
-0x28,0xea,0xe5,0x38 = bic.w r8, r8, r5, asr #15
-0x2c,0xea,0x76,0x7c = bic.w r12, r12, r6, ror #29
+0x28,0xea,0xe5,0x38 = bic.w r8, r8, r5, asr #0xf
+0x2c,0xea,0x76,0x7c = bic.w r12, r12, r6, ror #0x1d
 0x58,0xbf = it pl
-0xea,0xbe = bkpt #234
+0xea,0xbe = bkpt #0xea
 0xc5,0xf3,0x00,0x8f = bxj r5
 0x18,0xbf = it ne
-// 0xc7,0xf3,0x00,0x8f = bxjne r7
-// 0x1f,0xb9 = cbnz r7, #6
-// 0x37,0xb9 = cbnz r7, #12
+0xc7,0xf3,0x00,0x8f = bxjne r7
+0x1f,0xb9 = cbnz r7, #6
+0x37,0xb9 = cbnz r7, #0xc
 0x11,0xee,0x81,0x17 = cdp p7, #1, c1, c1, c1, #4
 0x11,0xfe,0x81,0x17 = cdp2 p7, #1, c1, c1, c1, #4
-0xbf,0xf3,0x2f,0x8f = clrex 
+0xbf,0xf3,0x2f,0x8f = clrex
 0x18,0xbf = it ne
-// 0xb2,0xfa,0x82,0xf1 = clz r1, r2
+0xbf,0xf3,0x2f,0x8f = clrexne
+0xb2,0xfa,0x82,0xf1 = clz r1, r2
 0x08,0xbf = it eq
-// 0xb2,0xfa,0x82,0xf1 = clzeq r1, r2
-0x11,0xf1,0x0f,0x0f = cmn.w r1, #15
+0xb2,0xfa,0x82,0xf1 = clzeq r1, r2
+0x11,0xf1,0x0f,0x0f = cmn.w r1, #0xf
 0x18,0xeb,0x06,0x0f = cmn.w r8, r6
-0x11,0xeb,0x86,0x2f = cmn.w r1, r6, lsl #10
-0x11,0xeb,0x96,0x2f = cmn.w r1, r6, lsr #10
-0x1d,0xeb,0x96,0x2f = cmn.w sp, r6, lsr #10
-0x11,0xeb,0xa6,0x2f = cmn.w r1, r6, asr #10
-0x11,0xeb,0xb6,0x2f = cmn.w r1, r6, ror #10
-0xb5,0xf5,0x7f,0x4f = cmp.w r5, #65280
+0x11,0xeb,0x86,0x2f = cmn.w r1, r6, lsl #0xa
+0x11,0xeb,0x96,0x2f = cmn.w r1, r6, lsr #0xa
+0x1d,0xeb,0x96,0x2f = cmn.w sp, r6, lsr #0xa
+0x11,0xeb,0xa6,0x2f = cmn.w r1, r6, asr #0xa
+0x11,0xeb,0xb6,0x2f = cmn.w r1, r6, ror #0xa
+0xb5,0xf5,0x7f,0x4f = cmp.w r5, #0xff00
 0xb4,0xeb,0x0c,0x0f = cmp.w r4, r12
-0xb9,0xeb,0x06,0x3f = cmp.w r9, r6, lsl #12
-0xb3,0xeb,0xd7,0x7f = cmp.w r3, r7, lsr #31
+0xb9,0xeb,0x06,0x3f = cmp.w r9, r6, lsl #0xc
+0xb3,0xeb,0xd7,0x7f = cmp.w r3, r7, lsr #0x1f
 0xbd,0xeb,0x56,0x0f = cmp.w sp, r6, lsr #1
-0xb2,0xeb,0x25,0x6f = cmp.w r2, r5, asr #24
-0xb1,0xeb,0xf4,0x3f = cmp.w r1, r4, ror #15
+0xb2,0xeb,0x25,0x6f = cmp.w r2, r5, asr #0x18
+0xb1,0xeb,0xf4,0x3f = cmp.w r1, r4, ror #0xf
 0x12,0xf1,0x02,0x0f = cmn.w r2, #2
 0xb9,0xf1,0x01,0x0f = cmp.w r9, #1
 0x61,0xb6 = cpsie f
@@ -132,13 +165,16 @@
 0xaf,0xf3,0x80,0x86 = cpsid.w a
 0xaf,0xf3,0x43,0x85 = cpsie i, #3
 0xaf,0xf3,0x43,0x85 = cpsie i, #3
-0xaf,0xf3,0x29,0x87 = cpsid f, #9
-0xaf,0xf3,0x29,0x87 = cpsid f, #9
+0xaf,0xf3,0x29,0x87 = cpsid f, #0x9
+0xaf,0xf3,0x29,0x87 = cpsid f, #0x9
 0xaf,0xf3,0x00,0x81 = cps #0
 0xaf,0xf3,0x00,0x81 = cps #0
 0xaf,0xf3,0xf5,0x80 = dbg #5
 0xaf,0xf3,0xf0,0x80 = dbg #0
-0xaf,0xf3,0xff,0x80 = dbg #15
+0xaf,0xf3,0xff,0x80 = dbg #0xf
+0xaf,0xf3,0xf0,0x80 = dbg #0
+0x18,0xbf = it ne
+0xaf,0xf3,0xf0,0x80 = dbgne #0
 0xbf,0xf3,0x5f,0x8f = dmb sy
 0xbf,0xf3,0x5e,0x8f = dmb st
 0xbf,0xf3,0x5d,0x8f = dmb #0xd
@@ -156,6 +192,7 @@
 0xbf,0xf3,0x51,0x8f = dmb #0x1
 0xbf,0xf3,0x50,0x8f = dmb #0x0
 0xbf,0xf3,0x5f,0x8f = dmb sy
+0xbf,0xf3,0x5f,0x8f = dmb sy
 0xbf,0xf3,0x5e,0x8f = dmb st
 0xbf,0xf3,0x5b,0x8f = dmb ish
 0xbf,0xf3,0x5b,0x8f = dmb ish
@@ -168,9 +205,11 @@
 0xbf,0xf3,0x53,0x8f = dmb osh
 0xbf,0xf3,0x52,0x8f = dmb oshst
 0xbf,0xf3,0x5f,0x8f = dmb sy
+0xbf,0xf3,0x5f,0x8f = dmb sy
 0xbf,0xf3,0x4f,0x8f = dsb sy
 0xbf,0xf3,0x4e,0x8f = dsb st
 0xbf,0xf3,0x4d,0x8f = dsb #0xd
+0xbf,0xf3,0x4c,0x8f = dsb #0xc
 0xbf,0xf3,0x4b,0x8f = dsb ish
 0xbf,0xf3,0x4a,0x8f = dsb ishst
 0xbf,0xf3,0x49,0x8f = dsb #0x9
@@ -178,11 +217,12 @@
 0xbf,0xf3,0x47,0x8f = dsb nsh
 0xbf,0xf3,0x46,0x8f = dsb nshst
 0xbf,0xf3,0x45,0x8f = dsb #0x5
-0xbf,0xf3,0x44,0x8f = dsb #0x4
+0xbf,0xf3,0x44,0x8f = pssbb
 0xbf,0xf3,0x43,0x8f = dsb osh
 0xbf,0xf3,0x42,0x8f = dsb oshst
 0xbf,0xf3,0x41,0x8f = dsb #0x1
-0xbf,0xf3,0x40,0x8f = dsb #0x0
+0xbf,0xf3,0x40,0x8f = ssbb
+0xbf,0xf3,0x4f,0x8f = dsb sy
 0xbf,0xf3,0x4f,0x8f = dsb sy
 0xbf,0xf3,0x4e,0x8f = dsb st
 0xbf,0xf3,0x4b,0x8f = dsb ish
@@ -196,7 +236,8 @@
 0xbf,0xf3,0x43,0x8f = dsb osh
 0xbf,0xf3,0x42,0x8f = dsb oshst
 0xbf,0xf3,0x4f,0x8f = dsb sy
-0x85,0xf4,0x70,0x44 = eor r4, r5, #61440
+0xbf,0xf3,0x4f,0x8f = dsb sy
+0x85,0xf4,0x70,0x44 = eor r4, r5, #0xf000
 0x85,0xea,0x06,0x04 = eor.w r4, r5, r6
 0x85,0xea,0x46,0x14 = eor.w r4, r5, r6, lsl #5
 0x85,0xea,0x56,0x14 = eor.w r4, r5, r6, lsr #5
@@ -206,39 +247,43 @@
 0xbf,0xf3,0x6f,0x8f = isb sy
 0xbf,0xf3,0x6f,0x8f = isb sy
 0xbf,0xf3,0x6f,0x8f = isb sy
+0xbf,0xf3,0x6f,0x8f = isb sy
+0xbf,0xf3,0x6f,0x8f = isb sy
 0xbf,0xf3,0x61,0x8f = isb #0x1
 0x0d,0xbf = iteet eq
-// 0x88,0x18 = addeq r0, r1, r2
-// 0x00,0xbf = nopne 
-// 0xf5,0x1b = subne r5, r6, r7
+0x88,0x18 = addeq r0, r1, r2
+0x00,0xbf = nopne
+0xf5,0x1b = subne r5, r6, r7
+0x11,0x1d = addeq r1, r2, #4
 0x0d,0xbf = iteet eq
-// 0x88,0x18 = addeq r0, r1, r2
-// 0x00,0xbf = nopne 
-// 0xf5,0x1b = subne r5, r6, r7
+0x88,0x18 = addeq r0, r1, r2
+0x00,0xbf = nopne
+0xf5,0x1b = subne r5, r6, r7
+0x11,0x1d = addeq r1, r2, #4
 0x91,0xfd,0x01,0x80 = ldc2 p0, c8, [r1, #4]
 0x92,0xfd,0x00,0x71 = ldc2 p1, c7, [r2]
-0x13,0xfd,0x38,0x62 = ldc2 p2, c6, [r3, #-224]
-0x34,0xfd,0x1e,0x53 = ldc2 p3, c5, [r4, #-120]!
-0xb5,0xfc,0x04,0x44 = ldc2 p4, c4, [r5], #16
-0x36,0xfc,0x12,0x35 = ldc2 p5, c3, [r6], #-72
+0x13,0xfd,0x38,0x62 = ldc2 p2, c6, [r3, #-0xe0]
+0x34,0xfd,0x1e,0x53 = ldc2 p3, c5, [r4, #-0x78]!
+0xb5,0xfc,0x04,0x44 = ldc2 p4, c4, [r5], #0x10
+0x36,0xfc,0x12,0x35 = ldc2 p5, c3, [r6], #-0x48
 0xd7,0xfd,0x01,0x26 = ldc2l p6, c2, [r7, #4]
 0xd8,0xfd,0x00,0x17 = ldc2l p7, c1, [r8]
-0x59,0xfd,0x38,0x08 = ldc2l p8, c0, [r9, #-224]
-0x7a,0xfd,0x1e,0x19 = ldc2l p9, c1, [r10, #-120]!
-0xfb,0xfc,0x04,0x20 = ldc2l p0, c2, [r11], #16
-0x7c,0xfc,0x12,0x31 = ldc2l p1, c3, [r12], #-72
+0x59,0xfd,0x38,0x08 = ldc2l p8, c0, [r9, #-0xe0]
+0x7a,0xfd,0x1e,0x19 = ldc2l p9, c1, [r10, #-0x78]!
+0xfb,0xfc,0x04,0x20 = ldc2l p0, c2, [r11], #0x10
+0x7c,0xfc,0x12,0x31 = ldc2l p1, c3, [r12], #-0x48
 0x90,0xed,0x01,0x4c = ldc p12, c4, [r0, #4]
 0x91,0xed,0x00,0x5d = ldc p13, c5, [r1]
-0x12,0xed,0x38,0x6e = ldc p14, c6, [r2, #-224]
-0x33,0xed,0x1e,0x7f = ldc p15, c7, [r3, #-120]!
-0xb4,0xec,0x04,0x85 = ldc p5, c8, [r4], #16
-0x35,0xec,0x12,0x94 = ldc p4, c9, [r5], #-72
+0x12,0xed,0x38,0x6e = ldc p14, c6, [r2, #-0xe0]
+0x33,0xed,0x1e,0x7f = ldc p15, c7, [r3, #-0x78]!
+0xb4,0xec,0x04,0x85 = ldc p5, c8, [r4], #0x10
+0x35,0xec,0x12,0x94 = ldc p4, c9, [r5], #-0x48
 0xd6,0xed,0x01,0xa3 = ldcl p3, c10, [r6, #4]
 0xd7,0xed,0x00,0xb2 = ldcl p2, c11, [r7]
-0x58,0xed,0x38,0xc1 = ldcl p1, c12, [r8, #-224]
-0x79,0xed,0x1e,0xd0 = ldcl p0, c13, [r9, #-120]!
-0xfa,0xec,0x04,0xe6 = ldcl p6, c14, [r10], #16
-0x7b,0xec,0x12,0xf7 = ldcl p7, c15, [r11], #-72
+0x58,0xed,0x38,0xc1 = ldcl p1, c12, [r8, #-0xe0]
+0x79,0xed,0x1e,0xd0 = ldcl p0, c13, [r9, #-0x78]!
+0xfa,0xec,0x04,0xe6 = ldcl p6, c14, [r10], #0x10
+0x7b,0xec,0x12,0xf7 = ldcl p7, c15, [r11], #-0x48
 0x91,0xfc,0x19,0x82 = ldc2 p2, c8, [r1], {25}
 0x94,0xe8,0x30,0x03 = ldm.w r4, {r4, r5, r8, r9}
 0x94,0xe8,0x60,0x00 = ldm.w r4, {r5, r6}
@@ -263,28 +308,29 @@
 0x14,0xe9,0x60,0x00 = ldmdb r4, {r5, r6}
 0x35,0xe9,0x08,0x01 = ldmdb r5!, {r3, r8}
 0x55,0xf8,0x04,0x5c = ldr r5, [r5, #-4]
-0x35,0x6a = ldr r5, [r6, #32]
-0xd6,0xf8,0x21,0x50 = ldr.w r5, [r6, #33]
-0xd6,0xf8,0x01,0x51 = ldr.w r5, [r6, #257]
-0xd7,0xf8,0x01,0xf1 = ldr.w pc, [r7, #257]
-0x54,0xf8,0xff,0x2f = ldr r2, [r4, #255]!
+0x35,0x6a = ldr r5, [r6, #0x20]
+0xd6,0xf8,0x21,0x50 = ldr.w r5, [r6, #0x21]
+0xd6,0xf8,0x01,0x51 = ldr.w r5, [r6, #0x101]
+0xd7,0xf8,0x01,0xf1 = ldr.w pc, [r7, #0x101]
+0x54,0xf8,0xff,0x2f = ldr r2, [r4, #0xff]!
 0x5d,0xf8,0x04,0x8f = ldr r8, [sp, #4]!
 0x5d,0xf8,0x04,0xed = ldr lr, [sp, #-4]!
-0x54,0xf8,0xff,0x2b = ldr r2, [r4], #255
+0x54,0xf8,0xff,0x2b = ldr r2, [r4], #0xff
 0x5d,0xf8,0x04,0x8b = ldr r8, [sp], #4
 0x5d,0xf8,0x04,0xe9 = ldr lr, [sp], #-4
 0x02,0x4f = ldr r7, [pc, #8]
 0x02,0x4f = ldr r7, [pc, #8]
 0xdf,0xf8,0x08,0x70 = ldr.w r7, [pc, #8]
-0xff,0x4c = ldr r4, [pc, #1020]
-0x5f,0xf8,0xfc,0x33 = ldr.w r3, [pc, #-1020]
-0xdf,0xf8,0x00,0x64 = ldr.w r6, [pc, #1024]
-0x5f,0xf8,0x00,0x04 = ldr.w r0, [pc, #-1024]
-0xdf,0xf8,0xff,0x2f = ldr.w r2, [pc, #4095]
-0x5f,0xf8,0xff,0x1f = ldr.w r1, [pc, #-4095]
-0xdf,0xf8,0x84,0x80 = ldr.w r8, [pc, #132]
-0xdf,0xf8,0x00,0xf1 = ldr.w pc, [pc, #256]
-0x5f,0xf8,0x90,0xf1 = ldr.w pc, [pc, #-400]
+0xff,0x4c = ldr r4, [pc, #0x3fc]
+0x5f,0xf8,0xfc,0x33 = ldr.w r3, [pc, #-0x3fc]
+0xdf,0xf8,0x00,0x64 = ldr.w r6, [pc, #0x400]
+0x5f,0xf8,0x00,0x04 = ldr.w r0, [pc, #-0x400]
+0xdf,0xf8,0xff,0x2f = ldr.w r2, [pc, #0xfff]
+0x5f,0xf8,0xff,0x1f = ldr.w r1, [pc, #-0xfff]
+0xdf,0xf8,0x84,0x80 = ldr.w r8, [pc, #0x84]
+0xdf,0xf8,0x00,0xf1 = ldr.w pc, [pc, #0x100]
+0x5f,0xf8,0x90,0xf1 = ldr.w pc, [pc, #-0x190]
+0xdf,0xf8,0x04,0xd0 = ldr.w sp, [pc, #4]
 0x1f,0xf8,0x00,0x90 = ldrb.w r9, [pc, #-0]
 0x1f,0xf9,0x00,0xb0 = ldrsb.w r11, [pc, #-0]
 0x3f,0xf8,0x00,0xa0 = ldrh.w r10, [pc, #-0]
@@ -297,14 +343,14 @@
 0x5d,0xf8,0x12,0x70 = ldr.w r7, [sp, r2, lsl #1]
 0x5d,0xf8,0x02,0x70 = ldr.w r7, [sp, r2]
 0x15,0xf8,0x04,0x5c = ldrb r5, [r5, #-4]
-0x96,0xf8,0x20,0x50 = ldrb.w r5, [r6, #32]
-0x96,0xf8,0x21,0x50 = ldrb.w r5, [r6, #33]
-0x96,0xf8,0x01,0x51 = ldrb.w r5, [r6, #257]
-0x97,0xf8,0x01,0xe1 = ldrb.w lr, [r7, #257]
-0x18,0xf8,0xff,0x5f = ldrb r5, [r8, #255]!
+0x96,0xf8,0x20,0x50 = ldrb.w r5, [r6, #0x20]
+0x96,0xf8,0x21,0x50 = ldrb.w r5, [r6, #0x21]
+0x96,0xf8,0x01,0x51 = ldrb.w r5, [r6, #0x101]
+0x97,0xf8,0x01,0xe1 = ldrb.w lr, [r7, #0x101]
+0x18,0xf8,0xff,0x5f = ldrb r5, [r8, #0xff]!
 0x15,0xf8,0x04,0x2f = ldrb r2, [r5, #4]!
 0x14,0xf8,0x04,0x1d = ldrb r1, [r4, #-4]!
-0x13,0xf8,0xff,0xeb = ldrb lr, [r3], #255
+0x13,0xf8,0xff,0xeb = ldrb lr, [r3], #0xff
 0x12,0xf8,0x04,0x9b = ldrb r9, [r2], #4
 0x1d,0xf8,0x04,0x39 = ldrb r3, [sp], #-4
 0x18,0xf8,0x01,0x10 = ldrb.w r1, [r8, r1]
@@ -316,9 +362,9 @@
 0x12,0xf8,0x00,0x1e = ldrbt r1, [r2]
 0x18,0xf8,0x00,0x1e = ldrbt r1, [r8]
 0x18,0xf8,0x03,0x1e = ldrbt r1, [r8, #3]
-0x18,0xf8,0xff,0x1e = ldrbt r1, [r8, #255]
-0xd6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #24]
-0xf6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #24]!
+0x18,0xf8,0xff,0x1e = ldrbt r1, [r8, #0xff]
+0xd6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #0x18]
+0xf6,0xe9,0x06,0x35 = ldrd r3, r5, [r6, #0x18]!
 0xf6,0xe8,0x01,0x35 = ldrd r3, r5, [r6], #4
 0x76,0xe8,0x02,0x35 = ldrd r3, r5, [r6], #-8
 0xd6,0xe9,0x00,0x35 = ldrd r3, r5, [r6]
@@ -328,19 +374,19 @@
 0x72,0xe8,0x00,0x01 = ldrd r0, r1, [r2], #-0
 0x54,0xe8,0x00,0x1f = ldrex r1, [r4]
 0x54,0xe8,0x00,0x8f = ldrex r8, [r4]
-0x5d,0xe8,0x20,0x2f = ldrex r2, [sp, #128]
+0x5d,0xe8,0x20,0x2f = ldrex r2, [sp, #0x80]
 0xd7,0xe8,0x4f,0x5f = ldrexb r5, [r7]
 0xdc,0xe8,0x5f,0x9f = ldrexh r9, [r12]
 0xd4,0xe8,0x7f,0x93 = ldrexd r9, r3, [r4]
 0x35,0xf8,0x04,0x5c = ldrh r5, [r5, #-4]
-0x35,0x8c = ldrh r5, [r6, #32]
-0xb6,0xf8,0x21,0x50 = ldrh.w r5, [r6, #33]
-0xb6,0xf8,0x01,0x51 = ldrh.w r5, [r6, #257]
-0xb7,0xf8,0x01,0xe1 = ldrh.w lr, [r7, #257]
-0x38,0xf8,0xff,0x5f = ldrh r5, [r8, #255]!
+0x35,0x8c = ldrh r5, [r6, #0x20]
+0xb6,0xf8,0x21,0x50 = ldrh.w r5, [r6, #0x21]
+0xb6,0xf8,0x01,0x51 = ldrh.w r5, [r6, #0x101]
+0xb7,0xf8,0x01,0xe1 = ldrh.w lr, [r7, #0x101]
+0x38,0xf8,0xff,0x5f = ldrh r5, [r8, #0xff]!
 0x35,0xf8,0x04,0x2f = ldrh r2, [r5, #4]!
 0x34,0xf8,0x04,0x1d = ldrh r1, [r4, #-4]!
-0x33,0xf8,0xff,0xeb = ldrh lr, [r3], #255
+0x33,0xf8,0xff,0xeb = ldrh lr, [r3], #0xff
 0x32,0xf8,0x04,0x9b = ldrh r9, [r2], #4
 0x3d,0xf8,0x04,0x39 = ldrh r3, [sp], #-4
 0x38,0xf8,0x01,0x10 = ldrh.w r1, [r8, r1]
@@ -352,74 +398,82 @@
 0x32,0xf8,0x00,0x1e = ldrht r1, [r2]
 0x38,0xf8,0x00,0x1e = ldrht r1, [r8]
 0x38,0xf8,0x03,0x1e = ldrht r1, [r8, #3]
-0x38,0xf8,0xff,0x1e = ldrht r1, [r8, #255]
+0x38,0xf8,0xff,0x1e = ldrht r1, [r8, #0xff]
 0x15,0xf9,0x04,0x5c = ldrsb r5, [r5, #-4]
-0x96,0xf9,0x20,0x50 = ldrsb.w r5, [r6, #32]
-0x96,0xf9,0x21,0x50 = ldrsb.w r5, [r6, #33]
-0x96,0xf9,0x01,0x51 = ldrsb.w r5, [r6, #257]
-0x97,0xf9,0x01,0xe1 = ldrsb.w lr, [r7, #257]
+0x96,0xf9,0x20,0x50 = ldrsb.w r5, [r6, #0x20]
+0x96,0xf9,0x21,0x50 = ldrsb.w r5, [r6, #0x21]
+0x96,0xf9,0x01,0x51 = ldrsb.w r5, [r6, #0x101]
+0x97,0xf9,0x01,0xe1 = ldrsb.w lr, [r7, #0x101]
 0x18,0xf9,0x01,0x10 = ldrsb.w r1, [r8, r1]
 0x15,0xf9,0x02,0x40 = ldrsb.w r4, [r5, r2]
 0x10,0xf9,0x32,0x60 = ldrsb.w r6, [r0, r2, lsl #3]
 0x18,0xf9,0x22,0x80 = ldrsb.w r8, [r8, r2, lsl #2]
 0x1d,0xf9,0x12,0x70 = ldrsb.w r7, [sp, r2, lsl #1]
 0x1d,0xf9,0x02,0x70 = ldrsb.w r7, [sp, r2]
-0x18,0xf9,0xff,0x5f = ldrsb r5, [r8, #255]!
+0x18,0xf9,0xff,0x5f = ldrsb r5, [r8, #0xff]!
 0x15,0xf9,0x04,0x2f = ldrsb r2, [r5, #4]!
 0x14,0xf9,0x04,0x1d = ldrsb r1, [r4, #-4]!
-0x13,0xf9,0xff,0xeb = ldrsb lr, [r3], #255
+0x13,0xf9,0xff,0xeb = ldrsb lr, [r3], #0xff
 0x12,0xf9,0x04,0x9b = ldrsb r9, [r2], #4
 0x1d,0xf9,0x04,0x39 = ldrsb r3, [sp], #-4
 0x12,0xf9,0x00,0x1e = ldrsbt r1, [r2]
 0x18,0xf9,0x00,0x1e = ldrsbt r1, [r8]
 0x18,0xf9,0x03,0x1e = ldrsbt r1, [r8, #3]
-0x18,0xf9,0xff,0x1e = ldrsbt r1, [r8, #255]
+0x18,0xf9,0xff,0x1e = ldrsbt r1, [r8, #0xff]
 0x35,0xf9,0x04,0x5c = ldrsh r5, [r5, #-4]
-0xb6,0xf9,0x20,0x50 = ldrsh.w r5, [r6, #32]
-0xb6,0xf9,0x21,0x50 = ldrsh.w r5, [r6, #33]
-0xb6,0xf9,0x01,0x51 = ldrsh.w r5, [r6, #257]
-0xb7,0xf9,0x01,0xe1 = ldrsh.w lr, [r7, #257]
+0xb6,0xf9,0x20,0x50 = ldrsh.w r5, [r6, #0x20]
+0xb6,0xf9,0x21,0x50 = ldrsh.w r5, [r6, #0x21]
+0xb6,0xf9,0x01,0x51 = ldrsh.w r5, [r6, #0x101]
+0xb7,0xf9,0x01,0xe1 = ldrsh.w lr, [r7, #0x101]
 0x38,0xf9,0x01,0x10 = ldrsh.w r1, [r8, r1]
 0x35,0xf9,0x02,0x40 = ldrsh.w r4, [r5, r2]
 0x30,0xf9,0x32,0x60 = ldrsh.w r6, [r0, r2, lsl #3]
 0x38,0xf9,0x22,0x80 = ldrsh.w r8, [r8, r2, lsl #2]
 0x3d,0xf9,0x12,0x70 = ldrsh.w r7, [sp, r2, lsl #1]
 0x3d,0xf9,0x02,0x70 = ldrsh.w r7, [sp, r2]
-0x38,0xf9,0xff,0x5f = ldrsh r5, [r8, #255]!
+0x38,0xf9,0xff,0x5f = ldrsh r5, [r8, #0xff]!
 0x35,0xf9,0x04,0x2f = ldrsh r2, [r5, #4]!
 0x34,0xf9,0x04,0x1d = ldrsh r1, [r4, #-4]!
-0x33,0xf9,0xff,0xeb = ldrsh lr, [r3], #255
+0x33,0xf9,0xff,0xeb = ldrsh lr, [r3], #0xff
 0x32,0xf9,0x04,0x9b = ldrsh r9, [r2], #4
 0x3d,0xf9,0x04,0x39 = ldrsh r3, [sp], #-4
 0x32,0xf9,0x00,0x1e = ldrsht r1, [r2]
 0x38,0xf9,0x00,0x1e = ldrsht r1, [r8]
 0x38,0xf9,0x03,0x1e = ldrsht r1, [r8, #3]
-0x38,0xf9,0xff,0x1e = ldrsht r1, [r8, #255]
+0x38,0xf9,0xff,0x1e = ldrsht r1, [r8, #0xff]
 0x52,0xf8,0x00,0x1e = ldrt r1, [r2]
 0x56,0xf8,0x00,0x2e = ldrt r2, [r6]
 0x57,0xf8,0x03,0x3e = ldrt r3, [r7, #3]
-0x59,0xf8,0xff,0x4e = ldrt r4, [r9, #255]
-0x4f,0xea,0x03,0x32 = lsl.w r2, r3, #12
-0x5f,0xea,0xc3,0x78 = lsls.w r8, r3, #31
+0x59,0xf8,0xff,0x4e = ldrt r4, [r9, #0xff]
+0x4f,0xea,0x03,0x32 = lsl.w r2, r3, #0xc
+0x5f,0xea,0xc3,0x78 = lsls.w r8, r3, #0x1f
 0x5f,0xea,0x43,0x02 = lsls.w r2, r3, #1
 0x4f,0xea,0x03,0x12 = lsl.w r2, r3, #4
-0x5f,0xea,0xcc,0x32 = lsls.w r2, r12, #15
-0x4f,0xea,0xc3,0x43 = lsl.w r3, r3, #19
+0x5f,0xea,0xcc,0x32 = lsls.w r2, r12, #0xf
+0x4f,0xea,0xc3,0x43 = lsl.w r3, r3, #0x13
 0x5f,0xea,0x88,0x08 = lsls.w r8, r8, #2
 0x5f,0xea,0x47,0x17 = lsls.w r7, r7, #5
-0x4f,0xea,0x4c,0x5c = lsl.w r12, r12, #21
+0x4f,0xea,0x4c,0x5c = lsl.w r12, r12, #0x15
+0x51,0x00 = lsls r1, r2, #1
+0x04,0xbf = itt eq
+0x5f,0xea,0x42,0x01 = lslseq.w r1, r2, #1
+0x51,0x00 = lsleq r1, r2, #1
 0x04,0xfa,0x02,0xf3 = lsl.w r3, r4, r2
 0x01,0xfa,0x02,0xf1 = lsl.w r1, r1, r2
 0x14,0xfa,0x08,0xf3 = lsls.w r3, r4, r8
-0x4f,0xea,0x13,0x32 = lsr.w r2, r3, #12
-0x5f,0xea,0x13,0x08 = lsrs.w r8, r3, #32
+0x4f,0xea,0x13,0x32 = lsr.w r2, r3, #0xc
+0x5f,0xea,0x13,0x08 = lsrs.w r8, r3, #0x20
 0x5f,0xea,0x53,0x02 = lsrs.w r2, r3, #1
 0x4f,0xea,0x13,0x12 = lsr.w r2, r3, #4
-0x5f,0xea,0xdc,0x32 = lsrs.w r2, r12, #15
-0x4f,0xea,0xd3,0x43 = lsr.w r3, r3, #19
+0x5f,0xea,0xdc,0x32 = lsrs.w r2, r12, #0xf
+0x4f,0xea,0xd3,0x43 = lsr.w r3, r3, #0x13
 0x5f,0xea,0x98,0x08 = lsrs.w r8, r8, #2
 0x5f,0xea,0x57,0x17 = lsrs.w r7, r7, #5
-0x4f,0xea,0x5c,0x5c = lsr.w r12, r12, #21
+0x4f,0xea,0x5c,0x5c = lsr.w r12, r12, #0x15
+0x51,0x08 = lsrs r1, r2, #1
+0x04,0xbf = itt eq
+0x5f,0xea,0x52,0x01 = lsrseq.w r1, r2, #1
+0x51,0x08 = lsreq r1, r2, #1
 0x24,0xfa,0x02,0xf3 = lsr.w r3, r4, r2
 0x21,0xfa,0x02,0xf1 = lsr.w r1, r1, r2
 0x34,0xfa,0x08,0xf3 = lsrs.w r3, r4, r8
@@ -427,55 +481,75 @@
 0x21,0xfe,0x91,0x57 = mcr2 p7, #1, r5, c1, c1, #4
 0x00,0xee,0x15,0x4e = mcr p14, #0, r4, c0, c5, #0
 0x41,0xfe,0x13,0x24 = mcr2 p4, #2, r2, c1, c3, #0
-0x44,0xec,0xf1,0x57 = mcrr p7, #15, r5, r4, c1
-0x44,0xfc,0xf1,0x57 = mcrr2 p7, #15, r5, r4, c1
+0x21,0xee,0x91,0x57 = mcr p7, #1, r5, c1, c1, #4
+0x21,0xfe,0x91,0x57 = mcr2 p7, #1, r5, c1, c1, #4
+0x00,0xee,0x15,0x4e = mcr p14, #0, r4, c0, c5, #0
+0x41,0xfe,0x13,0x24 = mcr2 p4, #2, r2, c1, c3, #0
+0x44,0xec,0xf1,0x57 = mcrr p7, #0xf, r5, r4, c1
+0x44,0xfc,0xf1,0x57 = mcrr2 p7, #0xf, r5, r4, c1
+0x44,0xec,0xf1,0x57 = mcrr p7, #0xf, r5, r4, c1
+0x44,0xfc,0xf1,0x57 = mcrr2 p7, #0xf, r5, r4, c1
 0x02,0xfb,0x03,0x41 = mla r1, r2, r3, r4
 0x02,0xfb,0x13,0x41 = mls r1, r2, r3, r4
-0x15,0x21 = movs r1, #21
-0x5f,0xf0,0x15,0x01 = movs.w r1, #21
-0x5f,0xf0,0x15,0x08 = movs.w r8, #21
-0x4f,0xf6,0xff,0x70 = movw r0, #65535
-0x4a,0xf6,0x01,0x31 = movw r1, #43777
-0x4a,0xf6,0x10,0x31 = movw r1, #43792
-0x4f,0xf0,0x7f,0x70 = mov.w r0, #66846720
-0x4f,0xf0,0x7f,0x70 = mov.w r0, #66846720
-0x5f,0xf0,0x7f,0x70 = movs.w r0, #66846720
+0x15,0x21 = movs r1, #0x15
+0x5f,0xf0,0x15,0x01 = movs.w r1, #0x15
+0x5f,0xf0,0x15,0x08 = movs.w r8, #0x15
+0x4f,0xf6,0xff,0x70 = movw r0, #0xffff
+0x4a,0xf6,0x01,0x31 = movw r1, #0xab01
+0x4a,0xf6,0x10,0x31 = movw r1, #0xab10
+0x4f,0xf0,0x7f,0x70 = mov.w r0, #0x3fc0000
+0x4f,0xf0,0x7f,0x70 = mov.w r0, #0x3fc0000
+0x5f,0xf0,0x7f,0x70 = movs.w r0, #0x3fc0000
 0x06,0xbf = itte eq
-// 0x5f,0xf0,0x0c,0x01 = movseq.w r1, #12
-// 0x0c,0x21 = moveq r1, #12
-// 0x4f,0xf0,0x0c,0x01 = movne.w r1, #12
-0x4f,0xf4,0xe1,0x76 = mov.w r6, #450
+0x5f,0xf0,0x0c,0x01 = movseq.w r1, #0xc
+0x0c,0x21 = moveq r1, #0xc
+0x4f,0xf0,0x0c,0x01 = movne.w r1, #0xc
+0x4f,0xf4,0xe1,0x76 = mov.w r6, #0x1c2
 0x38,0xbf = it lo
-// 0x4f,0xf0,0xff,0x31 = movlo.w r1, #-1
+0x4f,0xf0,0xff,0x31 = movlo.w r1, #-1
 0x6f,0xf0,0x02,0x03 = mvn r3, #2
-0x4a,0xf6,0xcd,0x3b = movw r11, #43981
+0x4a,0xf6,0xcd,0x3b = movw r11, #0xabcd
 0x01,0x20 = movs r0, #1
 0x18,0xbf = it ne
-// 0x0f,0x23 = movne r3, #15
+0x0f,0x23 = movne r3, #0xf
 0x04,0xbf = itt eq
-// 0xff,0x20 = moveq r0, #255
-// 0x40,0xf2,0x00,0x11 = movweq r1, #256
-0x4f,0xea,0x02,0x46 = lsl.w r6, r2, #16
-0x4f,0xea,0x12,0x46 = lsr.w r6, r2, #16
-0x16,0x10 = asrs r6, r2, #32
+0xff,0x20 = moveq r0, #0xff
+0x40,0xf2,0x00,0x11 = movweq r1, #0x100
+0x4f,0xea,0x02,0x46 = lsl.w r6, r2, #0x10
+0x4f,0xea,0x02,0x46 = lsl.w r6, r2, #0x10
+0x4f,0xea,0x12,0x46 = lsr.w r6, r2, #0x10
+0x4f,0xea,0x12,0x46 = lsr.w r6, r2, #0x10
+0x16,0x10 = asrs r6, r2, #0x20
+0x5f,0xea,0x22,0x06 = asrs.w r6, r2, #0x20
 0x5f,0xea,0x72,0x16 = rors.w r6, r2, #5
-// 0xac,0x40 = lsls r4, r5
-// 0xec,0x40 = lsrs r4, r5
-// 0x2c,0x41 = asrs r4, r5
-// 0xec,0x41 = rors r4, r5
+0x5f,0xea,0x72,0x16 = rors.w r6, r2, #5
+0xac,0x40 = lsls r4, r5
+0x14,0xfa,0x05,0xf4 = lsls.w r4, r4, r5
+0xec,0x40 = lsrs r4, r5
+0x34,0xfa,0x05,0xf4 = lsrs.w r4, r4, r5
+0x2c,0x41 = asrs r4, r5
+0x54,0xfa,0x05,0xf4 = asrs.w r4, r4, r5
+0xec,0x41 = rors r4, r5
+0x74,0xfa,0x05,0xf4 = rors.w r4, r4, r5
 0x04,0xfa,0x05,0xf4 = lsl.w r4, r4, r5
 0x74,0xfa,0x08,0xf4 = rors.w r4, r4, r8
 0x35,0xfa,0x06,0xf4 = lsrs.w r4, r5, r6
 0x01,0xbf = itttt eq
-// 0xac,0x40 = lsleq r4, r5
-// 0xec,0x40 = lsreq r4, r5
-// 0x2c,0x41 = asreq r4, r5
-// 0xec,0x41 = roreq r4, r5
+0xac,0x40 = lsleq r4, r5
+0xec,0x40 = lsreq r4, r5
+0x2c,0x41 = asreq r4, r5
+0xec,0x41 = roreq r4, r5
 0x4f,0xea,0x34,0x04 = rrx r4, r4
 0xc0,0xf2,0x07,0x03 = movt r3, #7
-0xcf,0xf6,0xff,0x76 = movt r6, #65535
+0xcf,0xf6,0xff,0x76 = movt r6, #0xffff
 0x08,0xbf = it eq
-// 0xc0,0xf6,0xf0,0x74 = movteq r4, #4080
+0xc0,0xf6,0xf0,0x74 = movteq r4, #0xff0
+0x11,0xee,0x92,0x1e = mrc p14, #0, r1, c1, c2, #4
+0xff,0xee,0xd6,0xff = mrc p15, #7, apsr_nzcv, c15, c6, #6
+0x32,0xee,0x12,0x19 = mrc p9, #1, r1, c2, c2, #0
+0x73,0xfe,0x14,0x3c = mrc2 p12, #3, r3, c3, c4, #0
+0x11,0xfe,0x92,0x1e = mrc2 p14, #0, r1, c1, c2, #4
+0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1
 0x11,0xee,0x92,0x1e = mrc p14, #0, r1, c1, c2, #4
 0xff,0xee,0xd6,0xff = mrc p15, #7, apsr_nzcv, c15, c6, #6
 0x32,0xee,0x12,0x19 = mrc p9, #1, r1, c2, c2, #0
@@ -484,60 +558,66 @@
 0xff,0xfe,0x30,0xf8 = mrc2 p8, #7, apsr_nzcv, c15, c0, #1
 0x54,0xec,0x11,0x57 = mrrc p7, #1, r5, r4, c1
 0x54,0xfc,0x11,0x57 = mrrc2 p7, #1, r5, r4, c1
+0x54,0xec,0x11,0x57 = mrrc p7, #1, r5, r4, c1
+0x54,0xfc,0x11,0x57 = mrrc2 p7, #1, r5, r4, c1
 0xef,0xf3,0x00,0x88 = mrs r8, apsr
 0xef,0xf3,0x00,0x88 = mrs r8, apsr
 0xff,0xf3,0x00,0x88 = mrs r8, spsr
-0x81,0xf3,0x00,0x88 = msr apsr_nzcvq, r1
-0x82,0xf3,0x00,0x84 = msr apsr_g, r2
-0x83,0xf3,0x00,0x88 = msr apsr_nzcvq, r3
-0x84,0xf3,0x00,0x88 = msr apsr_nzcvq, r4
-0x85,0xf3,0x00,0x8c = msr apsr_nzcvqg, r5
-0x86,0xf3,0x00,0x89 = msr cpsr_fc, r6
-0x87,0xf3,0x00,0x81 = msr cpsr_c, r7
-0x88,0xf3,0x00,0x82 = msr cpsr_x, r8
-0x89,0xf3,0x00,0x89 = msr cpsr_fc, r9
-0x8b,0xf3,0x00,0x89 = msr cpsr_fc, r11
-0x8c,0xf3,0x00,0x8e = msr cpsr_fsx, r12
-0x90,0xf3,0x00,0x89 = msr spsr_fc, r0
-0x95,0xf3,0x00,0x8f = msr spsr_fsxc, r5
-0x88,0xf3,0x00,0x8f = msr cpsr_fsxc, r8
-0x83,0xf3,0x00,0x89 = msr cpsr_fc, r3
+0x81,0xf3,0x00,0x88 = msr APSR_nzcvq, r1
+0x82,0xf3,0x00,0x84 = msr APSR_g, r2
+0x83,0xf3,0x00,0x88 = msr APSR_nzcvq, r3
+0x84,0xf3,0x00,0x88 = msr APSR_nzcvq, r4
+0x85,0xf3,0x00,0x8c = msr APSR_nzcvqg, r5
+0x86,0xf3,0x00,0x89 = msr CPSR_fc, r6
+0x87,0xf3,0x00,0x81 = msr CPSR_c, r7
+0x88,0xf3,0x00,0x82 = msr CPSR_x, r8
+0x89,0xf3,0x00,0x89 = msr CPSR_fc, r9
+0x8b,0xf3,0x00,0x89 = msr CPSR_fc, r11
+0x8c,0xf3,0x00,0x8e = msr CPSR_fsx, r12
+0x90,0xf3,0x00,0x89 = msr SPSR_fc, r0
+0x95,0xf3,0x00,0x8f = msr SPSR_fsxc, r5
+0x88,0xf3,0x00,0x8f = msr CPSR_fsxc, r8
+0x83,0xf3,0x00,0x89 = msr CPSR_fc, r3
 0x63,0x43 = muls r3, r4, r3
 0x04,0xfb,0x03,0xf3 = mul r3, r4, r3
 0x04,0xfb,0x06,0xf3 = mul r3, r4, r6
 0x08,0xbf = it eq
-// 0x04,0xfb,0x05,0xf3 = muleq r3, r4, r5
+0x04,0xfb,0x05,0xf3 = muleq r3, r4, r5
 0xd8,0xbf = it le
-// 0x04,0xfb,0x08,0xf4 = mulle r4, r4, r8
+0x04,0xfb,0x08,0xf4 = mulle r4, r4, r8
 0x06,0xfb,0x05,0xf5 = mul r5, r6, r5
-0x7f,0xf0,0x15,0x08 = mvns r8, #21
-0x6f,0xf0,0x7f,0x70 = mvn r0, #66846720
-0x7f,0xf0,0x7f,0x70 = mvns r0, #66846720
+0x7f,0xf0,0x15,0x08 = mvns r8, #0x15
+0x6f,0xf0,0x7f,0x70 = mvn r0, #0x3fc0000
+0x7f,0xf0,0x7f,0x70 = mvns r0, #0x3fc0000
 0x06,0xbf = itte eq
-// 0x7f,0xf0,0x0c,0x01 = mvnseq r1, #12
-// 0x6f,0xf0,0x0c,0x01 = mvneq r1, #12
-// 0x6f,0xf0,0x0c,0x01 = mvnne r1, #12
+0x7f,0xf0,0x0c,0x01 = mvnseq r1, #0xc
+0x6f,0xf0,0x0c,0x01 = mvneq r1, #0xc
+0x6f,0xf0,0x0c,0x01 = mvnne r1, #0xc
 0x6f,0xea,0x03,0x02 = mvn.w r2, r3
-// 0xda,0x43 = mvns r2, r3
-0x6f,0xea,0xc6,0x45 = mvn.w r5, r6, lsl #19
-0x6f,0xea,0x56,0x25 = mvn.w r5, r6, lsr #9
+0xda,0x43 = mvns r2, r3
+0x6f,0xea,0xc6,0x45 = mvn.w r5, r6, lsl #0x13
+0x6f,0xea,0x56,0x25 = mvn.w r5, r6, lsr #0x9
 0x6f,0xea,0x26,0x15 = mvn.w r5, r6, asr #4
 0x6f,0xea,0xb6,0x15 = mvn.w r5, r6, ror #6
 0x6f,0xea,0x36,0x05 = mvn.w r5, r6, rrx
 0x08,0xbf = it eq
-// 0xda,0x43 = mvneq r2, r3
+0xda,0x43 = mvneq r2, r3
 0xc2,0xf1,0x00,0x05 = rsb.w r5, r2, #0
 0xc8,0xf1,0x00,0x05 = rsb.w r5, r8, #0
-0xaf,0xf3,0x00,0x80 = nop.w 
-0x65,0xf4,0x70,0x44 = orn r4, r5, #61440
+0xaf,0xf3,0x00,0x80 = nop.w
+0x65,0xf4,0x70,0x44 = orn r4, r5, #0xf000
+0x65,0xf4,0x70,0x44 = orn r4, r5, #0xf000
+0x65,0xea,0x06,0x04 = orn r4, r5, r6
 0x65,0xea,0x06,0x04 = orn r4, r5, r6
 0x75,0xea,0x06,0x04 = orns r4, r5, r6
+0x75,0xea,0x06,0x04 = orns r4, r5, r6
+0x65,0xea,0x46,0x14 = orn r4, r5, r6, lsl #5
 0x65,0xea,0x46,0x14 = orn r4, r5, r6, lsl #5
 0x75,0xea,0x56,0x14 = orns r4, r5, r6, lsr #5
 0x65,0xea,0x56,0x14 = orn r4, r5, r6, lsr #5
 0x75,0xea,0x66,0x14 = orns r4, r5, r6, asr #5
 0x65,0xea,0x76,0x14 = orn r4, r5, r6, ror #5
-0x45,0xf4,0x70,0x44 = orr r4, r5, #61440
+0x45,0xf4,0x70,0x44 = orr r4, r5, #0xf000
 0x45,0xea,0x06,0x04 = orr.w r4, r5, r6
 0x45,0xea,0x46,0x14 = orr.w r4, r5, r6, lsl #5
 0x55,0xea,0x56,0x14 = orrs.w r4, r5, r6, lsr #5
@@ -545,319 +625,332 @@
 0x55,0xea,0x66,0x14 = orrs.w r4, r5, r6, asr #5
 0x45,0xea,0x76,0x14 = orr.w r4, r5, r6, ror #5
 0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3
-0xc2,0xea,0xc3,0x72 = pkhbt r2, r2, r3, lsl #31
+0xc2,0xea,0xc3,0x72 = pkhbt r2, r2, r3, lsl #0x1f
 0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3
-0xc2,0xea,0xc3,0x32 = pkhbt r2, r2, r3, lsl #15
-0xc2,0xea,0x03,0x02 = pkhbt r2, r2, r3
-0xc2,0xea,0xe3,0x72 = pkhtb r2, r2, r3, asr #31
-0xc2,0xea,0xe3,0x32 = pkhtb r2, r2, r3, asr #15
+0xc2,0xea,0xc3,0x32 = pkhbt r2, r2, r3, lsl #0xf
+0xc3,0xea,0x02,0x02 = pkhbt r2, r3, r2
+0xc2,0xea,0xe3,0x72 = pkhtb r2, r2, r3, asr #0x1f
+0xc2,0xea,0xe3,0x32 = pkhtb r2, r2, r3, asr #0xf
 0x15,0xf8,0x04,0xfc = pld [r5, #-4]
-0x96,0xf8,0x20,0xf0 = pld [r6, #32]
-0x96,0xf8,0x21,0xf0 = pld [r6, #33]
-0x96,0xf8,0x01,0xf1 = pld [r6, #257]
-0x97,0xf8,0x01,0xf1 = pld [r7, #257]
+0x96,0xf8,0x20,0xf0 = pld [r6, #0x20]
+0x96,0xf8,0x21,0xf0 = pld [r6, #0x21]
+0x96,0xf8,0x01,0xf1 = pld [r6, #0x101]
+0x97,0xf8,0x01,0xf1 = pld [r7, #0x101]
 0x91,0xf8,0x00,0xf0 = pld [r1]
 0x11,0xf8,0x00,0xfc = pld [r1, #-0]
-0x1f,0xf8,0xff,0xff = pld [pc, #-4095]
+0x11,0xf8,0x00,0xfc = pld [r1, #-0]
+0x1f,0xf8,0xff,0xff = pld [pc, #-0xfff]
+0x1f,0xf8,0xff,0xff = pld [pc, #-0xfff]
 0x18,0xf8,0x01,0xf0 = pld [r8, r1]
 0x15,0xf8,0x02,0xf0 = pld [r5, r2]
+0x15,0xf8,0x02,0xf0 = pld [r5, r2]
 0x10,0xf8,0x32,0xf0 = pld [r0, r2, lsl #3]
 0x18,0xf8,0x22,0xf0 = pld [r8, r2, lsl #2]
 0x1d,0xf8,0x12,0xf0 = pld [sp, r2, lsl #1]
 0x1d,0xf8,0x02,0xf0 = pld [sp, r2]
+0x1d,0xf8,0x12,0xf0 = pld [sp, r2, lsl #1]
 0x15,0xf9,0x04,0xfc = pli [r5, #-4]
-0x96,0xf9,0x20,0xf0 = pli [r6, #32]
-0x96,0xf9,0x21,0xf0 = pli [r6, #33]
-0x96,0xf9,0x01,0xf1 = pli [r6, #257]
-0x97,0xf9,0x01,0xf1 = pli [r7, #257]
-0x9f,0xf9,0xff,0xff = pli [pc, #4095]
-0x1f,0xf9,0xff,0xff = pli [pc, #-4095]
+0x96,0xf9,0x20,0xf0 = pli [r6, #0x20]
+0x96,0xf9,0x21,0xf0 = pli [r6, #0x21]
+0x96,0xf9,0x01,0xf1 = pli [r6, #0x101]
+0x97,0xf9,0x01,0xf1 = pli [r7, #0x101]
+0x9f,0xf9,0xff,0xff = pli [pc, #0xfff]
+0x1f,0xf9,0xff,0xff = pli [pc, #-0xfff]
+0x1f,0xf9,0xff,0xff = pli [pc, #-0xfff]
 0x18,0xf9,0x01,0xf0 = pli [r8, r1]
 0x15,0xf9,0x02,0xf0 = pli [r5, r2]
+0x15,0xf9,0x02,0xf0 = pli [r5, r2]
 0x10,0xf9,0x32,0xf0 = pli [r0, r2, lsl #3]
 0x18,0xf9,0x22,0xf0 = pli [r8, r2, lsl #2]
 0x1d,0xf9,0x12,0xf0 = pli [sp, r2, lsl #1]
 0x1d,0xf9,0x02,0xf0 = pli [sp, r2]
+0x1d,0xf9,0x12,0xf0 = pli [sp, r2, lsl #1]
 0xbd,0xe8,0x04,0x02 = pop.w {r2, r9}
 0x2d,0xe9,0x04,0x02 = push.w {r2, r9}
-// 0x83,0xfa,0x82,0xf1 = qadd r1, r2, r3
-// 0x92,0xfa,0x13,0xf1 = qadd16 r1, r2, r3
-// 0x82,0xfa,0x13,0xf1 = qadd8 r1, r2, r3
+0x83,0xfa,0x82,0xf1 = qadd r1, r2, r3
+0x92,0xfa,0x13,0xf1 = qadd16 r1, r2, r3
+0x82,0xfa,0x13,0xf1 = qadd8 r1, r2, r3
 0xc6,0xbf = itte gt
-// 0x83,0xfa,0x82,0xf1 = qaddgt r1, r2, r3
-// 0x92,0xfa,0x13,0xf1 = qadd16gt r1, r2, r3
-// 0x82,0xfa,0x13,0xf1 = qadd8le r1, r2, r3
-// 0x88,0xfa,0x97,0xf6 = qdadd r6, r7, r8
-// 0x88,0xfa,0xb7,0xf6 = qdsub r6, r7, r8
+0x83,0xfa,0x82,0xf1 = qaddgt r1, r2, r3
+0x92,0xfa,0x13,0xf1 = qadd16gt r1, r2, r3
+0x82,0xfa,0x13,0xf1 = qadd8le r1, r2, r3
+0x88,0xfa,0x97,0xf6 = qdadd r6, r7, r8
+0x88,0xfa,0xb7,0xf6 = qdsub r6, r7, r8
 0x84,0xbf = itt hi
-// 0x88,0xfa,0x97,0xf6 = qdaddhi r6, r7, r8
-// 0x88,0xfa,0xb7,0xf6 = qdsubhi r6, r7, r8
-// 0xec,0xfa,0x10,0xf9 = qsax r9, r12, r0
+0x88,0xfa,0x97,0xf6 = qdaddhi r6, r7, r8
+0x88,0xfa,0xb7,0xf6 = qdsubhi r6, r7, r8
+0xec,0xfa,0x10,0xf9 = qsax r9, r12, r0
 0x08,0xbf = it eq
-// 0xec,0xfa,0x10,0xf9 = qsaxeq r9, r12, r0
-// 0x83,0xfa,0xa2,0xf1 = qsub r1, r2, r3
-// 0xd2,0xfa,0x13,0xf1 = qsub16 r1, r2, r3
-// 0xc2,0xfa,0x13,0xf1 = qsub8 r1, r2, r3
+0xec,0xfa,0x10,0xf9 = qsaxeq r9, r12, r0
+0x83,0xfa,0xa2,0xf1 = qsub r1, r2, r3
+0xd2,0xfa,0x13,0xf1 = qsub16 r1, r2, r3
+0xc2,0xfa,0x13,0xf1 = qsub8 r1, r2, r3
 0xd6,0xbf = itet le
-// 0x83,0xfa,0xa2,0xf1 = qsuble r1, r2, r3
-// 0xd2,0xfa,0x13,0xf1 = qsub16gt r1, r2, r3
-// 0xc2,0xfa,0x13,0xf1 = qsub8le r1, r2, r3
-// 0x92,0xfa,0xa2,0xf1 = rbit r1, r2
+0x83,0xfa,0xa2,0xf1 = qsuble r1, r2, r3
+0xd2,0xfa,0x13,0xf1 = qsub16gt r1, r2, r3
+0xc2,0xfa,0x13,0xf1 = qsub8le r1, r2, r3
+0x92,0xfa,0xa2,0xf1 = rbit r1, r2
 0x18,0xbf = it ne
-// 0x92,0xfa,0xa2,0xf1 = rbitne r1, r2
+0x92,0xfa,0xa2,0xf1 = rbitne r1, r2
 0x92,0xfa,0x82,0xf1 = rev.w r1, r2
 0x98,0xfa,0x88,0xf2 = rev.w r2, r8
 0x1c,0xbf = itt ne
-// 0x11,0xba = revne r1, r2
-// 0x98,0xfa,0x88,0xf1 = revne.w r1, r8
+0x11,0xba = revne r1, r2
+0x98,0xfa,0x88,0xf1 = revne.w r1, r8
 0x92,0xfa,0x92,0xf1 = rev16.w r1, r2
 0x98,0xfa,0x98,0xf2 = rev16.w r2, r8
 0x1c,0xbf = itt ne
-// 0x51,0xba = rev16ne r1, r2
-// 0x98,0xfa,0x98,0xf1 = rev16ne.w r1, r8
+0x51,0xba = rev16ne r1, r2
+0x98,0xfa,0x98,0xf1 = rev16ne.w r1, r8
 0x92,0xfa,0xb2,0xf1 = revsh.w r1, r2
 0x98,0xfa,0xb8,0xf2 = revsh.w r2, r8
 0x1c,0xbf = itt ne
-// 0xd1,0xba = revshne r1, r2
-// 0x98,0xfa,0xb8,0xf1 = revshne.w r1, r8
-0x4f,0xea,0x33,0x32 = ror.w r2, r3, #12
-0x5f,0xea,0xf3,0x78 = rors.w r8, r3, #31
+0xd1,0xba = revshne r1, r2
+0x98,0xfa,0xb8,0xf1 = revshne.w r1, r8
+0x4f,0xea,0x33,0x32 = ror.w r2, r3, #0xc
+0x5f,0xea,0xf3,0x78 = rors.w r8, r3, #0x1f
 0x5f,0xea,0x73,0x02 = rors.w r2, r3, #1
 0x4f,0xea,0x33,0x12 = ror.w r2, r3, #4
-0x5f,0xea,0xfc,0x32 = rors.w r2, r12, #15
-0x4f,0xea,0xf3,0x43 = ror.w r3, r3, #19
+0x5f,0xea,0xfc,0x32 = rors.w r2, r12, #0xf
+0x4f,0xea,0xf3,0x43 = ror.w r3, r3, #0x13
 0x5f,0xea,0xb8,0x08 = rors.w r8, r8, #2
 0x5f,0xea,0x77,0x17 = rors.w r7, r7, #5
-0x4f,0xea,0x7c,0x5c = ror.w r12, r12, #21
+0x4f,0xea,0x7c,0x5c = ror.w r12, r12, #0x15
 0x64,0xfa,0x02,0xf3 = ror.w r3, r4, r2
 0x61,0xfa,0x02,0xf1 = ror.w r1, r1, r2
 0x74,0xfa,0x08,0xf3 = rors.w r3, r4, r8
 0x4f,0xea,0x32,0x01 = rrx r1, r2
 0x5f,0xea,0x32,0x01 = rrxs r1, r2
 0xb4,0xbf = ite lt
-// 0x4f,0xea,0x3c,0x09 = rrxlt r9, r12
-// 0x5f,0xea,0x33,0x08 = rrxsge r8, r3
-0xc5,0xf5,0x7f,0x22 = rsb.w r2, r5, #1044480
-0xdc,0xf1,0x0f,0x03 = rsbs.w r3, r12, #15
-0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #255
-0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #255
+0x4f,0xea,0x3c,0x09 = rrxlt r9, r12
+0x5f,0xea,0x33,0x08 = rrxsge r8, r3
+0xc5,0xf5,0x7f,0x22 = rsb.w r2, r5, #0xff000
+0xdc,0xf1,0x0f,0x03 = rsbs.w r3, r12, #0xf
+0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #0xff
+0xc1,0xf1,0xff,0x01 = rsb.w r1, r1, #0xff
 0xcb,0xf1,0x00,0x0b = rsb.w r11, r11, #0
 0xc9,0xf1,0x00,0x09 = rsb.w r9, r9, #0
 0x4b,0x42 = rsbs r3, r1, #0
 0xc1,0xf1,0x00,0x03 = rsb.w r3, r1, #0
 0xc4,0xeb,0x08,0x04 = rsb r4, r4, r8
+0xc4,0xeb,0x08,0x04 = rsb r4, r4, r8
+0xc9,0xeb,0x08,0x04 = rsb r4, r9, r8
 0xc9,0xeb,0x08,0x04 = rsb r4, r9, r8
 0xc4,0xeb,0xe8,0x01 = rsb r1, r4, r8, asr #3
+0xc4,0xeb,0xe8,0x01 = rsb r1, r4, r8, asr #3
 0xd1,0xeb,0x47,0x02 = rsbs r2, r1, r7, lsl #1
-// 0x94,0xfa,0x08,0xf3 = sadd16 r3, r4, r8
+0xd1,0xeb,0x47,0x02 = rsbs r2, r1, r7, lsl #1
+0xd1,0xeb,0x02,0x00 = rsbs r0, r1, r2
+0xd1,0xeb,0x02,0x00 = rsbs r0, r1, r2
+0x94,0xfa,0x08,0xf3 = sadd16 r3, r4, r8
 0x18,0xbf = it ne
-// 0x94,0xfa,0x08,0xf3 = sadd16ne r3, r4, r8
-// 0x84,0xfa,0x08,0xf3 = sadd8 r3, r4, r8
+0x94,0xfa,0x08,0xf3 = sadd16ne r3, r4, r8
+0x84,0xfa,0x08,0xf3 = sadd8 r3, r4, r8
 0x18,0xbf = it ne
-// 0x84,0xfa,0x08,0xf3 = sadd8ne r3, r4, r8
+0x84,0xfa,0x08,0xf3 = sadd8ne r3, r4, r8
 0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7
 0x18,0xbf = it ne
-// 0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6
+0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6
 0xa2,0xfa,0x07,0xf9 = sasx r9, r2, r7
 0x18,0xbf = it ne
-// 0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6
+0xa5,0xfa,0x06,0xf2 = sasxne r2, r5, r6
 0x61,0xf1,0x04,0x00 = sbc r0, r1, #4
 0x71,0xf1,0x00,0x00 = sbcs r0, r1, #0
-0x62,0xf1,0xff,0x01 = sbc r1, r2, #255
-0x67,0xf1,0x55,0x13 = sbc r3, r7, #5570645
-0x6c,0xf1,0xaa,0x28 = sbc r8, r12, #2852170240
-0x67,0xf1,0xa5,0x39 = sbc r9, r7, #2779096485
-0x63,0xf1,0x07,0x45 = sbc r5, r3, #2264924160
-0x62,0xf1,0xff,0x44 = sbc r4, r2, #2139095040
-0x62,0xf5,0xd0,0x64 = sbc r4, r2, #1664
+0x62,0xf1,0xff,0x01 = sbc r1, r2, #0xff
+0x67,0xf1,0x55,0x13 = sbc r3, r7, #0x550055
+0x6c,0xf1,0xaa,0x28 = sbc r8, r12, #0xaa00aa00
+0x67,0xf1,0xa5,0x39 = sbc r9, r7, #0xa5a5a5a5
+0x63,0xf1,0x07,0x45 = sbc r5, r3, #0x87000000
+0x62,0xf1,0xff,0x44 = sbc r4, r2, #0x7f800000
+0x62,0xf5,0xd0,0x64 = sbc r4, r2, #0x680
 0x65,0xeb,0x06,0x04 = sbc.w r4, r5, r6
 0x75,0xeb,0x06,0x04 = sbcs.w r4, r5, r6
 0x61,0xeb,0x03,0x09 = sbc.w r9, r1, r3
 0x71,0xeb,0x03,0x09 = sbcs.w r9, r1, r3
 0x61,0xeb,0x33,0x10 = sbc.w r0, r1, r3, ror #4
 0x71,0xeb,0xc3,0x10 = sbcs.w r0, r1, r3, lsl #7
-0x61,0xeb,0xd3,0x70 = sbc.w r0, r1, r3, lsr #31
-0x71,0xeb,0x23,0x00 = sbcs.w r0, r1, r3, asr #32
-0x45,0xf3,0x00,0x44 = sbfx r4, r5, #16, #1
+0x61,0xeb,0xd3,0x70 = sbc.w r0, r1, r3, lsr #0x1f
+0x71,0xeb,0x23,0x00 = sbcs.w r0, r1, r3, asr #0x20
+0x45,0xf3,0x00,0x44 = sbfx r4, r5, #0x10, #1
 0xc8,0xbf = it gt
-// 0x45,0xf3,0x0f,0x44 = sbfxgt r4, r5, #16, #16
-// 0xa9,0xfa,0x82,0xf5 = sel r5, r9, r2
+0x45,0xf3,0x0f,0x44 = sbfxgt r4, r5, #0x10, #0x10
+0xa9,0xfa,0x82,0xf5 = sel r5, r9, r2
 0xd8,0xbf = it le
-// 0xa9,0xfa,0x82,0xf5 = selle r5, r9, r2
-// 0xaf,0xf3,0x04,0x80 = sev.w 
+0xa9,0xfa,0x82,0xf5 = selle r5, r9, r2
+0xaf,0xf3,0x04,0x80 = sev.w
 0x08,0xbf = it eq
-// 0xaf,0xf3,0x04,0x80 = seveq.w 
-// 0x92,0xfa,0x03,0xf1 = sadd16 r1, r2, r3
-// 0x82,0xfa,0x03,0xf1 = sadd8 r1, r2, r3
+0xaf,0xf3,0x04,0x80 = seveq.w
+0x92,0xfa,0x03,0xf1 = sadd16 r1, r2, r3
+0x82,0xfa,0x03,0xf1 = sadd8 r1, r2, r3
 0xcc,0xbf = ite gt
-// 0x92,0xfa,0x03,0xf1 = sadd16gt r1, r2, r3
-// 0x82,0xfa,0x03,0xf1 = sadd8le r1, r2, r3
-// 0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2
+0x92,0xfa,0x03,0xf1 = sadd16gt r1, r2, r3
+0x82,0xfa,0x03,0xf1 = sadd8le r1, r2, r3
+0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2
 0xc8,0xbf = it gt
-// 0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2
-// 0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2
+0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2
+0xa8,0xfa,0x22,0xf4 = shasx r4, r8, r2
 0xc8,0xbf = it gt
-// 0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2
-// 0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2
+0xa8,0xfa,0x22,0xf4 = shasxgt r4, r8, r2
+0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2
 0xc8,0xbf = it gt
-// 0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2
-// 0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2
+0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2
+0xe8,0xfa,0x22,0xf4 = shsax r4, r8, r2
 0xc8,0xbf = it gt
-// 0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2
-// 0xd8,0xfa,0x22,0xf4 = shsub16 r4, r8, r2
-// 0xc8,0xfa,0x22,0xf4 = shsub8 r4, r8, r2
+0xe8,0xfa,0x22,0xf4 = shsaxgt r4, r8, r2
+0xd8,0xfa,0x22,0xf4 = shsub16 r4, r8, r2
+0xc8,0xfa,0x22,0xf4 = shsub8 r4, r8, r2
 0xc4,0xbf = itt gt
-// 0xd8,0xfa,0x22,0xf4 = shsub16gt r4, r8, r2
-// 0xc8,0xfa,0x22,0xf4 = shsub8gt r4, r8, r2
-// 0x11,0xfb,0x09,0x03 = smlabb r3, r1, r9, r0
-// 0x16,0xfb,0x14,0x15 = smlabt r5, r6, r4, r1
-// 0x12,0xfb,0x23,0x24 = smlatb r4, r2, r3, r2
-// 0x13,0xfb,0x38,0x48 = smlatt r8, r3, r8, r4
+0xd8,0xfa,0x22,0xf4 = shsub16gt r4, r8, r2
+0xc8,0xfa,0x22,0xf4 = shsub8gt r4, r8, r2
+0x11,0xfb,0x09,0x03 = smlabb r3, r1, r9, r0
+0x16,0xfb,0x14,0x15 = smlabt r5, r6, r4, r1
+0x12,0xfb,0x23,0x24 = smlatb r4, r2, r3, r2
+0x13,0xfb,0x38,0x48 = smlatt r8, r3, r8, r4
 0xcb,0xbf = itete gt
-// 0x11,0xfb,0x09,0x03 = smlabbgt r3, r1, r9, r0
-// 0x16,0xfb,0x14,0x15 = smlabtle r5, r6, r4, r1
-// 0x12,0xfb,0x23,0x24 = smlatbgt r4, r2, r3, r2
-// 0x13,0xfb,0x38,0x48 = smlattle r8, r3, r8, r4
-// 0x23,0xfb,0x05,0x82 = smlad r2, r3, r5, r8
-// 0x23,0xfb,0x15,0x82 = smladx r2, r3, r5, r8
+0x11,0xfb,0x09,0x03 = smlabbgt r3, r1, r9, r0
+0x16,0xfb,0x14,0x15 = smlabtle r5, r6, r4, r1
+0x12,0xfb,0x23,0x24 = smlatbgt r4, r2, r3, r2
+0x13,0xfb,0x38,0x48 = smlattle r8, r3, r8, r4
+0x23,0xfb,0x05,0x82 = smlad r2, r3, r5, r8
+0x23,0xfb,0x15,0x82 = smladx r2, r3, r5, r8
 0x84,0xbf = itt hi
-// 0x23,0xfb,0x05,0x82 = smladhi r2, r3, r5, r8
-// 0x23,0xfb,0x15,0x82 = smladxhi r2, r3, r5, r8
-// 0xc5,0xfb,0x08,0x23 = smlal r2, r3, r5, r8
+0x23,0xfb,0x05,0x82 = smladhi r2, r3, r5, r8
+0x23,0xfb,0x15,0x82 = smladxhi r2, r3, r5, r8
+0xc5,0xfb,0x08,0x23 = smlal r2, r3, r5, r8
 0x08,0xbf = it eq
-// 0xc5,0xfb,0x08,0x23 = smlaleq r2, r3, r5, r8
-// 0xc9,0xfb,0x80,0x31 = smlalbb r3, r1, r9, r0
-// 0xc4,0xfb,0x91,0x56 = smlalbt r5, r6, r4, r1
-// 0xc3,0xfb,0xa2,0x42 = smlaltb r4, r2, r3, r2
-// 0xc8,0xfb,0xb4,0x83 = smlaltt r8, r3, r8, r4
+0xc5,0xfb,0x08,0x23 = smlaleq r2, r3, r5, r8
+0xc9,0xfb,0x80,0x31 = smlalbb r3, r1, r9, r0
+0xc4,0xfb,0x91,0x56 = smlalbt r5, r6, r4, r1
+0xc3,0xfb,0xa2,0x42 = smlaltb r4, r2, r3, r2
+0xc8,0xfb,0xb4,0x83 = smlaltt r8, r3, r8, r4
 0xad,0xbf = iteet ge
-// 0xc9,0xfb,0x80,0x31 = smlalbbge r3, r1, r9, r0
-// 0xc4,0xfb,0x91,0x56 = smlalbtlt r5, r6, r4, r1
-// 0xc3,0xfb,0xa2,0x42 = smlaltblt r4, r2, r3, r2
-// 0xc8,0xfb,0xb4,0x83 = smlalttge r8, r3, r8, r4
-// 0xc5,0xfb,0xc8,0x23 = smlald r2, r3, r5, r8
-// 0xc5,0xfb,0xd8,0x23 = smlaldx r2, r3, r5, r8
+0xc9,0xfb,0x80,0x31 = smlalbbge r3, r1, r9, r0
+0xc4,0xfb,0x91,0x56 = smlalbtlt r5, r6, r4, r1
+0xc3,0xfb,0xa2,0x42 = smlaltblt r4, r2, r3, r2
+0xc8,0xfb,0xb4,0x83 = smlalttge r8, r3, r8, r4
+0xc5,0xfb,0xc8,0x23 = smlald r2, r3, r5, r8
+0xc5,0xfb,0xd8,0x23 = smlaldx r2, r3, r5, r8
 0x0c,0xbf = ite eq
-// 0xc5,0xfb,0xc8,0x23 = smlaldeq r2, r3, r5, r8
-// 0xc5,0xfb,0xd8,0x23 = smlaldxne r2, r3, r5, r8
+0xc5,0xfb,0xc8,0x23 = smlaldeq r2, r3, r5, r8
+0xc5,0xfb,0xd8,0x23 = smlaldxne r2, r3, r5, r8
 0x33,0xfb,0x0a,0x82 = smlawb r2, r3, r10, r8
 0x33,0xfb,0x15,0x98 = smlawt r8, r3, r5, r9
 0x0c,0xbf = ite eq
-// 0x37,0xfb,0x05,0x82 = smlawbeq r2, r7, r5, r8
-// 0x33,0xfb,0x10,0x81 = smlawtne r1, r3, r0, r8
-// 0x43,0xfb,0x05,0x82 = smlsd r2, r3, r5, r8
-// 0x43,0xfb,0x15,0x82 = smlsdx r2, r3, r5, r8
+0x37,0xfb,0x05,0x82 = smlawbeq r2, r7, r5, r8
+0x33,0xfb,0x10,0x81 = smlawtne r1, r3, r0, r8
+0x43,0xfb,0x05,0x82 = smlsd r2, r3, r5, r8
+0x43,0xfb,0x15,0x82 = smlsdx r2, r3, r5, r8
 0xd4,0xbf = ite le
-// 0x43,0xfb,0x05,0x82 = smlsdle r2, r3, r5, r8
-// 0x43,0xfb,0x15,0x82 = smlsdxgt r2, r3, r5, r8
+0x43,0xfb,0x05,0x82 = smlsdle r2, r3, r5, r8
+0x43,0xfb,0x15,0x82 = smlsdxgt r2, r3, r5, r8
 0xd5,0xfb,0xc1,0x29 = smlsld r2, r9, r5, r1
 0xd2,0xfb,0xd8,0x4b = smlsldx r4, r11, r2, r8
 0xac,0xbf = ite ge
-// 0xd5,0xfb,0xc6,0x82 = smlsldge r8, r2, r5, r6
-// 0xd3,0xfb,0xd8,0x10 = smlsldxlt r1, r0, r3, r8
-// 0x52,0xfb,0x03,0x41 = smmla r1, r2, r3, r4
-// 0x53,0xfb,0x12,0x14 = smmlar r4, r3, r2, r1
+0xd5,0xfb,0xc6,0x82 = smlsldge r8, r2, r5, r6
+0xd3,0xfb,0xd8,0x10 = smlsldxlt r1, r0, r3, r8
+0x52,0xfb,0x03,0x41 = smmla r1, r2, r3, r4
+0x53,0xfb,0x12,0x14 = smmlar r4, r3, r2, r1
 0x34,0xbf = ite lo
-// 0x52,0xfb,0x03,0x41 = smmlalo r1, r2, r3, r4
-// 0x53,0xfb,0x12,0x14 = smmlarhs r4, r3, r2, r1
-// 0x62,0xfb,0x03,0x41 = smmls r1, r2, r3, r4
-// 0x63,0xfb,0x12,0x14 = smmlsr r4, r3, r2, r1
+0x52,0xfb,0x03,0x41 = smmlalo r1, r2, r3, r4
+0x53,0xfb,0x12,0x14 = smmlarhs r4, r3, r2, r1
+0x62,0xfb,0x03,0x41 = smmls r1, r2, r3, r4
+0x63,0xfb,0x12,0x14 = smmlsr r4, r3, r2, r1
 0x34,0xbf = ite lo
-// 0x62,0xfb,0x03,0x41 = smmlslo r1, r2, r3, r4
-// 0x63,0xfb,0x12,0x14 = smmlsrhs r4, r3, r2, r1
-// 0x53,0xfb,0x04,0xf2 = smmul r2, r3, r4
-// 0x52,0xfb,0x11,0xf3 = smmulr r3, r2, r1
+0x62,0xfb,0x03,0x41 = smmlslo r1, r2, r3, r4
+0x63,0xfb,0x12,0x14 = smmlsrhs r4, r3, r2, r1
+0x53,0xfb,0x04,0xf2 = smmul r2, r3, r4
+0x52,0xfb,0x11,0xf3 = smmulr r3, r2, r1
 0x34,0xbf = ite lo
-// 0x53,0xfb,0x04,0xf2 = smmullo r2, r3, r4
-// 0x52,0xfb,0x11,0xf3 = smmulrhs r3, r2, r1
-// 0x23,0xfb,0x04,0xf2 = smuad r2, r3, r4
-// 0x22,0xfb,0x11,0xf3 = smuadx r3, r2, r1
+0x53,0xfb,0x04,0xf2 = smmullo r2, r3, r4
+0x52,0xfb,0x11,0xf3 = smmulrhs r3, r2, r1
+0x23,0xfb,0x04,0xf2 = smuad r2, r3, r4
+0x22,0xfb,0x11,0xf3 = smuadx r3, r2, r1
 0xb4,0xbf = ite lt
-// 0x23,0xfb,0x04,0xf2 = smuadlt r2, r3, r4
-// 0x22,0xfb,0x11,0xf3 = smuadxge r3, r2, r1
+0x23,0xfb,0x04,0xf2 = smuadlt r2, r3, r4
+0x22,0xfb,0x11,0xf3 = smuadxge r3, r2, r1
 0x19,0xfb,0x00,0xf3 = smulbb r3, r9, r0
 0x14,0xfb,0x11,0xf5 = smulbt r5, r4, r1
 0x12,0xfb,0x22,0xf4 = smultb r4, r2, r2
-// 0x13,0xfb,0x34,0xf8 = smultt r8, r3, r4
+0x13,0xfb,0x34,0xf8 = smultt r8, r3, r4
 0xab,0xbf = itete ge
-// 0x19,0xfb,0x00,0xf1 = smulbbge r1, r9, r0
-// 0x16,0xfb,0x14,0xf5 = smulbtlt r5, r6, r4
-// 0x13,0xfb,0x22,0xf2 = smultbge r2, r3, r2
-// 0x13,0xfb,0x34,0xf8 = smulttlt r8, r3, r4
+0x19,0xfb,0x00,0xf1 = smulbbge r1, r9, r0
+0x16,0xfb,0x14,0xf5 = smulbtlt r5, r6, r4
+0x13,0xfb,0x22,0xf2 = smultbge r2, r3, r2
+0x13,0xfb,0x34,0xf8 = smulttlt r8, r3, r4
 0x80,0xfb,0x01,0x39 = smull r3, r9, r0, r1
 0x08,0xbf = it eq
-// 0x84,0xfb,0x05,0x83 = smulleq r8, r3, r4, r5
-// 0x39,0xfb,0x00,0xf3 = smulwb r3, r9, r0
-// 0x39,0xfb,0x12,0xf3 = smulwt r3, r9, r2
+0x84,0xfb,0x05,0x83 = smulleq r8, r3, r4, r5
+0x39,0xfb,0x00,0xf3 = smulwb r3, r9, r0
+0x39,0xfb,0x12,0xf3 = smulwt r3, r9, r2
 0xcc,0xbf = ite gt
-// 0x39,0xfb,0x00,0xf3 = smulwbgt r3, r9, r0
-// 0x39,0xfb,0x12,0xf3 = smulwtle r3, r9, r2
+0x39,0xfb,0x00,0xf3 = smulwbgt r3, r9, r0
+0x39,0xfb,0x12,0xf3 = smulwtle r3, r9, r2
 0x40,0xfb,0x01,0xf3 = smusd r3, r0, r1
 0x49,0xfb,0x12,0xf3 = smusdx r3, r9, r2
 0x0c,0xbf = ite eq
-// 0x43,0xfb,0x02,0xf8 = smusdeq r8, r3, r2
-// 0x44,0xfb,0x13,0xf7 = smusdxne r7, r4, r3
+0x43,0xfb,0x02,0xf8 = smusdeq r8, r3, r2
+0x44,0xfb,0x13,0xf7 = smusdxne r7, r4, r3
 0x0d,0xe8,0x01,0xc0 = srsdb sp, #1
 0x8d,0xe9,0x00,0xc0 = srsia sp, #0
-0x2d,0xe8,0x13,0xc0 = srsdb sp!, #19
+0x2d,0xe8,0x13,0xc0 = srsdb sp!, #0x13
 0xad,0xe9,0x02,0xc0 = srsia sp!, #2
-0x8d,0xe9,0x0a,0xc0 = srsia sp, #10
-0x0d,0xe8,0x09,0xc0 = srsdb sp, #9
+0x8d,0xe9,0x0a,0xc0 = srsia sp, #0xa
+0x0d,0xe8,0x09,0xc0 = srsdb sp, #0x9
 0xad,0xe9,0x05,0xc0 = srsia sp!, #5
 0x2d,0xe8,0x05,0xc0 = srsdb sp!, #5
 0x8d,0xe9,0x05,0xc0 = srsia sp, #5
 0xad,0xe9,0x05,0xc0 = srsia sp!, #5
 0x0d,0xe8,0x01,0xc0 = srsdb sp, #1
 0x8d,0xe9,0x00,0xc0 = srsia sp, #0
-0x2d,0xe8,0x13,0xc0 = srsdb sp!, #19
+0x2d,0xe8,0x13,0xc0 = srsdb sp!, #0x13
 0xad,0xe9,0x02,0xc0 = srsia sp!, #2
-0x8d,0xe9,0x0a,0xc0 = srsia sp, #10
-0x0d,0xe8,0x09,0xc0 = srsdb sp, #9
+0x8d,0xe9,0x0a,0xc0 = srsia sp, #0xa
+0x0d,0xe8,0x09,0xc0 = srsdb sp, #0x9
 0xad,0xe9,0x05,0xc0 = srsia sp!, #5
 0x2d,0xe8,0x05,0xc0 = srsdb sp!, #5
 0x8d,0xe9,0x05,0xc0 = srsia sp, #5
 0xad,0xe9,0x05,0xc0 = srsia sp!, #5
 0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10
 0x0a,0xf3,0x00,0x08 = ssat r8, #1, r10
-0x0a,0xf3,0xc0,0x78 = ssat r8, #1, r10, lsl #31
+0x0a,0xf3,0xc0,0x78 = ssat r8, #1, r10, lsl #0x1f
 0x2a,0xf3,0x40,0x08 = ssat r8, #1, r10, asr #1
 0x27,0xf3,0x00,0x02 = ssat16 r2, #1, r7
-0x25,0xf3,0x0f,0x03 = ssat16 r3, #16, r5
-// 0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4
+0x25,0xf3,0x0f,0x03 = ssat16 r3, #0x10, r5
+0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4
 0xb8,0xbf = it lt
-// 0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4
-// 0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4
+0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4
+0xe3,0xfa,0x04,0xf2 = ssax r2, r3, r4
 0xb8,0xbf = it lt
-// 0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4
+0xe3,0xfa,0x04,0xf2 = ssaxlt r2, r3, r4
 0xd0,0xfa,0x06,0xf1 = ssub16 r1, r0, r6
 0xc2,0xfa,0x04,0xf9 = ssub8 r9, r2, r4
 0x14,0xbf = ite ne
-// 0xd3,0xfa,0x02,0xf5 = ssub16ne r5, r3, r2
-// 0xc1,0xfa,0x02,0xf5 = ssub8eq r5, r1, r2
+0xd3,0xfa,0x02,0xf5 = ssub16ne r5, r3, r2
+0xc1,0xfa,0x02,0xf5 = ssub8eq r5, r1, r2
 0x81,0xfd,0x01,0x80 = stc2 p0, c8, [r1, #4]
 0x82,0xfd,0x00,0x71 = stc2 p1, c7, [r2]
-0x03,0xfd,0x38,0x62 = stc2 p2, c6, [r3, #-224]
-0x24,0xfd,0x1e,0x53 = stc2 p3, c5, [r4, #-120]!
-0xa5,0xfc,0x04,0x44 = stc2 p4, c4, [r5], #16
-0x26,0xfc,0x12,0x35 = stc2 p5, c3, [r6], #-72
+0x03,0xfd,0x38,0x62 = stc2 p2, c6, [r3, #-0xe0]
+0x24,0xfd,0x1e,0x53 = stc2 p3, c5, [r4, #-0x78]!
+0xa5,0xfc,0x04,0x44 = stc2 p4, c4, [r5], #0x10
+0x26,0xfc,0x12,0x35 = stc2 p5, c3, [r6], #-0x48
 0xc7,0xfd,0x01,0x26 = stc2l p6, c2, [r7, #4]
 0xc8,0xfd,0x00,0x17 = stc2l p7, c1, [r8]
-0x49,0xfd,0x38,0x08 = stc2l p8, c0, [r9, #-224]
-0x6a,0xfd,0x1e,0x19 = stc2l p9, c1, [r10, #-120]!
-0xeb,0xfc,0x04,0x20 = stc2l p0, c2, [r11], #16
-0x6c,0xfc,0x12,0x31 = stc2l p1, c3, [r12], #-72
+0x49,0xfd,0x38,0x08 = stc2l p8, c0, [r9, #-0xe0]
+0x6a,0xfd,0x1e,0x19 = stc2l p9, c1, [r10, #-0x78]!
+0xeb,0xfc,0x04,0x20 = stc2l p0, c2, [r11], #0x10
+0x6c,0xfc,0x12,0x31 = stc2l p1, c3, [r12], #-0x48
 0x80,0xed,0x01,0x4c = stc p12, c4, [r0, #4]
 0x81,0xed,0x00,0x5d = stc p13, c5, [r1]
-0x02,0xed,0x38,0x6e = stc p14, c6, [r2, #-224]
-0x23,0xed,0x1e,0x7f = stc p15, c7, [r3, #-120]!
-0xa4,0xec,0x04,0x85 = stc p5, c8, [r4], #16
-0x25,0xec,0x12,0x94 = stc p4, c9, [r5], #-72
+0x02,0xed,0x38,0x6e = stc p14, c6, [r2, #-0xe0]
+0x23,0xed,0x1e,0x7f = stc p15, c7, [r3, #-0x78]!
+0xa4,0xec,0x04,0x85 = stc p5, c8, [r4], #0x10
+0x25,0xec,0x12,0x94 = stc p4, c9, [r5], #-0x48
 0xc6,0xed,0x01,0xa3 = stcl p3, c10, [r6, #4]
 0xc7,0xed,0x00,0xb2 = stcl p2, c11, [r7]
-0x48,0xed,0x38,0xc1 = stcl p1, c12, [r8, #-224]
-0x69,0xed,0x1e,0xd0 = stcl p0, c13, [r9, #-120]!
-0xea,0xec,0x04,0xe6 = stcl p6, c14, [r10], #16
-0x6b,0xec,0x12,0xf7 = stcl p7, c15, [r11], #-72
+0x48,0xed,0x38,0xc1 = stcl p1, c12, [r8, #-0xe0]
+0x69,0xed,0x1e,0xd0 = stcl p0, c13, [r9, #-0x78]!
+0xea,0xec,0x04,0xe6 = stcl p6, c14, [r10], #0x10
+0x6b,0xec,0x12,0xf7 = stcl p7, c15, [r11], #-0x48
 0x81,0xfc,0x19,0x82 = stc2 p2, c8, [r1], {25}
 0x84,0xe8,0x30,0x03 = stm.w r4, {r4, r5, r8, r9}
 0x84,0xe8,0x60,0x00 = stm.w r4, {r5, r6}
@@ -880,14 +973,14 @@
 0xa5,0xe8,0x08,0x01 = stm.w r5!, {r3, r8}
 0x05,0xe9,0x03,0x00 = stmdb r5, {r0, r1}
 0x45,0xf8,0x04,0x5c = str r5, [r5, #-4]
-0x35,0x62 = str r5, [r6, #32]
-0xc6,0xf8,0x21,0x50 = str.w r5, [r6, #33]
-0xc6,0xf8,0x01,0x51 = str.w r5, [r6, #257]
-0xc7,0xf8,0x01,0xf1 = str.w pc, [r7, #257]
-0x44,0xf8,0xff,0x2f = str r2, [r4, #255]!
+0x35,0x62 = str r5, [r6, #0x20]
+0xc6,0xf8,0x21,0x50 = str.w r5, [r6, #0x21]
+0xc6,0xf8,0x01,0x51 = str.w r5, [r6, #0x101]
+0xc7,0xf8,0x01,0xf1 = str.w pc, [r7, #0x101]
+0x44,0xf8,0xff,0x2f = str r2, [r4, #0xff]!
 0x4d,0xf8,0x04,0x8f = str r8, [sp, #4]!
 0x4d,0xf8,0x04,0xed = str lr, [sp, #-4]!
-0x44,0xf8,0xff,0x2b = str r2, [r4], #255
+0x44,0xf8,0xff,0x2b = str r2, [r4], #0xff
 0x4d,0xf8,0x04,0x8b = str r8, [sp], #4
 0x4d,0xf8,0x04,0xe9 = str lr, [sp], #-4
 0x48,0xf8,0x01,0x10 = str.w r1, [r8, r1]
@@ -897,14 +990,14 @@
 0x4d,0xf8,0x12,0x70 = str.w r7, [sp, r2, lsl #1]
 0x4d,0xf8,0x02,0x70 = str.w r7, [sp, r2]
 0x05,0xf8,0x04,0x5c = strb r5, [r5, #-4]
-0x86,0xf8,0x20,0x50 = strb.w r5, [r6, #32]
-0x86,0xf8,0x21,0x50 = strb.w r5, [r6, #33]
-0x86,0xf8,0x01,0x51 = strb.w r5, [r6, #257]
-0x87,0xf8,0x01,0xe1 = strb.w lr, [r7, #257]
-0x08,0xf8,0xff,0x5f = strb r5, [r8, #255]!
+0x86,0xf8,0x20,0x50 = strb.w r5, [r6, #0x20]
+0x86,0xf8,0x21,0x50 = strb.w r5, [r6, #0x21]
+0x86,0xf8,0x01,0x51 = strb.w r5, [r6, #0x101]
+0x87,0xf8,0x01,0xe1 = strb.w lr, [r7, #0x101]
+0x08,0xf8,0xff,0x5f = strb r5, [r8, #0xff]!
 0x05,0xf8,0x04,0x2f = strb r2, [r5, #4]!
 0x04,0xf8,0x04,0x1d = strb r1, [r4, #-4]!
-0x03,0xf8,0xff,0xeb = strb lr, [r3], #255
+0x03,0xf8,0xff,0xeb = strb lr, [r3], #0xff
 0x02,0xf8,0x04,0x9b = strb r9, [r2], #4
 0x0d,0xf8,0x04,0x39 = strb r3, [sp], #-4
 0x08,0xf8,0x00,0x4d = strb r4, [r8, #-0]!
@@ -918,9 +1011,9 @@
 0x02,0xf8,0x00,0x1e = strbt r1, [r2]
 0x08,0xf8,0x00,0x1e = strbt r1, [r8]
 0x08,0xf8,0x03,0x1e = strbt r1, [r8, #3]
-0x08,0xf8,0xff,0x1e = strbt r1, [r8, #255]
-0xc6,0xe9,0x06,0x35 = strd r3, r5, [r6, #24]
-0xe6,0xe9,0x06,0x35 = strd r3, r5, [r6, #24]!
+0x08,0xf8,0xff,0x1e = strbt r1, [r8, #0xff]
+0xc6,0xe9,0x06,0x35 = strd r3, r5, [r6, #0x18]
+0xe6,0xe9,0x06,0x35 = strd r3, r5, [r6, #0x18]!
 0xe6,0xe8,0x01,0x35 = strd r3, r5, [r6], #4
 0x66,0xe8,0x02,0x35 = strd r3, r5, [r6], #-8
 0xc6,0xe9,0x00,0x35 = strd r3, r5, [r6]
@@ -928,21 +1021,24 @@
 0x42,0xe9,0x00,0x01 = strd r0, r1, [r2, #-0]
 0x62,0xe9,0x00,0x01 = strd r0, r1, [r2, #-0]!
 0x62,0xe8,0x00,0x01 = strd r0, r1, [r2], #-0
+0xc2,0xe9,0x40,0x01 = strd r0, r1, [r2, #0x100]
+0xe2,0xe9,0x40,0x01 = strd r0, r1, [r2, #0x100]!
+0xe2,0xe8,0x40,0x01 = strd r0, r1, [r2], #0x100
 0x44,0xe8,0x00,0x81 = strex r1, r8, [r4]
 0x44,0xe8,0x00,0x28 = strex r8, r2, [r4]
-0x4d,0xe8,0x20,0xc2 = strex r2, ip, [sp, #128]
+0x4d,0xe8,0x20,0xc2 = strex r2, r12, [sp, #0x80]
 0xc7,0xe8,0x45,0x1f = strexb r5, r1, [r7]
 0xcc,0xe8,0x59,0x7f = strexh r9, r7, [r12]
 0xc4,0xe8,0x79,0x36 = strexd r9, r3, r6, [r4]
 0x25,0xf8,0x04,0x5c = strh r5, [r5, #-4]
-0x35,0x84 = strh r5, [r6, #32]
-0xa6,0xf8,0x21,0x50 = strh.w r5, [r6, #33]
-0xa6,0xf8,0x01,0x51 = strh.w r5, [r6, #257]
-0xa7,0xf8,0x01,0xe1 = strh.w lr, [r7, #257]
-0x28,0xf8,0xff,0x5f = strh r5, [r8, #255]!
+0x35,0x84 = strh r5, [r6, #0x20]
+0xa6,0xf8,0x21,0x50 = strh.w r5, [r6, #0x21]
+0xa6,0xf8,0x01,0x51 = strh.w r5, [r6, #0x101]
+0xa7,0xf8,0x01,0xe1 = strh.w lr, [r7, #0x101]
+0x28,0xf8,0xff,0x5f = strh r5, [r8, #0xff]!
 0x25,0xf8,0x04,0x2f = strh r2, [r5, #4]!
 0x24,0xf8,0x04,0x1d = strh r1, [r4, #-4]!
-0x23,0xf8,0xff,0xeb = strh lr, [r3], #255
+0x23,0xf8,0xff,0xeb = strh lr, [r3], #0xff
 0x22,0xf8,0x04,0x9b = strh r9, [r2], #4
 0x2d,0xf8,0x04,0x39 = strh r3, [sp], #-4
 0x28,0xf8,0x01,0x10 = strh.w r1, [r8, r1]
@@ -954,26 +1050,26 @@
 0x22,0xf8,0x00,0x1e = strht r1, [r2]
 0x28,0xf8,0x00,0x1e = strht r1, [r8]
 0x28,0xf8,0x03,0x1e = strht r1, [r8, #3]
-0x28,0xf8,0xff,0x1e = strht r1, [r8, #255]
+0x28,0xf8,0xff,0x1e = strht r1, [r8, #0xff]
 0x42,0xf8,0x00,0x1e = strt r1, [r2]
 0x48,0xf8,0x00,0x1e = strt r1, [r8]
 0x48,0xf8,0x03,0x1e = strt r1, [r8, #3]
-0x48,0xf8,0xff,0x1e = strt r1, [r8, #255]
+0x48,0xf8,0xff,0x1e = strt r1, [r8, #0xff]
 0x0a,0xbf = itet eq
-// 0x11,0x1f = subeq r1, r2, #4
-// 0xa3,0xf2,0xff,0x35 = subwne r5, r3, #1023
-// 0xa5,0xf2,0x25,0x14 = subweq r4, r5, #293
-0xad,0xf5,0x80,0x62 = sub.w r2, sp, #1024
-0xa8,0xf5,0x7f,0x42 = sub.w r2, r8, #65280
-0xa3,0xf2,0x01,0x12 = subw r2, r3, #257
-0xa3,0xf2,0x01,0x12 = subw r2, r3, #257
-0xa6,0xf5,0x80,0x7c = sub.w r12, r6, #256
-0xa6,0xf2,0x00,0x1c = subw r12, r6, #256
-0xb2,0xf5,0xf8,0x71 = subs.w r1, r2, #496
+0x11,0x1f = subeq r1, r2, #4
+0xa3,0xf2,0xff,0x35 = subwne r5, r3, #0x3ff
+0xa5,0xf2,0x25,0x14 = subweq r4, r5, #0x125
+0xad,0xf5,0x80,0x62 = sub.w r2, sp, #0x400
+0xa8,0xf5,0x7f,0x42 = sub.w r2, r8, #0xff00
+0xa3,0xf2,0x01,0x12 = subw r2, r3, #0x101
+0xa3,0xf2,0x01,0x12 = subw r2, r3, #0x101
+0xa6,0xf5,0x80,0x7c = sub.w r12, r6, #0x100
+0xa6,0xf2,0x00,0x1c = subw r12, r6, #0x100
+0xb2,0xf5,0xf8,0x71 = subs.w r1, r2, #0x1f0
 0xa2,0xf1,0x01,0x02 = sub.w r2, r2, #1
-0xa0,0xf1,0x20,0x00 = sub.w r0, r0, #32
-0x38,0x3a = subs r2, #56
-0x38,0x3a = subs r2, #56
+0xa0,0xf1,0x20,0x00 = sub.w r0, r0, #0x20
+0x38,0x3a = subs r2, #0x38
+0x38,0x3a = subs r2, #0x38
 0xa5,0xeb,0x06,0x04 = sub.w r4, r5, r6
 0xa5,0xeb,0x46,0x14 = sub.w r4, r5, r6, lsl #5
 0xa5,0xeb,0x56,0x14 = sub.w r4, r5, r6, lsr #5
@@ -981,259 +1077,265 @@
 0xa5,0xeb,0x66,0x14 = sub.w r4, r5, r6, asr #5
 0xa5,0xeb,0x76,0x14 = sub.w r4, r5, r6, ror #5
 0xa2,0xeb,0x3c,0x05 = sub.w r5, r2, r12, rrx
-0xad,0xeb,0x0c,0x02 = sub.w r2, sp, ip
-0xad,0xeb,0x0c,0x0d = sub.w sp, sp, ip
-0xad,0xeb,0x0c,0x02 = sub.w r2, sp, ip
-0xad,0xeb,0x0c,0x0d = sub.w sp, sp, ip
+0xad,0xeb,0x0c,0x02 = sub.w r2, sp, r12
+0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
+0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
+0xad,0xeb,0x0c,0x02 = sub.w r2, sp, r12
+0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
+0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
 0x00,0xdf = svc #0
-0x0c,0xbf = ite eq
-// 0xff,0xdf = svceq #255
-// 0x21,0xdf = svcne #33
+0x08,0xbf = it eq
+0xff,0xdf = svceq #0xff
+0x18,0xbf = it ne
+0x21,0xdf = svcne #0x21
+0x04,0xbf = itt eq
+0x00,0xdf = svceq #0
+0x01,0xdf = svceq #1
 0x43,0xfa,0x84,0xf2 = sxtab r2, r3, r4
 0x45,0xfa,0x86,0xf4 = sxtab r4, r5, r6
 0xb8,0xbf = it lt
-// 0x42,0xfa,0x99,0xf6 = sxtablt r6, r2, r9, ror #8
-0x41,0xfa,0xa4,0xf5 = sxtab r5, r1, r4, ror #16
-0x48,0xfa,0xb3,0xf7 = sxtab r7, r8, r3, ror #24
+0x42,0xfa,0x99,0xf6 = sxtablt r6, r2, r9, ror #8
+0x41,0xfa,0xa4,0xf5 = sxtab r5, r1, r4, ror #0x10
+0x48,0xfa,0xb3,0xf7 = sxtab r7, r8, r3, ror #0x18
 0x22,0xfa,0x87,0xf6 = sxtab16 r6, r2, r7
 0x25,0xfa,0x98,0xf3 = sxtab16 r3, r5, r8, ror #8
-0x22,0xfa,0xa1,0xf3 = sxtab16 r3, r2, r1, ror #16
+0x22,0xfa,0xa1,0xf3 = sxtab16 r3, r2, r1, ror #0x10
 0x14,0xbf = ite ne
-// 0x21,0xfa,0x84,0xf0 = sxtab16ne r0, r1, r4
-// 0x22,0xfa,0xb3,0xf1 = sxtab16eq r1, r2, r3, ror #24
+0x21,0xfa,0x84,0xf0 = sxtab16ne r0, r1, r4
+0x22,0xfa,0xb3,0xf1 = sxtab16eq r1, r2, r3, ror #0x18
 0x03,0xfa,0x89,0xf1 = sxtah r1, r3, r9
 0x08,0xfa,0x93,0xf3 = sxtah r3, r8, r3, ror #8
-0x03,0xfa,0xb3,0xf9 = sxtah r9, r3, r3, ror #24
+0x03,0xfa,0xb3,0xf9 = sxtah r9, r3, r3, ror #0x18
 0x8c,0xbf = ite hi
-// 0x01,0xfa,0x86,0xf6 = sxtahhi r6, r1, r6
-// 0x02,0xfa,0xa4,0xf2 = sxtahls r2, r2, r4, ror #16
+0x01,0xfa,0x86,0xf6 = sxtahhi r6, r1, r6
+0x02,0xfa,0xa4,0xf2 = sxtahls r2, r2, r4, ror #0x10
 0x75,0xb2 = sxtb r5, r6
 0x4f,0xfa,0x99,0xf6 = sxtb.w r6, r9, ror #8
-0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #24
+0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #0x18
 0xac,0xbf = ite ge
-// 0x62,0xb2 = sxtbge r2, r4
-// 0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #16
+0x62,0xb2 = sxtbge r2, r4
+0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #0x10
 0x4f,0xfa,0x88,0xf7 = sxtb.w r7, r8
 0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4
 0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7
-0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #16
+0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #0x10
 0x2c,0xbf = ite hs
-// 0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8
-// 0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #24
+0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8
+0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #0x18
 0x31,0xb2 = sxth r1, r6
 0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8
-0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #24
+0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #0x18
 0x1c,0xbf = itt ne
-// 0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9
-// 0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #16
+0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9
+0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #0x10
 0x0f,0xfa,0x88,0xf7 = sxth.w r7, r8
 0x75,0xb2 = sxtb r5, r6
 0x4f,0xfa,0x99,0xf6 = sxtb.w r6, r9, ror #8
-0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #24
+0x4f,0xfa,0xb3,0xf8 = sxtb.w r8, r3, ror #0x18
 0xac,0xbf = ite ge
-// 0x62,0xb2 = sxtbge r2, r4
-// 0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #16
+0x62,0xb2 = sxtbge r2, r4
+0x4f,0xfa,0xa1,0xf5 = sxtblt.w r5, r1, ror #0x10
 0x2f,0xfa,0x84,0xf1 = sxtb16 r1, r4
 0x2f,0xfa,0x87,0xf6 = sxtb16 r6, r7
-0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #16
+0x2f,0xfa,0xa1,0xf3 = sxtb16 r3, r1, ror #0x10
 0x2c,0xbf = ite hs
-// 0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8
-// 0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #24
+0x2f,0xfa,0x95,0xf3 = sxtb16hs r3, r5, ror #8
+0x2f,0xfa,0xb3,0xf2 = sxtb16lo r2, r3, ror #0x18
 0x31,0xb2 = sxth r1, r6
 0x0f,0xfa,0x98,0xf3 = sxth.w r3, r8, ror #8
-0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #24
+0x0f,0xfa,0xb3,0xf9 = sxth.w r9, r3, ror #0x18
 0x1c,0xbf = itt ne
-// 0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9
-// 0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #16
-// 0xd3,0xe8,0x08,0xf0 = tbb [r3, r8]
-// 0xd3,0xe8,0x18,0xf0 = tbh [r3, r8, lsl #1]
+0x0f,0xfa,0x89,0xf3 = sxthne.w r3, r9
+0x0f,0xfa,0xa2,0xf2 = sxthne.w r2, r2, ror #0x10
+0xd3,0xe8,0x08,0xf0 = tbb [r3, r8]
+0xd3,0xe8,0x18,0xf0 = tbh [r3, r8, lsl #1]
 0x08,0xbf = it eq
-// 0xd3,0xe8,0x08,0xf0 = tbbeq [r3, r8]
+0xd3,0xe8,0x08,0xf0 = tbbeq [r3, r8]
 0x28,0xbf = it hs
-// 0xd3,0xe8,0x18,0xf0 = tbhhs [r3, r8, lsl #1]
-0x95,0xf4,0x70,0x4f = teq.w r5, #61440
+0xd3,0xe8,0x18,0xf0 = tbhhs [r3, r8, lsl #1]
+0x95,0xf4,0x70,0x4f = teq.w r5, #0xf000
 0x94,0xea,0x05,0x0f = teq.w r4, r5
 0x94,0xea,0x45,0x1f = teq.w r4, r5, lsl #5
 0x94,0xea,0x55,0x1f = teq.w r4, r5, lsr #5
 0x94,0xea,0x55,0x1f = teq.w r4, r5, lsr #5
 0x94,0xea,0x65,0x1f = teq.w r4, r5, asr #5
 0x94,0xea,0x75,0x1f = teq.w r4, r5, ror #5
-0x15,0xf4,0x70,0x4f = tst.w r5, #61440
+0x15,0xf4,0x70,0x4f = tst.w r5, #0xf000
 0x2a,0x42 = tst r2, r5
 0x13,0xea,0x4c,0x1f = tst.w r3, r12, lsl #5
 0x14,0xea,0x1b,0x1f = tst.w r4, r11, lsr #4
-0x15,0xea,0x1a,0x3f = tst.w r5, r10, lsr #12
-0x16,0xea,0xa9,0x7f = tst.w r6, r9, asr #30
+0x15,0xea,0x1a,0x3f = tst.w r5, r10, lsr #0xc
+0x16,0xea,0xa9,0x7f = tst.w r6, r9, asr #0x1e
 0x17,0xea,0xb8,0x0f = tst.w r7, r8, ror #2
-// 0x92,0xfa,0x43,0xf1 = uadd16 r1, r2, r3
-// 0x82,0xfa,0x43,0xf1 = uadd8 r1, r2, r3
+0x92,0xfa,0x43,0xf1 = uadd16 r1, r2, r3
+0x82,0xfa,0x43,0xf1 = uadd8 r1, r2, r3
 0xcc,0xbf = ite gt
-// 0x92,0xfa,0x43,0xf1 = uadd16gt r1, r2, r3
-// 0x82,0xfa,0x43,0xf1 = uadd8le r1, r2, r3
-// 0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0
+0x92,0xfa,0x43,0xf1 = uadd16gt r1, r2, r3
+0x82,0xfa,0x43,0xf1 = uadd8le r1, r2, r3
+0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0
 0x08,0xbf = it eq
-// 0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0
-// 0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0
+0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0
+0xac,0xfa,0x40,0xf9 = uasx r9, r12, r0
 0x08,0xbf = it eq
-// 0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0
-0xc5,0xf3,0x00,0x44 = ubfx r4, r5, #16, #1
+0xac,0xfa,0x40,0xf9 = uasxeq r9, r12, r0
+0xc5,0xf3,0x00,0x44 = ubfx r4, r5, #0x10, #1
 0xc8,0xbf = it gt
-// 0xc5,0xf3,0x0f,0x44 = ubfxgt r4, r5, #16, #16
-// 0x98,0xfa,0x62,0xf4 = uhadd16 r4, r8, r2
-// 0x88,0xfa,0x62,0xf4 = uhadd8 r4, r8, r2
+0xc5,0xf3,0x0f,0x44 = ubfxgt r4, r5, #0x10, #0x10
+0x98,0xfa,0x62,0xf4 = uhadd16 r4, r8, r2
+0x88,0xfa,0x62,0xf4 = uhadd8 r4, r8, r2
 0xc4,0xbf = itt gt
-// 0x98,0xfa,0x62,0xf4 = uhadd16gt r4, r8, r2
-// 0x88,0xfa,0x62,0xf4 = uhadd8gt r4, r8, r2
+0x98,0xfa,0x62,0xf4 = uhadd16gt r4, r8, r2
+0x88,0xfa,0x62,0xf4 = uhadd8gt r4, r8, r2
 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5
 0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6
 0xc4,0xbf = itt gt
-// 0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8
-// 0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12
+0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8
+0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12
 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5
 0xe6,0xfa,0x66,0xf5 = uhsax r5, r6, r6
 0xc4,0xbf = itt gt
-// 0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8
-// 0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12
+0xa9,0xfa,0x68,0xf6 = uhasxgt r6, r9, r8
+0xe8,0xfa,0x6c,0xf7 = uhsaxgt r7, r8, r12
 0xd8,0xfa,0x63,0xf5 = uhsub16 r5, r8, r3
 0xc7,0xfa,0x66,0xf1 = uhsub8 r1, r7, r6
 0xbc,0xbf = itt lt
-// 0xd9,0xfa,0x6c,0xf4 = uhsub16lt r4, r9, r12
-// 0xc1,0xfa,0x65,0xf3 = uhsub8lt r3, r1, r5
-// 0xe5,0xfb,0x66,0x34 = umaal r3, r4, r5, r6
+0xd9,0xfa,0x6c,0xf4 = uhsub16lt r4, r9, r12
+0xc1,0xfa,0x65,0xf3 = uhsub8lt r3, r1, r5
+0xe5,0xfb,0x66,0x34 = umaal r3, r4, r5, r6
 0xb8,0xbf = it lt
-// 0xe5,0xfb,0x66,0x34 = umaallt r3, r4, r5, r6
+0xe5,0xfb,0x66,0x34 = umaallt r3, r4, r5, r6
 0xe6,0xfb,0x08,0x24 = umlal r2, r4, r6, r8
 0xc8,0xbf = it gt
-// 0xe2,0xfb,0x06,0x61 = umlalgt r6, r1, r2, r6
+0xe2,0xfb,0x06,0x61 = umlalgt r6, r1, r2, r6
 0xa6,0xfb,0x08,0x24 = umull r2, r4, r6, r8
 0xc8,0xbf = it gt
-// 0xa2,0xfb,0x06,0x61 = umullgt r6, r1, r2, r6
+0xa2,0xfb,0x06,0x61 = umullgt r6, r1, r2, r6
 0x92,0xfa,0x53,0xf1 = uqadd16 r1, r2, r3
 0x84,0xfa,0x58,0xf3 = uqadd8 r3, r4, r8
 0xcc,0xbf = ite gt
-// 0x97,0xfa,0x59,0xf4 = uqadd16gt r4, r7, r9
-// 0x81,0xfa,0x52,0xf8 = uqadd8le r8, r1, r2
+0x97,0xfa,0x59,0xf4 = uqadd16gt r4, r7, r9
+0x81,0xfa,0x52,0xf8 = uqadd8le r8, r1, r2
 0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3
 0xe4,0xfa,0x58,0xf3 = uqsax r3, r4, r8
 0xcc,0xbf = ite gt
-// 0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9
-// 0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2
+0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9
+0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2
 0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3
 0xe4,0xfa,0x58,0xf3 = uqsax r3, r4, r8
 0xcc,0xbf = ite gt
-// 0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9
-// 0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2
+0xa7,0xfa,0x59,0xf4 = uqasxgt r4, r7, r9
+0xe1,0xfa,0x52,0xf8 = uqsaxle r8, r1, r2
 0xc2,0xfa,0x59,0xf8 = uqsub8 r8, r2, r9
 0xd9,0xfa,0x57,0xf1 = uqsub16 r1, r9, r7
 0xcc,0xbf = ite gt
-// 0xc1,0xfa,0x56,0xf3 = uqsub8gt r3, r1, r6
-// 0xd6,0xfa,0x54,0xf4 = uqsub16le r4, r6, r4
+0xc1,0xfa,0x56,0xf3 = uqsub8gt r3, r1, r6
+0xd6,0xfa,0x54,0xf4 = uqsub16le r4, r6, r4
 0x79,0xfb,0x07,0xf1 = usad8 r1, r9, r7
 0x72,0xfb,0x09,0xc8 = usada8 r8, r2, r9, r12
 0xcc,0xbf = ite gt
-// 0x71,0xfb,0x06,0x93 = usada8gt r3, r1, r6, r9
-// 0x76,0xfb,0x04,0xf4 = usad8le r4, r6, r4
+0x71,0xfb,0x06,0x93 = usada8gt r3, r1, r6, r9
+0x76,0xfb,0x04,0xf4 = usad8le r4, r6, r4
 0x8a,0xf3,0x01,0x08 = usat r8, #1, r10
 0x8a,0xf3,0x04,0x08 = usat r8, #4, r10
-0x8a,0xf3,0xc5,0x78 = usat r8, #5, r10, lsl #31
-0xaa,0xf3,0x50,0x08 = usat r8, #16, r10, asr #1
+0x8a,0xf3,0xc5,0x78 = usat r8, #5, r10, lsl #0x1f
+0xaa,0xf3,0x50,0x08 = usat r8, #0x10, r10, asr #1
 0xa7,0xf3,0x02,0x02 = usat16 r2, #2, r7
-0xa5,0xf3,0x0f,0x03 = usat16 r3, #15, r5
+0xa5,0xf3,0x0f,0x03 = usat16 r3, #0xf, r5
 0xe3,0xfa,0x44,0xf2 = usax r2, r3, r4
 0x18,0xbf = it ne
-// 0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9
+0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9
 0xe3,0xfa,0x44,0xf2 = usax r2, r3, r4
 0x18,0xbf = it ne
-// 0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9
+0xe1,0xfa,0x49,0xf6 = usaxne r6, r1, r9
 0xd2,0xfa,0x47,0xf4 = usub16 r4, r2, r7
 0xc8,0xfa,0x45,0xf1 = usub8 r1, r8, r5
 0x8c,0xbf = ite hi
-// 0xd1,0xfa,0x43,0xf1 = usub16hi r1, r1, r3
-// 0xc2,0xfa,0x43,0xf9 = usub8ls r9, r2, r3
+0xd1,0xfa,0x43,0xf1 = usub16hi r1, r1, r3
+0xc2,0xfa,0x43,0xf9 = usub8ls r9, r2, r3
 0x53,0xfa,0x84,0xf2 = uxtab r2, r3, r4
 0x55,0xfa,0x86,0xf4 = uxtab r4, r5, r6
 0xb8,0xbf = it lt
-// 0x52,0xfa,0x99,0xf6 = uxtablt r6, r2, r9, ror #8
-0x51,0xfa,0xa4,0xf5 = uxtab r5, r1, r4, ror #16
-0x58,0xfa,0xb3,0xf7 = uxtab r7, r8, r3, ror #24
+0x52,0xfa,0x99,0xf6 = uxtablt r6, r2, r9, ror #8
+0x51,0xfa,0xa4,0xf5 = uxtab r5, r1, r4, ror #0x10
+0x58,0xfa,0xb3,0xf7 = uxtab r7, r8, r3, ror #0x18
 0xa8,0xbf = it ge
-// 0x31,0xfa,0x84,0xf0 = uxtab16ge r0, r1, r4
+0x31,0xfa,0x84,0xf0 = uxtab16ge r0, r1, r4
 0x32,0xfa,0x87,0xf6 = uxtab16 r6, r2, r7
 0x35,0xfa,0x98,0xf3 = uxtab16 r3, r5, r8, ror #8
-0x32,0xfa,0xa1,0xf3 = uxtab16 r3, r2, r1, ror #16
+0x32,0xfa,0xa1,0xf3 = uxtab16 r3, r2, r1, ror #0x10
 0x08,0xbf = it eq
-// 0x32,0xfa,0xb3,0xf1 = uxtab16eq r1, r2, r3, ror #24
+0x32,0xfa,0xb3,0xf1 = uxtab16eq r1, r2, r3, ror #0x18
 0x13,0xfa,0x89,0xf1 = uxtah r1, r3, r9
 0x88,0xbf = it hi
-// 0x11,0xfa,0x86,0xf6 = uxtahhi r6, r1, r6
+0x11,0xfa,0x86,0xf6 = uxtahhi r6, r1, r6
 0x18,0xfa,0x93,0xf3 = uxtah r3, r8, r3, ror #8
 0x38,0xbf = it lo
-// 0x12,0xfa,0xa4,0xf2 = uxtahlo r2, r2, r4, ror #16
-0x13,0xfa,0xb3,0xf9 = uxtah r9, r3, r3, ror #24
+0x12,0xfa,0xa4,0xf2 = uxtahlo r2, r2, r4, ror #0x10
+0x13,0xfa,0xb3,0xf9 = uxtah r9, r3, r3, ror #0x18
 0xa8,0xbf = it ge
-// 0xe2,0xb2 = uxtbge r2, r4
+0xe2,0xb2 = uxtbge r2, r4
 0xf5,0xb2 = uxtb r5, r6
 0x5f,0xfa,0x99,0xf6 = uxtb.w r6, r9, ror #8
 0x38,0xbf = it lo
-// 0x5f,0xfa,0xa1,0xf5 = uxtblo.w r5, r1, ror #16
-0x5f,0xfa,0xb3,0xf8 = uxtb.w r8, r3, ror #24
+0x5f,0xfa,0xa1,0xf5 = uxtblo.w r5, r1, ror #0x10
+0x5f,0xfa,0xb3,0xf8 = uxtb.w r8, r3, ror #0x18
 0x5f,0xfa,0x88,0xf7 = uxtb.w r7, r8
 0x3f,0xfa,0x84,0xf1 = uxtb16 r1, r4
 0x3f,0xfa,0x87,0xf6 = uxtb16 r6, r7
 0x28,0xbf = it hs
-// 0x3f,0xfa,0x95,0xf3 = uxtb16hs r3, r5, ror #8
-0x3f,0xfa,0xa1,0xf3 = uxtb16 r3, r1, ror #16
+0x3f,0xfa,0x95,0xf3 = uxtb16hs r3, r5, ror #8
+0x3f,0xfa,0xa1,0xf3 = uxtb16 r3, r1, ror #0x10
 0xa8,0xbf = it ge
-// 0x3f,0xfa,0xb3,0xf2 = uxtb16ge r2, r3, ror #24
+0x3f,0xfa,0xb3,0xf2 = uxtb16ge r2, r3, ror #0x18
 0x18,0xbf = it ne
-// 0x1f,0xfa,0x89,0xf3 = uxthne.w r3, r9
+0x1f,0xfa,0x89,0xf3 = uxthne.w r3, r9
 0xb1,0xb2 = uxth r1, r6
 0x1f,0xfa,0x98,0xf3 = uxth.w r3, r8, ror #8
 0xd8,0xbf = it le
-// 0x1f,0xfa,0xa2,0xf2 = uxthle.w r2, r2, ror #16
-0x1f,0xfa,0xb3,0xf9 = uxth.w r9, r3, ror #24
+0x1f,0xfa,0xa2,0xf2 = uxthle.w r2, r2, ror #0x10
+0x1f,0xfa,0xb3,0xf9 = uxth.w r9, r3, ror #0x18
 0x1f,0xfa,0x88,0xf7 = uxth.w r7, r8
-// 0x20,0xbf = wfe 
-// 0x30,0xbf = wfi 
-// 0x10,0xbf = yield 
+0x20,0xbf = wfe
+0x30,0xbf = wfi
+0x10,0xbf = yield
 0xb6,0xbf = itet lt
-// 0x20,0xbf = wfelt 
-// 0x30,0xbf = wfige 
-// 0x10,0xbf = yieldlt 
-// 0xaf,0xf3,0x04,0x80 = sev.w 
-0xaf,0xf3,0x03,0x80 = wfi.w 
-0xaf,0xf3,0x02,0x80 = wfe.w 
-0xaf,0xf3,0x01,0x80 = yield.w 
-0xaf,0xf3,0x00,0x80 = nop.w 
-0x40,0xbf = sev 
-// 0x30,0xbf = wfi 
-// 0x20,0xbf = wfe 
-// 0x10,0xbf = yield 
-// 0x00,0xbf = nop 
+0x20,0xbf = wfelt
+0x30,0xbf = wfige
+0x10,0xbf = yieldlt
+0xaf,0xf3,0x04,0x80 = sev.w
+0xaf,0xf3,0x03,0x80 = wfi.w
+0xaf,0xf3,0x02,0x80 = wfe.w
+0xaf,0xf3,0x01,0x80 = yield.w
+0xaf,0xf3,0x00,0x80 = nop.w
+0x40,0xbf = sev
+0x30,0xbf = wfi
+0x20,0xbf = wfe
+0x10,0xbf = yield
+0x00,0xbf = nop
 0xb6,0xbf = itet lt
-// 0xf0,0xbf = hintlt #15
-// 0xaf,0xf3,0x10,0x80 = hintge.w #16
-// 0xaf,0xf3,0xef,0x80 = hintlt.w #239
+0xf0,0xbf = hintlt #0xf
+0xaf,0xf3,0x10,0x80 = hintge.w #0x10
+0xaf,0xf3,0xef,0x80 = hintlt.w #0xef
 0x70,0xbf = hint #7
 0xaf,0xf3,0x07,0x80 = hint.w #7
-0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #22]
-0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #22]
-0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #22]
-0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #22]
-0xdf,0xf8,0x16,0xb0 = ldr.w r11, [pc, #22]
-0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #22]
-0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #22]
-0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #22]
-0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #22]
-0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-22]
-0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-22]
-0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-22]
-0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-22]
-0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-22]
-0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-22]
-0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-22]
-0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-22]
-0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-22]
-0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-22]
-0x03,0x49 = ldr r1, [pc, #12]
+0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #0x16]
+0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #0x16]
+0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #0x16]
+0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #0x16]
+0xdf,0xf8,0x16,0xb0 = ldr.w r11, [pc, #0x16]
+0x9f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #0x16]
+0xbf,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #0x16]
+0x9f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #0x16]
+0xbf,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #0x16]
+0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-0x16]
+0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-0x16]
+0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-0x16]
+0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-0x16]
+0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-0x16]
+0x5f,0xf8,0x16,0xb0 = ldr.w r11, [pc, #-0x16]
+0x1f,0xf8,0x16,0xb0 = ldrb.w r11, [pc, #-0x16]
+0x3f,0xf8,0x16,0xb0 = ldrh.w r11, [pc, #-0x16]
+0x1f,0xf9,0x16,0xb0 = ldrsb.w r11, [pc, #-0x16]
+0x3f,0xf9,0x16,0xb0 = ldrsh.w r11, [pc, #-0x16]
+0x03,0x49 = ldr r1, [pc, #0xc]
 0xde,0xf3,0x04,0x8f = subs pc, lr, #4
diff --git a/suite/MC/ARM/bfloat16-a32.s.cs b/suite/MC/ARM/bfloat16-a32.s.cs
new file mode 100644
index 000000000..75894d930
--- /dev/null
+++ b/suite/MC/ARM/bfloat16-a32.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x05,0x3d,0x04,0xfc = vdot.bf16 d3, d4, d5
diff --git a/suite/MC/ARM/bfloat16-t32.s.cs b/suite/MC/ARM/bfloat16-t32.s.cs
new file mode 100644
index 000000000..21117a7bb
--- /dev/null
+++ b/suite/MC/ARM/bfloat16-t32.s.cs
@@ -0,0 +1,4 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xb6,0xff,0x46,0x16 = vcvt.bf16.f32 d1, q3
+0x18,0xbf = it ne
+0xf3,0xee,0xe1,0x09 = vcvtt.bf16.f32  s1, s3
diff --git a/suite/MC/ARM/cde-integer.s.cs b/suite/MC/ARM/cde-integer.s.cs
new file mode 100644
index 000000000..b8e16ad8b
--- /dev/null
+++ b/suite/MC/ARM/cde-integer.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x06,0xbf = itte eq
diff --git a/suite/MC/ARM/cde-vec-pred.s.cs b/suite/MC/ARM/cde-vec-pred.s.cs
new file mode 100644
index 000000000..12ce5fc9d
--- /dev/null
+++ b/suite/MC/ARM/cde-vec-pred.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x41,0xfe,0x00,0xef = vptete.i8 eq, q0, q0
diff --git a/suite/MC/ARM/clrm-asm.s.cs b/suite/MC/ARM/clrm-asm.s.cs
new file mode 100644
index 000000000..75675da8c
--- /dev/null
+++ b/suite/MC/ARM/clrm-asm.s.cs
@@ -0,0 +1,7 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
+0x9f,0xe8,0x0f,0x00 = clrm {r0, r1, r2, r3}
+0x9f,0xe8,0x1e,0x00 = clrm {r1, r2, r3, r4}
+0x9f,0xe8,0xff,0xdf = clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr}
+0x9f,0xe8,0x00,0xc0 = clrm {lr, apsr}
+0x9f,0xe8,0x03,0x80 = clrm {r0, r1, apsr}
+0x9f,0xe8,0x1f,0xc0 = clrm {r0, r1, r2, r3, r4, lr, apsr}
diff --git a/suite/MC/ARM/cps.s.cs b/suite/MC/ARM/cps.s.cs
new file mode 100644
index 000000000..f1974c229
--- /dev/null
+++ b/suite/MC/ARM/cps.s.cs
@@ -0,0 +1,4 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x61,0xb6 = cpsie f
+0xaf,0xf3,0x43,0x85 = cpsie i, #3
+0xaf,0xf3,0x00,0x81 = cps #0
diff --git a/suite/MC/ARM/fconst.s.cs b/suite/MC/ARM/fconst.s.cs
new file mode 100644
index 000000000..7998f9c6e
--- /dev/null
+++ b/suite/MC/ARM/fconst.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x00,0x2a,0xb0,0xee = vmov.f32 s4, #2.000000e+00
+0x00,0x2a,0xb7,0xee = vmov.f32 s4, #1.000000e+00
+0x00,0x3b,0xb0,0xee = vmov.f64 d3, #2.000000e+00
+0x00,0x3b,0xb7,0xee = vmov.f64 d3, #1.000000e+00
+0x01,0x2a,0xf0,0x1e = vmovne.f32 s5, #2.125000e+00
+0x00,0x2a,0xf2,0xce = vmovgt.f32 s5, #8.000000e+00
+0x03,0x2b,0xb0,0xbe = vmovlt.f64 d2, #2.375000e+00
+0x00,0x2b,0xb4,0xae = vmovge.f64 d2, #1.250000e-01
diff --git a/suite/MC/ARM/gas-compl-copr-reg.s.cs b/suite/MC/ARM/gas-compl-copr-reg.s.cs
new file mode 100644
index 000000000..517d8042e
--- /dev/null
+++ b/suite/MC/ARM/gas-compl-copr-reg.s.cs
@@ -0,0 +1,5 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4]
+0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0]
+0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4]
+0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0]
diff --git a/suite/MC/ARM/implicit-it-generation.s.cs b/suite/MC/ARM/implicit-it-generation.s.cs
new file mode 100644
index 000000000..36e63ee96
--- /dev/null
+++ b/suite/MC/ARM/implicit-it-generation.s.cs
@@ -0,0 +1,12 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x01,0x30 = adds r0, #1
+0x10,0xf1,0x01,0x00 = adds.w r0, r0, #1
+0x80,0xe0 = b #0x100
+0x00,0xf0,0x00,0xbc = b.w #0x800
+0x02,0xd0 = beq #4
+0x00,0xf0,0x80,0x80 = beq.w #0x100
+0x02,0xe0 = b #4
+0x80,0xe0 = b #0x100
+0x00,0xf0,0x00,0xbc = b.w #0x800
+0x02,0xdc = bgt #4
+0x00,0xf3,0x80,0x80 = bgt.w #0x100
diff --git a/suite/MC/ARM/ldrd-strd-gnu-arm.s.cs b/suite/MC/ARM/ldrd-strd-gnu-arm.s.cs
new file mode 100644
index 000000000..0f4c6004a
--- /dev/null
+++ b/suite/MC/ARM/ldrd-strd-gnu-arm.s.cs
@@ -0,0 +1,7 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xd0,0x02,0xea,0xe1 = ldrd r0, r1, [r10, #0x20]!
+0xd0,0x02,0xca,0xe0 = ldrd r0, r1, [r10], #0x20
+0xd0,0x02,0xca,0xe1 = ldrd r0, r1, [r10, #0x20]
+0xf0,0x02,0xea,0xe1 = strd r0, r1, [r10, #0x20]!
+0xf0,0x02,0xca,0xe0 = strd r0, r1, [r10], #0x20
+0xf0,0x02,0xca,0xe1 = strd r0, r1, [r10, #0x20]
diff --git a/suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs b/suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs
new file mode 100644
index 000000000..081b432c2
--- /dev/null
+++ b/suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs
@@ -0,0 +1,13 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xfa,0xe9,0x80,0x01 = ldrd r0, r1, [r10, #0x200]!
+0xfa,0xe8,0x80,0x01 = ldrd r0, r1, [r10], #0x200
+0xda,0xe9,0x80,0x01 = ldrd r0, r1, [r10, #0x200]
+0xea,0xe9,0x80,0x01 = strd r0, r1, [r10, #0x200]!
+0xea,0xe8,0x80,0x01 = strd r0, r1, [r10], #0x200
+0xca,0xe9,0x80,0x01 = strd r0, r1, [r10, #0x200]
+0xfa,0xe9,0x80,0x12 = ldrd r1, r2, [r10, #0x200]!
+0xfa,0xe8,0x80,0x12 = ldrd r1, r2, [r10], #0x200
+0xda,0xe9,0x80,0x12 = ldrd r1, r2, [r10, #0x200]
+0xea,0xe9,0x80,0x12 = strd r1, r2, [r10, #0x200]!
+0xea,0xe8,0x80,0x12 = strd r1, r2, [r10], #0x200
+0xca,0xe9,0x80,0x12 = strd r1, r2, [r10, #0x200]
diff --git a/suite/MC/ARM/mode-switch.s.cs b/suite/MC/ARM/mode-switch.s.cs
deleted file mode 100644
index 78c7c46a3..000000000
--- a/suite/MC/ARM/mode-switch.s.cs
+++ /dev/null
@@ -1,5 +0,0 @@
-# CS_ARCH_ARM, CS_MODE_THUMB, None
-0x00,0xeb,0x01,0x00 = add.w r0, r0, r1
-0x40,0x18 = adds r0, r0, r1
-0x00,0xeb,0x01,0x00 = add.w r0, r0, r1
-0x40,0x18 = adds r0, r0, r1
diff --git a/suite/MC/ARM/mve-bitops.s.cs b/suite/MC/ARM/mve-bitops.s.cs
new file mode 100644
index 000000000..e5cabb651
--- /dev/null
+++ b/suite/MC/ARM/mve-bitops.s.cs
@@ -0,0 +1,96 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x81,0xef,0x52,0x09 = vorr.i16 q0, #0x12
+0x81,0xef,0x52,0x03 = vorr.i32 q0, #0x1200
+0x86,0xff,0x5d,0x09 = vorr.i16 q0, #0xed
+0x86,0xff,0x5d,0x03 = vorr.i32 q0, #0xed00
+0x86,0xff,0x5d,0x05 = vorr.i32 q0, #0xed0000
+0x86,0xff,0x5d,0x07 = vorr.i32 q0, #0xed000000
+0x82,0xef,0x72,0x09 = vbic.i16 q0, #0x22
+0x81,0xef,0x71,0x03 = vbic.i32 q0, #0x1100
+0x85,0xff,0x7d,0x09 = vbic.i16 q0, #0xdd
+0x85,0xff,0x7d,0x0b = vbic.i16 q0, #0xdd00
+0x86,0xff,0x7e,0x01 = vbic.i32 q0, #0xee
+0x86,0xff,0x7e,0x03 = vbic.i32 q0, #0xee00
+0x86,0xff,0x7e,0x05 = vbic.i32 q0, #0xee0000
+0x86,0xff,0x7e,0x07 = vbic.i32 q0, #0xee000000
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0xb0,0xff,0x48,0x00 = vrev64.8 q0, q4
+0xb4,0xff,0x46,0x20 = vrev64.16 q1, q3
+0xb8,0xff,0x44,0x00 = vrev64.32 q0, q2
+0xb0,0xff,0xc2,0x00 = vrev32.8 q0, q1
+0xb4,0xff,0xca,0x00 = vrev32.16 q0, q5
+0xb0,0xff,0x44,0x01 = vrev16.8 q0, q2
+0xb0,0xff,0xc4,0x05 = vmvn q0, q2
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x40,0xee,0x30,0x8b = vmov.8 q0[1], r8
+0x20,0xee,0x30,0x5b = vmov.16 q0[2], r5
+0x2d,0xee,0x10,0xbb = vmov.32 q6[3], r11
+0x12,0xee,0x10,0x0b = vmov.32 r0, q1[0]
+0x35,0xee,0x70,0x1b = vmov.s16 r1, q2[7]
+0x79,0xee,0x30,0x0b = vmov.s8 r0, q4[13]
+0x93,0xee,0x30,0x0b = vmov.u16 r0, q1[4]
+0xfa,0xee,0x70,0x0b = vmov.u8 r0, q5[7]
+0x71,0xfe,0x4d,0x8f = vpste
+0xb0,0xff,0xc2,0x05 = vmvnt q0, q1
+0xb0,0xff,0xc2,0x05 = vmvne q0, q1
+0x71,0xfe,0x4d,0x8f = vpste
+0x32,0xef,0x54,0x01 = vornt q0, q1, q2
+0x32,0xef,0x54,0x01 = vorne q0, q1, q2
diff --git a/suite/MC/ARM/mve-float.s.cs b/suite/MC/ARM/mve-float.s.cs
new file mode 100644
index 000000000..16bd64461
--- /dev/null
+++ b/suite/MC/ARM/mve-float.s.cs
@@ -0,0 +1,103 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None
+0xb6,0xff,0x40,0x24 = vrintn.f16 q1, q0
+0xba,0xff,0x48,0x04 = vrintn.f32 q0, q4
+0xb6,0xff,0x42,0x05 = vrinta.f16 q0, q1
+0xba,0xff,0x46,0x25 = vrinta.f32 q1, q3
+0xb6,0xff,0xca,0x06 = vrintm.f16 q0, q5
+0xba,0xff,0xc8,0x06 = vrintm.f32 q0, q4
+0xb6,0xff,0xc0,0x27 = vrintp.f16 q1, q0
+0xba,0xff,0xc2,0x07 = vrintp.f32 q0, q1
+0xb6,0xff,0xc4,0x24 = vrintx.f16 q1, q2
+0xba,0xff,0xc2,0x24 = vrintx.f32 q1, q1
+0xb6,0xff,0xcc,0x25 = vrintz.f16 q1, q6
+0xba,0xff,0xc0,0x25 = vrintz.f32 q1, q0
+0xb6,0xee,0x60,0x0a = vrintr.f32 s0, s1
+0xb6,0xee,0x41,0x0b = vrintr.f64 d0, d1
+0x12,0xff,0x56,0x4d = vmul.f16 q2, q1, q3
+0x00,0xff,0x5a,0x0d = vmul.f32 q0, q0, q5
+0x24,0xfc,0x42,0x68 = vcmla.f16 q3, q2, q1, #0
+0xa0,0xfc,0x4a,0x08 = vcmla.f16 q0, q0, q5, #0x5a
+0x2e,0xfd,0x44,0x68 = vcmla.f16 q3, q7, q2, #0xb4
+0xae,0xfd,0x4c,0x48 = vcmla.f16 q2, q7, q6, #0x10e
+0x3c,0xfc,0x4c,0x48 = vcmla.f32 q2, q6, q6, #0
+0xb2,0xfc,0x46,0xe8 = vcmla.f32 q7, q1, q3, #0x5a
+0x3a,0xfd,0x46,0x88 = vcmla.f32 q4, q5, q3, #0xb4
+0xb4,0xfd,0x4e,0x68 = vcmla.f32 q3, q2, q7, #0x10e
+0x14,0xef,0x56,0x0c = vfma.f16 q0, q2, q3
+0x06,0xef,0x5e,0x0c = vfma.f32 q0, q3, q7
+0x34,0xef,0x5a,0x0c = vfms.f16 q0, q2, q5
+0x22,0xef,0x54,0x2c = vfms.f32 q1, q1, q2
+0x10,0xef,0x4a,0x0d = vadd.f16 q0, q0, q5
+0x06,0xef,0x40,0x2d = vadd.f32 q1, q3, q0
+0x02,0xef,0x44,0x0d = vadd.f32 q0, q1, q2
+0x82,0xfc,0x4e,0x48 = vcadd.f16 q2, q1, q7, #0x5a
+0x8a,0xfd,0x4e,0x48 = vcadd.f16 q2, q5, q7, #0x10e
+0x98,0xfc,0x4e,0x08 = vcadd.f32 q0, q4, q7, #0x5a
+0x94,0xfd,0x46,0x48 = vcadd.f32 q2, q2, q3, #0x10e
+0x30,0xff,0x4c,0x0d = vabd.f16 q0, q0, q6
+0x22,0xff,0x48,0x0d = vabd.f32 q0, q1, q4
+0xbf,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #1
+0xb0,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #0x10
+0xb5,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #0xb
+0xbd,0xef,0x52,0x2d = vcvt.s16.f16 q1, q1, #3
+0xb6,0xff,0x52,0x4c = vcvt.f16.u16 q2, q1, #0xa
+0xbd,0xff,0x50,0x0d = vcvt.u16.f16 q0, q0, #3
+0xbf,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #1
+0xa0,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #0x20
+0xba,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #6
+0xab,0xef,0x50,0x2f = vcvt.s32.f32 q1, q0, #0x15
+0xbc,0xff,0x58,0x2e = vcvt.f32.u32 q1, q4, #4
+0xb8,0xff,0x5a,0x2f = vcvt.u32.f32 q1, q5, #8
+0xb7,0xff,0x42,0x06 = vcvt.f16.s16 q0, q1
+0xb7,0xff,0xc8,0x06 = vcvt.f16.u16 q0, q4
+0xb7,0xff,0x40,0x07 = vcvt.s16.f16 q0, q0
+0xb7,0xff,0xc0,0x07 = vcvt.u16.f16 q0, q0
+0xbb,0xff,0x40,0x06 = vcvt.f32.s32 q0, q0
+0xbb,0xff,0xc0,0x06 = vcvt.f32.u32 q0, q0
+0xbb,0xff,0x40,0x07 = vcvt.s32.f32 q0, q0
+0xbb,0xff,0xc4,0x07 = vcvt.u32.f32 q0, q2
+0xb7,0xff,0x4e,0x00 = vcvta.s16.f16 q0, q7
+0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3
+0xb7,0xff,0x4e,0x00 = vcvta.s16.f16 q0, q7
+0xbb,0xff,0xcc,0xe1 = vcvtn.u32.f32 q7, q6
+0xbb,0xff,0x4e,0x02 = vcvtp.s32.f32 q0, q7
+0xbb,0xff,0xc8,0x23 = vcvtm.u32.f32 q1, q4
+0xb5,0xff,0xce,0x07 = vneg.f16 q0, q7
+0xb9,0xff,0xc4,0x07 = vneg.f32 q0, q2
+0xb5,0xff,0x44,0x07 = vabs.f16 q0, q2
+0xb9,0xff,0x40,0x07 = vabs.f32 q0, q0
+0x3f,0xfe,0x83,0x2e = vmaxnma.f16 q1, q1
+0x3f,0xee,0x8d,0x4e = vmaxnma.f32 q2, q6
+0x3f,0xfe,0x85,0x1e = vminnma.f16 q0, q2
+0x3f,0xee,0x83,0x1e = vminnma.f32 q0, q1
+0x08,0xbf = it eq
+0x30,0xee,0x20,0x0a = vaddeq.f32 s0, s0, s1
+0x71,0xfe,0x4d,0x0f = vpst
+0x12,0xef,0x44,0x0d = vaddt.f16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0xbb,0xff,0xc2,0x03 = vcvtmt.u32.f32 q0, q1
+0xbb,0xff,0x42,0x01 = vcvtne.s32.f32 q0, q1
+0x18,0xbf = it ne
+0xbd,0xee,0xe0,0x0a = vcvtne.s32.f32 s0, s1
+0xa8,0xbf = it ge
+0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1
+0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1
+0xbb,0xff,0xc0,0x47 = vcvtt.u32.f32 q2, q0
+0xbb,0xff,0xc0,0x27 = vcvte.u32.f32 q1, q0
+0x0c,0xbf = ite eq
+0xbc,0xee,0xe0,0x0a = vcvteq.u32.f32 s0, s1
+0xb8,0xee,0x60,0x0a = vcvtne.f32.u32 s0, s1
+0x71,0xfe,0x4d,0x8f = vpste
+0x12,0xff,0x54,0x0d = vmult.f16 q0, q1, q2
+0x12,0xff,0x54,0x0d = vmule.f16 q0, q1, q2
+0x0c,0xbf = ite eq
+0x20,0xee,0x01,0x0b = vmuleq.f64 d0, d0, d1
+0x20,0xee,0x02,0x1b = vmulne.f64 d1, d0, d2
+0x08,0xbf = it eq
+0xb1,0xee,0x60,0x0a = vnegeq.f32 s0, s1
+0x04,0xbf = itt eq
+0x20,0xee,0xc1,0x0a = vnmuleq.f32 s0, s1, s2
+0x20,0xee,0x81,0x0a = vmuleq.f32 s0, s1, s2
+0x71,0xfe,0x4d,0x8f = vpste
+0xb6,0xff,0x42,0x04 = vrintnt.f16 q0, q1
+0xba,0xff,0x42,0x04 = vrintne.f32 q0, q1
diff --git a/suite/MC/ARM/mve-integer.s.cs b/suite/MC/ARM/mve-integer.s.cs
new file mode 100644
index 000000000..7429d617c
--- /dev/null
+++ b/suite/MC/ARM/mve-integer.s.cs
@@ -0,0 +1,100 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x81,0xef,0x5b,0x0c = vmov.i32 q0, #0x1bff
+0x85,0xef,0x5c,0x08 = vmov.i16 q0, #0x5c
+0x84,0xef,0x5c,0x0e = vmov.i8 q0, #0x4c
+0x80,0xff,0x5d,0x0f = vmov.f32 q0, #-3.625000e+00
+0x84,0xef,0x50,0x0f = vmov.f32 q0, #1.250000e-01
+0x84,0xef,0x51,0x0f = vmov.f32 q0, #1.328125e-01
+0x83,0xef,0x5f,0x0f = vmov.f32 q0, #3.100000e+01
+0xb0,0xee,0x60,0x8a = vmov.f32 s16, s1
+0xb0,0xee,0x41,0x0b = vmov.f64 d0, d1
+0x81,0xff,0x7f,0x0e = vmov.i64 q0, #0xff0000ffffffffff
+0x00,0xef,0x56,0x09 = vmul.i8 q0, q0, q3
+0x10,0xef,0x56,0xc9 = vmul.i16 q6, q0, q3
+0x26,0xef,0x5c,0xe9 = vmul.i32 q7, q3, q6
+0x0a,0xff,0x4a,0x0b = vqrdmulh.s8 q0, q5, q5
+0x18,0xff,0x44,0x2b = vqrdmulh.s16 q1, q4, q2
+0x2a,0xff,0x40,0x0b = vqrdmulh.s32 q0, q5, q0
+0x08,0xef,0x4a,0x0b = vqdmulh.s8 q0, q4, q5
+0x18,0xef,0x40,0xcb = vqdmulh.s16 q6, q4, q0
+0x20,0xef,0x4c,0xab = vqdmulh.s32 q5, q0, q6
+0x04,0xff,0x4a,0x68 = vsub.i8 q3, q2, q5
+0x16,0xff,0x4c,0x08 = vsub.i16 q0, q3, q6
+0x20,0xff,0x4c,0x08 = vsub.i32 q0, q0, q6
+0x04,0xef,0x44,0x08 = vadd.i8 q0, q2, q2
+0x14,0xef,0x42,0x48 = vadd.i16 q2, q2, q1
+0x20,0xef,0x4c,0x08 = vadd.i32 q0, q0, q6
+0x0c,0xef,0x50,0x22 = vqsub.s8 q1, q6, q0
+0x1c,0xef,0x52,0x02 = vqsub.s16 q0, q6, q1
+0x20,0xef,0x5a,0x02 = vqsub.s32 q0, q0, q5
+0x04,0xff,0x5c,0x02 = vqsub.u8 q0, q2, q6
+0x1e,0xff,0x52,0x02 = vqsub.u16 q0, q7, q1
+0x28,0xff,0x5e,0x22 = vqsub.u32 q1, q4, q7
+0x02,0xef,0x54,0x00 = vqadd.s8 q0, q1, q2
+0x08,0xef,0x5c,0x00 = vqadd.s8 q0, q4, q6
+0x1a,0xef,0x5a,0x00 = vqadd.s16 q0, q5, q5
+0x20,0xef,0x58,0x00 = vqadd.s32 q0, q0, q4
+0x08,0xff,0x54,0x00 = vqadd.u8 q0, q4, q2
+0x1c,0xff,0x5c,0x80 = vqadd.u16 q4, q6, q6
+0x22,0xff,0x54,0x00 = vqadd.u32 q0, q1, q2
+0x00,0xef,0x44,0x07 = vabd.s8 q0, q0, q2
+0x1a,0xef,0x48,0x27 = vabd.s16 q1, q5, q4
+0x26,0xef,0x44,0x47 = vabd.s32 q2, q3, q2
+0x0c,0xff,0x48,0x27 = vabd.u8 q1, q6, q4
+0x1c,0xff,0x44,0x07 = vabd.u16 q0, q6, q2
+0x2e,0xff,0x48,0x07 = vabd.u32 q0, q7, q4
+0x02,0xef,0x42,0x01 = vrhadd.s8 q0, q1, q1
+0x12,0xef,0x40,0x01 = vrhadd.s16 q0, q1, q0
+0x28,0xef,0x42,0x01 = vrhadd.s32 q0, q4, q1
+0x00,0xff,0x4c,0x21 = vrhadd.u8 q1, q0, q6
+0x14,0xff,0x4a,0x41 = vrhadd.u16 q2, q2, q5
+0x26,0xff,0x40,0x41 = vrhadd.u32 q2, q3, q0
+0x00,0xef,0x44,0x02 = vhsub.s8 q0, q0, q2
+0x16,0xef,0x42,0x22 = vhsub.s16 q1, q3, q1
+0x24,0xef,0x4a,0x02 = vhsub.s32 q0, q2, q5
+0x08,0xff,0x44,0x02 = vhsub.u8 q0, q4, q2
+0x1e,0xff,0x4a,0x02 = vhsub.u16 q0, q7, q5
+0x2c,0xff,0x48,0x42 = vhsub.u32 q2, q6, q4
+0x0e,0xef,0x40,0x00 = vhadd.s8 q0, q7, q0
+0x10,0xef,0x44,0x80 = vhadd.s16 q4, q0, q2
+0x26,0xef,0x42,0x00 = vhadd.s32 q0, q3, q1
+0x00,0xff,0x46,0x60 = vhadd.u8 q3, q0, q3
+0x12,0xff,0x46,0x00 = vhadd.u16 q0, q1, q3
+0x22,0xff,0x46,0x00 = vhadd.u32 q0, q1, q3
+0xec,0xee,0x10,0x8b = vdup.8 q6, r8
+0xae,0xee,0x30,0xeb = vdup.16 q7, lr
+0xa2,0xee,0x10,0x9b = vdup.32 q1, r9
+0xa0,0xee,0x30,0x1b = vdup.16 q0, r1
+0xa0,0xee,0x30,0x1b = vdup.16 q0, r1
+0xb0,0xff,0x42,0x44 = vcls.s8 q2, q1
+0xb4,0xff,0x48,0x04 = vcls.s16 q0, q4
+0xb8,0xff,0x40,0x04 = vcls.s32 q0, q0
+0xb0,0xff,0xce,0x04 = vclz.i8 q0, q7
+0xb4,0xff,0xce,0x84 = vclz.i16 q4, q7
+0xb8,0xff,0xca,0xe4 = vclz.i32 q7, q5
+0xb1,0xff,0xc0,0x23 = vneg.s8 q1, q0
+0xb5,0xff,0xc2,0x03 = vneg.s16 q0, q1
+0xb9,0xff,0xc4,0xe3 = vneg.s32 q7, q2
+0xb1,0xff,0x42,0x23 = vabs.s8 q1, q1
+0xb5,0xff,0x44,0x03 = vabs.s16 q0, q2
+0xb9,0xff,0x4e,0x03 = vabs.s32 q0, q7
+0xb0,0xff,0xc0,0x07 = vqneg.s8 q0, q0
+0xb4,0xff,0xc4,0xc7 = vqneg.s16 q6, q2
+0xb8,0xff,0xc4,0xe7 = vqneg.s32 q7, q2
+0xb0,0xff,0x48,0x47 = vqabs.s8 q2, q4
+0xb4,0xff,0x44,0x07 = vqabs.s16 q0, q2
+0xb8,0xff,0x4a,0x07 = vqabs.s32 q0, q5
+0x71,0xfe,0x4d,0x8f = vpste
+0xb1,0xff,0xc2,0x03 = vnegt.s8 q0, q1
+0xb1,0xff,0xc2,0x03 = vnege.s8 q0, q1
+0x71,0xfe,0x4d,0x0f = vpst
+0x12,0xef,0x54,0x00 = vqaddt.s16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0xb0,0xff,0xc2,0x07 = vqnegt.s8 q0, q1
+0xb4,0xff,0xc2,0x07 = vqnege.s16 q0, q1
+0x33,0xee,0x8f,0x3e = vmina.s8 q1, q7
+0x37,0xee,0x89,0x3e = vmina.s16 q1, q4
+0x3b,0xee,0x8f,0x1e = vmina.s32 q0, q7
+0x33,0xee,0x8f,0x0e = vmaxa.s8 q0, q7
+0x37,0xee,0x81,0x2e = vmaxa.s16 q1, q0
+0x3b,0xee,0x81,0x2e = vmaxa.s32 q1, q0
diff --git a/suite/MC/ARM/mve-interleave.s.cs b/suite/MC/ARM/mve-interleave.s.cs
new file mode 100644
index 000000000..5383ad790
--- /dev/null
+++ b/suite/MC/ARM/mve-interleave.s.cs
@@ -0,0 +1,68 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x9d,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [sp]
+0x90,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]
+0xb0,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]!
+0x9b,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r11]
+0xb0,0xfc,0x00,0xbe = vld20.8 {q5, q6}, [r0]!
+0x90,0xfc,0x20,0x1e = vld21.8 {q0, q1}, [r0]
+0xb0,0xfc,0x20,0x7e = vld21.8 {q3, q4}, [r0]!
+0x90,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]
+0xb0,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]!
+0x9b,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r11]
+0xb0,0xfc,0x80,0xbe = vld20.16 {q5, q6}, [r0]!
+0x90,0xfc,0xa0,0x1e = vld21.16 {q0, q1}, [r0]
+0xb0,0xfc,0xa0,0x7e = vld21.16 {q3, q4}, [r0]!
+0x90,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]
+0xb0,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]!
+0x9b,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r11]
+0xb0,0xfc,0x00,0xbf = vld20.32 {q5, q6}, [r0]!
+0x90,0xfc,0x20,0x1f = vld21.32 {q0, q1}, [r0]
+0xb0,0xfc,0x20,0x7f = vld21.32 {q3, q4}, [r0]!
+0x80,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]
+0xa0,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]!
+0x8b,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r11]
+0xa0,0xfc,0x00,0xbe = vst20.8 {q5, q6}, [r0]!
+0x80,0xfc,0x20,0x1e = vst21.8 {q0, q1}, [r0]
+0xa0,0xfc,0x20,0x7e = vst21.8 {q3, q4}, [r0]!
+0x80,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]
+0xa0,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]!
+0x8b,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r11]
+0xa0,0xfc,0x80,0xbe = vst20.16 {q5, q6}, [r0]!
+0x80,0xfc,0xa0,0x1e = vst21.16 {q0, q1}, [r0]
+0xa0,0xfc,0xa0,0x7e = vst21.16 {q3, q4}, [r0]!
+0x80,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]
+0xa0,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]!
+0x8b,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r11]
+0xa0,0xfc,0x00,0xbf = vst20.32 {q5, q6}, [r0]!
+0x80,0xfc,0x20,0x1f = vst21.32 {q0, q1}, [r0]
+0xa0,0xfc,0x20,0x7f = vst21.32 {q3, q4}, [r0]!
+0x90,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]!
+0x9b,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r11]
+0xb0,0xfc,0x01,0x7e = vld40.8 {q3, q4, q5, q6}, [r0]!
+0x90,0xfc,0x21,0x1e = vld41.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x21,0x9e = vld41.8 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]!
+0x90,0xfc,0x61,0x1e = vld43.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x61,0x9e = vld43.8 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]!
+0x9b,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r11]
+0xb0,0xfc,0x81,0x7e = vld40.16 {q3, q4, q5, q6}, [r0]!
+0x90,0xfc,0xa1,0x1e = vld41.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0xa1,0x9e = vld41.16 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]!
+0x90,0xfc,0xe1,0x1e = vld43.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0xe1,0x9e = vld43.16 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]!
+0x9b,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r11]
+0xb0,0xfc,0x01,0x7f = vld40.32 {q3, q4, q5, q6}, [r0]!
+0x90,0xfc,0x21,0x1f = vld41.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x21,0x9f = vld41.32 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]!
+0x90,0xfc,0x61,0x1f = vld43.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x61,0x9f = vld43.32 {q4, q5, q6, q7}, [r0]!
diff --git a/suite/MC/ARM/mve-load-store.s.cs b/suite/MC/ARM/mve-load-store.s.cs
new file mode 100644
index 000000000..5ffe9951e
--- /dev/null
+++ b/suite/MC/ARM/mve-load-store.s.cs
@@ -0,0 +1,443 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x90,0xed,0x00,0x1e = vldrb.u8 q0, [r0]
+0x90,0xed,0x00,0x3e = vldrb.u8 q1, [r0]
+0x9b,0xed,0x00,0x1e = vldrb.u8 q0, [r11]
+0x9b,0xed,0x00,0x7e = vldrb.u8 q3, [r11]
+0x94,0xed,0x38,0x1e = vldrb.u8 q0, [r4, #0x38]
+0x94,0xed,0x38,0x9e = vldrb.u8 q4, [r4, #0x38]
+0x98,0xed,0x38,0x1e = vldrb.u8 q0, [r8, #0x38]
+0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]!
+0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]!
+0x34,0xec,0x19,0xbe = vldrb.u8 q5, [r4], #-0x19
+0x3a,0xec,0x19,0xbe = vldrb.u8 q5, [r10], #-0x19
+0x1d,0xed,0x19,0xbe = vldrb.u8 q5, [sp, #-0x19]
+0x1d,0xed,0x7f,0xbe = vldrb.u8 q5, [sp, #-0x7f]
+0x80,0xed,0x00,0x1e = vstrb.8 q0, [r0]
+0x80,0xed,0x00,0x3e = vstrb.8 q1, [r0]
+0x8b,0xed,0x00,0x1e = vstrb.8 q0, [r11]
+0x8b,0xed,0x00,0x7e = vstrb.8 q3, [r11]
+0x84,0xed,0x38,0x1e = vstrb.8 q0, [r4, #0x38]
+0x84,0xed,0x38,0x9e = vstrb.8 q4, [r4, #0x38]
+0x88,0xed,0x38,0x1e = vstrb.8 q0, [r8, #0x38]
+0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]!
+0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]!
+0x24,0xec,0x19,0xbe = vstrb.8 q5, [r4], #-0x19
+0x2a,0xec,0x19,0xbe = vstrb.8 q5, [r10], #-0x19
+0x0d,0xed,0x19,0xbe = vstrb.8 q5, [sp, #-0x19]
+0x8d,0xed,0x7f,0xbe = vstrb.8 q5, [sp, #0x7f]
+0x90,0xfd,0x80,0x0e = vldrb.u16 q0, [r0]
+0x90,0xfd,0x80,0x2e = vldrb.u16 q1, [r0]
+0x97,0xfd,0x80,0x0e = vldrb.u16 q0, [r7]
+0x97,0xfd,0x80,0x6e = vldrb.u16 q3, [r7]
+0x94,0xfd,0xb8,0x0e = vldrb.u16 q0, [r4, #0x38]
+0x94,0xfd,0xb8,0x8e = vldrb.u16 q4, [r4, #0x38]
+0x92,0xfd,0xb8,0x0e = vldrb.u16 q0, [r2, #0x38]
+0xb4,0xfd,0xb8,0xae = vldrb.u16 q5, [r4, #0x38]!
+0xb4,0xfd,0xb8,0xae = vldrb.u16 q5, [r4, #0x38]!
+0x34,0xfc,0x81,0xae = vldrb.u16 q5, [r4], #-1
+0x33,0xfc,0x99,0xae = vldrb.u16 q5, [r3], #-0x19
+0x16,0xfd,0x99,0xae = vldrb.u16 q5, [r6, #-0x19]
+0x16,0xfd,0xc0,0xae = vldrb.u16 q5, [r6, #-0x40]
+0x90,0xed,0x80,0x0e = vldrb.s16 q0, [r0]
+0x90,0xed,0x80,0x2e = vldrb.s16 q1, [r0]
+0x97,0xed,0x80,0x0e = vldrb.s16 q0, [r7]
+0x97,0xed,0x80,0x6e = vldrb.s16 q3, [r7]
+0x94,0xed,0xb8,0x0e = vldrb.s16 q0, [r4, #0x38]
+0x94,0xed,0xb8,0x8e = vldrb.s16 q4, [r4, #0x38]
+0x92,0xed,0xb8,0x0e = vldrb.s16 q0, [r2, #0x38]
+0xb4,0xed,0xb8,0xae = vldrb.s16 q5, [r4, #0x38]!
+0xb4,0xed,0xb8,0xae = vldrb.s16 q5, [r4, #0x38]!
+0x34,0xec,0x99,0xae = vldrb.s16 q5, [r4], #-0x19
+0x33,0xec,0x99,0xae = vldrb.s16 q5, [r3], #-0x19
+0x16,0xed,0x99,0xae = vldrb.s16 q5, [r6, #-0x19]
+0x16,0xed,0xc0,0xae = vldrb.s16 q5, [r6, #-0x40]
+0x80,0xed,0x80,0x0e = vstrb.16 q0, [r0]
+0x80,0xed,0x80,0x2e = vstrb.16 q1, [r0]
+0x87,0xed,0x80,0x0e = vstrb.16 q0, [r7]
+0x87,0xed,0x80,0x6e = vstrb.16 q3, [r7]
+0x84,0xed,0xb8,0x0e = vstrb.16 q0, [r4, #0x38]
+0x84,0xed,0xb8,0x8e = vstrb.16 q4, [r4, #0x38]
+0x85,0xed,0xb8,0x0e = vstrb.16 q0, [r5, #0x38]
+0xa4,0xed,0xb8,0xae = vstrb.16 q5, [r4, #0x38]!
+0xa4,0xed,0xb8,0xae = vstrb.16 q5, [r4, #0x38]!
+0x24,0xec,0x99,0xae = vstrb.16 q5, [r4], #-0x19
+0x23,0xec,0x99,0xae = vstrb.16 q5, [r3], #-0x19
+0x02,0xed,0x99,0xae = vstrb.16 q5, [r2, #-0x19]
+0x02,0xed,0xc0,0xae = vstrb.16 q5, [r2, #-0x40]
+0x90,0xfd,0x00,0x0f = vldrb.u32 q0, [r0]
+0x90,0xfd,0x00,0x2f = vldrb.u32 q1, [r0]
+0x97,0xfd,0x00,0x0f = vldrb.u32 q0, [r7]
+0x97,0xfd,0x00,0x6f = vldrb.u32 q3, [r7]
+0x94,0xfd,0x38,0x0f = vldrb.u32 q0, [r4, #0x38]
+0x94,0xfd,0x38,0x8f = vldrb.u32 q4, [r4, #0x38]
+0x92,0xfd,0x38,0x0f = vldrb.u32 q0, [r2, #0x38]
+0xb4,0xfd,0x38,0xaf = vldrb.u32 q5, [r4, #0x38]!
+0xb4,0xfd,0x38,0xaf = vldrb.u32 q5, [r4, #0x38]!
+0x34,0xfc,0x19,0xaf = vldrb.u32 q5, [r4], #-0x19
+0x33,0xfc,0x19,0xaf = vldrb.u32 q5, [r3], #-0x19
+0x16,0xfd,0x19,0xaf = vldrb.u32 q5, [r6, #-0x19]
+0x16,0xfd,0x40,0xaf = vldrb.u32 q5, [r6, #-0x40]
+0x90,0xed,0x00,0x0f = vldrb.s32 q0, [r0]
+0x90,0xed,0x00,0x2f = vldrb.s32 q1, [r0]
+0x97,0xed,0x00,0x0f = vldrb.s32 q0, [r7]
+0x97,0xed,0x00,0x6f = vldrb.s32 q3, [r7]
+0x94,0xed,0x38,0x0f = vldrb.s32 q0, [r4, #0x38]
+0x94,0xed,0x38,0x8f = vldrb.s32 q4, [r4, #0x38]
+0x92,0xed,0x38,0x0f = vldrb.s32 q0, [r2, #0x38]
+0xb4,0xed,0x38,0xaf = vldrb.s32 q5, [r4, #0x38]!
+0xb4,0xed,0x38,0xaf = vldrb.s32 q5, [r4, #0x38]!
+0x34,0xec,0x19,0xaf = vldrb.s32 q5, [r4], #-0x19
+0x33,0xec,0x19,0xaf = vldrb.s32 q5, [r3], #-0x19
+0x16,0xed,0x19,0xaf = vldrb.s32 q5, [r6, #-0x19]
+0x16,0xed,0x40,0xaf = vldrb.s32 q5, [r6, #-0x40]
+0x80,0xed,0x00,0x0f = vstrb.32 q0, [r0]
+0x80,0xed,0x00,0x2f = vstrb.32 q1, [r0]
+0x87,0xed,0x00,0x0f = vstrb.32 q0, [r7]
+0x87,0xed,0x00,0x6f = vstrb.32 q3, [r7]
+0x84,0xed,0x38,0x0f = vstrb.32 q0, [r4, #0x38]
+0x84,0xed,0x38,0x8f = vstrb.32 q4, [r4, #0x38]
+0x85,0xed,0x38,0x0f = vstrb.32 q0, [r5, #0x38]
+0xa4,0xed,0x38,0xaf = vstrb.32 q5, [r4, #0x38]!
+0xa4,0xed,0x38,0xaf = vstrb.32 q5, [r4, #0x38]!
+0x24,0xec,0x19,0xaf = vstrb.32 q5, [r4], #-0x19
+0x23,0xec,0x19,0xaf = vstrb.32 q5, [r3], #-0x19
+0x02,0xed,0x19,0xaf = vstrb.32 q5, [r2, #-0x19]
+0x02,0xed,0x40,0xaf = vstrb.32 q5, [r2, #-0x40]
+0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0]
+0x90,0xed,0x80,0x3e = vldrh.u16 q1, [r0]
+0x9b,0xed,0x80,0x1e = vldrh.u16 q0, [r11]
+0x9b,0xed,0x80,0x7e = vldrh.u16 q3, [r11]
+0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38]
+0x94,0xed,0x9c,0x9e = vldrh.u16 q4, [r4, #0x38]
+0x98,0xed,0x9c,0x1e = vldrh.u16 q0, [r8, #0x38]
+0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]!
+0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]!
+0x34,0xec,0x8d,0xbe = vldrh.u16 q5, [r4], #-0x1a
+0x3a,0xec,0x8d,0xbe = vldrh.u16 q5, [r10], #-0x1a
+0x1d,0xed,0x8d,0xbe = vldrh.u16 q5, [sp, #-0x1a]
+0x1d,0xed,0xa0,0xbe = vldrh.u16 q5, [sp, #-0x40]
+0x1d,0xed,0xff,0xbe = vldrh.u16 q5, [sp, #-0xfe]
+0xba,0xec,0xff,0xbe = vldrh.u16 q5, [r10], #0xfe
+0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0]
+0x80,0xed,0x80,0x3e = vstrh.16 q1, [r0]
+0x8b,0xed,0x80,0x1e = vstrh.16 q0, [r11]
+0x8b,0xed,0x80,0x7e = vstrh.16 q3, [r11]
+0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38]
+0x84,0xed,0x9c,0x9e = vstrh.16 q4, [r4, #0x38]
+0x88,0xed,0x9c,0x1e = vstrh.16 q0, [r8, #0x38]
+0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]!
+0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]!
+0x24,0xec,0x8d,0xbe = vstrh.16 q5, [r4], #-0x1a
+0x2a,0xec,0x8d,0xbe = vstrh.16 q5, [r10], #-0x1a
+0x0d,0xed,0x8d,0xbe = vstrh.16 q5, [sp, #-0x1a]
+0x0d,0xed,0xa0,0xbe = vstrh.16 q5, [sp, #-0x40]
+0x0d,0xed,0xff,0xbe = vstrh.16 q5, [sp, #-0xfe]
+0xaa,0xec,0xff,0xbe = vstrh.16 q5, [r10], #0xfe
+0x98,0xfd,0x00,0x0f = vldrh.u32 q0, [r0]
+0x98,0xfd,0x00,0x2f = vldrh.u32 q1, [r0]
+0x9f,0xfd,0x00,0x0f = vldrh.u32 q0, [r7]
+0x9f,0xfd,0x00,0x6f = vldrh.u32 q3, [r7]
+0x9c,0xfd,0x1c,0x0f = vldrh.u32 q0, [r4, #0x38]
+0x9c,0xfd,0x1c,0x8f = vldrh.u32 q4, [r4, #0x38]
+0x9a,0xfd,0x1c,0x0f = vldrh.u32 q0, [r2, #0x38]
+0xbc,0xfd,0x1c,0xaf = vldrh.u32 q5, [r4, #0x38]!
+0xbc,0xfd,0x1c,0xaf = vldrh.u32 q5, [r4, #0x38]!
+0x3c,0xfc,0x0d,0xaf = vldrh.u32 q5, [r4], #-0x1a
+0x3b,0xfc,0x0d,0xaf = vldrh.u32 q5, [r3], #-0x1a
+0x1e,0xfd,0x0d,0xaf = vldrh.u32 q5, [r6, #-0x1a]
+0x1e,0xfd,0x20,0xaf = vldrh.u32 q5, [r6, #-0x40]
+0x1e,0xfd,0x7f,0xaf = vldrh.u32 q5, [r6, #-0xfe]
+0xbc,0xfd,0x7f,0xaf = vldrh.u32 q5, [r4, #0xfe]!
+0x98,0xed,0x00,0x0f = vldrh.s32 q0, [r0]
+0x98,0xed,0x00,0x2f = vldrh.s32 q1, [r0]
+0x9f,0xed,0x00,0x0f = vldrh.s32 q0, [r7]
+0x9f,0xed,0x00,0x6f = vldrh.s32 q3, [r7]
+0x9c,0xed,0x1c,0x0f = vldrh.s32 q0, [r4, #0x38]
+0x9c,0xed,0x1c,0x8f = vldrh.s32 q4, [r4, #0x38]
+0x9a,0xed,0x1c,0x0f = vldrh.s32 q0, [r2, #0x38]
+0xbc,0xed,0x1c,0xaf = vldrh.s32 q5, [r4, #0x38]!
+0xbc,0xed,0x1c,0xaf = vldrh.s32 q5, [r4, #0x38]!
+0x3c,0xec,0x0d,0xaf = vldrh.s32 q5, [r4], #-0x1a
+0x3b,0xec,0x0d,0xaf = vldrh.s32 q5, [r3], #-0x1a
+0x1e,0xed,0x0d,0xaf = vldrh.s32 q5, [r6, #-0x1a]
+0x1e,0xed,0x20,0xaf = vldrh.s32 q5, [r6, #-0x40]
+0x1e,0xed,0x7f,0xaf = vldrh.s32 q5, [r6, #-0xfe]
+0xbc,0xed,0x7f,0xaf = vldrh.s32 q5, [r4, #0xfe]!
+0x88,0xed,0x00,0x0f = vstrh.32 q0, [r0]
+0x88,0xed,0x00,0x2f = vstrh.32 q1, [r0]
+0x8f,0xed,0x00,0x0f = vstrh.32 q0, [r7]
+0x8f,0xed,0x00,0x6f = vstrh.32 q3, [r7]
+0x8c,0xed,0x1c,0x0f = vstrh.32 q0, [r4, #0x38]
+0x8c,0xed,0x1c,0x8f = vstrh.32 q4, [r4, #0x38]
+0x8d,0xed,0x1c,0x0f = vstrh.32 q0, [r5, #0x38]
+0xac,0xed,0x1c,0xaf = vstrh.32 q5, [r4, #0x38]!
+0xac,0xed,0x1c,0xaf = vstrh.32 q5, [r4, #0x38]!
+0x2c,0xec,0x0d,0xaf = vstrh.32 q5, [r4], #-0x1a
+0x2b,0xec,0x0d,0xaf = vstrh.32 q5, [r3], #-0x1a
+0x0a,0xed,0x0d,0xaf = vstrh.32 q5, [r2, #-0x1a]
+0x0a,0xed,0x20,0xaf = vstrh.32 q5, [r2, #-0x40]
+0x0a,0xed,0x7f,0xaf = vstrh.32 q5, [r2, #-0xfe]
+0xac,0xed,0x7f,0xaf = vstrh.32 q5, [r4, #0xfe]!
+0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0]
+0x90,0xed,0x00,0x3f = vldrw.u32 q1, [r0]
+0x9b,0xed,0x00,0x1f = vldrw.u32 q0, [r11]
+0x9b,0xed,0x00,0x7f = vldrw.u32 q3, [r11]
+0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38]
+0x94,0xed,0x0e,0x9f = vldrw.u32 q4, [r4, #0x38]
+0x98,0xed,0x0e,0x1f = vldrw.u32 q0, [r8, #0x38]
+0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]!
+0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]!
+0x34,0xec,0x07,0xbf = vldrw.u32 q5, [r4], #-0x1c
+0x3a,0xec,0x07,0xbf = vldrw.u32 q5, [r10], #-0x1c
+0x1d,0xed,0x07,0xbf = vldrw.u32 q5, [sp, #-0x1c]
+0x1d,0xed,0x10,0xbf = vldrw.u32 q5, [sp, #-0x40]
+0x1d,0xed,0x7f,0xbf = vldrw.u32 q5, [sp, #-0x1fc]
+0xb4,0xed,0x7f,0xbf = vldrw.u32 q5, [r4, #0x1fc]!
+0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0]
+0x80,0xed,0x00,0x3f = vstrw.32 q1, [r0]
+0x8b,0xed,0x00,0x1f = vstrw.32 q0, [r11]
+0x8b,0xed,0x00,0x7f = vstrw.32 q3, [r11]
+0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38]
+0x84,0xed,0x0e,0x9f = vstrw.32 q4, [r4, #0x38]
+0x88,0xed,0x0e,0x1f = vstrw.32 q0, [r8, #0x38]
+0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]!
+0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]!
+0x24,0xec,0x07,0xbf = vstrw.32 q5, [r4], #-0x1c
+0x2a,0xec,0x07,0xbf = vstrw.32 q5, [r10], #-0x1c
+0x0d,0xed,0x07,0xbf = vstrw.32 q5, [sp, #-0x1c]
+0x0d,0xed,0x10,0xbf = vstrw.32 q5, [sp, #-0x40]
+0x0d,0xed,0x7f,0xbf = vstrw.32 q5, [sp, #-0x1fc]
+0xa4,0xed,0x7f,0xbf = vstrw.32 q5, [r4, #0x1fc]!
+0x90,0xfc,0x02,0x0e = vldrb.u8 q0, [r0, q1]
+0x9a,0xfc,0x02,0x6e = vldrb.u8 q3, [r10, q1]
+0x90,0xfc,0x82,0x0e = vldrb.u16 q0, [r0, q1]
+0x99,0xfc,0x82,0x6e = vldrb.u16 q3, [r9, q1]
+0x90,0xec,0x82,0x0e = vldrb.s16 q0, [r0, q1]
+0x9d,0xec,0x82,0x6e = vldrb.s16 q3, [sp, q1]
+0x90,0xfc,0x02,0x0f = vldrb.u32 q0, [r0, q1]
+0x90,0xfc,0x02,0x6f = vldrb.u32 q3, [r0, q1]
+0x90,0xec,0x02,0x0f = vldrb.s32 q0, [r0, q1]
+0x90,0xec,0x02,0x6f = vldrb.s32 q3, [r0, q1]
+0x90,0xfc,0x92,0x0e = vldrh.u16 q0, [r0, q1]
+0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1]
+0x90,0xfc,0x12,0x0f = vldrh.u32 q0, [r0, q1]
+0x90,0xfc,0x12,0x6f = vldrh.u32 q3, [r0, q1]
+0x90,0xec,0x12,0x0f = vldrh.s32 q0, [r0, q1]
+0x90,0xec,0x12,0x6f = vldrh.s32 q3, [r0, q1]
+0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1]
+0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1]
+0x90,0xfc,0x42,0x6f = vldrw.u32 q3, [r0, q1]
+0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2]
+0x9d,0xfc,0x43,0x0f = vldrw.u32 q0, [sp, q1, uxtw #2]
+0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1]
+0x90,0xfc,0xd2,0x6f = vldrd.u64 q3, [r0, q1]
+0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3]
+0x9d,0xfc,0xd3,0x0f = vldrd.u64 q0, [sp, q1, uxtw #3]
+0x80,0xec,0x02,0x0e = vstrb.8 q0, [r0, q1]
+0x8a,0xec,0x02,0x6e = vstrb.8 q3, [r10, q1]
+0x80,0xec,0x06,0x6e = vstrb.8 q3, [r0, q3]
+0x80,0xec,0x82,0x0e = vstrb.16 q0, [r0, q1]
+0x8d,0xec,0x82,0x6e = vstrb.16 q3, [sp, q1]
+0x80,0xec,0x86,0x6e = vstrb.16 q3, [r0, q3]
+0x80,0xec,0x02,0x0f = vstrb.32 q0, [r0, q1]
+0x80,0xec,0x02,0x6f = vstrb.32 q3, [r0, q1]
+0x80,0xec,0x06,0x6f = vstrb.32 q3, [r0, q3]
+0x80,0xec,0x92,0x0e = vstrh.16 q0, [r0, q1]
+0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1]
+0x80,0xec,0x96,0x6e = vstrh.16 q3, [r0, q3]
+0x80,0xec,0x12,0x0f = vstrh.32 q0, [r0, q1]
+0x80,0xec,0x12,0x6f = vstrh.32 q3, [r0, q1]
+0x80,0xec,0x16,0x6f = vstrh.32 q3, [r0, q3]
+0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1]
+0x88,0xec,0x17,0x6f = vstrh.32 q3, [r8, q3, uxtw #1]
+0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1]
+0x80,0xec,0x42,0x6f = vstrw.32 q3, [r0, q1]
+0x80,0xec,0x46,0x6f = vstrw.32 q3, [r0, q3]
+0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2]
+0x8d,0xec,0x43,0x0f = vstrw.32 q0, [sp, q1, uxtw #2]
+0x80,0xec,0xd2,0x0f = vstrd.64 q0, [r0, q1]
+0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1]
+0x80,0xec,0xd6,0x6f = vstrd.64 q3, [r0, q3]
+0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3]
+0x8d,0xec,0xd3,0x0f = vstrd.64 q0, [sp, q1, uxtw #3]
+0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1]
+0x92,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]
+0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]!
+0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]
+0x12,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #-4]
+0x92,0xfd,0x7f,0xfe = vldrw.u32 q7, [q1, #0x1fc]
+0x12,0xfd,0x7f,0xfe = vldrw.u32 q7, [q1, #-0x1fc]
+0x92,0xfd,0x42,0xfe = vldrw.u32 q7, [q1, #0x108]
+0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]!
+0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1]
+0x82,0xfd,0x00,0x3e = vstrw.32 q1, [q1]
+0x82,0xfd,0x00,0xfe = vstrw.32 q7, [q1]
+0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]!
+0x8e,0xfd,0x00,0xfe = vstrw.32 q7, [q7]
+0x82,0xfd,0x01,0xfe = vstrw.32 q7, [q1, #4]
+0x02,0xfd,0x01,0xfe = vstrw.32 q7, [q1, #-4]
+0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc]
+0x02,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #-0x1fc]
+0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]!
+0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1]
+0x92,0xfd,0x00,0xff = vldrd.u64 q7, [q1]
+0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]!
+0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8]
+0x12,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #-8]
+0x92,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #0x3f8]
+0x12,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]
+0x92,0xfd,0x21,0xff = vldrd.u64 q7, [q1, #0x108]
+0x92,0xfd,0x4e,0xff = vldrd.u64 q7, [q1, #0x270]
+0x92,0xfd,0x21,0xff = vldrd.u64 q7, [q1, #0x108]
+0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]!
+0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1]
+0x82,0xfd,0x00,0x3f = vstrd.64 q1, [q1]
+0x82,0xfd,0x00,0xff = vstrd.64 q7, [q1]
+0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]!
+0x8e,0xfd,0x00,0xff = vstrd.64 q7, [q7]
+0x82,0xfd,0x01,0xff = vstrd.64 q7, [q1, #8]
+0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]!
+0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8]
+0x02,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #-0x3f8]
+0x82,0xfd,0x21,0xff = vstrd.64 q7, [q1, #0x108]
+0x82,0xfd,0x4e,0xff = vstrd.64 q7, [q1, #0x270]
+0x82,0xfd,0x21,0xff = vstrd.64 q7, [q1, #0x108]
+0x90,0xed,0x00,0x1e = vldrb.u8 q0, [r0]
+0x90,0xed,0x00,0x1e = vldrb.u8 q0, [r0]
+0x98,0xed,0x38,0x1e = vldrb.u8 q0, [r8, #0x38]
+0x98,0xed,0x38,0x1e = vldrb.u8 q0, [r8, #0x38]
+0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]!
+0xb4,0xed,0x38,0xbe = vldrb.u8 q5, [r4, #0x38]!
+0x80,0xed,0x00,0x1e = vstrb.8 q0, [r0]
+0x80,0xed,0x00,0x1e = vstrb.8 q0, [r0]
+0x84,0xed,0x38,0x9e = vstrb.8 q4, [r4, #0x38]
+0x84,0xed,0x38,0x9e = vstrb.8 q4, [r4, #0x38]
+0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]!
+0xa4,0xed,0x38,0xbe = vstrb.8 q5, [r4, #0x38]!
+0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0]
+0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0]
+0x90,0xed,0x80,0x1e = vldrh.u16 q0, [r0]
+0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38]
+0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38]
+0x94,0xed,0x9c,0x1e = vldrh.u16 q0, [r4, #0x38]
+0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]!
+0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]!
+0xb4,0xed,0x9c,0xbe = vldrh.u16 q5, [r4, #0x38]!
+0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0]
+0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0]
+0x80,0xed,0x80,0x1e = vstrh.16 q0, [r0]
+0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38]
+0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38]
+0x84,0xed,0x9c,0x1e = vstrh.16 q0, [r4, #0x38]
+0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]!
+0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]!
+0xa4,0xed,0x9c,0xbe = vstrh.16 q5, [r4, #0x38]!
+0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0]
+0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0]
+0x90,0xed,0x00,0x1f = vldrw.u32 q0, [r0]
+0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38]
+0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38]
+0x94,0xed,0x0e,0x1f = vldrw.u32 q0, [r4, #0x38]
+0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]!
+0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]!
+0xb4,0xed,0x0e,0xbf = vldrw.u32 q5, [r4, #0x38]!
+0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0]
+0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0]
+0x80,0xed,0x00,0x1f = vstrw.32 q0, [r0]
+0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38]
+0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38]
+0x84,0xed,0x0e,0x1f = vstrw.32 q0, [r4, #0x38]
+0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]!
+0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]!
+0xa4,0xed,0x0e,0xbf = vstrw.32 q5, [r4, #0x38]!
+0x90,0xfc,0x02,0x0e = vldrb.u8 q0, [r0, q1]
+0x90,0xfc,0x02,0x0e = vldrb.u8 q0, [r0, q1]
+0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1]
+0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1]
+0x90,0xfc,0x92,0x6e = vldrh.u16 q3, [r0, q1]
+0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1]
+0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1]
+0x90,0xfc,0x93,0x0e = vldrh.u16 q0, [r0, q1, uxtw #1]
+0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1]
+0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1]
+0x90,0xfc,0x42,0x0f = vldrw.u32 q0, [r0, q1]
+0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2]
+0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2]
+0x90,0xfc,0x43,0x0f = vldrw.u32 q0, [r0, q1, uxtw #2]
+0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1]
+0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1]
+0x90,0xfc,0xd2,0x0f = vldrd.u64 q0, [r0, q1]
+0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3]
+0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3]
+0x90,0xfc,0xd3,0x0f = vldrd.u64 q0, [r0, q1, uxtw #3]
+0x80,0xec,0x02,0x0e = vstrb.8 q0, [r0, q1]
+0x80,0xec,0x02,0x0e = vstrb.8 q0, [r0, q1]
+0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1]
+0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1]
+0x80,0xec,0x92,0x6e = vstrh.16 q3, [r0, q1]
+0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1]
+0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1]
+0x80,0xec,0x93,0x0e = vstrh.16 q0, [r0, q1, uxtw #1]
+0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1]
+0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1]
+0x80,0xec,0x42,0x0f = vstrw.32 q0, [r0, q1]
+0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2]
+0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2]
+0x80,0xec,0x43,0x0f = vstrw.32 q0, [r0, q1, uxtw #2]
+0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1]
+0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1]
+0x80,0xec,0xd2,0x6f = vstrd.64 q3, [r0, q1]
+0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3]
+0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3]
+0x80,0xec,0xd3,0x0f = vstrd.64 q0, [r0, q1, uxtw #3]
+0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1]
+0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1]
+0x92,0xfd,0x00,0x1e = vldrw.u32 q0, [q1]
+0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]!
+0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]!
+0xb2,0xfd,0x00,0xfe = vldrw.u32 q7, [q1]!
+0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]
+0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]
+0x92,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]
+0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]!
+0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]!
+0xb2,0xfd,0x01,0xfe = vldrw.u32 q7, [q1, #4]!
+0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1]
+0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1]
+0x82,0xfd,0x00,0x1e = vstrw.32 q0, [q1]
+0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]!
+0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]!
+0xa2,0xfd,0x00,0xfe = vstrw.32 q7, [q1]!
+0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc]
+0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc]
+0x82,0xfd,0x7f,0xfe = vstrw.32 q7, [q1, #0x1fc]
+0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]!
+0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]!
+0xa2,0xfd,0x42,0xfe = vstrw.32 q7, [q1, #0x108]!
+0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1]
+0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1]
+0x92,0xfd,0x00,0x1f = vldrd.u64 q0, [q1]
+0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]!
+0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]!
+0xb2,0xfd,0x00,0xff = vldrd.u64 q7, [q1]!
+0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8]
+0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8]
+0x92,0xfd,0x01,0xff = vldrd.u64 q7, [q1, #8]
+0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]!
+0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]!
+0x32,0xfd,0x7f,0xff = vldrd.u64 q7, [q1, #-0x3f8]!
+0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1]
+0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1]
+0x82,0xfd,0x00,0x1f = vstrd.64 q0, [q1]
+0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]!
+0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]!
+0xa2,0xfd,0x00,0xff = vstrd.64 q7, [q1]!
+0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8]
+0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8]
+0x82,0xfd,0x7f,0xff = vstrd.64 q7, [q1, #0x3f8]
+0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]!
+0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]!
+0x22,0xfd,0x01,0xff = vstrd.64 q7, [q1, #-8]!
+0x71,0xfe,0x4d,0x8f = vpste
+0xa2,0xfd,0x42,0xfe = vstrwt.32 q7, [q1, #0x108]!
+0x92,0xfd,0x01,0xff = vldrde.u64 q7, [q1, #8]
diff --git a/suite/MC/ARM/mve-minmax.s.cs b/suite/MC/ARM/mve-minmax.s.cs
new file mode 100644
index 000000000..e094e369e
--- /dev/null
+++ b/suite/MC/ARM/mve-minmax.s.cs
@@ -0,0 +1,18 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x02,0xff,0x58,0x0f = vmaxnm.f32 q0, q1, q4
+0x30,0xff,0x52,0x6f = vminnm.f16 q3, q0, q1
+0x00,0xef,0x5e,0x66 = vmin.s8 q3, q0, q7
+0x12,0xef,0x54,0x06 = vmin.s16 q0, q1, q2
+0x22,0xef,0x54,0x06 = vmin.s32 q0, q1, q2
+0x02,0xff,0x54,0x06 = vmin.u8 q0, q1, q2
+0x12,0xff,0x54,0x06 = vmin.u16 q0, q1, q2
+0x22,0xff,0x54,0x06 = vmin.u32 q0, q1, q2
+0x00,0xef,0x4e,0x66 = vmax.s8 q3, q0, q7
+0x12,0xef,0x44,0x06 = vmax.s16 q0, q1, q2
+0x22,0xef,0x44,0x06 = vmax.s32 q0, q1, q2
+0x02,0xff,0x44,0x06 = vmax.u8 q0, q1, q2
+0x12,0xff,0x44,0x06 = vmax.u16 q0, q1, q2
+0x22,0xff,0x44,0x06 = vmax.u32 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0x02,0xef,0x54,0x06 = vmint.s8 q0, q1, q2
+0x12,0xef,0x54,0x06 = vmine.s16 q0, q1, q2
diff --git a/suite/MC/ARM/mve-misc.s.cs b/suite/MC/ARM/mve-misc.s.cs
new file mode 100644
index 000000000..b2f715a51
--- /dev/null
+++ b/suite/MC/ARM/mve-misc.s.cs
@@ -0,0 +1,30 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x3b,0xfe,0x05,0x0f = vpsel q0, q5, q2
+0x31,0xfe,0x4d,0x0f = vpnot
+0x00,0xf0,0x43,0xc3 = wlstp.8 lr, r0, #0x684
+0x10,0xf0,0x43,0xc3 = wlstp.16 lr, r0, #0x684
+0x24,0xf0,0x49,0xcd = wlstp.32 lr, r4, #0xa92
+0x3e,0xf0,0xe9,0xcd = wlstp.64 lr, lr, #0xbd2
+0x05,0xf0,0xb7,0xc6 = wlstp.8 lr, r5, #0xd6c
+0x11,0xf0,0x13,0xc2 = wlstp.16 lr, r1, #0x424
+0x27,0xf0,0xe3,0xc7 = wlstp.32 lr, r7, #0xfc4
+0x01,0xf0,0x0d,0xc9 = wlstp.8 lr, r1, #0x21a
+0x0a,0xf0,0xbf,0xc2 = wlstp.8 lr, r10, #0x57c
+0x0a,0xf0,0xc1,0xc2 = wlstp.8 lr, r10, #0x580
+0x0a,0xf0,0x9b,0xcc = wlstp.8 lr, r10, #0x936
+0x0a,0xf0,0xfb,0xcf = wlstp.8 lr, r10, #0xff6
+0x0b,0xf0,0xd1,0xca = wlstp.8 lr, r11, #0x5a2
+0x35,0xf0,0x01,0xc0 = wlstp.64 lr, r5, #0
+0x05,0xf0,0x01,0xe0 = dlstp.8 lr, r5
+0x15,0xf0,0x01,0xe0 = dlstp.16 lr, r5
+0x27,0xf0,0x01,0xe0 = dlstp.32 lr, r7
+0x32,0xf0,0x01,0xe0 = dlstp.64 lr, r2
+0x1f,0xf0,0x01,0xc8 = letp lr, #-2
+0x1f,0xf0,0x05,0xc0 = letp lr, #-8
+0x1f,0xf0,0xff,0xcf = letp lr, #-0xffe
+0x0f,0xf0,0x01,0xe0 = lctp
+0x08,0xbf = it eq
+0x0f,0xf0,0x01,0xe0 = lctpeq
+0x71,0xfe,0x4d,0x8f = vpste
+0x33,0xfe,0x05,0x0f = vpselt q0, q1, q2
+0x33,0xfe,0x05,0x0f = vpsele q0, q1, q2
diff --git a/suite/MC/ARM/mve-qdest-qsrc.s.cs b/suite/MC/ARM/mve-qdest-qsrc.s.cs
new file mode 100644
index 000000000..1a847fbe3
--- /dev/null
+++ b/suite/MC/ARM/mve-qdest-qsrc.s.cs
@@ -0,0 +1,135 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x3f,0xee,0x09,0x2e = vcvtb.f16.f32 q1, q4
+0x3f,0xfe,0x03,0x1e = vcvtt.f32.f16 q0, q1
+0xb2,0xee,0xc0,0x0b = vcvtt.f64.f16 d0, s0
+0xf3,0xee,0xc2,0x0b = vcvtt.f16.f64 s1, d2
+0x3f,0xee,0x09,0x3e = vcvtt.f16.f32 q1, q4
+0x0c,0xee,0x0c,0x3e = vqdmladhx.s8 q1, q6, q6
+0x12,0xee,0x08,0x1e = vqdmladhx.s16 q0, q1, q4
+0x26,0xee,0x0e,0x1e = vqdmladhx.s32 q0, q3, q7
+0x02,0xee,0x02,0x0e = vqdmladh.s8 q0, q1, q1
+0x14,0xee,0x04,0x0e = vqdmladh.s16 q0, q2, q2
+0x2a,0xee,0x0e,0x2e = vqdmladh.s32 q1, q5, q7
+0x0e,0xee,0x01,0x1e = vqrdmladhx.s8 q0, q7, q0
+0x10,0xee,0x03,0x1e = vqrdmladhx.s16 q0, q0, q1
+0x20,0xee,0x09,0x3e = vqrdmladhx.s32 q1, q0, q4
+0x22,0xee,0x01,0x3e = vqrdmladhx.s32 q1, q1, q0
+0x20,0xee,0x03,0x3e = vqrdmladhx.s32 q1, q0, q1
+0x0c,0xee,0x05,0x0e = vqrdmladh.s8 q0, q6, q2
+0x1a,0xee,0x09,0x2e = vqrdmladh.s16 q1, q5, q4
+0x24,0xee,0x05,0x0e = vqrdmladh.s32 q0, q2, q2
+0x08,0xfe,0x0e,0x3e = vqdmlsdhx.s8 q1, q4, q7
+0x14,0xfe,0x0a,0x1e = vqdmlsdhx.s16 q0, q2, q5
+0x28,0xfe,0x0c,0x7e = vqdmlsdhx.s32 q3, q4, q6
+0x06,0xfe,0x0c,0x0e = vqdmlsdh.s8 q0, q3, q6
+0x18,0xfe,0x02,0x0e = vqdmlsdh.s16 q0, q4, q1
+0x2a,0xfe,0x00,0x4e = vqdmlsdh.s32 q2, q5, q0
+0x06,0xfe,0x03,0x1e = vqrdmlsdhx.s8 q0, q3, q1
+0x12,0xfe,0x09,0x1e = vqrdmlsdhx.s16 q0, q1, q4
+0x2c,0xfe,0x07,0x3e = vqrdmlsdhx.s32 q1, q6, q3
+0x06,0xfe,0x01,0x6e = vqrdmlsdh.s8 q3, q3, q0
+0x1e,0xfe,0x09,0x0e = vqrdmlsdh.s16 q0, q7, q4
+0x2c,0xfe,0x0f,0x0e = vqrdmlsdh.s32 q0, q6, q7
+0x20,0xfe,0x0f,0x0e = vqrdmlsdh.s32 q0, q0, q7
+0x2c,0xfe,0x01,0x0e = vqrdmlsdh.s32 q0, q6, q0
+0x32,0xee,0x05,0x0e = vcmul.f16 q0, q1, q2, #0x5a
+0x34,0xee,0x0a,0xce = vcmul.f16 q6, q2, q5, #0
+0x30,0xee,0x0b,0x2e = vcmul.f16 q1, q0, q5, #0x5a
+0x30,0xee,0x0a,0x3e = vcmul.f16 q1, q0, q5, #0xb4
+0x30,0xee,0x0b,0x3e = vcmul.f16 q1, q0, q5, #0x10e
+0x30,0xee,0x03,0x3e = vcmul.f16 q1, q0, q1, #0x10e
+0x3e,0xfe,0x0a,0x2e = vcmul.f32 q1, q7, q5, #0
+0x38,0xfe,0x05,0x6e = vcmul.f32 q3, q4, q2, #0x5a
+0x32,0xfe,0x06,0xbe = vcmul.f32 q5, q1, q3, #0xb4
+0x3e,0xfe,0x09,0x1e = vcmul.f32 q0, q7, q4, #0x10e
+0x0d,0xee,0x00,0x4e = vmullb.s8 q2, q6, q0
+0x19,0xee,0x06,0x6e = vmullb.s16 q3, q4, q3
+0x2b,0xee,0x0c,0x6e = vmullb.s32 q3, q5, q6
+0x0d,0xee,0x04,0x1e = vmullt.s8 q0, q6, q2
+0x11,0xee,0x04,0x1e = vmullt.s16 q0, q0, q2
+0x29,0xee,0x08,0x5e = vmullt.s32 q2, q4, q4
+0x37,0xee,0x0e,0x4e = vmullb.p8 q2, q3, q7
+0x33,0xfe,0x06,0x0e = vmullb.p16 q0, q1, q3
+0x33,0xee,0x0e,0x3e = vmullt.p8 q1, q1, q7
+0x3f,0xfe,0x0e,0x1e = vmullt.p16 q0, q7, q7
+0x09,0xee,0x0b,0x0e = vmulh.s8 q0, q4, q5
+0x1f,0xee,0x09,0x0e = vmulh.s16 q0, q7, q4
+0x2f,0xee,0x09,0x0e = vmulh.s32 q0, q7, q4
+0x0b,0xfe,0x05,0x6e = vmulh.u8 q3, q5, q2
+0x1f,0xfe,0x09,0x4e = vmulh.u16 q2, q7, q4
+0x27,0xfe,0x05,0x2e = vmulh.u32 q1, q3, q2
+0x03,0xee,0x05,0x3e = vrmulh.s8 q1, q1, q2
+0x13,0xee,0x05,0x3e = vrmulh.s16 q1, q1, q2
+0x23,0xee,0x01,0x7e = vrmulh.s32 q3, q1, q0
+0x0d,0xfe,0x01,0x3e = vrmulh.u8 q1, q6, q0
+0x17,0xfe,0x0d,0x9e = vrmulh.u16 q4, q3, q6
+0x25,0xfe,0x05,0x3e = vrmulh.u32 q1, q2, q2
+0x33,0xee,0x03,0x0e = vqmovnb.s16 q0, q1
+0x33,0xee,0x01,0x5e = vqmovnt.s16 q2, q0
+0x37,0xee,0x0b,0x0e = vqmovnb.s32 q0, q5
+0x37,0xee,0x03,0x1e = vqmovnt.s32 q0, q1
+0x33,0xfe,0x09,0x0e = vqmovnb.u16 q0, q4
+0x33,0xfe,0x0f,0x1e = vqmovnt.u16 q0, q7
+0x37,0xfe,0x09,0x0e = vqmovnb.u32 q0, q4
+0x37,0xfe,0x05,0x1e = vqmovnt.u32 q0, q2
+0x3f,0xee,0x09,0x2e = vcvtb.f16.f32 q1, q4
+0x3f,0xee,0x09,0x3e = vcvtt.f16.f32 q1, q4
+0x3f,0xfe,0x07,0x0e = vcvtb.f32.f16 q0, q3
+0x3f,0xfe,0x03,0x1e = vcvtt.f32.f16 q0, q1
+0x31,0xee,0x87,0x0e = vqmovunb.s16 q0, q3
+0x31,0xee,0x83,0x9e = vqmovunt.s16 q4, q1
+0x35,0xee,0x8f,0x2e = vqmovunb.s32 q1, q7
+0x35,0xee,0x85,0x1e = vqmovunt.s32 q0, q2
+0x31,0xfe,0x8b,0x2e = vmovnb.i16 q1, q5
+0x31,0xfe,0x81,0x1e = vmovnt.i16 q0, q0
+0x35,0xfe,0x81,0x2e = vmovnb.i32 q1, q0
+0x35,0xfe,0x87,0x7e = vmovnt.i32 q3, q3
+0x0e,0xee,0x0a,0x6f = vhcadd.s8 q3, q7, q5, #0x5a
+0x10,0xee,0x0c,0x0f = vhcadd.s16 q0, q0, q6, #0x5a
+0x10,0xee,0x0c,0x0f = vhcadd.s16 q0, q0, q6, #0x5a
+0x12,0xee,0x00,0x7f = vhcadd.s16 q3, q1, q0, #0x10e
+0x28,0xee,0x0a,0x6f = vhcadd.s32 q3, q4, q5, #0x5a
+0x2e,0xee,0x04,0xdf = vhcadd.s32 q6, q7, q2, #0x10e
+0x30,0xee,0x04,0x2f = vadc.i32 q1, q0, q2
+0x32,0xee,0x02,0x1f = vadci.i32 q0, q1, q1
+0x00,0xfe,0x04,0x2f = vcadd.i8 q1, q0, q2, #0x5a
+0x14,0xfe,0x06,0x0f = vcadd.i16 q0, q2, q3, #0x5a
+0x1a,0xfe,0x0a,0x1f = vcadd.i16 q0, q5, q5, #0x10e
+0x24,0xfe,0x0a,0x8f = vcadd.i32 q4, q2, q5, #0x5a
+0x2a,0xfe,0x00,0xbf = vcadd.i32 q5, q5, q0, #0x10e
+0x32,0xfe,0x02,0x6f = vsbc.i32 q3, q1, q1
+0x3c,0xfe,0x04,0x5f = vsbci.i32 q2, q6, q2
+0x38,0xee,0x0b,0x0f = vqdmullb.s16 q0, q4, q5
+0x3c,0xee,0x0b,0x1f = vqdmullt.s16 q0, q6, q5
+0x36,0xfe,0x0f,0x0f = vqdmullb.s32 q0, q3, q7
+0x3e,0xfe,0x0b,0x1f = vqdmullt.s32 q0, q7, q5
+0x32,0xee,0x01,0x0f = vqdmullb.s16 q0, q1, q0
+0x30,0xee,0x0b,0x1f = vqdmullt.s16 q0, q0, q5
+0x32,0xee,0x05,0x1f = vqdmullt.s16 q0, q1, q2
+0x30,0xee,0x60,0x0f = vqdmullb.s16 q0, q0, r0
+0x20,0xfe,0x02,0x1f = vcadd.i32 q0, q0, q1, #0x10e
+0x90,0xfd,0x42,0x08 = vcadd.f32 q0, q0, q1, #0x10e
+0x20,0xee,0x02,0x1f = vhcadd.s32 q0, q0, q1, #0x10e
+0x10,0xee,0x02,0x1f = vhcadd.s16 q0, q0, q1, #0x10e
+0xb0,0xff,0xc0,0x00 = vrev32.8 q0, q0
+0x71,0xfe,0x4d,0x8f = vpste
+0x32,0xfe,0x05,0x1f = vqdmulltt.s32 q0, q1, q2
+0x32,0xee,0x05,0x0f = vqdmullbe.s16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0x33,0xee,0x04,0x1e = vmulltt.p8 q0, q1, q2
+0x33,0xfe,0x04,0x0e = vmullbe.p16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0x32,0xee,0x04,0x1e = vcmult.f16 q0, q1, q2, #0xb4
+0x32,0xee,0x04,0x1e = vcmule.f16 q0, q1, q2, #0xb4
+0x71,0xfe,0x4d,0xcf = vpstet
+0x3f,0xee,0x03,0x0e = vcvtbt.f16.f32 q0, q1
+0xb7,0xff,0x42,0x01 = vcvtne.s16.f16 q0, q1
+0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1
+0x3f,0xee,0x01,0x5e = vcvttt.f16.f32 q2, q0
+0x3f,0xfe,0x01,0x3e = vcvtte.f32.f16 q1, q0
+0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1
+0x3f,0xee,0x01,0x4e = vcvtbt.f16.f32 q2, q0
+0x3f,0xfe,0x01,0x2e = vcvtbe.f32.f16 q1, q0
+0x0c,0xbf = ite eq
+0xb3,0xee,0xe0,0x0a = vcvtteq.f16.f32 s0, s1
+0xb3,0xee,0xe0,0x0a = vcvttne.f16.f32 s0, s1
diff --git a/suite/MC/ARM/mve-qdest-rsrc.s.cs b/suite/MC/ARM/mve-qdest-rsrc.s.cs
new file mode 100644
index 000000000..301f924b7
--- /dev/null
+++ b/suite/MC/ARM/mve-qdest-rsrc.s.cs
@@ -0,0 +1,143 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x07,0xee,0x43,0x1f = vsub.i8 q0, q3, r3
+0x1f,0xee,0x4e,0x1f = vsub.i16 q0, q7, lr
+0x2b,0xee,0x4a,0x3f = vsub.i32 q1, q5, r10
+0x09,0xee,0x47,0x2f = vadd.i8 q1, q4, r7
+0x1d,0xee,0x4b,0x0f = vadd.i16 q0, q6, r11
+0x23,0xee,0x46,0x0f = vadd.i32 q0, q1, r6
+0x04,0xee,0x68,0x5f = vqsub.s8 q2, q2, r8
+0x18,0xee,0x60,0x3f = vqsub.s16 q1, q4, r0
+0x24,0xee,0x60,0x1f = vqsub.s32 q0, q2, r0
+0x02,0xfe,0x62,0x1f = vqsub.u8 q0, q1, r2
+0x14,0xfe,0x66,0x1f = vqsub.u16 q0, q2, r6
+0x24,0xfe,0x62,0x1f = vqsub.u32 q0, q2, r2
+0x0c,0xee,0x61,0x0f = vqadd.s8 q0, q6, r1
+0x18,0xee,0x62,0x6f = vqadd.s16 q3, q4, r2
+0x2a,0xee,0x6b,0x0f = vqadd.s32 q0, q5, r11
+0x02,0xfe,0x68,0x0f = vqadd.u8 q0, q1, r8
+0x1a,0xfe,0x69,0x0f = vqadd.u16 q0, q5, r9
+0x20,0xfe,0x67,0x0f = vqadd.u32 q0, q0, r7
+0x32,0xee,0x66,0x0f = vqdmullb.s16 q0, q1, r6
+0x36,0xfe,0x0f,0x0f = vqdmullb.s32 q0, q3, q7
+0x32,0xee,0x60,0x1f = vqdmullt.s16 q0, q1, r0
+0x38,0xfe,0x65,0x1f = vqdmullt.s32 q0, q4, r5
+0x36,0xfe,0x47,0x1f = vsub.f16 q0, q3, r7
+0x32,0xee,0x4a,0x3f = vsub.f32 q1, q1, r10
+0x32,0xfe,0x4e,0x0f = vadd.f16 q0, q1, lr
+0x38,0xee,0x44,0x2f = vadd.f32 q1, q4, r4
+0x06,0xee,0x4e,0x1f = vhsub.s8 q0, q3, lr
+0x10,0xee,0x46,0x1f = vhsub.s16 q0, q0, r6
+0x24,0xee,0x47,0x3f = vhsub.s32 q1, q2, r7
+0x0c,0xfe,0x45,0x3f = vhsub.u8 q1, q6, r5
+0x18,0xfe,0x4a,0x1f = vhsub.u16 q0, q4, r10
+0x28,0xfe,0x4c,0x1f = vhsub.u32 q0, q4, r12
+0x04,0xee,0x41,0x0f = vhadd.s8 q0, q2, r1
+0x14,0xee,0x41,0x0f = vhadd.s16 q0, q2, r1
+0x20,0xee,0x4a,0x0f = vhadd.s32 q0, q0, r10
+0x0a,0xfe,0x4e,0x0f = vhadd.u8 q0, q5, lr
+0x14,0xfe,0x42,0x2f = vhadd.u16 q1, q2, r2
+0x24,0xfe,0x4b,0x0f = vhadd.u32 q0, q2, r11
+0x33,0xee,0xe0,0x1e = vqrshl.s8 q0, r0
+0x37,0xee,0xe3,0x1e = vqrshl.s16 q0, r3
+0x3b,0xee,0xee,0x1e = vqrshl.s32 q0, lr
+0x33,0xfe,0xe0,0x1e = vqrshl.u8 q0, r0
+0x37,0xfe,0xe2,0x1e = vqrshl.u16 q0, r2
+0x3b,0xfe,0xe3,0x1e = vqrshl.u32 q0, r3
+0x31,0xee,0xe0,0x1e = vqshl.s8 q0, r0
+0x35,0xee,0xe1,0x3e = vqshl.s16 q1, r1
+0x39,0xee,0xe3,0x1e = vqshl.s32 q0, r3
+0x31,0xfe,0xe1,0x1e = vqshl.u8 q0, r1
+0x35,0xfe,0xeb,0x1e = vqshl.u16 q0, r11
+0x39,0xfe,0xee,0x1e = vqshl.u32 q0, lr
+0x33,0xee,0x66,0x1e = vrshl.s8 q0, r6
+0x37,0xee,0x6e,0x1e = vrshl.s16 q0, lr
+0x3b,0xee,0x64,0x1e = vrshl.s32 q0, r4
+0x33,0xfe,0x60,0x1e = vrshl.u8 q0, r0
+0x37,0xfe,0x6a,0x1e = vrshl.u16 q0, r10
+0x3b,0xfe,0x61,0x1e = vrshl.u32 q0, r1
+0x31,0xee,0x6e,0x1e = vshl.s8 q0, lr
+0x35,0xee,0x6e,0x1e = vshl.s16 q0, lr
+0x39,0xee,0x61,0x1e = vshl.s32 q0, r1
+0x31,0xfe,0x6a,0x1e = vshl.u8 q0, r10
+0x35,0xfe,0x6a,0x3e = vshl.u16 q1, r10
+0x39,0xfe,0x6c,0x1e = vshl.u32 q0, r12
+0x09,0xfe,0x68,0x1e = vbrsr.8 q0, q4, r8
+0x13,0xfe,0x61,0x1e = vbrsr.16 q0, q1, r1
+0x2d,0xfe,0x60,0x1e = vbrsr.32 q0, q6, r0
+0x01,0xee,0x6c,0x1e = vmul.i8 q0, q0, r12
+0x19,0xee,0x67,0x1e = vmul.i16 q0, q4, r7
+0x23,0xee,0x6b,0x1e = vmul.i32 q0, q1, r11
+0x31,0xfe,0x6a,0x0e = vmul.f16 q0, q0, r10
+0x33,0xee,0x67,0x0e = vmul.f32 q0, q1, r7
+0x03,0xee,0x66,0x0e = vqdmulh.s8 q0, q1, r6
+0x15,0xee,0x62,0x0e = vqdmulh.s16 q0, q2, r2
+0x27,0xee,0x68,0x2e = vqdmulh.s32 q1, q3, r8
+0x05,0xfe,0x66,0x0e = vqrdmulh.s8 q0, q2, r6
+0x11,0xfe,0x62,0x0e = vqrdmulh.s16 q0, q0, r2
+0x21,0xfe,0x62,0x0e = vqrdmulh.s32 q0, q0, r2
+0x31,0xfe,0x4c,0x1e = vfmas.f16 q0, q0, r12
+0x37,0xee,0x4e,0x1e = vfmas.f32 q0, q3, lr
+0x01,0xee,0x46,0x1e = vmlas.i8 q0, q0, r6
+0x15,0xee,0x49,0x1e = vmlas.i16 q0, q2, r9
+0x2f,0xee,0x46,0x1e = vmlas.i32 q0, q7, r6
+0x01,0xee,0x46,0x1e = vmlas.i8 q0, q0, r6
+0x15,0xee,0x49,0x1e = vmlas.i16 q0, q2, r9
+0x2f,0xee,0x46,0x1e = vmlas.i32 q0, q7, r6
+0x0b,0xee,0x4e,0x1e = vmlas.i8 q0, q5, lr
+0x17,0xee,0x4c,0x1e = vmlas.i16 q0, q3, r12
+0x23,0xee,0x4b,0x3e = vmlas.i32 q1, q1, r11
+0x33,0xfe,0x46,0x2e = vfma.f16 q1, q1, r6
+0x39,0xee,0x46,0xfe = vfmas.f32 q7, q4, r6
+0x07,0xee,0x48,0x0e = vmla.i8 q0, q3, r8
+0x17,0xee,0x4a,0x2e = vmla.i16 q1, q3, r10
+0x27,0xee,0x41,0x2e = vmla.i32 q1, q3, r1
+0x07,0xee,0x48,0x0e = vmla.i8 q0, q3, r8
+0x17,0xee,0x4a,0x2e = vmla.i16 q1, q3, r10
+0x27,0xee,0x41,0x2e = vmla.i32 q1, q3, r1
+0x0f,0xee,0x4a,0x0e = vmla.i8 q0, q7, r10
+0x11,0xee,0x47,0x0e = vmla.i16 q0, q0, r7
+0x2d,0xee,0x4a,0x2e = vmla.i32 q1, q6, r10
+0x00,0xee,0x65,0x1e = vqdmlash.s8 q0, q0, r5
+0x1a,0xee,0x6e,0x1e = vqdmlash.s16 q0, q5, lr
+0x24,0xee,0x63,0x1e = vqdmlash.s32 q0, q2, r3
+0x06,0xee,0x63,0x0e = vqdmlah.s8 q0, q3, r3
+0x16,0xee,0x69,0xae = vqdmlah.s16 q5, q3, r9
+0x22,0xee,0x6b,0x0e = vqdmlah.s32 q0, q1, r11
+0x0a,0xee,0x4a,0x1e = vqrdmlash.s8 q0, q5, r10
+0x16,0xee,0x42,0x1e = vqrdmlash.s16 q0, q3, r2
+0x20,0xee,0x44,0x1e = vqrdmlash.s32 q0, q0, r4
+0x0a,0xee,0x4b,0x0e = vqrdmlah.s8 q0, q5, r11
+0x14,0xee,0x4a,0x0e = vqrdmlah.s16 q0, q2, r10
+0x28,0xee,0x4b,0x0e = vqrdmlah.s32 q0, q4, r11
+0x0f,0xee,0x60,0x0f = viwdup.u8 q0, lr, r1, #1
+0x1b,0xee,0xe1,0x2f = viwdup.u16 q1, r10, r1, #8
+0x2b,0xee,0xe4,0xcf = viwdup.u32 q6, r10, r5, #4
+0x0d,0xee,0xeb,0x1f = vdwdup.u8 q0, r12, r11, #8
+0x1d,0xee,0x61,0x1f = vdwdup.u16 q0, r12, r1, #2
+0x21,0xee,0xe7,0x1f = vdwdup.u32 q0, r0, r7, #8
+0x0f,0xee,0x6f,0x0f = vidup.u8 q0, lr, #2
+0x1f,0xee,0xee,0x0f = vidup.u16 q0, lr, #4
+0x2d,0xee,0x6e,0x0f = vidup.u32 q0, r12, #1
+0x05,0xee,0xee,0x1f = vddup.u8 q0, r4, #4
+0x1b,0xee,0xee,0x1f = vddup.u16 q0, r10, #4
+0x21,0xee,0xef,0x5f = vddup.u32 q2, r0, #8
+0x0e,0xf0,0x01,0xe8 = vctp.8 lr
+0x10,0xf0,0x01,0xe8 = vctp.16 r0
+0x2a,0xf0,0x01,0xe8 = vctp.32 r10
+0x31,0xf0,0x01,0xe8 = vctp.64 r1
+0x71,0xfe,0x4d,0x8f = vpste
+0x02,0xef,0x54,0x09 = vmult.i8 q0, q1, q2
+0x12,0xef,0x54,0x09 = vmule.i16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0x12,0xef,0x54,0x09 = vmult.i16 q0, q1, q2
+0x14,0xef,0x56,0x29 = vmule.i16 q1, q2, q3
+0x3b,0xfe,0xe0,0x1e = vqrshl.u32 q0, r0
+0x71,0xfe,0x4d,0x8f = vpste
+0x37,0xfe,0xe0,0x1e = vqrshlt.u16 q0, r0
+0x14,0xef,0x52,0x05 = vqrshle.s16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0x14,0xff,0x42,0x05 = vrshlt.u16 q0, q1, q2
+0x3b,0xee,0x60,0x1e = vrshle.s32 q0, r0
+0x71,0xfe,0x4d,0x8f = vpste
+0x31,0xee,0x60,0x1e = vshlt.s8 q0, r0
+0x39,0xfe,0x60,0x1e = vshle.u32 q0, r0
diff --git a/suite/MC/ARM/mve-reductions-fp.s.cs b/suite/MC/ARM/mve-reductions-fp.s.cs
new file mode 100644
index 000000000..c65225d30
--- /dev/null
+++ b/suite/MC/ARM/mve-reductions-fp.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0xee,0xfe,0x86,0xef = vminnmv.f16 lr, q3
+0xee,0xee,0x82,0xef = vminnmv.f32 lr, q1
+0xec,0xfe,0x80,0xef = vminnmav.f16 lr, q0
+0xec,0xee,0x86,0xef = vminnmav.f32 lr, q3
+0xee,0xfe,0x02,0xef = vmaxnmv.f16 lr, q1
+0xee,0xee,0x02,0xaf = vmaxnmv.f32 r10, q1
+0xec,0xfe,0x0c,0x0f = vmaxnmav.f16 r0, q6
+0xec,0xee,0x0e,0xef = vmaxnmav.f32 lr, q7
diff --git a/suite/MC/ARM/mve-reductions.s.cs b/suite/MC/ARM/mve-reductions.s.cs
new file mode 100644
index 000000000..b1623ce44
--- /dev/null
+++ b/suite/MC/ARM/mve-reductions.s.cs
@@ -0,0 +1,56 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x82,0xee,0x07,0x0f = vabav.s8 r0, q1, q3
+0x92,0xee,0x07,0x0f = vabav.s16 r0, q1, q3
+0xa2,0xee,0x07,0x0f = vabav.s32 r0, q1, q3
+0x82,0xfe,0x07,0x0f = vabav.u8 r0, q1, q3
+0x92,0xfe,0x07,0x0f = vabav.u16 r0, q1, q3
+0xa2,0xfe,0x07,0x0f = vabav.u32 r0, q1, q3
+0xf5,0xee,0x00,0xef = vaddv.s16 lr, q0
+0xf5,0xee,0x0c,0x0f = vaddv.s16 r0, q6
+0xf5,0xee,0x20,0xef = vaddva.s16 lr, q0
+0xc9,0xee,0x04,0x0f = vaddlv.s32 r0, r9, q2
+0x89,0xfe,0x02,0x0f = vaddlv.u32 r0, r1, q1
+0xe2,0xee,0x80,0xef = vminv.s8 lr, q0
+0xe6,0xee,0x80,0xef = vminv.s16 lr, q0
+0xea,0xee,0x84,0xef = vminv.s32 lr, q2
+0xe2,0xfe,0x80,0x0f = vminv.u8 r0, q0
+0xea,0xfe,0x86,0xaf = vminv.u32 r10, q3
+0xe4,0xee,0x80,0x0f = vminav.s16 r0, q0
+0xe0,0xee,0x82,0x0f = vminav.s8 r0, q1
+0xe8,0xee,0x82,0xef = vminav.s32 lr, q1
+0xe2,0xee,0x08,0xef = vmaxv.s8 lr, q4
+0xe6,0xee,0x00,0xef = vmaxv.s16 lr, q0
+0xea,0xee,0x02,0x1f = vmaxv.s32 r1, q1
+0xe2,0xfe,0x08,0x0f = vmaxv.u8 r0, q4
+0xe6,0xfe,0x02,0x0f = vmaxv.u16 r0, q1
+0xea,0xfe,0x00,0x1f = vmaxv.u32 r1, q0
+0xe0,0xee,0x0c,0xef = vmaxav.s8 lr, q6
+0xe4,0xee,0x0c,0x0f = vmaxav.s16 r0, q6
+0xe8,0xee,0x0e,0xaf = vmaxav.s32 r10, q7
+0xf0,0xee,0x0e,0xee = vmlav.s16 lr, q0, q7
+0xf1,0xee,0x08,0xee = vmlav.s32 lr, q0, q4
+0xf0,0xfe,0x0e,0xee = vmlav.u16 lr, q0, q7
+0xf1,0xfe,0x00,0xee = vmlav.u32 lr, q0, q0
+0xf0,0xee,0x28,0xee = vmlava.s16 lr, q0, q4
+0xf0,0xee,0x0e,0x1e = vmladavx.s16 r0, q0, q7
+0xf0,0xee,0x2e,0xfe = vmladavax.s16 lr, q0, q7
+0xf6,0xee,0x00,0xef = vmlav.s8 lr, q3, q0
+0xf2,0xfe,0x0e,0xef = vmlav.u8 lr, q1, q7
+0x8c,0xee,0x04,0xef = vrmlalvh.s32 lr, r1, q6, q2
+0x8a,0xfe,0x04,0xef = vrmlalvh.u32 lr, r1, q5, q2
+0x8a,0xfe,0x04,0xef = vrmlalvh.u32 lr, r1, q5, q2
+0x86,0xee,0x20,0xff = vrmlaldavhax.s32 lr, r1, q3, q0
+0xdc,0xfe,0x0b,0xee = vrmlsldavh.s32 lr, r11, q6, q5
+0xf0,0xee,0x07,0xee = vmlsdav.s16 lr, q0, q3
+0x8c,0xee,0x04,0xef = vrmlalvh.s32 lr, r1, q6, q2
+0x8a,0xfe,0x04,0xef = vrmlalvh.u32 lr, r1, q5, q2
+0x86,0xee,0x2c,0xef = vrmlalvha.s32 lr, r1, q3, q6
+0x8e,0xfe,0x22,0xef = vrmlalvha.u32 lr, r1, q7, q1
+0xf0,0xee,0x07,0xee = vmlsdav.s16 lr, q0, q3
+0xf5,0xee,0x0d,0xee = vmlsdav.s32 lr, q2, q6
+0xf2,0xee,0x29,0xfe = vmlsdavax.s16 lr, q1, q4
+0xf0,0xee,0x0e,0xee = vmlav.s16 lr, q0, q7
+0x88,0xee,0x02,0xee = vmlalv.s16 lr, r1, q4, q1
+0xd9,0xee,0x02,0xee = vmlalv.s32 lr, r11, q4, q1
+0x8f,0xee,0x0c,0x0e = vmlalv.s32 r0, r1, q7, q6
+0xda,0xfe,0x08,0xee = vmlalv.u16 lr, r11, q5, q4
diff --git a/suite/MC/ARM/mve-scalar-shift.s.cs b/suite/MC/ARM/mve-scalar-shift.s.cs
new file mode 100644
index 000000000..2f7acff99
--- /dev/null
+++ b/suite/MC/ARM/mve-scalar-shift.s.cs
@@ -0,0 +1,31 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x50,0xea,0xef,0x51 = asrl r0, r1, #0x17
+0x5e,0xea,0xef,0x61 = asrl lr, r1, #0x1b
+0x50,0xea,0x2d,0x41 = asrl r0, r1, r4
+0x52,0xea,0x22,0x9e = cinc lr, r2, lo
+0x57,0xea,0x47,0x9e = cinc lr, r7, pl
+0x5c,0xea,0x3c,0xae = cinv lr, r12, hs
+0x5a,0xea,0x3a,0xbe = cneg lr, r10, hs
+0x59,0xea,0x7b,0x89 = csel r9, r9, r11, vc
+0x5f,0xea,0x1f,0x9e = cset lr, eq
+0x5f,0xea,0x3f,0xae = csetm lr, hs
+0x5a,0xea,0xd7,0x9e = csinc lr, r10, r7, le
+0x55,0xea,0x2f,0xae = csinv lr, r5, zr, hs
+0x52,0xea,0x42,0xae = cinv lr, r2, pl
+0x51,0xea,0x7b,0xbe = csneg lr, r1, r11, vc
+0x5e,0xea,0xcf,0x21 = lsll lr, r1, #0xb
+0x5e,0xea,0x0d,0x41 = lsll lr, r1, r4
+0x5e,0xea,0x1f,0x31 = lsrl lr, r1, #0xc
+0x5e,0xea,0x2d,0xcf = sqrshr lr, r12
+0x5b,0xea,0x2d,0xcf = sqrshr r11, r12
+0x5f,0xea,0x2d,0x83 = sqrshrl lr, r3, #0x40, r8
+0x5e,0xea,0x7f,0x4f = sqshl lr, #0x11
+0x5f,0xea,0x3f,0x7b = sqshll lr, r11, #0x1c
+0x5e,0xea,0xef,0x2f = srshr lr, #0xb
+0x5f,0xea,0xef,0x5b = srshrl lr, r11, #0x17
+0x5e,0xea,0x0d,0x1f = uqrshl lr, r1
+0x5f,0xea,0x8d,0x41 = uqrshll lr, r1, #0x30, r4
+0x50,0xea,0x4f,0x0f = uqshl r0, #1
+0x5f,0xea,0xcf,0x17 = uqshll lr, r7, #7
+0x50,0xea,0x9f,0x2f = urshr r0, #0xa
+0x51,0xea,0x5f,0x79 = urshrl r0, r9, #0x1d
diff --git a/suite/MC/ARM/mve-shifts.s.cs b/suite/MC/ARM/mve-shifts.s.cs
new file mode 100644
index 000000000..292a95aaa
--- /dev/null
+++ b/suite/MC/ARM/mve-shifts.s.cs
@@ -0,0 +1,106 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None
+0xa8,0xee,0xce,0x0f = vshlc q0, lr, #8
+0xa8,0xee,0x4c,0x0f = vmovlb.s8 q0, q6
+0xa8,0xee,0x48,0x1f = vmovlt.s8 q0, q4
+0x41,0xfe,0x00,0x0f = vpt.i8 eq, q0, q0
+0xa8,0xee,0x48,0x1f = vmovltt.s8 q0, q4
+0xa8,0xfe,0x40,0x0f = vmovlb.u8 q0, q0
+0xa8,0xfe,0x44,0x1f = vmovlt.u8 q0, q2
+0xb0,0xfe,0x40,0x2f = vmovlb.u16 q1, q0
+0xb0,0xfe,0x44,0x1f = vmovlt.u16 q0, q2
+0x31,0xee,0x05,0x0e = vshllb.s8 q0, q2, #8
+0x31,0xee,0x0b,0x3e = vshllt.s8 q1, q5, #8
+0xaf,0xee,0x40,0x0f = vshllb.s8 q0, q0, #7
+0x31,0xfe,0x03,0x2e = vshllb.u8 q1, q1, #8
+0x31,0xfe,0x01,0x1e = vshllt.u8 q0, q0, #8
+0xab,0xfe,0x40,0x0f = vshllb.u8 q0, q0, #3
+0x35,0xfe,0x0b,0x0e = vshllb.u16 q0, q5, #0x10
+0x35,0xfe,0x07,0x1e = vshllt.u16 q0, q3, #0x10
+0x35,0xee,0x01,0x1e = vshllt.s16 q0, q0, #0x10
+0xbe,0xee,0x40,0x1f = vshllt.s16 q0, q0, #0xe
+0xbb,0xee,0x40,0x1f = vshllt.s16 q0, q0, #0xb
+0xb4,0xfe,0x44,0x0f = vshllb.u16 q0, q2, #4
+0x8f,0xfe,0xc7,0x0f = vrshrnb.i16 q0, q3, #1
+0x8b,0xfe,0xc5,0x1f = vrshrnt.i16 q0, q2, #5
+0x98,0xfe,0xc9,0x0f = vrshrnb.i32 q0, q4, #8
+0x99,0xfe,0xc5,0x1f = vrshrnt.i32 q0, q2, #7
+0x8f,0xee,0xc5,0x2f = vshrnb.i16 q1, q2, #1
+0x8f,0xee,0xc3,0x1f = vshrnt.i16 q0, q1, #1
+0x94,0xee,0xc1,0x0f = vshrnb.i32 q0, q0, #0xc
+0x9c,0xee,0xc5,0x1f = vshrnt.i32 q0, q2, #4
+0x88,0xfe,0xc4,0x0f = vqrshrunb.s16 q0, q2, #8
+0x8a,0xfe,0xc0,0x1f = vqrshrunt.s16 q0, q0, #6
+0x98,0xfe,0xc2,0x1f = vqrshrunt.s32 q0, q1, #8
+0x93,0xfe,0xce,0x0f = vqrshrunb.s32 q0, q7, #0xd
+0x8b,0xee,0xce,0x0f = vqshrunb.s16 q0, q7, #5
+0x89,0xee,0xc2,0x1f = vqshrunt.s16 q0, q1, #7
+0x9c,0xee,0xcc,0x0f = vqshrunb.s32 q0, q6, #4
+0x96,0xee,0xc4,0x1f = vqshrunt.s32 q0, q2, #0xa
+0x88,0xee,0x4f,0x0f = vqrshrnb.s16 q0, q7, #8
+0x8c,0xfe,0x47,0x3f = vqrshrnt.u16 q1, q3, #4
+0x99,0xfe,0x43,0x0f = vqrshrnb.u32 q0, q1, #7
+0x95,0xee,0x43,0x1f = vqrshrnt.s32 q0, q1, #0xb
+0x8b,0xee,0x4c,0x0f = vqshrnb.s16 q0, q6, #5
+0x8c,0xee,0x42,0x1f = vqshrnt.s16 q0, q1, #4
+0x89,0xfe,0x46,0x0f = vqshrnb.u16 q0, q3, #7
+0x88,0xfe,0x44,0x1f = vqshrnt.u16 q0, q2, #8
+0x9d,0xee,0x48,0x3f = vqshrnt.s32 q1, q4, #3
+0x92,0xfe,0x44,0x0f = vqshrnb.u32 q0, q2, #0xe
+0x0c,0xef,0x4c,0xc4 = vshl.s8 q6, q6, q6
+0x14,0xef,0x48,0x04 = vshl.s16 q0, q4, q2
+0x2a,0xef,0x42,0x24 = vshl.s32 q1, q1, q5
+0x04,0xff,0x4e,0x24 = vshl.u8 q1, q7, q2
+0x10,0xff,0x48,0x04 = vshl.u16 q0, q4, q0
+0x28,0xff,0x44,0x44 = vshl.u32 q2, q2, q4
+0x0c,0xef,0x52,0x04 = vqshl.s8 q0, q1, q6
+0x1e,0xef,0x56,0x84 = vqshl.s16 q4, q3, q7
+0x2a,0xef,0x5a,0x04 = vqshl.s32 q0, q5, q5
+0x0c,0xff,0x50,0x04 = vqshl.u8 q0, q0, q6
+0x18,0xff,0x5a,0x04 = vqshl.u16 q0, q5, q4
+0x28,0xff,0x50,0x24 = vqshl.u32 q1, q0, q4
+0x02,0xef,0x5c,0x25 = vqrshl.s8 q1, q6, q1
+0x1c,0xef,0x58,0x45 = vqrshl.s16 q2, q4, q6
+0x2a,0xef,0x50,0x05 = vqrshl.s32 q0, q0, q5
+0x02,0xff,0x54,0x05 = vqrshl.u8 q0, q2, q1
+0x10,0xff,0x5c,0x25 = vqrshl.u16 q1, q6, q0
+0x20,0xff,0x50,0x05 = vqrshl.u32 q0, q0, q0
+0x08,0xef,0x4c,0x05 = vrshl.s8 q0, q6, q4
+0x1e,0xef,0x48,0x25 = vrshl.s16 q1, q4, q7
+0x28,0xef,0x48,0x25 = vrshl.s32 q1, q4, q4
+0x0a,0xff,0x46,0x05 = vrshl.u8 q0, q3, q5
+0x1a,0xff,0x4c,0xa5 = vrshl.u16 q5, q6, q5
+0x26,0xff,0x4e,0x25 = vrshl.u32 q1, q7, q3
+0x8d,0xff,0x54,0x04 = vsri.8 q0, q2, #3
+0x9b,0xff,0x54,0x04 = vsri.16 q0, q2, #5
+0xb1,0xff,0x52,0x04 = vsri.32 q0, q1, #0xf
+0x8b,0xff,0x56,0x05 = vsli.8 q0, q3, #3
+0x9c,0xff,0x52,0x05 = vsli.16 q0, q1, #0xc
+0xa8,0xff,0x52,0x05 = vsli.32 q0, q1, #8
+0x8e,0xef,0x58,0x07 = vqshl.s8 q0, q4, #6
+0x8e,0xff,0x5c,0x07 = vqshl.u8 q0, q6, #6
+0x95,0xef,0x54,0x27 = vqshl.s16 q1, q2, #5
+0x93,0xff,0x5a,0x07 = vqshl.u16 q0, q5, #3
+0xbd,0xef,0x56,0x27 = vqshl.s32 q1, q3, #0x1d
+0xb3,0xff,0x54,0x07 = vqshl.u32 q0, q2, #0x13
+0x88,0xff,0x52,0x06 = vqshlu.s8 q0, q1, #0
+0x9c,0xff,0x52,0x46 = vqshlu.s16 q2, q1, #0xc
+0xba,0xff,0x58,0x06 = vqshlu.s32 q0, q4, #0x1a
+0x89,0xef,0x56,0x22 = vrshr.s8 q1, q3, #7
+0x8e,0xff,0x56,0x22 = vrshr.u8 q1, q3, #2
+0x96,0xef,0x52,0x02 = vrshr.s16 q0, q1, #0xa
+0x94,0xff,0x5a,0x02 = vrshr.u16 q0, q5, #0xc
+0xa9,0xef,0x5a,0x02 = vrshr.s32 q0, q5, #0x17
+0xa2,0xff,0x52,0x02 = vrshr.u32 q0, q1, #0x1e
+0x8c,0xef,0x5e,0x00 = vshr.s8 q0, q7, #4
+0x8b,0xff,0x54,0x00 = vshr.u8 q0, q2, #5
+0x90,0xef,0x56,0x00 = vshr.s16 q0, q3, #0x10
+0x98,0xff,0x5c,0xe0 = vshr.u16 q7, q6, #8
+0xa8,0xef,0x5c,0x00 = vshr.s32 q0, q6, #0x18
+0xa2,0xff,0x5a,0x40 = vshr.u32 q2, q5, #0x1e
+0x8e,0xef,0x5c,0x05 = vshl.i8 q0, q6, #6
+0x9c,0xef,0x50,0x25 = vshl.i16 q1, q0, #0xc
+0xba,0xef,0x54,0x45 = vshl.i32 q2, q2, #0x1a
+0xa9,0xee,0x42,0x1f = vshllt.s8 q0, q1, #1
+0x71,0xfe,0x4d,0x8f = vpste
+0xb4,0xee,0x42,0x1f = vshlltt.s16 q0, q1, #4
+0xb8,0xfe,0x42,0x0f = vshllbe.u16 q0, q1, #8
diff --git a/suite/MC/ARM/mve-vcmp.s.cs b/suite/MC/ARM/mve-vcmp.s.cs
new file mode 100644
index 000000000..4d9caa7b1
--- /dev/null
+++ b/suite/MC/ARM/mve-vcmp.s.cs
@@ -0,0 +1,57 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x31,0xfe,0x08,0x0f = vcmp.f16 eq, q0, q4
+0x35,0xfe,0x8e,0x0f = vcmp.f16 ne, q2, q7
+0x31,0xfe,0x00,0x1f = vcmp.f16 ge, q0, q0
+0x31,0xfe,0x82,0x1f = vcmp.f16 lt, q0, q1
+0x33,0xfe,0x09,0x1f = vcmp.f16 gt, q1, q4
+0x35,0xfe,0x8d,0x1f = vcmp.f16 le, q2, q6
+0x35,0xee,0x0a,0x0f = vcmp.f32 eq, q2, q5
+0x37,0xee,0x88,0x0f = vcmp.f32 ne, q3, q4
+0x31,0xee,0x0e,0x1f = vcmp.f32 ge, q0, q7
+0x3b,0xee,0x84,0x1f = vcmp.f32 lt, q5, q2
+0x35,0xee,0x0f,0x1f = vcmp.f32 gt, q2, q7
+0x35,0xee,0x89,0x1f = vcmp.f32 le, q2, q4
+0x09,0xfe,0x0c,0x0f = vcmp.i8 eq, q4, q6
+0x05,0xfe,0x84,0x0f = vcmp.i8 ne, q2, q2
+0x09,0xfe,0x0c,0x0f = vcmp.i8 eq, q4, q6
+0x05,0xfe,0x84,0x0f = vcmp.i8 ne, q2, q2
+0x09,0xfe,0x0c,0x0f = vcmp.i8 eq, q4, q6
+0x05,0xfe,0x84,0x0f = vcmp.i8 ne, q2, q2
+0x01,0xfe,0x00,0x1f = vcmp.s8 ge, q0, q0
+0x05,0xfe,0x8e,0x1f = vcmp.s8 lt, q2, q7
+0x09,0xfe,0x07,0x1f = vcmp.s8 gt, q4, q3
+0x0f,0xfe,0x87,0x1f = vcmp.s8 le, q7, q3
+0x03,0xfe,0x89,0x0f = vcmp.u8 hi, q1, q4
+0x03,0xfe,0x09,0x0f = vcmp.u8 cs, q1, q4
+0x19,0xfe,0x0e,0x0f = vcmp.i16 eq, q4, q7
+0x15,0xfe,0x82,0x0f = vcmp.i16 ne, q2, q1
+0x13,0xfe,0x0e,0x1f = vcmp.s16 ge, q1, q7
+0x11,0xfe,0x82,0x1f = vcmp.s16 lt, q0, q1
+0x13,0xfe,0x0f,0x1f = vcmp.s16 gt, q1, q7
+0x15,0xfe,0x83,0x1f = vcmp.s16 le, q2, q1
+0x13,0xfe,0x89,0x0f = vcmp.u16 hi, q1, q4
+0x13,0xfe,0x09,0x0f = vcmp.u16 cs, q1, q4
+0x25,0xfe,0x0e,0x0f = vcmp.i32 eq, q2, q7
+0x25,0xfe,0x88,0x0f = vcmp.i32 ne, q2, q4
+0x2b,0xfe,0x0a,0x1f = vcmp.s32 ge, q5, q5
+0x25,0xfe,0x84,0x1f = vcmp.s32 lt, q2, q2
+0x21,0xfe,0x03,0x1f = vcmp.s32 gt, q0, q1
+0x2b,0xfe,0x89,0x1f = vcmp.s32 le, q5, q4
+0x23,0xfe,0x89,0x0f = vcmp.u32 hi, q1, q4
+0x23,0xfe,0x09,0x0f = vcmp.u32 cs, q1, q4
+0x39,0xfe,0x6f,0x1f = vcmp.f16 gt, q4, zr
+0x39,0xfe,0x4c,0x0f = vcmp.f16 eq, q4, r12
+0x37,0xee,0xc0,0x0f = vcmp.f32 ne, q3, r0
+0x03,0xfe,0x40,0x0f = vcmp.i8 eq, q1, r0
+0x03,0xfe,0xe0,0x1f = vcmp.s8 le, q1, r0
+0x03,0xfe,0x60,0x0f = vcmp.u8 cs, q1, r0
+0x1b,0xfe,0x4a,0x0f = vcmp.i16 eq, q5, r10
+0x23,0xfe,0x44,0x0f = vcmp.i32 eq, q1, r4
+0x71,0xfe,0x4d,0x8f = vpste
+0x01,0xfe,0x40,0x0f = vcmpt.i8 eq, q0, r0
+0x11,0xfe,0xc0,0x0f = vcmpe.i16 ne, q0, r0
+0xb4,0xee,0x60,0x09 = vcmp.f16 s0, s1
+0xb4,0xee,0xe0,0x09 = vcmpe.f16 s0, s1
+0x04,0xbf = itt eq
+0xb4,0xee,0x60,0x0a = vcmpeq.f32 s0, s1
+0xb4,0xee,0xe0,0x0a = vcmpeeq.f32 s0, s1
diff --git a/suite/MC/ARM/mve-vmov-pair.s.cs b/suite/MC/ARM/mve-vmov-pair.s.cs
new file mode 100644
index 000000000..5486aee4c
--- /dev/null
+++ b/suite/MC/ARM/mve-vmov-pair.s.cs
@@ -0,0 +1,3 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x07,0xec,0x0e,0x8f = vmov lr, r7, q4[2], q4[0]
+0x11,0xec,0x14,0x6f = vmov q3[3], q3[1], r4, r1
diff --git a/suite/MC/ARM/mve-vpt.s.cs b/suite/MC/ARM/mve-vpt.s.cs
new file mode 100644
index 000000000..af44a45a6
--- /dev/null
+++ b/suite/MC/ARM/mve-vpt.s.cs
@@ -0,0 +1,5 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x41,0xfe,0x02,0x2f = vpteee.i8 eq, q0, q1
+0x21,0xfe,0x03,0x3f = vptttt.s32 gt, q0, q1
+0x71,0xfe,0x82,0xef = vptete.f16 ne, q0, q1
+0x1c,0xff,0x54,0x2f = vmaxnmt.f16 q1, q6, q2
diff --git a/suite/MC/ARM/negative-immediates.s.cs b/suite/MC/ARM/negative-immediates.s.cs
new file mode 100644
index 000000000..fa3abddb6
--- /dev/null
+++ b/suite/MC/ARM/negative-immediates.s.cs
@@ -0,0 +1,10 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x61,0xf1,0x01,0x10 = sbc r0, r1, #0x10001
+0x61,0xf1,0x01,0x20 = sbc r0, r1, #0x1000100
+0xa0,0xf1,0xfe,0x10 = sub.w r0, r0, #0xfe00fe
+0xa1,0xf2,0xff,0x00 = subw r0, r1, #0xff
+0xa1,0xf1,0xff,0x00 = sub.w r0, r1, #0xff
+0x21,0xf0,0x01,0x20 = bic r0, r1, #0x1000100
+0x01,0xf0,0x01,0x20 = and r0, r1, #0x1000100
+0x61,0xf0,0x01,0x20 = orn r0, r1, #0x1000100
+0x41,0xf0,0x01,0x20 = orr r0, r1, #0x1000100
diff --git a/suite/MC/ARM/neon-bitwise-encoding.s.cs b/suite/MC/ARM/neon-bitwise-encoding.s.cs
index b9b939e4e..1154b2e49 100644
--- a/suite/MC/ARM/neon-bitwise-encoding.s.cs
+++ b/suite/MC/ARM/neon-bitwise-encoding.s.cs
@@ -7,19 +7,45 @@
 0xf2,0x01,0x60,0xf2 = vorr q8, q8, q9
 0x11,0x07,0xc0,0xf2 = vorr.i32 d16, #0x1000000
 0x51,0x07,0xc0,0xf2 = vorr.i32 q8, #0x1000000
-0x50,0x01,0xc0,0xf2 = vorr.i32 q8, #0
+0x50,0x01,0xc0,0xf2 = vorr.i32 q8, #0x0
 0xb0,0x01,0x51,0xf2 = vbic d16, d17, d16
 0xf2,0x01,0x50,0xf2 = vbic q8, q8, q9
-0x3f,0x07,0xc7,0xf3 = vbic.i32 d16, #0xff000000
-0x7f,0x07,0xc7,0xf3 = vbic.i32 q8, #0xff000000
 0xf6,0x41,0x54,0xf2 = vbic q10, q10, q11
 0x11,0x91,0x19,0xf2 = vbic d9, d9, d1
+0x3f,0x0b,0xc7,0xf3 = vbic.i16 d16, #0xff00
+0x7f,0x0b,0xc7,0xf3 = vbic.i16 q8, #0xff00
+0x3f,0x09,0xc7,0xf3 = vbic.i16 d16, #0xff
+0x7f,0x09,0xc7,0xf3 = vbic.i16 q8, #0xff
+0x3f,0x07,0xc7,0xf3 = vbic.i32 d16, #0xff000000
+0x7f,0x07,0xc7,0xf3 = vbic.i32 q8, #0xff000000
+0x3f,0x05,0xc7,0xf3 = vbic.i32 d16, #0xff0000
+0x7f,0x05,0xc7,0xf3 = vbic.i32 q8, #0xff0000
+0x3f,0x03,0xc7,0xf3 = vbic.i32 d16, #0xff00
+0x7f,0x03,0xc7,0xf3 = vbic.i32 q8, #0xff00
+0x3f,0x01,0xc7,0xf3 = vbic.i32 d16, #0xff
+0x7f,0x01,0xc7,0xf3 = vbic.i32 q8, #0xff
+0x3c,0xa9,0x87,0xf3 = vbic.i16 d10, #0xfc
+0x7c,0x49,0xc7,0xf3 = vbic.i16 q10, #0xfc
+0x3c,0xab,0x87,0xf3 = vbic.i16 d10, #0xfc00
+0x7c,0x4b,0xc7,0xf3 = vbic.i16 q10, #0xfc00
+0x3c,0xa7,0x87,0xf3 = vbic.i32 d10, #0xfc000000
+0x7c,0x47,0xc7,0xf3 = vbic.i32 q10, #0xfc000000
+0x3c,0xa5,0x87,0xf3 = vbic.i32 d10, #0xfc0000
+0x7c,0x45,0xc7,0xf3 = vbic.i32 q10, #0xfc0000
+0x3c,0xa3,0x87,0xf3 = vbic.i32 d10, #0xfc00
+0x7c,0x43,0xc7,0xf3 = vbic.i32 q10, #0xfc00
+0x3c,0xa1,0x87,0xf3 = vbic.i32 d10, #0xfc
+0x7c,0x41,0xc7,0xf3 = vbic.i32 q10, #0xfc
 0xb0,0x01,0x71,0xf2 = vorn d16, d17, d16
 0xf2,0x01,0x70,0xf2 = vorn q8, q8, q9
 0xa0,0x05,0xf0,0xf3 = vmvn d16, d16
 0xe0,0x05,0xf0,0xf3 = vmvn q8, q8
 0xb0,0x21,0x51,0xf3 = vbsl d18, d17, d16
 0xf2,0x01,0x54,0xf3 = vbsl q8, q10, q9
+0xb0,0x21,0x61,0xf3 = vbit d18, d17, d16
+0xf2,0x01,0x64,0xf3 = vbit q8, q10, q9
+0xb0,0x21,0x71,0xf3 = vbif d18, d17, d16
+0xf2,0x01,0x74,0xf3 = vbif q8, q10, q9
 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
 0x56,0x81,0x0e,0xf3 = veor q4, q7, q3
diff --git a/suite/MC/ARM/neon-satshift-encoding.s.cs b/suite/MC/ARM/neon-satshift-encoding.s.cs
index 2137e0ba5..5066cd93a 100644
--- a/suite/MC/ARM/neon-satshift-encoding.s.cs
+++ b/suite/MC/ARM/neon-satshift-encoding.s.cs
@@ -16,29 +16,29 @@
 0xf0,0x04,0x62,0xf3 = vqshl.u32 q8, q8, q9
 0xf0,0x04,0x72,0xf3 = vqshl.u64 q8, q8, q9
 0x30,0x07,0xcf,0xf2 = vqshl.s8 d16, d16, #7
-0x30,0x07,0xdf,0xf2 = vqshl.s16 d16, d16, #15
-0x30,0x07,0xff,0xf2 = vqshl.s32 d16, d16, #31
-0xb0,0x07,0xff,0xf2 = vqshl.s64 d16, d16, #63
+0x30,0x07,0xdf,0xf2 = vqshl.s16 d16, d16, #0xf
+0x30,0x07,0xff,0xf2 = vqshl.s32 d16, d16, #0x1f
+0xb0,0x07,0xff,0xf2 = vqshl.s64 d16, d16, #0x3f
 0x30,0x07,0xcf,0xf3 = vqshl.u8 d16, d16, #7
-0x30,0x07,0xdf,0xf3 = vqshl.u16 d16, d16, #15
-0x30,0x07,0xff,0xf3 = vqshl.u32 d16, d16, #31
-0xb0,0x07,0xff,0xf3 = vqshl.u64 d16, d16, #63
+0x30,0x07,0xdf,0xf3 = vqshl.u16 d16, d16, #0xf
+0x30,0x07,0xff,0xf3 = vqshl.u32 d16, d16, #0x1f
+0xb0,0x07,0xff,0xf3 = vqshl.u64 d16, d16, #0x3f
 0x30,0x06,0xcf,0xf3 = vqshlu.s8 d16, d16, #7
-0x30,0x06,0xdf,0xf3 = vqshlu.s16 d16, d16, #15
-0x30,0x06,0xff,0xf3 = vqshlu.s32 d16, d16, #31
-0xb0,0x06,0xff,0xf3 = vqshlu.s64 d16, d16, #63
+0x30,0x06,0xdf,0xf3 = vqshlu.s16 d16, d16, #0xf
+0x30,0x06,0xff,0xf3 = vqshlu.s32 d16, d16, #0x1f
+0xb0,0x06,0xff,0xf3 = vqshlu.s64 d16, d16, #0x3f
 0x70,0x07,0xcf,0xf2 = vqshl.s8 q8, q8, #7
-0x70,0x07,0xdf,0xf2 = vqshl.s16 q8, q8, #15
-0x70,0x07,0xff,0xf2 = vqshl.s32 q8, q8, #31
-0xf0,0x07,0xff,0xf2 = vqshl.s64 q8, q8, #63
+0x70,0x07,0xdf,0xf2 = vqshl.s16 q8, q8, #0xf
+0x70,0x07,0xff,0xf2 = vqshl.s32 q8, q8, #0x1f
+0xf0,0x07,0xff,0xf2 = vqshl.s64 q8, q8, #0x3f
 0x70,0x07,0xcf,0xf3 = vqshl.u8 q8, q8, #7
-0x70,0x07,0xdf,0xf3 = vqshl.u16 q8, q8, #15
-0x70,0x07,0xff,0xf3 = vqshl.u32 q8, q8, #31
-0xf0,0x07,0xff,0xf3 = vqshl.u64 q8, q8, #63
+0x70,0x07,0xdf,0xf3 = vqshl.u16 q8, q8, #0xf
+0x70,0x07,0xff,0xf3 = vqshl.u32 q8, q8, #0x1f
+0xf0,0x07,0xff,0xf3 = vqshl.u64 q8, q8, #0x3f
 0x70,0x06,0xcf,0xf3 = vqshlu.s8 q8, q8, #7
-0x70,0x06,0xdf,0xf3 = vqshlu.s16 q8, q8, #15
-0x70,0x06,0xff,0xf3 = vqshlu.s32 q8, q8, #31
-0xf0,0x06,0xff,0xf3 = vqshlu.s64 q8, q8, #63
+0x70,0x06,0xdf,0xf3 = vqshlu.s16 q8, q8, #0xf
+0x70,0x06,0xff,0xf3 = vqshlu.s32 q8, q8, #0x1f
+0xf0,0x06,0xff,0xf3 = vqshlu.s64 q8, q8, #0x3f
 0xb0,0x05,0x41,0xf2 = vqrshl.s8 d16, d16, d17
 0xb0,0x05,0x51,0xf2 = vqrshl.s16 d16, d16, d17
 0xb0,0x05,0x61,0xf2 = vqrshl.s32 d16, d16, d17
@@ -56,20 +56,20 @@
 0xf0,0x05,0x62,0xf3 = vqrshl.u32 q8, q8, q9
 0xf0,0x05,0x72,0xf3 = vqrshl.u64 q8, q8, q9
 0x30,0x09,0xc8,0xf2 = vqshrn.s16 d16, q8, #8
-0x30,0x09,0xd0,0xf2 = vqshrn.s32 d16, q8, #16
-0x30,0x09,0xe0,0xf2 = vqshrn.s64 d16, q8, #32
+0x30,0x09,0xd0,0xf2 = vqshrn.s32 d16, q8, #0x10
+0x30,0x09,0xe0,0xf2 = vqshrn.s64 d16, q8, #0x20
 0x30,0x09,0xc8,0xf3 = vqshrn.u16 d16, q8, #8
-0x30,0x09,0xd0,0xf3 = vqshrn.u32 d16, q8, #16
-0x30,0x09,0xe0,0xf3 = vqshrn.u64 d16, q8, #32
+0x30,0x09,0xd0,0xf3 = vqshrn.u32 d16, q8, #0x10
+0x30,0x09,0xe0,0xf3 = vqshrn.u64 d16, q8, #0x20
 0x30,0x08,0xc8,0xf3 = vqshrun.s16 d16, q8, #8
-0x30,0x08,0xd0,0xf3 = vqshrun.s32 d16, q8, #16
-0x30,0x08,0xe0,0xf3 = vqshrun.s64 d16, q8, #32
+0x30,0x08,0xd0,0xf3 = vqshrun.s32 d16, q8, #0x10
+0x30,0x08,0xe0,0xf3 = vqshrun.s64 d16, q8, #0x20
 0x70,0x09,0xc8,0xf2 = vqrshrn.s16 d16, q8, #8
-0x70,0x09,0xd0,0xf2 = vqrshrn.s32 d16, q8, #16
-0x70,0x09,0xe0,0xf2 = vqrshrn.s64 d16, q8, #32
+0x70,0x09,0xd0,0xf2 = vqrshrn.s32 d16, q8, #0x10
+0x70,0x09,0xe0,0xf2 = vqrshrn.s64 d16, q8, #0x20
 0x70,0x09,0xc8,0xf3 = vqrshrn.u16 d16, q8, #8
-0x70,0x09,0xd0,0xf3 = vqrshrn.u32 d16, q8, #16
-0x70,0x09,0xe0,0xf3 = vqrshrn.u64 d16, q8, #32
+0x70,0x09,0xd0,0xf3 = vqrshrn.u32 d16, q8, #0x10
+0x70,0x09,0xe0,0xf3 = vqrshrn.u64 d16, q8, #0x20
 0x70,0x08,0xc8,0xf3 = vqrshrun.s16 d16, q8, #8
-0x70,0x08,0xd0,0xf3 = vqrshrun.s32 d16, q8, #16
-0x70,0x08,0xe0,0xf3 = vqrshrun.s64 d16, q8, #32
+0x70,0x08,0xd0,0xf3 = vqrshrun.s32 d16, q8, #0x10
+0x70,0x08,0xe0,0xf3 = vqrshrun.s64 d16, q8, #0x20
diff --git a/suite/MC/ARM/neon-shift-encoding.s.cs b/suite/MC/ARM/neon-shift-encoding.s.cs
index d4ca57b43..92383bd7d 100644
--- a/suite/MC/ARM/neon-shift-encoding.s.cs
+++ b/suite/MC/ARM/neon-shift-encoding.s.cs
@@ -4,125 +4,125 @@
 0xa1,0x04,0x60,0xf3 = vshl.u32 d16, d17, d16
 0xa1,0x04,0x70,0xf3 = vshl.u64 d16, d17, d16
 0x30,0x05,0xcf,0xf2 = vshl.i8 d16, d16, #7
-0x30,0x05,0xdf,0xf2 = vshl.i16 d16, d16, #15
-0x30,0x05,0xff,0xf2 = vshl.i32 d16, d16, #31
-0xb0,0x05,0xff,0xf2 = vshl.i64 d16, d16, #63
+0x30,0x05,0xdf,0xf2 = vshl.i16 d16, d16, #0xf
+0x30,0x05,0xff,0xf2 = vshl.i32 d16, d16, #0x1f
+0xb0,0x05,0xff,0xf2 = vshl.i64 d16, d16, #0x3f
 0xe2,0x04,0x40,0xf3 = vshl.u8 q8, q9, q8
 0xe2,0x04,0x50,0xf3 = vshl.u16 q8, q9, q8
 0xe2,0x04,0x60,0xf3 = vshl.u32 q8, q9, q8
 0xe2,0x04,0x70,0xf3 = vshl.u64 q8, q9, q8
 0x70,0x05,0xcf,0xf2 = vshl.i8 q8, q8, #7
-0x70,0x05,0xdf,0xf2 = vshl.i16 q8, q8, #15
-0x70,0x05,0xff,0xf2 = vshl.i32 q8, q8, #31
-0xf0,0x05,0xff,0xf2 = vshl.i64 q8, q8, #63
+0x70,0x05,0xdf,0xf2 = vshl.i16 q8, q8, #0xf
+0x70,0x05,0xff,0xf2 = vshl.i32 q8, q8, #0x1f
+0xf0,0x05,0xff,0xf2 = vshl.i64 q8, q8, #0x3f
 0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7
-0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #15
-0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #31
-0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #63
+0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #0xf
+0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #0x1f
+0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #0x3f
 0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7
-0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #15
-0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #31
-0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #63
+0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #0xf
+0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #0x1f
+0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #0x3f
 0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7
-0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #15
-0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #31
-0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #63
+0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #0xf
+0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #0x1f
+0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #0x3f
 0x70,0x00,0xc9,0xf2 = vshr.s8 q8, q8, #7
-0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #15
-0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #31
-0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #63
+0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #0xf
+0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #0x1f
+0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #0x3f
 0x30,0x00,0xc9,0xf3 = vshr.u8 d16, d16, #7
-0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #15
-0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #31
-0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #63
+0x30,0x00,0xd1,0xf3 = vshr.u16 d16, d16, #0xf
+0x30,0x00,0xe1,0xf3 = vshr.u32 d16, d16, #0x1f
+0xb0,0x00,0xc1,0xf3 = vshr.u64 d16, d16, #0x3f
 0x70,0x00,0xc9,0xf3 = vshr.u8 q8, q8, #7
-0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #15
-0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #31
-0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #63
+0x70,0x00,0xd1,0xf3 = vshr.u16 q8, q8, #0xf
+0x70,0x00,0xe1,0xf3 = vshr.u32 q8, q8, #0x1f
+0xf0,0x00,0xc1,0xf3 = vshr.u64 q8, q8, #0x3f
 0x30,0x00,0xc9,0xf2 = vshr.s8 d16, d16, #7
-0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #15
-0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #31
-0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #63
+0x30,0x00,0xd1,0xf2 = vshr.s16 d16, d16, #0xf
+0x30,0x00,0xe1,0xf2 = vshr.s32 d16, d16, #0x1f
+0xb0,0x00,0xc1,0xf2 = vshr.s64 d16, d16, #0x3f
 0x70,0x00,0xc9,0xf2 = vshr.s8 q8, q8, #7
-0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #15
-0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #31
-0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #63
+0x70,0x00,0xd1,0xf2 = vshr.s16 q8, q8, #0xf
+0x70,0x00,0xe1,0xf2 = vshr.s32 q8, q8, #0x1f
+0xf0,0x00,0xc1,0xf2 = vshr.s64 q8, q8, #0x3f
 0x16,0x01,0xc9,0xf2 = vsra.s8 d16, d6, #7
-0x32,0xa1,0xd1,0xf2 = vsra.s16 d26, d18, #15
-0x1a,0xb1,0xa1,0xf2 = vsra.s32 d11, d10, #31
-0xb3,0xc1,0x81,0xf2 = vsra.s64 d12, d19, #63
+0x32,0xa1,0xd1,0xf2 = vsra.s16 d26, d18, #0xf
+0x1a,0xb1,0xa1,0xf2 = vsra.s32 d11, d10, #0x1f
+0xb3,0xc1,0x81,0xf2 = vsra.s64 d12, d19, #0x3f
 0x70,0x21,0x89,0xf2 = vsra.s8 q1, q8, #7
-0x5e,0x41,0x91,0xf2 = vsra.s16 q2, q7, #15
-0x5c,0x61,0xa1,0xf2 = vsra.s32 q3, q6, #31
-0xda,0x81,0x81,0xf2 = vsra.s64 q4, q5, #63
+0x5e,0x41,0x91,0xf2 = vsra.s16 q2, q7, #0xf
+0x5c,0x61,0xa1,0xf2 = vsra.s32 q3, q6, #0x1f
+0xda,0x81,0x81,0xf2 = vsra.s64 q4, q5, #0x3f
 0x30,0x01,0xc9,0xf2 = vsra.s8 d16, d16, #7
-0x1f,0xf1,0x91,0xf2 = vsra.s16 d15, d15, #15
-0x1e,0xe1,0xa1,0xf2 = vsra.s32 d14, d14, #31
-0x9d,0xd1,0x81,0xf2 = vsra.s64 d13, d13, #63
+0x1f,0xf1,0x91,0xf2 = vsra.s16 d15, d15, #0xf
+0x1e,0xe1,0xa1,0xf2 = vsra.s32 d14, d14, #0x1f
+0x9d,0xd1,0x81,0xf2 = vsra.s64 d13, d13, #0x3f
 0x58,0x81,0x89,0xf2 = vsra.s8 q4, q4, #7
-0x5a,0xa1,0x91,0xf2 = vsra.s16 q5, q5, #15
-0x5c,0xc1,0xa1,0xf2 = vsra.s32 q6, q6, #31
-0xde,0xe1,0x81,0xf2 = vsra.s64 q7, q7, #63
+0x5a,0xa1,0x91,0xf2 = vsra.s16 q5, q5, #0xf
+0x5c,0xc1,0xa1,0xf2 = vsra.s32 q6, q6, #0x1f
+0xde,0xe1,0x81,0xf2 = vsra.s64 q7, q7, #0x3f
 0x16,0x01,0xc9,0xf3 = vsra.u8 d16, d6, #7
-0x32,0xa1,0xd1,0xf3 = vsra.u16 d26, d18, #15
-0x1a,0xb1,0xa1,0xf3 = vsra.u32 d11, d10, #31
-0xb3,0xc1,0x81,0xf3 = vsra.u64 d12, d19, #63
+0x32,0xa1,0xd1,0xf3 = vsra.u16 d26, d18, #0xf
+0x1a,0xb1,0xa1,0xf3 = vsra.u32 d11, d10, #0x1f
+0xb3,0xc1,0x81,0xf3 = vsra.u64 d12, d19, #0x3f
 0x70,0x21,0x89,0xf3 = vsra.u8 q1, q8, #7
-0x5e,0x41,0x91,0xf3 = vsra.u16 q2, q7, #15
-0x5c,0x61,0xa1,0xf3 = vsra.u32 q3, q6, #31
-0xda,0x81,0x81,0xf3 = vsra.u64 q4, q5, #63
+0x5e,0x41,0x91,0xf3 = vsra.u16 q2, q7, #0xf
+0x5c,0x61,0xa1,0xf3 = vsra.u32 q3, q6, #0x1f
+0xda,0x81,0x81,0xf3 = vsra.u64 q4, q5, #0x3f
 0x30,0x01,0xc9,0xf3 = vsra.u8 d16, d16, #7
-0x1f,0xf1,0x91,0xf3 = vsra.u16 d15, d15, #15
-0x1e,0xe1,0xa1,0xf3 = vsra.u32 d14, d14, #31
-0x9d,0xd1,0x81,0xf3 = vsra.u64 d13, d13, #63
+0x1f,0xf1,0x91,0xf3 = vsra.u16 d15, d15, #0xf
+0x1e,0xe1,0xa1,0xf3 = vsra.u32 d14, d14, #0x1f
+0x9d,0xd1,0x81,0xf3 = vsra.u64 d13, d13, #0x3f
 0x58,0x81,0x89,0xf3 = vsra.u8 q4, q4, #7
-0x5a,0xa1,0x91,0xf3 = vsra.u16 q5, q5, #15
-0x5c,0xc1,0xa1,0xf3 = vsra.u32 q6, q6, #31
-0xde,0xe1,0x81,0xf3 = vsra.u64 q7, q7, #63
+0x5a,0xa1,0x91,0xf3 = vsra.u16 q5, q5, #0xf
+0x5c,0xc1,0xa1,0xf3 = vsra.u32 q6, q6, #0x1f
+0xde,0xe1,0x81,0xf3 = vsra.u64 q7, q7, #0x3f
 0x16,0x04,0xc9,0xf3 = vsri.8 d16, d6, #7
-0x32,0xa4,0xd1,0xf3 = vsri.16 d26, d18, #15
-0x1a,0xb4,0xa1,0xf3 = vsri.32 d11, d10, #31
-0xb3,0xc4,0x81,0xf3 = vsri.64 d12, d19, #63
+0x32,0xa4,0xd1,0xf3 = vsri.16 d26, d18, #0xf
+0x1a,0xb4,0xa1,0xf3 = vsri.32 d11, d10, #0x1f
+0xb3,0xc4,0x81,0xf3 = vsri.64 d12, d19, #0x3f
 0x70,0x24,0x89,0xf3 = vsri.8 q1, q8, #7
-0x5e,0x44,0x91,0xf3 = vsri.16 q2, q7, #15
-0x5c,0x64,0xa1,0xf3 = vsri.32 q3, q6, #31
-0xda,0x84,0x81,0xf3 = vsri.64 q4, q5, #63
+0x5e,0x44,0x91,0xf3 = vsri.16 q2, q7, #0xf
+0x5c,0x64,0xa1,0xf3 = vsri.32 q3, q6, #0x1f
+0xda,0x84,0x81,0xf3 = vsri.64 q4, q5, #0x3f
 0x30,0x04,0xc9,0xf3 = vsri.8 d16, d16, #7
-0x1f,0xf4,0x91,0xf3 = vsri.16 d15, d15, #15
-0x1e,0xe4,0xa1,0xf3 = vsri.32 d14, d14, #31
-0x9d,0xd4,0x81,0xf3 = vsri.64 d13, d13, #63
+0x1f,0xf4,0x91,0xf3 = vsri.16 d15, d15, #0xf
+0x1e,0xe4,0xa1,0xf3 = vsri.32 d14, d14, #0x1f
+0x9d,0xd4,0x81,0xf3 = vsri.64 d13, d13, #0x3f
 0x58,0x84,0x89,0xf3 = vsri.8 q4, q4, #7
-0x5a,0xa4,0x91,0xf3 = vsri.16 q5, q5, #15
-0x5c,0xc4,0xa1,0xf3 = vsri.32 q6, q6, #31
-0xde,0xe4,0x81,0xf3 = vsri.64 q7, q7, #63
+0x5a,0xa4,0x91,0xf3 = vsri.16 q5, q5, #0xf
+0x5c,0xc4,0xa1,0xf3 = vsri.32 q6, q6, #0x1f
+0xde,0xe4,0x81,0xf3 = vsri.64 q7, q7, #0x3f
 0x16,0x05,0xcf,0xf3 = vsli.8 d16, d6, #7
-0x32,0xa5,0xdf,0xf3 = vsli.16 d26, d18, #15
-0x1a,0xb5,0xbf,0xf3 = vsli.32 d11, d10, #31
-0xb3,0xc5,0xbf,0xf3 = vsli.64 d12, d19, #63
+0x32,0xa5,0xdf,0xf3 = vsli.16 d26, d18, #0xf
+0x1a,0xb5,0xbf,0xf3 = vsli.32 d11, d10, #0x1f
+0xb3,0xc5,0xbf,0xf3 = vsli.64 d12, d19, #0x3f
 0x70,0x25,0x8f,0xf3 = vsli.8 q1, q8, #7
-0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #15
-0x5c,0x65,0xbf,0xf3 = vsli.32 q3, q6, #31
-0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #63
+0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #0xf
+0x5c,0x65,0xbf,0xf3 = vsli.32 q3, q6, #0x1f
+0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #0x3f
 0x30,0x05,0xcf,0xf3 = vsli.8 d16, d16, #7
-0x1f,0xf5,0x9f,0xf3 = vsli.16 d15, d15, #15
-0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #31
-0x9d,0xd5,0xbf,0xf3 = vsli.64 d13, d13, #63
+0x1f,0xf5,0x9f,0xf3 = vsli.16 d15, d15, #0xf
+0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #0x1f
+0x9d,0xd5,0xbf,0xf3 = vsli.64 d13, d13, #0x3f
 0x58,0x85,0x8f,0xf3 = vsli.8 q4, q4, #7
-0x5a,0xa5,0x9f,0xf3 = vsli.16 q5, q5, #15
-0x5c,0xc5,0xbf,0xf3 = vsli.32 q6, q6, #31
-0xde,0xe5,0xbf,0xf3 = vsli.64 q7, q7, #63
+0x5a,0xa5,0x9f,0xf3 = vsli.16 q5, q5, #0xf
+0x5c,0xc5,0xbf,0xf3 = vsli.32 q6, q6, #0x1f
+0xde,0xe5,0xbf,0xf3 = vsli.64 q7, q7, #0x3f
 0x30,0x0a,0xcf,0xf2 = vshll.s8 q8, d16, #7
-0x30,0x0a,0xdf,0xf2 = vshll.s16 q8, d16, #15
-0x30,0x0a,0xff,0xf2 = vshll.s32 q8, d16, #31
+0x30,0x0a,0xdf,0xf2 = vshll.s16 q8, d16, #0xf
+0x30,0x0a,0xff,0xf2 = vshll.s32 q8, d16, #0x1f
 0x30,0x0a,0xcf,0xf3 = vshll.u8 q8, d16, #7
-0x30,0x0a,0xdf,0xf3 = vshll.u16 q8, d16, #15
-0x30,0x0a,0xff,0xf3 = vshll.u32 q8, d16, #31
+0x30,0x0a,0xdf,0xf3 = vshll.u16 q8, d16, #0xf
+0x30,0x0a,0xff,0xf3 = vshll.u32 q8, d16, #0x1f
 0x20,0x03,0xf2,0xf3 = vshll.i8 q8, d16, #8
-0x20,0x03,0xf6,0xf3 = vshll.i16 q8, d16, #16
-0x20,0x03,0xfa,0xf3 = vshll.i32 q8, d16, #32
+0x20,0x03,0xf6,0xf3 = vshll.i16 q8, d16, #0x10
+0x20,0x03,0xfa,0xf3 = vshll.i32 q8, d16, #0x20
 0x30,0x08,0xc8,0xf2 = vshrn.i16 d16, q8, #8
-0x30,0x08,0xd0,0xf2 = vshrn.i32 d16, q8, #16
-0x30,0x08,0xe0,0xf2 = vshrn.i64 d16, q8, #32
+0x30,0x08,0xd0,0xf2 = vshrn.i32 d16, q8, #0x10
+0x30,0x08,0xe0,0xf2 = vshrn.i64 d16, q8, #0x20
 0xa1,0x05,0x40,0xf2 = vrshl.s8 d16, d17, d16
 0xa1,0x05,0x50,0xf2 = vrshl.s16 d16, d17, d16
 0xa1,0x05,0x60,0xf2 = vrshl.s32 d16, d17, d16
@@ -140,30 +140,30 @@
 0xe2,0x05,0x60,0xf3 = vrshl.u32 q8, q9, q8
 0xe2,0x05,0x70,0xf3 = vrshl.u64 q8, q9, q8
 0x30,0x02,0xc8,0xf2 = vrshr.s8 d16, d16, #8
-0x30,0x02,0xd0,0xf2 = vrshr.s16 d16, d16, #16
-0x30,0x02,0xe0,0xf2 = vrshr.s32 d16, d16, #32
-0xb0,0x02,0xc0,0xf2 = vrshr.s64 d16, d16, #64
+0x30,0x02,0xd0,0xf2 = vrshr.s16 d16, d16, #0x10
+0x30,0x02,0xe0,0xf2 = vrshr.s32 d16, d16, #0x20
+0xb0,0x02,0xc0,0xf2 = vrshr.s64 d16, d16, #0x40
 0x30,0x02,0xc8,0xf3 = vrshr.u8 d16, d16, #8
-0x30,0x02,0xd0,0xf3 = vrshr.u16 d16, d16, #16
-0x30,0x02,0xe0,0xf3 = vrshr.u32 d16, d16, #32
-0xb0,0x02,0xc0,0xf3 = vrshr.u64 d16, d16, #64
+0x30,0x02,0xd0,0xf3 = vrshr.u16 d16, d16, #0x10
+0x30,0x02,0xe0,0xf3 = vrshr.u32 d16, d16, #0x20
+0xb0,0x02,0xc0,0xf3 = vrshr.u64 d16, d16, #0x40
 0x70,0x02,0xc8,0xf2 = vrshr.s8 q8, q8, #8
-0x70,0x02,0xd0,0xf2 = vrshr.s16 q8, q8, #16
-0x70,0x02,0xe0,0xf2 = vrshr.s32 q8, q8, #32
-0xf0,0x02,0xc0,0xf2 = vrshr.s64 q8, q8, #64
+0x70,0x02,0xd0,0xf2 = vrshr.s16 q8, q8, #0x10
+0x70,0x02,0xe0,0xf2 = vrshr.s32 q8, q8, #0x20
+0xf0,0x02,0xc0,0xf2 = vrshr.s64 q8, q8, #0x40
 0x70,0x02,0xc8,0xf3 = vrshr.u8 q8, q8, #8
-0x70,0x02,0xd0,0xf3 = vrshr.u16 q8, q8, #16
-0x70,0x02,0xe0,0xf3 = vrshr.u32 q8, q8, #32
-0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #64
+0x70,0x02,0xd0,0xf3 = vrshr.u16 q8, q8, #0x10
+0x70,0x02,0xe0,0xf3 = vrshr.u32 q8, q8, #0x20
+0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #0x40
 0x70,0x08,0xc8,0xf2 = vrshrn.i16 d16, q8, #8
-0x70,0x08,0xd0,0xf2 = vrshrn.i32 d16, q8, #16
-0x70,0x08,0xe0,0xf2 = vrshrn.i64 d16, q8, #32
+0x70,0x08,0xd0,0xf2 = vrshrn.i32 d16, q8, #0x10
+0x70,0x08,0xe0,0xf2 = vrshrn.i64 d16, q8, #0x20
 0x70,0x09,0xcc,0xf2 = vqrshrn.s16 d16, q8, #4
-0x70,0x09,0xd3,0xf2 = vqrshrn.s32 d16, q8, #13
-0x70,0x09,0xf3,0xf2 = vqrshrn.s64 d16, q8, #13
+0x70,0x09,0xd3,0xf2 = vqrshrn.s32 d16, q8, #0xd
+0x70,0x09,0xf3,0xf2 = vqrshrn.s64 d16, q8, #0xd
 0x70,0x09,0xcc,0xf3 = vqrshrn.u16 d16, q8, #4
-0x70,0x09,0xd3,0xf3 = vqrshrn.u32 d16, q8, #13
-0x70,0x09,0xf3,0xf3 = vqrshrn.u64 d16, q8, #13
+0x70,0x09,0xd3,0xf3 = vqrshrn.u32 d16, q8, #0xd
+0x70,0x09,0xf3,0xf3 = vqrshrn.u64 d16, q8, #0xd
 0x48,0x84,0x0a,0xf2 = vshl.s8 q4, q4, q5
 0x48,0x84,0x1a,0xf2 = vshl.s16 q4, q4, q5
 0x48,0x84,0x2a,0xf2 = vshl.s32 q4, q4, q5
@@ -181,13 +181,13 @@
 0x04,0x44,0x25,0xf3 = vshl.u32 d4, d4, d5
 0x04,0x44,0x35,0xf3 = vshl.u64 d4, d4, d5
 0x58,0x85,0x8a,0xf2 = vshl.i8 q4, q4, #2
-0x58,0x85,0x9e,0xf2 = vshl.i16 q4, q4, #14
-0x58,0x85,0xbb,0xf2 = vshl.i32 q4, q4, #27
-0xd8,0x85,0xa3,0xf2 = vshl.i64 q4, q4, #35
+0x58,0x85,0x9e,0xf2 = vshl.i16 q4, q4, #0xe
+0x58,0x85,0xbb,0xf2 = vshl.i32 q4, q4, #0x1b
+0xd8,0x85,0xa3,0xf2 = vshl.i64 q4, q4, #0x23
 0x14,0x45,0x8e,0xf2 = vshl.i8 d4, d4, #6
-0x14,0x45,0x9a,0xf2 = vshl.i16 d4, d4, #10
-0x14,0x45,0xb1,0xf2 = vshl.i32 d4, d4, #17
-0x94,0x45,0xab,0xf2 = vshl.i64 d4, d4, #43
+0x14,0x45,0x9a,0xf2 = vshl.i16 d4, d4, #0xa
+0x14,0x45,0xb1,0xf2 = vshl.i32 d4, d4, #0x11
+0x94,0x45,0xab,0xf2 = vshl.i64 d4, d4, #0x2b
 0x0b,0xb5,0x04,0xf2 = vrshl.s8 d11, d11, d4
 0x0c,0xc5,0x15,0xf2 = vrshl.s16 d12, d12, d5
 0x0d,0xd5,0x26,0xf2 = vrshl.s32 d13, d13, d6
@@ -205,34 +205,34 @@
 0xce,0xe5,0x24,0xf3 = vrshl.u32 q7, q7, q10
 0xe0,0x05,0x72,0xf3 = vrshl.u64 q8, q8, q9
 0x1f,0xf0,0x88,0xf2 = vshr.s8 d15, d15, #8
-0x1c,0xc0,0x90,0xf2 = vshr.s16 d12, d12, #16
-0x1d,0xd0,0xa0,0xf2 = vshr.s32 d13, d13, #32
-0x9e,0xe0,0x80,0xf2 = vshr.s64 d14, d14, #64
+0x1c,0xc0,0x90,0xf2 = vshr.s16 d12, d12, #0x10
+0x1d,0xd0,0xa0,0xf2 = vshr.s32 d13, d13, #0x20
+0x9e,0xe0,0x80,0xf2 = vshr.s64 d14, d14, #0x40
 0x30,0x00,0xc8,0xf3 = vshr.u8 d16, d16, #8
-0x31,0x10,0xd0,0xf3 = vshr.u16 d17, d17, #16
-0x16,0x60,0xa0,0xf3 = vshr.u32 d6, d6, #32
-0x9a,0xa0,0x80,0xf3 = vshr.u64 d10, d10, #64
+0x31,0x10,0xd0,0xf3 = vshr.u16 d17, d17, #0x10
+0x16,0x60,0xa0,0xf3 = vshr.u32 d6, d6, #0x20
+0x9a,0xa0,0x80,0xf3 = vshr.u64 d10, d10, #0x40
 0x52,0x20,0x88,0xf2 = vshr.s8 q1, q1, #8
-0x54,0x40,0x90,0xf2 = vshr.s16 q2, q2, #16
-0x56,0x60,0xa0,0xf2 = vshr.s32 q3, q3, #32
-0xd8,0x80,0x80,0xf2 = vshr.s64 q4, q4, #64
+0x54,0x40,0x90,0xf2 = vshr.s16 q2, q2, #0x10
+0x56,0x60,0xa0,0xf2 = vshr.s32 q3, q3, #0x20
+0xd8,0x80,0x80,0xf2 = vshr.s64 q4, q4, #0x40
 0x5a,0xa0,0x88,0xf3 = vshr.u8 q5, q5, #8
-0x5c,0xc0,0x90,0xf3 = vshr.u16 q6, q6, #16
-0x5e,0xe0,0xa0,0xf3 = vshr.u32 q7, q7, #32
-0xf0,0x00,0xc0,0xf3 = vshr.u64 q8, q8, #64
+0x5c,0xc0,0x90,0xf3 = vshr.u16 q6, q6, #0x10
+0x5e,0xe0,0xa0,0xf3 = vshr.u32 q7, q7, #0x20
+0xf0,0x00,0xc0,0xf3 = vshr.u64 q8, q8, #0x40
 0x1f,0xf2,0x88,0xf2 = vrshr.s8 d15, d15, #8
-0x1c,0xc2,0x90,0xf2 = vrshr.s16 d12, d12, #16
-0x1d,0xd2,0xa0,0xf2 = vrshr.s32 d13, d13, #32
-0x9e,0xe2,0x80,0xf2 = vrshr.s64 d14, d14, #64
+0x1c,0xc2,0x90,0xf2 = vrshr.s16 d12, d12, #0x10
+0x1d,0xd2,0xa0,0xf2 = vrshr.s32 d13, d13, #0x20
+0x9e,0xe2,0x80,0xf2 = vrshr.s64 d14, d14, #0x40
 0x30,0x02,0xc8,0xf3 = vrshr.u8 d16, d16, #8
-0x31,0x12,0xd0,0xf3 = vrshr.u16 d17, d17, #16
-0x16,0x62,0xa0,0xf3 = vrshr.u32 d6, d6, #32
-0x9a,0xa2,0x80,0xf3 = vrshr.u64 d10, d10, #64
+0x31,0x12,0xd0,0xf3 = vrshr.u16 d17, d17, #0x10
+0x16,0x62,0xa0,0xf3 = vrshr.u32 d6, d6, #0x20
+0x9a,0xa2,0x80,0xf3 = vrshr.u64 d10, d10, #0x40
 0x52,0x22,0x88,0xf2 = vrshr.s8 q1, q1, #8
-0x54,0x42,0x90,0xf2 = vrshr.s16 q2, q2, #16
-0x56,0x62,0xa0,0xf2 = vrshr.s32 q3, q3, #32
-0xd8,0x82,0x80,0xf2 = vrshr.s64 q4, q4, #64
+0x54,0x42,0x90,0xf2 = vrshr.s16 q2, q2, #0x10
+0x56,0x62,0xa0,0xf2 = vrshr.s32 q3, q3, #0x20
+0xd8,0x82,0x80,0xf2 = vrshr.s64 q4, q4, #0x40
 0x5a,0xa2,0x88,0xf3 = vrshr.u8 q5, q5, #8
-0x5c,0xc2,0x90,0xf3 = vrshr.u16 q6, q6, #16
-0x5e,0xe2,0xa0,0xf3 = vrshr.u32 q7, q7, #32
-0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #64
+0x5c,0xc2,0x90,0xf3 = vrshr.u16 q6, q6, #0x10
+0x5e,0xe2,0xa0,0xf3 = vrshr.u32 q7, q7, #0x20
+0xf0,0x02,0xc0,0xf3 = vrshr.u64 q8, q8, #0x40
diff --git a/suite/MC/ARM/neon-shiftaccum-encoding.s.cs b/suite/MC/ARM/neon-shiftaccum-encoding.s.cs
index 7ea28dafb..e6d200705 100644
--- a/suite/MC/ARM/neon-shiftaccum-encoding.s.cs
+++ b/suite/MC/ARM/neon-shiftaccum-encoding.s.cs
@@ -1,97 +1,97 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
 0x30,0x11,0xc8,0xf2 = vsra.s8 d17, d16, #8
-0x1e,0xf1,0x90,0xf2 = vsra.s16 d15, d14, #16
-0x1c,0xd1,0xa0,0xf2 = vsra.s32 d13, d12, #32
-0x9a,0xb1,0x80,0xf2 = vsra.s64 d11, d10, #64
+0x1e,0xf1,0x90,0xf2 = vsra.s16 d15, d14, #0x10
+0x1c,0xd1,0xa0,0xf2 = vsra.s32 d13, d12, #0x20
+0x9a,0xb1,0x80,0xf2 = vsra.s64 d11, d10, #0x40
 0x54,0xe1,0x88,0xf2 = vsra.s8 q7, q2, #8
-0x5c,0x61,0x90,0xf2 = vsra.s16 q3, q6, #16
-0x5a,0x21,0xe0,0xf2 = vsra.s32 q9, q5, #32
-0xd8,0x01,0xc0,0xf2 = vsra.s64 q8, q4, #64
+0x5c,0x61,0x90,0xf2 = vsra.s16 q3, q6, #0x10
+0x5a,0x21,0xe0,0xf2 = vsra.s32 q9, q5, #0x20
+0xd8,0x01,0xc0,0xf2 = vsra.s64 q8, q4, #0x40
 0x30,0x11,0xc8,0xf3 = vsra.u8 d17, d16, #8
-0x1e,0xb1,0x95,0xf3 = vsra.u16 d11, d14, #11
-0x1f,0xc1,0xaa,0xf3 = vsra.u32 d12, d15, #22
-0xb0,0xd1,0x8a,0xf3 = vsra.u64 d13, d16, #54
+0x1e,0xb1,0x95,0xf3 = vsra.u16 d11, d14, #0xb
+0x1f,0xc1,0xaa,0xf3 = vsra.u32 d12, d15, #0x16
+0xb0,0xd1,0x8a,0xf3 = vsra.u64 d13, d16, #0x36
 0x5e,0x21,0x88,0xf3 = vsra.u8 q1, q7, #8
 0x5e,0x41,0x9a,0xf3 = vsra.u16 q2, q7, #6
-0x5c,0x61,0xab,0xf3 = vsra.u32 q3, q6, #21
-0xda,0x81,0xa7,0xf3 = vsra.u64 q4, q5, #25
+0x5c,0x61,0xab,0xf3 = vsra.u32 q3, q6, #0x15
+0xda,0x81,0xa7,0xf3 = vsra.u64 q4, q5, #0x19
 0x30,0x01,0xc8,0xf2 = vsra.s8 d16, d16, #8
-0x1e,0xe1,0x90,0xf2 = vsra.s16 d14, d14, #16
-0x1c,0xc1,0xa0,0xf2 = vsra.s32 d12, d12, #32
-0x9a,0xa1,0x80,0xf2 = vsra.s64 d10, d10, #64
+0x1e,0xe1,0x90,0xf2 = vsra.s16 d14, d14, #0x10
+0x1c,0xc1,0xa0,0xf2 = vsra.s32 d12, d12, #0x20
+0x9a,0xa1,0x80,0xf2 = vsra.s64 d10, d10, #0x40
 0x54,0x41,0x88,0xf2 = vsra.s8 q2, q2, #8
-0x5c,0xc1,0x90,0xf2 = vsra.s16 q6, q6, #16
-0x5a,0xa1,0xa0,0xf2 = vsra.s32 q5, q5, #32
-0xd8,0x81,0x80,0xf2 = vsra.s64 q4, q4, #64
+0x5c,0xc1,0x90,0xf2 = vsra.s16 q6, q6, #0x10
+0x5a,0xa1,0xa0,0xf2 = vsra.s32 q5, q5, #0x20
+0xd8,0x81,0x80,0xf2 = vsra.s64 q4, q4, #0x40
 0x30,0x01,0xc8,0xf3 = vsra.u8 d16, d16, #8
-0x1e,0xe1,0x95,0xf3 = vsra.u16 d14, d14, #11
-0x1f,0xf1,0xaa,0xf3 = vsra.u32 d15, d15, #22
-0xb0,0x01,0xca,0xf3 = vsra.u64 d16, d16, #54
+0x1e,0xe1,0x95,0xf3 = vsra.u16 d14, d14, #0xb
+0x1f,0xf1,0xaa,0xf3 = vsra.u32 d15, d15, #0x16
+0xb0,0x01,0xca,0xf3 = vsra.u64 d16, d16, #0x36
 0x5e,0xe1,0x88,0xf3 = vsra.u8 q7, q7, #8
 0x5e,0xe1,0x9a,0xf3 = vsra.u16 q7, q7, #6
-0x5c,0xc1,0xab,0xf3 = vsra.u32 q6, q6, #21
-0xda,0xa1,0xa7,0xf3 = vsra.u64 q5, q5, #25
+0x5c,0xc1,0xab,0xf3 = vsra.u32 q6, q6, #0x15
+0xda,0xa1,0xa7,0xf3 = vsra.u64 q5, q5, #0x19
 0x3a,0x53,0x88,0xf2 = vrsra.s8 d5, d26, #8
-0x39,0x63,0x90,0xf2 = vrsra.s16 d6, d25, #16
-0x38,0x73,0xa0,0xf2 = vrsra.s32 d7, d24, #32
-0xb7,0xe3,0x80,0xf2 = vrsra.s64 d14, d23, #64
+0x39,0x63,0x90,0xf2 = vrsra.s16 d6, d25, #0x10
+0x38,0x73,0xa0,0xf2 = vrsra.s32 d7, d24, #0x20
+0xb7,0xe3,0x80,0xf2 = vrsra.s64 d14, d23, #0x40
 0x36,0xf3,0x88,0xf3 = vrsra.u8 d15, d22, #8
-0x35,0x03,0xd0,0xf3 = vrsra.u16 d16, d21, #16
-0x34,0x13,0xe0,0xf3 = vrsra.u32 d17, d20, #32
-0xb3,0x23,0xc0,0xf3 = vrsra.u64 d18, d19, #64
+0x35,0x03,0xd0,0xf3 = vrsra.u16 d16, d21, #0x10
+0x34,0x13,0xe0,0xf3 = vrsra.u32 d17, d20, #0x20
+0xb3,0x23,0xc0,0xf3 = vrsra.u64 d18, d19, #0x40
 0x54,0x23,0x88,0xf2 = vrsra.s8 q1, q2, #8
-0x56,0x43,0x90,0xf2 = vrsra.s16 q2, q3, #16
-0x58,0x63,0xa0,0xf2 = vrsra.s32 q3, q4, #32
-0xda,0x83,0x80,0xf2 = vrsra.s64 q4, q5, #64
+0x56,0x43,0x90,0xf2 = vrsra.s16 q2, q3, #0x10
+0x58,0x63,0xa0,0xf2 = vrsra.s32 q3, q4, #0x20
+0xda,0x83,0x80,0xf2 = vrsra.s64 q4, q5, #0x40
 0x5c,0xa3,0x88,0xf3 = vrsra.u8 q5, q6, #8
-0x5e,0xc3,0x90,0xf3 = vrsra.u16 q6, q7, #16
-0x70,0xe3,0xa0,0xf3 = vrsra.u32 q7, q8, #32
-0xf2,0x03,0xc0,0xf3 = vrsra.u64 q8, q9, #64
+0x5e,0xc3,0x90,0xf3 = vrsra.u16 q6, q7, #0x10
+0x70,0xe3,0xa0,0xf3 = vrsra.u32 q7, q8, #0x20
+0xf2,0x03,0xc0,0xf3 = vrsra.u64 q8, q9, #0x40
 0x3a,0xa3,0xc8,0xf2 = vrsra.s8 d26, d26, #8
-0x39,0x93,0xd0,0xf2 = vrsra.s16 d25, d25, #16
-0x38,0x83,0xe0,0xf2 = vrsra.s32 d24, d24, #32
-0xb7,0x73,0xc0,0xf2 = vrsra.s64 d23, d23, #64
+0x39,0x93,0xd0,0xf2 = vrsra.s16 d25, d25, #0x10
+0x38,0x83,0xe0,0xf2 = vrsra.s32 d24, d24, #0x20
+0xb7,0x73,0xc0,0xf2 = vrsra.s64 d23, d23, #0x40
 0x36,0x63,0xc8,0xf3 = vrsra.u8 d22, d22, #8
-0x35,0x53,0xd0,0xf3 = vrsra.u16 d21, d21, #16
-0x34,0x43,0xe0,0xf3 = vrsra.u32 d20, d20, #32
-0xb3,0x33,0xc0,0xf3 = vrsra.u64 d19, d19, #64
+0x35,0x53,0xd0,0xf3 = vrsra.u16 d21, d21, #0x10
+0x34,0x43,0xe0,0xf3 = vrsra.u32 d20, d20, #0x20
+0xb3,0x33,0xc0,0xf3 = vrsra.u64 d19, d19, #0x40
 0x54,0x43,0x88,0xf2 = vrsra.s8 q2, q2, #8
-0x56,0x63,0x90,0xf2 = vrsra.s16 q3, q3, #16
-0x58,0x83,0xa0,0xf2 = vrsra.s32 q4, q4, #32
-0xda,0xa3,0x80,0xf2 = vrsra.s64 q5, q5, #64
+0x56,0x63,0x90,0xf2 = vrsra.s16 q3, q3, #0x10
+0x58,0x83,0xa0,0xf2 = vrsra.s32 q4, q4, #0x20
+0xda,0xa3,0x80,0xf2 = vrsra.s64 q5, q5, #0x40
 0x5c,0xc3,0x88,0xf3 = vrsra.u8 q6, q6, #8
-0x5e,0xe3,0x90,0xf3 = vrsra.u16 q7, q7, #16
-0x70,0x03,0xe0,0xf3 = vrsra.u32 q8, q8, #32
-0xf2,0x23,0xc0,0xf3 = vrsra.u64 q9, q9, #64
+0x5e,0xe3,0x90,0xf3 = vrsra.u16 q7, q7, #0x10
+0x70,0x03,0xe0,0xf3 = vrsra.u32 q8, q8, #0x20
+0xf2,0x23,0xc0,0xf3 = vrsra.u64 q9, q9, #0x40
 0x1c,0xb5,0x8f,0xf3 = vsli.8 d11, d12, #7
-0x1d,0xc5,0x9f,0xf3 = vsli.16 d12, d13, #15
-0x1e,0xd5,0xbf,0xf3 = vsli.32 d13, d14, #31
-0x9f,0xe5,0xbf,0xf3 = vsli.64 d14, d15, #63
+0x1d,0xc5,0x9f,0xf3 = vsli.16 d12, d13, #0xf
+0x1e,0xd5,0xbf,0xf3 = vsli.32 d13, d14, #0x1f
+0x9f,0xe5,0xbf,0xf3 = vsli.64 d14, d15, #0x3f
 0x70,0x25,0x8f,0xf3 = vsli.8 q1, q8, #7
-0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #15
-0x58,0x65,0xbf,0xf3 = vsli.32 q3, q4, #31
-0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #63
+0x5e,0x45,0x9f,0xf3 = vsli.16 q2, q7, #0xf
+0x58,0x65,0xbf,0xf3 = vsli.32 q3, q4, #0x1f
+0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #0x3f
 0x1b,0xc4,0xc8,0xf3 = vsri.8 d28, d11, #8
-0x1c,0xa4,0xd0,0xf3 = vsri.16 d26, d12, #16
-0x1d,0x84,0xe0,0xf3 = vsri.32 d24, d13, #32
-0x9e,0x54,0xc0,0xf3 = vsri.64 d21, d14, #64
+0x1c,0xa4,0xd0,0xf3 = vsri.16 d26, d12, #0x10
+0x1d,0x84,0xe0,0xf3 = vsri.32 d24, d13, #0x20
+0x9e,0x54,0xc0,0xf3 = vsri.64 d21, d14, #0x40
 0x70,0x24,0x88,0xf3 = vsri.8 q1, q8, #8
-0x54,0xa4,0x90,0xf3 = vsri.16 q5, q2, #16
-0x58,0xe4,0xa0,0xf3 = vsri.32 q7, q4, #32
-0xdc,0x24,0xc0,0xf3 = vsri.64 q9, q6, #64
+0x54,0xa4,0x90,0xf3 = vsri.16 q5, q2, #0x10
+0x58,0xe4,0xa0,0xf3 = vsri.32 q7, q4, #0x20
+0xdc,0x24,0xc0,0xf3 = vsri.64 q9, q6, #0x40
 0x1c,0xc5,0x8f,0xf3 = vsli.8 d12, d12, #7
-0x1d,0xd5,0x9f,0xf3 = vsli.16 d13, d13, #15
-0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #31
-0x9f,0xf5,0xbf,0xf3 = vsli.64 d15, d15, #63
+0x1d,0xd5,0x9f,0xf3 = vsli.16 d13, d13, #0xf
+0x1e,0xe5,0xbf,0xf3 = vsli.32 d14, d14, #0x1f
+0x9f,0xf5,0xbf,0xf3 = vsli.64 d15, d15, #0x3f
 0x70,0x05,0xcf,0xf3 = vsli.8 q8, q8, #7
-0x5e,0xe5,0x9f,0xf3 = vsli.16 q7, q7, #15
-0x58,0x85,0xbf,0xf3 = vsli.32 q4, q4, #31
-0xda,0xa5,0xbf,0xf3 = vsli.64 q5, q5, #63
+0x5e,0xe5,0x9f,0xf3 = vsli.16 q7, q7, #0xf
+0x58,0x85,0xbf,0xf3 = vsli.32 q4, q4, #0x1f
+0xda,0xa5,0xbf,0xf3 = vsli.64 q5, q5, #0x3f
 0x1b,0xb4,0x88,0xf3 = vsri.8 d11, d11, #8
-0x1c,0xc4,0x90,0xf3 = vsri.16 d12, d12, #16
-0x1d,0xd4,0xa0,0xf3 = vsri.32 d13, d13, #32
-0x9e,0xe4,0x80,0xf3 = vsri.64 d14, d14, #64
+0x1c,0xc4,0x90,0xf3 = vsri.16 d12, d12, #0x10
+0x1d,0xd4,0xa0,0xf3 = vsri.32 d13, d13, #0x20
+0x9e,0xe4,0x80,0xf3 = vsri.64 d14, d14, #0x40
 0x70,0x04,0xc8,0xf3 = vsri.8 q8, q8, #8
-0x54,0x44,0x90,0xf3 = vsri.16 q2, q2, #16
-0x58,0x84,0xa0,0xf3 = vsri.32 q4, q4, #32
-0xdc,0xc4,0x80,0xf3 = vsri.64 q6, q6, #64
+0x54,0x44,0x90,0xf3 = vsri.16 q2, q2, #0x10
+0x58,0x84,0xa0,0xf3 = vsri.32 q4, q4, #0x20
+0xdc,0xc4,0x80,0xf3 = vsri.64 q6, q6, #0x40
diff --git a/suite/MC/ARM/neon-vld-encoding.s.cs b/suite/MC/ARM/neon-vld-encoding.s.cs
index 2fbb3903f..38a938067 100644
--- a/suite/MC/ARM/neon-vld-encoding.s.cs
+++ b/suite/MC/ARM/neon-vld-encoding.s.cs
@@ -142,7 +142,7 @@
 0xcd,0x62,0xa8,0xf4 = vld3.8 {d6[6], d7[6], d8[6]}, [r8]!
 0x8d,0x96,0xa7,0xf4 = vld3.16 {d9[2], d10[2], d11[2]}, [r7]!
 0x8d,0x1a,0xa6,0xf4 = vld3.32 {d1[1], d2[1], d3[1]}, [r6]!
-// 0xad,0x46,0xe5,0xf4 = vld3.16 {d20[2], d21[2], d22[2]}, [r5]!
+0xad,0x46,0xe5,0xf4 = vld3.16 {d20[2], d22[2], d24[2]}, [r5]!
 0x4d,0x5a,0xa4,0xf4 = vld3.32 {d5[0], d7[0], d9[0]}, [r4]!
 0x0f,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1]
 0x4f,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2]
@@ -153,8 +153,8 @@
 0x0d,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1]!
 0x4d,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2]!
 0x8d,0x0e,0xe3,0xf4 = vld3.32 {d16[], d17[], d18[]}, [r3]!
-// 0x2d,0x1e,0xe7,0xf4 = vld3.8 {d17[], d18[], d19[]}, [r7]!
-// 0x6d,0x1e,0xe7,0xf4 = vld3.16 {d17[], d18[], d19[]}, [r7]!
+0x2d,0x1e,0xe7,0xf4 = vld3.8 {d17[], d19[], d21[]}, [r7]!
+0x6d,0x1e,0xe7,0xf4 = vld3.16 {d17[], d19[], d21[]}, [r7]!
 0xad,0x0e,0xe8,0xf4 = vld3.32 {d16[], d18[], d20[]}, [r8]!
 0x08,0x0e,0xe1,0xf4 = vld3.8 {d16[], d17[], d18[]}, [r1], r8
 0x47,0x0e,0xe2,0xf4 = vld3.16 {d16[], d17[], d18[]}, [r2], r7
@@ -170,7 +170,7 @@
 0x3d,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
 0x5d,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!
 0xad,0x0b,0xe3,0xf4 = vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!
-// 0x6d,0x17,0xe7,0xf4 = vld4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
+0x6d,0x17,0xe7,0xf4 = vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!
 0xcd,0x0b,0xe8,0xf4 = vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!
 0x38,0x03,0xe1,0xf4 = vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8
 0x47,0x07,0xe2,0xf4 = vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7
@@ -186,8 +186,8 @@
 0x0d,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1]!
 0x4d,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!
 0x8d,0x0f,0xe3,0xf4 = vld4.32 {d16[], d17[], d18[], d19[]}, [r3]!
-// 0x2d,0x1f,0xe7,0xf4 = vld4.8 {d17[], d18[], d19[], d20[]}, [r7]!
-// 0x6d,0x1f,0xe7,0xf4 = vld4.16 {d17[], d18[], d19[], d20[]}, [r7]!
+0x2d,0x1f,0xe7,0xf4 = vld4.8 {d17[], d19[], d21[], d23[]}, [r7]!
+0x6d,0x1f,0xe7,0xf4 = vld4.16 {d17[], d19[], d21[], d23[]}, [r7]!
 0xad,0x0f,0xe8,0xf4 = vld4.32 {d16[], d18[], d20[], d22[]}, [r8]!
 0x08,0x0f,0xe1,0xf4 = vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8
 0x47,0x0f,0xe2,0xf4 = vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7
diff --git a/suite/MC/ARM/neon-vld-vst-align.s.cs b/suite/MC/ARM/neon-vld-vst-align.s.cs
new file mode 100644
index 000000000..ad793b777
--- /dev/null
+++ b/suite/MC/ARM/neon-vld-vst-align.s.cs
@@ -0,0 +1,958 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x24,0xf9,0x0f,0x07 = vld1.8 {d0}, [r4]
+0x24,0xf9,0x1f,0x07 = vld1.8 {d0}, [r4:64]
+0x24,0xf9,0x0d,0x07 = vld1.8 {d0}, [r4]!
+0x24,0xf9,0x1d,0x07 = vld1.8 {d0}, [r4:64]!
+0x24,0xf9,0x06,0x07 = vld1.8 {d0}, [r4], r6
+0x24,0xf9,0x16,0x07 = vld1.8 {d0}, [r4:64], r6
+0x24,0xf9,0x0f,0x0a = vld1.8 {d0, d1}, [r4]
+0x24,0xf9,0x1f,0x0a = vld1.8 {d0, d1}, [r4:64]
+0x24,0xf9,0x2f,0x0a = vld1.8 {d0, d1}, [r4:128]
+0x24,0xf9,0x0d,0x0a = vld1.8 {d0, d1}, [r4]!
+0x24,0xf9,0x1d,0x0a = vld1.8 {d0, d1}, [r4:64]!
+0x24,0xf9,0x2d,0x0a = vld1.8 {d0, d1}, [r4:128]!
+0x24,0xf9,0x06,0x0a = vld1.8 {d0, d1}, [r4], r6
+0x24,0xf9,0x16,0x0a = vld1.8 {d0, d1}, [r4:64], r6
+0x24,0xf9,0x26,0x0a = vld1.8 {d0, d1}, [r4:128], r6
+0x24,0xf9,0x0f,0x06 = vld1.8 {d0, d1, d2}, [r4]
+0x24,0xf9,0x1f,0x06 = vld1.8 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0x0d,0x06 = vld1.8 {d0, d1, d2}, [r4]!
+0x24,0xf9,0x1d,0x06 = vld1.8 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0x06,0x06 = vld1.8 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0x16,0x06 = vld1.8 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0x0f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x1f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0x2f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0x3f,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x0d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x1d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0x2d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0x3d,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x06,0x02 = vld1.8 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x16,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0x26,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0x36,0x02 = vld1.8 {d0, d1, d2, d3}, [r4:256], r6
+0xa4,0xf9,0x4f,0x00 = vld1.8 {d0[2]}, [r4]
+0xa4,0xf9,0x4d,0x00 = vld1.8 {d0[2]}, [r4]!
+0xa4,0xf9,0x46,0x00 = vld1.8 {d0[2]}, [r4], r6
+0xa4,0xf9,0x0f,0x0c = vld1.8 {d0[]}, [r4]
+0xa4,0xf9,0x0d,0x0c = vld1.8 {d0[]}, [r4]!
+0xa4,0xf9,0x06,0x0c = vld1.8 {d0[]}, [r4], r6
+0xa4,0xf9,0x2f,0x0c = vld1.8 {d0[], d1[]}, [r4]
+0xa4,0xf9,0x2d,0x0c = vld1.8 {d0[], d1[]}, [r4]!
+0xa4,0xf9,0x26,0x0c = vld1.8 {d0[], d1[]}, [r4], r6
+0x24,0xf9,0x4f,0x07 = vld1.16 {d0}, [r4]
+0x24,0xf9,0x5f,0x07 = vld1.16 {d0}, [r4:64]
+0x24,0xf9,0x4d,0x07 = vld1.16 {d0}, [r4]!
+0x24,0xf9,0x5d,0x07 = vld1.16 {d0}, [r4:64]!
+0x24,0xf9,0x46,0x07 = vld1.16 {d0}, [r4], r6
+0x24,0xf9,0x56,0x07 = vld1.16 {d0}, [r4:64], r6
+0x24,0xf9,0x4f,0x0a = vld1.16 {d0, d1}, [r4]
+0x24,0xf9,0x5f,0x0a = vld1.16 {d0, d1}, [r4:64]
+0x24,0xf9,0x6f,0x0a = vld1.16 {d0, d1}, [r4:128]
+0x24,0xf9,0x4d,0x0a = vld1.16 {d0, d1}, [r4]!
+0x24,0xf9,0x5d,0x0a = vld1.16 {d0, d1}, [r4:64]!
+0x24,0xf9,0x6d,0x0a = vld1.16 {d0, d1}, [r4:128]!
+0x24,0xf9,0x46,0x0a = vld1.16 {d0, d1}, [r4], r6
+0x24,0xf9,0x56,0x0a = vld1.16 {d0, d1}, [r4:64], r6
+0x24,0xf9,0x66,0x0a = vld1.16 {d0, d1}, [r4:128], r6
+0x24,0xf9,0x4f,0x06 = vld1.16 {d0, d1, d2}, [r4]
+0x24,0xf9,0x5f,0x06 = vld1.16 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0x4d,0x06 = vld1.16 {d0, d1, d2}, [r4]!
+0x24,0xf9,0x5d,0x06 = vld1.16 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0x46,0x06 = vld1.16 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0x56,0x06 = vld1.16 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0x4f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x5f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0x6f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0x7f,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x4d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x5d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0x6d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0x7d,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x46,0x02 = vld1.16 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x56,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0x66,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0x76,0x02 = vld1.16 {d0, d1, d2, d3}, [r4:256], r6
+0xa4,0xf9,0x8f,0x04 = vld1.16 {d0[2]}, [r4]
+0xa4,0xf9,0x9f,0x04 = vld1.16 {d0[2]}, [r4:16]
+0xa4,0xf9,0x8d,0x04 = vld1.16 {d0[2]}, [r4]!
+0xa4,0xf9,0x9d,0x04 = vld1.16 {d0[2]}, [r4:16]!
+0xa4,0xf9,0x86,0x04 = vld1.16 {d0[2]}, [r4], r6
+0xa4,0xf9,0x96,0x04 = vld1.16 {d0[2]}, [r4:16], r6
+0xa4,0xf9,0x4f,0x0c = vld1.16 {d0[]}, [r4]
+0xa4,0xf9,0x5f,0x0c = vld1.16 {d0[]}, [r4:16]
+0xa4,0xf9,0x4d,0x0c = vld1.16 {d0[]}, [r4]!
+0xa4,0xf9,0x5d,0x0c = vld1.16 {d0[]}, [r4:16]!
+0xa4,0xf9,0x46,0x0c = vld1.16 {d0[]}, [r4], r6
+0xa4,0xf9,0x56,0x0c = vld1.16 {d0[]}, [r4:16], r6
+0xa4,0xf9,0x6f,0x0c = vld1.16 {d0[], d1[]}, [r4]
+0xa4,0xf9,0x7f,0x0c = vld1.16 {d0[], d1[]}, [r4:16]
+0xa4,0xf9,0x6d,0x0c = vld1.16 {d0[], d1[]}, [r4]!
+0xa4,0xf9,0x7d,0x0c = vld1.16 {d0[], d1[]}, [r4:16]!
+0xa4,0xf9,0x66,0x0c = vld1.16 {d0[], d1[]}, [r4], r6
+0xa4,0xf9,0x76,0x0c = vld1.16 {d0[], d1[]}, [r4:16], r6
+0x24,0xf9,0x8f,0x07 = vld1.32 {d0}, [r4]
+0x24,0xf9,0x9f,0x07 = vld1.32 {d0}, [r4:64]
+0x24,0xf9,0x8d,0x07 = vld1.32 {d0}, [r4]!
+0x24,0xf9,0x9d,0x07 = vld1.32 {d0}, [r4:64]!
+0x24,0xf9,0x86,0x07 = vld1.32 {d0}, [r4], r6
+0x24,0xf9,0x96,0x07 = vld1.32 {d0}, [r4:64], r6
+0x24,0xf9,0x8f,0x0a = vld1.32 {d0, d1}, [r4]
+0x24,0xf9,0x9f,0x0a = vld1.32 {d0, d1}, [r4:64]
+0x24,0xf9,0xaf,0x0a = vld1.32 {d0, d1}, [r4:128]
+0x24,0xf9,0x8d,0x0a = vld1.32 {d0, d1}, [r4]!
+0x24,0xf9,0x9d,0x0a = vld1.32 {d0, d1}, [r4:64]!
+0x24,0xf9,0xad,0x0a = vld1.32 {d0, d1}, [r4:128]!
+0x24,0xf9,0x86,0x0a = vld1.32 {d0, d1}, [r4], r6
+0x24,0xf9,0x96,0x0a = vld1.32 {d0, d1}, [r4:64], r6
+0x24,0xf9,0xa6,0x0a = vld1.32 {d0, d1}, [r4:128], r6
+0x24,0xf9,0x8f,0x06 = vld1.32 {d0, d1, d2}, [r4]
+0x24,0xf9,0x9f,0x06 = vld1.32 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0x8d,0x06 = vld1.32 {d0, d1, d2}, [r4]!
+0x24,0xf9,0x9d,0x06 = vld1.32 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0x86,0x06 = vld1.32 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0x96,0x06 = vld1.32 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0x8f,0x02 = vld1.32 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x9f,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0xaf,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0xbf,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x8d,0x02 = vld1.32 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x9d,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0xad,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0xbd,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x86,0x02 = vld1.32 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x96,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0xa6,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0xb6,0x02 = vld1.32 {d0, d1, d2, d3}, [r4:256], r6
+0xa4,0xf9,0x8f,0x08 = vld1.32 {d0[1]}, [r4]
+0xa4,0xf9,0xbf,0x08 = vld1.32 {d0[1]}, [r4:32]
+0xa4,0xf9,0x8d,0x08 = vld1.32 {d0[1]}, [r4]!
+0xa4,0xf9,0xbd,0x08 = vld1.32 {d0[1]}, [r4:32]!
+0xa4,0xf9,0x86,0x08 = vld1.32 {d0[1]}, [r4], r6
+0xa4,0xf9,0xb6,0x08 = vld1.32 {d0[1]}, [r4:32], r6
+0xa4,0xf9,0x8f,0x0c = vld1.32 {d0[]}, [r4]
+0xa4,0xf9,0x9f,0x0c = vld1.32 {d0[]}, [r4:32]
+0xa4,0xf9,0x8d,0x0c = vld1.32 {d0[]}, [r4]!
+0xa4,0xf9,0x9d,0x0c = vld1.32 {d0[]}, [r4:32]!
+0xa4,0xf9,0x86,0x0c = vld1.32 {d0[]}, [r4], r6
+0xa4,0xf9,0x96,0x0c = vld1.32 {d0[]}, [r4:32], r6
+0xa4,0xf9,0xaf,0x0c = vld1.32 {d0[], d1[]}, [r4]
+0xa4,0xf9,0xbf,0x0c = vld1.32 {d0[], d1[]}, [r4:32]
+0xa4,0xf9,0xad,0x0c = vld1.32 {d0[], d1[]}, [r4]!
+0xa4,0xf9,0xbd,0x0c = vld1.32 {d0[], d1[]}, [r4:32]!
+0xa4,0xf9,0xa6,0x0c = vld1.32 {d0[], d1[]}, [r4], r6
+0xa4,0xf9,0xb6,0x0c = vld1.32 {d0[], d1[]}, [r4:32], r6
+0xa4,0xf9,0x8f,0x08 = vld1.32 {d0[1]}, [r4]
+0xa4,0xf9,0xbf,0x08 = vld1.32 {d0[1]}, [r4:32]
+0xa4,0xf9,0x8d,0x08 = vld1.32 {d0[1]}, [r4]!
+0xa4,0xf9,0xbd,0x08 = vld1.32 {d0[1]}, [r4:32]!
+0xa4,0xf9,0x86,0x08 = vld1.32 {d0[1]}, [r4], r6
+0xa4,0xf9,0xb6,0x08 = vld1.32 {d0[1]}, [r4:32], r6
+0x24,0xf9,0xcf,0x07 = vld1.64 {d0}, [r4]
+0x24,0xf9,0xdf,0x07 = vld1.64 {d0}, [r4:64]
+0x24,0xf9,0xcd,0x07 = vld1.64 {d0}, [r4]!
+0x24,0xf9,0xdd,0x07 = vld1.64 {d0}, [r4:64]!
+0x24,0xf9,0xc6,0x07 = vld1.64 {d0}, [r4], r6
+0x24,0xf9,0xd6,0x07 = vld1.64 {d0}, [r4:64], r6
+0x24,0xf9,0xcf,0x0a = vld1.64 {d0, d1}, [r4]
+0x24,0xf9,0xdf,0x0a = vld1.64 {d0, d1}, [r4:64]
+0x24,0xf9,0xef,0x0a = vld1.64 {d0, d1}, [r4:128]
+0x24,0xf9,0xcd,0x0a = vld1.64 {d0, d1}, [r4]!
+0x24,0xf9,0xdd,0x0a = vld1.64 {d0, d1}, [r4:64]!
+0x24,0xf9,0xed,0x0a = vld1.64 {d0, d1}, [r4:128]!
+0x24,0xf9,0xc6,0x0a = vld1.64 {d0, d1}, [r4], r6
+0x24,0xf9,0xd6,0x0a = vld1.64 {d0, d1}, [r4:64], r6
+0x24,0xf9,0xe6,0x0a = vld1.64 {d0, d1}, [r4:128], r6
+0x24,0xf9,0xcf,0x06 = vld1.64 {d0, d1, d2}, [r4]
+0x24,0xf9,0xdf,0x06 = vld1.64 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0xcd,0x06 = vld1.64 {d0, d1, d2}, [r4]!
+0x24,0xf9,0xdd,0x06 = vld1.64 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0xc6,0x06 = vld1.64 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0xd6,0x06 = vld1.64 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0xcf,0x02 = vld1.64 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0xdf,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0xef,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0xff,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0xcd,0x02 = vld1.64 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0xdd,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0xed,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0xfd,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0xc6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0xd6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0xe6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0xf6,0x02 = vld1.64 {d0, d1, d2, d3}, [r4:256], r6
+0x24,0xf9,0x0f,0x08 = vld2.8 {d0, d1}, [r4]
+0x24,0xf9,0x1f,0x08 = vld2.8 {d0, d1}, [r4:64]
+0x24,0xf9,0x2f,0x08 = vld2.8 {d0, d1}, [r4:128]
+0x24,0xf9,0x0d,0x08 = vld2.8 {d0, d1}, [r4]!
+0x24,0xf9,0x1d,0x08 = vld2.8 {d0, d1}, [r4:64]!
+0x24,0xf9,0x2d,0x08 = vld2.8 {d0, d1}, [r4:128]!
+0x24,0xf9,0x06,0x08 = vld2.8 {d0, d1}, [r4], r6
+0x24,0xf9,0x16,0x08 = vld2.8 {d0, d1}, [r4:64], r6
+0x24,0xf9,0x26,0x08 = vld2.8 {d0, d1}, [r4:128], r6
+0x24,0xf9,0x0f,0x09 = vld2.8 {d0, d2}, [r4]
+0x24,0xf9,0x1f,0x09 = vld2.8 {d0, d2}, [r4:64]
+0x24,0xf9,0x2f,0x09 = vld2.8 {d0, d2}, [r4:128]
+0x24,0xf9,0x0d,0x09 = vld2.8 {d0, d2}, [r4]!
+0x24,0xf9,0x1d,0x09 = vld2.8 {d0, d2}, [r4:64]!
+0x24,0xf9,0x2d,0x09 = vld2.8 {d0, d2}, [r4:128]!
+0x24,0xf9,0x06,0x09 = vld2.8 {d0, d2}, [r4], r6
+0x24,0xf9,0x16,0x09 = vld2.8 {d0, d2}, [r4:64], r6
+0x24,0xf9,0x26,0x09 = vld2.8 {d0, d2}, [r4:128], r6
+0x24,0xf9,0x0f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x1f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0x2f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0x3f,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x0d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x1d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0x2d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0x3d,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x06,0x03 = vld2.8 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x16,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0x26,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0x36,0x03 = vld2.8 {d0, d1, d2, d3}, [r4:256], r6
+0xa4,0xf9,0x4f,0x01 = vld2.8 {d0[2], d1[2]}, [r4]
+0xa4,0xf9,0x5f,0x01 = vld2.8 {d0[2], d1[2]}, [r4:16]
+0xa4,0xf9,0x4d,0x01 = vld2.8 {d0[2], d1[2]}, [r4]!
+0xa4,0xf9,0x5d,0x01 = vld2.8 {d0[2], d1[2]}, [r4:16]!
+0xa4,0xf9,0x46,0x01 = vld2.8 {d0[2], d1[2]}, [r4], r6
+0xa4,0xf9,0x56,0x01 = vld2.8 {d0[2], d1[2]}, [r4:16], r6
+0xa4,0xf9,0x0f,0x0d = vld2.8 {d0[], d1[]}, [r4]
+0xa4,0xf9,0x1f,0x0d = vld2.8 {d0[], d1[]}, [r4:16]
+0xa4,0xf9,0x0d,0x0d = vld2.8 {d0[], d1[]}, [r4]!
+0xa4,0xf9,0x1d,0x0d = vld2.8 {d0[], d1[]}, [r4:16]!
+0xa4,0xf9,0x06,0x0d = vld2.8 {d0[], d1[]}, [r4], r6
+0xa4,0xf9,0x16,0x0d = vld2.8 {d0[], d1[]}, [r4:16], r6
+0xa4,0xf9,0x2f,0x0d = vld2.8 {d0[], d2[]}, [r4]
+0xa4,0xf9,0x3f,0x0d = vld2.8 {d0[], d2[]}, [r4:16]
+0xa4,0xf9,0x2d,0x0d = vld2.8 {d0[], d2[]}, [r4]!
+0xa4,0xf9,0x3d,0x0d = vld2.8 {d0[], d2[]}, [r4:16]!
+0xa4,0xf9,0x26,0x0d = vld2.8 {d0[], d2[]}, [r4], r6
+0xa4,0xf9,0x36,0x0d = vld2.8 {d0[], d2[]}, [r4:16], r6
+0x24,0xf9,0x4f,0x08 = vld2.16 {d0, d1}, [r4]
+0x24,0xf9,0x5f,0x08 = vld2.16 {d0, d1}, [r4:64]
+0x24,0xf9,0x6f,0x08 = vld2.16 {d0, d1}, [r4:128]
+0x24,0xf9,0x4d,0x08 = vld2.16 {d0, d1}, [r4]!
+0x24,0xf9,0x5d,0x08 = vld2.16 {d0, d1}, [r4:64]!
+0x24,0xf9,0x6d,0x08 = vld2.16 {d0, d1}, [r4:128]!
+0x24,0xf9,0x46,0x08 = vld2.16 {d0, d1}, [r4], r6
+0x24,0xf9,0x56,0x08 = vld2.16 {d0, d1}, [r4:64], r6
+0x24,0xf9,0x66,0x08 = vld2.16 {d0, d1}, [r4:128], r6
+0x24,0xf9,0x4f,0x09 = vld2.16 {d0, d2}, [r4]
+0x24,0xf9,0x5f,0x09 = vld2.16 {d0, d2}, [r4:64]
+0x24,0xf9,0x6f,0x09 = vld2.16 {d0, d2}, [r4:128]
+0x24,0xf9,0x4d,0x09 = vld2.16 {d0, d2}, [r4]!
+0x24,0xf9,0x5d,0x09 = vld2.16 {d0, d2}, [r4:64]!
+0x24,0xf9,0x6d,0x09 = vld2.16 {d0, d2}, [r4:128]!
+0x24,0xf9,0x46,0x09 = vld2.16 {d0, d2}, [r4], r6
+0x24,0xf9,0x56,0x09 = vld2.16 {d0, d2}, [r4:64], r6
+0x24,0xf9,0x66,0x09 = vld2.16 {d0, d2}, [r4:128], r6
+0x24,0xf9,0x4f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x5f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0x6f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0x7f,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x4d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x5d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0x6d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0x7d,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x46,0x03 = vld2.16 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x56,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0x66,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0x76,0x03 = vld2.16 {d0, d1, d2, d3}, [r4:256], r6
+0xa4,0xf9,0x8f,0x05 = vld2.16 {d0[2], d1[2]}, [r4]
+0xa4,0xf9,0x9f,0x05 = vld2.16 {d0[2], d1[2]}, [r4:32]
+0xa4,0xf9,0x8d,0x05 = vld2.16 {d0[2], d1[2]}, [r4]!
+0xa4,0xf9,0x9d,0x05 = vld2.16 {d0[2], d1[2]}, [r4:32]!
+0xa4,0xf9,0x86,0x05 = vld2.16 {d0[2], d1[2]}, [r4], r6
+0xa4,0xf9,0x96,0x05 = vld2.16 {d0[2], d1[2]}, [r4:32], r6
+0xa4,0xf9,0xaf,0x05 = vld2.16 {d0[2], d2[2]}, [r4]
+0xa4,0xf9,0xbf,0x05 = vld2.16 {d0[2], d2[2]}, [r4:32]
+0xa4,0xf9,0xad,0x05 = vld2.16 {d0[2], d2[2]}, [r4]!
+0xa4,0xf9,0xbd,0x05 = vld2.16 {d0[2], d2[2]}, [r4:32]!
+0xa4,0xf9,0xa6,0x05 = vld2.16 {d0[2], d2[2]}, [r4], r6
+0xa4,0xf9,0xb6,0x05 = vld2.16 {d0[2], d2[2]}, [r4:32], r6
+0xa4,0xf9,0x4f,0x0d = vld2.16 {d0[], d1[]}, [r4]
+0xa4,0xf9,0x5f,0x0d = vld2.16 {d0[], d1[]}, [r4:32]
+0xa4,0xf9,0x4d,0x0d = vld2.16 {d0[], d1[]}, [r4]!
+0xa4,0xf9,0x5d,0x0d = vld2.16 {d0[], d1[]}, [r4:32]!
+0xa4,0xf9,0x46,0x0d = vld2.16 {d0[], d1[]}, [r4], r6
+0xa4,0xf9,0x56,0x0d = vld2.16 {d0[], d1[]}, [r4:32], r6
+0xa4,0xf9,0x6f,0x0d = vld2.16 {d0[], d2[]}, [r4]
+0xa4,0xf9,0x7f,0x0d = vld2.16 {d0[], d2[]}, [r4:32]
+0xa4,0xf9,0x6d,0x0d = vld2.16 {d0[], d2[]}, [r4]!
+0xa4,0xf9,0x7d,0x0d = vld2.16 {d0[], d2[]}, [r4:32]!
+0xa4,0xf9,0x66,0x0d = vld2.16 {d0[], d2[]}, [r4], r6
+0xa4,0xf9,0x76,0x0d = vld2.16 {d0[], d2[]}, [r4:32], r6
+0x24,0xf9,0x8f,0x08 = vld2.32 {d0, d1}, [r4]
+0x24,0xf9,0x9f,0x08 = vld2.32 {d0, d1}, [r4:64]
+0x24,0xf9,0xaf,0x08 = vld2.32 {d0, d1}, [r4:128]
+0x24,0xf9,0x8d,0x08 = vld2.32 {d0, d1}, [r4]!
+0x24,0xf9,0x9d,0x08 = vld2.32 {d0, d1}, [r4:64]!
+0x24,0xf9,0xad,0x08 = vld2.32 {d0, d1}, [r4:128]!
+0x24,0xf9,0x86,0x08 = vld2.32 {d0, d1}, [r4], r6
+0x24,0xf9,0x96,0x08 = vld2.32 {d0, d1}, [r4:64], r6
+0x24,0xf9,0xa6,0x08 = vld2.32 {d0, d1}, [r4:128], r6
+0x24,0xf9,0x8f,0x09 = vld2.32 {d0, d2}, [r4]
+0x24,0xf9,0x9f,0x09 = vld2.32 {d0, d2}, [r4:64]
+0x24,0xf9,0xaf,0x09 = vld2.32 {d0, d2}, [r4:128]
+0x24,0xf9,0x8d,0x09 = vld2.32 {d0, d2}, [r4]!
+0x24,0xf9,0x9d,0x09 = vld2.32 {d0, d2}, [r4:64]!
+0x24,0xf9,0xad,0x09 = vld2.32 {d0, d2}, [r4:128]!
+0x24,0xf9,0x86,0x09 = vld2.32 {d0, d2}, [r4], r6
+0x24,0xf9,0x96,0x09 = vld2.32 {d0, d2}, [r4:64], r6
+0x24,0xf9,0xa6,0x09 = vld2.32 {d0, d2}, [r4:128], r6
+0x24,0xf9,0x8f,0x03 = vld2.32 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x9f,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0xaf,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0xbf,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x8d,0x03 = vld2.32 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x9d,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0xad,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0xbd,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x86,0x03 = vld2.32 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x96,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0xa6,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0xb6,0x03 = vld2.32 {d0, d1, d2, d3}, [r4:256], r6
+0xa4,0xf9,0x8f,0x09 = vld2.32 {d0[1], d1[1]}, [r4]
+0xa4,0xf9,0x9f,0x09 = vld2.32 {d0[1], d1[1]}, [r4:64]
+0xa4,0xf9,0x8d,0x09 = vld2.32 {d0[1], d1[1]}, [r4]!
+0xa4,0xf9,0x9d,0x09 = vld2.32 {d0[1], d1[1]}, [r4:64]!
+0xa4,0xf9,0x86,0x09 = vld2.32 {d0[1], d1[1]}, [r4], r6
+0xa4,0xf9,0x96,0x09 = vld2.32 {d0[1], d1[1]}, [r4:64], r6
+0xa4,0xf9,0xcf,0x09 = vld2.32 {d0[1], d2[1]}, [r4]
+0xa4,0xf9,0xdf,0x09 = vld2.32 {d0[1], d2[1]}, [r4:64]
+0xa4,0xf9,0xcd,0x09 = vld2.32 {d0[1], d2[1]}, [r4]!
+0xa4,0xf9,0xdd,0x09 = vld2.32 {d0[1], d2[1]}, [r4:64]!
+0xa4,0xf9,0xc6,0x09 = vld2.32 {d0[1], d2[1]}, [r4], r6
+0xa4,0xf9,0xd6,0x09 = vld2.32 {d0[1], d2[1]}, [r4:64], r6
+0xa4,0xf9,0x8f,0x0d = vld2.32 {d0[], d1[]}, [r4]
+0xa4,0xf9,0x9f,0x0d = vld2.32 {d0[], d1[]}, [r4:64]
+0xa4,0xf9,0x8d,0x0d = vld2.32 {d0[], d1[]}, [r4]!
+0xa4,0xf9,0x9d,0x0d = vld2.32 {d0[], d1[]}, [r4:64]!
+0xa4,0xf9,0x86,0x0d = vld2.32 {d0[], d1[]}, [r4], r6
+0xa4,0xf9,0x96,0x0d = vld2.32 {d0[], d1[]}, [r4:64], r6
+0xa4,0xf9,0xaf,0x0d = vld2.32 {d0[], d2[]}, [r4]
+0xa4,0xf9,0xbf,0x0d = vld2.32 {d0[], d2[]}, [r4:64]
+0xa4,0xf9,0xad,0x0d = vld2.32 {d0[], d2[]}, [r4]!
+0xa4,0xf9,0xbd,0x0d = vld2.32 {d0[], d2[]}, [r4:64]!
+0xa4,0xf9,0xa6,0x0d = vld2.32 {d0[], d2[]}, [r4], r6
+0xa4,0xf9,0xb6,0x0d = vld2.32 {d0[], d2[]}, [r4:64], r6
+0x24,0xf9,0x0f,0x04 = vld3.8 {d0, d1, d2}, [r4]
+0x24,0xf9,0x1f,0x04 = vld3.8 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0x0d,0x04 = vld3.8 {d0, d1, d2}, [r4]!
+0x24,0xf9,0x1d,0x04 = vld3.8 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0x06,0x04 = vld3.8 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0x16,0x04 = vld3.8 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0x0f,0x05 = vld3.8 {d0, d2, d4}, [r4]
+0x24,0xf9,0x1f,0x05 = vld3.8 {d0, d2, d4}, [r4:64]
+0x24,0xf9,0x0d,0x05 = vld3.8 {d0, d2, d4}, [r4]!
+0x24,0xf9,0x1d,0x05 = vld3.8 {d0, d2, d4}, [r4:64]!
+0x24,0xf9,0x06,0x05 = vld3.8 {d0, d2, d4}, [r4], r6
+0x24,0xf9,0x16,0x05 = vld3.8 {d0, d2, d4}, [r4:64], r6
+0xa4,0xf9,0x2f,0x02 = vld3.8 {d0[1], d1[1], d2[1]}, [r4]
+0xa4,0xf9,0x2d,0x02 = vld3.8 {d0[1], d1[1], d2[1]}, [r4]!
+0xa4,0xf9,0x26,0x02 = vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6
+0xa4,0xf9,0x0f,0x0e = vld3.8 {d0[], d1[], d2[]}, [r4]
+0xa4,0xf9,0x0d,0x0e = vld3.8 {d0[], d1[], d2[]}, [r4]!
+0xa4,0xf9,0x06,0x0e = vld3.8 {d0[], d1[], d2[]}, [r4], r6
+0xa4,0xf9,0x2f,0x0e = vld3.8 {d0[], d2[], d4[]}, [r4]
+0xa4,0xf9,0x2d,0x0e = vld3.8 {d0[], d2[], d4[]}, [r4]!
+0xa4,0xf9,0x26,0x0e = vld3.8 {d0[], d2[], d4[]}, [r4], r6
+0x24,0xf9,0x4f,0x04 = vld3.16 {d0, d1, d2}, [r4]
+0x24,0xf9,0x5f,0x04 = vld3.16 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0x4d,0x04 = vld3.16 {d0, d1, d2}, [r4]!
+0x24,0xf9,0x5d,0x04 = vld3.16 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0x46,0x04 = vld3.16 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0x56,0x04 = vld3.16 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0x4f,0x05 = vld3.16 {d0, d2, d4}, [r4]
+0x24,0xf9,0x5f,0x05 = vld3.16 {d0, d2, d4}, [r4:64]
+0x24,0xf9,0x4d,0x05 = vld3.16 {d0, d2, d4}, [r4]!
+0x24,0xf9,0x5d,0x05 = vld3.16 {d0, d2, d4}, [r4:64]!
+0x24,0xf9,0x46,0x05 = vld3.16 {d0, d2, d4}, [r4], r6
+0x24,0xf9,0x56,0x05 = vld3.16 {d0, d2, d4}, [r4:64], r6
+0xa4,0xf9,0x4f,0x06 = vld3.16 {d0[1], d1[1], d2[1]}, [r4]
+0xa4,0xf9,0x4d,0x06 = vld3.16 {d0[1], d1[1], d2[1]}, [r4]!
+0xa4,0xf9,0x46,0x06 = vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6
+0xa4,0xf9,0x6f,0x06 = vld3.16 {d0[1], d2[1], d4[1]}, [r4]
+0xa4,0xf9,0x6d,0x06 = vld3.16 {d0[1], d2[1], d4[1]}, [r4]!
+0xa4,0xf9,0x66,0x06 = vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6
+0xa4,0xf9,0x4f,0x0e = vld3.16 {d0[], d1[], d2[]}, [r4]
+0xa4,0xf9,0x4d,0x0e = vld3.16 {d0[], d1[], d2[]}, [r4]!
+0xa4,0xf9,0x46,0x0e = vld3.16 {d0[], d1[], d2[]}, [r4], r6
+0xa4,0xf9,0x6f,0x0e = vld3.16 {d0[], d2[], d4[]}, [r4]
+0xa4,0xf9,0x6d,0x0e = vld3.16 {d0[], d2[], d4[]}, [r4]!
+0xa4,0xf9,0x66,0x0e = vld3.16 {d0[], d2[], d4[]}, [r4], r6
+0x24,0xf9,0x8f,0x04 = vld3.32 {d0, d1, d2}, [r4]
+0x24,0xf9,0x9f,0x04 = vld3.32 {d0, d1, d2}, [r4:64]
+0x24,0xf9,0x8d,0x04 = vld3.32 {d0, d1, d2}, [r4]!
+0x24,0xf9,0x9d,0x04 = vld3.32 {d0, d1, d2}, [r4:64]!
+0x24,0xf9,0x86,0x04 = vld3.32 {d0, d1, d2}, [r4], r6
+0x24,0xf9,0x96,0x04 = vld3.32 {d0, d1, d2}, [r4:64], r6
+0x24,0xf9,0x8f,0x05 = vld3.32 {d0, d2, d4}, [r4]
+0x24,0xf9,0x9f,0x05 = vld3.32 {d0, d2, d4}, [r4:64]
+0x24,0xf9,0x8d,0x05 = vld3.32 {d0, d2, d4}, [r4]!
+0x24,0xf9,0x9d,0x05 = vld3.32 {d0, d2, d4}, [r4:64]!
+0x24,0xf9,0x86,0x05 = vld3.32 {d0, d2, d4}, [r4], r6
+0x24,0xf9,0x96,0x05 = vld3.32 {d0, d2, d4}, [r4:64], r6
+0xa4,0xf9,0x8f,0x0a = vld3.32 {d0[1], d1[1], d2[1]}, [r4]
+0xa4,0xf9,0x8d,0x0a = vld3.32 {d0[1], d1[1], d2[1]}, [r4]!
+0xa4,0xf9,0x86,0x0a = vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6
+0xa4,0xf9,0xcf,0x0a = vld3.32 {d0[1], d2[1], d4[1]}, [r4]
+0xa4,0xf9,0xcd,0x0a = vld3.32 {d0[1], d2[1], d4[1]}, [r4]!
+0xa4,0xf9,0xc6,0x0a = vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6
+0xa4,0xf9,0x8f,0x0e = vld3.32 {d0[], d1[], d2[]}, [r4]
+0xa4,0xf9,0x8d,0x0e = vld3.32 {d0[], d1[], d2[]}, [r4]!
+0xa4,0xf9,0x86,0x0e = vld3.32 {d0[], d1[], d2[]}, [r4], r6
+0xa4,0xf9,0xaf,0x0e = vld3.32 {d0[], d2[], d4[]}, [r4]
+0xa4,0xf9,0xad,0x0e = vld3.32 {d0[], d2[], d4[]}, [r4]!
+0xa4,0xf9,0xa6,0x0e = vld3.32 {d0[], d2[], d4[]}, [r4], r6
+0x24,0xf9,0x0f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x1f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0x2f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0x3f,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x0d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x1d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0x2d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0x3d,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x06,0x00 = vld4.8 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x16,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0x26,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0x36,0x00 = vld4.8 {d0, d1, d2, d3}, [r4:256], r6
+0x24,0xf9,0x0f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4]
+0x24,0xf9,0x1f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:64]
+0x24,0xf9,0x2f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:128]
+0x24,0xf9,0x3f,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:256]
+0x24,0xf9,0x0d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4]!
+0x24,0xf9,0x1d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:64]!
+0x24,0xf9,0x2d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:128]!
+0x24,0xf9,0x3d,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:256]!
+0x24,0xf9,0x06,0x01 = vld4.8 {d0, d2, d4, d6}, [r4], r6
+0x24,0xf9,0x16,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:64], r6
+0x24,0xf9,0x26,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:128], r6
+0x24,0xf9,0x36,0x01 = vld4.8 {d0, d2, d4, d6}, [r4:256], r6
+0xa4,0xf9,0x2f,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]
+0xa4,0xf9,0x3f,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]
+0xa4,0xf9,0x2d,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0xa4,0xf9,0x3d,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!
+0xa4,0xf9,0x26,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0xa4,0xf9,0x36,0x03 = vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6
+0xa4,0xf9,0x0f,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4]
+0xa4,0xf9,0x1f,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]
+0xa4,0xf9,0x0d,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4]!
+0xa4,0xf9,0x1d,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!
+0xa4,0xf9,0x06,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6
+0xa4,0xf9,0x16,0x0f = vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6
+0xa4,0xf9,0x2f,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4]
+0xa4,0xf9,0x3f,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]
+0xa4,0xf9,0x2d,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4]!
+0xa4,0xf9,0x3d,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]!
+0xa4,0xf9,0x26,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6
+0xa4,0xf9,0x36,0x0f = vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6
+0x24,0xf9,0x4f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x5f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0x6f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0x7f,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x4d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x5d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0x6d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0x7d,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x46,0x00 = vld4.16 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x56,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0x66,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0x76,0x00 = vld4.16 {d0, d1, d2, d3}, [r4:256], r6
+0x24,0xf9,0x4f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4]
+0x24,0xf9,0x5f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:64]
+0x24,0xf9,0x6f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:128]
+0x24,0xf9,0x7f,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:256]
+0x24,0xf9,0x4d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4]!
+0x24,0xf9,0x5d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:64]!
+0x24,0xf9,0x6d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:128]!
+0x24,0xf9,0x7d,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:256]!
+0x24,0xf9,0x46,0x01 = vld4.16 {d0, d2, d4, d6}, [r4], r6
+0x24,0xf9,0x56,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:64], r6
+0x24,0xf9,0x66,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:128], r6
+0x24,0xf9,0x76,0x01 = vld4.16 {d0, d2, d4, d6}, [r4:256], r6
+0xa4,0xf9,0x4f,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]
+0xa4,0xf9,0x5f,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]
+0xa4,0xf9,0x4d,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0xa4,0xf9,0x5d,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!
+0xa4,0xf9,0x46,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0xa4,0xf9,0x56,0x07 = vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6
+0xa4,0xf9,0x6f,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]
+0xa4,0xf9,0x7f,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]
+0xa4,0xf9,0x6d,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!
+0xa4,0xf9,0x7d,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!
+0xa4,0xf9,0x66,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6
+0xa4,0xf9,0x76,0x07 = vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6
+0xa4,0xf9,0x4f,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4]
+0xa4,0xf9,0x5f,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]
+0xa4,0xf9,0x4d,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4]!
+0xa4,0xf9,0x5d,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!
+0xa4,0xf9,0x46,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6
+0xa4,0xf9,0x56,0x0f = vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6
+0xa4,0xf9,0x6f,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4]
+0xa4,0xf9,0x7f,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]
+0xa4,0xf9,0x6d,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4]!
+0xa4,0xf9,0x7d,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]!
+0xa4,0xf9,0x66,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6
+0xa4,0xf9,0x76,0x0f = vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6
+0x24,0xf9,0x8f,0x00 = vld4.32 {d0, d1, d2, d3}, [r4]
+0x24,0xf9,0x9f,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:64]
+0x24,0xf9,0xaf,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:128]
+0x24,0xf9,0xbf,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:256]
+0x24,0xf9,0x8d,0x00 = vld4.32 {d0, d1, d2, d3}, [r4]!
+0x24,0xf9,0x9d,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:64]!
+0x24,0xf9,0xad,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:128]!
+0x24,0xf9,0xbd,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:256]!
+0x24,0xf9,0x86,0x00 = vld4.32 {d0, d1, d2, d3}, [r4], r6
+0x24,0xf9,0x96,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:64], r6
+0x24,0xf9,0xa6,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:128], r6
+0x24,0xf9,0xb6,0x00 = vld4.32 {d0, d1, d2, d3}, [r4:256], r6
+0x24,0xf9,0x8f,0x01 = vld4.32 {d0, d2, d4, d6}, [r4]
+0x24,0xf9,0x9f,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:64]
+0x24,0xf9,0xaf,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:128]
+0x24,0xf9,0xbf,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:256]
+0x24,0xf9,0x8d,0x01 = vld4.32 {d0, d2, d4, d6}, [r4]!
+0x24,0xf9,0x9d,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:64]!
+0x24,0xf9,0xad,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:128]!
+0x24,0xf9,0xbd,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:256]!
+0x24,0xf9,0x86,0x01 = vld4.32 {d0, d2, d4, d6}, [r4], r6
+0x24,0xf9,0x96,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:64], r6
+0x24,0xf9,0xa6,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:128], r6
+0x24,0xf9,0xb6,0x01 = vld4.32 {d0, d2, d4, d6}, [r4:256], r6
+0xa4,0xf9,0x8f,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]
+0xa4,0xf9,0x9f,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]
+0xa4,0xf9,0xaf,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]
+0xa4,0xf9,0x8d,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0xa4,0xf9,0x9d,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!
+0xa4,0xf9,0xad,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!
+0xa4,0xf9,0x86,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0xa4,0xf9,0x96,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6
+0xa4,0xf9,0xa6,0x0b = vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6
+0xa4,0xf9,0xcf,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]
+0xa4,0xf9,0xdf,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]
+0xa4,0xf9,0xef,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]
+0xa4,0xf9,0xcd,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!
+0xa4,0xf9,0xdd,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!
+0xa4,0xf9,0xed,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!
+0xa4,0xf9,0xc6,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6
+0xa4,0xf9,0xd6,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6
+0xa4,0xf9,0xe6,0x0b = vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6
+0xa4,0xf9,0x8f,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4]
+0xa4,0xf9,0x9f,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]
+0xa4,0xf9,0xdf,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]
+0xa4,0xf9,0x8d,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4]!
+0xa4,0xf9,0x9d,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]!
+0xa4,0xf9,0xdd,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!
+0xa4,0xf9,0x86,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6
+0xa4,0xf9,0x96,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6
+0xa4,0xf9,0xd6,0x0f = vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6
+0xa4,0xf9,0xaf,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4]
+0xa4,0xf9,0xbf,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]
+0xa4,0xf9,0xff,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]
+0xa4,0xf9,0xad,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4]!
+0xa4,0xf9,0xbd,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]!
+0xa4,0xf9,0xfd,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]!
+0xa4,0xf9,0xa6,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6
+0xa4,0xf9,0xb6,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6
+0xa4,0xf9,0xf6,0x0f = vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6
+0x04,0xf9,0x0f,0x07 = vst1.8 {d0}, [r4]
+0x04,0xf9,0x1f,0x07 = vst1.8 {d0}, [r4:64]
+0x04,0xf9,0x0d,0x07 = vst1.8 {d0}, [r4]!
+0x04,0xf9,0x1d,0x07 = vst1.8 {d0}, [r4:64]!
+0x04,0xf9,0x06,0x07 = vst1.8 {d0}, [r4], r6
+0x04,0xf9,0x16,0x07 = vst1.8 {d0}, [r4:64], r6
+0x04,0xf9,0x0f,0x0a = vst1.8 {d0, d1}, [r4]
+0x04,0xf9,0x1f,0x0a = vst1.8 {d0, d1}, [r4:64]
+0x04,0xf9,0x2f,0x0a = vst1.8 {d0, d1}, [r4:128]
+0x04,0xf9,0x0d,0x0a = vst1.8 {d0, d1}, [r4]!
+0x04,0xf9,0x1d,0x0a = vst1.8 {d0, d1}, [r4:64]!
+0x04,0xf9,0x2d,0x0a = vst1.8 {d0, d1}, [r4:128]!
+0x04,0xf9,0x06,0x0a = vst1.8 {d0, d1}, [r4], r6
+0x04,0xf9,0x16,0x0a = vst1.8 {d0, d1}, [r4:64], r6
+0x04,0xf9,0x26,0x0a = vst1.8 {d0, d1}, [r4:128], r6
+0x04,0xf9,0x0f,0x06 = vst1.8 {d0, d1, d2}, [r4]
+0x04,0xf9,0x1f,0x06 = vst1.8 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0x0d,0x06 = vst1.8 {d0, d1, d2}, [r4]!
+0x04,0xf9,0x1d,0x06 = vst1.8 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0x06,0x06 = vst1.8 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0x16,0x06 = vst1.8 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0x0f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x1f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0x2f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0x3f,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x0d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x1d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0x2d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0x3d,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x06,0x02 = vst1.8 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x16,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0x26,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0x36,0x02 = vst1.8 {d0, d1, d2, d3}, [r4:256], r6
+0x84,0xf9,0x4f,0x00 = vst1.8 {d0[2]}, [r4]
+0x84,0xf9,0x4d,0x00 = vst1.8 {d0[2]}, [r4]!
+0x84,0xf9,0x46,0x00 = vst1.8 {d0[2]}, [r4], r6
+0x04,0xf9,0x4f,0x07 = vst1.16 {d0}, [r4]
+0x04,0xf9,0x5f,0x07 = vst1.16 {d0}, [r4:64]
+0x04,0xf9,0x4d,0x07 = vst1.16 {d0}, [r4]!
+0x04,0xf9,0x5d,0x07 = vst1.16 {d0}, [r4:64]!
+0x04,0xf9,0x46,0x07 = vst1.16 {d0}, [r4], r6
+0x04,0xf9,0x56,0x07 = vst1.16 {d0}, [r4:64], r6
+0x04,0xf9,0x4f,0x0a = vst1.16 {d0, d1}, [r4]
+0x04,0xf9,0x5f,0x0a = vst1.16 {d0, d1}, [r4:64]
+0x04,0xf9,0x6f,0x0a = vst1.16 {d0, d1}, [r4:128]
+0x04,0xf9,0x4d,0x0a = vst1.16 {d0, d1}, [r4]!
+0x04,0xf9,0x5d,0x0a = vst1.16 {d0, d1}, [r4:64]!
+0x04,0xf9,0x6d,0x0a = vst1.16 {d0, d1}, [r4:128]!
+0x04,0xf9,0x46,0x0a = vst1.16 {d0, d1}, [r4], r6
+0x04,0xf9,0x56,0x0a = vst1.16 {d0, d1}, [r4:64], r6
+0x04,0xf9,0x66,0x0a = vst1.16 {d0, d1}, [r4:128], r6
+0x04,0xf9,0x4f,0x06 = vst1.16 {d0, d1, d2}, [r4]
+0x04,0xf9,0x5f,0x06 = vst1.16 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0x4d,0x06 = vst1.16 {d0, d1, d2}, [r4]!
+0x04,0xf9,0x5d,0x06 = vst1.16 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0x46,0x06 = vst1.16 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0x56,0x06 = vst1.16 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0x4f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x5f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0x6f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0x7f,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x4d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x5d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0x6d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0x7d,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x46,0x02 = vst1.16 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x56,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0x66,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0x76,0x02 = vst1.16 {d0, d1, d2, d3}, [r4:256], r6
+0x84,0xf9,0x8f,0x04 = vst1.16 {d0[2]}, [r4]
+0x84,0xf9,0x9f,0x04 = vst1.16 {d0[2]}, [r4:16]
+0x84,0xf9,0x8d,0x04 = vst1.16 {d0[2]}, [r4]!
+0x84,0xf9,0x9d,0x04 = vst1.16 {d0[2]}, [r4:16]!
+0x84,0xf9,0x86,0x04 = vst1.16 {d0[2]}, [r4], r6
+0x84,0xf9,0x96,0x04 = vst1.16 {d0[2]}, [r4:16], r6
+0x04,0xf9,0x8f,0x07 = vst1.32 {d0}, [r4]
+0x04,0xf9,0x9f,0x07 = vst1.32 {d0}, [r4:64]
+0x04,0xf9,0x8d,0x07 = vst1.32 {d0}, [r4]!
+0x04,0xf9,0x9d,0x07 = vst1.32 {d0}, [r4:64]!
+0x04,0xf9,0x86,0x07 = vst1.32 {d0}, [r4], r6
+0x04,0xf9,0x96,0x07 = vst1.32 {d0}, [r4:64], r6
+0x04,0xf9,0x8f,0x0a = vst1.32 {d0, d1}, [r4]
+0x04,0xf9,0x9f,0x0a = vst1.32 {d0, d1}, [r4:64]
+0x04,0xf9,0xaf,0x0a = vst1.32 {d0, d1}, [r4:128]
+0x04,0xf9,0x8d,0x0a = vst1.32 {d0, d1}, [r4]!
+0x04,0xf9,0x9d,0x0a = vst1.32 {d0, d1}, [r4:64]!
+0x04,0xf9,0xad,0x0a = vst1.32 {d0, d1}, [r4:128]!
+0x04,0xf9,0x86,0x0a = vst1.32 {d0, d1}, [r4], r6
+0x04,0xf9,0x96,0x0a = vst1.32 {d0, d1}, [r4:64], r6
+0x04,0xf9,0xa6,0x0a = vst1.32 {d0, d1}, [r4:128], r6
+0x04,0xf9,0x8f,0x06 = vst1.32 {d0, d1, d2}, [r4]
+0x04,0xf9,0x9f,0x06 = vst1.32 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0x8d,0x06 = vst1.32 {d0, d1, d2}, [r4]!
+0x04,0xf9,0x9d,0x06 = vst1.32 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0x86,0x06 = vst1.32 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0x96,0x06 = vst1.32 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0x8f,0x02 = vst1.32 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x9f,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0xaf,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0xbf,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x8d,0x02 = vst1.32 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x9d,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0xad,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0xbd,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x86,0x02 = vst1.32 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x96,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0xa6,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0xb6,0x02 = vst1.32 {d0, d1, d2, d3}, [r4:256], r6
+0x84,0xf9,0x8f,0x08 = vst1.32 {d0[1]}, [r4]
+0x84,0xf9,0xbf,0x08 = vst1.32 {d0[1]}, [r4:32]
+0x84,0xf9,0x8d,0x08 = vst1.32 {d0[1]}, [r4]!
+0x84,0xf9,0xbd,0x08 = vst1.32 {d0[1]}, [r4:32]!
+0x84,0xf9,0x86,0x08 = vst1.32 {d0[1]}, [r4], r6
+0x84,0xf9,0xb6,0x08 = vst1.32 {d0[1]}, [r4:32], r6
+0x04,0xf9,0xcf,0x07 = vst1.64 {d0}, [r4]
+0x04,0xf9,0xdf,0x07 = vst1.64 {d0}, [r4:64]
+0x04,0xf9,0xcd,0x07 = vst1.64 {d0}, [r4]!
+0x04,0xf9,0xdd,0x07 = vst1.64 {d0}, [r4:64]!
+0x04,0xf9,0xc6,0x07 = vst1.64 {d0}, [r4], r6
+0x04,0xf9,0xd6,0x07 = vst1.64 {d0}, [r4:64], r6
+0x04,0xf9,0xcf,0x0a = vst1.64 {d0, d1}, [r4]
+0x04,0xf9,0xdf,0x0a = vst1.64 {d0, d1}, [r4:64]
+0x04,0xf9,0xef,0x0a = vst1.64 {d0, d1}, [r4:128]
+0x04,0xf9,0xcd,0x0a = vst1.64 {d0, d1}, [r4]!
+0x04,0xf9,0xdd,0x0a = vst1.64 {d0, d1}, [r4:64]!
+0x04,0xf9,0xed,0x0a = vst1.64 {d0, d1}, [r4:128]!
+0x04,0xf9,0xc6,0x0a = vst1.64 {d0, d1}, [r4], r6
+0x04,0xf9,0xd6,0x0a = vst1.64 {d0, d1}, [r4:64], r6
+0x04,0xf9,0xe6,0x0a = vst1.64 {d0, d1}, [r4:128], r6
+0x04,0xf9,0xcf,0x06 = vst1.64 {d0, d1, d2}, [r4]
+0x04,0xf9,0xdf,0x06 = vst1.64 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0xcd,0x06 = vst1.64 {d0, d1, d2}, [r4]!
+0x04,0xf9,0xdd,0x06 = vst1.64 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0xc6,0x06 = vst1.64 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0xd6,0x06 = vst1.64 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0xcf,0x02 = vst1.64 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0xdf,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0xef,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0xff,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0xcd,0x02 = vst1.64 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0xdd,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0xed,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0xfd,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0xc6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0xd6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0xe6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0xf6,0x02 = vst1.64 {d0, d1, d2, d3}, [r4:256], r6
+0x04,0xf9,0x0f,0x08 = vst2.8 {d0, d1}, [r4]
+0x04,0xf9,0x1f,0x08 = vst2.8 {d0, d1}, [r4:64]
+0x04,0xf9,0x2f,0x08 = vst2.8 {d0, d1}, [r4:128]
+0x04,0xf9,0x0d,0x08 = vst2.8 {d0, d1}, [r4]!
+0x04,0xf9,0x1d,0x08 = vst2.8 {d0, d1}, [r4:64]!
+0x04,0xf9,0x2d,0x08 = vst2.8 {d0, d1}, [r4:128]!
+0x04,0xf9,0x06,0x08 = vst2.8 {d0, d1}, [r4], r6
+0x04,0xf9,0x16,0x08 = vst2.8 {d0, d1}, [r4:64], r6
+0x04,0xf9,0x26,0x08 = vst2.8 {d0, d1}, [r4:128], r6
+0x04,0xf9,0x0f,0x09 = vst2.8 {d0, d2}, [r4]
+0x04,0xf9,0x1f,0x09 = vst2.8 {d0, d2}, [r4:64]
+0x04,0xf9,0x2f,0x09 = vst2.8 {d0, d2}, [r4:128]
+0x04,0xf9,0x0d,0x09 = vst2.8 {d0, d2}, [r4]!
+0x04,0xf9,0x1d,0x09 = vst2.8 {d0, d2}, [r4:64]!
+0x04,0xf9,0x2d,0x09 = vst2.8 {d0, d2}, [r4:128]!
+0x04,0xf9,0x06,0x09 = vst2.8 {d0, d2}, [r4], r6
+0x04,0xf9,0x16,0x09 = vst2.8 {d0, d2}, [r4:64], r6
+0x04,0xf9,0x26,0x09 = vst2.8 {d0, d2}, [r4:128], r6
+0x04,0xf9,0x0f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x1f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0x2f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0x3f,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x0d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x1d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0x2d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0x3d,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x06,0x03 = vst2.8 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x16,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0x26,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0x36,0x03 = vst2.8 {d0, d1, d2, d3}, [r4:256], r6
+0x84,0xf9,0x4f,0x01 = vst2.8 {d0[2], d1[2]}, [r4]
+0x84,0xf9,0x5f,0x01 = vst2.8 {d0[2], d1[2]}, [r4:16]
+0x84,0xf9,0x4d,0x01 = vst2.8 {d0[2], d1[2]}, [r4]!
+0x84,0xf9,0x5d,0x01 = vst2.8 {d0[2], d1[2]}, [r4:16]!
+0x84,0xf9,0x46,0x01 = vst2.8 {d0[2], d1[2]}, [r4], r6
+0x84,0xf9,0x56,0x01 = vst2.8 {d0[2], d1[2]}, [r4:16], r6
+0x04,0xf9,0x8f,0x08 = vst2.32 {d0, d1}, [r4]
+0x04,0xf9,0x9f,0x08 = vst2.32 {d0, d1}, [r4:64]
+0x04,0xf9,0xaf,0x08 = vst2.32 {d0, d1}, [r4:128]
+0x04,0xf9,0x8d,0x08 = vst2.32 {d0, d1}, [r4]!
+0x04,0xf9,0x9d,0x08 = vst2.32 {d0, d1}, [r4:64]!
+0x04,0xf9,0xad,0x08 = vst2.32 {d0, d1}, [r4:128]!
+0x04,0xf9,0x86,0x08 = vst2.32 {d0, d1}, [r4], r6
+0x04,0xf9,0x96,0x08 = vst2.32 {d0, d1}, [r4:64], r6
+0x04,0xf9,0xa6,0x08 = vst2.32 {d0, d1}, [r4:128], r6
+0x04,0xf9,0x8f,0x09 = vst2.32 {d0, d2}, [r4]
+0x04,0xf9,0x9f,0x09 = vst2.32 {d0, d2}, [r4:64]
+0x04,0xf9,0xaf,0x09 = vst2.32 {d0, d2}, [r4:128]
+0x04,0xf9,0x8d,0x09 = vst2.32 {d0, d2}, [r4]!
+0x04,0xf9,0x9d,0x09 = vst2.32 {d0, d2}, [r4:64]!
+0x04,0xf9,0xad,0x09 = vst2.32 {d0, d2}, [r4:128]!
+0x04,0xf9,0x86,0x09 = vst2.32 {d0, d2}, [r4], r6
+0x04,0xf9,0x96,0x09 = vst2.32 {d0, d2}, [r4:64], r6
+0x04,0xf9,0xa6,0x09 = vst2.32 {d0, d2}, [r4:128], r6
+0x04,0xf9,0x8f,0x03 = vst2.32 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x9f,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0xaf,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0xbf,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x8d,0x03 = vst2.32 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x9d,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0xad,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0xbd,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x86,0x03 = vst2.32 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x96,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0xa6,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0xb6,0x03 = vst2.32 {d0, d1, d2, d3}, [r4:256], r6
+0x84,0xf9,0x8f,0x09 = vst2.32 {d0[1], d1[1]}, [r4]
+0x84,0xf9,0x9f,0x09 = vst2.32 {d0[1], d1[1]}, [r4:64]
+0x84,0xf9,0x8d,0x09 = vst2.32 {d0[1], d1[1]}, [r4]!
+0x84,0xf9,0x9d,0x09 = vst2.32 {d0[1], d1[1]}, [r4:64]!
+0x84,0xf9,0x86,0x09 = vst2.32 {d0[1], d1[1]}, [r4], r6
+0x84,0xf9,0x96,0x09 = vst2.32 {d0[1], d1[1]}, [r4:64], r6
+0x84,0xf9,0xcf,0x09 = vst2.32 {d0[1], d2[1]}, [r4]
+0x84,0xf9,0xdf,0x09 = vst2.32 {d0[1], d2[1]}, [r4:64]
+0x84,0xf9,0xcd,0x09 = vst2.32 {d0[1], d2[1]}, [r4]!
+0x84,0xf9,0xdd,0x09 = vst2.32 {d0[1], d2[1]}, [r4:64]!
+0x84,0xf9,0xc6,0x09 = vst2.32 {d0[1], d2[1]}, [r4], r6
+0x84,0xf9,0xd6,0x09 = vst2.32 {d0[1], d2[1]}, [r4:64], r6
+0x04,0xf9,0x0f,0x04 = vst3.8 {d0, d1, d2}, [r4]
+0x04,0xf9,0x1f,0x04 = vst3.8 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0x0d,0x04 = vst3.8 {d0, d1, d2}, [r4]!
+0x04,0xf9,0x1d,0x04 = vst3.8 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0x06,0x04 = vst3.8 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0x16,0x04 = vst3.8 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0x0f,0x05 = vst3.8 {d0, d2, d4}, [r4]
+0x04,0xf9,0x1f,0x05 = vst3.8 {d0, d2, d4}, [r4:64]
+0x04,0xf9,0x0d,0x05 = vst3.8 {d0, d2, d4}, [r4]!
+0x04,0xf9,0x1d,0x05 = vst3.8 {d0, d2, d4}, [r4:64]!
+0x04,0xf9,0x06,0x05 = vst3.8 {d0, d2, d4}, [r4], r6
+0x04,0xf9,0x16,0x05 = vst3.8 {d0, d2, d4}, [r4:64], r6
+0x84,0xf9,0x2f,0x02 = vst3.8 {d0[1], d1[1], d2[1]}, [r4]
+0x84,0xf9,0x2d,0x02 = vst3.8 {d0[1], d1[1], d2[1]}, [r4]!
+0x84,0xf9,0x26,0x02 = vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6
+0x04,0xf9,0x4f,0x04 = vst3.16 {d0, d1, d2}, [r4]
+0x04,0xf9,0x5f,0x04 = vst3.16 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0x4d,0x04 = vst3.16 {d0, d1, d2}, [r4]!
+0x04,0xf9,0x5d,0x04 = vst3.16 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0x46,0x04 = vst3.16 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0x56,0x04 = vst3.16 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0x4f,0x05 = vst3.16 {d0, d2, d4}, [r4]
+0x04,0xf9,0x5f,0x05 = vst3.16 {d0, d2, d4}, [r4:64]
+0x04,0xf9,0x4d,0x05 = vst3.16 {d0, d2, d4}, [r4]!
+0x04,0xf9,0x5d,0x05 = vst3.16 {d0, d2, d4}, [r4:64]!
+0x04,0xf9,0x46,0x05 = vst3.16 {d0, d2, d4}, [r4], r6
+0x04,0xf9,0x56,0x05 = vst3.16 {d0, d2, d4}, [r4:64], r6
+0x84,0xf9,0x4f,0x06 = vst3.16 {d0[1], d1[1], d2[1]}, [r4]
+0x84,0xf9,0x4d,0x06 = vst3.16 {d0[1], d1[1], d2[1]}, [r4]!
+0x84,0xf9,0x46,0x06 = vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6
+0x84,0xf9,0x6f,0x06 = vst3.16 {d0[1], d2[1], d4[1]}, [r4]
+0x84,0xf9,0x6d,0x06 = vst3.16 {d0[1], d2[1], d4[1]}, [r4]!
+0x84,0xf9,0x66,0x06 = vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6
+0x04,0xf9,0x8f,0x04 = vst3.32 {d0, d1, d2}, [r4]
+0x04,0xf9,0x9f,0x04 = vst3.32 {d0, d1, d2}, [r4:64]
+0x04,0xf9,0x8d,0x04 = vst3.32 {d0, d1, d2}, [r4]!
+0x04,0xf9,0x9d,0x04 = vst3.32 {d0, d1, d2}, [r4:64]!
+0x04,0xf9,0x86,0x04 = vst3.32 {d0, d1, d2}, [r4], r6
+0x04,0xf9,0x96,0x04 = vst3.32 {d0, d1, d2}, [r4:64], r6
+0x04,0xf9,0x8f,0x05 = vst3.32 {d0, d2, d4}, [r4]
+0x04,0xf9,0x9f,0x05 = vst3.32 {d0, d2, d4}, [r4:64]
+0x04,0xf9,0x8d,0x05 = vst3.32 {d0, d2, d4}, [r4]!
+0x04,0xf9,0x9d,0x05 = vst3.32 {d0, d2, d4}, [r4:64]!
+0x04,0xf9,0x86,0x05 = vst3.32 {d0, d2, d4}, [r4], r6
+0x04,0xf9,0x96,0x05 = vst3.32 {d0, d2, d4}, [r4:64], r6
+0x84,0xf9,0x8f,0x0a = vst3.32 {d0[1], d1[1], d2[1]}, [r4]
+0x84,0xf9,0x8d,0x0a = vst3.32 {d0[1], d1[1], d2[1]}, [r4]!
+0x84,0xf9,0x86,0x0a = vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6
+0x84,0xf9,0xcf,0x0a = vst3.32 {d0[1], d2[1], d4[1]}, [r4]
+0x84,0xf9,0xcd,0x0a = vst3.32 {d0[1], d2[1], d4[1]}, [r4]!
+0x84,0xf9,0xc6,0x0a = vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6
+0x04,0xf9,0x0f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x1f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0x2f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0x3f,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x0d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x1d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0x2d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0x3d,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x06,0x00 = vst4.8 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x16,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0x26,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0x36,0x00 = vst4.8 {d0, d1, d2, d3}, [r4:256], r6
+0x04,0xf9,0x0f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4]
+0x04,0xf9,0x1f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:64]
+0x04,0xf9,0x2f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:128]
+0x04,0xf9,0x3f,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:256]
+0x04,0xf9,0x0d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4]!
+0x04,0xf9,0x1d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:64]!
+0x04,0xf9,0x2d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:128]!
+0x04,0xf9,0x3d,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:256]!
+0x04,0xf9,0x06,0x01 = vst4.8 {d0, d2, d4, d6}, [r4], r6
+0x04,0xf9,0x16,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:64], r6
+0x04,0xf9,0x26,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:128], r6
+0x04,0xf9,0x36,0x01 = vst4.8 {d0, d2, d4, d6}, [r4:256], r6
+0x84,0xf9,0x2f,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]
+0x84,0xf9,0x3f,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]
+0x84,0xf9,0x2d,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0x84,0xf9,0x3d,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!
+0x84,0xf9,0x26,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0x84,0xf9,0x36,0x03 = vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6
+0x04,0xf9,0x4f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x5f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0x6f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0x7f,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x4d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x5d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0x6d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0x7d,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x46,0x00 = vst4.16 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x56,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0x66,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0x76,0x00 = vst4.16 {d0, d1, d2, d3}, [r4:256], r6
+0x04,0xf9,0x4f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4]
+0x04,0xf9,0x5f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:64]
+0x04,0xf9,0x6f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:128]
+0x04,0xf9,0x7f,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:256]
+0x04,0xf9,0x4d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4]!
+0x04,0xf9,0x5d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:64]!
+0x04,0xf9,0x6d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:128]!
+0x04,0xf9,0x7d,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:256]!
+0x04,0xf9,0x46,0x01 = vst4.16 {d0, d2, d4, d6}, [r4], r6
+0x04,0xf9,0x56,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:64], r6
+0x04,0xf9,0x66,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:128], r6
+0x04,0xf9,0x76,0x01 = vst4.16 {d0, d2, d4, d6}, [r4:256], r6
+0x84,0xf9,0x4f,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]
+0x84,0xf9,0x5f,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]
+0x84,0xf9,0x4d,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0x84,0xf9,0x5d,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!
+0x84,0xf9,0x46,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0x84,0xf9,0x56,0x07 = vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6
+0x84,0xf9,0x6f,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]
+0x84,0xf9,0x7f,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]
+0x84,0xf9,0x6d,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!
+0x84,0xf9,0x7d,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!
+0x84,0xf9,0x66,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6
+0x84,0xf9,0x76,0x07 = vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6
+0x04,0xf9,0x8f,0x00 = vst4.32 {d0, d1, d2, d3}, [r4]
+0x04,0xf9,0x9f,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:64]
+0x04,0xf9,0xaf,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:128]
+0x04,0xf9,0xbf,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:256]
+0x04,0xf9,0x8d,0x00 = vst4.32 {d0, d1, d2, d3}, [r4]!
+0x04,0xf9,0x9d,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:64]!
+0x04,0xf9,0xad,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:128]!
+0x04,0xf9,0xbd,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:256]!
+0x04,0xf9,0x86,0x00 = vst4.32 {d0, d1, d2, d3}, [r4], r6
+0x04,0xf9,0x96,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:64], r6
+0x04,0xf9,0xa6,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:128], r6
+0x04,0xf9,0xb6,0x00 = vst4.32 {d0, d1, d2, d3}, [r4:256], r6
+0x04,0xf9,0x8f,0x01 = vst4.32 {d0, d2, d4, d6}, [r4]
+0x04,0xf9,0x9f,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:64]
+0x04,0xf9,0xaf,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:128]
+0x04,0xf9,0xbf,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:256]
+0x04,0xf9,0x8d,0x01 = vst4.32 {d0, d2, d4, d6}, [r4]!
+0x04,0xf9,0x9d,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:64]!
+0x04,0xf9,0xad,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:128]!
+0x04,0xf9,0xbd,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:256]!
+0x04,0xf9,0x86,0x01 = vst4.32 {d0, d2, d4, d6}, [r4], r6
+0x04,0xf9,0x96,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:64], r6
+0x04,0xf9,0xa6,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:128], r6
+0x04,0xf9,0xb6,0x01 = vst4.32 {d0, d2, d4, d6}, [r4:256], r6
+0x84,0xf9,0x8f,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]
+0x84,0xf9,0x9f,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]
+0x84,0xf9,0xaf,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]
+0x84,0xf9,0x8d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0x84,0xf9,0x9d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!
+0x84,0xf9,0xad,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!
+0x84,0xf9,0x86,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0x84,0xf9,0x96,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6
+0x84,0xf9,0xa6,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6
+0x84,0xf9,0xcf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]
+0x84,0xf9,0xdf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]
+0x84,0xf9,0xef,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]
+0x84,0xf9,0xcd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!
+0x84,0xf9,0xdd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!
+0x84,0xf9,0xed,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!
+0x84,0xf9,0xc6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6
+0x84,0xf9,0xd6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6
+0x84,0xf9,0xe6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6
+0x84,0xf9,0x8d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!
+0x84,0xf9,0x9d,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!
+0x84,0xf9,0xad,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!
+0x84,0xf9,0x86,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6
+0x84,0xf9,0x96,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6
+0x84,0xf9,0xa6,0x0b = vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6
+0x84,0xf9,0xcf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]
+0x84,0xf9,0xdf,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]
+0x84,0xf9,0xef,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]
+0x84,0xf9,0xcd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!
+0x84,0xf9,0xdd,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!
+0x84,0xf9,0xed,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!
+0x84,0xf9,0xc6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6
+0x84,0xf9,0xd6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6
+0x84,0xf9,0xe6,0x0b = vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6
diff --git a/suite/MC/ARM/neon-vst-encoding.s.cs b/suite/MC/ARM/neon-vst-encoding.s.cs
index 09240adf8..db04fa225 100644
--- a/suite/MC/ARM/neon-vst-encoding.s.cs
+++ b/suite/MC/ARM/neon-vst-encoding.s.cs
@@ -1,4 +1,4 @@
-# CS_ARCH_ARM, CS_MODE_ARM, None
+# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
 0x1f,0x07,0x40,0xf4 = vst1.8 {d16}, [r0:64]
 0x4f,0x07,0x40,0xf4 = vst1.16 {d16}, [r0]
 0x8f,0x07,0x40,0xf4 = vst1.32 {d16}, [r0]
@@ -88,7 +88,7 @@
 0x2d,0x62,0x88,0xf4 = vst3.8 {d6[1], d7[1], d8[1]}, [r8]!
 0x4d,0x96,0x87,0xf4 = vst3.16 {d9[1], d10[1], d11[1]}, [r7]!
 0x8d,0x1a,0x86,0xf4 = vst3.32 {d1[1], d2[1], d3[1]}, [r6]!
-// 0x6d,0x46,0xc5,0xf4 = vst3.16 {d20[1], d21[1], d22[1]}, [r5]!
+0x6d,0x46,0xc5,0xf4 = vst3.16 {d20[1], d22[1], d24[1]}, [r5]!
 0xcd,0x5a,0x84,0xf4 = vst3.32 {d5[1], d7[1], d9[1]}, [r4]!
 0x2f,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]
 0x4f,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]
@@ -98,7 +98,7 @@
 0x3d,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
 0x5d,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!
 0xad,0x0b,0xc3,0xf4 = vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!
-// 0x6d,0x17,0xc7,0xf4 = vst4.16 {d17[1], d18[1], d19[1], d20[1]}, [r7]!
+0x6d,0x17,0xc7,0xf4 = vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!
 0xcd,0x0b,0xc8,0xf4 = vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!
 0x38,0x03,0xc1,0xf4 = vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8
 0x47,0x07,0xc2,0xf4 = vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7
diff --git a/suite/MC/ARM/neont2-bitwise-encoding.s.cs b/suite/MC/ARM/neont2-bitwise-encoding.s.cs
index 9d2d8983b..30cd6c6f6 100644
--- a/suite/MC/ARM/neont2-bitwise-encoding.s.cs
+++ b/suite/MC/ARM/neont2-bitwise-encoding.s.cs
@@ -13,3 +13,7 @@
 0xf0,0xff,0xe0,0x05 = vmvn q8, q8
 0x51,0xff,0xb0,0x21 = vbsl d18, d17, d16
 0x54,0xff,0xf2,0x01 = vbsl q8, q10, q9
+0x61,0xff,0xb0,0x21 = vbit d18, d17, d16
+0x64,0xff,0xf2,0x01 = vbit q8, q10, q9
+0x71,0xff,0xb0,0x21 = vbif d18, d17, d16
+0x74,0xff,0xf2,0x01 = vbif q8, q10, q9
diff --git a/suite/MC/ARM/neont2-satshift-encoding.s.cs b/suite/MC/ARM/neont2-satshift-encoding.s.cs
index 859b44a59..f971d11ad 100644
--- a/suite/MC/ARM/neont2-satshift-encoding.s.cs
+++ b/suite/MC/ARM/neont2-satshift-encoding.s.cs
@@ -16,29 +16,29 @@
 0x62,0xff,0xf0,0x04 = vqshl.u32 q8, q8, q9
 0x72,0xff,0xf0,0x04 = vqshl.u64 q8, q8, q9
 0xcf,0xef,0x30,0x07 = vqshl.s8 d16, d16, #7
-0xdf,0xef,0x30,0x07 = vqshl.s16 d16, d16, #15
-0xff,0xef,0x30,0x07 = vqshl.s32 d16, d16, #31
-0xff,0xef,0xb0,0x07 = vqshl.s64 d16, d16, #63
+0xdf,0xef,0x30,0x07 = vqshl.s16 d16, d16, #0xf
+0xff,0xef,0x30,0x07 = vqshl.s32 d16, d16, #0x1f
+0xff,0xef,0xb0,0x07 = vqshl.s64 d16, d16, #0x3f
 0xcf,0xff,0x30,0x07 = vqshl.u8 d16, d16, #7
-0xdf,0xff,0x30,0x07 = vqshl.u16 d16, d16, #15
-0xff,0xff,0x30,0x07 = vqshl.u32 d16, d16, #31
-0xff,0xff,0xb0,0x07 = vqshl.u64 d16, d16, #63
+0xdf,0xff,0x30,0x07 = vqshl.u16 d16, d16, #0xf
+0xff,0xff,0x30,0x07 = vqshl.u32 d16, d16, #0x1f
+0xff,0xff,0xb0,0x07 = vqshl.u64 d16, d16, #0x3f
 0xcf,0xff,0x30,0x06 = vqshlu.s8 d16, d16, #7
-0xdf,0xff,0x30,0x06 = vqshlu.s16 d16, d16, #15
-0xff,0xff,0x30,0x06 = vqshlu.s32 d16, d16, #31
-0xff,0xff,0xb0,0x06 = vqshlu.s64 d16, d16, #63
+0xdf,0xff,0x30,0x06 = vqshlu.s16 d16, d16, #0xf
+0xff,0xff,0x30,0x06 = vqshlu.s32 d16, d16, #0x1f
+0xff,0xff,0xb0,0x06 = vqshlu.s64 d16, d16, #0x3f
 0xcf,0xef,0x70,0x07 = vqshl.s8 q8, q8, #7
-0xdf,0xef,0x70,0x07 = vqshl.s16 q8, q8, #15
-0xff,0xef,0x70,0x07 = vqshl.s32 q8, q8, #31
-0xff,0xef,0xf0,0x07 = vqshl.s64 q8, q8, #63
+0xdf,0xef,0x70,0x07 = vqshl.s16 q8, q8, #0xf
+0xff,0xef,0x70,0x07 = vqshl.s32 q8, q8, #0x1f
+0xff,0xef,0xf0,0x07 = vqshl.s64 q8, q8, #0x3f
 0xcf,0xff,0x70,0x07 = vqshl.u8 q8, q8, #7
-0xdf,0xff,0x70,0x07 = vqshl.u16 q8, q8, #15
-0xff,0xff,0x70,0x07 = vqshl.u32 q8, q8, #31
-0xff,0xff,0xf0,0x07 = vqshl.u64 q8, q8, #63
+0xdf,0xff,0x70,0x07 = vqshl.u16 q8, q8, #0xf
+0xff,0xff,0x70,0x07 = vqshl.u32 q8, q8, #0x1f
+0xff,0xff,0xf0,0x07 = vqshl.u64 q8, q8, #0x3f
 0xcf,0xff,0x70,0x06 = vqshlu.s8 q8, q8, #7
-0xdf,0xff,0x70,0x06 = vqshlu.s16 q8, q8, #15
-0xff,0xff,0x70,0x06 = vqshlu.s32 q8, q8, #31
-0xff,0xff,0xf0,0x06 = vqshlu.s64 q8, q8, #63
+0xdf,0xff,0x70,0x06 = vqshlu.s16 q8, q8, #0xf
+0xff,0xff,0x70,0x06 = vqshlu.s32 q8, q8, #0x1f
+0xff,0xff,0xf0,0x06 = vqshlu.s64 q8, q8, #0x3f
 0x41,0xef,0xb0,0x05 = vqrshl.s8 d16, d16, d17
 0x51,0xef,0xb0,0x05 = vqrshl.s16 d16, d16, d17
 0x61,0xef,0xb0,0x05 = vqrshl.s32 d16, d16, d17
@@ -56,20 +56,20 @@
 0x62,0xff,0xf0,0x05 = vqrshl.u32 q8, q8, q9
 0x72,0xff,0xf0,0x05 = vqrshl.u64 q8, q8, q9
 0xc8,0xef,0x30,0x09 = vqshrn.s16 d16, q8, #8
-0xd0,0xef,0x30,0x09 = vqshrn.s32 d16, q8, #16
-0xe0,0xef,0x30,0x09 = vqshrn.s64 d16, q8, #32
+0xd0,0xef,0x30,0x09 = vqshrn.s32 d16, q8, #0x10
+0xe0,0xef,0x30,0x09 = vqshrn.s64 d16, q8, #0x20
 0xc8,0xff,0x30,0x09 = vqshrn.u16 d16, q8, #8
-0xd0,0xff,0x30,0x09 = vqshrn.u32 d16, q8, #16
-0xe0,0xff,0x30,0x09 = vqshrn.u64 d16, q8, #32
+0xd0,0xff,0x30,0x09 = vqshrn.u32 d16, q8, #0x10
+0xe0,0xff,0x30,0x09 = vqshrn.u64 d16, q8, #0x20
 0xc8,0xff,0x30,0x08 = vqshrun.s16 d16, q8, #8
-0xd0,0xff,0x30,0x08 = vqshrun.s32 d16, q8, #16
-0xe0,0xff,0x30,0x08 = vqshrun.s64 d16, q8, #32
+0xd0,0xff,0x30,0x08 = vqshrun.s32 d16, q8, #0x10
+0xe0,0xff,0x30,0x08 = vqshrun.s64 d16, q8, #0x20
 0xc8,0xef,0x70,0x09 = vqrshrn.s16 d16, q8, #8
-0xd0,0xef,0x70,0x09 = vqrshrn.s32 d16, q8, #16
-0xe0,0xef,0x70,0x09 = vqrshrn.s64 d16, q8, #32
+0xd0,0xef,0x70,0x09 = vqrshrn.s32 d16, q8, #0x10
+0xe0,0xef,0x70,0x09 = vqrshrn.s64 d16, q8, #0x20
 0xc8,0xff,0x70,0x09 = vqrshrn.u16 d16, q8, #8
-0xd0,0xff,0x70,0x09 = vqrshrn.u32 d16, q8, #16
-0xe0,0xff,0x70,0x09 = vqrshrn.u64 d16, q8, #32
+0xd0,0xff,0x70,0x09 = vqrshrn.u32 d16, q8, #0x10
+0xe0,0xff,0x70,0x09 = vqrshrn.u64 d16, q8, #0x20
 0xc8,0xff,0x70,0x08 = vqrshrun.s16 d16, q8, #8
-0xd0,0xff,0x70,0x08 = vqrshrun.s32 d16, q8, #16
-0xe0,0xff,0x70,0x08 = vqrshrun.s64 d16, q8, #32
+0xd0,0xff,0x70,0x08 = vqrshrun.s32 d16, q8, #0x10
+0xe0,0xff,0x70,0x08 = vqrshrun.s64 d16, q8, #0x20
diff --git a/suite/MC/ARM/neont2-shift-encoding.s.cs b/suite/MC/ARM/neont2-shift-encoding.s.cs
index b86f7e964..ca49ff36b 100644
--- a/suite/MC/ARM/neont2-shift-encoding.s.cs
+++ b/suite/MC/ARM/neont2-shift-encoding.s.cs
@@ -4,45 +4,45 @@
 0x60,0xff,0xa1,0x04 = vshl.u32 d16, d17, d16
 0x70,0xff,0xa1,0x04 = vshl.u64 d16, d17, d16
 0xcf,0xef,0x30,0x05 = vshl.i8 d16, d16, #7
-0xdf,0xef,0x30,0x05 = vshl.i16 d16, d16, #15
-0xff,0xef,0x30,0x05 = vshl.i32 d16, d16, #31
-0xff,0xef,0xb0,0x05 = vshl.i64 d16, d16, #63
+0xdf,0xef,0x30,0x05 = vshl.i16 d16, d16, #0xf
+0xff,0xef,0x30,0x05 = vshl.i32 d16, d16, #0x1f
+0xff,0xef,0xb0,0x05 = vshl.i64 d16, d16, #0x3f
 0x40,0xff,0xe2,0x04 = vshl.u8 q8, q9, q8
 0x50,0xff,0xe2,0x04 = vshl.u16 q8, q9, q8
 0x60,0xff,0xe2,0x04 = vshl.u32 q8, q9, q8
 0x70,0xff,0xe2,0x04 = vshl.u64 q8, q9, q8
 0xcf,0xef,0x70,0x05 = vshl.i8 q8, q8, #7
-0xdf,0xef,0x70,0x05 = vshl.i16 q8, q8, #15
-0xff,0xef,0x70,0x05 = vshl.i32 q8, q8, #31
-0xff,0xef,0xf0,0x05 = vshl.i64 q8, q8, #63
+0xdf,0xef,0x70,0x05 = vshl.i16 q8, q8, #0xf
+0xff,0xef,0x70,0x05 = vshl.i32 q8, q8, #0x1f
+0xff,0xef,0xf0,0x05 = vshl.i64 q8, q8, #0x3f
 0xc8,0xff,0x30,0x00 = vshr.u8 d16, d16, #8
-0xd0,0xff,0x30,0x00 = vshr.u16 d16, d16, #16
-0xe0,0xff,0x30,0x00 = vshr.u32 d16, d16, #32
-0xc0,0xff,0xb0,0x00 = vshr.u64 d16, d16, #64
+0xd0,0xff,0x30,0x00 = vshr.u16 d16, d16, #0x10
+0xe0,0xff,0x30,0x00 = vshr.u32 d16, d16, #0x20
+0xc0,0xff,0xb0,0x00 = vshr.u64 d16, d16, #0x40
 0xc8,0xff,0x70,0x00 = vshr.u8 q8, q8, #8
-0xd0,0xff,0x70,0x00 = vshr.u16 q8, q8, #16
-0xe0,0xff,0x70,0x00 = vshr.u32 q8, q8, #32
-0xc0,0xff,0xf0,0x00 = vshr.u64 q8, q8, #64
+0xd0,0xff,0x70,0x00 = vshr.u16 q8, q8, #0x10
+0xe0,0xff,0x70,0x00 = vshr.u32 q8, q8, #0x20
+0xc0,0xff,0xf0,0x00 = vshr.u64 q8, q8, #0x40
 0xc8,0xef,0x30,0x00 = vshr.s8 d16, d16, #8
-0xd0,0xef,0x30,0x00 = vshr.s16 d16, d16, #16
-0xe0,0xef,0x30,0x00 = vshr.s32 d16, d16, #32
-0xc0,0xef,0xb0,0x00 = vshr.s64 d16, d16, #64
+0xd0,0xef,0x30,0x00 = vshr.s16 d16, d16, #0x10
+0xe0,0xef,0x30,0x00 = vshr.s32 d16, d16, #0x20
+0xc0,0xef,0xb0,0x00 = vshr.s64 d16, d16, #0x40
 0xc8,0xef,0x70,0x00 = vshr.s8 q8, q8, #8
-0xd0,0xef,0x70,0x00 = vshr.s16 q8, q8, #16
-0xe0,0xef,0x70,0x00 = vshr.s32 q8, q8, #32
-0xc0,0xef,0xf0,0x00 = vshr.s64 q8, q8, #64
+0xd0,0xef,0x70,0x00 = vshr.s16 q8, q8, #0x10
+0xe0,0xef,0x70,0x00 = vshr.s32 q8, q8, #0x20
+0xc0,0xef,0xf0,0x00 = vshr.s64 q8, q8, #0x40
 0xcf,0xef,0x30,0x0a = vshll.s8 q8, d16, #7
-0xdf,0xef,0x30,0x0a = vshll.s16 q8, d16, #15
-0xff,0xef,0x30,0x0a = vshll.s32 q8, d16, #31
+0xdf,0xef,0x30,0x0a = vshll.s16 q8, d16, #0xf
+0xff,0xef,0x30,0x0a = vshll.s32 q8, d16, #0x1f
 0xcf,0xff,0x30,0x0a = vshll.u8 q8, d16, #7
-0xdf,0xff,0x30,0x0a = vshll.u16 q8, d16, #15
-0xff,0xff,0x30,0x0a = vshll.u32 q8, d16, #31
+0xdf,0xff,0x30,0x0a = vshll.u16 q8, d16, #0xf
+0xff,0xff,0x30,0x0a = vshll.u32 q8, d16, #0x1f
 0xf2,0xff,0x20,0x03 = vshll.i8 q8, d16, #8
-0xf6,0xff,0x20,0x03 = vshll.i16 q8, d16, #16
-0xfa,0xff,0x20,0x03 = vshll.i32 q8, d16, #32
+0xf6,0xff,0x20,0x03 = vshll.i16 q8, d16, #0x10
+0xfa,0xff,0x20,0x03 = vshll.i32 q8, d16, #0x20
 0xc8,0xef,0x30,0x08 = vshrn.i16 d16, q8, #8
-0xd0,0xef,0x30,0x08 = vshrn.i32 d16, q8, #16
-0xe0,0xef,0x30,0x08 = vshrn.i64 d16, q8, #32
+0xd0,0xef,0x30,0x08 = vshrn.i32 d16, q8, #0x10
+0xe0,0xef,0x30,0x08 = vshrn.i64 d16, q8, #0x20
 0x40,0xef,0xa1,0x05 = vrshl.s8 d16, d17, d16
 0x50,0xef,0xa1,0x05 = vrshl.s16 d16, d17, d16
 0x60,0xef,0xa1,0x05 = vrshl.s32 d16, d17, d16
@@ -60,21 +60,21 @@
 0x60,0xff,0xe2,0x05 = vrshl.u32 q8, q9, q8
 0x70,0xff,0xe2,0x05 = vrshl.u64 q8, q9, q8
 0xc8,0xef,0x30,0x02 = vrshr.s8 d16, d16, #8
-0xd0,0xef,0x30,0x02 = vrshr.s16 d16, d16, #16
-0xe0,0xef,0x30,0x02 = vrshr.s32 d16, d16, #32
-0xc0,0xef,0xb0,0x02 = vrshr.s64 d16, d16, #64
+0xd0,0xef,0x30,0x02 = vrshr.s16 d16, d16, #0x10
+0xe0,0xef,0x30,0x02 = vrshr.s32 d16, d16, #0x20
+0xc0,0xef,0xb0,0x02 = vrshr.s64 d16, d16, #0x40
 0xc8,0xff,0x30,0x02 = vrshr.u8 d16, d16, #8
-0xd0,0xff,0x30,0x02 = vrshr.u16 d16, d16, #16
-0xe0,0xff,0x30,0x02 = vrshr.u32 d16, d16, #32
-0xc0,0xff,0xb0,0x02 = vrshr.u64 d16, d16, #64
+0xd0,0xff,0x30,0x02 = vrshr.u16 d16, d16, #0x10
+0xe0,0xff,0x30,0x02 = vrshr.u32 d16, d16, #0x20
+0xc0,0xff,0xb0,0x02 = vrshr.u64 d16, d16, #0x40
 0xc8,0xef,0x70,0x02 = vrshr.s8 q8, q8, #8
-0xd0,0xef,0x70,0x02 = vrshr.s16 q8, q8, #16
-0xe0,0xef,0x70,0x02 = vrshr.s32 q8, q8, #32
-0xc0,0xef,0xf0,0x02 = vrshr.s64 q8, q8, #64
+0xd0,0xef,0x70,0x02 = vrshr.s16 q8, q8, #0x10
+0xe0,0xef,0x70,0x02 = vrshr.s32 q8, q8, #0x20
+0xc0,0xef,0xf0,0x02 = vrshr.s64 q8, q8, #0x40
 0xc8,0xff,0x70,0x02 = vrshr.u8 q8, q8, #8
-0xd0,0xff,0x70,0x02 = vrshr.u16 q8, q8, #16
-0xe0,0xff,0x70,0x02 = vrshr.u32 q8, q8, #32
-0xc0,0xff,0xf0,0x02 = vrshr.u64 q8, q8, #64
+0xd0,0xff,0x70,0x02 = vrshr.u16 q8, q8, #0x10
+0xe0,0xff,0x70,0x02 = vrshr.u32 q8, q8, #0x20
+0xc0,0xff,0xf0,0x02 = vrshr.u64 q8, q8, #0x40
 0xc8,0xef,0x70,0x08 = vrshrn.i16 d16, q8, #8
-0xd0,0xef,0x70,0x08 = vrshrn.i32 d16, q8, #16
-0xe0,0xef,0x70,0x08 = vrshrn.i64 d16, q8, #32
+0xd0,0xef,0x70,0x08 = vrshrn.i32 d16, q8, #0x10
+0xe0,0xef,0x70,0x08 = vrshrn.i64 d16, q8, #0x20
diff --git a/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs b/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs
index b2383a975..fb300d904 100644
--- a/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs
+++ b/suite/MC/ARM/neont2-shiftaccum-encoding.s.cs
@@ -1,97 +1,97 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
 0xc8,0xef,0x30,0x11 = vsra.s8 d17, d16, #8
-0x90,0xef,0x1e,0xf1 = vsra.s16 d15, d14, #16
-0xa0,0xef,0x1c,0xd1 = vsra.s32 d13, d12, #32
-0x80,0xef,0x9a,0xb1 = vsra.s64 d11, d10, #64
+0x90,0xef,0x1e,0xf1 = vsra.s16 d15, d14, #0x10
+0xa0,0xef,0x1c,0xd1 = vsra.s32 d13, d12, #0x20
+0x80,0xef,0x9a,0xb1 = vsra.s64 d11, d10, #0x40
 0x88,0xef,0x54,0xe1 = vsra.s8 q7, q2, #8
-0x90,0xef,0x5c,0x61 = vsra.s16 q3, q6, #16
-0xe0,0xef,0x5a,0x21 = vsra.s32 q9, q5, #32
-0xc0,0xef,0xd8,0x01 = vsra.s64 q8, q4, #64
+0x90,0xef,0x5c,0x61 = vsra.s16 q3, q6, #0x10
+0xe0,0xef,0x5a,0x21 = vsra.s32 q9, q5, #0x20
+0xc0,0xef,0xd8,0x01 = vsra.s64 q8, q4, #0x40
 0xc8,0xff,0x30,0x11 = vsra.u8 d17, d16, #8
-0x95,0xff,0x1e,0xb1 = vsra.u16 d11, d14, #11
-0xaa,0xff,0x1f,0xc1 = vsra.u32 d12, d15, #22
-0x8a,0xff,0xb0,0xd1 = vsra.u64 d13, d16, #54
+0x95,0xff,0x1e,0xb1 = vsra.u16 d11, d14, #0xb
+0xaa,0xff,0x1f,0xc1 = vsra.u32 d12, d15, #0x16
+0x8a,0xff,0xb0,0xd1 = vsra.u64 d13, d16, #0x36
 0x88,0xff,0x5e,0x21 = vsra.u8 q1, q7, #8
 0x9a,0xff,0x5e,0x41 = vsra.u16 q2, q7, #6
-0xab,0xff,0x5c,0x61 = vsra.u32 q3, q6, #21
-0xa7,0xff,0xda,0x81 = vsra.u64 q4, q5, #25
+0xab,0xff,0x5c,0x61 = vsra.u32 q3, q6, #0x15
+0xa7,0xff,0xda,0x81 = vsra.u64 q4, q5, #0x19
 0xc8,0xef,0x30,0x01 = vsra.s8 d16, d16, #8
-0x90,0xef,0x1e,0xe1 = vsra.s16 d14, d14, #16
-0xa0,0xef,0x1c,0xc1 = vsra.s32 d12, d12, #32
-0x80,0xef,0x9a,0xa1 = vsra.s64 d10, d10, #64
+0x90,0xef,0x1e,0xe1 = vsra.s16 d14, d14, #0x10
+0xa0,0xef,0x1c,0xc1 = vsra.s32 d12, d12, #0x20
+0x80,0xef,0x9a,0xa1 = vsra.s64 d10, d10, #0x40
 0x88,0xef,0x54,0x41 = vsra.s8 q2, q2, #8
-0x90,0xef,0x5c,0xc1 = vsra.s16 q6, q6, #16
-0xa0,0xef,0x5a,0xa1 = vsra.s32 q5, q5, #32
-0x80,0xef,0xd8,0x81 = vsra.s64 q4, q4, #64
+0x90,0xef,0x5c,0xc1 = vsra.s16 q6, q6, #0x10
+0xa0,0xef,0x5a,0xa1 = vsra.s32 q5, q5, #0x20
+0x80,0xef,0xd8,0x81 = vsra.s64 q4, q4, #0x40
 0xc8,0xff,0x30,0x01 = vsra.u8 d16, d16, #8
-0x95,0xff,0x1e,0xe1 = vsra.u16 d14, d14, #11
-0xaa,0xff,0x1f,0xf1 = vsra.u32 d15, d15, #22
-0xca,0xff,0xb0,0x01 = vsra.u64 d16, d16, #54
+0x95,0xff,0x1e,0xe1 = vsra.u16 d14, d14, #0xb
+0xaa,0xff,0x1f,0xf1 = vsra.u32 d15, d15, #0x16
+0xca,0xff,0xb0,0x01 = vsra.u64 d16, d16, #0x36
 0x88,0xff,0x5e,0xe1 = vsra.u8 q7, q7, #8
 0x9a,0xff,0x5e,0xe1 = vsra.u16 q7, q7, #6
-0xab,0xff,0x5c,0xc1 = vsra.u32 q6, q6, #21
-0xa7,0xff,0xda,0xa1 = vsra.u64 q5, q5, #25
+0xab,0xff,0x5c,0xc1 = vsra.u32 q6, q6, #0x15
+0xa7,0xff,0xda,0xa1 = vsra.u64 q5, q5, #0x19
 0x88,0xef,0x3a,0x53 = vrsra.s8 d5, d26, #8
-0x90,0xef,0x39,0x63 = vrsra.s16 d6, d25, #16
-0xa0,0xef,0x38,0x73 = vrsra.s32 d7, d24, #32
-0x80,0xef,0xb7,0xe3 = vrsra.s64 d14, d23, #64
+0x90,0xef,0x39,0x63 = vrsra.s16 d6, d25, #0x10
+0xa0,0xef,0x38,0x73 = vrsra.s32 d7, d24, #0x20
+0x80,0xef,0xb7,0xe3 = vrsra.s64 d14, d23, #0x40
 0x88,0xff,0x36,0xf3 = vrsra.u8 d15, d22, #8
-0xd0,0xff,0x35,0x03 = vrsra.u16 d16, d21, #16
-0xe0,0xff,0x34,0x13 = vrsra.u32 d17, d20, #32
-0xc0,0xff,0xb3,0x23 = vrsra.u64 d18, d19, #64
+0xd0,0xff,0x35,0x03 = vrsra.u16 d16, d21, #0x10
+0xe0,0xff,0x34,0x13 = vrsra.u32 d17, d20, #0x20
+0xc0,0xff,0xb3,0x23 = vrsra.u64 d18, d19, #0x40
 0x88,0xef,0x54,0x23 = vrsra.s8 q1, q2, #8
-0x90,0xef,0x56,0x43 = vrsra.s16 q2, q3, #16
-0xa0,0xef,0x58,0x63 = vrsra.s32 q3, q4, #32
-0x80,0xef,0xda,0x83 = vrsra.s64 q4, q5, #64
+0x90,0xef,0x56,0x43 = vrsra.s16 q2, q3, #0x10
+0xa0,0xef,0x58,0x63 = vrsra.s32 q3, q4, #0x20
+0x80,0xef,0xda,0x83 = vrsra.s64 q4, q5, #0x40
 0x88,0xff,0x5c,0xa3 = vrsra.u8 q5, q6, #8
-0x90,0xff,0x5e,0xc3 = vrsra.u16 q6, q7, #16
-0xa0,0xff,0x70,0xe3 = vrsra.u32 q7, q8, #32
-0xc0,0xff,0xf2,0x03 = vrsra.u64 q8, q9, #64
+0x90,0xff,0x5e,0xc3 = vrsra.u16 q6, q7, #0x10
+0xa0,0xff,0x70,0xe3 = vrsra.u32 q7, q8, #0x20
+0xc0,0xff,0xf2,0x03 = vrsra.u64 q8, q9, #0x40
 0xc8,0xef,0x3a,0xa3 = vrsra.s8 d26, d26, #8
-0xd0,0xef,0x39,0x93 = vrsra.s16 d25, d25, #16
-0xe0,0xef,0x38,0x83 = vrsra.s32 d24, d24, #32
-0xc0,0xef,0xb7,0x73 = vrsra.s64 d23, d23, #64
+0xd0,0xef,0x39,0x93 = vrsra.s16 d25, d25, #0x10
+0xe0,0xef,0x38,0x83 = vrsra.s32 d24, d24, #0x20
+0xc0,0xef,0xb7,0x73 = vrsra.s64 d23, d23, #0x40
 0xc8,0xff,0x36,0x63 = vrsra.u8 d22, d22, #8
-0xd0,0xff,0x35,0x53 = vrsra.u16 d21, d21, #16
-0xe0,0xff,0x34,0x43 = vrsra.u32 d20, d20, #32
-0xc0,0xff,0xb3,0x33 = vrsra.u64 d19, d19, #64
+0xd0,0xff,0x35,0x53 = vrsra.u16 d21, d21, #0x10
+0xe0,0xff,0x34,0x43 = vrsra.u32 d20, d20, #0x20
+0xc0,0xff,0xb3,0x33 = vrsra.u64 d19, d19, #0x40
 0x88,0xef,0x54,0x43 = vrsra.s8 q2, q2, #8
-0x90,0xef,0x56,0x63 = vrsra.s16 q3, q3, #16
-0xa0,0xef,0x58,0x83 = vrsra.s32 q4, q4, #32
-0x80,0xef,0xda,0xa3 = vrsra.s64 q5, q5, #64
+0x90,0xef,0x56,0x63 = vrsra.s16 q3, q3, #0x10
+0xa0,0xef,0x58,0x83 = vrsra.s32 q4, q4, #0x20
+0x80,0xef,0xda,0xa3 = vrsra.s64 q5, q5, #0x40
 0x88,0xff,0x5c,0xc3 = vrsra.u8 q6, q6, #8
-0x90,0xff,0x5e,0xe3 = vrsra.u16 q7, q7, #16
-0xe0,0xff,0x70,0x03 = vrsra.u32 q8, q8, #32
-0xc0,0xff,0xf2,0x23 = vrsra.u64 q9, q9, #64
+0x90,0xff,0x5e,0xe3 = vrsra.u16 q7, q7, #0x10
+0xe0,0xff,0x70,0x03 = vrsra.u32 q8, q8, #0x20
+0xc0,0xff,0xf2,0x23 = vrsra.u64 q9, q9, #0x40
 0x8f,0xff,0x1c,0xb5 = vsli.8 d11, d12, #7
-0x9f,0xff,0x1d,0xc5 = vsli.16 d12, d13, #15
-0xbf,0xff,0x1e,0xd5 = vsli.32 d13, d14, #31
-0xbf,0xff,0x9f,0xe5 = vsli.64 d14, d15, #63
+0x9f,0xff,0x1d,0xc5 = vsli.16 d12, d13, #0xf
+0xbf,0xff,0x1e,0xd5 = vsli.32 d13, d14, #0x1f
+0xbf,0xff,0x9f,0xe5 = vsli.64 d14, d15, #0x3f
 0x8f,0xff,0x70,0x25 = vsli.8 q1, q8, #7
-0x9f,0xff,0x5e,0x45 = vsli.16 q2, q7, #15
-0xbf,0xff,0x58,0x65 = vsli.32 q3, q4, #31
-0xbf,0xff,0xda,0x85 = vsli.64 q4, q5, #63
+0x9f,0xff,0x5e,0x45 = vsli.16 q2, q7, #0xf
+0xbf,0xff,0x58,0x65 = vsli.32 q3, q4, #0x1f
+0xbf,0xff,0xda,0x85 = vsli.64 q4, q5, #0x3f
 0xc8,0xff,0x1b,0xc4 = vsri.8 d28, d11, #8
-0xd0,0xff,0x1c,0xa4 = vsri.16 d26, d12, #16
-0xe0,0xff,0x1d,0x84 = vsri.32 d24, d13, #32
-0xc0,0xff,0x9e,0x54 = vsri.64 d21, d14, #64
+0xd0,0xff,0x1c,0xa4 = vsri.16 d26, d12, #0x10
+0xe0,0xff,0x1d,0x84 = vsri.32 d24, d13, #0x20
+0xc0,0xff,0x9e,0x54 = vsri.64 d21, d14, #0x40
 0x88,0xff,0x70,0x24 = vsri.8 q1, q8, #8
-0x90,0xff,0x54,0xa4 = vsri.16 q5, q2, #16
-0xa0,0xff,0x58,0xe4 = vsri.32 q7, q4, #32
-0xc0,0xff,0xdc,0x24 = vsri.64 q9, q6, #64
+0x90,0xff,0x54,0xa4 = vsri.16 q5, q2, #0x10
+0xa0,0xff,0x58,0xe4 = vsri.32 q7, q4, #0x20
+0xc0,0xff,0xdc,0x24 = vsri.64 q9, q6, #0x40
 0x8f,0xff,0x1c,0xc5 = vsli.8 d12, d12, #7
-0x9f,0xff,0x1d,0xd5 = vsli.16 d13, d13, #15
-0xbf,0xff,0x1e,0xe5 = vsli.32 d14, d14, #31
-0xbf,0xff,0x9f,0xf5 = vsli.64 d15, d15, #63
+0x9f,0xff,0x1d,0xd5 = vsli.16 d13, d13, #0xf
+0xbf,0xff,0x1e,0xe5 = vsli.32 d14, d14, #0x1f
+0xbf,0xff,0x9f,0xf5 = vsli.64 d15, d15, #0x3f
 0xcf,0xff,0x70,0x05 = vsli.8 q8, q8, #7
-0x9f,0xff,0x5e,0xe5 = vsli.16 q7, q7, #15
-0xbf,0xff,0x58,0x85 = vsli.32 q4, q4, #31
-0xbf,0xff,0xda,0xa5 = vsli.64 q5, q5, #63
+0x9f,0xff,0x5e,0xe5 = vsli.16 q7, q7, #0xf
+0xbf,0xff,0x58,0x85 = vsli.32 q4, q4, #0x1f
+0xbf,0xff,0xda,0xa5 = vsli.64 q5, q5, #0x3f
 0x88,0xff,0x1b,0xb4 = vsri.8 d11, d11, #8
-0x90,0xff,0x1c,0xc4 = vsri.16 d12, d12, #16
-0xa0,0xff,0x1d,0xd4 = vsri.32 d13, d13, #32
-0x80,0xff,0x9e,0xe4 = vsri.64 d14, d14, #64
+0x90,0xff,0x1c,0xc4 = vsri.16 d12, d12, #0x10
+0xa0,0xff,0x1d,0xd4 = vsri.32 d13, d13, #0x20
+0x80,0xff,0x9e,0xe4 = vsri.64 d14, d14, #0x40
 0xc8,0xff,0x70,0x04 = vsri.8 q8, q8, #8
-0x90,0xff,0x54,0x44 = vsri.16 q2, q2, #16
-0xa0,0xff,0x58,0x84 = vsri.32 q4, q4, #32
-0x80,0xff,0xdc,0xc4 = vsri.64 q6, q6, #64
+0x90,0xff,0x54,0x44 = vsri.16 q2, q2, #0x10
+0xa0,0xff,0x58,0x84 = vsri.32 q4, q4, #0x20
+0x80,0xff,0xdc,0xc4 = vsri.64 q6, q6, #0x40
diff --git a/suite/MC/ARM/simple-fp-encoding.s.cs b/suite/MC/ARM/simple-fp-encoding.s.cs
index 9ce0f492d..c8ec7702a 100644
--- a/suite/MC/ARM/simple-fp-encoding.s.cs
+++ b/suite/MC/ARM/simple-fp-encoding.s.cs
@@ -1,23 +1,49 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
+0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
 0x80,0x0a,0x30,0xee = vadd.f32 s0, s1, s0
+0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16
 0xc0,0x0a,0x30,0xee = vsub.f32 s0, s1, s0
+0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16
 0x80,0x0a,0x80,0xee = vdiv.f32 s0, s1, s0
 0xa3,0x2a,0xc2,0xee = vdiv.f32 s5, s5, s7
+0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7
+0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16
+0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17
 0x80,0x0a,0x20,0xee = vmul.f32 s0, s1, s0
 0xaa,0x5a,0x65,0xee = vmul.f32 s11, s11, s21
+0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16
 0xc0,0x0a,0x20,0xee = vnmul.f32 s0, s1, s0
+0x60,0x1b,0xf4,0xee = vcmp.f64 d17, d16
+0x40,0x0a,0xf4,0xee = vcmp.f32 s1, s0
+0x40,0x1b,0xf5,0xee = vcmp.f64 d17, #0
+0x40,0x0a,0xf5,0xee = vcmp.f32 s1, #0
+0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16
 0xc0,0x0a,0xf4,0xee = vcmpe.f32 s1, s0
+0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0
 0xc0,0x0a,0xb5,0xee = vcmpe.f32 s0, #0
+0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16
 0xc0,0x0a,0xb0,0xee = vabs.f32 s0, s0
+0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16
+0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0
+0x60,0x0b,0xf1,0xee = vneg.f64 d16, d16
 0x40,0x0a,0xb1,0xee = vneg.f32 s0, s0
+0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16
 0xc0,0x0a,0xb1,0xee = vsqrt.f32 s0, s0
+0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0
 0xc0,0x0a,0xb8,0xee = vcvt.f32.s32 s0, s0
+0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0
 0x40,0x0a,0xb8,0xee = vcvt.f32.u32 s0, s0
+0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16
 0xc0,0x0a,0xbd,0xee = vcvt.s32.f32 s0, s0
+0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16
 0xc0,0x0a,0xbc,0xee = vcvt.u32.f32 s0, s0
+0xa1,0x0b,0x42,0xee = vmla.f64 d16, d18, d17
 0x00,0x0a,0x41,0xee = vmla.f32 s1, s2, s0
+0xe1,0x0b,0x42,0xee = vmls.f64 d16, d18, d17
 0x40,0x0a,0x41,0xee = vmls.f32 s1, s2, s0
+0xe1,0x0b,0x52,0xee = vnmla.f64 d16, d18, d17
 0x40,0x0a,0x51,0xee = vnmla.f32 s1, s2, s0
+0xa1,0x0b,0x52,0xee = vnmls.f64 d16, d18, d17
 0x00,0x0a,0x51,0xee = vnmls.f32 s1, s2, s0
 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
 0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
@@ -26,6 +52,7 @@
 0x10,0x3a,0xf0,0xee = vmrs r3, fpsid
 0x10,0x4a,0xf7,0xee = vmrs r4, mvfr0
 0x10,0x5a,0xf6,0xee = vmrs r5, mvfr1
+0x60,0x0b,0xf1,0x1e = vnegne.f64 d16, d16
 0x10,0x0a,0x00,0x1e = vmovne s0, r0
 0x10,0x1a,0x00,0x0e = vmoveq s0, r1
 0x10,0x1a,0x11,0xee = vmov r1, s2
@@ -42,7 +69,9 @@
 0x10,0x0a,0xe0,0xee = vmsr fpsid, r0
 0x10,0x3a,0xe9,0xee = vmsr fpinst, r3
 0x10,0x4a,0xea,0xee = vmsr fpinst2, r4
+0x08,0x0b,0xf0,0xee = vmov.f64 d16, #3.000000e+00
 0x08,0x0a,0xb0,0xee = vmov.f32 s0, #3.000000e+00
+0x08,0x0b,0xf8,0xee = vmov.f64 d16, #-3.000000e+00
 0x08,0x0a,0xb8,0xee = vmov.f32 s0, #-3.000000e+00
 0x10,0x0a,0x00,0xee = vmov s0, r0
 0x90,0x1a,0x00,0xee = vmov s1, r1
@@ -64,27 +93,27 @@
 0x00,0x1b,0xd0,0xed = vldr d17, [r0]
 0x00,0x0a,0x9e,0xed = vldr s0, [lr]
 0x00,0x0b,0x9e,0xed = vldr d0, [lr]
-0x08,0x1b,0x92,0xed = vldr d1, [r2, #32]
-0x08,0x1b,0x12,0xed = vldr d1, [r2, #-32]
+0x08,0x1b,0x92,0xed = vldr d1, [r2, #0x20]
+0x08,0x1b,0x12,0xed = vldr d1, [r2, #-0x20]
 0x00,0x2b,0x93,0xed = vldr d2, [r3]
 0x00,0x3b,0x9f,0xed = vldr d3, [pc]
 0x00,0x3b,0x9f,0xed = vldr d3, [pc]
 0x00,0x3b,0x1f,0xed = vldr d3, [pc, #-0]
 0x00,0x6a,0xd0,0xed = vldr s13, [r0]
-0x08,0x0a,0xd2,0xed = vldr s1, [r2, #32]
-0x08,0x0a,0x52,0xed = vldr s1, [r2, #-32]
+0x08,0x0a,0xd2,0xed = vldr s1, [r2, #0x20]
+0x08,0x0a,0x52,0xed = vldr s1, [r2, #-0x20]
 0x00,0x1a,0x93,0xed = vldr s2, [r3]
 0x00,0x2a,0xdf,0xed = vldr s5, [pc]
 0x00,0x2a,0xdf,0xed = vldr s5, [pc]
 0x00,0x2a,0x5f,0xed = vldr s5, [pc, #-0]
 0x00,0x4b,0x81,0xed = vstr d4, [r1]
-0x06,0x4b,0x81,0xed = vstr d4, [r1, #24]
-0x06,0x4b,0x01,0xed = vstr d4, [r1, #-24]
+0x06,0x4b,0x81,0xed = vstr d4, [r1, #0x18]
+0x06,0x4b,0x01,0xed = vstr d4, [r1, #-0x18]
 0x00,0x0a,0x8e,0xed = vstr s0, [lr]
 0x00,0x0b,0x8e,0xed = vstr d0, [lr]
 0x00,0x2a,0x81,0xed = vstr s4, [r1]
-0x06,0x2a,0x81,0xed = vstr s4, [r1, #24]
-0x06,0x2a,0x01,0xed = vstr s4, [r1, #-24]
+0x06,0x2a,0x81,0xed = vstr s4, [r1, #0x18]
+0x06,0x2a,0x01,0xed = vstr s4, [r1, #-0x18]
 0x0c,0x2b,0x91,0xec = vldmia r1, {d2, d3, d4, d5, d6, d7}
 0x06,0x1a,0x91,0xec = vldmia r1, {s2, s3, s4, s5, s6, s7}
 0x0c,0x2b,0x81,0xec = vstmia r1, {d2, d3, d4, d5, d6, d7}
@@ -96,7 +125,9 @@
 0x11,0x0b,0xa5,0xec = fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7}
 0x05,0x8b,0x84,0x0c = fstmiaxeq r4, {d8, d9}
 0x07,0x2b,0x27,0x1d = fstmdbxne r7!, {d2, d3, d4}
+0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0
 0x60,0x0a,0xbd,0xee = vcvtr.s32.f32 s0, s1
+0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0
 0x60,0x0a,0xbc,0xee = vcvtr.u32.f32 s0, s1
 0x90,0x8a,0x00,0xee = vmov s1, r8
 0x10,0x4a,0x01,0xee = vmov s2, r4
@@ -110,13 +141,37 @@
 0x90,0x4a,0x10,0xee = vmov r4, s1
 0x10,0x5a,0x11,0xee = vmov r5, s2
 0x90,0x6a,0x11,0xee = vmov r6, s3
-0xc6,0x0a,0xbb,0xee = vcvt.f32.u32 s0, s0, #20
+0xc6,0x0a,0xbb,0xee = vcvt.f32.u32 s0, s0, #0x14
+0xc0,0x0b,0xba,0xee = vcvt.f64.s32 d0, d0, #0x20
 0x67,0x0a,0xbb,0xee = vcvt.f32.u16 s0, s0, #1
-0xc6,0x0a,0xfa,0xee = vcvt.f32.s32 s1, s1, #20
+0x40,0x0b,0xba,0xee = vcvt.f64.s16 d0, d0, #0x10
+0xc6,0x0a,0xfa,0xee = vcvt.f32.s32 s1, s1, #0x14
+0xc0,0x4b,0xfb,0xee = vcvt.f64.u32 d20, d20, #0x20
 0x67,0x8a,0xfa,0xee = vcvt.f32.s16 s17, s17, #1
-0xc6,0x6a,0xbf,0xee = vcvt.u32.f32 s12, s12, #20
+0x40,0x7b,0xfb,0xee = vcvt.f64.u16 d23, d23, #0x10
+0xc6,0x6a,0xbf,0xee = vcvt.u32.f32 s12, s12, #0x14
+0xc0,0x2b,0xbe,0xee = vcvt.s32.f64 d2, d2, #0x20
 0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1
-0xc6,0x0a,0xfe,0xee = vcvt.s32.f32 s1, s1, #20
+0x40,0xfb,0xbe,0xee = vcvt.s16.f64 d15, d15, #0x10
+0xc6,0x0a,0xfe,0xee = vcvt.s32.f32 s1, s1, #0x14
+0xc0,0x4b,0xff,0xee = vcvt.u32.f64 d20, d20, #0x20
 0x67,0x8a,0xfe,0xee = vcvt.s16.f32 s17, s17, #1
+0x40,0x7b,0xff,0xee = vcvt.u16.f64 d23, d23, #0x10
 0x10,0x40,0x80,0xf2 = vmov.i32 d4, #0x0
 0x12,0x46,0x84,0xf2 = vmov.i32 d4, #0x42000000
+0x00,0x2a,0xf7,0xee = vmov.f32 s5, #1.000000e+00
+0x00,0x2a,0xf4,0xee = vmov.f32 s5, #1.250000e-01
+0x0e,0x2a,0xff,0xee = vmov.f32 s5, #-1.875000e+00
+0x03,0x2a,0xfe,0xee = vmov.f32 s5, #-5.937500e-01
+0x00,0x6b,0xb7,0xee = vmov.f64 d6, #1.000000e+00
+0x00,0x6b,0xb4,0xee = vmov.f64 d6, #1.250000e-01
+0x0e,0x6b,0xbf,0xee = vmov.f64 d6, #-1.875000e+00
+0x03,0x6b,0xbe,0xee = vmov.f64 d6, #-5.937500e-01
+0x10,0x7f,0x87,0xf2 = vmov.f32 d7, #1.000000e+00
+0x10,0x7f,0x84,0xf2 = vmov.f32 d7, #1.250000e-01
+0x1e,0x7f,0x87,0xf3 = vmov.f32 d7, #-1.875000e+00
+0x13,0x7f,0x86,0xf3 = vmov.f32 d7, #-5.937500e-01
+0x50,0x0f,0xc7,0xf2 = vmov.f32 q8, #1.000000e+00
+0x50,0x0f,0xc4,0xf2 = vmov.f32 q8, #1.250000e-01
+0x5e,0x0f,0xc7,0xf3 = vmov.f32 q8, #-1.875000e+00
+0x53,0x0f,0xc6,0xf3 = vmov.f32 q8, #-5.937500e-01
diff --git a/suite/MC/ARM/thumb-add-sub-width.s.cs b/suite/MC/ARM/thumb-add-sub-width.s.cs
new file mode 100644
index 000000000..e18f3f2ef
--- /dev/null
+++ b/suite/MC/ARM/thumb-add-sub-width.s.cs
@@ -0,0 +1,25 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x08,0x44 = add r0, r1
+0x08,0x44 = add r0, r1
+0x40,0x18 = adds r0, r0, r1
+0x40,0x18 = adds r0, r0, r1
+0x08,0x44 = add r0, r1
+0x08,0x44 = add r0, r1
+0x40,0x18 = adds r0, r0, r1
+0x40,0x18 = adds r0, r0, r1
+0x01,0xbf = itttt eq
+0x40,0x18 = addeq r0, r0, r1
+0x08,0x44 = addeq r0, r1
+0x10,0xeb,0x01,0x00 = addseq.w r0, r0, r1
+0x10,0xeb,0x01,0x00 = addseq.w r0, r0, r1
+0x40,0x1a = subs r0, r0, r1
+0x40,0x1a = subs r0, r0, r1
+0xa0,0xeb,0x01,0x00 = sub.w r0, r0, r1
+0xa0,0xeb,0x01,0x00 = sub.w r0, r0, r1
+0x40,0x1a = subs r0, r0, r1
+0x40,0x1a = subs r0, r0, r1
+0x01,0xbf = itttt eq
+0x40,0x1a = subeq r0, r0, r1
+0x40,0x1a = subeq r0, r0, r1
+0xb0,0xeb,0x01,0x00 = subseq.w r0, r0, r1
+0xb0,0xeb,0x01,0x00 = subseq.w r0, r0, r1
diff --git a/suite/MC/ARM/thumb-fp-armv8.s.cs b/suite/MC/ARM/thumb-fp-armv8.s.cs
index fc7c412f3..07cccfdfe 100644
--- a/suite/MC/ARM/thumb-fp-armv8.s.cs
+++ b/suite/MC/ARM/thumb-fp-armv8.s.cs
@@ -1,12 +1,8 @@
 # CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
-// 0xb2,0xee,0xe0,0x3b = vcvtt.f64.f16 d3, s1
-// 0xf3,0xee,0xcc,0x2b = vcvtt.f16.f64 s5, d12
-// 0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1
-// 0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1
-// 0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1
-// 0xf3,0xee,0xcc,0x2b = vcvttgt.f16.f64 s5, d12
-// 0xb2,0xee,0x60,0x3b = vcvtbeq.f64.f16 d3, s1
-// 0xb3,0xee,0x41,0x2b = vcvtblt.f16.f64 s4, d1
+0xb2,0xee,0xe0,0x3b = vcvtt.f64.f16 d3, s1
+0xf3,0xee,0xcc,0x2b = vcvtt.f16.f64 s5, d12
+0xb2,0xee,0x60,0x3b = vcvtb.f64.f16 d3, s1
+0xb3,0xee,0x41,0x2b = vcvtb.f16.f64 s4, d1
 0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3
 0xbc,0xfe,0xc3,0x1b = vcvta.s32.f64 s2, d3
 0xbd,0xfe,0xeb,0x3a = vcvtn.s32.f32 s6, s23
@@ -35,12 +31,8 @@
 0x86,0xfe,0xae,0x5b = vmaxnm.f64 d5, d22, d30
 0x80,0xfe,0x46,0x0a = vminnm.f32 s0, s0, s12
 0x86,0xfe,0x49,0x4b = vminnm.f64 d4, d6, d9
-// 0xb6,0xee,0xcc,0x3b = vrintzge.f64 d3, d12
 0xf6,0xee,0xcc,0x1a = vrintz.f32 s3, s24
-// 0xb6,0xee,0x40,0x5b = vrintrlt.f64 d5, d0
 0xb6,0xee,0x64,0x0a = vrintr.f32 s0, s9
-// 0xf7,0xee,0x6e,0xcb = vrintxeq.f64 d28, d30
-// 0xb7,0xee,0x47,0x5a = vrintxvs.f32 s10, s14
 0xb8,0xfe,0x44,0x3b = vrinta.f64 d3, d4
 0xb8,0xfe,0x60,0x6a = vrinta.f32 s12, s1
 0xb9,0xfe,0x44,0x3b = vrintn.f64 d3, d4
diff --git a/suite/MC/ARM/thumb-hints.s.cs b/suite/MC/ARM/thumb-hints.s.cs
index ea9fd56c5..1885ec71b 100644
--- a/suite/MC/ARM/thumb-hints.s.cs
+++ b/suite/MC/ARM/thumb-hints.s.cs
@@ -1,9 +1,9 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
-0x00,0xbf = nop 
-0x10,0xbf = yield 
-0x20,0xbf = wfe 
-0x30,0xbf = wfi 
-0x40,0xbf = sev 
+0x00,0xbf = nop
+0x10,0xbf = yield
+0x20,0xbf = wfe
+0x30,0xbf = wfi
+0x40,0xbf = sev
 0xbf,0xf3,0x5f,0x8f = dmb sy
 0xbf,0xf3,0x5f,0x8f = dmb sy
 0xbf,0xf3,0x4f,0x8f = dsb sy
diff --git a/suite/MC/ARM/thumb-mov.s.cs b/suite/MC/ARM/thumb-mov.s.cs
new file mode 100644
index 000000000..f4ccba5b2
--- /dev/null
+++ b/suite/MC/ARM/thumb-mov.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x85,0x46 = mov sp, r0
+0x68,0x46 = mov r0, sp
+0xed,0x46 = mov sp, sp
+0x87,0x46 = mov pc, r0
+0x78,0x46 = mov r0, pc
+0xff,0x46 = mov pc, pc
+0x4f,0xea,0x00,0x0d = mov.w sp, r0
+0x4f,0xea,0x0d,0x00 = mov.w r0, sp
diff --git a/suite/MC/ARM/thumb-shift-encoding.s.cs b/suite/MC/ARM/thumb-shift-encoding.s.cs
index 78efe20e7..a177c87a6 100644
--- a/suite/MC/ARM/thumb-shift-encoding.s.cs
+++ b/suite/MC/ARM/thumb-shift-encoding.s.cs
@@ -1,19 +1,19 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
-0x6e,0xeb,0x00,0x0c = sbc.w ip, lr, r0
-0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #32
-0x67,0xeb,0x1f,0x42 = sbc.w r2, r7, pc, lsr #16
+0x6e,0xeb,0x00,0x0c = sbc.w r12, lr, r0
+0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #0x20
+0x67,0xeb,0x1a,0x42 = sbc.w r2, r7, r10, lsr #0x10
 0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10
-0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #16
-0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #32
-0x63,0xeb,0x2d,0x46 = sbc.w r6, r3, sp, asr #16
+0x65,0xeb,0x0e,0x44 = sbc.w r4, r5, lr, lsl #0x10
+0x64,0xeb,0x2b,0x05 = sbc.w r5, r4, r11, asr #0x20
+0x63,0xeb,0x2c,0x46 = sbc.w r6, r3, r12, asr #0x10
 0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx
-0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #16
-0x0e,0xea,0x00,0x0c = and.w ip, lr, r0
-0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #32
-0x07,0xea,0x1f,0x42 = and.w r2, r7, pc, lsr #16
+0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #0x10
+0x0e,0xea,0x00,0x0c = and.w r12, lr, r0
+0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #0x20
+0x07,0xea,0x1a,0x42 = and.w r2, r7, r10, lsr #0x10
 0x06,0xea,0x0a,0x03 = and.w r3, r6, r10
-0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #16
-0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #32
-0x03,0xea,0x2d,0x46 = and.w r6, r3, sp, asr #16
+0x05,0xea,0x0e,0x44 = and.w r4, r5, lr, lsl #0x10
+0x04,0xea,0x2b,0x05 = and.w r5, r4, r11, asr #0x20
+0x03,0xea,0x2c,0x46 = and.w r6, r3, r12, asr #0x10
 0x02,0xea,0x3c,0x07 = and.w r7, r2, r12, rrx
-0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #16
+0x01,0xea,0x30,0x48 = and.w r8, r1, r0, ror #0x10
diff --git a/suite/MC/ARM/thumb.s.cs b/suite/MC/ARM/thumb.s.cs
index 6d5bcbbb8..6a83a0916 100644
--- a/suite/MC/ARM/thumb.s.cs
+++ b/suite/MC/ARM/thumb.s.cs
@@ -1,7 +1,7 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
 0x91,0x42 = cmp r1, r2
 0x16,0xbc = pop {r1, r2, r4}
-0xfe,0xde = trap 
+0xfe,0xde = trap
 0xc8,0x47 = blx r9
 0xd0,0x47 = blx r10
 0x1a,0xba = rev r2, r3
diff --git a/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs b/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs
index 6927f57cb..7e936f8fd 100644
--- a/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs
+++ b/suite/MC/ARM/thumb2-b.w-encodingT4.s.cs
@@ -1,2 +1,2 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
-0x36,0xf0,0x06,0xbc = b.w #223248
+0x36,0xf0,0x06,0xbc = b.w #0x3680c
diff --git a/suite/MC/ARM/thumb2-branches.s.cs b/suite/MC/ARM/thumb2-branches.s.cs
index 98a729237..dbdfb917f 100644
--- a/suite/MC/ARM/thumb2-branches.s.cs
+++ b/suite/MC/ARM/thumb2-branches.s.cs
@@ -1,82 +1,93 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
-// 0xff,0xf7,0x00,0xbc = b.w #-2044
-// 0x00,0xf0,0xff,0xbb = b.w #2050
-// 0x66,0xf6,0x30,0xbc = b.w #-1677212
-// 0x99,0xf1,0xcf,0xbb = b.w #1677218
-// 0x00,0xe4 = b #-2044
-0xff,0xe3 = b #2050
-0xff,0xf7,0xff,0xbb = b.w #-2046
-0x00,0xf0,0x00,0xbc = b.w #2052
-// 0x66,0xf6,0x30,0xbc = b.w #-1677212
-// 0x99,0xf1,0xcf,0xbb = b.w #1677218
+0x00,0xe4 = b #-0x800
+0xff,0xe3 = b #0x7fe
+0xff,0xf7,0x00,0xbc = b.w #-0x800
+0x00,0xf0,0xff,0xbb = b.w #0x7fe
+0x66,0xf6,0x30,0xbc = b.w #-0x1997a0
+0x99,0xf1,0xcf,0xbb = b.w #0x19979e
+0x00,0xe4 = b #-0x800
+0xff,0xe3 = b #0x7fe
+0xff,0xf7,0xff,0xbb = b.w #-0x802
+0x00,0xf0,0x00,0xbc = b.w #0x800
+0x66,0xf6,0x30,0xbc = b.w #-0x1997a0
+0x99,0xf1,0xcf,0xbb = b.w #0x19979e
 0x08,0xbf = it eq
-// 0x00,0xe4 = beq #-2044
+0x00,0xe4 = beq #-0x800
 0x18,0xbf = it ne
-// 0x01,0xe4 = bne #-2042
+0x01,0xe4 = bne #-0x7fe
 0xc8,0xbf = it gt
-// 0xff,0xf7,0x00,0xbc = bgt.w #-2044
+0xff,0xf7,0x00,0xbc = bgt.w #-0x800
 0xd8,0xbf = it le
-// 0x00,0xf0,0xff,0xbb = ble.w #2050
+0x00,0xf0,0xff,0xbb = ble.w #0x7fe
 0xa8,0xbf = it ge
-// 0x66,0xf6,0x30,0xbc = bge.w #-1677212
+0x66,0xf6,0x30,0xbc = bge.w #-0x1997a0
 0xb8,0xbf = it lt
-// 0x99,0xf1,0xcf,0xbb = blt.w #1677218
-0x80,0xd0 = beq #-252
-0x7f,0xd1 = bne #258
-0x3f,0xf5,0x80,0xaf = bmi.w #-252
-0x40,0xf0,0x7f,0x80 = bne.w #258
-0xc0,0xf6,0x00,0x80 = blt.w #-1048572
-0xbf,0xf2,0xff,0xaf = bge.w #1048578
-0x80,0xd1 = bne #-252
-0x7f,0xdc = bgt #258
-0x7f,0xf4,0x7f,0xaf = bne.w #-254
-0x00,0xf3,0x80,0x80 = bgt.w #260
-0x40,0xf4,0x00,0x80 = bne.w #-1048572
-0x3f,0xf3,0xff,0xaf = bgt.w #1048578
-0x08,0xbf = it eq
-// 0x08,0x44 = addeq r0, r1
-0x40,0xd1 = bne #132
-0x0c,0xbf = ite eq
-// 0x08,0x44 = addeq r0, r1
-// 0x40,0xe0 = bne #132
-// 0x00,0xe4 = b #-2044
-// 0xff,0xf7,0x00,0xbc = b.w #-2044
-// 0x00,0xf0,0xff,0xbb = b.w #2050
-// 0x66,0xf6,0x30,0xbc = b.w #-1677212
-// 0x99,0xf1,0xcf,0xbb = b.w #1677218
-// 0x00,0xe4 = b #-2044
-0xff,0xe3 = b #2050
-0xff,0xf7,0xff,0xbb = b.w #-2046
-0x00,0xf0,0x00,0xbc = b.w #2052
-// 0x66,0xf6,0x30,0xbc = b.w #-1677212
-// 0x99,0xf1,0xcf,0xbb = b.w #1677218
-0x08,0xbf = it eq
-// 0x00,0xe4 = beq #-2044
+0x99,0xf1,0xcf,0xbb = blt.w #0x19979e
+0x80,0xd0 = beq #-0x100
+0x7f,0xd1 = bne #0xfe
+0x00,0xf0,0x80,0xf8 = bl #0x100
 0x18,0xbf = it ne
-// 0x01,0xe4 = bne #-2042
-0xc8,0xbf = it gt
-// 0xff,0xf7,0x00,0xbc = bgt.w #-2044
-0xd8,0xbf = it le
-// 0x00,0xf0,0xff,0xbb = ble.w #2050
-0xa8,0xbf = it ge
-// 0x66,0xf6,0x30,0xbc = bge.w #-1677212
-0xb8,0xbf = it lt
-// 0x99,0xf1,0xcf,0xbb = blt.w #1677218
-0x80,0xd0 = beq #-252
-0x7f,0xd1 = bne #258
-0x3f,0xf5,0x80,0xaf = bmi.w #-252
-0x40,0xf0,0x7f,0x80 = bne.w #258
-0xc0,0xf6,0x00,0x80 = blt.w #-1048572
-0xbf,0xf2,0xff,0xaf = bge.w #1048578
-0x80,0xd1 = bne #-252
-0x7f,0xdc = bgt #258
-0x7f,0xf4,0x7f,0xaf = bne.w #-254
-0x00,0xf3,0x80,0x80 = bgt.w #260
-0x40,0xf4,0x00,0x80 = bne.w #-1048572
-0x3f,0xf3,0xff,0xaf = bgt.w #1048578
+0x00,0xf0,0x80,0xf8 = blne #0x100
+0x3f,0xf5,0x80,0xaf = bmi.w #-0x100
+0x40,0xf0,0x7f,0x80 = bne.w #0xfe
+0xc0,0xf6,0x00,0x80 = blt.w #-0x100000
+0xbf,0xf2,0xff,0xaf = bge.w #0xffffe
+0x80,0xd1 = bne #-0x100
+0x7f,0xdc = bgt #0xfe
+0x7f,0xf4,0x7f,0xaf = bne.w #-0x102
+0x00,0xf3,0x80,0x80 = bgt.w #0x100
+0x40,0xf4,0x00,0x80 = bne.w #-0x100000
+0x3f,0xf3,0xff,0xaf = bgt.w #0xffffe
 0x08,0xbf = it eq
-// 0x08,0x44 = addeq r0, r1
-0x40,0xd1 = bne #132
+0x08,0x44 = addeq r0, r1
+0x40,0xd1 = bne #0x80
 0x0c,0xbf = ite eq
-// 0x08,0x44 = addeq r0, r1
-// 0x40,0xe0 = b #132
+0x08,0x44 = addeq r0, r1
+0x40,0xe0 = bne #0x80
+0x00,0xe4 = b #-0x800
+0xff,0xe3 = b #0x7fe
+0xff,0xf7,0x00,0xbc = b.w #-0x800
+0x00,0xf0,0xff,0xbb = b.w #0x7fe
+0x66,0xf6,0x30,0xbc = b.w #-0x1997a0
+0x99,0xf1,0xcf,0xbb = b.w #0x19979e
+0x00,0xe4 = b #-0x800
+0xff,0xe3 = b #0x7fe
+0xff,0xf7,0xff,0xbb = b.w #-0x802
+0x00,0xf0,0x00,0xbc = b.w #0x800
+0x66,0xf6,0x30,0xbc = b.w #-0x1997a0
+0x99,0xf1,0xcf,0xbb = b.w #0x19979e
+0x08,0xbf = it eq
+0x00,0xe4 = beq #-0x800
+0x18,0xbf = it ne
+0x01,0xe4 = bne #-0x7fe
+0xc8,0xbf = it gt
+0xff,0xf7,0x00,0xbc = bgt.w #-0x800
+0xd8,0xbf = it le
+0x00,0xf0,0xff,0xbb = ble.w #0x7fe
+0xa8,0xbf = it ge
+0x66,0xf6,0x30,0xbc = bge.w #-0x1997a0
+0xb8,0xbf = it lt
+0x99,0xf1,0xcf,0xbb = blt.w #0x19979e
+0x80,0xd0 = beq #-0x100
+0x7f,0xd1 = bne #0xfe
+0x3f,0xf5,0x80,0xaf = bmi.w #-0x100
+0x40,0xf0,0x7f,0x80 = bne.w #0xfe
+0xc0,0xf6,0x00,0x80 = blt.w #-0x100000
+0xbf,0xf2,0xff,0xaf = bge.w #0xffffe
+0x80,0xd1 = bne #-0x100
+0x7f,0xdc = bgt #0xfe
+0x7f,0xf4,0x7f,0xaf = bne.w #-0x102
+0x00,0xf3,0x80,0x80 = bgt.w #0x100
+0x40,0xf4,0x00,0x80 = bne.w #-0x100000
+0x3f,0xf3,0xff,0xaf = bgt.w #0xffffe
+0x08,0xbf = it eq
+0x08,0x44 = addeq r0, r1
+0x40,0xd1 = bne #0x80
+0x0c,0xbf = ite eq
+0x08,0x44 = addeq r0, r1
+0x40,0xe0 = bne #0x80
+0x01,0xe0 = b #2
+0x00,0xf0,0x01,0xf8 = bl #2
+0x01,0xd0 = beq #2
+0x08,0xb1 = cbz r0, #2
+0x00,0xf0,0x02,0xe8 = blx #4
diff --git a/suite/MC/ARM/thumb2-bxj-v8.s.cs b/suite/MC/ARM/thumb2-bxj-v8.s.cs
new file mode 100644
index 000000000..7a6aff37f
--- /dev/null
+++ b/suite/MC/ARM/thumb2-bxj-v8.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
+0xcd,0xf3,0x00,0x8f = bxj sp
diff --git a/suite/MC/ARM/thumb2-bxj.s.cs b/suite/MC/ARM/thumb2-bxj.s.cs
new file mode 100644
index 000000000..3d821beaa
--- /dev/null
+++ b/suite/MC/ARM/thumb2-bxj.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xc2,0xf3,0x00,0x8f = bxj r2
diff --git a/suite/MC/ARM/thumb2-ldr.w-str.w.s.cs b/suite/MC/ARM/thumb2-ldr.w-str.w.s.cs
new file mode 100644
index 000000000..f4f694bdf
--- /dev/null
+++ b/suite/MC/ARM/thumb2-ldr.w-str.w.s.cs
@@ -0,0 +1,56 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x51,0xf8,0x04,0x3b = ldr r3, [r1], #4
+0x51,0xf8,0x04,0x3b = ldr r3, [r1], #4
+0x40,0xf8,0x04,0x3b = str r3, [r0], #4
+0x40,0xf8,0x04,0x3b = str r3, [r0], #4
+0x51,0xf8,0x04,0x3d = ldr r3, [r1, #-4]!
+0x51,0xf8,0x04,0x3d = ldr r3, [r1, #-4]!
+0x40,0xf8,0x04,0x3d = str r3, [r0, #-4]!
+0x40,0xf8,0x04,0x3d = str r3, [r0, #-4]!
+0x51,0xf8,0x04,0x0d = ldr r0, [r1, #-4]!
+0x51,0xf8,0x04,0xdd = ldr sp, [r1, #-4]!
+0x51,0xf8,0x04,0xfd = ldr pc, [r1, #-4]!
+0x50,0xf8,0x04,0x1d = ldr r1, [r0, #-4]!
+0x5d,0xf8,0x04,0x1d = ldr r1, [sp, #-4]!
+0x50,0xf8,0xff,0x1f = ldr r1, [r0, #0xff]!
+0x50,0xf8,0xff,0x1d = ldr r1, [r0, #-0xff]!
+0x50,0xf8,0x00,0x1f = ldr r1, [r0, #0]!
+0x08,0xbf = it eq
+0x50,0xf8,0xff,0x1f = ldreq r1, [r0, #0xff]!
+0xd8,0xbf = it le
+0x50,0xf8,0xff,0x1f = ldrle r1, [r0, #0xff]!
+0x51,0xf8,0x04,0x0b = ldr r0, [r1], #4
+0x51,0xf8,0x04,0xdb = ldr sp, [r1], #4
+0x51,0xf8,0x04,0xfb = ldr pc, [r1], #4
+0x51,0xf8,0x04,0x0b = ldr r0, [r1], #4
+0x5d,0xf8,0x04,0x0b = ldr r0, [sp], #4
+0x5f,0xf8,0x04,0x0b = ldr.w	r0, [pc, #-0xb04]
+0x51,0xf8,0xff,0x0b = ldr r0, [r1], #0xff
+0x51,0xf8,0x00,0x0b = ldr r0, [r1], #0
+0x51,0xf8,0xff,0x09 = ldr r0, [r1], #-0xff
+0x08,0xbf = it eq
+0x51,0xf8,0xff,0x0b = ldreq r0, [r1], #0xff
+0xd8,0xbf = it le
+0x51,0xf8,0xff,0x0b = ldrle r0, [r1], #0xff
+0x40,0xf8,0x04,0x1d = str r1, [r0, #-4]!
+0x40,0xf8,0x04,0xdd = str sp, [r0, #-4]!
+0x42,0xf8,0x04,0x1d = str r1, [r2, #-4]!
+0x4d,0xf8,0x04,0x1d = str r1, [sp, #-4]!
+0x42,0xf8,0xff,0x1f = str r1, [r2, #0xff]!
+0x42,0xf8,0x00,0x1f = str r1, [r2, #0]!
+0x42,0xf8,0xff,0x1d = str r1, [r2, #-0xff]!
+0x08,0xbf = it eq
+0x42,0xf8,0xff,0x1f = streq r1, [r2, #0xff]!
+0xd8,0xbf = it le
+0x42,0xf8,0xff,0x1f = strle r1, [r2, #0xff]!
+0x40,0xf8,0x04,0x1b = str r1, [r0], #4
+0x40,0xf8,0x04,0xdb = str sp, [r0], #4
+0x41,0xf8,0x04,0x0b = str r0, [r1], #4
+0x4d,0xf8,0x04,0x0b = str r0, [sp], #4
+0x40,0xf8,0xff,0x1b = str r1, [r0], #0xff
+0x40,0xf8,0x00,0x1b = str r1, [r0], #0
+0x40,0xf8,0xff,0x19 = str r1, [r0], #-0xff
+0x08,0xbf = it eq
+0x40,0xf8,0xff,0x1b = streq r1, [r0], #0xff
+0xd8,0xbf = it le
+0x40,0xf8,0xff,0x1b = strle r1, [r0], #0xff
diff --git a/suite/MC/ARM/thumb2-ldrexd-strexd.s.cs b/suite/MC/ARM/thumb2-ldrexd-strexd.s.cs
new file mode 100644
index 000000000..9e1715e42
--- /dev/null
+++ b/suite/MC/ARM/thumb2-ldrexd-strexd.s.cs
@@ -0,0 +1,3 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xd2,0xe8,0x7f,0x01 = ldrexd r0, r1, [r2]
+0xc6,0xe8,0x73,0x45 = strexd r3, r4, r5, [r6]
diff --git a/suite/MC/ARM/thumb2-mclass.s.cs b/suite/MC/ARM/thumb2-mclass.s.cs
index 62446148d..0a1c3e05d 100644
--- a/suite/MC/ARM/thumb2-mclass.s.cs
+++ b/suite/MC/ARM/thumb2-mclass.s.cs
@@ -9,33 +9,11 @@
 0xef,0xf3,0x08,0x80 = mrs r0, msp
 0xef,0xf3,0x09,0x80 = mrs r0, psp
 0xef,0xf3,0x10,0x80 = mrs r0, primask
-0xef,0xf3,0x11,0x80 = mrs r0, basepri
-0xef,0xf3,0x12,0x80 = mrs r0, basepri_max
-0xef,0xf3,0x13,0x80 = mrs r0, faultmask
 0xef,0xf3,0x14,0x80 = mrs r0, control
-// 0x80,0xf3,0x00,0x88 = msr apsr, r0
-// 0x80,0xf3,0x00,0x88 = msr apsr, r0
-0x80,0xf3,0x00,0x84 = msr apsr_g, r0
-0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0
-// 0x80,0xf3,0x01,0x88 = msr iapsr, r0
-// 0x80,0xf3,0x01,0x88 = msr iapsr, r0
-0x80,0xf3,0x01,0x84 = msr iapsr_g, r0
-0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0
-// 0x80,0xf3,0x02,0x88 = msr eapsr, r0
-// 0x80,0xf3,0x02,0x88 = msr eapsr, r0
-0x80,0xf3,0x02,0x84 = msr eapsr_g, r0
-0x80,0xf3,0x02,0x8c = msr eapsr_nzcvqg, r0
-// 0x80,0xf3,0x03,0x88 = msr xpsr, r0
-// 0x80,0xf3,0x03,0x88 = msr xpsr, r0
-0x80,0xf3,0x03,0x84 = msr xpsr_g, r0
-0x80,0xf3,0x03,0x8c = msr xpsr_nzcvqg, r0
 0x80,0xf3,0x05,0x88 = msr ipsr, r0
 0x80,0xf3,0x06,0x88 = msr epsr, r0
 0x80,0xf3,0x07,0x88 = msr iepsr, r0
 0x80,0xf3,0x08,0x88 = msr msp, r0
 0x80,0xf3,0x09,0x88 = msr psp, r0
 0x80,0xf3,0x10,0x88 = msr primask, r0
-0x80,0xf3,0x11,0x88 = msr basepri, r0
-0x80,0xf3,0x12,0x88 = msr basepri_max, r0
-0x80,0xf3,0x13,0x88 = msr faultmask, r0
 0x80,0xf3,0x14,0x88 = msr control, r0
diff --git a/suite/MC/ARM/thumb2-narrow-dp.ll.cs b/suite/MC/ARM/thumb2-narrow-dp.ll.cs
index 8040e8b56..2ec77622e 100644
--- a/suite/MC/ARM/thumb2-narrow-dp.ll.cs
+++ b/suite/MC/ARM/thumb2-narrow-dp.ll.cs
@@ -1,12 +1,48 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
+0x40,0x1d = adds r0, r0, #5
+0x08,0x31 = adds r1, #8
+0x11,0xf1,0x08,0x01 = adds.w r1, r1, #8
+0x18,0xf1,0x08,0x08 = adds.w r8, r8, #8
+0x08,0xbf = it eq
+0x40,0x1d = addeq r0, r0, #5
+0x08,0xbf = it eq
+0x08,0x31 = addeq r1, #8
+0x08,0xbf = it eq
+0x10,0xf1,0x05,0x00 = addseq.w r0, r0, #5
+0x08,0xbf = it eq
+0x11,0xf1,0x08,0x01 = addseq.w r1, r1, #8
+0x50,0x18 = adds r0, r2, r1
+0x52,0x18 = adds r2, r2, r1
+0x0b,0x44 = add r3, r1
+0x08,0xbf = it eq
+0x50,0x18 = addeq r0, r2, r1
+0x08,0xbf = it eq
+0x52,0x18 = addeq r2, r2, r1
+0x08,0xbf = it eq
+0x12,0xeb,0x01,0x00 = addseq.w r0, r2, r1
+0x08,0xbf = it eq
+0x12,0xeb,0x01,0x02 = addseq.w r2, r2, r1
+0x0b,0x44 = add r3, r1
+0x7c,0x44 = add r4, pc
+0x7c,0x44 = add r4, pc
+0x97,0x44 = add pc, r2
+0x97,0x44 = add pc, r2
+0xef,0x44 = add pc, sp, pc
+0x05,0xb0 = add sp, #0x14
+0x7f,0xb0 = add sp, #0x1fc
+0x0d,0xf5,0x00,0x7d = add.w sp, sp, #0x200
+0xe9,0x44 = add r9, sp, r9
+0xd5,0x44 = add sp, r10
+0xd5,0x44 = add sp, r10
+0xfd,0x44 = add sp, pc
 0x12,0xea,0x01,0x00 = ands.w r0, r2, r1
 0x0a,0x40 = ands r2, r1
 0x0a,0x40 = ands r2, r1
 0x10,0xea,0x01,0x00 = ands.w r0, r0, r1
 0x11,0xea,0x03,0x03 = ands.w r3, r1, r3
 0x01,0xea,0x00,0x00 = and.w r0, r1, r0
-// 0x0f,0x40 = ands r7, r1
-// 0x0f,0x40 = ands r7, r1
+0x0f,0x40 = ands r7, r1
+0x0f,0x40 = ands r7, r1
 0x11,0xea,0x08,0x08 = ands.w r8, r1, r8
 0x18,0xea,0x01,0x08 = ands.w r8, r8, r1
 0x18,0xea,0x00,0x00 = ands.w r0, r8, r0
@@ -14,41 +50,41 @@
 0x12,0xea,0x41,0x02 = ands.w r2, r2, r1, lsl #1
 0x11,0xea,0x50,0x00 = ands.w r0, r1, r0, lsr #1
 0x08,0xbf = it eq
-// 0x02,0xea,0x01,0x00 = andeq.w r0, r2, r1
+0x02,0xea,0x01,0x00 = andeq.w r0, r2, r1
 0x08,0xbf = it eq
-// 0x0b,0x40 = andeq r3, r1
+0x0b,0x40 = andeq r3, r1
 0x08,0xbf = it eq
-// 0x0b,0x40 = andeq r3, r1
+0x0b,0x40 = andeq r3, r1
 0x08,0xbf = it eq
-// 0x00,0xea,0x01,0x00 = andeq.w r0, r0, r1
+0x00,0xea,0x01,0x00 = andeq.w r0, r0, r1
 0x08,0xbf = it eq
-// 0x01,0xea,0x02,0x02 = andeq.w r2, r1, r2
+0x01,0xea,0x02,0x02 = andeq.w r2, r1, r2
 0x08,0xbf = it eq
-// 0x11,0xea,0x00,0x00 = andseq.w r0, r1, r0
+0x11,0xea,0x00,0x00 = andseq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0x0f,0x40 = andeq r7, r1
+0x0f,0x40 = andeq r7, r1
 0x08,0xbf = it eq
-// 0x0f,0x40 = andeq r7, r1
+0x0f,0x40 = andeq r7, r1
 0x08,0xbf = it eq
-// 0x01,0xea,0x08,0x08 = andeq.w r8, r1, r8
+0x01,0xea,0x08,0x08 = andeq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x08,0xea,0x01,0x08 = andeq.w r8, r8, r1
+0x08,0xea,0x01,0x08 = andeq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x08,0xea,0x04,0x04 = andeq.w r4, r8, r4
+0x08,0xea,0x04,0x04 = andeq.w r4, r8, r4
 0x08,0xbf = it eq
-// 0x04,0xea,0x08,0x04 = andeq.w r4, r4, r8
+0x04,0xea,0x08,0x04 = andeq.w r4, r4, r8
 0x08,0xbf = it eq
-// 0x00,0xea,0x41,0x00 = andeq.w r0, r0, r1, lsl #1
+0x00,0xea,0x41,0x00 = andeq.w r0, r0, r1, lsl #1
 0x08,0xbf = it eq
-// 0x01,0xea,0x55,0x05 = andeq.w r5, r1, r5, lsr #1
+0x01,0xea,0x55,0x05 = andeq.w r5, r1, r5, lsr #1
 0x92,0xea,0x01,0x00 = eors.w r0, r2, r1
 0x4d,0x40 = eors r5, r1
 0x4d,0x40 = eors r5, r1
 0x90,0xea,0x01,0x00 = eors.w r0, r0, r1
 0x91,0xea,0x02,0x02 = eors.w r2, r1, r2
 0x81,0xea,0x01,0x01 = eor.w r1, r1, r1
-// 0x4f,0x40 = eors r7, r1
-// 0x4f,0x40 = eors r7, r1
+0x4f,0x40 = eors r7, r1
+0x4f,0x40 = eors r7, r1
 0x91,0xea,0x08,0x08 = eors.w r8, r1, r8
 0x98,0xea,0x01,0x08 = eors.w r8, r8, r1
 0x98,0xea,0x06,0x06 = eors.w r6, r8, r6
@@ -56,140 +92,140 @@
 0x92,0xea,0x41,0x02 = eors.w r2, r2, r1, lsl #1
 0x91,0xea,0x50,0x00 = eors.w r0, r1, r0, lsr #1
 0x08,0xbf = it eq
-// 0x82,0xea,0x01,0x03 = eoreq.w r3, r2, r1
+0x82,0xea,0x01,0x03 = eoreq.w r3, r2, r1
 0x08,0xbf = it eq
-// 0x48,0x40 = eoreq r0, r1
+0x48,0x40 = eoreq r0, r1
 0x08,0xbf = it eq
-// 0x4a,0x40 = eoreq r2, r1
+0x4a,0x40 = eoreq r2, r1
 0x08,0xbf = it eq
-// 0x83,0xea,0x01,0x03 = eoreq.w r3, r3, r1
+0x83,0xea,0x01,0x03 = eoreq.w r3, r3, r1
 0x08,0xbf = it eq
-// 0x81,0xea,0x00,0x00 = eoreq.w r0, r1, r0
+0x81,0xea,0x00,0x00 = eoreq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0x91,0xea,0x01,0x01 = eorseq.w r1, r1, r1
+0x91,0xea,0x01,0x01 = eorseq.w r1, r1, r1
 0x08,0xbf = it eq
-// 0x4f,0x40 = eoreq r7, r1
+0x4f,0x40 = eoreq r7, r1
 0x08,0xbf = it eq
-// 0x4f,0x40 = eoreq r7, r1
+0x4f,0x40 = eoreq r7, r1
 0x08,0xbf = it eq
-// 0x81,0xea,0x08,0x08 = eoreq.w r8, r1, r8
+0x81,0xea,0x08,0x08 = eoreq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x88,0xea,0x01,0x08 = eoreq.w r8, r8, r1
+0x88,0xea,0x01,0x08 = eoreq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x88,0xea,0x00,0x00 = eoreq.w r0, r8, r0
+0x88,0xea,0x00,0x00 = eoreq.w r0, r8, r0
 0x08,0xbf = it eq
-// 0x83,0xea,0x08,0x03 = eoreq.w r3, r3, r8
+0x83,0xea,0x08,0x03 = eoreq.w r3, r3, r8
 0x08,0xbf = it eq
-// 0x84,0xea,0x41,0x04 = eoreq.w r4, r4, r1, lsl #1
+0x84,0xea,0x41,0x04 = eoreq.w r4, r4, r1, lsl #1
 0x08,0xbf = it eq
-// 0x81,0xea,0x50,0x00 = eoreq.w r0, r1, r0, lsr #1
+0x81,0xea,0x50,0x00 = eoreq.w r0, r1, r0, lsr #1
 0x12,0xfa,0x01,0xf0 = lsls.w r0, r2, r1
-// 0x8a,0x40 = lsls r2, r1
+0x8a,0x40 = lsls r2, r1
 0x11,0xfa,0x02,0xf2 = lsls.w r2, r1, r2
 0x10,0xfa,0x01,0xf0 = lsls.w r0, r0, r1
-// 0x11,0xfa,0x04,0xf4 = lsls.w r4, r1, r4
+0x11,0xfa,0x04,0xf4 = lsls.w r4, r1, r4
 0x01,0xfa,0x04,0xf4 = lsl.w r4, r1, r4
-// 0x8f,0x40 = lsls r7, r1
+0x8f,0x40 = lsls r7, r1
 0x11,0xfa,0x08,0xf8 = lsls.w r8, r1, r8
 0x18,0xfa,0x01,0xf8 = lsls.w r8, r8, r1
 0x18,0xfa,0x03,0xf3 = lsls.w r3, r8, r3
 0x15,0xfa,0x08,0xf5 = lsls.w r5, r5, r8
 0x08,0xbf = it eq
-// 0x02,0xfa,0x01,0xf0 = lsleq.w r0, r2, r1
+0x02,0xfa,0x01,0xf0 = lsleq.w r0, r2, r1
 0x08,0xbf = it eq
-// 0x8a,0x40 = lsleq r2, r1
+0x8a,0x40 = lsleq r2, r1
 0x08,0xbf = it eq
-// 0x01,0xfa,0x02,0xf2 = lsleq.w r2, r1, r2
+0x01,0xfa,0x02,0xf2 = lsleq.w r2, r1, r2
 0x08,0xbf = it eq
-// 0x00,0xfa,0x01,0xf0 = lsleq.w r0, r0, r1
+0x00,0xfa,0x01,0xf0 = lsleq.w r0, r0, r1
 0x08,0xbf = it eq
-// 0x01,0xfa,0x03,0xf3 = lsleq.w r3, r1, r3
+0x01,0xfa,0x03,0xf3 = lsleq.w r3, r1, r3
 0x08,0xbf = it eq
-// 0x11,0xfa,0x04,0xf4 = lslseq.w r4, r1, r4
+0x11,0xfa,0x04,0xf4 = lslseq.w r4, r1, r4
 0x08,0xbf = it eq
-// 0x8f,0x40 = lsleq r7, r1
+0x8f,0x40 = lsleq r7, r1
 0x08,0xbf = it eq
-// 0x01,0xfa,0x08,0xf8 = lsleq.w r8, r1, r8
+0x01,0xfa,0x08,0xf8 = lsleq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x08,0xfa,0x01,0xf8 = lsleq.w r8, r8, r1
+0x08,0xfa,0x01,0xf8 = lsleq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x08,0xfa,0x00,0xf0 = lsleq.w r0, r8, r0
+0x08,0xfa,0x00,0xf0 = lsleq.w r0, r8, r0
 0x08,0xbf = it eq
-// 0x03,0xfa,0x08,0xf3 = lsleq.w r3, r3, r8
+0x03,0xfa,0x08,0xf3 = lsleq.w r3, r3, r8
 0x32,0xfa,0x01,0xf6 = lsrs.w r6, r2, r1
 0xca,0x40 = lsrs r2, r1
 0x31,0xfa,0x02,0xf2 = lsrs.w r2, r1, r2
 0x32,0xfa,0x01,0xf2 = lsrs.w r2, r2, r1
 0x31,0xfa,0x03,0xf3 = lsrs.w r3, r1, r3
 0x21,0xfa,0x04,0xf4 = lsr.w r4, r1, r4
-// 0xcf,0x40 = lsrs r7, r1
+0xcf,0x40 = lsrs r7, r1
 0x31,0xfa,0x08,0xf8 = lsrs.w r8, r1, r8
 0x38,0xfa,0x01,0xf8 = lsrs.w r8, r8, r1
 0x38,0xfa,0x02,0xf2 = lsrs.w r2, r8, r2
 0x35,0xfa,0x08,0xf5 = lsrs.w r5, r5, r8
 0x08,0xbf = it eq
-// 0x22,0xfa,0x01,0xf6 = lsreq.w r6, r2, r1
+0x22,0xfa,0x01,0xf6 = lsreq.w r6, r2, r1
 0x08,0xbf = it eq
-// 0xcf,0x40 = lsreq r7, r1
+0xcf,0x40 = lsreq r7, r1
 0x08,0xbf = it eq
-// 0x21,0xfa,0x07,0xf7 = lsreq.w r7, r1, r7
+0x21,0xfa,0x07,0xf7 = lsreq.w r7, r1, r7
 0x08,0xbf = it eq
-// 0x27,0xfa,0x01,0xf7 = lsreq.w r7, r7, r1
+0x27,0xfa,0x01,0xf7 = lsreq.w r7, r7, r1
 0x08,0xbf = it eq
-// 0x21,0xfa,0x02,0xf2 = lsreq.w r2, r1, r2
+0x21,0xfa,0x02,0xf2 = lsreq.w r2, r1, r2
 0x08,0xbf = it eq
-// 0x31,0xfa,0x00,0xf0 = lsrseq.w r0, r1, r0
+0x31,0xfa,0x00,0xf0 = lsrseq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0xcf,0x40 = lsreq r7, r1
+0xcf,0x40 = lsreq r7, r1
 0x08,0xbf = it eq
-// 0x21,0xfa,0x08,0xf8 = lsreq.w r8, r1, r8
+0x21,0xfa,0x08,0xf8 = lsreq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x28,0xfa,0x01,0xf8 = lsreq.w r8, r8, r1
+0x28,0xfa,0x01,0xf8 = lsreq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x28,0xfa,0x01,0xf1 = lsreq.w r1, r8, r1
+0x28,0xfa,0x01,0xf1 = lsreq.w r1, r8, r1
 0x08,0xbf = it eq
-// 0x24,0xfa,0x08,0xf4 = lsreq.w r4, r4, r8
+0x24,0xfa,0x08,0xf4 = lsreq.w r4, r4, r8
 0x56,0xfa,0x05,0xf7 = asrs.w r7, r6, r5
 0x08,0x41 = asrs r0, r1
 0x51,0xfa,0x00,0xf0 = asrs.w r0, r1, r0
 0x53,0xfa,0x01,0xf3 = asrs.w r3, r3, r1
 0x51,0xfa,0x01,0xf1 = asrs.w r1, r1, r1
 0x41,0xfa,0x00,0xf0 = asr.w r0, r1, r0
-// 0x0f,0x41 = asrs r7, r1
+0x0f,0x41 = asrs r7, r1
 0x51,0xfa,0x08,0xf8 = asrs.w r8, r1, r8
 0x58,0xfa,0x01,0xf8 = asrs.w r8, r8, r1
 0x58,0xfa,0x05,0xf5 = asrs.w r5, r8, r5
 0x55,0xfa,0x08,0xf5 = asrs.w r5, r5, r8
 0x08,0xbf = it eq
-// 0x42,0xfa,0x01,0xf0 = asreq.w r0, r2, r1
+0x42,0xfa,0x01,0xf0 = asreq.w r0, r2, r1
 0x08,0xbf = it eq
-// 0x0a,0x41 = asreq r2, r1
+0x0a,0x41 = asreq r2, r1
 0x08,0xbf = it eq
-// 0x42,0xfa,0x01,0xf1 = asreq.w r1, r2, r1
+0x42,0xfa,0x01,0xf1 = asreq.w r1, r2, r1
 0x08,0xbf = it eq
-// 0x44,0xfa,0x01,0xf4 = asreq.w r4, r4, r1
+0x44,0xfa,0x01,0xf4 = asreq.w r4, r4, r1
 0x08,0xbf = it eq
-// 0x41,0xfa,0x06,0xf6 = asreq.w r6, r1, r6
+0x41,0xfa,0x06,0xf6 = asreq.w r6, r1, r6
 0x08,0xbf = it eq
-// 0x51,0xfa,0x03,0xf3 = asrseq.w r3, r1, r3
+0x51,0xfa,0x03,0xf3 = asrseq.w r3, r1, r3
 0x08,0xbf = it eq
-// 0x0f,0x41 = asreq r7, r1
+0x0f,0x41 = asreq r7, r1
 0x08,0xbf = it eq
-// 0x41,0xfa,0x08,0xf8 = asreq.w r8, r1, r8
+0x41,0xfa,0x08,0xf8 = asreq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x48,0xfa,0x01,0xf8 = asreq.w r8, r8, r1
+0x48,0xfa,0x01,0xf8 = asreq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x48,0xfa,0x01,0xf1 = asreq.w r1, r8, r1
+0x48,0xfa,0x01,0xf1 = asreq.w r1, r8, r1
 0x08,0xbf = it eq
-// 0x43,0xfa,0x08,0xf3 = asreq.w r3, r3, r8
+0x43,0xfa,0x08,0xf3 = asreq.w r3, r3, r8
 0x52,0xeb,0x01,0x05 = adcs.w r5, r2, r1
 0x4d,0x41 = adcs r5, r1
-// 0x4b,0x41 = adcs r3, r1
+0x4b,0x41 = adcs r3, r1
 0x52,0xeb,0x01,0x02 = adcs.w r2, r2, r1
-// 0x51,0xeb,0x03,0x03 = adcs.w r3, r1, r3
-// 0x41,0xeb,0x00,0x00 = adc.w r0, r1, r0
-// 0x4f,0x41 = adcs r7, r1
-// 0x4f,0x41 = adcs r7, r1
+0x51,0xeb,0x03,0x03 = adcs.w r3, r1, r3
+0x41,0xeb,0x00,0x00 = adc.w r0, r1, r0
+0x4f,0x41 = adcs r7, r1
+0x4f,0x41 = adcs r7, r1
 0x51,0xeb,0x08,0x08 = adcs.w r8, r1, r8
 0x58,0xeb,0x01,0x08 = adcs.w r8, r8, r1
 0x58,0xeb,0x05,0x05 = adcs.w r5, r8, r5
@@ -197,40 +233,40 @@
 0x53,0xeb,0x41,0x03 = adcs.w r3, r3, r1, lsl #1
 0x51,0xeb,0x54,0x04 = adcs.w r4, r1, r4, lsr #1
 0x08,0xbf = it eq
-// 0x42,0xeb,0x03,0x01 = adceq.w r1, r2, r3
+0x42,0xeb,0x03,0x01 = adceq.w r1, r2, r3
 0x08,0xbf = it eq
-// 0x49,0x41 = adceq r1, r1
+0x49,0x41 = adceq r1, r1
 0x08,0xbf = it eq
-// 0x4b,0x41 = adceq r3, r1
+0x4b,0x41 = adceq r3, r1
 0x08,0xbf = it eq
-// 0x43,0xeb,0x01,0x03 = adceq.w r3, r3, r1
+0x43,0xeb,0x01,0x03 = adceq.w r3, r3, r1
 0x08,0xbf = it eq
-// 0x41,0xeb,0x00,0x00 = adceq.w r0, r1, r0
+0x41,0xeb,0x00,0x00 = adceq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0x51,0xeb,0x03,0x03 = adcseq.w r3, r1, r3
+0x51,0xeb,0x03,0x03 = adcseq.w r3, r1, r3
 0x08,0xbf = it eq
-// 0x4f,0x41 = adceq r7, r1
+0x4f,0x41 = adceq r7, r1
 0x08,0xbf = it eq
-// 0x4f,0x41 = adceq r7, r1
+0x4f,0x41 = adceq r7, r1
 0x08,0xbf = it eq
-// 0x41,0xeb,0x08,0x08 = adceq.w r8, r1, r8
+0x41,0xeb,0x08,0x08 = adceq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x48,0xeb,0x01,0x08 = adceq.w r8, r8, r1
+0x48,0xeb,0x01,0x08 = adceq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x48,0xeb,0x03,0x03 = adceq.w r3, r8, r3
+0x48,0xeb,0x03,0x03 = adceq.w r3, r8, r3
 0x08,0xbf = it eq
-// 0x41,0xeb,0x08,0x01 = adceq.w r1, r1, r8
+0x41,0xeb,0x08,0x01 = adceq.w r1, r1, r8
 0x08,0xbf = it eq
-// 0x42,0xeb,0x41,0x02 = adceq.w r2, r2, r1, lsl #1
+0x42,0xeb,0x41,0x02 = adceq.w r2, r2, r1, lsl #1
 0x08,0xbf = it eq
-// 0x41,0xeb,0x51,0x01 = adceq.w r1, r1, r1, lsr #1
+0x41,0xeb,0x51,0x01 = adceq.w r1, r1, r1, lsr #1
 0x72,0xeb,0x01,0x03 = sbcs.w r3, r2, r1
 0x8c,0x41 = sbcs r4, r1
 0x74,0xeb,0x01,0x01 = sbcs.w r1, r4, r1
 0x74,0xeb,0x01,0x04 = sbcs.w r4, r4, r1
-// 0x71,0xeb,0x02,0x02 = sbcs.w r2, r1, r2
-// 0x61,0xeb,0x00,0x00 = sbc.w r0, r1, r0
-// 0x8f,0x41 = sbcs r7, r1
+0x71,0xeb,0x02,0x02 = sbcs.w r2, r1, r2
+0x61,0xeb,0x00,0x00 = sbc.w r0, r1, r0
+0x8f,0x41 = sbcs r7, r1
 0x71,0xeb,0x08,0x08 = sbcs.w r8, r1, r8
 0x78,0xeb,0x01,0x08 = sbcs.w r8, r8, r1
 0x78,0xeb,0x04,0x04 = sbcs.w r4, r8, r4
@@ -238,72 +274,72 @@
 0x72,0xeb,0x41,0x02 = sbcs.w r2, r2, r1, lsl #1
 0x71,0xeb,0x55,0x05 = sbcs.w r5, r1, r5, lsr #1
 0x08,0xbf = it eq
-// 0x62,0xeb,0x01,0x05 = sbceq.w r5, r2, r1
+0x62,0xeb,0x01,0x05 = sbceq.w r5, r2, r1
 0x08,0xbf = it eq
-// 0x8d,0x41 = sbceq r5, r1
+0x8d,0x41 = sbceq r5, r1
 0x08,0xbf = it eq
-// 0x65,0xeb,0x01,0x01 = sbceq.w r1, r5, r1
+0x65,0xeb,0x01,0x01 = sbceq.w r1, r5, r1
 0x08,0xbf = it eq
-// 0x65,0xeb,0x01,0x05 = sbceq.w r5, r5, r1
+0x65,0xeb,0x01,0x05 = sbceq.w r5, r5, r1
 0x08,0xbf = it eq
-// 0x61,0xeb,0x00,0x00 = sbceq.w r0, r1, r0
+0x61,0xeb,0x00,0x00 = sbceq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0x71,0xeb,0x02,0x02 = sbcseq.w r2, r1, r2
+0x71,0xeb,0x02,0x02 = sbcseq.w r2, r1, r2
 0x08,0xbf = it eq
-// 0x8f,0x41 = sbceq r7, r1
+0x8f,0x41 = sbceq r7, r1
 0x08,0xbf = it eq
-// 0x61,0xeb,0x08,0x08 = sbceq.w r8, r1, r8
+0x61,0xeb,0x08,0x08 = sbceq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x68,0xeb,0x01,0x08 = sbceq.w r8, r8, r1
+0x68,0xeb,0x01,0x08 = sbceq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x68,0xeb,0x07,0x07 = sbceq.w r7, r8, r7
+0x68,0xeb,0x07,0x07 = sbceq.w r7, r8, r7
 0x08,0xbf = it eq
-// 0x67,0xeb,0x08,0x07 = sbceq.w r7, r7, r8
+0x67,0xeb,0x08,0x07 = sbceq.w r7, r7, r8
 0x08,0xbf = it eq
-// 0x62,0xeb,0x41,0x02 = sbceq.w r2, r2, r1, lsl #1
+0x62,0xeb,0x41,0x02 = sbceq.w r2, r2, r1, lsl #1
 0x08,0xbf = it eq
-// 0x61,0xeb,0x55,0x05 = sbceq.w r5, r1, r5, lsr #1
+0x61,0xeb,0x55,0x05 = sbceq.w r5, r1, r5, lsr #1
 0x72,0xfa,0x01,0xf3 = rors.w r3, r2, r1
 0xc8,0x41 = rors r0, r1
 0x70,0xfa,0x01,0xf1 = rors.w r1, r0, r1
 0x72,0xfa,0x01,0xf2 = rors.w r2, r2, r1
 0x71,0xfa,0x02,0xf2 = rors.w r2, r1, r2
 0x61,0xfa,0x05,0xf5 = ror.w r5, r1, r5
-// 0xcf,0x41 = rors r7, r1
+0xcf,0x41 = rors r7, r1
 0x71,0xfa,0x08,0xf8 = rors.w r8, r1, r8
 0x78,0xfa,0x01,0xf8 = rors.w r8, r8, r1
 0x78,0xfa,0x06,0xf6 = rors.w r6, r8, r6
 0x76,0xfa,0x08,0xf6 = rors.w r6, r6, r8
 0x08,0xbf = it eq
-// 0x62,0xfa,0x01,0xf4 = roreq.w r4, r2, r1
+0x62,0xfa,0x01,0xf4 = roreq.w r4, r2, r1
 0x08,0xbf = it eq
-// 0xcc,0x41 = roreq r4, r1
+0xcc,0x41 = roreq r4, r1
 0x08,0xbf = it eq
-// 0x64,0xfa,0x01,0xf1 = roreq.w r1, r4, r1
+0x64,0xfa,0x01,0xf1 = roreq.w r1, r4, r1
 0x08,0xbf = it eq
-// 0x64,0xfa,0x01,0xf4 = roreq.w r4, r4, r1
+0x64,0xfa,0x01,0xf4 = roreq.w r4, r4, r1
 0x08,0xbf = it eq
-// 0x61,0xfa,0x00,0xf0 = roreq.w r0, r1, r0
+0x61,0xfa,0x00,0xf0 = roreq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0x71,0xfa,0x00,0xf0 = rorseq.w r0, r1, r0
+0x71,0xfa,0x00,0xf0 = rorseq.w r0, r1, r0
 0x08,0xbf = it eq
-// 0xcf,0x41 = roreq r7, r1
+0xcf,0x41 = roreq r7, r1
 0x08,0xbf = it eq
-// 0x61,0xfa,0x08,0xf8 = roreq.w r8, r1, r8
+0x61,0xfa,0x08,0xf8 = roreq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x68,0xfa,0x01,0xf8 = roreq.w r8, r8, r1
+0x68,0xfa,0x01,0xf8 = roreq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x68,0xfa,0x03,0xf3 = roreq.w r3, r8, r3
+0x68,0xfa,0x03,0xf3 = roreq.w r3, r8, r3
 0x08,0xbf = it eq
-// 0x61,0xfa,0x08,0xf1 = roreq.w r1, r1, r8
+0x61,0xfa,0x08,0xf1 = roreq.w r1, r1, r8
 0x52,0xea,0x01,0x07 = orrs.w r7, r2, r1
 0x0a,0x43 = orrs r2, r1
 0x0b,0x43 = orrs r3, r1
 0x54,0xea,0x01,0x04 = orrs.w r4, r4, r1
 0x51,0xea,0x05,0x05 = orrs.w r5, r1, r5
 0x41,0xea,0x02,0x02 = orr.w r2, r1, r2
-// 0x0f,0x43 = orrs r7, r1
-// 0x0f,0x43 = orrs r7, r1
+0x0f,0x43 = orrs r7, r1
+0x0f,0x43 = orrs r7, r1
 0x51,0xea,0x08,0x08 = orrs.w r8, r1, r8
 0x58,0xea,0x01,0x08 = orrs.w r8, r8, r1
 0x58,0xea,0x01,0x01 = orrs.w r1, r8, r1
@@ -311,40 +347,40 @@
 0x51,0xea,0x41,0x01 = orrs.w r1, r1, r1, lsl #1
 0x51,0xea,0x50,0x00 = orrs.w r0, r1, r0, lsr #1
 0x08,0xbf = it eq
-// 0x42,0xea,0x01,0x00 = orreq.w r0, r2, r1
+0x42,0xea,0x01,0x00 = orreq.w r0, r2, r1
 0x08,0xbf = it eq
-// 0x0d,0x43 = orreq r5, r1
+0x0d,0x43 = orreq r5, r1
 0x08,0xbf = it eq
-// 0x0d,0x43 = orreq r5, r1
+0x0d,0x43 = orreq r5, r1
 0x08,0xbf = it eq
-// 0x42,0xea,0x01,0x02 = orreq.w r2, r2, r1
+0x42,0xea,0x01,0x02 = orreq.w r2, r2, r1
 0x08,0xbf = it eq
-// 0x41,0xea,0x03,0x03 = orreq.w r3, r1, r3
+0x41,0xea,0x03,0x03 = orreq.w r3, r1, r3
 0x08,0xbf = it eq
-// 0x51,0xea,0x04,0x04 = orrseq.w r4, r1, r4
+0x51,0xea,0x04,0x04 = orrseq.w r4, r1, r4
 0x08,0xbf = it eq
-// 0x0f,0x43 = orreq r7, r1
+0x0f,0x43 = orreq r7, r1
 0x08,0xbf = it eq
-// 0x0f,0x43 = orreq r7, r1
+0x0f,0x43 = orreq r7, r1
 0x08,0xbf = it eq
-// 0x41,0xea,0x08,0x08 = orreq.w r8, r1, r8
+0x41,0xea,0x08,0x08 = orreq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x48,0xea,0x01,0x08 = orreq.w r8, r8, r1
+0x48,0xea,0x01,0x08 = orreq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x48,0xea,0x00,0x00 = orreq.w r0, r8, r0
+0x48,0xea,0x00,0x00 = orreq.w r0, r8, r0
 0x08,0xbf = it eq
-// 0x40,0xea,0x08,0x00 = orreq.w r0, r0, r8
+0x40,0xea,0x08,0x00 = orreq.w r0, r0, r8
 0x08,0xbf = it eq
-// 0x42,0xea,0x41,0x02 = orreq.w r2, r2, r1, lsl #1
+0x42,0xea,0x41,0x02 = orreq.w r2, r2, r1, lsl #1
 0x08,0xbf = it eq
-// 0x41,0xea,0x52,0x02 = orreq.w r2, r1, r2, lsr #1
+0x41,0xea,0x52,0x02 = orreq.w r2, r1, r2, lsr #1
 0x32,0xea,0x01,0x03 = bics.w r3, r2, r1
 0x8a,0x43 = bics r2, r1
 0x32,0xea,0x01,0x01 = bics.w r1, r2, r1
 0x32,0xea,0x01,0x02 = bics.w r2, r2, r1
 0x31,0xea,0x00,0x00 = bics.w r0, r1, r0
 0x21,0xea,0x00,0x00 = bic.w r0, r1, r0
-// 0x8f,0x43 = bics r7, r1
+0x8f,0x43 = bics r7, r1
 0x31,0xea,0x08,0x08 = bics.w r8, r1, r8
 0x38,0xea,0x01,0x08 = bics.w r8, r8, r1
 0x38,0xea,0x07,0x07 = bics.w r7, r8, r7
@@ -352,28 +388,28 @@
 0x33,0xea,0x41,0x03 = bics.w r3, r3, r1, lsl #1
 0x31,0xea,0x54,0x04 = bics.w r4, r1, r4, lsr #1
 0x08,0xbf = it eq
-// 0x22,0xea,0x01,0x00 = biceq.w r0, r2, r1
+0x22,0xea,0x01,0x00 = biceq.w r0, r2, r1
 0x08,0xbf = it eq
-// 0x8d,0x43 = biceq r5, r1
+0x8d,0x43 = biceq r5, r1
 0x08,0xbf = it eq
-// 0x25,0xea,0x01,0x01 = biceq.w r1, r5, r1
+0x25,0xea,0x01,0x01 = biceq.w r1, r5, r1
 0x08,0xbf = it eq
-// 0x24,0xea,0x01,0x04 = biceq.w r4, r4, r1
+0x24,0xea,0x01,0x04 = biceq.w r4, r4, r1
 0x08,0xbf = it eq
-// 0x21,0xea,0x02,0x02 = biceq.w r2, r1, r2
+0x21,0xea,0x02,0x02 = biceq.w r2, r1, r2
 0x08,0xbf = it eq
-// 0x31,0xea,0x05,0x05 = bicseq.w r5, r1, r5
+0x31,0xea,0x05,0x05 = bicseq.w r5, r1, r5
 0x08,0xbf = it eq
-// 0x8f,0x43 = biceq r7, r1
+0x8f,0x43 = biceq r7, r1
 0x08,0xbf = it eq
-// 0x21,0xea,0x08,0x08 = biceq.w r8, r1, r8
+0x21,0xea,0x08,0x08 = biceq.w r8, r1, r8
 0x08,0xbf = it eq
-// 0x28,0xea,0x01,0x08 = biceq.w r8, r8, r1
+0x28,0xea,0x01,0x08 = biceq.w r8, r8, r1
 0x08,0xbf = it eq
-// 0x28,0xea,0x00,0x00 = biceq.w r0, r8, r0
+0x28,0xea,0x00,0x00 = biceq.w r0, r8, r0
 0x08,0xbf = it eq
-// 0x22,0xea,0x08,0x02 = biceq.w r2, r2, r8
+0x22,0xea,0x08,0x02 = biceq.w r2, r2, r8
 0x08,0xbf = it eq
-// 0x24,0xea,0x41,0x04 = biceq.w r4, r4, r1, lsl #1
+0x24,0xea,0x41,0x04 = biceq.w r4, r4, r1, lsl #1
 0x08,0xbf = it eq
-// 0x21,0xea,0x55,0x05 = biceq.w r5, r1, r5, lsr #1
+0x21,0xea,0x55,0x05 = biceq.w r5, r1, r5, lsr #1
diff --git a/suite/MC/ARM/thumb2-pldw.s.cs b/suite/MC/ARM/thumb2-pldw.s.cs
index 0c367168f..9bd52250e 100644
--- a/suite/MC/ARM/thumb2-pldw.s.cs
+++ b/suite/MC/ARM/thumb2-pldw.s.cs
@@ -1,2 +1,2 @@
 # CS_ARCH_ARM, CS_MODE_THUMB, None
-0xb0,0xf8,0x01,0xf1 = pldw [r0, #257]
+0xb0,0xf8,0x01,0xf1 = pldw [r0, #0x101]
diff --git a/suite/MC/ARM/thumb_rewrites.s.cs b/suite/MC/ARM/thumb_rewrites.s.cs
new file mode 100644
index 000000000..377e967c1
--- /dev/null
+++ b/suite/MC/ARM/thumb_rewrites.s.cs
@@ -0,0 +1,32 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xc9,0x1c = adds r1, r1, #3
+0x03,0x31 = adds r1, #3
+0x08,0x30 = adds r0, #8
+0x00,0x18 = adds r0, r0, r0
+0x40,0x44 = add r0, r8
+0x41,0x44 = add r1, r8
+0x85,0x44 = add sp, r0
+0x6c,0x44 = add r4, sp, r4
+0x08,0xb0 = add sp, #0x20
+0xfe,0xad = add r5, sp, #0x3f8
+0x08,0x44 = add r0, r1
+0x1a,0x44 = add r2, r3
+0x00,0x1a = subs r0, r0, r0
+0x5b,0x1f = subs r3, r3, #5
+0x05,0x3b = subs r3, #5
+0x08,0x3a = subs r2, #8
+0x84,0xb0 = sub sp, #0x10
+0x08,0x40 = ands r0, r1
+0x08,0x40 = ands r0, r1
+0x48,0x40 = eors r0, r1
+0x48,0x40 = eors r0, r1
+0x88,0x40 = lsls r0, r1
+0xc8,0x40 = lsrs r0, r1
+0x08,0x41 = asrs r0, r1
+0x48,0x41 = adcs r0, r1
+0x48,0x41 = adcs r0, r1
+0x88,0x41 = sbcs r0, r1
+0xc8,0x41 = rors r0, r1
+0x08,0x43 = orrs r0, r1
+0x08,0x43 = orrs r0, r1
+0x88,0x43 = bics r0, r1
diff --git a/suite/MC/ARM/thumbv7em.s.cs b/suite/MC/ARM/thumbv7em.s.cs
new file mode 100644
index 000000000..6d915cbc6
--- /dev/null
+++ b/suite/MC/ARM/thumbv7em.s.cs
@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None
+0x80,0xf3,0x00,0x84 = msr apsr_g, r0
+0x80,0xf3,0x00,0x8c = msr apsr_nzcvqg, r0
+0x80,0xf3,0x01,0x84 = msr iapsr_g, r0
+0x80,0xf3,0x01,0x8c = msr iapsr_nzcvqg, r0
+0x80,0xf3,0x02,0x84 = msr eapsr_g, r0
+0x80,0xf3,0x02,0x8c = msr eapsr_nzcvqg, r0
+0x80,0xf3,0x03,0x84 = msr xpsr_g, r0
+0x80,0xf3,0x03,0x8c = msr xpsr_nzcvqg, r0
diff --git a/suite/MC/ARM/thumbv7m.s.cs b/suite/MC/ARM/thumbv7m.s.cs
new file mode 100644
index 000000000..b18931c11
--- /dev/null
+++ b/suite/MC/ARM/thumbv7m.s.cs
@@ -0,0 +1,7 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None
+0xef,0xf3,0x11,0x80 = mrs r0, basepri
+0xef,0xf3,0x12,0x80 = mrs r0, basepri_max
+0xef,0xf3,0x13,0x80 = mrs r0, faultmask
+0x80,0xf3,0x11,0x88 = msr basepri, r0
+0x80,0xf3,0x12,0x88 = msr basepri_max, r0
+0x80,0xf3,0x13,0x88 = msr faultmask, r0
diff --git a/suite/MC/ARM/thumbv8.1m-vmrs-vmsr.s.cs b/suite/MC/ARM/thumbv8.1m-vmrs-vmsr.s.cs
new file mode 100644
index 000000000..677c7770c
--- /dev/null
+++ b/suite/MC/ARM/thumbv8.1m-vmrs-vmsr.s.cs
@@ -0,0 +1,12 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0xe2,0xee,0x10,0x0a = vmsr fpscr_nzcvqc, r0
+0xf2,0xee,0x10,0xaa = vmrs r10, fpscr_nzcvqc
+0xfe,0xee,0x10,0x0a = vmrs r0, fpcxtns
+0xee,0xee,0x10,0xaa = vmsr fpcxtns, r10
+0xef,0xee,0x10,0x5a = vmsr fpcxts, r5
+0xfe,0xee,0x10,0x3a = vmrs r3, fpcxtns
+0xff,0xee,0x10,0x0a = vmrs r0, fpcxts
+0xfc,0xee,0x10,0x0a = vmrs r0, vpr
+0xfd,0xee,0x10,0x4a = vmrs r4, p0
+0xec,0xee,0x10,0x0a = vmsr vpr, r0
+0xed,0xee,0x10,0x4a = vmsr p0, r4
diff --git a/suite/MC/ARM/thumbv8.1m.s.cs b/suite/MC/ARM/thumbv8.1m.s.cs
new file mode 100644
index 000000000..dd183b419
--- /dev/null
+++ b/suite/MC/ARM/thumbv8.1m.s.cs
@@ -0,0 +1,166 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
+0x42,0xf0,0x01,0xe0 = dls lr, r2
+0x4e,0xf0,0x01,0xe0 = dls lr, lr
+0x40,0xf0,0x01,0xe0 = dls lr, r0
+0x41,0xf0,0x01,0xe0 = dls lr, r1
+0x4a,0xf0,0x01,0xe0 = dls lr, r10
+0x4b,0xf0,0x01,0xe0 = dls lr, r11
+0x4c,0xf0,0x01,0xe0 = dls lr, r12
+0x42,0xf0,0x01,0xe0 = dls lr, r2
+0x43,0xf0,0x01,0xe0 = dls lr, r3
+0x45,0xf0,0x01,0xe0 = dls lr, r5
+0x46,0xf0,0x01,0xe0 = dls lr, r6
+0x47,0xf0,0x01,0xe0 = dls lr, r7
+0x48,0xf0,0x01,0xe0 = dls lr, r8
+0x49,0xf0,0x01,0xe0 = dls lr, r9
+0x2f,0xf0,0x35,0xc8 = le #-0x6a
+0x2f,0xf0,0x4b,0xc2 = le #-0x494
+0x2f,0xf0,0x5d,0xca = le #-0x4ba
+0x2f,0xf0,0x77,0xc2 = le #-0x4ec
+0x2f,0xf0,0x77,0xca = le #-0x4ee
+0x2f,0xf0,0x83,0xc2 = le #-0x504
+0x2f,0xf0,0x83,0xca = le #-0x506
+0x2f,0xf0,0x0b,0xc3 = le #-0x614
+0x2f,0xf0,0x59,0xc8 = le #-0xb2
+0x2f,0xf0,0xad,0xcb = le #-0x75a
+0x2f,0xf0,0xb7,0xc3 = le #-0x76c
+0x2f,0xf0,0xbb,0xcb = le #-0x776
+0x2f,0xf0,0x0f,0xc4 = le #-0x81c
+0x2f,0xf0,0x6d,0xcc = le #-0x8da
+0x2f,0xf0,0x8b,0xc4 = le #-0x914
+0x2f,0xf0,0x8d,0xc4 = le #-0x918
+0x2f,0xf0,0xcd,0xc4 = le #-0x998
+0x2f,0xf0,0x7b,0xc8 = le #-0xf6
+0x2f,0xf0,0xd7,0xc4 = le #-0x9ac
+0x2f,0xf0,0x09,0xcd = le #-0xa12
+0x2f,0xf0,0x83,0xc8 = le #-0x106
+0x2f,0xf0,0x33,0xc5 = le #-0xa64
+0x2f,0xf0,0x51,0xcd = le #-0xaa2
+0x2f,0xf0,0x9b,0xc5 = le #-0xb34
+0x2f,0xf0,0xa1,0xcd = le #-0xb42
+0x2f,0xf0,0x29,0xce = le #-0xc52
+0x2f,0xf0,0x65,0xce = le #-0xcca
+0x2f,0xf0,0x8d,0xc6 = le #-0xd18
+0x2f,0xf0,0xa9,0xc8 = le #-0x152
+0x2f,0xf0,0xc1,0xce = le #-0xd82
+0x2f,0xf0,0xcd,0xc6 = le #-0xd98
+0x2f,0xf0,0xeb,0xce = le #-0xdd6
+0x2f,0xf0,0x1f,0xc7 = le #-0xe3c
+0x2f,0xf0,0x2f,0xc7 = le #-0xe5c
+0x2f,0xf0,0x37,0xc7 = le #-0xe6c
+0x2f,0xf0,0x8b,0xc7 = le #-0xf14
+0x2f,0xf0,0xc9,0xcf = le #-0xf92
+0x2f,0xf0,0xd3,0xcf = le #-0xfa6
+0x2f,0xf0,0xe1,0xcf = le #-0xfc2
+0x2f,0xf0,0xef,0xc7 = le #-0xfdc
+0x2f,0xf0,0xf3,0xc7 = le #-0xfe4
+0x2f,0xf0,0xef,0xc8 = le #-0x1de
+0x2f,0xf0,0x11,0xc1 = le #-0x220
+0x2f,0xf0,0x25,0xc9 = le #-0x24a
+0x2f,0xf0,0x2f,0xc9 = le #-0x25e
+0x2f,0xf0,0x49,0xc1 = le #-0x290
+0x2f,0xf0,0x73,0xc1 = le #-0x2e4
+0x2f,0xf0,0x7d,0xc9 = le #-0x2fa
+0x2f,0xf0,0xaf,0xc9 = le #-0x35e
+0x2f,0xf0,0xb3,0xc9 = le #-0x366
+0x0f,0xf0,0x1d,0xc2 = le lr, #-0x438
+0x0f,0xf0,0x29,0xc2 = le lr, #-0x450
+0x0f,0xf0,0x41,0xc2 = le lr, #-0x480
+0x0f,0xf0,0xdb,0xca = le lr, #-0x5b6
+0x0f,0xf0,0xdf,0xca = le lr, #-0x5be
+0x0f,0xf0,0x27,0xc3 = le lr, #-0x64c
+0x0f,0xf0,0x31,0xc3 = le lr, #-0x660
+0x0f,0xf0,0x4f,0xcb = le lr, #-0x69e
+0x0f,0xf0,0x59,0xcb = le lr, #-0x6b2
+0x0f,0xf0,0x9d,0xcb = le lr, #-0x73a
+0x0f,0xf0,0xab,0xcb = le lr, #-0x756
+0x0f,0xf0,0xb5,0xc3 = le lr, #-0x768
+0x0f,0xf0,0xc1,0xcb = le lr, #-0x782
+0x0f,0xf0,0xc3,0xcb = le lr, #-0x786
+0x0f,0xf0,0x01,0xc8 = le lr, #-2
+0x0f,0xf0,0x1d,0xc4 = le lr, #-0x838
+0x0f,0xf0,0x23,0xc4 = le lr, #-0x844
+0x0f,0xf0,0x31,0xc4 = le lr, #-0x860
+0x0f,0xf0,0x47,0xc4 = le lr, #-0x88c
+0x0f,0xf0,0x95,0xc4 = le lr, #-0x928
+0x0f,0xf0,0xcd,0xc4 = le lr, #-0x998
+0x0f,0xf0,0x19,0xc5 = le lr, #-0xa30
+0x0f,0xf0,0x1d,0xc5 = le lr, #-0xa38
+0x0f,0xf0,0x1f,0xcd = le lr, #-0xa3e
+0x0f,0xf0,0x3d,0xc5 = le lr, #-0xa78
+0x0f,0xf0,0x43,0xcd = le lr, #-0xa86
+0x0f,0xf0,0x91,0xcd = le lr, #-0xb22
+0x0f,0xf0,0x97,0xc5 = le lr, #-0xb2c
+0x0f,0xf0,0xdf,0xc5 = le lr, #-0xbbc
+0x0f,0xf0,0xe5,0xcd = le lr, #-0xbca
+0x0f,0xf0,0x99,0xc0 = le lr, #-0x130
+0x0f,0xf0,0x0d,0xce = le lr, #-0xc1a
+0x0f,0xf0,0x4f,0xc6 = le lr, #-0xc9c
+0x0f,0xf0,0x7b,0xc6 = le lr, #-0xcf4
+0x0f,0xf0,0x83,0xc6 = le lr, #-0xd04
+0x0f,0xf0,0x8d,0xce = le lr, #-0xd1a
+0x0f,0xf0,0xbd,0xcf = le lr, #-0xf7a
+0x0f,0xf0,0xe5,0xcf = le lr, #-0xfca
+0x0f,0xf0,0xeb,0xc7 = le lr, #-0xfd4
+0x0f,0xf0,0xe5,0xc8 = le lr, #-0x1ca
+0x0f,0xf0,0x1d,0xc0 = le lr, #-0x38
+0x0f,0xf0,0x23,0xc9 = le lr, #-0x246
+0x0f,0xf0,0x53,0xc1 = le lr, #-0x2a4
+0x0f,0xf0,0x79,0xc1 = le lr, #-0x2f0
+0x0f,0xf0,0x27,0xc0 = le lr, #-0x4c
+0x0f,0xf0,0x91,0xc9 = le lr, #-0x322
+0x0f,0xf0,0xaf,0xc9 = le lr, #-0x35e
+0x0f,0xf0,0xc3,0xc9 = le lr, #-0x386
+0x0f,0xf0,0xe5,0xc1 = le lr, #-0x3c8
+0x4e,0xf0,0x55,0xc2 = wls lr, lr, #0x4a8
+0x4e,0xf0,0x2b,0xcc = wls lr, lr, #0x856
+0x4e,0xf0,0xe1,0xc9 = wls lr, lr, #0x3c2
+0x40,0xf0,0x43,0xc3 = wls lr, r0, #0x684
+0x40,0xf0,0x49,0xcd = wls lr, r0, #0xa92
+0x40,0xf0,0xe9,0xcd = wls lr, r0, #0xbd2
+0x40,0xf0,0xb7,0xc6 = wls lr, r0, #0xd6c
+0x41,0xf0,0x13,0xc2 = wls lr, r1, #0x424
+0x41,0xf0,0xe3,0xc7 = wls lr, r1, #0xfc4
+0x41,0xf0,0x0d,0xc9 = wls lr, r1, #0x21a
+0x4a,0xf0,0xbf,0xc2 = wls lr, r10, #0x57c
+0x4a,0xf0,0xc1,0xc2 = wls lr, r10, #0x580
+0x4a,0xf0,0x9b,0xcc = wls lr, r10, #0x936
+0x4a,0xf0,0xfb,0xcf = wls lr, r10, #0xff6
+0x4b,0xf0,0xd1,0xca = wls lr, r11, #0x5a2
+0x4b,0xf0,0x3b,0xcd = wls lr, r11, #0xa76
+0x4b,0xf0,0x0d,0xcf = wls lr, r11, #0xe1a
+0x4c,0xf0,0x67,0xc8 = wls lr, r12, #0xce
+0x4c,0xf0,0xa9,0xc5 = wls lr, r12, #0xb50
+0x4c,0xf0,0x5d,0xce = wls lr, r12, #0xcba
+0x42,0xf0,0x55,0xce = wls lr, r2, #0xcaa
+0x42,0xf0,0x7d,0xc7 = wls lr, r2, #0xef8
+0x42,0xf0,0xb5,0xc1 = wls lr, r2, #0x368
+0x43,0xf0,0xdd,0xce = wls lr, r3, #0xdba
+0x43,0xf0,0x1b,0xc7 = wls lr, r3, #0xe34
+0x43,0xf0,0xb3,0xcf = wls lr, r3, #0xf66
+0x43,0xf0,0x65,0xc1 = wls lr, r3, #0x2c8
+0x44,0xf0,0x31,0xcc = wls lr, r4, #0x862
+0x44,0xf0,0xdb,0xcc = wls lr, r4, #0x9b6
+0x45,0xf0,0xb9,0xcb = wls lr, r5, #0x772
+0x45,0xf0,0xa3,0xc6 = wls lr, r5, #0xd44
+0x46,0xf0,0x7f,0xce = wls lr, r6, #0xcfe
+0x46,0xf0,0xd1,0xc0 = wls lr, r6, #0x1a0
+0x46,0xf0,0xd3,0xc8 = wls lr, r6, #0x1a6
+0x47,0xf0,0xc9,0xce = wls lr, r7, #0xd92
+0x47,0xf0,0x1d,0xc7 = wls lr, r7, #0xe38
+0x48,0xf0,0x47,0xc5 = wls lr, r8, #0xa8c
+0x49,0xf0,0x2d,0xca = wls lr, r9, #0x45a
+0x49,0xf0,0xe1,0xc3 = wls lr, r9, #0x7c0
+0x49,0xf0,0x57,0xcf = wls lr, r9, #0xeae
+0x49,0xf0,0x6b,0xc7 = wls lr, r9, #0xed4
+0x52,0xea,0x22,0x9e = cinc lr, r2, lo
+0x57,0xea,0x47,0x9e = cinc lr, r7, pl
+0x5c,0xea,0x3c,0xae = cinv lr, r12, hs
+0x5a,0xea,0x3a,0xbe = cneg lr, r10, hs
+0x59,0xea,0x7b,0x89 = csel r9, r9, r11, vc
+0x5f,0xea,0x1f,0x9e = cset lr, eq
+0x5f,0xea,0x3f,0xae = csetm lr, hs
+0x5a,0xea,0xd7,0x9e = csinc lr, r10, r7, le
+0x55,0xea,0x2f,0xae = csinv lr, r5, zr, hs
+0x52,0xea,0x42,0xae = cinv lr, r2, pl
+0x50,0xea,0x01,0x80 = csel r0, r0, r1, eq
diff --git a/suite/MC/ARM/thumbv8m.s.cs b/suite/MC/ARM/thumbv8m.s.cs
new file mode 100644
index 000000000..236be89a5
--- /dev/null
+++ b/suite/MC/ARM/thumbv8m.s.cs
@@ -0,0 +1,47 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0xbf,0xf3,0x6f,0x8f = isb sy
+0x92,0xfb,0xf3,0xf1 = sdiv r1, r2, r3
+0xb2,0xfb,0xf3,0xf1 = udiv r1, r2, r3
+0xbf,0xf3,0x2f,0x8f = clrex
+0x52,0xe8,0x01,0x1f = ldrex r1, [r2, #4]
+0xd2,0xe8,0x4f,0x1f = ldrexb r1, [r2]
+0xd2,0xe8,0x5f,0x1f = ldrexh r1, [r2]
+0x43,0xe8,0x01,0x21 = strex r1, r2, [r3, #4]
+0xc3,0xe8,0x41,0x2f = strexb r1, r2, [r3]
+0xc3,0xe8,0x51,0x2f = strexh r1, r2, [r3]
+0x4f,0xf6,0xff,0x71 = movw r1, #0xffff
+0xcf,0xf6,0xff,0x71 = movt r1, #0xffff
+0xd2,0xe8,0xaf,0x1f = lda r1, [r2]
+0xd2,0xe8,0x8f,0x1f = ldab r1, [r2]
+0xd2,0xe8,0x9f,0x1f = ldah r1, [r2]
+0xc3,0xe8,0xaf,0x1f = stl r1, [r3]
+0xc3,0xe8,0x8f,0x1f = stlb r1, [r3]
+0xc3,0xe8,0x9f,0x1f = stlh r1, [r3]
+0xd2,0xe8,0xef,0x1f = ldaex r1, [r2]
+0xd2,0xe8,0xcf,0x1f = ldaexb r1, [r2]
+0xd2,0xe8,0xdf,0x1f = ldaexh r1, [r2]
+0xc3,0xe8,0xe1,0x2f = stlex r1, r2, [r3]
+0xc3,0xe8,0xc1,0x2f = stlexb r1, r2, [r3]
+0xc3,0xe8,0xd1,0x2f = stlexh r1, r2, [r3]
+0x7f,0xe9,0x7f,0xe9 = sg
+0x04,0x47 = bxns r0
+0x74,0x47 = bxns lr
+0x84,0x47 = blxns r0
+0x41,0xe8,0x00,0xf0 = tt r0, r1
+0x4d,0xe8,0x00,0xf0 = tt r0, sp
+0x41,0xe8,0x80,0xf0 = tta r0, r1
+0x41,0xe8,0x40,0xf0 = ttt r0, r1
+0x41,0xe8,0xc0,0xf0 = ttat r0, r1
+0xef,0xf3,0x88,0x81 = mrs r1, msp_ns
+0x82,0xf3,0x89,0x88 = msr psp_ns, r2
+0xef,0xf3,0x90,0x83 = mrs r3, primask_ns
+0x84,0xf3,0x94,0x88 = msr control_ns, r4
+0xef,0xf3,0x98,0x85 = mrs r5, sp_ns
+0xef,0xf3,0x0a,0x86 = mrs r6, msplim
+0xef,0xf3,0x0b,0x87 = mrs r7, psplim
+0x88,0xf3,0x0a,0x88 = msr msplim, r8
+0x89,0xf3,0x0b,0x88 = msr psplim, r9
+0xef,0xf3,0x8a,0x8a = mrs r10, msplim_ns
+0x8b,0xf3,0x8b,0x88 = msr psplim_ns, r11
+0xef,0xf3,0x92,0x88 = mrs r8, 0x92
+0x88,0xf3,0x92,0x80 = msr 0x92, r8
diff --git a/suite/MC/ARM/udf-arm.s.cs b/suite/MC/ARM/udf-arm.s.cs
new file mode 100644
index 000000000..7ae893892
--- /dev/null
+++ b/suite/MC/ARM/udf-arm.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xf0,0x00,0xf0,0xe7 = udf #0
diff --git a/suite/MC/ARM/udf-thumb-2.s.cs b/suite/MC/ARM/udf-thumb-2.s.cs
new file mode 100644
index 000000000..b18fb6cd9
--- /dev/null
+++ b/suite/MC/ARM/udf-thumb-2.s.cs
@@ -0,0 +1,3 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x00,0xde = udf #0
+0xf0,0xf7,0x00,0xa0 = udf.w #0
diff --git a/suite/MC/ARM/udf-thumb.s.cs b/suite/MC/ARM/udf-thumb.s.cs
new file mode 100644
index 000000000..2920cdfa6
--- /dev/null
+++ b/suite/MC/ARM/udf-thumb.s.cs
@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x00,0xde = udf #0
diff --git a/suite/MC/ARM/vmov-vmvn-replicate.s.cs b/suite/MC/ARM/vmov-vmvn-replicate.s.cs
new file mode 100644
index 000000000..9e87f255d
--- /dev/null
+++ b/suite/MC/ARM/vmov-vmvn-replicate.s.cs
@@ -0,0 +1,47 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x3f,0x2e,0x87,0xf3 = vmov.i64 d2, #0xffffffffffffffff
+0x7f,0x4e,0x87,0xf3 = vmov.i64 q2, #0xffffffffffffffff
+0x1f,0x2e,0x87,0xf3 = vmov.i8 d2, #0xff
+0x5f,0x4e,0x87,0xf3 = vmov.i8 q2, #0xff
+0x1b,0x2e,0x82,0xf3 = vmov.i8 d2, #0xab
+0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab
+0x1b,0x2e,0x82,0xf3 = vmov.i8 d2, #0xab
+0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab
+0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab
+0x5b,0x4e,0x82,0xf3 = vmov.i8 q2, #0xab
+0x3a,0x2e,0x82,0xf3 = vmov.i64 d2, #0xff00ff00ff00ff00
+0x7a,0x4e,0x82,0xf3 = vmov.i64 q2, #0xff00ff00ff00ff00
+0x15,0x28,0x82,0xf3 = vmov.i16 d2, #0xa5
+0x55,0x48,0x82,0xf3 = vmov.i16 q2, #0xa5
+0x15,0x28,0x82,0xf3 = vmov.i16 d2, #0xa5
+0x55,0x48,0x82,0xf3 = vmov.i16 q2, #0xa5
+0x15,0x2a,0x82,0xf3 = vmov.i16 d2, #0xa500
+0x55,0x4a,0x82,0xf3 = vmov.i16 q2, #0xa500
+0x15,0x2a,0x82,0xf3 = vmov.i16 d2, #0xa500
+0x55,0x4a,0x82,0xf3 = vmov.i16 q2, #0xa500
+0x15,0x20,0x82,0xf3 = vmov.i32 d2, #0xa5
+0x55,0x40,0x82,0xf3 = vmov.i32 q2, #0xa5
+0x15,0x2d,0x82,0xf3 = vmov.i32 d2, #0xa5ffff
+0x55,0x4d,0x82,0xf3 = vmov.i32 q2, #0xa5ffff
+0x10,0x2e,0x80,0xf2 = vmov.i8 d2, #0x0
+0x50,0x4e,0x80,0xf2 = vmov.i8 q2, #0x0
+0x10,0x2e,0x80,0xf2 = vmov.i8 d2, #0x0
+0x50,0x4e,0x80,0xf2 = vmov.i8 q2, #0x0
+0x14,0x2e,0x85,0xf2 = vmov.i8 d2, #0x54
+0x54,0x4e,0x85,0xf2 = vmov.i8 q2, #0x54
+0x14,0x2e,0x85,0xf2 = vmov.i8 d2, #0x54
+0x54,0x4e,0x85,0xf2 = vmov.i8 q2, #0x54
+0x14,0x2e,0x85,0xf2 = vmov.i8 d2, #0x54
+0x54,0x4e,0x85,0xf2 = vmov.i8 q2, #0x54
+0x35,0x28,0x82,0xf3 = vmvn.i16 d2, #0xa5
+0x75,0x48,0x82,0xf3 = vmvn.i16 q2, #0xa5
+0x35,0x28,0x82,0xf3 = vmvn.i16 d2, #0xa5
+0x75,0x48,0x82,0xf3 = vmvn.i16 q2, #0xa5
+0x35,0x2a,0x82,0xf3 = vmvn.i16 d2, #0xa500
+0x75,0x4a,0x82,0xf3 = vmvn.i16 q2, #0xa500
+0x35,0x2a,0x82,0xf3 = vmvn.i16 d2, #0xa500
+0x75,0x4a,0x82,0xf3 = vmvn.i16 q2, #0xa500
+0x35,0x20,0x82,0xf3 = vmvn.i32 d2, #0xa5
+0x75,0x40,0x82,0xf3 = vmvn.i32 q2, #0xa5
+0x35,0x2d,0x82,0xf3 = vmvn.i32 d2, #0xa5ffff
+0x75,0x4d,0x82,0xf3 = vmvn.i32 q2, #0xa5ffff
diff --git a/suite/MC/ARM/vmovhr.s.cs b/suite/MC/ARM/vmovhr.s.cs
new file mode 100644
index 000000000..56a516f84
--- /dev/null
+++ b/suite/MC/ARM/vmovhr.s.cs
@@ -0,0 +1,5 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
+0x16,0xee,0x90,0x09 = vmov.f16 r0, s13
+0x0a,0xee,0x90,0x19 = vmov.f16 s21, r1
+0x01,0xee,0x10,0xd9 = vmov.f16 s2, sp
+0x12,0xee,0x90,0xd9 = vmov.f16 sp, s5
diff --git a/suite/MC/ARM/vscclrm-asm.s.cs b/suite/MC/ARM/vscclrm-asm.s.cs
new file mode 100644
index 000000000..89a682c12
--- /dev/null
+++ b/suite/MC/ARM/vscclrm-asm.s.cs
@@ -0,0 +1,10 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
+0x9f,0xec,0x04,0x0a = vscclrm {s0, s1, s2, s3, vpr}
+0xdf,0xec,0x06,0x1a = vscclrm {s3, s4, s5, s6, s7, s8, vpr}
+0x9f,0xec,0x0c,0x9a = vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}
+0xdf,0xec,0x01,0xfa = vscclrm {s31, vpr}
+0x9f,0xec,0x04,0x0b = vscclrm {d0, d1, vpr}
+0x9f,0xec,0x08,0x0b = vscclrm {d0, d1, d2, d3, vpr}
+0x9f,0xec,0x06,0x5b = vscclrm {d5, d6, d7, vpr}
+0x88,0xbf = it hi
+0xdf,0xec,0x1d,0x1a = vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
diff --git a/suite/MC/ARM/vstrldr_sys.s.cs b/suite/MC/ARM/vstrldr_sys.s.cs
new file mode 100644
index 000000000..d8fcc88a5
--- /dev/null
+++ b/suite/MC/ARM/vstrldr_sys.s.cs
@@ -0,0 +1,48 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x80,0xed,0x80,0x2f = vstr fpscr, [r0]
+0x09,0xed,0x86,0x4f = vstr fpscr_nzcvqc, [r9, #-0x18]
+0x29,0xed,0x86,0x4f = vstr fpscr_nzcvqc, [r9, #-0x18]!
+0x29,0xec,0x86,0x4f = vstr fpscr_nzcvqc, [r9], #-0x18
+0x88,0xbf = it hi
+0x80,0xed,0x80,0x2f = vstrhi fpscr, [r0]
+0x90,0xed,0x80,0x2f = vldr fpscr, [r0]
+0x19,0xed,0x86,0x4f = vldr fpscr_nzcvqc, [r9, #-0x18]
+0x39,0xed,0x86,0x4f = vldr fpscr_nzcvqc, [r9, #-0x18]!
+0x39,0xec,0x86,0x4f = vldr fpscr_nzcvqc, [r9], #-0x18
+0x3d,0xec,0x8d,0x4f = vldr fpscr_nzcvqc, [sp], #-0x34
+0x88,0xbf = it hi
+0x90,0xed,0x80,0x2f = vldrhi fpscr, [r0]
+0xcc,0xed,0xff,0xef = vstr fpcxts, [r12, #0x1fc]
+0xec,0xed,0xff,0xef = vstr fpcxts, [r12, #0x1fc]!
+0xec,0xec,0xff,0xef = vstr fpcxts, [r12], #0x1fc
+0x6d,0xec,0x86,0xef = vstr fpcxts, [sp], #-0x18
+0xdc,0xed,0xff,0xef = vldr fpcxts, [r12, #0x1fc]
+0xfc,0xed,0xff,0xef = vldr fpcxts, [r12, #0x1fc]!
+0xfc,0xec,0xff,0xef = vldr fpcxts, [r12], #0x1fc
+0x7d,0xec,0x86,0xef = vldr fpcxts, [sp], #-0x18
+0xc0,0xed,0x80,0xcf = vstr fpcxtns, [r0]
+0x49,0xed,0x86,0xcf = vstr fpcxtns, [r9, #-0x18]
+0xc6,0xed,0xfd,0xcf = vstr fpcxtns, [r6, #0x1f4]
+0x4e,0xed,0xff,0xcf = vstr fpcxtns, [lr, #-0x1fc]
+0xcc,0xed,0xff,0xcf = vstr fpcxtns, [r12, #0x1fc]
+0x6d,0xec,0x86,0xcf = vstr fpcxtns, [sp], #-0x18
+0xd0,0xed,0x80,0xcf = vldr fpcxtns, [r0]
+0x59,0xed,0x86,0xcf = vldr fpcxtns, [r9, #-0x18]
+0xd6,0xed,0xfd,0xcf = vldr fpcxtns, [r6, #0x1f4]
+0x5e,0xed,0xff,0xcf = vldr fpcxtns, [lr, #-0x1fc]
+0xdc,0xed,0xff,0xcf = vldr fpcxtns, [r12, #0x1fc]
+0x7d,0xec,0x86,0xcf = vldr fpcxtns, [sp], #-0x18
+0xc6,0xed,0xfd,0x8f = vstr vpr, [r6, #0x1f4]
+0x4e,0xed,0xff,0xaf = vstr p0, [lr, #-0x1fc]
+0xe6,0xed,0xfd,0x8f = vstr vpr, [r6, #0x1f4]!
+0x6e,0xed,0xff,0xaf = vstr p0, [lr, #-0x1fc]!
+0xe6,0xec,0xfd,0x8f = vstr vpr, [r6], #0x1f4
+0x6e,0xec,0xff,0xaf = vstr p0, [lr], #-0x1fc
+0x6d,0xec,0x86,0xaf = vstr p0, [sp], #-0x18
+0xd6,0xed,0xfd,0x8f = vldr vpr, [r6, #0x1f4]
+0x5e,0xed,0xff,0xaf = vldr p0, [lr, #-0x1fc]
+0xf6,0xed,0xfd,0x8f = vldr vpr, [r6, #0x1f4]!
+0x7e,0xed,0xff,0xaf = vldr p0, [lr, #-0x1fc]!
+0xf6,0xec,0xfd,0x8f = vldr vpr, [r6], #0x1f4
+0x7e,0xec,0xff,0xaf = vldr p0, [lr], #-0x1fc
+0x7d,0xec,0x86,0xaf = vldr p0, [sp], #-0x18
diff --git a/suite/MC/README b/suite/MC/README
index b39d13f11..7722a3544 100644
--- a/suite/MC/README
+++ b/suite/MC/README
@@ -1,10 +1,55 @@
-Input files for testing Capstone engine.
+## Input files for testing Capstone engine.
 
-Format of input files:
+Input files used to test instructions of architectures and modes.
 
+The test cases are taken from `llvm/test/MC`. Note that the LLVM tests
+are for **encoding** of instructions (`asm_string -> bytes`).
+
+We test the decoding (`bytes -> asm_string`).
+A few tests might decode to a different asm string than
+used to encode the instruction (because the behavior
+of instructions can be equivalent).
+
+Fix the obvious broken tests first and test the rest
+against `llvm-objdump`.
+
+### Update test files
+
+Run the update script with the paths to LLVM's `MC` test directories
+
+```
+cd capstone/suite/MC
+./Update.py -a <ARCH> -d llvm-project/llvm/test/MC
+./Update.py -a <ARCH> -d llvm-project/llvm/test/MC/Disassembler
+```
+
+You can update more fine grained. Check the help to get the possible options.
+
+### Test file formatting
+
+**Format of input files:**
+```
 # ARCH, MODE, OPTION
 hexcode = assembly
+```
 
-Format of issue file:
-# ARCH, MODE, OPTION
-hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count
\ No newline at end of file
+**Example**
+```
+# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
+0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
+...
+```
+
+**Format of issue file:**
+
+```
+!# ARCH, MODE, OPTION
+hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count
+```
+
+**Example**
+```
+!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
+0xc0,0x1e,0x0c,0x4e == mov v0.s[1], w22 ; operands[0].vas: 0xb ; operands[0].vector_index: 1
+...
+```
diff --git a/suite/MC/Update.py b/suite/MC/Update.py
new file mode 100755
index 000000000..1e4851254
--- /dev/null
+++ b/suite/MC/Update.py
@@ -0,0 +1,304 @@
+#!/usr/bin/env python3
+
+from pathlib import Path
+
+import argparse
+import re
+import os
+
+
+def cwd():
+    """Return current working directory."""
+    return os.path.dirname(os.path.realpath(__file__))
+
+
+def fatal_error(msg: str) -> None:
+    """Prints an error message and exists with error code 1."""
+    print(f"[x] {msg}")
+    exit(1)
+
+
+def warn(msg: str) -> None:
+    """Prints a warning message."""
+    print(f"[!] {msg}")
+
+
+def info(msg: str) -> None:
+    """Prints an info message."""
+    print(f"[*] {msg}")
+
+
+def check_paths(llvm_dir: Path, arch: str) -> None:
+    """Checks all relevant directories for errors and if they exist."""
+    if not llvm_dir.exists():
+        fatal_error(f"{llvm_dir} does not exist.")
+
+    if not llvm_dir.is_dir():
+        fatal_error(f"{llvm_dir} is not a directory.")
+
+    out_dir: Path = Path(cwd()).joinpath(arch)
+    if not out_dir.exists():
+        fatal_error(f"Output directory {out_dir} does not exist.")
+
+    if not out_dir.is_dir():
+        fatal_error(f"Output directory {out_dir} is not a directory.")
+
+    arch_dir = llvm_dir.joinpath(arch)
+    if not arch_dir.exists():
+        fatal_error(f"Test file directory {arch_dir} does not exist.")
+
+    if not arch_dir.is_dir():
+        fatal_error(f"Test file directory {arch_dir} is not a directory.")
+
+
+def get_included_files(
+    arch_dir: Path,
+    out_path: Path,
+    included_files: set[str],
+    excluded_files: set[str] = None,
+) -> list[tuple[Path, Path]]:
+    """
+    Generates the file list to update. Only the files listed
+    via command line arguments are added.
+    """
+    files = list()
+    file: Path
+    for file in arch_dir.iterdir():
+        stem = file.stem
+        if stem not in included_files:
+            continue
+        if excluded_files and stem in excluded_files:
+            included_files.remove(stem)
+            continue
+
+        included_files.remove(stem)
+        files.append((file, out_path.joinpath(file.name + ".cs")))
+
+    if len(included_files) != 0:
+        warn(
+            f"Could not find {', '.join(included_files)} in the LLVM test files."
+        )
+
+    return files
+
+
+def get_all_files(
+    arch_dir: Path,
+    out_path: Path,
+    excluded_files: set[str] = None,
+) -> list[tuple[Path, Path]]:
+    """
+    Generates the file list to update. All files of an
+    architecture are added.
+    """
+    files = list()
+    file: Path
+    for file in arch_dir.iterdir():
+        stem = file.stem
+        if excluded_files and stem in excluded_files:
+            continue
+
+        files.append((file, out_path.joinpath(file.name + ".cs")))
+    return files
+
+
+def get_file_list(
+    llvm_dir: Path,
+    arch: str = None,
+    excluded_files: set[str] = None,
+    included_files: set[str] = None,
+) -> list[tuple[Path, Path]]:
+    """
+    Generates a list of files to update.
+    The list contains tuples of the form: (llvm_file_path, cs_file_path)
+    """
+
+    out_dir: Path = Path(cwd()).joinpath(arch)
+    arch_dir = llvm_dir.joinpath(arch)
+
+    if included_files and len(included_files) != 0:
+        return get_included_files(
+            arch_dir, out_dir, included_files, excluded_files
+        )
+    return get_all_files(arch_dir, out_dir, excluded_files)
+
+
+def create_new_test_file(arch: str, cs_file: Path) -> str:
+    """
+    Creates a new test files and asks for the tesst parameter for it.
+    :return: The test parameter string.
+    """
+    info(f"Add new test file: {cs_file}")
+    info("You need to provide the test parameters for it.")
+    test_parameters = f"# CS_ARCH_{arch.upper()}, "
+    test_parameters += input(
+        "\nAdd architecture mode of tests"
+        "(CS_MODE_THUMB, CS_MODE_BIG_ENDIAN, ...)\n"
+        "> "
+    )
+    test_parameters += ", "
+    test_parameters += input(
+        "\nAdd disassembly options for this test file"
+        "(CS_OPT_SYNTAX_NOREGNAME, CS_OPT_SYNTAX_ATT, None, ...)\n"
+        "> "
+    )
+    test_parameters += "\n"
+    cs_file.touch()
+    return test_parameters
+
+
+def get_test_parameters(cs_file: Path) -> str:
+    """
+    Extracts the test parameters string from
+    an existing Capstone test file.
+    """
+    with open(cs_file) as f:
+        line = f.readline()
+
+    # Check for "# CS_ARCH_<ARCH>, CS_MODE_<MODE>, ..." lines
+    regex = r"#\s*CS_ARCH_.+,\s*CS_MODE_.+,\s*.+"
+    if not re.search(regex, line):
+        fatal_error(
+            f"The first line in {cs_file} is not "
+            f"the test parameter line.\nLine: {line}"
+        )
+    return line
+
+
+def decimal_to_hex_fix(asm: str) -> str:
+    """
+    Replaces every immediate number in the asm string with its hex form.
+    If it is larger than the hex threshold.
+    """
+    # Defined in utils.h
+    hex_threshold = 9
+    matches = re.findall(r"([#\s]-?\d+)", asm)
+    if not matches:
+        return asm
+
+    for m in matches:
+        num = int(m[1:])
+        neg_num = num < 0
+        sign = ""
+        if neg_num:
+            num = num * -1
+            sign = "-"
+        if num < hex_threshold:
+            continue
+        prefix = m[0]
+        asm = re.sub(m, rf"{prefix}{sign}{hex(num)}", asm)
+    return asm
+
+
+def extract_tests(llvm_file: Path) -> str:
+    """
+    Extracts all compatible test cases in the given llvm_file
+    and returns them as string.
+    """
+    hex_encoding = r"(0x[a-fA-F0-9][a-fA-F0-9],?\s*)+"
+    asm_regex = r"(.*)"
+
+    test_case_patterns = [
+        rf"#?\s*@?\s*CHECK:\s+{asm_regex}\s+@\s+encoding:\s+\[({hex_encoding})\]",
+    ]
+
+    result = ""
+
+    if llvm_file.is_dir():
+        return result
+
+    f = open(llvm_file)
+    for line in f.readlines():
+        match = list()
+        for regex in test_case_patterns:
+            match: list = re.findall(regex, line)
+            if match:
+                break
+        if not match:
+            continue
+        match = match[0]
+        asm = re.sub(r"\s+", " ", match[0])
+        asm = asm.strip(" ")
+        asm = decimal_to_hex_fix(asm)
+        hexbytes = re.sub(r"\s", "", match[1])
+        result += f"{hexbytes} = {asm}\n"
+    f.close()
+    return result
+
+
+def update(
+    llvm_dir: Path,
+    arch: str,
+    excluded_files: set[str] = None,
+    included_files: set[str] = None,
+) -> None:
+    """
+    Updates all regression test files for Capstone.
+    """
+
+    check_paths(llvm_dir, arch)
+
+    files: list[tuple[Path, Path]] = get_file_list(
+        llvm_dir, arch, excluded_files, included_files
+    )
+
+    for file in files:
+        llvm_file = file[0]
+        cs_file = file[1]
+
+        cs_tests = extract_tests(llvm_file)
+        if cs_tests == "":
+            continue
+
+        if not cs_file.exists():
+            test_parameters = create_new_test_file(arch, cs_file)
+        else:
+            test_parameters = get_test_parameters(cs_file)
+
+        with open(cs_file, "w") as f:
+            f.write(test_parameters)
+            f.write(cs_tests)
+    info("Update done")
+
+
+def parse_args() -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        prog="Test file updater",
+        description="Synchronizes test files with LLVM",
+    )
+    parser.add_argument(
+        "-d",
+        dest="llvm_dir",
+        help="Path to the LLVM MC Disassembler test files.",
+        required=True,
+        type=Path,
+    )
+    parser.add_argument(
+        "-a",
+        dest="arch",
+        help="Name of architecture to update.",
+        choices=["ARM"],
+        required=True,
+    )
+    parser.add_argument(
+        "-e",
+        dest="excluded_files",
+        metavar="filename",
+        nargs="+",
+        help="File names to exclude from update (without file extension).",
+        type=list,
+    )
+    parser.add_argument(
+        "-f",
+        dest="included_files",
+        metavar="filename",
+        nargs="+",
+        help="Specific list of file names to update (without file extension).",
+    )
+    arguments = parser.parse_args()
+    return arguments
+
+
+if __name__ == "__main__":
+    args = parse_args()
+    update(args.llvm_dir, args.arch, args.excluded_files, args.included_files)
diff --git a/suite/arm/test_arm_regression.c b/suite/arm/test_arm_regression.c
index 31a46c25a..18b2d2644 100644
--- a/suite/arm/test_arm_regression.c
+++ b/suite/arm/test_arm_regression.c
@@ -114,7 +114,7 @@ static void snprint_insn_detail(char * buf, size_t * cur, size_t * left, cs_insn
 		}
 	}
 
-	if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID) {
+	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF) {
 		_this_printf("\tCode condition: %u\n", arm->cc);
 	}
 
@@ -122,7 +122,7 @@ static void snprint_insn_detail(char * buf, size_t * cur, size_t * left, cs_insn
 		_this_printf("\tUpdate-flags: True\n");
 	}
 
-	if (arm->writeback) {
+	if (ins->detail->writeback) {
 		_this_printf("\tWrite-back: True\n");
 	}
 
@@ -285,6 +285,7 @@ static void test_valids()
 	}};
 
 	struct valid_instructions *valid = NULL;
+
 	cs_insn *insn;
 	int i;
 	int j;
diff --git a/suite/auto-sync/.gitignore b/suite/auto-sync/.gitignore
new file mode 100644
index 000000000..629db61c1
--- /dev/null
+++ b/suite/auto-sync/.gitignore
@@ -0,0 +1,2 @@
+build/
+vendor/llvm_root
diff --git a/suite/auto-sync/CppTranslator/.gitignore b/suite/auto-sync/CppTranslator/.gitignore
new file mode 100644
index 000000000..f06d0bbb4
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/.gitignore
@@ -0,0 +1,2 @@
+.venv
+.idea/
diff --git a/suite/auto-sync/CppTranslator/Configurator.py b/suite/auto-sync/CppTranslator/Configurator.py
new file mode 100644
index 000000000..713e7cb7d
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Configurator.py
@@ -0,0 +1,87 @@
+import json
+from pathlib import Path
+
+from tree_sitter import Language, Parser
+import logging as log
+
+
+class Configurator:
+    """
+    Holds common setup procedures for the configuration.
+    It reads the configuration file, compiles languages and initializes the Parser.
+    """
+
+    arch: str
+    config_path: Path
+    ts_so_path: Path
+    ts_grammar_path: Path
+    config: dict = None
+    ts_cpp_lang: Language = None
+    parser: Parser = None
+
+    def __init__(self, arch: str, config_path: Path, ts_grammar_path: Path, ts_so_path: Path) -> None:
+        self.arch = arch
+        self.config_path = config_path
+        self.ts_so_path = ts_so_path
+        self.ts_grammar_path = ts_grammar_path
+        self.load_config()
+        self.ts_compile_cpp()
+        self.ts_set_cpp_language()
+        self.init_parser()
+
+    def get_arch(self) -> str:
+        return self.arch
+
+    def get_cpp_lang(self) -> Language:
+        if self.ts_cpp_lang:
+            return self.ts_cpp_lang
+        self.ts_set_cpp_language()
+        return self.ts_cpp_lang
+
+    def get_parser(self) -> Parser:
+        if self.parser:
+            return self.parser
+        self.init_parser()
+        return self.parser
+
+    def get_arch_config(self) -> dict:
+        if self.config:
+            return self.config[self.arch]
+        self.load_config()
+        return self.config[self.arch]
+
+    def get_general_config(self) -> dict:
+        if self.config:
+            return self.config["General"]
+        self.load_config()
+        return self.config["General"]
+
+    def load_config(self) -> None:
+        if not Path.exists(self.config_path):
+            log.fatal(f"Could not load arch config file at '{self.config_path}'")
+            exit(1)
+        with open(self.config_path) as f:
+            conf = json.loads(f.read())
+        if self.arch not in conf:
+            log.fatal(f"{self.arch} has no configuration. Please add them in {self.config_path}!")
+            exit(1)
+        self.config = conf
+
+    def ts_compile_cpp(self) -> None:
+        log.info("Compile Cpp language")
+        if not Path.exists(self.ts_grammar_path):
+            log.fatal(f"Could not load the tree-sitter grammar at '{self.ts_grammar_path}'")
+            exit(1)
+        Language.build_library(str(self.ts_so_path), [self.ts_grammar_path])
+
+    def ts_set_cpp_language(self) -> None:
+        log.info(f"Load language '{self.ts_so_path}'")
+        if not Path.exists(self.ts_so_path):
+            log.fatal(f"Could not load the tree-sitter language shared object at '{self.ts_so_path}'")
+            exit(1)
+        self.ts_cpp_lang = Language(self.ts_so_path, "cpp")
+
+    def init_parser(self) -> None:
+        log.debug("Init parser")
+        self.parser = Parser()
+        self.parser.set_language(self.ts_cpp_lang)
diff --git a/suite/auto-sync/CppTranslator/CppTranslator.py b/suite/auto-sync/CppTranslator/CppTranslator.py
new file mode 100755
index 000000000..bf036bf69
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/CppTranslator.py
@@ -0,0 +1,453 @@
+#!/usr/bin/env python3
+import subprocess
+from pathlib import Path
+
+import termcolor
+from tree_sitter import Language, Parser, Tree, Node
+import argparse
+import logging as log
+import sys
+
+from tree_sitter.binding import Query
+
+from Configurator import Configurator
+from Helper import convert_loglevel, print_prominent_warning, get_header, run_clang_format
+from Patches.AddCSDetail import AddCSDetail
+from Patches.AddOperand import AddOperand
+from Patches.Assert import Assert
+from Patches.CheckDecoderStatus import CheckDecoderStatus
+from Patches.ClassConstructorDef import ClassConstructorDef
+from Patches.ClassesDef import ClassesDef
+from Patches.ConstMCInstParameter import ConstMCInstParameter
+from Patches.ConstMCOperand import ConstMCOperand
+from Patches.CreateOperand0 import CreateOperand0
+from Patches.CreateOperand1 import CreateOperand1
+from Patches.DeclarationInConditionClause import DeclarationInConditionalClause
+from Patches.DecodeInstruction import DecodeInstruction
+from Patches.DecoderCast import DecoderCast
+from Patches.DecoderParameter import DecoderParameter
+from Patches.FallThrough import FallThrough
+from Patches.FeatureBits import FeatureBits
+from Patches.FeatureBitsDecl import FeatureBitsDecl
+from Patches.FieldFromInstr import FieldFromInstr
+from Patches.GetNumOperands import GetNumOperands
+from Patches.GetOpcode import GetOpcode
+from Patches.GetOperandRegImm import GetOperandRegImm
+from Patches.GetOperand import GetOperand
+from Patches.GetSubReg import GetSubReg
+from Patches.Includes import Includes
+from Patches.InlineToStaticInline import InlineToStaticInline
+from Patches.IsOptionalDef import IsOptionalDef
+from Patches.IsPredicate import IsPredicate
+from Patches.LLVMFallThrough import LLVMFallThrough
+from Patches.LLVMunreachable import LLVMUnreachable
+from Patches.MethodToFunctions import MethodToFunction
+from Patches.MethodTypeQualifier import MethodTypeQualifier
+from Patches.NamespaceLLVM import NamespaceLLVM
+from Patches.NamespaceAnon import NamespaceAnon
+from Patches.NamespaceArch import NamespaceArch
+from Patches.OutStreamParam import OutStreamParam
+from Patches.PredicateBlockFunctions import PredicateBlockFunctions
+from Patches.PrintAnnotation import PrintAnnotation
+from Patches.PrintRegImmShift import PrintRegImmShift
+from Patches.QualifiedIdentifier import QualifiedIdentifier
+from Patches.Patch import Patch
+from Patches.ReferencesDecl import ReferencesDecl
+from Patches.STIArgument import STIArgument
+from Patches.STIFeatureBits import STIFeatureBits
+from Patches.STParameter import SubtargetInfoParam
+from Patches.SetOpcode import SetOpcode
+from Patches.SignExtend32 import SignExtend32
+from Patches.SizeAssignments import SizeAssignment
+from Patches.StreamOperation import StreamOperations
+from Patches.TemplateDeclaration import TemplateDeclaration
+from Patches.TemplateDefinition import TemplateDefinition
+from Patches.TemplateParamDecl import TemplateParamDecl
+from Patches.TemplateRefs import TemplateRefs
+from Patches.UseMarkup import UseMarkup
+from Patches.UsingDeclaration import UsingDeclaration
+from TemplateCollector import TemplateCollector
+
+
+class Translator:
+    ts_cpp_lang: Language = None
+    parser: Parser = None
+    template_collector: TemplateCollector = None
+    src_paths: [Path]
+    out_paths: [Path]
+    conf: dict
+    src = b""
+    current_src_path_in: Path = None
+    current_src_path_out: Path = None
+    tree: Tree = None
+
+    # Patch priorities: The bigger the number the later the patch will be applied.
+    # Patches which create templates must always be executed last. Since syntax
+    # in macros is no longer parsed as such (but is only recognized as macro body).
+    #
+    # If a patch must be executed before another patch (because the matching rules depend on it)
+    # mark this dependency as you see below.
+    patches: [Patch] = list()
+
+    patch_priorities: {str: int} = {
+        PrintRegImmShift.__name__: 0,
+        InlineToStaticInline.__name__: 0,
+        GetSubReg.__name__: 0,
+        UseMarkup.__name__: 0,
+        ConstMCOperand.__name__: 0,
+        ClassConstructorDef.__name__: 0,
+        ConstMCInstParameter.__name__: 0,
+        PrintAnnotation.__name__: 0,
+        GetNumOperands.__name__: 0,
+        STIArgument.__name__: 0,
+        DecodeInstruction.__name__: 0,
+        FallThrough.__name__: 0,
+        SizeAssignment.__name__: 0,
+        FieldFromInstr.__name__: 0,
+        FeatureBitsDecl.__name__: 0,
+        FeatureBits.__name__: 0,
+        STIFeatureBits.__name__: 0,
+        Includes.__name__: 0,
+        CreateOperand0.__name__: 0,  # ◁───┐ `CreateOperand0` removes most calls to MI.addOperand().
+        AddOperand.__name__: 1,  # ────────┘ The ones left are fixed with the `AddOperand` patch.
+        CreateOperand1.__name__: 0,
+        GetOpcode.__name__: 0,
+        SetOpcode.__name__: 0,
+        GetOperand.__name__: 0,
+        GetOperandRegImm.__name__: 0,
+        SignExtend32.__name__: 0,
+        DecoderParameter.__name__: 0,
+        UsingDeclaration.__name__: 0,
+        DecoderCast.__name__: 0,
+        IsPredicate.__name__: 0,
+        IsOptionalDef.__name__: 0,
+        Assert.__name__: 0,  # ◁─────────┐ The llvm_unreachable calls are replaced with asserts.
+        LLVMUnreachable.__name__: 1,  # ─┘ Those assert should stay.
+        LLVMFallThrough.__name__: 0,
+        DeclarationInConditionalClause.__name__: 0,
+        StreamOperations.__name__: 0,
+        OutStreamParam.__name__: 0,  # ◁──────┐ add_cs_detail() is added to printOperand functions with a certain
+        SubtargetInfoParam.__name__: 0,  # ◁──┤ signature. This signature depends on those patches.
+        MethodToFunction.__name__: 0,  # ◁────┤
+        AddCSDetail.__name__: 1,  # ──────────┘
+        NamespaceAnon.__name__: 0,  # ◁─────┐ "llvm" and anonymous namespaces must be removed first,
+        NamespaceLLVM.__name__: 0,  # ◁─────┤ so they don't match in NamespaceArch.
+        NamespaceArch.__name__: 1,  # ──────┘
+        PredicateBlockFunctions.__name__: 0,
+        ClassesDef.__name__: 0,  # ◁────────┐ Declarations must be extracted first from the classes.
+        MethodTypeQualifier.__name__: 1,  # ┘
+        # All previous patches can contain qualified identifiers (Ids with the "::" operator) in their search patterns.
+        # After this patch they are removed.
+        QualifiedIdentifier.__name__: 2,
+        ReferencesDecl.__name__: 3,  # ◁────┐
+        CheckDecoderStatus.__name__: 4,  # ─┘ Reference declarations must be removed first.
+        TemplateParamDecl.__name__: 5,
+        TemplateRefs.__name__: 5,
+        # Template declarations are replaced with macros.
+        # Those declarations are parsed as macro afterwards
+        TemplateDeclaration.__name__: 5,
+        # Template definitions are replaced with macros.
+        # Those template functions are parsed as macro afterwards.
+        TemplateDefinition.__name__: 6,
+    }
+
+    def __init__(self, configure: Configurator):
+        self.configurator = configure
+        self.arch = self.configurator.get_arch()
+        self.conf = self.configurator.get_arch_config()
+        self.conf_general = self.configurator.get_general_config()
+        self.ts_cpp_lang = self.configurator.get_cpp_lang()
+        self.parser = self.configurator.get_parser()
+
+        self.src_paths: [Path] = [Path(sp["in"]) for sp in self.conf["files_to_translate"]]
+        t_out_dir = self.conf_general["translation_out_dir"]
+        self.out_paths: [Path] = [Path(t_out_dir + sp["out"]) for sp in self.conf["files_to_translate"]]
+
+        self.collect_template_instances()
+        self.init_patches()
+
+    def read_src_file(self, src_path: Path) -> None:
+        """Reads the file at src_path into self.src"""
+        log.debug(f"Read {src_path}")
+        if not Path.exists(src_path):
+            log.fatal(f"Could not open the source file '{src_path}'")
+            exit(1)
+        with open(src_path) as f:
+            self.src = bytes(f.read(), "utf8")
+
+    def init_patches(self):
+        log.debug("Init patches")
+        priorities = dict(sorted(self.patch_priorities.items(), key=lambda item: item[1]))
+        for ptype, p in priorities.items():
+            if ptype == CheckDecoderStatus.__name__:
+                patch = CheckDecoderStatus(p)
+            elif ptype == ReferencesDecl.__name__:
+                patch = ReferencesDecl(p)
+            elif ptype == FieldFromInstr.__name__:
+                patch = FieldFromInstr(p)
+            elif ptype == FeatureBitsDecl.__name__:
+                patch = FeatureBitsDecl(p)
+            elif ptype == FeatureBits.__name__:
+                patch = FeatureBits(p, bytes(self.arch, "utf8"))
+            elif ptype == STIFeatureBits.__name__:
+                patch = STIFeatureBits(p, bytes(self.arch, "utf8"))
+            elif ptype == QualifiedIdentifier.__name__:
+                patch = QualifiedIdentifier(p)
+            elif ptype == Includes.__name__:
+                patch = Includes(p, self.arch)
+            elif ptype == ClassesDef.__name__:
+                patch = ClassesDef(p)
+            elif ptype == CreateOperand0.__name__:
+                patch = CreateOperand0(p)
+            elif ptype == CreateOperand1.__name__:
+                patch = CreateOperand1(p)
+            elif ptype == GetOpcode.__name__:
+                patch = GetOpcode(p)
+            elif ptype == SetOpcode.__name__:
+                patch = SetOpcode(p)
+            elif ptype == GetOperand.__name__:
+                patch = GetOperand(p)
+            elif ptype == SignExtend32.__name__:
+                patch = SignExtend32(p)
+            elif ptype == TemplateDeclaration.__name__:
+                patch = TemplateDeclaration(p, self.template_collector)
+            elif ptype == TemplateDefinition.__name__:
+                patch = TemplateDefinition(p, self.template_collector)
+            elif ptype == DecoderParameter.__name__:
+                patch = DecoderParameter(p)
+            elif ptype == TemplateRefs.__name__:
+                patch = TemplateRefs(p)
+            elif ptype == TemplateParamDecl.__name__:
+                patch = TemplateParamDecl(p)
+            elif ptype == MethodTypeQualifier.__name__:
+                patch = MethodTypeQualifier(p)
+            elif ptype == UsingDeclaration.__name__:
+                patch = UsingDeclaration(p)
+            elif ptype == NamespaceLLVM.__name__:
+                patch = NamespaceLLVM(p)
+            elif ptype == DecoderCast.__name__:
+                patch = DecoderCast(p)
+            elif ptype == IsPredicate.__name__:
+                patch = IsPredicate(p)
+            elif ptype == IsOptionalDef.__name__:
+                patch = IsOptionalDef(p)
+            elif ptype == Assert.__name__:
+                patch = Assert(p)
+            elif ptype == LLVMFallThrough.__name__:
+                patch = LLVMFallThrough(p)
+            elif ptype == DeclarationInConditionalClause.__name__:
+                patch = DeclarationInConditionalClause(p)
+            elif ptype == OutStreamParam.__name__:
+                patch = OutStreamParam(p)
+            elif ptype == MethodToFunction.__name__:
+                patch = MethodToFunction(p)
+            elif ptype == GetOperandRegImm.__name__:
+                patch = GetOperandRegImm(p)
+            elif ptype == StreamOperations.__name__:
+                patch = StreamOperations(p)
+            elif ptype == SubtargetInfoParam.__name__:
+                patch = SubtargetInfoParam(p)
+            elif ptype == SizeAssignment.__name__:
+                patch = SizeAssignment(p)
+            elif ptype == NamespaceArch.__name__:
+                patch = NamespaceArch(p)
+            elif ptype == NamespaceAnon.__name__:
+                patch = NamespaceAnon(p)
+            elif ptype == PredicateBlockFunctions.__name__:
+                patch = PredicateBlockFunctions(p)
+            elif ptype == FallThrough.__name__:
+                patch = FallThrough(p)
+            elif ptype == DecodeInstruction.__name__:
+                patch = DecodeInstruction(p)
+            elif ptype == STIArgument.__name__:
+                patch = STIArgument(p)
+            elif ptype == GetNumOperands.__name__:
+                patch = GetNumOperands(p)
+            elif ptype == AddOperand.__name__:
+                patch = AddOperand(p)
+            elif ptype == PrintAnnotation.__name__:
+                patch = PrintAnnotation(p)
+            elif ptype == ConstMCInstParameter.__name__:
+                patch = ConstMCInstParameter(p)
+            elif ptype == LLVMUnreachable.__name__:
+                patch = LLVMUnreachable(p)
+            elif ptype == ClassConstructorDef.__name__:
+                patch = ClassConstructorDef(p)
+            elif ptype == ConstMCOperand.__name__:
+                patch = ConstMCOperand(p)
+            elif ptype == UseMarkup.__name__:
+                patch = UseMarkup(p)
+            elif ptype == GetSubReg.__name__:
+                patch = GetSubReg(p)
+            elif ptype == InlineToStaticInline.__name__:
+                patch = InlineToStaticInline(p)
+            elif ptype == AddCSDetail.__name__:
+                patch = AddCSDetail(p, self.arch)
+            elif ptype == PrintRegImmShift.__name__:
+                patch = PrintRegImmShift(p)
+            else:
+                log.fatal(f"Patch type {ptype} not in Patch init routine.")
+                exit(1)
+            self.patches.append(patch)
+
+    def parse(self, src_path: Path) -> None:
+        self.read_src_file(src_path)
+        log.debug("Parse source code")
+        self.tree = self.parser.parse(self.src, keep_text=True)
+
+    def patch_src(self, p_list: [(bytes, Node)]) -> None:
+        if len(p_list) == 0:
+            return
+        # Sort list of patches descending so the patches which are last in the file
+        # get patched first. This way the indices of the code snippets before
+        # don't change.
+        patches = sorted(p_list, key=lambda x: x[1].start_byte, reverse=True)
+
+        new_src = b""
+        patch: bytes
+        node: Node
+        for patch, node in patches:
+            start_byte: int = node.start_byte
+            old_end_byte: int = node.end_byte
+            start_point: (int, int) = node.start_point
+            old_end_point: (int, int) = node.end_point
+
+            new_src = self.src[:start_byte] + patch + self.src[old_end_byte:]
+            self.src = new_src
+            d = len(patch) - (old_end_byte - start_byte)
+            self.tree.edit(
+                start_byte=start_byte,
+                old_end_byte=old_end_byte,
+                new_end_byte=old_end_byte + d,
+                start_point=start_point,
+                old_end_point=old_end_point,
+                new_end_point=(old_end_point[0], old_end_point[1] + d),
+            )
+        self.tree = self.parser.parse(new_src, self.tree, keep_text=True)
+
+    def apply_patch(self, patch: Patch) -> bool:
+        """Tests if the given patch should be applied for the current architecture or file."""
+        has_apply_only = len(patch.apply_only_to["files"]) > 0 or len(patch.apply_only_to["archs"]) > 0
+        has_do_not_apply = len(patch.do_not_apply["files"]) > 0 or len(patch.do_not_apply["archs"]) > 0
+
+        if not (has_apply_only or has_do_not_apply):
+            # Lists empty.
+            return True
+
+        if has_apply_only:
+            if self.arch in patch.apply_only_to["archs"]:
+                return True
+            elif self.current_src_path_in.name in patch.apply_only_to["files"]:
+                return True
+            return False
+        elif has_do_not_apply:
+            if self.arch in patch.do_not_apply["archs"]:
+                return False
+            elif self.current_src_path_in.name in patch.do_not_apply["files"]:
+                return False
+            return True
+        log.fatal("Logical error.")
+        exit(1)
+
+    def translate(self) -> None:
+        for self.current_src_path_in, self.current_src_path_out in zip(self.src_paths, self.out_paths):
+            log.info(f"Translate '{self.current_src_path_in}'")
+            self.parse(self.current_src_path_in)
+            patch: Patch
+            for patch in self.patches:
+                if not self.apply_patch(patch):
+                    log.debug(f"Skip patch {patch.__class__.__name__}")
+                    continue
+                pattern: str = patch.get_search_pattern()
+
+                # Each patch has a capture which includes the whole subtree searched for.
+                # Additionally, it can include captures within this subtree.
+                # Here we bundle these captures together.
+                query: Query = self.ts_cpp_lang.query(pattern)
+                captures_bundle: [[(Node, str)]] = list()
+                for q in query.captures(self.tree.root_node):
+                    if q[1] == patch.get_main_capture_name():
+                        # The main capture the patch is looking for.
+                        captures_bundle.append([q])
+                    else:
+                        # A capture which is part of the main capture.
+                        # Add it to the bundle.
+                        captures_bundle[-1].append(q)
+
+                log.debug(f"Patch {patch.__class__.__name__} (to patch: {len(captures_bundle)}).")
+
+                p_list: (bytes, Node) = list()
+                cb: [(Node, str)]
+                for cb in captures_bundle:
+                    patch_kwargs = self.get_patch_kwargs(patch)
+                    bytes_patch: bytes = patch.get_patch(cb, self.src, **patch_kwargs)
+                    p_list.append((bytes_patch, cb[0][0]))
+                self.patch_src(p_list)
+            log.info(f"Patched file at '{self.current_src_path_out}'")
+            with open(self.current_src_path_out, "w") as f:
+                f.write(get_header())
+                f.write(self.src.decode("utf8"))
+        run_clang_format(self.out_paths, Path(self.conf_general["clang_format_file"]))
+
+    def collect_template_instances(self):
+        search_paths = [Path(p) for p in self.conf["files_for_template_search"]]
+        self.template_collector = TemplateCollector(self.parser, self.ts_cpp_lang, search_paths)
+        self.template_collector.collect()
+
+    def get_patch_kwargs(self, patch):
+        if isinstance(patch, Includes):
+            return {"filename": self.current_src_path_in.name}
+        return dict()
+
+    def remark_manual_files(self) -> None:
+        manual_edited = self.conf["manually_edited_files"]
+        msg = ""
+        if len(manual_edited) > 0:
+            msg += (
+                termcolor.colored(
+                    "The following files are too complex to translate! Please check them by hand.", attrs=["bold"]
+                )
+                + "\n"
+            )
+        for f in manual_edited:
+            msg += f
+        print_prominent_warning(msg)
+
+
+def parse_args() -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        prog="CppTranslator",
+        description="Capstones C++ to C translator for LLVM source files",
+    )
+    parser.add_argument("-a", dest="arch", help="Name of target architecture.", choices=["ARM"], required=True)
+    parser.add_argument(
+        "-v",
+        dest="verbosity",
+        help="Verbosity of the log messages.",
+        choices=["debug", "info", "warning", "fatal"],
+        default="info",
+    )
+    parser.add_argument(
+        "-c", dest="config_path", help="Config file for architectures.", default="arch_config.json", type=Path
+    )
+    parser.add_argument(
+        "-g", dest="grammar", help="Path to the tree-sitter C++ grammar.", default="vendor/tree-sitter-cpp", type=Path
+    )
+    parser.add_argument(
+        "-l", dest="lang_so", help="File to store the compiled C++ language.", default="build/ts-cpp.so", type=Path
+    )
+    arguments = parser.parse_args()
+    return arguments
+
+
+if __name__ == "__main__":
+    args = parse_args()
+    log.basicConfig(
+        level=convert_loglevel(args.verbosity),
+        stream=sys.stdout,
+        format="%(levelname)-5s - %(message)s",
+    )
+    configurator = Configurator(args.arch, args.config_path, args.grammar, args.lang_so)
+    translator = Translator(configurator)
+    translator.translate()
+    translator.remark_manual_files()
diff --git a/suite/auto-sync/CppTranslator/Differ.py b/suite/auto-sync/CppTranslator/Differ.py
new file mode 100755
index 000000000..9cafc2c1d
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Differ.py
@@ -0,0 +1,641 @@
+#!/usr/bin/env python3
+import json
+from enum import StrEnum
+from pathlib import Path
+from typing import Iterator
+
+from tree_sitter import Language, Parser, Tree, Node
+from shutil import copy2
+import argparse
+import difflib as dl
+import logging as log
+import sys
+
+from Configurator import Configurator
+from Helper import (
+    convert_loglevel,
+    find_id_by_type,
+    print_prominent_info,
+    bold,
+    colored,
+    separator_line_1,
+    separator_line_2,
+    print_prominent_warning,
+    get_sha256,
+    run_clang_format,
+)
+
+
+class PatchCoord:
+    """Holds the coordinate information of tree-sitter nodes."""
+
+    start_byte: int
+    end_byte: int
+    start_point: tuple[int, int]
+    end_point: tuple[int, int]
+
+    def __init__(self, start_byte: int, end_byte: int, start_point: tuple[int, int], end_point: tuple[int, int]):
+        self.start_byte = start_byte
+        self.end_byte = end_byte
+        self.start_point = start_point
+        self.end_point = end_point
+
+    def __lt__(self, other):
+        if not (
+            (self.start_byte <= other.start_byte and self.end_byte <= other.end_byte)
+            or (self.start_byte >= other.start_byte and self.end_byte >= other.end_byte)
+        ):
+            raise IndexError(
+                f"Coordinates overlap. No comparison possible.\n"
+                f"a.start_byte = {self.start_byte} a.end_byte = {self.end_byte}\n"
+                f"b.start_byte = {other.start_byte} b.end_byte = {other.end_byte}\n"
+            )
+        return self.end_byte < other.start_byte
+
+    def __str__(self) -> str:
+        return f"s: {self.start_byte} e: {self.end_byte}"
+
+    @staticmethod
+    def get_coordinates_from_node(node: Node):
+        return PatchCoord(node.start_byte, node.end_byte, node.start_point, node.end_point)
+
+
+class ApplyType(StrEnum):
+    OLD = "OLD"  # Apply version from old file
+    NEW = "NEW"  # Apply version from new file (leave unchanged)
+    SAVED = "SAVED"  # Use saved resolution
+    EDIT = "EDIT"  # Edit patch and apply
+    OLD_ALL = "OLD_ALL"  # Apply all versions from old file.
+    PREVIOUS = "PREVIOUS"  # Ignore diff and go to previous
+
+
+class Patch:
+    node_id: str
+    coord: PatchCoord
+    apply: ApplyType
+    old: bytes
+    new: bytes
+    edit: bytes
+    old_hash: str
+    new_hash: str
+
+    def __init__(
+        self, node_id: str, old: bytes, new: bytes, coord: PatchCoord, apply: ApplyType, edit: bytes = None
+    ) -> None:
+        if apply == ApplyType.SAVED:
+            raise NotImplemented("Not yet implemented.")
+        self.node_id = node_id
+        self.apply = apply
+        self.coord = coord
+        self.old = old
+        self.new = new
+        self.edit = edit
+        self.old_hash = ""
+        self.new_hash = ""
+        if self.old:
+            self.old_hash = get_sha256(self.old)
+        if self.new:
+            self.new_hash = get_sha256(self.new)
+
+    def get_persist_info(self) -> dict:
+        """Returns a dictionary with the relevant information to back up this patch."""
+        backup = dict()
+        backup[self.node_id] = dict()
+        backup[self.node_id]["apply_type"] = str(self.apply)
+        backup[self.node_id]["old_hash"] = self.old_hash
+        backup[self.node_id]["new_hash"] = self.new_hash
+        backup[self.node_id]["edit"] = self.edit.decode("utf8") if self.edit else ""
+        return backup
+
+    def merge(self, other) -> None:
+        """
+        Merge two patches to one. Necessary if two old nodes are not present in the new file.
+        And therefore share PatchCoordinates.
+        """
+        if other.new:
+            raise ValueError("This patch should not have a .new set.")
+        if not other.old:
+            raise ValueError("No data in .old")
+        self.old = other.old + self.old
+        self.old_hash = get_sha256(self.old)
+
+    def __lt__(self, other):
+        try:
+            return self.coord < other.coord
+        except IndexError as e:
+            raise IndexError(f"Nodes overlap: {self} - {other}")
+
+    def __str__(self) -> str:
+        return f"{self.node_id} @ {self.coord}"
+
+
+class Differ:
+    """
+    Diffs the newly translated C++ files against the old version.
+    """
+
+    ts_cpp_lang: Language = None
+    parser: Parser = None
+    translated_files: [Path]
+    diff_dest_files: [Path] = list()
+    old_files: [Path]
+    conf_arch: dict
+    conf_general: dict
+    tree: Tree = None
+    persistence_filepath: Path
+    saved_patches: dict = None
+    patches: list[Patch]
+
+    current_patch: Patch
+    cur_old_node: Node = None
+    cur_new_node: Node = None
+    cur_nid: str = None
+
+    def __init__(self, configurator: Configurator, no_auto_apply: bool):
+
+        self.configurator = configurator
+        self.no_auto_apply = no_auto_apply
+        self.arch = self.configurator.get_arch()
+        self.conf_arch = self.configurator.get_arch_config()
+        self.conf_general = self.configurator.get_general_config()
+        self.ts_cpp_lang = self.configurator.get_cpp_lang()
+        self.parser = self.configurator.get_parser()
+        self.differ = dl.Differ()
+
+        t_out_dir = self.conf_general["translation_out_dir"]
+        self.translated_files = [Path(t_out_dir + sp["out"]) for sp in self.conf_arch["files_to_translate"]]
+        cs_arch_src = self.conf_general["cs_arch_src"]
+        self.old_files = [
+            Path(cs_arch_src + f"/{self.arch}/" + sp["out"]) for sp in self.conf_arch["files_to_translate"]
+        ]
+        self.load_persistence_file()
+
+    def load_persistence_file(self) -> None:
+        self.persistence_filepath = Path(self.conf_general["patch_persistence_file"])
+        if not self.persistence_filepath.exists():
+            self.saved_patches = dict()
+            return
+
+        with open(self.persistence_filepath, "rb") as f:
+            try:
+                self.saved_patches = json.load(f)
+            except json.decoder.JSONDecodeError as e:
+                log.fatal(f"Persistence file {bold(self.persistence_filepath.name)} corrupt.")
+                log.fatal(f"Delete it or fix it by hand.")
+                log.fatal(f"JSON Exception: {e}")
+                exit(1)
+
+    def save_to_persistence_file(self) -> None:
+        with open(self.persistence_filepath, "w") as f:
+            json.dump(self.saved_patches, f, indent=2)
+
+    def persist_patch(self, filename: Path, patch: Patch) -> None:
+        if filename.name not in self.saved_patches:
+            self.saved_patches[filename.name] = dict()
+        log.debug(f"Save: {patch.get_persist_info()}")
+        self.saved_patches[filename.name].update(patch.get_persist_info())
+
+    def copy_files(self) -> None:
+        """
+        Copy translated files to diff directory for editing.
+        """
+        log.info("Copy files for editing")
+        diff_dir = self.conf_general["diff_out_dir"]
+        for f in self.translated_files:
+            dest = Path(diff_dir + f.name)
+            copy2(f, dest)
+            self.diff_dest_files.append(dest)
+
+    def get_diff_intro_msg(
+        self, old_filename: Path, new_filename: Path, current: int, total: int, num_diffs: int
+    ) -> str:
+        color_new = self.conf_general["diff_color_new"]
+        color_old = self.conf_general["diff_color_old"]
+        return (
+            f"{bold(f'Diffing files - {current}/{total}')} \n\n"
+            + f"{bold('NEW FILE: ', color_new)} {str(new_filename)}\n"
+            + f"{bold('OLD FILE: ', color_old)} {str(old_filename)}\n\n"
+            + f"{bold('Diffs to process: ')} {num_diffs}\n\n"
+            + f"{bold('Changes get written to: ')} {bold('NEW FILE', color_new)}\n"
+        )
+
+    def get_diff_node_id(self, node: Node) -> bytes:
+        """
+        Searches in the nodes children for the identifier node and returns its text.
+        """
+        id_types = [""]
+        for n in self.conf_general["nodes_to_diff"]:
+            if n["node_type"] == node.type:
+                id_types = n["identifier_node_type"]
+        if not id_types:
+            log.fatal(f"Diffing: Node of type {node.type} has not identifier type specified.")
+            exit(1)
+        identifier = ""
+        for id_type in id_types:
+            identifier = find_id_by_type(node, id_type.split("/"), False)
+            if identifier:
+                break
+        if not identifier:
+            log.fatal(f'Diffing: Cannot find node type "{id_types}" in named-children.')
+            exit(1)
+        return identifier
+
+    def parse_file(self, file: Path) -> dict:
+        """
+        Parse a files and return all nodes which should be diffed.
+        Nodes are indexed by a unique identifier.
+        """
+        with open(file) as f:
+            content = bytes(f.read(), "utf8")
+
+        tree: Tree = self.parser.parse(content, keep_text=True)
+
+        node_types_to_diff = [n["node_type"] for n in self.conf_general["nodes_to_diff"]]
+        content = None
+        if file.suffix == ".h":
+            # Header file. Get the content in between the include guard
+            for n in tree.root_node.named_children:
+                if n.type == "preproc_ifdef":
+                    content = n
+                    break
+        if not content:
+            content = tree.root_node
+        duplicates = list()
+        nodes_to_diff = dict()
+        node: Node
+        # Get diff candidates and add them to the dict.
+        for node in content.named_children:
+            if node.type not in node_types_to_diff:
+                continue
+            identifier = self.get_diff_node_id(node).decode("utf8")
+            if identifier in nodes_to_diff.keys() or identifier in duplicates:
+                # This happens if the chosen identifier is not unique.
+                log.info(f"Duplicate {bold(identifier)}: Nodes will not be diffed!")
+                if identifier in nodes_to_diff.keys():
+                    nodes_to_diff.pop(identifier)
+                duplicates.append(identifier)
+                continue
+            log.debug(f"Add node to diff: {identifier}")
+            nodes_to_diff[identifier] = node
+        return nodes_to_diff
+
+    def print_diff(self, diff_lines: list[str], node_id: str, current: int, total: int):
+        new_color = self.conf_general["diff_color_new"]
+        old_color = self.conf_general["diff_color_old"]
+        print(separator_line_1())
+        print(f"{bold('Patch:')} {current}/{total}\n")
+        print(f"{bold('Node:')} {node_id}")
+        print(f"{bold('Color:')} {colored('NEW FILE - (Just translated)', new_color)}")
+        print(f"{bold('Color:')} {colored('OLD FILE - (Currently in Capstone)', old_color)}\n")
+        print(separator_line_1())
+        for line in diff_lines:
+            if line[0] == "+":
+                print(colored(line, new_color))
+            elif line[0] == "-":
+                print(colored(line, old_color))
+            elif line[0] == "?":
+                continue
+            else:
+                print(line)
+        print(separator_line_2())
+
+    @staticmethod
+    def no_difference(diff_lines: Iterator[str]) -> bool:
+        for line in diff_lines:
+            if line[0] != " ":
+                return False
+        return True
+
+    def print_prompt(self, saved_diff_present: bool = False, saved_choice: ApplyType = None) -> str:
+        new_color = self.conf_general["diff_color_new"]
+        old_color = self.conf_general["diff_color_old"]
+        edited_color = self.conf_general["diff_color_edited"]
+        saved_selection = self.get_saved_choice_prompt(saved_diff_present, saved_choice)
+
+        choice = input(
+            f"Choice: {colored('O', old_color)}, {bold('o', old_color)}, {bold('n', new_color)}, "
+            f"{saved_selection}, {colored('e', edited_color)}, p, q, ? > "
+        )
+        return choice
+
+    def get_saved_choice_prompt(self, saved_diff_present: bool = False, saved_choice: ApplyType = None):
+        new_color = self.conf_general["diff_color_new"]
+        old_color = self.conf_general["diff_color_old"]
+        edited_color = self.conf_general["diff_color_edited"]
+        saved_color = self.conf_general["diff_color_saved"] if saved_diff_present else "dark_grey"
+        saved_selection = f"{bold('s', saved_color)}"
+        if saved_choice == ApplyType.OLD:
+            saved_selection += f" ({colored('old', old_color)}) "
+        elif saved_choice == ApplyType.NEW:
+            saved_selection += f" ({colored('new', new_color)}) "
+        elif saved_choice == ApplyType.EDIT:
+            saved_selection += f" ({colored('edited', edited_color)}) "
+        elif not saved_choice:
+            saved_selection += f" ({colored('none', 'dark_grey')}) "
+        return saved_selection
+
+    def print_prompt_help(self, saved_diff_present: bool = False, saved_choice: ApplyType = None) -> None:
+        new_color = self.conf_general["diff_color_new"]
+        old_color = self.conf_general["diff_color_old"]
+        edited_color = self.conf_general["diff_color_edited"]
+        saved_choice = self.get_saved_choice_prompt(saved_diff_present, saved_choice)
+
+        print(
+            f"{colored('O', old_color)}\t\t- Accept ALL old diffs\n"
+            f"{bold('o', old_color)}\t\t- Accept old diff\n"
+            f"{bold('n', new_color)}\t\t- Accept new diff\n"
+            f"{colored('e', edited_color)}\t\t- Edit diff (not yet implemented)\n"
+            f"{saved_choice}\t- Select saved choice\n"
+            f"p\t\t- Ignore and go to previous diff\n"
+            f"q\t\t- Quit (previous selections will be saved)\n"
+            f"?\t\t- Show this help\n\n"
+        )
+
+    def get_user_choice(self, saved_diff_present: bool, saved_choice: ApplyType) -> ApplyType:
+        while True:
+            choice = self.print_prompt(saved_diff_present, saved_choice)
+            if choice not in ["O", "o", "n", "e", "s", "p", "q", "?", "help"]:
+                print(f"{bold(choice)} is not valid.")
+                self.print_prompt_help(saved_diff_present, saved_choice)
+                continue
+
+            if choice == "q":
+                print(f"{bold('Quit...')}")
+                self.save_to_persistence_file()
+                exit(0)
+            elif choice == "o":
+                return ApplyType.OLD
+            elif choice == "n":
+                return ApplyType.NEW
+            elif choice == "O":
+                return ApplyType.OLD_ALL
+            elif choice == "e":
+                return ApplyType.EDIT
+            elif choice == "s":
+                return ApplyType.SAVED
+            elif choice in ["?", "help"]:
+                self.print_prompt_help(saved_diff_present, saved_choice)
+                continue
+            elif choice == "p":
+                return ApplyType.PREVIOUS
+
+    def saved_patch_matches(self, saved: dict) -> bool:
+        if self.cur_old_node:
+            old_hash = get_sha256(self.cur_old_node.text)
+        else:
+            old_hash = ""
+        if self.cur_new_node:
+            new_hash = get_sha256(self.cur_new_node.text)
+        else:
+            new_hash = ""
+        return saved["old_hash"] == old_hash and saved["new_hash"] == new_hash
+
+    def create_patch(self, coord: PatchCoord, choice: ApplyType, saved_patch: dict = None):
+        old = self.cur_old_node.text if self.cur_old_node else b""
+        new = self.cur_new_node.text if self.cur_new_node else b""
+        return Patch(self.cur_nid, old, new, coord, saved_patch["apply_type"] if saved_patch else choice)
+
+    def add_patch(
+        self,
+        apply_type: ApplyType,
+        consec_old: int,
+        old_filepath: Path,
+        patch_coord: PatchCoord,
+    ) -> None:
+        self.current_patch = self.create_patch(patch_coord, apply_type)
+        self.persist_patch(old_filepath, self.current_patch)
+        if consec_old > 1:
+            # Two or more old nodes are not present in the new file.
+            # Merge them to one patch.
+            self.patches[-1].merge(self.current_patch)
+        else:
+            self.patches.append(self.current_patch)
+
+    def diff_nodes(self, old_filepath: Path, new_nodes: dict[bytes, Node], old_nodes: dict[bytes, Node]) -> list[Patch]:
+        """
+        Asks the user for each different node, which version should be written.
+        It writes the choice to a file, so the previous choice can be applied again if nothing changed.
+        """
+        # Sort list of nodes descending.
+        # This is necessary because
+        #   a) we need to apply the patches backwards (so the coordinates in the file don't change.
+        #   b) If there is an old node, which is not present in the new file, we search for
+        #      a node which is adjacent (random node order wouldn't allow this).
+        new_nodes = {k: v for k, v in sorted(new_nodes.items(), key=lambda item: item[1].start_byte, reverse=True)}
+        old_nodes = {k: v for k, v in sorted(old_nodes.items(), key=lambda item: item[1].start_byte, reverse=True)}
+
+        # Collect all node ids of this file
+        node_ids = set()
+        for new_node_id, old_node_id in zip(new_nodes.keys(), old_nodes.keys()):
+            node_ids.add(new_node_id)
+            node_ids.add(old_node_id)
+
+        # The initial patch coordinates point after the last node in the file.
+        n0 = new_nodes[list(new_nodes.keys())[0]]
+        patch_coord = PatchCoord(n0.end_byte, n0.end_byte, n0.end_point, n0.end_point)
+
+        node_ids = sorted(node_ids)
+        self.patches = list()
+        matching_nodes_count = 0
+        # Counts the number of old nodes which have no equivalent new node.
+        consec_old = 0
+        choice: ApplyType = None
+        i = 0
+        while i < len(node_ids):
+            self.cur_nid = node_ids[i]
+            self.cur_new_node = None
+            if self.cur_nid in new_nodes:
+                self.cur_new_node = new_nodes[self.cur_nid]
+            self.cur_old_node = None
+            if self.cur_nid in old_nodes:
+                self.cur_old_node = old_nodes[self.cur_nid]
+
+            n = self.cur_new_node.text.decode("utf8").splitlines() if self.cur_new_node else [""]
+            o = self.cur_old_node.text.decode("utf8").splitlines() if self.cur_old_node else [""]
+
+            diff_lines = list(self.differ.compare(o, n))
+            if self.no_difference(diff_lines):
+                log.debug(f"Nodes {bold(self.cur_nid)} match.")
+                matching_nodes_count += 1
+                i += 1
+                continue
+
+            if self.cur_new_node:
+                consec_old = 0
+                patch_coord = PatchCoord.get_coordinates_from_node(self.cur_new_node)
+            else:
+                consec_old += 1
+                # If the old node has no equivalent new node,
+                # we search for the next adjacent old node which exist also in new nodes.
+                # The single old node is insert before the found new one.
+                old_node_ids = list(old_nodes.keys())
+                j = old_node_ids.index(self.cur_nid)
+                while j >= 0 and (old_node_ids[j] not in new_nodes.keys()):
+                    j -= 1
+                ref_new: Node = new_nodes[old_node_ids[j]] if old_node_ids[j] in new_nodes.keys() else new_nodes[0]
+                ref_end_byte = ref_new.start_byte
+                patch_coord = PatchCoord(
+                    ref_end_byte - 1,
+                    ref_end_byte - 1,
+                    ref_end_byte,
+                    ref_end_byte,
+                )
+
+            save_exists = False
+            saved = None
+            if old_filepath.name in self.saved_patches and self.cur_nid in self.saved_patches[old_filepath.name]:
+                saved: dict = self.saved_patches[old_filepath.name][self.cur_nid]
+                save_exists = True
+                if self.saved_patch_matches(saved) and not self.no_auto_apply:
+                    apply_type = ApplyType(saved["apply_type"])
+                    self.add_patch(apply_type, consec_old, old_filepath, patch_coord)
+                    log.info(f"Auto apply patch for {bold(self.cur_nid)}")
+                    i += 1
+                    continue
+
+            if choice == ApplyType.OLD_ALL:
+                self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord)
+                i += 1
+                continue
+
+            self.print_diff(diff_lines, self.cur_nid, i + 1, len(node_ids))
+            choice = self.get_user_choice(save_exists, None if not saved else saved["apply_type"])
+            if choice == ApplyType.OLD:
+                if not self.cur_old_node:
+                    # No data in old node. Skip
+                    i += 1
+                    continue
+                self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord)
+            elif choice == ApplyType.NEW:
+                # Already in file. Only save patch.
+                self.persist_patch(old_filepath, self.create_patch(patch_coord, choice))
+            elif choice == ApplyType.SAVED:
+                if not save_exists:
+                    print(bold("Save does not exist."))
+                    continue
+                self.add_patch(saved["apply_type"], consec_old, old_filepath, patch_coord)
+            elif choice == ApplyType.OLD_ALL:
+                continue
+            elif choice == ApplyType.EDIT:
+                print(f"{bold('Editing not yet implemented.', 'light_red')}")
+                continue
+            elif choice == ApplyType.PREVIOUS:
+                if i == 0:
+                    print(bold(f"There is no previous diff for {old_filepath.name}!"))
+                    input("Press enter...")
+                    continue
+                i -= 1
+                continue
+            i += 1
+        log.info(f"Number of matching nodes = {matching_nodes_count}")
+        return self.patches
+
+    def diff(self) -> None:
+        """
+        Diffs certain nodes from the newly translated and old source files to each other.
+        The user then selects which diff should be written to the new file.
+        """
+
+        # We do not write to the translated files directly.
+        self.copy_files()
+        new_file = dict()
+        old_file = dict()
+        i = 0
+        for old_filepath, new_filepath in zip(self.old_files, self.diff_dest_files):
+            new_file[i] = dict()
+            new_file[i]["filepath"] = new_filepath
+            new_file[i]["nodes"] = self.parse_file(new_filepath)
+
+            old_file[i] = dict()
+            old_file[i]["filepath"] = old_filepath
+            old_file[i]["nodes"] = self.parse_file(old_filepath)
+            i += 1
+
+        patches = dict()
+        # diff each file
+        for k in range(i):
+            old_filepath = old_file[k]["filepath"]
+            new_filepath = new_file[k]["filepath"]
+            diffs_to_process = max(len(new_file[k]["nodes"]), len(old_file[k]["nodes"]))
+            print_prominent_info(self.get_diff_intro_msg(old_filepath, new_filepath, k + 1, i, diffs_to_process))
+            if diffs_to_process == 0:
+                continue
+            patches[new_filepath] = self.diff_nodes(old_filepath, new_file[k]["nodes"], old_file[k]["nodes"])
+        self.patch_files(patches)
+        log.info("Done")
+
+    def patch_files(self, file_patches: dict[Path, list[Patch]]) -> None:
+        log.info("Write patches...")
+        for filepath, patches in file_patches.items():
+            patches = sorted(patches, reverse=True)
+            with open(filepath, "rb") as f:
+                src = f.read()
+            patch: Patch
+            for patch in patches:
+                start_byte = patch.coord.start_byte
+                end_byte = patch.coord.end_byte
+                if patch.apply == ApplyType.OLD:
+                    data = patch.old
+                elif patch.apply == ApplyType.NEW:
+                    data = patch.new
+                elif patch.apply == ApplyType.EDIT:
+                    data = patch.edit
+                else:
+                    print_prominent_warning(f"No data for {patch.apply} defined.")
+                    return
+                src = src[:start_byte] + data + src[end_byte:]
+            with open(filepath, "wb") as f:
+                f.write(src)
+        run_clang_format(list(file_patches.keys()), Path(self.conf_general["clang_format_file"]))
+        return
+
+
+def parse_args() -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        prog="Differ",
+        description="Diffs translated C++ files to previous version.",
+    )
+    parser.add_argument(
+        "-e",
+        dest="no_auto_apply",
+        help="Do not apply saved diff resolutions. Ask for every diff again.",
+        action="store_true",
+    )
+    parser.add_argument("-a", dest="arch", help="Name of target architecture.", choices=["ARM"], required=True)
+    parser.add_argument(
+        "-v",
+        dest="verbosity",
+        help="Verbosity of the log messages.",
+        choices=["debug", "info", "warning", "fatal"],
+        default="info",
+    )
+    parser.add_argument(
+        "-c", dest="config_path", help="Config file for architectures.", default="arch_config.json", type=Path
+    )
+    parser.add_argument(
+        "-g", dest="grammar", help="Path to the tree-sitter C++ grammar.", default="vendor/tree-sitter-cpp", type=Path
+    )
+    parser.add_argument(
+        "-l", dest="lang_so", help="File to store the compiled C++ language.", default="build/ts-cpp.so", type=Path
+    )
+    arguments = parser.parse_args()
+    return arguments
+
+
+if __name__ == "__main__":
+    args = parse_args()
+    log.basicConfig(
+        level=convert_loglevel(args.verbosity),
+        stream=sys.stdout,
+        format="%(levelname)-5s - %(message)s",
+    )
+    cfg = Configurator(args.arch, args.config_path, args.grammar, args.lang_so)
+
+    differ = Differ(cfg, args.no_auto_apply)
+    try:
+        differ.diff()
+    except Exception as e:
+        raise e
+    finally:
+        print("\nSave choices...\n")
+        differ.save_to_persistence_file()
diff --git a/suite/auto-sync/CppTranslator/Helper.py b/suite/auto-sync/CppTranslator/Helper.py
new file mode 100644
index 000000000..aab854ed6
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Helper.py
@@ -0,0 +1,141 @@
+import hashlib
+import logging as log
+import shutil
+import subprocess
+from pathlib import Path
+
+import termcolor
+
+from tree_sitter import Node
+
+
+def convert_loglevel(level: str) -> int:
+    if level == "debug":
+        return log.DEBUG
+    elif level == "info":
+        return log.INFO
+    elif level == "warning":
+        return log.WARNING
+    elif level == "error":
+        return log.ERROR
+    elif level == "fatal":
+        return log.FATAL
+    elif level == "critical":
+        return log.CRITICAL
+    raise ValueError(f'Unknown loglevel "{level}"')
+
+
+def find_id_by_type(node: Node, node_types: [str], type_must_match: bool) -> bytes:
+    """
+    Recursively searches for a node sequence with given node types.
+
+    A valid sequence is a path from !\f$node_n\f$ to !\f$node_{(n + |node\_types|-1)}\f$ where
+    !\f$\forall i \in \{0, ..., |node\_types|-1\}: type(node_{(n + i)}) = node\_types_i\f$.
+
+    If a node sequence is found, this functions returns the text associated with the
+    last node in the sequence.
+
+    :param node: Current node.
+    :param node_types: List of node types.
+    :param type_must_match: If true, it is mandatory for the current node that its type matches node_types[0]
+    :return: The nodes text of the last node in a valid sequence of and empty string of no such sequence exists.
+    """
+    if len(node_types) == 0:
+        # No ids left to compare to: Nothing found
+        return b""
+
+    # Set true if:
+    #     current node type matches.
+    #  OR
+    #     parent dictates that node type match
+    type_must_match = node.type == node_types[0] or type_must_match
+    if type_must_match and node.type != node_types[0]:
+        # This child has no matching type. Return.
+        return b""
+
+    if len(node_types) == 1 and type_must_match:
+        if node.type == node_types[0]:
+            # Found it
+            return node.text
+        else:
+            # Not found. Return to parent
+            return b""
+
+    # If this nodes type matches the first in the list
+    # we remove this one from the list.
+    # Otherwise, give the whole list to the child (since our type does not matter).
+    children_id_types = node_types[1:] if type_must_match else node_types
+
+    # Check if any child has a matching type.
+    for child in node.named_children:
+        res = find_id_by_type(child, children_id_types, type_must_match)
+        if res:
+            # A path from this node matches the id_types!
+            return res
+
+    # None of our children matched the type list.
+    return b""
+
+
+def print_prominent_warning(msg: str) -> None:
+    print("\n" + separator_line_1("yellow"))
+    print(termcolor.colored("WARNING", "yellow", attrs=["bold"]) + "\n")
+    print(msg)
+    print(separator_line_1("yellow"))
+    input("Press enter to continue...\n")
+
+
+def term_width() -> int:
+    return shutil.get_terminal_size()[0]
+
+
+def print_prominent_info(msg: str) -> None:
+    print("\n" + separator_line_1("blue"))
+    print(msg)
+    print(separator_line_1("blue"))
+    input("Press enter to continue...\n")
+
+
+def bold(msg: str, color: str = None) -> str:
+    if color:
+        return termcolor.colored(msg, attrs=["bold"], color=color)
+    return termcolor.colored(msg, attrs=["bold"])
+
+
+def colored(msg: str, color: str) -> str:
+    return termcolor.colored(msg, color=color)
+
+
+def separator_line_1(color: str = None) -> str:
+    return f"{bold(f'⎼' * int(term_width() / 2), color)}\n"
+
+
+def separator_line_2(color: str = None) -> str:
+    return f"{bold(f'═' * int(term_width() / 2), color)}\n"
+
+
+def get_sha256(data: bytes) -> str:
+    h = hashlib.sha256()
+    h.update(data)
+    return h.hexdigest()
+
+
+def get_header() -> str:
+    return (
+        "/* Capstone Disassembly Engine, http://www.capstone-engine.org */\n"
+        "/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */\n"
+        "/*    Rot127 <unisono@quyllur.org> 2022-2023 */\n"
+        "/* Automatically translated source file from LLVM. */\n\n"
+        "/* LLVM-commit: <commit> */\n"
+        "/* LLVM-tag: <tag> */\n\n"
+        "/* Only small edits allowed. */\n"
+        "/* For multiple similiar edits, please create a Patch for the translator. */\n\n"
+        "/* Capstone's C++ file translator: */\n"
+        "/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */\n\n"
+    )
+
+
+def run_clang_format(out_paths: list[Path], clang_format_file: Path):
+    for out_file in out_paths:
+        log.info(f"Format {out_file}")
+        subprocess.run(["clang-format-16", f"-style=file:{clang_format_file.absolute().name}", "-i", out_file])
diff --git a/suite/auto-sync/CppTranslator/Patches/AddCSDetail.py b/suite/auto-sync/CppTranslator/Patches/AddCSDetail.py
new file mode 100644
index 000000000..11bd97691
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/AddCSDetail.py
@@ -0,0 +1,95 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_MCInst_var_name, template_param_list_to_dict
+from Patches.Patch import Patch
+
+
+class AddCSDetail(Patch):
+    """
+    Adds calls to `add_cs_detail()` for printOperand functions in <ARCH>InstPrinter.c
+
+    Patch   void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O) {...}
+    to      void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O) {
+                add_cs_detail(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, ...);
+                ...
+            }
+    """
+
+    # Parameter lists of printOperand() functions we need to add `add_cs_detail()` to.
+    # SPaces are removed, so we only need to check the letters.
+    valid_param_lists = [
+        b"(MCInst*MI,unsignedOpNum,SStream*O)",  # Default printOperand parameters.
+        b"(MCInst*MI,unsignedOpNo,SStream*O)",  # ARM - printComplexRotationOp
+        b"(SStream*O,ARM_AM::ShiftOpcShOpc,unsignedShImm,boolgetUseMarkup())",  # ARM - printRegImmShift
+    ]
+
+    def __init__(self, priority: int, arch: str):
+        super().__init__(priority)
+        self.arch = arch
+        self.apply_only_to = {"files": ["ARMInstPrinter.cpp"], "archs": list()}
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(function_definition"
+            "   (_)+"
+            "   (function_declarator"
+            '       ((identifier) @fcn_id (#match? @fcn_id "print.*"))'
+            "       ((parameter_list) @p_list)"
+            "   )"
+            "   (compound_statement) @comp_stmt"
+            ") @print_op"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "print_op"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        fcn_def: Node = captures[0][0]
+        params = captures[2][0]
+        params = get_text(src, params.start_byte, params.end_byte)
+        if re.sub(b" ", b"", params) not in self.valid_param_lists:
+            return get_text(src, fcn_def.start_byte, fcn_def.end_byte)
+
+        fcn_id = captures[1][0]
+        fcn_id = get_text(src, fcn_id.start_byte, fcn_id.end_byte)
+
+        add_cs_detail = self.get_add_cs_detail(src, fcn_def, fcn_id, params)
+
+        comp = captures[3][0]
+        comp = get_text(src, comp.start_byte, comp.end_byte)
+        return b"void " + fcn_id + params + b"{ " + add_cs_detail + comp.strip(b"{")
+
+    def get_add_cs_detail(self, src: bytes, fcn_def: Node, fcn_id: bytes, params: bytes) -> bytes:
+        op_group_enum = self.arch.encode("utf8") + b"_OP_GROUP_" + fcn_id[5:]  # Remove "print" from function id
+
+        is_template = fcn_def.prev_sibling.type == "template_parameter_list"
+        op_num_var_name = b"OpNum" if b"OpNum" in params else (b"OpNo" if b"OpNo" in params else b"-.-")
+        if not is_template and op_num_var_name in params:
+            # Standard printOperand() parameters
+            mcinst_var = get_MCInst_var_name(src, fcn_def)
+            return b"add_cs_detail(" + mcinst_var + b", " + op_group_enum + b", " + op_num_var_name + b");"
+        elif op_group_enum == b"ARM_OP_GROUP_RegImmShift":
+            return b"add_cs_detail(MI, " + op_group_enum + b", ShOpc, ShImm);"
+        elif is_template and op_num_var_name in params:
+            mcinst_var = get_MCInst_var_name(src, fcn_def)
+            templ_p = template_param_list_to_dict(fcn_def.prev_sibling)
+            cs_args = b""
+            for tp in templ_p:
+                op_group_enum = b"CONCAT(" + op_group_enum + b", " + tp["identifier"] + b")"
+                cs_args += b", " + tp["identifier"]
+            return (
+                b"add_cs_detail("
+                + mcinst_var
+                + b", "
+                + op_group_enum
+                + b", "
+                + op_num_var_name
+                + b" "
+                + cs_args
+                + b");"
+            )
+        log.fatal(f"Case {op_group_enum} not handled.")
+        exit(1)
diff --git a/suite/auto-sync/CppTranslator/Patches/AddOperand.py b/suite/auto-sync/CppTranslator/Patches/AddOperand.py
new file mode 100644
index 000000000..89b338901
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/AddOperand.py
@@ -0,0 +1,38 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class AddOperand(Patch):
+    """
+    Patch   MI.addOperand(...)
+    to      MCInst_addOperand(MI, ...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        q = (
+            "(call_expression "
+            "   (field_expression"
+            "       ((identifier) @inst_var)"
+            '       ((field_identifier) @field_id_op (#eq? @field_id_op "addOperand"))'
+            "   )"
+            "   ((argument_list) @arg_list)"
+            ") @add_operand"
+        )
+        return q
+
+    def get_main_capture_name(self) -> str:
+        return "add_operand"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get instruction variable name (MI, Inst)
+        inst_var: Node = captures[1][0]
+        # Arguments of getOperand(...)
+        get_op_args = captures[3][0]
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        args = get_text(src, get_op_args.start_byte, get_op_args.end_byte)
+        return b"MCInst_addOperand2(" + inst + b", " + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/Assert.py b/suite/auto-sync/CppTranslator/Patches/Assert.py
new file mode 100644
index 000000000..1ce516604
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/Assert.py
@@ -0,0 +1,32 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class Assert(Patch):
+    """
+    Patch   Remove asserts
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(expression_statement"
+            "   (call_expression"
+            '       ((identifier) @id (#eq? @id "assert"))'
+            "       (argument_list)"
+            "   )"
+            ") @assert"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "assert"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""
diff --git a/suite/auto-sync/CppTranslator/Patches/CheckDecoderStatus.py b/suite/auto-sync/CppTranslator/Patches/CheckDecoderStatus.py
new file mode 100644
index 000000000..a03cbad82
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/CheckDecoderStatus.py
@@ -0,0 +1,34 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class CheckDecoderStatus(Patch):
+    """
+    Patch  "Check(S, ..."
+    to     "Check(&S, ..."
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            '    ((identifier) @fcn_name (#eq? @fcn_name "Check"))'
+            "    ((argument_list) @arg_list)"
+            ") @check_call"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "check_call"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        call_expr: Node = captures[0][0]
+        first_arg: Node = captures[2][0].named_children[0]
+
+        call_text = get_text(src, call_expr.start_byte, call_expr.end_byte)
+        first_arg_text = get_text(src, first_arg.start_byte, first_arg.end_byte)
+
+        return call_text.replace(first_arg_text + b",", b"&" + first_arg_text + b",")
diff --git a/suite/auto-sync/CppTranslator/Patches/ClassConstructorDef.py b/suite/auto-sync/CppTranslator/Patches/ClassConstructorDef.py
new file mode 100644
index 000000000..0b8f29747
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/ClassConstructorDef.py
@@ -0,0 +1,28 @@
+from tree_sitter import Node
+from Patches.Patch import Patch
+
+
+class ClassConstructorDef(Patch):
+    """
+    Removes Class constructor definitions with a field initializer list.
+    Removes Class::Class(...) : ... {}
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        q = (
+            "(function_definition"
+            "   (function_declarator)"
+            "   (field_initializer_list)"
+            "   (compound_statement)"
+            ") @class_constructor"
+        )
+        return q
+
+    def get_main_capture_name(self) -> str:
+        return "class_constructor"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""
diff --git a/suite/auto-sync/CppTranslator/Patches/ClassesDef.py b/suite/auto-sync/CppTranslator/Patches/ClassesDef.py
new file mode 100644
index 000000000..df5751ed8
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/ClassesDef.py
@@ -0,0 +1,42 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class ClassesDef(Patch):
+    """
+    Patch   Class definitions
+    to      Removes class but extracts method declarations.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(class_specifier (_)* ((field_declaration_list) @decl_list)*) @class_specifier"
+
+    def get_main_capture_name(self) -> str:
+        return "class_specifier"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        field_decl_list = captures[1][0]
+        functions = list()
+        for field_decl in field_decl_list.named_children:
+            if (
+                field_decl.type in "field_declaration"
+                and ("function_declarator" in [t.type for t in field_decl.named_children])
+            ) or field_decl.type == "template_declaration":
+                # Keep comments
+                sibling = field_decl.prev_named_sibling
+                while sibling.type == "comment":
+                    functions.append(sibling)
+                    sibling = sibling.prev_named_sibling
+                functions.append(field_decl)
+        fcn_decl_text = b""
+        for f in functions:
+            fcn_decl_text += get_text(src, f.start_byte, f.end_byte) + b"\n"
+        return fcn_decl_text
diff --git a/suite/auto-sync/CppTranslator/Patches/ConstMCInstParameter.py b/suite/auto-sync/CppTranslator/Patches/ConstMCInstParameter.py
new file mode 100644
index 000000000..eb074735a
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/ConstMCInstParameter.py
@@ -0,0 +1,33 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class ConstMCInstParameter(Patch):
+    """
+    Patch   const MCInst *MI
+    to      MCInst *MI
+
+    Removes the const qualifier from MCInst parameters because functions like MCInst_getOperand() ignore them anyway.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(parameter_declaration"
+            "   ((type_qualifier) @type_qualifier)"
+            '   ((type_identifier) @type_id (#eq? @type_id "MCInst"))'
+            "   (pointer_declarator) @ptr_decl"
+            ") @mcinst_param"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "mcinst_param"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        inst = captures[3][0]
+        inst = get_text(src, inst.start_byte, inst.end_byte)
+        return b"MCInst " + inst
diff --git a/suite/auto-sync/CppTranslator/Patches/ConstMCOperand.py b/suite/auto-sync/CppTranslator/Patches/ConstMCOperand.py
new file mode 100644
index 000000000..d1192f536
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/ConstMCOperand.py
@@ -0,0 +1,33 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class ConstMCOperand(Patch):
+    """
+    Patch   const MCOperand ...
+    to      MCOperand
+
+    Removes the const qualifier from MCOperand declarations. They are ignored by the following functions.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(declaration"
+            "   (type_qualifier)"
+            '   ((type_identifier) @tid (#eq? @tid "MCOperand"))'
+            "   (init_declarator) @init_decl"
+            ") @const_mcoperand"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "const_mcoperand"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        init_decl = captures[2][0]
+        init_decl = get_text(src, init_decl.start_byte, init_decl.end_byte)
+        return b"MCOperand " + init_decl + b";"
diff --git a/suite/auto-sync/CppTranslator/Patches/CreateOperand0.py b/suite/auto-sync/CppTranslator/Patches/CreateOperand0.py
new file mode 100644
index 000000000..c2e524cd8
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/CreateOperand0.py
@@ -0,0 +1,53 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class CreateOperand0(Patch):
+    """
+    Patch   Inst.addOperand(MCOperand::createReg(...));
+    to      MCOperand_CreateReg0(...)
+    (and equivalent for CreateImm)
+
+    This is the `0` variant of the CS `CreateReg`/`CreateImm` functions. It is used if the
+    operand is added via `addOperand()`.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression "
+            "    (field_expression ((identifier) @inst_var"
+            '                        (field_identifier) @field_id (#eq? @field_id "addOperand")))'
+            "    (argument_list (call_expression "
+            "                        (qualified_identifier ((_) (identifier) @create_fcn))"
+            "                        (argument_list) @arg_list"
+            "                    )"
+            "    )"
+            ") @create_operand0"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "create_operand0"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get name of instruction variable
+        inst_var: Node = captures[1][0]
+        # Get 'create[Reg/Imm]'
+        op_create_fcn: Node = captures[3][0]
+        # Get arg list
+        op_create_args: Node = captures[4][0]
+
+        # Capstone spells the function with capital letter 'C' for whatever reason.
+        fcn = re.sub(b"create", b"Create", get_text(src, op_create_fcn.start_byte, op_create_fcn.end_byte))
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        args = get_text(src, op_create_args.start_byte, op_create_args.end_byte)
+        if args[0] == b"(" and args[-1] == b")":
+            args = args
+        return b"MCOperand_" + fcn + b"0(" + inst + b", " + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/CreateOperand1.py b/suite/auto-sync/CppTranslator/Patches/CreateOperand1.py
new file mode 100644
index 000000000..e42f64466
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/CreateOperand1.py
@@ -0,0 +1,70 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_MCInst_var_name
+from Patches.Patch import Patch
+
+
+class CreateOperand1(Patch):
+    """
+    Patch   MI.insert(..., MCOperand::createReg(...));
+    to      MCInst_insert0(..., MCOperand_createReg1(...));
+    (and equivalent for CreateImm)
+
+    This is the `1` variant of the CS `CreateReg`/`CreateImm` functions. It is used if the
+    operand is added via `insert()`.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression "
+            "    (field_expression ((identifier) @MC_id"
+            '                       ((field_identifier) @field_id (#match? @field_id "insert")))'
+            "    )"
+            "    (argument_list"
+            "        ((identifier) @inst_var"
+            "         (call_expression"
+            "            (qualified_identifier ((_) (identifier) @create_fcn))"
+            "            (argument_list) @arg_list)"
+            "        )"
+            "    )"
+            ") @create_operand1"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "create_operand1"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get instruction variable
+        inst_var: Node = captures[1][0]
+        # Get argument of .insert() call
+        insert_arg: Node = captures[3][0]
+        # Get 'create[Reg/Imm]'
+        op_create_fcn: Node = captures[4][0]
+        # CreateReg/Imm args
+        op_create_args: Node = captures[5][0]
+
+        insert_arg_t = get_text(src, insert_arg.start_byte, insert_arg.end_byte)
+        # Capstone spells the function with capital letter 'C' for whatever reason.
+        fcn = re.sub(b"create", b"Create", get_text(src, op_create_fcn.start_byte, op_create_fcn.end_byte))
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        args = get_text(src, op_create_args.start_byte, op_create_args.end_byte)
+        return (
+            b"MCInst_insert0("
+            + inst
+            + b", "
+            + insert_arg_t
+            + b", "
+            + b"MCOperand_"
+            + fcn
+            + b"1("
+            + get_MCInst_var_name(src, inst_var)
+            + b", "
+            + args
+            + b"))"
+        )
diff --git a/suite/auto-sync/CppTranslator/Patches/DeclarationInConditionClause.py b/suite/auto-sync/CppTranslator/Patches/DeclarationInConditionClause.py
new file mode 100644
index 000000000..db4611bcd
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/DeclarationInConditionClause.py
@@ -0,0 +1,45 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class DeclarationInConditionalClause(Patch):
+    """
+    Patch   if (DECLARATION) ...
+    to      DECLARATION
+            if (VAR) ...
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(if_statement"
+            "   (condition_clause"
+            "       (declaration"
+            "           (_)"
+            "           ((identifier) @id)"
+            "           (_)"
+            "       ) @decl"
+            "   )"
+            "   (_) @if_body"
+            ") @condition_clause"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "condition_clause"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        declaration = captures[1][0]
+        identifier = captures[2][0]
+        if_body = captures[3][0]
+        identifier = get_text(src, identifier.start_byte, identifier.end_byte)
+        declaration = get_text(src, declaration.start_byte, declaration.end_byte)
+        if_body = get_text(src, if_body.start_byte, if_body.end_byte)
+        res = declaration + b";\nif (" + identifier + b")\n" + if_body
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/DecodeInstruction.py b/suite/auto-sync/CppTranslator/Patches/DecodeInstruction.py
new file mode 100644
index 000000000..51461c17a
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/DecodeInstruction.py
@@ -0,0 +1,46 @@
+import logging as log
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class DecodeInstruction(Patch):
+    """
+    Patch   decodeInstruction(..., this, STI)
+    to      decodeInstruction_<instr_width>(...)
+
+    It also removes the arguments `this, STI`.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression ("
+            '   (identifier) @fcn_name (#eq? @fcn_name "decodeInstruction")'
+            "   ((argument_list) @arg_list)"
+            ")) @decode_instr"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "decode_instr"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        arg_list = captures[2][0]
+        args_text = get_text(src, arg_list.start_byte, arg_list.end_byte).strip(b"()")
+
+        table, mi_inst, opcode_var, address, this, sti = args_text.split(b",")
+        is_32bit = table[-2:].decode("utf8") == "32" or opcode_var[-2:].decode("utf8") == "32"
+        is_16bit = table[-2:].decode("utf8") == "16" or opcode_var[-2:].decode("utf8") == "16"
+        args = table + b", " + mi_inst + b", " + opcode_var + b", " + address
+
+        if is_16bit and not is_32bit:
+            return b"decodeInstruction_2(" + args + b")"
+        elif is_32bit and not is_16bit:
+            return b"decodeInstruction_4(" + args + b")"
+        else:
+            # Cannot determine instruction width easily. Only update the calls arguments.
+            return b"decodeInstruction(" + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/DecoderCast.py b/suite/auto-sync/CppTranslator/Patches/DecoderCast.py
new file mode 100644
index 000000000..e480fe803
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/DecoderCast.py
@@ -0,0 +1,39 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class DecoderCast(Patch):
+    """
+    Patch   Removes casts like `const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);`
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(declaration"
+            "   (type_qualifier)*"
+            '   ((type_identifier) @tid (#eq? @tid "MCDisassembler"))'
+            "   (init_declarator"
+            "       (pointer_declarator)"
+            "       (call_expression"
+            "           (template_function)"  # static_cast<const MCDisassembler>
+            "           (argument_list"
+            '               ((identifier) @id (#eq? @id "Decoder"))'
+            "           )"
+            "       )"
+            "   )"
+            ") @decoder_cast"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "decoder_cast"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""
diff --git a/suite/auto-sync/CppTranslator/Patches/DecoderParameter.py b/suite/auto-sync/CppTranslator/Patches/DecoderParameter.py
new file mode 100644
index 000000000..7fb8e1310
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/DecoderParameter.py
@@ -0,0 +1,32 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class DecoderParameter(Patch):
+    """
+    Patch   const MCDisassembler *Decoder
+    to      const void *Decoder
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(parameter_declaration"
+            "   ((type_qualifier) @type_qualifier)"
+            '   ((type_identifier) @type_id (#eq? @type_id "MCDisassembler"))'
+            "   (pointer_declarator) @ptr_decl"
+            ") @decoder_param"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "decoder_param"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b"const void *Decoder"
diff --git a/suite/auto-sync/CppTranslator/Patches/FallThrough.py b/suite/auto-sync/CppTranslator/Patches/FallThrough.py
new file mode 100644
index 000000000..26a990964
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/FallThrough.py
@@ -0,0 +1,21 @@
+from tree_sitter import Node
+from Patches.Patch import Patch
+
+
+class FallThrough(Patch):
+    """
+    Patch   [[fallthrough]]
+    to      // fall through
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return '(attributed_statement) @attr (#match? @attr "fallthrough")'
+
+    def get_main_capture_name(self) -> str:
+        return "attr"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b"// fall through"
diff --git a/suite/auto-sync/CppTranslator/Patches/FeatureBits.py b/suite/auto-sync/CppTranslator/Patches/FeatureBits.py
new file mode 100644
index 000000000..01da8e390
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/FeatureBits.py
@@ -0,0 +1,37 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_function_params_of_node, get_MCInst_var_name
+from Patches.Patch import Patch
+
+
+class FeatureBits(Patch):
+    """
+    Patch   featureBits[FLAG]
+    to      ARCH_getFeatureBits(Inst->csh->mode, ...)
+    """
+
+    def __init__(self, priority: int, arch: bytes):
+        self.arch = arch
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        # Search for featureBits usage.
+        return (
+            "(subscript_expression "
+            '   ((identifier) @id (#match? @id "[fF]eatureBits"))'
+            "   ((qualified_identifier) @qid)"
+            ") @feature_bits"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "feature_bits"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get flag name of feature bit.
+        qualified_id: Node = captures[2][0]
+        flag = get_text(src, qualified_id.start_byte, qualified_id.end_byte)
+        mcinst_var_name = get_MCInst_var_name(src, qualified_id)
+        return self.arch + b"_getFeatureBits(" + mcinst_var_name + b"->csh->mode, " + flag + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/FeatureBitsDecl.py b/suite/auto-sync/CppTranslator/Patches/FeatureBitsDecl.py
new file mode 100644
index 000000000..030a2984f
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/FeatureBitsDecl.py
@@ -0,0 +1,31 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class FeatureBitsDecl(Patch):
+    """
+    Patch   ... featureBits = ...
+    to      REMOVED
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        # Search for featureBits declarations.
+        return (
+            "(declaration (init_declarator (reference_declarator "
+            '((identifier) @id (#match? @id "[fF]eatureBits"))))) @feature_bits_decl'
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "feature_bits_decl"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Remove declaration
+        return b""
diff --git a/suite/auto-sync/CppTranslator/Patches/FieldFromInstr.py b/suite/auto-sync/CppTranslator/Patches/FieldFromInstr.py
new file mode 100644
index 000000000..108508054
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/FieldFromInstr.py
@@ -0,0 +1,66 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_function_params_of_node
+from Patches.Patch import Patch
+
+
+class FieldFromInstr(Patch):
+    """
+    Patch   fieldFromInstr(...)
+    to      fieldFromInstr_<instr_width>(...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        # Search for fieldFromInstruction() calls.
+        return (
+            "(call_expression"
+            '   ((identifier) @fcn_name (#eq? @fcn_name "fieldFromInstruction"))'
+            "   (argument_list ((identifier) @first_arg) (_) (_))"
+            ") @field_from_instr"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "field_from_instr"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        ffi_call: Node = captures[0][0]
+        ffi_first_arg: Node = captures[2][0]
+        param_list_caller = get_function_params_of_node(ffi_call)
+        ffi_first_arg_text = get_text(src, ffi_first_arg.start_byte, ffi_first_arg.end_byte).decode("utf8")
+
+        # Determine width of instruction by the variable name.
+        if ffi_first_arg_text[-2:] == "32":
+            inst_width = 4
+        elif ffi_first_arg_text[-2:] == "16":
+            inst_width = 2
+        else:
+            # Get the Val/Inst parameter.
+            # Its type determines the instruction width.
+            inst_param: Node = param_list_caller.named_children[1]
+            inst_param_text = get_text(src, inst_param.start_byte, inst_param.end_byte)
+
+            # Search for the 'Inst' parameter and determine its type
+            # and with it the width of the instruction.
+            inst_type = inst_param_text.split(b" ")[0]
+            if inst_type:
+                if inst_type in [b"unsigned", b"uint32_t"]:
+                    inst_width = 4
+                elif inst_type in [b"uint16_t"]:
+                    inst_width = 2
+                else:
+                    log.fatal(f"Type {inst_type} no handled.")
+                    exit(1)
+            else:
+                # Needs manual fix
+                return get_text(src, ffi_call.start_byte, ffi_call.end_byte)
+        return re.sub(
+            rb"fieldFromInstruction",
+            b"fieldFromInstruction_%d" % inst_width,
+            get_text(src, ffi_call.start_byte, ffi_call.end_byte),
+        )
diff --git a/suite/auto-sync/CppTranslator/Patches/GetNumOperands.py b/suite/auto-sync/CppTranslator/Patches/GetNumOperands.py
new file mode 100644
index 000000000..4a97483e5
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/GetNumOperands.py
@@ -0,0 +1,38 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class GetNumOperands(Patch):
+    """
+    Patch   MI.getNumOperands()
+    to      MCInst_getNumOperands(MI)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        q = (
+            "(call_expression "
+            "   (field_expression"
+            "       ((identifier) @inst_var)"
+            '       ((field_identifier) @field_id_op (#eq? @field_id_op "getNumOperands"))'
+            "   )"
+            "   ((argument_list) @arg_list)"
+            ") @get_num_operands"
+        )
+        return q
+
+    def get_main_capture_name(self) -> str:
+        return "get_num_operands"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get instruction variable name: MI, Inst etc.
+        inst_var: Node = captures[1][0]
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        return b"MCInst_getNumOperands(" + inst + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/GetOpcode.py b/suite/auto-sync/CppTranslator/Patches/GetOpcode.py
new file mode 100644
index 000000000..cfff27c20
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/GetOpcode.py
@@ -0,0 +1,44 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class GetOpcode(Patch):
+    """
+    Patch   Inst.getOpcode()
+    to      MCInst_getOpcode(Inst)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            "    (field_expression ("
+            "        ((identifier) @inst_var)"
+            '        ((field_identifier) @field_id (#eq? @field_id "getOpcode")))'
+            "     )"
+            "    (argument_list) @arg_list"
+            ") @get_opcode"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "get_opcode"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Instruction variable
+        inst_var: Node = captures[1][0]
+        arg_list: Node = captures[3][0]
+
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        args = get_text(src, arg_list.start_byte, arg_list.end_byte)
+        if args != b"()":
+            args = b", " + args
+        else:
+            args = b""
+        return b"MCInst_getOpcode(" + inst + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/GetOperand.py b/suite/auto-sync/CppTranslator/Patches/GetOperand.py
new file mode 100644
index 000000000..8a5b4d79b
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/GetOperand.py
@@ -0,0 +1,41 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class GetOperand(Patch):
+    """
+    Patch   MI.getOperand(...)
+    to      MCInst_getOperand(MI, ...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        q = (
+            "(call_expression "
+            "   (field_expression"
+            "       ((identifier) @inst_var)"
+            '       ((field_identifier) @field_id_op (#eq? @field_id_op "getOperand"))'
+            "   )"
+            "   ((argument_list) @arg_list)"
+            ") @get_operand"
+        )
+        return q
+
+    def get_main_capture_name(self) -> str:
+        return "get_operand"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get instruction variable name (MI, Inst)
+        inst_var: Node = captures[1][0]
+        # Arguments of getOperand(...)
+        get_op_args = captures[3][0]
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        args = get_text(src, get_op_args.start_byte, get_op_args.end_byte)
+        return b"MCInst_getOperand(" + inst + b", " + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/GetOperandRegImm.py b/suite/auto-sync/CppTranslator/Patches/GetOperandRegImm.py
new file mode 100644
index 000000000..549fe8783
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/GetOperandRegImm.py
@@ -0,0 +1,42 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class GetOperandRegImm(Patch):
+    """
+    Patch   OPERAND.getReg()
+    to      MCOperand_getReg(OPERAND)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        q = (
+            "(call_expression"
+            "    (field_expression"
+            "        ((_) @operand)"
+            '        ((field_identifier) @field_id (#match? @field_id "get[RI][em][gm]"))'
+            "    )"
+            "    (argument_list)"
+            ") @get_operand"
+        )
+        return q
+
+    def get_main_capture_name(self) -> str:
+        return "get_operand"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # The operand
+        operand: Node = captures[1][0]
+        # 'getReg()/getImm()'
+        get_reg_imm = captures[2][0]
+
+        fcn = get_text(src, get_reg_imm.start_byte, get_reg_imm.end_byte)
+        op = get_text(src, operand.start_byte, operand.end_byte)
+        return b"MCOperand_" + fcn + b"(" + op + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/GetSubReg.py b/suite/auto-sync/CppTranslator/Patches/GetSubReg.py
new file mode 100644
index 000000000..0439a59d0
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/GetSubReg.py
@@ -0,0 +1,40 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_MCInst_var_name
+from Patches.Patch import Patch
+
+
+class GetSubReg(Patch):
+    """
+    Patch   MRI.getSubReg(...);
+    to      MCRegisterInfo_getSubReg(MI->MRI, ...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            "    (field_expression ("
+            "        (identifier)"
+            '        ((field_identifier) @field_id (#eq? @field_id "getSubReg")))'
+            "     )"
+            "    (argument_list) @arg_list"
+            ") @get_sub_reg"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "get_sub_reg"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get arg list
+        op_create_args: Node = captures[2][0]
+
+        # Capstone spells the function with capital letter 'C' for whatever reason.
+        args = get_text(src, op_create_args.start_byte, op_create_args.end_byte).strip(b"()")
+        mcinst_var_name = get_MCInst_var_name(src, op_create_args)
+        return b"MCRegisterInfo_getSubReg(" + mcinst_var_name + b"->MRI, " + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/HelperMethods.py b/suite/auto-sync/CppTranslator/Patches/HelperMethods.py
new file mode 100644
index 000000000..2fdfa50ce
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/HelperMethods.py
@@ -0,0 +1,107 @@
+import re
+
+from tree_sitter import Node
+import logging as log
+
+
+def get_function_params_of_node(n: Node) -> Node:
+    """
+    Returns for a given node the parameters of the function this node is a children from.
+    Or None if the node is not part of a function definition.
+    """
+    fcn_def: Node = n
+    while fcn_def.type != "function_definition":
+        if fcn_def.parent == None:
+            # root node reached
+            return None
+        fcn_def = fcn_def.parent
+
+    # Get parameter list of the function definition
+    param_list: Node = None
+    for child in fcn_def.children:
+        if child.type == "function_declarator":
+            param_list = child.children[1]
+            break
+    if not param_list:
+        log.warning(f"Could not find the functions parameter list for {n.text}")
+    return param_list
+
+
+def get_MCInst_var_name(src: bytes, n: Node) -> bytes:
+    """Searches for the name of the parameter of type MCInst and returns it."""
+    params = get_function_params_of_node(n)
+    mcinst_var_name = b""
+    for p in params.named_children:
+        p_text = get_text(src, p.start_byte, p.end_byte)
+        if b"MCInst" in p_text:
+            mcinst_var_name = p_text.split((b"&" if b"&" in p_text else b"*"))[1]
+            break
+    if mcinst_var_name == b"":
+        log.debug("Could not find `MCInst` variable name. Defaulting to `Inst`.")
+        mcinst_var_name = b"Inst"
+    return mcinst_var_name
+
+
+def template_param_list_to_dict(param_list: Node) -> [dict]:
+    if param_list.type != "template_parameter_list":
+        log.fatal(f"Node of type {param_list.type} given. Not 'template_parameter_list'.")
+    pl = list()
+    for c in param_list.named_children:
+        pl.append(parameter_declaration_to_dict(c))
+    return pl
+
+
+def parameter_declaration_to_dict(param_decl: Node) -> dict:
+    if param_decl.type != "parameter_declaration":
+        log.fatal(f"Node of type {param_decl.type} given. Not 'parameter_declaration'.")
+    return {
+        "prim_type": param_decl.children[0].type == "primitive_type",
+        "type": param_decl.children[0].text,
+        "identifier": param_decl.children[1].text,
+    }
+
+
+def get_text(src: bytes, start_byte: int, end_byte: int) -> bytes:
+    """Workaround for https://github.com/tree-sitter/py-tree-sitter/issues/122"""
+    return src[start_byte:end_byte]
+
+
+def namespace_enum(src: bytes, ns_id: bytes, enum: Node) -> bytes:
+    """
+    Alters an enum in the way that it prepends the namespace id to every enum member.
+    Example: naemspace_id = "ARM"
+             enum { X } -> enum { ARM_X }
+    """
+    enumerator_list: Node = None
+    for c in enum.named_children:
+        if c.type == "enumerator_list":
+            enumerator_list = c
+
+    if not enumerator_list:
+        log.fatal("Could not find enumerator_list.")
+        exit(1)
+
+    res = get_text(src, enum.start_byte, enum.end_byte)
+    for e in enumerator_list.named_children:
+        if e.type == "enumerator":
+            enum_entry_text = get_text(src, e.start_byte, e.end_byte)
+            res = re.sub(enum_entry_text, ns_id + b"_" + enum_entry_text, res)
+    return res
+
+
+def namespace_fcn_def(src: bytes, ns_id: bytes, fcn_def: Node) -> bytes:
+    fcn_id: Node = None
+    for c in fcn_def.named_children:
+        if c.type == "function_declarator":
+            fcn_id = c.named_children[0]
+            break
+        elif c.named_children and c.named_children[0].type == "function_declarator":
+            fcn_id = c.named_children[0].named_children[0]
+            break
+    if not fcn_id:
+        log.fatal("Could not find function declarator in one of the first children.")
+        exit(1)
+    fcn_id_text = get_text(src, fcn_id.start_byte, fcn_id.end_byte)
+    fcn_def_text = get_text(src, fcn_def.start_byte, fcn_def.end_byte)
+    res = re.sub(fcn_id_text, ns_id + b"_" + fcn_id_text, fcn_def_text)
+    return res
diff --git a/suite/auto-sync/CppTranslator/Patches/Includes.py b/suite/auto-sync/CppTranslator/Patches/Includes.py
new file mode 100644
index 000000000..c199eec71
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/Includes.py
@@ -0,0 +1,120 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class Includes(Patch):
+    """
+    Patch   LLVM includes
+    to      Capstone includes
+    """
+
+    include_count = dict()
+
+    def __init__(self, priority: int, arch: str):
+        self.arch = arch
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(preproc_include) @preproc_include"
+
+    def get_main_capture_name(self) -> str:
+        return "preproc_include"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        filename = kwargs["filename"]
+        if filename not in self.include_count:
+            self.include_count[filename] = 1
+        else:
+            self.include_count[filename] += 1
+
+        include_text = get_text(src, captures[0][0].start_byte, captures[0][0].end_byte)
+        # Special cases, which appear somewhere in the code.
+        if b"GenDisassemblerTables.inc" in include_text:
+            return b'#include "' + bytes(self.arch, "utf8") + b'GenDisassemblerTables.inc"\n\n'
+        elif b"GenAsmWriter.inc" in include_text:
+            return b'#include "' + bytes(self.arch, "utf8") + b'GenAsmWriter.inc"\n\n'
+
+        if self.include_count[filename] > 1:
+            # Only the first include is replaced with all CS includes.
+            return b""
+
+        # All includes which belong to the source files top.
+        res = get_general_inc()
+        if self.arch == "ARM":
+            return res + get_ARM_includes(filename) + get_general_macros()
+        else:
+            log.fatal(f"Includes of {self.arch} not handled.")
+            exit(1)
+
+
+def get_general_inc() -> bytes:
+    return (
+        b"#include <stdio.h>\n"
+        + b"#include <string.h>\n"
+        + b"#include <stdlib.h>\n"
+        + b"#include <capstone/platform.h>\n\n"
+    )
+
+
+def get_ARM_includes(filename: str) -> bytes:
+    if filename == "ARMDisassembler.cpp":
+        return (
+            b'#include "../../LEB128.h"\n'
+            + b'#include "../../MCDisassembler.h"\n'
+            + b'#include "../../MCFixedLenDisassembler.h"\n'
+            + b'#include "../../MCInst.h"\n'
+            + b'#include "../../MCInstrDesc.h"\n'
+            + b'#include "../../MCRegisterInfo.h"\n'
+            + b'#include "../../MathExtras.h"\n'
+            + b'#include "../../cs_priv.h"\n'
+            + b'#include "../../utils.h"\n'
+            + b'#include "ARMAddressingModes.h"\n'
+            + b'#include "ARMBaseInfo.h"\n'
+            + b'#include "ARMDisassemblerExtension.h"\n'
+            + b'#include "ARMInstPrinter.h"\n'
+            + b'#include "ARMLinkage.h"\n'
+            + b'#include "ARMMapping.h"\n\n'
+            + b"#define GET_INSTRINFO_MC_DESC\n"
+            + b'#include "ARMGenInstrInfo.inc"\n\n'
+        )
+    elif filename == "ARMInstPrinter.cpp":
+        return (
+            b'#include "../../Mapping.h"\n'
+            + b'#include "../../MCInst.h"\n'
+            + b'#include "../../MCInstPrinter.h"\n'
+            + b'#include "../../MCRegisterInfo.h"\n'
+            + b'#include "../../SStream.h"\n'
+            + b'#include "../../utils.h"\n'
+            + b'#include "ARMAddressingModes.h"\n'
+            + b'#include "ARMBaseInfo.h"\n'
+            + b'#include "ARMDisassemblerExtension.h"\n'
+            + b'#include "ARMInstPrinter.h"\n'
+            + b'#include "ARMLinkage.h"\n'
+            + b'#include "ARMMapping.h"\n\n'
+            + b'#define GET_BANKEDREG_IMPL\n'
+            + b'#include "ARMGenSystemRegister.inc"\n'
+        )
+    elif filename == "ARMInstPrinter.h":
+        return (
+            b'#include "ARMMapping.h"\n\n'
+            + b'#include "../../MCInst.h"\n'
+            + b'#include "../../SStream.h"\n'
+            + b'#include "../../MCRegisterInfo.h"\n'
+            + b'#include "../../MCInstPrinter.h"\n'
+            + b'#include "../../utils.h"\n\n'
+        )
+    elif filename == "ARMBaseInfo.cpp":
+        return b'#include "ARMBaseInfo.h"\n\n'
+    elif filename == "ARMAddressingModes.h":
+        return b"#include <assert.h>\n" + b'#include "../../MathExtras.h"\n\n'
+    log.fatal(f"No includes given for ARM source file: {filename}")
+    exit(1)
+
+
+def get_general_macros():
+    return b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n"
diff --git a/suite/auto-sync/CppTranslator/Patches/InlineToStaticInline.py b/suite/auto-sync/CppTranslator/Patches/InlineToStaticInline.py
new file mode 100644
index 000000000..81ae0099f
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/InlineToStaticInline.py
@@ -0,0 +1,32 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class InlineToStaticInline(Patch):
+    """
+    Removes the qualified identifier of the class from method definitions.
+    Translating them to functions.
+
+    Patch   inline void FUNCTION(...) {...}
+    to      static inline void FUNCTION(...) {...}
+
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+        self.apply_only_to = {"files": ["ARMAddressingModes.h"], "archs": list()}
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(function_definition" '   ((storage_class_specifier) @scs (#eq? @scs "inline"))' "   (_)+" ") @inline_def"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "inline_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        inline_def = captures[0][0]
+        inline_def = get_text(src, inline_def.start_byte, inline_def.end_byte)
+        return b"static " + inline_def
diff --git a/suite/auto-sync/CppTranslator/Patches/IsOptionalDef.py b/suite/auto-sync/CppTranslator/Patches/IsOptionalDef.py
new file mode 100644
index 000000000..3fcd3a22d
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/IsOptionalDef.py
@@ -0,0 +1,40 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class IsOptionalDef(Patch):
+    """
+    Patch   OpInfo[i].isPredicate()
+    to      MCOperandInfo_isPredicate(&OpInfo[i])
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            "   (field_expression"
+            "       (subscript_expression"
+            "           ((identifier) @op_info_var)"
+            "           ((_) @index)"
+            "       )"
+            '       ((field_identifier) @fid (#eq? @fid "isOptionalDef"))'
+            "   )"
+            ") @is_optional_def"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "is_optional_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        op_info_var = captures[1][0]
+        index = captures[2][0]
+        op_info_var = get_text(src, op_info_var.start_byte, op_info_var.end_byte)
+        index = get_text(src, index.start_byte, index.end_byte)
+        return b"MCOperandInfo_isOptionalDef(&" + op_info_var + b"[" + index + b"])"
diff --git a/suite/auto-sync/CppTranslator/Patches/IsPredicate.py b/suite/auto-sync/CppTranslator/Patches/IsPredicate.py
new file mode 100644
index 000000000..272ea32b1
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/IsPredicate.py
@@ -0,0 +1,40 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class IsPredicate(Patch):
+    """
+    Patch   OpInfo[i].isPredicate()
+    to      MCOperandInfo_isPredicate(&OpInfo[i])
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            "   (field_expression"
+            "       (subscript_expression"
+            "           ((identifier) @op_info_var)"
+            "           ((_) @index)"
+            "       )"
+            '       ((field_identifier) @fid (#eq? @fid "isPredicate"))'
+            "   )"
+            ") @is_predicate"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "is_predicate"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        op_info_var = captures[1][0]
+        index = captures[2][0]
+        op_info_var = get_text(src, op_info_var.start_byte, op_info_var.end_byte)
+        index = get_text(src, index.start_byte, index.end_byte)
+        return b"MCOperandInfo_isPredicate(&" + op_info_var + b"[" + index + b"])"
diff --git a/suite/auto-sync/CppTranslator/Patches/LLVMFallThrough.py b/suite/auto-sync/CppTranslator/Patches/LLVMFallThrough.py
new file mode 100644
index 000000000..89270e34a
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/LLVMFallThrough.py
@@ -0,0 +1,25 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class LLVMFallThrough(Patch):
+    """
+    Patch   Remove LLVM_FALLTHROUGH
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(expression_statement" '   ((identifier) @id (#eq? @id "LLVM_FALLTHROUGH"))' ") @llvm_fall_through"
+
+    def get_main_capture_name(self) -> str:
+        return "llvm_fall_through"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""
diff --git a/suite/auto-sync/CppTranslator/Patches/LLVMunreachable.py b/suite/auto-sync/CppTranslator/Patches/LLVMunreachable.py
new file mode 100644
index 000000000..d49ddc202
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/LLVMunreachable.py
@@ -0,0 +1,31 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class LLVMUnreachable(Patch):
+    """
+    Patch   llvm_unreachable("Error msg")
+    to      assert(0 && "Error msg")
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression ("
+            '   (identifier) @fcn_name (#eq? @fcn_name "llvm_unreachable")'
+            "   (argument_list) @err_msg"
+            ")) @llvm_unreachable"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "llvm_unreachable"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        err_msg = captures[2][0]
+        err_msg = get_text(src, err_msg.start_byte, err_msg.end_byte).strip(b"()")
+        res = b"assert(0 && " + err_msg + b")"
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/MethodToFunctions.py b/suite/auto-sync/CppTranslator/Patches/MethodToFunctions.py
new file mode 100644
index 000000000..59d7298c5
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/MethodToFunctions.py
@@ -0,0 +1,43 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class MethodToFunction(Patch):
+    """
+    Removes the qualified identifier of the class from method definitions.
+    Translating them to functions.
+
+    Patch   void CLASS::METHOD_NAME(...) {...}
+    to      void METHOD_NAME(...) {...}
+
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(function_declarator"
+            "   (qualified_identifier"
+            "       (namespace_identifier)"
+            "       (identifier) @method_name"
+            "   )"
+            "   (parameter_list) @param_list"
+            ") @method_def"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "method_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        name = captures[1][0]
+        parameter_list = captures[2][0]
+        name = get_text(src, name.start_byte, name.end_byte)
+        parameter_list = get_text(src, parameter_list.start_byte, parameter_list.end_byte)
+        res = name + parameter_list
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/MethodTypeQualifier.py b/suite/auto-sync/CppTranslator/Patches/MethodTypeQualifier.py
new file mode 100644
index 000000000..5a9701632
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/MethodTypeQualifier.py
@@ -0,0 +1,37 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class MethodTypeQualifier(Patch):
+    """
+    Patch   Removes type qualifiers like "const" etc. from methods.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(function_declarator"
+            "    (["
+            "        (qualified_identifier)"
+            "        (identifier)"
+            "    ]) @id"
+            "    (parameter_list) @param_list"
+            "    (type_qualifier)"
+            ")"
+            "@method_type_qualifier"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "method_type_qualifier"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        identifier = captures[1][0]
+        parameter_list = captures[2][0]
+        identifier = get_text(src, identifier.start_byte, identifier.end_byte)
+        p_list = get_text(src, parameter_list.start_byte, parameter_list.end_byte)
+        res = identifier + p_list
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/NamespaceAnon.py b/suite/auto-sync/CppTranslator/Patches/NamespaceAnon.py
new file mode 100644
index 000000000..c6c46ebf8
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/NamespaceAnon.py
@@ -0,0 +1,27 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class NamespaceAnon(Patch):
+    """
+    Patch   namespace {CONTENT}
+    to      CONTENT
+
+    Only for anonymous or llvm namespaces
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(namespace_definition" "   (declaration_list) @decl_list" ") @namespace_def"
+
+    def get_main_capture_name(self) -> str:
+        return "namespace_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        decl_list = captures[1][0]
+        dl = get_text(src, decl_list.start_byte, decl_list.end_byte).strip(b"{}")
+        return dl
diff --git a/suite/auto-sync/CppTranslator/Patches/NamespaceArch.py b/suite/auto-sync/CppTranslator/Patches/NamespaceArch.py
new file mode 100644
index 000000000..f3f5d9e3f
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/NamespaceArch.py
@@ -0,0 +1,39 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, namespace_enum, namespace_fcn_def
+from Patches.Patch import Patch
+
+
+class NamespaceArch(Patch):
+    """
+    Patch   namespace ArchSpecificNamespace {CONTENT}
+    to      CONTENT
+
+    Patches namespaces specific to architecture. This needs to patch enums and functions within this namespace.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(namespace_definition" "   (identifier)" "   (declaration_list) @decl_list" ") @namespace_def"
+
+    def get_main_capture_name(self) -> str:
+        return "namespace_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        namespace = captures[0][0]
+        decl_list = captures[1][0]
+        namespace_id = get_text(src, namespace.named_children[0].start_byte, namespace.named_children[0].end_byte)
+
+        # We need to prepend the namespace id to all enum members and function declarators.
+        # Because in the generated files they are accessed via NAMESPACE::X which becomes NAMESPACE_X.
+        res = b""
+        for d in decl_list.named_children:
+            if d.type == "enum_specifier":
+                res += namespace_enum(src, namespace_id, d) + b";\n\n"
+            elif d.type == "function_definition":
+                res += namespace_fcn_def(src, namespace_id, d) + b"\n\n"
+            else:
+                res += get_text(src, d.start_byte, d.end_byte) + b"\n"
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/NamespaceLLVM.py b/suite/auto-sync/CppTranslator/Patches/NamespaceLLVM.py
new file mode 100644
index 000000000..31204e04e
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/NamespaceLLVM.py
@@ -0,0 +1,32 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class NamespaceLLVM(Patch):
+    """
+    Patch   namespace {CONTENT}
+    to      CONTENT
+
+    Only for anonymous or llvm namespaces
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(namespace_definition"
+            '   (identifier) @id (#eq? @id "llvm")'
+            "   (declaration_list) @decl_list"
+            ") @namespace_def"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "namespace_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        decl_list = captures[2][0]
+        dl = get_text(src, decl_list.start_byte, decl_list.end_byte).strip(b"{}")
+        return dl
diff --git a/suite/auto-sync/CppTranslator/Patches/OutStreamParam.py b/suite/auto-sync/CppTranslator/Patches/OutStreamParam.py
new file mode 100644
index 000000000..907aa2c03
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/OutStreamParam.py
@@ -0,0 +1,42 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class OutStreamParam(Patch):
+    """
+    Patch   raw_ostream &OS
+    to      SStream *OS
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(parameter_list"
+            "   (_)*"
+            "   (parameter_declaration"
+            '       ((type_identifier) @tid (#eq? @tid "raw_ostream"))'
+            "       (_)"
+            "   )"
+            "   (_)*"
+            ") @ostream_param"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "ostream_param"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        param_list = list()
+        for param in captures[0][0].named_children:
+            p_text = get_text(src, param.start_byte, param.end_byte)
+            if b"raw_ostream" in p_text:
+                p_text = p_text.replace(b"raw_ostream", b"SStream").replace(b"&", b"*")
+            param_list.append(p_text)
+        res = b"(" + b", ".join(param_list) + b")"
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/Patch.py b/suite/auto-sync/CppTranslator/Patches/Patch.py
new file mode 100644
index 000000000..54e71fcfa
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/Patch.py
@@ -0,0 +1,53 @@
+from tree_sitter import Tree, Node
+import logging as log
+
+
+class Patch:
+    priority: int = None
+
+    # List of filenames and architectures this patch applies to or not.
+    # Order of testing:
+    # 1. apply_only_to.archs
+    # 2. apply_only_to.files
+    # 3. do_not_apply.archs
+    # 4. do_not_apply.files
+    # Contains the filenames and architectures this patch should be applied to. Empty list means all.
+    apply_only_to = {"files": list(), "archs": list()}
+    # Contains the filenames and architectures this patch should NOT be applied to.
+    do_not_apply = {"files": list(), "archs": list()}
+
+    def __init__(self, priority: int = 0):
+        self.priority = priority
+
+    def get_search_pattern(self) -> str:
+        """
+        Returns a search pattern for the syntax tree of the C++ file.
+        The search pattern must be formed according to:
+        https://tree-sitter.github.io/tree-sitter/using-parsers#pattern-matching-with-queries
+
+        Also, each pattern needs to be assigned a name in order to work.
+        See: https://github.com/tree-sitter/py-tree-sitter/issues/77
+
+        :return: The search pattern which matches a part in the syntax tree which will be patched.
+        """
+        log.fatal("Method must be overloaded.")
+        exit(1)
+
+    def get_main_capture_name(self) -> str:
+        """
+        :return: The name of the capture which matches the complete syntax to be patched.
+        """
+        log.fatal("Method must be overloaded.")
+        exit(1)
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        """
+        Patches the given subtree accordingly and returns the patch as string.
+
+        :param src: The source code currently patched.
+        :param captures: The subtree and its name which needs to be patched.
+        :param **kwargs: Additional arguments the Patch might need.
+        :return: The patched version of the code.
+        """
+        log.fatal("Method must be overloaded.")
+        exit(1)
diff --git a/suite/auto-sync/CppTranslator/Patches/PredicateBlockFunctions.py b/suite/auto-sync/CppTranslator/Patches/PredicateBlockFunctions.py
new file mode 100644
index 000000000..075b0f31b
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/PredicateBlockFunctions.py
@@ -0,0 +1,45 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_MCInst_var_name
+from Patches.Patch import Patch
+
+
+class PredicateBlockFunctions(Patch):
+    """
+    Patch   VPTBlock.instrInVPTBlock()
+    to      VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))
+
+    And other functions of VPTBlock and ITBlock
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression "
+            "   (field_expression"
+            '       ((identifier) @block_var (#match? @block_var "[VI][PT]T?Block"))'
+            "       ((field_identifier) @field_id)"
+            "   )"
+            "   ((argument_list) @arg_list)"
+            ") @block_fcns"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "block_fcns"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        block_var = captures[1][0]
+        fcn_id = captures[2][0]
+        args = captures[3][0]
+        block_var_text = get_text(src, block_var.start_byte, block_var.end_byte)
+        fcn_id_text = get_text(src, fcn_id.start_byte, fcn_id.end_byte)
+        args_text = get_text(src, args.start_byte, args.end_byte)
+        mcinst_var: bytes = get_MCInst_var_name(src, block_var)
+
+        a = b"&(" + mcinst_var + b"->csh->" + block_var_text + b")"
+        args_text = args_text.strip(b"()")
+        if args_text:
+            a += b"," + args_text
+        return block_var_text + b"_" + fcn_id_text + b"(" + a + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/PrintAnnotation.py b/suite/auto-sync/CppTranslator/Patches/PrintAnnotation.py
new file mode 100644
index 000000000..61b08b93d
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/PrintAnnotation.py
@@ -0,0 +1,25 @@
+from tree_sitter import Node
+from Patches.Patch import Patch
+
+
+class PrintAnnotation(Patch):
+    """
+    Removes printAnnotation(...) calls.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression ("
+            '   (identifier) @fcn_name (#eq? @fcn_name "printAnnotation")'
+            "   (argument_list)"
+            ")) @print_annotation"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "print_annotation"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""
diff --git a/suite/auto-sync/CppTranslator/Patches/PrintRegImmShift.py b/suite/auto-sync/CppTranslator/Patches/PrintRegImmShift.py
new file mode 100644
index 000000000..b25d4388b
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/PrintRegImmShift.py
@@ -0,0 +1,33 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_MCInst_var_name
+from Patches.Patch import Patch
+
+
+class PrintRegImmShift(Patch):
+    """
+    Patch   printRegImmShift(...)
+    to      printRegImmShift(MI, ...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+        self.apply_only_to = {"files": ["ARMInstPrinter.cpp"], "archs": list()}
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression ("
+            '   (identifier) @fcn_name (#eq? @fcn_name "printRegImmShift")'
+            "   ((argument_list) @arg_list)"
+            ")) @print_call"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "print_call"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        call: Node = captures[0][0]
+        mcinst_var = get_MCInst_var_name(src, call)
+        params = captures[2][0]
+        params = get_text(src, params.start_byte, params.end_byte)
+        return b"printRegImmShift(" + mcinst_var + b", " + params.strip(b"(")
diff --git a/suite/auto-sync/CppTranslator/Patches/QualifiedIdentifier.py b/suite/auto-sync/CppTranslator/Patches/QualifiedIdentifier.py
new file mode 100644
index 000000000..e1d6f20ac
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/QualifiedIdentifier.py
@@ -0,0 +1,30 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class QualifiedIdentifier(Patch):
+    """
+    Patch   NAMESPACE::ID
+    to      NAMESPACE_ID
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(qualified_identifier) @qualified_id"
+
+    def get_main_capture_name(self) -> str:
+        return "qualified_id"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        namespace = captures[0][0].named_children[0]
+        identifier = captures[0][0].named_children[1]
+        namespace = get_text(src, namespace.start_byte, namespace.end_byte)
+        identifier = get_text(src, identifier.start_byte, identifier.end_byte)
+        return namespace + b"_" + identifier
diff --git a/suite/auto-sync/CppTranslator/Patches/ReferencesDecl.py b/suite/auto-sync/CppTranslator/Patches/ReferencesDecl.py
new file mode 100644
index 000000000..bf5291ee5
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/ReferencesDecl.py
@@ -0,0 +1,31 @@
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class ReferencesDecl(Patch):
+    """
+    Patch   TYPE &Param
+    to      TYPE *Param
+
+    Param is optional
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "[" "(reference_declarator)" "(type_identifier) (abstract_reference_declarator)" "] @reference_decl"
+
+    def get_main_capture_name(self) -> str:
+        return "reference_decl"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        ref_decl: Node = captures[0][0]
+        ref_decl_text = get_text(src, ref_decl.start_byte, ref_decl.end_byte)
+
+        res = re.sub(rb"&", b"*", ref_decl_text)
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/STIArgument.py b/suite/auto-sync/CppTranslator/Patches/STIArgument.py
new file mode 100644
index 000000000..453a828c8
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/STIArgument.py
@@ -0,0 +1,30 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class STIArgument(Patch):
+    """
+    Patch   printSomeOperand(MI, NUM, STI, NUM)
+    to      printSomeOperand(MI, NUM, NUM)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return '(argument_list (_) (_) (_)? ((identifier) @id (#eq? @id "STI")) (_)) @sti_arg'
+
+    def get_main_capture_name(self) -> str:
+        return "sti_arg"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        param_list = list()
+        for param in captures[0][0].named_children:
+            p_text = get_text(src, param.start_byte, param.end_byte)
+            if b"STI" in p_text:
+                continue
+            param_list.append(p_text)
+        res = b"(" + b", ".join(param_list) + b")"
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/STIFeatureBits.py b/suite/auto-sync/CppTranslator/Patches/STIFeatureBits.py
new file mode 100644
index 000000000..93d0d8f8f
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/STIFeatureBits.py
@@ -0,0 +1,42 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class STIFeatureBits(Patch):
+    """
+    Patch   STI.getFeatureBits()[FLAG]
+    to      ARCH_getFeatureBits(Inst->csh->mode, ...)
+    """
+
+    def __init__(self, priority: int, arch: bytes):
+        self.arch = arch
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        # Search for featureBits usage.
+        return (
+            "(subscript_expression "
+            "   (call_expression"
+            "       (field_expression"
+            "           (identifier)"
+            '           ((field_identifier) @fid (#eq? @fid "getFeatureBits"))'
+            "       )"
+            "       (argument_list)"
+            "   )"
+            "   ((qualified_identifier) @flag)"
+            ") @sti_feature_bits"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "sti_feature_bits"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Get flag name of feature bit.
+        qualified_id: Node = captures[2][0]
+        flag = get_text(src, qualified_id.start_byte, qualified_id.end_byte)
+        return self.arch + b"_getFeatureBits(Inst->csh->mode, " + flag + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/STParameter.py b/suite/auto-sync/CppTranslator/Patches/STParameter.py
new file mode 100644
index 000000000..f4dc738ed
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/STParameter.py
@@ -0,0 +1,41 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class SubtargetInfoParam(Patch):
+    """
+    Patch   Removes MCSubtargetInfo &STI parameter
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(parameter_list"
+            "   (_)*"
+            "   (parameter_declaration"
+            '       ((type_identifier) @tid (#eq? @tid "MCSubtargetInfo"))'
+            "       (_)"
+            "   )"
+            "   (_)*"
+            ") @subtarget_info_param"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "subtarget_info_param"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        param_list = list()
+        for param in captures[0][0].named_children:
+            p_text = get_text(src, param.start_byte, param.end_byte)
+            if b"MCSubtargetInfo" in p_text:
+                continue
+            param_list.append(p_text)
+        res = b"(" + b", ".join(param_list) + b")"
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/SetOpcode.py b/suite/auto-sync/CppTranslator/Patches/SetOpcode.py
new file mode 100644
index 000000000..fee23a8a5
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/SetOpcode.py
@@ -0,0 +1,44 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class SetOpcode(Patch):
+    """
+    Patch   Inst.setOpcode(...)
+    to      MCInst_setOpcode(Inst, ...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            "    (field_expression ("
+            "        ((identifier) @inst_var)"
+            '        ((field_identifier) @field_id (#eq? @field_id "setOpcode")))'
+            "     )"
+            "    (argument_list) @arg_list"
+            ") @set_opcode"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "set_opcode"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        # Instruction variable
+        inst_var: Node = captures[1][0]
+        arg_list: Node = captures[3][0]
+
+        inst = get_text(src, inst_var.start_byte, inst_var.end_byte)
+        args = get_text(src, arg_list.start_byte, arg_list.end_byte)
+        if args != b"()":
+            args = b", " + args
+        else:
+            args = b""
+        return b"MCInst_setOpcode(" + inst + args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/SignExtend32.py b/suite/auto-sync/CppTranslator/Patches/SignExtend32.py
new file mode 100644
index 000000000..82fb4ea04
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/SignExtend32.py
@@ -0,0 +1,43 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+from TemplateCollector import TemplateRefInstance, TemplateCollector
+
+
+class SignExtend32(Patch):
+    """
+    Patch   SignExtend32<A>(...)
+    to      SignExtend32(..., A)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(call_expression"
+            "     (template_function"
+            '         ((identifier) @name (#eq? @name "SignExtend32"))'
+            "         ((template_argument_list) @templ_args)"
+            "     )"
+            "     ((argument_list) @fcn_args)"
+            ") @sign_extend"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "sign_extend"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        se32: Node = captures[1][0]
+        templ_args: Node = captures[2][0]
+        fcn_args: Node = captures[3][0]
+
+        name = get_text(src, se32.start_byte, se32.end_byte)
+        t_args = get_text(src, templ_args.start_byte, templ_args.end_byte)
+        t_args = b", ".join(TemplateCollector.templ_params_to_list(t_args))
+        f_args = get_text(src, fcn_args.start_byte, fcn_args.end_byte)
+        return name + b"(" + f_args + b", " + t_args + b")"
diff --git a/suite/auto-sync/CppTranslator/Patches/SizeAssignments.py b/suite/auto-sync/CppTranslator/Patches/SizeAssignments.py
new file mode 100644
index 000000000..1f4144e2d
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/SizeAssignments.py
@@ -0,0 +1,39 @@
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text, get_function_params_of_node
+from Patches.Patch import Patch
+
+
+class SizeAssignment(Patch):
+    """
+    Patch   Size = <num>
+    to      *Size = <num>
+
+    if Size is a reference.
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "(assignment_expression" '    ((identifier) @id (#eq? @id "Size"))' ") @assign"
+
+    def get_main_capture_name(self) -> str:
+        return "assign"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        assign = captures[0][0]
+        assign_text = get_text(src, assign.start_byte, assign.end_byte)
+
+        param_list = get_function_params_of_node(assign)
+        if not param_list:
+            return assign_text
+
+        for p in param_list.named_children:
+            p_text = get_text(src, p.start_byte, p.end_byte)
+            if b"&Size" in p_text:
+                return re.sub(b"Size", b"*Size", assign_text)
+
+        return assign_text
diff --git a/suite/auto-sync/CppTranslator/Patches/StreamOperation.py b/suite/auto-sync/CppTranslator/Patches/StreamOperation.py
new file mode 100644
index 000000000..c5845e651
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/StreamOperation.py
@@ -0,0 +1,96 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class StreamOperations(Patch):
+    """
+    Patch   OS << ...
+    to      SStream_concat(OS, ...)
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(expression_statement"
+            "   (binary_expression"
+            "       ((binary_expression)"
+            '       "<<"'
+            "       (_))*"
+            "   ) @bin_expr"
+            ") @stream"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "stream"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        bin_expr = captures[1][0]
+        # Extract operands passed to the stream into a list.
+        ops = list()
+        while bin_expr.type == "binary_expression":
+            ops.append(bin_expr.named_children[1])
+            bin_expr = bin_expr.named_children[0]
+        s_name = get_text(src, bin_expr.start_byte, bin_expr.end_byte)
+        # We added the operands from right to left.
+        # We reversing it so the left most operand comes first.
+        ops.reverse()
+
+        res = b""
+        # Capstone uses the following functions to copy the strings to a buffer:
+        # SStream_concat  - Copies multiple strings.
+        # SStream_concat1 - Copies a char.
+        # SStream_concat0 - Copies a string and null terminates the buffer.
+        last_op: Node = ops[-1]
+        op: Node = ops[0]
+        string_ops = list()
+        i = 0
+        while op != last_op:
+            if op.type == "char_literal":
+                if len(string_ops) != 0:
+                    # Make a SStream_concat call with all string literals collected before.
+                    res += (
+                        b"SStream_concat("
+                        + s_name
+                        + b', "'
+                        + b"%s" * len(string_ops)
+                        + b'", '
+                        + b", ".join([get_text(src, o.start_byte, o.end_byte) for o in string_ops])
+                        + b");\n"
+                    )
+                    string_ops.clear()
+                res += b"SStream_concat1(" + s_name + b", " + get_text(src, op.start_byte, op.end_byte) + b");\n"
+            else:
+                string_ops.append(op)
+            i += 1
+            op = ops[i]
+
+        if len(string_ops) != 0:
+            res += (
+                b"SStream_concat("
+                + s_name
+                + b', "'
+                + b"%s" * len(string_ops)
+                + b'", '
+                + b", ".join([get_text(src, o.start_byte, o.end_byte) for o in string_ops])
+                + b");\n"
+            )
+            string_ops.clear()
+
+        last_op_text = get_text(src, last_op.start_byte, last_op.end_byte)
+        if last_op.type == "char_literal":
+            res += b"SStream_concat0(" + s_name + b", " + last_op_text.replace(b"'", b'"') + b");\n"
+        else:
+            res += b"SStream_concat0(" + s_name + b", " + last_op_text + b");"
+        stream = captures[0][0]
+        if len(ops) > 1 and stream.parent.type in ["if_statement"]:
+            # If statements without {} brackets might execute a single line `OS << ...;` statement.
+            # Which we then translate into multiple lines. For this case we need to add the brackets.
+            res = b"{ " + res + b" }"
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/TemplateDeclaration.py b/suite/auto-sync/CppTranslator/Patches/TemplateDeclaration.py
new file mode 100644
index 000000000..3e3a31b2f
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/TemplateDeclaration.py
@@ -0,0 +1,73 @@
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+from TemplateCollector import TemplateCollector, TemplateRefInstance
+
+
+class TemplateDeclaration(Patch):
+    """
+    Patch   template<A, B>
+            RET_TYPE TemplateFunction(...);
+
+    to      #define DECLARE_TemplateFunction_A_B \
+            RET_TYPE CONCAT(TemplateFunction, CONCAT(A, B))(...);
+    """
+
+    def __init__(self, priority: int, template_collector: TemplateCollector):
+        self.collector: TemplateCollector = template_collector
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(template_declaration"
+            "     ((template_parameter_list) @templ_params)"
+            "     (declaration"
+            "        ((storage_class_specifier)* @storage_class_id)"
+            "        ([(type_identifier)(primitive_type)] @type_id)"
+            "        (function_declarator"
+            "            ((identifier) @fcn_name)"
+            "            ((parameter_list) @fcn_params)"
+            "        )"
+            "     )"
+            ") @template_decl"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "template_decl"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        has_storage_class_id = any([c[1] == "storage_class_id" for c in captures])
+        templ_params: Node = captures[1][0]
+        if has_storage_class_id:
+            sc_id: Node = captures[2][0]
+            type_id: Node = captures[3][0]
+            fcn_name: Node = captures[4][0]
+            fcn_params: Node = captures[5][0]
+        else:
+            sc_id = None
+            type_id: Node = captures[2][0]
+            fcn_name: Node = captures[3][0]
+            fcn_params: Node = captures[4][0]
+
+        t_params: list = TemplateCollector.templ_params_to_list(
+            get_text(src, templ_params.start_byte, templ_params.end_byte)
+        )
+        sc = get_text(src, sc_id.start_byte, sc_id.end_byte) + b" " if has_storage_class_id else b""
+        tid = get_text(src, type_id.start_byte, type_id.end_byte)
+        f_name = get_text(src, fcn_name.start_byte, fcn_name.end_byte)
+        f_params = get_text(src, fcn_params.start_byte, fcn_params.end_byte)
+
+        declaration = b"#define DECLARE_" + f_name + b"(" + b", ".join(t_params) + b")\n"
+        declaration += sc + tid + b" " + TemplateCollector.get_macro_c_call(f_name, t_params, f_params) + b";"
+        declaration = declaration.replace(b"\n", b" \\\n") + b"\n"
+
+        template_instance: TemplateRefInstance
+        declared_implementations = list()
+        for template_instance in self.collector.template_refs[f_name]:
+            d = b"DECLARE_" + f_name + b"(" + b", ".join(template_instance.args_list) + b")\n"
+            if d in declared_implementations:
+                continue
+            declared_implementations.append(d)
+            declaration += d
+        return declaration
diff --git a/suite/auto-sync/CppTranslator/Patches/TemplateDefinition.py b/suite/auto-sync/CppTranslator/Patches/TemplateDefinition.py
new file mode 100644
index 000000000..47fbddfcf
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/TemplateDefinition.py
@@ -0,0 +1,81 @@
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+from TemplateCollector import TemplateCollector, TemplateRefInstance
+
+
+class TemplateDefinition(Patch):
+    """
+    Patch   template<A, B>
+            RET_TYPE TemplateFunction(...) {...}
+
+    to      #define DEFINE_TemplateFunction_A_B \
+            RET_TYPE CONCAT(TemplateFunction, CONCAT(A, B))(...) {...}
+    """
+
+    def __init__(self, priority: int, template_collector: TemplateCollector):
+        self.collector: TemplateCollector = template_collector
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(template_declaration"
+            "     ((template_parameter_list) @templ_params)"
+            "     (function_definition"
+            "        ((storage_class_specifier)* @storage_class_id)"
+            "        ([(type_identifier)(primitive_type)] @type_id)"
+            "        (function_declarator"
+            "            ((identifier) @fcn_name)"
+            "            ((parameter_list) @fcn_params)"
+            "        )"
+            "        ((compound_statement) @compound)"
+            "     )"
+            ") @template_def"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "template_def"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        has_storage_class_id = any([c[1] == "storage_class_id" for c in captures])
+        templ_params: Node = captures[1][0]
+        if has_storage_class_id:
+            sc_id: Node = captures[2][0]
+            type_id: Node = captures[3][0]
+            fcn_name: Node = captures[4][0]
+            fcn_params: Node = captures[5][0]
+            compound: Node = captures[6][0]
+        else:
+            sc_id = None
+            type_id: Node = captures[2][0]
+            fcn_name: Node = captures[3][0]
+            fcn_params: Node = captures[4][0]
+            compound: Node = captures[5][0]
+
+        t_params: list = TemplateCollector.templ_params_to_list(
+            get_text(src, templ_params.start_byte, templ_params.end_byte)
+        )
+        sc = get_text(src, sc_id.start_byte, sc_id.end_byte) + b" " if has_storage_class_id else b""
+        tid = get_text(src, type_id.start_byte, type_id.end_byte)
+        f_name = get_text(src, fcn_name.start_byte, fcn_name.end_byte)
+        f_params = get_text(src, fcn_params.start_byte, fcn_params.end_byte)
+        f_compound = get_text(src, compound.start_byte, compound.end_byte)
+
+        definition = b"#define DEFINE_" + f_name + b"(" + b", ".join(t_params) + b")\n"
+        definition += sc + tid + b" " + TemplateCollector.get_macro_c_call(f_name, t_params, f_params) + f_compound
+        # Remove // comments
+        definition = re.sub(b" *//.*", b"", definition)
+        definition = definition.replace(b"\n", b" \\\n") + b"\n"
+
+        template_instance: TemplateRefInstance
+        declared_implementations = list()
+        for template_instance in self.collector.template_refs[f_name]:
+            d = b"DEFINE_" + f_name + b"(" + b", ".join(template_instance.args_list) + b")\n"
+            if d in declared_implementations:
+                continue
+            declared_implementations.append(d)
+            definition += d
+        return definition
diff --git a/suite/auto-sync/CppTranslator/Patches/TemplateParamDecl.py b/suite/auto-sync/CppTranslator/Patches/TemplateParamDecl.py
new file mode 100644
index 000000000..0a158e32e
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/TemplateParamDecl.py
@@ -0,0 +1,47 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class TemplateParamDecl(Patch):
+    """
+    Example:
+
+    Patch   ArrayRef<uint8_t> x
+    to      const uint8_t *x
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(parameter_declaration"
+            "   (template_type"
+            "       (type_identifier) @templ_type"
+            "       (template_argument_list) @arg_list"
+            "   )"
+            "   (identifier) @param_id"
+            ") @template_param_decl"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "template_param_decl"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        template_type = captures[1][0]
+        arg_list = captures[2][0]
+        param_id = captures[3][0]
+        templ_type = get_text(src, template_type.start_byte, template_type.end_byte)
+        args = get_text(src, arg_list.start_byte, arg_list.end_byte)
+        p_id = get_text(src, param_id.start_byte, param_id.end_byte)
+
+        if templ_type == b"ArrayRef":
+            res = b"const " + args.strip(b"<>") + b" *" + p_id
+            return res
+        log.fatal(f"Template type {templ_type} not handled as parameter")
+        exit(1)
diff --git a/suite/auto-sync/CppTranslator/Patches/TemplateRefs.py b/suite/auto-sync/CppTranslator/Patches/TemplateRefs.py
new file mode 100644
index 000000000..5ecd1fad9
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/TemplateRefs.py
@@ -0,0 +1,41 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+from TemplateCollector import TemplateRefInstance, TemplateCollector
+
+
+class TemplateRefs(Patch):
+    """
+    Patch   TemplateFunction<A, B>
+    to      CONCAT(TemplateFunction, CONCAT(A, B))
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return (
+            "(template_function"
+            "     ((identifier) @name)"
+            "     ((template_argument_list) @templ_args)"
+            ") @template_refs"
+        )
+
+    def get_main_capture_name(self) -> str:
+        return "template_refs"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        tc: Node = captures[1][0]
+        templ_args: Node = captures[2][0]
+
+        name = get_text(src, tc.start_byte, tc.end_byte)
+        t_params = get_text(src, templ_args.start_byte, templ_args.end_byte)
+        if name == b"static_cast":
+            return t_params.replace(b"<", b"(").replace(b">", b")")
+        t_params_list = TemplateCollector.templ_params_to_list(t_params)
+        res = TemplateCollector.get_macro_c_call(name, t_params_list)
+        return res
diff --git a/suite/auto-sync/CppTranslator/Patches/UseMarkup.py b/suite/auto-sync/CppTranslator/Patches/UseMarkup.py
new file mode 100644
index 000000000..73bfb8f8a
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/UseMarkup.py
@@ -0,0 +1,21 @@
+from tree_sitter import Node
+from Patches.Patch import Patch
+
+
+class UseMarkup(Patch):
+    """
+    Patch   UseMarkup
+    to      getUseMarkup()
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return '((identifier) @use_markup (#eq? @use_markup "UseMarkup"))'
+
+    def get_main_capture_name(self) -> str:
+        return "use_markup"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b"getUseMarkup()"
diff --git a/suite/auto-sync/CppTranslator/Patches/UsingDeclaration.py b/suite/auto-sync/CppTranslator/Patches/UsingDeclaration.py
new file mode 100644
index 000000000..fe161783b
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/Patches/UsingDeclaration.py
@@ -0,0 +1,25 @@
+import logging as log
+import re
+
+from tree_sitter import Node
+
+from Patches.HelperMethods import get_text
+from Patches.Patch import Patch
+
+
+class UsingDeclaration(Patch):
+    """
+    Patch   Removes declarations with the keyword "using"
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return "([(using_declaration) (alias_declaration)]) @using_declaration"
+
+    def get_main_capture_name(self) -> str:
+        return "using_declaration"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""
diff --git a/suite/auto-sync/CppTranslator/README.md b/suite/auto-sync/CppTranslator/README.md
new file mode 100644
index 000000000..2f337abda
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/README.md
@@ -0,0 +1,161 @@
+# C++ Translator
+
+Capstone uses source files from LLVM to disassemble opcodes.
+Because LLVM is written in C++ we must translate those files to C.
+
+The task of the `CppTranslator` is to do just that.
+The translation will not result in a completely correct C file! But it takes away most of the manual work.
+
+## The configuration file
+
+The configuration for each architecture is set in `arch_config.json`.
+
+The config values have the following meaning:
+
+- `General`: Settings valid for all architectures.
+   - `clang_format_file`: Path to Capstone's `.clang-format` file.
+   - `patch_persistent_file`: Path to the file which saves the selections from the `Differ`.
+   - `cs_arch_src`: Path to Capstone's `arch` directory.
+   - `translation_out_dir`: Path to the directory where the `CppTranslator` stores its files.
+   - `diff_out_dir`: Path to the directory where the `Differ` stores its files.
+   - `diff_color_new`: Color in the `Differ` for translated content.
+   - `diff_color_old`: Color in the `Differ` for old/current Capstone content.
+   - `diff_color_saved`: Color in the `Differ` for saved content.
+   - `diff_color_edited`: Color in the `Differ` for edited content.
+   - `nodes_to_diff`: List of parse tree nodes which get diffed - *Mind the note below*.
+      - `node_type`: The `type` of the node to be diffed.
+      - `identifier_node_type`: Types of child nodes which identify the node during diffing (the identifier must be the same in the translated and the old file!).
+- `<ARCH>`: Settings valid for a specific architecture
+   - `files_to_translate`: A list of file paths to translate.
+      - `in`: *Path* to a specific source file.
+      - `out`: The *filename* of the translated file.
+   - `files_for_template_search`: List of file paths to search for calls to template functions.
+   - `manually_edite_files`: List of files which are too complicated to translate. The user will be warned about them.
+
+_Note_: To understand the `nodes_to_diff` setting, check out `Differ.py`.
+
+## Translation process
+
+The translation process simply searches for certain syntax and patches it.
+
+To allow searches for complicated patterns we parse the C++ file with Tree-sitter.
+Afterward we can use [pattern queries](https://tree-sitter.github.io/tree-sitter/using-parsers#pattern-matching-with-queries)
+to find our syntax we would like to patch.
+
+Here is an overview of the procedure:
+
+- First the source file is parsed with Tree-Sitter.
+- Afterward the translator iterates of a number of patches.
+
+For each patch we do the following.
+
+```
+
+ Translator                                  Patch
+   +---+
+   |   |                                     +----+
+   |   |  Request pattern to search for      |    |
+   |   | ----------------------------------> |    |
+   |   |                                     |    |
+   |   |  Return pattern                     |    |
+   |   | <---------------------------------  |    |
+   |   |                                     |    |
+   |   | ---+                                |    |
+   |   |    | Find                           |    |
+   |   |    | captures                       |    |
+   |   |    | in src                         |    |
+   |   | <--+                                |    |
+   |   |                                     |    |
+   |   |  Return captures found              |    |
+   |   | ----------------------------------> |    |
+   |   |                                     |    |
+   |   |                                 +-- |    |
+   |   |                     Use capture |   |    |
+   |   |                     info to     |   |    |
+   |   |                     build new   |   |    |
+   |   |                     syntax str  |   |    |
+   |   |                                 +-> |    |
+   |   |                                     |    |
+   |   | Return new syntax string to patch   |    |
+   |   | <---------------------------------- |    |
+   |   |                                     |    |
+   |   | ---+                                |    |
+   |   |    | Replace old                    |    |
+   |   |    | with new syntax                |    |
+   |   |    | at all occurrences             |    |
+   |   |    | in the file.                   |    |
+   |   | <--+                                |    |
+   |   |                                     |    |
+   +---+                                     +----+
+```
+
+## C++ Template translation
+
+Most of the C++ syntax is simple to translate. But unfortunately the one exception are C++ templates.
+
+Translating template functions and calls from C++ to C is tricky.
+Since each template has a number of actual implementations we do the following.
+
+- A template function definition is translated into a C macro.
+- The template parameters get translated to the macro parameters.
+- To differentiate the C implementations, the functions follow the naming pattern `fcn_[template_param_0]_[template_param_1]()`
+
+<hr>
+
+**Example**
+
+This C++ template function
+
+```cpp
+template<unsigned X>
+void fcn() {
+   unsigned a = X * 8;
+}
+```
+becomes
+```
+#define DEFINE_FCN(X)  \
+void fcn ## _ ## X() { \
+   unsigned a = X * 8; \
+}
+```
+To define an implementation where `X = 0` we do
+```
+DEFINE_FCN(0)
+```
+To call this implementation we call `fcn_0()`.
+
+_(There is a special case when a template parameter is passed on to a template call. But this is explained in the code.)_
+<hr>
+
+### Enumerate template instances
+
+In our C++ code a template function can be called with different template parameters.
+For each of those calls we need to define a template implementation in C.
+
+To do that we first scan source files for calls to template functions (`TemplateCollector.py` does this).
+For each unique call we check the parameter list.
+Knowing the parameter list we can now define a C function which uses exactly those parameters.
+For the definition we use a macro as above.
+
+<hr>
+
+**Example**
+
+Within this C++ code we see two template function calls:
+
+```cpp
+void main() {
+   fcn<0>();
+   fcn<4>();
+}
+```
+With the knowledge that once parameter `1` and once parameter `4` was passed to the template,
+we can define the implementations with the help of our `DEFINE_FCN` macro.
+```c
+DEFINE_FCN(0)
+DEFINE_FCN(4)
+```
+
+Within the C code we can now call those with `fcn_0()` and `fcn_4()`.
+<hr>
diff --git a/suite/auto-sync/CppTranslator/TemplateCollector.py b/suite/auto-sync/CppTranslator/TemplateCollector.py
new file mode 100644
index 000000000..c11e44d50
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/TemplateCollector.py
@@ -0,0 +1,275 @@
+from copy import deepcopy
+from pathlib import Path
+
+from tree_sitter import Language, Parser
+import logging as log
+
+from tree_sitter.binding import Query, Node
+from Patches.HelperMethods import get_text
+
+
+class TemplateRefInstance:
+    """
+    Represents a concrete instance of a template function reference.
+    E.g. DecodeT2Imm7<shift, 2>
+    """
+
+    name: bytes
+    args: bytes
+    args_list: list
+    dependent_calls = list()
+
+    # Holds the indices of the caller template parameters which set the templ. parameters
+    # of this TemplateCallInstance.
+    # Structure: {caller_name: i, "self_i": k}
+    #
+    # Only used if this is an incomplete TemplateInstance
+    # (parameters are set by the template parameters of the calling function).
+    caller_param_indices: [{str: int}] = list()
+
+    def __init__(self, name: bytes, args: bytes, start_point, start_byte, end_point, end_byte):
+        self.name = name
+        self.args = args
+        self.start_point = start_point
+        self.start_byte = start_byte
+        self.end_point = end_point
+        self.end_byte = end_byte
+        self.args_list = TemplateCollector.templ_params_to_list(args)
+        self.templ_name = name + args
+
+    def __eq__(self, other):
+        return (
+            self.name == other.name
+            and self.args == other.args
+            and any([a == b for a, b in zip(self.caller_param_indices, other.caller_param_indices)])
+            and self.start_byte == other.start_byte
+            and self.start_point == other.start_point
+            and self.end_byte == other.end_byte
+            and self.end_point == other.end_point
+        )
+
+    def set_dep_calls(self, deps: list):
+        self.dependent_calls = deps
+
+    def get_c_name(self):
+        return b"_".join([self.name] + self.args_list)
+
+
+class TemplateCollector:
+    """
+    Searches through the given files for calls to template functions.
+    And creates a list with concrete template instances.
+    """
+
+    # List of completed template instances indexed by their name.
+    # One function can have multiple template instances. Depending on the template arguments
+    template_refs: {bytes: [TemplateRefInstance]} = dict()
+    # List of incomplete template instances indexed by the **function name they depend on**!
+    incomplete_template_refs: {bytes: [TemplateRefInstance]} = dict()
+    sources: [{str: bytes}] = list()
+
+    def __init__(self, ts_parser: Parser, ts_cpp: Language, searchable_files: [Path]):
+        self.parser = ts_parser
+        self.lang_cpp = ts_cpp
+        self.searchable_files = searchable_files
+
+    def collect(self):
+        self.read_files()
+        for x in self.sources:
+            path = x["path"]
+            src = x["content"]
+            log.debug(f"Search for template references in {path}")
+
+            tree = self.parser.parse(src, keep_text=True)
+            query: Query = self.lang_cpp.query(self.get_template_pattern())
+            self.get_capture_bundles(query, tree)
+            capture_bundles = self.get_capture_bundles(query, tree)
+
+            for cb in capture_bundles:
+                templ_name: Node = cb[1][0]
+                templ_args: Node = cb[2][0]
+                name = get_text(src, templ_name.start_byte, templ_name.end_byte)
+                args = get_text(src, templ_args.start_byte, templ_args.end_byte)
+
+                ti = TemplateRefInstance(
+                    name, args, cb[0][0].start_point, cb[0][0].start_byte, cb[0][0].end_point, cb[0][0].end_byte
+                )
+
+                log.debug(f"Found new template ref: {name.decode('utf8')}{args.decode('utf8')}")
+
+                if not self.contains_template_dependent_param(src, ti, cb[0]):
+                    if name not in self.template_refs:
+                        self.template_refs[name] = list()
+                    # The template function has no parameter which is part of a previous
+                    # template definition. So all template parameters are well-defined.
+                    # Add it to the well-defined list.
+                    if ti not in self.template_refs[name]:
+                        self.template_refs[name].append(ti)
+        self.resolve_dependencies()
+
+    def resolve_dependencies(self):
+        # Resolve dependencies of templates until nothing new was resolved.
+        prev_len = 0
+        while len(self.incomplete_template_refs) > 0 and len(self.incomplete_template_refs) != prev_len:
+            # Dict with new template calls which were previously incomplete
+            # because one or more parameters were unknown.
+            new_completed_tcs: {str: list} = dict()
+            tc_instance_list: [TemplateRefInstance]
+            for caller_name, tc_instance_list in self.template_refs.items():
+                # Check if this caller has a dependent template call.
+                # In other words: If a template parameter of this caller is given
+                # to another template call in the callers body.
+                if caller_name not in self.incomplete_template_refs:
+                    # Not in the dependency list. Skip it.
+                    continue
+                # For each configuration of template parameters we complete a template reference.
+                for caller_template in tc_instance_list:
+                    incomplete_tc: TemplateRefInstance
+                    for incomplete_tc in self.incomplete_template_refs[caller_name]:
+                        new_tc: TemplateRefInstance = self.get_completed_tc(caller_template, incomplete_tc)
+                        callee_name = new_tc.name
+                        if callee_name not in new_completed_tcs:
+                            new_completed_tcs[callee_name] = list()
+                        if new_tc not in new_completed_tcs[callee_name]:
+                            new_completed_tcs[callee_name].append(new_tc)
+                del self.incomplete_template_refs[caller_name]
+
+            for templ_name, tc_list in new_completed_tcs.items():
+                if templ_name in self.template_refs:
+                    self.template_refs[templ_name] += tc_list
+                else:
+                    self.template_refs[templ_name] = tc_list
+            prev_len = len(self.incomplete_template_refs)
+        if prev_len > 0:
+            log.info(f"Unresolved template calls: {self.incomplete_template_refs.keys()}. Patch them by hand!")
+
+    @staticmethod
+    def get_completed_tc(tc: TemplateRefInstance, itc: TemplateRefInstance) -> TemplateRefInstance:
+        new_tc = TemplateRefInstance(itc.name, itc.args, itc.start_byte, itc.start_byte, itc.end_point, itc.end_byte)
+        for indices in itc.caller_param_indices:
+            if tc.name not in indices:
+                # Index of other caller function. Skip.
+                continue
+            caller_i = indices[tc.name]
+            self_i = indices["self_i"]
+            new_tc.args_list[self_i] = tc.args_list[caller_i]
+            new_tc.args = TemplateCollector.list_to_templ_params(new_tc.args_list)
+        new_tc.templ_name = new_tc.name + new_tc.args
+        return new_tc
+
+    def contains_template_dependent_param(self, src, ti: TemplateRefInstance, parse_tree: (Node, str)) -> bool:
+        """Here we check if one of the template parameters of the given template call,
+        is a parameter of the callers template definition.
+
+        Let's assume we find the template call `func_B<X>()`.
+        Now look at the context `func_B<X>` is in:
+
+        template<X>
+        void func_A() {
+            func_B<X>(a)
+        }
+
+        Since `X` is a template parameter of `func_A` we have to wait until we see a call
+        to `func_A<X>` where `X` gets properly defined.
+
+        Until then we save the TemplateInstance of `func_B<X>` in a list of incomplete
+        template calls and note that it depends on `func_A`.
+        If later a call to function `func_A` is found (with a concrete value for `X`) we can add
+        a concrete TemplateInstance of `func_B`.
+
+        :param: src The current source code to operate on.
+        :param: ti The TemplateInstance for which to check dependencies.
+        :param: parse_tree The parse tree of the template call.
+        :return: True if a dependency was found. False otherwise.
+        """
+
+        # Search up to the function definition this call belongs to
+        node: Node = parse_tree[0]
+        while node.type != "function_definition":
+            node = node.parent
+        if not node.prev_named_sibling.type == "template_parameter_list":
+            # Caller is a normal function definition.
+            # Nothing to do here.
+            return False
+
+        caller_fcn_id = node.named_children[2].named_children[0]
+        caller_fcn_name = get_text(src, caller_fcn_id.start_byte, caller_fcn_id.end_byte)
+        caller_templ_params = get_text(src, node.prev_sibling.start_byte, node.prev_sibling.end_byte)
+        pl = TemplateCollector.templ_params_to_list(caller_templ_params)
+        has_parameter_dependency = False
+        for i, param in enumerate(pl):
+            if param in ti.args_list:
+                has_parameter_dependency = True
+                ti.caller_param_indices.append({caller_fcn_name: i, "self_i": ti.args_list.index(param)})
+
+        if not has_parameter_dependency:
+            return False
+
+        if caller_fcn_name not in self.incomplete_template_refs:
+            self.incomplete_template_refs[caller_fcn_name] = list()
+        if ti not in self.incomplete_template_refs[caller_fcn_name]:
+            self.incomplete_template_refs[caller_fcn_name].append(ti)
+        return True
+
+    def read_files(self):
+        for sf in self.searchable_files:
+            if not Path.exists(sf):
+                log.fatal(f"TemplateCollector: Could not find '{sf}' for search.")
+                exit(1)
+            log.debug(f"TemplateCollector: Read {sf}")
+            with open(sf) as f:
+                file = {"path": sf, "content": bytes(f.read(), "utf8")}
+                self.sources.append(file)
+
+    @staticmethod
+    def get_capture_bundles(query, tree):
+        captures_bundle: [[(Node, str)]] = list()
+        for q in query.captures(tree.root_node):
+            if q[1] == "templ_ref":
+                captures_bundle.append([q])
+            else:
+                captures_bundle[-1].append(q)
+        return captures_bundle
+
+    @staticmethod
+    def get_template_pattern():
+        """
+        :return: A pattern which finds either a template function calls or references.
+        """
+        return (
+            "(template_function"
+            "     ((identifier) @name)"
+            "     ((template_argument_list) @templ_args)"
+            ") @templ_ref"
+        )
+
+    @staticmethod
+    def templ_params_to_list(templ_params: bytes) -> [bytes]:
+        params = templ_params.strip(b"<>").split(b",")
+        params = [p.strip() for p in params]
+        res = list()
+        for p in params:
+            if len(p.split(b" ")) == 2:
+                # Typename specified for parameter. Remove it.
+                # If it was more than one space, it is likely an operation like `size + 1`
+                p = p.split(b" ")[1]
+            # true and false get resolved to 1 and 0
+            if p == "true":
+                p = "1"
+            elif p == "false":
+                p = "0"
+            res.append(p)
+        return res
+
+    @staticmethod
+    def list_to_templ_params(temp_param_list: list) -> bytes:
+        return b"<" + b", ".join(temp_param_list) + b">"
+
+    @staticmethod
+    def get_macro_c_call(name: bytes, arg_param_list: [bytes], fcn_args: bytes = b""):
+        res = b""
+        fa = [name] + arg_param_list
+        for x in fa[:-1]:
+            res += b"CONCAT(" + x + b", "
+        res += fa[-1]
+        return res + (b")" * (len(fa) - 1)) + fcn_args
diff --git a/suite/auto-sync/CppTranslator/arch_config.json b/suite/auto-sync/CppTranslator/arch_config.json
new file mode 100644
index 000000000..5cf757ecf
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/arch_config.json
@@ -0,0 +1,57 @@
+{
+  "General": {
+    "clang_format_file": "../../../.clang-format",
+    "patch_persistence_file": "./saved_patches.json",
+    "cs_arch_src": "../../../arch/",
+    "translation_out_dir": "../build/trans_out/",
+    "diff_out_dir": "../build/diff_out/",
+    "diff_color_new": "green",
+    "diff_color_old": "light_blue",
+    "diff_color_saved": "yellow",
+    "diff_color_edited": "light_magenta",
+    "nodes_to_diff": [
+      {
+        "node_type": "function_definition",
+        "identifier_node_type": ["function_declarator/identifier"]
+      },{
+        "node_type": "preproc_function_def",
+        "identifier_node_type": ["identifier"]
+      },{
+        "node_type": "preproc_include",
+        "identifier_node_type": ["string_literal", "system_lib_string"]
+      },{
+        "node_type": "preproc_define",
+        "identifier_node_type": ["identifier"]
+      }
+    ]
+  },
+  "ARM": {
+    "files_to_translate": [
+      {
+        "in": "../vendor/llvm_root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp",
+        "out": "ARMDisassembler.c"
+      },{
+        "in": "../vendor/llvm_root/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp",
+        "out": "ARMInstPrinter.c"
+      },{
+        "in": "../vendor/llvm_root/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h",
+        "out": "ARMInstPrinter.h"
+      },{
+        "in": "../vendor/llvm_root/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h",
+        "out": "ARMAddressingModes.h"
+      },{
+        "in": "../vendor/llvm_root/llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp",
+        "out": "ARMBaseInfo.c"
+      }
+    ],
+    "files_for_template_search": [
+      "../build/llvm_inc/ARMGenDisassemblerTables.inc",
+      "../build/llvm_inc/ARMGenAsmWriter.inc",
+      "../vendor/llvm_root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp",
+      "../vendor/llvm_root/llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp"
+    ],
+    "manually_edited_files": [
+      "../vendor/llvm_root/llvm/lib/Target/ARM/Disassembler/ARMBaseInfo.h"
+    ]
+  }
+}
diff --git a/suite/auto-sync/CppTranslator/requirements.txt b/suite/auto-sync/CppTranslator/requirements.txt
new file mode 100644
index 000000000..b4af2b8b5
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/requirements.txt
@@ -0,0 +1,2 @@
+tree-sitter==0.20.1
+termcolor==2.2.0
diff --git a/suite/auto-sync/CppTranslator/saved_patches.json b/suite/auto-sync/CppTranslator/saved_patches.json
new file mode 100644
index 000000000..11cb4ddb4
--- /dev/null
+++ b/suite/auto-sync/CppTranslator/saved_patches.json
@@ -0,0 +1,1140 @@
+{
+  "ARMDisassembler.c": {
+    "AddThumb1SBit": {
+      "apply_type": "OLD",
+      "old_hash": "e16fd83b02dc4539a153f003f89ecd789699e8c689212e8a051fd7dfd71515be",
+      "new_hash": "0b07623e68389bb5cadccad8f9bbf609da2cb3290bb0eda48d70fb272dd24740",
+      "edit": ""
+    },
+    "AddThumbPredicate": {
+      "apply_type": "OLD",
+      "old_hash": "8f80910dc0f93f0228e5146baca8edf6da72a6b57594938ed637b0a23b0a4225",
+      "new_hash": "268bc4f2284655b632d6465e28e0ccb698089b9ca8d31ac4e003de3271b0959c",
+      "edit": ""
+    },
+    "DecodeBankedReg": {
+      "apply_type": "OLD",
+      "old_hash": "591ff78f00921ed414fa6a59f4f6640077bded5d091aaefc5b70cf0aa78467b4",
+      "new_hash": "c7683990b16d1e08d33b257943b9367942ff633782e2a435e761c55bc5287a2d",
+      "edit": ""
+    },
+    "DecodeCoprocessor": {
+      "apply_type": "OLD",
+      "old_hash": "cc712cea5428075692669b3710f0b09e5310a455f92256436a4bdaf6e151b57e",
+      "new_hash": "daa85b7f91aac75ff19cb6d86ae64dd250607267385e6b14739f150b74d5aef2",
+      "edit": ""
+    },
+    "DecodeDPRRegListOperand": {
+      "apply_type": "OLD",
+      "old_hash": "a7a204c5f5526cfafedf94d7a190357289b1429029f9a04f43512bd452a4c13d",
+      "new_hash": "873fd7c40cbe345fface74171973599c7ebdd88f1d10639a4c38c36d8925531d",
+      "edit": ""
+    },
+    "DecodeLOLoop": {
+      "apply_type": "OLD",
+      "old_hash": "6d19cf244c1ad61065307dcee6d83f242687335a904c6f5e48b99d7a43821300",
+      "new_hash": "92d03993387cb3f2a89a487f41c7a1eda1e7c712489ed82d10e4cfbd730d672f",
+      "edit": ""
+    },
+    "DecodeMVEOverlappingLongShift": {
+      "apply_type": "OLD",
+      "old_hash": "a54bdf2f7e6acc5c897ceda54d9e06b38280031fa5affab7f7342a090b8149a9",
+      "new_hash": "ce92360c0070cb0bb6d3141e7da1aad93def0c89d0a1bc6956666b86932eaef0",
+      "edit": ""
+    },
+    "DecodeNEONComplexLane64Instruction": {
+      "apply_type": "OLD",
+      "old_hash": "385087526ea2f96921c0acdc5031e58289b362dc879617d67b6ad360f5f6650c",
+      "new_hash": "d515a9bf62f84f761c87038d4ef8dd524ce5f1732c27c571ca34eb24df553a01",
+      "edit": ""
+    },
+    "DecodePredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "11c75b2eebe14a12b404685d28e860efc317ba3ec3a2fe1be690768bb6dcdd74",
+      "new_hash": "25af886f52628b188c04f49c943dabd4fdeb7cc2f36b1996fe23c46538dec630",
+      "edit": ""
+    },
+    "DecodeRegListOperand": {
+      "apply_type": "OLD",
+      "old_hash": "03b7f5eb4616cb71b6cab451cc206d209c24f72af691111a5a0e8d928249f34f",
+      "new_hash": "c6385d9305c219139648b25b6ad565efb632fe98eb240e74ef2505a54def59df",
+      "edit": ""
+    },
+    "DecodeSORegMemOperand": {
+      "apply_type": "OLD",
+      "old_hash": "29550703c82a70275340d930c4b810b77a2cb31acde412321b7a12368de866d5",
+      "new_hash": "da86338e5af47615570d63e8871bc85786cc666af3cca282e748afaca30092e4",
+      "edit": ""
+    },
+    "DecodeSPRRegListOperand": {
+      "apply_type": "OLD",
+      "old_hash": "62f44fc1ce2dd99a384cafc88b548db13f72c1ad570c1b78170acc92c358a8f0",
+      "new_hash": "e735b1996fa4e46588f0eda8053f703889f2450bbfa9e3d68a4949e6a34ceb1f",
+      "edit": ""
+    },
+    "DecodeVpredNOperand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "f75ffc6297941d5b99c59b80e4541d09d8dfd2aa579300a349bd59f284c0c368",
+      "edit": ""
+    },
+    "UpdateThumbVFPPredicate": {
+      "apply_type": "OLD",
+      "old_hash": "e7ddf147351b4f50ec9873669ca873383beb837dd9b487bcc095e68cf82d61a5",
+      "new_hash": "0e92a16b350185abea1aa073bff5fe5a03b3394dd842700b5f11251b50605a4a",
+      "edit": ""
+    },
+    "checkDecodedInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "69e2594d21a456a8c4278918d9a61e48dc9f72a4a1f6ab4036d076122397c7f1",
+      "new_hash": "afc0e9b79bb308fe0bc83e43b45f194bb3586b8b22e0f35db27dbd5aac5ee6c6",
+      "edit": ""
+    },
+    "createARMDisassembler": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "606ce64d2ffb7388277a2167d951b14bec44db29d7fcba17c19c5eea0f6e4f58",
+      "edit": ""
+    },
+    "endianSensitiveOpcode16": {
+      "apply_type": "OLD",
+      "old_hash": "62d92f7c8bac5715e5d6b4a5f24d9db2bf4bbe65908df8db065f21d6acc9f3b3",
+      "new_hash": "",
+      "edit": ""
+    },
+    "endianSensitiveOpcode32": {
+      "apply_type": "OLD",
+      "old_hash": "cc04456b7311c419f71f4e3df699d268a757f44b74107c89319b6a5f33f94202",
+      "new_hash": "",
+      "edit": ""
+    },
+    "getARMInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "991fe5885c6cba420d46d0b0b6365612116c091b6afd03e08af86620b5ae054e",
+      "new_hash": "77a9a2ccf0ff001ba8b7a767b4fb724c13ecf98157b20b16da6e4b29e0a8a741",
+      "edit": ""
+    },
+    "getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "103b8e5e79d3f02012e777e72620ccb3b4ebfb9ca4046cf3ab3f0d0aa741c397",
+      "new_hash": "2ca1ebf16c1a881f4baf7521655027af1dce0139c29a6bc36e32472d522994d3",
+      "edit": ""
+    },
+    "getThumbInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "81b172eabb79001c03f54cab171241da27e59939f42b89245bc1aca01372ac5b",
+      "new_hash": "73763b1aa82f419f2ab35287b5258b172f7d5aaab50a0830745a64aeda26adf3",
+      "edit": ""
+    },
+    "suggestBytesToSkip": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "0aa21749305ce0d629fc521ce34f2e0b37aa6c3df7adbbbdfefd68d2d9aa902b",
+      "edit": ""
+    },
+    "tryAddingPcLoadReferenceComment": {
+      "apply_type": "OLD",
+      "old_hash": "bd518e25602001178dcc1d96c4f087f726060909fe6ae4ab0bfa56caf6bcf5d0",
+      "new_hash": "dfe5eeae157c1dfe6ac79e5145e573b744e64c5ed743240bf3979722e152f35b",
+      "edit": ""
+    },
+    "tryAddingSymbolicOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f87c74198ad758f08700947dccf281ba1d068a31290cd921e70b0653893d2d44",
+      "new_hash": "acf81a43081f705ad92fd9f2e295eb0c5b983d67793d03490f1aeb9776ff65aa",
+      "edit": ""
+    },
+    "isVectorPredicable": {
+      "apply_type": "OLD",
+      "old_hash": "e0025f215966ee66db69bb0a71f1376707c17f753b1dc77f6ca4853db9fadc2f",
+      "new_hash": "1fde7ed766d751e64cbea32d32b42f4162c8d58cfe997ed17060f425f5c89eb7",
+      "edit": ""
+    },
+    "\"../../MathExtras.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "c6ce14448320faf6eb6a6386c8917b014947f3ffe02d3741941e3acbb23f408d",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"ARMDisassemblerExtension.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "851288252991845820ca25879f96f74e61c35f315acea1453f88d6622e1d4303",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"ARMGenInstrInfo.inc\"": {
+      "apply_type": "OLD",
+      "old_hash": "ca97dd129bda8d7161b6732f2c1b80c70e1d64be483c824f46f54ce4e1f172a3",
+      "new_hash": "",
+      "edit": ""
+    },
+    "/* Capstone's C++ file translator: */": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "b1ea27f4adc10229946cced84510362e2b8561030cfe6dee4df30b1fa8df4458",
+      "edit": ""
+    },
+    "/* For multiple similiar edits, please create a Patch for the translator. */": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "31b4c019cfb61410081d33444965f1c2fffd36d91105400ac4ed3325e9092a25",
+      "edit": ""
+    },
+    "/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "98bc99aadc54580ddc91940c36e2b15287de7946ca6d731b81e2b56f40a2c0a0",
+      "edit": ""
+    },
+    "// end namespace llvm": {
+      "apply_type": "NEW",
+      "old_hash": "11db4f68c44ac574388a19898cbd3a0df9f6058e57c1b137e91cc7f591087353",
+      "new_hash": "",
+      "edit": ""
+    },
+    "/// ARM disassembler for all ARM platforms.": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "3c4bb90e3955714234a70a4478737cd7fc9199907554d722d53a1667e5ae9266",
+      "edit": ""
+    },
+    "DecodeT2AddSubSPImm": {
+      "apply_type": "OLD",
+      "old_hash": "9892c4f47a1d4e935970a08e09ba7d1f0010f23b54248142b4add2c8b3e66ea7",
+      "new_hash": "6f5bac5b333965df6a2fdf0ef49141651dd5203966ea221d6b4744ceb034bdc3",
+      "edit": ""
+    }
+  },
+  "ARMInstPrinter.c": {
+    "DEFINE_printAddrMode3Operand": {
+      "apply_type": "OLD",
+      "old_hash": "af7ea9416ba2cc6ede4f38fd7ed7a3c2ae5b4fa3e4baf64c066e0c7934f8f47b",
+      "new_hash": "2b9a93b6041a6835b40560d21110f72ba75bfc587e21dfe455b558c03eefb75f",
+      "edit": ""
+    },
+    "DEFINE_printAddrMode5FP16Operand": {
+      "apply_type": "OLD",
+      "old_hash": "fd9d633a61805162dd594a75960f7249f29f0860d1282fdeb86c5ec61751106a",
+      "new_hash": "83a3a526a1062a3c9b44b8e0d1e90be9814a46ed82e7bc5430b9cb0ea06e6137",
+      "edit": ""
+    },
+    "DEFINE_printAddrMode5Operand": {
+      "apply_type": "OLD",
+      "old_hash": "846db22d9ffd5b6a2880560f2024b31fff69a7cccc7a7bec960bb15db2e1a44a",
+      "new_hash": "4c2e9a485f7656e68350e2c0ddaccb533bf2f735de1a6959e5b4b5f9088d097d",
+      "edit": ""
+    },
+    "DEFINE_printAddrModeImm12Operand": {
+      "apply_type": "OLD",
+      "old_hash": "ec820754ffb1f31c0fb40486c6f3bb3b5c7069010ad95ca0ba7c76cae7af2847",
+      "new_hash": "c24bc49c480c4cd7cb9c704c90fcb47e19526a5f3b5f5467277dcd4116197273",
+      "edit": ""
+    },
+    "DEFINE_printAdrLabelOperand": {
+      "apply_type": "OLD",
+      "old_hash": "3080ddb15e84c493c4971cbdf6d3347a478d75f6452598650676a77cf1a9990f",
+      "new_hash": "5c0576e89fbddaf5b3565960fbafb124a15febd98aa787a4ede5322976e4090f",
+      "edit": ""
+    },
+    "DEFINE_printComplexRotationOp": {
+      "apply_type": "OLD",
+      "old_hash": "7c8fb93bbc82f8691d638671a0e547b26c39864a57f5afcf1fad8bd992374752",
+      "new_hash": "637fed4e607334f94c4820d71b56d38e6d917c1fd8809855b2520c19ecc3d233",
+      "edit": ""
+    },
+    "DEFINE_printMVEVectorList": {
+      "apply_type": "OLD",
+      "old_hash": "9dfb1a71d6d828c919c6bc217a346c37d622fa56d369f22f51c7889fb5285158",
+      "new_hash": "92fbf764f6efefb68befc890dca5cb5b3ea3a97d68ac43ffa2f7ec0bfda5e422",
+      "edit": ""
+    },
+    "DEFINE_printMveAddrModeRQOperand": {
+      "apply_type": "OLD",
+      "old_hash": "6abd4b1369876754b5c0662f7064a9d9ca77a2fcc55565e000ad017fbc1c5056",
+      "new_hash": "e68fef2691a4b1183c3ff98be9feb65525df46b8de61757c3656f6e9ef9f4fb0",
+      "edit": ""
+    },
+    "DEFINE_printT2AddrModeImm8Operand": {
+      "apply_type": "OLD",
+      "old_hash": "eff8301730a686100632b69f02afdeb56035114ffa080ffc61621153b27338d3",
+      "new_hash": "cb5d2159ce8fe5213ccbc6445c68c8a5ca6592523a5c863a512600d6db4dedba",
+      "edit": ""
+    },
+    "DEFINE_printT2AddrModeImm8s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "df809120708a14ea78e4327720d45508f651896b2b5682d8bb91190b75b75e30",
+      "new_hash": "c6d55fdc81a855db87090c4bf75cf2148f168af3db14d2913b28bc1bec0f3145",
+      "edit": ""
+    },
+    "applyTargetSpecificCLOption": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "1939abc1c7e369df85230bae9d6cb351140861961d09a79108b648a1bf7d4670",
+      "edit": ""
+    },
+    "printAM2PreOrOffsetIndexOp": {
+      "apply_type": "OLD",
+      "old_hash": "1fdbd48631dbcf8f626c4f0b51ed7305717eeca7f7e003c13b8903b635661a59",
+      "new_hash": "58d6e2fdbe27f1d3bce462d33f9d5055f679ef3d2409f2e8c316bf7ba6f7eb18",
+      "edit": ""
+    },
+    "printAM3PreOrOffsetIndexOp": {
+      "apply_type": "OLD",
+      "old_hash": "a26eb2f383267adea6ccf73a9135cedcf76224aed297546697a9bc91e02a6726",
+      "new_hash": "74ea21a49410da52792d905187f111b2006f09fe6d564d32f5771b4f085cb54c",
+      "edit": ""
+    },
+    "printAddrMode2OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "c1b30a543967f380b19268c183b0e27c9dd1ba3df757eb2d8b791a4a3a0f1e7f",
+      "new_hash": "4a63705970d00ae5433afb7e2052e6fac649565c37ca0130422c2449ff9b528e",
+      "edit": ""
+    },
+    "printAddrMode2Operand": {
+      "apply_type": "OLD",
+      "old_hash": "230d465ca69ac5473beb0f4a6f1d5c10889f6e641fee285a827efe060d00a6ef",
+      "new_hash": "0cf0e43712f47bdc9f27da66f6f4d27c81a7780f1ad545d8b0e7927df7688ef3",
+      "edit": ""
+    },
+    "printAddrMode3OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "09c12dd52372078a4b40c9f1ac5307de4483835682d0dc0d6ef34178ec8176d8",
+      "new_hash": "3d334ad4d88b692b83860225d494bde88b55e6b9c1aa21d0361ff91448c2ea6c",
+      "edit": ""
+    },
+    "printAddrMode6Operand": {
+      "apply_type": "OLD",
+      "old_hash": "b4fe0818f81a87e7846492b6e4b0e940cc7a7754c68294bc84edf74f8d605a9d",
+      "new_hash": "812ef2e29246185246fad917ba3e563ca354b7df63d06add221a906442ccbf74",
+      "edit": ""
+    },
+    "printAddrModeTBB": {
+      "apply_type": "OLD",
+      "old_hash": "2b6af4d44046ed26cc4907bbdbce871f58be9306031974e75118bb06873c94f4",
+      "new_hash": "86e68e07e3e39fa03f166aef4b8c159535eefcbb1208dd10da93c18e3c4ad990",
+      "edit": ""
+    },
+    "printAddrModeTBH": {
+      "apply_type": "OLD",
+      "old_hash": "585f957d549eee873ba6b63c87e578c52039c1195bd75b773063e61bef23ed2d",
+      "new_hash": "c4c65926f574a9e53965a9e1cbe722c216eb4d3003a1e65aaa10d69d580ceeb8",
+      "edit": ""
+    },
+    "printBankedRegOperand": {
+      "apply_type": "OLD",
+      "old_hash": "43743a8b9716df5836df06c6152617cf3cc990c4fc9d0bb3b28d78f35f8fdfa5",
+      "new_hash": "b01a60a479b0d736ff85868dc7abc5835f2465c0b9f019f79337f23171779cb9",
+      "edit": ""
+    },
+    "printBitfieldInvMaskImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "69a5a2c342bbd121ec05acc8449754f5e4156ac71a1258c69e5002c03ee75a34",
+      "new_hash": "e4969f0b3649a32e96d2067b4b7fe34e84cb116d91559ec9e716dc2b58502d45",
+      "edit": ""
+    },
+    "printCImmediate": {
+      "apply_type": "OLD",
+      "old_hash": "afcb089aad56b5fa5f0be84f20c1211982a20b90b29cc7f38cd3ad02ba6e3cff",
+      "new_hash": "18189a16121e22d13f068b9e5c854fdaf7b093a03899f363320b21d115e6a802",
+      "edit": ""
+    },
+    "printCoprocOptionImm": {
+      "apply_type": "OLD",
+      "old_hash": "d8022789f9bce2fed4423f14122462a11ae1044a7bd8d05b8722ff1e86823c99",
+      "new_hash": "7535754b2a47fae26076816d8a5a9d68a5270b328454ce0d39e9067eceabca0e",
+      "edit": ""
+    },
+    "printFBits16": {
+      "apply_type": "OLD",
+      "old_hash": "d786587739a17c72c7ddf969ace7912bd5d7f15f10d34efbf106bb163f10aa5a",
+      "new_hash": "056e4db3f03d21c832f867cc7e07e61f0f212d0faec8ea530d9c04c97bc703ac",
+      "edit": ""
+    },
+    "printFBits32": {
+      "apply_type": "OLD",
+      "old_hash": "cf8b1fbec5f2523b933028dd0ed39912d4783035d79522e79c718fd05639a67d",
+      "new_hash": "0b4c176919da4632010afd57004125c958e5ad6ec467cdaf4245c178aab8eb3e",
+      "edit": ""
+    },
+    "printFPImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f145952b34b4c7651b5ec4b42e5ca351f39f386d5cb7bc31e238b50626fd089c",
+      "new_hash": "14deaa47743b68acb3f5dbc260cc7815e2bb4d4fb37ebd112d9c2b0555592219",
+      "edit": ""
+    },
+    "printImmPlusOneOperand": {
+      "apply_type": "OLD",
+      "old_hash": "ec1dafafd60de21c0a274d68812f99e12f0baaff5067f184e4374ff2b37a28f7",
+      "new_hash": "7700056069222c71a5a6bce4723ab8e5192e903269fe8cbb7dbcb948c1b3b746",
+      "edit": ""
+    },
+    "printInst": {
+      "apply_type": "OLD",
+      "old_hash": "c751d526f6b3f56656df1f7744b52770d5e59e14c03c32f1eb82f8f2a3640d0c",
+      "new_hash": "679cadb26bb1e0e1980c949417ddf015ea1cbc2b72faf149ffe1757c431e8a9a",
+      "edit": ""
+    },
+    "printLdStmModeOperand": {
+      "apply_type": "OLD",
+      "old_hash": "4990300d297524408a55bc945388d4ce6465b1585ad2bf4b6493a0d7e3dc3e20",
+      "new_hash": "15fec9399f83d47d8ced75d1e71de628c0ec1b6a94aac0dabfeea17a2d6130f4",
+      "edit": ""
+    },
+    "printMSRMaskOperand": {
+      "apply_type": "OLD",
+      "old_hash": "96bc50d1f859e84eaced0bae7d072df9dcd3682ea3440d0ad3604fba59105cc2",
+      "new_hash": "1188aa817281efe36d31cb4b71d01880bff211cec256e679605c9d49c265f440",
+      "edit": ""
+    },
+    "printMandatoryInvertedPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "d89595b75c7ce86a7c9a4d1e9cb8813ea3b16624294c7e82251f42a74e0573c9",
+      "new_hash": "f466f0aef159a8585b8f819ac7ec81801f23ed8a87b32fa8565fd04ff5f60d7c",
+      "edit": ""
+    },
+    "printMandatoryPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f055949e40ea6e2c156fb2666a1286884eefefd2c5ffda513d3a651fab437928",
+      "new_hash": "869c0a7b9cff8b6e49c4d1a831497d30fff928f406d16b5d319f830b5167a71c",
+      "edit": ""
+    },
+    "printMandatoryRestrictedPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "5cb657d162c7f209b211ff648f78d81207139da616ee2525f355f88bef392c07",
+      "new_hash": "264a03894fbecaa1905c0e813d8d97b6bb1750c4c317a6fd9e392658bcbc3576",
+      "edit": ""
+    },
+    "printMemBOption": {
+      "apply_type": "OLD",
+      "old_hash": "84e89538daa5f2372cf30aee9380570c55d1889e26e65976c5fc283e5c3989db",
+      "new_hash": "03464e08ad25c3e5d89e7196ea07f068879813ff803a96fe7a29b240e6a87370",
+      "edit": ""
+    },
+    "printModImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "08e8cec6f9b66f2b1abb8df29785fee3a3592c8df7f8b8fb03ff1412fc4fba37",
+      "new_hash": "68ed77cd5ddb655c1772c47a4574cbb921b6fb952f8cec394cd75cef50545b2e",
+      "edit": ""
+    },
+    "printMveSaturateOp": {
+      "apply_type": "OLD",
+      "old_hash": "19041125e884b3bcfdebd4a88c316dbff6ed17637baac100fc35681db10f3346",
+      "new_hash": "8daaad36c055497f8ba1ebb559fd65c427fec3c74576d6c216a9fac73e784835",
+      "edit": ""
+    },
+    "printNoHashImmediate": {
+      "apply_type": "OLD",
+      "old_hash": "5eca0dcad4b6a9556639c1e27d56eafd7148cc22ff5c44dcb86d39b322cae69e",
+      "new_hash": "6ba021d35466d081b88b56b2e6d8920533c77885bb8b7eaa8185b0c026c00396",
+      "edit": ""
+    },
+    "printOperand": {
+      "apply_type": "OLD",
+      "old_hash": "e66c45ad0c409969e9df95f5044663751e871c72e460db73e7e98f3065f640dd",
+      "new_hash": "",
+      "edit": ""
+    },
+    "printOperandAddr": {
+      "apply_type": "OLD",
+      "old_hash": "9abb796cd4753e9deb86185c4759f625230c278f01b23bbb9ab689fed7cebd48",
+      "new_hash": "",
+      "edit": ""
+    },
+    "printPCLabel": {
+      "apply_type": "OLD",
+      "old_hash": "9fed7969e83fad1c33bee6c48ecf4c24d475d84e8cb42858f6bddc6237c951e1",
+      "new_hash": "ade84eb1a15afb848ef6613ecc22dd9635c287961d68284954e0d80da13af5bb",
+      "edit": ""
+    },
+    "printPImmediate": {
+      "apply_type": "OLD",
+      "old_hash": "d306e15c1f370997604e282277bffad5f9b8130895b9feaadaa9e52aaed900ac",
+      "new_hash": "682ddf037f5302a3a5b0b0b84181f1a90ed7ccf475e68142f11a6496624238fc",
+      "edit": ""
+    },
+    "printPKHASRShiftImm": {
+      "apply_type": "OLD",
+      "old_hash": "71d2c4b54a4593979975483eb0b1235c7e98ff8279b2bb0e10628b5323021062",
+      "new_hash": "cb379ce7f93eeca3e7a0e26f0de9eb38a85a37c7c912e7dd04b9c5fd3aa00001",
+      "edit": ""
+    },
+    "printPKHLSLShiftImm": {
+      "apply_type": "OLD",
+      "old_hash": "bdf1d8a29f6ba423b1e5e2aa8ecb75025135cc9e0b00afc03bf8cbfa91c3bbed",
+      "new_hash": "ea18ff49154d6e98e64b070c14539b1cb9bf2605fc1b54c6b584d0cef4472511",
+      "edit": ""
+    },
+    "printPostIdxImm8Operand": {
+      "apply_type": "OLD",
+      "old_hash": "19577955ef15d0ffd3f4da5d6250103256997f30603326a3a900ca344f66999a",
+      "new_hash": "fd5fb966072ff39e9e69f0bbf1413bda4f67782c62f0b67cec3365ef9be19808",
+      "edit": ""
+    },
+    "printPostIdxImm8s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "d86795b49368c0085fdce9d3b0d225a737f9371a8c3b63b560d6e47de1886350",
+      "new_hash": "64d50dfbcb48d7ec0c160d63d319f58e6b7fbd70eb9815759a00a3b5a7453f80",
+      "edit": ""
+    },
+    "printRegImmShift": {
+      "apply_type": "OLD",
+      "old_hash": "fe387d2307f0afa1258d838a38fc0e3a1cec278589ea533d4dbe47b30b61022e",
+      "new_hash": "f5f9e7d13397f41b16bc8ae9c6fb4e22340b9f234cb73e5e6ea583066e33a8b3",
+      "edit": ""
+    },
+    "printRegName": {
+      "apply_type": "OLD",
+      "old_hash": "b1fe3d90fb876baaa30fd192924db576307c2dfe15401763eefff652d893d58c",
+      "new_hash": "4f610d8d53df44717b9d6afc902b095e02f0ba8b71b2f0921f9a8c6a9a7335a7",
+      "edit": ""
+    },
+    "printRotImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "2be39b4db0740667261692917852504071b882d16aa5afe0de54f2ff44fcf134",
+      "new_hash": "1cc162cba6dc29942e357504feb012c509522eed4e15fcb1a36050055c84f03b",
+      "edit": ""
+    },
+    "printShiftImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "7f1299f202c7103edbe37fa729326c7da3c76b98d000d7b3adc5245bd72ba955",
+      "new_hash": "125bdf3ca38df9d7e9b43ae20e14b132fba0342da474841b6bd8918e79e87fa9",
+      "edit": ""
+    },
+    "printT2AddrModeImm0_1020s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "cbba19c1ef758dade62a56e6b33dd89923859ae113673d252c42af9075537e76",
+      "new_hash": "861508ab43ce5a3433b663effb73c99804534ab3dad51f852ed2fb79a8264b71",
+      "edit": ""
+    },
+    "printT2AddrModeImm8OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "57b6bebfa994d0e9154b232a5fa13283bb37f070ec0f12f24cc5c22510f35500",
+      "new_hash": "4d29e3fe51efc7bdb28aff362c42277bb8db59363a7261fe4766bcc5b2e13020",
+      "edit": ""
+    },
+    "printT2AddrModeImm8s4OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f2069b50e98d4faf11b5200b418abac998deda28baf95f0be081a8e8449b4528",
+      "new_hash": "92d3a1dcdd32cffd03ababb2a0b10c0605f74900f2bb3ab304c81967be6a82ed",
+      "edit": ""
+    },
+    "printT2AddrModeSoRegOperand": {
+      "apply_type": "OLD",
+      "old_hash": "43172bb3484e3751a2f7e258bb29db0d7c6d37a6ce375749b1829efb713dd36f",
+      "new_hash": "d5defc297c3ebaaf74c7dc8ba35003437964c40ca3683d7bb685a6ae42b49e06",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5S1Operand": {
+      "apply_type": "OLD",
+      "old_hash": "4a2e4e03452e1916fa2ec0aa0c9db3041c675e681d3e349b5d0436eeb3a3849d",
+      "new_hash": "1269c0298774c8eb4ce5a6c0a27dc5a80c323c3f6e70b7c9faabf575ef1a9249",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5S2Operand": {
+      "apply_type": "OLD",
+      "old_hash": "c1828a2e08a01240583f68c9d59bde99ca4555d65490dc547029cae94299a83a",
+      "new_hash": "517873dc4755e3bc6d7ce50a80bd716e03fef549b344295ad908bc84e6101c41",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5S4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "196c943ec78b1aad2ad8377c1ed245074f8d0c4cb2f875a5ed5a83a9b2b60bb2",
+      "new_hash": "083d4bdec37438584a608c2daeea1fa1589bd3de77f156bce608007aad0e2d16",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5SOperand": {
+      "apply_type": "OLD",
+      "old_hash": "7c394c550f612ae896f6a179f428c815c5c4b1e004974f7221f6e2ed92633657",
+      "new_hash": "2a6214e2cced1ff113efd71b57aa9ff1ccc81aa85ce30e9a47e6940594f40181",
+      "edit": ""
+    },
+    "printThumbAddrModeRROperand": {
+      "apply_type": "OLD",
+      "old_hash": "8be022d793139b99a3190c02d70ab975d611db6c92a5b569aff7081ffd9c353c",
+      "new_hash": "458751b418c22e394ba712f940a93e2733206f3d393f4b46c366e6743a96dd2d",
+      "edit": ""
+    },
+    "printThumbAddrModeSPOperand": {
+      "apply_type": "OLD",
+      "old_hash": "6396900cc18ff022f337ea572ae44f924a42c63f584abe6ff49c4a726749da4b",
+      "new_hash": "82705b397763b51819a79f609e5c58f8ff8d0995ae0c6d1e402a5d4bd3e79fcd",
+      "edit": ""
+    },
+    "printThumbITMask": {
+      "apply_type": "OLD",
+      "old_hash": "fbf9c241234cee08381e20204ed20b51e46781b78ba5a2feb8c680901ae8d86a",
+      "new_hash": "1f94d7de8502624ac21e03f2a2f1d7aab0964ada2b0a8a218297fccbe39f2f86",
+      "edit": ""
+    },
+    "printThumbLdrLabelOperand": {
+      "apply_type": "OLD",
+      "old_hash": "efb84da0302610393d6a7e5391241239b647a5b4c82668326d0e9a47a47a18bb",
+      "new_hash": "74199ee6f3a0679c738ee863b7e09fdbdf54c3a82076db1a08f9f9f64f1e80d1",
+      "edit": ""
+    },
+    "printThumbS4ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "a054fa53c071d5adda4eaba8d6f58a6bc3b155347b2bad91436ad9934fab6168",
+      "new_hash": "4a2059ff0c2ad62de628c31faa4fd2bf2ca6939b70e619f670ab53f9da2cc890",
+      "edit": ""
+    },
+    "printThumbSRImm": {
+      "apply_type": "OLD",
+      "old_hash": "a4e8c585111cfca9eb24e81f14e27ae0a5d9332393409760ee53f167e97dc3e3",
+      "new_hash": "cd1ea350e2f17cc235668020500af30b565471033f22be9a5b673ffd2deb5a10",
+      "edit": ""
+    },
+    "printVMOVModImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "3a12f73636ba9a968615b9ac0da5e66b1abc84170c125bb726f6af923be610ee",
+      "new_hash": "ee434466ac232cdadfba36ed4a6f70559e2fc751b99bad3a9b53924582823269",
+      "edit": ""
+    },
+    "printVPTMask": {
+      "apply_type": "OLD",
+      "old_hash": "3ac3e6830271fad2e5b3099916a92aa352c3f411fedf56fa5a2ee3fc8cad44f5",
+      "new_hash": "dcb3d8c40afce2cb58af848c0a0c7681aadd5f45cf6f4b0f7d0a8a2f829862c5",
+      "edit": ""
+    },
+    "printVPTPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "c7495070d9b75c99d7200b7e4933e8736894ebb44337795a43f22de9761689e7",
+      "new_hash": "1e9e98d0348bd3a0b49bea58b760dcf74a5c7c5db59660109cfe83d89ddd8ff7",
+      "edit": ""
+    },
+    "printVectorIndex": {
+      "apply_type": "OLD",
+      "old_hash": "a22263974ee3716ee63ec009f792b8fefc477637a8a258ddeb4981773dce20a4",
+      "new_hash": "2b260e8edaf33bd8ff81391d55f851862feaae945edb454c64ee20aa97a684c4",
+      "edit": ""
+    },
+    "printVectorListFourSpacedAllLanes": {
+      "apply_type": "OLD",
+      "old_hash": "166e91fa105bcd4dd30e9152264eb6f717ae115aebd2db19d264349b044dc7eb",
+      "new_hash": "d9fdf29c55985c5585fa6ae9e5b5e76f77a6a5460c150e3a10628f03688b5493",
+      "edit": ""
+    },
+    "printVectorListThreeSpacedAllLanes": {
+      "apply_type": "OLD",
+      "old_hash": "c9d6f66f03052ffa94279e30ac20f9cfccdfb02dd37c270c7011c153f66ebbe9",
+      "new_hash": "9eea9d7a79fa7aeeec57d7d1e7be829eaf856b745b6b8cd71b2cc35d25074409",
+      "edit": ""
+    },
+    "printVectorListTwoSpacedAllLanes": {
+      "apply_type": "OLD",
+      "old_hash": "aae283e427412d233ba2d783ad6c999958de2615bbd21c1543c7862398f61d15",
+      "new_hash": "0e4b72ae6eee17618fc9f66af493dd3b3c1e4e6bdf8796ccc2773b12544c74a8",
+      "edit": ""
+    },
+    "translateShiftImm": {
+      "apply_type": "OLD",
+      "old_hash": "e2d84d0521152490aae8ba013d5d06a3bec5fdf1b85dae03a7dab85a37c1486b",
+      "new_hash": "80629627e546f6a8623e75f101abd4c645a020a308c756b4e5393b7d033686aa",
+      "edit": ""
+    }
+  },
+  "ARMInstPrinter.h": {
+    "DECLARE_printAddrMode3Operand": {
+      "apply_type": "OLD",
+      "old_hash": "393fbcbfa8dd4028f0407d9f2488e2e9199007fe5f4cac8bdb53783cd853bcda",
+      "new_hash": "c666d706dc70ef935ea3ce3a0b3a926dfe46aff3aceb842d125ce35f55392ca4",
+      "edit": ""
+    },
+    "DECLARE_printAddrMode5FP16Operand": {
+      "apply_type": "OLD",
+      "old_hash": "b5f19a03bfd519a25e63c3a0915288088d8c013cf3072889f27bd7f78a150f8e",
+      "new_hash": "b4f43c435aa48a3a96f11c991e2cfffbb1e86797d35ae5c3df677c71d9629bfb",
+      "edit": ""
+    },
+    "DECLARE_printAddrMode5Operand": {
+      "apply_type": "OLD",
+      "old_hash": "8e1d447e8a0a0c1d079060007fa977b19f0315ad23f051fc6268cb47a02b5a6a",
+      "new_hash": "167c618729c81f7b5d0c113f999cb0b5b18c96a8ad36bb5524269307f9b478ba",
+      "edit": ""
+    },
+    "DECLARE_printAddrModeImm12Operand": {
+      "apply_type": "OLD",
+      "old_hash": "8db80cc06b17150e50e63f8763fdfa8d47d60675d023e3a9574db7f366e31ac7",
+      "new_hash": "d5396e68a91b970a4be8ccfcb3ea144007b57118aa6a381f6433fa54074dff44",
+      "edit": ""
+    },
+    "DECLARE_printAdrLabelOperand": {
+      "apply_type": "OLD",
+      "old_hash": "d8823baab85bbfe957433207e6618fdf5ad9e7cfa03856b376da2f55d64fff74",
+      "new_hash": "6169de4fca56dcf4c28a0dcff06bfc547066b7e4507e897d2c4fa3be3cb71574",
+      "edit": ""
+    },
+    "DECLARE_printComplexRotationOp": {
+      "apply_type": "OLD",
+      "old_hash": "7edf22601536c2da376f23cf87130dd1eb1da0516564ae9500ca14eec2804b45",
+      "new_hash": "a6cf8af8f48a60260428625c56741fb44b619634b5d5bfc41a680ca9a98e029d",
+      "edit": ""
+    },
+    "DECLARE_printMVEVectorList": {
+      "apply_type": "OLD",
+      "old_hash": "184ca6b74e9475ea9c496562d8ae4514fe6fd596adff6c0043d6669d93bd8d0d",
+      "new_hash": "34fecb1960b6b89daeee285fb724612592432c9107283895ec9de129db8ede58",
+      "edit": ""
+    },
+    "DECLARE_printMveAddrModeRQOperand": {
+      "apply_type": "OLD",
+      "old_hash": "7e6b18b04bbde182ddb08f39c308cdf25f608de9d1c1869650141f71d53fc40f",
+      "new_hash": "ba7d3a23c12149f6997aecc64062daf91e137573e1ebb275a98e16c96c2cf6c6",
+      "edit": ""
+    },
+    "DECLARE_printT2AddrModeImm8Operand": {
+      "apply_type": "OLD",
+      "old_hash": "55b5d1e3f38b9373f08b1bb272c0f3591c0b5081053d3b967a84b249a2a96e83",
+      "new_hash": "678a07ac256780dc77c035939a5b1f0205ab5648d298f7612a612fe662de9f4c",
+      "edit": ""
+    },
+    "DECLARE_printT2AddrModeImm8s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "354ba33df5106d0e03225fd041c7c20304659f303bdfffa5974101d10ea91f6f",
+      "new_hash": "6eb210b770604d8c08e65896aee289e91f82b846d4efd4e0fefc697b23cd18ec",
+      "edit": ""
+    },
+    "DEFINE_printAdrLabelOperand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "bbb96db98eb56e5934b6c7197e48afcbc1cd275b3f92c36c57db28b5045cae40",
+      "edit": ""
+    },
+    "DEFINE_printAdrLabelOperandAddr": {
+      "apply_type": "OLD",
+      "old_hash": "c42f5abbe91823ee78ab4413e71564f67e83fa2bb542bf7c088124d67d4cce77",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"../../utils.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "bba3ceddc5b6ca88f7f5a17acc4d2545a08e4011ca8224462a64a30eff35e9eb",
+      "new_hash": "cb41b18c2131c68da16a903ae7b7d7172f7883ab3494e3f89480c09e6c218da4",
+      "edit": ""
+    },
+    "\"ARMMapping.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "e010fe7fc5dbf57e7bdcec6beec5538edecf8fa40f2426bf12d2b37fff5cde57",
+      "edit": ""
+    }
+  },
+  "ARMAddressingModes.h": {
+    "ARM_AM_createVMOVModImm": {
+      "apply_type": "OLD",
+      "old_hash": "9fdfe761698ec14ee8ec8d867175327cde1b29ac01653bef157568f00a380094",
+      "new_hash": "2d67792843d1ccbace90c0861da72fd30785dcc30e24824ebebf5ed5e1874fc6",
+      "edit": ""
+    },
+    "ARM_AM_decodeVMOVModImm": {
+      "apply_type": "OLD",
+      "old_hash": "993ce2cf247ceedceee63d2cbdd2573632860111577fa226a56cbeb049aa0eb9",
+      "new_hash": "0f40d66f524e9c77f58eb74427a3344acf7b50c946f2b6a8bcb3287bde206463",
+      "edit": ""
+    },
+    "ARM_AM_encodeNEONi16splat": {
+      "apply_type": "OLD",
+      "old_hash": "05a8c9026d52566a444ca430a3b625485ee00e7726e8f60f5987b2eaa10810c6",
+      "new_hash": "e3ef8dc6988f2c7f32df2de20d0939134765e5f4cfa25844b3cae2add946b17f",
+      "edit": ""
+    },
+    "ARM_AM_encodeNEONi32splat": {
+      "apply_type": "OLD",
+      "old_hash": "8a4fb58682368d6b5a303a882e30a80a9f3530bb5bfb0d667bdabed48ec2f987",
+      "new_hash": "9c8b757326264d8b6a107c9c877550ec459622aabc8612825e71243ca3cb435b",
+      "edit": ""
+    },
+    "ARM_AM_getAM2IdxMode": {
+      "apply_type": "OLD",
+      "old_hash": "59c09986a56e7e775072e34fb51efaecb0272920b85d2c9422f75342ae00610c",
+      "new_hash": "e5e5ff685e501cac90b08d0dca399739546ce0423b935da83ef1ef1a41ae7498",
+      "edit": ""
+    },
+    "ARM_AM_getAM2Offset": {
+      "apply_type": "OLD",
+      "old_hash": "eb69c387b7a7c48c974bc63a110256aff086046ddb6f1a8b315d55813f5f40bf",
+      "new_hash": "374b3176223a2d1b5f1bbb0b97b671bd91b2d97f56cf42e953c63e692ecf5509",
+      "edit": ""
+    },
+    "ARM_AM_getAM2Op": {
+      "apply_type": "OLD",
+      "old_hash": "8eacd33cf973cd4c388a67967d0ccb1571c1f5acd7a96b01c21a7c9d22b1b3e3",
+      "new_hash": "9170286ed54ad2096bece239299246e09e2d1c4c0207d9bf67045c3c2e6760b0",
+      "edit": ""
+    },
+    "ARM_AM_getAM2Opc": {
+      "apply_type": "OLD",
+      "old_hash": "d0bc64e4b232db82001dea523aab12f38b2324c0f0bb9b994cc937918831fdfb",
+      "new_hash": "950183b6fe310411a92b84e91218b9cc0b142220ae54045d6f30b93efe1269a7",
+      "edit": ""
+    },
+    "ARM_AM_getAM2ShiftOpc": {
+      "apply_type": "OLD",
+      "old_hash": "c8948f4fcc5c119e386121c1001a9054fed8defbee9061cd72f2ba0365d5979d",
+      "new_hash": "65b0f515e542d325a16a79bfbcca1879f34d116bd36ee72210b399e875a9e804",
+      "edit": ""
+    },
+    "ARM_AM_getAM3IdxMode": {
+      "apply_type": "OLD",
+      "old_hash": "dd2adc35fe94347c445c80fa60e4840d3ceca15439d143ad6a0f5cc250f70f26",
+      "new_hash": "d87713cc6706e0acadaa0088c23726caefb0a2f6aeb54fe8a07696cb2058af76",
+      "edit": ""
+    },
+    "ARM_AM_getAM3Offset": {
+      "apply_type": "OLD",
+      "old_hash": "968fa24b564182bb2c961214bc8700c12f498b6555af347b69e7d8f92bec19cf",
+      "new_hash": "8349811ce80fb52f135d10ec018d4374d67a4ea77256dc0a9de93f8b5d2dc6f2",
+      "edit": ""
+    },
+    "ARM_AM_getAM3Op": {
+      "apply_type": "OLD",
+      "old_hash": "313f8eef19d721a770f3d18494d35101a59c102aa226ee8ecb0c7e2a2ad8b59e",
+      "new_hash": "30bd50d0368d2d9a87dfc7649d5e55855efdd0e1c6f153e4d1cb4ffb88cfee4b",
+      "edit": ""
+    },
+    "ARM_AM_getAM3Opc": {
+      "apply_type": "OLD",
+      "old_hash": "5ca20ce5d2ed07dcdd912965c02c5323ddd36a6f7712e7fcbe15711c3d4ee8f3",
+      "new_hash": "4d5e5d1d60bf680c9d87c30fbaf4d5ee8d9b781071ea35edf9969357ccdb8969",
+      "edit": ""
+    },
+    "ARM_AM_getAM4ModeImm": {
+      "apply_type": "OLD",
+      "old_hash": "39dd93dc2516d2babe9cf9b1b22c6d6358e0887ac691d3a8210c7def682c1d99",
+      "new_hash": "057f0b69b8885126db65609d61d7861e745f70678fc0b4cdd547517cf3781bf9",
+      "edit": ""
+    },
+    "ARM_AM_getAM4SubMode": {
+      "apply_type": "OLD",
+      "old_hash": "8e23306f176900bf3b9ce26172465532d65485eeb57757b32323fd76a72b157c",
+      "new_hash": "8ae0289c976949aab7de97549fb8655e285e3dd8f39b5b0077fbeacfc1ddd6cb",
+      "edit": ""
+    },
+    "ARM_AM_getAM5FP16Offset": {
+      "apply_type": "OLD",
+      "old_hash": "54e6ff39be8d31e9198ce0a58a34f6be2d6f79f30d4b9708eac808bc9522ffc7",
+      "new_hash": "e81b4c7f1f316ec048c33a8b8bb11acde25e1f6517095d39a8346fa7f72cd73c",
+      "edit": ""
+    },
+    "ARM_AM_getAM5FP16Op": {
+      "apply_type": "OLD",
+      "old_hash": "cfa02ca36fbe0391ea693aaf88673e0808d025312e887dbedfefec315fc09090",
+      "new_hash": "1200c63f8b75d7dd7088822ed94f2c30449655fce6e5043433ed9694b7c5752d",
+      "edit": ""
+    },
+    "ARM_AM_getAM5FP16Opc": {
+      "apply_type": "OLD",
+      "old_hash": "31ab00e2e5ca6d7e6f6558cc797badf547e2cb1d4e420c156ab33a2c9ad36dc5",
+      "new_hash": "1cfbde6a8ae285af27337b536b83521fc8ecd6cec0ccbd3e93e4e5811fbbb804",
+      "edit": ""
+    },
+    "ARM_AM_getAM5Offset": {
+      "apply_type": "OLD",
+      "old_hash": "39753b85a04c603500cd241e51b6051ab1f1161c5751f9cc9943feba8a933604",
+      "new_hash": "bc79a25f4f45a320661960582232f93d05aa139685fe5407dad5091f8b7dc018",
+      "edit": ""
+    },
+    "ARM_AM_getAM5Op": {
+      "apply_type": "OLD",
+      "old_hash": "8cb5b71316ea64e4d1397cc83b338ffdf03db131e8800f4a28c1453b04da6354",
+      "new_hash": "147ac382e3d1542f09f972885ee58c519b1df96ce0c8bdc6448f070a08963d68",
+      "edit": ""
+    },
+    "ARM_AM_getAM5Opc": {
+      "apply_type": "OLD",
+      "old_hash": "db8343f2a60ac06405d6dd9407f19060f0e208e578dbcccbbb812c327f9ed152",
+      "new_hash": "096cfd20c543e9c5d47a76bad44ab0fea7c1770f56fe2722e49aec1f820e12ad",
+      "edit": ""
+    },
+    "ARM_AM_getAMSubModeStr": {
+      "apply_type": "OLD",
+      "old_hash": "ce74d91930ae0836a39773acc93f9d9af3d176fb386c03045fdce659ddafc93a",
+      "new_hash": "2e559b4426dcacb7193a54663ba3e5fe0a9bb460e69538d19862c8e80c14a8c5",
+      "edit": ""
+    },
+    "ARM_AM_getAddrOpcStr": {
+      "apply_type": "OLD",
+      "old_hash": "874cd615fbae834cb493ec7e6c12497df8f71144d1d5f73863e24b2688a86a06",
+      "new_hash": "43f7343aed1cdd5e7d91231393e2298bafc9985ab1171603da4dab017231e3e4",
+      "edit": ""
+    },
+    "ARM_AM_getFPImmFloat": {
+      "apply_type": "OLD",
+      "old_hash": "b701b7192bbf232f992fb75f6b025609b6243881c56decaf3a3ec789e26b75c1",
+      "new_hash": "2c1787344950c82894a99240d9214aabab60924844b1c2eef4938c7ec0019e16",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmTwoPartFirst": {
+      "apply_type": "OLD",
+      "old_hash": "dc859c73453011a9165e6511738df1809f61d9939cb0e98097cab241d307ad68",
+      "new_hash": "b85e8d0b0218afddef20b20796ac641eaec59cae58aefb4262ad09d7922de7c2",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmTwoPartSecond": {
+      "apply_type": "OLD",
+      "old_hash": "2a4827167b657ea2b42aad88488e0d8c6e1c8eb76c92b26556e511244220ade0",
+      "new_hash": "543a85d41852c18f79d9987bdfbe869f9ae885426fc97ef61b9110ac878e43ce",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmVal": {
+      "apply_type": "OLD",
+      "old_hash": "43428220c58b44e2c989b3cc8c0f13cacda3bf53a49276ee6953db163a2c453b",
+      "new_hash": "dbe694b9859c85f70fad45da59df204321688105c7a0327084a9f9a7750f37e4",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmValImm": {
+      "apply_type": "OLD",
+      "old_hash": "bb0e902aa755a8d041eee1d7798bf0087a57f6beeb17e9d93a0370d62e0c1f14",
+      "new_hash": "86aaaf11a33a1b7f71aa58824675fac2c52fc017031ade13f595964cfbdd0231",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmValRot": {
+      "apply_type": "OLD",
+      "old_hash": "e922391e2bcc7bacc4df2b7fb70bbb1ebfe21f0604ab8c2898b24a231a3eadce",
+      "new_hash": "c9b1eda0b78fee9cbc5e1c7ccbf85be0eb9f67517fc6febcf3820d122add2fc9",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmValRotate": {
+      "apply_type": "OLD",
+      "old_hash": "093636bc78707389262f3f4fc443333ad996c7618ce4e8bd79a654d67ff8a940",
+      "new_hash": "01ba2494a7d43a8623095d2cffa039fdbd5edab4da984fe68a2dc8124f031d71",
+      "edit": ""
+    },
+    "ARM_AM_getSORegOffset": {
+      "apply_type": "OLD",
+      "old_hash": "a1f9f169b6579833d965db979941ee0b72d322f651df219222ca45d0ca24f6e7",
+      "new_hash": "bbae7e4abeadd5577b7df0dad8b72ada71db2ad23334e252b08b58cb0a8a384c",
+      "edit": ""
+    },
+    "ARM_AM_getSORegOpc": {
+      "apply_type": "OLD",
+      "old_hash": "86f5d2f46956379d3bcd34a438f4e3c0b5ae9220e21d029ddc073577cbf58427",
+      "new_hash": "4a31bcbc12e3920187297ef75306c1504548c87fb703223bb2de59aece89a109",
+      "edit": ""
+    },
+    "ARM_AM_getSORegShOp": {
+      "apply_type": "OLD",
+      "old_hash": "1a394d97f642a946279b28f8e7f12e5dd567c5a6d09ec02da795bc42960a5a87",
+      "new_hash": "221f5b7b8f4633174f8f9b856fa71dbe9c1929320c30c505d02926c5a8a1fe0e",
+      "edit": ""
+    },
+    "ARM_AM_getShiftOpcEncoding": {
+      "apply_type": "OLD",
+      "old_hash": "111fc0a3953dcf8e371a38bf178569b5e4b68e34e3b902a6b16cfbbc29e240a3",
+      "new_hash": "aa29dc3a4d73dbba90ce12de56d1fbc8eb78b9b124cd1b2e6f4fbddcb156e404",
+      "edit": ""
+    },
+    "ARM_AM_getShiftOpcStr": {
+      "apply_type": "OLD",
+      "old_hash": "feba37bca7fc4dedcc0727e4c0f0f46e01c0dc005589d3a60e8fbbf918d31485",
+      "new_hash": "164aee3544ec40e08408e599f8c287e7755e2e26de333d78f07b803fb4a8282a",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmTwoPartFirst": {
+      "apply_type": "OLD",
+      "old_hash": "aaae88603b39401c81c249b7c0335cfac95d3e34211e4b73cf0f18b75a792ad8",
+      "new_hash": "9471fecfeed2cc1bfea9194e36fe8107f413f9d91927b1fb8c463725e0bfa1e6",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmTwoPartSecond": {
+      "apply_type": "OLD",
+      "old_hash": "28f2af7ddacdf2b78e988b62fe5008a9f40ce64a06303022f126c5a146dc178d",
+      "new_hash": "da03c0d957937e69d618bea142f5615e911650b8df0d82e9ec58bd6572efffcc",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmVal": {
+      "apply_type": "OLD",
+      "old_hash": "0169fc2c1a915a598f8d2844353b80ea10374675156fd83960a01f37c74a3940",
+      "new_hash": "f078fa9fadd3ea56aa317feef8c80fb99dc8bb0b3687b2627911015f5182f5cb",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmValRotate": {
+      "apply_type": "OLD",
+      "old_hash": "7d5e9489c3ef1a80f452f4b6bd8b290c853a7e10a34fab6d891988d7cf0c8df8",
+      "new_hash": "19522b7e9d857a2dbb99f1673a595bf0da9007db078b3f6c7e2085a31df6fd1a",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmValRotateVal": {
+      "apply_type": "OLD",
+      "old_hash": "5e2aa248184c27af379dbfc1bafe403e3f0367de297d49beb893afc875362866",
+      "new_hash": "3c969521da0444705ed23cb50c36a073b754dd4f8eec04c8087b476ec5cf1b07",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmValSplatVal": {
+      "apply_type": "OLD",
+      "old_hash": "8646ff69d711508d3a895b5e403f41adf8ac1d884bd8db53d43276d41d3709d6",
+      "new_hash": "d65aeb9204ec89f72cfc31ea7928d9a88e3db93bfe6585136d2f9d8ddfe4b06e",
+      "edit": ""
+    },
+    "ARM_AM_getThumbImm16ValShift": {
+      "apply_type": "OLD",
+      "old_hash": "cb2d3b9c433f847b3c5a45439aad7c917af46fbaa34d738663cab1e96bbb88e4",
+      "new_hash": "8d90a8b8b4f91d5ab7a1a9f866a40446f89890f67baccc58a885933e9d9217eb",
+      "edit": ""
+    },
+    "ARM_AM_getThumbImmNonShiftedVal": {
+      "apply_type": "OLD",
+      "old_hash": "3822416499583204306abfa37f6af89e8e00e0f492c29aca032335238d134fd7",
+      "new_hash": "41e3c78bc92aad095de33b88c1a9400997804d2ad69344184f701b264fdbaa00",
+      "edit": ""
+    },
+    "ARM_AM_getThumbImmValShift": {
+      "apply_type": "OLD",
+      "old_hash": "64e51398dde6bdb03c645425557944517740dad87f7f3acd3a132529a6d88f5c",
+      "new_hash": "62072076bcef753b21752e6e1f27e3b93909eb197e208d09866aa6e4dd02ed99",
+      "edit": ""
+    },
+    "ARM_AM_getVMOVModImmOpCmode": {
+      "apply_type": "OLD",
+      "old_hash": "3dc201029cbfc7eaf84bc2778c2d677a0906da9b0378f50d0a4499e19e2eccdc",
+      "new_hash": "6713eccf00c4127a96b8147da41c2eb7d8d91896dedd7ff01f97b6b8c91ab492",
+      "edit": ""
+    },
+    "ARM_AM_getVMOVModImmVal": {
+      "apply_type": "OLD",
+      "old_hash": "b7e474123c49f78fc16b20a129d160ebd473d5a5e00a0ca8dd91834e94d602f8",
+      "new_hash": "cb1525c3552784d93be28f8330c116273df1685eb7ed974edb744d32621a1dee",
+      "edit": ""
+    },
+    "ARM_AM_isNEONBytesplat": {
+      "apply_type": "OLD",
+      "old_hash": "8332f2fd86baed5a2427550d62ee833cd3c6054a99a4cef38e7fba2e2d889c6b",
+      "new_hash": "53190f9c11fc5a7e0c1e38474b72156d69c5b3893d538a4c76d090e6f6034a0a",
+      "edit": ""
+    },
+    "ARM_AM_isNEONi16splat": {
+      "apply_type": "OLD",
+      "old_hash": "a0938026315cc63cb531a85471e6d45f58eb50a4058a622c25472f453b2b8619",
+      "new_hash": "2a3a64ccb9a6155cfe4e5a9ad67ee16f1d5dd45f1cd3b1564600c1b28c0d6c01",
+      "edit": ""
+    },
+    "ARM_AM_isNEONi32splat": {
+      "apply_type": "OLD",
+      "old_hash": "e82588ad097f60ed35e179264ba1e3e7644ea64a7162622f944692bd9adab37e",
+      "new_hash": "9bef85dfdb0e7f6309eaac91a55697d410a950abe7e8e24098b64c4faca89f33",
+      "edit": ""
+    },
+    "ARM_AM_isSOImmTwoPartVal": {
+      "apply_type": "OLD",
+      "old_hash": "8239a5ed54d74daa8eb26ee113f07c2de10b04e50c13a2b982a8b11fd675ea66",
+      "new_hash": "ce0c930874ec6803d2b171e516218178cccde91a19577887ae5c021a123440db",
+      "edit": ""
+    },
+    "ARM_AM_isSOImmTwoPartValNeg": {
+      "apply_type": "OLD",
+      "old_hash": "caa5671e598be177e85348dc91e7750ba7b04655689c17a9351a298b6a23a34e",
+      "new_hash": "c00be464bbfac51e71628c71bdd8d2e5d775f14911b5556b7f926e7b3f3a59d1",
+      "edit": ""
+    },
+    "ARM_AM_isT2SOImmTwoPartVal": {
+      "apply_type": "OLD",
+      "old_hash": "6cb24668a4e3d4946703eb15695547429008f5a85e9dcc7b909684cdc29e6913",
+      "new_hash": "9e98720bcb01546e795c8ceb52d3b1167eaa5c9e43a9671dc52797529e71d0ef",
+      "edit": ""
+    },
+    "ARM_AM_isThumbImm16ShiftedVal": {
+      "apply_type": "OLD",
+      "old_hash": "465b428de9df7274b97fe809f14d9daaf182980700aa88178a021716848215cb",
+      "new_hash": "d56f0a8e4dd0f7105405ab3543784572b669abbd542b40f9b1fae0dc05fccd9b",
+      "edit": ""
+    },
+    "ARM_AM_isThumbImmShiftedVal": {
+      "apply_type": "OLD",
+      "old_hash": "cf9a79c66fbc0cdc23188e8fae364995e78bbbb80e7f232c02c9e706b806e059",
+      "new_hash": "a79c7bfcab2471647f1a471f6cfaa8456050c67144b53477ea5b90a3e1d9c590",
+      "edit": ""
+    },
+    "ARM_AM_rotl32": {
+      "apply_type": "OLD",
+      "old_hash": "49814ded27d6461862f6fe0c61f1ea90e34e8e384295fafeba8d3798698c8836",
+      "new_hash": "1c4e01d119292eea41f99f0d876e8cfce8fa817837b2b8a0ca93da1aae775b3c",
+      "edit": ""
+    },
+    "ARM_AM_rotr32": {
+      "apply_type": "OLD",
+      "old_hash": "0d1d02c7bc72b178174913e3a39a36d680a83234954a6018b54102b9a8ca7f0a",
+      "new_hash": "7372b1713eac46155f82a51f57ca7fc8dee71efda6b88f36693d57c30552570d",
+      "edit": ""
+    },
+    "CONCAT": {
+      "apply_type": "OLD",
+      "old_hash": "9d54def8e6c2e86efddf81ae412925c77492de8e619f178600b2b92cb8294a44",
+      "new_hash": "e4820f6346c51882017758424dbd39c22bb34a7c43a2aa02295c421e610963dc",
+      "edit": ""
+    }
+  },
+  "ARMBaseInfo.c": {
+    "ARMSysReg_lookupMClassSysRegAPSRNonDeprecated": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "46a413e3efb1147c7f53e9bfca46a008b1e674743af943a919aa9da3a621a24e",
+      "edit": ""
+    },
+    "ARMSysReg_lookupMClassSysRegBy12bitSYSmValue": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "faa313843f323f690e2b7d068f4c73ddfd02a855c6929b974cfe5619ac5bf77f",
+      "edit": ""
+    },
+    "ARMSysReg_lookupMClassSysRegBy8bitSYSmValue": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "a742d04516ad454bbae24b897a8446be964c2fe94d69c8bfd70e1049042c990b",
+      "edit": ""
+    },
+    "CONCAT": {
+      "apply_type": "OLD",
+      "old_hash": "9d54def8e6c2e86efddf81ae412925c77492de8e619f178600b2b92cb8294a44",
+      "new_hash": "e4820f6346c51882017758424dbd39c22bb34a7c43a2aa02295c421e610963dc",
+      "edit": ""
+    },
+    "expandPredBlockMask": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "d438f752cf47f9ce9b5c86ecb0f5c533967e669d722b10bca5f7b8bb9438c3a1",
+      "edit": ""
+    },
+    "get_pred_mask": {
+      "apply_type": "OLD",
+      "old_hash": "2df9f0a4b700c0018e11b43f128edf5e56ca51994895f573ba372657f1b42ac3",
+      "new_hash": "",
+      "edit": ""
+    },
+    "lookupMClassSysRegAPSRNonDeprecated": {
+      "apply_type": "OLD",
+      "old_hash": "b424a3c3bb4fd75e9e0cdb11fd783c942519fa25fe31e930fde1e033bc7c695a",
+      "new_hash": "",
+      "edit": ""
+    },
+    "lookupMClassSysRegBy12bitSYSmValue": {
+      "apply_type": "OLD",
+      "old_hash": "eea213a2863c54ffa542d667b376919e4a1b8094f3f41cf950e9a1cc2fd73b1c",
+      "new_hash": "",
+      "edit": ""
+    },
+    "lookupMClassSysRegBy8bitSYSmValue": {
+      "apply_type": "OLD",
+      "old_hash": "544a8a7ac86577daa605ad976141d8166491017176b0e3a73d2e79581dff8501",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"ARMBaseInfo.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "c2628208478c4f7d6c48f4657e7cf14e1f896657f8370938b8c438ca5517c45f",
+      "new_hash": "2be2e93095820dd9bd4b4974e4568fb2c45c8f7401a92553fc0e222812889efa",
+      "edit": ""
+    },
+    "\"ARMGenSystemRegister.inc\"": {
+      "apply_type": "OLD",
+      "old_hash": "76a3d513fb74a9c14aaf369a2e41e6692dcb2ea64984e6430e7be44b72c8cbc3",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"ARMMapping.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "e010fe7fc5dbf57e7bdcec6beec5538edecf8fa40f2426bf12d2b37fff5cde57",
+      "new_hash": "",
+      "edit": ""
+    }
+  }
+}
\ No newline at end of file
diff --git a/suite/auto-sync/LLVM_Deprecated_Features.md b/suite/auto-sync/LLVM_Deprecated_Features.md
new file mode 100644
index 000000000..c16189e7f
--- /dev/null
+++ b/suite/auto-sync/LLVM_Deprecated_Features.md
@@ -0,0 +1,34 @@
+Capstone needs to support features which were removed by LLVM in the past.
+All the steps described must be done in the LLVM repository.
+
+To get the old features back we copy them from the old `.td` files and include them in the new ones.
+
+To include removed features from previous LLVM versions do the following:
+
+1. Checkout the last LLVM version the feature was present.
+2. Copy all feature related definitions into a `<ARCH>Deprecated.td` file.
+3. Checkout the newest LLVM version again.
+4. Wrap the different definition types in include guards. For example the `InstrInfo` definitions could be included in:
+
+```
+#ifndef INCLUDED_CAPSTONE_DEPR_INSTR
+#ifdef CAPSTONE_DEPR_INSTR
+#define INCLUDED_CAPSTONE_DEPR_INSTR // Ensures it is only included once
+
+[Instruction definitions of removed feature]
+
+#endif // INCLUDED_CAPSTONE_DEPR_INSTR
+#endif // CAPSTONE_DEPR_INSTR
+```
+
+Note that the order of `#ifndef` and `#ifdef` matters (otherwise you'll get an error from `tblgen`).
+
+4. Include the definitions in the current definition files with:
+
+```
+#define CAPSTONE_DEPR_INSTR
+include "<ARCH>Deprecated.md"
+```
+
+- It is possible that you have to change some definitions slightly (e.g.: `GCCBuiltin` -> `ClangBuiltin`).
+- Some new processors might need to have the feature flag (`Has<DeprecatedFeature>`) added to their `UnsupportedFeatures` list.
diff --git a/suite/auto-sync/PatchMainHeader.py b/suite/auto-sync/PatchMainHeader.py
new file mode 100755
index 000000000..75c688fd6
--- /dev/null
+++ b/suite/auto-sync/PatchMainHeader.py
@@ -0,0 +1,83 @@
+#!/usr/bin/env python3
+
+import argparse
+import re
+from pathlib import Path
+
+
+def parse_args() -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        prog="PatchHeaders",
+        description="Patches generated enums into the main arch header file.",
+    )
+    parser.add_argument("--header", dest="header", help="Path header file.", type=Path, required=True)
+    parser.add_argument("--inc", dest="inc", help="Path inc file.", type=Path, required=True)
+    arguments = parser.parse_args()
+    return arguments
+
+
+def error_exit(msg: str) -> None:
+    print(f"[x] {msg}")
+    exit(1)
+
+
+def patch_header(header: Path, inc: Path) -> None:
+    if not (header.exists() or header.is_file()):
+        error_exit(f"Header file {header.name} does not exist.")
+
+    if not (inc.exists() or inc.is_file()):
+        error_exit(f".inc file {inc.name} does not exist.")
+
+    with open(header) as f:
+        header_content = f.read()
+
+    if inc.name not in header_content:
+        error_exit(f"{inc.name} has no include comments in {header.name}")
+
+    with open(inc) as f:
+        inc_content = f.read()
+
+    to_write: dict[str:str] = {}
+    enum_vals_id = ""
+    for line in inc_content.splitlines():
+        # No comments and empty lines
+        if "/*" == line[:2] or not line:
+            continue
+
+        if "#ifdef" in line:
+            enum_vals_id = line[7:].strip("\n")
+            to_write[enum_vals_id] = ""
+        elif "#endif" in line:
+            enum_vals_id = ""
+        elif "#undef" in line:
+            continue
+        else:
+            if not enum_vals_id:
+                raise ValueError(f"{inc.name} incorrectly formatted. No #ifdef getter.")
+            to_write[enum_vals_id] += re.sub(r"^(\s+)?", "\t", line) + "\n"
+    for ev_id in to_write.keys():
+        regex = (
+            rf"\s*// generated content <{inc.name}:{ev_id}> begin.*(\n)"
+            rf"(.*\n)+"
+            rf"\s*// generated content <{inc.name}:{ev_id}> end.*(\n)"
+        )
+        if not re.search(regex, header_content):
+            error_exit(f"Could not locate include comments for {inc.name}")
+
+        new_content = (
+            f"\n\t// generated content <{inc.name}:{ev_id}> begin\n"
+            + "\t// clang-format off\n\n"
+            + to_write[ev_id]
+            + "\n\t// clang-format on\n"
+            + f"\t// generated content <{inc.name}:{ev_id}> end\n"
+        )
+
+        header_content = re.sub(regex, new_content, header_content)
+    with open(header, "w") as f:
+        f.write(header_content)
+    print(f"[*] Patched {inc.name} into {header.name}")
+
+
+if __name__ == "__main__":
+    args = parse_args()
+    patch_header(args.header, args.inc)
diff --git a/suite/auto-sync/README.md b/suite/auto-sync/README.md
new file mode 100644
index 000000000..24a5656ca
--- /dev/null
+++ b/suite/auto-sync/README.md
@@ -0,0 +1,115 @@
+# Architecture updater
+
+This is Capstones updater for some architectures.
+Unfortunately not all architectures are supported yet.
+
+## Install dependencies
+
+Clone C++ grammar
+
+```
+git submodule update --init --recursive ./vendor/
+```
+
+Setup Python environment and Tree-sitter
+
+```
+sudo apt install python3-venv
+cd CppTranslator
+python3 -m venv ./.venv
+source ./.venv/bin/activate
+pip3 install -r requirements.txt
+cd ..
+```
+
+Install clang-format
+
+```
+sudo apt install clang-format-16
+```
+
+## Update
+
+Check if your architecture is supported.
+
+```
+./Update-Arch.sh -h
+```
+
+Clone Capstones LLVM fork.
+
+```
+git clone https://github.com/capstone-engine/llvm-capstone
+cd llvm-capstone
+```
+
+Checkout the branch with the refactored backends
+
+```
+git checkout auto-sync
+```
+
+Build `llvm-tblgen`
+
+```
+mkdir build
+cd build
+cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
+cmake --build . --target llvm-tblgen --config Debug
+cd ../../
+```
+
+Run the updater
+
+```
+mkdir build
+cd build
+../Update-Arch.sh <ARCH> ./llvm-capstone
+```
+
+## Post-processing steps
+
+This update translates some LLVM C++ files to C.
+Because the translation is not perfect (maybe it will some day)
+you will get build errors if you try to compile Capstone.
+
+The last step to finish the update is to fix those build errors by hand.
+
+## Developer
+
+### Overview updated files
+
+This is a rough overview what files of an architecture are updated and where they are coming from.
+
+**Files originating from LLVM** (Automatically updated)
+
+TODO: The "<ARCH>LLVM*" files are not renamed yet.
+
+- `<ARCH>LLVM*.*`: These files are LLVM source files which were translated from C++ to C.
+  - Because the translation is not perfect, those files need some hands on work afterwards (see below).
+- `<ARCH>Gen*.inc`: These files are exclusively generated by LLVM TableGen backends.
+
+These files form the actual disassembler and assembler printer.
+
+**Capstone module files** (Not automatically updated)
+
+- `<ARCH>Mapping.*`: Binding code between the architecture module and the LLVM files.
+- `<ARCH>Module.*`: Interface for the Capstone core.
+- `<ARCH>DisassemblerExtension.*` All kind of functions which are needed by `<ARCH>LLVMDisassembler.c` but could not be generated or translated.
+
+### Update procedure
+
+1. Run the `Update-Arch.sh` script.
+2. Compare the functions in `<ARCH>DisassemblerExtension.*` to LLVM (search the function names in the LLVM root)
+and update them if necessary.
+3. Try to build Capstone and fix the build errors.
+
+### Update details
+
+**LLVM file translation**
+
+For details about the C++ to C translation of the LLVM files refer to `CppTranslator/README.md`.
+
+**Generated .inc files**
+
+Documentation about the `.inc` file generation is in the [llvm-capstone](https://github.com/capstone-engine/llvm-capstone) repository.
\ No newline at end of file
diff --git a/suite/auto-sync/Update-Arch.sh b/suite/auto-sync/Update-Arch.sh
new file mode 100755
index 000000000..7380bf9b1
--- /dev/null
+++ b/suite/auto-sync/Update-Arch.sh
@@ -0,0 +1,175 @@
+#!/bin/sh
+
+check_llvm() {
+  llvm_root=$1
+  tblgen=$2
+
+  if [ ! -e "../vendor/llvm_root" ]; then
+    echo "[*] Create symlink '../vendor/llvm_root -> $llvm_root'."
+    ln -s "$llvm_root" ../vendor/llvm_root
+  fi
+
+  if [ ! -f $tblgen ]; then
+    echo "[x] llvm-tblgen not found at '$tblgen'"
+    exit
+  fi
+}
+
+
+llvm_c_inc_dir="llvm_c_inc"
+llvm_inc_dir="llvm_inc"
+translator_dir="trans_out"
+ts_so_dir="ts_libs"
+diff_dir="diff_out"
+
+setup_build_dir() {
+  if [ ! -d "$llvm_inc_dir" ]; then
+    echo "[*] Create ./$llvm_inc_dir directory"
+    mkdir $llvm_inc_dir
+  fi  
+
+  if [ ! -d "$llvm_c_inc_dir" ]; then
+    echo "[*] Create ./$llvm_c_inc_dir directory"
+    mkdir $llvm_c_inc_dir
+  fi
+
+  if [ ! -d "$translator_dir" ]; then
+    echo "[*] Create ./$translator_dir directory"
+    mkdir $translator_dir
+  fi
+
+  if [ ! -d "$ts_so_dir" ]; then
+    echo "[*] Create ./$ts_so_dir directory"
+    mkdir $ts_so_dir
+  fi
+
+  if [ ! -d "$diff_dir" ]; then
+    echo "[*] Create ./$diff_dir directory"
+    mkdir $diff_dir
+  fi  
+}
+
+#
+# Main
+#
+
+supported="ARM"
+
+if [ $# -ne 3 ] || [ "$1" = "-h" ] || [ "$1" = "--help" ]; then
+  echo "$0 <arch> <path-llvm-project> <llvm-release-commit>"
+  echo "\nCurrently supported architectures: $supported"
+  exit
+fi
+
+arch="$1"
+llvm_root="$2"
+llvm_release_commit="$3"
+tblgen="$llvm_root/build/bin/llvm-tblgen"
+llvm_target_dir="$1"
+
+if ! echo $supported | grep -q -w "$arch" ; then
+  echo "[x] $arch is not supported by the updater. Supported are: $supported"
+  exit
+fi
+
+if [ $arch = "PPC" ]; then
+  llvm_target_dir="PowerPC"
+fi
+
+setup_build_dir
+check_llvm $llvm_root $tblgen
+
+echo "[*] Generate Disassembler tables..."
+$tblgen --printerLang=CCS --gen-disassembler -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_c_inc_dir"/"$arch"GenDisassemblerTables.inc"
+$tblgen --printerLang=C++ --gen-disassembler -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_inc_dir"/"$arch"GenDisassemblerTables.inc"
+
+echo "[*] Generate AsmWriter tables..."
+$tblgen --printerLang=CCS --gen-asm-writer -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_c_inc_dir"/"$arch"GenAsmWriter.inc"
+$tblgen --printerLang=C++ --gen-asm-writer -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_inc_dir"/"$arch"GenAsmWriter.inc"
+
+echo "[*] Generate RegisterInfo tables..."
+$tblgen --printerLang=CCS --gen-register-info -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_c_inc_dir"/"$arch"GenRegisterInfo.inc"
+
+echo "[*] Generate InstrInfo tables..."
+$tblgen --printerLang=CCS --gen-instr-info -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_c_inc_dir"/"$arch"GenInstrInfo.inc"
+
+echo "[*] Generate SubtargetInfo tables..."
+$tblgen --printerLang=CCS --gen-subtarget -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td" > $llvm_c_inc_dir"/"$arch"GenSubtargetInfo.inc"
+
+echo "[*] Generate Mapping tables..."
+$tblgen --printerLang=CCS --gen-asm-matcher -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td"
+
+echo "[*] Generate System Register tables..."
+$tblgen --printerLang=CCS --gen-searchable-tables -I "$llvm_root/llvm/include/" -I "$llvm_root/llvm/lib/Target/$llvm_target_dir/" "$llvm_root/llvm/lib/Target/$llvm_target_dir/$arch.td"
+sed -i "s/##ARCH##/$arch/g" __ARCH__GenCSSystemRegisterEnum.inc
+sed -i "s/##ARCH##/$arch/g" __ARCH__GenSystemRegister.inc
+cp __ARCH__GenCSSystemRegisterEnum.inc $arch"GenCSSystemRegisterEnum.inc"
+cp __ARCH__GenSystemRegister.inc $arch"GenSystemRegister.inc"
+
+if find -- "../vendor/tree-sitter-cpp/" -prune -type d -empty | grep -q '^'; then
+  echo "[*] Clone tree-sitter-cpp..."
+  git submodule update --init --recursive
+fi
+
+echo "[*] Translate LLVM source files..."
+cd ../CppTranslator/
+if [ ! -d "./.venv" ] ; then
+  echo "[*] Setup python3 venv and install dependencies"
+  python3 -m venv .venv
+  . ./.venv/bin/activate
+  pip3 install -r requirements.txt
+else
+  . ./.venv/bin/activate
+fi
+./CppTranslator.py -a "$arch" -g "../vendor/tree-sitter-cpp/" -l "../build/ts_libs/ts-cpp.so"
+echo "[*] Run differ..."
+./Differ.py -a "$arch" -g "../vendor/tree-sitter-cpp"
+cd ../build
+
+cs_root=$(git rev-parse --show-toplevel)
+
+cd $llvm_root
+llvm_release_tag=$(git describe --tag $llvm_release_commit)
+cd "$cs_root/suite/auto-sync/build"
+
+cs_arch_dir="$cs_root/arch/$arch/"
+cs_inc_dir="$cs_root/include/capstone"
+
+into_arch_main_header=$arch"GenCSInsnEnum.inc "$arch"GenCSFeatureEnum.inc "$arch"GenCSRegEnum.inc "$arch"GenCSSystemRegisterEnum.inc"
+header_file=$(echo "$arch" | awk '{print tolower($0)}')
+main_header="$cs_inc_dir/$header_file.h"
+
+for f in $into_arch_main_header; do
+  ../PatchMainHeader.py --header "$main_header" --inc "$f"
+done
+
+for f in $(ls | grep "\.inc"); do
+  if ! echo $into_arch_main_header | grep -q -w $f ; then
+    sed -i "s/LLVM-commit: <commit>/LLVM-commit: $llvm_release_commit/g" $f
+    sed -i "s/LLVM-tag: <tag>/LLVM-tag: $llvm_release_tag/g" $f
+    cp $f $cs_arch_dir
+    echo "[*] Copy $f"
+  fi
+done
+for f in $(ls $llvm_c_inc_dir/$arch*); do
+  sed -i "s/LLVM-commit: <commit>/LLVM-commit: $llvm_release_commit/g" $f
+  sed -i "s/LLVM-tag: <tag>/LLVM-tag: $llvm_release_tag/g" $f
+  cp $f $cs_arch_dir
+  echo "[*] Copy $f"
+done
+
+for f in $(ls $diff_dir/$arch*); do
+  sed -i "s/LLVM-commit: <commit>/LLVM-commit: $llvm_release_commit/g" $f
+  sed -i "s/LLVM-tag: <tag>/LLVM-tag: $llvm_release_tag/g" $f
+  cp $f $cs_arch_dir
+  echo "[*] Copy $f"
+done
+
+echo "[*] Apply patches to inc files"
+
+cd $cs_root
+p_dir="$cs_root/suite/auto-sync/inc_patches"
+for f in $(ls $p_dir); do
+  echo "[*] Apply $f"
+  git apply "$p_dir/$f"
+done
diff --git a/suite/auto-sync/inc_patches/01_LDM_written_reglists.patch b/suite/auto-sync/inc_patches/01_LDM_written_reglists.patch
new file mode 100644
index 000000000..b77876c65
--- /dev/null
+++ b/suite/auto-sync/inc_patches/01_LDM_written_reglists.patch
@@ -0,0 +1,289 @@
+# Sets the correct access attributes for register lists of LDM instrucions.
+# See issue: https://github.com/llvm/llvm-project/issues/62455
+
+ arch/ARM/ARMGenCSMappingInsnOp.inc | 62 +++++++++++++++++++-------------------
+ 1 file changed, 31 insertions(+), 31 deletions(-)
+
+diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
+index 3b4e2843..e64bdc8f 100644
+--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
++++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
+@@ -4703,7 +4703,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -4712,7 +4712,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -4722,7 +4722,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -4988,7 +4988,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -4998,7 +4998,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -5007,7 +5007,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -5017,7 +5017,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -5026,7 +5026,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -5036,7 +5036,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -5045,7 +5045,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -5055,7 +5055,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -22916,7 +22916,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -22925,7 +22925,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -22935,7 +22935,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -22948,7 +22948,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -22957,7 +22957,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -22967,7 +22967,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32467,7 +32467,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32477,7 +32477,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32486,7 +32486,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32496,7 +32496,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32505,7 +32505,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32515,7 +32515,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32524,7 +32524,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -32534,7 +32534,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -33417,7 +33417,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -33427,7 +33427,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -33436,7 +33436,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -33446,7 +33446,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -36467,7 +36467,7 @@
+   { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* Rn */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+@@ -36659,7 +36659,7 @@
+ {
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
diff --git a/suite/auto-sync/inc_patches/02_VSCCLRM_written_reglists.patch b/suite/auto-sync/inc_patches/02_VSCCLRM_written_reglists.patch
new file mode 100644
index 000000000..1b454510a
--- /dev/null
+++ b/suite/auto-sync/inc_patches/02_VSCCLRM_written_reglists.patch
@@ -0,0 +1,27 @@
+# Sets the correct access attributes for register lists of VSCCLRM instrucions.
+# See issue: https://github.com/llvm/llvm-project/issues/62455
+
+diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc
+index 1e3b9570b..524f339b7 100644
+--- a/arch/ARM/ARMGenCSMappingInsnOp.inc
++++ b/arch/ARM/ARMGenCSMappingInsnOp.inc
+@@ -28304,17 +28304,17 @@
+ }},
+ { /* ARM_VSCCLRMD (3410) - ARM_INS_VSCCLRM - vscclrm{$p}	$regs */
+ {
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
+ { /* ARM_VSCCLRMS (3411) - ARM_INS_VSCCLRM - vscclrm{$p}	$regs */
+ {
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+   { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* p - i32imm */
+-  { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
++  { CS_OP_IMM, CS_AC_WRITE, { CS_DATA_TYPE_i32, CS_DATA_TYPE_LAST } }, /* regs */
+   { CS_OP_INVALID, CS_AC_READ, { CS_DATA_TYPE_LAST } }, /*  */
+   { 0 }
+ }},
diff --git a/suite/cstest/include/helper.h b/suite/cstest/include/helper.h
index 102230385..fcdeabffa 100644
--- a/suite/cstest/include/helper.h
+++ b/suite/cstest/include/helper.h
@@ -24,6 +24,7 @@ void add_str(char **src, const char *format, ...);
 void trim_str(char *src);
 void replace_hex(char *src);
 void replace_negative(char *src, int mode);
+void replace_tabs(char *str);
 const char *get_filename_ext(const char *filename);
 
 char *readfile(const char *filename);
diff --git a/suite/cstest/src/arm_detail.c b/suite/cstest/src/arm_detail.c
index f1d6402a9..92d820af0 100644
--- a/suite/cstest/src/arm_detail.c
+++ b/suite/cstest/src/arm_detail.c
@@ -103,13 +103,19 @@ char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
 			add_str(&result, " ; Subtracted: True");
 	}
 
-	if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
+	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF)
 		add_str(&result, " ; Code condition: %u", arm->cc);
 
+	if (arm->pred_mask)
+		add_str(&result, " ; Predicate Mask: 0x%x", arm->pred_mask);
+
+	if (arm->vcc != ARMVCC_None)
+		add_str(&result, " ; Vector code condition: %u", arm->vcc);
+
 	if (arm->update_flags)
 		add_str(&result, " ; Update-flags: True");
 
-	if (arm->writeback)
+	if (ins->detail->writeback)
 		add_str(&result, " ; Write-back: True");
 
 	if (arm->cps_mode)
diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c
index aca123682..446acbda3 100644
--- a/suite/cstest/src/capstone_test.c
+++ b/suite/cstest/src/capstone_test.c
@@ -2,6 +2,7 @@
 /* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
 
 
+#include "../../../cs_priv.h"
 #include "capstone_test.h"
 
 char *(*function)(csh *, cs_mode, cs_insn*) = NULL;
@@ -34,6 +35,7 @@ void test_single_MC(csh *handle, int mc_mode, char *line)
 		code[i] = (unsigned char)strtol(list_byte[i], NULL, 16);
 	}
 
+	((struct cs_struct *)(uintptr_t)*handle)->PrintBranchImmNotAsAddress = true;
 	count = cs_disasm(*handle, code, size_byte, offset, 0, &insn);
 	if (count == 0) {
 		fprintf(stderr, "[  ERROR   ] --- %s --- Failed to disassemble given code!\n", list_part[0]);
@@ -59,6 +61,7 @@ void test_single_MC(csh *handle, int mc_mode, char *line)
 	strcpy(tmp_mc, list_part[1]);
 	replace_hex(tmp_mc);
 	replace_negative(tmp_mc, mc_mode);
+	replace_tabs(tmp_mc);
 
 	strcpy(tmp, insn[0].mnemonic);
 	if (strlen(insn[0].op_str) > 0) {
@@ -70,9 +73,16 @@ void test_single_MC(csh *handle, int mc_mode, char *line)
 	strcpy(origin, tmp);
 	replace_hex(tmp);
 	replace_negative(tmp, mc_mode);
+	replace_tabs(tmp);
+	for (p = tmp; *p; ++p) *p = tolower(*p);
 
-	if (cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME) == CS_ERR_OK) {
+	// Skip ARM because the duplicate disassembly messes with the IT/VPT states
+	// and laeds to wrong results.
+	cs_arch arch = ((struct cs_struct *)(uintptr_t)*handle)->arch;
+	if ((arch != CS_ARCH_ARM) &&
+			(cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME) == CS_ERR_OK)) {
 		cs_disasm(*handle, code, size_byte, offset, 0, &insn);
+
 		strcpy(tmp_noreg, insn[0].mnemonic);
 		if (strlen(insn[0].op_str) > 0) {
 			tmp_noreg[strlen(insn[0].mnemonic)] = ' ';
diff --git a/suite/cstest/src/helper.c b/suite/cstest/src/helper.c
index a70dca3d4..ccf9f1d46 100644
--- a/suite/cstest/src/helper.c
+++ b/suite/cstest/src/helper.c
@@ -265,3 +265,28 @@ void trim_str(char *str)
 
 	return;
 }
+
+void replace_tabs(char *str)
+{
+	char tmp[MAXMEM];
+	bool space_char = false;
+
+	int j = 0;
+	for (int i = 0; i <= strlen(str); ++i) {
+		if (str[i] == ' ' || str[i] == '\t') {
+			space_char = true;
+			continue;
+		}
+		if (space_char) {
+			space_char = false;
+			tmp[j++] = ' ';
+		}
+
+		tmp[j++] = str[i];
+	}
+
+	tmp[j] = '\0';
+	strcpy(str, tmp);
+
+	return;
+}
diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c
index 09591e1de..bed4303c4 100644
--- a/suite/cstest/src/main.c
+++ b/suite/cstest/src/main.c
@@ -80,6 +80,7 @@ static single_dict arches[] = {
 	{"CS_OPT_SYNTAX_ATT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT},
 	{"CS_OPT_SYNTAX_NOREGNAME", CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME},
 	{"CS_OPT_SYNTAX_MASM", CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM},
+	{"CS_OPT_BRANCH_OFFSET", CS_OPT_NO_BRANCH_OFFSET, CS_OPT_NO_BRANCH_OFFSET},
 	{"CS_MODE_LITTLE_ENDIAN", CS_OPT_MODE, CS_MODE_LITTLE_ENDIAN},
 	{"CS_MODE_ARM", CS_OPT_MODE, CS_MODE_ARM},
 	{"CS_MODE_16", CS_OPT_MODE, CS_MODE_16},
@@ -135,8 +136,7 @@ static int getDetail;
 static int mc_mode;
 static int e_flag;
 
-static int setup_MC(void **state)
-{
+static int setup_state(void **state) {
 	csh *handle;
 	char **list_params;	
 	int size_params;
@@ -197,18 +197,13 @@ static int setup_MC(void **state)
 		failed_setup = 1;
 		return -1;
 	}
-	
-	for (i = 0; i < ARR_SIZE(options); ++i) {
-		if (strstr(list_params[2], options[i].str)) {
-			if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) {
-				fprintf(stderr, "[  ERROR   ] --- Option is not supported for this arch/mode\n");
-				failed_setup = 1;
-				return -1;
-			}
-		}
-	}
-
 	*state = (void *)handle;
+	free_strs(list_params, size_params);
+	return 0;
+}
+
+static int setup_MC(void **state)
+{
 	counter++;
 	if (e_flag == 0)
 		while (counter < size_lines && strncmp(list_lines[counter], "0x", 2))
@@ -217,7 +212,6 @@ static int setup_MC(void **state)
 		while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5))
 			counter++;
 
-	free_strs(list_params, size_params);
 	return 0;
 }
 
@@ -229,7 +223,7 @@ static void test_MC(void **state)
 		test_single_MC((csh *)*state, mc_mode, list_lines[counter]);
 }
 
-static int teardown_MC(void **state)
+static int teardown_state(void **state)
 {
 	cs_close(*state);
 	free(*state);
@@ -405,13 +399,13 @@ static void test_file(const char *filename)
 				tmp = (char *)malloc(sizeof(char) * 100);
 				sprintf(tmp, "Line %d", i+1);
 				tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1));
-				tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_MC, setup_MC, teardown_MC);
+				tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_MC, setup_MC, NULL);
 				tests[number_of_tests].name = tmp;
 				number_of_tests ++;
 			}
 		}
 
-		_cmocka_run_group_tests("Testing MC", tests, number_of_tests, NULL, NULL);
+		_cmocka_run_group_tests("Testing MC", tests, number_of_tests, setup_state, teardown_state);
 	}
 
 	printf("[+] DONE: %s\n", filename);
diff --git a/suite/fuzz/README.md b/suite/fuzz/README.md
index 27c1c0c36..b1e73cf9b 100644
--- a/suite/fuzz/README.md
+++ b/suite/fuzz/README.md
@@ -16,6 +16,12 @@ You can find this in travis configuration `.travis.yml`
 
 Another way is to use oss-fuzz, see https://github.com/google/oss-fuzz/blob/master/projects/capstone/build.sh
 
+Troubleshooting
+------
+
+If you get `cc: error: unrecognized argument to ‘-fsanitize=’ option: ‘fuzzer’` check if you have a workable
+version of `libfuzz` installed. Also try to build with `CC=clang make`
+
 Fuzz drivers
 ------
 
diff --git a/suite/test_corpus.py b/suite/test_corpus.py
index def608a0c..fe91a49e7 100755
--- a/suite/test_corpus.py
+++ b/suite/test_corpus.py
@@ -47,6 +47,7 @@ def test_file(fname):
         "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8,
         "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8,
         "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
+        "CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS,
         "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
         "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
         "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
@@ -78,32 +79,33 @@ def test_file(fname):
         ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): 4,
         ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): 5,
         ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): 6,
-        ("CS_ARCH_ARM64", "0"): 7,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 8,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 9,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 10,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 11,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 12,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 13,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 13,
-        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 14,
-        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 15,
-        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 16,
-        ("CS_ARCH_SYSZ", "0"): 17,
-        ("CS_ARCH_XCORE", "0"): 18,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 19,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 20,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 21,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 22,
-        ("CS_ARCH_M68K", "0"): 23,
-        ("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 24,
-        ("CS_ARCH_EVM", "0"): 25,
-        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC"): 29,
-        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED"): 30,
-        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC"): 31,
-        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 32,
-        ("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 44,
-        ("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 45,
+        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS"): 7,
+        ("CS_ARCH_ARM64", "0"): 8,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 9,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 10,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 11,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 12,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 13,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 14,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 14,
+        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 15,
+        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 16,
+        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 17,
+        ("CS_ARCH_SYSZ", "0"): 18,
+        ("CS_ARCH_XCORE", "0"): 19,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 20,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 21,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 22,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 23,
+        ("CS_ARCH_M68K", "0"): 24,
+        ("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 25,
+        ("CS_ARCH_EVM", "0"): 26,
+        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC"): 30,
+        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED"): 31,
+        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC"): 32,
+        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 33,
+        ("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 45,
+        ("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 46,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_110"): 47,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_120"): 48,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_130"): 49,
diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py
index 88de76d08..3780233f6 100755
--- a/suite/test_corpus3.py
+++ b/suite/test_corpus3.py
@@ -57,6 +57,7 @@ def test_file(fname):
         "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM + CS_MODE_V8,
         "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB + CS_MODE_V8,
         "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB + CS_MODE_MCLASS,
+        "CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS,
         "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
         "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
         "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64 + CS_MODE_LITTLE_ENDIAN,
@@ -88,32 +89,33 @@ def test_file(fname):
         ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): 4,
         ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): 5,
         ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): 6,
-        ("CS_ARCH_ARM64", "0"): 7,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 8,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 9,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 10,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 11,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 12,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 13,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 13,
-        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 14,
-        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 15,
-        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 16,
-        ("CS_ARCH_SYSZ", "0"): 17,
-        ("CS_ARCH_XCORE", "0"): 18,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 19,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 20,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 21,
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 22,
-        ("CS_ARCH_M68K", "0"): 23,
-        ("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 24,
-        ("CS_ARCH_EVM", "0"): 25,
-        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC"): 29,
-        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED"): 30,
-        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC"): 31,
-        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 32,
-        ("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 44,
-        ("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 45,
+        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS"): 7,
+        ("CS_ARCH_ARM64", "0"): 8,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 9,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 10,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 11,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 12,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 13,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 14,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 14,
+        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 15,
+        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 16,
+        ("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 17,
+        ("CS_ARCH_SYSZ", "0"): 18,
+        ("CS_ARCH_XCORE", "0"): 19,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 20,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 21,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 22,
+        ("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 23,
+        ("CS_ARCH_M68K", "0"): 24,
+        ("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 25,
+        ("CS_ARCH_EVM", "0"): 26,
+        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC"): 30,
+        ("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED"): 31,
+        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC"): 32,
+        ("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 33,
+        ("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 45,
+        ("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 46,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_110"): 47,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_120"): 48,
         ("CS_ARCH_TRICORE", "CS_MODE_TRICORE_130"): 49,
diff --git a/tests/cs_details/README.md b/tests/cs_details/README.md
new file mode 100644
index 000000000..16730b34b
--- /dev/null
+++ b/tests/cs_details/README.md
@@ -0,0 +1,4 @@
+## Test instruction details
+
+This directory contains test cases for the `cs_detail` struct.
+Test files are consumed by the `cstest` tool (see: `suite/cstest`).
diff --git a/tests/cs_details/issue.cs b/tests/cs_details/issue.cs
new file mode 100644
index 000000000..5beb0be8d
--- /dev/null
+++ b/tests/cs_details/issue.cs
@@ -0,0 +1,206 @@
+!# issue 0 ARM operand groups 0x90,0xe8,0x0e,0x00 == ldm.w r0, {r1, r2, r3} ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x90,0xe8,0x0e,0x00 == ldm.w r0, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Registers read: r0 ; Registers modified: r1 r2 r3 ; Groups: IsThumb2
+
+!# issue 0 ARM operand groups 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x0e,0xc8 == ldm r0!, {r1, r2, r3}  ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsThumb
+
+!# issue 0 ARM operand groups 0x00,0x2a,0xf7,0xee == vmov.f32 s5, #1.000000e+00 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x00,0x2a,0xf7,0xee == vmov.f32 s5, #1.000000e+00 ; op_count: 2 ; operands[0].type: REG = s5 ; operands[0].access: WRITE ; operands[1].type: FP = 1.000000 ; Registers modified: s5 ; Groups: HasVFP3
+
+!# issue 0 ARM operand groups 0x0f,0x00,0x71,0xe3 == cmn r1, #15 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x0f,0x00,0x71,0xe3 == cmn r1, #0xf ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: READ ; operands[1].type: IMM = 0xf ; operands[1].access: READ ; Update-flags: True ; Registers read: r1 ; Registers modified: cpsr ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0x03,0x20,0xb0,0xe1 == movs r2, r3 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x03,0x20,0xb0,0xe1 == movs r2, r3 ;  op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r3 ; operands[1].access: READ ; Update-flags: True ; Registers read: r3 ; Registers modified: cpsr r2 ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0xfd,0x8f == ldrh r5, [r7, #62] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xfd,0x8f == ldrh r5, [r7, #0x3e] ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r7 ; operands[1].mem.disp: 0x3e ; operands[1].access: READ ; Registers read: r7 ; Registers modified: r5 ; Groups: IsThumb
+
+!# issue 0 ARM operand groups 0x61,0xb6 == cpsie f ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x61,0xb6 == cpsie f ; CPSI-mode: 2 ; CPSI-flag: 1 ; Groups: IsThumb
+
+!# issue 0 ARM operand groups 0x18,0xf8,0x03,0x1e == ldrbt r1, [r8, #3] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x18,0xf8,0x03,0x1e == ldrbt r1, [r8, #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r8 ; operands[1].mem.disp: 0x3 ; operands[1].access: READ ; Registers read: r8 ; Registers modified: r1 ; Groups: IsThumb2
+
+!# issue 0 ARM operand groups 0xb0,0xf8,0x01,0xf1 == pldw [r0, #257] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xb0,0xf8,0x01,0xf1 == pldw [r0, #0x101] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.disp: 0x101 ; operands[0].access: READ ; Registers read: r0 ; Groups: IsThumb2 HasV7 HasMP
+
+!# issue 0 ARM operand groups 0xd3,0xe8,0x08,0xf0 == tbb [r3, r8] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xd3,0xe8,0x08,0xf0 == tbb [r3, r8] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r3 ; operands[0].mem.index: REG = r8 ; operands[0].mem.scale: 0 ; operands[0].access: READ ; Registers read: r3 r8 ; Groups: jump IsThumb2
+
+!# issue 0 ARM operand groups 0xd3,0xe8,0x18,0xf0 == tbh [r3, r8, lsl #1] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xd3,0xe8,0x18,0xf0 == tbh [r3, r8, lsl #1] ;  op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r3 ; operands[0].mem.index: REG = r8 ; operands[0].mem.scale: 0 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r3 r8 ; Groups: jump IsThumb2
+
+!# issue 0 ARM operand groups 0xaf,0xf3,0x43,0x85 == cpsie i, #3 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xaf,0xf3,0x43,0x85 == cpsie i, #3 ; cpsie i, #3 ; op_count: 1 ; operands[0].type: IMM = 0x3 ; operands[0].access: READ ; CPSI-mode: 2 ; CPSI-flag: 2 ; Groups: IsThumb2 IsNotMClass
+
+!# issue 0 ARM operand groups 0xbf,0xf3,0x6f,0x8f == isb sy ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xbf,0xf3,0x6f,0x8f == isb sy ; isb sy ; Memory-barrier: 15 ; Groups: IsThumb HasDB
+
+!# issue 0 ARM operand groups 0x59,0xea,0x7b,0x89 == csel r9, r9, r11, vc ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
+0x59,0xea,0x7b,0x89 == csel r9, r9, r11, vc ; op_count: 3 ; operands[0].type: REG = r9 ; operands[0].access: WRITE ; operands[1].type: REG = r9 ; operands[1].access: READ ; operands[2].type: REG = r11 ; operands[2].access: READ ; Code condition: 7 ; Registers read: cpsr r9 r11 ; Registers modified: r9 ; Groups: HasV8_1MMainline
+
+!# issue 0 ARM operand groups 0xbf,0xf3,0x56,0x8f == dmb nshst ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xbf,0xf3,0x56,0x8f == dmb nshst ; dmb nshst ; Memory-barrier: 6 ; Groups: IsThumb HasDB
+
+!# issue 0 ARM operand groups 0x31,0xfa,0x02,0xf2 == lsrs.w r2, r1, r2 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x31,0xfa,0x02,0xf2 == lsrs.w r2, r1, r2 ;  op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; operands[2].type: REG = r2 ; operands[2].access: READ ; Update-flags: True ; Registers read: r1 r2 ; Registers modified: cpsr r2 ; Groups: IsThumb2
+
+!# issue 0 ARM operand groups 0x5f,0xf0,0x0c,0x01 == movseq.w r1, #12 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x08,0xbf == it eq ; Code condition: 0 ; Predicate Mask: 0x1 ; Registers modified: itstate ; Groups: IsThumb2
+0x5f,0xf0,0x0c,0x01 == movseq.w r1, #0xc ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: IMM = 0xc ; operands[1].access: READ ; Code condition: 0 ; Update-flags: True ; Registers modified: cpsr r1 ; Groups: IsThumb2
+
+!# issue 0 ARM operand groups 0x52,0xe8,0x01,0x1f == ldrex r1, [r2, #4] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x52,0xe8,0x01,0x1f == ldrex r1, [r2, #4] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.disp: 0x4 ; operands[1].access: READ ; Registers read: r2 ; Registers modified: r1 ; Groups: IsThumb HasV8MBaseline
+
+!# issue 0 ARM operand groups 0xdf,0xec,0x1d,0x1a == vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
+0x88,0xbf == it hi ; Code condition: 8 ; Predicate Mask: 0x1 ; Groups: IsThumb2
+0xdf,0xec,0x1d,0x1a == vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} ; op_count: 30 ; operands[0].type: REG = s3 ; operands[0].access: WRITE ; operands[1].type: REG = s4 ; operands[1].access: WRITE ; operands[2].type: REG = s5 ; operands[2].access: WRITE ; operands[3].type: REG = s6 ; operands[3].access: WRITE ; operands[4].type: REG = s7 ; operands[4].access: WRITE ; operands[5].type: REG = s8 ; operands[5].access: WRITE ; operands[6].type: REG = s9 ; operands[6].access: WRITE ; operands[7].type: REG = s10 ; operands[7].access: WRITE ; operands[8].type: REG = s11 ; operands[8].access: WRITE ; operands[9].type: REG = s12 ; operands[9].access: WRITE ; operands[10].type: REG = s13 ; operands[10].access: WRITE ; operands[11].type: REG = s14 ; operands[11].access: WRITE ; operands[12].type: REG = s15 ; operands[12].access: WRITE ; operands[13].type: REG = s16 ; operands[13].access: WRITE ; operands[14].type: REG = s17 ; operands[14].access: WRITE ; operands[15].type: REG = s18 ; operands[15].access: WRITE ; operands[16].type: REG = s19 ; operands[16].access: WRITE ; operands[17].type: REG = s20 ; operands[17].access: WRITE ; operands[18].type: REG = s21 ; operands[18].access: WRITE ; operands[19].type: REG = s22 ; operands[19].access: WRITE ; operands[20].type: REG = s23 ; operands[20].access: WRITE ; operands[21].type: REG = s24 ; operands[21].access: WRITE ; operands[22].type: REG = s25 ; operands[22].access: WRITE ; operands[23].type: REG = s26 ; operands[23].access: WRITE ; operands[24].type: REG = s27 ; operands[24].access: WRITE ; operands[25].type: REG = s28 ; operands[25].access: WRITE ; operands[26].type: REG = s29 ; operands[26].access: WRITE ; operands[27].type: REG = s30 ; operands[27].access: WRITE ; operands[28].type: REG = s31 ; operands[28].access: WRITE ; operands[29].type: REG = vpr ; operands[29].access: WRITE ; Code condition: 8 ; Registers modified: s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 vpr ; Groups: HasV8_1MMainline Has8MSecExt
+
+!# issue 0 ARM operand groups 0x9f,0xec,0x06,0x5b == vscclrm {d5, d6, d7, vpr} ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
+0x9f,0xec,0x06,0x5b == vscclrm {d5, d6, d7, vpr} ; op_count: 4 ; operands[0].type: REG = d5 ; operands[0].access: WRITE ; operands[1].type: REG = d6 ; operands[1].access: WRITE ; operands[2].type: REG = d7 ; operands[2].access: WRITE ; operands[3].type: REG = vpr ; operands[3].access: WRITE ; Registers modified: d5 d6 d7 vpr ; Groups: HasV8_1MMainline Has8MSecExt
+
+!# issue 0 ARM operand groups 0xbc,0xfd,0x7f,0xaf == vldrh.u32 q5, [r4, #254]! ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_MCLASS, CS_OPT_DETAIL
+0xbc,0xfd,0x7f,0xaf == vldrh.u32 q5, [r4, #0xfe]! ; op_count: 2 ; operands[0].type: REG = q5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r4 ; operands[1].mem.disp: 0xfe ; operands[1].access: READ ; Write-back: True ; Registers read: r4 ; Registers modified: r4 q5 ; Groups: HasMVEInt
+
+!# issue 0 ARM operand groups 0x80,0xfc,0x80,0x1e == vst20.16 {q0, q1}, [r0] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
+0x80,0xfc,0x80,0x1e == vst20.16 {q0, q1}, [r0] ; op_count: 3 ; operands[0].type: REG = q0 ; operands[0].access: READ ; operands[1].type: REG = q1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].mem.scale: 0 ; operands[2].access: WRITE ; Registers read: q0 q1 r0 ; Groups: HasMVEInt
+
+!# issue 0 ARM operand groups 0x98,0xfc,0x4e,0x08 == vcadd.f32 q0, q4, q7, #90 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
+0x98,0xfc,0x4e,0x08 == vcadd.f32 q0, q4, q7, #90 ; op_count: 4 ; operands[0].type: REG = q0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = q4 ; operands[1].access: READ ; operands[2].type: REG = q7 ; operands[2].access: READ ; operands[3].type: IMM = 0x5a ; operands[3].access: READ ; Registers read: q0 q4 q7 ; Registers modified: q0 ; Groups: HasMVEFloat
+
+!# issue 0 ARM operand groups 0x94,0xfd,0x46,0x48 == vcadd.f32 q2, q2, q3, #270 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
+0x94,0xfd,0x46,0x48 == vcadd.f32 q2, q2, q3, #270 ; op_count: 4 ; operands[0].type: REG = q2 ; operands[0].access: WRITE ; operands[1].type: REG = q2 ; operands[1].access: READ ; operands[2].type: REG = q3 ; operands[2].access: READ ; operands[3].type: IMM = 0x10e ; operands[3].access: READ ; Registers read: q2 q3 ; Registers modified: q2 ; Groups: HasNEON HasV8_3a
+
+!# issue 0 ARM operand groups 0x9d,0xec,0x82,0x6e == vldrb.s16 q3, [sp, q1] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
+0x9d,0xec,0x82,0x6e == vldrb.s16 q3, [sp, q1] ; op_count: 2 ; operands[0].type: REG = q3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r13 ; operands[1].mem.index: REG = q1 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Registers read: r13 q1 ; Registers modified: q3 ; Groups: HasMVEInt
+
+!# issue 0 ARM operand groups 0x90,0xec,0x12,0x6f == vldrh.s32 q3, [r0, q1] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
+0x90,0xec,0x12,0x6f == vldrh.s32 q3, [r0, q1] ; op_count: 2 ; operands[0].type: REG = q3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].mem.index: REG = q1 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Registers read: r0 q1 ; Registers modified: q3 ; Groups: HasMVEInt
+
+!# issue 0 ARM operand groups 0x5f,0xea,0x2d,0x83 == sqrshrl lr, r3, #64, r8 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_MCLASS, CS_OPT_DETAIL
+0x5f,0xea,0x2d,0x83 == sqrshrl lr, r3, #0x40, r8 ; op_count: 4 ; operands[0].type: REG = r14 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r3 ; operands[1].access: READ | WRITE ; operands[2].type: IMM = 0x40 ; operands[2].access: READ ; operands[3].type: REG = r8 ; operands[3].access: READ ; Write-back: True ; Registers read: r14 r3 r8 ; Registers modified: r14 r3 ; Groups: HasV8_1MMainline HasMVEInt
+
+!# issue 0 ARM operand groups 0x82,0xfd,0x21,0xff == vstrd.64 q7, [q1, #264] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
+0x82,0xfd,0x21,0xff == vstrd.64 q7, [q1, #0x108] ; op_count: 2 ; operands[0].type: REG = q7 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = q1 ; operands[1].mem.disp: 0x108 ; operands[1].access: WRITE ; Registers read: q7 q1 ; Groups: HasMVEInt
+
+!# issue 0 ARM operand groups 0x06,0x16,0x72,0xe6 == ldrbt r1, [r2], -r6, lsl #12 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x06,0x16,0x72,0xe6 == ldrbt r1, [r2], -r6, lsl #0xc ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r6 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Shift: 2 = 12 ; Subtracted: True ; Write-back: True ; Registers read: r2 r6 ; Registers modified: r2 r1 ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0xf6,0x50,0x33,0xe1 == ldrsh r5, [r3, -r6]! ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0xf6,0x50,0x33,0xe1 == ldrsh r5, [r3, -r6]! ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r3 ; operands[1].mem.index: REG = r6 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Subtracted: True ; Write-back: True ; Registers read: r3 r6 ; Registers modified: r3 r5 ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0x1e,0x19,0x7a,0xfd == ldc2l p9, c1, [r10, #-120]! ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x1e,0x19,0x7a,0xfd == ldc2l p9, c1, [r10, #-0x78]! ; op_count: 3 ; operands[0].type: P-IMM = 9 ; operands[0].access: READ ; operands[1].type: C-IMM = 1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r10 ; operands[2].mem.disp: 0xffffff88 ; operands[2].access: READ ; Registers read: r10 ; Registers modified: r10 ; Groups: IsARM PreV8
+
+!# issue 0 ARM operand groups 0x12,0x31,0x7c,0xfc == ldc2l p1, c3, [r12], #-72 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x12,0x31,0x7c,0xfc == ldc2l p1, c3, [r12], #-0x48 ; op_count: 3 ; operands[0].type: P-IMM = 1 ; operands[0].access: READ ; operands[1].type: C-IMM = 3 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r12 ; operands[2].mem.scale: 0 ; operands[2].access: READ ; operands[2].mem.disp: 0x48 ; Subtracted: True ; Registers read: r12 ; Groups: IsARM PreV8
+
+!# issue 0 ARM operand groups 0xa4,0xf9,0x6d,0x0e == vld3.16 {d0[], d2[], d4[]}, [r4]! ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xa4,0xf9,0x6d,0x0e == vld3.16 {d0[], d2[], d4[]}, [r4]! ; op_count: 4 ; operands[0].type: REG = d0 ; operands[0].access: WRITE ; operands[1].type: REG = d2 ; operands[1].access: WRITE ; operands[2].type: REG = d4 ; operands[2].access: WRITE ; operands[3].type: MEM ; operands[3].mem.index: REG = r4 ; operands[3].mem.scale: 0 ; operands[3].access: READ ; Write-back: True ; Registers read: r4 ; Registers modified: r4 d0 d2 d4
+
+!# issue 0 ARM operand groups 0x0d,0x50,0x66,0xe4 == strbt r5, [r6], #-13 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x0d,0x50,0x66,0xe4 == strbt r5, [r6], #-0xd ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = r6 ; operands[1].mem.scale: 0 ; operands[1].access: WRITE ; operands[1].mem.disp: 0xd ; Subtracted: True ; Write-back: True ; Registers read: r5 r6 ; Registers modified: r6 ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0x00,0x10,0x4f,0xe2 == sub r1, pc, #0 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x00,0x10,0x4f,0xe2 == sub r1, pc, #0 ; op_count: 3 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: READ ; operands[2].type: IMM = 0x0 ; operands[2].access: READ ; Update-flags: True ; Registers read: r15 ; Registers modified: cpsr r1 ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0x9f,0x51,0xd3,0xe7 == bfc r5, #3, #17 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x9f,0x51,0xd3,0xe7 == bfc r5, #3, #0x11 ; op_count: 3 ; operands[0].type: REG = r5 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x3 ; operands[1].access: READ ; operands[2].type: IMM = 0x11 ; operands[2].access: READ ; Write-back: True ; Registers read: r5 ; Registers modified: r5 ; Groups: IsARM HasV6T2
+
+!# issue 0 ARM operand groups 0xd8,0xe8,0xff,0x67 == ldaexd r6, r7, [r8] ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xd8,0xe8,0xff,0x67 == ldaexd r6, r7, [r8] ; op_count: 3 ; operands[0].type: REG = r6 ; operands[0].access: WRITE ; operands[1].type: REG = r7 ; operands[1].access: WRITE ; operands[2].type: MEM ; operands[2].mem.base: REG = r8 ; operands[2].mem.scale: 0 ; operands[2].access: READ ; Registers read: r8 ; Registers modified: r6 r7 ; Groups: IsThumb HasAcquireRelease HasV7Clrex IsNotMClass
+
+!# issue 0 ARM operand groups 0x30,0x0f,0xa6,0xe6 == ssat16 r0, #7, r0 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x30,0x0f,0xa6,0xe6 == ssat16 r0, #7, r0 ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x7 ; operands[1].access: READ ; operands[2].type: REG = r0 ; operands[2].access: READ ; Registers read: r0 ; Registers modified: r0 ; Groups: IsARM HasV6
+
+!# issue 0 ARM operand groups 0x9a,0x8f,0xa0,0xe6 == ssat r8, #1, r10, lsl #31 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x9a,0x8f,0xa0,0xe6 == ssat r8, #1, r10, lsl #0x1f ; op_count: 3 ; operands[0].type: REG = r8 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x1 ; operands[1].access: READ ; operands[2].type: REG = r10 ; operands[2].access: READ ; Shift: 2 = 31 ; Registers read: r10 ; Registers modified: r8 ; Groups: IsARM HasV6
+
+!# issue 0 ARM operand groups 0x40,0x1b,0xf5,0xee == vcmp.f64 d17, #0 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x40,0x1b,0xf5,0xee == vcmp.f64 d17, #0 ; op_count: 1 ; operands[0].type: REG = d17 ; operands[0].access: READ ; Registers read: d17 ; Registers modified: fpscr_nzcv ; Groups: HasVFP2 HasDPVFP
+
+!# issue 0 ARM operand groups 0x05,0xf0,0x2f,0xe3 == msr CPSR_fsxc, #5 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x05,0xf0,0x2f,0xe3 == msr cpsr_fsxc, #5 ; op_count: 2 ; operands[0].type: SYSREG = 15 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x5 ; operands[1].access: READ ; Update-flags: True ; Registers modified: cpsr ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0xa4,0xf9,0xed,0x0b == vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xa4,0xf9,0xed,0x0b == vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:0x80]! ; op_count: 5 ; operands[0].type: REG = d0 ; operands[0].neon_lane = 1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = d2 ; operands[1].neon_lane = 1 ; operands[1].access: READ | WRITE ; operands[2].type: REG = d4 ; operands[2].neon_lane = 1 ; operands[2].access: READ | WRITE ; operands[3].type: REG = d6 ; operands[3].neon_lane = 1 ; operands[3].access: READ | WRITE ; operands[4].type: MEM ; operands[4].mem.index: REG = r4 ; operands[4].mem.scale: 0 ; operands[4].mem.disp: 0x80 ; operands[4].access: READ ; Write-back: True ; Registers read: d0 d2 d4 d6 r4 ; Registers modified: r4 d0 d2 d4 d6
+
+!# issue 0 ARM operand groups 0x42,0x03,0xb0,0xf3 == aesd.8 q0, q1 ;
+!# CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8, CS_OPT_DETAIL
+0x42,0x03,0xb0,0xf3 == aesd.8 q0, q1 ; op_count: 2 ; operands[0].type: REG = q0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = q1 ; operands[1].access: READ ; Write-back: True ; Registers read: q0 q1 ; Registers modified: q0 ; Groups: HasV8 HasAES
+
+!# issue 0 ARM operand groups 0x11,0x57,0x54,0xfc == mrrc2 p7, #1, r5, r4, c1 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x11,0x57,0x54,0xfc == mrrc2 p7, #1, r5, r4, c1 ; op_count: 5 ; operands[0].type: P-IMM = 7 ; operands[0].access: READ ; operands[1].type: IMM = 0x1 ; operands[1].access: READ ; operands[2].type: REG = r5 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: C-IMM = 1 ; operands[4].access: READ ; Registers modified: r5 r4 ; Groups: IsARM PreV8
+
+!# issue 0 ARM operand groups 0xd3,0x2f,0x82,0xe6 == pkhtb r2, r2, r3, asr #31 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0xd3,0x2f,0x82,0xe6 == pkhtb r2, r2, r3, asr #0x1f ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r2 ; operands[1].access: READ ; operands[2].type: REG = r3 ; operands[2].access: READ ; Shift: 1 = 31 ; Registers read: r2 r3 ; Registers modified: r2 ; Groups: IsARM HasV6
+
+!# issue 0 ARM operand groups 0x93,0x27,0x82,0xe6 == pkhbt r2, r2, r3, lsl #15 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x93,0x27,0x82,0xe6 == pkhbt r2, r2, r3, lsl #0xf ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r2 ; operands[1].access: READ ; operands[2].type: REG = r3 ; operands[2].access: READ ; Shift: 2 = 15 ; Registers read: r2 r3 ; Registers modified: r2 ; Groups: IsARM HasV6
+
+!# issue 0 ARM operand groups 0xb4,0x10,0xf0,0xe0 == ldrht r1, [r0], #4 ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0xb4,0x10,0xf0,0xe0 == ldrht r1, [r0], #4 ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; operands[1].mem.disp: 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0x2f,0xfa,0xa1,0xf3 == sxtb16 r3, r1, ror #16 ;
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0x2f,0xfa,0xa1,0xf3 == sxtb16 r3, r1, ror #0x10 ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; Shift: 4 = 16 ; Registers read: r1 ; Registers modified: r3 ; Groups: HasDSP IsThumb2
+
+!# issue 0 ARM operand groups 0x00,0x02,0x01,0xf1 == setend be ;
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0x00,0x02,0x01,0xf1 == setend be ; op_count: 1 ; operands[0].type: SETEND = be ; Groups: IsARM
+
+!# issue 0 ARM operand groups 0xd0,0xe8,0xaf,0x0f == lda r0, [r0]
+!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
+0xd0,0xe8,0xaf,0x0f == lda r0, [r0] ; op_count: 2 ; operands[0].type: REG = r0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Registers read: r0 ; Registers modified: r0 ; Groups: IsThumb HasAcquireRelease
+
+!# issue 0 ARM operand groups 0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #0x3ef]
+!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
+0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef] ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.disp: 0xfffffc11 ; operands[1].access: READ ; Code condition: 8 ; Registers read: r1 ; Registers modified: r15 ; Groups: IsARM
+
diff --git a/tests/test_arm.c b/tests/test_arm.c
index a5016fafb..6220ab39c 100644
--- a/tests/test_arm.c
+++ b/tests/test_arm.c
@@ -131,13 +131,13 @@ static void print_insn_detail(csh cs_handle, cs_insn *ins)
 			printf("\t\tSubtracted: True\n");
 	}
 
-	if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
+	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF)
 		printf("\tCode condition: %u\n", arm->cc);
 
 	if (arm->update_flags)
 		printf("\tUpdate-flags: True\n");
 
-	if (arm->writeback)
+	if (ins->detail->writeback)
 		printf("\tWrite-back: True\n");
 
 	if (arm->cps_mode)
@@ -157,6 +157,9 @@ static void print_insn_detail(csh cs_handle, cs_insn *ins)
 
 	if (arm->mem_barrier)
 		printf("\tMemory-barrier: %u\n", arm->mem_barrier);
+	
+	if (arm->pred_mask)
+		printf("\tPredicate Mask: 0x%x\n", arm->pred_mask);
 
 	// Print out all registers accessed by this instruction (either implicit or explicit)
 	if (!cs_regs_access(cs_handle, ins,
diff --git a/utils.c b/utils.c
index 2bcbd1eec..af9a39a63 100644
--- a/utils.c
+++ b/utils.c
@@ -81,37 +81,6 @@ bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id)
 	return false;
 }
 
-// binary search for encoding in IndexType array
-// return -1 if not found, or index if found
-unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding)
-{
-	// binary searching since the index is sorted in encoding order
-	size_t left, right, m;
-
-	right = size - 1;
-
-	if (encoding < index[0].encoding || encoding > index[right].encoding)
-		// not found
-		return -1;
-
-	left = 0;
-
-	while(left <= right) {
-		m = (left + right) / 2;
-		if (encoding == index[m].encoding) {
-			return m;
-		}
-
-		if (encoding < index[m].encoding)
-			right = m - 1;
-		else
-			left = m + 1;
-	}
-
-	// not found
-	return -1;
-}
-
 /// Reads 4 bytes in the endian order specified in MI->cs->mode.
 uint32_t readBytes32(MCInst *MI, const uint8_t *Bytes)
 {
diff --git a/utils.h b/utils.h
index 5076e00b1..1a6b5a77d 100644
--- a/utils.h
+++ b/utils.h
@@ -11,7 +11,6 @@
 #include "include/capstone/capstone.h"
 #endif
 #include "cs_priv.h"
-#include "Mapping.h"
 
 // threshold number, so above this number will be printed in hexa mode
 #define HEX_THRESHOLD 9
@@ -38,15 +37,6 @@ bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id);
 
 bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id);
 
-struct IndexType {
-	uint16_t encoding;
-	unsigned index;
-};
-
-// binary search for encoding in IndexType array
-// return -1 if not found, or index if found
-unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding);
-
 uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes);
 uint32_t readBytes32(MCInst *MI, const uint8_t *Bytes);