Architecture updater (auto-sync) - Updating ARM (#1949)

* Add auto-sync updater.

* Update Capstone core with auto-sync changes.

* Update ARM via auto-sync.

* Make changes to arch modules which are introduced by auto-sync.

* Update tests for ARM.

* Fix build warnings for make

* Remove meson.build

* Print shift amount in decimal

* Patch non LLVM register alias.

* Change type of immediate operand to unsiged (due to: #771)

* Replace all occurances of a register with its alias.

* Fix printing of signed imms

* Print rotate amount in decimal

* CHange imm type to int64_t to match LLVM imm type.

* Fix search for register names, by completing string first.

* Print ModImm operands always in decimal

* Use number format of previous capstone version.

* Correct implicit writes and update_flags according to SBit.

* Add missing test for RegImmShift

* Reverse incorrect comparision.

* Set shift information for move instructions.

* Set mem access for all memory operands

* Set subtracted flag if offset is negative.

* Add flag for post-index memory operands.

* Add detail op for BX_RET and MOVPCLR

* Use instruction post_index operand.

* Add VPOP and VPUSH as unique CS IDs.

* Add shifting info for MOVsr.

* Add TODOs.

* Add in LLVM hardcoded operands to detail.

* Move detail editing from InstPrinter to Mapping

* Formatting

* Add removed check.

* Add writeback register and constraints to RFEI instructions.

* Translate shift immediate

* Print negative immediates

* Remove duplicate invalid entry

* Add CS groups to instructions

* Fix write attriutes of stores.

* Add missing names of added instructions

* Fix LLVM bug

* Add more post_index flags

* http -> https

* Make generated functions static

* Remove tab prefix for alias instructions.

* Set ValidateMCOperand to NULL.

* Fix AddrMode3Operand operands

* Allow getting system and banked register name via API

* Add writeback to STC/LDC instructions.

* Fix (hopefully) last case where disp is negative and subtracted = true

* Remove accidentially introduced regressions

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "suite/auto-sync/vendor/tree-sitter-cpp"]
+	path = suite/auto-sync/vendor/tree-sitter-cpp
+	url = https://github.com/tree-sitter/tree-sitter-cpp.git

CMakeLists.txt

@@ -101,6 +101,7 @@ set(SOURCES_ENGINE
     Mapping.c
     MCInst.c
     MCInstrDesc.c
+    MCInstPrinter.c
     MCRegisterInfo.c
     SStream.c
     utils.c
@@ -115,6 +116,7 @@ set(HEADERS_ENGINE
     MCFixedLenDisassembler.h
     MCInst.h
     MCInstrDesc.h
+    MCInstPrinter.h
     MCRegisterInfo.h
     SStream.h
     utils.h
@@ -141,6 +143,7 @@ set(HEADERS_COMMON
     include/capstone/sh.h
     include/capstone/tricore.h
     include/capstone/platform.h
+    include/capstone/sh.h
 )
 
 set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
@@ -149,7 +152,9 @@ set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
 if(CAPSTONE_ARM_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_ARM)
     set(SOURCES_ARM
+        arch/ARM/ARMBaseInfo.c
         arch/ARM/ARMDisassembler.c
+        arch/ARM/ARMDisassemblerExtension.c
         arch/ARM/ARMInstPrinter.c
         arch/ARM/ARMMapping.c
         arch/ARM/ARMModule.c
@@ -157,20 +162,20 @@ if(CAPSTONE_ARM_SUPPORT)
     set(HEADERS_ARM
         arch/ARM/ARMAddressingModes.h
         arch/ARM/ARMBaseInfo.h
-        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMDisassemblerExtension.h
         arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMLinkage.h
         arch/ARM/ARMMapping.h
         arch/ARM/ARMGenAsmWriter.inc
         arch/ARM/ARMGenDisassemblerTables.inc
         arch/ARM/ARMGenInstrInfo.inc
         arch/ARM/ARMGenRegisterInfo.inc
         arch/ARM/ARMGenSubtargetInfo.inc
-        arch/ARM/ARMMappingInsn.inc
+        arch/ARM/ARMGenCSFeatureName.inc
-        arch/ARM/ARMMappingInsnOp.inc
+        arch/ARM/ARMGenCSMappingInsn.inc
-        arch/ARM/ARMGenRegisterName.inc
+        arch/ARM/ARMGenCSMappingInsnOp.inc
-        arch/ARM/ARMGenRegisterName_digit.inc
+        arch/ARM/ARMGenCSMappingInsnName.inc
         arch/ARM/ARMGenSystemRegister.inc
-        arch/ARM/ARMMappingInsnName.inc
     )
     set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
 endif()
@@ -696,6 +701,7 @@ if(CAPSTONE_INSTALL)
     include("GNUInstallDirs")
 
     install(FILES ${HEADERS_COMMON} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone)
+    install(FILES ${HEADERS_INC} DESTINATION ${CMAKE_INSTALL_INCLUDEDIR}/capstone/inc)
 
     configure_file(capstone.pc.in ${CMAKE_BINARY_DIR}/capstone.pc @ONLY)
     install(FILES ${CMAKE_BINARY_DIR}/capstone.pc DESTINATION ${CMAKE_INSTALL_LIBDIR}/pkgconfig)

HACK.TXT

@@ -61,10 +61,35 @@ Coding style
 - C code follows Linux kernel coding style, using tabs for indentation.
 - Python code uses 4 spaces for indentation.
 
+Updating an Architecture
+------------------------
+
+The update tool for Capstone is called `auto-sync` and can be found in `suite/auto-sync`.
+
+Not all architectures are supported yet.
+Run `suite/auto-sync/Update-Arch.sh -h` to get a list of currently supported architectures.
+
+The documentation how to update with `auto-sync` or refactor an architecture module
+can be found in [docs/AutoSync.md](docs/AutoSync.md).
+
+If a module does not support `auto-sync` yet, it is highly recommended to refactor it
+instead of attempting to update it manually.
+Refactoring will take less time and updates it during the procedure.
+
+The one exception is `x86`. In LLVM we use several emitter backends to generate C code.
+One of those LLVM backends (the `DecoderEmitter`) has two versions.
+One for `x86` and another for all the other architectures.
+Until now it was not worth it to refactoring this unique `x86` backend. So `x86` is not
+supported currently.
 
 Adding an architecture
 ----------------------
 
+If your architecture is supported in LLVM or one of its forks, you can use `auto-sync` to
+add the new module.
+
+<!-- TODO: Move this info to the auto-sync docs -->
+
 Obviously, you first need to write all the logic and put it in a new directory arch/newarch
 Then, you have to modify other files.
 (You can look for one architecture such as EVM in these files to get what you need to do)

MCInst.c

@@ -27,7 +27,6 @@ void MCInst_Init(MCInst *inst)
 	inst->size = 0;
 	inst->has_imm = false;
 	inst->op1_size = 0;
-	inst->writeback = false;
 	inst->ac_idx = 0;
 	inst->popcode_adjust = 0;
 	inst->assembly[0] = '\0';
@@ -268,3 +267,16 @@ bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum)
 	assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
 	return MI->tied_op_idx[OpNum] != -1;
 }
+
+/// Returns the value of the @MCInst operand at index @OpNum.
+uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
+{
+	assert(OpNum < MAX_MC_OPS);
+	MCOperand *op = MCInst_getOperand(MI, OpNum);
+	if (MCOperand_isReg(op))
+		return MCOperand_getReg(op);
+	else if (MCOperand_isImm(op))
+		return MCOperand_getImm(op);
+	else
+		assert(0 && "Operand type not handled in this getter.");
+}

MCInst.h

@@ -38,7 +38,6 @@ struct MCOperand {
 		kDFPImmediate, ///< Double-Floating-point immediate operand.
 		kExpr,	       ///< Relocatable immediate operand.
 		kInst	       ///< Sub-instruction operand.
-
 	} MachineOperandType;
 	unsigned char Kind;
 
@@ -162,4 +161,6 @@ bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum);
 
 bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum);
 
+uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum);
+
 #endif

MCInstPrinter.c

@@ -0,0 +1,227 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+#include "MCInstPrinter.h"
+#include "cs_priv.h"
+#include <capstone/platform.h>
+
+extern bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
+
+static bool testFeatureBits(const MCInst *MI, uint32_t Value)
+{
+	assert(MI && MI->csh);
+	switch (MI->csh->arch) {
+	default:
+		assert(0 && "Not implemented for current arch.");
+	case CS_ARCH_ARM:
+		return ARM_getFeatureBits(MI->csh->mode, Value);
+	}
+}
+
+static bool matchAliasCondition(MCInst *MI, const MCRegisterInfo *MRI,
+								unsigned *OpIdx, const AliasMatchingData *M,
+								const AliasPatternCond *C,
+								bool *OrPredicateResult)
+{
+	// Feature tests are special, they don't consume operands.
+	if (C->Kind == AliasPatternCond_K_Feature)
+		return testFeatureBits(MI, C->Value);
+	if (C->Kind == AliasPatternCond_K_NegFeature)
+		return !testFeatureBits(MI, C->Value);
+	// For feature tests where just one feature is required in a list, set the
+	// predicate result bit to whether the expression will return true, and only
+	// return the real result at the end of list marker.
+	if (C->Kind == AliasPatternCond_K_OrFeature) {
+		*OrPredicateResult |= testFeatureBits(MI, C->Value);
+		return true;
+	}
+	if (C->Kind == AliasPatternCond_K_OrNegFeature) {
+		*OrPredicateResult |= !(testFeatureBits(MI, C->Value));
+		return true;
+	}
+	if (C->Kind == AliasPatternCond_K_EndOrFeatures) {
+		bool Res = *OrPredicateResult;
+		*OrPredicateResult = false;
+		return Res;
+	}
+
+	// Get and consume an operand.
+	MCOperand *Opnd = MCInst_getOperand(MI, *OpIdx);
+	++(*OpIdx);
+
+	// Check the specific condition for the operand.
+	switch (C->Kind) {
+	case AliasPatternCond_K_Imm:
+		// Operand must be a specific immediate.
+		return MCOperand_isImm(Opnd) &&
+			   MCOperand_getImm(Opnd) == (int32_t)C->Value;
+	case AliasPatternCond_K_Reg:
+		// Operand must be a specific register.
+		return MCOperand_isReg(Opnd) && MCOperand_getReg(Opnd) == C->Value;
+	case AliasPatternCond_K_TiedReg:
+		// Operand must match the register of another operand.
+		return MCOperand_isReg(Opnd) &&
+			   MCOperand_getReg(Opnd) ==
+				   MCOperand_getReg(MCInst_getOperand(MI, C->Value));
+	case AliasPatternCond_K_RegClass:
+		// Operand must be a register in this class. Value is a register class
+		// id.
+		return MCOperand_isReg(Opnd) &&
+			   MCRegisterClass_contains(
+				   MCRegisterInfo_getRegClass(MRI, C->Value),
+				   MCOperand_getReg(Opnd));
+	case AliasPatternCond_K_Custom:
+		// Operand must match some custom criteria.
+		assert(M->ValidateMCOperand && "A custom validator should be set but isn't.");
+		return M->ValidateMCOperand(Opnd, C->Value);
+	case AliasPatternCond_K_Ignore:
+		// Operand can be anything.
+		return true;
+	case AliasPatternCond_K_Feature:
+	case AliasPatternCond_K_NegFeature:
+	case AliasPatternCond_K_OrFeature:
+	case AliasPatternCond_K_OrNegFeature:
+	case AliasPatternCond_K_EndOrFeatures:
+		assert(0 && "handled earlier");
+	}
+	assert(0 && "invalid kind");
+}
+
+/// Check if PatternsForOpcode is all zero.
+static inline bool validOpToPatter(const PatternsForOpcode *P)
+{
+	return !(P->Opcode == 0 && P->PatternStart == 0 && P->NumPatterns == 0);
+}
+
+const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M)
+{
+	// TODO Rewrite to C
+
+	// auto It = lower_bound(M.OpToPatterns, MI->getOpcode(),
+	//                       [](const PatternsForOpcode &L, unsigned Opcode) {
+	//                         return L.Opcode < Opcode;
+	//                       });
+	// if (It == M.OpToPatterns.end() || It->Opcode != MI->getOpcode())
+	//   return nullptr;
+
+	// Binary search by opcode. Return false if there are no aliases for this
+	// opcode.
+	unsigned MIOpcode = MI->Opcode;
+	size_t i = 0;
+	uint32_t PatternOpcode = M->OpToPatterns[i].Opcode;
+	while (PatternOpcode < MIOpcode && validOpToPatter(&M->OpToPatterns[i]))
+		PatternOpcode = M->OpToPatterns[++i].Opcode;
+	if (PatternOpcode != MI->Opcode || !validOpToPatter(&M->OpToPatterns[i]))
+		return NULL;
+
+	// // Try all patterns for this opcode.
+	uint32_t AsmStrOffset = ~0U;
+	const AliasPattern *Patterns = M->Patterns + M->OpToPatterns[i].PatternStart;
+	for (const AliasPattern *P = Patterns;
+		P != Patterns + M->OpToPatterns[i].NumPatterns; ++P) {
+		// Check operand count first.
+		if (MCInst_getNumOperands(MI) != P->NumOperands)
+			return NULL;
+
+		// Test all conditions for this pattern.
+		const AliasPatternCond *Conds = M->PatternConds + P->AliasCondStart;
+		unsigned OpIdx = 0;
+		bool OrPredicateResult = false;
+		bool allMatch = true;
+		for (const AliasPatternCond *C = Conds; C != Conds + P->NumConds; ++C) {
+			if (!matchAliasCondition(MI, MI->MRI, &OpIdx, M, C, &OrPredicateResult)) {
+				allMatch = false;
+				break;
+			}
+		}
+		if (allMatch) {
+			AsmStrOffset = P->AsmStrOffset;
+			break;
+		}
+	}
+	// If no alias matched, don't print an alias.
+	if (AsmStrOffset == ~0U)
+		return NULL;
+
+	// Go to offset AsmStrOffset and use the null terminated string there. The
+	// offset should point to the beginning of an alias string, so it should
+	// either be zero or be preceded by a null byte.
+	return M->AsmStrings + AsmStrOffset;
+}
+
+// TODO Add functionality to toggle the flag.
+bool getUseMarkup(void) { return false; }
+
+/// Utility functions to make adding mark ups simpler.
+const char *markup(const char *s)
+{
+	static const char *no_markup = "";
+	if (getUseMarkup())
+		return s;
+	else
+		return no_markup;
+}
+
+// binary search for encoding in IndexType array
+// return -1 if not found, or index if found
+unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding)
+{
+	// binary searching since the index is sorted in encoding order
+	size_t left, right, m;
+
+	right = size - 1;
+
+	if (encoding < index[0].encoding || encoding > index[right].encoding)
+		// not found
+		return -1;
+
+	left = 0;
+
+	while(left <= right) {
+		m = (left + right) / 2;
+		if (encoding == index[m].encoding) {
+			return m;
+		}
+
+		if (encoding < index[m].encoding)
+			right = m - 1;
+		else
+			left = m + 1;
+	}
+
+	// not found
+	return -1;
+}
+
+// binary search for encoding in IndexTypeStr array
+// return -1 if not found, or index if found
+unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name)
+{
+	// binary searching since the index is sorted in encoding order
+	size_t left, right, m;
+
+	right = size - 1;
+
+	size_t str_left_cmp = strcmp(name, index[0].name);
+	size_t str_right_cmp = strcmp(name, index[right].name);
+	if (str_left_cmp < 0 || str_right_cmp > 0)
+		// not found
+		return -1;
+
+	left = 0;
+
+	while(left <= right) {
+		m = (left + right) / 2;
+		if (strcmp(name, index[m].name) == 0) {
+			return m;
+		}
+
+		if (strcmp(name, index[m].name) < 0)
+			right = m - 1;
+		else
+			left = m + 1;
+	}
+
+	// not found
+	return -1;
+}

MCInstPrinter.h

@@ -0,0 +1,84 @@
+/* Capstone Disassembly Engine */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+#ifndef CS_MCINSTPRINTER_H
+#define CS_MCINSTPRINTER_H
+
+#include "MCInst.h"
+#include <assert.h>
+#include <capstone/platform.h>
+
+/// Returned by getMnemonic() of the AsmPrinters.
+typedef struct {
+	const char *first; // Menmonic
+	uint64_t second;   // Bits
+} MnemonicBitsInfo;
+
+/// Map from opcode to pattern list by binary search.
+typedef struct {
+	uint32_t Opcode;
+	uint16_t PatternStart;
+	uint16_t NumPatterns;
+} PatternsForOpcode;
+
+/// Data for each alias pattern. Includes feature bits, string, number of
+/// operands, and a variadic list of conditions to check.
+typedef struct {
+	uint32_t AsmStrOffset;
+	uint32_t AliasCondStart;
+	uint8_t NumOperands;
+	uint8_t NumConds;
+} AliasPattern;
+
+typedef enum {
+	AliasPatternCond_K_Feature,	   // Match only if a feature is enabled.
+	AliasPatternCond_K_NegFeature, // Match only if a feature is disabled.
+	AliasPatternCond_K_OrFeature,  // Match only if one of a set of features is
+								   // enabled.
+	AliasPatternCond_K_OrNegFeature,  // Match only if one of a set of features
+									 // is disabled.
+	AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features.
+	AliasPatternCond_K_Ignore,		  // Match any operand.
+	AliasPatternCond_K_Reg,			  // Match a specific register.
+	AliasPatternCond_K_TiedReg,		  // Match another already matched register.
+	AliasPatternCond_K_Imm,			  // Match a specific immediate.
+	AliasPatternCond_K_RegClass,	  // Match registers in a class.
+	AliasPatternCond_K_Custom,		  // Call custom matcher by index.
+} AliasPatternCond_CondKind;
+
+typedef struct {
+	AliasPatternCond_CondKind Kind;
+	uint32_t Value;
+} AliasPatternCond;
+
+typedef bool (*ValidateMCOperandFunc)(const MCOperand *MCOp, unsigned PredicateIndex);
+
+/// Tablegenerated data structures needed to match alias patterns.
+typedef struct {
+	const PatternsForOpcode *OpToPatterns;
+	const AliasPattern *Patterns;
+	const AliasPatternCond *PatternConds;
+	const char *AsmStrings;
+	const ValidateMCOperandFunc ValidateMCOperand;
+} AliasMatchingData;
+
+const char *matchAliasPatterns(MCInst *MI, const AliasMatchingData *M);
+bool getUseMarkup(void);
+const char *markup(const char *s);
+
+struct IndexType {
+	uint16_t encoding;
+	unsigned index;
+};
+
+struct IndexTypeStr {
+	const char *name;
+	unsigned index;
+};
+
+// binary search for encoding in IndexType array
+// return -1 if not found, or index if found
+unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding);
+unsigned int binsearch_IndexTypeStrEncoding(const struct IndexTypeStr *index, size_t size, const char *name);
+
+#endif // CS_MCINSTPRINTER_H

MCInstrDesc.h

@@ -91,9 +91,9 @@ typedef struct MCOperandInfo {
 	/// Information about the type of the operand.
 	uint8_t OperandType;
 
-	/// The lower 16 bits are used to specify which constraints are set.
+	/// The lower 3 bits are used to specify which constraints are set.
-	/// The higher 16 bits are used to specify the value of constraints (4 bits each).
+	/// The higher 13 bits are used to specify the value of constraints (4 bits each).
-	uint32_t Constraints;
+	uint16_t Constraints;
 	/// Currently no other information.
 } MCOperandInfo;
 

Makefile

@@ -326,7 +326,7 @@ endif
 
 
 LIBOBJ =
-LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/Mapping.o
+LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
 LIBOBJ += $(LIBOBJ_TRICORE)

Mapping.c

@@ -85,6 +85,30 @@ void map_add_implicit_write(MCInst *MI, uint32_t Reg)
 	}
 }
 
+/// Removes a register from the implicit write register list.
+void map_remove_implicit_write(MCInst *MI, uint32_t Reg)
+{
+	if (!MI->flat_insn->detail)
+		return;
+
+	uint16_t *regs_write = MI->flat_insn->detail->regs_write;
+	bool shorten_list = false;
+	for (int i = 0; i < MAX_IMPL_W_REGS; ++i) {
+		if (shorten_list) {
+			regs_write[i - 1] = regs_write[i];
+		}
+		if (i >= MI->flat_insn->detail->regs_write_count)
+			return;
+
+		if (regs_write[i] == Reg) {
+			MI->flat_insn->detail->regs_write_count--;
+			// The register should exist only once in the list.
+			assert(!shorten_list);
+			shorten_list = true;
+		}
+	}
+}
+
 /// Copies the implicit read registers of @imap to @MI->flat_insn.
 /// Already present registers will be preserved.
 void map_implicit_reads(MCInst *MI, const insn_map *imap)
@@ -135,6 +159,21 @@ void map_implicit_writes(MCInst *MI, const insn_map *imap)
 #endif // CAPSTONE_DIET
 }
 
+/// Adds a given group to @MI->flat_insn.
+void add_group(MCInst *MI, unsigned /* arch_group */ group) {
+#ifndef CAPSTONE_DIET
+	if (!MI->flat_insn->detail)
+		return;
+
+	cs_detail *detail = MI->flat_insn->detail;
+	if (detail->groups_count >= MAX_NUM_GROUPS) {
+		printf("ERROR: Too many groups defined.\n");
+		return;
+	}
+	detail->groups[detail->groups_count++] = group;
+#endif // CAPSTONE_DIET
+}
+
 /// Copies the groups from @imap to @MI->flat_insn.
 /// Already present groups will be preserved.
 void map_groups(MCInst *MI, const insn_map *imap)

Mapping.h

@@ -98,11 +98,14 @@ int name2id(const name_map *map, int max, const char *name);
 const char *id2name(const name_map *map, int max, const unsigned int id);
 
 void map_add_implicit_write(MCInst *MI, uint32_t Reg);
+void map_remove_implicit_write(MCInst *MI, uint32_t Reg);
 
 void map_implicit_reads(MCInst *MI, const insn_map *imap);
 
 void map_implicit_writes(MCInst *MI, const insn_map *imap);
 
+void add_group(MCInst *MI, unsigned /* arch_group */ group);
+
 void map_groups(MCInst *MI, const insn_map *imap);
 
 void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);

MathExtras.h

@@ -203,6 +203,18 @@ static inline unsigned CountTrailingZeros_32(uint32_t Value) {
 #endif
 }
 
+// Count trailing zeros as in:
+// https://graphics.stanford.edu/~seander/bithacks.html#ZerosOnRightParallel
+static inline unsigned CountTrailingZeros_8(uint8_t Value) {
+	uint8_t c = 8;
+	Value &= -((int8_t)Value);
+	if (Value) c--;
+	if (Value & 0x0F) c -= 4;
+	if (Value & 0x33) c -= 2;
+	if (Value & 0x55) c -= 1;
+	return c;
+}
+
 /// CountTrailingOnes_32 - this function performs the operation of
 /// counting the number of ones from the least significant bit to the first zero
 /// bit.  Ex. CountTrailingOnes_32(0x00FF00FF) == 8.

SStream.c

@@ -28,9 +28,14 @@ void SStream_Init(SStream *ss)
 	ss->buffer[0] = '\0';
 }
 
+/**
+ * Copy the string \p s to the buffer of \p ss and terminate it with a '\\0' byte.
+ */
 void SStream_concat0(SStream *ss, const char *s)
 {
 #ifndef CAPSTONE_DIET
+	if (s[0] == '\0')
+		return;
 	unsigned int len = (unsigned int) strlen(s);
 
 	memcpy(ss->buffer + ss->index, s, len);
@@ -39,15 +44,23 @@ void SStream_concat0(SStream *ss, const char *s)
 #endif
 }
 
+/**
+ * Copy the single char \p c to the buffer of \p ss.
+ */
 void SStream_concat1(SStream *ss, const char c)
 {
 #ifndef CAPSTONE_DIET
+	if (c == '\0')
+		return;
 	ss->buffer[ss->index] = c;
 	ss->index++;
 	ss->buffer[ss->index] = '\0';
 #endif
 }
 
+/**
+ * Copy all strings given to the buffer of \p ss according to formatting \p fmt.
+ */
 void SStream_concat(SStream *ss, const char *fmt, ...)
 {
 #ifndef CAPSTONE_DIET
@@ -179,3 +192,13 @@ void printUInt32(SStream *O, uint32_t val)
 	else
 		SStream_concat(O, "%u", val);
 }
+
+void printFloat(SStream *O, float val)
+{
+	SStream_concat(O, "%e", val);
+}
+
+void printFloatBang(SStream *O, float val)
+{
+	SStream_concat(O, "#%e", val);
+}

SStream.h

@@ -37,4 +37,8 @@ void printUInt32(SStream *O, uint32_t val);
 // print number in decimal mode
 void printInt32BangDec(SStream *O, int32_t val);
 
+void printFloat(SStream *O, float val);
+
+void printFloatBang(SStream *O, float val);
+
 #endif

arch/AArch64/AArch64BaseInfo.h

@@ -22,6 +22,8 @@
 
 #include <ctype.h>
 #include <string.h>
+
+#include "../../MCInstPrinter.h"
 #include "AArch64Mapping.h"
 
 #ifndef __cplusplus
@@ -541,45 +543,6 @@ void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result);
 // These are required for the updated printAliasInstr() function in
 // $ARCHGenAsmWriter.inc
 
-/// Map from opcode to pattern list by binary search.
-typedef struct PatternsForOpcode {
-  uint32_t Opcode;
-  uint16_t PatternStart;
-  uint16_t NumPatterns;
-} PatternsForOpcode;
-
-/// Data for each alias pattern. Includes feature bits, string, number of
-/// operands, and a variadic list of conditions to check.
-typedef struct AliasPattern {
-  uint32_t AsmStrOffset;
-  uint32_t AliasCondStart;
-  uint8_t NumOperands;
-  uint8_t NumConds;
-} AliasPattern;
-
-enum CondKind {
-  AliasPatternCond_K_Feature,	      // Match only if a feature is enabled.
-  AliasPatternCond_K_NegFeature,    // Match only if a feature is disabled.
-  AliasPatternCond_K_OrFeature,	    // Match only if one of a set of features is
-				                            // enabled.
-  AliasPatternCond_K_OrNegFeature,  // Match only if one of a set of features is
-				                            // disabled.
-  AliasPatternCond_K_EndOrFeatures, // Note end of list of K_Or(Neg)?Features.
-  AliasPatternCond_K_Ignore,	      // Match any operand.
-  AliasPatternCond_K_Reg,	          // Match a specific register.
-  AliasPatternCond_K_TiedReg,	      // Match another already matched register.
-  AliasPatternCond_K_Imm,	          // Match a specific immediate.
-  AliasPatternCond_K_RegClass,	    // Match registers in a class.
-  AliasPatternCond_K_Custom,	      // Call custom matcher by index.
-};
-
-typedef struct AliasPatternCond {
-  int Kind;
-  uint32_t Value;
-} AliasPatternCond;
-
-// ---------------------------------------------------------------------------
-
 #include "AArch64GenSystemOperands_enum.inc"
 
 #endif

arch/AArch64/AArch64Mapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "AArch64Mapping.h"

arch/ARM/ARMAddressingModes.h

@@ -1,9 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
 //===-- ARMAddressingModes.h - ARM Addressing Modes -------------*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-//
+// See https://llvm.org/LICENSE.txt for license information.
-// This file is distributed under the University of Illinois Open Source
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -11,29 +24,32 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
+#ifndef CS_ARM_ADDRESSINGMODES_H
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+#define CS_ARM_ADDRESSINGMODES_H
 
-#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+#include <capstone/platform.h>
-#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
-#include "capstone/platform.h"
 #include "../../MathExtras.h"
+#include <assert.h>
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
 
 /// ARM_AM - ARM Addressing Mode Stuff
-typedef enum ARM_AM_ShiftOpc {
+typedef enum ShiftOpc {
 	ARM_AM_no_shift = 0,
 	ARM_AM_asr,
 	ARM_AM_lsl,
 	ARM_AM_lsr,
 	ARM_AM_ror,
-	ARM_AM_rrx
+	ARM_AM_rrx,
+	ARM_AM_uxtw
 } ARM_AM_ShiftOpc;
 
-typedef enum ARM_AM_AddrOpc {
+typedef enum AddrOpc { ARM_AM_sub = 0, ARM_AM_add } ARM_AM_AddrOpc;
-	ARM_AM_sub = 0,
-	ARM_AM_add
-} ARM_AM_AddrOpc;
 
 static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
 {
@@ -43,59 +59,77 @@ static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
 static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
 {
 	switch (Op) {
-		default: return "";	//llvm_unreachable("Unknown shift opc!");
+	default:
-		case ARM_AM_asr: return "asr";
+		assert(0 && "Unknown shift opc!");
-		case ARM_AM_lsl: return "lsl";
+	case ARM_AM_asr:
-		case ARM_AM_lsr: return "lsr";
+		return "asr";
-		case ARM_AM_ror: return "ror";
+	case ARM_AM_lsl:
-		case ARM_AM_rrx: return "rrx";
+		return "lsl";
+	case ARM_AM_lsr:
+		return "lsr";
+	case ARM_AM_ror:
+		return "ror";
+	case ARM_AM_rrx:
+		return "rrx";
+	case ARM_AM_uxtw:
+		return "uxtw";
 	}
 }
 
 static inline unsigned ARM_AM_getShiftOpcEncoding(ARM_AM_ShiftOpc Op)
 {
 	switch (Op) {
-		default: return (unsigned int)-1;	//llvm_unreachable("Unknown shift opc!");
+	default:
-		case ARM_AM_asr: return 2;
+		assert(0 && "Unknown shift opc!");
-		case ARM_AM_lsl: return 0;
+	case ARM_AM_asr:
-		case ARM_AM_lsr: return 1;
+		return 2;
-		case ARM_AM_ror: return 3;
+	case ARM_AM_lsl:
+		return 0;
+	case ARM_AM_lsr:
+		return 1;
+	case ARM_AM_ror:
+		return 3;
 	}
 }
 
-typedef enum ARM_AM_AMSubMode {
+typedef enum AMSubMode {
 	ARM_AM_bad_am_submode = 0,
 	ARM_AM_ia,
 	ARM_AM_ib,
 	ARM_AM_da,
 	ARM_AM_db
-} ARM_AM_AMSubMode;
+} ARM_AM_SubMode;
 
-static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_AMSubMode Mode)
+static inline const char *ARM_AM_getAMSubModeStr(ARM_AM_SubMode Mode)
 {
 	switch (Mode) {
-		default: return "";
+	default:
-		case ARM_AM_ia: return "ia";
+		assert(0 && "Unknown addressing sub-mode!");
-		case ARM_AM_ib: return "ib";
+	case ARM_AM_ia:
-		case ARM_AM_da: return "da";
+		return "ia";
-		case ARM_AM_db: return "db";
+	case ARM_AM_ib:
+		return "ib";
+	case ARM_AM_da:
+		return "da";
+	case ARM_AM_db:
+		return "db";
 	}
 }
 
 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.
 ///
-static inline unsigned rotr32(unsigned Val, unsigned Amt)
+static inline unsigned ARM_AM_rotr32(unsigned Val, unsigned Amt)
 {
-	//assert(Amt < 32 && "Invalid rotate amount");
+
-	return (Val >> Amt) | (Val << ((32-Amt)&31));
+	return (Val >> Amt) | (Val << ((32 - Amt) & 31));
 }
 
 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.
 ///
-static inline unsigned rotl32(unsigned Val, unsigned Amt)
+static inline unsigned ARM_AM_rotl32(unsigned Val, unsigned Amt)
 {
-	//assert(Amt < 32 && "Invalid rotate amount");
+
-	return (Val << Amt) | (Val >> ((32-Amt)&31));
+	return (Val << Amt) | (Val >> ((32 - Amt) & 31));
 }
 
 //===--------------------------------------------------------------------===//
@@ -112,15 +146,12 @@ static inline unsigned rotl32(unsigned Val, unsigned Amt)
 // reg, the second is the shift amount (or reg0 if not present or imm).  The
 // third operand encodes the shift opcode and the imm if a reg isn't present.
 //
-static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
+static inline unsigned ARM_AM_getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm)
 {
 	return ShOp | (Imm << 3);
 }
 
-static inline unsigned getSORegOffset(unsigned Op)
+static inline unsigned ARM_AM_getSORegOffset(unsigned Op) { return Op >> 3; }
-{
-	return Op >> 3;
-}
 
 static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
 {
@@ -129,14 +160,14 @@ static inline ARM_AM_ShiftOpc ARM_AM_getSORegShOp(unsigned Op)
 
 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
 /// the 8-bit imm value.
-static inline unsigned getSOImmValImm(unsigned Imm)
+static inline unsigned ARM_AM_getSOImmValImm(unsigned Imm)
 {
 	return Imm & 0xFF;
 }
 
 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
 /// the rotate amount.
-static inline unsigned getSOImmValRot(unsigned Imm)
+static inline unsigned ARM_AM_getSOImmValRot(unsigned Imm)
 {
 	return (Imm >> 8) * 2;
 }
@@ -145,99 +176,115 @@ static inline unsigned getSOImmValRot(unsigned Imm)
 /// computing the rotate amount to use.  If this immediate value cannot be
 /// handled with a single shifter-op, determine a good rotate amount that will
 /// take a maximal chunk of bits out of the immediate.
-static inline unsigned getSOImmValRotate(unsigned Imm)
+static inline unsigned ARM_AM_getSOImmValRotate(unsigned Imm)
 {
-	unsigned TZ, RotAmt;
 	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
 	// of zero.
-	if ((Imm & ~255U) == 0) return 0;
+	if ((Imm & ~255U) == 0)
+		return 0;
 
 	// Use CTZ to compute the rotate amount.
-	TZ = CountTrailingZeros_32(Imm);
+	unsigned TZ = CountTrailingZeros_32(Imm);
 
 	// Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
 	// not 9.
-	RotAmt = TZ & ~1;
+	unsigned RotAmt = TZ & ~1;
 
 	// If we can handle this spread, return it.
-	if ((rotr32(Imm, RotAmt) & ~255U) == 0)
+	if ((ARM_AM_rotr32(Imm, RotAmt) & ~255U) == 0)
-		return (32-RotAmt)&31;  // HW rotates right, not left.
+		return (32 - RotAmt) & 31; // HW rotates right, not left.
 
 	// For values like 0xF000000F, we should ignore the low 6 bits, then
 	// retry the hunt.
 	if (Imm & 63U) {
 		unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
 		unsigned RotAmt2 = TZ2 & ~1;
-		if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
+		if ((ARM_AM_rotr32(Imm, RotAmt2) & ~255U) == 0)
-			return (32-RotAmt2)&31;  // HW rotates right, not left.
+			return (32 - RotAmt2) & 31; // HW rotates right, not left.
 	}
 
 	// Otherwise, we have no way to cover this span of bits with a single
 	// shifter_op immediate.  Return a chunk of bits that will be useful to
 	// handle.
-	return (32-RotAmt)&31;  // HW rotates right, not left.
+	return (32 - RotAmt) & 31; // HW rotates right, not left.
 }
 
 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit
 /// into an shifter_operand immediate operand, return the 12-bit encoding for
 /// it.  If not, return -1.
-static inline int getSOImmVal(unsigned Arg)
+static inline int ARM_AM_getSOImmVal(unsigned Arg)
 {
-	unsigned RotAmt;
 	// 8-bit (or less) immediates are trivially shifter_operands with a rotate
 	// of zero.
-	if ((Arg & ~255U) == 0) return Arg;
+	if ((Arg & ~255U) == 0)
+		return Arg;
 
-	RotAmt = getSOImmValRotate(Arg);
+	unsigned RotAmt = ARM_AM_getSOImmValRotate(Arg);
 
 	// If this cannot be handled with a single shifter_op, bail out.
-	if (rotr32(~255U, RotAmt) & Arg)
+	if (ARM_AM_rotr32(~255U, RotAmt) & Arg)
 		return -1;
 
 	// Encode this correctly.
-	return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
+	return ARM_AM_rotl32(Arg, RotAmt) | ((RotAmt >> 1) << 8);
 }
 
 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
 /// or'ing together two SOImmVal's.
-static inline bool isSOImmTwoPartVal(unsigned V)
+static inline bool ARM_AM_isSOImmTwoPartVal(unsigned V)
 {
 	// If this can be handled with a single shifter_op, bail out.
-	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
 	if (V == 0)
 		return false;
 
 	// If this can be handled with two shifter_op's, accept.
-	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
 	return V == 0;
 }
 
 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal,
 /// return the first chunk of it.
-static inline unsigned getSOImmTwoPartFirst(unsigned V)
+static inline unsigned ARM_AM_getSOImmTwoPartFirst(unsigned V)
 {
-	return rotr32(255U, getSOImmValRotate(V)) & V;
+	return ARM_AM_rotr32(255U, ARM_AM_getSOImmValRotate(V)) & V;
 }
 
 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal,
 /// return the second chunk of it.
-static inline unsigned getSOImmTwoPartSecond(unsigned V)
+static inline unsigned ARM_AM_getSOImmTwoPartSecond(unsigned V)
 {
 	// Mask out the first hunk.
-	V = rotr32(~255U, getSOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(V)) & V;
 
 	// Take what's left.
-	//assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
+
 	return V;
 }
 
+/// isSOImmTwoPartValNeg - Return true if the specified value can be obtained
+/// by two SOImmVal, that -V = First + Second.
+/// "R+V" can be optimized to (sub (sub R, First), Second).
+/// "R=V" can be optimized to (sub (mvn R, ~(-First)), Second).
+static inline bool ARM_AM_isSOImmTwoPartValNeg(unsigned V)
+{
+	unsigned First;
+	if (!ARM_AM_isSOImmTwoPartVal(-V))
+		return false;
+	// Return false if ~(-First) is not a SoImmval.
+	First = ARM_AM_getSOImmTwoPartFirst(-V);
+	First = ~(-First);
+	return !(ARM_AM_rotr32(~255U, ARM_AM_getSOImmValRotate(First)) & First);
+}
+
 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
 /// by a left shift. Returns the shift amount to use.
-static inline unsigned getThumbImmValShift(unsigned Imm)
+static inline unsigned ARM_AM_getThumbImmValShift(unsigned Imm)
 {
 	// 8-bit (or less) immediates are trivially immediate operand with a shift
 	// of zero.
-	if ((Imm & ~255U) == 0) return 0;
+	if ((Imm & ~255U) == 0)
+		return 0;
 
 	// Use CTZ to compute the shift amount.
 	return CountTrailingZeros_32(Imm);
@@ -245,20 +292,21 @@ static inline unsigned getThumbImmValShift(unsigned Imm)
 
 /// isThumbImmShiftedVal - Return true if the specified value can be obtained
 /// by left shifting a 8-bit immediate.
-static inline bool isThumbImmShiftedVal(unsigned V)
+static inline bool ARM_AM_isThumbImmShiftedVal(unsigned V)
 {
 	// If this can be handled with
-	V = (~255U << getThumbImmValShift(V)) & V;
+	V = (~255U << ARM_AM_getThumbImmValShift(V)) & V;
 	return V == 0;
 }
 
 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
 /// by a left shift. Returns the shift amount to use.
-static inline unsigned getThumbImm16ValShift(unsigned Imm)
+static inline unsigned ARM_AM_getThumbImm16ValShift(unsigned Imm)
 {
 	// 16-bit (or less) immediates are trivially immediate operand with a shift
 	// of zero.
-	if ((Imm & ~65535U) == 0) return 0;
+	if ((Imm & ~65535U) == 0)
+		return 0;
 
 	// Use CTZ to compute the shift amount.
 	return CountTrailingZeros_32(Imm);
@@ -266,21 +314,20 @@ static inline unsigned getThumbImm16ValShift(unsigned Imm)
 
 /// isThumbImm16ShiftedVal - Return true if the specified value can be
 /// obtained by left shifting a 16-bit immediate.
-static inline bool isThumbImm16ShiftedVal(unsigned V)
+static inline bool ARM_AM_isThumbImm16ShiftedVal(unsigned V)
 {
 	// If this can be handled with
-	V = (~65535U << getThumbImm16ValShift(V)) & V;
+	V = (~65535U << ARM_AM_getThumbImm16ValShift(V)) & V;
 	return V == 0;
 }
 
 /// getThumbImmNonShiftedVal - If V is a value that satisfies
 /// isThumbImmShiftedVal, return the non-shiftd value.
-static inline unsigned getThumbImmNonShiftedVal(unsigned V)
+static inline unsigned ARM_AM_getThumbImmNonShiftedVal(unsigned V)
 {
-	return V >> getThumbImmValShift(V);
+	return V >> ARM_AM_getThumbImmValShift(V);
 }
 
-
 /// getT2SOImmValSplat - Return the 12-bit encoded representation
 /// if the specified value can be obtained by splatting the low 8 bits
 /// into every other byte or every byte of a 32-bit value. i.e.,
@@ -290,7 +337,7 @@ static inline unsigned getThumbImmNonShiftedVal(unsigned V)
 ///     abcdefgh abcdefgh abcdefgh abcdefgh    control = 3
 /// Return -1 if none of the above apply.
 /// See ARM Reference Manual A6.3.2.
-static inline int getT2SOImmValSplatVal(unsigned V)
+static inline int ARM_AM_getT2SOImmValSplatVal(unsigned V)
 {
 	unsigned u, Vs, Imm;
 	// control = 0
@@ -319,15 +366,15 @@ static inline int getT2SOImmValSplatVal(unsigned V)
 /// specified value is a rotated 8-bit value. Return -1 if no rotation
 /// encoding is possible.
 /// See ARM Reference Manual A6.3.2.
-static inline int getT2SOImmValRotateVal(unsigned V)
+static inline int ARM_AM_getT2SOImmValRotateVal(unsigned V)
 {
 	unsigned RotAmt = CountLeadingZeros_32(V);
 	if (RotAmt >= 24)
 		return -1;
 
 	// If 'Arg' can be handled with a single shifter_op return the value.
-	if ((rotr32(0xff000000U, RotAmt) & V) == V)
+	if ((ARM_AM_rotr32(0xff000000U, RotAmt) & V) == V)
-		return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
+		return (ARM_AM_rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
 
 	return -1;
 }
@@ -336,91 +383,87 @@ static inline int getT2SOImmValRotateVal(unsigned V)
 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
 /// encoding for it.  If not, return -1.
 /// See ARM Reference Manual A6.3.2.
-static inline int getT2SOImmVal(unsigned Arg)
+static inline int ARM_AM_getT2SOImmVal(unsigned Arg)
 {
-	int Rot;
 	// If 'Arg' is an 8-bit splat, then get the encoded value.
-	int Splat = getT2SOImmValSplatVal(Arg);
+	int Splat = ARM_AM_getT2SOImmValSplatVal(Arg);
 	if (Splat != -1)
 		return Splat;
 
 	// If 'Arg' can be handled with a single shifter_op return the value.
-	Rot = getT2SOImmValRotateVal(Arg);
+	int Rot = ARM_AM_getT2SOImmValRotateVal(Arg);
 	if (Rot != -1)
 		return Rot;
 
 	return -1;
 }
 
-static inline unsigned getT2SOImmValRotate(unsigned V)
+static inline unsigned ARM_AM_getT2SOImmValRotate(unsigned V)
 {
-	unsigned RotAmt;
-
 	if ((V & ~255U) == 0)
 		return 0;
-
 	// Use CTZ to compute the rotate amount.
-	RotAmt = CountTrailingZeros_32(V);
+	unsigned RotAmt = CountTrailingZeros_32(V);
 	return (32 - RotAmt) & 31;
 }
 
-static inline bool isT2SOImmTwoPartVal (unsigned Imm)
+static inline bool ARM_AM_isT2SOImmTwoPartVal(unsigned Imm)
 {
 	unsigned V = Imm;
 	// Passing values can be any combination of splat values and shifter
 	// values. If this can be handled with a single shifter or splat, bail
 	// out. Those should be handled directly, not with a two-part val.
-	if (getT2SOImmValSplatVal(V) != -1)
+	if (ARM_AM_getT2SOImmValSplatVal(V) != -1)
 		return false;
-	V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+	V = ARM_AM_rotr32(~255U, ARM_AM_getT2SOImmValRotate(V)) & V;
 	if (V == 0)
 		return false;
 
 	// If this can be handled as an immediate, accept.
-	if (getT2SOImmVal(V) != -1) return true;
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return true;
 
 	// Likewise, try masking out a splat value first.
 	V = Imm;
-	if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+	if (ARM_AM_getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
 		V &= ~0xff00ff00U;
-	else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+	else if (ARM_AM_getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
 		V &= ~0x00ff00ffU;
 	// If what's left can be handled as an immediate, accept.
-	if (getT2SOImmVal(V) != -1) return true;
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return true;
 
 	// Otherwise, do not accept.
 	return false;
 }
 
-static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm)
+static inline unsigned ARM_AM_getT2SOImmTwoPartFirst(unsigned Imm)
 {
-	//assert (isT2SOImmTwoPartVal(Imm) &&
+
-	//        "Immedate cannot be encoded as two part immediate!");
 	// Try a shifter operand as one part
-	unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
+	unsigned V = ARM_AM_rotr32(~255, ARM_AM_getT2SOImmValRotate(Imm)) & Imm;
 	// If the rest is encodable as an immediate, then return it.
-	if (getT2SOImmVal(V) != -1) return V;
+	if (ARM_AM_getT2SOImmVal(V) != -1)
+		return V;
 
 	// Try masking out a splat value first.
-	if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+	if (ARM_AM_getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
 		return Imm & 0xff00ff00U;
 
 	// The other splat is all that's left as an option.
-	//assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+
 	return Imm & 0x00ff00ffU;
 }
 
-static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
+static inline unsigned ARM_AM_getT2SOImmTwoPartSecond(unsigned Imm)
 {
 	// Mask out the first hunk
-	Imm ^= getT2SOImmTwoPartFirst(Imm);
+	Imm ^= ARM_AM_getT2SOImmTwoPartFirst(Imm);
 	// Return what's left
-	//assert (getT2SOImmVal(Imm) != -1 &&
+
-	//        "Unable to encode second part of T2 two part SO immediate");
 	return Imm;
 }
 
-
 //===--------------------------------------------------------------------===//
 // Addressing Mode #2
 //===--------------------------------------------------------------------===//
@@ -439,30 +482,30 @@ static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm)
 // and code rewriting), this operand will have the form:  FI#, reg0, <offs>
 // with no shift amount for the frame offset.
 //
-static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO,
+static inline unsigned ARM_AM_getAM2Opc(ARM_AM_AddrOpc Opc, unsigned Imm12,
-		unsigned IdxMode)
+										ARM_AM_ShiftOpc SO, unsigned IdxMode)
 {
-	//assert(Imm12 < (1 << 12) && "Imm too large!");
+
 	bool isSub = Opc == ARM_AM_sub;
-	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
+	return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16);
 }
 
-static inline unsigned getAM2Offset(unsigned AM2Opc)
+static inline unsigned ARM_AM_getAM2Offset(unsigned AM2Opc)
 {
-	return AM2Opc & ((1 << 12)-1);
+	return AM2Opc & ((1 << 12) - 1);
 }
 
-static inline ARM_AM_AddrOpc getAM2Op(unsigned AM2Opc)
+static inline ARM_AM_AddrOpc ARM_AM_getAM2Op(unsigned AM2Opc)
 {
 	return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
-static inline ARM_AM_ShiftOpc getAM2ShiftOpc(unsigned AM2Opc)
+static inline ARM_AM_ShiftOpc ARM_AM_getAM2ShiftOpc(unsigned AM2Opc)
 {
 	return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
 }
 
-static inline unsigned getAM2IdxMode(unsigned AM2Opc)
+static inline unsigned ARM_AM_getAM2IdxMode(unsigned AM2Opc)
 {
 	return (AM2Opc >> 16);
 }
@@ -480,26 +523,25 @@ static inline unsigned getAM2IdxMode(unsigned AM2Opc)
 // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
 // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
 // index mode.
-
 /// getAM3Opc - This function encodes the addrmode3 opc field.
-static inline unsigned getAM3Opc(ARM_AM_AddrOpc Opc, unsigned char Offset,
+static inline unsigned ARM_AM_getAM3Opc(ARM_AM_AddrOpc Opc,
-		unsigned IdxMode)
+										unsigned char Offset, unsigned IdxMode)
 {
 	bool isSub = Opc == ARM_AM_sub;
 	return ((int)isSub << 8) | Offset | (IdxMode << 9);
 }
 
-static inline unsigned char getAM3Offset(unsigned AM3Opc)
+static inline unsigned char ARM_AM_getAM3Offset(unsigned AM3Opc)
 {
 	return AM3Opc & 0xFF;
 }
 
-static inline ARM_AM_AddrOpc getAM3Op(unsigned AM3Opc)
+static inline ARM_AM_AddrOpc ARM_AM_getAM3Op(unsigned AM3Opc)
 {
 	return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
 
-static inline unsigned getAM3IdxMode(unsigned AM3Opc)
+static inline unsigned ARM_AM_getAM3IdxMode(unsigned AM3Opc)
 {
 	return (AM3Opc >> 9);
 }
@@ -518,13 +560,12 @@ static inline unsigned getAM3IdxMode(unsigned AM3Opc)
 //    DA - Decrement after
 //    DB - Decrement before
 // For VFP instructions, only the IA and DB modes are valid.
-
+static inline ARM_AM_SubMode ARM_AM_getAM4SubMode(unsigned Mode)
-static inline ARM_AM_AMSubMode getAM4SubMode(unsigned Mode)
 {
-	return (ARM_AM_AMSubMode)(Mode & 0x7);
+	return (ARM_AM_SubMode)(Mode & 0x7);
 }
 
-static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
+static inline unsigned ARM_AM_getAM4ModeImm(ARM_AM_SubMode SubMode)
 {
 	return (int)SubMode;
 }
@@ -538,18 +579,20 @@ static inline unsigned getAM4ModeImm(ARM_AM_AMSubMode SubMode)
 // addrmode5 := reg +/- imm8*4
 //
 // The first operand is always a Reg.  The second operand encodes the
-// operation in bit 8 and the immediate in bits 0-7.
+// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
-
 /// getAM5Opc - This function encodes the addrmode5 opc field.
-static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
+static inline unsigned ARM_AM_getAM5Opc(ARM_AM_AddrOpc Opc,
+										unsigned char Offset)
 {
 	bool isSub = Opc == ARM_AM_sub;
 	return ((int)isSub << 8) | Offset;
 }
+
 static inline unsigned char ARM_AM_getAM5Offset(unsigned AM5Opc)
 {
 	return AM5Opc & 0xFF;
 }
+
 static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
 {
 	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
@@ -565,20 +608,20 @@ static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
 //
 // The first operand is always a Reg.  The second operand encodes the
 // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
-
 /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
-static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
+static inline unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc,
+											unsigned char Offset)
 {
 	bool isSub = Opc == ARM_AM_sub;
 	return ((int)isSub << 8) | Offset;
 }
 
-static inline unsigned char getAM5FP16Offset(unsigned AM5Opc)
+static inline unsigned char ARM_AM_getAM5FP16Offset(unsigned AM5Opc)
 {
 	return AM5Opc & 0xFF;
 }
 
-static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc)
+static inline ARM_AM_AddrOpc ARM_AM_getAM5FP16Op(unsigned AM5Opc)
 {
 	return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
 }
@@ -595,41 +638,41 @@ static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc)
 // address register.  The second operand is the value of the alignment
 // specifier in bytes or zero if no explicit alignment.
 // Valid alignments depend on the specific instruction.
-
 //===--------------------------------------------------------------------===//
-// NEON Modified Immediates
+// NEON/MVE Modified Immediates
 //===--------------------------------------------------------------------===//
 //
-// Several NEON instructions (e.g., VMOV) take a "modified immediate"
+// Several NEON and MVE instructions (e.g., VMOV) take a "modified immediate"
 // vector operand, where a small immediate encoded in the instruction
 // specifies a full NEON vector value.  These modified immediates are
 // represented here as encoded integers.  The low 8 bits hold the immediate
 // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold
 // the "Cmode" field of the instruction.  The interfaces below treat the
 // Op and Cmode values as a single 5-bit value.
-
+static inline unsigned ARM_AM_createVMOVModImm(unsigned OpCmode, unsigned Val)
-static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val)
 {
 	return (OpCmode << 8) | Val;
 }
-static inline unsigned getNEONModImmOpCmode(unsigned ModImm)
+
+static inline unsigned ARM_AM_getVMOVModImmOpCmode(unsigned ModImm)
 {
 	return (ModImm >> 8) & 0x1f;
 }
-static inline unsigned getNEONModImmVal(unsigned ModImm)
+
+static inline unsigned ARM_AM_getVMOVModImmVal(unsigned ModImm)
 {
 	return ModImm & 0xff;
 }
 
-/// decodeNEONModImm - Decode a NEON modified immediate value into the
+/// decodeVMOVModImm - Decode a NEON/MVE modified immediate value into the
 /// element value and the element size in bits.  (If the element size is
 /// smaller than the vector, it is splatted into all the elements.)
-static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBits)
+static inline uint64_t ARM_AM_decodeVMOVModImm(unsigned ModImm,
+											   unsigned *EltBits)
 {
-	unsigned OpCmode = getNEONModImmOpCmode(ModImm);
+	unsigned OpCmode = ARM_AM_getVMOVModImmOpCmode(ModImm);
-	unsigned Imm8 = getNEONModImmVal(ModImm);
+	unsigned Imm8 = ARM_AM_getVMOVModImmVal(ModImm);
 	uint64_t Val = 0;
-	unsigned ByteNum;
 
 	if (OpCmode == 0xe) {
 		// 8-bit vector elements
@@ -637,62 +680,107 @@ static inline uint64_t ARM_AM_decodeNEONModImm(unsigned ModImm, unsigned *EltBit
 		*EltBits = 8;
 	} else if ((OpCmode & 0xc) == 0x8) {
 		// 16-bit vector elements
-		ByteNum = (OpCmode & 0x6) >> 1;
+		unsigned ByteNum = (OpCmode & 0x6) >> 1;
-		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		Val = Imm8 << (8 * ByteNum);
 		*EltBits = 16;
 	} else if ((OpCmode & 0x8) == 0) {
 		// 32-bit vector elements, zero with one byte set
-		ByteNum = (OpCmode & 0x6) >> 1;
+		unsigned ByteNum = (OpCmode & 0x6) >> 1;
-		Val = (uint64_t)Imm8 << (8 * ByteNum);
+		Val = Imm8 << (8 * ByteNum);
 		*EltBits = 32;
 	} else if ((OpCmode & 0xe) == 0xc) {
 		// 32-bit vector elements, one byte with low bits set
-		ByteNum = 1 + (OpCmode & 0x1);
+		unsigned ByteNum = 1 + (OpCmode & 0x1);
 		Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
 		*EltBits = 32;
 	} else if (OpCmode == 0x1e) {
 		// 64-bit vector elements
-		for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
+		for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) {
 			if ((ModImm >> ByteNum) & 1)
 				Val |= (uint64_t)0xff << (8 * ByteNum);
 		}
 		*EltBits = 64;
 	} else {
-		//llvm_unreachable("Unsupported NEON immediate");
+		assert(0 && "Unsupported VMOV immediate");
 	}
 	return Val;
 }
 
-ARM_AM_AMSubMode getLoadStoreMultipleSubMode(int Opcode);
+// Generic validation for single-byte immediate (0X00, 00X0, etc).
+static inline bool ARM_AM_isNEONBytesplat(unsigned Value, unsigned Size)
+{
+
+	unsigned count = 0;
+	for (unsigned i = 0; i < Size; ++i) {
+		if (Value & 0xff)
+			count++;
+		Value >>= 8;
+	}
+	return count == 1;
+}
+
+/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
+static inline bool ARM_AM_isNEONi16splat(unsigned Value)
+{
+	if (Value > 0xffff)
+		return false;
+	// i16 value with set bits only in one byte X0 or 0X.
+	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 2);
+}
+
+// Encode NEON 16 bits Splat immediate for instructions like VBIC/VORR
+static inline unsigned ARM_AM_encodeNEONi16splat(unsigned Value)
+{
+
+	if (Value >= 0x100)
+		Value = (Value >> 8) | 0xa00;
+	else
+		Value |= 0x800;
+	return Value;
+}
+
+/// Checks if Value is a correct immediate for instructions like VBIC/VORR.
+static inline bool ARM_AM_isNEONi32splat(unsigned Value)
+{
+	// i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
+	return Value == 0 || ARM_AM_isNEONBytesplat(Value, 4);
+}
+
+/// Encode NEON 32 bits Splat immediate for instructions like VBIC/VORR.
+static inline unsigned ARM_AM_encodeNEONi32splat(unsigned Value)
+{
+
+	if (Value >= 0x100 && Value <= 0xff00)
+		Value = (Value >> 8) | 0x200;
+	else if (Value > 0xffff && Value <= 0xff0000)
+		Value = (Value >> 16) | 0x400;
+	else if (Value > 0xffffff)
+		Value = (Value >> 24) | 0x600;
+	return Value;
+}
 
 //===--------------------------------------------------------------------===//
 // Floating-point Immediates
 //
-static inline float getFPImmFloat(unsigned Imm)
+static inline float ARM_AM_getFPImmFloat(unsigned Imm)
 {
 	// We expect an 8-bit binary encoding of a floating-point number here.
-	union {
-		uint32_t I;
-		float F;
-	} FPUnion;
 
 	uint8_t Sign = (Imm >> 7) & 0x1;
 	uint8_t Exp = (Imm >> 4) & 0x7;
 	uint8_t Mantissa = Imm & 0xf;
 
-	//   8-bit FP    iEEEE Float Encoding
+	//   8-bit FP    IEEE Float Encoding
 	//   abcd efgh   aBbbbbbc defgh000 00000000 00000000
 	//
 	// where B = NOT(b);
-
+	uint32_t I = 0;
-	FPUnion.I = 0;
+	I |= Sign << 31;
-	FPUnion.I |= ((uint32_t) Sign) << 31;
+	I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
-	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
+	I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
-	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
+	I |= (Exp & 0x3) << 23;
-	FPUnion.I |= (Exp & 0x3) << 23;
+	I |= Mantissa << 19;
-	FPUnion.I |= Mantissa << 19;
+	return BitsToFloat(I);
-	return FPUnion.F;
 }
 
-#endif
+#endif // CS_ARM_ADDRESSINGMODES_H
-

arch/ARM/ARMBaseInfo.c

@@ -0,0 +1,96 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides basic encoding and assembly information for ARM.
+//
+//===----------------------------------------------------------------------===//
+#include <capstone/platform.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "ARMBaseInfo.h"
+#include "ARMMapping.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+const char *get_pred_mask(ARM_PredBlockMask pred_mask)
+{
+	switch (pred_mask) {
+	default:
+		assert(0 && "pred_mask not handled.");
+	case ARM_T:
+		return "T";
+	case ARM_TT:
+		return "TT";
+	case ARM_TE:
+		return "TE";
+	case ARM_TTT:
+		return "TTT";
+	case ARM_TTE:
+		return "TTE";
+	case ARM_TEE:
+		return "TEE";
+	case ARM_TET:
+		return "TET";
+	case ARM_TTTT:
+		return "TTTT";
+	case ARM_TTTE:
+		return "TTTE";
+	case ARM_TTEE:
+		return "TTEE";
+	case ARM_TTET:
+		return "TTET";
+	case ARM_TEEE:
+		return "TEEE";
+	case ARM_TEET:
+		return "TEET";
+	case ARM_TETT:
+		return "TETT";
+	case ARM_TETE:
+		return "TETE";
+	}
+}
+
+#define GET_MCLASSSYSREG_IMPL
+#include "ARMGenSystemRegister.inc"
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
+}
+
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) | (SYSm & 0xFF));
+}
+
+// lookup system registers using 8-bit SYSm value
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
+{
+	return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) | (SYSm & 0xFF));
+}

arch/ARM/ARMBaseInfo.h

@@ -1,9 +1,8 @@
-//===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
+//===-- ARMBaseInfo.h - Top level definitions for ARM ---*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-//
+// See https://llvm.org/LICENSE.txt for license information.
-// This file is distributed under the University of Illinois Open Source
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -14,180 +13,239 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
+#ifndef CS_ARM_BASEINFO_H
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+#define CS_ARM_BASEINFO_H
 
-#ifndef CS_ARMBASEINFO_H
+#include <assert.h>
-#define CS_ARMBASEINFO_H
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
 
+#include "../../MCInstPrinter.h"
+#include "../../utils.h"
 #include "capstone/arm.h"
 
-// Defines symbolic names for ARM registers.  This defines a mapping from
+#define GET_INSTRINFO_ENUM
-// register name to register number.
+#include "ARMGenInstrInfo.inc"
-//
-#define GET_REGINFO_ENUM
-#include "ARMGenRegisterInfo.inc"
 
-// Enums corresponding to ARM condition codes
+// System Registers
-// The CondCodes constants map directly to the 4-bit encoding of the
+typedef struct MClassSysReg {
-// condition field for predicated instructions.
+	const char *Name;
-typedef enum ARMCC_CondCodes { // Meaning (integer)          Meaning (floating-point)
+	arm_sysop_reg sysreg;
-	ARMCC_EQ,            // Equal                      Equal
+	uint16_t M1Encoding12;
-	ARMCC_NE,            // Not equal                  Not equal, or unordered
+	uint16_t M2M3Encoding8;
-	ARMCC_HS,            // Carry set                  >, ==, or unordered
+	uint16_t Encoding;
-	ARMCC_LO,            // Carry clear                Less than
+	int FeaturesRequired[2];
-	ARMCC_MI,            // Minus, negative            Less than
+} ARMSysReg_MClassSysReg;
-	ARMCC_PL,            // Plus, positive or zero     >, ==, or unordered
-	ARMCC_VS,            // Overflow                   Unordered
-	ARMCC_VC,            // No overflow                Not unordered
-	ARMCC_HI,            // Unsigned higher            Greater than, or unordered
-	ARMCC_LS,            // Unsigned lower or same     Less than or equal
-	ARMCC_GE,            // Greater than or equal      Greater than or equal
-	ARMCC_LT,            // Less than                  Less than, or unordered
-	ARMCC_GT,            // Greater than               Greater than
-	ARMCC_LE,            // Less than or equal         <, ==, or unordered
-	ARMCC_AL             // Always (unconditional)     Always (unconditional)
-} ARMCC_CondCodes;
 
-inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
+// return true if FeaturesRequired are all present in ActiveFeatures
+static inline bool hasRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg, int ActiveFeatures)
 {
-	switch (CC) {
+	return (TheReg->FeaturesRequired[0] == ActiveFeatures ||
-		case ARMCC_EQ: return ARMCC_NE;
+			TheReg->FeaturesRequired[1] == ActiveFeatures);
-		case ARMCC_NE: return ARMCC_EQ;
-		case ARMCC_HS: return ARMCC_LO;
-		case ARMCC_LO: return ARMCC_HS;
-		case ARMCC_MI: return ARMCC_PL;
-		case ARMCC_PL: return ARMCC_MI;
-		case ARMCC_VS: return ARMCC_VC;
-		case ARMCC_VC: return ARMCC_VS;
-		case ARMCC_HI: return ARMCC_LS;
-		case ARMCC_LS: return ARMCC_HI;
-		case ARMCC_GE: return ARMCC_LT;
-		case ARMCC_LT: return ARMCC_GE;
-		case ARMCC_GT: return ARMCC_LE;
-		case ARMCC_LE: return ARMCC_GT;
-		default: return ARMCC_AL;
-	}
 }
 
-inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
+// returns true if TestFeatures are all present in FeaturesRequired
+static inline bool MClassSysReg_isInRequiredFeatures(const ARMSysReg_MClassSysReg *TheReg,
+													 int TestFeatures)
 {
-	switch (CC) {
+	return (TheReg->FeaturesRequired[0] == TestFeatures ||
-		case ARMCC_EQ:  return "eq";
+			TheReg->FeaturesRequired[1] == TestFeatures);
-		case ARMCC_NE:  return "ne";
-		case ARMCC_HS:  return "hs";
-		case ARMCC_LO:  return "lo";
-		case ARMCC_MI:  return "mi";
-		case ARMCC_PL:  return "pl";
-		case ARMCC_VS:  return "vs";
-		case ARMCC_VC:  return "vc";
-		case ARMCC_HI:  return "hi";
-		case ARMCC_LS:  return "ls";
-		case ARMCC_GE:  return "ge";
-		case ARMCC_LT:  return "lt";
-		case ARMCC_GT:  return "gt";
-		case ARMCC_LE:  return "le";
-		case ARMCC_AL:  return "al";
-		default: return "";
-	}
 }
 
+#define GET_SUBTARGETINFO_ENUM
+#include "ARMGenSubtargetInfo.inc"
+
+// lookup system register using 12-bit SYSm value.
+// Note: the search is uniqued using M1 mask
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm);
+// returns APSR with _<bits> qualifier.
+// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm);
+// lookup system registers using 8-bit SYSm value
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm);
+// end namespace ARMSysReg
+
+// Banked Registers
+typedef struct BankedReg {
+	const char *Name;
+	arm_sysop_reg sysreg;
+	uint16_t Encoding;
+} ARMBankedReg_BankedReg;
+
+#define GET_BANKEDREG_DECL
+#define GET_MCLASSSYSREG_DECL
+#include "ARMGenSystemRegister.inc"
+
+typedef enum IMod { ARM_PROC_IE = 2, ARM_PROC_ID = 3 } ARM_PROC_IMod;
+
+typedef enum IFlags {
+	ARM_PROC_F = 1,
+	ARM_PROC_I = 2,
+	ARM_PROC_A = 4
+} ARM_PROC_IFlags;
+
 inline static const char *ARM_PROC_IFlagsToString(unsigned val)
 {
 	switch (val) {
-		case ARM_CPSFLAG_F: return "f";
+	default:
-		case ARM_CPSFLAG_I: return "i";
+		// llvm_unreachable("Unknown iflags operand");
-		case ARM_CPSFLAG_A: return "a";
+	case ARM_PROC_F:
-		default: return "";
+		return "f";
+	case ARM_PROC_I:
+		return "i";
+	case ARM_PROC_A:
+		return "a";
 	}
 }
 
 inline static const char *ARM_PROC_IModToString(unsigned val)
 {
 	switch (val) {
-		case ARM_CPSMODE_IE: return "ie";
+	default:
-		case ARM_CPSMODE_ID: return "id";
+		// llvm_unreachable("Unknown imod operand");
-		default: return "";
+		assert(0);
+	case ARM_PROC_IE:
+		return "ie";
+	case ARM_PROC_ID:
+		return "id";
 	}
 }
 
 inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
 {
-	// TODO: add details
+	switch (val) {
-	switch (val + 1) {
+	default:
-		default: return "BUGBUG";
+		// llvm_unreachable("Unknown memory operation");
-		case ARM_MB_SY:    return "sy";
+		assert(0);
-		case ARM_MB_ST:    return "st";
+	case ARM_MB_SY:
-		case ARM_MB_LD: return HasV8 ? "ld" : "#0xd";
+		return "sy";
-		case ARM_MB_RESERVED_12: return "#0xc";
+	case ARM_MB_ST:
-		case ARM_MB_ISH:   return "ish";
+		return "st";
-		case ARM_MB_ISHST: return "ishst";
+	case ARM_MB_LD:
-		case ARM_MB_ISHLD: return HasV8 ?  "ishld" : "#9";
+		return HasV8 ? "ld" : "#0xd";
-		case ARM_MB_RESERVED_8: return "#8";
+	case ARM_MB_RESERVED_12:
-		case ARM_MB_NSH:   return "nsh";
+		return "#0xc";
-		case ARM_MB_NSHST: return "nshst";
+	case ARM_MB_ISH:
-		case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5";
+		return "ish";
-		case ARM_MB_RESERVED_4: return "#4";
+	case ARM_MB_ISHST:
-		case ARM_MB_OSH:   return "osh";
+		return "ishst";
-		case ARM_MB_OSHST: return "oshst";
+	case ARM_MB_ISHLD:
-		case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1";
+		return HasV8 ? "ishld" : "#0x9";
-		case ARM_MB_RESERVED_0: return "#0";
+	case ARM_MB_RESERVED_8:
+		return "#0x8";
+	case ARM_MB_NSH:
+		return "nsh";
+	case ARM_MB_NSHST:
+		return "nshst";
+	case ARM_MB_NSHLD:
+		return HasV8 ? "nshld" : "#0x5";
+	case ARM_MB_RESERVED_4:
+		return "#0x4";
+	case ARM_MB_OSH:
+		return "osh";
+	case ARM_MB_OSHST:
+		return "oshst";
+	case ARM_MB_OSHLD:
+		return HasV8 ? "oshld" : "#0x1";
+	case ARM_MB_RESERVED_0:
+		return "#0x0";
 	}
 }
 
-enum ARM_ISB_InstSyncBOpt {
+typedef enum TraceSyncBOpt { ARM_TSB_CSYNC = 0 } ARM_TSB_TraceSyncBOpt;
-    ARM_ISB_RESERVED_0 = 0,
+
-    ARM_ISB_RESERVED_1 = 1,
+inline static const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
-    ARM_ISB_RESERVED_2 = 2,
+{
-    ARM_ISB_RESERVED_3 = 3,
+	switch (val) {
-    ARM_ISB_RESERVED_4 = 4,
+	default:
-    ARM_ISB_RESERVED_5 = 5,
+		// llvm_unreachable("Unknown trace synchronization barrier operation");
-    ARM_ISB_RESERVED_6 = 6,
+		assert(0);
-    ARM_ISB_RESERVED_7 = 7,
+	case ARM_TSB_CSYNC:
-    ARM_ISB_RESERVED_8 = 8,
+		return "csync";
-    ARM_ISB_RESERVED_9 = 9,
+	}
-    ARM_ISB_RESERVED_10 = 10,
+}
-    ARM_ISB_RESERVED_11 = 11,
+
-    ARM_ISB_RESERVED_12 = 12,
+typedef enum InstSyncBOpt {
-    ARM_ISB_RESERVED_13 = 13,
+	ARM_ISB_RESERVED_0 = 0,
-    ARM_ISB_RESERVED_14 = 14,
+	ARM_ISB_RESERVED_1 = 1,
-    ARM_ISB_SY = 15
+	ARM_ISB_RESERVED_2 = 2,
-};
+	ARM_ISB_RESERVED_3 = 3,
+	ARM_ISB_RESERVED_4 = 4,
+	ARM_ISB_RESERVED_5 = 5,
+	ARM_ISB_RESERVED_6 = 6,
+	ARM_ISB_RESERVED_7 = 7,
+	ARM_ISB_RESERVED_8 = 8,
+	ARM_ISB_RESERVED_9 = 9,
+	ARM_ISB_RESERVED_10 = 10,
+	ARM_ISB_RESERVED_11 = 11,
+	ARM_ISB_RESERVED_12 = 12,
+	ARM_ISB_RESERVED_13 = 13,
+	ARM_ISB_RESERVED_14 = 14,
+	ARM_ISB_SY = 15
+} ARM_ISB_InstSyncBOpt;
 
 inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
 {
 	switch (val) {
-		default: // never reach
+	default:
-		case ARM_ISB_RESERVED_0:  return "#0x0";
+		// llvm_unreachable("Unknown memory operation");
-		case ARM_ISB_RESERVED_1:  return "#0x1";
+		assert(0);
-		case ARM_ISB_RESERVED_2:  return "#0x2";
+	case ARM_ISB_RESERVED_0:
-		case ARM_ISB_RESERVED_3:  return "#0x3";
+		return "#0x0";
-		case ARM_ISB_RESERVED_4:  return "#0x4";
+	case ARM_ISB_RESERVED_1:
-		case ARM_ISB_RESERVED_5:  return "#0x5";
+		return "#0x1";
-		case ARM_ISB_RESERVED_6:  return "#0x6";
+	case ARM_ISB_RESERVED_2:
-		case ARM_ISB_RESERVED_7:  return "#0x7";
+		return "#0x2";
-		case ARM_ISB_RESERVED_8:  return "#0x8";
+	case ARM_ISB_RESERVED_3:
-		case ARM_ISB_RESERVED_9:  return "#0x9";
+		return "#0x3";
-		case ARM_ISB_RESERVED_10: return "#0xa";
+	case ARM_ISB_RESERVED_4:
-		case ARM_ISB_RESERVED_11: return "#0xb";
+		return "#0x4";
-		case ARM_ISB_RESERVED_12: return "#0xc";
+	case ARM_ISB_RESERVED_5:
-		case ARM_ISB_RESERVED_13: return "#0xd";
+		return "#0x5";
-		case ARM_ISB_RESERVED_14: return "#0xe";
+	case ARM_ISB_RESERVED_6:
-		case ARM_ISB_SY:          return "sy";
+		return "#0x6";
+	case ARM_ISB_RESERVED_7:
+		return "#0x7";
+	case ARM_ISB_RESERVED_8:
+		return "#0x8";
+	case ARM_ISB_RESERVED_9:
+		return "#0x9";
+	case ARM_ISB_RESERVED_10:
+		return "#0xa";
+	case ARM_ISB_RESERVED_11:
+		return "#0xb";
+	case ARM_ISB_RESERVED_12:
+		return "#0xc";
+	case ARM_ISB_RESERVED_13:
+		return "#0xd";
+	case ARM_ISB_RESERVED_14:
+		return "#0xe";
+	case ARM_ISB_SY:
+		return "sy";
 	}
 }
 
+#define GET_REGINFO_ENUM
+#include "ARMGenRegisterInfo.inc"
+
 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
 ///
 static inline bool isARMLowRegister(unsigned Reg)
 {
-	//using namespace ARM;
+
 	switch (Reg) {
-		case ARM_R0:  case ARM_R1:  case ARM_R2:  case ARM_R3:
+	case ARM_R0:
-		case ARM_R4:  case ARM_R5:  case ARM_R6:  case ARM_R7:
+	case ARM_R1:
-			return true;
+	case ARM_R2:
-		default:
+	case ARM_R3:
-			return false;
+	case ARM_R4:
+	case ARM_R5:
+	case ARM_R6:
+	case ARM_R7:
+		return true;
+	default:
+		return false;
 	}
 }
 
@@ -195,99 +253,150 @@ static inline bool isARMLowRegister(unsigned Reg)
 /// instruction info tracks.
 ///
 /// ARM Index Modes
-enum ARMII_IndexMode {
+typedef enum IndexMode {
-	ARMII_IndexModeNone  = 0,
+	ARMII_IndexModeNone = 0,
-	ARMII_IndexModePre   = 1,
+	ARMII_IndexModePre = 1,
-	ARMII_IndexModePost  = 2,
+	ARMII_IndexModePost = 2,
-	ARMII_IndexModeUpd   = 3
+	ARMII_IndexModeUpd = 3
-};
+} ARMII_IndexMode;
 
 /// ARM Addressing Modes
-typedef enum ARMII_AddrMode {
+typedef enum AddrMode {
-	ARMII_AddrModeNone    = 0,
+	ARMII_AddrModeNone = 0,
-	ARMII_AddrMode1       = 1,
+	ARMII_AddrMode1 = 1,
-	ARMII_AddrMode2       = 2,
+	ARMII_AddrMode2 = 2,
-	ARMII_AddrMode3       = 3,
+	ARMII_AddrMode3 = 3,
-	ARMII_AddrMode4       = 4,
+	ARMII_AddrMode4 = 4,
-	ARMII_AddrMode5       = 5,
+	ARMII_AddrMode5 = 5,
-	ARMII_AddrMode6       = 6,
+	ARMII_AddrMode6 = 6,
-	ARMII_AddrModeT1_1    = 7,
+	ARMII_AddrModeT1_1 = 7,
-	ARMII_AddrModeT1_2    = 8,
+	ARMII_AddrModeT1_2 = 8,
-	ARMII_AddrModeT1_4    = 9,
+	ARMII_AddrModeT1_4 = 9,
-	ARMII_AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
+	ARMII_AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
-	ARMII_AddrModeT2_i12  = 11,
+	ARMII_AddrModeT2_i12 = 11,
-	ARMII_AddrModeT2_i8   = 12,
+	ARMII_AddrModeT2_i8 = 12,	 // +/- i8
-	ARMII_AddrModeT2_so   = 13,
+	ARMII_AddrModeT2_i8pos = 13, // + i8
-	ARMII_AddrModeT2_pc   = 14, // +/- i12 for pc relative data
+	ARMII_AddrModeT2_i8neg = 14, // - i8
-	ARMII_AddrModeT2_i8s4 = 15, // i8 * 4
+	ARMII_AddrModeT2_so = 15,
-	ARMII_AddrMode_i12    = 16
+	ARMII_AddrModeT2_pc = 16,	// +/- i12 for pc relative data
+	ARMII_AddrModeT2_i8s4 = 17, // i8 * 4
+	ARMII_AddrMode_i12 = 18,
+	ARMII_AddrMode5FP16 = 19,	 // i8 * 2
+	ARMII_AddrModeT2_ldrex = 20, // i8 * 4, with unscaled offset in MCInst
+	ARMII_AddrModeT2_i7s4 = 21,	 // i7 * 4
+	ARMII_AddrModeT2_i7s2 = 22,	 // i7 * 2
+	ARMII_AddrModeT2_i7 = 23,	 // i7 * 1
 } ARMII_AddrMode;
 
 inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
 {
 	switch (addrmode) {
-		case ARMII_AddrModeNone:    return "AddrModeNone";
+	case ARMII_AddrModeNone:
-		case ARMII_AddrMode1:       return "AddrMode1";
+		return "AddrModeNone";
-		case ARMII_AddrMode2:       return "AddrMode2";
+	case ARMII_AddrMode1:
-		case ARMII_AddrMode3:       return "AddrMode3";
+		return "AddrMode1";
-		case ARMII_AddrMode4:       return "AddrMode4";
+	case ARMII_AddrMode2:
-		case ARMII_AddrMode5:       return "AddrMode5";
+		return "AddrMode2";
-		case ARMII_AddrMode6:       return "AddrMode6";
+	case ARMII_AddrMode3:
-		case ARMII_AddrModeT1_1:    return "AddrModeT1_1";
+		return "AddrMode3";
-		case ARMII_AddrModeT1_2:    return "AddrModeT1_2";
+	case ARMII_AddrMode4:
-		case ARMII_AddrModeT1_4:    return "AddrModeT1_4";
+		return "AddrMode4";
-		case ARMII_AddrModeT1_s:    return "AddrModeT1_s";
+	case ARMII_AddrMode5:
-		case ARMII_AddrModeT2_i12:  return "AddrModeT2_i12";
+		return "AddrMode5";
-		case ARMII_AddrModeT2_i8:   return "AddrModeT2_i8";
+	case ARMII_AddrMode5FP16:
-		case ARMII_AddrModeT2_so:   return "AddrModeT2_so";
+		return "AddrMode5FP16";
-		case ARMII_AddrModeT2_pc:   return "AddrModeT2_pc";
+	case ARMII_AddrMode6:
-		case ARMII_AddrModeT2_i8s4: return "AddrModeT2_i8s4";
+		return "AddrMode6";
-		case ARMII_AddrMode_i12:    return "AddrMode_i12";
+	case ARMII_AddrModeT1_1:
+		return "AddrModeT1_1";
+	case ARMII_AddrModeT1_2:
+		return "AddrModeT1_2";
+	case ARMII_AddrModeT1_4:
+		return "AddrModeT1_4";
+	case ARMII_AddrModeT1_s:
+		return "AddrModeT1_s";
+	case ARMII_AddrModeT2_i12:
+		return "AddrModeT2_i12";
+	case ARMII_AddrModeT2_i8:
+		return "AddrModeT2_i8";
+	case ARMII_AddrModeT2_i8pos:
+		return "AddrModeT2_i8pos";
+	case ARMII_AddrModeT2_i8neg:
+		return "AddrModeT2_i8neg";
+	case ARMII_AddrModeT2_so:
+		return "AddrModeT2_so";
+	case ARMII_AddrModeT2_pc:
+		return "AddrModeT2_pc";
+	case ARMII_AddrModeT2_i8s4:
+		return "AddrModeT2_i8s4";
+	case ARMII_AddrMode_i12:
+		return "AddrMode_i12";
+	case ARMII_AddrModeT2_ldrex:
+		return "AddrModeT2_ldrex";
+	case ARMII_AddrModeT2_i7s4:
+		return "AddrModeT2_i7s4";
+	case ARMII_AddrModeT2_i7s2:
+		return "AddrModeT2_i7s2";
+	case ARMII_AddrModeT2_i7:
+		return "AddrModeT2_i7";
 	}
 }
 
 /// Target Operand Flag enum.
-enum ARMII_TOF {
+typedef enum TOF {
 	//===------------------------------------------------------------------===//
 	// ARM Specific MachineOperand flags.
 
-	ARMII_MO_NO_FLAG,
+	ARMII_MO_NO_FLAG = 0,
 
 	/// MO_LO16 - On a symbol operand, this represents a relocation containing
 	/// lower 16 bit of the address. Used only via movw instruction.
-	ARMII_MO_LO16,
+	ARMII_MO_LO16 = 0x1,
 
 	/// MO_HI16 - On a symbol operand, this represents a relocation containing
 	/// higher 16 bit of the address. Used only via movt instruction.
-	ARMII_MO_HI16,
+	ARMII_MO_HI16 = 0x2,
 
-	/// MO_LO16_NONLAZY - On a symbol operand "FOO", this represents a
+	/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
-	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+	/// just that part of the flag set.
-	/// i.e. "FOO$non_lazy_ptr".
+	ARMII_MO_OPTION_MASK = 0x3,
-	/// Used only via movw instruction.
-	ARMII_MO_LO16_NONLAZY,
 
-	/// MO_HI16_NONLAZY - On a symbol operand "FOO", this represents a
+	/// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
-	/// relocation containing lower 16 bit of the non-lazy-ptr indirect symbol,
+	/// reference is actually to the ".refptr.FOO" symbol.  This is used for
-	/// i.e. "FOO$non_lazy_ptr". Used only via movt instruction.
+	/// stub symbols on windows.
-	ARMII_MO_HI16_NONLAZY,
+	ARMII_MO_COFFSTUB = 0x4,
 
-	/// MO_LO16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+	/// MO_GOT - On a symbol operand, this represents a GOT relative relocation.
-	/// relocation containing lower 16 bit of the PC relative address of the
+	ARMII_MO_GOT = 0x8,
-	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
-	/// Used only via movw instruction.
-	ARMII_MO_LO16_NONLAZY_PIC,
 
-	/// MO_HI16_NONLAZY_PIC - On a symbol operand "FOO", this represents a
+	/// MO_SBREL - On a symbol operand, this represents a static base relative
-	/// relocation containing lower 16 bit of the PC relative address of the
+	/// relocation. Used in movw and movt instructions.
-	/// non-lazy-ptr indirect symbol, i.e. "FOO$non_lazy_ptr - LABEL".
+	ARMII_MO_SBREL = 0x10,
-	/// Used only via movt instruction.
-	ARMII_MO_HI16_NONLAZY_PIC,
 
-	/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
+	/// MO_DLLIMPORT - On a symbol operand, this represents that the reference
-	/// call operand.
+	/// to the symbol is for an import stub.  This is used for DLL import
-	ARMII_MO_PLT
+	/// storage class indication on Windows.
-};
+	ARMII_MO_DLLIMPORT = 0x20,
+
+	/// MO_SECREL - On a symbol operand this indicates that the immediate is
+	/// the offset from beginning of section.
+	///
+	/// This is the TLS offset for the COFF/Windows TLS mechanism.
+	ARMII_MO_SECREL = 0x40,
+
+	/// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
+	/// represents a symbol which, if indirect, will get special Darwin mangling
+	/// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
+	/// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
+	/// example).
+	ARMII_MO_NONLAZY = 0x80,
+
+	// It's undefined behaviour if an enum overflows the range between its
+	// smallest and largest values, but since these are |ed together, it can
+	// happen. Put a sentinel in (values of this enum are stored as "unsigned
+	// char").
+	ARMII_MO_UNUSED_MAXIMUM = 0xff
+} ARMII_TOF;
 
 enum {
 	//===------------------------------------------------------------------===//
@@ -295,110 +404,136 @@ enum {
 
 	//===------------------------------------------------------------------===//
 	// This four-bit field describes the addressing mode used.
-	ARMII_AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
+	ARMII_AddrModeMask =
+		0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
 
 	// IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
 	// and store ops only.  Generic "updating" flag is used for ld/st multiple.
 	// The index mode enums are declared in ARMBaseInfo.h
 	ARMII_IndexModeShift = 5,
-	ARMII_IndexModeMask  = 3 << ARMII_IndexModeShift,
+	ARMII_IndexModeMask = 3 << ARMII_IndexModeShift,
 
 	//===------------------------------------------------------------------===//
 	// Instruction encoding formats.
 	//
-	ARMII_FormShift     = 7,
+	ARMII_FormShift = 7,
-	ARMII_FormMask      = 0x3f << ARMII_FormShift,
+	ARMII_FormMask = 0x3f << ARMII_FormShift,
 
 	// Pseudo instructions
-	ARMII_Pseudo        = 0  << ARMII_FormShift,
+	ARMII_Pseudo = 0 << ARMII_FormShift,
 
 	// Multiply instructions
-	ARMII_MulFrm        = 1  << ARMII_FormShift,
+	ARMII_MulFrm = 1 << ARMII_FormShift,
 
 	// Branch instructions
-	ARMII_BrFrm         = 2  << ARMII_FormShift,
+	ARMII_BrFrm = 2 << ARMII_FormShift,
-	ARMII_BrMiscFrm     = 3  << ARMII_FormShift,
+	ARMII_BrMiscFrm = 3 << ARMII_FormShift,
 
 	// Data Processing instructions
-	ARMII_DPFrm         = 4  << ARMII_FormShift,
+	ARMII_DPFrm = 4 << ARMII_FormShift,
-	ARMII_DPSoRegFrm    = 5  << ARMII_FormShift,
+	ARMII_DPSoRegFrm = 5 << ARMII_FormShift,
 
 	// Load and Store
-	ARMII_LdFrm         = 6  << ARMII_FormShift,
+	ARMII_LdFrm = 6 << ARMII_FormShift,
-	ARMII_StFrm         = 7  << ARMII_FormShift,
+	ARMII_StFrm = 7 << ARMII_FormShift,
-	ARMII_LdMiscFrm     = 8  << ARMII_FormShift,
+	ARMII_LdMiscFrm = 8 << ARMII_FormShift,
-	ARMII_StMiscFrm     = 9  << ARMII_FormShift,
+	ARMII_StMiscFrm = 9 << ARMII_FormShift,
-	ARMII_LdStMulFrm    = 10 << ARMII_FormShift,
+	ARMII_LdStMulFrm = 10 << ARMII_FormShift,
 
-	ARMII_LdStExFrm     = 11 << ARMII_FormShift,
+	ARMII_LdStExFrm = 11 << ARMII_FormShift,
 
 	// Miscellaneous arithmetic instructions
-	ARMII_ArithMiscFrm  = 12 << ARMII_FormShift,
+	ARMII_ArithMiscFrm = 12 << ARMII_FormShift,
-	ARMII_SatFrm        = 13 << ARMII_FormShift,
+	ARMII_SatFrm = 13 << ARMII_FormShift,
 
 	// Extend instructions
-	ARMII_ExtFrm        = 14 << ARMII_FormShift,
+	ARMII_ExtFrm = 14 << ARMII_FormShift,
 
 	// VFP formats
-	ARMII_VFPUnaryFrm   = 15 << ARMII_FormShift,
+	ARMII_VFPUnaryFrm = 15 << ARMII_FormShift,
-	ARMII_VFPBinaryFrm  = 16 << ARMII_FormShift,
+	ARMII_VFPBinaryFrm = 16 << ARMII_FormShift,
-	ARMII_VFPConv1Frm   = 17 << ARMII_FormShift,
+	ARMII_VFPConv1Frm = 17 << ARMII_FormShift,
-	ARMII_VFPConv2Frm   = 18 << ARMII_FormShift,
+	ARMII_VFPConv2Frm = 18 << ARMII_FormShift,
-	ARMII_VFPConv3Frm   = 19 << ARMII_FormShift,
+	ARMII_VFPConv3Frm = 19 << ARMII_FormShift,
-	ARMII_VFPConv4Frm   = 20 << ARMII_FormShift,
+	ARMII_VFPConv4Frm = 20 << ARMII_FormShift,
-	ARMII_VFPConv5Frm   = 21 << ARMII_FormShift,
+	ARMII_VFPConv5Frm = 21 << ARMII_FormShift,
-	ARMII_VFPLdStFrm    = 22 << ARMII_FormShift,
+	ARMII_VFPLdStFrm = 22 << ARMII_FormShift,
 	ARMII_VFPLdStMulFrm = 23 << ARMII_FormShift,
-	ARMII_VFPMiscFrm    = 24 << ARMII_FormShift,
+	ARMII_VFPMiscFrm = 24 << ARMII_FormShift,
 
 	// Thumb format
-	ARMII_ThumbFrm      = 25 << ARMII_FormShift,
+	ARMII_ThumbFrm = 25 << ARMII_FormShift,
 
 	// Miscelleaneous format
-	ARMII_MiscFrm       = 26 << ARMII_FormShift,
+	ARMII_MiscFrm = 26 << ARMII_FormShift,
 
 	// NEON formats
-	ARMII_NGetLnFrm     = 27 << ARMII_FormShift,
+	ARMII_NGetLnFrm = 27 << ARMII_FormShift,
-	ARMII_NSetLnFrm     = 28 << ARMII_FormShift,
+	ARMII_NSetLnFrm = 28 << ARMII_FormShift,
-	ARMII_NDupFrm       = 29 << ARMII_FormShift,
+	ARMII_NDupFrm = 29 << ARMII_FormShift,
-	ARMII_NLdStFrm      = 30 << ARMII_FormShift,
+	ARMII_NLdStFrm = 30 << ARMII_FormShift,
-	ARMII_N1RegModImmFrm= 31 << ARMII_FormShift,
+	ARMII_N1RegModImmFrm = 31 << ARMII_FormShift,
-	ARMII_N2RegFrm      = 32 << ARMII_FormShift,
+	ARMII_N2RegFrm = 32 << ARMII_FormShift,
-	ARMII_NVCVTFrm      = 33 << ARMII_FormShift,
+	ARMII_NVCVTFrm = 33 << ARMII_FormShift,
-	ARMII_NVDupLnFrm    = 34 << ARMII_FormShift,
+	ARMII_NVDupLnFrm = 34 << ARMII_FormShift,
-	ARMII_N2RegVShLFrm  = 35 << ARMII_FormShift,
+	ARMII_N2RegVShLFrm = 35 << ARMII_FormShift,
-	ARMII_N2RegVShRFrm  = 36 << ARMII_FormShift,
+	ARMII_N2RegVShRFrm = 36 << ARMII_FormShift,
-	ARMII_N3RegFrm      = 37 << ARMII_FormShift,
+	ARMII_N3RegFrm = 37 << ARMII_FormShift,
-	ARMII_N3RegVShFrm   = 38 << ARMII_FormShift,
+	ARMII_N3RegVShFrm = 38 << ARMII_FormShift,
-	ARMII_NVExtFrm      = 39 << ARMII_FormShift,
+	ARMII_NVExtFrm = 39 << ARMII_FormShift,
-	ARMII_NVMulSLFrm    = 40 << ARMII_FormShift,
+	ARMII_NVMulSLFrm = 40 << ARMII_FormShift,
-	ARMII_NVTBLFrm      = 41 << ARMII_FormShift,
+	ARMII_NVTBLFrm = 41 << ARMII_FormShift,
+	ARMII_N3RegCplxFrm = 43 << ARMII_FormShift,
 
 	//===------------------------------------------------------------------===//
 	// Misc flags.
 
 	// UnaryDP - Indicates this is a unary data processing instruction, i.e.
 	// it doesn't have a Rn operand.
-	ARMII_UnaryDP       = 1 << 13,
+	ARMII_UnaryDP = 1 << 13,
 
 	// Xform16Bit - Indicates this Thumb2 instruction may be transformed into
 	// a 16-bit Thumb instruction if certain conditions are met.
-	ARMII_Xform16Bit    = 1 << 14,
+	ARMII_Xform16Bit = 1 << 14,
 
 	// ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
 	// instruction. Used by the parser to determine whether to require the 'S'
 	// suffix on the mnemonic (when not in an IT block) or preclude it (when
 	// in an IT block).
-	ARMII_ThumbArithFlagSetting = 1 << 18,
+	ARMII_ThumbArithFlagSetting = 1 << 19,
+
+	// Whether an instruction can be included in an MVE tail-predicated loop,
+	// though extra validity checks may need to be performed too.
+	ARMII_ValidForTailPredication = 1 << 20,
+
+	// Whether an instruction writes to the top/bottom half of a vector element
+	// and leaves the other half untouched.
+	ARMII_RetainsPreviousHalfElement = 1 << 21,
+
+	// Whether the instruction produces a scalar result from vector operands.
+	ARMII_HorizontalReduction = 1 << 22,
+
+	// Whether this instruction produces a vector result that is larger than
+	// its input, typically reading from the top/bottom halves of the input(s).
+	ARMII_DoubleWidthResult = 1 << 23,
+
+	// The vector element size for MVE instructions. 00 = i8, 01 = i16, 10 = i32
+	// and 11 = i64. This is the largest type if multiple are present, so a
+	// MVE_VMOVLs8bh is ize 01=i16, as it extends from a i8 to a i16. There are
+	// some caveats so cannot be used blindly, such as exchanging VMLADAVA's and
+	// complex instructions, which may use different input lanes.
+	ARMII_VecSizeShift = 24,
+	ARMII_VecSize = 3 << ARMII_VecSizeShift,
 
 	//===------------------------------------------------------------------===//
 	// Code domain.
-	ARMII_DomainShift   = 15,
+	ARMII_DomainShift = 15,
-	ARMII_DomainMask    = 7 << ARMII_DomainShift,
+	ARMII_DomainMask = 15 << ARMII_DomainShift,
 	ARMII_DomainGeneral = 0 << ARMII_DomainShift,
-	ARMII_DomainVFP     = 1 << ARMII_DomainShift,
+	ARMII_DomainVFP = 1 << ARMII_DomainShift,
-	ARMII_DomainNEON    = 2 << ARMII_DomainShift,
+	ARMII_DomainNEON = 2 << ARMII_DomainShift,
-	ARMII_DomainNEONA8  = 4 << ARMII_DomainShift,
+	ARMII_DomainNEONA8 = 4 << ARMII_DomainShift,
+	ARMII_DomainMVE = 8 << ARMII_DomainShift,
 
 	//===------------------------------------------------------------------===//
 	// Field shifts - such shifts are used to set field while generating
@@ -408,79 +543,28 @@ enum {
 	// takes shape and the ARMCodeEmitter.cpp bits go away.
 	ARMII_ShiftTypeShift = 4,
 
-	ARMII_M_BitShift     = 5,
+	ARMII_M_BitShift = 5,
-	ARMII_ShiftImmShift  = 5,
+	ARMII_ShiftImmShift = 5,
-	ARMII_ShiftShift     = 7,
+	ARMII_ShiftShift = 7,
-	ARMII_N_BitShift     = 7,
+	ARMII_N_BitShift = 7,
-	ARMII_ImmHiShift     = 8,
+	ARMII_ImmHiShift = 8,
-	ARMII_SoRotImmShift  = 8,
+	ARMII_SoRotImmShift = 8,
-	ARMII_RegRsShift     = 8,
+	ARMII_RegRsShift = 8,
 	ARMII_ExtRotImmShift = 10,
-	ARMII_RegRdLoShift   = 12,
+	ARMII_RegRdLoShift = 12,
-	ARMII_RegRdShift     = 12,
+	ARMII_RegRdShift = 12,
-	ARMII_RegRdHiShift   = 16,
+	ARMII_RegRdHiShift = 16,
-	ARMII_RegRnShift     = 16,
+	ARMII_RegRnShift = 16,
-	ARMII_S_BitShift     = 20,
+	ARMII_S_BitShift = 20,
-	ARMII_W_BitShift     = 21,
+	ARMII_W_BitShift = 21,
 	ARMII_AM3_I_BitShift = 22,
-	ARMII_D_BitShift     = 22,
+	ARMII_D_BitShift = 22,
-	ARMII_U_BitShift     = 23,
+	ARMII_U_BitShift = 23,
-	ARMII_P_BitShift     = 24,
+	ARMII_P_BitShift = 24,
-	ARMII_I_BitShift     = 25,
+	ARMII_I_BitShift = 25,
-	ARMII_CondShift      = 28
+	ARMII_CondShift = 28
 };
 
-typedef struct MClassSysReg {
+const char *get_pred_mask(ARM_PredBlockMask pred_mask);
-	const char *Name;
-	arm_sysreg sysreg;
-	uint16_t M1Encoding12;
-	uint16_t M2M3Encoding8;
-	uint16_t Encoding;
-	int FeaturesRequired[2];	// 2 is enough for MClassSysRegsList
-} MClassSysReg;
 
-enum TraceSyncBOpt {
+#endif // CS_ARM_BASEINFO_H
-	CSYNC = 0
-};
-
-const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
-const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
-
-// returns APSR with _<bits> qualifier.
-// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
-static inline const MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
-{
-	return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF));
-}
-
-static inline const MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
-{
-	return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF));
-}
-
-// returns true if TestFeatures are all present in FeaturesRequired
-static inline bool MClassSysReg_isInRequiredFeatures(const MClassSysReg *TheReg, int TestFeatures)
-{
-	return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures);
-}
-
-// lookup system register using 12-bit SYSm value.
-// Note: the search is uniqued using M1 mask
-static inline const MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
-{
-  return lookupMClassSysRegByM1Encoding12(SYSm);
-}
-
-static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
-{
-	switch (val) {
-		default:
-			// llvm_unreachable("Unknown trace synchronization barrier operation");
-			return NULL;
-
-		case CSYNC:
-			return "csync";
-	}
-}
-
-#endif

arch/ARM/ARMDisassembler.h

@@ -1,18 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#ifndef CS_ARMDISASSEMBLER_H
-#define CS_ARMDISASSEMBLER_H
-
-#include "capstone/capstone.h"
-#include "../../MCRegisterInfo.h"
-
-void ARM_init(MCRegisterInfo *MRI);
-
-bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
-
-bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
-
-bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
-
-#endif

arch/ARM/ARMDisassemblerExtension.c

@@ -0,0 +1,227 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#include "ARMDisassemblerExtension.h"
+#include "ARMBaseInfo.h"
+
+bool ITBlock_push_back(ARM_ITBlock *it, char v)
+{
+	if (it->size >= sizeof(it->ITStates)) {
+		// TODO: consider warning user.
+		it->size = 0;
+	}
+	it->ITStates[it->size] = v;
+	it->size++;
+
+	return true;
+}
+
+// Returns true if the current instruction is in an IT block
+bool ITBlock_instrInITBlock(ARM_ITBlock *it)
+{
+	return (it->size > 0);
+}
+
+// Returns true if current instruction is the last instruction in an IT block
+bool ITBlock_instrLastInITBlock(ARM_ITBlock *it) { return (it->size == 1); }
+
+// Returns the condition code for instruction in IT block
+unsigned ITBlock_getITCC(ARM_ITBlock *it)
+{
+	unsigned CC = ARMCC_AL;
+
+	if (ITBlock_instrInITBlock(it))
+		CC = it->ITStates[it->size - 1];
+
+	return CC;
+}
+
+// Advances the IT block state to the next T or E
+void ITBlock_advanceITState(ARM_ITBlock *it)
+{
+	it->size--;
+}
+
+// Called when decoding an IT instruction. Sets the IT state for the following
+// instructions that for the IT block. Firstcond and Mask correspond to the
+// fields in the IT instruction encoding.
+void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask)
+{
+	// (3 - the number of trailing zeros) is the number of then / else.
+	unsigned NumTZ = CountTrailingZeros_8(Mask);
+	unsigned char CCBits = (unsigned char)(Firstcond & 0xf);
+	assert(NumTZ <= 3 && "Invalid IT mask!");
+	// push condition codes onto the stack the correct order for the pops
+	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
+		unsigned Else = (Mask >> Pos) & 1;
+		ITBlock_push_back(it, CCBits ^ Else);
+	}
+	ITBlock_push_back(it, CCBits);
+}
+
+bool VPTBlock_push_back(ARM_VPTBlock *it, char v)
+{
+	if (it->size >= sizeof(it->VPTStates)) {
+		// TODO: consider warning user.
+		it->size = 0;
+	}
+	it->VPTStates[it->size] = v;
+	it->size++;
+
+	return true;
+}
+
+bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT) { return VPT->size > 0; }
+
+unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT)
+{
+	unsigned Pred = ARMVCC_None;
+	if (VPTBlock_instrInVPTBlock(VPT))
+		Pred = VPT->VPTStates[VPT->size - 1];
+	return Pred;
+}
+
+void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT) { VPT->size--; }
+
+void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask)
+{
+	// (3 - the number of trailing zeros) is the number of then / else.
+	unsigned NumTZ = CountTrailingZeros_8(Mask);
+	assert(NumTZ <= 3 && "Invalid VPT mask!");
+	// push predicates onto the stack the correct order for the pops
+	for (unsigned Pos = NumTZ + 1; Pos <= 3; ++Pos) {
+		bool T = ((Mask >> Pos) & 1) == 0;
+		if (T)
+			VPTBlock_push_back(VPT, ARMVCC_Then);
+		else
+			VPTBlock_push_back(VPT, ARMVCC_Else);
+	}
+	VPTBlock_push_back(VPT, ARMVCC_Then);
+}
+
+/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
+
+bool Check(DecodeStatus *Out, DecodeStatus In)
+{
+	switch (In) {
+	case MCDisassembler_Success:
+		// Out stays the same.
+		return true;
+	case MCDisassembler_SoftFail:
+		*Out = In;
+		return true;
+	case MCDisassembler_Fail:
+		*Out = In;
+		return false;
+	default: // never reached
+		return false;
+	}
+}
+
+// Imported from ARMBaseInstrInfo.h
+//
+/// isValidCoprocessorNumber - decide whether an explicit coprocessor
+/// number is legal in generic instructions like CDP. The answer can
+/// vary with the subtarget.
+bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num)
+{
+	// In Armv7 and Armv8-M CP10 and CP11 clash with VFP/NEON, however, the
+	// coprocessor is still valid for CDP/MCR/MRC and friends. Allowing it is
+	// useful for code which is shared with older architectures which do not
+	// know the new VFP/NEON mnemonics.
+
+	// Armv8-A disallows everything *other* than 111x (CP14 and CP15).
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8Ops) && (Num & 0xE) != 0xE)
+		return false;
+
+	// Armv8.1-M disallows 100x (CP8,CP9) and 111x (CP14,CP15)
+	// which clash with MVE.
+	if (ARM_getFeatureBits(Inst->csh->mode, ARM_HasV8_1MMainlineOps) &&
+		((Num & 0xE) == 0x8 || (Num & 0xE) == 0xE))
+		return false;
+
+	return true;
+}
+
+// Imported from ARMMCTargetDesc.h
+bool ARM_isVpred(arm_op_type op)
+{
+	return op == ARM_OP_VPRED_R || op == ARM_OP_VPRED_N;
+}
+
+// Imported from ARMBaseInstrInfo.h
+//
+// This table shows the VPT instruction variants, i.e. the different
+// mask field encodings, see also B5.6. Predication/conditional execution in
+// the ArmARM.
+bool isVPTOpcode(int Opc)
+{
+	return Opc == ARM_MVE_VPTv16i8 || Opc == ARM_MVE_VPTv16u8 ||
+		   Opc == ARM_MVE_VPTv16s8 || Opc == ARM_MVE_VPTv8i16 ||
+		   Opc == ARM_MVE_VPTv8u16 || Opc == ARM_MVE_VPTv8s16 ||
+		   Opc == ARM_MVE_VPTv4i32 || Opc == ARM_MVE_VPTv4u32 ||
+		   Opc == ARM_MVE_VPTv4s32 || Opc == ARM_MVE_VPTv4f32 ||
+		   Opc == ARM_MVE_VPTv8f16 || Opc == ARM_MVE_VPTv16i8r ||
+		   Opc == ARM_MVE_VPTv16u8r || Opc == ARM_MVE_VPTv16s8r ||
+		   Opc == ARM_MVE_VPTv8i16r || Opc == ARM_MVE_VPTv8u16r ||
+		   Opc == ARM_MVE_VPTv8s16r || Opc == ARM_MVE_VPTv4i32r ||
+		   Opc == ARM_MVE_VPTv4u32r || Opc == ARM_MVE_VPTv4s32r ||
+		   Opc == ARM_MVE_VPTv4f32r || Opc == ARM_MVE_VPTv8f16r ||
+		   Opc == ARM_MVE_VPST;
+}
+
+// Imported from ARMMCTargetDesc.cpp
+bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI)
+{
+	// Unfortunately we don't have ARMTargetInfo in the disassembler, so we have
+	// to rely on feature bits.
+	if (Coproc >= 8)
+		return false;
+
+	return ARM_getFeatureBits(MI->csh->mode, ARM_FeatureCoprocCDE0 + Coproc);
+}
+
+// Hacky: enable all features for disassembler
+bool ARM_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+
+	if (feature == ARM_ModeThumb) {
+		if (mode & CS_MODE_THUMB)
+			return true;
+		return false;
+	}
+
+	if (feature == ARM_FeatureDFB)
+		return false;
+
+	if (feature == ARM_FeatureRAS)
+		return false;
+
+	if (feature == ARM_FeatureMClass && (mode & CS_MODE_MCLASS) == 0)
+		return false;
+
+	if ((feature == ARM_HasMVEIntegerOps || feature == ARM_HasMVEFloatOps ||
+		 feature == ARM_FeatureMVEVectorCostFactor1 ||
+		 feature == ARM_FeatureMVEVectorCostFactor2 ||
+		 feature == ARM_FeatureMVEVectorCostFactor4) &&
+		(mode & CS_MODE_MCLASS) == 0)
+		return false;
+
+	if ((feature == ARM_HasV8Ops || feature == ARM_HasV8_1MMainlineOps ||
+		 feature == ARM_HasV8_1aOps || feature == ARM_HasV8_2aOps ||
+		 feature == ARM_HasV8_3aOps || feature == ARM_HasV8_4aOps ||
+		 feature == ARM_HasV8_5aOps || feature == ARM_HasV8_6aOps ||
+		 feature == ARM_HasV8_7aOps || feature == ARM_HasV8_8aOps ||
+		 feature == ARM_HasV8_9aOps) &&
+		(mode & CS_MODE_V8) == 0)
+		return false;
+
+	if (feature >= ARM_FeatureCoprocCDE0 && feature <= ARM_FeatureCoprocCDE7)
+		// We currently have no way to detect CDE (Custom-Datapath-Extension)
+		// coprocessors.
+		return false;
+
+	// we support everything
+	return true;
+}

arch/ARM/ARMDisassemblerExtension.h

@@ -0,0 +1,51 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_ARM_DISASSEMBLER_EXTENSION_H
+#define CS_ARM_DISASSEMBLER_EXTENSION_H
+
+#include "../../MCDisassembler.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MathExtras.h"
+#include "../../cs_priv.h"
+#include "ARMAddressingModes.h"
+#include "capstone/capstone.h"
+
+unsigned ARM_AM_getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset);
+
+bool ITBlock_push_back(ARM_ITBlock *it, char v);
+
+bool ITBlock_instrInITBlock(ARM_ITBlock *it);
+
+bool ITBlock_instrLastInITBlock(ARM_ITBlock *it);
+
+unsigned ITBlock_getITCC(ARM_ITBlock *it);
+
+void ITBlock_advanceITState(ARM_ITBlock *it);
+
+void ITBlock_setITState(ARM_ITBlock *it, char Firstcond, char Mask);
+
+bool Check(DecodeStatus *Out, DecodeStatus In);
+
+bool isValidCoprocessorNumber(MCInst *Inst, unsigned Num);
+
+bool ARM_isVpred(arm_op_type op);
+
+bool isVPTOpcode(int Opc);
+
+bool ARM_isCDECoproc(size_t Coproc, const MCInst *MI);
+
+bool VPTBlock_push_back(ARM_VPTBlock *it, char v);
+
+bool VPTBlock_instrInVPTBlock(ARM_VPTBlock *VPT);
+
+unsigned VPTBlock_getVPTPred(ARM_VPTBlock *VPT);
+
+void VPTBlock_advanceVPTState(ARM_VPTBlock *VPT);
+
+void VPTBlock_setVPTState(ARM_VPTBlock *VPT, char Mask);
+
+bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
+
+#endif // CS_ARM_DISASSEMBLER_EXTENSION_H

arch/ARM/ARMFeatureEnum.inc

@@ -0,0 +1,61 @@
+  ARM_FEATURE_IsThumb = 128,
+  ARM_FEATURE_IsARM,
+  ARM_FEATURE_UseNegativeImmediates,
+  ARM_FEATURE_IsThumb2,
+  ARM_FEATURE_HasV8,
+  ARM_FEATURE_HasAES,
+  ARM_FEATURE_HasV8_1MMainline,
+  ARM_FEATURE_HasMVEInt,
+  ARM_FEATURE_HasV7,
+  ARM_FEATURE_IsMClass,
+  ARM_FEATURE_HasPACBTI,
+  ARM_FEATURE_HasV8MBaseline,
+  ARM_FEATURE_HasLOB,
+  ARM_FEATURE_HasV6T2,
+  ARM_FEATURE_HasV5T,
+  ARM_FEATURE_IsNotMClass,
+  ARM_FEATURE_Has8MSecExt,
+  ARM_FEATURE_HasV4T,
+  ARM_FEATURE_PreV8,
+  ARM_FEATURE_HasCLRBHB,
+  ARM_FEATURE_HasV6K,
+  ARM_FEATURE_HasV7Clrex,
+  ARM_FEATURE_HasCRC,
+  ARM_FEATURE_HasCDE,
+  ARM_FEATURE_HasDFB,
+  ARM_FEATURE_HasDB,
+  ARM_FEATURE_HasVirtualization,
+  ARM_FEATURE_HasRAS,
+  ARM_FEATURE_HasVFP2,
+  ARM_FEATURE_HasDPVFP,
+  ARM_FEATURE_HasVFP3,
+  ARM_FEATURE_HasFPRegs,
+  ARM_FEATURE_HasV6M,
+  ARM_FEATURE_HasV6,
+  ARM_FEATURE_HasAcquireRelease,
+  ARM_FEATURE_HasV5TE,
+  ARM_FEATURE_HasDSP,
+  ARM_FEATURE_HasMP,
+  ARM_FEATURE_HasSB,
+  ARM_FEATURE_HasDivideInThumb,
+  ARM_FEATURE_HasDivideInARM,
+  ARM_FEATURE_HasV8_1a,
+  ARM_FEATURE_HasSHA2,
+  ARM_FEATURE_HasTrustZone,
+  ARM_FEATURE_UseNaClTrap,
+  ARM_FEATURE_HasV8_4a,
+  ARM_FEATURE_HasNEON,
+  ARM_FEATURE_HasFullFP16,
+  ARM_FEATURE_HasMVEFloat,
+  ARM_FEATURE_HasV8_3a,
+  ARM_FEATURE_HasFP16,
+  ARM_FEATURE_HasBF16,
+  ARM_FEATURE_HasFPARMv8,
+  ARM_FEATURE_HasVFP4,
+  ARM_FEATURE_HasFP16FML,
+  ARM_FEATURE_HasFPRegs16,
+  ARM_FEATURE_HasV8MMainline,
+  ARM_FEATURE_HasFPRegs64,
+  ARM_FEATURE_HasFPRegsV8_1M,
+  ARM_FEATURE_HasDotProd,
+  ARM_FEATURE_HasMatMulInt8,

arch/ARM/ARMGenCSFeatureName.inc

@@ -0,0 +1,70 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+{ ARM_FEATURE_IsARM, "IsARM" },
+{ ARM_FEATURE_HasV5T, "HasV5T" },
+{ ARM_FEATURE_HasV4T, "HasV4T" },
+{ ARM_FEATURE_HasVFP2, "HasVFP2" },
+{ ARM_FEATURE_HasV5TE, "HasV5TE" },
+{ ARM_FEATURE_HasV6T2, "HasV6T2" },
+{ ARM_FEATURE_HasMVEInt, "HasMVEInt" },
+{ ARM_FEATURE_HasNEON, "HasNEON" },
+{ ARM_FEATURE_HasFPRegs64, "HasFPRegs64" },
+{ ARM_FEATURE_HasFPRegs, "HasFPRegs" },
+{ ARM_FEATURE_IsThumb2, "IsThumb2" },
+{ ARM_FEATURE_HasV8_1MMainline, "HasV8_1MMainline" },
+{ ARM_FEATURE_HasLOB, "HasLOB" },
+{ ARM_FEATURE_IsThumb, "IsThumb" },
+{ ARM_FEATURE_HasV8MBaseline, "HasV8MBaseline" },
+{ ARM_FEATURE_Has8MSecExt, "Has8MSecExt" },
+{ ARM_FEATURE_HasV8, "HasV8" },
+{ ARM_FEATURE_HasAES, "HasAES" },
+{ ARM_FEATURE_HasBF16, "HasBF16" },
+{ ARM_FEATURE_HasCDE, "HasCDE" },
+{ ARM_FEATURE_PreV8, "PreV8" },
+{ ARM_FEATURE_HasV6K, "HasV6K" },
+{ ARM_FEATURE_HasCRC, "HasCRC" },
+{ ARM_FEATURE_HasV7, "HasV7" },
+{ ARM_FEATURE_HasDB, "HasDB" },
+{ ARM_FEATURE_HasVirtualization, "HasVirtualization" },
+{ ARM_FEATURE_HasVFP3, "HasVFP3" },
+{ ARM_FEATURE_HasDPVFP, "HasDPVFP" },
+{ ARM_FEATURE_HasFullFP16, "HasFullFP16" },
+{ ARM_FEATURE_HasV6, "HasV6" },
+{ ARM_FEATURE_HasAcquireRelease, "HasAcquireRelease" },
+{ ARM_FEATURE_HasV7Clrex, "HasV7Clrex" },
+{ ARM_FEATURE_HasMVEFloat, "HasMVEFloat" },
+{ ARM_FEATURE_HasFPRegsV8_1M, "HasFPRegsV8_1M" },
+{ ARM_FEATURE_HasMP, "HasMP" },
+{ ARM_FEATURE_HasSB, "HasSB" },
+{ ARM_FEATURE_HasDivideInARM, "HasDivideInARM" },
+{ ARM_FEATURE_HasV8_1a, "HasV8_1a" },
+{ ARM_FEATURE_HasSHA2, "HasSHA2" },
+{ ARM_FEATURE_HasTrustZone, "HasTrustZone" },
+{ ARM_FEATURE_UseNaClTrap, "UseNaClTrap" },
+{ ARM_FEATURE_HasV8_4a, "HasV8_4a" },
+{ ARM_FEATURE_HasV8_3a, "HasV8_3a" },
+{ ARM_FEATURE_HasFPARMv8, "HasFPARMv8" },
+{ ARM_FEATURE_HasFP16, "HasFP16" },
+{ ARM_FEATURE_HasVFP4, "HasVFP4" },
+{ ARM_FEATURE_HasFP16FML, "HasFP16FML" },
+{ ARM_FEATURE_HasFPRegs16, "HasFPRegs16" },
+{ ARM_FEATURE_HasV8MMainline, "HasV8MMainline" },
+{ ARM_FEATURE_HasDotProd, "HasDotProd" },
+{ ARM_FEATURE_HasMatMulInt8, "HasMatMulInt8" },
+{ ARM_FEATURE_IsMClass, "IsMClass" },
+{ ARM_FEATURE_HasPACBTI, "HasPACBTI" },
+{ ARM_FEATURE_IsNotMClass, "IsNotMClass" },
+{ ARM_FEATURE_HasDSP, "HasDSP" },
+{ ARM_FEATURE_HasDivideInThumb, "HasDivideInThumb" },
+{ ARM_FEATURE_HasV6M, "HasV6M" },

arch/ARM/ARMGenCSMappingInsnName.inc

@@ -0,0 +1,650 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  "invalid", // ARM_INS_INVALID
+  "asr", // ARM_INS_ASR
+  "it", // ARM_INS_IT
+  "ldrbt", // ARM_INS_LDRBT
+  "ldr", // ARM_INS_LDR
+  "ldrht", // ARM_INS_LDRHT
+  "ldrsbt", // ARM_INS_LDRSBT
+  "ldrsht", // ARM_INS_LDRSHT
+  "ldrt", // ARM_INS_LDRT
+  "lsl", // ARM_INS_LSL
+  "lsr", // ARM_INS_LSR
+  "ror", // ARM_INS_ROR
+  "rrx", // ARM_INS_RRX
+  "strbt", // ARM_INS_STRBT
+  "strt", // ARM_INS_STRT
+  "vld1", // ARM_INS_VLD1
+  "vld2", // ARM_INS_VLD2
+  "vld3", // ARM_INS_VLD3
+  "vld4", // ARM_INS_VLD4
+  "vst1", // ARM_INS_VST1
+  "vst2", // ARM_INS_VST2
+  "vst3", // ARM_INS_VST3
+  "vst4", // ARM_INS_VST4
+  "ldrb", // ARM_INS_LDRB
+  "ldrh", // ARM_INS_LDRH
+  "ldrsb", // ARM_INS_LDRSB
+  "ldrsh", // ARM_INS_LDRSH
+  "movs", // ARM_INS_MOVS
+  "mov", // ARM_INS_MOV
+  "str", // ARM_INS_STR
+  "adc", // ARM_INS_ADC
+  "add", // ARM_INS_ADD
+  "adr", // ARM_INS_ADR
+  "aesd", // ARM_INS_AESD
+  "aese", // ARM_INS_AESE
+  "aesimc", // ARM_INS_AESIMC
+  "aesmc", // ARM_INS_AESMC
+  "and", // ARM_INS_AND
+  "vdot", // ARM_INS_VDOT
+  "vcvt", // ARM_INS_VCVT
+  "vcvtb", // ARM_INS_VCVTB
+  "vcvtt", // ARM_INS_VCVTT
+  "bfc", // ARM_INS_BFC
+  "bfi", // ARM_INS_BFI
+  "bic", // ARM_INS_BIC
+  "bkpt", // ARM_INS_BKPT
+  "bl", // ARM_INS_BL
+  "blx", // ARM_INS_BLX
+  "bx", // ARM_INS_BX
+  "bxj", // ARM_INS_BXJ
+  "b", // ARM_INS_B
+  "cx1", // ARM_INS_CX1
+  "cx1a", // ARM_INS_CX1A
+  "cx1d", // ARM_INS_CX1D
+  "cx1da", // ARM_INS_CX1DA
+  "cx2", // ARM_INS_CX2
+  "cx2a", // ARM_INS_CX2A
+  "cx2d", // ARM_INS_CX2D
+  "cx2da", // ARM_INS_CX2DA
+  "cx3", // ARM_INS_CX3
+  "cx3a", // ARM_INS_CX3A
+  "cx3d", // ARM_INS_CX3D
+  "cx3da", // ARM_INS_CX3DA
+  "vcx1a", // ARM_INS_VCX1A
+  "vcx1", // ARM_INS_VCX1
+  "vcx2a", // ARM_INS_VCX2A
+  "vcx2", // ARM_INS_VCX2
+  "vcx3a", // ARM_INS_VCX3A
+  "vcx3", // ARM_INS_VCX3
+  "cdp", // ARM_INS_CDP
+  "cdp2", // ARM_INS_CDP2
+  "clrex", // ARM_INS_CLREX
+  "clz", // ARM_INS_CLZ
+  "cmn", // ARM_INS_CMN
+  "cmp", // ARM_INS_CMP
+  "cps", // ARM_INS_CPS
+  "crc32b", // ARM_INS_CRC32B
+  "crc32cb", // ARM_INS_CRC32CB
+  "crc32ch", // ARM_INS_CRC32CH
+  "crc32cw", // ARM_INS_CRC32CW
+  "crc32h", // ARM_INS_CRC32H
+  "crc32w", // ARM_INS_CRC32W
+  "dbg", // ARM_INS_DBG
+  "dmb", // ARM_INS_DMB
+  "dsb", // ARM_INS_DSB
+  "eor", // ARM_INS_EOR
+  "eret", // ARM_INS_ERET
+  "vmov", // ARM_INS_VMOV
+  "fldmdbx", // ARM_INS_FLDMDBX
+  "fldmiax", // ARM_INS_FLDMIAX
+  "vmrs", // ARM_INS_VMRS
+  "fstmdbx", // ARM_INS_FSTMDBX
+  "fstmiax", // ARM_INS_FSTMIAX
+  "hint", // ARM_INS_HINT
+  "hlt", // ARM_INS_HLT
+  "hvc", // ARM_INS_HVC
+  "isb", // ARM_INS_ISB
+  "lda", // ARM_INS_LDA
+  "ldab", // ARM_INS_LDAB
+  "ldaex", // ARM_INS_LDAEX
+  "ldaexb", // ARM_INS_LDAEXB
+  "ldaexd", // ARM_INS_LDAEXD
+  "ldaexh", // ARM_INS_LDAEXH
+  "ldah", // ARM_INS_LDAH
+  "ldc2l", // ARM_INS_LDC2L
+  "ldc2", // ARM_INS_LDC2
+  "ldcl", // ARM_INS_LDCL
+  "ldc", // ARM_INS_LDC
+  "ldmda", // ARM_INS_LDMDA
+  "ldmdb", // ARM_INS_LDMDB
+  "ldm", // ARM_INS_LDM
+  "ldmib", // ARM_INS_LDMIB
+  "ldrd", // ARM_INS_LDRD
+  "ldrex", // ARM_INS_LDREX
+  "ldrexb", // ARM_INS_LDREXB
+  "ldrexd", // ARM_INS_LDREXD
+  "ldrexh", // ARM_INS_LDREXH
+  "mcr", // ARM_INS_MCR
+  "mcr2", // ARM_INS_MCR2
+  "mcrr", // ARM_INS_MCRR
+  "mcrr2", // ARM_INS_MCRR2
+  "mla", // ARM_INS_MLA
+  "mls", // ARM_INS_MLS
+  "movt", // ARM_INS_MOVT
+  "movw", // ARM_INS_MOVW
+  "mrc", // ARM_INS_MRC
+  "mrc2", // ARM_INS_MRC2
+  "mrrc", // ARM_INS_MRRC
+  "mrrc2", // ARM_INS_MRRC2
+  "mrs", // ARM_INS_MRS
+  "msr", // ARM_INS_MSR
+  "mul", // ARM_INS_MUL
+  "asrl", // ARM_INS_ASRL
+  "dlstp", // ARM_INS_DLSTP
+  "lctp", // ARM_INS_LCTP
+  "letp", // ARM_INS_LETP
+  "lsll", // ARM_INS_LSLL
+  "lsrl", // ARM_INS_LSRL
+  "sqrshr", // ARM_INS_SQRSHR
+  "sqrshrl", // ARM_INS_SQRSHRL
+  "sqshl", // ARM_INS_SQSHL
+  "sqshll", // ARM_INS_SQSHLL
+  "srshr", // ARM_INS_SRSHR
+  "srshrl", // ARM_INS_SRSHRL
+  "uqrshl", // ARM_INS_UQRSHL
+  "uqrshll", // ARM_INS_UQRSHLL
+  "uqshl", // ARM_INS_UQSHL
+  "uqshll", // ARM_INS_UQSHLL
+  "urshr", // ARM_INS_URSHR
+  "urshrl", // ARM_INS_URSHRL
+  "vabav", // ARM_INS_VABAV
+  "vabd", // ARM_INS_VABD
+  "vabs", // ARM_INS_VABS
+  "vadc", // ARM_INS_VADC
+  "vadci", // ARM_INS_VADCI
+  "vaddlva", // ARM_INS_VADDLVA
+  "vaddlv", // ARM_INS_VADDLV
+  "vaddva", // ARM_INS_VADDVA
+  "vaddv", // ARM_INS_VADDV
+  "vadd", // ARM_INS_VADD
+  "vand", // ARM_INS_VAND
+  "vbic", // ARM_INS_VBIC
+  "vbrsr", // ARM_INS_VBRSR
+  "vcadd", // ARM_INS_VCADD
+  "vcls", // ARM_INS_VCLS
+  "vclz", // ARM_INS_VCLZ
+  "vcmla", // ARM_INS_VCMLA
+  "vcmp", // ARM_INS_VCMP
+  "vcmul", // ARM_INS_VCMUL
+  "vctp", // ARM_INS_VCTP
+  "vcvta", // ARM_INS_VCVTA
+  "vcvtm", // ARM_INS_VCVTM
+  "vcvtn", // ARM_INS_VCVTN
+  "vcvtp", // ARM_INS_VCVTP
+  "vddup", // ARM_INS_VDDUP
+  "vdup", // ARM_INS_VDUP
+  "vdwdup", // ARM_INS_VDWDUP
+  "veor", // ARM_INS_VEOR
+  "vfmas", // ARM_INS_VFMAS
+  "vfma", // ARM_INS_VFMA
+  "vfms", // ARM_INS_VFMS
+  "vhadd", // ARM_INS_VHADD
+  "vhcadd", // ARM_INS_VHCADD
+  "vhsub", // ARM_INS_VHSUB
+  "vidup", // ARM_INS_VIDUP
+  "viwdup", // ARM_INS_VIWDUP
+  "vld20", // ARM_INS_VLD20
+  "vld21", // ARM_INS_VLD21
+  "vld40", // ARM_INS_VLD40
+  "vld41", // ARM_INS_VLD41
+  "vld42", // ARM_INS_VLD42
+  "vld43", // ARM_INS_VLD43
+  "vldrb", // ARM_INS_VLDRB
+  "vldrd", // ARM_INS_VLDRD
+  "vldrh", // ARM_INS_VLDRH
+  "vldrw", // ARM_INS_VLDRW
+  "vmaxav", // ARM_INS_VMAXAV
+  "vmaxa", // ARM_INS_VMAXA
+  "vmaxnmav", // ARM_INS_VMAXNMAV
+  "vmaxnma", // ARM_INS_VMAXNMA
+  "vmaxnmv", // ARM_INS_VMAXNMV
+  "vmaxnm", // ARM_INS_VMAXNM
+  "vmaxv", // ARM_INS_VMAXV
+  "vmax", // ARM_INS_VMAX
+  "vminav", // ARM_INS_VMINAV
+  "vmina", // ARM_INS_VMINA
+  "vminnmav", // ARM_INS_VMINNMAV
+  "vminnma", // ARM_INS_VMINNMA
+  "vminnmv", // ARM_INS_VMINNMV
+  "vminnm", // ARM_INS_VMINNM
+  "vminv", // ARM_INS_VMINV
+  "vmin", // ARM_INS_VMIN
+  "vmladava", // ARM_INS_VMLADAVA
+  "vmladavax", // ARM_INS_VMLADAVAX
+  "vmladav", // ARM_INS_VMLADAV
+  "vmladavx", // ARM_INS_VMLADAVX
+  "vmlaldava", // ARM_INS_VMLALDAVA
+  "vmlaldavax", // ARM_INS_VMLALDAVAX
+  "vmlaldav", // ARM_INS_VMLALDAV
+  "vmlaldavx", // ARM_INS_VMLALDAVX
+  "vmlas", // ARM_INS_VMLAS
+  "vmla", // ARM_INS_VMLA
+  "vmlsdava", // ARM_INS_VMLSDAVA
+  "vmlsdavax", // ARM_INS_VMLSDAVAX
+  "vmlsdav", // ARM_INS_VMLSDAV
+  "vmlsdavx", // ARM_INS_VMLSDAVX
+  "vmlsldava", // ARM_INS_VMLSLDAVA
+  "vmlsldavax", // ARM_INS_VMLSLDAVAX
+  "vmlsldav", // ARM_INS_VMLSLDAV
+  "vmlsldavx", // ARM_INS_VMLSLDAVX
+  "vmovlb", // ARM_INS_VMOVLB
+  "vmovlt", // ARM_INS_VMOVLT
+  "vmovnb", // ARM_INS_VMOVNB
+  "vmovnt", // ARM_INS_VMOVNT
+  "vmulh", // ARM_INS_VMULH
+  "vmullb", // ARM_INS_VMULLB
+  "vmullt", // ARM_INS_VMULLT
+  "vmul", // ARM_INS_VMUL
+  "vmvn", // ARM_INS_VMVN
+  "vneg", // ARM_INS_VNEG
+  "vorn", // ARM_INS_VORN
+  "vorr", // ARM_INS_VORR
+  "vpnot", // ARM_INS_VPNOT
+  "vpsel", // ARM_INS_VPSEL
+  "vpst", // ARM_INS_VPST
+  "vpt", // ARM_INS_VPT
+  "vqabs", // ARM_INS_VQABS
+  "vqadd", // ARM_INS_VQADD
+  "vqdmladhx", // ARM_INS_VQDMLADHX
+  "vqdmladh", // ARM_INS_VQDMLADH
+  "vqdmlah", // ARM_INS_VQDMLAH
+  "vqdmlash", // ARM_INS_VQDMLASH
+  "vqdmlsdhx", // ARM_INS_VQDMLSDHX
+  "vqdmlsdh", // ARM_INS_VQDMLSDH
+  "vqdmulh", // ARM_INS_VQDMULH
+  "vqdmullb", // ARM_INS_VQDMULLB
+  "vqdmullt", // ARM_INS_VQDMULLT
+  "vqmovnb", // ARM_INS_VQMOVNB
+  "vqmovnt", // ARM_INS_VQMOVNT
+  "vqmovunb", // ARM_INS_VQMOVUNB
+  "vqmovunt", // ARM_INS_VQMOVUNT
+  "vqneg", // ARM_INS_VQNEG
+  "vqrdmladhx", // ARM_INS_VQRDMLADHX
+  "vqrdmladh", // ARM_INS_VQRDMLADH
+  "vqrdmlah", // ARM_INS_VQRDMLAH
+  "vqrdmlash", // ARM_INS_VQRDMLASH
+  "vqrdmlsdhx", // ARM_INS_VQRDMLSDHX
+  "vqrdmlsdh", // ARM_INS_VQRDMLSDH
+  "vqrdmulh", // ARM_INS_VQRDMULH
+  "vqrshl", // ARM_INS_VQRSHL
+  "vqrshrnb", // ARM_INS_VQRSHRNB
+  "vqrshrnt", // ARM_INS_VQRSHRNT
+  "vqrshrunb", // ARM_INS_VQRSHRUNB
+  "vqrshrunt", // ARM_INS_VQRSHRUNT
+  "vqshlu", // ARM_INS_VQSHLU
+  "vqshl", // ARM_INS_VQSHL
+  "vqshrnb", // ARM_INS_VQSHRNB
+  "vqshrnt", // ARM_INS_VQSHRNT
+  "vqshrunb", // ARM_INS_VQSHRUNB
+  "vqshrunt", // ARM_INS_VQSHRUNT
+  "vqsub", // ARM_INS_VQSUB
+  "vrev16", // ARM_INS_VREV16
+  "vrev32", // ARM_INS_VREV32
+  "vrev64", // ARM_INS_VREV64
+  "vrhadd", // ARM_INS_VRHADD
+  "vrinta", // ARM_INS_VRINTA
+  "vrintm", // ARM_INS_VRINTM
+  "vrintn", // ARM_INS_VRINTN
+  "vrintp", // ARM_INS_VRINTP
+  "vrintx", // ARM_INS_VRINTX
+  "vrintz", // ARM_INS_VRINTZ
+  "vrmlaldavha", // ARM_INS_VRMLALDAVHA
+  "vrmlaldavhax", // ARM_INS_VRMLALDAVHAX
+  "vrmlaldavh", // ARM_INS_VRMLALDAVH
+  "vrmlaldavhx", // ARM_INS_VRMLALDAVHX
+  "vrmlsldavha", // ARM_INS_VRMLSLDAVHA
+  "vrmlsldavhax", // ARM_INS_VRMLSLDAVHAX
+  "vrmlsldavh", // ARM_INS_VRMLSLDAVH
+  "vrmlsldavhx", // ARM_INS_VRMLSLDAVHX
+  "vrmulh", // ARM_INS_VRMULH
+  "vrshl", // ARM_INS_VRSHL
+  "vrshrnb", // ARM_INS_VRSHRNB
+  "vrshrnt", // ARM_INS_VRSHRNT
+  "vrshr", // ARM_INS_VRSHR
+  "vsbc", // ARM_INS_VSBC
+  "vsbci", // ARM_INS_VSBCI
+  "vshlc", // ARM_INS_VSHLC
+  "vshllb", // ARM_INS_VSHLLB
+  "vshllt", // ARM_INS_VSHLLT
+  "vshl", // ARM_INS_VSHL
+  "vshrnb", // ARM_INS_VSHRNB
+  "vshrnt", // ARM_INS_VSHRNT
+  "vshr", // ARM_INS_VSHR
+  "vsli", // ARM_INS_VSLI
+  "vsri", // ARM_INS_VSRI
+  "vst20", // ARM_INS_VST20
+  "vst21", // ARM_INS_VST21
+  "vst40", // ARM_INS_VST40
+  "vst41", // ARM_INS_VST41
+  "vst42", // ARM_INS_VST42
+  "vst43", // ARM_INS_VST43
+  "vstrb", // ARM_INS_VSTRB
+  "vstrd", // ARM_INS_VSTRD
+  "vstrh", // ARM_INS_VSTRH
+  "vstrw", // ARM_INS_VSTRW
+  "vsub", // ARM_INS_VSUB
+  "wlstp", // ARM_INS_WLSTP
+  "mvn", // ARM_INS_MVN
+  "orr", // ARM_INS_ORR
+  "pkhbt", // ARM_INS_PKHBT
+  "pkhtb", // ARM_INS_PKHTB
+  "pldw", // ARM_INS_PLDW
+  "pld", // ARM_INS_PLD
+  "pli", // ARM_INS_PLI
+  "qadd", // ARM_INS_QADD
+  "qadd16", // ARM_INS_QADD16
+  "qadd8", // ARM_INS_QADD8
+  "qasx", // ARM_INS_QASX
+  "qdadd", // ARM_INS_QDADD
+  "qdsub", // ARM_INS_QDSUB
+  "qsax", // ARM_INS_QSAX
+  "qsub", // ARM_INS_QSUB
+  "qsub16", // ARM_INS_QSUB16
+  "qsub8", // ARM_INS_QSUB8
+  "rbit", // ARM_INS_RBIT
+  "rev", // ARM_INS_REV
+  "rev16", // ARM_INS_REV16
+  "revsh", // ARM_INS_REVSH
+  "rfeda", // ARM_INS_RFEDA
+  "rfedb", // ARM_INS_RFEDB
+  "rfeia", // ARM_INS_RFEIA
+  "rfeib", // ARM_INS_RFEIB
+  "rsb", // ARM_INS_RSB
+  "rsc", // ARM_INS_RSC
+  "sadd16", // ARM_INS_SADD16
+  "sadd8", // ARM_INS_SADD8
+  "sasx", // ARM_INS_SASX
+  "sb", // ARM_INS_SB
+  "sbc", // ARM_INS_SBC
+  "sbfx", // ARM_INS_SBFX
+  "sdiv", // ARM_INS_SDIV
+  "sel", // ARM_INS_SEL
+  "setend", // ARM_INS_SETEND
+  "setpan", // ARM_INS_SETPAN
+  "sha1c", // ARM_INS_SHA1C
+  "sha1h", // ARM_INS_SHA1H
+  "sha1m", // ARM_INS_SHA1M
+  "sha1p", // ARM_INS_SHA1P
+  "sha1su0", // ARM_INS_SHA1SU0
+  "sha1su1", // ARM_INS_SHA1SU1
+  "sha256h", // ARM_INS_SHA256H
+  "sha256h2", // ARM_INS_SHA256H2
+  "sha256su0", // ARM_INS_SHA256SU0
+  "sha256su1", // ARM_INS_SHA256SU1
+  "shadd16", // ARM_INS_SHADD16
+  "shadd8", // ARM_INS_SHADD8
+  "shasx", // ARM_INS_SHASX
+  "shsax", // ARM_INS_SHSAX
+  "shsub16", // ARM_INS_SHSUB16
+  "shsub8", // ARM_INS_SHSUB8
+  "smc", // ARM_INS_SMC
+  "smlabb", // ARM_INS_SMLABB
+  "smlabt", // ARM_INS_SMLABT
+  "smlad", // ARM_INS_SMLAD
+  "smladx", // ARM_INS_SMLADX
+  "smlal", // ARM_INS_SMLAL
+  "smlalbb", // ARM_INS_SMLALBB
+  "smlalbt", // ARM_INS_SMLALBT
+  "smlald", // ARM_INS_SMLALD
+  "smlaldx", // ARM_INS_SMLALDX
+  "smlaltb", // ARM_INS_SMLALTB
+  "smlaltt", // ARM_INS_SMLALTT
+  "smlatb", // ARM_INS_SMLATB
+  "smlatt", // ARM_INS_SMLATT
+  "smlawb", // ARM_INS_SMLAWB
+  "smlawt", // ARM_INS_SMLAWT
+  "smlsd", // ARM_INS_SMLSD
+  "smlsdx", // ARM_INS_SMLSDX
+  "smlsld", // ARM_INS_SMLSLD
+  "smlsldx", // ARM_INS_SMLSLDX
+  "smmla", // ARM_INS_SMMLA
+  "smmlar", // ARM_INS_SMMLAR
+  "smmls", // ARM_INS_SMMLS
+  "smmlsr", // ARM_INS_SMMLSR
+  "smmul", // ARM_INS_SMMUL
+  "smmulr", // ARM_INS_SMMULR
+  "smuad", // ARM_INS_SMUAD
+  "smuadx", // ARM_INS_SMUADX
+  "smulbb", // ARM_INS_SMULBB
+  "smulbt", // ARM_INS_SMULBT
+  "smull", // ARM_INS_SMULL
+  "smultb", // ARM_INS_SMULTB
+  "smultt", // ARM_INS_SMULTT
+  "smulwb", // ARM_INS_SMULWB
+  "smulwt", // ARM_INS_SMULWT
+  "smusd", // ARM_INS_SMUSD
+  "smusdx", // ARM_INS_SMUSDX
+  "srsda", // ARM_INS_SRSDA
+  "srsdb", // ARM_INS_SRSDB
+  "srsia", // ARM_INS_SRSIA
+  "srsib", // ARM_INS_SRSIB
+  "ssat", // ARM_INS_SSAT
+  "ssat16", // ARM_INS_SSAT16
+  "ssax", // ARM_INS_SSAX
+  "ssub16", // ARM_INS_SSUB16
+  "ssub8", // ARM_INS_SSUB8
+  "stc2l", // ARM_INS_STC2L
+  "stc2", // ARM_INS_STC2
+  "stcl", // ARM_INS_STCL
+  "stc", // ARM_INS_STC
+  "stl", // ARM_INS_STL
+  "stlb", // ARM_INS_STLB
+  "stlex", // ARM_INS_STLEX
+  "stlexb", // ARM_INS_STLEXB
+  "stlexd", // ARM_INS_STLEXD
+  "stlexh", // ARM_INS_STLEXH
+  "stlh", // ARM_INS_STLH
+  "stmda", // ARM_INS_STMDA
+  "stmdb", // ARM_INS_STMDB
+  "stm", // ARM_INS_STM
+  "stmib", // ARM_INS_STMIB
+  "strb", // ARM_INS_STRB
+  "strd", // ARM_INS_STRD
+  "strex", // ARM_INS_STREX
+  "strexb", // ARM_INS_STREXB
+  "strexd", // ARM_INS_STREXD
+  "strexh", // ARM_INS_STREXH
+  "strh", // ARM_INS_STRH
+  "strht", // ARM_INS_STRHT
+  "sub", // ARM_INS_SUB
+  "svc", // ARM_INS_SVC
+  "swp", // ARM_INS_SWP
+  "swpb", // ARM_INS_SWPB
+  "sxtab", // ARM_INS_SXTAB
+  "sxtab16", // ARM_INS_SXTAB16
+  "sxtah", // ARM_INS_SXTAH
+  "sxtb", // ARM_INS_SXTB
+  "sxtb16", // ARM_INS_SXTB16
+  "sxth", // ARM_INS_SXTH
+  "teq", // ARM_INS_TEQ
+  "trap", // ARM_INS_TRAP
+  "tsb", // ARM_INS_TSB
+  "tst", // ARM_INS_TST
+  "uadd16", // ARM_INS_UADD16
+  "uadd8", // ARM_INS_UADD8
+  "uasx", // ARM_INS_UASX
+  "ubfx", // ARM_INS_UBFX
+  "udf", // ARM_INS_UDF
+  "udiv", // ARM_INS_UDIV
+  "uhadd16", // ARM_INS_UHADD16
+  "uhadd8", // ARM_INS_UHADD8
+  "uhasx", // ARM_INS_UHASX
+  "uhsax", // ARM_INS_UHSAX
+  "uhsub16", // ARM_INS_UHSUB16
+  "uhsub8", // ARM_INS_UHSUB8
+  "umaal", // ARM_INS_UMAAL
+  "umlal", // ARM_INS_UMLAL
+  "umull", // ARM_INS_UMULL
+  "uqadd16", // ARM_INS_UQADD16
+  "uqadd8", // ARM_INS_UQADD8
+  "uqasx", // ARM_INS_UQASX
+  "uqsax", // ARM_INS_UQSAX
+  "uqsub16", // ARM_INS_UQSUB16
+  "uqsub8", // ARM_INS_UQSUB8
+  "usad8", // ARM_INS_USAD8
+  "usada8", // ARM_INS_USADA8
+  "usat", // ARM_INS_USAT
+  "usat16", // ARM_INS_USAT16
+  "usax", // ARM_INS_USAX
+  "usub16", // ARM_INS_USUB16
+  "usub8", // ARM_INS_USUB8
+  "uxtab", // ARM_INS_UXTAB
+  "uxtab16", // ARM_INS_UXTAB16
+  "uxtah", // ARM_INS_UXTAH
+  "uxtb", // ARM_INS_UXTB
+  "uxtb16", // ARM_INS_UXTB16
+  "uxth", // ARM_INS_UXTH
+  "vabal", // ARM_INS_VABAL
+  "vaba", // ARM_INS_VABA
+  "vabdl", // ARM_INS_VABDL
+  "vacge", // ARM_INS_VACGE
+  "vacgt", // ARM_INS_VACGT
+  "vaddhn", // ARM_INS_VADDHN
+  "vaddl", // ARM_INS_VADDL
+  "vaddw", // ARM_INS_VADDW
+  "vfmab", // ARM_INS_VFMAB
+  "vfmat", // ARM_INS_VFMAT
+  "vbif", // ARM_INS_VBIF
+  "vbit", // ARM_INS_VBIT
+  "vbsl", // ARM_INS_VBSL
+  "vceq", // ARM_INS_VCEQ
+  "vcge", // ARM_INS_VCGE
+  "vcgt", // ARM_INS_VCGT
+  "vcle", // ARM_INS_VCLE
+  "vclt", // ARM_INS_VCLT
+  "vcmpe", // ARM_INS_VCMPE
+  "vcnt", // ARM_INS_VCNT
+  "vdiv", // ARM_INS_VDIV
+  "vext", // ARM_INS_VEXT
+  "vfmal", // ARM_INS_VFMAL
+  "vfmsl", // ARM_INS_VFMSL
+  "vfnma", // ARM_INS_VFNMA
+  "vfnms", // ARM_INS_VFNMS
+  "vins", // ARM_INS_VINS
+  "vjcvt", // ARM_INS_VJCVT
+  "vldmdb", // ARM_INS_VLDMDB
+  "vldmia", // ARM_INS_VLDMIA
+  "vldr", // ARM_INS_VLDR
+  "vlldm", // ARM_INS_VLLDM
+  "vlstm", // ARM_INS_VLSTM
+  "vmlal", // ARM_INS_VMLAL
+  "vmls", // ARM_INS_VMLS
+  "vmlsl", // ARM_INS_VMLSL
+  "vmmla", // ARM_INS_VMMLA
+  "vmovx", // ARM_INS_VMOVX
+  "vmovl", // ARM_INS_VMOVL
+  "vmovn", // ARM_INS_VMOVN
+  "vmsr", // ARM_INS_VMSR
+  "vmull", // ARM_INS_VMULL
+  "vnmla", // ARM_INS_VNMLA
+  "vnmls", // ARM_INS_VNMLS
+  "vnmul", // ARM_INS_VNMUL
+  "vpadal", // ARM_INS_VPADAL
+  "vpaddl", // ARM_INS_VPADDL
+  "vpadd", // ARM_INS_VPADD
+  "vpmax", // ARM_INS_VPMAX
+  "vpmin", // ARM_INS_VPMIN
+  "vqdmlal", // ARM_INS_VQDMLAL
+  "vqdmlsl", // ARM_INS_VQDMLSL
+  "vqdmull", // ARM_INS_VQDMULL
+  "vqmovun", // ARM_INS_VQMOVUN
+  "vqmovn", // ARM_INS_VQMOVN
+  "vqrdmlsh", // ARM_INS_VQRDMLSH
+  "vqrshrn", // ARM_INS_VQRSHRN
+  "vqrshrun", // ARM_INS_VQRSHRUN
+  "vqshrn", // ARM_INS_VQSHRN
+  "vqshrun", // ARM_INS_VQSHRUN
+  "vraddhn", // ARM_INS_VRADDHN
+  "vrecpe", // ARM_INS_VRECPE
+  "vrecps", // ARM_INS_VRECPS
+  "vrintr", // ARM_INS_VRINTR
+  "vrshrn", // ARM_INS_VRSHRN
+  "vrsqrte", // ARM_INS_VRSQRTE
+  "vrsqrts", // ARM_INS_VRSQRTS
+  "vrsra", // ARM_INS_VRSRA
+  "vrsubhn", // ARM_INS_VRSUBHN
+  "vscclrm", // ARM_INS_VSCCLRM
+  "vsdot", // ARM_INS_VSDOT
+  "vseleq", // ARM_INS_VSELEQ
+  "vselge", // ARM_INS_VSELGE
+  "vselgt", // ARM_INS_VSELGT
+  "vselvs", // ARM_INS_VSELVS
+  "vshll", // ARM_INS_VSHLL
+  "vshrn", // ARM_INS_VSHRN
+  "vsmmla", // ARM_INS_VSMMLA
+  "vsqrt", // ARM_INS_VSQRT
+  "vsra", // ARM_INS_VSRA
+  "vstmdb", // ARM_INS_VSTMDB
+  "vstmia", // ARM_INS_VSTMIA
+  "vstr", // ARM_INS_VSTR
+  "vsubhn", // ARM_INS_VSUBHN
+  "vsubl", // ARM_INS_VSUBL
+  "vsubw", // ARM_INS_VSUBW
+  "vsudot", // ARM_INS_VSUDOT
+  "vswp", // ARM_INS_VSWP
+  "vtbl", // ARM_INS_VTBL
+  "vtbx", // ARM_INS_VTBX
+  "vcvtr", // ARM_INS_VCVTR
+  "vtrn", // ARM_INS_VTRN
+  "vtst", // ARM_INS_VTST
+  "vudot", // ARM_INS_VUDOT
+  "vummla", // ARM_INS_VUMMLA
+  "vusdot", // ARM_INS_VUSDOT
+  "vusmmla", // ARM_INS_VUSMMLA
+  "vuzp", // ARM_INS_VUZP
+  "vzip", // ARM_INS_VZIP
+  "addw", // ARM_INS_ADDW
+  "aut", // ARM_INS_AUT
+  "autg", // ARM_INS_AUTG
+  "bfl", // ARM_INS_BFL
+  "bflx", // ARM_INS_BFLX
+  "bf", // ARM_INS_BF
+  "bfcsel", // ARM_INS_BFCSEL
+  "bfx", // ARM_INS_BFX
+  "bti", // ARM_INS_BTI
+  "bxaut", // ARM_INS_BXAUT
+  "clrm", // ARM_INS_CLRM
+  "csel", // ARM_INS_CSEL
+  "csinc", // ARM_INS_CSINC
+  "csinv", // ARM_INS_CSINV
+  "csneg", // ARM_INS_CSNEG
+  "dcps1", // ARM_INS_DCPS1
+  "dcps2", // ARM_INS_DCPS2
+  "dcps3", // ARM_INS_DCPS3
+  "dls", // ARM_INS_DLS
+  "le", // ARM_INS_LE
+  "orn", // ARM_INS_ORN
+  "pac", // ARM_INS_PAC
+  "pacbti", // ARM_INS_PACBTI
+  "pacg", // ARM_INS_PACG
+  "sg", // ARM_INS_SG
+  "subs", // ARM_INS_SUBS
+  "subw", // ARM_INS_SUBW
+  "tbb", // ARM_INS_TBB
+  "tbh", // ARM_INS_TBH
+  "tt", // ARM_INS_TT
+  "tta", // ARM_INS_TTA
+  "ttat", // ARM_INS_TTAT
+  "ttt", // ARM_INS_TTT
+  "wls", // ARM_INS_WLS
+  "blxns", // ARM_INS_BLXNS
+  "bxns", // ARM_INS_BXNS
+  "cbnz", // ARM_INS_CBNZ
+  "cbz", // ARM_INS_CBZ
+  "pop", // ARM_INS_POP
+  "push", // ARM_INS_PUSH
+  "__brkdiv0", // ARM_INS___BRKDIV0

arch/ARM/ARMGenCSOpGroup.inc

@@ -0,0 +1,115 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+  ARM_OP_GROUP_RegImmShift = 0,
+  ARM_OP_GROUP_LdStmModeOperand = 1,
+  ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 2,
+  ARM_OP_GROUP_Operand = 3,
+  ARM_OP_GROUP_ModImmOperand = 4,
+  ARM_OP_GROUP_PredicateOperand = 5,
+  ARM_OP_GROUP_SORegImmOperand = 6,
+  ARM_OP_GROUP_SORegRegOperand = 7,
+  ARM_OP_GROUP_SBitModifierOperand = 8,
+  ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
+  ARM_OP_GROUP_AddrMode2Operand = 10,
+  ARM_OP_GROUP_CPInstOperand = 11,
+  ARM_OP_GROUP_MandatoryPredicateOperand = 12,
+  ARM_OP_GROUP_ThumbITMask = 13,
+  ARM_OP_GROUP_RegisterList = 14,
+  ARM_OP_GROUP_AddrMode7Operand = 15,
+  ARM_OP_GROUP_GPRPairOperand = 16,
+  ARM_OP_GROUP_AddrMode3Operand_0 = 17,
+  ARM_OP_GROUP_PCLabel = 18,
+  ARM_OP_GROUP_AddrModePCOperand = 19,
+  ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
+  ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
+  ARM_OP_GROUP_AddrMode6Operand = 22,
+  ARM_OP_GROUP_VectorListThreeAllLanes = 23,
+  ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24,
+  ARM_OP_GROUP_VectorListThree = 25,
+  ARM_OP_GROUP_VectorListThreeSpaced = 26,
+  ARM_OP_GROUP_VectorListFourAllLanes = 27,
+  ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
+  ARM_OP_GROUP_VectorListFour = 29,
+  ARM_OP_GROUP_VectorListFourSpaced = 30,
+  ARM_OP_GROUP_T2SOOperand = 31,
+  ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 32,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 33,
+  ARM_OP_GROUP_AdrLabelOperand_0 = 34,
+  ARM_OP_GROUP_VectorIndex = 35,
+  ARM_OP_GROUP_BitfieldInvMaskImmOperand = 36,
+  ARM_OP_GROUP_PImmediate = 37,
+  ARM_OP_GROUP_VPTPredicateOperand = 38,
+  ARM_OP_GROUP_CImmediate = 39,
+  ARM_OP_GROUP_CPSIMod = 40,
+  ARM_OP_GROUP_CPSIFlag = 41,
+  ARM_OP_GROUP_MemBOption = 42,
+  ARM_OP_GROUP_FPImmOperand = 43,
+  ARM_OP_GROUP_InstSyncBOption = 44,
+  ARM_OP_GROUP_AddrMode5Operand_0 = 45,
+  ARM_OP_GROUP_CoprocOptionImm = 46,
+  ARM_OP_GROUP_PostIdxImm8s4Operand = 47,
+  ARM_OP_GROUP_AddrMode5Operand_1 = 48,
+  ARM_OP_GROUP_AddrModeImm12Operand_1 = 49,
+  ARM_OP_GROUP_AddrMode3Operand_1 = 50,
+  ARM_OP_GROUP_PostIdxImm8Operand = 51,
+  ARM_OP_GROUP_PostIdxRegOperand = 52,
+  ARM_OP_GROUP_BankedRegOperand = 53,
+  ARM_OP_GROUP_MSRMaskOperand = 54,
+  ARM_OP_GROUP_MveSaturateOp = 55,
+  ARM_OP_GROUP_VMOVModImmOperand = 56,
+  ARM_OP_GROUP_ComplexRotationOp_180_90 = 57,
+  ARM_OP_GROUP_ComplexRotationOp_90_0 = 58,
+  ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 59,
+  ARM_OP_GROUP_MVEVectorList_2 = 60,
+  ARM_OP_GROUP_MVEVectorList_4 = 61,
+  ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 62,
+  ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
+  ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
+  ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
+  ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66,
+  ARM_OP_GROUP_VPTMask = 67,
+  ARM_OP_GROUP_PKHLSLShiftImm = 68,
+  ARM_OP_GROUP_PKHASRShiftImm = 69,
+  ARM_OP_GROUP_ImmPlusOneOperand = 70,
+  ARM_OP_GROUP_SetendOperand = 71,
+  ARM_OP_GROUP_ShiftImmOperand = 72,
+  ARM_OP_GROUP_RotImmOperand = 73,
+  ARM_OP_GROUP_TraceSyncBOption = 74,
+  ARM_OP_GROUP_VectorListOneAllLanes = 75,
+  ARM_OP_GROUP_VectorListTwoAllLanes = 76,
+  ARM_OP_GROUP_NoHashImmediate = 77,
+  ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
+  ARM_OP_GROUP_VectorListOne = 79,
+  ARM_OP_GROUP_VectorListTwo = 80,
+  ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
+  ARM_OP_GROUP_VectorListTwoSpaced = 82,
+  ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
+  ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
+  ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86,
+  ARM_OP_GROUP_FBits16 = 87,
+  ARM_OP_GROUP_FBits32 = 88,
+  ARM_OP_GROUP_ThumbSRImm = 89,
+  ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
+  ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
+  ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
+  ARM_OP_GROUP_AddrModeTBB = 93,
+  ARM_OP_GROUP_AddrModeTBH = 94,
+  ARM_OP_GROUP_ThumbS4ImmOperand = 95,
+  ARM_OP_GROUP_AdrLabelOperand_2 = 96,
+  ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
+  ARM_OP_GROUP_ThumbAddrModeRROperand = 98,
+  ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99,
+  ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100,
+  ARM_OP_GROUP_ThumbAddrModeSPOperand = 101,

arch/ARM/ARMGenRegisterName.inc

@@ -1,231 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-/// getRegisterName - This method is automatically generated by tblgen
-/// from the register set description.  This returns the assembler name
-/// for the specified register.
-static const char *getRegisterName(unsigned RegNo)
-{
-
-#ifndef CAPSTONE_DIET
-  static const char AsmStrs[] = {
-  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
-  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
-  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
-  /* 39 */ 'd', '1', '0', 0,
-  /* 43 */ 'q', '1', '0', 0,
-  /* 47 */ 's', '1', '0', 0,
-  /* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
-  /* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
-  /* 83 */ 'd', '2', '0', 0,
-  /* 87 */ 's', '2', '0', 0,
-  /* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
-  /* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
-  /* 123 */ 'd', '3', '0', 0,
-  /* 127 */ 's', '3', '0', 0,
-  /* 131 */ 'd', '0', 0,
-  /* 134 */ 'q', '0', 0,
-  /* 137 */ 'm', 'v', 'f', 'r', '0', 0,
-  /* 143 */ 's', '0', 0,
-  /* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
-  /* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
-  /* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
-  /* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
-  /* 192 */ 'd', '1', '1', 0,
-  /* 196 */ 'q', '1', '1', 0,
-  /* 200 */ 's', '1', '1', 0,
-  /* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
-  /* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
-  /* 232 */ 'd', '2', '1', 0,
-  /* 236 */ 's', '2', '1', 0,
-  /* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
-  /* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
-  /* 268 */ 'd', '3', '1', 0,
-  /* 272 */ 's', '3', '1', 0,
-  /* 276 */ 'Q', '0', '_', 'Q', '1', 0,
-  /* 282 */ 'R', '0', '_', 'R', '1', 0,
-  /* 288 */ 'd', '1', 0,
-  /* 291 */ 'q', '1', 0,
-  /* 294 */ 'm', 'v', 'f', 'r', '1', 0,
-  /* 300 */ 's', '1', 0,
-  /* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
-  /* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
-  /* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
-  /* 347 */ 'd', '1', '2', 0,
-  /* 351 */ 'q', '1', '2', 0,
-  /* 355 */ 's', '1', '2', 0,
-  /* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
-  /* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
-  /* 391 */ 'd', '2', '2', 0,
-  /* 395 */ 's', '2', '2', 0,
-  /* 399 */ 'D', '0', '_', 'D', '2', 0,
-  /* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
-  /* 414 */ 'Q', '1', '_', 'Q', '2', 0,
-  /* 420 */ 'd', '2', 0,
-  /* 423 */ 'q', '2', 0,
-  /* 426 */ 'm', 'v', 'f', 'r', '2', 0,
-  /* 432 */ 's', '2', 0,
-  /* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
-  /* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
-  /* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
-  /* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
-  /* 485 */ 'd', '1', '3', 0,
-  /* 489 */ 'q', '1', '3', 0,
-  /* 493 */ 's', '1', '3', 0,
-  /* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
-  /* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
-  /* 525 */ 'd', '2', '3', 0,
-  /* 529 */ 's', '2', '3', 0,
-  /* 533 */ 'D', '1', '_', 'D', '3', 0,
-  /* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
-  /* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
-  /* 560 */ 'R', '2', '_', 'R', '3', 0,
-  /* 566 */ 'd', '3', 0,
-  /* 569 */ 'q', '3', 0,
-  /* 572 */ 'r', '3', 0,
-  /* 575 */ 's', '3', 0,
-  /* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
-  /* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
-  /* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
-  /* 625 */ 'd', '1', '4', 0,
-  /* 629 */ 'q', '1', '4', 0,
-  /* 633 */ 's', '1', '4', 0,
-  /* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
-  /* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
-  /* 669 */ 'd', '2', '4', 0,
-  /* 673 */ 's', '2', '4', 0,
-  /* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
-  /* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
-  /* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
-  /* 710 */ 'd', '4', 0,
-  /* 713 */ 'q', '4', 0,
-  /* 716 */ 'r', '4', 0,
-  /* 719 */ 's', '4', 0,
-  /* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
-  /* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
-  /* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
-  /* 765 */ 'd', '1', '5', 0,
-  /* 769 */ 'q', '1', '5', 0,
-  /* 773 */ 's', '1', '5', 0,
-  /* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
-  /* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
-  /* 805 */ 'd', '2', '5', 0,
-  /* 809 */ 's', '2', '5', 0,
-  /* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
-  /* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
-  /* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
-  /* 843 */ 'R', '4', '_', 'R', '5', 0,
-  /* 849 */ 'd', '5', 0,
-  /* 852 */ 'q', '5', 0,
-  /* 855 */ 'r', '5', 0,
-  /* 858 */ 's', '5', 0,
-  /* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
-  /* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
-  /* 893 */ 'd', '1', '6', 0,
-  /* 897 */ 's', '1', '6', 0,
-  /* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
-  /* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
-  /* 933 */ 'd', '2', '6', 0,
-  /* 937 */ 's', '2', '6', 0,
-  /* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
-  /* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
-  /* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
-  /* 977 */ 'd', '6', 0,
-  /* 980 */ 'q', '6', 0,
-  /* 983 */ 'r', '6', 0,
-  /* 986 */ 's', '6', 0,
-  /* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
-  /* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
-  /* 1017 */ 'd', '1', '7', 0,
-  /* 1021 */ 's', '1', '7', 0,
-  /* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
-  /* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
-  /* 1053 */ 'd', '2', '7', 0,
-  /* 1057 */ 's', '2', '7', 0,
-  /* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
-  /* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
-  /* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
-  /* 1094 */ 'R', '6', '_', 'R', '7', 0,
-  /* 1100 */ 'd', '7', 0,
-  /* 1103 */ 'q', '7', 0,
-  /* 1106 */ 'r', '7', 0,
-  /* 1109 */ 's', '7', 0,
-  /* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
-  /* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
-  /* 1144 */ 'd', '1', '8', 0,
-  /* 1148 */ 's', '1', '8', 0,
-  /* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
-  /* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
-  /* 1184 */ 'd', '2', '8', 0,
-  /* 1188 */ 's', '2', '8', 0,
-  /* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
-  /* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
-  /* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
-  /* 1228 */ 'd', '8', 0,
-  /* 1231 */ 'q', '8', 0,
-  /* 1234 */ 'r', '8', 0,
-  /* 1237 */ 's', '8', 0,
-  /* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
-  /* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
-  /* 1268 */ 'd', '1', '9', 0,
-  /* 1272 */ 's', '1', '9', 0,
-  /* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
-  /* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
-  /* 1304 */ 'd', '2', '9', 0,
-  /* 1308 */ 's', '2', '9', 0,
-  /* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
-  /* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
-  /* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
-  /* 1345 */ 'R', '8', '_', 'R', '9', 0,
-  /* 1351 */ 'd', '9', 0,
-  /* 1354 */ 'q', '9', 0,
-  /* 1357 */ 's', '9', 0,
-  /* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0,
-  /* 1367 */ 's', 'b', 0,
-  /* 1370 */ 'p', 'c', 0,
-  /* 1373 */ 'f', 'p', 'e', 'x', 'c', 0,
-  /* 1379 */ 'f', 'p', 's', 'i', 'd', 0,
-  /* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
-  /* 1393 */ 's', 'l', 0,
-  /* 1396 */ 'f', 'p', 0,
-  /* 1399 */ 'i', 'p', 0,
-  /* 1402 */ 's', 'p', 0,
-  /* 1405 */ 'f', 'p', 's', 'c', 'r', 0,
-  /* 1411 */ 'l', 'r', 0,
-  /* 1414 */ 'a', 'p', 's', 'r', 0,
-  /* 1419 */ 'c', 'p', 's', 'r', 0,
-  /* 1424 */ 's', 'p', 's', 'r', 0,
-  /* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0,
-  /* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  /* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  };
-
-  static const uint16_t RegAsmOffset[] = {
-    1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131,
-    288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625,
-    765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184,
-    1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980,
-    1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716,
-    855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858,
-    986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272,
-    87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533,
-    680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997,
-    1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260,
-    276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617,
-    757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749,
-    1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207,
-    1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379,
-    513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195,
-    1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363,
-    501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0,
-    157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637,
-    777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601,
-    885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593,
-    877, 1128, 67, 375, 653, 917, 1168, 107,
-  };
-
-  return AsmStrs+RegAsmOffset[RegNo-1];
-#else
-  return NULL;
-#endif
-}

arch/ARM/ARMGenRegisterName_digit.inc

@@ -1,231 +0,0 @@
-/* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-/// getRegisterName - This method is automatically generated by tblgen
-/// from the register set description.  This returns the assembler name
-/// for the specified register.
-static const char *getRegisterName_digit(unsigned RegNo)
-{
-
-#ifndef CAPSTONE_DIET
-  static const char AsmStrs[] = {
-  /* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
-  /* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
-  /* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
-  /* 39 */ 'd', '1', '0', 0,
-  /* 43 */ 'q', '1', '0', 0,
-  /* 47 */ 'r', '1', '0', 0,
-  /* 51 */ 's', '1', '0', 0,
-  /* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
-  /* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
-  /* 87 */ 'd', '2', '0', 0,
-  /* 91 */ 's', '2', '0', 0,
-  /* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
-  /* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
-  /* 127 */ 'd', '3', '0', 0,
-  /* 131 */ 's', '3', '0', 0,
-  /* 135 */ 'd', '0', 0,
-  /* 138 */ 'q', '0', 0,
-  /* 141 */ 'm', 'v', 'f', 'r', '0', 0,
-  /* 147 */ 's', '0', 0,
-  /* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
-  /* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
-  /* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
-  /* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
-  /* 196 */ 'd', '1', '1', 0,
-  /* 200 */ 'q', '1', '1', 0,
-  /* 204 */ 'r', '1', '1', 0,
-  /* 208 */ 's', '1', '1', 0,
-  /* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
-  /* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
-  /* 240 */ 'd', '2', '1', 0,
-  /* 244 */ 's', '2', '1', 0,
-  /* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
-  /* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
-  /* 276 */ 'd', '3', '1', 0,
-  /* 280 */ 's', '3', '1', 0,
-  /* 284 */ 'Q', '0', '_', 'Q', '1', 0,
-  /* 290 */ 'R', '0', '_', 'R', '1', 0,
-  /* 296 */ 'd', '1', 0,
-  /* 299 */ 'q', '1', 0,
-  /* 302 */ 'm', 'v', 'f', 'r', '1', 0,
-  /* 308 */ 's', '1', 0,
-  /* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
-  /* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
-  /* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
-  /* 355 */ 'd', '1', '2', 0,
-  /* 359 */ 'q', '1', '2', 0,
-  /* 363 */ 'r', '1', '2', 0,
-  /* 367 */ 's', '1', '2', 0,
-  /* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
-  /* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
-  /* 403 */ 'd', '2', '2', 0,
-  /* 407 */ 's', '2', '2', 0,
-  /* 411 */ 'D', '0', '_', 'D', '2', 0,
-  /* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
-  /* 426 */ 'Q', '1', '_', 'Q', '2', 0,
-  /* 432 */ 'd', '2', 0,
-  /* 435 */ 'q', '2', 0,
-  /* 438 */ 'm', 'v', 'f', 'r', '2', 0,
-  /* 444 */ 's', '2', 0,
-  /* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
-  /* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
-  /* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
-  /* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
-  /* 497 */ 'd', '1', '3', 0,
-  /* 501 */ 'q', '1', '3', 0,
-  /* 505 */ 'r', '1', '3', 0,
-  /* 509 */ 's', '1', '3', 0,
-  /* 513 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
-  /* 529 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
-  /* 541 */ 'd', '2', '3', 0,
-  /* 545 */ 's', '2', '3', 0,
-  /* 549 */ 'D', '1', '_', 'D', '3', 0,
-  /* 555 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
-  /* 564 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
-  /* 576 */ 'R', '2', '_', 'R', '3', 0,
-  /* 582 */ 'd', '3', 0,
-  /* 585 */ 'q', '3', 0,
-  /* 588 */ 'r', '3', 0,
-  /* 591 */ 's', '3', 0,
-  /* 594 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
-  /* 609 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
-  /* 625 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
-  /* 641 */ 'd', '1', '4', 0,
-  /* 645 */ 'q', '1', '4', 0,
-  /* 649 */ 'r', '1', '4', 0,
-  /* 653 */ 's', '1', '4', 0,
-  /* 657 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
-  /* 673 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
-  /* 689 */ 'd', '2', '4', 0,
-  /* 693 */ 's', '2', '4', 0,
-  /* 697 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
-  /* 706 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
-  /* 718 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
-  /* 730 */ 'd', '4', 0,
-  /* 733 */ 'q', '4', 0,
-  /* 736 */ 'r', '4', 0,
-  /* 739 */ 's', '4', 0,
-  /* 742 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
-  /* 757 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
-  /* 769 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
-  /* 785 */ 'd', '1', '5', 0,
-  /* 789 */ 'q', '1', '5', 0,
-  /* 793 */ 's', '1', '5', 0,
-  /* 797 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
-  /* 813 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
-  /* 825 */ 'd', '2', '5', 0,
-  /* 829 */ 's', '2', '5', 0,
-  /* 833 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
-  /* 842 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
-  /* 851 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
-  /* 863 */ 'R', '4', '_', 'R', '5', 0,
-  /* 869 */ 'd', '5', 0,
-  /* 872 */ 'q', '5', 0,
-  /* 875 */ 'r', '5', 0,
-  /* 878 */ 's', '5', 0,
-  /* 881 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
-  /* 897 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
-  /* 913 */ 'd', '1', '6', 0,
-  /* 917 */ 's', '1', '6', 0,
-  /* 921 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
-  /* 937 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
-  /* 953 */ 'd', '2', '6', 0,
-  /* 957 */ 's', '2', '6', 0,
-  /* 961 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
-  /* 973 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
-  /* 985 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
-  /* 997 */ 'd', '6', 0,
-  /* 1000 */ 'q', '6', 0,
-  /* 1003 */ 'r', '6', 0,
-  /* 1006 */ 's', '6', 0,
-  /* 1009 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
-  /* 1025 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
-  /* 1037 */ 'd', '1', '7', 0,
-  /* 1041 */ 's', '1', '7', 0,
-  /* 1045 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
-  /* 1061 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
-  /* 1073 */ 'd', '2', '7', 0,
-  /* 1077 */ 's', '2', '7', 0,
-  /* 1081 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
-  /* 1093 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
-  /* 1102 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
-  /* 1114 */ 'R', '6', '_', 'R', '7', 0,
-  /* 1120 */ 'd', '7', 0,
-  /* 1123 */ 'q', '7', 0,
-  /* 1126 */ 'r', '7', 0,
-  /* 1129 */ 's', '7', 0,
-  /* 1132 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
-  /* 1148 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
-  /* 1164 */ 'd', '1', '8', 0,
-  /* 1168 */ 's', '1', '8', 0,
-  /* 1172 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
-  /* 1188 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
-  /* 1204 */ 'd', '2', '8', 0,
-  /* 1208 */ 's', '2', '8', 0,
-  /* 1212 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
-  /* 1224 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
-  /* 1236 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
-  /* 1248 */ 'd', '8', 0,
-  /* 1251 */ 'q', '8', 0,
-  /* 1254 */ 'r', '8', 0,
-  /* 1257 */ 's', '8', 0,
-  /* 1260 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
-  /* 1276 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
-  /* 1288 */ 'd', '1', '9', 0,
-  /* 1292 */ 's', '1', '9', 0,
-  /* 1296 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
-  /* 1312 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
-  /* 1324 */ 'd', '2', '9', 0,
-  /* 1328 */ 's', '2', '9', 0,
-  /* 1332 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
-  /* 1344 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
-  /* 1353 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
-  /* 1365 */ 'R', '8', '_', 'R', '9', 0,
-  /* 1371 */ 'd', '9', 0,
-  /* 1374 */ 'q', '9', 0,
-  /* 1377 */ 'r', '9', 0,
-  /* 1380 */ 's', '9', 0,
-  /* 1383 */ 'R', '1', '2', '_', 'S', 'P', 0,
-  /* 1390 */ 'p', 'c', 0,
-  /* 1393 */ 'f', 'p', 'e', 'x', 'c', 0,
-  /* 1399 */ 'f', 'p', 's', 'i', 'd', 0,
-  /* 1405 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
-  /* 1413 */ 'f', 'p', 's', 'c', 'r', 0,
-  /* 1419 */ 'a', 'p', 's', 'r', 0,
-  /* 1424 */ 'c', 'p', 's', 'r', 0,
-  /* 1429 */ 's', 'p', 's', 'r', 0,
-  /* 1434 */ 'f', 'p', 'i', 'n', 's', 't', 0,
-  /* 1441 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  /* 1452 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
-  };
-
-  static const uint16_t RegAsmOffset[] = {
-    1419, 1452, 1424, 1393, 1434, 1413, 1441, 1399, 1405, 649, 1390, 505, 1429, 135,
-    296, 432, 582, 730, 869, 997, 1120, 1248, 1371, 39, 196, 355, 497, 641,
-    785, 913, 1037, 1164, 1288, 87, 240, 403, 541, 689, 825, 953, 1073, 1204,
-    1324, 127, 276, 447, 141, 302, 438, 138, 299, 435, 585, 733, 872, 1000,
-    1123, 1251, 1374, 43, 200, 359, 501, 645, 789, 144, 305, 441, 588, 736,
-    875, 1003, 1126, 1254, 1377, 47, 204, 363, 147, 308, 444, 591, 739, 878,
-    1006, 1129, 1257, 1380, 51, 208, 367, 509, 653, 793, 917, 1041, 1168, 1292,
-    91, 244, 407, 545, 693, 829, 957, 1077, 1208, 1328, 131, 280, 411, 549,
-    700, 836, 967, 1087, 1218, 1338, 6, 167, 317, 461, 601, 749, 889, 1017,
-    1140, 1268, 63, 232, 379, 521, 665, 805, 929, 1053, 1180, 1304, 103, 268,
-    284, 426, 570, 724, 857, 991, 1108, 1242, 1359, 32, 180, 347, 489, 633,
-    777, 564, 718, 851, 985, 1102, 1236, 1353, 26, 174, 340, 481, 625, 769,
-    1383, 290, 576, 863, 1114, 1365, 188, 417, 555, 709, 842, 976, 1093, 1227,
-    1344, 16, 150, 328, 469, 613, 757, 901, 1025, 1152, 1276, 75, 212, 391,
-    529, 677, 813, 941, 1061, 1192, 1312, 115, 248, 697, 833, 964, 1084, 1215,
-    1335, 3, 164, 314, 458, 597, 745, 885, 1013, 1136, 1264, 59, 228, 375,
-    517, 661, 801, 925, 1049, 1176, 1300, 99, 264, 961, 1081, 1212, 1332, 0,
-    161, 311, 455, 594, 742, 881, 1009, 1132, 1260, 55, 224, 371, 513, 657,
-    797, 921, 1045, 1172, 1296, 95, 260, 420, 712, 979, 1230, 19, 332, 617,
-    905, 1156, 79, 395, 681, 945, 1196, 119, 706, 973, 1224, 13, 325, 609,
-    897, 1148, 71, 387, 673, 937, 1188, 111,
-  };
-
-  return AsmStrs+RegAsmOffset[RegNo-1];
-#else
-  return NULL;
-#endif
-}

arch/ARM/ARMGenSubtargetInfo.inc

@@ -1,162 +1,244 @@
-
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-|* Subtarget Enumeration Source Fragment                                      *|
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
 
+/* Do not edit. */
+
+/* Capstone's LLVM TableGen Backends: */
+/* https://github.com/capstone-engine/llvm-capstone */
+
+#ifdef GET_SUBTARGETINFO_ENUM
+#undef GET_SUBTARGETINFO_ENUM
 
 enum {
-  ARM_ARMv2 = 0,
+  ARM_ARMv4 = 0,
-  ARM_ARMv2a = 1,
+  ARM_ARMv4t = 1,
-  ARM_ARMv3 = 2,
+  ARM_ARMv5t = 2,
-  ARM_ARMv3m = 3,
+  ARM_ARMv5te = 3,
-  ARM_ARMv4 = 4,
+  ARM_ARMv5tej = 4,
-  ARM_ARMv4t = 5,
+  ARM_ARMv6 = 5,
-  ARM_ARMv5t = 6,
+  ARM_ARMv6j = 6,
-  ARM_ARMv5te = 7,
+  ARM_ARMv6k = 7,
-  ARM_ARMv5tej = 8,
+  ARM_ARMv6kz = 8,
-  ARM_ARMv6 = 9,
+  ARM_ARMv6m = 9,
-  ARM_ARMv6j = 10,
+  ARM_ARMv6sm = 10,
-  ARM_ARMv6k = 11,
+  ARM_ARMv6t2 = 11,
-  ARM_ARMv6kz = 12,
+  ARM_ARMv7a = 12,
-  ARM_ARMv6m = 13,
+  ARM_ARMv7em = 13,
-  ARM_ARMv6sm = 14,
+  ARM_ARMv7k = 14,
-  ARM_ARMv6t2 = 15,
+  ARM_ARMv7m = 15,
-  ARM_ARMv7a = 16,
+  ARM_ARMv7r = 16,
-  ARM_ARMv7em = 17,
+  ARM_ARMv7s = 17,
-  ARM_ARMv7k = 18,
+  ARM_ARMv7ve = 18,
-  ARM_ARMv7m = 19,
+  ARM_ARMv8a = 19,
-  ARM_ARMv7r = 20,
+  ARM_ARMv8mBaseline = 20,
-  ARM_ARMv7s = 21,
+  ARM_ARMv8mMainline = 21,
-  ARM_ARMv7ve = 22,
+  ARM_ARMv8r = 22,
-  ARM_ARMv8a = 23,
+  ARM_ARMv9a = 23,
-  ARM_ARMv8mBaseline = 24,
+  ARM_ARMv81a = 24,
-  ARM_ARMv8mMainline = 25,
+  ARM_ARMv81mMainline = 25,
-  ARM_ARMv8r = 26,
+  ARM_ARMv82a = 26,
-  ARM_ARMv81a = 27,
+  ARM_ARMv83a = 27,
-  ARM_ARMv82a = 28,
+  ARM_ARMv84a = 28,
-  ARM_ARMv83a = 29,
+  ARM_ARMv85a = 29,
-  ARM_ARMv84a = 30,
+  ARM_ARMv86a = 30,
-  ARM_Feature8MSecExt = 31,
+  ARM_ARMv87a = 31,
-  ARM_FeatureAClass = 32,
+  ARM_ARMv88a = 32,
-  ARM_FeatureAES = 33,
+  ARM_ARMv89a = 33,
-  ARM_FeatureAcquireRelease = 34,
+  ARM_ARMv91a = 34,
-  ARM_FeatureAvoidMOVsShOp = 35,
+  ARM_ARMv92a = 35,
-  ARM_FeatureAvoidPartialCPSR = 36,
+  ARM_ARMv93a = 36,
-  ARM_FeatureCRC = 37,
+  ARM_ARMv94a = 37,
-  ARM_FeatureCheapPredicableCPSR = 38,
+  ARM_Feature8MSecExt = 38,
-  ARM_FeatureCheckVLDnAlign = 39,
+  ARM_FeatureAAPCSFrameChain = 39,
-  ARM_FeatureCrypto = 40,
+  ARM_FeatureAAPCSFrameChainLeaf = 40,
-  ARM_FeatureD16 = 41,
+  ARM_FeatureAClass = 41,
-  ARM_FeatureDB = 42,
+  ARM_FeatureAES = 42,
-  ARM_FeatureDFB = 43,
+  ARM_FeatureAcquireRelease = 43,
-  ARM_FeatureDSP = 44,
+  ARM_FeatureAtomics32 = 44,
-  ARM_FeatureDontWidenVMOVS = 45,
+  ARM_FeatureAvoidMOVsShOp = 45,
-  ARM_FeatureDotProd = 46,
+  ARM_FeatureAvoidPartialCPSR = 46,
-  ARM_FeatureExecuteOnly = 47,
+  ARM_FeatureBF16 = 47,
-  ARM_FeatureExpandMLx = 48,
+  ARM_FeatureCLRBHB = 48,
-  ARM_FeatureFP16 = 49,
+  ARM_FeatureCRC = 49,
-  ARM_FeatureFPAO = 50,
+  ARM_FeatureCheapPredicableCPSR = 50,
-  ARM_FeatureFPARMv8 = 51,
+  ARM_FeatureCheckVLDnAlign = 51,
-  ARM_FeatureFullFP16 = 52,
+  ARM_FeatureCoprocCDE0 = 52,
-  ARM_FeatureFuseAES = 53,
+  ARM_FeatureCoprocCDE1 = 53,
-  ARM_FeatureFuseLiterals = 54,
+  ARM_FeatureCoprocCDE2 = 54,
-  ARM_FeatureHWDivARM = 55,
+  ARM_FeatureCoprocCDE3 = 55,
-  ARM_FeatureHWDivThumb = 56,
+  ARM_FeatureCoprocCDE4 = 56,
-  ARM_FeatureHasNoBranchPredictor = 57,
+  ARM_FeatureCoprocCDE5 = 57,
-  ARM_FeatureHasRetAddrStack = 58,
+  ARM_FeatureCoprocCDE6 = 58,
-  ARM_FeatureHasSlowFPVMLx = 59,
+  ARM_FeatureCoprocCDE7 = 59,
-  ARM_FeatureHasVMLxHazards = 60,
+  ARM_FeatureCrypto = 60,
-  ARM_FeatureLongCalls = 61,
+  ARM_FeatureD32 = 61,
-  ARM_FeatureMClass = 62,
+  ARM_FeatureDB = 62,
-  ARM_FeatureMP = 63,
+  ARM_FeatureDFB = 63,
-  ARM_FeatureMuxedUnits = 64,
+  ARM_FeatureDSP = 64,
-  ARM_FeatureNEON = 65,
+  ARM_FeatureDontWidenVMOVS = 65,
-  ARM_FeatureNEONForFP = 66,
+  ARM_FeatureDotProd = 66,
-  ARM_FeatureNEONForFPMovs = 67,
+  ARM_FeatureExecuteOnly = 67,
-  ARM_FeatureNaClTrap = 68,
+  ARM_FeatureExpandMLx = 68,
-  ARM_FeatureNoARM = 69,
+  ARM_FeatureFP16 = 69,
-  ARM_FeatureNoMovt = 70,
+  ARM_FeatureFP16FML = 70,
-  ARM_FeatureNoNegativeImmediates = 71,
+  ARM_FeatureFP64 = 71,
-  ARM_FeatureNoPostRASched = 72,
+  ARM_FeatureFPAO = 72,
-  ARM_FeatureNonpipelinedVFP = 73,
+  ARM_FeatureFPARMv8 = 73,
-  ARM_FeaturePerfMon = 74,
+  ARM_FeatureFPARMv8_D16 = 74,
-  ARM_FeaturePref32BitThumb = 75,
+  ARM_FeatureFPARMv8_D16_SP = 75,
-  ARM_FeaturePrefISHSTBarrier = 76,
+  ARM_FeatureFPARMv8_SP = 76,
-  ARM_FeaturePreferVMOVSR = 77,
+  ARM_FeatureFPRegs = 77,
-  ARM_FeatureProfUnpredicate = 78,
+  ARM_FeatureFPRegs16 = 78,
-  ARM_FeatureRAS = 79,
+  ARM_FeatureFPRegs64 = 79,
-  ARM_FeatureRClass = 80,
+  ARM_FeatureFixCMSE_CVE_2021_35465 = 80,
-  ARM_FeatureReadTp = 81,
+  ARM_FeatureFixCortexA57AES1742098 = 81,
-  ARM_FeatureReserveR9 = 82,
+  ARM_FeatureFullFP16 = 82,
-  ARM_FeatureSHA2 = 83,
+  ARM_FeatureFuseAES = 83,
-  ARM_FeatureSlowFPBrcc = 84,
+  ARM_FeatureFuseLiterals = 84,
-  ARM_FeatureSlowLoadDSubreg = 85,
+  ARM_FeatureHWDivARM = 85,
-  ARM_FeatureSlowOddRegister = 86,
+  ARM_FeatureHWDivThumb = 86,
-  ARM_FeatureSlowVDUP32 = 87,
+  ARM_FeatureHardenSlsBlr = 87,
-  ARM_FeatureSlowVGETLNi32 = 88,
+  ARM_FeatureHardenSlsNoComdat = 88,
-  ARM_FeatureSplatVFPToNeon = 89,
+  ARM_FeatureHardenSlsRetBr = 89,
-  ARM_FeatureStrictAlign = 90,
+  ARM_FeatureHasNoBranchPredictor = 90,
-  ARM_FeatureThumb2 = 91,
+  ARM_FeatureHasRetAddrStack = 91,
-  ARM_FeatureTrustZone = 92,
+  ARM_FeatureHasSlowFPVFMx = 92,
-  ARM_FeatureUseAA = 93,
+  ARM_FeatureHasSlowFPVMLx = 93,
-  ARM_FeatureUseMISched = 94,
+  ARM_FeatureHasVMLxHazards = 94,
-  ARM_FeatureV7Clrex = 95,
+  ARM_FeatureLOB = 95,
-  ARM_FeatureVFP2 = 96,
+  ARM_FeatureLongCalls = 96,
-  ARM_FeatureVFP3 = 97,
+  ARM_FeatureMClass = 97,
-  ARM_FeatureVFP4 = 98,
+  ARM_FeatureMP = 98,
-  ARM_FeatureVFPOnlySP = 99,
+  ARM_FeatureMVEVectorCostFactor1 = 99,
-  ARM_FeatureVMLxForwarding = 100,
+  ARM_FeatureMVEVectorCostFactor2 = 100,
-  ARM_FeatureVirtualization = 101,
+  ARM_FeatureMVEVectorCostFactor4 = 101,
-  ARM_FeatureZCZeroing = 102,
+  ARM_FeatureMatMulInt8 = 102,
-  ARM_HasV4TOps = 103,
+  ARM_FeatureMuxedUnits = 103,
-  ARM_HasV5TEOps = 104,
+  ARM_FeatureNEON = 104,
-  ARM_HasV5TOps = 105,
+  ARM_FeatureNEONForFP = 105,
-  ARM_HasV6KOps = 106,
+  ARM_FeatureNEONForFPMovs = 106,
-  ARM_HasV6MOps = 107,
+  ARM_FeatureNaClTrap = 107,
-  ARM_HasV6Ops = 108,
+  ARM_FeatureNoARM = 108,
-  ARM_HasV6T2Ops = 109,
+  ARM_FeatureNoBTIAtReturnTwice = 109,
-  ARM_HasV7Ops = 110,
+  ARM_FeatureNoMovt = 110,
-  ARM_HasV8MBaselineOps = 111,
+  ARM_FeatureNoNegativeImmediates = 111,
-  ARM_HasV8MMainlineOps = 112,
+  ARM_FeatureNoPostRASched = 112,
-  ARM_HasV8Ops = 113,
+  ARM_FeatureNonpipelinedVFP = 113,
-  ARM_HasV8_1aOps = 114,
+  ARM_FeaturePACBTI = 114,
-  ARM_HasV8_2aOps = 115,
+  ARM_FeaturePerfMon = 115,
-  ARM_HasV8_3aOps = 116,
+  ARM_FeaturePref32BitThumb = 116,
-  ARM_HasV8_4aOps = 117,
+  ARM_FeaturePrefISHSTBarrier = 117,
-  ARM_IWMMXT = 118,
+  ARM_FeaturePrefLoopAlign32 = 118,
-  ARM_IWMMXT2 = 119,
+  ARM_FeaturePreferVMOVSR = 119,
-  ARM_ModeSoftFloat = 120,
+  ARM_FeatureProfUnpredicate = 120,
-  ARM_ModeThumb = 121,
+  ARM_FeatureRAS = 121,
-  ARM_ProcA5 = 122,
+  ARM_FeatureRClass = 122,
-  ARM_ProcA7 = 123,
+  ARM_FeatureReadTp = 123,
-  ARM_ProcA8 = 124,
+  ARM_FeatureReserveR9 = 124,
-  ARM_ProcA9 = 125,
+  ARM_FeatureSB = 125,
-  ARM_ProcA12 = 126,
+  ARM_FeatureSHA2 = 126,
-  ARM_ProcA15 = 127,
+  ARM_FeatureSlowFPBrcc = 127,
-  ARM_ProcA17 = 128,
+  ARM_FeatureSlowLoadDSubreg = 128,
-  ARM_ProcA32 = 129,
+  ARM_FeatureSlowOddRegister = 129,
-  ARM_ProcA35 = 130,
+  ARM_FeatureSlowVDUP32 = 130,
-  ARM_ProcA53 = 131,
+  ARM_FeatureSlowVGETLNi32 = 131,
-  ARM_ProcA55 = 132,
+  ARM_FeatureSplatVFPToNeon = 132,
-  ARM_ProcA57 = 133,
+  ARM_FeatureStrictAlign = 133,
-  ARM_ProcA72 = 134,
+  ARM_FeatureThumb2 = 134,
-  ARM_ProcA73 = 135,
+  ARM_FeatureTrustZone = 135,
-  ARM_ProcA75 = 136,
+  ARM_FeatureUseMIPipeliner = 136,
-  ARM_ProcExynosM1 = 137,
+  ARM_FeatureUseMISched = 137,
-  ARM_ProcKrait = 138,
+  ARM_FeatureUseWideStrideVFP = 138,
-  ARM_ProcKryo = 139,
+  ARM_FeatureV7Clrex = 139,
-  ARM_ProcM3 = 140,
+  ARM_FeatureVFP2 = 140,
-  ARM_ProcR4 = 141,
+  ARM_FeatureVFP2_SP = 141,
-  ARM_ProcR5 = 142,
+  ARM_FeatureVFP3 = 142,
-  ARM_ProcR7 = 143,
+  ARM_FeatureVFP3_D16 = 143,
-  ARM_ProcR52 = 144,
+  ARM_FeatureVFP3_D16_SP = 144,
-  ARM_ProcSwift = 145,
+  ARM_FeatureVFP3_SP = 145,
-  ARM_XScale = 146,
+  ARM_FeatureVFP4 = 146,
+  ARM_FeatureVFP4_D16 = 147,
+  ARM_FeatureVFP4_D16_SP = 148,
+  ARM_FeatureVFP4_SP = 149,
+  ARM_FeatureVMLxForwarding = 150,
+  ARM_FeatureVirtualization = 151,
+  ARM_FeatureZCZeroing = 152,
+  ARM_HasCDEOps = 153,
+  ARM_HasMVEFloatOps = 154,
+  ARM_HasMVEIntegerOps = 155,
+  ARM_HasV4TOps = 156,
+  ARM_HasV5TEOps = 157,
+  ARM_HasV5TOps = 158,
+  ARM_HasV6KOps = 159,
+  ARM_HasV6MOps = 160,
+  ARM_HasV6Ops = 161,
+  ARM_HasV6T2Ops = 162,
+  ARM_HasV7Ops = 163,
+  ARM_HasV8MBaselineOps = 164,
+  ARM_HasV8MMainlineOps = 165,
+  ARM_HasV8Ops = 166,
+  ARM_HasV8_1MMainlineOps = 167,
+  ARM_HasV8_1aOps = 168,
+  ARM_HasV8_2aOps = 169,
+  ARM_HasV8_3aOps = 170,
+  ARM_HasV8_4aOps = 171,
+  ARM_HasV8_5aOps = 172,
+  ARM_HasV8_6aOps = 173,
+  ARM_HasV8_7aOps = 174,
+  ARM_HasV8_8aOps = 175,
+  ARM_HasV8_9aOps = 176,
+  ARM_HasV9_0aOps = 177,
+  ARM_HasV9_1aOps = 178,
+  ARM_HasV9_2aOps = 179,
+  ARM_HasV9_3aOps = 180,
+  ARM_HasV9_4aOps = 181,
+  ARM_IWMMXT = 182,
+  ARM_IWMMXT2 = 183,
+  ARM_ModeBigEndianInstructions = 184,
+  ARM_ModeSoftFloat = 185,
+  ARM_ModeThumb = 186,
+  ARM_ProcA5 = 187,
+  ARM_ProcA7 = 188,
+  ARM_ProcA8 = 189,
+  ARM_ProcA9 = 190,
+  ARM_ProcA12 = 191,
+  ARM_ProcA15 = 192,
+  ARM_ProcA17 = 193,
+  ARM_ProcA32 = 194,
+  ARM_ProcA35 = 195,
+  ARM_ProcA53 = 196,
+  ARM_ProcA55 = 197,
+  ARM_ProcA57 = 198,
+  ARM_ProcA72 = 199,
+  ARM_ProcA73 = 200,
+  ARM_ProcA75 = 201,
+  ARM_ProcA76 = 202,
+  ARM_ProcA77 = 203,
+  ARM_ProcA78 = 204,
+  ARM_ProcA78C = 205,
+  ARM_ProcA710 = 206,
+  ARM_ProcExynos = 207,
+  ARM_ProcKrait = 208,
+  ARM_ProcKryo = 209,
+  ARM_ProcM3 = 210,
+  ARM_ProcM7 = 211,
+  ARM_ProcR4 = 212,
+  ARM_ProcR5 = 213,
+  ARM_ProcR7 = 214,
+  ARM_ProcR52 = 215,
+  ARM_ProcSwift = 216,
+  ARM_ProcV1 = 217,
+  ARM_ProcX1 = 218,
+  ARM_ProcX1C = 219,
+  ARM_XScale = 220,
+  ARM_NumSubtargetFeatures = 221
 };
+#endif // GET_SUBTARGETINFO_ENUM
+
+
 

arch/ARM/ARMGenSystemRegister.inc

@@ -1,270 +1,475 @@
-
 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
 
-/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|*                                                                            *|
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
-|* GenSystemRegister Source Fragment                                          *|
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
-|*                                                                            *|
-|* Automatically generated file, do not edit!                                 *|
-|*                                                                            *|
-\*===----------------------------------------------------------------------===*/
 
+/* Do not edit. */
 
-enum BankedRegValues {
+/* Capstone's LLVM TableGen Backends: */
-	elr_hyp = 0,
+/* https://github.com/capstone-engine/llvm-capstone */
-	lr_abt = 1,
-	lr_fiq = 2,
-	lr_irq = 3,
-	lr_mon = 4,
-	lr_svc = 5,
-	lr_und = 6,
-	lr_usr = 7,
-	r10_fiq = 8,
-	r10_usr = 9,
-	r11_fiq = 10,
-	r11_usr = 11,
-	r12_fiq = 12,
-	r12_usr = 13,
-	r8_fiq = 14,
-	r8_usr = 15,
-	r9_fiq = 16,
-	r9_usr = 17,
-	sp_abt = 18,
-	sp_fiq = 19,
-	sp_hyp = 20,
-	sp_irq = 21,
-	sp_mon = 22,
-	sp_svc = 23,
-	sp_und = 24,
-	sp_usr = 25,
-	spsr_abt = 26,
-	spsr_fiq = 27,
-	spsr_hyp = 28,
-	spsr_irq = 29,
-	spsr_mon = 30,
-	spsr_svc = 31,
-	spsr_und = 32,
-};
 
-static const MClassSysReg MClassSysRegsList[] = {
+#ifdef GET_BANKEDREG_DECL
-  { "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 0
+#endif
-  { "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 1
-  { "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 2
-  { "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 3
-  { "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 4
-  { "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 5
-  { "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 6
-  { "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 7
-  { "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800,  { 0 }  }, // 8
-  { "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800,  { 0 }  }, // 9
-  { "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801,  { 0 }  }, // 10
-  { "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801,  { 0 }  }, // 11
-  { "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802,  { 0 }  }, // 12
-  { "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802,  { 0 }  }, // 13
-  { "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803,  { 0 }  }, // 14
-  { "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803,  { 0 }  }, // 15
-  { "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805,  { 0 }  }, // 16
-  { "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806,  { 0 }  }, // 17
-  { "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807,  { 0 }  }, // 18
-  { "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808,  { 0 }  }, // 19
-  { "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809,  { 0 }  }, // 20
-  { "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 21
-  { "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 22
-  { "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810,  { 0 }  }, // 23
-  { "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 24
-  { "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 25
-  { "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 26
-  { "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814,  { 0 }  }, // 27
-  { "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 28
-  { "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 29
-  { "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 30
-  { "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 31
-  { "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890,  { 0 }  }, // 32
-  { "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 33
-  { "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 34
-  { "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 35
-  { "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 36
-};
 
-static const BankedReg BankedRegsList[] = {
+#ifdef GET_MCLASSSYSREG_DECL
-  { "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
+#endif
-  { "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
-  { "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
-  { "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3
-  { "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4
-  { "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5
-  { "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6
-  { "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7
-  { "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8
-  { "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9
-  { "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10
-  { "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11
-  { "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12
-  { "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13
-  { "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14
-  { "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15
-  { "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16
-  { "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17
-  { "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18
-  { "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19
-  { "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20
-  { "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21
-  { "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22
-  { "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23
-  { "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24
-  { "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25
-  { "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26
-  { "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27
-  { "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28
-  { "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29
-  { "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30
-  { "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31
-  { "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
-};
 
-const MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
+#ifdef GET_BANKEDREG_DECL
-{
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name);
-  unsigned int i;
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
-  static const struct IndexType Index[] = {
+#endif
-    { 0x0, 0 },
+
-    { 0x1, 2 },
+#ifdef GET_MCLASSSYSREG_DECL
-    { 0x2, 4 },
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name);
-    { 0x3, 6 },
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
-    { 0x100, 8 },
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8);
-    { 0x101, 10 },
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
-    { 0x102, 12 },
+#endif
-    { 0x103, 14 },
+
-    { 0x105, 16 },
+#ifdef GET_BANKEDREG_IMPL
-    { 0x106, 17 },
+static const ARMBankedReg_BankedReg BankedRegsList[] = {
-    { 0x107, 18 },
+  { "elr_hyp", { ARM_BANKEDREG_ELR_HYP }, 0x1E }, // 0
-    { 0x108, 19 },
+  { "lr_abt", { ARM_BANKEDREG_LR_ABT }, 0x14 }, // 1
-    { 0x109, 20 },
+  { "lr_fiq", { ARM_BANKEDREG_LR_FIQ }, 0xE }, // 2
-    { 0x10A, 21 },
+  { "lr_irq", { ARM_BANKEDREG_LR_IRQ }, 0x10 }, // 3
-    { 0x10B, 22 },
+  { "lr_mon", { ARM_BANKEDREG_LR_MON }, 0x1C }, // 4
-    { 0x110, 23 },
+  { "lr_svc", { ARM_BANKEDREG_LR_SVC }, 0x12 }, // 5
-    { 0x111, 24 },
+  { "lr_und", { ARM_BANKEDREG_LR_UND }, 0x16 }, // 6
-    { 0x112, 25 },
+  { "lr_usr", { ARM_BANKEDREG_LR_USR }, 0x6 }, // 7
-    { 0x113, 26 },
+  { "r10_fiq", { ARM_BANKEDREG_R10_FIQ }, 0xA }, // 8
-    { 0x114, 27 },
+  { "r10_usr", { ARM_BANKEDREG_R10_USR }, 0x2 }, // 9
-    { 0x188, 28 },
+  { "r11_fiq", { ARM_BANKEDREG_R11_FIQ }, 0xB }, // 10
-    { 0x189, 29 },
+  { "r11_usr", { ARM_BANKEDREG_R11_USR }, 0x3 }, // 11
-    { 0x18A, 30 },
+  { "r12_fiq", { ARM_BANKEDREG_R12_FIQ }, 0xC }, // 12
-    { 0x18B, 31 },
+  { "r12_usr", { ARM_BANKEDREG_R12_USR }, 0x4 }, // 13
-    { 0x190, 32 },
+  { "r8_fiq", { ARM_BANKEDREG_R8_FIQ }, 0x8 }, // 14
-    { 0x191, 33 },
+  { "r8_usr", { ARM_BANKEDREG_R8_USR }, 0x0 }, // 15
-    { 0x193, 34 },
+  { "r9_fiq", { ARM_BANKEDREG_R9_FIQ }, 0x9 }, // 16
-    { 0x194, 35 },
+  { "r9_usr", { ARM_BANKEDREG_R9_USR }, 0x1 }, // 17
-    { 0x198, 36 },
+  { "spsr_abt", { ARM_BANKEDREG_SPSR_ABT }, 0x34 }, // 18
-    { 0x200, 9 },
+  { "spsr_fiq", { ARM_BANKEDREG_SPSR_FIQ }, 0x2E }, // 19
-    { 0x201, 11 },
+  { "spsr_hyp", { ARM_BANKEDREG_SPSR_HYP }, 0x3E }, // 20
-    { 0x202, 13 },
+  { "spsr_irq", { ARM_BANKEDREG_SPSR_IRQ }, 0x30 }, // 21
-    { 0x203, 15 },
+  { "spsr_mon", { ARM_BANKEDREG_SPSR_MON }, 0x3C }, // 22
-    { 0x300, 1 },
+  { "spsr_svc", { ARM_BANKEDREG_SPSR_SVC }, 0x32 }, // 23
-    { 0x301, 3 },
+  { "spsr_und", { ARM_BANKEDREG_SPSR_UND }, 0x36 }, // 24
-    { 0x302, 5 },
+  { "sp_abt", { ARM_BANKEDREG_SP_ABT }, 0x15 }, // 25
-    { 0x303, 7 },
+  { "sp_fiq", { ARM_BANKEDREG_SP_FIQ }, 0xD }, // 26
+  { "sp_hyp", { ARM_BANKEDREG_SP_HYP }, 0x1F }, // 27
+  { "sp_irq", { ARM_BANKEDREG_SP_IRQ }, 0x11 }, // 28
+  { "sp_mon", { ARM_BANKEDREG_SP_MON }, 0x1D }, // 29
+  { "sp_svc", { ARM_BANKEDREG_SP_SVC }, 0x13 }, // 30
+  { "sp_und", { ARM_BANKEDREG_SP_UND }, 0x17 }, // 31
+  { "sp_usr", { ARM_BANKEDREG_SP_USR }, 0x5 }, // 32
   };
 
-  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByName(const char * Name) {
-  if (i == -1)
+  static const struct IndexTypeStr Index[] = {
-    return NULL;
+    { "ELR_HYP", 0 },
-  else
+    { "LR_ABT", 1 },
-    return &MClassSysRegsList[Index[i].index];
+    { "LR_FIQ", 2 },
-}
+    { "LR_IRQ", 3 },
-
+    { "LR_MON", 4 },
-const MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
+    { "LR_SVC", 5 },
-{
+    { "LR_UND", 6 },
-  unsigned int i;
+    { "LR_USR", 7 },
-  static const struct IndexType Index[] = {
+    { "R10_FIQ", 8 },
-    { 0x400, 0 },
+    { "R10_USR", 9 },
-    { 0x401, 2 },
+    { "R11_FIQ", 10 },
-    { 0x402, 4 },
+    { "R11_USR", 11 },
-    { 0x403, 6 },
+    { "R12_FIQ", 12 },
-    { 0x800, 8 },
+    { "R12_USR", 13 },
-    { 0x801, 10 },
+    { "R8_FIQ", 14 },
-    { 0x802, 12 },
+    { "R8_USR", 15 },
-    { 0x803, 14 },
+    { "R9_FIQ", 16 },
-    { 0x805, 16 },
+    { "R9_USR", 17 },
-    { 0x806, 17 },
+    { "SPSR_ABT", 18 },
-    { 0x807, 18 },
+    { "SPSR_FIQ", 19 },
-    { 0x808, 19 },
+    { "SPSR_HYP", 20 },
-    { 0x809, 20 },
+    { "SPSR_IRQ", 21 },
-    { 0x80A, 21 },
+    { "SPSR_MON", 22 },
-    { 0x80B, 22 },
+    { "SPSR_SVC", 23 },
-    { 0x810, 23 },
+    { "SPSR_UND", 24 },
-    { 0x811, 24 },
+    { "SP_ABT", 25 },
-    { 0x812, 25 },
+    { "SP_FIQ", 26 },
-    { 0x813, 26 },
+    { "SP_HYP", 27 },
-    { 0x814, 27 },
+    { "SP_IRQ", 28 },
-    { 0x888, 28 },
+    { "SP_MON", 29 },
-    { 0x889, 29 },
+    { "SP_SVC", 30 },
-    { 0x88A, 30 },
+    { "SP_UND", 31 },
-    { 0x88B, 31 },
+    { "SP_USR", 32 },
-    { 0x890, 32 },
-    { 0x891, 33 },
-    { 0x893, 34 },
-    { 0x894, 35 },
-    { 0x898, 36 },
-    { 0xC00, 1 },
-    { 0xC01, 3 },
-    { 0xC02, 5 },
-    { 0xC03, 7 },
-    { 0x1800, 9 },
-    { 0x1801, 11 },
-    { 0x1802, 13 },
-    { 0x1803, 15 },
   };
 
-  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
-  if (i == -1)
+   if (i == -1)
-    return NULL;
+      return NULL;
-  else
+   else
-    return &MClassSysRegsList[Index[i].index];
+      return &BankedRegsList[Index[i].index];
 }
 
-const BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding) {
-{
-  unsigned int i;
   static const struct IndexType Index[] = {
-    { 0x0, 0 },
+    { 0x0, 15 },
-    { 0x1, 1 },
+    { 0x1, 17 },
-    { 0x2, 2 },
+    { 0x2, 9 },
-    { 0x3, 3 },
+    { 0x3, 11 },
-    { 0x4, 4 },
+    { 0x4, 13 },
-    { 0x5, 5 },
+    { 0x5, 32 },
-    { 0x6, 6 },
+    { 0x6, 7 },
-    { 0x8, 7 },
+    { 0x8, 14 },
-    { 0x9, 8 },
+    { 0x9, 16 },
-    { 0xA, 9 },
+    { 0xA, 8 },
     { 0xB, 10 },
-    { 0xC, 11 },
+    { 0xC, 12 },
-    { 0xD, 12 },
+    { 0xD, 26 },
-    { 0xE, 13 },
+    { 0xE, 2 },
-    { 0x10, 14 },
+    { 0x10, 3 },
-    { 0x11, 15 },
+    { 0x11, 28 },
-    { 0x12, 16 },
+    { 0x12, 5 },
-    { 0x13, 17 },
+    { 0x13, 30 },
-    { 0x14, 18 },
+    { 0x14, 1 },
-    { 0x15, 19 },
+    { 0x15, 25 },
-    { 0x16, 20 },
+    { 0x16, 6 },
-    { 0x17, 21 },
+    { 0x17, 31 },
-    { 0x1C, 22 },
+    { 0x1C, 4 },
-    { 0x1D, 23 },
+    { 0x1D, 29 },
-    { 0x1E, 24 },
+    { 0x1E, 0 },
-    { 0x1F, 25 },
+    { 0x1F, 27 },
-    { 0x2E, 26 },
+    { 0x2E, 19 },
-    { 0x30, 27 },
+    { 0x30, 21 },
-    { 0x32, 28 },
+    { 0x32, 23 },
-    { 0x34, 29 },
+    { 0x34, 18 },
-    { 0x36, 30 },
+    { 0x36, 24 },
-    { 0x3C, 31 },
+    { 0x3C, 22 },
-    { 0x3E, 32 },
+    { 0x3E, 20 },
   };
 
-  i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding);
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
-  if (i == -1)
+   if (i == -1)
-    return NULL;
+      return NULL;
-  else
+   else
-    return &BankedRegsList[Index[i].index];
+      return &BankedRegsList[Index[i].index];
 }
 
+#endif
+
+#ifdef GET_MCLASSSYSREG_IMPL
+static const ARMSysReg_MClassSysReg MClassSysRegsList[] = {
+  { "apsr", { ARM_MCLASSSYSREG_APSR }, 0x800, 0x100, 0x800,  {0}  }, // 0
+  { "apsr_g", { ARM_MCLASSSYSREG_APSR_G }, 0x400, 0x0, 0x400,  {ARM_FeatureDSP}  }, // 1
+  { "apsr_nzcvq", { ARM_MCLASSSYSREG_APSR_NZCVQ }, 0x1800, 0x200, 0x800,  {0}  }, // 2
+  { "apsr_nzcvqg", { ARM_MCLASSSYSREG_APSR_NZCVQG }, 0xC00, 0x300, 0xC00,  {ARM_FeatureDSP}  }, // 3
+  { "basepri", { ARM_MCLASSSYSREG_BASEPRI }, 0x811, 0x111, 0x811,  {ARM_HasV7Ops}  }, // 4
+  { "basepri_max", { ARM_MCLASSSYSREG_BASEPRI_MAX }, 0x812, 0x112, 0x812,  {ARM_HasV7Ops}  }, // 5
+  { "basepri_ns", { ARM_MCLASSSYSREG_BASEPRI_NS }, 0x891, 0x191, 0x891,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 6
+  { "control", { ARM_MCLASSSYSREG_CONTROL }, 0x814, 0x114, 0x814,  {0}  }, // 7
+  { "control_ns", { ARM_MCLASSSYSREG_CONTROL_NS }, 0x894, 0x194, 0x894,  {ARM_Feature8MSecExt}  }, // 8
+  { "eapsr", { ARM_MCLASSSYSREG_EAPSR }, 0x802, 0x102, 0x802,  {0}  }, // 9
+  { "eapsr_g", { ARM_MCLASSSYSREG_EAPSR_G }, 0x402, 0x2, 0x402,  {ARM_FeatureDSP}  }, // 10
+  { "eapsr_nzcvq", { ARM_MCLASSSYSREG_EAPSR_NZCVQ }, 0x1802, 0x202, 0x802,  {0}  }, // 11
+  { "eapsr_nzcvqg", { ARM_MCLASSSYSREG_EAPSR_NZCVQG }, 0xC02, 0x302, 0xC02,  {ARM_FeatureDSP}  }, // 12
+  { "epsr", { ARM_MCLASSSYSREG_EPSR }, 0x806, 0x106, 0x806,  {0}  }, // 13
+  { "faultmask", { ARM_MCLASSSYSREG_FAULTMASK }, 0x813, 0x113, 0x813,  {ARM_HasV7Ops}  }, // 14
+  { "faultmask_ns", { ARM_MCLASSSYSREG_FAULTMASK_NS }, 0x893, 0x193, 0x893,  {ARM_Feature8MSecExt, ARM_HasV7Ops}  }, // 15
+  { "iapsr", { ARM_MCLASSSYSREG_IAPSR }, 0x801, 0x101, 0x801,  {0}  }, // 16
+  { "iapsr_g", { ARM_MCLASSSYSREG_IAPSR_G }, 0x401, 0x1, 0x401,  {ARM_FeatureDSP}  }, // 17
+  { "iapsr_nzcvq", { ARM_MCLASSSYSREG_IAPSR_NZCVQ }, 0x1801, 0x201, 0x801,  {0}  }, // 18
+  { "iapsr_nzcvqg", { ARM_MCLASSSYSREG_IAPSR_NZCVQG }, 0xC01, 0x301, 0xC01,  {ARM_FeatureDSP}  }, // 19
+  { "iepsr", { ARM_MCLASSSYSREG_IEPSR }, 0x807, 0x107, 0x807,  {0}  }, // 20
+  { "ipsr", { ARM_MCLASSSYSREG_IPSR }, 0x805, 0x105, 0x805,  {0}  }, // 21
+  { "msp", { ARM_MCLASSSYSREG_MSP }, 0x808, 0x108, 0x808,  {0}  }, // 22
+  { "msplim", { ARM_MCLASSSYSREG_MSPLIM }, 0x80A, 0x10A, 0x80A,  {ARM_HasV8MBaselineOps}  }, // 23
+  { "msplim_ns", { ARM_MCLASSSYSREG_MSPLIM_NS }, 0x88A, 0x18A, 0x88A,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 24
+  { "msp_ns", { ARM_MCLASSSYSREG_MSP_NS }, 0x888, 0x188, 0x888,  {ARM_Feature8MSecExt}  }, // 25
+  { "pac_key_p_0", { ARM_MCLASSSYSREG_PAC_KEY_P_0 }, 0x820, 0x120, 0x820,  {ARM_FeaturePACBTI}  }, // 26
+  { "pac_key_p_0_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_0_NS }, 0x8A0, 0x1A0, 0x8A0,  {ARM_FeaturePACBTI}  }, // 27
+  { "pac_key_p_1", { ARM_MCLASSSYSREG_PAC_KEY_P_1 }, 0x821, 0x121, 0x821,  {ARM_FeaturePACBTI}  }, // 28
+  { "pac_key_p_1_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_1_NS }, 0x8A1, 0x1A1, 0x8A1,  {ARM_FeaturePACBTI}  }, // 29
+  { "pac_key_p_2", { ARM_MCLASSSYSREG_PAC_KEY_P_2 }, 0x822, 0x122, 0x822,  {ARM_FeaturePACBTI}  }, // 30
+  { "pac_key_p_2_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_2_NS }, 0x8A2, 0x1A2, 0x8A2,  {ARM_FeaturePACBTI}  }, // 31
+  { "pac_key_p_3", { ARM_MCLASSSYSREG_PAC_KEY_P_3 }, 0x823, 0x123, 0x823,  {ARM_FeaturePACBTI}  }, // 32
+  { "pac_key_p_3_ns", { ARM_MCLASSSYSREG_PAC_KEY_P_3_NS }, 0x8A3, 0x1A3, 0x8A3,  {ARM_FeaturePACBTI}  }, // 33
+  { "pac_key_u_0", { ARM_MCLASSSYSREG_PAC_KEY_U_0 }, 0x824, 0x124, 0x824,  {ARM_FeaturePACBTI}  }, // 34
+  { "pac_key_u_0_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_0_NS }, 0x8A4, 0x1A4, 0x8A4,  {ARM_FeaturePACBTI}  }, // 35
+  { "pac_key_u_1", { ARM_MCLASSSYSREG_PAC_KEY_U_1 }, 0x825, 0x125, 0x825,  {ARM_FeaturePACBTI}  }, // 36
+  { "pac_key_u_1_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_1_NS }, 0x8A5, 0x1A5, 0x8A5,  {ARM_FeaturePACBTI}  }, // 37
+  { "pac_key_u_2", { ARM_MCLASSSYSREG_PAC_KEY_U_2 }, 0x826, 0x126, 0x826,  {ARM_FeaturePACBTI}  }, // 38
+  { "pac_key_u_2_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_2_NS }, 0x8A6, 0x1A6, 0x8A6,  {ARM_FeaturePACBTI}  }, // 39
+  { "pac_key_u_3", { ARM_MCLASSSYSREG_PAC_KEY_U_3 }, 0x827, 0x127, 0x827,  {ARM_FeaturePACBTI}  }, // 40
+  { "pac_key_u_3_ns", { ARM_MCLASSSYSREG_PAC_KEY_U_3_NS }, 0x8A7, 0x1A7, 0x8A7,  {ARM_FeaturePACBTI}  }, // 41
+  { "primask", { ARM_MCLASSSYSREG_PRIMASK }, 0x810, 0x110, 0x810,  {0}  }, // 42
+  { "primask_ns", { ARM_MCLASSSYSREG_PRIMASK_NS }, 0x890, 0x190, 0x890,  {0}  }, // 43
+  { "psp", { ARM_MCLASSSYSREG_PSP }, 0x809, 0x109, 0x809,  {0}  }, // 44
+  { "psplim", { ARM_MCLASSSYSREG_PSPLIM }, 0x80B, 0x10B, 0x80B,  {ARM_HasV8MBaselineOps}  }, // 45
+  { "psplim_ns", { ARM_MCLASSSYSREG_PSPLIM_NS }, 0x88B, 0x18B, 0x88B,  {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps}  }, // 46
+  { "psp_ns", { ARM_MCLASSSYSREG_PSP_NS }, 0x889, 0x189, 0x889,  {ARM_Feature8MSecExt}  }, // 47
+  { "sp_ns", { ARM_MCLASSSYSREG_SP_NS }, 0x898, 0x198, 0x898,  {ARM_Feature8MSecExt}  }, // 48
+  { "xpsr", { ARM_MCLASSSYSREG_XPSR }, 0x803, 0x103, 0x803,  {0}  }, // 49
+  { "xpsr_g", { ARM_MCLASSSYSREG_XPSR_G }, 0x403, 0x3, 0x403,  {ARM_FeatureDSP}  }, // 50
+  { "xpsr_nzcvq", { ARM_MCLASSSYSREG_XPSR_NZCVQ }, 0x1803, 0x203, 0x803,  {0}  }, // 51
+  { "xpsr_nzcvqg", { ARM_MCLASSSYSREG_XPSR_NZCVQG }, 0xC03, 0x303, 0xC03,  {ARM_FeatureDSP}  }, // 52
+  };
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByName(const char * Name) {
+  static const struct IndexTypeStr Index[] = {
+    { "APSR", 0 },
+    { "APSR_G", 1 },
+    { "APSR_NZCVQ", 2 },
+    { "APSR_NZCVQG", 3 },
+    { "BASEPRI", 4 },
+    { "BASEPRI_MAX", 5 },
+    { "BASEPRI_NS", 6 },
+    { "CONTROL", 7 },
+    { "CONTROL_NS", 8 },
+    { "EAPSR", 9 },
+    { "EAPSR_G", 10 },
+    { "EAPSR_NZCVQ", 11 },
+    { "EAPSR_NZCVQG", 12 },
+    { "EPSR", 13 },
+    { "FAULTMASK", 14 },
+    { "FAULTMASK_NS", 15 },
+    { "IAPSR", 16 },
+    { "IAPSR_G", 17 },
+    { "IAPSR_NZCVQ", 18 },
+    { "IAPSR_NZCVQG", 19 },
+    { "IEPSR", 20 },
+    { "IPSR", 21 },
+    { "MSP", 22 },
+    { "MSPLIM", 23 },
+    { "MSPLIM_NS", 24 },
+    { "MSP_NS", 25 },
+    { "PAC_KEY_P_0", 26 },
+    { "PAC_KEY_P_0_NS", 27 },
+    { "PAC_KEY_P_1", 28 },
+    { "PAC_KEY_P_1_NS", 29 },
+    { "PAC_KEY_P_2", 30 },
+    { "PAC_KEY_P_2_NS", 31 },
+    { "PAC_KEY_P_3", 32 },
+    { "PAC_KEY_P_3_NS", 33 },
+    { "PAC_KEY_U_0", 34 },
+    { "PAC_KEY_U_0_NS", 35 },
+    { "PAC_KEY_U_1", 36 },
+    { "PAC_KEY_U_1_NS", 37 },
+    { "PAC_KEY_U_2", 38 },
+    { "PAC_KEY_U_2_NS", 39 },
+    { "PAC_KEY_U_3", 40 },
+    { "PAC_KEY_U_3_NS", 41 },
+    { "PRIMASK", 42 },
+    { "PRIMASK_NS", 43 },
+    { "PSP", 44 },
+    { "PSPLIM", 45 },
+    { "PSPLIM_NS", 46 },
+    { "PSP_NS", 47 },
+    { "SP_NS", 48 },
+    { "XPSR", 49 },
+    { "XPSR_G", 50 },
+    { "XPSR_NZCVQ", 51 },
+    { "XPSR_NZCVQG", 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12) {
+  static const struct IndexType Index[] = {
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x801, 16 },
+    { 0x802, 9 },
+    { 0x803, 49 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+    { 0x1800, 2 },
+    { 0x1801, 18 },
+    { 0x1802, 11 },
+    { 0x1803, 51 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M1Encoding12);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByM2M3Encoding8(uint16_t M2M3Encoding8) {
+  static const struct IndexType Index[] = {
+    { 0x0, 1 },
+    { 0x1, 17 },
+    { 0x2, 10 },
+    { 0x3, 50 },
+    { 0x100, 0 },
+    { 0x101, 16 },
+    { 0x102, 9 },
+    { 0x103, 49 },
+    { 0x105, 21 },
+    { 0x106, 13 },
+    { 0x107, 20 },
+    { 0x108, 22 },
+    { 0x109, 44 },
+    { 0x10A, 23 },
+    { 0x10B, 45 },
+    { 0x110, 42 },
+    { 0x111, 4 },
+    { 0x112, 5 },
+    { 0x113, 14 },
+    { 0x114, 7 },
+    { 0x120, 26 },
+    { 0x121, 28 },
+    { 0x122, 30 },
+    { 0x123, 32 },
+    { 0x124, 34 },
+    { 0x125, 36 },
+    { 0x126, 38 },
+    { 0x127, 40 },
+    { 0x188, 25 },
+    { 0x189, 47 },
+    { 0x18A, 24 },
+    { 0x18B, 46 },
+    { 0x190, 43 },
+    { 0x191, 6 },
+    { 0x193, 15 },
+    { 0x194, 8 },
+    { 0x198, 48 },
+    { 0x1A0, 27 },
+    { 0x1A1, 29 },
+    { 0x1A2, 31 },
+    { 0x1A3, 33 },
+    { 0x1A4, 35 },
+    { 0x1A5, 37 },
+    { 0x1A6, 39 },
+    { 0x1A7, 41 },
+    { 0x200, 2 },
+    { 0x201, 18 },
+    { 0x202, 11 },
+    { 0x203, 51 },
+    { 0x300, 3 },
+    { 0x301, 19 },
+    { 0x302, 12 },
+    { 0x303, 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), M2M3Encoding8);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding) {
+  static const struct IndexType Index[] = {
+    { 0x400, 1 },
+    { 0x401, 17 },
+    { 0x402, 10 },
+    { 0x403, 50 },
+    { 0x800, 0 },
+    { 0x800, 2 },
+    { 0x801, 16 },
+    { 0x801, 18 },
+    { 0x802, 9 },
+    { 0x802, 11 },
+    { 0x803, 49 },
+    { 0x803, 51 },
+    { 0x805, 21 },
+    { 0x806, 13 },
+    { 0x807, 20 },
+    { 0x808, 22 },
+    { 0x809, 44 },
+    { 0x80A, 23 },
+    { 0x80B, 45 },
+    { 0x810, 42 },
+    { 0x811, 4 },
+    { 0x812, 5 },
+    { 0x813, 14 },
+    { 0x814, 7 },
+    { 0x820, 26 },
+    { 0x821, 28 },
+    { 0x822, 30 },
+    { 0x823, 32 },
+    { 0x824, 34 },
+    { 0x825, 36 },
+    { 0x826, 38 },
+    { 0x827, 40 },
+    { 0x888, 25 },
+    { 0x889, 47 },
+    { 0x88A, 24 },
+    { 0x88B, 46 },
+    { 0x890, 43 },
+    { 0x891, 6 },
+    { 0x893, 15 },
+    { 0x894, 8 },
+    { 0x898, 48 },
+    { 0x8A0, 27 },
+    { 0x8A1, 29 },
+    { 0x8A2, 31 },
+    { 0x8A3, 33 },
+    { 0x8A4, 35 },
+    { 0x8A5, 37 },
+    { 0x8A6, 39 },
+    { 0x8A7, 41 },
+    { 0xC00, 3 },
+    { 0xC01, 19 },
+    { 0xC02, 12 },
+    { 0xC03, 52 },
+  };
+
+   unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding);
+   if (i == -1)
+      return NULL;
+   else
+      return &MClassSysRegsList[Index[i].index];
+}
+
+#endif
+
+#undef GET_BANKEDREG_DECL
+#undef GET_MCLASSSYSREG_DECL

arch/ARM/ARMInsnEnum.inc

@@ -0,0 +1,682 @@
+/* Capstone Disassembly Engine, https://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+/* By Rot127 <unisono@quyllur.org>, 2023 */
+
+/* Auto generated file. Do not edit. */
+/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+  ARM_INS___BRKDIV0,
+  ARM_INS_ADC,
+  ARM_INS_ADD,
+  ARM_INS_ADDW,
+  ARM_INS_ADR,
+  ARM_INS_AESD,
+  ARM_INS_AESE,
+  ARM_INS_AESIMC,
+  ARM_INS_AESMC,
+  ARM_INS_AND,
+  ARM_INS_ASR,
+  ARM_INS_ASRL,
+  ARM_INS_AUT,
+  ARM_INS_AUTG,
+  ARM_INS_B,
+  ARM_INS_BF,
+  ARM_INS_BFC,
+  ARM_INS_BFCSEL,
+  ARM_INS_BFI,
+  ARM_INS_BFL,
+  ARM_INS_BFLX,
+  ARM_INS_BFX,
+  ARM_INS_BIC,
+  ARM_INS_BKPT,
+  ARM_INS_BL,
+  ARM_INS_BLX,
+  ARM_INS_BLXNS,
+  ARM_INS_BTI,
+  ARM_INS_BX,
+  ARM_INS_BXAUT,
+  ARM_INS_BXJ,
+  ARM_INS_BXNS,
+  ARM_INS_CBNZ,
+  ARM_INS_CBZ,
+  ARM_INS_CDP,
+  ARM_INS_CDP2,
+  ARM_INS_CINC,
+  ARM_INS_CINV,
+  ARM_INS_CLRBHB,
+  ARM_INS_CLREX,
+  ARM_INS_CLRM,
+  ARM_INS_CLZ,
+  ARM_INS_CMN,
+  ARM_INS_CMP,
+  ARM_INS_CNEG,
+  ARM_INS_CPS,
+  ARM_INS_CRC32B,
+  ARM_INS_CRC32CB,
+  ARM_INS_CRC32CH,
+  ARM_INS_CRC32CW,
+  ARM_INS_CRC32H,
+  ARM_INS_CRC32W,
+  ARM_INS_CSDB,
+  ARM_INS_CSEL,
+  ARM_INS_CSET,
+  ARM_INS_CSETM,
+  ARM_INS_CSINC,
+  ARM_INS_CSINV,
+  ARM_INS_CSNEG,
+  ARM_INS_CX1,
+  ARM_INS_CX1A,
+  ARM_INS_CX1D,
+  ARM_INS_CX1DA,
+  ARM_INS_CX2,
+  ARM_INS_CX2A,
+  ARM_INS_CX2D,
+  ARM_INS_CX2DA,
+  ARM_INS_CX3,
+  ARM_INS_CX3A,
+  ARM_INS_CX3D,
+  ARM_INS_CX3DA,
+  ARM_INS_DBG,
+  ARM_INS_DCPS1,
+  ARM_INS_DCPS2,
+  ARM_INS_DCPS3,
+  ARM_INS_DFB,
+  ARM_INS_DLS,
+  ARM_INS_DLSTP,
+  ARM_INS_DMB,
+  ARM_INS_DSB,
+  ARM_INS_EOR,
+  ARM_INS_ERET,
+  ARM_INS_ESB,
+  ARM_INS_FADDD,
+  ARM_INS_FADDS,
+  ARM_INS_FCMPZD,
+  ARM_INS_FCMPZS,
+  ARM_INS_FCONSTD,
+  ARM_INS_FCONSTS,
+  ARM_INS_FLDMDBX,
+  ARM_INS_FLDMIAX,
+  ARM_INS_FMDHR,
+  ARM_INS_FMDLR,
+  ARM_INS_FMSTAT,
+  ARM_INS_FSTMDBX,
+  ARM_INS_FSTMIAX,
+  ARM_INS_FSUBD,
+  ARM_INS_FSUBS,
+  ARM_INS_HINT,
+  ARM_INS_HLT,
+  ARM_INS_HVC,
+  ARM_INS_ISB,
+  ARM_INS_IT,
+  ARM_INS_LCTP,
+  ARM_INS_LDA,
+  ARM_INS_LDAB,
+  ARM_INS_LDAEX,
+  ARM_INS_LDAEXB,
+  ARM_INS_LDAEXD,
+  ARM_INS_LDAEXH,
+  ARM_INS_LDAH,
+  ARM_INS_LDC,
+  ARM_INS_LDC2,
+  ARM_INS_LDC2L,
+  ARM_INS_LDCL,
+  ARM_INS_LDM,
+  ARM_INS_LDMDA,
+  ARM_INS_LDMDB,
+  ARM_INS_LDMIB,
+  ARM_INS_LDR,
+  ARM_INS_LDRB,
+  ARM_INS_LDRBT,
+  ARM_INS_LDRD,
+  ARM_INS_LDREX,
+  ARM_INS_LDREXB,
+  ARM_INS_LDREXD,
+  ARM_INS_LDREXH,
+  ARM_INS_LDRH,
+  ARM_INS_LDRHT,
+  ARM_INS_LDRSB,
+  ARM_INS_LDRSBT,
+  ARM_INS_LDRSH,
+  ARM_INS_LDRSHT,
+  ARM_INS_LDRT,
+  ARM_INS_LE,
+  ARM_INS_LETP,
+  ARM_INS_LSL,
+  ARM_INS_LSLL,
+  ARM_INS_LSR,
+  ARM_INS_LSRL,
+  ARM_INS_MCR,
+  ARM_INS_MCR2,
+  ARM_INS_MCRR,
+  ARM_INS_MCRR2,
+  ARM_INS_MLA,
+  ARM_INS_MLS,
+  ARM_INS_MOV,
+  ARM_INS_MOVS,
+  ARM_INS_MOVT,
+  ARM_INS_MOVW,
+  ARM_INS_MRC,
+  ARM_INS_MRC2,
+  ARM_INS_MRRC,
+  ARM_INS_MRRC2,
+  ARM_INS_MRS,
+  ARM_INS_MSR,
+  ARM_INS_MUL,
+  ARM_INS_MVN,
+  ARM_INS_NEG,
+  ARM_INS_NOP,
+  ARM_INS_ORN,
+  ARM_INS_ORR,
+  ARM_INS_PAC,
+  ARM_INS_PACBTI,
+  ARM_INS_PACG,
+  ARM_INS_PKHBT,
+  ARM_INS_PKHTB,
+  ARM_INS_PLD,
+  ARM_INS_PLDW,
+  ARM_INS_PLI,
+  ARM_INS_POP,
+  ARM_INS_PSSBB,
+  ARM_INS_PUSH,
+  ARM_INS_QADD,
+  ARM_INS_QADD16,
+  ARM_INS_QADD8,
+  ARM_INS_QASX,
+  ARM_INS_QDADD,
+  ARM_INS_QDSUB,
+  ARM_INS_QSAX,
+  ARM_INS_QSUB,
+  ARM_INS_QSUB16,
+  ARM_INS_QSUB8,
+  ARM_INS_RBIT,
+  ARM_INS_REV,
+  ARM_INS_REV16,
+  ARM_INS_REVSH,
+  ARM_INS_RFEDA,
+  ARM_INS_RFEDB,
+  ARM_INS_RFEIA,
+  ARM_INS_RFEIB,
+  ARM_INS_ROR,
+  ARM_INS_RRX,
+  ARM_INS_RSB,
+  ARM_INS_RSC,
+  ARM_INS_SADD16,
+  ARM_INS_SADD8,
+  ARM_INS_SASX,
+  ARM_INS_SB,
+  ARM_INS_SBC,
+  ARM_INS_SBFX,
+  ARM_INS_SDIV,
+  ARM_INS_SEL,
+  ARM_INS_SETEND,
+  ARM_INS_SETPAN,
+  ARM_INS_SEV,
+  ARM_INS_SEVL,
+  ARM_INS_SG,
+  ARM_INS_SHA1C,
+  ARM_INS_SHA1H,
+  ARM_INS_SHA1M,
+  ARM_INS_SHA1P,
+  ARM_INS_SHA1SU0,
+  ARM_INS_SHA1SU1,
+  ARM_INS_SHA256H,
+  ARM_INS_SHA256H2,
+  ARM_INS_SHA256SU0,
+  ARM_INS_SHA256SU1,
+  ARM_INS_SHADD16,
+  ARM_INS_SHADD8,
+  ARM_INS_SHASX,
+  ARM_INS_SHSAX,
+  ARM_INS_SHSUB16,
+  ARM_INS_SHSUB8,
+  ARM_INS_SMC,
+  ARM_INS_SMLABB,
+  ARM_INS_SMLABT,
+  ARM_INS_SMLAD,
+  ARM_INS_SMLADX,
+  ARM_INS_SMLAL,
+  ARM_INS_SMLALBB,
+  ARM_INS_SMLALBT,
+  ARM_INS_SMLALD,
+  ARM_INS_SMLALDX,
+  ARM_INS_SMLALTB,
+  ARM_INS_SMLALTT,
+  ARM_INS_SMLATB,
+  ARM_INS_SMLATT,
+  ARM_INS_SMLAWB,
+  ARM_INS_SMLAWT,
+  ARM_INS_SMLSD,
+  ARM_INS_SMLSDX,
+  ARM_INS_SMLSLD,
+  ARM_INS_SMLSLDX,
+  ARM_INS_SMMLA,
+  ARM_INS_SMMLAR,
+  ARM_INS_SMMLS,
+  ARM_INS_SMMLSR,
+  ARM_INS_SMMUL,
+  ARM_INS_SMMULR,
+  ARM_INS_SMUAD,
+  ARM_INS_SMUADX,
+  ARM_INS_SMULBB,
+  ARM_INS_SMULBT,
+  ARM_INS_SMULL,
+  ARM_INS_SMULTB,
+  ARM_INS_SMULTT,
+  ARM_INS_SMULWB,
+  ARM_INS_SMULWT,
+  ARM_INS_SMUSD,
+  ARM_INS_SMUSDX,
+  ARM_INS_SQRSHR,
+  ARM_INS_SQRSHRL,
+  ARM_INS_SQSHL,
+  ARM_INS_SQSHLL,
+  ARM_INS_SRSDA,
+  ARM_INS_SRSDB,
+  ARM_INS_SRSHR,
+  ARM_INS_SRSHRL,
+  ARM_INS_SRSIA,
+  ARM_INS_SRSIB,
+  ARM_INS_SSAT,
+  ARM_INS_SSAT16,
+  ARM_INS_SSAX,
+  ARM_INS_SSBB,
+  ARM_INS_SSUB16,
+  ARM_INS_SSUB8,
+  ARM_INS_STC,
+  ARM_INS_STC2,
+  ARM_INS_STC2L,
+  ARM_INS_STCL,
+  ARM_INS_STL,
+  ARM_INS_STLB,
+  ARM_INS_STLEX,
+  ARM_INS_STLEXB,
+  ARM_INS_STLEXD,
+  ARM_INS_STLEXH,
+  ARM_INS_STLH,
+  ARM_INS_STM,
+  ARM_INS_STMDA,
+  ARM_INS_STMDB,
+  ARM_INS_STMIB,
+  ARM_INS_STR,
+  ARM_INS_STRB,
+  ARM_INS_STRBT,
+  ARM_INS_STRD,
+  ARM_INS_STREX,
+  ARM_INS_STREXB,
+  ARM_INS_STREXD,
+  ARM_INS_STREXH,
+  ARM_INS_STRH,
+  ARM_INS_STRHT,
+  ARM_INS_STRT,
+  ARM_INS_SUB,
+  ARM_INS_SUBS,
+  ARM_INS_SUBW,
+  ARM_INS_SVC,
+  ARM_INS_SWP,
+  ARM_INS_SWPB,
+  ARM_INS_SXTAB,
+  ARM_INS_SXTAB16,
+  ARM_INS_SXTAH,
+  ARM_INS_SXTB,
+  ARM_INS_SXTB16,
+  ARM_INS_SXTH,
+  ARM_INS_TBB,
+  ARM_INS_TBH,
+  ARM_INS_TEQ,
+  ARM_INS_TRAP,
+  ARM_INS_TSB,
+  ARM_INS_TST,
+  ARM_INS_TT,
+  ARM_INS_TTA,
+  ARM_INS_TTAT,
+  ARM_INS_TTT,
+  ARM_INS_UADD16,
+  ARM_INS_UADD8,
+  ARM_INS_UASX,
+  ARM_INS_UBFX,
+  ARM_INS_UDF,
+  ARM_INS_UDIV,
+  ARM_INS_UHADD16,
+  ARM_INS_UHADD8,
+  ARM_INS_UHASX,
+  ARM_INS_UHSAX,
+  ARM_INS_UHSUB16,
+  ARM_INS_UHSUB8,
+  ARM_INS_UMAAL,
+  ARM_INS_UMLAL,
+  ARM_INS_UMULL,
+  ARM_INS_UQADD16,
+  ARM_INS_UQADD8,
+  ARM_INS_UQASX,
+  ARM_INS_UQRSHL,
+  ARM_INS_UQRSHLL,
+  ARM_INS_UQSAX,
+  ARM_INS_UQSHL,
+  ARM_INS_UQSHLL,
+  ARM_INS_UQSUB16,
+  ARM_INS_UQSUB8,
+  ARM_INS_URSHR,
+  ARM_INS_URSHRL,
+  ARM_INS_USAD8,
+  ARM_INS_USADA8,
+  ARM_INS_USAT,
+  ARM_INS_USAT16,
+  ARM_INS_USAX,
+  ARM_INS_USUB16,
+  ARM_INS_USUB8,
+  ARM_INS_UXTAB,
+  ARM_INS_UXTAB16,
+  ARM_INS_UXTAH,
+  ARM_INS_UXTB,
+  ARM_INS_UXTB16,
+  ARM_INS_UXTH,
+  ARM_INS_VABA,
+  ARM_INS_VABAL,
+  ARM_INS_VABAV,
+  ARM_INS_VABD,
+  ARM_INS_VABDL,
+  ARM_INS_VABS,
+  ARM_INS_VACGE,
+  ARM_INS_VACGT,
+  ARM_INS_VACLE,
+  ARM_INS_VACLT,
+  ARM_INS_VADC,
+  ARM_INS_VADCI,
+  ARM_INS_VADD,
+  ARM_INS_VADDHN,
+  ARM_INS_VADDL,
+  ARM_INS_VADDLV,
+  ARM_INS_VADDLVA,
+  ARM_INS_VADDV,
+  ARM_INS_VADDVA,
+  ARM_INS_VADDW,
+  ARM_INS_VAND,
+  ARM_INS_VBIC,
+  ARM_INS_VBIF,
+  ARM_INS_VBIT,
+  ARM_INS_VBRSR,
+  ARM_INS_VBSL,
+  ARM_INS_VCADD,
+  ARM_INS_VCEQ,
+  ARM_INS_VCGE,
+  ARM_INS_VCGT,
+  ARM_INS_VCLE,
+  ARM_INS_VCLS,
+  ARM_INS_VCLT,
+  ARM_INS_VCLZ,
+  ARM_INS_VCMLA,
+  ARM_INS_VCMP,
+  ARM_INS_VCMPE,
+  ARM_INS_VCMUL,
+  ARM_INS_VCNT,
+  ARM_INS_VCTP,
+  ARM_INS_VCVT,
+  ARM_INS_VCVTA,
+  ARM_INS_VCVTB,
+  ARM_INS_VCVTM,
+  ARM_INS_VCVTN,
+  ARM_INS_VCVTP,
+  ARM_INS_VCVTR,
+  ARM_INS_VCVTT,
+  ARM_INS_VCX1,
+  ARM_INS_VCX1A,
+  ARM_INS_VCX2,
+  ARM_INS_VCX2A,
+  ARM_INS_VCX3,
+  ARM_INS_VCX3A,
+  ARM_INS_VDDUP,
+  ARM_INS_VDIV,
+  ARM_INS_VDOT,
+  ARM_INS_VDUP,
+  ARM_INS_VDWDUP,
+  ARM_INS_VEOR,
+  ARM_INS_VEXT,
+  ARM_INS_VFMA,
+  ARM_INS_VFMAB,
+  ARM_INS_VFMAL,
+  ARM_INS_VFMAS,
+  ARM_INS_VFMAT,
+  ARM_INS_VFMS,
+  ARM_INS_VFMSL,
+  ARM_INS_VFNMA,
+  ARM_INS_VFNMS,
+  ARM_INS_VHADD,
+  ARM_INS_VHCADD,
+  ARM_INS_VHSUB,
+  ARM_INS_VIDUP,
+  ARM_INS_VINS,
+  ARM_INS_VIWDUP,
+  ARM_INS_VJCVT,
+  ARM_INS_VLD1,
+  ARM_INS_VLD2,
+  ARM_INS_VLD20,
+  ARM_INS_VLD21,
+  ARM_INS_VLD3,
+  ARM_INS_VLD4,
+  ARM_INS_VLD40,
+  ARM_INS_VLD41,
+  ARM_INS_VLD42,
+  ARM_INS_VLD43,
+  ARM_INS_VLDMDB,
+  ARM_INS_VLDMIA,
+  ARM_INS_VLDR,
+  ARM_INS_VLDRB,
+  ARM_INS_VLDRD,
+  ARM_INS_VLDRH,
+  ARM_INS_VLDRW,
+  ARM_INS_VLLDM,
+  ARM_INS_VLSTM,
+  ARM_INS_VMAX,
+  ARM_INS_VMAXA,
+  ARM_INS_VMAXAV,
+  ARM_INS_VMAXNM,
+  ARM_INS_VMAXNMA,
+  ARM_INS_VMAXNMAV,
+  ARM_INS_VMAXNMV,
+  ARM_INS_VMAXV,
+  ARM_INS_VMIN,
+  ARM_INS_VMINA,
+  ARM_INS_VMINAV,
+  ARM_INS_VMINNM,
+  ARM_INS_VMINNMA,
+  ARM_INS_VMINNMAV,
+  ARM_INS_VMINNMV,
+  ARM_INS_VMINV,
+  ARM_INS_VMLA,
+  ARM_INS_VMLADAV,
+  ARM_INS_VMLADAVA,
+  ARM_INS_VMLADAVAX,
+  ARM_INS_VMLADAVX,
+  ARM_INS_VMLAL,
+  ARM_INS_VMLALDAV,
+  ARM_INS_VMLALDAVA,
+  ARM_INS_VMLALDAVAX,
+  ARM_INS_VMLALDAVX,
+  ARM_INS_VMLALV,
+  ARM_INS_VMLALVA,
+  ARM_INS_VMLAS,
+  ARM_INS_VMLAV,
+  ARM_INS_VMLAVA,
+  ARM_INS_VMLS,
+  ARM_INS_VMLSDAV,
+  ARM_INS_VMLSDAVA,
+  ARM_INS_VMLSDAVAX,
+  ARM_INS_VMLSDAVX,
+  ARM_INS_VMLSL,
+  ARM_INS_VMLSLDAV,
+  ARM_INS_VMLSLDAVA,
+  ARM_INS_VMLSLDAVAX,
+  ARM_INS_VMLSLDAVX,
+  ARM_INS_VMMLA,
+  ARM_INS_VMOV,
+  ARM_INS_VMOVL,
+  ARM_INS_VMOVLB,
+  ARM_INS_VMOVLT,
+  ARM_INS_VMOVN,
+  ARM_INS_VMOVNB,
+  ARM_INS_VMOVNT,
+  ARM_INS_VMOVX,
+  ARM_INS_VMRS,
+  ARM_INS_VMSR,
+  ARM_INS_VMUL,
+  ARM_INS_VMULH,
+  ARM_INS_VMULL,
+  ARM_INS_VMULLB,
+  ARM_INS_VMULLT,
+  ARM_INS_VMVN,
+  ARM_INS_VNEG,
+  ARM_INS_VNMLA,
+  ARM_INS_VNMLS,
+  ARM_INS_VNMUL,
+  ARM_INS_VORN,
+  ARM_INS_VORR,
+  ARM_INS_VPADAL,
+  ARM_INS_VPADD,
+  ARM_INS_VPADDL,
+  ARM_INS_VPMAX,
+  ARM_INS_VPMIN,
+  ARM_INS_VPNOT,
+  ARM_INS_VPOP,
+  ARM_INS_VPSEL,
+  ARM_INS_VPST,
+  ARM_INS_VPT,
+  ARM_INS_VPUSH,
+  ARM_INS_VQABS,
+  ARM_INS_VQADD,
+  ARM_INS_VQDMLADH,
+  ARM_INS_VQDMLADHX,
+  ARM_INS_VQDMLAH,
+  ARM_INS_VQDMLAL,
+  ARM_INS_VQDMLASH,
+  ARM_INS_VQDMLSDH,
+  ARM_INS_VQDMLSDHX,
+  ARM_INS_VQDMLSL,
+  ARM_INS_VQDMULH,
+  ARM_INS_VQDMULL,
+  ARM_INS_VQDMULLB,
+  ARM_INS_VQDMULLT,
+  ARM_INS_VQMOVN,
+  ARM_INS_VQMOVNB,
+  ARM_INS_VQMOVNT,
+  ARM_INS_VQMOVUN,
+  ARM_INS_VQMOVUNB,
+  ARM_INS_VQMOVUNT,
+  ARM_INS_VQNEG,
+  ARM_INS_VQRDMLADH,
+  ARM_INS_VQRDMLADHX,
+  ARM_INS_VQRDMLAH,
+  ARM_INS_VQRDMLASH,
+  ARM_INS_VQRDMLSDH,
+  ARM_INS_VQRDMLSDHX,
+  ARM_INS_VQRDMLSH,
+  ARM_INS_VQRDMULH,
+  ARM_INS_VQRSHL,
+  ARM_INS_VQRSHRN,
+  ARM_INS_VQRSHRNB,
+  ARM_INS_VQRSHRNT,
+  ARM_INS_VQRSHRUN,
+  ARM_INS_VQRSHRUNB,
+  ARM_INS_VQRSHRUNT,
+  ARM_INS_VQSHL,
+  ARM_INS_VQSHLU,
+  ARM_INS_VQSHRN,
+  ARM_INS_VQSHRNB,
+  ARM_INS_VQSHRNT,
+  ARM_INS_VQSHRUN,
+  ARM_INS_VQSHRUNB,
+  ARM_INS_VQSHRUNT,
+  ARM_INS_VQSUB,
+  ARM_INS_VRADDHN,
+  ARM_INS_VRECPE,
+  ARM_INS_VRECPS,
+  ARM_INS_VREV16,
+  ARM_INS_VREV32,
+  ARM_INS_VREV64,
+  ARM_INS_VRHADD,
+  ARM_INS_VRINTA,
+  ARM_INS_VRINTM,
+  ARM_INS_VRINTN,
+  ARM_INS_VRINTP,
+  ARM_INS_VRINTR,
+  ARM_INS_VRINTX,
+  ARM_INS_VRINTZ,
+  ARM_INS_VRMLALDAVH,
+  ARM_INS_VRMLALDAVHA,
+  ARM_INS_VRMLALDAVHAX,
+  ARM_INS_VRMLALDAVHX,
+  ARM_INS_VRMLALVH,
+  ARM_INS_VRMLALVHA,
+  ARM_INS_VRMLSLDAVH,
+  ARM_INS_VRMLSLDAVHA,
+  ARM_INS_VRMLSLDAVHAX,
+  ARM_INS_VRMLSLDAVHX,
+  ARM_INS_VRMULH,
+  ARM_INS_VRSHL,
+  ARM_INS_VRSHR,
+  ARM_INS_VRSHRN,
+  ARM_INS_VRSHRNB,
+  ARM_INS_VRSHRNT,
+  ARM_INS_VRSQRTE,
+  ARM_INS_VRSQRTS,
+  ARM_INS_VRSRA,
+  ARM_INS_VRSUBHN,
+  ARM_INS_VSBC,
+  ARM_INS_VSBCI,
+  ARM_INS_VSCCLRM,
+  ARM_INS_VSDOT,
+  ARM_INS_VSELEQ,
+  ARM_INS_VSELGE,
+  ARM_INS_VSELGT,
+  ARM_INS_VSELVS,
+  ARM_INS_VSHL,
+  ARM_INS_VSHLC,
+  ARM_INS_VSHLL,
+  ARM_INS_VSHLLB,
+  ARM_INS_VSHLLT,
+  ARM_INS_VSHR,
+  ARM_INS_VSHRN,
+  ARM_INS_VSHRNB,
+  ARM_INS_VSHRNT,
+  ARM_INS_VSLI,
+  ARM_INS_VSMMLA,
+  ARM_INS_VSQRT,
+  ARM_INS_VSRA,
+  ARM_INS_VSRI,
+  ARM_INS_VST1,
+  ARM_INS_VST2,
+  ARM_INS_VST20,
+  ARM_INS_VST21,
+  ARM_INS_VST3,
+  ARM_INS_VST4,
+  ARM_INS_VST40,
+  ARM_INS_VST41,
+  ARM_INS_VST42,
+  ARM_INS_VST43,
+  ARM_INS_VSTMDB,
+  ARM_INS_VSTMIA,
+  ARM_INS_VSTR,
+  ARM_INS_VSTRB,
+  ARM_INS_VSTRD,
+  ARM_INS_VSTRH,
+  ARM_INS_VSTRW,
+  ARM_INS_VSUB,
+  ARM_INS_VSUBHN,
+  ARM_INS_VSUBL,
+  ARM_INS_VSUBW,
+  ARM_INS_VSUDOT,
+  ARM_INS_VSWP,
+  ARM_INS_VTBL,
+  ARM_INS_VTBX,
+  ARM_INS_VTRN,
+  ARM_INS_VTST,
+  ARM_INS_VUDOT,
+  ARM_INS_VUMMLA,
+  ARM_INS_VUSDOT,
+  ARM_INS_VUSMMLA,
+  ARM_INS_VUZP,
+  ARM_INS_VZIP,
+  ARM_INS_WFE,
+  ARM_INS_WFI,
+  ARM_INS_WLS,
+  ARM_INS_WLSTP,
+  ARM_INS_YIELD,

arch/ARM/ARMInstPrinter.h

@@ -1,9 +1,22 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: 464bda7750a3ba9e23823fc707d7e7b6fc38438d */
+/* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */
+
+/* Only small edits allowed. */
+/* For multiple similiar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
 //===- ARMInstPrinter.h - Convert ARM MCInst to assembly syntax -*- C++ -*-===//
 //
-//                     The LLVM Compiler Infrastructure
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-//
+// See https://llvm.org/LICENSE.txt for license information.
-// This file is distributed under the University of Illinois Open Source
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -11,33 +24,175 @@
 //
 //===----------------------------------------------------------------------===//
 
-/* Capstone Disassembly Engine */
+#ifndef CS_ARM_INSTPRINTER_H
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+#define CS_ARM_INSTPRINTER_H
 
-#ifndef CS_ARMINSTPRINTER_H
+#include <capstone/platform.h>
-#define CS_ARMINSTPRINTER_H
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
 
 #include "../../MCInst.h"
+#include "../../MCInstPrinter.h"
 #include "../../MCRegisterInfo.h"
 #include "../../SStream.h"
+#include "../../utils.h"
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
 
-void ARM_printInst(MCInst *MI, SStream *O, void *Info);
+bool applyTargetSpecificCLOption(const char *Opt);
-void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem, MCInst *mci);
+// Autogenerated by tblgen.
+void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
+void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAM2PostIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAddrMode3Operand(AlwaysPrintImm0)                         \
+	void CONCAT(printAddrMode3Operand,                                         \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printAddrMode3Operand(false) DECLARE_printAddrMode3Operand(true)
 
-// setup handle->get_regname
+	void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void ARM_getRegName(cs_struct *handle, int value);
+void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
+								bool AlwaysPrintImm0);
+void printPostIdxImm8Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printLdStmModeOperand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAddrMode5Operand(AlwaysPrintImm0)                         \
+	void CONCAT(printAddrMode5Operand,                                         \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printAddrMode5Operand(false) DECLARE_printAddrMode5Operand(true)
 
-// specify vector data type for vector instructions
+#define DECLARE_printAddrMode5FP16Operand(AlwaysPrintImm0)                     \
-void ARM_addVectorDataType(MCInst *MI, arm_vectordata_type vd);
+	void CONCAT(printAddrMode5FP16Operand,                                     \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+	DECLARE_printAddrMode5FP16Operand(false)
 
-void ARM_addVectorDataSize(MCInst *MI, int size);
+		void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O);
+void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
+void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAdrLabelOperand(scale)                                    \
+	void CONCAT(printAdrLabelOperand, scale)(MCInst * MI, unsigned OpNum,      \
+											 SStream *O);
+DECLARE_printAdrLabelOperand(0) DECLARE_printAdrLabelOperand(2)
 
-void ARM_addReg(MCInst *MI, int reg);
+#define DEFINE_printAdrLabelOperandAddr(scale)                                 \
+	static inline void CONCAT(printAdrLabelOperandAddr, scale)(                \
+		MCInst * MI, uint64_t Address, unsigned OpNum, SStream *O)             \
+	{                                                                          \
+		CONCAT(printAdrLabelOperand, scale)(MI, OpNum, O);                     \
+	}
+	DEFINE_printAdrLabelOperandAddr(0) DEFINE_printAdrLabelOperandAddr(2)
 
-// load usermode registers (LDM, STM)
+		void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
-void ARM_addUserMode(MCInst *MI);
+void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbITMask(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeRROperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned OpNum, SStream *O,
+									unsigned Scale);
+void printThumbAddrModeImm5S1Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeImm5S2Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeImm5S4Operand(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbAddrModeSPOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printAddrModeImm12Operand(AlwaysPrintImm0)                     \
+	void CONCAT(printAddrModeImm12Operand,                                     \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+DECLARE_printAddrModeImm12Operand(false) DECLARE_printAddrModeImm12Operand(true)
 
-// sysreg for MRS/MSR
+#define DECLARE_printT2AddrModeImm8Operand(AlwaysPrintImm0)                    \
-void ARM_addSysReg(MCInst *MI, arm_sysreg reg);
+	void CONCAT(printT2AddrModeImm8Operand,                                    \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+	DECLARE_printT2AddrModeImm8Operand(true)
+		DECLARE_printT2AddrModeImm8Operand(false)
 
-#endif
+#define DECLARE_printT2AddrModeImm8s4Operand(AlwaysPrintImm0)                  \
+	void CONCAT(printT2AddrModeImm8s4Operand,                                  \
+				AlwaysPrintImm0)(MCInst * MI, unsigned OpNum, SStream *O);
+			DECLARE_printT2AddrModeImm8s4Operand(false)
+				DECLARE_printT2AddrModeImm8s4Operand(true)
+
+					void printT2AddrModeImm0_1020s4Operand(MCInst *MI,
+														   unsigned OpNum,
+														   SStream *O);
+void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printT2AddrModeSoRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O);
+void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O);
+void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum,
+											  SStream *O);
+void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum,
+											SStream *O);
+void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O);
+void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O);
+void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O);
+void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O);
+void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O);
+void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printVMOVModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printImmPlusOneOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printRotImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printModImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printPCLabel(MCInst *MI, unsigned OpNum, SStream *O);
+void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printFBits16(MCInst *MI, unsigned OpNum, SStream *O);
+void printFBits32(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O);
+void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMVEVectorList(NumRegs)                                    \
+	void CONCAT(printMVEVectorList, NumRegs)(MCInst * MI, unsigned OpNum,      \
+											 SStream *O);
+DECLARE_printMVEVectorList(2) DECLARE_printMVEVectorList(4)
+
+#define DECLARE_printComplexRotationOp(Angle, Remainder)                       \
+	void CONCAT(printComplexRotationOp, CONCAT(Angle, Remainder))(             \
+		MCInst * MI, unsigned OpNum, SStream *O);
+	DECLARE_printComplexRotationOp(90, 0)
+		DECLARE_printComplexRotationOp(180, 90)
+
+	// MVE
+	void printVPTPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
+void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O);
+#define DECLARE_printMveAddrModeRQOperand(shift)                               \
+	void CONCAT(printMveAddrModeRQOperand, shift)(MCInst * MI, unsigned OpNum, \
+												  SStream *O);
+DECLARE_printMveAddrModeRQOperand(0) DECLARE_printMveAddrModeRQOperand(3)
+	DECLARE_printMveAddrModeRQOperand(1) DECLARE_printMveAddrModeRQOperand(2)
+
+		void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O);
+
+unsigned translateShiftImm(unsigned imm);
+
+#endif // CS_ARM_INSTPRINTER_H

arch/ARM/ARMLinkage.h

@@ -0,0 +1,21 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
+
+#ifndef CS_ARM_LINKAGE_H
+#define CS_ARM_LINKAGE_H
+
+// Function defintions to call static LLVM functions.
+
+#include "../../MCDisassembler.h"
+#include "../../MCInst.h"
+#include "../../MCRegisterInfo.h"
+#include "../../SStream.h"
+#include "capstone/capstone.h"
+
+DecodeStatus ARM_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
+							MCInst *MI, uint16_t *Size, uint64_t Address,
+							void *Info);
+const char *ARM_LLVM_getRegisterName(unsigned RegNo, unsigned AltIdx);
+void ARM_LLVM_printInstruction(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info);
+
+#endif // CS_ARM_LINKAGE_H

arch/ARM/ARMMapping.h

@@ -1,15 +1,24 @@
 /* Capstone Disassembly Engine */
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
 
-#ifndef CS_ARM_MAP_H
+#ifndef CS_ARM_MAPPING_H
-#define CS_ARM_MAP_H
+#define CS_ARM_MAPPING_H
 
 #include "../../include/capstone/capstone.h"
 #include "../../utils.h"
+#include "ARMBaseInfo.h"
+
+typedef enum {
+#include "ARMGenCSOpGroup.inc"
+} arm_op_group;
+
+extern const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding);
+extern const ARMSysReg_MClassSysReg *ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding);
 
 // return name of regiser in friendly string
 const char *ARM_reg_name(csh handle, unsigned int reg);
-const char *ARM_reg_name2(csh handle, unsigned int reg);
+
+void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */info);
 
 // given internal insn id, return public instruction ID
 void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
@@ -23,18 +32,48 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
 
 bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);
 
-const uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
+void ARM_reg_access(const cs_insn *insn, cs_regs regs_read,
+					uint8_t *regs_read_count, cs_regs regs_write,
+					uint8_t *regs_write_count);
 
-void ARM_reg_access(const cs_insn *insn,
+const ARMBankedReg_BankedReg *ARMBankedReg_lookupBankedRegByEncoding(uint8_t encoding);
-		cs_regs regs_read, uint8_t *regs_read_count,
-		cs_regs regs_write, uint8_t *regs_write_count);
 
-typedef struct BankedReg {
+bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len,
-	const char *Name;
+						MCInst *instr, uint16_t *size, uint64_t address,
-	arm_sysreg sysreg;
+						void *info);
-	uint16_t Encoding;
+void ARM_set_instr_map_data(MCInst *MI);
-} BankedReg;
 
-const BankedReg *lookupBankedRegByEncoding(uint8_t encoding);
+void ARM_init_mri(MCRegisterInfo *MRI);
 
-#endif
+// cs_detail related functions
+void ARM_init_cs_detail(MCInst *MI);
+void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+					   va_list args);
+static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group,
+								 ...)
+{
+	if (!MI->flat_insn->detail)
+		return;
+	va_list args;
+	va_start(args, op_group);
+	ARM_add_cs_detail(MI, op_group, args);
+	va_end(args);
+}
+
+void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, cs_ac_type access);
+void ARM_set_detail_op_reg(MCInst *MI, unsigned OpNum, arm_reg Reg);
+void ARM_set_detail_op_sysreg(MCInst *MI, int SysReg, bool IsOutReg);
+void ARM_set_detail_op_imm(MCInst *MI, unsigned OpNum, arm_op_type ImmType,
+						   int64_t Imm);
+void ARM_set_detail_op_float(MCInst *MI, unsigned OpNum, uint64_t Imm);
+void ARM_set_detail_op_mem(MCInst *MI, unsigned OpNum, bool is_index_reg,
+						   int scale, int lshift, uint64_t Val);
+void ARM_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val,
+								  bool subtracted);
+void ARM_set_detail_op_neon_lane(MCInst *MI, unsigned OpNum);
+
+void ARM_check_updates_flags(MCInst *MI);
+
+void ARM_setup_op(cs_arm_op *op);
+
+#endif // CS_ARM_MAPPING_H

arch/ARM/ARMModule.c

@@ -1,60 +1,49 @@
 /* Capstone Disassembly Engine */
 /* By Dang Hoang Vu <danghvu@gmail.com> 2013 */
 
+#include "capstone/capstone.h"
 #ifdef CAPSTONE_HAS_ARM
 
-#include "../../cs_priv.h"
+#include "ARMModule.h"
 #include "../../MCRegisterInfo.h"
-#include "ARMDisassembler.h"
+#include "../../cs_priv.h"
 #include "ARMInstPrinter.h"
 #include "ARMMapping.h"
-#include "ARMModule.h"
 
 cs_err ARM_global_init(cs_struct *ud)
 {
 	MCRegisterInfo *mri;
 	mri = cs_mem_malloc(sizeof(*mri));
 
-	ARM_init(mri);
+	ARM_init_mri(mri);
-	ARM_getRegName(ud, 0);	// use default get_regname
 
-	ud->printer = ARM_printInst;
+	ud->printer = ARM_printer;
 	ud->printer_info = mri;
 	ud->reg_name = ARM_reg_name;
 	ud->insn_id = ARM_get_insn_id;
 	ud->insn_name = ARM_insn_name;
 	ud->group_name = ARM_group_name;
-	ud->post_printer = ARM_post_printer;
+	ud->post_printer = NULL;
 #ifndef CAPSTONE_DIET
 	ud->reg_access = ARM_reg_access;
 #endif
 
-	if (ud->mode & CS_MODE_THUMB)
+	ud->disasm = ARM_getInstruction;
-		ud->disasm = Thumb_getInstruction;
-	else
-		ud->disasm = ARM_getInstruction;
 
 	return CS_ERR_OK;
 }
 
 cs_err ARM_option(cs_struct *handle, cs_opt_type type, size_t value)
 {
-	switch(type) {
+	switch (type) {
-		case CS_OPT_MODE:
+	case CS_OPT_MODE:
-			if (value & CS_MODE_THUMB)
+		handle->mode = (cs_mode)value;
-				handle->disasm = Thumb_getInstruction;
+		break;
-			else
+	case CS_OPT_SYNTAX:
-				handle->disasm = ARM_getInstruction;
+		handle->syntax |= (int)value;
-
+		break;
-			handle->mode = (cs_mode)value;
+	default:
-
+		break;
-			break;
-		case CS_OPT_SYNTAX:
-			ARM_getRegName(handle, (int)value);
-			handle->syntax = (int)value;
-			break;
-		default:
-			break;
 	}
 
 	return CS_ERR_OK;

arch/BPF/BPFMapping.c

@@ -5,6 +5,7 @@
 
 #include "BPFConstants.h"
 #include "BPFMapping.h"
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #ifndef CAPSTONE_DIET

arch/EVM/EVMMapping.c

@@ -6,6 +6,7 @@
 #include <string.h>
 
 #include "../../cs_priv.h"
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "EVMMapping.h"

arch/M680X/M680XInstPrinter.c

@@ -11,6 +11,8 @@
 #include "../../MCInst.h"
 #include "../../SStream.h"
 #include "../../MCRegisterInfo.h"
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
 #include "../../utils.h"
 #include "M680XInstPrinter.h"
 #include "M680XDisassembler.h"

arch/M68K/M68KInstPrinter.c

@@ -21,6 +21,7 @@
 #include "M68KDisassembler.h"
 
 #include "../../cs_priv.h"
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "../../MCInst.h"

arch/Mips/MipsMapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "MipsMapping.h"

arch/PowerPC/PPCMapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "PPCMapping.h"

arch/RISCV/RISCVMapping.c

@@ -4,6 +4,7 @@
 #include <stdio.h>		// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "RISCVMapping.h"

arch/SH/SHInstPrinter.c

@@ -2,6 +2,8 @@
 /* By Yoshinori Sato, 2022 */
 
 #include <string.h>
+
+#include "../../Mapping.h"
 #include "SHInstPrinter.h"
 
 

arch/Sparc/SparcMapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "SparcMapping.h"

arch/SystemZ/SystemZMapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "SystemZMapping.h"

arch/TMS320C64x/TMS320C64xMapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "TMS320C64xMapping.h"

arch/TriCore/TriCoreInstPrinter.c

@@ -23,6 +23,7 @@
 
 #include "../../MCInst.h"
 #include "../../MCRegisterInfo.h"
+#include "../../Mapping.h"
 #include "../../MathExtras.h"
 #include "../../SStream.h"
 #include "../../utils.h"

arch/TriCore/TriCoreMapping.c

@@ -7,6 +7,7 @@
 #include <string.h>
 #include <assert.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 #include "../../cs_simple_types.h"
 
@@ -136,7 +137,7 @@ typedef struct {
 	insn_op ops[16]; ///< NULL terminated array of operands.
 } insn_ops;
 
-const insn_ops insn_operands[] = {
+static const insn_ops insn_operands[] = {
 #include "TriCoreGenCSMappingInsnOp.inc"
 };
 #endif

arch/WASM/WASMMapping.c

@@ -8,6 +8,7 @@
 #include "../../cs_priv.h"
 #include "../../utils.h"
 
+#include "../../Mapping.h"
 #include "WASMMapping.h"
 
 // fill in details

arch/X86/X86Mapping.c

@@ -12,6 +12,8 @@
 #include <stdlib.h>
 #endif
 
+#include "../../Mapping.h"
+#include "../../MCInstPrinter.h"
 #include "X86Mapping.h"
 #include "X86DisassemblerDecoder.h"
 

arch/XCore/XCoreMapping.c

@@ -6,6 +6,7 @@
 #include <stdio.h>	// debug
 #include <string.h>
 
+#include "../../Mapping.h"
 #include "../../utils.h"
 
 #include "XCoreMapping.h"

cs.c

@@ -815,6 +815,10 @@ cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
 				return CS_ERR_OPTION;
 			}
 			break;
+		case CS_OPT_NO_BRANCH_OFFSET:
+			if (handle->PrintBranchImmNotAsAddress)
+				return CS_ERR_OK;
+			break;
 	}
 
 	return arch_configs[handle->arch].arch_option(handle, type, value);
@@ -883,10 +887,6 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64
 
 	handle->errnum = CS_ERR_OK;
 
-	// reset IT block of ARM structure
-	if (handle->arch == CS_ARCH_ARM)
-		handle->ITBlock.size = 0;
-
 #ifdef CAPSTONE_USE_SYS_DYN_MEM
 	if (count > 0 && count <= INSN_CACHE_SIZE)
 		cache_size = (unsigned int) count;

cs_operand.h

@@ -0,0 +1,38 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+/*    Rot127 <unisono@quyllur.org>, 2022-2023 */
+
+#ifndef CS_OPERAND_H
+#define CS_OPERAND_H
+
+/// Common instruction operand types - to be consistent across all architectures.
+typedef enum cs_op_type {
+	CS_OP_INVALID = 0,  ///< uninitialized/invalid operand.
+	CS_OP_REG = 1,          ///< Register operand.
+	CS_OP_IMM = 2,          ///< Immediate operand.
+	CS_OP_FP = 3,           ///< Floating-Point operand.
+	CS_OP_PRED = 4,				  ///< Predicate operand.
+	CS_OP_RESERVED_5 = 5,
+	CS_OP_RESERVED_6 = 6,
+	CS_OP_RESERVED_7 = 7,
+	CS_OP_RESERVED_8 = 8,
+	CS_OP_RESERVED_9 = 9,
+	CS_OP_RESERVED_10 = 10,
+	CS_OP_RESERVED_11 = 11,
+	CS_OP_RESERVED_12 = 12,
+	CS_OP_RESERVED_13 = 13,
+	CS_OP_RESERVED_14 = 14,
+	CS_OP_RESERVED_15 = 15,
+	CS_OP_SPECIAL = 0x10, ///< Special operands from archs
+	CS_OP_MEM = 0x80,   ///< Memory operand. Can be ORed with another operand type.
+} cs_op_type;
+
+/// Common instruction operand access types - to be consistent across all architectures.
+/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
+typedef enum cs_ac_type {
+	CS_AC_INVALID = 0,        ///< Uninitialized/invalid access type.
+	CS_AC_READ    = 1 << 0,   ///< Operand read from memory or register.
+	CS_AC_WRITE   = 1 << 1,   ///< Operand write to memory or register.
+} cs_ac_type;
+
+#endif // CS_OPERAND_H

cs_priv.h

@@ -24,19 +24,21 @@ typedef const char *(*GetName_t)(csh handle, unsigned int id);
 
 typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
 
-// return register name, given register ID
-typedef const char *(*GetRegisterName_t)(unsigned RegNo);
-
 // return registers accessed by instruction
 typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
 		cs_regs regs_read, uint8_t *regs_read_count,
 		cs_regs regs_write, uint8_t *regs_write_count);
 
 // for ARM only
-typedef struct ARM_ITStatus {
+typedef struct ARM_ITBlock {
 	unsigned char ITStates[8];
 	unsigned int size;
-} ARM_ITStatus;
+} ARM_ITBlock;
+
+typedef struct ARM_VPTBlock {
+	unsigned char VPTStates[8];
+	unsigned int size;
+} ARM_VPTBlock;
 
 // Customize mnemonic for instructions with alternative name.
 struct customized_mnem {
@@ -64,13 +66,14 @@ struct cs_struct {
 	GetID_t insn_id;
 	PostPrinter_t post_printer;
 	cs_err errnum;
-	ARM_ITStatus ITBlock;	// for Arm only
+	ARM_ITBlock ITBlock;	// for Arm only
+	ARM_VPTBlock VPTBlock;  // for ARM only
+	bool PrintBranchImmNotAsAddress;
 	cs_opt_value detail, imm_unsigned;
 	int syntax;	// asm syntax for simple printer such as ARM, Mips & PPC
 	bool doing_mem;	// handling memory operand in InstPrinter code
 	bool doing_SME_Index; // handling a SME instruction that has index
 	unsigned short *insn_cache;	// index caching for mapping.c
-	GetRegisterName_t get_regname;
 	bool skipdata;	// set this to True if we skip data when disassembling
 	uint8_t skipdata_size;	// how many bytes to skip
 	cs_opt_skipdata skipdata_setup;	// user-defined skipdata setup

cstool/cstool.c

@@ -26,6 +26,7 @@ static struct {
 	{ "armv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
 	{ "thumbv8be", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_BIG_ENDIAN },
 	{ "cortexm", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS },
+	{ "cortexv8m", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_MCLASS | CS_MODE_V8 },
 	{ "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
 	{ "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
 	{ "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
@@ -195,6 +196,7 @@ static void usage(char *prog)
 		printf("        thumb       thumb mode\n");
 		printf("        thumbbe     thumb + big endian\n");
 		printf("        cortexm     thumb + cortex-m extensions\n");
+		printf("        cortexv8m   thumb + cortex-m extensions + v8\n");
 		printf("        armv8       arm v8\n");
 		printf("        thumbv8     thumb v8\n");
 		printf("        armv8be     arm v8 + big endian\n");
@@ -387,7 +389,7 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
 		default: break;
 	}
 
-	if (ins->detail->groups_count) {
+	if (ins->detail && ins->detail->groups_count) {
 		int j;
 
 		printf("\tGroups: ");
@@ -415,10 +417,14 @@ int main(int argc, char **argv)
 	bool detail_flag = false;
 	bool unsigned_flag = false;
 	bool skipdata = false;
+	bool custom_reg_alias = false;
 	int args_left;
 
-	while ((c = getopt (argc, argv, "sudhv")) != -1) {
+	while ((c = getopt (argc, argv, "asudhv")) != -1) {
 		switch (c) {
+			case 'a':
+				custom_reg_alias = true;
+				break;
 			case 's':
 				skipdata = true;
 				break;
@@ -583,6 +589,10 @@ int main(int argc, char **argv)
 		cs_option(handle, CS_OPT_UNSIGNED, CS_OPT_ON);
 	}
 
+	if (custom_reg_alias) {
+		cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_CS_REG_ALIAS);
+	}
+
 	count = cs_disasm(handle, assembly, size, address, 0, &insn);
 	if (count > 0) {
 		size_t i;

cstool/cstool_arm.c

@@ -28,8 +28,16 @@ void print_insn_detail_arm(csh handle, cs_insn *ins)
 			case ARM_OP_REG:
 				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
 				break;
-			case ARM_OP_IMM:
+			case ARM_OP_IMM: {
-				printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
+				bool neg_imm = op->imm < 0;
+				if (neg_imm)
+					printf("\t\toperands[%u].type: IMM = -0x%lx\n", i, -(op->imm));
+				else
+					printf("\t\toperands[%u].type: IMM = 0x%lx\n", i, op->imm);
+				break;
+			}
+			case ARM_OP_PRED:
+				printf("\t\toperands[%u].type: PRED = %d\n", i, op->pred);
 				break;
 			case ARM_OP_FP:
 #if defined(_KERNEL_MODE)
@@ -105,14 +113,19 @@ void print_insn_detail_arm(csh handle, cs_insn *ins)
 			printf("\t\tSubtracted: True\n");
 	}
 
-	if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
+	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF)
 		printf("\tCode condition: %u\n", arm->cc);
 
+	if (arm->vcc != ARMVCC_None)
+		printf("\tVector code condition: %u\n", arm->vcc);
+
 	if (arm->update_flags)
 		printf("\tUpdate-flags: True\n");
 
-	if (arm->writeback)
+	if (ins->detail->writeback) {
 		printf("\tWrite-back: True\n");
+		printf("\tPost index: %s\n", arm->post_index ? "true" : "false");
+	}
 
 	if (arm->cps_mode)
 		printf("\tCPSI-mode: %u\n", arm->cps_mode);
@@ -132,6 +145,9 @@ void print_insn_detail_arm(csh handle, cs_insn *ins)
 	if (arm->mem_barrier)
 		printf("\tMemory-barrier: %u\n", arm->mem_barrier);
 
+	if (arm->pred_mask)
+		printf("\tPredicate Mask: 0x%x\n", arm->pred_mask);
+
 	// Print out all registers accessed by this instruction (either implicit or explicit)
 	if (!cs_regs_access(handle, ins,
 				regs_read, &regs_read_count,

docs/ARCHITECTURE.md

@@ -0,0 +1,118 @@
+# Capstone Architecture overview
+
+## Architecture of Capstone
+
+TODO
+
+## Architecture of a Module
+
+An architecture module is split into two components.
+
+1. The disassembler logic, which decodes bytes to instructions.
+2. The mapping logic, which maps the result from component 1 to
+a Capstone internal representation and adds additional detail.
+
+### Component 1 - Disassembler logic
+
+The disassembler logic consists exclusively of code from LLVM.
+It uses:
+
+- Generated state machines, enums and the like for instruction decoding.
+- Handwritten disassembler logic for decoding instruction operands
+and controlling the decoding procedure.
+
+### Component 2 - Mapping logic
+
+The mapping component has three different task:
+
+1. Serving as programmable interface for the Capstone core to the LLVM code.
+2. Mapping LLVM decoded instructions to a Capstone instruction.
+3. Adding additional detail to the Capstone instructions
+(e.g. operand `read/write` attributes etc.).
+
+### Instruction representation
+
+There exist two structs which represent an instruction:
+
+- `MCInst`: The LLVM representation of an instruction.
+- `cs_insn`: The Capstone representation of an instruction.
+
+The `MCInst` is used by the disassembler component for storing the decoded instruction.
+The mapping component on the other hand, uses the `MCInst` to populate the `cs_insn`.
+
+The `cs_insn` is meant to be used by the Capstone core.
+It is distinct from the `MCInst`. It uses different instruction identifiers, other operand representation
+and holds more details about an instruction.
+
+### Disassembling process
+
+There are two steps in disassembling an instruction.
+
+1. Decoding bytes to a `MCInst`.
+2. Decoding the assembler string for the `MCInst` AND mapping it to a `cs_insn` in the same step.
+
+Here is a boiled down explanation about these steps.
+
+**Step 1**
+
+```
+                                                             Forward to               
+                                     getInstr(bytes)    ┌───┐LLVM code     ┌─────────┐            ┌──────────┐
+                                    ┌──────────────────►│ A ├────────────► │         ├───────────►│          ├────┐
+                                    │                   │ R │              │ LLVM    │            │ LLVM     │    │ Decode
+                                    │                   │ C │              │         │            │          │    │ Instr.
+                                    │                   │ H │              │         │decode(Op0) │          │◄───┘
+┌────────┐ disasm(bytes) ┌──────────┴──┐                │   │              │ Disass- │ ◄──────────┤ Decoder  │
+│CS Core ├──────────────►│ ARCH Module │                │   │              │ embler  ├──────────► │ State    │
+└────────┘               └─────────────┘                │ M │              │         │            │ Machine  │
+                                    ▲                   │ A │              │         │decode(Op1) │          │
+                                    │                   │ P │              │         │ ◄──────────┤          │
+                                    │                   │ P │              │         ├──────────► │          │
+                                    │                   │ I │              │         │            │          │
+                                    │                   │ N │              │         │            │          │
+                                    └───────────────────┤ G │◄─────────────┤         │◄───────────┤          │
+                                                        └───┘              └─────────┘            └──────────┘
+```
+
+In the first decoding step the instruction bytes get forwarded to the
+decoder state machine.
+After the instruction was identified, the state machine calls decoder functions
+for each operand to extract the operand values from the bytes.
+
+The disassembler and the state machine are equivalent to what `llvm-objdump` uses
+(in fact they use the same files, except we translated them from C++ to C).
+
+**Step 2**
+
+```
+                                                        printInst(
+                                                               MCInst,
+                                                   ┌───┐       asm_buf) ┌────────┐            ┌──────────┐
+                                      ┌───────────►│ A ├──────────────► │        ├───────────►│          ├──────┐
+                                      │            │ R │                │ LLVM   │            │ LLVM     │      │ Decode
+                                      │            │ C │ add_cs_detail  │        │            │          │      │ Mnemonic
+                                      │            │ H │ (Op0)          │        │ print(Op0) │          │◄─────┘
+                                      │            │   │ ◄──────────────┤        │ ◄──────────┤          │
+           printer(MCInst,            │            │   ├──────────────► │        ├──────────► │ Asm-     │
+┌────────┐         asm_buf)┌──────────┴──┐         │   │                │ Inst   │            │ Writer   │
+│CS Core ├────────────────►│ ARCH Module │         │   │                │ Printer│            │ State    │
+└────────┘                 └─────────────┘         │ M │ add_cs_detail  │        │            │ Machine  │
+                                      ▲            │ A │ (Op1)          │        │ print(Op1) │          │
+                                      │            │ P │ ◄──────────────┤        │ ◄──────────┤          │
+                                      │            │ P ├──────────────► │        ├──────────► │          │
+                                      │            │ I │                │        │            │          │
+                                      │            │ N │                │        │            │          │
+                                      └────────────┤ G │◄───────────────┤        │◄───────────┤          │
+                                                   └───┘                └────────┘            └──────────┘
+```
+
+The second decoding step passes the `MCInst` and a buffer to the printer.
+
+After determining the mnemonic, each operand is printed by using
+functions defined in the `InstPrinter`.
+
+Each time an operand is printed, the mapping component is called
+to populate the `cs_insn` with the operand information and details.
+
+Again the `InstPrinter` and `AsmWriter` are translated code from LLVM,
+and with that mirror the behavior of `llvm-objdump`.

docs/AutoSync.md

@@ -0,0 +1,198 @@
+# Auto-Sync
+
+`auto-sync` is the architecture update tool for Capstone.
+Because the architecture modules of Capstone use mostly code from LLVM,
+we need to update this part with every LLVM release. `auto-sync` helps
+with this synchronization between LLVM and Capstone's modules by
+automating most of it.
+
+You can find it in `suite/auto-sync`.
+
+This document is split into four parts.
+
+1. An overview of the update process and which subcomponents of `auto-sync` do what.
+2. The instructions how to update an architecture which already supports `auto-sync`.
+3. Instructions how to refactor an architecture to use `auto-sync`.
+4. Notes about how to add a new architecture to Capstone with `auto-sync`.
+
+Please read the section about architecture module design in
+[ARCHITECTURE.md](ARCHITECTURE.md) before proceeding.
+The architectural understanding is important for the following.
+
+## Update procedure
+
+As already described in the `ARCHITECTURE` document, Capstone uses translated
+and generated source code from LLVM.
+
+Because LLVM is written in C++ and Capstone in C the update process is
+internally complicated but almost completely automated.
+
+`auto-sync` categorizes source files of a module into three groups. Each group is updated differently.
+
+| File type                         | Update method | Edits by hand |
+|-----------------------------------|----------------------|------------------------|
+| Generated files | Generated by patched LLVM backends | Never/Not allowed |
+| Translated LLVM C++ files         | `CppTranslater` and `Differ` | Only changes which are too complicated for automation. |
+| Capstone files                    | By hand | all |
+
+Let's look at the update procedure for each group in detail.
+
+**Note**: The only exception to touch generated files is via git patches. This is the last resort
+if something is broken in LLVM, and we cannot generate correct files.
+
+**Generated files**
+
+Generated files always have the file extension `.inc`.
+
+There are generated files for the LLVM code and for Capstone. They can be distinguished by their names:
+
+- For Capstone: `<ARCH>GenCS<NAME>.inc`.
+- For LLVM code: `<ARCH>Gen<NAME>.inc`.
+
+The files are generated by refactored [LLVM TableGen emitter backends](https://github.com/capstone-engine/llvm-capstone/tree/dev/llvm/utils/TableGen).
+
+The procedure looks roughly like this:
+
+```
+                                                                   ┌──────────┐
+    1               2                 3                4           │CS .inc   │
+┌───────┐     ┌───────────┐     ┌───────────┐     ┌──────────┐  ┌─►│files     │
+│ .td   │     │           │     │           │     │ Code-    │  │  └──────────┘
+│ files ├────►│ TableGen  ├────►│  CodeGen  ├────►│ Emitter  ├──┤
+└───────┘     └──────┬────┘     └───────────┘     └──────────┘  │  ┌──────────┐
+                     │                                 ▲        └─►│LLVM .inc │
+                     └─────────────────────────────────┘           │files     │
+                                                                   └──────────┘
+```
+
+
+1. LLVM architectures are defined in `.td` files. They describe instructions, operands,
+features and other properties of an architecture.
+
+2. [LLVM TableGen](https://llvm.org/docs/TableGen/index.html) parses these files
+and converts them to an internal representation.
+
+3. In the second step a TableGen component called [CodeGen](https://llvm.org/docs/CodeGenerator.html)
+abstracts the these properties even further.
+The result is a representation which is _not_ specific to any architecture
+(e.g. the `CodeGenInstruction` class can represent a machine instruction of any architecture).
+
+4. The `Code-Emitter` uses the abstract representation of the architecture (provided from `CodeGen`) to
+generated state machines for instruction decoding.
+Architecture specific information (think of register names, operand properties etc.)
+is taken from `TableGen's` internal representation.
+
+The result is emitted to `.inc` files. Those are included in the translated C++ files or Capstone code where necessary.
+
+**Translation of LLVM C++ files**
+
+We use two tools to translate C++ to C files.
+
+First the `CppTranslator` and afterward the `Differ`.
+
+The `CppTranslator` parses the C++ files and patches C++ syntax
+with its equivalent C syntax.
+
+_Note_: For details about this checkout `suite/auto-sync/CppTranslator/README.md`.
+
+Because the result of the `CppTranslator` is not perfect,
+we still have many syntax problems left.
+
+Those need to be fixed by hand.
+In order to ease this process we run the `Differ` after the `CppTranslator`.
+
+The `Differ` parses each _translated_ file and the corresponding source file _currently_ used in Capstone.
+It then compares specific nodes from the just translated file to the equivalent nodes in the old file.
+
+The user can choose if she accepts the version from the translated file or the old file.
+This decision is saved for every node.
+If there exists a saved decision for a node, the previous decision automatically applied again.
+
+Every other syntax error must be solved manually.
+
+## Update an architecture
+
+To update an architecture do the following:
+
+Rebase `llvm-capstone` onto the new LLVM release (if not already done).
+```
+# 1. Clone Capstone's LLVM
+git clone https://github.com/capstone-engine/llvm-capstone
+
+# 2. Rebase onto the new LLVM release and resolve the conflicts.
+
+# 3. Build tblgen
+mkdir build
+cd build
+cmake -G Ninja -DLLVM_TARGETS_TO_BUILD=<ARCH> -DCMAKE_BUILD_TYPE=Debug ../llvm
+cmake --build . --target llvm-tblgen --config Debug
+
+# 4. Run git log and copy the hash of the release commit for the next step.
+git log
+
+# 5. Run the updater
+cd ../../suite/auto-sync/
+mkdir build
+cd build
+../Update-Arch.sh <ARCH> <PATH-TO-LLVM> <LLVM-RELEASE_HASH>
+```
+
+The update script will execute the steps described above and copy the new files to their directories.
+
+Afterward try to build Capstone and fix any build errors left.
+
+If new instructions or operands were added, add test cases for those
+(recession tests for instructions are located in `suite/MC/`).
+
+TODO: Operand and detail tests
+<!--
+TODO: Wait until `cstest` is rewritten and add description about operand testing.
+Issue: https://github.com/capstone-engine/capstone/issues/1984
+-->
+
+## Refactor an architecture for `auto-sync`
+
+To refactor an architecture to use `auto-sync`, you need to add it to the configuration.
+
+1. Add the architecture to the supported architectures list in `Update-Arch.sh`.
+2. Configure the `CppTranslator` for your architecture (`suite/auto-sync/CppTranslator/arch_config.json`)
+
+Now, manually run the update commands within `Update-Arch.sh` but *skip* the `Differ` step.
+
+The task after this is to:
+
+- Replace leftover C++ syntax with its C equivalent.
+- Implement the `add_cs_detail()` handler in `<ARCH>Mapping` for each operand type.
+- Add any missing logic to the translated files.
+- Make it build and write tests.
+- Run the Differ again and always select the old nodes.
+
+**Notes:**
+
+- If you find yourself fixing the same syntax error multiple times,
+please consider adding a `Patch` to the `CppTranslator` for this case.
+
+- Please check out the implementation of ARM's `add_cs_detail()` before implementing your own.
+
+- Running the `Differ` after everything is done, preserves your version of syntax corrections, and the next user can auto-apply them.
+
+- Sometimes the LLVM code uses a single function from a larger source file.
+It is not worth it to translate the whole file just for this function.
+Bundle those lonely functions in `<ARCH>DisassemblerExtension.c`.
+
+- Some generated enums must be included in the `include/capstone/<ARCH>.h` header.
+At the position where the enum should be inserted, add a comment like this (don't remove the `<>` brackets):
+
+    ```
+    // generate content <FILENAME.inc> begin
+    // generate content <FILENAME.inc> end
+    ```
+
+The update script will insert the content of the `.inc` file at this place.
+
+## Adding a new architecture
+
+Adding a new architecture follows the same steps as above. With the exception that you need
+to implement all the Capstone files from scratch.
+
+Check out an `auto-sync` supporting architectures for guidance and open an issue if you need help.

include/capstone/capstone.h

@@ -17,6 +17,7 @@ extern "C" {
 #include <stdio.h>
 #endif
 
+#include "../../cs_operand.h"
 #include "platform.h"
 
 #ifdef _MSC_VER
@@ -216,33 +217,16 @@ typedef enum cs_opt_type {
 /// Runtime option value (associated with option type above)
 typedef enum cs_opt_value {
 	CS_OPT_OFF = 0,  ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
-	CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
+	CS_OPT_ON = 1 << 0, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
-	CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_DEFAULT = 1 << 1, ///< Default asm syntax (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_INTEL = 1 << 2, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_ATT,   ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_ATT = 1 << 3,   ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)
+	CS_OPT_SYNTAX_NOREGNAME = 1 << 4, ///< Prints register name with only number (CS_OPT_SYNTAX)
-	CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_MASM = 1 << 5, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
-	CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix
+	CS_OPT_SYNTAX_MOTOROLA = 1 << 6, ///< MOS65XX use $ as hex prefix
+	CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7, ///< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
 } cs_opt_value;
 
-/// Common instruction operand types - to be consistent across all architectures.
-typedef enum cs_op_type {
-	CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
-	CS_OP_REG,	   ///< Register operand.
-	CS_OP_IMM,	   ///< Immediate operand.
-	CS_OP_FP,	   ///< Floating-Point operand.
-	CS_OP_MEM =
-		0x80, ///< Memory operand. Can be ORed with another operand type.
-} cs_op_type;
-
-/// Common instruction operand access types - to be consistent across all architectures.
-/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
-typedef enum cs_ac_type {
-	CS_AC_INVALID = 0,        ///< Uninitialized/invalid access type.
-	CS_AC_READ    = 1 << 0,   ///< Operand read from memory or register.
-	CS_AC_WRITE   = 1 << 1,   ///< Operand write to memory or register.
-} cs_ac_type;
-
 /// Common instruction groups - to be consistent across all architectures.
 typedef enum cs_group_type {
 	CS_GRP_INVALID = 0,  ///< uninitialized/invalid group.

include/capstone/tricore.h

@@ -12,6 +12,7 @@ extern "C" {
 #include <stdint.h>
 #endif
 
+#include "../../cs_operand.h"
 #include "platform.h"
 
 #ifdef _MSC_VER

suite/MC/ARM/arm-arithmetic-aliases.s.cs

@@ -47,4 +47,4 @@
 0x06,0x20,0xd2,0x03 = bicseq r2, r2, #6
 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3
 0x03,0x20,0xd2,0x01 = bicseq r2, r2, r3
-0x7b,0x00,0x8f,0xe2 = add r0, pc, #123
+0x7b,0x00,0x8f,0xe2 = add r0, pc, #0x7b

suite/MC/ARM/arm-branches.s.cs

@@ -0,0 +1,6 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x01,0x00,0x00,0xea = b #4
+0x01,0x00,0x00,0xeb = bl #4
+0x01,0x00,0x00,0x0a = beq #4
+0x00,0x00,0x00,0xfb = blx #2
+0x01,0x00,0x00,0xea = b #4

suite/MC/ARM/arm-memory-instructions.s.cs

@@ -1,9 +1,9 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
 0x00,0x50,0x97,0xe5 = ldr r5, [r7]
-0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #63]
+0x3f,0x60,0x93,0xe5 = ldr r6, [r3, #0x3f]
-0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #4095]!
+0xff,0x2f,0xb4,0xe5 = ldr r2, [r4, #0xfff]!
-0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #30
+0x1e,0x10,0x92,0xe4 = ldr r1, [r2], #0x1e
-0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-30
+0x1e,0x30,0x11,0xe4 = ldr r3, [r1], #-0x1e
 0x00,0x90,0x12,0xe4 = ldr r9, [r2], #-0
 0x01,0x30,0x98,0xe7 = ldr r3, [r8, r1]
 0x03,0x20,0x15,0xe7 = ldr r2, [r5, -r3]
@@ -12,28 +12,28 @@
 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
 0x02,0x50,0x99,0xe6 = ldr r5, [r9], r2
 0x06,0x40,0x13,0xe6 = ldr r4, [r3], -r6
-0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #15]
+0x82,0x37,0x18,0xe7 = ldr r3, [r8, -r2, lsl #0xf]
-0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #15
+0xc3,0x17,0x95,0xe6 = ldr r1, [r5], r3, asr #0xf
 0x00,0x30,0xd8,0xe5 = ldrb r3, [r8]
-0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #63]
+0x3f,0x10,0xdd,0xe5 = ldrb r1, [sp, #0x3f]
-0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #4095]!
+0xff,0x9f,0xf3,0xe5 = ldrb r9, [r3, #0xfff]!
-0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #22
+0x16,0x80,0xd1,0xe4 = ldrb r8, [r1], #0x16
-0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-19
+0x13,0x20,0x57,0xe4 = ldrb r2, [r7], #-0x13
 0x05,0x90,0xd8,0xe7 = ldrb r9, [r8, r5]
 0x01,0x10,0x55,0xe7 = ldrb r1, [r5, -r1]
 0x02,0x30,0xf5,0xe7 = ldrb r3, [r5, r2]!
 0x03,0x60,0x79,0xe7 = ldrb r6, [r9, -r3]!
 0x04,0x20,0xd1,0xe6 = ldrb r2, [r1], r4
 0x05,0x80,0x54,0xe6 = ldrb r8, [r4], -r5
-0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #15]
+0x81,0x77,0x5c,0xe7 = ldrb r7, [r12, -r1, lsl #0xf]
-0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #15
+0xc9,0x57,0xd2,0xe6 = ldrb r5, [r2], r9, asr #0xf
 0x04,0x30,0xf1,0xe4 = ldrbt r3, [r1], #4
 0x08,0x20,0x78,0xe4 = ldrbt r2, [r8], #-8
 0x06,0x80,0xf7,0xe6 = ldrbt r8, [r7], r6
-0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #12
+0x06,0x16,0x72,0xe6 = ldrbt r1, [r2], -r6, lsl #0xc
 0xd0,0x20,0xc5,0xe1 = ldrd r2, r3, [r5]
-0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #15]
+0xdf,0x60,0xc2,0xe1 = ldrd r6, r7, [r2, #0xf]
-0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #32]!
+0xd0,0x02,0xe9,0xe1 = ldrd r0, r1, [r9, #0x20]!
 0xd8,0x60,0xc1,0xe0 = ldrd r6, r7, [r1], #8
 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
 0xd0,0x00,0xc8,0xe0 = ldrd r0, r1, [r8], #0
@@ -44,48 +44,51 @@
 0xdc,0x00,0x08,0xe0 = ldrd r0, r1, [r8], -r12
 0xb0,0x30,0xd4,0xe1 = ldrh r3, [r4]
 0xb4,0x20,0xd7,0xe1 = ldrh r2, [r7, #4]
-0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #64]!
+0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #0x40]!
-0xb4,0xc0,0xdd,0xe0 = ldrh ip, [sp], #4
+0xb4,0xc0,0xdd,0xe0 = ldrh r12, [sp], #4
 0xb4,0x60,0x95,0xe1 = ldrh r6, [r5, r4]
 0xbb,0x30,0xb8,0xe1 = ldrh r3, [r8, r11]!
 0xb1,0x10,0x32,0xe1 = ldrh r1, [r2, -r1]!
 0xb2,0x90,0x97,0xe0 = ldrh r9, [r7], r2
 0xb2,0x40,0x13,0xe0 = ldrh r4, [r3], -r2
-0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #128
+0xb0,0x98,0xf7,0xe0 = ldrht r9, [r7], #0x80
-0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-75
+0xbb,0x44,0x73,0xe0 = ldrht r4, [r3], #-0x4b
+0xb0,0x40,0xf3,0xe0 = ldrht r4, [r3], #0
 0xb2,0x90,0xb7,0xe0 = ldrht r9, [r7], r2
 0xb2,0x40,0x33,0xe0 = ldrht r4, [r3], -r2
 0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4]
-0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #17]
+0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #0x11]
-0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #255]!
+0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #0xff]!
-0xd9,0xc0,0xdd,0xe0 = ldrsb ip, [sp], #9
+0xd9,0xc0,0xdd,0xe0 = ldrsb r12, [sp], #0x9
 0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4]
 0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]!
 0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]!
 0xd2,0x90,0x97,0xe0 = ldrsb r9, [r7], r2
 0xd2,0x40,0x13,0xe0 = ldrsb r4, [r3], -r2
 0xd1,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #1
-0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-12
+0xdc,0x30,0x78,0xe0 = ldrsbt r3, [r8], #-0xc
+0xd0,0x50,0xf6,0xe0 = ldrsbt r5, [r6], #0
 0xd5,0x80,0xb9,0xe0 = ldrsbt r8, [r9], r5
 0xd4,0x20,0x31,0xe0 = ldrsbt r2, [r1], -r4
 0xf0,0x50,0xd9,0xe1 = ldrsh r5, [r9]
 0xf7,0x40,0xd5,0xe1 = ldrsh r4, [r5, #7]
-0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #55]!
+0xf7,0x33,0xf6,0xe1 = ldrsh r3, [r6, #0x37]!
-0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-9
+0xf9,0x20,0x57,0xe0 = ldrsh r2, [r7], #-0x9
 0xf5,0x30,0x91,0xe1 = ldrsh r3, [r1, r5]
 0xf1,0x40,0xb6,0xe1 = ldrsh r4, [r6, r1]!
 0xf6,0x50,0x33,0xe1 = ldrsh r5, [r3, -r6]!
 0xf8,0x60,0x99,0xe0 = ldrsh r6, [r9], r8
 0xf3,0x70,0x18,0xe0 = ldrsh r7, [r8], -r3
 0xf1,0x50,0xf6,0xe0 = ldrsht r5, [r6], #1
-0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-12
+0xfc,0x30,0x78,0xe0 = ldrsht r3, [r8], #-0xc
+0xf0,0x50,0xf6,0xe0 = ldrsht r5, [r6], #0
 0xf5,0x80,0xb9,0xe0 = ldrsht r8, [r9], r5
 0xf4,0x20,0x31,0xe0 = ldrsht r2, [r1], -r4
 0x00,0x80,0x8c,0xe5 = str r8, [r12]
-0x0c,0x70,0x81,0xe5 = str r7, [r1, #12]
+0x0c,0x70,0x81,0xe5 = str r7, [r1, #0xc]
-0x28,0x30,0xa5,0xe5 = str r3, [r5, #40]!
+0x28,0x30,0xa5,0xe5 = str r3, [r5, #0x28]!
-0xff,0x9f,0x8d,0xe4 = str sb, [sp], #4095
+0xff,0x9f,0x8d,0xe4 = str r9, [sp], #0xfff
-0x80,0x10,0x07,0xe4 = str r1, [r7], #-128
+0x80,0x10,0x07,0xe4 = str r1, [r7], #-0x80
 0x00,0x10,0x00,0xe4 = str r1, [r0], #-0
 0x03,0x90,0x86,0xe7 = str r9, [r6, r3]
 0x02,0x80,0x00,0xe7 = str r8, [r0, -r2]
@@ -94,11 +97,11 @@
 0x09,0x50,0x83,0xe6 = str r5, [r3], r9
 0x05,0x40,0x02,0xe6 = str r4, [r2], -r5
 0x02,0x31,0x04,0xe7 = str r3, [r4, -r2, lsl #2]
-0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #24
+0x43,0x2c,0x87,0xe6 = str r2, [r7], r3, asr #0x18
 0x00,0x90,0xc2,0xe5 = strb r9, [r2]
 0x03,0x70,0xc1,0xe5 = strb r7, [r1, #3]
-0x95,0x61,0xe4,0xe5 = strb r6, [r4, #405]!
+0x95,0x61,0xe4,0xe5 = strb r6, [r4, #0x195]!
-0x48,0x50,0xc7,0xe4 = strb r5, [r7], #72
+0x48,0x50,0xc7,0xe4 = strb r5, [r7], #0x48
 0x01,0x10,0x4d,0xe4 = strb r1, [sp], #-1
 0x09,0x10,0xc2,0xe7 = strb r1, [r2, r9]
 0x08,0x20,0x43,0xe7 = strb r2, [r3, -r8]
@@ -107,32 +110,34 @@
 0x05,0x50,0xc6,0xe6 = strb r5, [r6], r5
 0x04,0x60,0x42,0xe6 = strb r6, [r2], -r4
 0x83,0x72,0x4c,0xe7 = strb r7, [r12, -r3, lsl #5]
-0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #12
+0x42,0xd6,0xc7,0xe6 = strb sp, [r7], r2, asr #0xc
-0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #12
+0x0c,0x60,0xe2,0xe4 = strbt r6, [r2], #0xc
-0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-13
+0x0d,0x50,0x66,0xe4 = strbt r5, [r6], #-0xd
 0x05,0x40,0xe9,0xe6 = strbt r4, [r9], r5
 0x82,0x31,0x68,0xe6 = strbt r3, [r8], -r2, lsl #3
-0xf0,0x10,0xc4,0xe1 = strd r1, r2, [r4]
+0xf0,0x20,0xc4,0xe1 = strd r2, r3, [r4]
 0xf1,0x20,0xc6,0xe1 = strd r2, r3, [r6, #1]
-0xf6,0x31,0xe7,0xe1 = strd r3, r4, [r7, #22]!
+0xf6,0x01,0xe7,0xe1 = strd r0, r1, [r7, #0x16]!
 0xf7,0x40,0xc8,0xe0 = strd r4, r5, [r8], #7
-0xf0,0x50,0xcd,0xe0 = strd r5, r6, [sp], #0
+0xf0,0x40,0xcd,0xe0 = strd r4, r5, [sp], #0
 0xf0,0x60,0xce,0xe0 = strd r6, r7, [lr], #0
-0xf0,0x70,0x49,0xe0 = strd r7, r8, [r9], #-0
+0xf0,0xa0,0x49,0xe0 = strd r10, r11, [r9], #-0
 0xf1,0x80,0x84,0xe1 = strd r8, r9, [r4, r1]
-0xf9,0x70,0xa3,0xe1 = strd r7, r8, [r3, r9]!
+0xf9,0x60,0xa3,0xe1 = strd r6, r7, [r3, r9]!
 0xf8,0x60,0x85,0xe0 = strd r6, r7, [r5], r8
-0xfa,0x50,0x0c,0xe0 = strd r5, r6, [r12], -r10
+0xfa,0x40,0x0c,0xe0 = strd r4, r5, [r12], -r10
 0xb0,0x30,0xc4,0xe1 = strh r3, [r4]
 0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4]
-0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #64]!
+0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #0x40]!
-0xb4,0xc0,0xcd,0xe0 = strh ip, [sp], #4
+0xb4,0xc0,0xcd,0xe0 = strh r12, [sp], #4
 0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4]
 0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]!
 0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]!
 0xb2,0x90,0x87,0xe0 = strh r9, [r7], r2
 0xb2,0x40,0x03,0xe0 = strh r4, [r3], -r2
-0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #76
+0xbc,0x24,0xe5,0xe0 = strht r2, [r5], #0x4c
-0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-25
+0xb9,0x81,0x61,0xe0 = strht r8, [r1], #-0x19
 0xb4,0x50,0xa3,0xe0 = strht r5, [r3], r4
 0xb0,0x60,0x28,0xe0 = strht r6, [r8], -r0
+0xd0,0x00,0xcd,0xe1 = ldrd r0, r1, [sp]
+0xf0,0x00,0xcd,0xe1 = strd r0, r1, [sp]

suite/MC/ARM/arm-shift-encoding.s.cs

@@ -1,50 +1,50 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
-0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
+0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #0x20]
-0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
+0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #0x10]
 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
-0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16]
+0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #0x10]
-0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
+0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #0x20]
-0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
+0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #0x10]
 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
-0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16]
+0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #0x10]
 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
-0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #32]
+0x20,0xf0,0xd0,0xf7 = pld [r0, r0, lsr #0x20]
-0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #16]
+0x20,0xf8,0xd0,0xf7 = pld [r0, r0, lsr #0x10]
 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
-0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #16]
+0x00,0xf8,0xd0,0xf7 = pld [r0, r0, lsl #0x10]
-0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #32]
+0x40,0xf0,0xd0,0xf7 = pld [r0, r0, asr #0x20]
-0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #16]
+0x40,0xf8,0xd0,0xf7 = pld [r0, r0, asr #0x10]
 0x60,0xf0,0xd0,0xf7 = pld [r0, r0, rrx]
-0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #16]
+0x60,0xf8,0xd0,0xf7 = pld [r0, r0, ror #0x10]
 0x00,0x00,0x80,0xe7 = str r0, [r0, r0]
-0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #32]
+0x20,0x00,0x80,0xe7 = str r0, [r0, r0, lsr #0x20]
-0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #16]
+0x20,0x08,0x80,0xe7 = str r0, [r0, r0, lsr #0x10]
 0x00,0x00,0x80,0xe7 = str r0, [r0, r0]
-0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #16]
+0x00,0x08,0x80,0xe7 = str r0, [r0, r0, lsl #0x10]
-0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #32]
+0x40,0x00,0x80,0xe7 = str r0, [r0, r0, asr #0x20]
-0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #16]
+0x40,0x08,0x80,0xe7 = str r0, [r0, r0, asr #0x10]
 0x60,0x00,0x80,0xe7 = str r0, [r0, r0, rrx]
-0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #16]
+0x60,0x08,0x80,0xe7 = str r0, [r0, r0, ror #0x10]
 0x62,0x00,0x91,0xe6 = ldr r0, [r1], r2, rrx
 0x05,0x30,0x94,0xe6 = ldr r3, [r4], r5
 0x08,0x60,0x87,0xe6 = str r6, [r7], r8
 0x0b,0x90,0x8a,0xe6 = str r9, [r10], r11
 0x0f,0xd0,0xae,0xe0 = adc sp, lr, pc
-0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #32
+0x29,0x10,0xa8,0xe0 = adc r1, r8, r9, lsr #0x20
-0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #16
+0x2f,0x28,0xa7,0xe0 = adc r2, r7, pc, lsr #0x10
 0x0a,0x30,0xa6,0xe0 = adc r3, r6, r10
-0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #16
+0x0e,0x48,0xa5,0xe0 = adc r4, r5, lr, lsl #0x10
-0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #32
+0x4b,0x50,0xa4,0xe0 = adc r5, r4, r11, asr #0x20
-0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #16
+0x4d,0x68,0xa3,0xe0 = adc r6, r3, sp, asr #0x10
 0x6c,0x70,0xa2,0xe0 = adc r7, r2, r12, rrx
-0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #16
+0x60,0x88,0xa1,0xe0 = adc r8, r1, r0, ror #0x10
 0x0e,0x00,0x5d,0xe1 = cmp sp, lr
-0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #32
+0x28,0x00,0x51,0xe1 = cmp r1, r8, lsr #0x20
-0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #16
+0x27,0x08,0x52,0xe1 = cmp r2, r7, lsr #0x10
 0x06,0x00,0x53,0xe1 = cmp r3, r6
-0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #16
+0x05,0x08,0x54,0xe1 = cmp r4, r5, lsl #0x10
-0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #32
+0x44,0x00,0x55,0xe1 = cmp r5, r4, asr #0x20
-0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #16
+0x43,0x08,0x56,0xe1 = cmp r6, r3, asr #0x10
 0x62,0x00,0x57,0xe1 = cmp r7, r2, rrx
-0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #16
+0x61,0x08,0x58,0xe1 = cmp r8, r1, ror #0x10

suite/MC/ARM/arm_addrmode2.s.cs

@@ -2,14 +2,18 @@
 0x02,0x10,0xb0,0xe6 = ldrt r1, [r0], r2
 0xa2,0x11,0xb0,0xe6 = ldrt r1, [r0], r2, lsr #3
 0x04,0x10,0xb0,0xe4 = ldrt r1, [r0], #4
+0x00,0x10,0xb0,0xe4 = ldrt r1, [r0], #0
 0x02,0x10,0xf0,0xe6 = ldrbt r1, [r0], r2
 0xa2,0x11,0xf0,0xe6 = ldrbt r1, [r0], r2, lsr #3
 0x04,0x10,0xf0,0xe4 = ldrbt r1, [r0], #4
+0x00,0x10,0xf0,0xe4 = ldrbt r1, [r0], #0
 0x02,0x10,0xa0,0xe6 = strt r1, [r0], r2
 0xa2,0x11,0xa0,0xe6 = strt r1, [r0], r2, lsr #3
 0x04,0x10,0xa0,0xe4 = strt r1, [r0], #4
+0x00,0x10,0xa0,0xe4 = strt r1, [r0], #0
 0x02,0x10,0xe0,0xe6 = strbt r1, [r0], r2
 0xa2,0x11,0xe0,0xe6 = strbt r1, [r0], r2, lsr #3
 0x04,0x10,0xe0,0xe4 = strbt r1, [r0], #4
+0x00,0x10,0xe0,0xe4 = strbt r1, [r0], #0
 0xa2,0x11,0xb0,0xe7 = ldr r1, [r0, r2, lsr #3]!
 0xa2,0x11,0xf0,0xe7 = ldrb r1, [r0, r2, lsr #3]!

suite/MC/ARM/arm_instructions.s.cs

@@ -1,6 +1,4 @@
 # CS_ARCH_ARM, CS_MODE_ARM, None
-0x1e,0xff,0x2f,0xe1 = bx lr
-0xa0,0x0d,0xe1,0xf2 = vqdmull.s32 q8, d17, d16
 0x03,0x10,0x02,0xe0 = and r1, r2, r3
 0x03,0x10,0x12,0xe0 = ands r1, r2, r3
 0x03,0x10,0x22,0xe0 = eor r1, r2, r3
@@ -16,7 +14,7 @@
 0x02,0x10,0xe0,0xe1 = mvn r1, r2
 0x02,0x10,0xf0,0xe1 = mvns r1, r2
 0x90,0x02,0xcb,0xe7 = bfi r0, r0, #5, #7
-0x7a,0x00,0x20,0xe1 = bkpt #10
+0x7a,0x00,0x20,0xe1 = bkpt #0xa
 0x81,0x17,0x11,0xee = cdp p7, #1, c1, c1, c1, #4
 0x81,0x17,0x11,0xfe = cdp2 p7, #1, c1, c1, c1, #4
 0x13,0x14,0x82,0xe0 = add r1, r2, r3, lsl r4

suite/MC/ARM/armv8.1m-pacbti.s.cs

@@ -0,0 +1,6 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xaf,0xf3,0x2d,0x80 = aut r12, lr, sp
+0xaf,0xf3,0x0f,0x80 = bti
+0xaf,0xf3,0x0f,0x80 = bti
+0xaf,0xf3,0x1d,0x80 = pac r12, lr, sp
+0xaf,0xf3,0x0d,0x80 = pacbti r12, lr, sp

suite/MC/ARM/armv8.2a-dotprod-a32.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x12,0x0d,0x21,0xfc = vudot.u8 d0, d1, d2
+0x02,0x0d,0x21,0xfc = vsdot.s8 d0, d1, d2
+0x58,0x0d,0x22,0xfc = vudot.u8 q0, q1, q4
+0x48,0x0d,0x22,0xfc = vsdot.s8 q0, q1, q4
+0x12,0x0d,0x21,0xfe = vudot.u8 d0, d1, d2[0]
+0x22,0x0d,0x21,0xfe = vsdot.s8 d0, d1, d2[1]
+0x54,0x0d,0x22,0xfe = vudot.u8 q0, q1, d4[0]
+0x64,0x0d,0x22,0xfe = vsdot.s8 q0, q1, d4[1]

suite/MC/ARM/armv8.2a-dotprod-t32.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x21,0xfc,0x12,0x0d = vudot.u8 d0, d1, d2
+0x21,0xfc,0x02,0x0d = vsdot.s8 d0, d1, d2
+0x22,0xfc,0x58,0x0d = vudot.u8 q0, q1, q4
+0x22,0xfc,0x48,0x0d = vsdot.s8 q0, q1, q4
+0x21,0xfe,0x12,0x0d = vudot.u8 d0, d1, d2[0]
+0x21,0xfe,0x22,0x0d = vsdot.s8 d0, d1, d2[1]
+0x22,0xfe,0x54,0x0d = vudot.u8 q0, q1, d4[0]
+0x22,0xfe,0x64,0x0d = vsdot.s8 q0, q1, d4[1]

suite/MC/ARM/armv8.5a-sb.s.cs

@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x70,0xf0,0x7f,0xf5 = sb

suite/MC/ARM/armv8a-fpmul.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x91,0x08,0x20,0xfc = vfmal.f16 d0, s1, s2
+0x91,0x08,0xa0,0xfc = vfmsl.f16 d0, s1, s2
+0x52,0x08,0x21,0xfc = vfmal.f16 q0, d1, d2
+0x52,0x08,0xa1,0xfc = vfmsl.f16 q0, d1, d2
+0x99,0x08,0x00,0xfe = vfmal.f16 d0, s1, s2[1]
+0x99,0x08,0x10,0xfe = vfmsl.f16 d0, s1, s2[1]
+0x7a,0x08,0x01,0xfe = vfmal.f16 q0, d1, d2[3]
+0x7a,0x08,0x11,0xfe = vfmsl.f16 q0, d1, d2[3]

suite/MC/ARM/basic-thumb-instructions.s.cs

@@ -6,37 +6,37 @@
 0xd1,0x18 = adds r1, r2, r3
 0x42,0x44 = add r2, r8
 0x01,0xb0 = add sp, #4
-0x7f,0xb0 = add sp, #508
+0x7f,0xb0 = add sp, #0x1fc
 0x01,0xb0 = add sp, #4
 0x02,0xaa = add r2, sp, #8
-0xff,0xaa = add r2, sp, #1020
+0xff,0xaa = add r2, sp, #0x3fc
 0x82,0xb0 = sub sp, #8
 0x82,0xb0 = sub sp, #8
 0x9d,0x44 = add sp, r3
 0x6a,0x44 = add r2, sp, r2
 0x00,0xa5 = adr r5, #0
 0x01,0xa2 = adr r2, #4
-0xff,0xa3 = adr r3, #1020
+0xff,0xa3 = adr r3, #0x3fc
-0x1a,0x10 = asrs r2, r3, #32
+0x1a,0x10 = asrs r2, r3, #0x20
 0x5a,0x11 = asrs r2, r3, #5
 0x5a,0x10 = asrs r2, r3, #1
-0x6d,0x15 = asrs r5, r5, #21
+0x6d,0x15 = asrs r5, r5, #0x15
-0x6d,0x15 = asrs r5, r5, #21
+0x6d,0x15 = asrs r5, r5, #0x15
-0x6b,0x15 = asrs r3, r5, #21
+0x6b,0x15 = asrs r3, r5, #0x15
 0x15,0x41 = asrs r5, r2
-0x97,0xe3 = b #1842
+0x97,0xe3 = b #0x72e
-0x2e,0xe7 = b #-416
+0x2e,0xe7 = b #-0x1a4
-0x80,0xd0 = beq #-252
+0x80,0xd0 = beq #-0x100
-0x50,0xd0 = beq #164
+0x50,0xd0 = beq #0xa0
-0xd8,0xf0,0x20,0xe8 = blx #884804
+0xd8,0xf0,0x20,0xe8 = blx #0xd8040
-0xb0,0xf1,0x40,0xe8 = blx #1769604
+0xb0,0xf1,0x40,0xe8 = blx #0x1b0080
 0xb1,0x43 = bics r1, r6
 0x00,0xbe = bkpt #0
-0xff,0xbe = bkpt #255
+0xff,0xbe = bkpt #0xff
 0xa0,0x47 = blx r4
 0x10,0x47 = bx r2
 0xcd,0x42 = cmn r5, r1
-0x20,0x2e = cmp r6, #32
+0x20,0x2e = cmp r6, #0x20
 0xa3,0x42 = cmp r3, r4
 0x88,0x45 = cmp r8, r1
 0x61,0xb6 = cpsie f
@@ -46,39 +46,39 @@
 0xba,0xca = ldm r2!, {r1, r3, r4, r5, r7}
 0x02,0xc9 = ldm r1, {r1}
 0x29,0x68 = ldr r1, [r5]
-0x32,0x6a = ldr r2, [r6, #32]
+0x32,0x6a = ldr r2, [r6, #0x20]
-0xfb,0x6f = ldr r3, [r7, #124]
+0xfb,0x6f = ldr r3, [r7, #0x7c]
 0x00,0x99 = ldr r1, [sp]
-0x06,0x9a = ldr r2, [sp, #24]
+0x06,0x9a = ldr r2, [sp, #0x18]
-0xff,0x9b = ldr r3, [sp, #1020]
+0xff,0x9b = ldr r3, [sp, #0x3fc]
-0x97,0x4b = ldr r3, [pc, #604]
+0x97,0x4b = ldr r3, [pc, #0x25c]
-0x5c,0x4b = ldr r3, [pc, #368]
+0x5c,0x4b = ldr r3, [pc, #0x170]
 0xd1,0x58 = ldr r1, [r2, r3]
 0x1c,0x78 = ldrb r4, [r3]
 0x35,0x78 = ldrb r5, [r6]
-0xfe,0x7f = ldrb r6, [r7, #31]
+0xfe,0x7f = ldrb r6, [r7, #0x1f]
 0x66,0x5d = ldrb r6, [r4, r5]
 0x1b,0x88 = ldrh r3, [r3]
 0x74,0x88 = ldrh r4, [r6, #2]
-0xfd,0x8f = ldrh r5, [r7, #62]
+0xfd,0x8f = ldrh r5, [r7, #0x3e]
 0x96,0x5b = ldrh r6, [r2, r6]
 0x96,0x57 = ldrsb r6, [r2, r6]
 0x7b,0x5e = ldrsh r3, [r7, r1]
-// 0x2c,0x00 = lsls r4, r5, #0
+0x2c,0x00 = movs r4, r5
 0x2c,0x01 = lsls r4, r5, #4
-0x1b,0x03 = lsls r3, r3, #12
+0x1b,0x03 = lsls r3, r3, #0xc
-0x1b,0x03 = lsls r3, r3, #12
+0x1b,0x03 = lsls r3, r3, #0xc
-0x19,0x03 = lsls r1, r3, #12
+0x19,0x03 = lsls r1, r3, #0xc
 0xb2,0x40 = lsls r2, r6
 0x59,0x08 = lsrs r1, r3, #1
-0x19,0x08 = lsrs r1, r3, #32
+0x19,0x08 = lsrs r1, r3, #0x20
-0x24,0x0d = lsrs r4, r4, #20
+0x24,0x0d = lsrs r4, r4, #0x14
-0x24,0x0d = lsrs r4, r4, #20
+0x24,0x0d = lsrs r4, r4, #0x14
-0x22,0x0d = lsrs r2, r4, #20
+0x22,0x0d = lsrs r2, r4, #0x14
 0xf2,0x40 = lsrs r2, r6
 0x00,0x22 = movs r2, #0
-0xff,0x22 = movs r2, #255
+0xff,0x22 = movs r2, #0xff
-0x17,0x22 = movs r2, #23
+0x17,0x22 = movs r2, #0x17
 0x23,0x46 = mov r3, r4
 0x19,0x00 = movs r1, r3
 0x51,0x43 = muls r1, r2, r1
@@ -101,28 +101,28 @@
 0x3a,0x60 = str r2, [r7]
 0x3a,0x60 = str r2, [r7]
 0x4d,0x60 = str r5, [r1, #4]
-0xfb,0x67 = str r3, [r7, #124]
+0xfb,0x67 = str r3, [r7, #0x7c]
 0x00,0x92 = str r2, [sp]
 0x00,0x93 = str r3, [sp]
-0x05,0x94 = str r4, [sp, #20]
+0x05,0x94 = str r4, [sp, #0x14]
-0xff,0x95 = str r5, [sp, #1020]
+0xff,0x95 = str r5, [sp, #0x3fc]
 0xfa,0x50 = str r2, [r7, r3]
 0x1c,0x70 = strb r4, [r3]
 0x35,0x70 = strb r5, [r6]
-0xfe,0x77 = strb r6, [r7, #31]
+0xfe,0x77 = strb r6, [r7, #0x1f]
 0x66,0x55 = strb r6, [r4, r5]
 0x1b,0x80 = strh r3, [r3]
 0x74,0x80 = strh r4, [r6, #2]
-0xfd,0x87 = strh r5, [r7, #62]
+0xfd,0x87 = strh r5, [r7, #0x3e]
 0x96,0x53 = strh r6, [r2, r6]
 0xd1,0x1e = subs r1, r2, #3
 0x03,0x3a = subs r2, #3
 0x08,0x3a = subs r2, #8
-0x83,0xb0 = sub sp, #12
+0x83,0xb0 = sub sp, #0xc
-0xff,0xb0 = sub sp, #508
+0xff,0xb0 = sub sp, #0x1fc
 0xd1,0x1a = subs r1, r2, r3
 0x00,0xdf = svc #0
-0xff,0xdf = svc #255
+0xff,0xdf = svc #0xff
 0x6b,0xb2 = sxtb r3, r5
 0x2b,0xb2 = sxth r3, r5
 0x0e,0x42 = tst r6, r1

suite/MC/ARM/bfloat16-a32.s.cs

@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x05,0x3d,0x04,0xfc = vdot.bf16 d3, d4, d5

suite/MC/ARM/bfloat16-t32.s.cs

@@ -0,0 +1,4 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xb6,0xff,0x46,0x16 = vcvt.bf16.f32 d1, q3
+0x18,0xbf = it ne
+0xf3,0xee,0xe1,0x09 = vcvtt.bf16.f32  s1, s3

suite/MC/ARM/cde-integer.s.cs

@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x06,0xbf = itte eq

suite/MC/ARM/cde-vec-pred.s.cs

@@ -0,0 +1,2 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x41,0xfe,0x00,0xef = vptete.i8 eq, q0, q0

suite/MC/ARM/clrm-asm.s.cs

@@ -0,0 +1,7 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8, None
+0x9f,0xe8,0x0f,0x00 = clrm {r0, r1, r2, r3}
+0x9f,0xe8,0x1e,0x00 = clrm {r1, r2, r3, r4}
+0x9f,0xe8,0xff,0xdf = clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr}
+0x9f,0xe8,0x00,0xc0 = clrm {lr, apsr}
+0x9f,0xe8,0x03,0x80 = clrm {r0, r1, apsr}
+0x9f,0xe8,0x1f,0xc0 = clrm {r0, r1, r2, r3, r4, lr, apsr}

suite/MC/ARM/cps.s.cs

@@ -0,0 +1,4 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x61,0xb6 = cpsie f
+0xaf,0xf3,0x43,0x85 = cpsie i, #3
+0xaf,0xf3,0x00,0x81 = cps #0

suite/MC/ARM/fconst.s.cs

@@ -0,0 +1,9 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x00,0x2a,0xb0,0xee = vmov.f32 s4, #2.000000e+00
+0x00,0x2a,0xb7,0xee = vmov.f32 s4, #1.000000e+00
+0x00,0x3b,0xb0,0xee = vmov.f64 d3, #2.000000e+00
+0x00,0x3b,0xb7,0xee = vmov.f64 d3, #1.000000e+00
+0x01,0x2a,0xf0,0x1e = vmovne.f32 s5, #2.125000e+00
+0x00,0x2a,0xf2,0xce = vmovgt.f32 s5, #8.000000e+00
+0x03,0x2b,0xb0,0xbe = vmovlt.f64 d2, #2.375000e+00
+0x00,0x2b,0xb4,0xae = vmovge.f64 d2, #1.250000e-01

suite/MC/ARM/gas-compl-copr-reg.s.cs

@@ -0,0 +1,5 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4]
+0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0]
+0x01,0x4c,0x90,0xed = ldc p12, c4, [r0, #4]
+0x38,0x6e,0x02,0xed = stc p14, c6, [r2, #-0xe0]

suite/MC/ARM/implicit-it-generation.s.cs

@@ -0,0 +1,12 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0x01,0x30 = adds r0, #1
+0x10,0xf1,0x01,0x00 = adds.w r0, r0, #1
+0x80,0xe0 = b #0x100
+0x00,0xf0,0x00,0xbc = b.w #0x800
+0x02,0xd0 = beq #4
+0x00,0xf0,0x80,0x80 = beq.w #0x100
+0x02,0xe0 = b #4
+0x80,0xe0 = b #0x100
+0x00,0xf0,0x00,0xbc = b.w #0x800
+0x02,0xdc = bgt #4
+0x00,0xf3,0x80,0x80 = bgt.w #0x100

suite/MC/ARM/ldrd-strd-gnu-arm.s.cs

@@ -0,0 +1,7 @@
+# CS_ARCH_ARM, CS_MODE_ARM, None
+0xd0,0x02,0xea,0xe1 = ldrd r0, r1, [r10, #0x20]!
+0xd0,0x02,0xca,0xe0 = ldrd r0, r1, [r10], #0x20
+0xd0,0x02,0xca,0xe1 = ldrd r0, r1, [r10, #0x20]
+0xf0,0x02,0xea,0xe1 = strd r0, r1, [r10, #0x20]!
+0xf0,0x02,0xca,0xe0 = strd r0, r1, [r10], #0x20
+0xf0,0x02,0xca,0xe1 = strd r0, r1, [r10, #0x20]

suite/MC/ARM/ldrd-strd-gnu-thumb.s.cs

@@ -0,0 +1,13 @@
+# CS_ARCH_ARM, CS_MODE_THUMB, None
+0xfa,0xe9,0x80,0x01 = ldrd r0, r1, [r10, #0x200]!
+0xfa,0xe8,0x80,0x01 = ldrd r0, r1, [r10], #0x200
+0xda,0xe9,0x80,0x01 = ldrd r0, r1, [r10, #0x200]
+0xea,0xe9,0x80,0x01 = strd r0, r1, [r10, #0x200]!
+0xea,0xe8,0x80,0x01 = strd r0, r1, [r10], #0x200
+0xca,0xe9,0x80,0x01 = strd r0, r1, [r10, #0x200]
+0xfa,0xe9,0x80,0x12 = ldrd r1, r2, [r10, #0x200]!
+0xfa,0xe8,0x80,0x12 = ldrd r1, r2, [r10], #0x200
+0xda,0xe9,0x80,0x12 = ldrd r1, r2, [r10, #0x200]
+0xea,0xe9,0x80,0x12 = strd r1, r2, [r10, #0x200]!
+0xea,0xe8,0x80,0x12 = strd r1, r2, [r10], #0x200
+0xca,0xe9,0x80,0x12 = strd r1, r2, [r10, #0x200]

suite/MC/ARM/mode-switch.s.cs

@@ -1,5 +0,0 @@
-# CS_ARCH_ARM, CS_MODE_THUMB, None
-0x00,0xeb,0x01,0x00 = add.w r0, r0, r1
-0x40,0x18 = adds r0, r0, r1
-0x00,0xeb,0x01,0x00 = add.w r0, r0, r1
-0x40,0x18 = adds r0, r0, r1

suite/MC/ARM/mve-bitops.s.cs

@@ -0,0 +1,96 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x81,0xef,0x52,0x09 = vorr.i16 q0, #0x12
+0x81,0xef,0x52,0x03 = vorr.i32 q0, #0x1200
+0x86,0xff,0x5d,0x09 = vorr.i16 q0, #0xed
+0x86,0xff,0x5d,0x03 = vorr.i32 q0, #0xed00
+0x86,0xff,0x5d,0x05 = vorr.i32 q0, #0xed0000
+0x86,0xff,0x5d,0x07 = vorr.i32 q0, #0xed000000
+0x82,0xef,0x72,0x09 = vbic.i16 q0, #0x22
+0x81,0xef,0x71,0x03 = vbic.i32 q0, #0x1100
+0x85,0xff,0x7d,0x09 = vbic.i16 q0, #0xdd
+0x85,0xff,0x7d,0x0b = vbic.i16 q0, #0xdd00
+0x86,0xff,0x7e,0x01 = vbic.i32 q0, #0xee
+0x86,0xff,0x7e,0x03 = vbic.i32 q0, #0xee00
+0x86,0xff,0x7e,0x05 = vbic.i32 q0, #0xee0000
+0x86,0xff,0x7e,0x07 = vbic.i32 q0, #0xee000000
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0x12,0xef,0x5e,0x01 = vbic q0, q1, q7
+0xb0,0xff,0x48,0x00 = vrev64.8 q0, q4
+0xb4,0xff,0x46,0x20 = vrev64.16 q1, q3
+0xb8,0xff,0x44,0x00 = vrev64.32 q0, q2
+0xb0,0xff,0xc2,0x00 = vrev32.8 q0, q1
+0xb4,0xff,0xca,0x00 = vrev32.16 q0, q5
+0xb0,0xff,0x44,0x01 = vrev16.8 q0, q2
+0xb0,0xff,0xc4,0x05 = vmvn q0, q2
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x02,0xff,0x5e,0x41 = veor q2, q1, q7
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x36,0xef,0x54,0x01 = vorn q0, q3, q2
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x24,0xef,0x52,0x21 = vorr q1, q2, q1
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x04,0xef,0x50,0x01 = vand q0, q2, q0
+0x40,0xee,0x30,0x8b = vmov.8 q0[1], r8
+0x20,0xee,0x30,0x5b = vmov.16 q0[2], r5
+0x2d,0xee,0x10,0xbb = vmov.32 q6[3], r11
+0x12,0xee,0x10,0x0b = vmov.32 r0, q1[0]
+0x35,0xee,0x70,0x1b = vmov.s16 r1, q2[7]
+0x79,0xee,0x30,0x0b = vmov.s8 r0, q4[13]
+0x93,0xee,0x30,0x0b = vmov.u16 r0, q1[4]
+0xfa,0xee,0x70,0x0b = vmov.u8 r0, q5[7]
+0x71,0xfe,0x4d,0x8f = vpste
+0xb0,0xff,0xc2,0x05 = vmvnt q0, q1
+0xb0,0xff,0xc2,0x05 = vmvne q0, q1
+0x71,0xfe,0x4d,0x8f = vpste
+0x32,0xef,0x54,0x01 = vornt q0, q1, q2
+0x32,0xef,0x54,0x01 = vorne q0, q1, q2

suite/MC/ARM/mve-float.s.cs

@@ -0,0 +1,103 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_MCLASS, None
+0xb6,0xff,0x40,0x24 = vrintn.f16 q1, q0
+0xba,0xff,0x48,0x04 = vrintn.f32 q0, q4
+0xb6,0xff,0x42,0x05 = vrinta.f16 q0, q1
+0xba,0xff,0x46,0x25 = vrinta.f32 q1, q3
+0xb6,0xff,0xca,0x06 = vrintm.f16 q0, q5
+0xba,0xff,0xc8,0x06 = vrintm.f32 q0, q4
+0xb6,0xff,0xc0,0x27 = vrintp.f16 q1, q0
+0xba,0xff,0xc2,0x07 = vrintp.f32 q0, q1
+0xb6,0xff,0xc4,0x24 = vrintx.f16 q1, q2
+0xba,0xff,0xc2,0x24 = vrintx.f32 q1, q1
+0xb6,0xff,0xcc,0x25 = vrintz.f16 q1, q6
+0xba,0xff,0xc0,0x25 = vrintz.f32 q1, q0
+0xb6,0xee,0x60,0x0a = vrintr.f32 s0, s1
+0xb6,0xee,0x41,0x0b = vrintr.f64 d0, d1
+0x12,0xff,0x56,0x4d = vmul.f16 q2, q1, q3
+0x00,0xff,0x5a,0x0d = vmul.f32 q0, q0, q5
+0x24,0xfc,0x42,0x68 = vcmla.f16 q3, q2, q1, #0
+0xa0,0xfc,0x4a,0x08 = vcmla.f16 q0, q0, q5, #0x5a
+0x2e,0xfd,0x44,0x68 = vcmla.f16 q3, q7, q2, #0xb4
+0xae,0xfd,0x4c,0x48 = vcmla.f16 q2, q7, q6, #0x10e
+0x3c,0xfc,0x4c,0x48 = vcmla.f32 q2, q6, q6, #0
+0xb2,0xfc,0x46,0xe8 = vcmla.f32 q7, q1, q3, #0x5a
+0x3a,0xfd,0x46,0x88 = vcmla.f32 q4, q5, q3, #0xb4
+0xb4,0xfd,0x4e,0x68 = vcmla.f32 q3, q2, q7, #0x10e
+0x14,0xef,0x56,0x0c = vfma.f16 q0, q2, q3
+0x06,0xef,0x5e,0x0c = vfma.f32 q0, q3, q7
+0x34,0xef,0x5a,0x0c = vfms.f16 q0, q2, q5
+0x22,0xef,0x54,0x2c = vfms.f32 q1, q1, q2
+0x10,0xef,0x4a,0x0d = vadd.f16 q0, q0, q5
+0x06,0xef,0x40,0x2d = vadd.f32 q1, q3, q0
+0x02,0xef,0x44,0x0d = vadd.f32 q0, q1, q2
+0x82,0xfc,0x4e,0x48 = vcadd.f16 q2, q1, q7, #0x5a
+0x8a,0xfd,0x4e,0x48 = vcadd.f16 q2, q5, q7, #0x10e
+0x98,0xfc,0x4e,0x08 = vcadd.f32 q0, q4, q7, #0x5a
+0x94,0xfd,0x46,0x48 = vcadd.f32 q2, q2, q3, #0x10e
+0x30,0xff,0x4c,0x0d = vabd.f16 q0, q0, q6
+0x22,0xff,0x48,0x0d = vabd.f32 q0, q1, q4
+0xbf,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #1
+0xb0,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #0x10
+0xb5,0xef,0x5e,0x2c = vcvt.f16.s16 q1, q7, #0xb
+0xbd,0xef,0x52,0x2d = vcvt.s16.f16 q1, q1, #3
+0xb6,0xff,0x52,0x4c = vcvt.f16.u16 q2, q1, #0xa
+0xbd,0xff,0x50,0x0d = vcvt.u16.f16 q0, q0, #3
+0xbf,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #1
+0xa0,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #0x20
+0xba,0xef,0x5e,0x2e = vcvt.f32.s32 q1, q7, #6
+0xab,0xef,0x50,0x2f = vcvt.s32.f32 q1, q0, #0x15
+0xbc,0xff,0x58,0x2e = vcvt.f32.u32 q1, q4, #4
+0xb8,0xff,0x5a,0x2f = vcvt.u32.f32 q1, q5, #8
+0xb7,0xff,0x42,0x06 = vcvt.f16.s16 q0, q1
+0xb7,0xff,0xc8,0x06 = vcvt.f16.u16 q0, q4
+0xb7,0xff,0x40,0x07 = vcvt.s16.f16 q0, q0
+0xb7,0xff,0xc0,0x07 = vcvt.u16.f16 q0, q0
+0xbb,0xff,0x40,0x06 = vcvt.f32.s32 q0, q0
+0xbb,0xff,0xc0,0x06 = vcvt.f32.u32 q0, q0
+0xbb,0xff,0x40,0x07 = vcvt.s32.f32 q0, q0
+0xbb,0xff,0xc4,0x07 = vcvt.u32.f32 q0, q2
+0xb7,0xff,0x4e,0x00 = vcvta.s16.f16 q0, q7
+0xbc,0xfe,0xe1,0x1a = vcvta.s32.f32 s2, s3
+0xb7,0xff,0x4e,0x00 = vcvta.s16.f16 q0, q7
+0xbb,0xff,0xcc,0xe1 = vcvtn.u32.f32 q7, q6
+0xbb,0xff,0x4e,0x02 = vcvtp.s32.f32 q0, q7
+0xbb,0xff,0xc8,0x23 = vcvtm.u32.f32 q1, q4
+0xb5,0xff,0xce,0x07 = vneg.f16 q0, q7
+0xb9,0xff,0xc4,0x07 = vneg.f32 q0, q2
+0xb5,0xff,0x44,0x07 = vabs.f16 q0, q2
+0xb9,0xff,0x40,0x07 = vabs.f32 q0, q0
+0x3f,0xfe,0x83,0x2e = vmaxnma.f16 q1, q1
+0x3f,0xee,0x8d,0x4e = vmaxnma.f32 q2, q6
+0x3f,0xfe,0x85,0x1e = vminnma.f16 q0, q2
+0x3f,0xee,0x83,0x1e = vminnma.f32 q0, q1
+0x08,0xbf = it eq
+0x30,0xee,0x20,0x0a = vaddeq.f32 s0, s0, s1
+0x71,0xfe,0x4d,0x0f = vpst
+0x12,0xef,0x44,0x0d = vaddt.f16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0xbb,0xff,0xc2,0x03 = vcvtmt.u32.f32 q0, q1
+0xbb,0xff,0x42,0x01 = vcvtne.s32.f32 q0, q1
+0x18,0xbf = it ne
+0xbd,0xee,0xe0,0x0a = vcvtne.s32.f32 s0, s1
+0xa8,0xbf = it ge
+0xb2,0xee,0xe0,0x3b = vcvttge.f64.f16 d3, s1
+0x77,0xee,0xc1,0x9f = vpte.f32 lt, q3, r1
+0xbb,0xff,0xc0,0x47 = vcvtt.u32.f32 q2, q0
+0xbb,0xff,0xc0,0x27 = vcvte.u32.f32 q1, q0
+0x0c,0xbf = ite eq
+0xbc,0xee,0xe0,0x0a = vcvteq.u32.f32 s0, s1
+0xb8,0xee,0x60,0x0a = vcvtne.f32.u32 s0, s1
+0x71,0xfe,0x4d,0x8f = vpste
+0x12,0xff,0x54,0x0d = vmult.f16 q0, q1, q2
+0x12,0xff,0x54,0x0d = vmule.f16 q0, q1, q2
+0x0c,0xbf = ite eq
+0x20,0xee,0x01,0x0b = vmuleq.f64 d0, d0, d1
+0x20,0xee,0x02,0x1b = vmulne.f64 d1, d0, d2
+0x08,0xbf = it eq
+0xb1,0xee,0x60,0x0a = vnegeq.f32 s0, s1
+0x04,0xbf = itt eq
+0x20,0xee,0xc1,0x0a = vnmuleq.f32 s0, s1, s2
+0x20,0xee,0x81,0x0a = vmuleq.f32 s0, s1, s2
+0x71,0xfe,0x4d,0x8f = vpste
+0xb6,0xff,0x42,0x04 = vrintnt.f16 q0, q1
+0xba,0xff,0x42,0x04 = vrintne.f32 q0, q1

suite/MC/ARM/mve-integer.s.cs

@@ -0,0 +1,100 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x81,0xef,0x5b,0x0c = vmov.i32 q0, #0x1bff
+0x85,0xef,0x5c,0x08 = vmov.i16 q0, #0x5c
+0x84,0xef,0x5c,0x0e = vmov.i8 q0, #0x4c
+0x80,0xff,0x5d,0x0f = vmov.f32 q0, #-3.625000e+00
+0x84,0xef,0x50,0x0f = vmov.f32 q0, #1.250000e-01
+0x84,0xef,0x51,0x0f = vmov.f32 q0, #1.328125e-01
+0x83,0xef,0x5f,0x0f = vmov.f32 q0, #3.100000e+01
+0xb0,0xee,0x60,0x8a = vmov.f32 s16, s1
+0xb0,0xee,0x41,0x0b = vmov.f64 d0, d1
+0x81,0xff,0x7f,0x0e = vmov.i64 q0, #0xff0000ffffffffff
+0x00,0xef,0x56,0x09 = vmul.i8 q0, q0, q3
+0x10,0xef,0x56,0xc9 = vmul.i16 q6, q0, q3
+0x26,0xef,0x5c,0xe9 = vmul.i32 q7, q3, q6
+0x0a,0xff,0x4a,0x0b = vqrdmulh.s8 q0, q5, q5
+0x18,0xff,0x44,0x2b = vqrdmulh.s16 q1, q4, q2
+0x2a,0xff,0x40,0x0b = vqrdmulh.s32 q0, q5, q0
+0x08,0xef,0x4a,0x0b = vqdmulh.s8 q0, q4, q5
+0x18,0xef,0x40,0xcb = vqdmulh.s16 q6, q4, q0
+0x20,0xef,0x4c,0xab = vqdmulh.s32 q5, q0, q6
+0x04,0xff,0x4a,0x68 = vsub.i8 q3, q2, q5
+0x16,0xff,0x4c,0x08 = vsub.i16 q0, q3, q6
+0x20,0xff,0x4c,0x08 = vsub.i32 q0, q0, q6
+0x04,0xef,0x44,0x08 = vadd.i8 q0, q2, q2
+0x14,0xef,0x42,0x48 = vadd.i16 q2, q2, q1
+0x20,0xef,0x4c,0x08 = vadd.i32 q0, q0, q6
+0x0c,0xef,0x50,0x22 = vqsub.s8 q1, q6, q0
+0x1c,0xef,0x52,0x02 = vqsub.s16 q0, q6, q1
+0x20,0xef,0x5a,0x02 = vqsub.s32 q0, q0, q5
+0x04,0xff,0x5c,0x02 = vqsub.u8 q0, q2, q6
+0x1e,0xff,0x52,0x02 = vqsub.u16 q0, q7, q1
+0x28,0xff,0x5e,0x22 = vqsub.u32 q1, q4, q7
+0x02,0xef,0x54,0x00 = vqadd.s8 q0, q1, q2
+0x08,0xef,0x5c,0x00 = vqadd.s8 q0, q4, q6
+0x1a,0xef,0x5a,0x00 = vqadd.s16 q0, q5, q5
+0x20,0xef,0x58,0x00 = vqadd.s32 q0, q0, q4
+0x08,0xff,0x54,0x00 = vqadd.u8 q0, q4, q2
+0x1c,0xff,0x5c,0x80 = vqadd.u16 q4, q6, q6
+0x22,0xff,0x54,0x00 = vqadd.u32 q0, q1, q2
+0x00,0xef,0x44,0x07 = vabd.s8 q0, q0, q2
+0x1a,0xef,0x48,0x27 = vabd.s16 q1, q5, q4
+0x26,0xef,0x44,0x47 = vabd.s32 q2, q3, q2
+0x0c,0xff,0x48,0x27 = vabd.u8 q1, q6, q4
+0x1c,0xff,0x44,0x07 = vabd.u16 q0, q6, q2
+0x2e,0xff,0x48,0x07 = vabd.u32 q0, q7, q4
+0x02,0xef,0x42,0x01 = vrhadd.s8 q0, q1, q1
+0x12,0xef,0x40,0x01 = vrhadd.s16 q0, q1, q0
+0x28,0xef,0x42,0x01 = vrhadd.s32 q0, q4, q1
+0x00,0xff,0x4c,0x21 = vrhadd.u8 q1, q0, q6
+0x14,0xff,0x4a,0x41 = vrhadd.u16 q2, q2, q5
+0x26,0xff,0x40,0x41 = vrhadd.u32 q2, q3, q0
+0x00,0xef,0x44,0x02 = vhsub.s8 q0, q0, q2
+0x16,0xef,0x42,0x22 = vhsub.s16 q1, q3, q1
+0x24,0xef,0x4a,0x02 = vhsub.s32 q0, q2, q5
+0x08,0xff,0x44,0x02 = vhsub.u8 q0, q4, q2
+0x1e,0xff,0x4a,0x02 = vhsub.u16 q0, q7, q5
+0x2c,0xff,0x48,0x42 = vhsub.u32 q2, q6, q4
+0x0e,0xef,0x40,0x00 = vhadd.s8 q0, q7, q0
+0x10,0xef,0x44,0x80 = vhadd.s16 q4, q0, q2
+0x26,0xef,0x42,0x00 = vhadd.s32 q0, q3, q1
+0x00,0xff,0x46,0x60 = vhadd.u8 q3, q0, q3
+0x12,0xff,0x46,0x00 = vhadd.u16 q0, q1, q3
+0x22,0xff,0x46,0x00 = vhadd.u32 q0, q1, q3
+0xec,0xee,0x10,0x8b = vdup.8 q6, r8
+0xae,0xee,0x30,0xeb = vdup.16 q7, lr
+0xa2,0xee,0x10,0x9b = vdup.32 q1, r9
+0xa0,0xee,0x30,0x1b = vdup.16 q0, r1
+0xa0,0xee,0x30,0x1b = vdup.16 q0, r1
+0xb0,0xff,0x42,0x44 = vcls.s8 q2, q1
+0xb4,0xff,0x48,0x04 = vcls.s16 q0, q4
+0xb8,0xff,0x40,0x04 = vcls.s32 q0, q0
+0xb0,0xff,0xce,0x04 = vclz.i8 q0, q7
+0xb4,0xff,0xce,0x84 = vclz.i16 q4, q7
+0xb8,0xff,0xca,0xe4 = vclz.i32 q7, q5
+0xb1,0xff,0xc0,0x23 = vneg.s8 q1, q0
+0xb5,0xff,0xc2,0x03 = vneg.s16 q0, q1
+0xb9,0xff,0xc4,0xe3 = vneg.s32 q7, q2
+0xb1,0xff,0x42,0x23 = vabs.s8 q1, q1
+0xb5,0xff,0x44,0x03 = vabs.s16 q0, q2
+0xb9,0xff,0x4e,0x03 = vabs.s32 q0, q7
+0xb0,0xff,0xc0,0x07 = vqneg.s8 q0, q0
+0xb4,0xff,0xc4,0xc7 = vqneg.s16 q6, q2
+0xb8,0xff,0xc4,0xe7 = vqneg.s32 q7, q2
+0xb0,0xff,0x48,0x47 = vqabs.s8 q2, q4
+0xb4,0xff,0x44,0x07 = vqabs.s16 q0, q2
+0xb8,0xff,0x4a,0x07 = vqabs.s32 q0, q5
+0x71,0xfe,0x4d,0x8f = vpste
+0xb1,0xff,0xc2,0x03 = vnegt.s8 q0, q1
+0xb1,0xff,0xc2,0x03 = vnege.s8 q0, q1
+0x71,0xfe,0x4d,0x0f = vpst
+0x12,0xef,0x54,0x00 = vqaddt.s16 q0, q1, q2
+0x71,0xfe,0x4d,0x8f = vpste
+0xb0,0xff,0xc2,0x07 = vqnegt.s8 q0, q1
+0xb4,0xff,0xc2,0x07 = vqnege.s16 q0, q1
+0x33,0xee,0x8f,0x3e = vmina.s8 q1, q7
+0x37,0xee,0x89,0x3e = vmina.s16 q1, q4
+0x3b,0xee,0x8f,0x1e = vmina.s32 q0, q7
+0x33,0xee,0x8f,0x0e = vmaxa.s8 q0, q7
+0x37,0xee,0x81,0x2e = vmaxa.s16 q1, q0
+0x3b,0xee,0x81,0x2e = vmaxa.s32 q1, q0

suite/MC/ARM/mve-interleave.s.cs

@@ -0,0 +1,68 @@
+# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
+0x9d,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [sp]
+0x90,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]
+0xb0,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]!
+0x9b,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r11]
+0xb0,0xfc,0x00,0xbe = vld20.8 {q5, q6}, [r0]!
+0x90,0xfc,0x20,0x1e = vld21.8 {q0, q1}, [r0]
+0xb0,0xfc,0x20,0x7e = vld21.8 {q3, q4}, [r0]!
+0x90,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]
+0xb0,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]!
+0x9b,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r11]
+0xb0,0xfc,0x80,0xbe = vld20.16 {q5, q6}, [r0]!
+0x90,0xfc,0xa0,0x1e = vld21.16 {q0, q1}, [r0]
+0xb0,0xfc,0xa0,0x7e = vld21.16 {q3, q4}, [r0]!
+0x90,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]
+0xb0,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]!
+0x9b,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r11]
+0xb0,0xfc,0x00,0xbf = vld20.32 {q5, q6}, [r0]!
+0x90,0xfc,0x20,0x1f = vld21.32 {q0, q1}, [r0]
+0xb0,0xfc,0x20,0x7f = vld21.32 {q3, q4}, [r0]!
+0x80,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]
+0xa0,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]!
+0x8b,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r11]
+0xa0,0xfc,0x00,0xbe = vst20.8 {q5, q6}, [r0]!
+0x80,0xfc,0x20,0x1e = vst21.8 {q0, q1}, [r0]
+0xa0,0xfc,0x20,0x7e = vst21.8 {q3, q4}, [r0]!
+0x80,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]
+0xa0,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]!
+0x8b,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r11]
+0xa0,0xfc,0x80,0xbe = vst20.16 {q5, q6}, [r0]!
+0x80,0xfc,0xa0,0x1e = vst21.16 {q0, q1}, [r0]
+0xa0,0xfc,0xa0,0x7e = vst21.16 {q3, q4}, [r0]!
+0x80,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]
+0xa0,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]!
+0x8b,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r11]
+0xa0,0xfc,0x00,0xbf = vst20.32 {q5, q6}, [r0]!
+0x80,0xfc,0x20,0x1f = vst21.32 {q0, q1}, [r0]
+0xa0,0xfc,0x20,0x7f = vst21.32 {q3, q4}, [r0]!
+0x90,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]!
+0x9b,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r11]
+0xb0,0xfc,0x01,0x7e = vld40.8 {q3, q4, q5, q6}, [r0]!
+0x90,0xfc,0x21,0x1e = vld41.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x21,0x9e = vld41.8 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]!
+0x90,0xfc,0x61,0x1e = vld43.8 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x61,0x9e = vld43.8 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]!
+0x9b,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r11]
+0xb0,0xfc,0x81,0x7e = vld40.16 {q3, q4, q5, q6}, [r0]!
+0x90,0xfc,0xa1,0x1e = vld41.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0xa1,0x9e = vld41.16 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]!
+0x90,0xfc,0xe1,0x1e = vld43.16 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0xe1,0x9e = vld43.16 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]!
+0x9b,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r11]
+0xb0,0xfc,0x01,0x7f = vld40.32 {q3, q4, q5, q6}, [r0]!
+0x90,0xfc,0x21,0x1f = vld41.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x21,0x9f = vld41.32 {q4, q5, q6, q7}, [r0]!
+0x90,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]!
+0x90,0xfc,0x61,0x1f = vld43.32 {q0, q1, q2, q3}, [r0]
+0xb0,0xfc,0x61,0x9f = vld43.32 {q4, q5, q6, q7}, [r0]!