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fix

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billow 2023-03-27 04:00:47 +08:00
parent cba2891741
commit 18954aa9ea
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GPG Key ID: CA735DC44D699DE6
7 changed files with 970 additions and 969 deletions
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1845
arch/TriCore/TriCoreGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

32
arch/TriCore/TriCoreGenDisassemblerTables.inc
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@ -36,9 +36,9 @@ static const uint8_t DecoderTable16[] = {
/* 55 */ MCD_OPC_FilterValue, 10, 251, 4, 0, // Skip to: 1335
/* 60 */ MCD_OPC_Decode, 248, 2, 0, // Opcode: DEBUG_sr
/* 64 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 73
/* 69 */ MCD_OPC_Decode, 205, 5, 1, // Opcode: MOV_AA_srr
/* 69 */ MCD_OPC_Decode, 206, 5, 1, // Opcode: MOV_AA_srr
/* 73 */ MCD_OPC_FilterValue, 2, 233, 4, 0, // Skip to: 1335
/* 78 */ MCD_OPC_Decode, 210, 5, 1, // Opcode: MOV_D_srr
/* 78 */ MCD_OPC_Decode, 211, 5, 1, // Opcode: MOV_D_srr
/* 82 */ MCD_OPC_FilterValue, 2, 39, 0, 0, // Skip to: 126
/* 87 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ...
/* 90 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 99
@ -173,9 +173,9 @@ static const uint8_t DecoderTable16[] = {
/* 670 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 679
/* 675 */ MCD_OPC_Decode, 136, 8, 8, // Opcode: SUB_A_sc
/* 679 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 688
/* 684 */ MCD_OPC_Decode, 208, 5, 1, // Opcode: MOV_A_srr
/* 684 */ MCD_OPC_Decode, 209, 5, 1, // Opcode: MOV_A_srr
/* 688 */ MCD_OPC_FilterValue, 2, 4, 0, 0, // Skip to: 697
/* 693 */ MCD_OPC_Decode, 207, 5, 2, // Opcode: MOV_A_src
/* 693 */ MCD_OPC_Decode, 208, 5, 2, // Opcode: MOV_A_src
/* 697 */ MCD_OPC_FilterValue, 3, 121, 2, 0, // Skip to: 1335
/* 702 */ MCD_OPC_Decode, 188, 2, 8, // Opcode: BISR_sc
/* 706 */ MCD_OPC_FilterValue, 34, 39, 0, 0, // Skip to: 750
@ -318,7 +318,7 @@ static const uint8_t DecoderTable16[] = {
/* 1326 */ MCD_OPC_FilterValue, 3, 4, 0, 0, // Skip to: 1335
/* 1331 */ MCD_OPC_Decode, 230, 3, 6, // Opcode: JNE_sbr2
/* 1335 */ MCD_OPC_Fail,
0
0
};
static const uint8_t DecoderTable32[] = {
@ -331,7 +331,7 @@ static const uint8_t DecoderTable32[] = {
/* 32 */ MCD_OPC_ExtractField, 18, 10, // Inst{27-18} ...
/* 35 */ MCD_OPC_FilterValue, 0, 11, 0, 0, // Skip to: 51
/* 40 */ MCD_OPC_CheckField, 7, 1, 0, 226, 43, 0, // Skip to: 11281
/* 47 */ MCD_OPC_Decode, 204, 5, 15, // Opcode: MOV_AA_rr
/* 47 */ MCD_OPC_Decode, 205, 5, 15, // Opcode: MOV_AA_rr
/* 51 */ MCD_OPC_FilterValue, 4, 11, 0, 0, // Skip to: 67
/* 56 */ MCD_OPC_CheckField, 7, 1, 0, 210, 43, 0, // Skip to: 11281
/* 63 */ MCD_OPC_Decode, 149, 2, 15, // Opcode: ADD_A_rr
@ -358,7 +358,7 @@ static const uint8_t DecoderTable32[] = {
/* 181 */ MCD_OPC_Decode, 220, 6, 15, // Opcode: NEZ_A
/* 185 */ MCD_OPC_FilterValue, 176, 2, 11, 0, 0, // Skip to: 202
/* 191 */ MCD_OPC_CheckField, 7, 1, 0, 75, 43, 0, // Skip to: 11281
/* 198 */ MCD_OPC_Decode, 209, 5, 15, // Opcode: MOV_D_rr
/* 198 */ MCD_OPC_Decode, 210, 5, 15, // Opcode: MOV_D_rr
/* 202 */ MCD_OPC_FilterValue, 128, 3, 11, 0, 0, // Skip to: 219
/* 208 */ MCD_OPC_CheckField, 7, 1, 0, 58, 43, 0, // Skip to: 11281
/* 215 */ MCD_OPC_Decode, 138, 2, 15, // Opcode: ADDSC_A_rr
@ -367,7 +367,7 @@ static const uint8_t DecoderTable32[] = {
/* 232 */ MCD_OPC_Decode, 137, 2, 15, // Opcode: ADDSC_AT_rr
/* 236 */ MCD_OPC_FilterValue, 140, 3, 31, 43, 0, // Skip to: 11281
/* 242 */ MCD_OPC_CheckField, 7, 1, 0, 24, 43, 0, // Skip to: 11281
/* 249 */ MCD_OPC_Decode, 206, 5, 15, // Opcode: MOV_A_rr
/* 249 */ MCD_OPC_Decode, 207, 5, 15, // Opcode: MOV_A_rr
/* 253 */ MCD_OPC_FilterValue, 3, 248, 1, 0, // Skip to: 762
/* 258 */ MCD_OPC_ExtractField, 18, 6, // Inst{23-18} ...
/* 261 */ MCD_OPC_FilterValue, 2, 18, 0, 0, // Skip to: 284
@ -2626,7 +2626,7 @@ static const uint8_t DecoderTable32[] = {
/* 11135 */ MCD_OPC_FilterValue, 123, 21, 0, 0, // Skip to: 11161
/* 11140 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ...
/* 11143 */ MCD_OPC_FilterValue, 0, 4, 0, 0, // Skip to: 11152
/* 11148 */ MCD_OPC_Decode, 211, 5, 23, // Opcode: MOV_H_rlc
/* 11148 */ MCD_OPC_Decode, 204, 5, 23, // Opcode: MOVH_rlc
/* 11152 */ MCD_OPC_FilterValue, 1, 124, 0, 0, // Skip to: 11281
/* 11157 */ MCD_OPC_Decode, 214, 5, 23, // Opcode: MOV_rlcEc
/* 11161 */ MCD_OPC_FilterValue, 125, 55, 0, 0, // Skip to: 11221
@ -2658,11 +2658,11 @@ static const uint8_t DecoderTable32[] = {
/* 11272 */ MCD_OPC_FilterValue, 1, 4, 0, 0, // Skip to: 11281
/* 11277 */ MCD_OPC_Decode, 204, 3, 32, // Opcode: JGE_U_brc
/* 11281 */ MCD_OPC_Fail,
0
0
};
static bool checkDecoderPredicate(MCInst *Inst, unsigned Idx) {
/* llvm_unreachable("Invalid index!"); */
/* llvm_unreachable("Invalid index!"); */
}
#define DecodeToMCInst(fname, fieldname, InsnType) \
@ -2833,7 +2833,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
NumToSkip |= (*Ptr++) << 16; \
if (ExpectedValue != FieldValue) \
if (ExpectedValue != FieldValue) \
Ptr += NumToSkip; \
break; \
} \
@ -2842,7 +2842,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
Ptr += Len; \
NumToSkip = *Ptr++; \
NumToSkip |= (*Ptr++) << 8; \
NumToSkip |= (*Ptr++) << 16; \
NumToSkip |= (*Ptr++) << 16; \
Pred = checkDecoderPredicate(MI, PIdx); \
if (!Pred) \
Ptr += NumToSkip; \
@ -2854,9 +2854,9 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
DecodeIdx = decodeULEB128(Ptr, &Len); \
Ptr += Len; \
MCInst_clear(MI); \
MCInst_setOpcode(MI, Opc); \
MCInst_setOpcode(MI, Opc); \
return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
} \
} \
case MCD_OPC_TryDecode: { \
/* Decode the Opcode value. */ \
Opc = decodeULEB128(++Ptr, &Len); \
@ -2881,7 +2881,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
} \
break; \
} \
case MCD_OPC_SoftFail: { \
case MCD_OPC_SoftFail: { \
PositiveMask = decodeULEB128(++Ptr, &Len); \
Ptr += Len; \
NegativeMask = decodeULEB128(Ptr, &Len); \

18
arch/TriCore/TriCoreGenInstrInfo.inc
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@ -724,14 +724,14 @@
TriCore_MIN_rc = 713,
TriCore_MIN_rr = 714,
TriCore_MOVH_A_rlc = 715,
TriCore_MOV_AA_rr = 716,
TriCore_MOV_AA_srr = 717,
TriCore_MOV_A_rr = 718,
TriCore_MOV_A_src = 719,
TriCore_MOV_A_srr = 720,
TriCore_MOV_D_rr = 721,
TriCore_MOV_D_srr = 722,
TriCore_MOV_H_rlc = 723,
TriCore_MOVH_rlc = 716,
TriCore_MOV_AA_rr = 717,
TriCore_MOV_AA_srr = 718,
TriCore_MOV_A_rr = 719,
TriCore_MOV_A_src = 720,
TriCore_MOV_A_srr = 721,
TriCore_MOV_D_rr = 722,
TriCore_MOV_D_srr = 723,
TriCore_MOV_U_rlc = 724,
TriCore_MOV_rlcDc = 725,
TriCore_MOV_rlcEc = 726,
@ -1929,6 +1929,7 @@ static const MCInstrDesc TriCoreInsts[] = {
{ 3, OperandInfo46 },
{ 3, OperandInfo45 },
{ 2, OperandInfo51 },
{ 2, OperandInfo53 },
{ 3, OperandInfo50 },
{ 2, OperandInfo60 },
{ 3, OperandInfo50 },
@ -1938,7 +1939,6 @@ static const MCInstrDesc TriCoreInsts[] = {
{ 2, OperandInfo60 },
{ 2, OperandInfo53 },
{ 2, OperandInfo53 },
{ 2, OperandInfo53 },
{ 2, OperandInfo106 },
{ 3, OperandInfo45 },
{ 3, OperandInfo67 },

20
arch/TriCore/TriCoreInstrInfo.td
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@ -388,20 +388,18 @@ class IRLC<bits<8> op1, string asmstr>
[]>;
class ISRR_2<bits<8> op1, string asmstr, RegisterClass rc1, RegisterClass rc2>
: SRR<op1, (outs rc1:$d), (ins rc2:$s2),
asmstr # " $d, $s2", []>;
class ISRR<bits<8> op1, string asmstr>
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s2),
asmstr # " $d, $s2",
[]>;
: ISRR_2<op1, asmstr, DataRegs, DataRegs>;
class ISRR_AaAb<bits<8> op1, string asmstr>
: SRR<op1, (outs AddrRegs:$d), (ins AddrRegs:$s2),
asmstr # " $d, $s2",
[]>;
: ISRR_2<op1, asmstr, AddrRegs, AddrRegs>;
class ISRR_AaDb<bits<8> op1, string asmstr>
: SRR<op1, (outs AddrRegs:$d), (ins DataRegs:$s2),
asmstr # " $d, $s2",
[]>;
: ISRR_2<op1, asmstr, AddrRegs, DataRegs>;
class ISRR_a15<bits<8> op1, string asmstr>
: SRR<op1, (outs DataRegs:$d), (ins DataRegs:$s2),
@ -1389,7 +1387,7 @@ def MOV_D_rr : IRR_b<0x01, 0x4C, "mov.d", AddrRegs, AddrRegs>;
def MOV_D_srr : ISRR_AaAb<0x80, "mov.d">;
def MOV_U_rlc : IRLC_1<0xBB, "mov.u", DataRegs>;
def MOV_H_rlc : IRLC_1<0x7B, "mov.h", DataRegs>;
def MOVH_rlc : IRLC_1<0x7B, "movh", DataRegs>;
def MOVH_A_rlc : IRLC_1<0x91, "movh.a", AddrRegs>;
defm MSUB : mIRCR<0x33, 0x01, 0x33, 0x03, "msub">
@ -1740,7 +1738,7 @@ def MADD_F_rrr : IRRR_DcDdDaDb<0x6B, 0x06, "madd.f">;
def MSUB_F_rrr : IRRR_DcDdDaDb<0x6B, 0x07, "msub.f">;
def ADD_F_rrr : IRRR_DcDdDa<0x6B, 0x02, "add.f">;
def SUB_F_rrr : IRRR_DcDdDa<0x6B, 0x03, "sub.f">;
def MUL_F_rrr : IRR_DcDaDb<0x4B, 0x04, "msub.f">;
def MUL_F_rrr : IRR_DcDaDb<0x4B, 0x04, "mul.f">;
def DIV_F_rr : IRR_DcDaDb<0x4B, 0x05, "div.f">;
def CMP_F_rr : IRR_DcDaDb<0x4B, 0x00, "cmp.f">;

18
arch/TriCore/gen/TriCoreGenCSMappingInsn.inc
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@ -4302,49 +4302,49 @@
#endif
},
{
TriCore_MOV_AA_rr /* 716 */, TriCore_INS_MOV_AA,
TriCore_MOVH_rlc /* 716 */, TriCore_INS_MOVH,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_AA_srr /* 717 */, TriCore_INS_MOV_AA,
TriCore_MOV_AA_rr /* 717 */, TriCore_INS_MOV_AA,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_A_rr /* 718 */, TriCore_INS_MOV_A,
TriCore_MOV_AA_srr /* 718 */, TriCore_INS_MOV_AA,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_A_src /* 719 */, TriCore_INS_MOV_A,
TriCore_MOV_A_rr /* 719 */, TriCore_INS_MOV_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_A_srr /* 720 */, TriCore_INS_MOV_A,
TriCore_MOV_A_src /* 720 */, TriCore_INS_MOV_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_D_rr /* 721 */, TriCore_INS_MOV_D,
TriCore_MOV_A_srr /* 721 */, TriCore_INS_MOV_A,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_D_srr /* 722 */, TriCore_INS_MOV_D,
TriCore_MOV_D_rr /* 722 */, TriCore_INS_MOV_D,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
},
{
TriCore_MOV_H_rlc /* 723 */, TriCore_INS_MOV_H,
TriCore_MOV_D_srr /* 723 */, TriCore_INS_MOV_D,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif
@ -5028,7 +5028,7 @@
#endif
},
{
TriCore_MUL_F_rrr /* 837 */, TriCore_INS_MSUB_F,
TriCore_MUL_F_rrr /* 837 */, TriCore_INS_MUL_F,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
#endif

3
arch/TriCore/gen/TriCoreGenCSMappingInsnName.inc
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@ -213,10 +213,10 @@
"min.u", // TriCore_INS_MIN.U
"min", // TriCore_INS_MIN
"movh.a", // TriCore_INS_MOVH.A
"movh", // TriCore_INS_MOVH
"mov.aa", // TriCore_INS_MOV.AA
"mov.a", // TriCore_INS_MOV.A
"mov.d", // TriCore_INS_MOV.D
"mov.h", // TriCore_INS_MOV.H
"mov.u", // TriCore_INS_MOV.U
"mov", // TriCore_INS_MOV
"msubadms.h", // TriCore_INS_MSUBADMS.H
@ -243,6 +243,7 @@
"mulr.q", // TriCore_INS_MULR.Q
"muls.u", // TriCore_INS_MULS.U
"muls", // TriCore_INS_MULS
"mul.f", // TriCore_INS_MUL.F
"mul.h", // TriCore_INS_MUL.H
"mul.q", // TriCore_INS_MUL.Q
"mul.u", // TriCore_INS_MUL.U

3
include/capstone/inc/TriCoreGenCSInsnEnum.inc
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@ -213,10 +213,10 @@
TriCore_INS_MIN_U,
TriCore_INS_MIN,
TriCore_INS_MOVH_A,
TriCore_INS_MOVH,
TriCore_INS_MOV_AA,
TriCore_INS_MOV_A,
TriCore_INS_MOV_D,
TriCore_INS_MOV_H,
TriCore_INS_MOV_U,
TriCore_INS_MOV,
TriCore_INS_MSUBADMS_H,
@ -243,6 +243,7 @@
TriCore_INS_MULR_Q,
TriCore_INS_MULS_U,
TriCore_INS_MULS,
TriCore_INS_MUL_F,
TriCore_INS_MUL_H,
TriCore_INS_MUL_Q,
TriCore_INS_MUL_U,