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https://github.com/capstone-engine/capstone.git
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ST SUB SYSCALL XOR XNOR
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billow
parent
1e44b5346d
commit
1a148e2b65
@ -241,10 +241,14 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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/// 16-Bit Opcode Formats
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class ISC<bits<8> op1, string asmstr>
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class ISC_D15<bits<8> op1, string asmstr>
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: SC<op1, (outs), (ins u8imm:$const8),
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asmstr # " %d15, $const8", []>;
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class ISC_A10<bits<8> op1, string asmstr>
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: SC<op1, (outs), (ins u8imm:$const8),
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asmstr # " %a10, $const8", []>;
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class ISC_A15A10C<bits<8> op1, string asmstr>
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: SC<op1, (outs), (ins u8imm:$const8),
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asmstr # " %a15, %a10, $const8", []>;
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@ -257,8 +261,8 @@ class ISC_0<bits<8> op1, string asmstr>
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: SC<op1, (outs), (ins u8imm:$const8),
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asmstr # " $const8", []>;
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multiclass mISC_s<bits<8> op1, string asmstr> {
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def _src : ISC<op1, asmstr>;
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multiclass mISC_D15<bits<8> op1, string asmstr> {
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def _src : ISC_D15<op1, asmstr>;
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}
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let Constraints = "$s1 = $d" in {
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@ -403,7 +407,8 @@ multiclass mISRR_s<bits<8> op1, string asmstr>{
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}
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multiclass mISRR_a15a<bits<8> op1, bits<8> op2, bits<8> op3,
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string asmstr> : mISRR_s<op1,asmstr>{
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string asmstr>{
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def _srr : ISRR<op1, asmstr>;
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def _srr_a15 : ISRR_a15<op2, asmstr>;
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def _srr_15a : ISRR_15a<op3, asmstr>;
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}
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@ -533,7 +538,7 @@ defm ADDX : mIRR_RC<0x0B, 0x04, 0x8B, 0x04, "addx">;
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defm AND : mIRR_RC<0x0F, 0x08, 0x8F, 0x08, "and">,
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mISRR_s<0x26, "and">,
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mISC_s<0x16, "and">;
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mISC_D15<0x16, "and">;
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def AND_AND_T : IBIT<0x47, 0x00, "and.and.t">;
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def AND_ANDN_T : IBIT<0x47, 0x03, "and.andn.t">;
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@ -1356,7 +1361,7 @@ def MOV_rlcEc : IRLC_1<0xFB, "mov", ExtRegs>;
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def MOV_rrDcDb : IRR_DcDb<0x0B, 0x1F, "mov">;
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def MOV_rrEcDb : IRR_b<0x0B, 0x80, "mov", ExtRegs, DataRegs>;
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def MOV_rrEcDaDb : IRR_EcDaDb<0x0B, 0x81, "mov">;
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def MOV_sc : ISC<0xDA, "mov">;
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def MOV_sc : ISC_D15<0xDA, "mov">;
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def MOV_srcDa : ISRC<0x82, "mov">;
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def MOV_srcEa : ISRC_1<0xD2, "mov", ExtRegs>;
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def MOV_srr : ISRR<0x02, "mov">;
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@ -1492,7 +1497,7 @@ def NOR_T : IBIT<0x87, 0x02, "nor.t">;
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def NOT_sr : ISR_1<0x46, 0x00, "not">;
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defm OR : mIRR_RC<0x0F, 0x0A, 0x8F, 0x0A, "or">;
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def OR_sc : ISC<0x96, "or">;
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def OR_sc : ISC_D15<0x96, "or">;
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def OR_srr : ISRR<0xA6, "or">;
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def OR_AND_T : IBIT<0xC7, 0x00, "or.and.t">;
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@ -1511,7 +1516,7 @@ def OR_T : IBIT<0x87, 0x01, "or.t">;
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defm ORN : mIRR_RC<0x0F, 0x0F, 0x8F, 0x0F, "orn">;
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def ORN_T : IBIT<0x07, 0x02, "orn.t">;
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def ORN_T : IBIT<0x07, 0x01, "orn.t">;
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def PACK_rrr : IRRR_DcEdDa<0x6B, 0x00, "pack">;
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@ -1606,13 +1611,11 @@ class IBO_pre_st<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
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asmstr # " $d, [${s1}+]$off10", []>;
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}
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multiclass mIABS_BO_st<bits<8> abs1, bits<2> abs2, ///_abs
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bits<8> prefix1, bits<8> prefix2,
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bits<6> bso2, ///_bso
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bits<6> pos_r, ///_pos|_r
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bits<6> pre_c, ///_pre|_c
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string asmstr, RegisterClass rc>{
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def _abs : IABS_OR<abs1, abs2, asmstr, rc>;
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multiclass mIBO_st<bits<8> prefix1, bits<8> prefix2,
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bits<6> bso2, ///_bso
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bits<6> pos_r, ///_pos|_r
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bits<6> pre_c, ///_pre|_c
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string asmstr, RegisterClass rc>{
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def _bo_bso : IBO_bso_st<prefix1, bso2, asmstr, rc>;
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def _bo_pos : IBO_pos_st<prefix1, pos_r, asmstr, rc>;
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def _bo_pre : IBO_pre_st<prefix1, pre_c, asmstr, rc>;
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@ -1620,6 +1623,16 @@ multiclass mIABS_BO_st<bits<8> abs1, bits<2> abs2, ///_abs
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def _bo_c : IBO_c_st<prefix2, pre_c, asmstr, rc>;
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}
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multiclass mIABS_BO_st<bits<8> abs1, bits<2> abs2, ///_abs
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bits<8> prefix1, bits<8> prefix2,
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bits<6> bso2, ///_bso
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bits<6> pos_r, ///_pos|_r
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bits<6> pre_c, ///_pre|_c
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string asmstr, RegisterClass rc>
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: mIBO_st<prefix1, prefix2, bso2, pos_r, pre_c, asmstr, rc>{
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def _abs : IABS_OR<abs1, abs2, asmstr, rc>;
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}
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defm ST_A : mIABS_BO_st<0xA5, 0x02, 0x89, 0xA9, 0x26, 0x06, 0x16, "st.a", AddrRegs>;
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defm ST_B : mIABS_BO_st<0x25, 0x00, 0x89, 0xA9, 0x20, 0x00, 0x10, "st.b", DataRegs>;
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defm ST_D : mIABS_BO_st<0xA5, 0x01, 0x89, 0xA9, 0x25, 0x05, 0x15, "st.d", ExtRegs>;
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@ -1648,22 +1661,78 @@ defm ST_B : mISRO_SSR_SSRO_st<0x2C, 0x34, 0x24, 0x28, "st.b", AddrRegs>;
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def ST_H_bol : IBOL_AbOR<0xF9, "st.h", DataRegs>;
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defm ST_H : mISRO_SSR_SSRO_st<0xAC, 0xB4, 0xA4, 0xA8, "st.h", AddrRegs>;
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// def ST_T : ;
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def ST_T : ABSB<0xD5, 0x00, (outs), (ins i32imm:$off18, i32imm:$bpos3, i32imm:$b),
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"st.t $off18, $bpos3, $b", []>;
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let Defs = [PSW], Uses = [PSW] in {
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def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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"subc $d, $s1, $s2",
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[(set DataRegs:$d, (subc DataRegs:$s1, DataRegs:$s2)),
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(implicit PSW)]>;
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defm ST_W : mIABS_BO_st<0xA5, 0x00, 0x89, 0xA9, 0x24, 0x04, 0x14, "st.w", DataRegs>;
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def ST_W_bol : IBOL_AbOR<0x59, "st.w", DataRegs>;
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defm ST_W : mISRO_SSR_SSRO_st<0x6C, 0x74, 0x64, 0x68, "st.w", DataRegs>;
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def SUBXrr : RR<0x0B, 0x0C, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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"subx $d, $s1, $s2",
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[(set DataRegs:$d, (sube DataRegs:$s1, DataRegs:$s2)),
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(implicit PSW)]>;
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def STLCX_abs : IABS_off18<0x15, 0x00, "stlcx">;
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def STLCX_bo_bso : IBO_bso<0x49, 0x26, "stlcx">;
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} // let Defs = [PSW], Uses = [PSW]
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def STUCX_abs : IABS_off18<0x15, 0x01, "stucx">;
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def STUCX_bo_bso : IBO_bso<0x49, 0x27, "stucx">;
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def SUB_rr : IRR_DcDaDb<0x0B, 0x08, "sub">;
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defm SUB : mISRR_a15a<0xA2, 0x52, 0x5A, "sub">
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, mIB_H<0x0B, 0x48, 0x0B, 0x68, "sub">;
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def SUB_A_rr : IRR_2<0x01, 0x02, "sub.a", AddrRegs, AddrRegs, AddrRegs>;
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def SUB_A_sc : ISC_A10<0x20, "sub.a">;
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def SUBC_rr : IRR2_RcDaDb<0x0B, 0x0D, "subc", DataRegs>;
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def SUBS_rr : IRR2_RcDaDb<0x0B, 0x0A, "subs", DataRegs>;
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def SUBS_srr : ISRR<0x62, "subs">;
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def SUBS_U_rr : IRR2_RcDaDb<0x0B, 0x0B, "subs.u", DataRegs>;
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def SUBS_H_rr : IRR2_RcDaDb<0x0B, 0x6A, "subs.h", DataRegs>;
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def SUBS_HU_rr : IRR2_RcDaDb<0x0B, 0x6B, "subs.hu", DataRegs>;
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def SUBX_rr : IRR2_RcDaDb<0x0B, 0x0C, "subx", DataRegs>;
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def SVLCX_sys : ISYS_0<0x0D, 0x08, "svlcx">;
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defm SWAP_W : mIABS_BO_st<0xE5, 0x00, 0x49, 0x69, 0x20, 0x00, 0x10, "swap.w", DataRegs>;
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defm SWAPMSK_W : mIBO_st<0x49, 0x69, 0x22, 0x02, 0x12, "swapmsk.w", ExtRegs>;
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def SYSCALL_rc : IRC<0xAD, 0x04, "syscall">;
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def TRAPSV_sys : ISYS_0<0x0D, 0x15, "trapsv">;
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def TRAPV_sys : ISYS_0<0x0D, 0x14, "trapv">;
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def UNPACK_rr : IRR_EcDa<0x4B, 0x08, "unpack">;
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def WAIT_sys : ISYS_0<0x0D, 0x16, "wait">;
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defm XNOR : mIRR_RC<0x0F, 0x0D, 0x8F, 0x0D, "xnor">;
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def XNOR_T : IBIT<0x07, 0x02, "xnor.t">;
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defm XOR : mIRR_RC<0x0F, 0x0C, 0x8F, 0x0C, "xor">;
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def XOR_srr : ISRR<0xC6, "xor">;
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def XOR_T : IBIT<0x07, 0x03, "xor.t">;
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defm XOR_EQ : mIRR_RC<0x0B, 0x2F, 0x8B, 0x2F, "xor.eq">;
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defm XOR_NE : mIRR_RC<0x0B, 0x30, 0x8B, 0x30, "xor.nq">;
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defm XOR_GE : mIRR_RC<0x0B, 0x33, 0x8B, 0x33, "xor.ge">;
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defm XOR_GE_U : mIRR_RC<0x0B, 0x34, 0x8B, 0x34, "xor.ge.u">;
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defm XOR_LT : mIRR_RC<0x0B, 0x31, 0x8B, 0x31, "xor.lt">;
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defm XOR_LT_U : mIRR_RC<0x0B, 0x32, 0x8B, 0x32, "xor.lt.u">;
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// let Defs = [PSW], Uses = [PSW] in {
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// def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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// (ins DataRegs:$s1, DataRegs:$s2),
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// "subc $d, $s1, $s2",
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// [(set DataRegs:$d, (subc DataRegs:$s1, DataRegs:$s2)),
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// (implicit PSW)]>;
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// def SUBXrr : RR<0x0B, 0x0C, (outs DataRegs:$d),
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// (ins DataRegs:$s1, DataRegs:$s2),
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// "subx $d, $s1, $s2",
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// [(set DataRegs:$d, (sube DataRegs:$s1, DataRegs:$s2)),
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// (implicit PSW)]>;
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// } // let Defs = [PSW], Uses = [PSW]
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def imml_32_h_32 : Operand<i64>, PatLeaf<(imm), [{
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@ -1675,34 +1744,34 @@ def imml_32_h_32 : Operand<i64>, PatLeaf<(imm), [{
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}]>;
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let Defs = [PSW] in {
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def ADDi64C : Pseudo<(outs ExtRegs:$d),
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(ins ExtRegs:$s1, imml_32_h_32:$const64),
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"ADDi64C Pseudo",
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[(set ExtRegs:$d, (add ExtRegs:$s1, imml_32_h_32:$const64)),
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(implicit PSW)]>;
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// let Defs = [PSW] in {
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// def ADDi64C : Pseudo<(outs ExtRegs:$d),
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// (ins ExtRegs:$s1, imml_32_h_32:$const64),
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// "ADDi64C Pseudo",
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// [(set ExtRegs:$d, (add ExtRegs:$s1, imml_32_h_32:$const64)),
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// (implicit PSW)]>;
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def ADDi64 : Pseudo<(outs ExtRegs:$d),
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(ins ExtRegs:$s1, ExtRegs:$s2),
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"ADDi64 Pseudo",
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[(set ExtRegs:$d, (add ExtRegs:$s1, ExtRegs:$s2)),
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(implicit PSW)]>;
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// def ADDi64 : Pseudo<(outs ExtRegs:$d),
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// (ins ExtRegs:$s1, ExtRegs:$s2),
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// "ADDi64 Pseudo",
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// [(set ExtRegs:$d, (add ExtRegs:$s1, ExtRegs:$s2)),
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// (implicit PSW)]>;
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def SUBi64 : Pseudo<(outs ExtRegs:$d),
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(ins ExtRegs:$s1, ExtRegs:$s2),
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"SUBi64 Pseudo",
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[(set ExtRegs:$d, (sub ExtRegs:$s1, ExtRegs:$s2)),
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(implicit PSW)]>;
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// def SUBi64 : Pseudo<(outs ExtRegs:$d),
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// (ins ExtRegs:$s1, ExtRegs:$s2),
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// "SUBi64 Pseudo",
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// [(set ExtRegs:$d, (sub ExtRegs:$s1, ExtRegs:$s2)),
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// (implicit PSW)]>;
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} //let Defs = [PSW]
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// } //let Defs = [PSW]
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let Defs = [A10], Uses = [A10] in
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def SUB_Asc : SC<0x20, (outs), (ins u8imm:$const8), "sub.a %a10, $const8",
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[(set A10, (sub A10, immZExt8:$const8) )]>;
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// let Defs = [A10], Uses = [A10] in
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// def SUB_Asc : SC<0x20, (outs), (ins u8imm:$const8), "sub.a %a10, $const8",
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// [(set A10, (sub A10, immZExt8:$const8) )]>;
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def SUB_Arr : RR<0x01, 0x02, (outs AddrRegs:$d),
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(ins AddrRegs:$s1, AddrRegs:$s2), "sub.a $d, $s1, $s2",
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[(set AddrRegs:$d, (sub AddrRegs:$s1, AddrRegs:$s2) )]>;
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// def SUB_Arr : RR<0x01, 0x02, (outs AddrRegs:$d),
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// (ins AddrRegs:$s1, AddrRegs:$s2), "sub.a $d, $s1, $s2",
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// [(set AddrRegs:$d, (sub AddrRegs:$s1, AddrRegs:$s2) )]>;
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// def RSUBrc : RC<0x8B, 0x08, (outs DataRegs:$d),
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// (ins DataRegs:$s1, s9imm:$const9) ,"rsub $d, $s1, $const9",
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