Add PPC paired-singles ext

cs.c

@@ -121,7 +121,7 @@ static const struct {
 		PPC_global_init,
 		PPC_option,
 		~(CS_MODE_LITTLE_ENDIAN | CS_MODE_32 | CS_MODE_64 | CS_MODE_BIG_ENDIAN
-				| CS_MODE_QPX),
+				| CS_MODE_QPX | CS_MODE_PS),
 	},
 #else
 	{ NULL, NULL, 0 },

include/capstone/capstone.h

@@ -120,6 +120,7 @@ typedef enum cs_mode {
 	CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
 	CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
 	CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
+	CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
 	CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
 	CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
 	CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode

include/capstone/ppc.h

@@ -2030,6 +2030,46 @@ typedef enum ppc_insn {
 	PPC_INS_XXSPLTIB,
 	PPC_INS_XXSPLTW,
 	PPC_INS_XXSWAPD,
+
+	PPC_INS_DCBZ_L,
+	PPC_INS_PSQ_L,
+	PPC_INS_PSQ_LU,
+	PPC_INS_PSQ_LUX,
+	PPC_INS_PSQ_LX,
+	PPC_INS_PSQ_ST,
+	PPC_INS_PSQ_STU,
+	PPC_INS_PSQ_STUX,
+	PPC_INS_PSQ_STX,
+	PPC_INS_PS_ABS,
+	PPC_INS_PS_ADD,
+	PPC_INS_PS_CMPO0,
+	PPC_INS_PS_CMPO1,
+	PPC_INS_PS_CMPU0,
+	PPC_INS_PS_CMPU1,
+	PPC_INS_PS_DIV,
+	PPC_INS_PS_MADD,
+	PPC_INS_PS_MADDS0,
+	PPC_INS_PS_MADDS1,
+	PPC_INS_PS_MERGE00,
+	PPC_INS_PS_MERGE01,
+	PPC_INS_PS_MERGE10,
+	PPC_INS_PS_MERGE11,
+	PPC_INS_PS_MR,
+	PPC_INS_PS_MSUB,
+	PPC_INS_PS_MUL,
+	PPC_INS_PS_MULS0,
+	PPC_INS_PS_MULS1,
+	PPC_INS_PS_NABS,
+	PPC_INS_PS_NEG,
+	PPC_INS_PS_NMADD,
+	PPC_INS_PS_NMSUB,
+	PPC_INS_PS_RES,
+	PPC_INS_PS_RSQRTE,
+	PPC_INS_PS_SEL,
+	PPC_INS_PS_SUB,
+	PPC_INS_PS_SUM0,
+	PPC_INS_PS_SUM1,
+
 	PPC_INS_ENDING,   // <-- mark the end of the list of instructions
 } ppc_insn;
 
@@ -2056,6 +2096,7 @@ typedef enum ppc_insn_group {
 	PPC_GRP_P8ALTIVEC,
 	PPC_GRP_P8VECTOR,
 	PPC_GRP_QPX,
+	PPC_GRP_PS,
 
 	PPC_GRP_ENDING,   // <-- mark the end of the list of groups
 } ppc_insn_group;

suite/cstest/src/main.c

@@ -37,6 +37,7 @@ static single_dict arches[] = {
 	{"CS_MODE_MIPS2", CS_MODE_MIPS2},
 	{"CS_MODE_V9", CS_MODE_V9},
 	{"CS_MODE_QPX", CS_MODE_QPX},
+	{"CS_MODE_PS", CS_MODE_PS},
 	{"CS_MODE_M68K_000", CS_MODE_M68K_000},
 	{"CS_MODE_M68K_010", CS_MODE_M68K_010},
 	{"CS_MODE_M68K_020", CS_MODE_M68K_020},
@@ -84,6 +85,7 @@ static single_dict arches[] = {
 	{"CS_MODE_MIPS2", CS_OPT_MODE, CS_MODE_MIPS2},
 	{"CS_MODE_V9", CS_OPT_MODE, CS_MODE_V9},
 	{"CS_MODE_QPX", CS_OPT_MODE, CS_MODE_QPX},
+	{"CS_MODE_PS", CS_OPT_MODE, CS_MODE_PS},
 	{"CS_MODE_M68K_000", CS_OPT_MODE, CS_MODE_M68K_000},
 	{"CS_MODE_M68K_010", CS_OPT_MODE, CS_MODE_M68K_010},
 	{"CS_MODE_M68K_020", CS_OPT_MODE, CS_MODE_M68K_020},

suite/synctools/tablegen/PPC/PPC.td

@@ -191,6 +191,9 @@ def FeatureP9Vector  : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
                                         "Enable POWER9 vector instructions",
                                         [FeatureISA3_0, FeatureP8Vector,
                                          FeatureP9Altivec]>;
+def FeaturePS        : SubtargetFeature<"ps","HasPS","false",
+                              "Enable paired-singles instructions",
+                              [FeatureFPU]>;
 
 // Since new processors generally contain a superset of features of those that
 // came before them, the idea is to make implementations of new processors
@@ -335,6 +338,9 @@ def : Processor<"620", G3Itineraries, [Directive620,
 def : Processor<"750", G4Itineraries, [Directive750,
                                        FeatureFRES, FeatureFRSQRTE,
                                        FeatureMFTB]>;
+def : Processor<"750cl", G4Itineraries, [Directive750,
+                                       FeatureFRES, FeatureFRSQRTE,
+                                       FeatureMFTB, FeaturePS]>;
 def : Processor<"g3", G3Itineraries, [Directive750,
                                       FeatureFRES, FeatureFRSQRTE,
                                       FeatureMFTB]>;

suite/synctools/tablegen/PPC/PPCInstrFormats.td

@@ -1365,6 +1365,106 @@ class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{31}    = 0;
 }
 
+// PSForm_qd - Undocumented paired-singles quantized load/store form direct.
+class PSForm_qd<bits<6> op, dag OOL, dag IOL, string asmstr,
+                InstrItinClass itin>
+    : I<op, OOL, IOL, asmstr, itin> {
+  bits<5> FRT;
+  bit W;
+  bits<3> I;
+  bits<12> d;
+  bits<5> A;
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-15} = A;
+  let Inst{16}    = W;
+  let Inst{17-19} = I;
+  let Inst{20-31} = d;
+}
+
+// PSForm_qi - Undocumented paired-singles quantized load/store form indexed.
+class PSForm_qi<bits<6> psqop, dag OOL, dag IOL, string asmstr,
+                InstrItinClass itin>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> FRT;
+  bits<5> A;
+  bits<5> B;
+  bit W;
+  bits<3> I;
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21}    = W;
+  let Inst{22-24} = I;
+  let Inst{25-30} = psqop;
+  let Inst{31}    = 0;
+}
+
+// PSForm_x - Undocumented paired-singles operation base form, short opcode.
+class PSForm_x<bits<5> psxop, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> FRT;
+  bits<5> FRA;
+  bits<5> FRB;
+  bits<5> FRC;
+  bit RC = 0; // set by isDOT
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-15} = FRA;
+  let Inst{16-20} = FRB;
+  let Inst{21-25} = FRC;
+  let Inst{26-30} = psxop;
+  let Inst{31}    = RC;
+}
+
+// PSForm_y - Undocumented paired-singles operation base form, long opcode.
+class PSForm_y<bits<10> psyop, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> FRT;
+  bits<5> FRA;
+  bits<5> FRB;
+  bit RC = 0; // set by isDOT
+
+  let Inst{6-10}  = FRT;
+  let Inst{11-15} = FRA;
+  let Inst{16-20} = FRB;
+  let Inst{21-30} = psyop;
+  let Inst{31}    = RC;
+}
+
+// PSForm_c - Undocumented paired-singles compare form.
+class PSForm_c<bits<10> pszop, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<5> FRA;
+  bits<5> FRB;
+
+  let Inst{6-8}   = BF;
+  let Inst{9-10}  = 0;
+  let Inst{11-15} = FRA;
+  let Inst{16-20} = FRB;
+  let Inst{21-30} = pszop;
+  let Inst{31}    = 0;
+}
+
+// Undocumented dcbz_l instruction.
+class DCBZL_Form<bits<10> xop, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> A;
+  bits<5> B;
+
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xop;
+  let Inst{31}    = 0;
+}
+
 // 1.7.7 XL-Form
 class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>

suite/synctools/tablegen/PPC/PPCInstrInfo.td

@@ -801,6 +801,13 @@ def PPCDispSPE2Operand : AsmOperandClass {
 def dispSPE2 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE2Operand;
 }
+def PPCDispRID12Operand : AsmOperandClass {
+ let Name = "DispRID12"; let PredicateMethod = "isS12Imm";
+ let RenderMethod = "addImmOperands";
+}
+def dispRID12 : Operand<iPTR> {
+  let ParserMatchClass = PPCDispRID12Operand;
+}
 
 def memri : Operand<iPTR> {
   let PrintMethod = "printMemRegImm";
@@ -842,6 +849,10 @@ def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
   let EncoderMethod = "getSPE2DisEncoding";
   let DecoderMethod = "decodeSPE2Operands";
 }
+def memrid12 : Operand<iPTR> {  // Paired Single displacement where imm is 12 bits.
+  let PrintMethod = "printMemRegImm";
+  let MIOperandInfo = (ops dispRID12:$imm, ptr_rc_nor0:$reg);
+}
 
 // A single-register address. This is used with the SjLj
 // pseudo-instructions which tranlates to LD/LWZ.  These instructions requires
@@ -3166,6 +3177,7 @@ def : Pat<(fcopysign f32:$frB, f64:$frA),
 }
 
 include "PPCInstrAltivec.td"
+include "PPCInstrPS.td"
 include "PPCInstrSPE.td"
 include "PPCInstr64Bit.td"
 include "PPCInstrVSX.td"

suite/synctools/tablegen/PPC/PPCInstrPS.td

@@ -0,0 +1,219 @@
+def HasPS : Predicate<"PPCSubTarget->hasPS()">;
+let Predicates = [HasPS] in {
+let DecoderNamespace = "PS" in {
+
+def PSQ_L    : PSForm_qd<56,
+               (outs f8rc:$FRT), (ins memrid12:$src, u1imm:$W, u3imm: $I),
+               "psq_l $FRT, $src, $W, $I", IIC_FPGeneral>;
+def PSQ_LU   : PSForm_qd<57,
+               (outs f8rc:$FRT), (ins memrid12:$src, u1imm:$W, u3imm: $I),
+               "psq_lu $FRT, $src, $W, $I", IIC_FPGeneral>;
+def PSQ_ST   : PSForm_qd<60,
+               (outs), (ins f8rc:$FRT, memrid12:$dst, u1imm:$W, u3imm: $I),
+               "psq_st $FRT, $dst, $W, $I", IIC_FPGeneral>;
+def PSQ_STU  : PSForm_qd<61,
+               (outs), (ins f8rc:$FRT, memrid12:$dst, u1imm:$W, u3imm: $I),
+               "psq_stu $FRT, $dst, $W, $I", IIC_FPGeneral>;
+
+def PSQ_LX   : PSForm_qi<6,
+               (outs f8rc:$FRT), (ins gprc:$rA, gprc:$rB, u1imm:$W, u3imm: $I),
+               "psq_lx $FRT, $rA, $rB, $W, $I", IIC_FPGeneral>;
+def PSQ_STX  : PSForm_qi<7,
+               (outs), (ins f8rc:$FRT,gprc:$rA, gprc:$rB, u1imm:$W, u3imm: $I),
+               "psq_stx $FRT, $rA, $rB, $W, $I", IIC_FPGeneral>;
+def PSQ_LUX  : PSForm_qi<38,
+               (outs f8rc:$FRT), (ins gprc:$rA, gprc:$rB, u1imm:$W, u3imm: $I),
+               "psq_lux $FRT, $rA, $rB, $W, $I", IIC_FPGeneral>;
+def PSQ_STUX : PSForm_qi<39,
+               (outs), (ins f8rc:$FRT,gprc:$rA, gprc:$rB, u1imm:$W, u3imm: $I),
+               "psq_stux $FRT, $rA, $rB, $W, $I", IIC_FPGeneral>;
+
+// op. FRT, FRA, FRC, FRB
+multiclass PSForm_xr<bits<5> psxop, dag OOL, dag IOL, string asmbase,
+                     string asmstr, InstrItinClass itin> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_x<psxop, OOL, IOL,
+                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin>;
+    let Defs = [CR1] in
+    def o    : PSForm_x<psxop, OOL, IOL,
+                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin>,
+                        isDOT;
+  }
+}
+
+// op FRT, FRA, FRB
+class PSForm_x1<bits<5> psxop, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin>
+    : PSForm_x<psxop, OOL, IOL, asmstr, itin> {
+  let FRC = 0;
+}
+
+// op. FRT, FRA, FRB
+multiclass PSForm_x1r<bits<5> psxop, dag OOL, dag IOL, string asmbase,
+                      string asmstr, InstrItinClass itin> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_x1<psxop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin>;
+    let Defs = [CR1] in
+    def o    : PSForm_x1<psxop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin>,
+                         isDOT;
+  }
+}
+
+// op FRT, FRB
+class PSForm_x2<bits<5> psxop, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin>
+    : PSForm_x<psxop, OOL, IOL, asmstr, itin> {
+  let FRA = 0;
+  let FRC = 0;
+}
+
+// op. FRT, FRB
+multiclass PSForm_x2r<bits<5> psxop, dag OOL, dag IOL, string asmbase,
+                      string asmstr, InstrItinClass itin> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_x2<psxop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin>;
+    let Defs = [CR1] in
+    def o    : PSForm_x2<psxop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin>,
+                         isDOT;
+  }
+}
+
+// op FRT, FRA, FRC
+class PSForm_x3<bits<5> psxop, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin>
+    : PSForm_x<psxop, OOL, IOL, asmstr, itin> {
+  let FRB = 0;
+}
+
+// op. FRT, FRA, FRC
+multiclass PSForm_x3r<bits<5> psxop, dag OOL, dag IOL, string asmbase,
+                      string asmstr, InstrItinClass itin> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_x3<psxop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin>;
+    let Defs = [CR1] in
+    def o    : PSForm_x3<psxop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin>,
+                         isDOT;
+  }
+}
+
+// op. FRT, FRA, FRB
+multiclass PSForm_yr<bits<10> psyop, dag OOL, dag IOL, string asmbase,
+                     string asmstr, InstrItinClass itin> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_y<psyop, OOL, IOL,
+                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin>;
+    let Defs = [CR1] in
+    def o    : PSForm_y<psyop, OOL, IOL,
+                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin>,
+                        isDOT;
+  }
+}
+
+// op FRT, FRA, FRB
+class PSForm_y2<bits<10> psyop, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin>
+    : PSForm_y<psyop, OOL, IOL, asmstr, itin> {
+  let FRA = 0;
+}
+
+// op. FRT, FRB
+multiclass PSForm_y2r<bits<10> psyop, dag OOL, dag IOL, string asmbase,
+                      string asmstr, InstrItinClass itin> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_y2<psyop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(" ", asmstr)), itin>;
+    let Defs = [CR1] in
+    def o    : PSForm_y2<psyop, OOL, IOL,
+                         !strconcat(asmbase, !strconcat(". ", asmstr)), itin>,
+                         isDOT;
+  }
+}
+
+defm PS_DIV : PSForm_x1r<18, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_div", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_SUB : PSForm_x1r<20, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_sub", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_ADD : PSForm_x1r<21, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_add", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_SEL : PSForm_xr<23,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_sel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_RES : PSForm_x2r<24, (outs f8rc:$FRT), (ins f8rc:$FRB),
+                      "ps_res", "$FRT, $FRB", IIC_FPGeneral>;
+defm PS_MUL : PSForm_x3r<25, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
+                      "ps_mul", "$FRT, $FRA, $FRC", IIC_FPGeneral>;
+defm PS_RSQRTE : PSForm_x2r<26, (outs f8rc:$FRT), (ins f8rc:$FRB),
+                      "ps_rsqrte", "$FRT, $FRB", IIC_FPGeneral>;
+defm PS_MSUB : PSForm_xr<28,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_msub", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_MADD : PSForm_xr<29,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_madd", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_NMSUB : PSForm_xr<30,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_nmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_NMADD : PSForm_xr<31,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_nmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_NEG : PSForm_y2r<40, (outs f8rc:$FRT), (ins f8rc:$FRB),
+                      "ps_neg", "$FRT, $FRB", IIC_FPGeneral>;
+defm PS_MR : PSForm_y2r<72, (outs f8rc:$FRT), (ins f8rc:$FRB),
+                      "ps_mr", "$FRT, $FRB", IIC_FPGeneral>;
+defm PS_NABS : PSForm_y2r<136, (outs f8rc:$FRT), (ins f8rc:$FRB),
+                      "ps_nabs", "$FRT, $FRB", IIC_FPGeneral>;
+defm PS_ABS : PSForm_y2r<264, (outs f8rc:$FRT), (ins f8rc:$FRB),
+                      "ps_abs", "$FRT, $FRB", IIC_FPGeneral>;
+defm PS_SUM0 : PSForm_xr<10,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_sum0", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_SUM1 : PSForm_xr<11,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_sum1", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_MULS0 : PSForm_x3r<12, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
+                      "ps_muls0", "$FRT, $FRA, $FRC", IIC_FPGeneral>;
+defm PS_MULS1 : PSForm_x3r<13, (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
+                      "ps_muls1", "$FRT, $FRA, $FRC", IIC_FPGeneral>;
+defm PS_MADDS0 : PSForm_xr<14,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_madds0", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+defm PS_MADDS1 : PSForm_xr<15,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
+                      "ps_madds1", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral>;
+def PS_CMPU0 : PSForm_c<0,
+                      (outs crrc:$crD), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_cmpu0 $crD, $FRA, $FRB", IIC_FPGeneral>;
+def PS_CMPO0 : PSForm_c<32,
+                      (outs crrc:$crD), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_cmpo0 $crD, $FRA, $FRB", IIC_FPGeneral>;
+def PS_CMPU1 : PSForm_c<64,
+                      (outs crrc:$crD), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_cmpu1 $crD, $FRA, $FRB", IIC_FPGeneral>;
+def PS_CMPO1 : PSForm_c<96,
+                      (outs crrc:$crD), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_cmpo1 $crD, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_MERGE00 : PSForm_yr<528,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_merge00", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_MERGE01 : PSForm_yr<560,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_merge01", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_MERGE10 : PSForm_yr<592,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_merge10", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+defm PS_MERGE11 : PSForm_yr<624,
+                      (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB),
+                      "ps_merge11", "$FRT, $FRA, $FRB", IIC_FPGeneral>;
+
+def PSC_DCBZL : DCBZL_Form<1014,
+                           (outs), (ins gprc:$rA, gprc:$rB),
+                           "dcbz_l $rA, $rB", IIC_FPGeneral>;
+
+}
+}

suite/synctools/tablegen/PPC/PPCScheduleP9.td

@@ -37,7 +37,7 @@ def P9Model : SchedMachineModel {
 
   // Do not support QPX (Quad Processing eXtension) or SPE (Signal Procesing
   // Engine) on Power 9.
-  let UnsupportedFeatures = [HasQPX, HasSPE];
+  let UnsupportedFeatures = [HasQPX, HasSPE, HasPS];
 
 }
 

suite/test_group_name.py

@@ -146,6 +146,7 @@ ppc_dict = {
     PPC_GRP_P8ALTIVEC: "p8altivec",
     PPC_GRP_P8VECTOR: "p8vector",
     PPC_GRP_QPX: "qpx",
+    PPC_GRP_PS: "ps",
 }
 
 sparc_dict = {

tests/test_ppc.c

@@ -115,6 +115,7 @@ static void test()
 {
 #define PPC_CODE "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
 #define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
+#define PPC_CODE3 "\x10\x00\x1f\xec\xe0\x6d\x80\x04\xe4\x6d\x80\x04\x10\x60\x1c\x4c\x10\x60\x1c\x0c\xf0\x6d\x80\x04\xf4\x6d\x80\x04\x10\x60\x1c\x4e\x10\x60\x1c\x0e\x10\x60\x1a\x10\x10\x60\x1a\x11\x10\x63\x20\x2a\x10\x63\x20\x2b\x10\x83\x20\x40\x10\x83\x20\xC0\x10\x83\x20\x00\x10\x83\x20\x80\x10\x63\x20\x24\x10\x63\x20\x25\x10\x63\x29\x3a\x10\x63\x29\x3b\x10\x63\x29\x1c\x10\x63\x29\x1d\x10\x63\x29\x1e\x10\x63\x29\x1f\x10\x63\x24\x20\x10\x63\x24\x21\x10\x63\x24\x60\x10\x63\x24\x61\x10\x63\x24\xA0\x10\x63\x24\xA1\x10\x63\x24\xE0\x10\x63\x24\xE1\x10\x60\x20\x90\x10\x60\x20\x91\x10\x63\x29\x38\x10\x63\x29\x39\x10\x63\x01\x32\x10\x63\x01\x33\x10\x63\x01\x18\x10\x63\x01\x19\x10\x63\x01\x1A\x10\x63\x01\x1B\x10\x60\x19\x10\x10\x60\x19\x11\x10\x60\x18\x50\x10\x60\x18\x51\x10\x63\x29\x3e\x10\x63\x29\x3f\x10\x63\x29\x3c\x10\x63\x29\x3d\x10\x60\x18\x30\x10\x60\x18\x31\x10\x60\x18\x34\x10\x60\x18\x35\x10\x63\x29\x2e\x10\x63\x29\x2f\x10\x63\x20\x28\x10\x63\x20\x29\x10\x63\x29\x14\x10\x63\x29\x15\x10\x63\x29\x16\x10\x63\x29\x17"
 
 	struct platform platforms[] = {
 		{
@@ -131,6 +132,13 @@ static void test()
 			sizeof(PPC_CODE2) - 1,
 			"PPC-64 + QPX",
 		},
+		{
+			CS_ARCH_PPC,
+			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_PS),
+			(unsigned char*)PPC_CODE3,
+			sizeof(PPC_CODE3) - 1,
+			"PPC + PS",
+		},
 	};
 
 	uint64_t address = 0x1000;