From 1a6921f5cc3e1084a6658ad05ed2c00a7ff1fd00 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Fri, 31 May 2024 12:07:03 +0000 Subject: [PATCH] AArch64 compatibility header (#2321) --- .github/workflows/CITest.yml | 6 + CMakeLists.txt | 1 + docs/cs_v6_release_guide.md | 26 +- include/capstone/arm64.h | 4481 +++++++++++++++++ include/capstone/capstone.h | 21 +- suite/auto-sync/c_tests/README.md | 6 + .../src/test_arm64_compatibility_header.c | 40 + suite/auto-sync/src/autosync/ASUpdater.py | 9 +- suite/auto-sync/src/autosync/HeaderPatcher.py | 156 +- .../src/autosync/Tests/test_aarch64_header.h | 49 + .../src/autosync/Tests/test_arm64_header.h | 34 + .../src/autosync/Tests/test_header_patcher.py | 13 +- suite/auto-sync/src/autosync/path_vars.json | 6 +- 13 files changed, 4833 insertions(+), 15 deletions(-) create mode 100644 include/capstone/arm64.h create mode 100644 suite/auto-sync/c_tests/README.md create mode 100644 suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c create mode 100644 suite/auto-sync/src/autosync/Tests/test_aarch64_header.h create mode 100644 suite/auto-sync/src/autosync/Tests/test_arm64_header.h diff --git a/.github/workflows/CITest.yml b/.github/workflows/CITest.yml index b4da67c8d..c8fd87c66 100644 --- a/.github/workflows/CITest.yml +++ b/.github/workflows/CITest.yml @@ -100,6 +100,12 @@ jobs: cp libcapstone.* ../tests/ cp test_* ../tests/ + - name: "Compatibility header test build" + run: | + cd "$(git rev-parse --show-toplevel)/suite/auto-sync/c_tests/" + clang -lcapstone src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header + ./test_arm64_compatibility_header + - name: cstool - reaches disassembler engine run: | sh suite/run_invalid_cstool.sh diff --git a/CMakeLists.txt b/CMakeLists.txt index 0a42ef28b..e7df843f4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -157,6 +157,7 @@ set(HEADERS_ENGINE set(HEADERS_COMMON include/capstone/aarch64.h + include/capstone/arm64.h include/capstone/arm.h include/capstone/capstone.h include/capstone/cs_operand.h diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index 4ac1b2bc3..896479c91 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -84,16 +84,30 @@ With all that said, we hope you enjoy the new release! `ARM64` was everywhere renamed to `AArch64`. This is a necessity to ensure that the update scripts stay reasonably simple. Capstone was very inconsistent with the naming before (sometimes `AArch64` sometimes `ARM64`). -Because Capstone uses a huge amount of LLVM code, we renamed everything to `AArch64`. This reduces complexity enormously. +Because Capstone uses a huge amount of LLVM code, we renamed everything to `AArch64`. This reduces complexity enormously because it follows the naming of LLVM. -Because this would completely break maintaining Capstone `v6` and `pre-v6` in a project, we added macros for meta-programming. +Because this would completely break maintaining Capstone `v6` and `pre-v6` in a project, we added two solutions: -If you need to support the previous version of Capstone as well, you can use those macros (see below helper scripts). -Also, your can exclude/include code by checking `CS_NEXT_VERSION < 6`. +1. Make `arm64.h` a compatibility header which merely maps every member to the one in the `aarch64.h` header. +2. Macros for meta-programming which select the right name. -The following `sed` commands in a sh script should ease the renaming from `ARM64` to `AArch64` a lot. +We will continue to maintain both solutions. +So if you need to support the previous version of Capstone as well, you can use either of the solutions. -Replacing with version sensitive macros: +_Compatibility header_ + +If you want to use the compatibility header and stick with the `ARM64` naming, you can define `CAPSTONE_AARCH64_COMPAT_HEADER` before including `capstone.h`. + +```c +#define CAPSTONE_AARCH64_COMPAT_HEADER +#include + +// Your code... +``` + +_Meta programming macros_ + +The following `sed` commands in a sh script should ease the replacement of `ARM64` with the macros a lot. ```sh #!/bin/sh diff --git a/include/capstone/arm64.h b/include/capstone/arm64.h new file mode 100644 index 000000000..5e9d80268 --- /dev/null +++ b/include/capstone/arm64.h @@ -0,0 +1,4481 @@ +#ifndef CAPSTONE_ARM64_H +#define CAPSTONE_ARM64_H + +/* Capstone Disassembly Engine */ +/* By Nguyen Anh Quynh , 2013-2015 */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "cs_operand.h" +#include "platform.h" + +#include + +#ifdef _MSC_VER +#pragma warning(disable : 4201) +#endif + +typedef enum { + ARM64_SFT_INVALID = AArch64_SFT_INVALID, + ARM64_SFT_LSL = AArch64_SFT_LSL, + ARM64_SFT_MSL = AArch64_SFT_MSL, + ARM64_SFT_LSR = AArch64_SFT_LSR, + ARM64_SFT_ASR = AArch64_SFT_ASR, + ARM64_SFT_ROR = AArch64_SFT_ROR, +} arm64_shifter; + +typedef enum { + ARM64_EXT_INVALID = AArch64_EXT_INVALID, + ARM64_EXT_UXTB = AArch64_EXT_UXTB, + ARM64_EXT_UXTH = AArch64_EXT_UXTH, + ARM64_EXT_UXTW = AArch64_EXT_UXTW, + ARM64_EXT_UXTX = AArch64_EXT_UXTX, + ARM64_EXT_SXTB = AArch64_EXT_SXTB, + ARM64_EXT_SXTH = AArch64_EXT_SXTH, + ARM64_EXT_SXTW = AArch64_EXT_SXTW, + ARM64_EXT_SXTX = AArch64_EXT_SXTX, +} arm64_extender; + +typedef enum { + ARM64Layout_Invalid = AArch64Layout_Invalid, + ARM64Layout_VL_B = AArch64Layout_VL_B, + ARM64Layout_VL_H = AArch64Layout_VL_H, + ARM64Layout_VL_S = AArch64Layout_VL_S, + ARM64Layout_VL_D = AArch64Layout_VL_D, + ARM64Layout_VL_Q = AArch64Layout_VL_Q, + + ARM64Layout_VL_4B = AArch64Layout_VL_4B, + ARM64Layout_VL_2H = AArch64Layout_VL_2H, + ARM64Layout_VL_1S = AArch64Layout_VL_1S, + + ARM64Layout_VL_8B = AArch64Layout_VL_8B, + ARM64Layout_VL_4H = AArch64Layout_VL_4H, + ARM64Layout_VL_2S = AArch64Layout_VL_2S, + ARM64Layout_VL_1D = AArch64Layout_VL_1D, + + ARM64Layout_VL_16B = AArch64Layout_VL_16B, + ARM64Layout_VL_8H = AArch64Layout_VL_8H, + ARM64Layout_VL_4S = AArch64Layout_VL_4S, + ARM64Layout_VL_2D = AArch64Layout_VL_2D, + ARM64Layout_VL_1Q = AArch64Layout_VL_1Q, + + ARM64Layout_VL_64B = AArch64Layout_VL_64B, + ARM64Layout_VL_32H = AArch64Layout_VL_32H, + ARM64Layout_VL_16S = AArch64Layout_VL_16S, + ARM64Layout_VL_8D = AArch64Layout_VL_8D, + + ARM64Layout_VL_Complete = AArch64Layout_VL_Complete, +} ARM64Layout_VectorLayout; + + +typedef enum { + ARM64CC_EQ = AArch64CC_EQ, + ARM64CC_NE = AArch64CC_NE, + ARM64CC_HS = AArch64CC_HS, + ARM64CC_LO = AArch64CC_LO, + ARM64CC_MI = AArch64CC_MI, + ARM64CC_PL = AArch64CC_PL, + ARM64CC_VS = AArch64CC_VS, + ARM64CC_VC = AArch64CC_VC, + ARM64CC_HI = AArch64CC_HI, + ARM64CC_LS = AArch64CC_LS, + ARM64CC_GE = AArch64CC_GE, + ARM64CC_LT = AArch64CC_LT, + ARM64CC_GT = AArch64CC_GT, + ARM64CC_LE = AArch64CC_LE, + ARM64CC_AL = AArch64CC_AL, + ARM64CC_NV = AArch64CC_NV, + ARM64CC_Invalid = AArch64CC_Invalid, + + ARM64CC_ANY_ACTIVE = AArch64CC_ANY_ACTIVE, + ARM64CC_FIRST_ACTIVE = AArch64CC_FIRST_ACTIVE, + ARM64CC_LAST_ACTIVE = AArch64CC_LAST_ACTIVE, + ARM64CC_NONE_ACTIVE = AArch64CC_NONE_ACTIVE, +} ARM64CC_CondCode; + +inline static const char *ARM64CC_getCondCodeName(ARM64CC_CondCode Code) +{ + switch (Code) { + default: + assert(0 && "Unknown condition code"); + case ARM64CC_EQ: + return "eq"; + case ARM64CC_NE: + return "ne"; + case ARM64CC_HS: + return "hs"; + case ARM64CC_LO: + return "lo"; + case ARM64CC_MI: + return "mi"; + case ARM64CC_PL: + return "pl"; + case ARM64CC_VS: + return "vs"; + case ARM64CC_VC: + return "vc"; + case ARM64CC_HI: + return "hi"; + case ARM64CC_LS: + return "ls"; + case ARM64CC_GE: + return "ge"; + case ARM64CC_LT: + return "lt"; + case ARM64CC_GT: + return "gt"; + case ARM64CC_LE: + return "le"; + case ARM64CC_AL: + return "al"; + case ARM64CC_NV: + return "nv"; + } +} + +inline static ARM64CC_CondCode ARM64CC_getInvertedCondCode(ARM64CC_CondCode Code) +{ + + return (ARM64CC_CondCode)((unsigned)(Code) ^ 0x1); +} + +inline static unsigned ARM64CC_getNZCVToSatisfyCondCode(ARM64CC_CondCode Code) +{ + enum { N = 8, Z = 4, C = 2, V = 1 }; + switch (Code) { + default: + assert(0 && "Unknown condition code"); + case ARM64CC_EQ: + return Z; // Z == 1 + case ARM64CC_NE: + return 0; // Z == 0 + case ARM64CC_HS: + return C; // C == 1 + case ARM64CC_LO: + return 0; // C == 0 + case ARM64CC_MI: + return N; // N == 1 + case ARM64CC_PL: + return 0; // N == 0 + case ARM64CC_VS: + return V; // V == 1 + case ARM64CC_VC: + return 0; // V == 0 + case ARM64CC_HI: + return C; // C == 1 && Z == 0 + case ARM64CC_LS: + return 0; // C == 0 || Z == 1 + case ARM64CC_GE: + return 0; // N == V + case ARM64CC_LT: + return N; // N != V + case ARM64CC_GT: + return 0; // Z == 0 && N == V + case ARM64CC_LE: + return Z; // Z == 1 || N != V + } +} + +inline static bool ARM64CC_isReflexive(ARM64CC_CondCode Code) +{ + switch (Code) { + case ARM64CC_EQ: + case ARM64CC_HS: + case ARM64CC_PL: + case ARM64CC_LS: + case ARM64CC_GE: + case ARM64CC_LE: + case ARM64CC_AL: + case ARM64CC_NV: + return true; + default: + return false; + } +} + +inline static bool ARM64CC_isIrreflexive(ARM64CC_CondCode Code) +{ + switch (Code) { + case ARM64CC_NE: + case ARM64CC_LO: + case ARM64CC_MI: + case ARM64CC_HI: + case ARM64CC_LT: + case ARM64CC_GT: + return true; + default: + return false; + } +} + + +typedef enum { + + ARM64_TLBI_ALLE1 = AArch64_TLBI_ALLE1, + ARM64_TLBI_ALLE1IS = AArch64_TLBI_ALLE1IS, + ARM64_TLBI_ALLE1ISNXS = AArch64_TLBI_ALLE1ISNXS, + ARM64_TLBI_ALLE1NXS = AArch64_TLBI_ALLE1NXS, + ARM64_TLBI_ALLE1OS = AArch64_TLBI_ALLE1OS, + ARM64_TLBI_ALLE1OSNXS = AArch64_TLBI_ALLE1OSNXS, + ARM64_TLBI_ALLE2 = AArch64_TLBI_ALLE2, + ARM64_TLBI_ALLE2IS = AArch64_TLBI_ALLE2IS, + ARM64_TLBI_ALLE2ISNXS = AArch64_TLBI_ALLE2ISNXS, + ARM64_TLBI_ALLE2NXS = AArch64_TLBI_ALLE2NXS, + ARM64_TLBI_ALLE2OS = AArch64_TLBI_ALLE2OS, + ARM64_TLBI_ALLE2OSNXS = AArch64_TLBI_ALLE2OSNXS, + ARM64_TLBI_ALLE3 = AArch64_TLBI_ALLE3, + ARM64_TLBI_ALLE3IS = AArch64_TLBI_ALLE3IS, + ARM64_TLBI_ALLE3ISNXS = AArch64_TLBI_ALLE3ISNXS, + ARM64_TLBI_ALLE3NXS = AArch64_TLBI_ALLE3NXS, + ARM64_TLBI_ALLE3OS = AArch64_TLBI_ALLE3OS, + ARM64_TLBI_ALLE3OSNXS = AArch64_TLBI_ALLE3OSNXS, + ARM64_TLBI_ASIDE1 = AArch64_TLBI_ASIDE1, + ARM64_TLBI_ASIDE1IS = AArch64_TLBI_ASIDE1IS, + ARM64_TLBI_ASIDE1ISNXS = AArch64_TLBI_ASIDE1ISNXS, + ARM64_TLBI_ASIDE1NXS = AArch64_TLBI_ASIDE1NXS, + ARM64_TLBI_ASIDE1OS = AArch64_TLBI_ASIDE1OS, + ARM64_TLBI_ASIDE1OSNXS = AArch64_TLBI_ASIDE1OSNXS, + ARM64_TLBI_IPAS2E1 = AArch64_TLBI_IPAS2E1, + ARM64_TLBI_IPAS2E1IS = AArch64_TLBI_IPAS2E1IS, + ARM64_TLBI_IPAS2E1ISNXS = AArch64_TLBI_IPAS2E1ISNXS, + ARM64_TLBI_IPAS2E1NXS = AArch64_TLBI_IPAS2E1NXS, + ARM64_TLBI_IPAS2E1OS = AArch64_TLBI_IPAS2E1OS, + ARM64_TLBI_IPAS2E1OSNXS = AArch64_TLBI_IPAS2E1OSNXS, + ARM64_TLBI_IPAS2LE1 = AArch64_TLBI_IPAS2LE1, + ARM64_TLBI_IPAS2LE1IS = AArch64_TLBI_IPAS2LE1IS, + ARM64_TLBI_IPAS2LE1ISNXS = AArch64_TLBI_IPAS2LE1ISNXS, + ARM64_TLBI_IPAS2LE1NXS = AArch64_TLBI_IPAS2LE1NXS, + ARM64_TLBI_IPAS2LE1OS = AArch64_TLBI_IPAS2LE1OS, + ARM64_TLBI_IPAS2LE1OSNXS = AArch64_TLBI_IPAS2LE1OSNXS, + ARM64_TLBI_PAALL = AArch64_TLBI_PAALL, + ARM64_TLBI_PAALLNXS = AArch64_TLBI_PAALLNXS, + ARM64_TLBI_PAALLOS = AArch64_TLBI_PAALLOS, + ARM64_TLBI_PAALLOSNXS = AArch64_TLBI_PAALLOSNXS, + ARM64_TLBI_RIPAS2E1 = AArch64_TLBI_RIPAS2E1, + ARM64_TLBI_RIPAS2E1IS = AArch64_TLBI_RIPAS2E1IS, + ARM64_TLBI_RIPAS2E1ISNXS = AArch64_TLBI_RIPAS2E1ISNXS, + ARM64_TLBI_RIPAS2E1NXS = AArch64_TLBI_RIPAS2E1NXS, + ARM64_TLBI_RIPAS2E1OS = AArch64_TLBI_RIPAS2E1OS, + ARM64_TLBI_RIPAS2E1OSNXS = AArch64_TLBI_RIPAS2E1OSNXS, + ARM64_TLBI_RIPAS2LE1 = AArch64_TLBI_RIPAS2LE1, + ARM64_TLBI_RIPAS2LE1IS = AArch64_TLBI_RIPAS2LE1IS, + ARM64_TLBI_RIPAS2LE1ISNXS = AArch64_TLBI_RIPAS2LE1ISNXS, + ARM64_TLBI_RIPAS2LE1NXS = AArch64_TLBI_RIPAS2LE1NXS, + ARM64_TLBI_RIPAS2LE1OS = AArch64_TLBI_RIPAS2LE1OS, + ARM64_TLBI_RIPAS2LE1OSNXS = AArch64_TLBI_RIPAS2LE1OSNXS, + ARM64_TLBI_RPALOS = AArch64_TLBI_RPALOS, + ARM64_TLBI_RPALOSNXS = AArch64_TLBI_RPALOSNXS, + ARM64_TLBI_RPAOS = AArch64_TLBI_RPAOS, + ARM64_TLBI_RPAOSNXS = AArch64_TLBI_RPAOSNXS, + ARM64_TLBI_RVAAE1 = AArch64_TLBI_RVAAE1, + ARM64_TLBI_RVAAE1IS = AArch64_TLBI_RVAAE1IS, + ARM64_TLBI_RVAAE1ISNXS = AArch64_TLBI_RVAAE1ISNXS, + ARM64_TLBI_RVAAE1NXS = AArch64_TLBI_RVAAE1NXS, + ARM64_TLBI_RVAAE1OS = AArch64_TLBI_RVAAE1OS, + ARM64_TLBI_RVAAE1OSNXS = AArch64_TLBI_RVAAE1OSNXS, + ARM64_TLBI_RVAALE1 = AArch64_TLBI_RVAALE1, + ARM64_TLBI_RVAALE1IS = AArch64_TLBI_RVAALE1IS, + ARM64_TLBI_RVAALE1ISNXS = AArch64_TLBI_RVAALE1ISNXS, + ARM64_TLBI_RVAALE1NXS = AArch64_TLBI_RVAALE1NXS, + ARM64_TLBI_RVAALE1OS = AArch64_TLBI_RVAALE1OS, + ARM64_TLBI_RVAALE1OSNXS = AArch64_TLBI_RVAALE1OSNXS, + ARM64_TLBI_RVAE1 = AArch64_TLBI_RVAE1, + ARM64_TLBI_RVAE1IS = AArch64_TLBI_RVAE1IS, + ARM64_TLBI_RVAE1ISNXS = AArch64_TLBI_RVAE1ISNXS, + ARM64_TLBI_RVAE1NXS = AArch64_TLBI_RVAE1NXS, + ARM64_TLBI_RVAE1OS = AArch64_TLBI_RVAE1OS, + ARM64_TLBI_RVAE1OSNXS = AArch64_TLBI_RVAE1OSNXS, + ARM64_TLBI_RVAE2 = AArch64_TLBI_RVAE2, + ARM64_TLBI_RVAE2IS = AArch64_TLBI_RVAE2IS, + ARM64_TLBI_RVAE2ISNXS = AArch64_TLBI_RVAE2ISNXS, + ARM64_TLBI_RVAE2NXS = AArch64_TLBI_RVAE2NXS, + ARM64_TLBI_RVAE2OS = AArch64_TLBI_RVAE2OS, + ARM64_TLBI_RVAE2OSNXS = AArch64_TLBI_RVAE2OSNXS, + ARM64_TLBI_RVAE3 = AArch64_TLBI_RVAE3, + ARM64_TLBI_RVAE3IS = AArch64_TLBI_RVAE3IS, + ARM64_TLBI_RVAE3ISNXS = AArch64_TLBI_RVAE3ISNXS, + ARM64_TLBI_RVAE3NXS = AArch64_TLBI_RVAE3NXS, + ARM64_TLBI_RVAE3OS = AArch64_TLBI_RVAE3OS, + ARM64_TLBI_RVAE3OSNXS = AArch64_TLBI_RVAE3OSNXS, + ARM64_TLBI_RVALE1 = AArch64_TLBI_RVALE1, + ARM64_TLBI_RVALE1IS = AArch64_TLBI_RVALE1IS, + ARM64_TLBI_RVALE1ISNXS = AArch64_TLBI_RVALE1ISNXS, + ARM64_TLBI_RVALE1NXS = AArch64_TLBI_RVALE1NXS, + ARM64_TLBI_RVALE1OS = AArch64_TLBI_RVALE1OS, + ARM64_TLBI_RVALE1OSNXS = AArch64_TLBI_RVALE1OSNXS, + ARM64_TLBI_RVALE2 = AArch64_TLBI_RVALE2, + ARM64_TLBI_RVALE2IS = AArch64_TLBI_RVALE2IS, + ARM64_TLBI_RVALE2ISNXS = AArch64_TLBI_RVALE2ISNXS, + ARM64_TLBI_RVALE2NXS = AArch64_TLBI_RVALE2NXS, + ARM64_TLBI_RVALE2OS = AArch64_TLBI_RVALE2OS, + ARM64_TLBI_RVALE2OSNXS = AArch64_TLBI_RVALE2OSNXS, + ARM64_TLBI_RVALE3 = AArch64_TLBI_RVALE3, + ARM64_TLBI_RVALE3IS = AArch64_TLBI_RVALE3IS, + ARM64_TLBI_RVALE3ISNXS = AArch64_TLBI_RVALE3ISNXS, + ARM64_TLBI_RVALE3NXS = AArch64_TLBI_RVALE3NXS, + ARM64_TLBI_RVALE3OS = AArch64_TLBI_RVALE3OS, + ARM64_TLBI_RVALE3OSNXS = AArch64_TLBI_RVALE3OSNXS, + ARM64_TLBI_VAAE1 = AArch64_TLBI_VAAE1, + ARM64_TLBI_VAAE1IS = AArch64_TLBI_VAAE1IS, + ARM64_TLBI_VAAE1ISNXS = AArch64_TLBI_VAAE1ISNXS, + ARM64_TLBI_VAAE1NXS = AArch64_TLBI_VAAE1NXS, + ARM64_TLBI_VAAE1OS = AArch64_TLBI_VAAE1OS, + ARM64_TLBI_VAAE1OSNXS = AArch64_TLBI_VAAE1OSNXS, + ARM64_TLBI_VAALE1 = AArch64_TLBI_VAALE1, + ARM64_TLBI_VAALE1IS = AArch64_TLBI_VAALE1IS, + ARM64_TLBI_VAALE1ISNXS = AArch64_TLBI_VAALE1ISNXS, + ARM64_TLBI_VAALE1NXS = AArch64_TLBI_VAALE1NXS, + ARM64_TLBI_VAALE1OS = AArch64_TLBI_VAALE1OS, + ARM64_TLBI_VAALE1OSNXS = AArch64_TLBI_VAALE1OSNXS, + ARM64_TLBI_VAE1 = AArch64_TLBI_VAE1, + ARM64_TLBI_VAE1IS = AArch64_TLBI_VAE1IS, + ARM64_TLBI_VAE1ISNXS = AArch64_TLBI_VAE1ISNXS, + ARM64_TLBI_VAE1NXS = AArch64_TLBI_VAE1NXS, + ARM64_TLBI_VAE1OS = AArch64_TLBI_VAE1OS, + ARM64_TLBI_VAE1OSNXS = AArch64_TLBI_VAE1OSNXS, + ARM64_TLBI_VAE2 = AArch64_TLBI_VAE2, + ARM64_TLBI_VAE2IS = AArch64_TLBI_VAE2IS, + ARM64_TLBI_VAE2ISNXS = AArch64_TLBI_VAE2ISNXS, + ARM64_TLBI_VAE2NXS = AArch64_TLBI_VAE2NXS, + ARM64_TLBI_VAE2OS = AArch64_TLBI_VAE2OS, + ARM64_TLBI_VAE2OSNXS = AArch64_TLBI_VAE2OSNXS, + ARM64_TLBI_VAE3 = AArch64_TLBI_VAE3, + ARM64_TLBI_VAE3IS = AArch64_TLBI_VAE3IS, + ARM64_TLBI_VAE3ISNXS = AArch64_TLBI_VAE3ISNXS, + ARM64_TLBI_VAE3NXS = AArch64_TLBI_VAE3NXS, + ARM64_TLBI_VAE3OS = AArch64_TLBI_VAE3OS, + ARM64_TLBI_VAE3OSNXS = AArch64_TLBI_VAE3OSNXS, + ARM64_TLBI_VALE1 = AArch64_TLBI_VALE1, + ARM64_TLBI_VALE1IS = AArch64_TLBI_VALE1IS, + ARM64_TLBI_VALE1ISNXS = AArch64_TLBI_VALE1ISNXS, + ARM64_TLBI_VALE1NXS = AArch64_TLBI_VALE1NXS, + ARM64_TLBI_VALE1OS = AArch64_TLBI_VALE1OS, + ARM64_TLBI_VALE1OSNXS = AArch64_TLBI_VALE1OSNXS, + ARM64_TLBI_VALE2 = AArch64_TLBI_VALE2, + ARM64_TLBI_VALE2IS = AArch64_TLBI_VALE2IS, + ARM64_TLBI_VALE2ISNXS = AArch64_TLBI_VALE2ISNXS, + ARM64_TLBI_VALE2NXS = AArch64_TLBI_VALE2NXS, + ARM64_TLBI_VALE2OS = AArch64_TLBI_VALE2OS, + ARM64_TLBI_VALE2OSNXS = AArch64_TLBI_VALE2OSNXS, + ARM64_TLBI_VALE3 = AArch64_TLBI_VALE3, + ARM64_TLBI_VALE3IS = AArch64_TLBI_VALE3IS, + ARM64_TLBI_VALE3ISNXS = AArch64_TLBI_VALE3ISNXS, + ARM64_TLBI_VALE3NXS = AArch64_TLBI_VALE3NXS, + ARM64_TLBI_VALE3OS = AArch64_TLBI_VALE3OS, + ARM64_TLBI_VALE3OSNXS = AArch64_TLBI_VALE3OSNXS, + ARM64_TLBI_VMALLE1 = AArch64_TLBI_VMALLE1, + ARM64_TLBI_VMALLE1IS = AArch64_TLBI_VMALLE1IS, + ARM64_TLBI_VMALLE1ISNXS = AArch64_TLBI_VMALLE1ISNXS, + ARM64_TLBI_VMALLE1NXS = AArch64_TLBI_VMALLE1NXS, + ARM64_TLBI_VMALLE1OS = AArch64_TLBI_VMALLE1OS, + ARM64_TLBI_VMALLE1OSNXS = AArch64_TLBI_VMALLE1OSNXS, + ARM64_TLBI_VMALLS12E1 = AArch64_TLBI_VMALLS12E1, + ARM64_TLBI_VMALLS12E1IS = AArch64_TLBI_VMALLS12E1IS, + ARM64_TLBI_VMALLS12E1ISNXS = AArch64_TLBI_VMALLS12E1ISNXS, + ARM64_TLBI_VMALLS12E1NXS = AArch64_TLBI_VMALLS12E1NXS, + ARM64_TLBI_VMALLS12E1OS = AArch64_TLBI_VMALLS12E1OS, + ARM64_TLBI_VMALLS12E1OSNXS = AArch64_TLBI_VMALLS12E1OSNXS, + + ARM64_TLBI_ENDING = AArch64_TLBI_ENDING, +} arm64_tlbi; + +typedef enum { + + ARM64_AT_S12E0R = AArch64_AT_S12E0R, + ARM64_AT_S12E0W = AArch64_AT_S12E0W, + ARM64_AT_S12E1R = AArch64_AT_S12E1R, + ARM64_AT_S12E1W = AArch64_AT_S12E1W, + ARM64_AT_S1E0R = AArch64_AT_S1E0R, + ARM64_AT_S1E0W = AArch64_AT_S1E0W, + ARM64_AT_S1E1R = AArch64_AT_S1E1R, + ARM64_AT_S1E1RP = AArch64_AT_S1E1RP, + ARM64_AT_S1E1W = AArch64_AT_S1E1W, + ARM64_AT_S1E1WP = AArch64_AT_S1E1WP, + ARM64_AT_S1E2R = AArch64_AT_S1E2R, + ARM64_AT_S1E2W = AArch64_AT_S1E2W, + ARM64_AT_S1E3R = AArch64_AT_S1E3R, + ARM64_AT_S1E3W = AArch64_AT_S1E3W, + + ARM64_AT_ENDING = AArch64_AT_ENDING, +} arm64_at; + +typedef enum { + + ARM64_BTI_C = AArch64_BTI_C, + ARM64_BTI_J = AArch64_BTI_J, + ARM64_BTI_JC = AArch64_BTI_JC, + + ARM64_BTI_ENDING = AArch64_BTI_ENDING, +} arm64_bti; + +typedef enum { + + ARM64_DB_ISH = AArch64_DB_ISH, + ARM64_DB_ISHLD = AArch64_DB_ISHLD, + ARM64_DB_ISHST = AArch64_DB_ISHST, + ARM64_DB_LD = AArch64_DB_LD, + ARM64_DB_NSH = AArch64_DB_NSH, + ARM64_DB_NSHLD = AArch64_DB_NSHLD, + ARM64_DB_NSHST = AArch64_DB_NSHST, + ARM64_DB_OSH = AArch64_DB_OSH, + ARM64_DB_OSHLD = AArch64_DB_OSHLD, + ARM64_DB_OSHST = AArch64_DB_OSHST, + ARM64_DB_ST = AArch64_DB_ST, + ARM64_DB_SY = AArch64_DB_SY, + + ARM64_DB_ENDING = AArch64_DB_ENDING, +} arm64_db; + +typedef enum { + + ARM64_DBNXS_ISHNXS = AArch64_DBNXS_ISHNXS, + ARM64_DBNXS_NSHNXS = AArch64_DBNXS_NSHNXS, + ARM64_DBNXS_OSHNXS = AArch64_DBNXS_OSHNXS, + ARM64_DBNXS_SYNXS = AArch64_DBNXS_SYNXS, + + ARM64_DBNXS_ENDING = AArch64_DBNXS_ENDING, +} arm64_dbnxs; + +typedef enum { + + ARM64_DC_CGDSW = AArch64_DC_CGDSW, + ARM64_DC_CGDVAC = AArch64_DC_CGDVAC, + ARM64_DC_CGDVADP = AArch64_DC_CGDVADP, + ARM64_DC_CGDVAP = AArch64_DC_CGDVAP, + ARM64_DC_CGSW = AArch64_DC_CGSW, + ARM64_DC_CGVAC = AArch64_DC_CGVAC, + ARM64_DC_CGVADP = AArch64_DC_CGVADP, + ARM64_DC_CGVAP = AArch64_DC_CGVAP, + ARM64_DC_CIGDPAE = AArch64_DC_CIGDPAE, + ARM64_DC_CIGDSW = AArch64_DC_CIGDSW, + ARM64_DC_CIGDVAC = AArch64_DC_CIGDVAC, + ARM64_DC_CIGSW = AArch64_DC_CIGSW, + ARM64_DC_CIGVAC = AArch64_DC_CIGVAC, + ARM64_DC_CIPAE = AArch64_DC_CIPAE, + ARM64_DC_CISW = AArch64_DC_CISW, + ARM64_DC_CIVAC = AArch64_DC_CIVAC, + ARM64_DC_CSW = AArch64_DC_CSW, + ARM64_DC_CVAC = AArch64_DC_CVAC, + ARM64_DC_CVADP = AArch64_DC_CVADP, + ARM64_DC_CVAP = AArch64_DC_CVAP, + ARM64_DC_CVAU = AArch64_DC_CVAU, + ARM64_DC_GVA = AArch64_DC_GVA, + ARM64_DC_GZVA = AArch64_DC_GZVA, + ARM64_DC_IGDSW = AArch64_DC_IGDSW, + ARM64_DC_IGDVAC = AArch64_DC_IGDVAC, + ARM64_DC_IGSW = AArch64_DC_IGSW, + ARM64_DC_IGVAC = AArch64_DC_IGVAC, + ARM64_DC_ISW = AArch64_DC_ISW, + ARM64_DC_IVAC = AArch64_DC_IVAC, + ARM64_DC_ZVA = AArch64_DC_ZVA, + + ARM64_DC_ENDING = AArch64_DC_ENDING, +} arm64_dc; + +typedef enum { + + ARM64_EXACTFPIMM_HALF = AArch64_EXACTFPIMM_HALF, + ARM64_EXACTFPIMM_ONE = AArch64_EXACTFPIMM_ONE, + ARM64_EXACTFPIMM_TWO = AArch64_EXACTFPIMM_TWO, + ARM64_EXACTFPIMM_ZERO = AArch64_EXACTFPIMM_ZERO, + + ARM64_EXACTFPIMM_ENDING = AArch64_EXACTFPIMM_ENDING, +} arm64_exactfpimm; + +typedef enum { + + ARM64_IC_IALLU = AArch64_IC_IALLU, + ARM64_IC_IALLUIS = AArch64_IC_IALLUIS, + ARM64_IC_IVAU = AArch64_IC_IVAU, + + ARM64_IC_ENDING = AArch64_IC_ENDING, +} arm64_ic; + +typedef enum { + + ARM64_ISB_SY = AArch64_ISB_SY, + + ARM64_ISB_ENDING = AArch64_ISB_ENDING, +} arm64_isb; + +typedef enum { + + ARM64_PRFM_PLDL1KEEP = AArch64_PRFM_PLDL1KEEP, + ARM64_PRFM_PLDL1STRM = AArch64_PRFM_PLDL1STRM, + ARM64_PRFM_PLDL2KEEP = AArch64_PRFM_PLDL2KEEP, + ARM64_PRFM_PLDL2STRM = AArch64_PRFM_PLDL2STRM, + ARM64_PRFM_PLDL3KEEP = AArch64_PRFM_PLDL3KEEP, + ARM64_PRFM_PLDL3STRM = AArch64_PRFM_PLDL3STRM, + ARM64_PRFM_PLDSLCKEEP = AArch64_PRFM_PLDSLCKEEP, + ARM64_PRFM_PLDSLCSTRM = AArch64_PRFM_PLDSLCSTRM, + ARM64_PRFM_PLIL1KEEP = AArch64_PRFM_PLIL1KEEP, + ARM64_PRFM_PLIL1STRM = AArch64_PRFM_PLIL1STRM, + ARM64_PRFM_PLIL2KEEP = AArch64_PRFM_PLIL2KEEP, + ARM64_PRFM_PLIL2STRM = AArch64_PRFM_PLIL2STRM, + ARM64_PRFM_PLIL3KEEP = AArch64_PRFM_PLIL3KEEP, + ARM64_PRFM_PLIL3STRM = AArch64_PRFM_PLIL3STRM, + ARM64_PRFM_PLISLCKEEP = AArch64_PRFM_PLISLCKEEP, + ARM64_PRFM_PLISLCSTRM = AArch64_PRFM_PLISLCSTRM, + ARM64_PRFM_PSTL1KEEP = AArch64_PRFM_PSTL1KEEP, + ARM64_PRFM_PSTL1STRM = AArch64_PRFM_PSTL1STRM, + ARM64_PRFM_PSTL2KEEP = AArch64_PRFM_PSTL2KEEP, + ARM64_PRFM_PSTL2STRM = AArch64_PRFM_PSTL2STRM, + ARM64_PRFM_PSTL3KEEP = AArch64_PRFM_PSTL3KEEP, + ARM64_PRFM_PSTL3STRM = AArch64_PRFM_PSTL3STRM, + ARM64_PRFM_PSTSLCKEEP = AArch64_PRFM_PSTSLCKEEP, + ARM64_PRFM_PSTSLCSTRM = AArch64_PRFM_PSTSLCSTRM, + + ARM64_PRFM_ENDING = AArch64_PRFM_ENDING, +} arm64_prfm; + +typedef enum { + + ARM64_PSB_CSYNC = AArch64_PSB_CSYNC, + + ARM64_PSB_ENDING = AArch64_PSB_ENDING, +} arm64_psb; + +typedef enum { + + ARM64_PSTATEIMM0_1_ALLINT = AArch64_PSTATEIMM0_1_ALLINT, + ARM64_PSTATEIMM0_1_PM = AArch64_PSTATEIMM0_1_PM, + + ARM64_PSTATEIMM0_1_ENDING = AArch64_PSTATEIMM0_1_ENDING, +} arm64_pstateimm0_1; + +typedef enum { + + ARM64_PSTATEIMM0_15_DAIFCLR = AArch64_PSTATEIMM0_15_DAIFCLR, + ARM64_PSTATEIMM0_15_DAIFSET = AArch64_PSTATEIMM0_15_DAIFSET, + ARM64_PSTATEIMM0_15_DIT = AArch64_PSTATEIMM0_15_DIT, + ARM64_PSTATEIMM0_15_PAN = AArch64_PSTATEIMM0_15_PAN, + ARM64_PSTATEIMM0_15_SPSEL = AArch64_PSTATEIMM0_15_SPSEL, + ARM64_PSTATEIMM0_15_SSBS = AArch64_PSTATEIMM0_15_SSBS, + ARM64_PSTATEIMM0_15_TCO = AArch64_PSTATEIMM0_15_TCO, + ARM64_PSTATEIMM0_15_UAO = AArch64_PSTATEIMM0_15_UAO, + + ARM64_PSTATEIMM0_15_ENDING = AArch64_PSTATEIMM0_15_ENDING, +} arm64_pstateimm0_15; + +typedef enum { + + ARM64_RPRFM_PLDKEEP = AArch64_RPRFM_PLDKEEP, + ARM64_RPRFM_PLDSTRM = AArch64_RPRFM_PLDSTRM, + ARM64_RPRFM_PSTKEEP = AArch64_RPRFM_PSTKEEP, + ARM64_RPRFM_PSTSTRM = AArch64_RPRFM_PSTSTRM, + + ARM64_RPRFM_ENDING = AArch64_RPRFM_ENDING, +} arm64_rprfm; + +typedef enum { + + ARM64_SVCR_SVCRSM = AArch64_SVCR_SVCRSM, + ARM64_SVCR_SVCRSMZA = AArch64_SVCR_SVCRSMZA, + ARM64_SVCR_SVCRZA = AArch64_SVCR_SVCRZA, + + ARM64_SVCR_ENDING = AArch64_SVCR_ENDING, +} arm64_svcr; + +typedef enum { + + ARM64_SVEPREDPAT_ALL = AArch64_SVEPREDPAT_ALL, + ARM64_SVEPREDPAT_MUL3 = AArch64_SVEPREDPAT_MUL3, + ARM64_SVEPREDPAT_MUL4 = AArch64_SVEPREDPAT_MUL4, + ARM64_SVEPREDPAT_POW2 = AArch64_SVEPREDPAT_POW2, + ARM64_SVEPREDPAT_VL1 = AArch64_SVEPREDPAT_VL1, + ARM64_SVEPREDPAT_VL128 = AArch64_SVEPREDPAT_VL128, + ARM64_SVEPREDPAT_VL16 = AArch64_SVEPREDPAT_VL16, + ARM64_SVEPREDPAT_VL2 = AArch64_SVEPREDPAT_VL2, + ARM64_SVEPREDPAT_VL256 = AArch64_SVEPREDPAT_VL256, + ARM64_SVEPREDPAT_VL3 = AArch64_SVEPREDPAT_VL3, + ARM64_SVEPREDPAT_VL32 = AArch64_SVEPREDPAT_VL32, + ARM64_SVEPREDPAT_VL4 = AArch64_SVEPREDPAT_VL4, + ARM64_SVEPREDPAT_VL5 = AArch64_SVEPREDPAT_VL5, + ARM64_SVEPREDPAT_VL6 = AArch64_SVEPREDPAT_VL6, + ARM64_SVEPREDPAT_VL64 = AArch64_SVEPREDPAT_VL64, + ARM64_SVEPREDPAT_VL7 = AArch64_SVEPREDPAT_VL7, + ARM64_SVEPREDPAT_VL8 = AArch64_SVEPREDPAT_VL8, + + ARM64_SVEPREDPAT_ENDING = AArch64_SVEPREDPAT_ENDING, +} arm64_svepredpat; + +typedef enum { + + ARM64_SVEPRFM_PLDL1KEEP = AArch64_SVEPRFM_PLDL1KEEP, + ARM64_SVEPRFM_PLDL1STRM = AArch64_SVEPRFM_PLDL1STRM, + ARM64_SVEPRFM_PLDL2KEEP = AArch64_SVEPRFM_PLDL2KEEP, + ARM64_SVEPRFM_PLDL2STRM = AArch64_SVEPRFM_PLDL2STRM, + ARM64_SVEPRFM_PLDL3KEEP = AArch64_SVEPRFM_PLDL3KEEP, + ARM64_SVEPRFM_PLDL3STRM = AArch64_SVEPRFM_PLDL3STRM, + ARM64_SVEPRFM_PSTL1KEEP = AArch64_SVEPRFM_PSTL1KEEP, + ARM64_SVEPRFM_PSTL1STRM = AArch64_SVEPRFM_PSTL1STRM, + ARM64_SVEPRFM_PSTL2KEEP = AArch64_SVEPRFM_PSTL2KEEP, + ARM64_SVEPRFM_PSTL2STRM = AArch64_SVEPRFM_PSTL2STRM, + ARM64_SVEPRFM_PSTL3KEEP = AArch64_SVEPRFM_PSTL3KEEP, + ARM64_SVEPRFM_PSTL3STRM = AArch64_SVEPRFM_PSTL3STRM, + + ARM64_SVEPRFM_ENDING = AArch64_SVEPRFM_ENDING, +} arm64_sveprfm; + +typedef enum { + + ARM64_SVEVECLENSPECIFIER_VLX2 = AArch64_SVEVECLENSPECIFIER_VLX2, + ARM64_SVEVECLENSPECIFIER_VLX4 = AArch64_SVEVECLENSPECIFIER_VLX4, + + ARM64_SVEVECLENSPECIFIER_ENDING = AArch64_SVEVECLENSPECIFIER_ENDING, +} arm64_sveveclenspecifier; + +typedef enum { + + ARM64_SYSREG_ACCDATA_EL1 = AArch64_SYSREG_ACCDATA_EL1, + ARM64_SYSREG_ACTLR_EL1 = AArch64_SYSREG_ACTLR_EL1, + ARM64_SYSREG_ACTLR_EL2 = AArch64_SYSREG_ACTLR_EL2, + ARM64_SYSREG_ACTLR_EL3 = AArch64_SYSREG_ACTLR_EL3, + ARM64_SYSREG_AFSR0_EL1 = AArch64_SYSREG_AFSR0_EL1, + ARM64_SYSREG_AFSR0_EL12 = AArch64_SYSREG_AFSR0_EL12, + ARM64_SYSREG_AFSR0_EL2 = AArch64_SYSREG_AFSR0_EL2, + ARM64_SYSREG_AFSR0_EL3 = AArch64_SYSREG_AFSR0_EL3, + ARM64_SYSREG_AFSR1_EL1 = AArch64_SYSREG_AFSR1_EL1, + ARM64_SYSREG_AFSR1_EL12 = AArch64_SYSREG_AFSR1_EL12, + ARM64_SYSREG_AFSR1_EL2 = AArch64_SYSREG_AFSR1_EL2, + ARM64_SYSREG_AFSR1_EL3 = AArch64_SYSREG_AFSR1_EL3, + ARM64_SYSREG_AIDR_EL1 = AArch64_SYSREG_AIDR_EL1, + ARM64_SYSREG_ALLINT = AArch64_SYSREG_ALLINT, + ARM64_SYSREG_AMAIR2_EL1 = AArch64_SYSREG_AMAIR2_EL1, + ARM64_SYSREG_AMAIR2_EL12 = AArch64_SYSREG_AMAIR2_EL12, + ARM64_SYSREG_AMAIR2_EL2 = AArch64_SYSREG_AMAIR2_EL2, + ARM64_SYSREG_AMAIR2_EL3 = AArch64_SYSREG_AMAIR2_EL3, + ARM64_SYSREG_AMAIR_EL1 = AArch64_SYSREG_AMAIR_EL1, + ARM64_SYSREG_AMAIR_EL12 = AArch64_SYSREG_AMAIR_EL12, + ARM64_SYSREG_AMAIR_EL2 = AArch64_SYSREG_AMAIR_EL2, + ARM64_SYSREG_AMAIR_EL3 = AArch64_SYSREG_AMAIR_EL3, + ARM64_SYSREG_AMCFGR_EL0 = AArch64_SYSREG_AMCFGR_EL0, + ARM64_SYSREG_AMCG1IDR_EL0 = AArch64_SYSREG_AMCG1IDR_EL0, + ARM64_SYSREG_AMCGCR_EL0 = AArch64_SYSREG_AMCGCR_EL0, + ARM64_SYSREG_AMCNTENCLR0_EL0 = AArch64_SYSREG_AMCNTENCLR0_EL0, + ARM64_SYSREG_AMCNTENCLR1_EL0 = AArch64_SYSREG_AMCNTENCLR1_EL0, + ARM64_SYSREG_AMCNTENSET0_EL0 = AArch64_SYSREG_AMCNTENSET0_EL0, + ARM64_SYSREG_AMCNTENSET1_EL0 = AArch64_SYSREG_AMCNTENSET1_EL0, + ARM64_SYSREG_AMCR_EL0 = AArch64_SYSREG_AMCR_EL0, + ARM64_SYSREG_AMEVCNTR00_EL0 = AArch64_SYSREG_AMEVCNTR00_EL0, + ARM64_SYSREG_AMEVCNTR01_EL0 = AArch64_SYSREG_AMEVCNTR01_EL0, + ARM64_SYSREG_AMEVCNTR02_EL0 = AArch64_SYSREG_AMEVCNTR02_EL0, + ARM64_SYSREG_AMEVCNTR03_EL0 = AArch64_SYSREG_AMEVCNTR03_EL0, + ARM64_SYSREG_AMEVCNTR10_EL0 = AArch64_SYSREG_AMEVCNTR10_EL0, + ARM64_SYSREG_AMEVCNTR110_EL0 = AArch64_SYSREG_AMEVCNTR110_EL0, + ARM64_SYSREG_AMEVCNTR111_EL0 = AArch64_SYSREG_AMEVCNTR111_EL0, + ARM64_SYSREG_AMEVCNTR112_EL0 = AArch64_SYSREG_AMEVCNTR112_EL0, + ARM64_SYSREG_AMEVCNTR113_EL0 = AArch64_SYSREG_AMEVCNTR113_EL0, + ARM64_SYSREG_AMEVCNTR114_EL0 = AArch64_SYSREG_AMEVCNTR114_EL0, + ARM64_SYSREG_AMEVCNTR115_EL0 = AArch64_SYSREG_AMEVCNTR115_EL0, + ARM64_SYSREG_AMEVCNTR11_EL0 = AArch64_SYSREG_AMEVCNTR11_EL0, + ARM64_SYSREG_AMEVCNTR12_EL0 = AArch64_SYSREG_AMEVCNTR12_EL0, + ARM64_SYSREG_AMEVCNTR13_EL0 = AArch64_SYSREG_AMEVCNTR13_EL0, + ARM64_SYSREG_AMEVCNTR14_EL0 = AArch64_SYSREG_AMEVCNTR14_EL0, + ARM64_SYSREG_AMEVCNTR15_EL0 = AArch64_SYSREG_AMEVCNTR15_EL0, + ARM64_SYSREG_AMEVCNTR16_EL0 = AArch64_SYSREG_AMEVCNTR16_EL0, + ARM64_SYSREG_AMEVCNTR17_EL0 = AArch64_SYSREG_AMEVCNTR17_EL0, + ARM64_SYSREG_AMEVCNTR18_EL0 = AArch64_SYSREG_AMEVCNTR18_EL0, + ARM64_SYSREG_AMEVCNTR19_EL0 = AArch64_SYSREG_AMEVCNTR19_EL0, + ARM64_SYSREG_AMEVCNTVOFF00_EL2 = AArch64_SYSREG_AMEVCNTVOFF00_EL2, + ARM64_SYSREG_AMEVCNTVOFF010_EL2 = AArch64_SYSREG_AMEVCNTVOFF010_EL2, + ARM64_SYSREG_AMEVCNTVOFF011_EL2 = AArch64_SYSREG_AMEVCNTVOFF011_EL2, + ARM64_SYSREG_AMEVCNTVOFF012_EL2 = AArch64_SYSREG_AMEVCNTVOFF012_EL2, + ARM64_SYSREG_AMEVCNTVOFF013_EL2 = AArch64_SYSREG_AMEVCNTVOFF013_EL2, + ARM64_SYSREG_AMEVCNTVOFF014_EL2 = AArch64_SYSREG_AMEVCNTVOFF014_EL2, + ARM64_SYSREG_AMEVCNTVOFF015_EL2 = AArch64_SYSREG_AMEVCNTVOFF015_EL2, + ARM64_SYSREG_AMEVCNTVOFF01_EL2 = AArch64_SYSREG_AMEVCNTVOFF01_EL2, + ARM64_SYSREG_AMEVCNTVOFF02_EL2 = AArch64_SYSREG_AMEVCNTVOFF02_EL2, + ARM64_SYSREG_AMEVCNTVOFF03_EL2 = AArch64_SYSREG_AMEVCNTVOFF03_EL2, + ARM64_SYSREG_AMEVCNTVOFF04_EL2 = AArch64_SYSREG_AMEVCNTVOFF04_EL2, + ARM64_SYSREG_AMEVCNTVOFF05_EL2 = AArch64_SYSREG_AMEVCNTVOFF05_EL2, + ARM64_SYSREG_AMEVCNTVOFF06_EL2 = AArch64_SYSREG_AMEVCNTVOFF06_EL2, + ARM64_SYSREG_AMEVCNTVOFF07_EL2 = AArch64_SYSREG_AMEVCNTVOFF07_EL2, + ARM64_SYSREG_AMEVCNTVOFF08_EL2 = AArch64_SYSREG_AMEVCNTVOFF08_EL2, + ARM64_SYSREG_AMEVCNTVOFF09_EL2 = AArch64_SYSREG_AMEVCNTVOFF09_EL2, + ARM64_SYSREG_AMEVCNTVOFF10_EL2 = AArch64_SYSREG_AMEVCNTVOFF10_EL2, + ARM64_SYSREG_AMEVCNTVOFF110_EL2 = AArch64_SYSREG_AMEVCNTVOFF110_EL2, + ARM64_SYSREG_AMEVCNTVOFF111_EL2 = AArch64_SYSREG_AMEVCNTVOFF111_EL2, + ARM64_SYSREG_AMEVCNTVOFF112_EL2 = AArch64_SYSREG_AMEVCNTVOFF112_EL2, + ARM64_SYSREG_AMEVCNTVOFF113_EL2 = AArch64_SYSREG_AMEVCNTVOFF113_EL2, + ARM64_SYSREG_AMEVCNTVOFF114_EL2 = AArch64_SYSREG_AMEVCNTVOFF114_EL2, + ARM64_SYSREG_AMEVCNTVOFF115_EL2 = AArch64_SYSREG_AMEVCNTVOFF115_EL2, + ARM64_SYSREG_AMEVCNTVOFF11_EL2 = AArch64_SYSREG_AMEVCNTVOFF11_EL2, + ARM64_SYSREG_AMEVCNTVOFF12_EL2 = AArch64_SYSREG_AMEVCNTVOFF12_EL2, + ARM64_SYSREG_AMEVCNTVOFF13_EL2 = AArch64_SYSREG_AMEVCNTVOFF13_EL2, + ARM64_SYSREG_AMEVCNTVOFF14_EL2 = AArch64_SYSREG_AMEVCNTVOFF14_EL2, + ARM64_SYSREG_AMEVCNTVOFF15_EL2 = AArch64_SYSREG_AMEVCNTVOFF15_EL2, + ARM64_SYSREG_AMEVCNTVOFF16_EL2 = AArch64_SYSREG_AMEVCNTVOFF16_EL2, + ARM64_SYSREG_AMEVCNTVOFF17_EL2 = AArch64_SYSREG_AMEVCNTVOFF17_EL2, + ARM64_SYSREG_AMEVCNTVOFF18_EL2 = AArch64_SYSREG_AMEVCNTVOFF18_EL2, + ARM64_SYSREG_AMEVCNTVOFF19_EL2 = AArch64_SYSREG_AMEVCNTVOFF19_EL2, + ARM64_SYSREG_AMEVTYPER00_EL0 = AArch64_SYSREG_AMEVTYPER00_EL0, + ARM64_SYSREG_AMEVTYPER01_EL0 = AArch64_SYSREG_AMEVTYPER01_EL0, + ARM64_SYSREG_AMEVTYPER02_EL0 = AArch64_SYSREG_AMEVTYPER02_EL0, + ARM64_SYSREG_AMEVTYPER03_EL0 = AArch64_SYSREG_AMEVTYPER03_EL0, + ARM64_SYSREG_AMEVTYPER10_EL0 = AArch64_SYSREG_AMEVTYPER10_EL0, + ARM64_SYSREG_AMEVTYPER110_EL0 = AArch64_SYSREG_AMEVTYPER110_EL0, + ARM64_SYSREG_AMEVTYPER111_EL0 = AArch64_SYSREG_AMEVTYPER111_EL0, + ARM64_SYSREG_AMEVTYPER112_EL0 = AArch64_SYSREG_AMEVTYPER112_EL0, + ARM64_SYSREG_AMEVTYPER113_EL0 = AArch64_SYSREG_AMEVTYPER113_EL0, + ARM64_SYSREG_AMEVTYPER114_EL0 = AArch64_SYSREG_AMEVTYPER114_EL0, + ARM64_SYSREG_AMEVTYPER115_EL0 = AArch64_SYSREG_AMEVTYPER115_EL0, + ARM64_SYSREG_AMEVTYPER11_EL0 = AArch64_SYSREG_AMEVTYPER11_EL0, + ARM64_SYSREG_AMEVTYPER12_EL0 = AArch64_SYSREG_AMEVTYPER12_EL0, + ARM64_SYSREG_AMEVTYPER13_EL0 = AArch64_SYSREG_AMEVTYPER13_EL0, + ARM64_SYSREG_AMEVTYPER14_EL0 = AArch64_SYSREG_AMEVTYPER14_EL0, + ARM64_SYSREG_AMEVTYPER15_EL0 = AArch64_SYSREG_AMEVTYPER15_EL0, + ARM64_SYSREG_AMEVTYPER16_EL0 = AArch64_SYSREG_AMEVTYPER16_EL0, + ARM64_SYSREG_AMEVTYPER17_EL0 = AArch64_SYSREG_AMEVTYPER17_EL0, + ARM64_SYSREG_AMEVTYPER18_EL0 = AArch64_SYSREG_AMEVTYPER18_EL0, + ARM64_SYSREG_AMEVTYPER19_EL0 = AArch64_SYSREG_AMEVTYPER19_EL0, + ARM64_SYSREG_AMUSERENR_EL0 = AArch64_SYSREG_AMUSERENR_EL0, + ARM64_SYSREG_APDAKEYHI_EL1 = AArch64_SYSREG_APDAKEYHI_EL1, + ARM64_SYSREG_APDAKEYLO_EL1 = AArch64_SYSREG_APDAKEYLO_EL1, + ARM64_SYSREG_APDBKEYHI_EL1 = AArch64_SYSREG_APDBKEYHI_EL1, + ARM64_SYSREG_APDBKEYLO_EL1 = AArch64_SYSREG_APDBKEYLO_EL1, + ARM64_SYSREG_APGAKEYHI_EL1 = AArch64_SYSREG_APGAKEYHI_EL1, + ARM64_SYSREG_APGAKEYLO_EL1 = AArch64_SYSREG_APGAKEYLO_EL1, + ARM64_SYSREG_APIAKEYHI_EL1 = AArch64_SYSREG_APIAKEYHI_EL1, + ARM64_SYSREG_APIAKEYLO_EL1 = AArch64_SYSREG_APIAKEYLO_EL1, + ARM64_SYSREG_APIBKEYHI_EL1 = AArch64_SYSREG_APIBKEYHI_EL1, + ARM64_SYSREG_APIBKEYLO_EL1 = AArch64_SYSREG_APIBKEYLO_EL1, + ARM64_SYSREG_BRBCR_EL1 = AArch64_SYSREG_BRBCR_EL1, + ARM64_SYSREG_BRBCR_EL12 = AArch64_SYSREG_BRBCR_EL12, + ARM64_SYSREG_BRBCR_EL2 = AArch64_SYSREG_BRBCR_EL2, + ARM64_SYSREG_BRBFCR_EL1 = AArch64_SYSREG_BRBFCR_EL1, + ARM64_SYSREG_BRBIDR0_EL1 = AArch64_SYSREG_BRBIDR0_EL1, + ARM64_SYSREG_BRBINF0_EL1 = AArch64_SYSREG_BRBINF0_EL1, + ARM64_SYSREG_BRBINF10_EL1 = AArch64_SYSREG_BRBINF10_EL1, + ARM64_SYSREG_BRBINF11_EL1 = AArch64_SYSREG_BRBINF11_EL1, + ARM64_SYSREG_BRBINF12_EL1 = AArch64_SYSREG_BRBINF12_EL1, + ARM64_SYSREG_BRBINF13_EL1 = AArch64_SYSREG_BRBINF13_EL1, + ARM64_SYSREG_BRBINF14_EL1 = AArch64_SYSREG_BRBINF14_EL1, + ARM64_SYSREG_BRBINF15_EL1 = AArch64_SYSREG_BRBINF15_EL1, + ARM64_SYSREG_BRBINF16_EL1 = AArch64_SYSREG_BRBINF16_EL1, + ARM64_SYSREG_BRBINF17_EL1 = AArch64_SYSREG_BRBINF17_EL1, + ARM64_SYSREG_BRBINF18_EL1 = AArch64_SYSREG_BRBINF18_EL1, + ARM64_SYSREG_BRBINF19_EL1 = AArch64_SYSREG_BRBINF19_EL1, + ARM64_SYSREG_BRBINF1_EL1 = AArch64_SYSREG_BRBINF1_EL1, + ARM64_SYSREG_BRBINF20_EL1 = AArch64_SYSREG_BRBINF20_EL1, + ARM64_SYSREG_BRBINF21_EL1 = AArch64_SYSREG_BRBINF21_EL1, + ARM64_SYSREG_BRBINF22_EL1 = AArch64_SYSREG_BRBINF22_EL1, + ARM64_SYSREG_BRBINF23_EL1 = AArch64_SYSREG_BRBINF23_EL1, + ARM64_SYSREG_BRBINF24_EL1 = AArch64_SYSREG_BRBINF24_EL1, + ARM64_SYSREG_BRBINF25_EL1 = AArch64_SYSREG_BRBINF25_EL1, + ARM64_SYSREG_BRBINF26_EL1 = AArch64_SYSREG_BRBINF26_EL1, + ARM64_SYSREG_BRBINF27_EL1 = AArch64_SYSREG_BRBINF27_EL1, + ARM64_SYSREG_BRBINF28_EL1 = AArch64_SYSREG_BRBINF28_EL1, + ARM64_SYSREG_BRBINF29_EL1 = AArch64_SYSREG_BRBINF29_EL1, + ARM64_SYSREG_BRBINF2_EL1 = AArch64_SYSREG_BRBINF2_EL1, + ARM64_SYSREG_BRBINF30_EL1 = AArch64_SYSREG_BRBINF30_EL1, + ARM64_SYSREG_BRBINF31_EL1 = AArch64_SYSREG_BRBINF31_EL1, + ARM64_SYSREG_BRBINF3_EL1 = AArch64_SYSREG_BRBINF3_EL1, + ARM64_SYSREG_BRBINF4_EL1 = AArch64_SYSREG_BRBINF4_EL1, + ARM64_SYSREG_BRBINF5_EL1 = AArch64_SYSREG_BRBINF5_EL1, + ARM64_SYSREG_BRBINF6_EL1 = AArch64_SYSREG_BRBINF6_EL1, + ARM64_SYSREG_BRBINF7_EL1 = AArch64_SYSREG_BRBINF7_EL1, + ARM64_SYSREG_BRBINF8_EL1 = AArch64_SYSREG_BRBINF8_EL1, + ARM64_SYSREG_BRBINF9_EL1 = AArch64_SYSREG_BRBINF9_EL1, + ARM64_SYSREG_BRBINFINJ_EL1 = AArch64_SYSREG_BRBINFINJ_EL1, + ARM64_SYSREG_BRBSRC0_EL1 = AArch64_SYSREG_BRBSRC0_EL1, + ARM64_SYSREG_BRBSRC10_EL1 = AArch64_SYSREG_BRBSRC10_EL1, + ARM64_SYSREG_BRBSRC11_EL1 = AArch64_SYSREG_BRBSRC11_EL1, + ARM64_SYSREG_BRBSRC12_EL1 = AArch64_SYSREG_BRBSRC12_EL1, + ARM64_SYSREG_BRBSRC13_EL1 = AArch64_SYSREG_BRBSRC13_EL1, + ARM64_SYSREG_BRBSRC14_EL1 = AArch64_SYSREG_BRBSRC14_EL1, + ARM64_SYSREG_BRBSRC15_EL1 = AArch64_SYSREG_BRBSRC15_EL1, + ARM64_SYSREG_BRBSRC16_EL1 = AArch64_SYSREG_BRBSRC16_EL1, + ARM64_SYSREG_BRBSRC17_EL1 = AArch64_SYSREG_BRBSRC17_EL1, + ARM64_SYSREG_BRBSRC18_EL1 = AArch64_SYSREG_BRBSRC18_EL1, + ARM64_SYSREG_BRBSRC19_EL1 = AArch64_SYSREG_BRBSRC19_EL1, + ARM64_SYSREG_BRBSRC1_EL1 = AArch64_SYSREG_BRBSRC1_EL1, + ARM64_SYSREG_BRBSRC20_EL1 = AArch64_SYSREG_BRBSRC20_EL1, + ARM64_SYSREG_BRBSRC21_EL1 = AArch64_SYSREG_BRBSRC21_EL1, + ARM64_SYSREG_BRBSRC22_EL1 = AArch64_SYSREG_BRBSRC22_EL1, + ARM64_SYSREG_BRBSRC23_EL1 = AArch64_SYSREG_BRBSRC23_EL1, + ARM64_SYSREG_BRBSRC24_EL1 = AArch64_SYSREG_BRBSRC24_EL1, + ARM64_SYSREG_BRBSRC25_EL1 = AArch64_SYSREG_BRBSRC25_EL1, + ARM64_SYSREG_BRBSRC26_EL1 = AArch64_SYSREG_BRBSRC26_EL1, + ARM64_SYSREG_BRBSRC27_EL1 = AArch64_SYSREG_BRBSRC27_EL1, + ARM64_SYSREG_BRBSRC28_EL1 = AArch64_SYSREG_BRBSRC28_EL1, + ARM64_SYSREG_BRBSRC29_EL1 = AArch64_SYSREG_BRBSRC29_EL1, + ARM64_SYSREG_BRBSRC2_EL1 = AArch64_SYSREG_BRBSRC2_EL1, + ARM64_SYSREG_BRBSRC30_EL1 = AArch64_SYSREG_BRBSRC30_EL1, + ARM64_SYSREG_BRBSRC31_EL1 = AArch64_SYSREG_BRBSRC31_EL1, + ARM64_SYSREG_BRBSRC3_EL1 = AArch64_SYSREG_BRBSRC3_EL1, + ARM64_SYSREG_BRBSRC4_EL1 = AArch64_SYSREG_BRBSRC4_EL1, + ARM64_SYSREG_BRBSRC5_EL1 = AArch64_SYSREG_BRBSRC5_EL1, + ARM64_SYSREG_BRBSRC6_EL1 = AArch64_SYSREG_BRBSRC6_EL1, + ARM64_SYSREG_BRBSRC7_EL1 = AArch64_SYSREG_BRBSRC7_EL1, + ARM64_SYSREG_BRBSRC8_EL1 = AArch64_SYSREG_BRBSRC8_EL1, + ARM64_SYSREG_BRBSRC9_EL1 = AArch64_SYSREG_BRBSRC9_EL1, + ARM64_SYSREG_BRBSRCINJ_EL1 = AArch64_SYSREG_BRBSRCINJ_EL1, + ARM64_SYSREG_BRBTGT0_EL1 = AArch64_SYSREG_BRBTGT0_EL1, + ARM64_SYSREG_BRBTGT10_EL1 = AArch64_SYSREG_BRBTGT10_EL1, + ARM64_SYSREG_BRBTGT11_EL1 = AArch64_SYSREG_BRBTGT11_EL1, + ARM64_SYSREG_BRBTGT12_EL1 = AArch64_SYSREG_BRBTGT12_EL1, + ARM64_SYSREG_BRBTGT13_EL1 = AArch64_SYSREG_BRBTGT13_EL1, + ARM64_SYSREG_BRBTGT14_EL1 = AArch64_SYSREG_BRBTGT14_EL1, + ARM64_SYSREG_BRBTGT15_EL1 = AArch64_SYSREG_BRBTGT15_EL1, + ARM64_SYSREG_BRBTGT16_EL1 = AArch64_SYSREG_BRBTGT16_EL1, + ARM64_SYSREG_BRBTGT17_EL1 = AArch64_SYSREG_BRBTGT17_EL1, + ARM64_SYSREG_BRBTGT18_EL1 = AArch64_SYSREG_BRBTGT18_EL1, + ARM64_SYSREG_BRBTGT19_EL1 = AArch64_SYSREG_BRBTGT19_EL1, + ARM64_SYSREG_BRBTGT1_EL1 = AArch64_SYSREG_BRBTGT1_EL1, + ARM64_SYSREG_BRBTGT20_EL1 = AArch64_SYSREG_BRBTGT20_EL1, + ARM64_SYSREG_BRBTGT21_EL1 = AArch64_SYSREG_BRBTGT21_EL1, + ARM64_SYSREG_BRBTGT22_EL1 = AArch64_SYSREG_BRBTGT22_EL1, + ARM64_SYSREG_BRBTGT23_EL1 = AArch64_SYSREG_BRBTGT23_EL1, + ARM64_SYSREG_BRBTGT24_EL1 = AArch64_SYSREG_BRBTGT24_EL1, + ARM64_SYSREG_BRBTGT25_EL1 = AArch64_SYSREG_BRBTGT25_EL1, + ARM64_SYSREG_BRBTGT26_EL1 = AArch64_SYSREG_BRBTGT26_EL1, + ARM64_SYSREG_BRBTGT27_EL1 = AArch64_SYSREG_BRBTGT27_EL1, + ARM64_SYSREG_BRBTGT28_EL1 = AArch64_SYSREG_BRBTGT28_EL1, + ARM64_SYSREG_BRBTGT29_EL1 = AArch64_SYSREG_BRBTGT29_EL1, + ARM64_SYSREG_BRBTGT2_EL1 = AArch64_SYSREG_BRBTGT2_EL1, + ARM64_SYSREG_BRBTGT30_EL1 = AArch64_SYSREG_BRBTGT30_EL1, + ARM64_SYSREG_BRBTGT31_EL1 = AArch64_SYSREG_BRBTGT31_EL1, + ARM64_SYSREG_BRBTGT3_EL1 = AArch64_SYSREG_BRBTGT3_EL1, + ARM64_SYSREG_BRBTGT4_EL1 = AArch64_SYSREG_BRBTGT4_EL1, + ARM64_SYSREG_BRBTGT5_EL1 = AArch64_SYSREG_BRBTGT5_EL1, + ARM64_SYSREG_BRBTGT6_EL1 = AArch64_SYSREG_BRBTGT6_EL1, + ARM64_SYSREG_BRBTGT7_EL1 = AArch64_SYSREG_BRBTGT7_EL1, + ARM64_SYSREG_BRBTGT8_EL1 = AArch64_SYSREG_BRBTGT8_EL1, + ARM64_SYSREG_BRBTGT9_EL1 = AArch64_SYSREG_BRBTGT9_EL1, + ARM64_SYSREG_BRBTGTINJ_EL1 = AArch64_SYSREG_BRBTGTINJ_EL1, + ARM64_SYSREG_BRBTS_EL1 = AArch64_SYSREG_BRBTS_EL1, + ARM64_SYSREG_CCSIDR2_EL1 = AArch64_SYSREG_CCSIDR2_EL1, + ARM64_SYSREG_CCSIDR_EL1 = AArch64_SYSREG_CCSIDR_EL1, + ARM64_SYSREG_CLIDR_EL1 = AArch64_SYSREG_CLIDR_EL1, + ARM64_SYSREG_CNTFRQ_EL0 = AArch64_SYSREG_CNTFRQ_EL0, + ARM64_SYSREG_CNTHCTL_EL2 = AArch64_SYSREG_CNTHCTL_EL2, + ARM64_SYSREG_CNTHPS_CTL_EL2 = AArch64_SYSREG_CNTHPS_CTL_EL2, + ARM64_SYSREG_CNTHPS_CVAL_EL2 = AArch64_SYSREG_CNTHPS_CVAL_EL2, + ARM64_SYSREG_CNTHPS_TVAL_EL2 = AArch64_SYSREG_CNTHPS_TVAL_EL2, + ARM64_SYSREG_CNTHP_CTL_EL2 = AArch64_SYSREG_CNTHP_CTL_EL2, + ARM64_SYSREG_CNTHP_CVAL_EL2 = AArch64_SYSREG_CNTHP_CVAL_EL2, + ARM64_SYSREG_CNTHP_TVAL_EL2 = AArch64_SYSREG_CNTHP_TVAL_EL2, + ARM64_SYSREG_CNTHVS_CTL_EL2 = AArch64_SYSREG_CNTHVS_CTL_EL2, + ARM64_SYSREG_CNTHVS_CVAL_EL2 = AArch64_SYSREG_CNTHVS_CVAL_EL2, + ARM64_SYSREG_CNTHVS_TVAL_EL2 = AArch64_SYSREG_CNTHVS_TVAL_EL2, + ARM64_SYSREG_CNTHV_CTL_EL2 = AArch64_SYSREG_CNTHV_CTL_EL2, + ARM64_SYSREG_CNTHV_CVAL_EL2 = AArch64_SYSREG_CNTHV_CVAL_EL2, + ARM64_SYSREG_CNTHV_TVAL_EL2 = AArch64_SYSREG_CNTHV_TVAL_EL2, + ARM64_SYSREG_CNTISCALE_EL2 = AArch64_SYSREG_CNTISCALE_EL2, + ARM64_SYSREG_CNTKCTL_EL1 = AArch64_SYSREG_CNTKCTL_EL1, + ARM64_SYSREG_CNTKCTL_EL12 = AArch64_SYSREG_CNTKCTL_EL12, + ARM64_SYSREG_CNTPCTSS_EL0 = AArch64_SYSREG_CNTPCTSS_EL0, + ARM64_SYSREG_CNTPCT_EL0 = AArch64_SYSREG_CNTPCT_EL0, + ARM64_SYSREG_CNTPOFF_EL2 = AArch64_SYSREG_CNTPOFF_EL2, + ARM64_SYSREG_CNTPS_CTL_EL1 = AArch64_SYSREG_CNTPS_CTL_EL1, + ARM64_SYSREG_CNTPS_CVAL_EL1 = AArch64_SYSREG_CNTPS_CVAL_EL1, + ARM64_SYSREG_CNTPS_TVAL_EL1 = AArch64_SYSREG_CNTPS_TVAL_EL1, + ARM64_SYSREG_CNTP_CTL_EL0 = AArch64_SYSREG_CNTP_CTL_EL0, + ARM64_SYSREG_CNTP_CTL_EL02 = AArch64_SYSREG_CNTP_CTL_EL02, + ARM64_SYSREG_CNTP_CVAL_EL0 = AArch64_SYSREG_CNTP_CVAL_EL0, + ARM64_SYSREG_CNTP_CVAL_EL02 = AArch64_SYSREG_CNTP_CVAL_EL02, + ARM64_SYSREG_CNTP_TVAL_EL0 = AArch64_SYSREG_CNTP_TVAL_EL0, + ARM64_SYSREG_CNTP_TVAL_EL02 = AArch64_SYSREG_CNTP_TVAL_EL02, + ARM64_SYSREG_CNTSCALE_EL2 = AArch64_SYSREG_CNTSCALE_EL2, + ARM64_SYSREG_CNTVCTSS_EL0 = AArch64_SYSREG_CNTVCTSS_EL0, + ARM64_SYSREG_CNTVCT_EL0 = AArch64_SYSREG_CNTVCT_EL0, + ARM64_SYSREG_CNTVFRQ_EL2 = AArch64_SYSREG_CNTVFRQ_EL2, + ARM64_SYSREG_CNTVOFF_EL2 = AArch64_SYSREG_CNTVOFF_EL2, + ARM64_SYSREG_CNTV_CTL_EL0 = AArch64_SYSREG_CNTV_CTL_EL0, + ARM64_SYSREG_CNTV_CTL_EL02 = AArch64_SYSREG_CNTV_CTL_EL02, + ARM64_SYSREG_CNTV_CVAL_EL0 = AArch64_SYSREG_CNTV_CVAL_EL0, + ARM64_SYSREG_CNTV_CVAL_EL02 = AArch64_SYSREG_CNTV_CVAL_EL02, + ARM64_SYSREG_CNTV_TVAL_EL0 = AArch64_SYSREG_CNTV_TVAL_EL0, + ARM64_SYSREG_CNTV_TVAL_EL02 = AArch64_SYSREG_CNTV_TVAL_EL02, + ARM64_SYSREG_CONTEXTIDR_EL1 = AArch64_SYSREG_CONTEXTIDR_EL1, + ARM64_SYSREG_CONTEXTIDR_EL12 = AArch64_SYSREG_CONTEXTIDR_EL12, + ARM64_SYSREG_CONTEXTIDR_EL2 = AArch64_SYSREG_CONTEXTIDR_EL2, + ARM64_SYSREG_CPACR_EL1 = AArch64_SYSREG_CPACR_EL1, + ARM64_SYSREG_CPACR_EL12 = AArch64_SYSREG_CPACR_EL12, + ARM64_SYSREG_CPM_IOACC_CTL_EL3 = AArch64_SYSREG_CPM_IOACC_CTL_EL3, + ARM64_SYSREG_CPTR_EL2 = AArch64_SYSREG_CPTR_EL2, + ARM64_SYSREG_CPTR_EL3 = AArch64_SYSREG_CPTR_EL3, + ARM64_SYSREG_CSSELR_EL1 = AArch64_SYSREG_CSSELR_EL1, + ARM64_SYSREG_CTR_EL0 = AArch64_SYSREG_CTR_EL0, + ARM64_SYSREG_CURRENTEL = AArch64_SYSREG_CURRENTEL, + ARM64_SYSREG_DACR32_EL2 = AArch64_SYSREG_DACR32_EL2, + ARM64_SYSREG_DAIF = AArch64_SYSREG_DAIF, + ARM64_SYSREG_DBGAUTHSTATUS_EL1 = AArch64_SYSREG_DBGAUTHSTATUS_EL1, + ARM64_SYSREG_DBGBCR0_EL1 = AArch64_SYSREG_DBGBCR0_EL1, + ARM64_SYSREG_DBGBCR10_EL1 = AArch64_SYSREG_DBGBCR10_EL1, + ARM64_SYSREG_DBGBCR11_EL1 = AArch64_SYSREG_DBGBCR11_EL1, + ARM64_SYSREG_DBGBCR12_EL1 = AArch64_SYSREG_DBGBCR12_EL1, + ARM64_SYSREG_DBGBCR13_EL1 = AArch64_SYSREG_DBGBCR13_EL1, + ARM64_SYSREG_DBGBCR14_EL1 = AArch64_SYSREG_DBGBCR14_EL1, + ARM64_SYSREG_DBGBCR15_EL1 = AArch64_SYSREG_DBGBCR15_EL1, + ARM64_SYSREG_DBGBCR1_EL1 = AArch64_SYSREG_DBGBCR1_EL1, + ARM64_SYSREG_DBGBCR2_EL1 = AArch64_SYSREG_DBGBCR2_EL1, + ARM64_SYSREG_DBGBCR3_EL1 = AArch64_SYSREG_DBGBCR3_EL1, + ARM64_SYSREG_DBGBCR4_EL1 = AArch64_SYSREG_DBGBCR4_EL1, + ARM64_SYSREG_DBGBCR5_EL1 = AArch64_SYSREG_DBGBCR5_EL1, + ARM64_SYSREG_DBGBCR6_EL1 = AArch64_SYSREG_DBGBCR6_EL1, + ARM64_SYSREG_DBGBCR7_EL1 = AArch64_SYSREG_DBGBCR7_EL1, + ARM64_SYSREG_DBGBCR8_EL1 = AArch64_SYSREG_DBGBCR8_EL1, + ARM64_SYSREG_DBGBCR9_EL1 = AArch64_SYSREG_DBGBCR9_EL1, + ARM64_SYSREG_DBGBVR0_EL1 = AArch64_SYSREG_DBGBVR0_EL1, + ARM64_SYSREG_DBGBVR10_EL1 = AArch64_SYSREG_DBGBVR10_EL1, + ARM64_SYSREG_DBGBVR11_EL1 = AArch64_SYSREG_DBGBVR11_EL1, + ARM64_SYSREG_DBGBVR12_EL1 = AArch64_SYSREG_DBGBVR12_EL1, + ARM64_SYSREG_DBGBVR13_EL1 = AArch64_SYSREG_DBGBVR13_EL1, + ARM64_SYSREG_DBGBVR14_EL1 = AArch64_SYSREG_DBGBVR14_EL1, + ARM64_SYSREG_DBGBVR15_EL1 = AArch64_SYSREG_DBGBVR15_EL1, + ARM64_SYSREG_DBGBVR1_EL1 = AArch64_SYSREG_DBGBVR1_EL1, + ARM64_SYSREG_DBGBVR2_EL1 = AArch64_SYSREG_DBGBVR2_EL1, + ARM64_SYSREG_DBGBVR3_EL1 = AArch64_SYSREG_DBGBVR3_EL1, + ARM64_SYSREG_DBGBVR4_EL1 = AArch64_SYSREG_DBGBVR4_EL1, + ARM64_SYSREG_DBGBVR5_EL1 = AArch64_SYSREG_DBGBVR5_EL1, + ARM64_SYSREG_DBGBVR6_EL1 = AArch64_SYSREG_DBGBVR6_EL1, + ARM64_SYSREG_DBGBVR7_EL1 = AArch64_SYSREG_DBGBVR7_EL1, + ARM64_SYSREG_DBGBVR8_EL1 = AArch64_SYSREG_DBGBVR8_EL1, + ARM64_SYSREG_DBGBVR9_EL1 = AArch64_SYSREG_DBGBVR9_EL1, + ARM64_SYSREG_DBGCLAIMCLR_EL1 = AArch64_SYSREG_DBGCLAIMCLR_EL1, + ARM64_SYSREG_DBGCLAIMSET_EL1 = AArch64_SYSREG_DBGCLAIMSET_EL1, + ARM64_SYSREG_DBGDTRRX_EL0 = AArch64_SYSREG_DBGDTRRX_EL0, + ARM64_SYSREG_DBGDTRTX_EL0 = AArch64_SYSREG_DBGDTRTX_EL0, + ARM64_SYSREG_DBGDTR_EL0 = AArch64_SYSREG_DBGDTR_EL0, + ARM64_SYSREG_DBGPRCR_EL1 = AArch64_SYSREG_DBGPRCR_EL1, + ARM64_SYSREG_DBGVCR32_EL2 = AArch64_SYSREG_DBGVCR32_EL2, + ARM64_SYSREG_DBGWCR0_EL1 = AArch64_SYSREG_DBGWCR0_EL1, + ARM64_SYSREG_DBGWCR10_EL1 = AArch64_SYSREG_DBGWCR10_EL1, + ARM64_SYSREG_DBGWCR11_EL1 = AArch64_SYSREG_DBGWCR11_EL1, + ARM64_SYSREG_DBGWCR12_EL1 = AArch64_SYSREG_DBGWCR12_EL1, + ARM64_SYSREG_DBGWCR13_EL1 = AArch64_SYSREG_DBGWCR13_EL1, + ARM64_SYSREG_DBGWCR14_EL1 = AArch64_SYSREG_DBGWCR14_EL1, + ARM64_SYSREG_DBGWCR15_EL1 = AArch64_SYSREG_DBGWCR15_EL1, + ARM64_SYSREG_DBGWCR1_EL1 = AArch64_SYSREG_DBGWCR1_EL1, + ARM64_SYSREG_DBGWCR2_EL1 = AArch64_SYSREG_DBGWCR2_EL1, + ARM64_SYSREG_DBGWCR3_EL1 = AArch64_SYSREG_DBGWCR3_EL1, + ARM64_SYSREG_DBGWCR4_EL1 = AArch64_SYSREG_DBGWCR4_EL1, + ARM64_SYSREG_DBGWCR5_EL1 = AArch64_SYSREG_DBGWCR5_EL1, + ARM64_SYSREG_DBGWCR6_EL1 = AArch64_SYSREG_DBGWCR6_EL1, + ARM64_SYSREG_DBGWCR7_EL1 = AArch64_SYSREG_DBGWCR7_EL1, + ARM64_SYSREG_DBGWCR8_EL1 = AArch64_SYSREG_DBGWCR8_EL1, + ARM64_SYSREG_DBGWCR9_EL1 = AArch64_SYSREG_DBGWCR9_EL1, + ARM64_SYSREG_DBGWVR0_EL1 = AArch64_SYSREG_DBGWVR0_EL1, + ARM64_SYSREG_DBGWVR10_EL1 = AArch64_SYSREG_DBGWVR10_EL1, + ARM64_SYSREG_DBGWVR11_EL1 = AArch64_SYSREG_DBGWVR11_EL1, + ARM64_SYSREG_DBGWVR12_EL1 = AArch64_SYSREG_DBGWVR12_EL1, + ARM64_SYSREG_DBGWVR13_EL1 = AArch64_SYSREG_DBGWVR13_EL1, + ARM64_SYSREG_DBGWVR14_EL1 = AArch64_SYSREG_DBGWVR14_EL1, + ARM64_SYSREG_DBGWVR15_EL1 = AArch64_SYSREG_DBGWVR15_EL1, + ARM64_SYSREG_DBGWVR1_EL1 = AArch64_SYSREG_DBGWVR1_EL1, + ARM64_SYSREG_DBGWVR2_EL1 = AArch64_SYSREG_DBGWVR2_EL1, + ARM64_SYSREG_DBGWVR3_EL1 = AArch64_SYSREG_DBGWVR3_EL1, + ARM64_SYSREG_DBGWVR4_EL1 = AArch64_SYSREG_DBGWVR4_EL1, + ARM64_SYSREG_DBGWVR5_EL1 = AArch64_SYSREG_DBGWVR5_EL1, + ARM64_SYSREG_DBGWVR6_EL1 = AArch64_SYSREG_DBGWVR6_EL1, + ARM64_SYSREG_DBGWVR7_EL1 = AArch64_SYSREG_DBGWVR7_EL1, + ARM64_SYSREG_DBGWVR8_EL1 = AArch64_SYSREG_DBGWVR8_EL1, + ARM64_SYSREG_DBGWVR9_EL1 = AArch64_SYSREG_DBGWVR9_EL1, + ARM64_SYSREG_DCZID_EL0 = AArch64_SYSREG_DCZID_EL0, + ARM64_SYSREG_DISR_EL1 = AArch64_SYSREG_DISR_EL1, + ARM64_SYSREG_DIT = AArch64_SYSREG_DIT, + ARM64_SYSREG_DLR_EL0 = AArch64_SYSREG_DLR_EL0, + ARM64_SYSREG_DSPSR_EL0 = AArch64_SYSREG_DSPSR_EL0, + ARM64_SYSREG_ELR_EL1 = AArch64_SYSREG_ELR_EL1, + ARM64_SYSREG_ELR_EL12 = AArch64_SYSREG_ELR_EL12, + ARM64_SYSREG_ELR_EL2 = AArch64_SYSREG_ELR_EL2, + ARM64_SYSREG_ELR_EL3 = AArch64_SYSREG_ELR_EL3, + ARM64_SYSREG_ERRIDR_EL1 = AArch64_SYSREG_ERRIDR_EL1, + ARM64_SYSREG_ERRSELR_EL1 = AArch64_SYSREG_ERRSELR_EL1, + ARM64_SYSREG_ERXADDR_EL1 = AArch64_SYSREG_ERXADDR_EL1, + ARM64_SYSREG_ERXCTLR_EL1 = AArch64_SYSREG_ERXCTLR_EL1, + ARM64_SYSREG_ERXFR_EL1 = AArch64_SYSREG_ERXFR_EL1, + ARM64_SYSREG_ERXGSR_EL1 = AArch64_SYSREG_ERXGSR_EL1, + ARM64_SYSREG_ERXMISC0_EL1 = AArch64_SYSREG_ERXMISC0_EL1, + ARM64_SYSREG_ERXMISC1_EL1 = AArch64_SYSREG_ERXMISC1_EL1, + ARM64_SYSREG_ERXMISC2_EL1 = AArch64_SYSREG_ERXMISC2_EL1, + ARM64_SYSREG_ERXMISC3_EL1 = AArch64_SYSREG_ERXMISC3_EL1, + ARM64_SYSREG_ERXPFGCDN_EL1 = AArch64_SYSREG_ERXPFGCDN_EL1, + ARM64_SYSREG_ERXPFGCTL_EL1 = AArch64_SYSREG_ERXPFGCTL_EL1, + ARM64_SYSREG_ERXPFGF_EL1 = AArch64_SYSREG_ERXPFGF_EL1, + ARM64_SYSREG_ERXSTATUS_EL1 = AArch64_SYSREG_ERXSTATUS_EL1, + ARM64_SYSREG_ESR_EL1 = AArch64_SYSREG_ESR_EL1, + ARM64_SYSREG_ESR_EL12 = AArch64_SYSREG_ESR_EL12, + ARM64_SYSREG_ESR_EL2 = AArch64_SYSREG_ESR_EL2, + ARM64_SYSREG_ESR_EL3 = AArch64_SYSREG_ESR_EL3, + ARM64_SYSREG_FAR_EL1 = AArch64_SYSREG_FAR_EL1, + ARM64_SYSREG_FAR_EL12 = AArch64_SYSREG_FAR_EL12, + ARM64_SYSREG_FAR_EL2 = AArch64_SYSREG_FAR_EL2, + ARM64_SYSREG_FAR_EL3 = AArch64_SYSREG_FAR_EL3, + ARM64_SYSREG_FPCR = AArch64_SYSREG_FPCR, + ARM64_SYSREG_FPEXC32_EL2 = AArch64_SYSREG_FPEXC32_EL2, + ARM64_SYSREG_FPSR = AArch64_SYSREG_FPSR, + ARM64_SYSREG_GCR_EL1 = AArch64_SYSREG_GCR_EL1, + ARM64_SYSREG_GMID_EL1 = AArch64_SYSREG_GMID_EL1, + ARM64_SYSREG_GPCCR_EL3 = AArch64_SYSREG_GPCCR_EL3, + ARM64_SYSREG_GPTBR_EL3 = AArch64_SYSREG_GPTBR_EL3, + ARM64_SYSREG_HACR_EL2 = AArch64_SYSREG_HACR_EL2, + ARM64_SYSREG_HAFGRTR_EL2 = AArch64_SYSREG_HAFGRTR_EL2, + ARM64_SYSREG_HCRX_EL2 = AArch64_SYSREG_HCRX_EL2, + ARM64_SYSREG_HCR_EL2 = AArch64_SYSREG_HCR_EL2, + ARM64_SYSREG_HDFGRTR2_EL2 = AArch64_SYSREG_HDFGRTR2_EL2, + ARM64_SYSREG_HDFGRTR_EL2 = AArch64_SYSREG_HDFGRTR_EL2, + ARM64_SYSREG_HDFGWTR2_EL2 = AArch64_SYSREG_HDFGWTR2_EL2, + ARM64_SYSREG_HDFGWTR_EL2 = AArch64_SYSREG_HDFGWTR_EL2, + ARM64_SYSREG_HFGITR2_EL2 = AArch64_SYSREG_HFGITR2_EL2, + ARM64_SYSREG_HFGITR_EL2 = AArch64_SYSREG_HFGITR_EL2, + ARM64_SYSREG_HFGRTR2_EL2 = AArch64_SYSREG_HFGRTR2_EL2, + ARM64_SYSREG_HFGRTR_EL2 = AArch64_SYSREG_HFGRTR_EL2, + ARM64_SYSREG_HFGWTR2_EL2 = AArch64_SYSREG_HFGWTR2_EL2, + ARM64_SYSREG_HFGWTR_EL2 = AArch64_SYSREG_HFGWTR_EL2, + ARM64_SYSREG_HPFAR_EL2 = AArch64_SYSREG_HPFAR_EL2, + ARM64_SYSREG_HSTR_EL2 = AArch64_SYSREG_HSTR_EL2, + ARM64_SYSREG_ICC_AP0R0_EL1 = AArch64_SYSREG_ICC_AP0R0_EL1, + ARM64_SYSREG_ICC_AP0R1_EL1 = AArch64_SYSREG_ICC_AP0R1_EL1, + ARM64_SYSREG_ICC_AP0R2_EL1 = AArch64_SYSREG_ICC_AP0R2_EL1, + ARM64_SYSREG_ICC_AP0R3_EL1 = AArch64_SYSREG_ICC_AP0R3_EL1, + ARM64_SYSREG_ICC_AP1R0_EL1 = AArch64_SYSREG_ICC_AP1R0_EL1, + ARM64_SYSREG_ICC_AP1R1_EL1 = AArch64_SYSREG_ICC_AP1R1_EL1, + ARM64_SYSREG_ICC_AP1R2_EL1 = AArch64_SYSREG_ICC_AP1R2_EL1, + ARM64_SYSREG_ICC_AP1R3_EL1 = AArch64_SYSREG_ICC_AP1R3_EL1, + ARM64_SYSREG_ICC_ASGI1R_EL1 = AArch64_SYSREG_ICC_ASGI1R_EL1, + ARM64_SYSREG_ICC_BPR0_EL1 = AArch64_SYSREG_ICC_BPR0_EL1, + ARM64_SYSREG_ICC_BPR1_EL1 = AArch64_SYSREG_ICC_BPR1_EL1, + ARM64_SYSREG_ICC_CTLR_EL1 = AArch64_SYSREG_ICC_CTLR_EL1, + ARM64_SYSREG_ICC_CTLR_EL3 = AArch64_SYSREG_ICC_CTLR_EL3, + ARM64_SYSREG_ICC_DIR_EL1 = AArch64_SYSREG_ICC_DIR_EL1, + ARM64_SYSREG_ICC_EOIR0_EL1 = AArch64_SYSREG_ICC_EOIR0_EL1, + ARM64_SYSREG_ICC_EOIR1_EL1 = AArch64_SYSREG_ICC_EOIR1_EL1, + ARM64_SYSREG_ICC_HPPIR0_EL1 = AArch64_SYSREG_ICC_HPPIR0_EL1, + ARM64_SYSREG_ICC_HPPIR1_EL1 = AArch64_SYSREG_ICC_HPPIR1_EL1, + ARM64_SYSREG_ICC_IAR0_EL1 = AArch64_SYSREG_ICC_IAR0_EL1, + ARM64_SYSREG_ICC_IAR1_EL1 = AArch64_SYSREG_ICC_IAR1_EL1, + ARM64_SYSREG_ICC_IGRPEN0_EL1 = AArch64_SYSREG_ICC_IGRPEN0_EL1, + ARM64_SYSREG_ICC_IGRPEN1_EL1 = AArch64_SYSREG_ICC_IGRPEN1_EL1, + ARM64_SYSREG_ICC_IGRPEN1_EL3 = AArch64_SYSREG_ICC_IGRPEN1_EL3, + ARM64_SYSREG_ICC_NMIAR1_EL1 = AArch64_SYSREG_ICC_NMIAR1_EL1, + ARM64_SYSREG_ICC_PMR_EL1 = AArch64_SYSREG_ICC_PMR_EL1, + ARM64_SYSREG_ICC_RPR_EL1 = AArch64_SYSREG_ICC_RPR_EL1, + ARM64_SYSREG_ICC_SGI0R_EL1 = AArch64_SYSREG_ICC_SGI0R_EL1, + ARM64_SYSREG_ICC_SGI1R_EL1 = AArch64_SYSREG_ICC_SGI1R_EL1, + ARM64_SYSREG_ICC_SRE_EL1 = AArch64_SYSREG_ICC_SRE_EL1, + ARM64_SYSREG_ICC_SRE_EL2 = AArch64_SYSREG_ICC_SRE_EL2, + ARM64_SYSREG_ICC_SRE_EL3 = AArch64_SYSREG_ICC_SRE_EL3, + ARM64_SYSREG_ICH_AP0R0_EL2 = AArch64_SYSREG_ICH_AP0R0_EL2, + ARM64_SYSREG_ICH_AP0R1_EL2 = AArch64_SYSREG_ICH_AP0R1_EL2, + ARM64_SYSREG_ICH_AP0R2_EL2 = AArch64_SYSREG_ICH_AP0R2_EL2, + ARM64_SYSREG_ICH_AP0R3_EL2 = AArch64_SYSREG_ICH_AP0R3_EL2, + ARM64_SYSREG_ICH_AP1R0_EL2 = AArch64_SYSREG_ICH_AP1R0_EL2, + ARM64_SYSREG_ICH_AP1R1_EL2 = AArch64_SYSREG_ICH_AP1R1_EL2, + ARM64_SYSREG_ICH_AP1R2_EL2 = AArch64_SYSREG_ICH_AP1R2_EL2, + ARM64_SYSREG_ICH_AP1R3_EL2 = AArch64_SYSREG_ICH_AP1R3_EL2, + ARM64_SYSREG_ICH_EISR_EL2 = AArch64_SYSREG_ICH_EISR_EL2, + ARM64_SYSREG_ICH_ELRSR_EL2 = AArch64_SYSREG_ICH_ELRSR_EL2, + ARM64_SYSREG_ICH_HCR_EL2 = AArch64_SYSREG_ICH_HCR_EL2, + ARM64_SYSREG_ICH_LR0_EL2 = AArch64_SYSREG_ICH_LR0_EL2, + ARM64_SYSREG_ICH_LR10_EL2 = AArch64_SYSREG_ICH_LR10_EL2, + ARM64_SYSREG_ICH_LR11_EL2 = AArch64_SYSREG_ICH_LR11_EL2, + ARM64_SYSREG_ICH_LR12_EL2 = AArch64_SYSREG_ICH_LR12_EL2, + ARM64_SYSREG_ICH_LR13_EL2 = AArch64_SYSREG_ICH_LR13_EL2, + ARM64_SYSREG_ICH_LR14_EL2 = AArch64_SYSREG_ICH_LR14_EL2, + ARM64_SYSREG_ICH_LR15_EL2 = AArch64_SYSREG_ICH_LR15_EL2, + ARM64_SYSREG_ICH_LR1_EL2 = AArch64_SYSREG_ICH_LR1_EL2, + ARM64_SYSREG_ICH_LR2_EL2 = AArch64_SYSREG_ICH_LR2_EL2, + ARM64_SYSREG_ICH_LR3_EL2 = AArch64_SYSREG_ICH_LR3_EL2, + ARM64_SYSREG_ICH_LR4_EL2 = AArch64_SYSREG_ICH_LR4_EL2, + ARM64_SYSREG_ICH_LR5_EL2 = AArch64_SYSREG_ICH_LR5_EL2, + ARM64_SYSREG_ICH_LR6_EL2 = AArch64_SYSREG_ICH_LR6_EL2, + ARM64_SYSREG_ICH_LR7_EL2 = AArch64_SYSREG_ICH_LR7_EL2, + ARM64_SYSREG_ICH_LR8_EL2 = AArch64_SYSREG_ICH_LR8_EL2, + ARM64_SYSREG_ICH_LR9_EL2 = AArch64_SYSREG_ICH_LR9_EL2, + ARM64_SYSREG_ICH_MISR_EL2 = AArch64_SYSREG_ICH_MISR_EL2, + ARM64_SYSREG_ICH_VMCR_EL2 = AArch64_SYSREG_ICH_VMCR_EL2, + ARM64_SYSREG_ICH_VTR_EL2 = AArch64_SYSREG_ICH_VTR_EL2, + ARM64_SYSREG_ID_AA64AFR0_EL1 = AArch64_SYSREG_ID_AA64AFR0_EL1, + ARM64_SYSREG_ID_AA64AFR1_EL1 = AArch64_SYSREG_ID_AA64AFR1_EL1, + ARM64_SYSREG_ID_AA64DFR0_EL1 = AArch64_SYSREG_ID_AA64DFR0_EL1, + ARM64_SYSREG_ID_AA64DFR1_EL1 = AArch64_SYSREG_ID_AA64DFR1_EL1, + ARM64_SYSREG_ID_AA64ISAR0_EL1 = AArch64_SYSREG_ID_AA64ISAR0_EL1, + ARM64_SYSREG_ID_AA64ISAR1_EL1 = AArch64_SYSREG_ID_AA64ISAR1_EL1, + ARM64_SYSREG_ID_AA64ISAR2_EL1 = AArch64_SYSREG_ID_AA64ISAR2_EL1, + ARM64_SYSREG_ID_AA64MMFR0_EL1 = AArch64_SYSREG_ID_AA64MMFR0_EL1, + ARM64_SYSREG_ID_AA64MMFR1_EL1 = AArch64_SYSREG_ID_AA64MMFR1_EL1, + ARM64_SYSREG_ID_AA64MMFR2_EL1 = AArch64_SYSREG_ID_AA64MMFR2_EL1, + ARM64_SYSREG_ID_AA64MMFR3_EL1 = AArch64_SYSREG_ID_AA64MMFR3_EL1, + ARM64_SYSREG_ID_AA64MMFR4_EL1 = AArch64_SYSREG_ID_AA64MMFR4_EL1, + ARM64_SYSREG_ID_AA64PFR0_EL1 = AArch64_SYSREG_ID_AA64PFR0_EL1, + ARM64_SYSREG_ID_AA64PFR1_EL1 = AArch64_SYSREG_ID_AA64PFR1_EL1, + ARM64_SYSREG_ID_AA64PFR2_EL1 = AArch64_SYSREG_ID_AA64PFR2_EL1, + ARM64_SYSREG_ID_AA64SMFR0_EL1 = AArch64_SYSREG_ID_AA64SMFR0_EL1, + ARM64_SYSREG_ID_AA64ZFR0_EL1 = AArch64_SYSREG_ID_AA64ZFR0_EL1, + ARM64_SYSREG_ID_AFR0_EL1 = AArch64_SYSREG_ID_AFR0_EL1, + ARM64_SYSREG_ID_DFR0_EL1 = AArch64_SYSREG_ID_DFR0_EL1, + ARM64_SYSREG_ID_DFR1_EL1 = AArch64_SYSREG_ID_DFR1_EL1, + ARM64_SYSREG_ID_ISAR0_EL1 = AArch64_SYSREG_ID_ISAR0_EL1, + ARM64_SYSREG_ID_ISAR1_EL1 = AArch64_SYSREG_ID_ISAR1_EL1, + ARM64_SYSREG_ID_ISAR2_EL1 = AArch64_SYSREG_ID_ISAR2_EL1, + ARM64_SYSREG_ID_ISAR3_EL1 = AArch64_SYSREG_ID_ISAR3_EL1, + ARM64_SYSREG_ID_ISAR4_EL1 = AArch64_SYSREG_ID_ISAR4_EL1, + ARM64_SYSREG_ID_ISAR5_EL1 = AArch64_SYSREG_ID_ISAR5_EL1, + ARM64_SYSREG_ID_ISAR6_EL1 = AArch64_SYSREG_ID_ISAR6_EL1, + ARM64_SYSREG_ID_MMFR0_EL1 = AArch64_SYSREG_ID_MMFR0_EL1, + ARM64_SYSREG_ID_MMFR1_EL1 = AArch64_SYSREG_ID_MMFR1_EL1, + ARM64_SYSREG_ID_MMFR2_EL1 = AArch64_SYSREG_ID_MMFR2_EL1, + ARM64_SYSREG_ID_MMFR3_EL1 = AArch64_SYSREG_ID_MMFR3_EL1, + ARM64_SYSREG_ID_MMFR4_EL1 = AArch64_SYSREG_ID_MMFR4_EL1, + ARM64_SYSREG_ID_MMFR5_EL1 = AArch64_SYSREG_ID_MMFR5_EL1, + ARM64_SYSREG_ID_PFR0_EL1 = AArch64_SYSREG_ID_PFR0_EL1, + ARM64_SYSREG_ID_PFR1_EL1 = AArch64_SYSREG_ID_PFR1_EL1, + ARM64_SYSREG_ID_PFR2_EL1 = AArch64_SYSREG_ID_PFR2_EL1, + ARM64_SYSREG_IFSR32_EL2 = AArch64_SYSREG_IFSR32_EL2, + ARM64_SYSREG_ISR_EL1 = AArch64_SYSREG_ISR_EL1, + ARM64_SYSREG_LORC_EL1 = AArch64_SYSREG_LORC_EL1, + ARM64_SYSREG_LOREA_EL1 = AArch64_SYSREG_LOREA_EL1, + ARM64_SYSREG_LORID_EL1 = AArch64_SYSREG_LORID_EL1, + ARM64_SYSREG_LORN_EL1 = AArch64_SYSREG_LORN_EL1, + ARM64_SYSREG_LORSA_EL1 = AArch64_SYSREG_LORSA_EL1, + ARM64_SYSREG_MAIR2_EL1 = AArch64_SYSREG_MAIR2_EL1, + ARM64_SYSREG_MAIR2_EL12 = AArch64_SYSREG_MAIR2_EL12, + ARM64_SYSREG_MAIR2_EL2 = AArch64_SYSREG_MAIR2_EL2, + ARM64_SYSREG_MAIR2_EL3 = AArch64_SYSREG_MAIR2_EL3, + ARM64_SYSREG_MAIR_EL1 = AArch64_SYSREG_MAIR_EL1, + ARM64_SYSREG_MAIR_EL12 = AArch64_SYSREG_MAIR_EL12, + ARM64_SYSREG_MAIR_EL2 = AArch64_SYSREG_MAIR_EL2, + ARM64_SYSREG_MAIR_EL3 = AArch64_SYSREG_MAIR_EL3, + ARM64_SYSREG_MDCCINT_EL1 = AArch64_SYSREG_MDCCINT_EL1, + ARM64_SYSREG_MDCCSR_EL0 = AArch64_SYSREG_MDCCSR_EL0, + ARM64_SYSREG_MDCR_EL2 = AArch64_SYSREG_MDCR_EL2, + ARM64_SYSREG_MDCR_EL3 = AArch64_SYSREG_MDCR_EL3, + ARM64_SYSREG_MDRAR_EL1 = AArch64_SYSREG_MDRAR_EL1, + ARM64_SYSREG_MDSCR_EL1 = AArch64_SYSREG_MDSCR_EL1, + ARM64_SYSREG_MDSELR_EL1 = AArch64_SYSREG_MDSELR_EL1, + ARM64_SYSREG_MECIDR_EL2 = AArch64_SYSREG_MECIDR_EL2, + ARM64_SYSREG_MECID_A0_EL2 = AArch64_SYSREG_MECID_A0_EL2, + ARM64_SYSREG_MECID_A1_EL2 = AArch64_SYSREG_MECID_A1_EL2, + ARM64_SYSREG_MECID_P0_EL2 = AArch64_SYSREG_MECID_P0_EL2, + ARM64_SYSREG_MECID_P1_EL2 = AArch64_SYSREG_MECID_P1_EL2, + ARM64_SYSREG_MECID_RL_A_EL3 = AArch64_SYSREG_MECID_RL_A_EL3, + ARM64_SYSREG_MFAR_EL3 = AArch64_SYSREG_MFAR_EL3, + ARM64_SYSREG_MIDR_EL1 = AArch64_SYSREG_MIDR_EL1, + ARM64_SYSREG_MPAM0_EL1 = AArch64_SYSREG_MPAM0_EL1, + ARM64_SYSREG_MPAM1_EL1 = AArch64_SYSREG_MPAM1_EL1, + ARM64_SYSREG_MPAM1_EL12 = AArch64_SYSREG_MPAM1_EL12, + ARM64_SYSREG_MPAM2_EL2 = AArch64_SYSREG_MPAM2_EL2, + ARM64_SYSREG_MPAM3_EL3 = AArch64_SYSREG_MPAM3_EL3, + ARM64_SYSREG_MPAMHCR_EL2 = AArch64_SYSREG_MPAMHCR_EL2, + ARM64_SYSREG_MPAMIDR_EL1 = AArch64_SYSREG_MPAMIDR_EL1, + ARM64_SYSREG_MPAMSM_EL1 = AArch64_SYSREG_MPAMSM_EL1, + ARM64_SYSREG_MPAMVPM0_EL2 = AArch64_SYSREG_MPAMVPM0_EL2, + ARM64_SYSREG_MPAMVPM1_EL2 = AArch64_SYSREG_MPAMVPM1_EL2, + ARM64_SYSREG_MPAMVPM2_EL2 = AArch64_SYSREG_MPAMVPM2_EL2, + ARM64_SYSREG_MPAMVPM3_EL2 = AArch64_SYSREG_MPAMVPM3_EL2, + ARM64_SYSREG_MPAMVPM4_EL2 = AArch64_SYSREG_MPAMVPM4_EL2, + ARM64_SYSREG_MPAMVPM5_EL2 = AArch64_SYSREG_MPAMVPM5_EL2, + ARM64_SYSREG_MPAMVPM6_EL2 = AArch64_SYSREG_MPAMVPM6_EL2, + ARM64_SYSREG_MPAMVPM7_EL2 = AArch64_SYSREG_MPAMVPM7_EL2, + ARM64_SYSREG_MPAMVPMV_EL2 = AArch64_SYSREG_MPAMVPMV_EL2, + ARM64_SYSREG_MPIDR_EL1 = AArch64_SYSREG_MPIDR_EL1, + ARM64_SYSREG_MPUIR_EL1 = AArch64_SYSREG_MPUIR_EL1, + ARM64_SYSREG_MPUIR_EL2 = AArch64_SYSREG_MPUIR_EL2, + ARM64_SYSREG_MVFR0_EL1 = AArch64_SYSREG_MVFR0_EL1, + ARM64_SYSREG_MVFR1_EL1 = AArch64_SYSREG_MVFR1_EL1, + ARM64_SYSREG_MVFR2_EL1 = AArch64_SYSREG_MVFR2_EL1, + ARM64_SYSREG_NZCV = AArch64_SYSREG_NZCV, + ARM64_SYSREG_OSDLR_EL1 = AArch64_SYSREG_OSDLR_EL1, + ARM64_SYSREG_OSDTRRX_EL1 = AArch64_SYSREG_OSDTRRX_EL1, + ARM64_SYSREG_OSDTRTX_EL1 = AArch64_SYSREG_OSDTRTX_EL1, + ARM64_SYSREG_OSECCR_EL1 = AArch64_SYSREG_OSECCR_EL1, + ARM64_SYSREG_OSLAR_EL1 = AArch64_SYSREG_OSLAR_EL1, + ARM64_SYSREG_OSLSR_EL1 = AArch64_SYSREG_OSLSR_EL1, + ARM64_SYSREG_PAN = AArch64_SYSREG_PAN, + ARM64_SYSREG_PAR_EL1 = AArch64_SYSREG_PAR_EL1, + ARM64_SYSREG_PFAR_EL1 = AArch64_SYSREG_PFAR_EL1, + ARM64_SYSREG_PFAR_EL12 = AArch64_SYSREG_PFAR_EL12, + ARM64_SYSREG_PFAR_EL2 = AArch64_SYSREG_PFAR_EL2, + ARM64_SYSREG_PIRE0_EL1 = AArch64_SYSREG_PIRE0_EL1, + ARM64_SYSREG_PIRE0_EL12 = AArch64_SYSREG_PIRE0_EL12, + ARM64_SYSREG_PIRE0_EL2 = AArch64_SYSREG_PIRE0_EL2, + ARM64_SYSREG_PIR_EL1 = AArch64_SYSREG_PIR_EL1, + ARM64_SYSREG_PIR_EL12 = AArch64_SYSREG_PIR_EL12, + ARM64_SYSREG_PIR_EL2 = AArch64_SYSREG_PIR_EL2, + ARM64_SYSREG_PIR_EL3 = AArch64_SYSREG_PIR_EL3, + ARM64_SYSREG_PM = AArch64_SYSREG_PM, + ARM64_SYSREG_PMBIDR_EL1 = AArch64_SYSREG_PMBIDR_EL1, + ARM64_SYSREG_PMBLIMITR_EL1 = AArch64_SYSREG_PMBLIMITR_EL1, + ARM64_SYSREG_PMBPTR_EL1 = AArch64_SYSREG_PMBPTR_EL1, + ARM64_SYSREG_PMBSR_EL1 = AArch64_SYSREG_PMBSR_EL1, + ARM64_SYSREG_PMCCFILTR_EL0 = AArch64_SYSREG_PMCCFILTR_EL0, + ARM64_SYSREG_PMCCNTR_EL0 = AArch64_SYSREG_PMCCNTR_EL0, + ARM64_SYSREG_PMCCNTSVR_EL1 = AArch64_SYSREG_PMCCNTSVR_EL1, + ARM64_SYSREG_PMCEID0_EL0 = AArch64_SYSREG_PMCEID0_EL0, + ARM64_SYSREG_PMCEID1_EL0 = AArch64_SYSREG_PMCEID1_EL0, + ARM64_SYSREG_PMCNTENCLR_EL0 = AArch64_SYSREG_PMCNTENCLR_EL0, + ARM64_SYSREG_PMCNTENSET_EL0 = AArch64_SYSREG_PMCNTENSET_EL0, + ARM64_SYSREG_PMCR_EL0 = AArch64_SYSREG_PMCR_EL0, + ARM64_SYSREG_PMECR_EL1 = AArch64_SYSREG_PMECR_EL1, + ARM64_SYSREG_PMEVCNTR0_EL0 = AArch64_SYSREG_PMEVCNTR0_EL0, + ARM64_SYSREG_PMEVCNTR10_EL0 = AArch64_SYSREG_PMEVCNTR10_EL0, + ARM64_SYSREG_PMEVCNTR11_EL0 = AArch64_SYSREG_PMEVCNTR11_EL0, + ARM64_SYSREG_PMEVCNTR12_EL0 = AArch64_SYSREG_PMEVCNTR12_EL0, + ARM64_SYSREG_PMEVCNTR13_EL0 = AArch64_SYSREG_PMEVCNTR13_EL0, + ARM64_SYSREG_PMEVCNTR14_EL0 = AArch64_SYSREG_PMEVCNTR14_EL0, + ARM64_SYSREG_PMEVCNTR15_EL0 = AArch64_SYSREG_PMEVCNTR15_EL0, + ARM64_SYSREG_PMEVCNTR16_EL0 = AArch64_SYSREG_PMEVCNTR16_EL0, + ARM64_SYSREG_PMEVCNTR17_EL0 = AArch64_SYSREG_PMEVCNTR17_EL0, + ARM64_SYSREG_PMEVCNTR18_EL0 = AArch64_SYSREG_PMEVCNTR18_EL0, + ARM64_SYSREG_PMEVCNTR19_EL0 = AArch64_SYSREG_PMEVCNTR19_EL0, + ARM64_SYSREG_PMEVCNTR1_EL0 = AArch64_SYSREG_PMEVCNTR1_EL0, + ARM64_SYSREG_PMEVCNTR20_EL0 = AArch64_SYSREG_PMEVCNTR20_EL0, + ARM64_SYSREG_PMEVCNTR21_EL0 = AArch64_SYSREG_PMEVCNTR21_EL0, + ARM64_SYSREG_PMEVCNTR22_EL0 = AArch64_SYSREG_PMEVCNTR22_EL0, + ARM64_SYSREG_PMEVCNTR23_EL0 = AArch64_SYSREG_PMEVCNTR23_EL0, + ARM64_SYSREG_PMEVCNTR24_EL0 = AArch64_SYSREG_PMEVCNTR24_EL0, + ARM64_SYSREG_PMEVCNTR25_EL0 = AArch64_SYSREG_PMEVCNTR25_EL0, + ARM64_SYSREG_PMEVCNTR26_EL0 = AArch64_SYSREG_PMEVCNTR26_EL0, + ARM64_SYSREG_PMEVCNTR27_EL0 = AArch64_SYSREG_PMEVCNTR27_EL0, + ARM64_SYSREG_PMEVCNTR28_EL0 = AArch64_SYSREG_PMEVCNTR28_EL0, + ARM64_SYSREG_PMEVCNTR29_EL0 = AArch64_SYSREG_PMEVCNTR29_EL0, + ARM64_SYSREG_PMEVCNTR2_EL0 = AArch64_SYSREG_PMEVCNTR2_EL0, + ARM64_SYSREG_PMEVCNTR30_EL0 = AArch64_SYSREG_PMEVCNTR30_EL0, + ARM64_SYSREG_PMEVCNTR3_EL0 = AArch64_SYSREG_PMEVCNTR3_EL0, + ARM64_SYSREG_PMEVCNTR4_EL0 = AArch64_SYSREG_PMEVCNTR4_EL0, + ARM64_SYSREG_PMEVCNTR5_EL0 = AArch64_SYSREG_PMEVCNTR5_EL0, + ARM64_SYSREG_PMEVCNTR6_EL0 = AArch64_SYSREG_PMEVCNTR6_EL0, + ARM64_SYSREG_PMEVCNTR7_EL0 = AArch64_SYSREG_PMEVCNTR7_EL0, + ARM64_SYSREG_PMEVCNTR8_EL0 = AArch64_SYSREG_PMEVCNTR8_EL0, + ARM64_SYSREG_PMEVCNTR9_EL0 = AArch64_SYSREG_PMEVCNTR9_EL0, + ARM64_SYSREG_PMEVCNTSVR0_EL1 = AArch64_SYSREG_PMEVCNTSVR0_EL1, + ARM64_SYSREG_PMEVCNTSVR10_EL1 = AArch64_SYSREG_PMEVCNTSVR10_EL1, + ARM64_SYSREG_PMEVCNTSVR11_EL1 = AArch64_SYSREG_PMEVCNTSVR11_EL1, + ARM64_SYSREG_PMEVCNTSVR12_EL1 = AArch64_SYSREG_PMEVCNTSVR12_EL1, + ARM64_SYSREG_PMEVCNTSVR13_EL1 = AArch64_SYSREG_PMEVCNTSVR13_EL1, + ARM64_SYSREG_PMEVCNTSVR14_EL1 = AArch64_SYSREG_PMEVCNTSVR14_EL1, + ARM64_SYSREG_PMEVCNTSVR15_EL1 = AArch64_SYSREG_PMEVCNTSVR15_EL1, + ARM64_SYSREG_PMEVCNTSVR16_EL1 = AArch64_SYSREG_PMEVCNTSVR16_EL1, + ARM64_SYSREG_PMEVCNTSVR17_EL1 = AArch64_SYSREG_PMEVCNTSVR17_EL1, + ARM64_SYSREG_PMEVCNTSVR18_EL1 = AArch64_SYSREG_PMEVCNTSVR18_EL1, + ARM64_SYSREG_PMEVCNTSVR19_EL1 = AArch64_SYSREG_PMEVCNTSVR19_EL1, + ARM64_SYSREG_PMEVCNTSVR1_EL1 = AArch64_SYSREG_PMEVCNTSVR1_EL1, + ARM64_SYSREG_PMEVCNTSVR20_EL1 = AArch64_SYSREG_PMEVCNTSVR20_EL1, + ARM64_SYSREG_PMEVCNTSVR21_EL1 = AArch64_SYSREG_PMEVCNTSVR21_EL1, + ARM64_SYSREG_PMEVCNTSVR22_EL1 = AArch64_SYSREG_PMEVCNTSVR22_EL1, + ARM64_SYSREG_PMEVCNTSVR23_EL1 = AArch64_SYSREG_PMEVCNTSVR23_EL1, + ARM64_SYSREG_PMEVCNTSVR24_EL1 = AArch64_SYSREG_PMEVCNTSVR24_EL1, + ARM64_SYSREG_PMEVCNTSVR25_EL1 = AArch64_SYSREG_PMEVCNTSVR25_EL1, + ARM64_SYSREG_PMEVCNTSVR26_EL1 = AArch64_SYSREG_PMEVCNTSVR26_EL1, + ARM64_SYSREG_PMEVCNTSVR27_EL1 = AArch64_SYSREG_PMEVCNTSVR27_EL1, + ARM64_SYSREG_PMEVCNTSVR28_EL1 = AArch64_SYSREG_PMEVCNTSVR28_EL1, + ARM64_SYSREG_PMEVCNTSVR29_EL1 = AArch64_SYSREG_PMEVCNTSVR29_EL1, + ARM64_SYSREG_PMEVCNTSVR2_EL1 = AArch64_SYSREG_PMEVCNTSVR2_EL1, + ARM64_SYSREG_PMEVCNTSVR30_EL1 = AArch64_SYSREG_PMEVCNTSVR30_EL1, + ARM64_SYSREG_PMEVCNTSVR3_EL1 = AArch64_SYSREG_PMEVCNTSVR3_EL1, + ARM64_SYSREG_PMEVCNTSVR4_EL1 = AArch64_SYSREG_PMEVCNTSVR4_EL1, + ARM64_SYSREG_PMEVCNTSVR5_EL1 = AArch64_SYSREG_PMEVCNTSVR5_EL1, + ARM64_SYSREG_PMEVCNTSVR6_EL1 = AArch64_SYSREG_PMEVCNTSVR6_EL1, + ARM64_SYSREG_PMEVCNTSVR7_EL1 = AArch64_SYSREG_PMEVCNTSVR7_EL1, + ARM64_SYSREG_PMEVCNTSVR8_EL1 = AArch64_SYSREG_PMEVCNTSVR8_EL1, + ARM64_SYSREG_PMEVCNTSVR9_EL1 = AArch64_SYSREG_PMEVCNTSVR9_EL1, + ARM64_SYSREG_PMEVTYPER0_EL0 = AArch64_SYSREG_PMEVTYPER0_EL0, + ARM64_SYSREG_PMEVTYPER10_EL0 = AArch64_SYSREG_PMEVTYPER10_EL0, + ARM64_SYSREG_PMEVTYPER11_EL0 = AArch64_SYSREG_PMEVTYPER11_EL0, + ARM64_SYSREG_PMEVTYPER12_EL0 = AArch64_SYSREG_PMEVTYPER12_EL0, + ARM64_SYSREG_PMEVTYPER13_EL0 = AArch64_SYSREG_PMEVTYPER13_EL0, + ARM64_SYSREG_PMEVTYPER14_EL0 = AArch64_SYSREG_PMEVTYPER14_EL0, + ARM64_SYSREG_PMEVTYPER15_EL0 = AArch64_SYSREG_PMEVTYPER15_EL0, + ARM64_SYSREG_PMEVTYPER16_EL0 = AArch64_SYSREG_PMEVTYPER16_EL0, + ARM64_SYSREG_PMEVTYPER17_EL0 = AArch64_SYSREG_PMEVTYPER17_EL0, + ARM64_SYSREG_PMEVTYPER18_EL0 = AArch64_SYSREG_PMEVTYPER18_EL0, + ARM64_SYSREG_PMEVTYPER19_EL0 = AArch64_SYSREG_PMEVTYPER19_EL0, + ARM64_SYSREG_PMEVTYPER1_EL0 = AArch64_SYSREG_PMEVTYPER1_EL0, + ARM64_SYSREG_PMEVTYPER20_EL0 = AArch64_SYSREG_PMEVTYPER20_EL0, + ARM64_SYSREG_PMEVTYPER21_EL0 = AArch64_SYSREG_PMEVTYPER21_EL0, + ARM64_SYSREG_PMEVTYPER22_EL0 = AArch64_SYSREG_PMEVTYPER22_EL0, + ARM64_SYSREG_PMEVTYPER23_EL0 = AArch64_SYSREG_PMEVTYPER23_EL0, + ARM64_SYSREG_PMEVTYPER24_EL0 = AArch64_SYSREG_PMEVTYPER24_EL0, + ARM64_SYSREG_PMEVTYPER25_EL0 = AArch64_SYSREG_PMEVTYPER25_EL0, + ARM64_SYSREG_PMEVTYPER26_EL0 = AArch64_SYSREG_PMEVTYPER26_EL0, + ARM64_SYSREG_PMEVTYPER27_EL0 = AArch64_SYSREG_PMEVTYPER27_EL0, + ARM64_SYSREG_PMEVTYPER28_EL0 = AArch64_SYSREG_PMEVTYPER28_EL0, + ARM64_SYSREG_PMEVTYPER29_EL0 = AArch64_SYSREG_PMEVTYPER29_EL0, + ARM64_SYSREG_PMEVTYPER2_EL0 = AArch64_SYSREG_PMEVTYPER2_EL0, + ARM64_SYSREG_PMEVTYPER30_EL0 = AArch64_SYSREG_PMEVTYPER30_EL0, + ARM64_SYSREG_PMEVTYPER3_EL0 = AArch64_SYSREG_PMEVTYPER3_EL0, + ARM64_SYSREG_PMEVTYPER4_EL0 = AArch64_SYSREG_PMEVTYPER4_EL0, + ARM64_SYSREG_PMEVTYPER5_EL0 = AArch64_SYSREG_PMEVTYPER5_EL0, + ARM64_SYSREG_PMEVTYPER6_EL0 = AArch64_SYSREG_PMEVTYPER6_EL0, + ARM64_SYSREG_PMEVTYPER7_EL0 = AArch64_SYSREG_PMEVTYPER7_EL0, + ARM64_SYSREG_PMEVTYPER8_EL0 = AArch64_SYSREG_PMEVTYPER8_EL0, + ARM64_SYSREG_PMEVTYPER9_EL0 = AArch64_SYSREG_PMEVTYPER9_EL0, + ARM64_SYSREG_PMIAR_EL1 = AArch64_SYSREG_PMIAR_EL1, + ARM64_SYSREG_PMICFILTR_EL0 = AArch64_SYSREG_PMICFILTR_EL0, + ARM64_SYSREG_PMICNTR_EL0 = AArch64_SYSREG_PMICNTR_EL0, + ARM64_SYSREG_PMICNTSVR_EL1 = AArch64_SYSREG_PMICNTSVR_EL1, + ARM64_SYSREG_PMINTENCLR_EL1 = AArch64_SYSREG_PMINTENCLR_EL1, + ARM64_SYSREG_PMINTENSET_EL1 = AArch64_SYSREG_PMINTENSET_EL1, + ARM64_SYSREG_PMMIR_EL1 = AArch64_SYSREG_PMMIR_EL1, + ARM64_SYSREG_PMOVSCLR_EL0 = AArch64_SYSREG_PMOVSCLR_EL0, + ARM64_SYSREG_PMOVSSET_EL0 = AArch64_SYSREG_PMOVSSET_EL0, + ARM64_SYSREG_PMSCR_EL1 = AArch64_SYSREG_PMSCR_EL1, + ARM64_SYSREG_PMSCR_EL12 = AArch64_SYSREG_PMSCR_EL12, + ARM64_SYSREG_PMSCR_EL2 = AArch64_SYSREG_PMSCR_EL2, + ARM64_SYSREG_PMSDSFR_EL1 = AArch64_SYSREG_PMSDSFR_EL1, + ARM64_SYSREG_PMSELR_EL0 = AArch64_SYSREG_PMSELR_EL0, + ARM64_SYSREG_PMSEVFR_EL1 = AArch64_SYSREG_PMSEVFR_EL1, + ARM64_SYSREG_PMSFCR_EL1 = AArch64_SYSREG_PMSFCR_EL1, + ARM64_SYSREG_PMSICR_EL1 = AArch64_SYSREG_PMSICR_EL1, + ARM64_SYSREG_PMSIDR_EL1 = AArch64_SYSREG_PMSIDR_EL1, + ARM64_SYSREG_PMSIRR_EL1 = AArch64_SYSREG_PMSIRR_EL1, + ARM64_SYSREG_PMSLATFR_EL1 = AArch64_SYSREG_PMSLATFR_EL1, + ARM64_SYSREG_PMSNEVFR_EL1 = AArch64_SYSREG_PMSNEVFR_EL1, + ARM64_SYSREG_PMSSCR_EL1 = AArch64_SYSREG_PMSSCR_EL1, + ARM64_SYSREG_PMSWINC_EL0 = AArch64_SYSREG_PMSWINC_EL0, + ARM64_SYSREG_PMUACR_EL1 = AArch64_SYSREG_PMUACR_EL1, + ARM64_SYSREG_PMUSERENR_EL0 = AArch64_SYSREG_PMUSERENR_EL0, + ARM64_SYSREG_PMXEVCNTR_EL0 = AArch64_SYSREG_PMXEVCNTR_EL0, + ARM64_SYSREG_PMXEVTYPER_EL0 = AArch64_SYSREG_PMXEVTYPER_EL0, + ARM64_SYSREG_PMZR_EL0 = AArch64_SYSREG_PMZR_EL0, + ARM64_SYSREG_POR_EL0 = AArch64_SYSREG_POR_EL0, + ARM64_SYSREG_POR_EL1 = AArch64_SYSREG_POR_EL1, + ARM64_SYSREG_POR_EL12 = AArch64_SYSREG_POR_EL12, + ARM64_SYSREG_POR_EL2 = AArch64_SYSREG_POR_EL2, + ARM64_SYSREG_POR_EL3 = AArch64_SYSREG_POR_EL3, + ARM64_SYSREG_PRBAR10_EL1 = AArch64_SYSREG_PRBAR10_EL1, + ARM64_SYSREG_PRBAR10_EL2 = AArch64_SYSREG_PRBAR10_EL2, + ARM64_SYSREG_PRBAR11_EL1 = AArch64_SYSREG_PRBAR11_EL1, + ARM64_SYSREG_PRBAR11_EL2 = AArch64_SYSREG_PRBAR11_EL2, + ARM64_SYSREG_PRBAR12_EL1 = AArch64_SYSREG_PRBAR12_EL1, + ARM64_SYSREG_PRBAR12_EL2 = AArch64_SYSREG_PRBAR12_EL2, + ARM64_SYSREG_PRBAR13_EL1 = AArch64_SYSREG_PRBAR13_EL1, + ARM64_SYSREG_PRBAR13_EL2 = AArch64_SYSREG_PRBAR13_EL2, + ARM64_SYSREG_PRBAR14_EL1 = AArch64_SYSREG_PRBAR14_EL1, + ARM64_SYSREG_PRBAR14_EL2 = AArch64_SYSREG_PRBAR14_EL2, + ARM64_SYSREG_PRBAR15_EL1 = AArch64_SYSREG_PRBAR15_EL1, + ARM64_SYSREG_PRBAR15_EL2 = AArch64_SYSREG_PRBAR15_EL2, + ARM64_SYSREG_PRBAR1_EL1 = AArch64_SYSREG_PRBAR1_EL1, + ARM64_SYSREG_PRBAR1_EL2 = AArch64_SYSREG_PRBAR1_EL2, + ARM64_SYSREG_PRBAR2_EL1 = AArch64_SYSREG_PRBAR2_EL1, + ARM64_SYSREG_PRBAR2_EL2 = AArch64_SYSREG_PRBAR2_EL2, + ARM64_SYSREG_PRBAR3_EL1 = AArch64_SYSREG_PRBAR3_EL1, + ARM64_SYSREG_PRBAR3_EL2 = AArch64_SYSREG_PRBAR3_EL2, + ARM64_SYSREG_PRBAR4_EL1 = AArch64_SYSREG_PRBAR4_EL1, + ARM64_SYSREG_PRBAR4_EL2 = AArch64_SYSREG_PRBAR4_EL2, + ARM64_SYSREG_PRBAR5_EL1 = AArch64_SYSREG_PRBAR5_EL1, + ARM64_SYSREG_PRBAR5_EL2 = AArch64_SYSREG_PRBAR5_EL2, + ARM64_SYSREG_PRBAR6_EL1 = AArch64_SYSREG_PRBAR6_EL1, + ARM64_SYSREG_PRBAR6_EL2 = AArch64_SYSREG_PRBAR6_EL2, + ARM64_SYSREG_PRBAR7_EL1 = AArch64_SYSREG_PRBAR7_EL1, + ARM64_SYSREG_PRBAR7_EL2 = AArch64_SYSREG_PRBAR7_EL2, + ARM64_SYSREG_PRBAR8_EL1 = AArch64_SYSREG_PRBAR8_EL1, + ARM64_SYSREG_PRBAR8_EL2 = AArch64_SYSREG_PRBAR8_EL2, + ARM64_SYSREG_PRBAR9_EL1 = AArch64_SYSREG_PRBAR9_EL1, + ARM64_SYSREG_PRBAR9_EL2 = AArch64_SYSREG_PRBAR9_EL2, + ARM64_SYSREG_PRBAR_EL1 = AArch64_SYSREG_PRBAR_EL1, + ARM64_SYSREG_PRBAR_EL2 = AArch64_SYSREG_PRBAR_EL2, + ARM64_SYSREG_PRENR_EL1 = AArch64_SYSREG_PRENR_EL1, + ARM64_SYSREG_PRENR_EL2 = AArch64_SYSREG_PRENR_EL2, + ARM64_SYSREG_PRLAR10_EL1 = AArch64_SYSREG_PRLAR10_EL1, + ARM64_SYSREG_PRLAR10_EL2 = AArch64_SYSREG_PRLAR10_EL2, + ARM64_SYSREG_PRLAR11_EL1 = AArch64_SYSREG_PRLAR11_EL1, + ARM64_SYSREG_PRLAR11_EL2 = AArch64_SYSREG_PRLAR11_EL2, + ARM64_SYSREG_PRLAR12_EL1 = AArch64_SYSREG_PRLAR12_EL1, + ARM64_SYSREG_PRLAR12_EL2 = AArch64_SYSREG_PRLAR12_EL2, + ARM64_SYSREG_PRLAR13_EL1 = AArch64_SYSREG_PRLAR13_EL1, + ARM64_SYSREG_PRLAR13_EL2 = AArch64_SYSREG_PRLAR13_EL2, + ARM64_SYSREG_PRLAR14_EL1 = AArch64_SYSREG_PRLAR14_EL1, + ARM64_SYSREG_PRLAR14_EL2 = AArch64_SYSREG_PRLAR14_EL2, + ARM64_SYSREG_PRLAR15_EL1 = AArch64_SYSREG_PRLAR15_EL1, + ARM64_SYSREG_PRLAR15_EL2 = AArch64_SYSREG_PRLAR15_EL2, + ARM64_SYSREG_PRLAR1_EL1 = AArch64_SYSREG_PRLAR1_EL1, + ARM64_SYSREG_PRLAR1_EL2 = AArch64_SYSREG_PRLAR1_EL2, + ARM64_SYSREG_PRLAR2_EL1 = AArch64_SYSREG_PRLAR2_EL1, + ARM64_SYSREG_PRLAR2_EL2 = AArch64_SYSREG_PRLAR2_EL2, + ARM64_SYSREG_PRLAR3_EL1 = AArch64_SYSREG_PRLAR3_EL1, + ARM64_SYSREG_PRLAR3_EL2 = AArch64_SYSREG_PRLAR3_EL2, + ARM64_SYSREG_PRLAR4_EL1 = AArch64_SYSREG_PRLAR4_EL1, + ARM64_SYSREG_PRLAR4_EL2 = AArch64_SYSREG_PRLAR4_EL2, + ARM64_SYSREG_PRLAR5_EL1 = AArch64_SYSREG_PRLAR5_EL1, + ARM64_SYSREG_PRLAR5_EL2 = AArch64_SYSREG_PRLAR5_EL2, + ARM64_SYSREG_PRLAR6_EL1 = AArch64_SYSREG_PRLAR6_EL1, + ARM64_SYSREG_PRLAR6_EL2 = AArch64_SYSREG_PRLAR6_EL2, + ARM64_SYSREG_PRLAR7_EL1 = AArch64_SYSREG_PRLAR7_EL1, + ARM64_SYSREG_PRLAR7_EL2 = AArch64_SYSREG_PRLAR7_EL2, + ARM64_SYSREG_PRLAR8_EL1 = AArch64_SYSREG_PRLAR8_EL1, + ARM64_SYSREG_PRLAR8_EL2 = AArch64_SYSREG_PRLAR8_EL2, + ARM64_SYSREG_PRLAR9_EL1 = AArch64_SYSREG_PRLAR9_EL1, + ARM64_SYSREG_PRLAR9_EL2 = AArch64_SYSREG_PRLAR9_EL2, + ARM64_SYSREG_PRLAR_EL1 = AArch64_SYSREG_PRLAR_EL1, + ARM64_SYSREG_PRLAR_EL2 = AArch64_SYSREG_PRLAR_EL2, + ARM64_SYSREG_PRSELR_EL1 = AArch64_SYSREG_PRSELR_EL1, + ARM64_SYSREG_PRSELR_EL2 = AArch64_SYSREG_PRSELR_EL2, + ARM64_SYSREG_RCWMASK_EL1 = AArch64_SYSREG_RCWMASK_EL1, + ARM64_SYSREG_RCWSMASK_EL1 = AArch64_SYSREG_RCWSMASK_EL1, + ARM64_SYSREG_REVIDR_EL1 = AArch64_SYSREG_REVIDR_EL1, + ARM64_SYSREG_RGSR_EL1 = AArch64_SYSREG_RGSR_EL1, + ARM64_SYSREG_RMR_EL1 = AArch64_SYSREG_RMR_EL1, + ARM64_SYSREG_RMR_EL2 = AArch64_SYSREG_RMR_EL2, + ARM64_SYSREG_RMR_EL3 = AArch64_SYSREG_RMR_EL3, + ARM64_SYSREG_RNDR = AArch64_SYSREG_RNDR, + ARM64_SYSREG_RNDRRS = AArch64_SYSREG_RNDRRS, + ARM64_SYSREG_RVBAR_EL1 = AArch64_SYSREG_RVBAR_EL1, + ARM64_SYSREG_RVBAR_EL2 = AArch64_SYSREG_RVBAR_EL2, + ARM64_SYSREG_RVBAR_EL3 = AArch64_SYSREG_RVBAR_EL3, + ARM64_SYSREG_S2PIR_EL2 = AArch64_SYSREG_S2PIR_EL2, + ARM64_SYSREG_S2POR_EL1 = AArch64_SYSREG_S2POR_EL1, + ARM64_SYSREG_SCR_EL3 = AArch64_SYSREG_SCR_EL3, + ARM64_SYSREG_SCTLR2_EL1 = AArch64_SYSREG_SCTLR2_EL1, + ARM64_SYSREG_SCTLR2_EL12 = AArch64_SYSREG_SCTLR2_EL12, + ARM64_SYSREG_SCTLR2_EL2 = AArch64_SYSREG_SCTLR2_EL2, + ARM64_SYSREG_SCTLR2_EL3 = AArch64_SYSREG_SCTLR2_EL3, + ARM64_SYSREG_SCTLR_EL1 = AArch64_SYSREG_SCTLR_EL1, + ARM64_SYSREG_SCTLR_EL12 = AArch64_SYSREG_SCTLR_EL12, + ARM64_SYSREG_SCTLR_EL2 = AArch64_SYSREG_SCTLR_EL2, + ARM64_SYSREG_SCTLR_EL3 = AArch64_SYSREG_SCTLR_EL3, + ARM64_SYSREG_SCXTNUM_EL0 = AArch64_SYSREG_SCXTNUM_EL0, + ARM64_SYSREG_SCXTNUM_EL1 = AArch64_SYSREG_SCXTNUM_EL1, + ARM64_SYSREG_SCXTNUM_EL12 = AArch64_SYSREG_SCXTNUM_EL12, + ARM64_SYSREG_SCXTNUM_EL2 = AArch64_SYSREG_SCXTNUM_EL2, + ARM64_SYSREG_SCXTNUM_EL3 = AArch64_SYSREG_SCXTNUM_EL3, + ARM64_SYSREG_SDER32_EL2 = AArch64_SYSREG_SDER32_EL2, + ARM64_SYSREG_SDER32_EL3 = AArch64_SYSREG_SDER32_EL3, + ARM64_SYSREG_SMCR_EL1 = AArch64_SYSREG_SMCR_EL1, + ARM64_SYSREG_SMCR_EL12 = AArch64_SYSREG_SMCR_EL12, + ARM64_SYSREG_SMCR_EL2 = AArch64_SYSREG_SMCR_EL2, + ARM64_SYSREG_SMCR_EL3 = AArch64_SYSREG_SMCR_EL3, + ARM64_SYSREG_SMIDR_EL1 = AArch64_SYSREG_SMIDR_EL1, + ARM64_SYSREG_SMPRIMAP_EL2 = AArch64_SYSREG_SMPRIMAP_EL2, + ARM64_SYSREG_SMPRI_EL1 = AArch64_SYSREG_SMPRI_EL1, + ARM64_SYSREG_SPMACCESSR_EL1 = AArch64_SYSREG_SPMACCESSR_EL1, + ARM64_SYSREG_SPMACCESSR_EL12 = AArch64_SYSREG_SPMACCESSR_EL12, + ARM64_SYSREG_SPMACCESSR_EL2 = AArch64_SYSREG_SPMACCESSR_EL2, + ARM64_SYSREG_SPMACCESSR_EL3 = AArch64_SYSREG_SPMACCESSR_EL3, + ARM64_SYSREG_SPMCFGR_EL1 = AArch64_SYSREG_SPMCFGR_EL1, + ARM64_SYSREG_SPMCGCR0_EL1 = AArch64_SYSREG_SPMCGCR0_EL1, + ARM64_SYSREG_SPMCGCR1_EL1 = AArch64_SYSREG_SPMCGCR1_EL1, + ARM64_SYSREG_SPMCNTENCLR_EL0 = AArch64_SYSREG_SPMCNTENCLR_EL0, + ARM64_SYSREG_SPMCNTENSET_EL0 = AArch64_SYSREG_SPMCNTENSET_EL0, + ARM64_SYSREG_SPMCR_EL0 = AArch64_SYSREG_SPMCR_EL0, + ARM64_SYSREG_SPMDEVAFF_EL1 = AArch64_SYSREG_SPMDEVAFF_EL1, + ARM64_SYSREG_SPMDEVARCH_EL1 = AArch64_SYSREG_SPMDEVARCH_EL1, + ARM64_SYSREG_SPMEVCNTR0_EL0 = AArch64_SYSREG_SPMEVCNTR0_EL0, + ARM64_SYSREG_SPMEVCNTR10_EL0 = AArch64_SYSREG_SPMEVCNTR10_EL0, + ARM64_SYSREG_SPMEVCNTR11_EL0 = AArch64_SYSREG_SPMEVCNTR11_EL0, + ARM64_SYSREG_SPMEVCNTR12_EL0 = AArch64_SYSREG_SPMEVCNTR12_EL0, + ARM64_SYSREG_SPMEVCNTR13_EL0 = AArch64_SYSREG_SPMEVCNTR13_EL0, + ARM64_SYSREG_SPMEVCNTR14_EL0 = AArch64_SYSREG_SPMEVCNTR14_EL0, + ARM64_SYSREG_SPMEVCNTR15_EL0 = AArch64_SYSREG_SPMEVCNTR15_EL0, + ARM64_SYSREG_SPMEVCNTR1_EL0 = AArch64_SYSREG_SPMEVCNTR1_EL0, + ARM64_SYSREG_SPMEVCNTR2_EL0 = AArch64_SYSREG_SPMEVCNTR2_EL0, + ARM64_SYSREG_SPMEVCNTR3_EL0 = AArch64_SYSREG_SPMEVCNTR3_EL0, + ARM64_SYSREG_SPMEVCNTR4_EL0 = AArch64_SYSREG_SPMEVCNTR4_EL0, + ARM64_SYSREG_SPMEVCNTR5_EL0 = AArch64_SYSREG_SPMEVCNTR5_EL0, + ARM64_SYSREG_SPMEVCNTR6_EL0 = AArch64_SYSREG_SPMEVCNTR6_EL0, + ARM64_SYSREG_SPMEVCNTR7_EL0 = AArch64_SYSREG_SPMEVCNTR7_EL0, + ARM64_SYSREG_SPMEVCNTR8_EL0 = AArch64_SYSREG_SPMEVCNTR8_EL0, + ARM64_SYSREG_SPMEVCNTR9_EL0 = AArch64_SYSREG_SPMEVCNTR9_EL0, + ARM64_SYSREG_SPMEVFILT2R0_EL0 = AArch64_SYSREG_SPMEVFILT2R0_EL0, + ARM64_SYSREG_SPMEVFILT2R10_EL0 = AArch64_SYSREG_SPMEVFILT2R10_EL0, + ARM64_SYSREG_SPMEVFILT2R11_EL0 = AArch64_SYSREG_SPMEVFILT2R11_EL0, + ARM64_SYSREG_SPMEVFILT2R12_EL0 = AArch64_SYSREG_SPMEVFILT2R12_EL0, + ARM64_SYSREG_SPMEVFILT2R13_EL0 = AArch64_SYSREG_SPMEVFILT2R13_EL0, + ARM64_SYSREG_SPMEVFILT2R14_EL0 = AArch64_SYSREG_SPMEVFILT2R14_EL0, + ARM64_SYSREG_SPMEVFILT2R15_EL0 = AArch64_SYSREG_SPMEVFILT2R15_EL0, + ARM64_SYSREG_SPMEVFILT2R1_EL0 = AArch64_SYSREG_SPMEVFILT2R1_EL0, + ARM64_SYSREG_SPMEVFILT2R2_EL0 = AArch64_SYSREG_SPMEVFILT2R2_EL0, + ARM64_SYSREG_SPMEVFILT2R3_EL0 = AArch64_SYSREG_SPMEVFILT2R3_EL0, + ARM64_SYSREG_SPMEVFILT2R4_EL0 = AArch64_SYSREG_SPMEVFILT2R4_EL0, + ARM64_SYSREG_SPMEVFILT2R5_EL0 = AArch64_SYSREG_SPMEVFILT2R5_EL0, + ARM64_SYSREG_SPMEVFILT2R6_EL0 = AArch64_SYSREG_SPMEVFILT2R6_EL0, + ARM64_SYSREG_SPMEVFILT2R7_EL0 = AArch64_SYSREG_SPMEVFILT2R7_EL0, + ARM64_SYSREG_SPMEVFILT2R8_EL0 = AArch64_SYSREG_SPMEVFILT2R8_EL0, + ARM64_SYSREG_SPMEVFILT2R9_EL0 = AArch64_SYSREG_SPMEVFILT2R9_EL0, + ARM64_SYSREG_SPMEVFILTR0_EL0 = AArch64_SYSREG_SPMEVFILTR0_EL0, + ARM64_SYSREG_SPMEVFILTR10_EL0 = AArch64_SYSREG_SPMEVFILTR10_EL0, + ARM64_SYSREG_SPMEVFILTR11_EL0 = AArch64_SYSREG_SPMEVFILTR11_EL0, + ARM64_SYSREG_SPMEVFILTR12_EL0 = AArch64_SYSREG_SPMEVFILTR12_EL0, + ARM64_SYSREG_SPMEVFILTR13_EL0 = AArch64_SYSREG_SPMEVFILTR13_EL0, + ARM64_SYSREG_SPMEVFILTR14_EL0 = AArch64_SYSREG_SPMEVFILTR14_EL0, + ARM64_SYSREG_SPMEVFILTR15_EL0 = AArch64_SYSREG_SPMEVFILTR15_EL0, + ARM64_SYSREG_SPMEVFILTR1_EL0 = AArch64_SYSREG_SPMEVFILTR1_EL0, + ARM64_SYSREG_SPMEVFILTR2_EL0 = AArch64_SYSREG_SPMEVFILTR2_EL0, + ARM64_SYSREG_SPMEVFILTR3_EL0 = AArch64_SYSREG_SPMEVFILTR3_EL0, + ARM64_SYSREG_SPMEVFILTR4_EL0 = AArch64_SYSREG_SPMEVFILTR4_EL0, + ARM64_SYSREG_SPMEVFILTR5_EL0 = AArch64_SYSREG_SPMEVFILTR5_EL0, + ARM64_SYSREG_SPMEVFILTR6_EL0 = AArch64_SYSREG_SPMEVFILTR6_EL0, + ARM64_SYSREG_SPMEVFILTR7_EL0 = AArch64_SYSREG_SPMEVFILTR7_EL0, + ARM64_SYSREG_SPMEVFILTR8_EL0 = AArch64_SYSREG_SPMEVFILTR8_EL0, + ARM64_SYSREG_SPMEVFILTR9_EL0 = AArch64_SYSREG_SPMEVFILTR9_EL0, + ARM64_SYSREG_SPMEVTYPER0_EL0 = AArch64_SYSREG_SPMEVTYPER0_EL0, + ARM64_SYSREG_SPMEVTYPER10_EL0 = AArch64_SYSREG_SPMEVTYPER10_EL0, + ARM64_SYSREG_SPMEVTYPER11_EL0 = AArch64_SYSREG_SPMEVTYPER11_EL0, + ARM64_SYSREG_SPMEVTYPER12_EL0 = AArch64_SYSREG_SPMEVTYPER12_EL0, + ARM64_SYSREG_SPMEVTYPER13_EL0 = AArch64_SYSREG_SPMEVTYPER13_EL0, + ARM64_SYSREG_SPMEVTYPER14_EL0 = AArch64_SYSREG_SPMEVTYPER14_EL0, + ARM64_SYSREG_SPMEVTYPER15_EL0 = AArch64_SYSREG_SPMEVTYPER15_EL0, + ARM64_SYSREG_SPMEVTYPER1_EL0 = AArch64_SYSREG_SPMEVTYPER1_EL0, + ARM64_SYSREG_SPMEVTYPER2_EL0 = AArch64_SYSREG_SPMEVTYPER2_EL0, + ARM64_SYSREG_SPMEVTYPER3_EL0 = AArch64_SYSREG_SPMEVTYPER3_EL0, + ARM64_SYSREG_SPMEVTYPER4_EL0 = AArch64_SYSREG_SPMEVTYPER4_EL0, + ARM64_SYSREG_SPMEVTYPER5_EL0 = AArch64_SYSREG_SPMEVTYPER5_EL0, + ARM64_SYSREG_SPMEVTYPER6_EL0 = AArch64_SYSREG_SPMEVTYPER6_EL0, + ARM64_SYSREG_SPMEVTYPER7_EL0 = AArch64_SYSREG_SPMEVTYPER7_EL0, + ARM64_SYSREG_SPMEVTYPER8_EL0 = AArch64_SYSREG_SPMEVTYPER8_EL0, + ARM64_SYSREG_SPMEVTYPER9_EL0 = AArch64_SYSREG_SPMEVTYPER9_EL0, + ARM64_SYSREG_SPMIIDR_EL1 = AArch64_SYSREG_SPMIIDR_EL1, + ARM64_SYSREG_SPMINTENCLR_EL1 = AArch64_SYSREG_SPMINTENCLR_EL1, + ARM64_SYSREG_SPMINTENSET_EL1 = AArch64_SYSREG_SPMINTENSET_EL1, + ARM64_SYSREG_SPMOVSCLR_EL0 = AArch64_SYSREG_SPMOVSCLR_EL0, + ARM64_SYSREG_SPMOVSSET_EL0 = AArch64_SYSREG_SPMOVSSET_EL0, + ARM64_SYSREG_SPMROOTCR_EL3 = AArch64_SYSREG_SPMROOTCR_EL3, + ARM64_SYSREG_SPMSCR_EL1 = AArch64_SYSREG_SPMSCR_EL1, + ARM64_SYSREG_SPMSELR_EL0 = AArch64_SYSREG_SPMSELR_EL0, + ARM64_SYSREG_SPSEL = AArch64_SYSREG_SPSEL, + ARM64_SYSREG_SPSR_ABT = AArch64_SYSREG_SPSR_ABT, + ARM64_SYSREG_SPSR_EL1 = AArch64_SYSREG_SPSR_EL1, + ARM64_SYSREG_SPSR_EL12 = AArch64_SYSREG_SPSR_EL12, + ARM64_SYSREG_SPSR_EL2 = AArch64_SYSREG_SPSR_EL2, + ARM64_SYSREG_SPSR_EL3 = AArch64_SYSREG_SPSR_EL3, + ARM64_SYSREG_SPSR_FIQ = AArch64_SYSREG_SPSR_FIQ, + ARM64_SYSREG_SPSR_IRQ = AArch64_SYSREG_SPSR_IRQ, + ARM64_SYSREG_SPSR_UND = AArch64_SYSREG_SPSR_UND, + ARM64_SYSREG_SP_EL0 = AArch64_SYSREG_SP_EL0, + ARM64_SYSREG_SP_EL1 = AArch64_SYSREG_SP_EL1, + ARM64_SYSREG_SP_EL2 = AArch64_SYSREG_SP_EL2, + ARM64_SYSREG_SSBS = AArch64_SYSREG_SSBS, + ARM64_SYSREG_SVCR = AArch64_SYSREG_SVCR, + ARM64_SYSREG_TCO = AArch64_SYSREG_TCO, + ARM64_SYSREG_TCR2_EL1 = AArch64_SYSREG_TCR2_EL1, + ARM64_SYSREG_TCR2_EL12 = AArch64_SYSREG_TCR2_EL12, + ARM64_SYSREG_TCR2_EL2 = AArch64_SYSREG_TCR2_EL2, + ARM64_SYSREG_TCR_EL1 = AArch64_SYSREG_TCR_EL1, + ARM64_SYSREG_TCR_EL12 = AArch64_SYSREG_TCR_EL12, + ARM64_SYSREG_TCR_EL2 = AArch64_SYSREG_TCR_EL2, + ARM64_SYSREG_TCR_EL3 = AArch64_SYSREG_TCR_EL3, + ARM64_SYSREG_TEECR32_EL1 = AArch64_SYSREG_TEECR32_EL1, + ARM64_SYSREG_TEEHBR32_EL1 = AArch64_SYSREG_TEEHBR32_EL1, + ARM64_SYSREG_TFSRE0_EL1 = AArch64_SYSREG_TFSRE0_EL1, + ARM64_SYSREG_TFSR_EL1 = AArch64_SYSREG_TFSR_EL1, + ARM64_SYSREG_TFSR_EL12 = AArch64_SYSREG_TFSR_EL12, + ARM64_SYSREG_TFSR_EL2 = AArch64_SYSREG_TFSR_EL2, + ARM64_SYSREG_TFSR_EL3 = AArch64_SYSREG_TFSR_EL3, + ARM64_SYSREG_TPIDR2_EL0 = AArch64_SYSREG_TPIDR2_EL0, + ARM64_SYSREG_TPIDRRO_EL0 = AArch64_SYSREG_TPIDRRO_EL0, + ARM64_SYSREG_TPIDR_EL0 = AArch64_SYSREG_TPIDR_EL0, + ARM64_SYSREG_TPIDR_EL1 = AArch64_SYSREG_TPIDR_EL1, + ARM64_SYSREG_TPIDR_EL2 = AArch64_SYSREG_TPIDR_EL2, + ARM64_SYSREG_TPIDR_EL3 = AArch64_SYSREG_TPIDR_EL3, + ARM64_SYSREG_TRBBASER_EL1 = AArch64_SYSREG_TRBBASER_EL1, + ARM64_SYSREG_TRBIDR_EL1 = AArch64_SYSREG_TRBIDR_EL1, + ARM64_SYSREG_TRBLIMITR_EL1 = AArch64_SYSREG_TRBLIMITR_EL1, + ARM64_SYSREG_TRBMAR_EL1 = AArch64_SYSREG_TRBMAR_EL1, + ARM64_SYSREG_TRBPTR_EL1 = AArch64_SYSREG_TRBPTR_EL1, + ARM64_SYSREG_TRBSR_EL1 = AArch64_SYSREG_TRBSR_EL1, + ARM64_SYSREG_TRBTRG_EL1 = AArch64_SYSREG_TRBTRG_EL1, + ARM64_SYSREG_TRCACATR0 = AArch64_SYSREG_TRCACATR0, + ARM64_SYSREG_TRCACATR1 = AArch64_SYSREG_TRCACATR1, + ARM64_SYSREG_TRCACATR10 = AArch64_SYSREG_TRCACATR10, + ARM64_SYSREG_TRCACATR11 = AArch64_SYSREG_TRCACATR11, + ARM64_SYSREG_TRCACATR12 = AArch64_SYSREG_TRCACATR12, + ARM64_SYSREG_TRCACATR13 = AArch64_SYSREG_TRCACATR13, + ARM64_SYSREG_TRCACATR14 = AArch64_SYSREG_TRCACATR14, + ARM64_SYSREG_TRCACATR15 = AArch64_SYSREG_TRCACATR15, + ARM64_SYSREG_TRCACATR2 = AArch64_SYSREG_TRCACATR2, + ARM64_SYSREG_TRCACATR3 = AArch64_SYSREG_TRCACATR3, + ARM64_SYSREG_TRCACATR4 = AArch64_SYSREG_TRCACATR4, + ARM64_SYSREG_TRCACATR5 = AArch64_SYSREG_TRCACATR5, + ARM64_SYSREG_TRCACATR6 = AArch64_SYSREG_TRCACATR6, + ARM64_SYSREG_TRCACATR7 = AArch64_SYSREG_TRCACATR7, + ARM64_SYSREG_TRCACATR8 = AArch64_SYSREG_TRCACATR8, + ARM64_SYSREG_TRCACATR9 = AArch64_SYSREG_TRCACATR9, + ARM64_SYSREG_TRCACVR0 = AArch64_SYSREG_TRCACVR0, + ARM64_SYSREG_TRCACVR1 = AArch64_SYSREG_TRCACVR1, + ARM64_SYSREG_TRCACVR10 = AArch64_SYSREG_TRCACVR10, + ARM64_SYSREG_TRCACVR11 = AArch64_SYSREG_TRCACVR11, + ARM64_SYSREG_TRCACVR12 = AArch64_SYSREG_TRCACVR12, + ARM64_SYSREG_TRCACVR13 = AArch64_SYSREG_TRCACVR13, + ARM64_SYSREG_TRCACVR14 = AArch64_SYSREG_TRCACVR14, + ARM64_SYSREG_TRCACVR15 = AArch64_SYSREG_TRCACVR15, + ARM64_SYSREG_TRCACVR2 = AArch64_SYSREG_TRCACVR2, + ARM64_SYSREG_TRCACVR3 = AArch64_SYSREG_TRCACVR3, + ARM64_SYSREG_TRCACVR4 = AArch64_SYSREG_TRCACVR4, + ARM64_SYSREG_TRCACVR5 = AArch64_SYSREG_TRCACVR5, + ARM64_SYSREG_TRCACVR6 = AArch64_SYSREG_TRCACVR6, + ARM64_SYSREG_TRCACVR7 = AArch64_SYSREG_TRCACVR7, + ARM64_SYSREG_TRCACVR8 = AArch64_SYSREG_TRCACVR8, + ARM64_SYSREG_TRCACVR9 = AArch64_SYSREG_TRCACVR9, + ARM64_SYSREG_TRCAUTHSTATUS = AArch64_SYSREG_TRCAUTHSTATUS, + ARM64_SYSREG_TRCAUXCTLR = AArch64_SYSREG_TRCAUXCTLR, + ARM64_SYSREG_TRCBBCTLR = AArch64_SYSREG_TRCBBCTLR, + ARM64_SYSREG_TRCCCCTLR = AArch64_SYSREG_TRCCCCTLR, + ARM64_SYSREG_TRCCIDCCTLR0 = AArch64_SYSREG_TRCCIDCCTLR0, + ARM64_SYSREG_TRCCIDCCTLR1 = AArch64_SYSREG_TRCCIDCCTLR1, + ARM64_SYSREG_TRCCIDCVR0 = AArch64_SYSREG_TRCCIDCVR0, + ARM64_SYSREG_TRCCIDCVR1 = AArch64_SYSREG_TRCCIDCVR1, + ARM64_SYSREG_TRCCIDCVR2 = AArch64_SYSREG_TRCCIDCVR2, + ARM64_SYSREG_TRCCIDCVR3 = AArch64_SYSREG_TRCCIDCVR3, + ARM64_SYSREG_TRCCIDCVR4 = AArch64_SYSREG_TRCCIDCVR4, + ARM64_SYSREG_TRCCIDCVR5 = AArch64_SYSREG_TRCCIDCVR5, + ARM64_SYSREG_TRCCIDCVR6 = AArch64_SYSREG_TRCCIDCVR6, + ARM64_SYSREG_TRCCIDCVR7 = AArch64_SYSREG_TRCCIDCVR7, + ARM64_SYSREG_TRCCIDR0 = AArch64_SYSREG_TRCCIDR0, + ARM64_SYSREG_TRCCIDR1 = AArch64_SYSREG_TRCCIDR1, + ARM64_SYSREG_TRCCIDR2 = AArch64_SYSREG_TRCCIDR2, + ARM64_SYSREG_TRCCIDR3 = AArch64_SYSREG_TRCCIDR3, + ARM64_SYSREG_TRCCLAIMCLR = AArch64_SYSREG_TRCCLAIMCLR, + ARM64_SYSREG_TRCCLAIMSET = AArch64_SYSREG_TRCCLAIMSET, + ARM64_SYSREG_TRCCNTCTLR0 = AArch64_SYSREG_TRCCNTCTLR0, + ARM64_SYSREG_TRCCNTCTLR1 = AArch64_SYSREG_TRCCNTCTLR1, + ARM64_SYSREG_TRCCNTCTLR2 = AArch64_SYSREG_TRCCNTCTLR2, + ARM64_SYSREG_TRCCNTCTLR3 = AArch64_SYSREG_TRCCNTCTLR3, + ARM64_SYSREG_TRCCNTRLDVR0 = AArch64_SYSREG_TRCCNTRLDVR0, + ARM64_SYSREG_TRCCNTRLDVR1 = AArch64_SYSREG_TRCCNTRLDVR1, + ARM64_SYSREG_TRCCNTRLDVR2 = AArch64_SYSREG_TRCCNTRLDVR2, + ARM64_SYSREG_TRCCNTRLDVR3 = AArch64_SYSREG_TRCCNTRLDVR3, + ARM64_SYSREG_TRCCNTVR0 = AArch64_SYSREG_TRCCNTVR0, + ARM64_SYSREG_TRCCNTVR1 = AArch64_SYSREG_TRCCNTVR1, + ARM64_SYSREG_TRCCNTVR2 = AArch64_SYSREG_TRCCNTVR2, + ARM64_SYSREG_TRCCNTVR3 = AArch64_SYSREG_TRCCNTVR3, + ARM64_SYSREG_TRCCONFIGR = AArch64_SYSREG_TRCCONFIGR, + ARM64_SYSREG_TRCDEVAFF0 = AArch64_SYSREG_TRCDEVAFF0, + ARM64_SYSREG_TRCDEVAFF1 = AArch64_SYSREG_TRCDEVAFF1, + ARM64_SYSREG_TRCDEVARCH = AArch64_SYSREG_TRCDEVARCH, + ARM64_SYSREG_TRCDEVID = AArch64_SYSREG_TRCDEVID, + ARM64_SYSREG_TRCDEVTYPE = AArch64_SYSREG_TRCDEVTYPE, + ARM64_SYSREG_TRCDVCMR0 = AArch64_SYSREG_TRCDVCMR0, + ARM64_SYSREG_TRCDVCMR1 = AArch64_SYSREG_TRCDVCMR1, + ARM64_SYSREG_TRCDVCMR2 = AArch64_SYSREG_TRCDVCMR2, + ARM64_SYSREG_TRCDVCMR3 = AArch64_SYSREG_TRCDVCMR3, + ARM64_SYSREG_TRCDVCMR4 = AArch64_SYSREG_TRCDVCMR4, + ARM64_SYSREG_TRCDVCMR5 = AArch64_SYSREG_TRCDVCMR5, + ARM64_SYSREG_TRCDVCMR6 = AArch64_SYSREG_TRCDVCMR6, + ARM64_SYSREG_TRCDVCMR7 = AArch64_SYSREG_TRCDVCMR7, + ARM64_SYSREG_TRCDVCVR0 = AArch64_SYSREG_TRCDVCVR0, + ARM64_SYSREG_TRCDVCVR1 = AArch64_SYSREG_TRCDVCVR1, + ARM64_SYSREG_TRCDVCVR2 = AArch64_SYSREG_TRCDVCVR2, + ARM64_SYSREG_TRCDVCVR3 = AArch64_SYSREG_TRCDVCVR3, + ARM64_SYSREG_TRCDVCVR4 = AArch64_SYSREG_TRCDVCVR4, + ARM64_SYSREG_TRCDVCVR5 = AArch64_SYSREG_TRCDVCVR5, + ARM64_SYSREG_TRCDVCVR6 = AArch64_SYSREG_TRCDVCVR6, + ARM64_SYSREG_TRCDVCVR7 = AArch64_SYSREG_TRCDVCVR7, + ARM64_SYSREG_TRCEVENTCTL0R = AArch64_SYSREG_TRCEVENTCTL0R, + ARM64_SYSREG_TRCEVENTCTL1R = AArch64_SYSREG_TRCEVENTCTL1R, + ARM64_SYSREG_TRCEXTINSELR = AArch64_SYSREG_TRCEXTINSELR, + ARM64_SYSREG_TRCEXTINSELR0 = AArch64_SYSREG_TRCEXTINSELR0, + ARM64_SYSREG_TRCEXTINSELR1 = AArch64_SYSREG_TRCEXTINSELR1, + ARM64_SYSREG_TRCEXTINSELR2 = AArch64_SYSREG_TRCEXTINSELR2, + ARM64_SYSREG_TRCEXTINSELR3 = AArch64_SYSREG_TRCEXTINSELR3, + ARM64_SYSREG_TRCIDR0 = AArch64_SYSREG_TRCIDR0, + ARM64_SYSREG_TRCIDR1 = AArch64_SYSREG_TRCIDR1, + ARM64_SYSREG_TRCIDR10 = AArch64_SYSREG_TRCIDR10, + ARM64_SYSREG_TRCIDR11 = AArch64_SYSREG_TRCIDR11, + ARM64_SYSREG_TRCIDR12 = AArch64_SYSREG_TRCIDR12, + ARM64_SYSREG_TRCIDR13 = AArch64_SYSREG_TRCIDR13, + ARM64_SYSREG_TRCIDR2 = AArch64_SYSREG_TRCIDR2, + ARM64_SYSREG_TRCIDR3 = AArch64_SYSREG_TRCIDR3, + ARM64_SYSREG_TRCIDR4 = AArch64_SYSREG_TRCIDR4, + ARM64_SYSREG_TRCIDR5 = AArch64_SYSREG_TRCIDR5, + ARM64_SYSREG_TRCIDR6 = AArch64_SYSREG_TRCIDR6, + ARM64_SYSREG_TRCIDR7 = AArch64_SYSREG_TRCIDR7, + ARM64_SYSREG_TRCIDR8 = AArch64_SYSREG_TRCIDR8, + ARM64_SYSREG_TRCIDR9 = AArch64_SYSREG_TRCIDR9, + ARM64_SYSREG_TRCIMSPEC0 = AArch64_SYSREG_TRCIMSPEC0, + ARM64_SYSREG_TRCIMSPEC1 = AArch64_SYSREG_TRCIMSPEC1, + ARM64_SYSREG_TRCIMSPEC2 = AArch64_SYSREG_TRCIMSPEC2, + ARM64_SYSREG_TRCIMSPEC3 = AArch64_SYSREG_TRCIMSPEC3, + ARM64_SYSREG_TRCIMSPEC4 = AArch64_SYSREG_TRCIMSPEC4, + ARM64_SYSREG_TRCIMSPEC5 = AArch64_SYSREG_TRCIMSPEC5, + ARM64_SYSREG_TRCIMSPEC6 = AArch64_SYSREG_TRCIMSPEC6, + ARM64_SYSREG_TRCIMSPEC7 = AArch64_SYSREG_TRCIMSPEC7, + ARM64_SYSREG_TRCITCTRL = AArch64_SYSREG_TRCITCTRL, + ARM64_SYSREG_TRCITECR_EL1 = AArch64_SYSREG_TRCITECR_EL1, + ARM64_SYSREG_TRCITECR_EL12 = AArch64_SYSREG_TRCITECR_EL12, + ARM64_SYSREG_TRCITECR_EL2 = AArch64_SYSREG_TRCITECR_EL2, + ARM64_SYSREG_TRCITEEDCR = AArch64_SYSREG_TRCITEEDCR, + ARM64_SYSREG_TRCLAR = AArch64_SYSREG_TRCLAR, + ARM64_SYSREG_TRCLSR = AArch64_SYSREG_TRCLSR, + ARM64_SYSREG_TRCOSLAR = AArch64_SYSREG_TRCOSLAR, + ARM64_SYSREG_TRCOSLSR = AArch64_SYSREG_TRCOSLSR, + ARM64_SYSREG_TRCPDCR = AArch64_SYSREG_TRCPDCR, + ARM64_SYSREG_TRCPDSR = AArch64_SYSREG_TRCPDSR, + ARM64_SYSREG_TRCPIDR0 = AArch64_SYSREG_TRCPIDR0, + ARM64_SYSREG_TRCPIDR1 = AArch64_SYSREG_TRCPIDR1, + ARM64_SYSREG_TRCPIDR2 = AArch64_SYSREG_TRCPIDR2, + ARM64_SYSREG_TRCPIDR3 = AArch64_SYSREG_TRCPIDR3, + ARM64_SYSREG_TRCPIDR4 = AArch64_SYSREG_TRCPIDR4, + ARM64_SYSREG_TRCPIDR5 = AArch64_SYSREG_TRCPIDR5, + ARM64_SYSREG_TRCPIDR6 = AArch64_SYSREG_TRCPIDR6, + ARM64_SYSREG_TRCPIDR7 = AArch64_SYSREG_TRCPIDR7, + ARM64_SYSREG_TRCPRGCTLR = AArch64_SYSREG_TRCPRGCTLR, + ARM64_SYSREG_TRCPROCSELR = AArch64_SYSREG_TRCPROCSELR, + ARM64_SYSREG_TRCQCTLR = AArch64_SYSREG_TRCQCTLR, + ARM64_SYSREG_TRCRSCTLR10 = AArch64_SYSREG_TRCRSCTLR10, + ARM64_SYSREG_TRCRSCTLR11 = AArch64_SYSREG_TRCRSCTLR11, + ARM64_SYSREG_TRCRSCTLR12 = AArch64_SYSREG_TRCRSCTLR12, + ARM64_SYSREG_TRCRSCTLR13 = AArch64_SYSREG_TRCRSCTLR13, + ARM64_SYSREG_TRCRSCTLR14 = AArch64_SYSREG_TRCRSCTLR14, + ARM64_SYSREG_TRCRSCTLR15 = AArch64_SYSREG_TRCRSCTLR15, + ARM64_SYSREG_TRCRSCTLR16 = AArch64_SYSREG_TRCRSCTLR16, + ARM64_SYSREG_TRCRSCTLR17 = AArch64_SYSREG_TRCRSCTLR17, + ARM64_SYSREG_TRCRSCTLR18 = AArch64_SYSREG_TRCRSCTLR18, + ARM64_SYSREG_TRCRSCTLR19 = AArch64_SYSREG_TRCRSCTLR19, + ARM64_SYSREG_TRCRSCTLR2 = AArch64_SYSREG_TRCRSCTLR2, + ARM64_SYSREG_TRCRSCTLR20 = AArch64_SYSREG_TRCRSCTLR20, + ARM64_SYSREG_TRCRSCTLR21 = AArch64_SYSREG_TRCRSCTLR21, + ARM64_SYSREG_TRCRSCTLR22 = AArch64_SYSREG_TRCRSCTLR22, + ARM64_SYSREG_TRCRSCTLR23 = AArch64_SYSREG_TRCRSCTLR23, + ARM64_SYSREG_TRCRSCTLR24 = AArch64_SYSREG_TRCRSCTLR24, + ARM64_SYSREG_TRCRSCTLR25 = AArch64_SYSREG_TRCRSCTLR25, + ARM64_SYSREG_TRCRSCTLR26 = AArch64_SYSREG_TRCRSCTLR26, + ARM64_SYSREG_TRCRSCTLR27 = AArch64_SYSREG_TRCRSCTLR27, + ARM64_SYSREG_TRCRSCTLR28 = AArch64_SYSREG_TRCRSCTLR28, + ARM64_SYSREG_TRCRSCTLR29 = AArch64_SYSREG_TRCRSCTLR29, + ARM64_SYSREG_TRCRSCTLR3 = AArch64_SYSREG_TRCRSCTLR3, + ARM64_SYSREG_TRCRSCTLR30 = AArch64_SYSREG_TRCRSCTLR30, + ARM64_SYSREG_TRCRSCTLR31 = AArch64_SYSREG_TRCRSCTLR31, + ARM64_SYSREG_TRCRSCTLR4 = AArch64_SYSREG_TRCRSCTLR4, + ARM64_SYSREG_TRCRSCTLR5 = AArch64_SYSREG_TRCRSCTLR5, + ARM64_SYSREG_TRCRSCTLR6 = AArch64_SYSREG_TRCRSCTLR6, + ARM64_SYSREG_TRCRSCTLR7 = AArch64_SYSREG_TRCRSCTLR7, + ARM64_SYSREG_TRCRSCTLR8 = AArch64_SYSREG_TRCRSCTLR8, + ARM64_SYSREG_TRCRSCTLR9 = AArch64_SYSREG_TRCRSCTLR9, + ARM64_SYSREG_TRCRSR = AArch64_SYSREG_TRCRSR, + ARM64_SYSREG_TRCSEQEVR0 = AArch64_SYSREG_TRCSEQEVR0, + ARM64_SYSREG_TRCSEQEVR1 = AArch64_SYSREG_TRCSEQEVR1, + ARM64_SYSREG_TRCSEQEVR2 = AArch64_SYSREG_TRCSEQEVR2, + ARM64_SYSREG_TRCSEQRSTEVR = AArch64_SYSREG_TRCSEQRSTEVR, + ARM64_SYSREG_TRCSEQSTR = AArch64_SYSREG_TRCSEQSTR, + ARM64_SYSREG_TRCSSCCR0 = AArch64_SYSREG_TRCSSCCR0, + ARM64_SYSREG_TRCSSCCR1 = AArch64_SYSREG_TRCSSCCR1, + ARM64_SYSREG_TRCSSCCR2 = AArch64_SYSREG_TRCSSCCR2, + ARM64_SYSREG_TRCSSCCR3 = AArch64_SYSREG_TRCSSCCR3, + ARM64_SYSREG_TRCSSCCR4 = AArch64_SYSREG_TRCSSCCR4, + ARM64_SYSREG_TRCSSCCR5 = AArch64_SYSREG_TRCSSCCR5, + ARM64_SYSREG_TRCSSCCR6 = AArch64_SYSREG_TRCSSCCR6, + ARM64_SYSREG_TRCSSCCR7 = AArch64_SYSREG_TRCSSCCR7, + ARM64_SYSREG_TRCSSCSR0 = AArch64_SYSREG_TRCSSCSR0, + ARM64_SYSREG_TRCSSCSR1 = AArch64_SYSREG_TRCSSCSR1, + ARM64_SYSREG_TRCSSCSR2 = AArch64_SYSREG_TRCSSCSR2, + ARM64_SYSREG_TRCSSCSR3 = AArch64_SYSREG_TRCSSCSR3, + ARM64_SYSREG_TRCSSCSR4 = AArch64_SYSREG_TRCSSCSR4, + ARM64_SYSREG_TRCSSCSR5 = AArch64_SYSREG_TRCSSCSR5, + ARM64_SYSREG_TRCSSCSR6 = AArch64_SYSREG_TRCSSCSR6, + ARM64_SYSREG_TRCSSCSR7 = AArch64_SYSREG_TRCSSCSR7, + ARM64_SYSREG_TRCSSPCICR0 = AArch64_SYSREG_TRCSSPCICR0, + ARM64_SYSREG_TRCSSPCICR1 = AArch64_SYSREG_TRCSSPCICR1, + ARM64_SYSREG_TRCSSPCICR2 = AArch64_SYSREG_TRCSSPCICR2, + ARM64_SYSREG_TRCSSPCICR3 = AArch64_SYSREG_TRCSSPCICR3, + ARM64_SYSREG_TRCSSPCICR4 = AArch64_SYSREG_TRCSSPCICR4, + ARM64_SYSREG_TRCSSPCICR5 = AArch64_SYSREG_TRCSSPCICR5, + ARM64_SYSREG_TRCSSPCICR6 = AArch64_SYSREG_TRCSSPCICR6, + ARM64_SYSREG_TRCSSPCICR7 = AArch64_SYSREG_TRCSSPCICR7, + ARM64_SYSREG_TRCSTALLCTLR = AArch64_SYSREG_TRCSTALLCTLR, + ARM64_SYSREG_TRCSTATR = AArch64_SYSREG_TRCSTATR, + ARM64_SYSREG_TRCSYNCPR = AArch64_SYSREG_TRCSYNCPR, + ARM64_SYSREG_TRCTRACEIDR = AArch64_SYSREG_TRCTRACEIDR, + ARM64_SYSREG_TRCTSCTLR = AArch64_SYSREG_TRCTSCTLR, + ARM64_SYSREG_TRCVDARCCTLR = AArch64_SYSREG_TRCVDARCCTLR, + ARM64_SYSREG_TRCVDCTLR = AArch64_SYSREG_TRCVDCTLR, + ARM64_SYSREG_TRCVDSACCTLR = AArch64_SYSREG_TRCVDSACCTLR, + ARM64_SYSREG_TRCVICTLR = AArch64_SYSREG_TRCVICTLR, + ARM64_SYSREG_TRCVIIECTLR = AArch64_SYSREG_TRCVIIECTLR, + ARM64_SYSREG_TRCVIPCSSCTLR = AArch64_SYSREG_TRCVIPCSSCTLR, + ARM64_SYSREG_TRCVISSCTLR = AArch64_SYSREG_TRCVISSCTLR, + ARM64_SYSREG_TRCVMIDCCTLR0 = AArch64_SYSREG_TRCVMIDCCTLR0, + ARM64_SYSREG_TRCVMIDCCTLR1 = AArch64_SYSREG_TRCVMIDCCTLR1, + ARM64_SYSREG_TRCVMIDCVR0 = AArch64_SYSREG_TRCVMIDCVR0, + ARM64_SYSREG_TRCVMIDCVR1 = AArch64_SYSREG_TRCVMIDCVR1, + ARM64_SYSREG_TRCVMIDCVR2 = AArch64_SYSREG_TRCVMIDCVR2, + ARM64_SYSREG_TRCVMIDCVR3 = AArch64_SYSREG_TRCVMIDCVR3, + ARM64_SYSREG_TRCVMIDCVR4 = AArch64_SYSREG_TRCVMIDCVR4, + ARM64_SYSREG_TRCVMIDCVR5 = AArch64_SYSREG_TRCVMIDCVR5, + ARM64_SYSREG_TRCVMIDCVR6 = AArch64_SYSREG_TRCVMIDCVR6, + ARM64_SYSREG_TRCVMIDCVR7 = AArch64_SYSREG_TRCVMIDCVR7, + ARM64_SYSREG_TRFCR_EL1 = AArch64_SYSREG_TRFCR_EL1, + ARM64_SYSREG_TRFCR_EL12 = AArch64_SYSREG_TRFCR_EL12, + ARM64_SYSREG_TRFCR_EL2 = AArch64_SYSREG_TRFCR_EL2, + ARM64_SYSREG_TTBR0_EL1 = AArch64_SYSREG_TTBR0_EL1, + ARM64_SYSREG_TTBR0_EL12 = AArch64_SYSREG_TTBR0_EL12, + ARM64_SYSREG_TTBR0_EL2 = AArch64_SYSREG_TTBR0_EL2, + ARM64_SYSREG_VSCTLR_EL2 = AArch64_SYSREG_VSCTLR_EL2, + ARM64_SYSREG_TTBR0_EL3 = AArch64_SYSREG_TTBR0_EL3, + ARM64_SYSREG_TTBR1_EL1 = AArch64_SYSREG_TTBR1_EL1, + ARM64_SYSREG_TTBR1_EL12 = AArch64_SYSREG_TTBR1_EL12, + ARM64_SYSREG_TTBR1_EL2 = AArch64_SYSREG_TTBR1_EL2, + ARM64_SYSREG_UAO = AArch64_SYSREG_UAO, + ARM64_SYSREG_VBAR_EL1 = AArch64_SYSREG_VBAR_EL1, + ARM64_SYSREG_VBAR_EL12 = AArch64_SYSREG_VBAR_EL12, + ARM64_SYSREG_VBAR_EL2 = AArch64_SYSREG_VBAR_EL2, + ARM64_SYSREG_VBAR_EL3 = AArch64_SYSREG_VBAR_EL3, + ARM64_SYSREG_VDISR_EL2 = AArch64_SYSREG_VDISR_EL2, + ARM64_SYSREG_VMECID_A_EL2 = AArch64_SYSREG_VMECID_A_EL2, + ARM64_SYSREG_VMECID_P_EL2 = AArch64_SYSREG_VMECID_P_EL2, + ARM64_SYSREG_VMPIDR_EL2 = AArch64_SYSREG_VMPIDR_EL2, + ARM64_SYSREG_VNCR_EL2 = AArch64_SYSREG_VNCR_EL2, + ARM64_SYSREG_VPIDR_EL2 = AArch64_SYSREG_VPIDR_EL2, + ARM64_SYSREG_VSESR_EL2 = AArch64_SYSREG_VSESR_EL2, + ARM64_SYSREG_VSTCR_EL2 = AArch64_SYSREG_VSTCR_EL2, + ARM64_SYSREG_VSTTBR_EL2 = AArch64_SYSREG_VSTTBR_EL2, + ARM64_SYSREG_VTCR_EL2 = AArch64_SYSREG_VTCR_EL2, + ARM64_SYSREG_VTTBR_EL2 = AArch64_SYSREG_VTTBR_EL2, + ARM64_SYSREG_ZCR_EL1 = AArch64_SYSREG_ZCR_EL1, + ARM64_SYSREG_ZCR_EL12 = AArch64_SYSREG_ZCR_EL12, + ARM64_SYSREG_ZCR_EL2 = AArch64_SYSREG_ZCR_EL2, + ARM64_SYSREG_ZCR_EL3 = AArch64_SYSREG_ZCR_EL3, + + ARM64_SYSREG_ENDING = AArch64_SYSREG_ENDING, +} arm64_sysreg; + +typedef enum { + + ARM64_TSB_CSYNC = AArch64_TSB_CSYNC, + + ARM64_TSB_ENDING = AArch64_TSB_ENDING, +} arm64_tsb; + +typedef aarch64_sysop_reg arm64_sysop_reg; + +typedef aarch64_sysop_imm arm64_sysop_imm; + +typedef aarch64_sysop_alias arm64_sysop_alias; + +typedef enum { + ARM64_OP_INVALID = AArch64_OP_INVALID, + ARM64_OP_REG = AArch64_OP_REG, + ARM64_OP_IMM = AArch64_OP_IMM, + ARM64_OP_MEM_REG = AArch64_OP_MEM_REG, + ARM64_OP_MEM_IMM = AArch64_OP_MEM_IMM, + ARM64_OP_MEM = AArch64_OP_MEM, + ARM64_OP_FP = AArch64_OP_FP, + ARM64_OP_CIMM = AArch64_OP_CIMM, + ARM64_OP_REG_MRS = AArch64_OP_REG_MRS, + ARM64_OP_REG_MSR = AArch64_OP_REG_MSR, + ARM64_OP_IMPLICIT_IMM_0 = AArch64_OP_IMPLICIT_IMM_0, + ARM64_OP_SVCR = AArch64_OP_SVCR, + ARM64_OP_AT = AArch64_OP_AT, + ARM64_OP_DB = AArch64_OP_DB, + ARM64_OP_DC = AArch64_OP_DC, + ARM64_OP_ISB = AArch64_OP_ISB, + ARM64_OP_TSB = AArch64_OP_TSB, + ARM64_OP_PRFM = AArch64_OP_PRFM, + ARM64_OP_SVEPRFM = AArch64_OP_SVEPRFM, + ARM64_OP_RPRFM = AArch64_OP_RPRFM, + ARM64_OP_PSTATEIMM0_15 = AArch64_OP_PSTATEIMM0_15, + ARM64_OP_PSTATEIMM0_1 = AArch64_OP_PSTATEIMM0_1, + ARM64_OP_PSB = AArch64_OP_PSB, + ARM64_OP_BTI = AArch64_OP_BTI, + ARM64_OP_SVEPREDPAT = AArch64_OP_SVEPREDPAT, + ARM64_OP_SVEVECLENSPECIFIER = AArch64_OP_SVEVECLENSPECIFIER, + ARM64_OP_SME_MATRIX = AArch64_OP_SME_MATRIX, + ARM64_OP_IMM_RANGE = AArch64_OP_IMM_RANGE, + ARM64_OP_TLBI = AArch64_OP_TLBI, + ARM64_OP_IC = AArch64_OP_IC, + ARM64_OP_DBNXS = AArch64_OP_DBNXS, + ARM64_OP_EXACTFPIMM = AArch64_OP_EXACTFPIMM, + ARM64_OP_SYSREG = AArch64_OP_SYSREG, + ARM64_OP_SYSIMM = AArch64_OP_SYSIMM, + ARM64_OP_SYSALIAS = AArch64_OP_SYSALIAS, +} arm64_op_type; + +typedef aarch64_sysop arm64_sysop; + +typedef enum { + + ARM64_REG_INVALID = AArch64_REG_INVALID, + ARM64_REG_FFR = AArch64_REG_FFR, + ARM64_REG_FP = AArch64_REG_FP, + ARM64_REG_FPCR = AArch64_REG_FPCR, + ARM64_REG_LR = AArch64_REG_LR, + ARM64_REG_NZCV = AArch64_REG_NZCV, + ARM64_REG_SP = AArch64_REG_SP, + ARM64_REG_VG = AArch64_REG_VG, + ARM64_REG_WSP = AArch64_REG_WSP, + ARM64_REG_WZR = AArch64_REG_WZR, + ARM64_REG_XZR = AArch64_REG_XZR, + ARM64_REG_ZA = AArch64_REG_ZA, + ARM64_REG_B0 = AArch64_REG_B0, + ARM64_REG_B1 = AArch64_REG_B1, + ARM64_REG_B2 = AArch64_REG_B2, + ARM64_REG_B3 = AArch64_REG_B3, + ARM64_REG_B4 = AArch64_REG_B4, + ARM64_REG_B5 = AArch64_REG_B5, + ARM64_REG_B6 = AArch64_REG_B6, + ARM64_REG_B7 = AArch64_REG_B7, + ARM64_REG_B8 = AArch64_REG_B8, + ARM64_REG_B9 = AArch64_REG_B9, + ARM64_REG_B10 = AArch64_REG_B10, + ARM64_REG_B11 = AArch64_REG_B11, + ARM64_REG_B12 = AArch64_REG_B12, + ARM64_REG_B13 = AArch64_REG_B13, + ARM64_REG_B14 = AArch64_REG_B14, + ARM64_REG_B15 = AArch64_REG_B15, + ARM64_REG_B16 = AArch64_REG_B16, + ARM64_REG_B17 = AArch64_REG_B17, + ARM64_REG_B18 = AArch64_REG_B18, + ARM64_REG_B19 = AArch64_REG_B19, + ARM64_REG_B20 = AArch64_REG_B20, + ARM64_REG_B21 = AArch64_REG_B21, + ARM64_REG_B22 = AArch64_REG_B22, + ARM64_REG_B23 = AArch64_REG_B23, + ARM64_REG_B24 = AArch64_REG_B24, + ARM64_REG_B25 = AArch64_REG_B25, + ARM64_REG_B26 = AArch64_REG_B26, + ARM64_REG_B27 = AArch64_REG_B27, + ARM64_REG_B28 = AArch64_REG_B28, + ARM64_REG_B29 = AArch64_REG_B29, + ARM64_REG_B30 = AArch64_REG_B30, + ARM64_REG_B31 = AArch64_REG_B31, + ARM64_REG_D0 = AArch64_REG_D0, + ARM64_REG_D1 = AArch64_REG_D1, + ARM64_REG_D2 = AArch64_REG_D2, + ARM64_REG_D3 = AArch64_REG_D3, + ARM64_REG_D4 = AArch64_REG_D4, + ARM64_REG_D5 = AArch64_REG_D5, + ARM64_REG_D6 = AArch64_REG_D6, + ARM64_REG_D7 = AArch64_REG_D7, + ARM64_REG_D8 = AArch64_REG_D8, + ARM64_REG_D9 = AArch64_REG_D9, + ARM64_REG_D10 = AArch64_REG_D10, + ARM64_REG_D11 = AArch64_REG_D11, + ARM64_REG_D12 = AArch64_REG_D12, + ARM64_REG_D13 = AArch64_REG_D13, + ARM64_REG_D14 = AArch64_REG_D14, + ARM64_REG_D15 = AArch64_REG_D15, + ARM64_REG_D16 = AArch64_REG_D16, + ARM64_REG_D17 = AArch64_REG_D17, + ARM64_REG_D18 = AArch64_REG_D18, + ARM64_REG_D19 = AArch64_REG_D19, + ARM64_REG_D20 = AArch64_REG_D20, + ARM64_REG_D21 = AArch64_REG_D21, + ARM64_REG_D22 = AArch64_REG_D22, + ARM64_REG_D23 = AArch64_REG_D23, + ARM64_REG_D24 = AArch64_REG_D24, + ARM64_REG_D25 = AArch64_REG_D25, + ARM64_REG_D26 = AArch64_REG_D26, + ARM64_REG_D27 = AArch64_REG_D27, + ARM64_REG_D28 = AArch64_REG_D28, + ARM64_REG_D29 = AArch64_REG_D29, + ARM64_REG_D30 = AArch64_REG_D30, + ARM64_REG_D31 = AArch64_REG_D31, + ARM64_REG_H0 = AArch64_REG_H0, + ARM64_REG_H1 = AArch64_REG_H1, + ARM64_REG_H2 = AArch64_REG_H2, + ARM64_REG_H3 = AArch64_REG_H3, + ARM64_REG_H4 = AArch64_REG_H4, + ARM64_REG_H5 = AArch64_REG_H5, + ARM64_REG_H6 = AArch64_REG_H6, + ARM64_REG_H7 = AArch64_REG_H7, + ARM64_REG_H8 = AArch64_REG_H8, + ARM64_REG_H9 = AArch64_REG_H9, + ARM64_REG_H10 = AArch64_REG_H10, + ARM64_REG_H11 = AArch64_REG_H11, + ARM64_REG_H12 = AArch64_REG_H12, + ARM64_REG_H13 = AArch64_REG_H13, + ARM64_REG_H14 = AArch64_REG_H14, + ARM64_REG_H15 = AArch64_REG_H15, + ARM64_REG_H16 = AArch64_REG_H16, + ARM64_REG_H17 = AArch64_REG_H17, + ARM64_REG_H18 = AArch64_REG_H18, + ARM64_REG_H19 = AArch64_REG_H19, + ARM64_REG_H20 = AArch64_REG_H20, + ARM64_REG_H21 = AArch64_REG_H21, + ARM64_REG_H22 = AArch64_REG_H22, + ARM64_REG_H23 = AArch64_REG_H23, + ARM64_REG_H24 = AArch64_REG_H24, + ARM64_REG_H25 = AArch64_REG_H25, + ARM64_REG_H26 = AArch64_REG_H26, + ARM64_REG_H27 = AArch64_REG_H27, + ARM64_REG_H28 = AArch64_REG_H28, + ARM64_REG_H29 = AArch64_REG_H29, + ARM64_REG_H30 = AArch64_REG_H30, + ARM64_REG_H31 = AArch64_REG_H31, + ARM64_REG_P0 = AArch64_REG_P0, + ARM64_REG_P1 = AArch64_REG_P1, + ARM64_REG_P2 = AArch64_REG_P2, + ARM64_REG_P3 = AArch64_REG_P3, + ARM64_REG_P4 = AArch64_REG_P4, + ARM64_REG_P5 = AArch64_REG_P5, + ARM64_REG_P6 = AArch64_REG_P6, + ARM64_REG_P7 = AArch64_REG_P7, + ARM64_REG_P8 = AArch64_REG_P8, + ARM64_REG_P9 = AArch64_REG_P9, + ARM64_REG_P10 = AArch64_REG_P10, + ARM64_REG_P11 = AArch64_REG_P11, + ARM64_REG_P12 = AArch64_REG_P12, + ARM64_REG_P13 = AArch64_REG_P13, + ARM64_REG_P14 = AArch64_REG_P14, + ARM64_REG_P15 = AArch64_REG_P15, + ARM64_REG_Q0 = AArch64_REG_Q0, + ARM64_REG_Q1 = AArch64_REG_Q1, + ARM64_REG_Q2 = AArch64_REG_Q2, + ARM64_REG_Q3 = AArch64_REG_Q3, + ARM64_REG_Q4 = AArch64_REG_Q4, + ARM64_REG_Q5 = AArch64_REG_Q5, + ARM64_REG_Q6 = AArch64_REG_Q6, + ARM64_REG_Q7 = AArch64_REG_Q7, + ARM64_REG_Q8 = AArch64_REG_Q8, + ARM64_REG_Q9 = AArch64_REG_Q9, + ARM64_REG_Q10 = AArch64_REG_Q10, + ARM64_REG_Q11 = AArch64_REG_Q11, + ARM64_REG_Q12 = AArch64_REG_Q12, + ARM64_REG_Q13 = AArch64_REG_Q13, + ARM64_REG_Q14 = AArch64_REG_Q14, + ARM64_REG_Q15 = AArch64_REG_Q15, + ARM64_REG_Q16 = AArch64_REG_Q16, + ARM64_REG_Q17 = AArch64_REG_Q17, + ARM64_REG_Q18 = AArch64_REG_Q18, + ARM64_REG_Q19 = AArch64_REG_Q19, + ARM64_REG_Q20 = AArch64_REG_Q20, + ARM64_REG_Q21 = AArch64_REG_Q21, + ARM64_REG_Q22 = AArch64_REG_Q22, + ARM64_REG_Q23 = AArch64_REG_Q23, + ARM64_REG_Q24 = AArch64_REG_Q24, + ARM64_REG_Q25 = AArch64_REG_Q25, + ARM64_REG_Q26 = AArch64_REG_Q26, + ARM64_REG_Q27 = AArch64_REG_Q27, + ARM64_REG_Q28 = AArch64_REG_Q28, + ARM64_REG_Q29 = AArch64_REG_Q29, + ARM64_REG_Q30 = AArch64_REG_Q30, + ARM64_REG_Q31 = AArch64_REG_Q31, + ARM64_REG_S0 = AArch64_REG_S0, + ARM64_REG_S1 = AArch64_REG_S1, + ARM64_REG_S2 = AArch64_REG_S2, + ARM64_REG_S3 = AArch64_REG_S3, + ARM64_REG_S4 = AArch64_REG_S4, + ARM64_REG_S5 = AArch64_REG_S5, + ARM64_REG_S6 = AArch64_REG_S6, + ARM64_REG_S7 = AArch64_REG_S7, + ARM64_REG_S8 = AArch64_REG_S8, + ARM64_REG_S9 = AArch64_REG_S9, + ARM64_REG_S10 = AArch64_REG_S10, + ARM64_REG_S11 = AArch64_REG_S11, + ARM64_REG_S12 = AArch64_REG_S12, + ARM64_REG_S13 = AArch64_REG_S13, + ARM64_REG_S14 = AArch64_REG_S14, + ARM64_REG_S15 = AArch64_REG_S15, + ARM64_REG_S16 = AArch64_REG_S16, + ARM64_REG_S17 = AArch64_REG_S17, + ARM64_REG_S18 = AArch64_REG_S18, + ARM64_REG_S19 = AArch64_REG_S19, + ARM64_REG_S20 = AArch64_REG_S20, + ARM64_REG_S21 = AArch64_REG_S21, + ARM64_REG_S22 = AArch64_REG_S22, + ARM64_REG_S23 = AArch64_REG_S23, + ARM64_REG_S24 = AArch64_REG_S24, + ARM64_REG_S25 = AArch64_REG_S25, + ARM64_REG_S26 = AArch64_REG_S26, + ARM64_REG_S27 = AArch64_REG_S27, + ARM64_REG_S28 = AArch64_REG_S28, + ARM64_REG_S29 = AArch64_REG_S29, + ARM64_REG_S30 = AArch64_REG_S30, + ARM64_REG_S31 = AArch64_REG_S31, + ARM64_REG_W0 = AArch64_REG_W0, + ARM64_REG_W1 = AArch64_REG_W1, + ARM64_REG_W2 = AArch64_REG_W2, + ARM64_REG_W3 = AArch64_REG_W3, + ARM64_REG_W4 = AArch64_REG_W4, + ARM64_REG_W5 = AArch64_REG_W5, + ARM64_REG_W6 = AArch64_REG_W6, + ARM64_REG_W7 = AArch64_REG_W7, + ARM64_REG_W8 = AArch64_REG_W8, + ARM64_REG_W9 = AArch64_REG_W9, + ARM64_REG_W10 = AArch64_REG_W10, + ARM64_REG_W11 = AArch64_REG_W11, + ARM64_REG_W12 = AArch64_REG_W12, + ARM64_REG_W13 = AArch64_REG_W13, + ARM64_REG_W14 = AArch64_REG_W14, + ARM64_REG_W15 = AArch64_REG_W15, + ARM64_REG_W16 = AArch64_REG_W16, + ARM64_REG_W17 = AArch64_REG_W17, + ARM64_REG_W18 = AArch64_REG_W18, + ARM64_REG_W19 = AArch64_REG_W19, + ARM64_REG_W20 = AArch64_REG_W20, + ARM64_REG_W21 = AArch64_REG_W21, + ARM64_REG_W22 = AArch64_REG_W22, + ARM64_REG_W23 = AArch64_REG_W23, + ARM64_REG_W24 = AArch64_REG_W24, + ARM64_REG_W25 = AArch64_REG_W25, + ARM64_REG_W26 = AArch64_REG_W26, + ARM64_REG_W27 = AArch64_REG_W27, + ARM64_REG_W28 = AArch64_REG_W28, + ARM64_REG_W29 = AArch64_REG_W29, + ARM64_REG_W30 = AArch64_REG_W30, + ARM64_REG_X0 = AArch64_REG_X0, + ARM64_REG_X1 = AArch64_REG_X1, + ARM64_REG_X2 = AArch64_REG_X2, + ARM64_REG_X3 = AArch64_REG_X3, + ARM64_REG_X4 = AArch64_REG_X4, + ARM64_REG_X5 = AArch64_REG_X5, + ARM64_REG_X6 = AArch64_REG_X6, + ARM64_REG_X7 = AArch64_REG_X7, + ARM64_REG_X8 = AArch64_REG_X8, + ARM64_REG_X9 = AArch64_REG_X9, + ARM64_REG_X10 = AArch64_REG_X10, + ARM64_REG_X11 = AArch64_REG_X11, + ARM64_REG_X12 = AArch64_REG_X12, + ARM64_REG_X13 = AArch64_REG_X13, + ARM64_REG_X14 = AArch64_REG_X14, + ARM64_REG_X15 = AArch64_REG_X15, + ARM64_REG_X16 = AArch64_REG_X16, + ARM64_REG_X17 = AArch64_REG_X17, + ARM64_REG_X18 = AArch64_REG_X18, + ARM64_REG_X19 = AArch64_REG_X19, + ARM64_REG_X20 = AArch64_REG_X20, + ARM64_REG_X21 = AArch64_REG_X21, + ARM64_REG_X22 = AArch64_REG_X22, + ARM64_REG_X23 = AArch64_REG_X23, + ARM64_REG_X24 = AArch64_REG_X24, + ARM64_REG_X25 = AArch64_REG_X25, + ARM64_REG_X26 = AArch64_REG_X26, + ARM64_REG_X27 = AArch64_REG_X27, + ARM64_REG_X28 = AArch64_REG_X28, + ARM64_REG_Z0 = AArch64_REG_Z0, + ARM64_REG_Z1 = AArch64_REG_Z1, + ARM64_REG_Z2 = AArch64_REG_Z2, + ARM64_REG_Z3 = AArch64_REG_Z3, + ARM64_REG_Z4 = AArch64_REG_Z4, + ARM64_REG_Z5 = AArch64_REG_Z5, + ARM64_REG_Z6 = AArch64_REG_Z6, + ARM64_REG_Z7 = AArch64_REG_Z7, + ARM64_REG_Z8 = AArch64_REG_Z8, + ARM64_REG_Z9 = AArch64_REG_Z9, + ARM64_REG_Z10 = AArch64_REG_Z10, + ARM64_REG_Z11 = AArch64_REG_Z11, + ARM64_REG_Z12 = AArch64_REG_Z12, + ARM64_REG_Z13 = AArch64_REG_Z13, + ARM64_REG_Z14 = AArch64_REG_Z14, + ARM64_REG_Z15 = AArch64_REG_Z15, + ARM64_REG_Z16 = AArch64_REG_Z16, + ARM64_REG_Z17 = AArch64_REG_Z17, + ARM64_REG_Z18 = AArch64_REG_Z18, + ARM64_REG_Z19 = AArch64_REG_Z19, + ARM64_REG_Z20 = AArch64_REG_Z20, + ARM64_REG_Z21 = AArch64_REG_Z21, + ARM64_REG_Z22 = AArch64_REG_Z22, + ARM64_REG_Z23 = AArch64_REG_Z23, + ARM64_REG_Z24 = AArch64_REG_Z24, + ARM64_REG_Z25 = AArch64_REG_Z25, + ARM64_REG_Z26 = AArch64_REG_Z26, + ARM64_REG_Z27 = AArch64_REG_Z27, + ARM64_REG_Z28 = AArch64_REG_Z28, + ARM64_REG_Z29 = AArch64_REG_Z29, + ARM64_REG_Z30 = AArch64_REG_Z30, + ARM64_REG_Z31 = AArch64_REG_Z31, + ARM64_REG_ZAB0 = AArch64_REG_ZAB0, + ARM64_REG_ZAD0 = AArch64_REG_ZAD0, + ARM64_REG_ZAD1 = AArch64_REG_ZAD1, + ARM64_REG_ZAD2 = AArch64_REG_ZAD2, + ARM64_REG_ZAD3 = AArch64_REG_ZAD3, + ARM64_REG_ZAD4 = AArch64_REG_ZAD4, + ARM64_REG_ZAD5 = AArch64_REG_ZAD5, + ARM64_REG_ZAD6 = AArch64_REG_ZAD6, + ARM64_REG_ZAD7 = AArch64_REG_ZAD7, + ARM64_REG_ZAH0 = AArch64_REG_ZAH0, + ARM64_REG_ZAH1 = AArch64_REG_ZAH1, + ARM64_REG_ZAQ0 = AArch64_REG_ZAQ0, + ARM64_REG_ZAQ1 = AArch64_REG_ZAQ1, + ARM64_REG_ZAQ2 = AArch64_REG_ZAQ2, + ARM64_REG_ZAQ3 = AArch64_REG_ZAQ3, + ARM64_REG_ZAQ4 = AArch64_REG_ZAQ4, + ARM64_REG_ZAQ5 = AArch64_REG_ZAQ5, + ARM64_REG_ZAQ6 = AArch64_REG_ZAQ6, + ARM64_REG_ZAQ7 = AArch64_REG_ZAQ7, + ARM64_REG_ZAQ8 = AArch64_REG_ZAQ8, + ARM64_REG_ZAQ9 = AArch64_REG_ZAQ9, + ARM64_REG_ZAQ10 = AArch64_REG_ZAQ10, + ARM64_REG_ZAQ11 = AArch64_REG_ZAQ11, + ARM64_REG_ZAQ12 = AArch64_REG_ZAQ12, + ARM64_REG_ZAQ13 = AArch64_REG_ZAQ13, + ARM64_REG_ZAQ14 = AArch64_REG_ZAQ14, + ARM64_REG_ZAQ15 = AArch64_REG_ZAQ15, + ARM64_REG_ZAS0 = AArch64_REG_ZAS0, + ARM64_REG_ZAS1 = AArch64_REG_ZAS1, + ARM64_REG_ZAS2 = AArch64_REG_ZAS2, + ARM64_REG_ZAS3 = AArch64_REG_ZAS3, + ARM64_REG_ZT0 = AArch64_REG_ZT0, + ARM64_REG_Z0_HI = AArch64_REG_Z0_HI, + ARM64_REG_Z1_HI = AArch64_REG_Z1_HI, + ARM64_REG_Z2_HI = AArch64_REG_Z2_HI, + ARM64_REG_Z3_HI = AArch64_REG_Z3_HI, + ARM64_REG_Z4_HI = AArch64_REG_Z4_HI, + ARM64_REG_Z5_HI = AArch64_REG_Z5_HI, + ARM64_REG_Z6_HI = AArch64_REG_Z6_HI, + ARM64_REG_Z7_HI = AArch64_REG_Z7_HI, + ARM64_REG_Z8_HI = AArch64_REG_Z8_HI, + ARM64_REG_Z9_HI = AArch64_REG_Z9_HI, + ARM64_REG_Z10_HI = AArch64_REG_Z10_HI, + ARM64_REG_Z11_HI = AArch64_REG_Z11_HI, + ARM64_REG_Z12_HI = AArch64_REG_Z12_HI, + ARM64_REG_Z13_HI = AArch64_REG_Z13_HI, + ARM64_REG_Z14_HI = AArch64_REG_Z14_HI, + ARM64_REG_Z15_HI = AArch64_REG_Z15_HI, + ARM64_REG_Z16_HI = AArch64_REG_Z16_HI, + ARM64_REG_Z17_HI = AArch64_REG_Z17_HI, + ARM64_REG_Z18_HI = AArch64_REG_Z18_HI, + ARM64_REG_Z19_HI = AArch64_REG_Z19_HI, + ARM64_REG_Z20_HI = AArch64_REG_Z20_HI, + ARM64_REG_Z21_HI = AArch64_REG_Z21_HI, + ARM64_REG_Z22_HI = AArch64_REG_Z22_HI, + ARM64_REG_Z23_HI = AArch64_REG_Z23_HI, + ARM64_REG_Z24_HI = AArch64_REG_Z24_HI, + ARM64_REG_Z25_HI = AArch64_REG_Z25_HI, + ARM64_REG_Z26_HI = AArch64_REG_Z26_HI, + ARM64_REG_Z27_HI = AArch64_REG_Z27_HI, + ARM64_REG_Z28_HI = AArch64_REG_Z28_HI, + ARM64_REG_Z29_HI = AArch64_REG_Z29_HI, + ARM64_REG_Z30_HI = AArch64_REG_Z30_HI, + ARM64_REG_Z31_HI = AArch64_REG_Z31_HI, + ARM64_REG_D0_D1 = AArch64_REG_D0_D1, + ARM64_REG_D1_D2 = AArch64_REG_D1_D2, + ARM64_REG_D2_D3 = AArch64_REG_D2_D3, + ARM64_REG_D3_D4 = AArch64_REG_D3_D4, + ARM64_REG_D4_D5 = AArch64_REG_D4_D5, + ARM64_REG_D5_D6 = AArch64_REG_D5_D6, + ARM64_REG_D6_D7 = AArch64_REG_D6_D7, + ARM64_REG_D7_D8 = AArch64_REG_D7_D8, + ARM64_REG_D8_D9 = AArch64_REG_D8_D9, + ARM64_REG_D9_D10 = AArch64_REG_D9_D10, + ARM64_REG_D10_D11 = AArch64_REG_D10_D11, + ARM64_REG_D11_D12 = AArch64_REG_D11_D12, + ARM64_REG_D12_D13 = AArch64_REG_D12_D13, + ARM64_REG_D13_D14 = AArch64_REG_D13_D14, + ARM64_REG_D14_D15 = AArch64_REG_D14_D15, + ARM64_REG_D15_D16 = AArch64_REG_D15_D16, + ARM64_REG_D16_D17 = AArch64_REG_D16_D17, + ARM64_REG_D17_D18 = AArch64_REG_D17_D18, + ARM64_REG_D18_D19 = AArch64_REG_D18_D19, + ARM64_REG_D19_D20 = AArch64_REG_D19_D20, + ARM64_REG_D20_D21 = AArch64_REG_D20_D21, + ARM64_REG_D21_D22 = AArch64_REG_D21_D22, + ARM64_REG_D22_D23 = AArch64_REG_D22_D23, + ARM64_REG_D23_D24 = AArch64_REG_D23_D24, + ARM64_REG_D24_D25 = AArch64_REG_D24_D25, + ARM64_REG_D25_D26 = AArch64_REG_D25_D26, + ARM64_REG_D26_D27 = AArch64_REG_D26_D27, + ARM64_REG_D27_D28 = AArch64_REG_D27_D28, + ARM64_REG_D28_D29 = AArch64_REG_D28_D29, + ARM64_REG_D29_D30 = AArch64_REG_D29_D30, + ARM64_REG_D30_D31 = AArch64_REG_D30_D31, + ARM64_REG_D31_D0 = AArch64_REG_D31_D0, + ARM64_REG_D0_D1_D2_D3 = AArch64_REG_D0_D1_D2_D3, + ARM64_REG_D1_D2_D3_D4 = AArch64_REG_D1_D2_D3_D4, + ARM64_REG_D2_D3_D4_D5 = AArch64_REG_D2_D3_D4_D5, + ARM64_REG_D3_D4_D5_D6 = AArch64_REG_D3_D4_D5_D6, + ARM64_REG_D4_D5_D6_D7 = AArch64_REG_D4_D5_D6_D7, + ARM64_REG_D5_D6_D7_D8 = AArch64_REG_D5_D6_D7_D8, + ARM64_REG_D6_D7_D8_D9 = AArch64_REG_D6_D7_D8_D9, + ARM64_REG_D7_D8_D9_D10 = AArch64_REG_D7_D8_D9_D10, + ARM64_REG_D8_D9_D10_D11 = AArch64_REG_D8_D9_D10_D11, + ARM64_REG_D9_D10_D11_D12 = AArch64_REG_D9_D10_D11_D12, + ARM64_REG_D10_D11_D12_D13 = AArch64_REG_D10_D11_D12_D13, + ARM64_REG_D11_D12_D13_D14 = AArch64_REG_D11_D12_D13_D14, + ARM64_REG_D12_D13_D14_D15 = AArch64_REG_D12_D13_D14_D15, + ARM64_REG_D13_D14_D15_D16 = AArch64_REG_D13_D14_D15_D16, + ARM64_REG_D14_D15_D16_D17 = AArch64_REG_D14_D15_D16_D17, + ARM64_REG_D15_D16_D17_D18 = AArch64_REG_D15_D16_D17_D18, + ARM64_REG_D16_D17_D18_D19 = AArch64_REG_D16_D17_D18_D19, + ARM64_REG_D17_D18_D19_D20 = AArch64_REG_D17_D18_D19_D20, + ARM64_REG_D18_D19_D20_D21 = AArch64_REG_D18_D19_D20_D21, + ARM64_REG_D19_D20_D21_D22 = AArch64_REG_D19_D20_D21_D22, + ARM64_REG_D20_D21_D22_D23 = AArch64_REG_D20_D21_D22_D23, + ARM64_REG_D21_D22_D23_D24 = AArch64_REG_D21_D22_D23_D24, + ARM64_REG_D22_D23_D24_D25 = AArch64_REG_D22_D23_D24_D25, + ARM64_REG_D23_D24_D25_D26 = AArch64_REG_D23_D24_D25_D26, + ARM64_REG_D24_D25_D26_D27 = AArch64_REG_D24_D25_D26_D27, + ARM64_REG_D25_D26_D27_D28 = AArch64_REG_D25_D26_D27_D28, + ARM64_REG_D26_D27_D28_D29 = AArch64_REG_D26_D27_D28_D29, + ARM64_REG_D27_D28_D29_D30 = AArch64_REG_D27_D28_D29_D30, + ARM64_REG_D28_D29_D30_D31 = AArch64_REG_D28_D29_D30_D31, + ARM64_REG_D29_D30_D31_D0 = AArch64_REG_D29_D30_D31_D0, + ARM64_REG_D30_D31_D0_D1 = AArch64_REG_D30_D31_D0_D1, + ARM64_REG_D31_D0_D1_D2 = AArch64_REG_D31_D0_D1_D2, + ARM64_REG_D0_D1_D2 = AArch64_REG_D0_D1_D2, + ARM64_REG_D1_D2_D3 = AArch64_REG_D1_D2_D3, + ARM64_REG_D2_D3_D4 = AArch64_REG_D2_D3_D4, + ARM64_REG_D3_D4_D5 = AArch64_REG_D3_D4_D5, + ARM64_REG_D4_D5_D6 = AArch64_REG_D4_D5_D6, + ARM64_REG_D5_D6_D7 = AArch64_REG_D5_D6_D7, + ARM64_REG_D6_D7_D8 = AArch64_REG_D6_D7_D8, + ARM64_REG_D7_D8_D9 = AArch64_REG_D7_D8_D9, + ARM64_REG_D8_D9_D10 = AArch64_REG_D8_D9_D10, + ARM64_REG_D9_D10_D11 = AArch64_REG_D9_D10_D11, + ARM64_REG_D10_D11_D12 = AArch64_REG_D10_D11_D12, + ARM64_REG_D11_D12_D13 = AArch64_REG_D11_D12_D13, + ARM64_REG_D12_D13_D14 = AArch64_REG_D12_D13_D14, + ARM64_REG_D13_D14_D15 = AArch64_REG_D13_D14_D15, + ARM64_REG_D14_D15_D16 = AArch64_REG_D14_D15_D16, + ARM64_REG_D15_D16_D17 = AArch64_REG_D15_D16_D17, + ARM64_REG_D16_D17_D18 = AArch64_REG_D16_D17_D18, + ARM64_REG_D17_D18_D19 = AArch64_REG_D17_D18_D19, + ARM64_REG_D18_D19_D20 = AArch64_REG_D18_D19_D20, + ARM64_REG_D19_D20_D21 = AArch64_REG_D19_D20_D21, + ARM64_REG_D20_D21_D22 = AArch64_REG_D20_D21_D22, + ARM64_REG_D21_D22_D23 = AArch64_REG_D21_D22_D23, + ARM64_REG_D22_D23_D24 = AArch64_REG_D22_D23_D24, + ARM64_REG_D23_D24_D25 = AArch64_REG_D23_D24_D25, + ARM64_REG_D24_D25_D26 = AArch64_REG_D24_D25_D26, + ARM64_REG_D25_D26_D27 = AArch64_REG_D25_D26_D27, + ARM64_REG_D26_D27_D28 = AArch64_REG_D26_D27_D28, + ARM64_REG_D27_D28_D29 = AArch64_REG_D27_D28_D29, + ARM64_REG_D28_D29_D30 = AArch64_REG_D28_D29_D30, + ARM64_REG_D29_D30_D31 = AArch64_REG_D29_D30_D31, + ARM64_REG_D30_D31_D0 = AArch64_REG_D30_D31_D0, + ARM64_REG_D31_D0_D1 = AArch64_REG_D31_D0_D1, + ARM64_REG_P0_P1 = AArch64_REG_P0_P1, + ARM64_REG_P1_P2 = AArch64_REG_P1_P2, + ARM64_REG_P2_P3 = AArch64_REG_P2_P3, + ARM64_REG_P3_P4 = AArch64_REG_P3_P4, + ARM64_REG_P4_P5 = AArch64_REG_P4_P5, + ARM64_REG_P5_P6 = AArch64_REG_P5_P6, + ARM64_REG_P6_P7 = AArch64_REG_P6_P7, + ARM64_REG_P7_P8 = AArch64_REG_P7_P8, + ARM64_REG_P8_P9 = AArch64_REG_P8_P9, + ARM64_REG_P9_P10 = AArch64_REG_P9_P10, + ARM64_REG_P10_P11 = AArch64_REG_P10_P11, + ARM64_REG_P11_P12 = AArch64_REG_P11_P12, + ARM64_REG_P12_P13 = AArch64_REG_P12_P13, + ARM64_REG_P13_P14 = AArch64_REG_P13_P14, + ARM64_REG_P14_P15 = AArch64_REG_P14_P15, + ARM64_REG_P15_P0 = AArch64_REG_P15_P0, + ARM64_REG_Q0_Q1 = AArch64_REG_Q0_Q1, + ARM64_REG_Q1_Q2 = AArch64_REG_Q1_Q2, + ARM64_REG_Q2_Q3 = AArch64_REG_Q2_Q3, + ARM64_REG_Q3_Q4 = AArch64_REG_Q3_Q4, + ARM64_REG_Q4_Q5 = AArch64_REG_Q4_Q5, + ARM64_REG_Q5_Q6 = AArch64_REG_Q5_Q6, + ARM64_REG_Q6_Q7 = AArch64_REG_Q6_Q7, + ARM64_REG_Q7_Q8 = AArch64_REG_Q7_Q8, + ARM64_REG_Q8_Q9 = AArch64_REG_Q8_Q9, + ARM64_REG_Q9_Q10 = AArch64_REG_Q9_Q10, + ARM64_REG_Q10_Q11 = AArch64_REG_Q10_Q11, + ARM64_REG_Q11_Q12 = AArch64_REG_Q11_Q12, + ARM64_REG_Q12_Q13 = AArch64_REG_Q12_Q13, + ARM64_REG_Q13_Q14 = AArch64_REG_Q13_Q14, + ARM64_REG_Q14_Q15 = AArch64_REG_Q14_Q15, + ARM64_REG_Q15_Q16 = AArch64_REG_Q15_Q16, + ARM64_REG_Q16_Q17 = AArch64_REG_Q16_Q17, + ARM64_REG_Q17_Q18 = AArch64_REG_Q17_Q18, + ARM64_REG_Q18_Q19 = AArch64_REG_Q18_Q19, + ARM64_REG_Q19_Q20 = AArch64_REG_Q19_Q20, + ARM64_REG_Q20_Q21 = AArch64_REG_Q20_Q21, + ARM64_REG_Q21_Q22 = AArch64_REG_Q21_Q22, + ARM64_REG_Q22_Q23 = AArch64_REG_Q22_Q23, + ARM64_REG_Q23_Q24 = AArch64_REG_Q23_Q24, + ARM64_REG_Q24_Q25 = AArch64_REG_Q24_Q25, + ARM64_REG_Q25_Q26 = AArch64_REG_Q25_Q26, + ARM64_REG_Q26_Q27 = AArch64_REG_Q26_Q27, + ARM64_REG_Q27_Q28 = AArch64_REG_Q27_Q28, + ARM64_REG_Q28_Q29 = AArch64_REG_Q28_Q29, + ARM64_REG_Q29_Q30 = AArch64_REG_Q29_Q30, + ARM64_REG_Q30_Q31 = AArch64_REG_Q30_Q31, + ARM64_REG_Q31_Q0 = AArch64_REG_Q31_Q0, + ARM64_REG_Q0_Q1_Q2_Q3 = AArch64_REG_Q0_Q1_Q2_Q3, + ARM64_REG_Q1_Q2_Q3_Q4 = AArch64_REG_Q1_Q2_Q3_Q4, + ARM64_REG_Q2_Q3_Q4_Q5 = AArch64_REG_Q2_Q3_Q4_Q5, + ARM64_REG_Q3_Q4_Q5_Q6 = AArch64_REG_Q3_Q4_Q5_Q6, + ARM64_REG_Q4_Q5_Q6_Q7 = AArch64_REG_Q4_Q5_Q6_Q7, + ARM64_REG_Q5_Q6_Q7_Q8 = AArch64_REG_Q5_Q6_Q7_Q8, + ARM64_REG_Q6_Q7_Q8_Q9 = AArch64_REG_Q6_Q7_Q8_Q9, + ARM64_REG_Q7_Q8_Q9_Q10 = AArch64_REG_Q7_Q8_Q9_Q10, + ARM64_REG_Q8_Q9_Q10_Q11 = AArch64_REG_Q8_Q9_Q10_Q11, + ARM64_REG_Q9_Q10_Q11_Q12 = AArch64_REG_Q9_Q10_Q11_Q12, + ARM64_REG_Q10_Q11_Q12_Q13 = AArch64_REG_Q10_Q11_Q12_Q13, + ARM64_REG_Q11_Q12_Q13_Q14 = AArch64_REG_Q11_Q12_Q13_Q14, + ARM64_REG_Q12_Q13_Q14_Q15 = AArch64_REG_Q12_Q13_Q14_Q15, + ARM64_REG_Q13_Q14_Q15_Q16 = AArch64_REG_Q13_Q14_Q15_Q16, + ARM64_REG_Q14_Q15_Q16_Q17 = AArch64_REG_Q14_Q15_Q16_Q17, + ARM64_REG_Q15_Q16_Q17_Q18 = AArch64_REG_Q15_Q16_Q17_Q18, + ARM64_REG_Q16_Q17_Q18_Q19 = AArch64_REG_Q16_Q17_Q18_Q19, + ARM64_REG_Q17_Q18_Q19_Q20 = AArch64_REG_Q17_Q18_Q19_Q20, + ARM64_REG_Q18_Q19_Q20_Q21 = AArch64_REG_Q18_Q19_Q20_Q21, + ARM64_REG_Q19_Q20_Q21_Q22 = AArch64_REG_Q19_Q20_Q21_Q22, + ARM64_REG_Q20_Q21_Q22_Q23 = AArch64_REG_Q20_Q21_Q22_Q23, + ARM64_REG_Q21_Q22_Q23_Q24 = AArch64_REG_Q21_Q22_Q23_Q24, + ARM64_REG_Q22_Q23_Q24_Q25 = AArch64_REG_Q22_Q23_Q24_Q25, + ARM64_REG_Q23_Q24_Q25_Q26 = AArch64_REG_Q23_Q24_Q25_Q26, + ARM64_REG_Q24_Q25_Q26_Q27 = AArch64_REG_Q24_Q25_Q26_Q27, + ARM64_REG_Q25_Q26_Q27_Q28 = AArch64_REG_Q25_Q26_Q27_Q28, + ARM64_REG_Q26_Q27_Q28_Q29 = AArch64_REG_Q26_Q27_Q28_Q29, + ARM64_REG_Q27_Q28_Q29_Q30 = AArch64_REG_Q27_Q28_Q29_Q30, + ARM64_REG_Q28_Q29_Q30_Q31 = AArch64_REG_Q28_Q29_Q30_Q31, + ARM64_REG_Q29_Q30_Q31_Q0 = AArch64_REG_Q29_Q30_Q31_Q0, + ARM64_REG_Q30_Q31_Q0_Q1 = AArch64_REG_Q30_Q31_Q0_Q1, + ARM64_REG_Q31_Q0_Q1_Q2 = AArch64_REG_Q31_Q0_Q1_Q2, + ARM64_REG_Q0_Q1_Q2 = AArch64_REG_Q0_Q1_Q2, + ARM64_REG_Q1_Q2_Q3 = AArch64_REG_Q1_Q2_Q3, + ARM64_REG_Q2_Q3_Q4 = AArch64_REG_Q2_Q3_Q4, + ARM64_REG_Q3_Q4_Q5 = AArch64_REG_Q3_Q4_Q5, + ARM64_REG_Q4_Q5_Q6 = AArch64_REG_Q4_Q5_Q6, + ARM64_REG_Q5_Q6_Q7 = AArch64_REG_Q5_Q6_Q7, + ARM64_REG_Q6_Q7_Q8 = AArch64_REG_Q6_Q7_Q8, + ARM64_REG_Q7_Q8_Q9 = AArch64_REG_Q7_Q8_Q9, + ARM64_REG_Q8_Q9_Q10 = AArch64_REG_Q8_Q9_Q10, + ARM64_REG_Q9_Q10_Q11 = AArch64_REG_Q9_Q10_Q11, + ARM64_REG_Q10_Q11_Q12 = AArch64_REG_Q10_Q11_Q12, + ARM64_REG_Q11_Q12_Q13 = AArch64_REG_Q11_Q12_Q13, + ARM64_REG_Q12_Q13_Q14 = AArch64_REG_Q12_Q13_Q14, + ARM64_REG_Q13_Q14_Q15 = AArch64_REG_Q13_Q14_Q15, + ARM64_REG_Q14_Q15_Q16 = AArch64_REG_Q14_Q15_Q16, + ARM64_REG_Q15_Q16_Q17 = AArch64_REG_Q15_Q16_Q17, + ARM64_REG_Q16_Q17_Q18 = AArch64_REG_Q16_Q17_Q18, + ARM64_REG_Q17_Q18_Q19 = AArch64_REG_Q17_Q18_Q19, + ARM64_REG_Q18_Q19_Q20 = AArch64_REG_Q18_Q19_Q20, + ARM64_REG_Q19_Q20_Q21 = AArch64_REG_Q19_Q20_Q21, + ARM64_REG_Q20_Q21_Q22 = AArch64_REG_Q20_Q21_Q22, + ARM64_REG_Q21_Q22_Q23 = AArch64_REG_Q21_Q22_Q23, + ARM64_REG_Q22_Q23_Q24 = AArch64_REG_Q22_Q23_Q24, + ARM64_REG_Q23_Q24_Q25 = AArch64_REG_Q23_Q24_Q25, + ARM64_REG_Q24_Q25_Q26 = AArch64_REG_Q24_Q25_Q26, + ARM64_REG_Q25_Q26_Q27 = AArch64_REG_Q25_Q26_Q27, + ARM64_REG_Q26_Q27_Q28 = AArch64_REG_Q26_Q27_Q28, + ARM64_REG_Q27_Q28_Q29 = AArch64_REG_Q27_Q28_Q29, + ARM64_REG_Q28_Q29_Q30 = AArch64_REG_Q28_Q29_Q30, + ARM64_REG_Q29_Q30_Q31 = AArch64_REG_Q29_Q30_Q31, + ARM64_REG_Q30_Q31_Q0 = AArch64_REG_Q30_Q31_Q0, + ARM64_REG_Q31_Q0_Q1 = AArch64_REG_Q31_Q0_Q1, + ARM64_REG_X22_X23_X24_X25_X26_X27_X28_FP = AArch64_REG_X22_X23_X24_X25_X26_X27_X28_FP, + ARM64_REG_X0_X1_X2_X3_X4_X5_X6_X7 = AArch64_REG_X0_X1_X2_X3_X4_X5_X6_X7, + ARM64_REG_X2_X3_X4_X5_X6_X7_X8_X9 = AArch64_REG_X2_X3_X4_X5_X6_X7_X8_X9, + ARM64_REG_X4_X5_X6_X7_X8_X9_X10_X11 = AArch64_REG_X4_X5_X6_X7_X8_X9_X10_X11, + ARM64_REG_X6_X7_X8_X9_X10_X11_X12_X13 = AArch64_REG_X6_X7_X8_X9_X10_X11_X12_X13, + ARM64_REG_X8_X9_X10_X11_X12_X13_X14_X15 = AArch64_REG_X8_X9_X10_X11_X12_X13_X14_X15, + ARM64_REG_X10_X11_X12_X13_X14_X15_X16_X17 = AArch64_REG_X10_X11_X12_X13_X14_X15_X16_X17, + ARM64_REG_X12_X13_X14_X15_X16_X17_X18_X19 = AArch64_REG_X12_X13_X14_X15_X16_X17_X18_X19, + ARM64_REG_X14_X15_X16_X17_X18_X19_X20_X21 = AArch64_REG_X14_X15_X16_X17_X18_X19_X20_X21, + ARM64_REG_X16_X17_X18_X19_X20_X21_X22_X23 = AArch64_REG_X16_X17_X18_X19_X20_X21_X22_X23, + ARM64_REG_X18_X19_X20_X21_X22_X23_X24_X25 = AArch64_REG_X18_X19_X20_X21_X22_X23_X24_X25, + ARM64_REG_X20_X21_X22_X23_X24_X25_X26_X27 = AArch64_REG_X20_X21_X22_X23_X24_X25_X26_X27, + ARM64_REG_W30_WZR = AArch64_REG_W30_WZR, + ARM64_REG_W0_W1 = AArch64_REG_W0_W1, + ARM64_REG_W2_W3 = AArch64_REG_W2_W3, + ARM64_REG_W4_W5 = AArch64_REG_W4_W5, + ARM64_REG_W6_W7 = AArch64_REG_W6_W7, + ARM64_REG_W8_W9 = AArch64_REG_W8_W9, + ARM64_REG_W10_W11 = AArch64_REG_W10_W11, + ARM64_REG_W12_W13 = AArch64_REG_W12_W13, + ARM64_REG_W14_W15 = AArch64_REG_W14_W15, + ARM64_REG_W16_W17 = AArch64_REG_W16_W17, + ARM64_REG_W18_W19 = AArch64_REG_W18_W19, + ARM64_REG_W20_W21 = AArch64_REG_W20_W21, + ARM64_REG_W22_W23 = AArch64_REG_W22_W23, + ARM64_REG_W24_W25 = AArch64_REG_W24_W25, + ARM64_REG_W26_W27 = AArch64_REG_W26_W27, + ARM64_REG_W28_W29 = AArch64_REG_W28_W29, + ARM64_REG_LR_XZR = AArch64_REG_LR_XZR, + ARM64_REG_X28_FP = AArch64_REG_X28_FP, + ARM64_REG_X0_X1 = AArch64_REG_X0_X1, + ARM64_REG_X2_X3 = AArch64_REG_X2_X3, + ARM64_REG_X4_X5 = AArch64_REG_X4_X5, + ARM64_REG_X6_X7 = AArch64_REG_X6_X7, + ARM64_REG_X8_X9 = AArch64_REG_X8_X9, + ARM64_REG_X10_X11 = AArch64_REG_X10_X11, + ARM64_REG_X12_X13 = AArch64_REG_X12_X13, + ARM64_REG_X14_X15 = AArch64_REG_X14_X15, + ARM64_REG_X16_X17 = AArch64_REG_X16_X17, + ARM64_REG_X18_X19 = AArch64_REG_X18_X19, + ARM64_REG_X20_X21 = AArch64_REG_X20_X21, + ARM64_REG_X22_X23 = AArch64_REG_X22_X23, + ARM64_REG_X24_X25 = AArch64_REG_X24_X25, + ARM64_REG_X26_X27 = AArch64_REG_X26_X27, + ARM64_REG_Z0_Z1 = AArch64_REG_Z0_Z1, + ARM64_REG_Z1_Z2 = AArch64_REG_Z1_Z2, + ARM64_REG_Z2_Z3 = AArch64_REG_Z2_Z3, + ARM64_REG_Z3_Z4 = AArch64_REG_Z3_Z4, + ARM64_REG_Z4_Z5 = AArch64_REG_Z4_Z5, + ARM64_REG_Z5_Z6 = AArch64_REG_Z5_Z6, + ARM64_REG_Z6_Z7 = AArch64_REG_Z6_Z7, + ARM64_REG_Z7_Z8 = AArch64_REG_Z7_Z8, + ARM64_REG_Z8_Z9 = AArch64_REG_Z8_Z9, + ARM64_REG_Z9_Z10 = AArch64_REG_Z9_Z10, + ARM64_REG_Z10_Z11 = AArch64_REG_Z10_Z11, + ARM64_REG_Z11_Z12 = AArch64_REG_Z11_Z12, + ARM64_REG_Z12_Z13 = AArch64_REG_Z12_Z13, + ARM64_REG_Z13_Z14 = AArch64_REG_Z13_Z14, + ARM64_REG_Z14_Z15 = AArch64_REG_Z14_Z15, + ARM64_REG_Z15_Z16 = AArch64_REG_Z15_Z16, + ARM64_REG_Z16_Z17 = AArch64_REG_Z16_Z17, + ARM64_REG_Z17_Z18 = AArch64_REG_Z17_Z18, + ARM64_REG_Z18_Z19 = AArch64_REG_Z18_Z19, + ARM64_REG_Z19_Z20 = AArch64_REG_Z19_Z20, + ARM64_REG_Z20_Z21 = AArch64_REG_Z20_Z21, + ARM64_REG_Z21_Z22 = AArch64_REG_Z21_Z22, + ARM64_REG_Z22_Z23 = AArch64_REG_Z22_Z23, + ARM64_REG_Z23_Z24 = AArch64_REG_Z23_Z24, + ARM64_REG_Z24_Z25 = AArch64_REG_Z24_Z25, + ARM64_REG_Z25_Z26 = AArch64_REG_Z25_Z26, + ARM64_REG_Z26_Z27 = AArch64_REG_Z26_Z27, + ARM64_REG_Z27_Z28 = AArch64_REG_Z27_Z28, + ARM64_REG_Z28_Z29 = AArch64_REG_Z28_Z29, + ARM64_REG_Z29_Z30 = AArch64_REG_Z29_Z30, + ARM64_REG_Z30_Z31 = AArch64_REG_Z30_Z31, + ARM64_REG_Z31_Z0 = AArch64_REG_Z31_Z0, + ARM64_REG_Z0_Z1_Z2_Z3 = AArch64_REG_Z0_Z1_Z2_Z3, + ARM64_REG_Z1_Z2_Z3_Z4 = AArch64_REG_Z1_Z2_Z3_Z4, + ARM64_REG_Z2_Z3_Z4_Z5 = AArch64_REG_Z2_Z3_Z4_Z5, + ARM64_REG_Z3_Z4_Z5_Z6 = AArch64_REG_Z3_Z4_Z5_Z6, + ARM64_REG_Z4_Z5_Z6_Z7 = AArch64_REG_Z4_Z5_Z6_Z7, + ARM64_REG_Z5_Z6_Z7_Z8 = AArch64_REG_Z5_Z6_Z7_Z8, + ARM64_REG_Z6_Z7_Z8_Z9 = AArch64_REG_Z6_Z7_Z8_Z9, + ARM64_REG_Z7_Z8_Z9_Z10 = AArch64_REG_Z7_Z8_Z9_Z10, + ARM64_REG_Z8_Z9_Z10_Z11 = AArch64_REG_Z8_Z9_Z10_Z11, + ARM64_REG_Z9_Z10_Z11_Z12 = AArch64_REG_Z9_Z10_Z11_Z12, + ARM64_REG_Z10_Z11_Z12_Z13 = AArch64_REG_Z10_Z11_Z12_Z13, + ARM64_REG_Z11_Z12_Z13_Z14 = AArch64_REG_Z11_Z12_Z13_Z14, + ARM64_REG_Z12_Z13_Z14_Z15 = AArch64_REG_Z12_Z13_Z14_Z15, + ARM64_REG_Z13_Z14_Z15_Z16 = AArch64_REG_Z13_Z14_Z15_Z16, + ARM64_REG_Z14_Z15_Z16_Z17 = AArch64_REG_Z14_Z15_Z16_Z17, + ARM64_REG_Z15_Z16_Z17_Z18 = AArch64_REG_Z15_Z16_Z17_Z18, + ARM64_REG_Z16_Z17_Z18_Z19 = AArch64_REG_Z16_Z17_Z18_Z19, + ARM64_REG_Z17_Z18_Z19_Z20 = AArch64_REG_Z17_Z18_Z19_Z20, + ARM64_REG_Z18_Z19_Z20_Z21 = AArch64_REG_Z18_Z19_Z20_Z21, + ARM64_REG_Z19_Z20_Z21_Z22 = AArch64_REG_Z19_Z20_Z21_Z22, + ARM64_REG_Z20_Z21_Z22_Z23 = AArch64_REG_Z20_Z21_Z22_Z23, + ARM64_REG_Z21_Z22_Z23_Z24 = AArch64_REG_Z21_Z22_Z23_Z24, + ARM64_REG_Z22_Z23_Z24_Z25 = AArch64_REG_Z22_Z23_Z24_Z25, + ARM64_REG_Z23_Z24_Z25_Z26 = AArch64_REG_Z23_Z24_Z25_Z26, + ARM64_REG_Z24_Z25_Z26_Z27 = AArch64_REG_Z24_Z25_Z26_Z27, + ARM64_REG_Z25_Z26_Z27_Z28 = AArch64_REG_Z25_Z26_Z27_Z28, + ARM64_REG_Z26_Z27_Z28_Z29 = AArch64_REG_Z26_Z27_Z28_Z29, + ARM64_REG_Z27_Z28_Z29_Z30 = AArch64_REG_Z27_Z28_Z29_Z30, + ARM64_REG_Z28_Z29_Z30_Z31 = AArch64_REG_Z28_Z29_Z30_Z31, + ARM64_REG_Z29_Z30_Z31_Z0 = AArch64_REG_Z29_Z30_Z31_Z0, + ARM64_REG_Z30_Z31_Z0_Z1 = AArch64_REG_Z30_Z31_Z0_Z1, + ARM64_REG_Z31_Z0_Z1_Z2 = AArch64_REG_Z31_Z0_Z1_Z2, + ARM64_REG_Z0_Z1_Z2 = AArch64_REG_Z0_Z1_Z2, + ARM64_REG_Z1_Z2_Z3 = AArch64_REG_Z1_Z2_Z3, + ARM64_REG_Z2_Z3_Z4 = AArch64_REG_Z2_Z3_Z4, + ARM64_REG_Z3_Z4_Z5 = AArch64_REG_Z3_Z4_Z5, + ARM64_REG_Z4_Z5_Z6 = AArch64_REG_Z4_Z5_Z6, + ARM64_REG_Z5_Z6_Z7 = AArch64_REG_Z5_Z6_Z7, + ARM64_REG_Z6_Z7_Z8 = AArch64_REG_Z6_Z7_Z8, + ARM64_REG_Z7_Z8_Z9 = AArch64_REG_Z7_Z8_Z9, + ARM64_REG_Z8_Z9_Z10 = AArch64_REG_Z8_Z9_Z10, + ARM64_REG_Z9_Z10_Z11 = AArch64_REG_Z9_Z10_Z11, + ARM64_REG_Z10_Z11_Z12 = AArch64_REG_Z10_Z11_Z12, + ARM64_REG_Z11_Z12_Z13 = AArch64_REG_Z11_Z12_Z13, + ARM64_REG_Z12_Z13_Z14 = AArch64_REG_Z12_Z13_Z14, + ARM64_REG_Z13_Z14_Z15 = AArch64_REG_Z13_Z14_Z15, + ARM64_REG_Z14_Z15_Z16 = AArch64_REG_Z14_Z15_Z16, + ARM64_REG_Z15_Z16_Z17 = AArch64_REG_Z15_Z16_Z17, + ARM64_REG_Z16_Z17_Z18 = AArch64_REG_Z16_Z17_Z18, + ARM64_REG_Z17_Z18_Z19 = AArch64_REG_Z17_Z18_Z19, + ARM64_REG_Z18_Z19_Z20 = AArch64_REG_Z18_Z19_Z20, + ARM64_REG_Z19_Z20_Z21 = AArch64_REG_Z19_Z20_Z21, + ARM64_REG_Z20_Z21_Z22 = AArch64_REG_Z20_Z21_Z22, + ARM64_REG_Z21_Z22_Z23 = AArch64_REG_Z21_Z22_Z23, + ARM64_REG_Z22_Z23_Z24 = AArch64_REG_Z22_Z23_Z24, + ARM64_REG_Z23_Z24_Z25 = AArch64_REG_Z23_Z24_Z25, + ARM64_REG_Z24_Z25_Z26 = AArch64_REG_Z24_Z25_Z26, + ARM64_REG_Z25_Z26_Z27 = AArch64_REG_Z25_Z26_Z27, + ARM64_REG_Z26_Z27_Z28 = AArch64_REG_Z26_Z27_Z28, + ARM64_REG_Z27_Z28_Z29 = AArch64_REG_Z27_Z28_Z29, + ARM64_REG_Z28_Z29_Z30 = AArch64_REG_Z28_Z29_Z30, + ARM64_REG_Z29_Z30_Z31 = AArch64_REG_Z29_Z30_Z31, + ARM64_REG_Z30_Z31_Z0 = AArch64_REG_Z30_Z31_Z0, + ARM64_REG_Z31_Z0_Z1 = AArch64_REG_Z31_Z0_Z1, + ARM64_REG_Z16_Z24 = AArch64_REG_Z16_Z24, + ARM64_REG_Z17_Z25 = AArch64_REG_Z17_Z25, + ARM64_REG_Z18_Z26 = AArch64_REG_Z18_Z26, + ARM64_REG_Z19_Z27 = AArch64_REG_Z19_Z27, + ARM64_REG_Z20_Z28 = AArch64_REG_Z20_Z28, + ARM64_REG_Z21_Z29 = AArch64_REG_Z21_Z29, + ARM64_REG_Z22_Z30 = AArch64_REG_Z22_Z30, + ARM64_REG_Z23_Z31 = AArch64_REG_Z23_Z31, + ARM64_REG_Z0_Z8 = AArch64_REG_Z0_Z8, + ARM64_REG_Z1_Z9 = AArch64_REG_Z1_Z9, + ARM64_REG_Z2_Z10 = AArch64_REG_Z2_Z10, + ARM64_REG_Z3_Z11 = AArch64_REG_Z3_Z11, + ARM64_REG_Z4_Z12 = AArch64_REG_Z4_Z12, + ARM64_REG_Z5_Z13 = AArch64_REG_Z5_Z13, + ARM64_REG_Z6_Z14 = AArch64_REG_Z6_Z14, + ARM64_REG_Z7_Z15 = AArch64_REG_Z7_Z15, + ARM64_REG_Z16_Z20_Z24_Z28 = AArch64_REG_Z16_Z20_Z24_Z28, + ARM64_REG_Z17_Z21_Z25_Z29 = AArch64_REG_Z17_Z21_Z25_Z29, + ARM64_REG_Z18_Z22_Z26_Z30 = AArch64_REG_Z18_Z22_Z26_Z30, + ARM64_REG_Z19_Z23_Z27_Z31 = AArch64_REG_Z19_Z23_Z27_Z31, + ARM64_REG_Z0_Z4_Z8_Z12 = AArch64_REG_Z0_Z4_Z8_Z12, + ARM64_REG_Z1_Z5_Z9_Z13 = AArch64_REG_Z1_Z5_Z9_Z13, + ARM64_REG_Z2_Z6_Z10_Z14 = AArch64_REG_Z2_Z6_Z10_Z14, + ARM64_REG_Z3_Z7_Z11_Z15 = AArch64_REG_Z3_Z7_Z11_Z15, + ARM64_REG_ENDING = AArch64_REG_ENDING, + + + ARM64_REG_IP0 = AArch64_REG_IP0, + ARM64_REG_IP1 = AArch64_REG_IP1, + ARM64_REG_X29 = AArch64_REG_X29, + ARM64_REG_X30 = AArch64_REG_X30, +} arm64_reg; + +typedef aarch64_op_mem arm64_op_mem; + +typedef enum { + ARM64_SME_MATRIX_TILE = AArch64_SME_MATRIX_TILE, + ARM64_SME_MATRIX_TILE_LIST = AArch64_SME_MATRIX_TILE_LIST, + ARM64_SME_MATRIX_SLICE_REG = AArch64_SME_MATRIX_SLICE_REG, + ARM64_SME_MATRIX_SLICE_OFF = AArch64_SME_MATRIX_SLICE_OFF, + ARM64_SME_MATRIX_SLICE_OFF_RANGE = AArch64_SME_MATRIX_SLICE_OFF_RANGE, +} arm64_sme_op_part; + +typedef enum { + ARM64_SME_OP_INVALID = AArch64_SME_OP_INVALID, + ARM64_SME_OP_TILE = AArch64_SME_OP_TILE, + ARM64_SME_OP_TILE_VEC = AArch64_SME_OP_TILE_VEC, +} arm64_sme_op_type; + +typedef aarch64_imm_range arm64_imm_range; + +typedef aarch64_op_sme arm64_op_sme; + +typedef cs_aarch64_op cs_arm64_op; + +#define MAX_ARM64_OPS 8 + +typedef cs_aarch64 cs_arm64; + +typedef enum { + + ARM64_INS_INVALID = AArch64_INS_INVALID, + ARM64_INS_ABS = AArch64_INS_ABS, + ARM64_INS_ADCLB = AArch64_INS_ADCLB, + ARM64_INS_ADCLT = AArch64_INS_ADCLT, + ARM64_INS_ADCS = AArch64_INS_ADCS, + ARM64_INS_ADC = AArch64_INS_ADC, + ARM64_INS_ADDG = AArch64_INS_ADDG, + ARM64_INS_ADDHA = AArch64_INS_ADDHA, + ARM64_INS_ADDHNB = AArch64_INS_ADDHNB, + ARM64_INS_ADDHNT = AArch64_INS_ADDHNT, + ARM64_INS_ADDHN = AArch64_INS_ADDHN, + ARM64_INS_ADDHN2 = AArch64_INS_ADDHN2, + ARM64_INS_ADDPL = AArch64_INS_ADDPL, + ARM64_INS_ADDP = AArch64_INS_ADDP, + ARM64_INS_ADDQV = AArch64_INS_ADDQV, + ARM64_INS_ADDSPL = AArch64_INS_ADDSPL, + ARM64_INS_ADDSVL = AArch64_INS_ADDSVL, + ARM64_INS_ADDS = AArch64_INS_ADDS, + ARM64_INS_ADDVA = AArch64_INS_ADDVA, + ARM64_INS_ADDVL = AArch64_INS_ADDVL, + ARM64_INS_ADDV = AArch64_INS_ADDV, + ARM64_INS_ADD = AArch64_INS_ADD, + ARM64_INS_ADR = AArch64_INS_ADR, + ARM64_INS_ADRP = AArch64_INS_ADRP, + ARM64_INS_AESD = AArch64_INS_AESD, + ARM64_INS_AESE = AArch64_INS_AESE, + ARM64_INS_AESIMC = AArch64_INS_AESIMC, + ARM64_INS_AESMC = AArch64_INS_AESMC, + ARM64_INS_ANDQV = AArch64_INS_ANDQV, + ARM64_INS_ANDS = AArch64_INS_ANDS, + ARM64_INS_ANDV = AArch64_INS_ANDV, + ARM64_INS_AND = AArch64_INS_AND, + ARM64_INS_ASRD = AArch64_INS_ASRD, + ARM64_INS_ASRR = AArch64_INS_ASRR, + ARM64_INS_ASR = AArch64_INS_ASR, + ARM64_INS_AUTDA = AArch64_INS_AUTDA, + ARM64_INS_AUTDB = AArch64_INS_AUTDB, + ARM64_INS_AUTDZA = AArch64_INS_AUTDZA, + ARM64_INS_AUTDZB = AArch64_INS_AUTDZB, + ARM64_INS_AUTIA = AArch64_INS_AUTIA, + ARM64_INS_HINT = AArch64_INS_HINT, + ARM64_INS_AUTIB = AArch64_INS_AUTIB, + ARM64_INS_AUTIZA = AArch64_INS_AUTIZA, + ARM64_INS_AUTIZB = AArch64_INS_AUTIZB, + ARM64_INS_AXFLAG = AArch64_INS_AXFLAG, + ARM64_INS_B = AArch64_INS_B, + ARM64_INS_BCAX = AArch64_INS_BCAX, + ARM64_INS_BC = AArch64_INS_BC, + ARM64_INS_BDEP = AArch64_INS_BDEP, + ARM64_INS_BEXT = AArch64_INS_BEXT, + ARM64_INS_BFDOT = AArch64_INS_BFDOT, + ARM64_INS_BFADD = AArch64_INS_BFADD, + ARM64_INS_BFCLAMP = AArch64_INS_BFCLAMP, + ARM64_INS_BFCVT = AArch64_INS_BFCVT, + ARM64_INS_BFCVTN = AArch64_INS_BFCVTN, + ARM64_INS_BFCVTN2 = AArch64_INS_BFCVTN2, + ARM64_INS_BFCVTNT = AArch64_INS_BFCVTNT, + ARM64_INS_BFMAXNM = AArch64_INS_BFMAXNM, + ARM64_INS_BFMAX = AArch64_INS_BFMAX, + ARM64_INS_BFMINNM = AArch64_INS_BFMINNM, + ARM64_INS_BFMIN = AArch64_INS_BFMIN, + ARM64_INS_BFMLALB = AArch64_INS_BFMLALB, + ARM64_INS_BFMLALT = AArch64_INS_BFMLALT, + ARM64_INS_BFMLAL = AArch64_INS_BFMLAL, + ARM64_INS_BFMLA = AArch64_INS_BFMLA, + ARM64_INS_BFMLSLB = AArch64_INS_BFMLSLB, + ARM64_INS_BFMLSLT = AArch64_INS_BFMLSLT, + ARM64_INS_BFMLSL = AArch64_INS_BFMLSL, + ARM64_INS_BFMLS = AArch64_INS_BFMLS, + ARM64_INS_BFMMLA = AArch64_INS_BFMMLA, + ARM64_INS_BFMOPA = AArch64_INS_BFMOPA, + ARM64_INS_BFMOPS = AArch64_INS_BFMOPS, + ARM64_INS_BFMUL = AArch64_INS_BFMUL, + ARM64_INS_BFM = AArch64_INS_BFM, + ARM64_INS_BFSUB = AArch64_INS_BFSUB, + ARM64_INS_BFVDOT = AArch64_INS_BFVDOT, + ARM64_INS_BGRP = AArch64_INS_BGRP, + ARM64_INS_BICS = AArch64_INS_BICS, + ARM64_INS_BIC = AArch64_INS_BIC, + ARM64_INS_BIF = AArch64_INS_BIF, + ARM64_INS_BIT = AArch64_INS_BIT, + ARM64_INS_BL = AArch64_INS_BL, + ARM64_INS_BLR = AArch64_INS_BLR, + ARM64_INS_BLRAA = AArch64_INS_BLRAA, + ARM64_INS_BLRAAZ = AArch64_INS_BLRAAZ, + ARM64_INS_BLRAB = AArch64_INS_BLRAB, + ARM64_INS_BLRABZ = AArch64_INS_BLRABZ, + ARM64_INS_BMOPA = AArch64_INS_BMOPA, + ARM64_INS_BMOPS = AArch64_INS_BMOPS, + ARM64_INS_BR = AArch64_INS_BR, + ARM64_INS_BRAA = AArch64_INS_BRAA, + ARM64_INS_BRAAZ = AArch64_INS_BRAAZ, + ARM64_INS_BRAB = AArch64_INS_BRAB, + ARM64_INS_BRABZ = AArch64_INS_BRABZ, + ARM64_INS_BRB = AArch64_INS_BRB, + ARM64_INS_BRK = AArch64_INS_BRK, + ARM64_INS_BRKAS = AArch64_INS_BRKAS, + ARM64_INS_BRKA = AArch64_INS_BRKA, + ARM64_INS_BRKBS = AArch64_INS_BRKBS, + ARM64_INS_BRKB = AArch64_INS_BRKB, + ARM64_INS_BRKNS = AArch64_INS_BRKNS, + ARM64_INS_BRKN = AArch64_INS_BRKN, + ARM64_INS_BRKPAS = AArch64_INS_BRKPAS, + ARM64_INS_BRKPA = AArch64_INS_BRKPA, + ARM64_INS_BRKPBS = AArch64_INS_BRKPBS, + ARM64_INS_BRKPB = AArch64_INS_BRKPB, + ARM64_INS_BSL1N = AArch64_INS_BSL1N, + ARM64_INS_BSL2N = AArch64_INS_BSL2N, + ARM64_INS_BSL = AArch64_INS_BSL, + ARM64_INS_CADD = AArch64_INS_CADD, + ARM64_INS_CASAB = AArch64_INS_CASAB, + ARM64_INS_CASAH = AArch64_INS_CASAH, + ARM64_INS_CASALB = AArch64_INS_CASALB, + ARM64_INS_CASALH = AArch64_INS_CASALH, + ARM64_INS_CASAL = AArch64_INS_CASAL, + ARM64_INS_CASA = AArch64_INS_CASA, + ARM64_INS_CASB = AArch64_INS_CASB, + ARM64_INS_CASH = AArch64_INS_CASH, + ARM64_INS_CASLB = AArch64_INS_CASLB, + ARM64_INS_CASLH = AArch64_INS_CASLH, + ARM64_INS_CASL = AArch64_INS_CASL, + ARM64_INS_CASPAL = AArch64_INS_CASPAL, + ARM64_INS_CASPA = AArch64_INS_CASPA, + ARM64_INS_CASPL = AArch64_INS_CASPL, + ARM64_INS_CASP = AArch64_INS_CASP, + ARM64_INS_CAS = AArch64_INS_CAS, + ARM64_INS_CBNZ = AArch64_INS_CBNZ, + ARM64_INS_CBZ = AArch64_INS_CBZ, + ARM64_INS_CCMN = AArch64_INS_CCMN, + ARM64_INS_CCMP = AArch64_INS_CCMP, + ARM64_INS_CDOT = AArch64_INS_CDOT, + ARM64_INS_CFINV = AArch64_INS_CFINV, + ARM64_INS_CLASTA = AArch64_INS_CLASTA, + ARM64_INS_CLASTB = AArch64_INS_CLASTB, + ARM64_INS_CLREX = AArch64_INS_CLREX, + ARM64_INS_CLS = AArch64_INS_CLS, + ARM64_INS_CLZ = AArch64_INS_CLZ, + ARM64_INS_CMEQ = AArch64_INS_CMEQ, + ARM64_INS_CMGE = AArch64_INS_CMGE, + ARM64_INS_CMGT = AArch64_INS_CMGT, + ARM64_INS_CMHI = AArch64_INS_CMHI, + ARM64_INS_CMHS = AArch64_INS_CMHS, + ARM64_INS_CMLA = AArch64_INS_CMLA, + ARM64_INS_CMLE = AArch64_INS_CMLE, + ARM64_INS_CMLT = AArch64_INS_CMLT, + ARM64_INS_CMPEQ = AArch64_INS_CMPEQ, + ARM64_INS_CMPGE = AArch64_INS_CMPGE, + ARM64_INS_CMPGT = AArch64_INS_CMPGT, + ARM64_INS_CMPHI = AArch64_INS_CMPHI, + ARM64_INS_CMPHS = AArch64_INS_CMPHS, + ARM64_INS_CMPLE = AArch64_INS_CMPLE, + ARM64_INS_CMPLO = AArch64_INS_CMPLO, + ARM64_INS_CMPLS = AArch64_INS_CMPLS, + ARM64_INS_CMPLT = AArch64_INS_CMPLT, + ARM64_INS_CMPNE = AArch64_INS_CMPNE, + ARM64_INS_CMTST = AArch64_INS_CMTST, + ARM64_INS_CNOT = AArch64_INS_CNOT, + ARM64_INS_CNTB = AArch64_INS_CNTB, + ARM64_INS_CNTD = AArch64_INS_CNTD, + ARM64_INS_CNTH = AArch64_INS_CNTH, + ARM64_INS_CNTP = AArch64_INS_CNTP, + ARM64_INS_CNTW = AArch64_INS_CNTW, + ARM64_INS_CNT = AArch64_INS_CNT, + ARM64_INS_COMPACT = AArch64_INS_COMPACT, + ARM64_INS_CPYE = AArch64_INS_CPYE, + ARM64_INS_CPYEN = AArch64_INS_CPYEN, + ARM64_INS_CPYERN = AArch64_INS_CPYERN, + ARM64_INS_CPYERT = AArch64_INS_CPYERT, + ARM64_INS_CPYERTN = AArch64_INS_CPYERTN, + ARM64_INS_CPYERTRN = AArch64_INS_CPYERTRN, + ARM64_INS_CPYERTWN = AArch64_INS_CPYERTWN, + ARM64_INS_CPYET = AArch64_INS_CPYET, + ARM64_INS_CPYETN = AArch64_INS_CPYETN, + ARM64_INS_CPYETRN = AArch64_INS_CPYETRN, + ARM64_INS_CPYETWN = AArch64_INS_CPYETWN, + ARM64_INS_CPYEWN = AArch64_INS_CPYEWN, + ARM64_INS_CPYEWT = AArch64_INS_CPYEWT, + ARM64_INS_CPYEWTN = AArch64_INS_CPYEWTN, + ARM64_INS_CPYEWTRN = AArch64_INS_CPYEWTRN, + ARM64_INS_CPYEWTWN = AArch64_INS_CPYEWTWN, + ARM64_INS_CPYFE = AArch64_INS_CPYFE, + ARM64_INS_CPYFEN = AArch64_INS_CPYFEN, + ARM64_INS_CPYFERN = AArch64_INS_CPYFERN, + ARM64_INS_CPYFERT = AArch64_INS_CPYFERT, + ARM64_INS_CPYFERTN = AArch64_INS_CPYFERTN, + ARM64_INS_CPYFERTRN = AArch64_INS_CPYFERTRN, + ARM64_INS_CPYFERTWN = AArch64_INS_CPYFERTWN, + ARM64_INS_CPYFET = AArch64_INS_CPYFET, + ARM64_INS_CPYFETN = AArch64_INS_CPYFETN, + ARM64_INS_CPYFETRN = AArch64_INS_CPYFETRN, + ARM64_INS_CPYFETWN = AArch64_INS_CPYFETWN, + ARM64_INS_CPYFEWN = AArch64_INS_CPYFEWN, + ARM64_INS_CPYFEWT = AArch64_INS_CPYFEWT, + ARM64_INS_CPYFEWTN = AArch64_INS_CPYFEWTN, + ARM64_INS_CPYFEWTRN = AArch64_INS_CPYFEWTRN, + ARM64_INS_CPYFEWTWN = AArch64_INS_CPYFEWTWN, + ARM64_INS_CPYFM = AArch64_INS_CPYFM, + ARM64_INS_CPYFMN = AArch64_INS_CPYFMN, + ARM64_INS_CPYFMRN = AArch64_INS_CPYFMRN, + ARM64_INS_CPYFMRT = AArch64_INS_CPYFMRT, + ARM64_INS_CPYFMRTN = AArch64_INS_CPYFMRTN, + ARM64_INS_CPYFMRTRN = AArch64_INS_CPYFMRTRN, + ARM64_INS_CPYFMRTWN = AArch64_INS_CPYFMRTWN, + ARM64_INS_CPYFMT = AArch64_INS_CPYFMT, + ARM64_INS_CPYFMTN = AArch64_INS_CPYFMTN, + ARM64_INS_CPYFMTRN = AArch64_INS_CPYFMTRN, + ARM64_INS_CPYFMTWN = AArch64_INS_CPYFMTWN, + ARM64_INS_CPYFMWN = AArch64_INS_CPYFMWN, + ARM64_INS_CPYFMWT = AArch64_INS_CPYFMWT, + ARM64_INS_CPYFMWTN = AArch64_INS_CPYFMWTN, + ARM64_INS_CPYFMWTRN = AArch64_INS_CPYFMWTRN, + ARM64_INS_CPYFMWTWN = AArch64_INS_CPYFMWTWN, + ARM64_INS_CPYFP = AArch64_INS_CPYFP, + ARM64_INS_CPYFPN = AArch64_INS_CPYFPN, + ARM64_INS_CPYFPRN = AArch64_INS_CPYFPRN, + ARM64_INS_CPYFPRT = AArch64_INS_CPYFPRT, + ARM64_INS_CPYFPRTN = AArch64_INS_CPYFPRTN, + ARM64_INS_CPYFPRTRN = AArch64_INS_CPYFPRTRN, + ARM64_INS_CPYFPRTWN = AArch64_INS_CPYFPRTWN, + ARM64_INS_CPYFPT = AArch64_INS_CPYFPT, + ARM64_INS_CPYFPTN = AArch64_INS_CPYFPTN, + ARM64_INS_CPYFPTRN = AArch64_INS_CPYFPTRN, + ARM64_INS_CPYFPTWN = AArch64_INS_CPYFPTWN, + ARM64_INS_CPYFPWN = AArch64_INS_CPYFPWN, + ARM64_INS_CPYFPWT = AArch64_INS_CPYFPWT, + ARM64_INS_CPYFPWTN = AArch64_INS_CPYFPWTN, + ARM64_INS_CPYFPWTRN = AArch64_INS_CPYFPWTRN, + ARM64_INS_CPYFPWTWN = AArch64_INS_CPYFPWTWN, + ARM64_INS_CPYM = AArch64_INS_CPYM, + ARM64_INS_CPYMN = AArch64_INS_CPYMN, + ARM64_INS_CPYMRN = AArch64_INS_CPYMRN, + ARM64_INS_CPYMRT = AArch64_INS_CPYMRT, + ARM64_INS_CPYMRTN = AArch64_INS_CPYMRTN, + ARM64_INS_CPYMRTRN = AArch64_INS_CPYMRTRN, + ARM64_INS_CPYMRTWN = AArch64_INS_CPYMRTWN, + ARM64_INS_CPYMT = AArch64_INS_CPYMT, + ARM64_INS_CPYMTN = AArch64_INS_CPYMTN, + ARM64_INS_CPYMTRN = AArch64_INS_CPYMTRN, + ARM64_INS_CPYMTWN = AArch64_INS_CPYMTWN, + ARM64_INS_CPYMWN = AArch64_INS_CPYMWN, + ARM64_INS_CPYMWT = AArch64_INS_CPYMWT, + ARM64_INS_CPYMWTN = AArch64_INS_CPYMWTN, + ARM64_INS_CPYMWTRN = AArch64_INS_CPYMWTRN, + ARM64_INS_CPYMWTWN = AArch64_INS_CPYMWTWN, + ARM64_INS_CPYP = AArch64_INS_CPYP, + ARM64_INS_CPYPN = AArch64_INS_CPYPN, + ARM64_INS_CPYPRN = AArch64_INS_CPYPRN, + ARM64_INS_CPYPRT = AArch64_INS_CPYPRT, + ARM64_INS_CPYPRTN = AArch64_INS_CPYPRTN, + ARM64_INS_CPYPRTRN = AArch64_INS_CPYPRTRN, + ARM64_INS_CPYPRTWN = AArch64_INS_CPYPRTWN, + ARM64_INS_CPYPT = AArch64_INS_CPYPT, + ARM64_INS_CPYPTN = AArch64_INS_CPYPTN, + ARM64_INS_CPYPTRN = AArch64_INS_CPYPTRN, + ARM64_INS_CPYPTWN = AArch64_INS_CPYPTWN, + ARM64_INS_CPYPWN = AArch64_INS_CPYPWN, + ARM64_INS_CPYPWT = AArch64_INS_CPYPWT, + ARM64_INS_CPYPWTN = AArch64_INS_CPYPWTN, + ARM64_INS_CPYPWTRN = AArch64_INS_CPYPWTRN, + ARM64_INS_CPYPWTWN = AArch64_INS_CPYPWTWN, + ARM64_INS_CPY = AArch64_INS_CPY, + ARM64_INS_CRC32B = AArch64_INS_CRC32B, + ARM64_INS_CRC32CB = AArch64_INS_CRC32CB, + ARM64_INS_CRC32CH = AArch64_INS_CRC32CH, + ARM64_INS_CRC32CW = AArch64_INS_CRC32CW, + ARM64_INS_CRC32CX = AArch64_INS_CRC32CX, + ARM64_INS_CRC32H = AArch64_INS_CRC32H, + ARM64_INS_CRC32W = AArch64_INS_CRC32W, + ARM64_INS_CRC32X = AArch64_INS_CRC32X, + ARM64_INS_CSEL = AArch64_INS_CSEL, + ARM64_INS_CSINC = AArch64_INS_CSINC, + ARM64_INS_CSINV = AArch64_INS_CSINV, + ARM64_INS_CSNEG = AArch64_INS_CSNEG, + ARM64_INS_CTERMEQ = AArch64_INS_CTERMEQ, + ARM64_INS_CTERMNE = AArch64_INS_CTERMNE, + ARM64_INS_CTZ = AArch64_INS_CTZ, + ARM64_INS_DCPS1 = AArch64_INS_DCPS1, + ARM64_INS_DCPS2 = AArch64_INS_DCPS2, + ARM64_INS_DCPS3 = AArch64_INS_DCPS3, + ARM64_INS_DECB = AArch64_INS_DECB, + ARM64_INS_DECD = AArch64_INS_DECD, + ARM64_INS_DECH = AArch64_INS_DECH, + ARM64_INS_DECP = AArch64_INS_DECP, + ARM64_INS_DECW = AArch64_INS_DECW, + ARM64_INS_DMB = AArch64_INS_DMB, + ARM64_INS_DRPS = AArch64_INS_DRPS, + ARM64_INS_DSB = AArch64_INS_DSB, + ARM64_INS_DUPM = AArch64_INS_DUPM, + ARM64_INS_DUPQ = AArch64_INS_DUPQ, + ARM64_INS_DUP = AArch64_INS_DUP, + ARM64_INS_MOV = AArch64_INS_MOV, + ARM64_INS_EON = AArch64_INS_EON, + ARM64_INS_EOR3 = AArch64_INS_EOR3, + ARM64_INS_EORBT = AArch64_INS_EORBT, + ARM64_INS_EORQV = AArch64_INS_EORQV, + ARM64_INS_EORS = AArch64_INS_EORS, + ARM64_INS_EORTB = AArch64_INS_EORTB, + ARM64_INS_EORV = AArch64_INS_EORV, + ARM64_INS_EOR = AArch64_INS_EOR, + ARM64_INS_ERET = AArch64_INS_ERET, + ARM64_INS_ERETAA = AArch64_INS_ERETAA, + ARM64_INS_ERETAB = AArch64_INS_ERETAB, + ARM64_INS_EXTQ = AArch64_INS_EXTQ, + ARM64_INS_MOVA = AArch64_INS_MOVA, + ARM64_INS_EXTR = AArch64_INS_EXTR, + ARM64_INS_EXT = AArch64_INS_EXT, + ARM64_INS_FABD = AArch64_INS_FABD, + ARM64_INS_FABS = AArch64_INS_FABS, + ARM64_INS_FACGE = AArch64_INS_FACGE, + ARM64_INS_FACGT = AArch64_INS_FACGT, + ARM64_INS_FADDA = AArch64_INS_FADDA, + ARM64_INS_FADD = AArch64_INS_FADD, + ARM64_INS_FADDP = AArch64_INS_FADDP, + ARM64_INS_FADDQV = AArch64_INS_FADDQV, + ARM64_INS_FADDV = AArch64_INS_FADDV, + ARM64_INS_FCADD = AArch64_INS_FCADD, + ARM64_INS_FCCMP = AArch64_INS_FCCMP, + ARM64_INS_FCCMPE = AArch64_INS_FCCMPE, + ARM64_INS_FCLAMP = AArch64_INS_FCLAMP, + ARM64_INS_FCMEQ = AArch64_INS_FCMEQ, + ARM64_INS_FCMGE = AArch64_INS_FCMGE, + ARM64_INS_FCMGT = AArch64_INS_FCMGT, + ARM64_INS_FCMLA = AArch64_INS_FCMLA, + ARM64_INS_FCMLE = AArch64_INS_FCMLE, + ARM64_INS_FCMLT = AArch64_INS_FCMLT, + ARM64_INS_FCMNE = AArch64_INS_FCMNE, + ARM64_INS_FCMP = AArch64_INS_FCMP, + ARM64_INS_FCMPE = AArch64_INS_FCMPE, + ARM64_INS_FCMUO = AArch64_INS_FCMUO, + ARM64_INS_FCPY = AArch64_INS_FCPY, + ARM64_INS_FCSEL = AArch64_INS_FCSEL, + ARM64_INS_FCVTAS = AArch64_INS_FCVTAS, + ARM64_INS_FCVTAU = AArch64_INS_FCVTAU, + ARM64_INS_FCVT = AArch64_INS_FCVT, + ARM64_INS_FCVTLT = AArch64_INS_FCVTLT, + ARM64_INS_FCVTL = AArch64_INS_FCVTL, + ARM64_INS_FCVTL2 = AArch64_INS_FCVTL2, + ARM64_INS_FCVTMS = AArch64_INS_FCVTMS, + ARM64_INS_FCVTMU = AArch64_INS_FCVTMU, + ARM64_INS_FCVTNS = AArch64_INS_FCVTNS, + ARM64_INS_FCVTNT = AArch64_INS_FCVTNT, + ARM64_INS_FCVTNU = AArch64_INS_FCVTNU, + ARM64_INS_FCVTN = AArch64_INS_FCVTN, + ARM64_INS_FCVTN2 = AArch64_INS_FCVTN2, + ARM64_INS_FCVTPS = AArch64_INS_FCVTPS, + ARM64_INS_FCVTPU = AArch64_INS_FCVTPU, + ARM64_INS_FCVTXNT = AArch64_INS_FCVTXNT, + ARM64_INS_FCVTXN = AArch64_INS_FCVTXN, + ARM64_INS_FCVTXN2 = AArch64_INS_FCVTXN2, + ARM64_INS_FCVTX = AArch64_INS_FCVTX, + ARM64_INS_FCVTZS = AArch64_INS_FCVTZS, + ARM64_INS_FCVTZU = AArch64_INS_FCVTZU, + ARM64_INS_FDIV = AArch64_INS_FDIV, + ARM64_INS_FDIVR = AArch64_INS_FDIVR, + ARM64_INS_FDOT = AArch64_INS_FDOT, + ARM64_INS_FDUP = AArch64_INS_FDUP, + ARM64_INS_FEXPA = AArch64_INS_FEXPA, + ARM64_INS_FJCVTZS = AArch64_INS_FJCVTZS, + ARM64_INS_FLOGB = AArch64_INS_FLOGB, + ARM64_INS_FMADD = AArch64_INS_FMADD, + ARM64_INS_FMAD = AArch64_INS_FMAD, + ARM64_INS_FMAX = AArch64_INS_FMAX, + ARM64_INS_FMAXNM = AArch64_INS_FMAXNM, + ARM64_INS_FMAXNMP = AArch64_INS_FMAXNMP, + ARM64_INS_FMAXNMQV = AArch64_INS_FMAXNMQV, + ARM64_INS_FMAXNMV = AArch64_INS_FMAXNMV, + ARM64_INS_FMAXP = AArch64_INS_FMAXP, + ARM64_INS_FMAXQV = AArch64_INS_FMAXQV, + ARM64_INS_FMAXV = AArch64_INS_FMAXV, + ARM64_INS_FMIN = AArch64_INS_FMIN, + ARM64_INS_FMINNM = AArch64_INS_FMINNM, + ARM64_INS_FMINNMP = AArch64_INS_FMINNMP, + ARM64_INS_FMINNMQV = AArch64_INS_FMINNMQV, + ARM64_INS_FMINNMV = AArch64_INS_FMINNMV, + ARM64_INS_FMINP = AArch64_INS_FMINP, + ARM64_INS_FMINQV = AArch64_INS_FMINQV, + ARM64_INS_FMINV = AArch64_INS_FMINV, + ARM64_INS_FMLAL2 = AArch64_INS_FMLAL2, + ARM64_INS_FMLALB = AArch64_INS_FMLALB, + ARM64_INS_FMLALT = AArch64_INS_FMLALT, + ARM64_INS_FMLAL = AArch64_INS_FMLAL, + ARM64_INS_FMLA = AArch64_INS_FMLA, + ARM64_INS_FMLSL2 = AArch64_INS_FMLSL2, + ARM64_INS_FMLSLB = AArch64_INS_FMLSLB, + ARM64_INS_FMLSLT = AArch64_INS_FMLSLT, + ARM64_INS_FMLSL = AArch64_INS_FMLSL, + ARM64_INS_FMLS = AArch64_INS_FMLS, + ARM64_INS_FMMLA = AArch64_INS_FMMLA, + ARM64_INS_FMOPA = AArch64_INS_FMOPA, + ARM64_INS_FMOPS = AArch64_INS_FMOPS, + ARM64_INS_FMOV = AArch64_INS_FMOV, + ARM64_INS_FMSB = AArch64_INS_FMSB, + ARM64_INS_FMSUB = AArch64_INS_FMSUB, + ARM64_INS_FMUL = AArch64_INS_FMUL, + ARM64_INS_FMULX = AArch64_INS_FMULX, + ARM64_INS_FNEG = AArch64_INS_FNEG, + ARM64_INS_FNMADD = AArch64_INS_FNMADD, + ARM64_INS_FNMAD = AArch64_INS_FNMAD, + ARM64_INS_FNMLA = AArch64_INS_FNMLA, + ARM64_INS_FNMLS = AArch64_INS_FNMLS, + ARM64_INS_FNMSB = AArch64_INS_FNMSB, + ARM64_INS_FNMSUB = AArch64_INS_FNMSUB, + ARM64_INS_FNMUL = AArch64_INS_FNMUL, + ARM64_INS_FRECPE = AArch64_INS_FRECPE, + ARM64_INS_FRECPS = AArch64_INS_FRECPS, + ARM64_INS_FRECPX = AArch64_INS_FRECPX, + ARM64_INS_FRINT32X = AArch64_INS_FRINT32X, + ARM64_INS_FRINT32Z = AArch64_INS_FRINT32Z, + ARM64_INS_FRINT64X = AArch64_INS_FRINT64X, + ARM64_INS_FRINT64Z = AArch64_INS_FRINT64Z, + ARM64_INS_FRINTA = AArch64_INS_FRINTA, + ARM64_INS_FRINTI = AArch64_INS_FRINTI, + ARM64_INS_FRINTM = AArch64_INS_FRINTM, + ARM64_INS_FRINTN = AArch64_INS_FRINTN, + ARM64_INS_FRINTP = AArch64_INS_FRINTP, + ARM64_INS_FRINTX = AArch64_INS_FRINTX, + ARM64_INS_FRINTZ = AArch64_INS_FRINTZ, + ARM64_INS_FRSQRTE = AArch64_INS_FRSQRTE, + ARM64_INS_FRSQRTS = AArch64_INS_FRSQRTS, + ARM64_INS_FSCALE = AArch64_INS_FSCALE, + ARM64_INS_FSQRT = AArch64_INS_FSQRT, + ARM64_INS_FSUB = AArch64_INS_FSUB, + ARM64_INS_FSUBR = AArch64_INS_FSUBR, + ARM64_INS_FTMAD = AArch64_INS_FTMAD, + ARM64_INS_FTSMUL = AArch64_INS_FTSMUL, + ARM64_INS_FTSSEL = AArch64_INS_FTSSEL, + ARM64_INS_FVDOT = AArch64_INS_FVDOT, + ARM64_INS_LD1B = AArch64_INS_LD1B, + ARM64_INS_LD1D = AArch64_INS_LD1D, + ARM64_INS_LD1H = AArch64_INS_LD1H, + ARM64_INS_LD1Q = AArch64_INS_LD1Q, + ARM64_INS_LD1SB = AArch64_INS_LD1SB, + ARM64_INS_LD1SH = AArch64_INS_LD1SH, + ARM64_INS_LD1SW = AArch64_INS_LD1SW, + ARM64_INS_LD1W = AArch64_INS_LD1W, + ARM64_INS_LDFF1B = AArch64_INS_LDFF1B, + ARM64_INS_LDFF1D = AArch64_INS_LDFF1D, + ARM64_INS_LDFF1H = AArch64_INS_LDFF1H, + ARM64_INS_LDFF1SB = AArch64_INS_LDFF1SB, + ARM64_INS_LDFF1SH = AArch64_INS_LDFF1SH, + ARM64_INS_LDFF1SW = AArch64_INS_LDFF1SW, + ARM64_INS_LDFF1W = AArch64_INS_LDFF1W, + ARM64_INS_GMI = AArch64_INS_GMI, + ARM64_INS_HISTCNT = AArch64_INS_HISTCNT, + ARM64_INS_HISTSEG = AArch64_INS_HISTSEG, + ARM64_INS_HLT = AArch64_INS_HLT, + ARM64_INS_HVC = AArch64_INS_HVC, + ARM64_INS_INCB = AArch64_INS_INCB, + ARM64_INS_INCD = AArch64_INS_INCD, + ARM64_INS_INCH = AArch64_INS_INCH, + ARM64_INS_INCP = AArch64_INS_INCP, + ARM64_INS_INCW = AArch64_INS_INCW, + ARM64_INS_INDEX = AArch64_INS_INDEX, + ARM64_INS_INSR = AArch64_INS_INSR, + ARM64_INS_INS = AArch64_INS_INS, + ARM64_INS_IRG = AArch64_INS_IRG, + ARM64_INS_ISB = AArch64_INS_ISB, + ARM64_INS_LASTA = AArch64_INS_LASTA, + ARM64_INS_LASTB = AArch64_INS_LASTB, + ARM64_INS_LD1 = AArch64_INS_LD1, + ARM64_INS_LD1RB = AArch64_INS_LD1RB, + ARM64_INS_LD1RD = AArch64_INS_LD1RD, + ARM64_INS_LD1RH = AArch64_INS_LD1RH, + ARM64_INS_LD1ROB = AArch64_INS_LD1ROB, + ARM64_INS_LD1ROD = AArch64_INS_LD1ROD, + ARM64_INS_LD1ROH = AArch64_INS_LD1ROH, + ARM64_INS_LD1ROW = AArch64_INS_LD1ROW, + ARM64_INS_LD1RQB = AArch64_INS_LD1RQB, + ARM64_INS_LD1RQD = AArch64_INS_LD1RQD, + ARM64_INS_LD1RQH = AArch64_INS_LD1RQH, + ARM64_INS_LD1RQW = AArch64_INS_LD1RQW, + ARM64_INS_LD1RSB = AArch64_INS_LD1RSB, + ARM64_INS_LD1RSH = AArch64_INS_LD1RSH, + ARM64_INS_LD1RSW = AArch64_INS_LD1RSW, + ARM64_INS_LD1RW = AArch64_INS_LD1RW, + ARM64_INS_LD1R = AArch64_INS_LD1R, + ARM64_INS_LD2B = AArch64_INS_LD2B, + ARM64_INS_LD2D = AArch64_INS_LD2D, + ARM64_INS_LD2H = AArch64_INS_LD2H, + ARM64_INS_LD2Q = AArch64_INS_LD2Q, + ARM64_INS_LD2R = AArch64_INS_LD2R, + ARM64_INS_LD2 = AArch64_INS_LD2, + ARM64_INS_LD2W = AArch64_INS_LD2W, + ARM64_INS_LD3B = AArch64_INS_LD3B, + ARM64_INS_LD3D = AArch64_INS_LD3D, + ARM64_INS_LD3H = AArch64_INS_LD3H, + ARM64_INS_LD3Q = AArch64_INS_LD3Q, + ARM64_INS_LD3R = AArch64_INS_LD3R, + ARM64_INS_LD3 = AArch64_INS_LD3, + ARM64_INS_LD3W = AArch64_INS_LD3W, + ARM64_INS_LD4B = AArch64_INS_LD4B, + ARM64_INS_LD4D = AArch64_INS_LD4D, + ARM64_INS_LD4 = AArch64_INS_LD4, + ARM64_INS_LD4H = AArch64_INS_LD4H, + ARM64_INS_LD4Q = AArch64_INS_LD4Q, + ARM64_INS_LD4R = AArch64_INS_LD4R, + ARM64_INS_LD4W = AArch64_INS_LD4W, + ARM64_INS_LD64B = AArch64_INS_LD64B, + ARM64_INS_LDADDAB = AArch64_INS_LDADDAB, + ARM64_INS_LDADDAH = AArch64_INS_LDADDAH, + ARM64_INS_LDADDALB = AArch64_INS_LDADDALB, + ARM64_INS_LDADDALH = AArch64_INS_LDADDALH, + ARM64_INS_LDADDAL = AArch64_INS_LDADDAL, + ARM64_INS_LDADDA = AArch64_INS_LDADDA, + ARM64_INS_LDADDB = AArch64_INS_LDADDB, + ARM64_INS_LDADDH = AArch64_INS_LDADDH, + ARM64_INS_LDADDLB = AArch64_INS_LDADDLB, + ARM64_INS_LDADDLH = AArch64_INS_LDADDLH, + ARM64_INS_LDADDL = AArch64_INS_LDADDL, + ARM64_INS_LDADD = AArch64_INS_LDADD, + ARM64_INS_LDAP1 = AArch64_INS_LDAP1, + ARM64_INS_LDAPRB = AArch64_INS_LDAPRB, + ARM64_INS_LDAPRH = AArch64_INS_LDAPRH, + ARM64_INS_LDAPR = AArch64_INS_LDAPR, + ARM64_INS_LDAPURB = AArch64_INS_LDAPURB, + ARM64_INS_LDAPURH = AArch64_INS_LDAPURH, + ARM64_INS_LDAPURSB = AArch64_INS_LDAPURSB, + ARM64_INS_LDAPURSH = AArch64_INS_LDAPURSH, + ARM64_INS_LDAPURSW = AArch64_INS_LDAPURSW, + ARM64_INS_LDAPUR = AArch64_INS_LDAPUR, + ARM64_INS_LDARB = AArch64_INS_LDARB, + ARM64_INS_LDARH = AArch64_INS_LDARH, + ARM64_INS_LDAR = AArch64_INS_LDAR, + ARM64_INS_LDAXP = AArch64_INS_LDAXP, + ARM64_INS_LDAXRB = AArch64_INS_LDAXRB, + ARM64_INS_LDAXRH = AArch64_INS_LDAXRH, + ARM64_INS_LDAXR = AArch64_INS_LDAXR, + ARM64_INS_LDCLRAB = AArch64_INS_LDCLRAB, + ARM64_INS_LDCLRAH = AArch64_INS_LDCLRAH, + ARM64_INS_LDCLRALB = AArch64_INS_LDCLRALB, + ARM64_INS_LDCLRALH = AArch64_INS_LDCLRALH, + ARM64_INS_LDCLRAL = AArch64_INS_LDCLRAL, + ARM64_INS_LDCLRA = AArch64_INS_LDCLRA, + ARM64_INS_LDCLRB = AArch64_INS_LDCLRB, + ARM64_INS_LDCLRH = AArch64_INS_LDCLRH, + ARM64_INS_LDCLRLB = AArch64_INS_LDCLRLB, + ARM64_INS_LDCLRLH = AArch64_INS_LDCLRLH, + ARM64_INS_LDCLRL = AArch64_INS_LDCLRL, + ARM64_INS_LDCLRP = AArch64_INS_LDCLRP, + ARM64_INS_LDCLRPA = AArch64_INS_LDCLRPA, + ARM64_INS_LDCLRPAL = AArch64_INS_LDCLRPAL, + ARM64_INS_LDCLRPL = AArch64_INS_LDCLRPL, + ARM64_INS_LDCLR = AArch64_INS_LDCLR, + ARM64_INS_LDEORAB = AArch64_INS_LDEORAB, + ARM64_INS_LDEORAH = AArch64_INS_LDEORAH, + ARM64_INS_LDEORALB = AArch64_INS_LDEORALB, + ARM64_INS_LDEORALH = AArch64_INS_LDEORALH, + ARM64_INS_LDEORAL = AArch64_INS_LDEORAL, + ARM64_INS_LDEORA = AArch64_INS_LDEORA, + ARM64_INS_LDEORB = AArch64_INS_LDEORB, + ARM64_INS_LDEORH = AArch64_INS_LDEORH, + ARM64_INS_LDEORLB = AArch64_INS_LDEORLB, + ARM64_INS_LDEORLH = AArch64_INS_LDEORLH, + ARM64_INS_LDEORL = AArch64_INS_LDEORL, + ARM64_INS_LDEOR = AArch64_INS_LDEOR, + ARM64_INS_LDG = AArch64_INS_LDG, + ARM64_INS_LDGM = AArch64_INS_LDGM, + ARM64_INS_LDIAPP = AArch64_INS_LDIAPP, + ARM64_INS_LDLARB = AArch64_INS_LDLARB, + ARM64_INS_LDLARH = AArch64_INS_LDLARH, + ARM64_INS_LDLAR = AArch64_INS_LDLAR, + ARM64_INS_LDNF1B = AArch64_INS_LDNF1B, + ARM64_INS_LDNF1D = AArch64_INS_LDNF1D, + ARM64_INS_LDNF1H = AArch64_INS_LDNF1H, + ARM64_INS_LDNF1SB = AArch64_INS_LDNF1SB, + ARM64_INS_LDNF1SH = AArch64_INS_LDNF1SH, + ARM64_INS_LDNF1SW = AArch64_INS_LDNF1SW, + ARM64_INS_LDNF1W = AArch64_INS_LDNF1W, + ARM64_INS_LDNP = AArch64_INS_LDNP, + ARM64_INS_LDNT1B = AArch64_INS_LDNT1B, + ARM64_INS_LDNT1D = AArch64_INS_LDNT1D, + ARM64_INS_LDNT1H = AArch64_INS_LDNT1H, + ARM64_INS_LDNT1SB = AArch64_INS_LDNT1SB, + ARM64_INS_LDNT1SH = AArch64_INS_LDNT1SH, + ARM64_INS_LDNT1SW = AArch64_INS_LDNT1SW, + ARM64_INS_LDNT1W = AArch64_INS_LDNT1W, + ARM64_INS_LDP = AArch64_INS_LDP, + ARM64_INS_LDPSW = AArch64_INS_LDPSW, + ARM64_INS_LDRAA = AArch64_INS_LDRAA, + ARM64_INS_LDRAB = AArch64_INS_LDRAB, + ARM64_INS_LDRB = AArch64_INS_LDRB, + ARM64_INS_LDR = AArch64_INS_LDR, + ARM64_INS_LDRH = AArch64_INS_LDRH, + ARM64_INS_LDRSB = AArch64_INS_LDRSB, + ARM64_INS_LDRSH = AArch64_INS_LDRSH, + ARM64_INS_LDRSW = AArch64_INS_LDRSW, + ARM64_INS_LDSETAB = AArch64_INS_LDSETAB, + ARM64_INS_LDSETAH = AArch64_INS_LDSETAH, + ARM64_INS_LDSETALB = AArch64_INS_LDSETALB, + ARM64_INS_LDSETALH = AArch64_INS_LDSETALH, + ARM64_INS_LDSETAL = AArch64_INS_LDSETAL, + ARM64_INS_LDSETA = AArch64_INS_LDSETA, + ARM64_INS_LDSETB = AArch64_INS_LDSETB, + ARM64_INS_LDSETH = AArch64_INS_LDSETH, + ARM64_INS_LDSETLB = AArch64_INS_LDSETLB, + ARM64_INS_LDSETLH = AArch64_INS_LDSETLH, + ARM64_INS_LDSETL = AArch64_INS_LDSETL, + ARM64_INS_LDSETP = AArch64_INS_LDSETP, + ARM64_INS_LDSETPA = AArch64_INS_LDSETPA, + ARM64_INS_LDSETPAL = AArch64_INS_LDSETPAL, + ARM64_INS_LDSETPL = AArch64_INS_LDSETPL, + ARM64_INS_LDSET = AArch64_INS_LDSET, + ARM64_INS_LDSMAXAB = AArch64_INS_LDSMAXAB, + ARM64_INS_LDSMAXAH = AArch64_INS_LDSMAXAH, + ARM64_INS_LDSMAXALB = AArch64_INS_LDSMAXALB, + ARM64_INS_LDSMAXALH = AArch64_INS_LDSMAXALH, + ARM64_INS_LDSMAXAL = AArch64_INS_LDSMAXAL, + ARM64_INS_LDSMAXA = AArch64_INS_LDSMAXA, + ARM64_INS_LDSMAXB = AArch64_INS_LDSMAXB, + ARM64_INS_LDSMAXH = AArch64_INS_LDSMAXH, + ARM64_INS_LDSMAXLB = AArch64_INS_LDSMAXLB, + ARM64_INS_LDSMAXLH = AArch64_INS_LDSMAXLH, + ARM64_INS_LDSMAXL = AArch64_INS_LDSMAXL, + ARM64_INS_LDSMAX = AArch64_INS_LDSMAX, + ARM64_INS_LDSMINAB = AArch64_INS_LDSMINAB, + ARM64_INS_LDSMINAH = AArch64_INS_LDSMINAH, + ARM64_INS_LDSMINALB = AArch64_INS_LDSMINALB, + ARM64_INS_LDSMINALH = AArch64_INS_LDSMINALH, + ARM64_INS_LDSMINAL = AArch64_INS_LDSMINAL, + ARM64_INS_LDSMINA = AArch64_INS_LDSMINA, + ARM64_INS_LDSMINB = AArch64_INS_LDSMINB, + ARM64_INS_LDSMINH = AArch64_INS_LDSMINH, + ARM64_INS_LDSMINLB = AArch64_INS_LDSMINLB, + ARM64_INS_LDSMINLH = AArch64_INS_LDSMINLH, + ARM64_INS_LDSMINL = AArch64_INS_LDSMINL, + ARM64_INS_LDSMIN = AArch64_INS_LDSMIN, + ARM64_INS_LDTRB = AArch64_INS_LDTRB, + ARM64_INS_LDTRH = AArch64_INS_LDTRH, + ARM64_INS_LDTRSB = AArch64_INS_LDTRSB, + ARM64_INS_LDTRSH = AArch64_INS_LDTRSH, + ARM64_INS_LDTRSW = AArch64_INS_LDTRSW, + ARM64_INS_LDTR = AArch64_INS_LDTR, + ARM64_INS_LDUMAXAB = AArch64_INS_LDUMAXAB, + ARM64_INS_LDUMAXAH = AArch64_INS_LDUMAXAH, + ARM64_INS_LDUMAXALB = AArch64_INS_LDUMAXALB, + ARM64_INS_LDUMAXALH = AArch64_INS_LDUMAXALH, + ARM64_INS_LDUMAXAL = AArch64_INS_LDUMAXAL, + ARM64_INS_LDUMAXA = AArch64_INS_LDUMAXA, + ARM64_INS_LDUMAXB = AArch64_INS_LDUMAXB, + ARM64_INS_LDUMAXH = AArch64_INS_LDUMAXH, + ARM64_INS_LDUMAXLB = AArch64_INS_LDUMAXLB, + ARM64_INS_LDUMAXLH = AArch64_INS_LDUMAXLH, + ARM64_INS_LDUMAXL = AArch64_INS_LDUMAXL, + ARM64_INS_LDUMAX = AArch64_INS_LDUMAX, + ARM64_INS_LDUMINAB = AArch64_INS_LDUMINAB, + ARM64_INS_LDUMINAH = AArch64_INS_LDUMINAH, + ARM64_INS_LDUMINALB = AArch64_INS_LDUMINALB, + ARM64_INS_LDUMINALH = AArch64_INS_LDUMINALH, + ARM64_INS_LDUMINAL = AArch64_INS_LDUMINAL, + ARM64_INS_LDUMINA = AArch64_INS_LDUMINA, + ARM64_INS_LDUMINB = AArch64_INS_LDUMINB, + ARM64_INS_LDUMINH = AArch64_INS_LDUMINH, + ARM64_INS_LDUMINLB = AArch64_INS_LDUMINLB, + ARM64_INS_LDUMINLH = AArch64_INS_LDUMINLH, + ARM64_INS_LDUMINL = AArch64_INS_LDUMINL, + ARM64_INS_LDUMIN = AArch64_INS_LDUMIN, + ARM64_INS_LDURB = AArch64_INS_LDURB, + ARM64_INS_LDUR = AArch64_INS_LDUR, + ARM64_INS_LDURH = AArch64_INS_LDURH, + ARM64_INS_LDURSB = AArch64_INS_LDURSB, + ARM64_INS_LDURSH = AArch64_INS_LDURSH, + ARM64_INS_LDURSW = AArch64_INS_LDURSW, + ARM64_INS_LDXP = AArch64_INS_LDXP, + ARM64_INS_LDXRB = AArch64_INS_LDXRB, + ARM64_INS_LDXRH = AArch64_INS_LDXRH, + ARM64_INS_LDXR = AArch64_INS_LDXR, + ARM64_INS_LSLR = AArch64_INS_LSLR, + ARM64_INS_LSL = AArch64_INS_LSL, + ARM64_INS_LSRR = AArch64_INS_LSRR, + ARM64_INS_LSR = AArch64_INS_LSR, + ARM64_INS_LUTI2 = AArch64_INS_LUTI2, + ARM64_INS_LUTI4 = AArch64_INS_LUTI4, + ARM64_INS_MADD = AArch64_INS_MADD, + ARM64_INS_MAD = AArch64_INS_MAD, + ARM64_INS_MATCH = AArch64_INS_MATCH, + ARM64_INS_MLA = AArch64_INS_MLA, + ARM64_INS_MLS = AArch64_INS_MLS, + ARM64_INS_SETGE = AArch64_INS_SETGE, + ARM64_INS_SETGEN = AArch64_INS_SETGEN, + ARM64_INS_SETGET = AArch64_INS_SETGET, + ARM64_INS_SETGETN = AArch64_INS_SETGETN, + ARM64_INS_MOVAZ = AArch64_INS_MOVAZ, + ARM64_INS_MOVI = AArch64_INS_MOVI, + ARM64_INS_MOVK = AArch64_INS_MOVK, + ARM64_INS_MOVN = AArch64_INS_MOVN, + ARM64_INS_MOVPRFX = AArch64_INS_MOVPRFX, + ARM64_INS_MOVT = AArch64_INS_MOVT, + ARM64_INS_MOVZ = AArch64_INS_MOVZ, + ARM64_INS_MRRS = AArch64_INS_MRRS, + ARM64_INS_MRS = AArch64_INS_MRS, + ARM64_INS_MSB = AArch64_INS_MSB, + ARM64_INS_MSR = AArch64_INS_MSR, + ARM64_INS_MSRR = AArch64_INS_MSRR, + ARM64_INS_MSUB = AArch64_INS_MSUB, + ARM64_INS_MUL = AArch64_INS_MUL, + ARM64_INS_MVNI = AArch64_INS_MVNI, + ARM64_INS_NANDS = AArch64_INS_NANDS, + ARM64_INS_NAND = AArch64_INS_NAND, + ARM64_INS_NBSL = AArch64_INS_NBSL, + ARM64_INS_NEG = AArch64_INS_NEG, + ARM64_INS_NMATCH = AArch64_INS_NMATCH, + ARM64_INS_NORS = AArch64_INS_NORS, + ARM64_INS_NOR = AArch64_INS_NOR, + ARM64_INS_NOT = AArch64_INS_NOT, + ARM64_INS_ORNS = AArch64_INS_ORNS, + ARM64_INS_ORN = AArch64_INS_ORN, + ARM64_INS_ORQV = AArch64_INS_ORQV, + ARM64_INS_ORRS = AArch64_INS_ORRS, + ARM64_INS_ORR = AArch64_INS_ORR, + ARM64_INS_ORV = AArch64_INS_ORV, + ARM64_INS_PACDA = AArch64_INS_PACDA, + ARM64_INS_PACDB = AArch64_INS_PACDB, + ARM64_INS_PACDZA = AArch64_INS_PACDZA, + ARM64_INS_PACDZB = AArch64_INS_PACDZB, + ARM64_INS_PACGA = AArch64_INS_PACGA, + ARM64_INS_PACIA = AArch64_INS_PACIA, + ARM64_INS_PACIB = AArch64_INS_PACIB, + ARM64_INS_PACIZA = AArch64_INS_PACIZA, + ARM64_INS_PACIZB = AArch64_INS_PACIZB, + ARM64_INS_PEXT = AArch64_INS_PEXT, + ARM64_INS_PFALSE = AArch64_INS_PFALSE, + ARM64_INS_PFIRST = AArch64_INS_PFIRST, + ARM64_INS_PMOV = AArch64_INS_PMOV, + ARM64_INS_PMULLB = AArch64_INS_PMULLB, + ARM64_INS_PMULLT = AArch64_INS_PMULLT, + ARM64_INS_PMULL2 = AArch64_INS_PMULL2, + ARM64_INS_PMULL = AArch64_INS_PMULL, + ARM64_INS_PMUL = AArch64_INS_PMUL, + ARM64_INS_PNEXT = AArch64_INS_PNEXT, + ARM64_INS_PRFB = AArch64_INS_PRFB, + ARM64_INS_PRFD = AArch64_INS_PRFD, + ARM64_INS_PRFH = AArch64_INS_PRFH, + ARM64_INS_PRFM = AArch64_INS_PRFM, + ARM64_INS_PRFUM = AArch64_INS_PRFUM, + ARM64_INS_PRFW = AArch64_INS_PRFW, + ARM64_INS_PSEL = AArch64_INS_PSEL, + ARM64_INS_PTEST = AArch64_INS_PTEST, + ARM64_INS_PTRUES = AArch64_INS_PTRUES, + ARM64_INS_PTRUE = AArch64_INS_PTRUE, + ARM64_INS_PUNPKHI = AArch64_INS_PUNPKHI, + ARM64_INS_PUNPKLO = AArch64_INS_PUNPKLO, + ARM64_INS_RADDHNB = AArch64_INS_RADDHNB, + ARM64_INS_RADDHNT = AArch64_INS_RADDHNT, + ARM64_INS_RADDHN = AArch64_INS_RADDHN, + ARM64_INS_RADDHN2 = AArch64_INS_RADDHN2, + ARM64_INS_RAX1 = AArch64_INS_RAX1, + ARM64_INS_RBIT = AArch64_INS_RBIT, + ARM64_INS_RCWCAS = AArch64_INS_RCWCAS, + ARM64_INS_RCWCASA = AArch64_INS_RCWCASA, + ARM64_INS_RCWCASAL = AArch64_INS_RCWCASAL, + ARM64_INS_RCWCASL = AArch64_INS_RCWCASL, + ARM64_INS_RCWCASP = AArch64_INS_RCWCASP, + ARM64_INS_RCWCASPA = AArch64_INS_RCWCASPA, + ARM64_INS_RCWCASPAL = AArch64_INS_RCWCASPAL, + ARM64_INS_RCWCASPL = AArch64_INS_RCWCASPL, + ARM64_INS_RCWCLR = AArch64_INS_RCWCLR, + ARM64_INS_RCWCLRA = AArch64_INS_RCWCLRA, + ARM64_INS_RCWCLRAL = AArch64_INS_RCWCLRAL, + ARM64_INS_RCWCLRL = AArch64_INS_RCWCLRL, + ARM64_INS_RCWCLRP = AArch64_INS_RCWCLRP, + ARM64_INS_RCWCLRPA = AArch64_INS_RCWCLRPA, + ARM64_INS_RCWCLRPAL = AArch64_INS_RCWCLRPAL, + ARM64_INS_RCWCLRPL = AArch64_INS_RCWCLRPL, + ARM64_INS_RCWSCLR = AArch64_INS_RCWSCLR, + ARM64_INS_RCWSCLRA = AArch64_INS_RCWSCLRA, + ARM64_INS_RCWSCLRAL = AArch64_INS_RCWSCLRAL, + ARM64_INS_RCWSCLRL = AArch64_INS_RCWSCLRL, + ARM64_INS_RCWSCLRP = AArch64_INS_RCWSCLRP, + ARM64_INS_RCWSCLRPA = AArch64_INS_RCWSCLRPA, + ARM64_INS_RCWSCLRPAL = AArch64_INS_RCWSCLRPAL, + ARM64_INS_RCWSCLRPL = AArch64_INS_RCWSCLRPL, + ARM64_INS_RCWSCAS = AArch64_INS_RCWSCAS, + ARM64_INS_RCWSCASA = AArch64_INS_RCWSCASA, + ARM64_INS_RCWSCASAL = AArch64_INS_RCWSCASAL, + ARM64_INS_RCWSCASL = AArch64_INS_RCWSCASL, + ARM64_INS_RCWSCASP = AArch64_INS_RCWSCASP, + ARM64_INS_RCWSCASPA = AArch64_INS_RCWSCASPA, + ARM64_INS_RCWSCASPAL = AArch64_INS_RCWSCASPAL, + ARM64_INS_RCWSCASPL = AArch64_INS_RCWSCASPL, + ARM64_INS_RCWSET = AArch64_INS_RCWSET, + ARM64_INS_RCWSETA = AArch64_INS_RCWSETA, + ARM64_INS_RCWSETAL = AArch64_INS_RCWSETAL, + ARM64_INS_RCWSETL = AArch64_INS_RCWSETL, + ARM64_INS_RCWSETP = AArch64_INS_RCWSETP, + ARM64_INS_RCWSETPA = AArch64_INS_RCWSETPA, + ARM64_INS_RCWSETPAL = AArch64_INS_RCWSETPAL, + ARM64_INS_RCWSETPL = AArch64_INS_RCWSETPL, + ARM64_INS_RCWSSET = AArch64_INS_RCWSSET, + ARM64_INS_RCWSSETA = AArch64_INS_RCWSSETA, + ARM64_INS_RCWSSETAL = AArch64_INS_RCWSSETAL, + ARM64_INS_RCWSSETL = AArch64_INS_RCWSSETL, + ARM64_INS_RCWSSETP = AArch64_INS_RCWSSETP, + ARM64_INS_RCWSSETPA = AArch64_INS_RCWSSETPA, + ARM64_INS_RCWSSETPAL = AArch64_INS_RCWSSETPAL, + ARM64_INS_RCWSSETPL = AArch64_INS_RCWSSETPL, + ARM64_INS_RCWSWP = AArch64_INS_RCWSWP, + ARM64_INS_RCWSWPA = AArch64_INS_RCWSWPA, + ARM64_INS_RCWSWPAL = AArch64_INS_RCWSWPAL, + ARM64_INS_RCWSWPL = AArch64_INS_RCWSWPL, + ARM64_INS_RCWSWPP = AArch64_INS_RCWSWPP, + ARM64_INS_RCWSWPPA = AArch64_INS_RCWSWPPA, + ARM64_INS_RCWSWPPAL = AArch64_INS_RCWSWPPAL, + ARM64_INS_RCWSWPPL = AArch64_INS_RCWSWPPL, + ARM64_INS_RCWSSWP = AArch64_INS_RCWSSWP, + ARM64_INS_RCWSSWPA = AArch64_INS_RCWSSWPA, + ARM64_INS_RCWSSWPAL = AArch64_INS_RCWSSWPAL, + ARM64_INS_RCWSSWPL = AArch64_INS_RCWSSWPL, + ARM64_INS_RCWSSWPP = AArch64_INS_RCWSSWPP, + ARM64_INS_RCWSSWPPA = AArch64_INS_RCWSSWPPA, + ARM64_INS_RCWSSWPPAL = AArch64_INS_RCWSSWPPAL, + ARM64_INS_RCWSSWPPL = AArch64_INS_RCWSSWPPL, + ARM64_INS_RDFFRS = AArch64_INS_RDFFRS, + ARM64_INS_RDFFR = AArch64_INS_RDFFR, + ARM64_INS_RDSVL = AArch64_INS_RDSVL, + ARM64_INS_RDVL = AArch64_INS_RDVL, + ARM64_INS_RET = AArch64_INS_RET, + ARM64_INS_RETAA = AArch64_INS_RETAA, + ARM64_INS_RETAB = AArch64_INS_RETAB, + ARM64_INS_REV16 = AArch64_INS_REV16, + ARM64_INS_REV32 = AArch64_INS_REV32, + ARM64_INS_REV64 = AArch64_INS_REV64, + ARM64_INS_REVB = AArch64_INS_REVB, + ARM64_INS_REVD = AArch64_INS_REVD, + ARM64_INS_REVH = AArch64_INS_REVH, + ARM64_INS_REVW = AArch64_INS_REVW, + ARM64_INS_REV = AArch64_INS_REV, + ARM64_INS_RMIF = AArch64_INS_RMIF, + ARM64_INS_ROR = AArch64_INS_ROR, + ARM64_INS_RPRFM = AArch64_INS_RPRFM, + ARM64_INS_RSHRNB = AArch64_INS_RSHRNB, + ARM64_INS_RSHRNT = AArch64_INS_RSHRNT, + ARM64_INS_RSHRN2 = AArch64_INS_RSHRN2, + ARM64_INS_RSHRN = AArch64_INS_RSHRN, + ARM64_INS_RSUBHNB = AArch64_INS_RSUBHNB, + ARM64_INS_RSUBHNT = AArch64_INS_RSUBHNT, + ARM64_INS_RSUBHN = AArch64_INS_RSUBHN, + ARM64_INS_RSUBHN2 = AArch64_INS_RSUBHN2, + ARM64_INS_SABALB = AArch64_INS_SABALB, + ARM64_INS_SABALT = AArch64_INS_SABALT, + ARM64_INS_SABAL2 = AArch64_INS_SABAL2, + ARM64_INS_SABAL = AArch64_INS_SABAL, + ARM64_INS_SABA = AArch64_INS_SABA, + ARM64_INS_SABDLB = AArch64_INS_SABDLB, + ARM64_INS_SABDLT = AArch64_INS_SABDLT, + ARM64_INS_SABDL2 = AArch64_INS_SABDL2, + ARM64_INS_SABDL = AArch64_INS_SABDL, + ARM64_INS_SABD = AArch64_INS_SABD, + ARM64_INS_SADALP = AArch64_INS_SADALP, + ARM64_INS_SADDLBT = AArch64_INS_SADDLBT, + ARM64_INS_SADDLB = AArch64_INS_SADDLB, + ARM64_INS_SADDLP = AArch64_INS_SADDLP, + ARM64_INS_SADDLT = AArch64_INS_SADDLT, + ARM64_INS_SADDLV = AArch64_INS_SADDLV, + ARM64_INS_SADDL2 = AArch64_INS_SADDL2, + ARM64_INS_SADDL = AArch64_INS_SADDL, + ARM64_INS_SADDV = AArch64_INS_SADDV, + ARM64_INS_SADDWB = AArch64_INS_SADDWB, + ARM64_INS_SADDWT = AArch64_INS_SADDWT, + ARM64_INS_SADDW2 = AArch64_INS_SADDW2, + ARM64_INS_SADDW = AArch64_INS_SADDW, + ARM64_INS_SB = AArch64_INS_SB, + ARM64_INS_SBCLB = AArch64_INS_SBCLB, + ARM64_INS_SBCLT = AArch64_INS_SBCLT, + ARM64_INS_SBCS = AArch64_INS_SBCS, + ARM64_INS_SBC = AArch64_INS_SBC, + ARM64_INS_SBFM = AArch64_INS_SBFM, + ARM64_INS_SCLAMP = AArch64_INS_SCLAMP, + ARM64_INS_SCVTF = AArch64_INS_SCVTF, + ARM64_INS_SDIVR = AArch64_INS_SDIVR, + ARM64_INS_SDIV = AArch64_INS_SDIV, + ARM64_INS_SDOT = AArch64_INS_SDOT, + ARM64_INS_SEL = AArch64_INS_SEL, + ARM64_INS_SETE = AArch64_INS_SETE, + ARM64_INS_SETEN = AArch64_INS_SETEN, + ARM64_INS_SETET = AArch64_INS_SETET, + ARM64_INS_SETETN = AArch64_INS_SETETN, + ARM64_INS_SETF16 = AArch64_INS_SETF16, + ARM64_INS_SETF8 = AArch64_INS_SETF8, + ARM64_INS_SETFFR = AArch64_INS_SETFFR, + ARM64_INS_SETGM = AArch64_INS_SETGM, + ARM64_INS_SETGMN = AArch64_INS_SETGMN, + ARM64_INS_SETGMT = AArch64_INS_SETGMT, + ARM64_INS_SETGMTN = AArch64_INS_SETGMTN, + ARM64_INS_SETGP = AArch64_INS_SETGP, + ARM64_INS_SETGPN = AArch64_INS_SETGPN, + ARM64_INS_SETGPT = AArch64_INS_SETGPT, + ARM64_INS_SETGPTN = AArch64_INS_SETGPTN, + ARM64_INS_SETM = AArch64_INS_SETM, + ARM64_INS_SETMN = AArch64_INS_SETMN, + ARM64_INS_SETMT = AArch64_INS_SETMT, + ARM64_INS_SETMTN = AArch64_INS_SETMTN, + ARM64_INS_SETP = AArch64_INS_SETP, + ARM64_INS_SETPN = AArch64_INS_SETPN, + ARM64_INS_SETPT = AArch64_INS_SETPT, + ARM64_INS_SETPTN = AArch64_INS_SETPTN, + ARM64_INS_SHA1C = AArch64_INS_SHA1C, + ARM64_INS_SHA1H = AArch64_INS_SHA1H, + ARM64_INS_SHA1M = AArch64_INS_SHA1M, + ARM64_INS_SHA1P = AArch64_INS_SHA1P, + ARM64_INS_SHA1SU0 = AArch64_INS_SHA1SU0, + ARM64_INS_SHA1SU1 = AArch64_INS_SHA1SU1, + ARM64_INS_SHA256H2 = AArch64_INS_SHA256H2, + ARM64_INS_SHA256H = AArch64_INS_SHA256H, + ARM64_INS_SHA256SU0 = AArch64_INS_SHA256SU0, + ARM64_INS_SHA256SU1 = AArch64_INS_SHA256SU1, + ARM64_INS_SHA512H = AArch64_INS_SHA512H, + ARM64_INS_SHA512H2 = AArch64_INS_SHA512H2, + ARM64_INS_SHA512SU0 = AArch64_INS_SHA512SU0, + ARM64_INS_SHA512SU1 = AArch64_INS_SHA512SU1, + ARM64_INS_SHADD = AArch64_INS_SHADD, + ARM64_INS_SHLL2 = AArch64_INS_SHLL2, + ARM64_INS_SHLL = AArch64_INS_SHLL, + ARM64_INS_SHL = AArch64_INS_SHL, + ARM64_INS_SHRNB = AArch64_INS_SHRNB, + ARM64_INS_SHRNT = AArch64_INS_SHRNT, + ARM64_INS_SHRN2 = AArch64_INS_SHRN2, + ARM64_INS_SHRN = AArch64_INS_SHRN, + ARM64_INS_SHSUBR = AArch64_INS_SHSUBR, + ARM64_INS_SHSUB = AArch64_INS_SHSUB, + ARM64_INS_SLI = AArch64_INS_SLI, + ARM64_INS_SM3PARTW1 = AArch64_INS_SM3PARTW1, + ARM64_INS_SM3PARTW2 = AArch64_INS_SM3PARTW2, + ARM64_INS_SM3SS1 = AArch64_INS_SM3SS1, + ARM64_INS_SM3TT1A = AArch64_INS_SM3TT1A, + ARM64_INS_SM3TT1B = AArch64_INS_SM3TT1B, + ARM64_INS_SM3TT2A = AArch64_INS_SM3TT2A, + ARM64_INS_SM3TT2B = AArch64_INS_SM3TT2B, + ARM64_INS_SM4E = AArch64_INS_SM4E, + ARM64_INS_SM4EKEY = AArch64_INS_SM4EKEY, + ARM64_INS_SMADDL = AArch64_INS_SMADDL, + ARM64_INS_SMAXP = AArch64_INS_SMAXP, + ARM64_INS_SMAXQV = AArch64_INS_SMAXQV, + ARM64_INS_SMAXV = AArch64_INS_SMAXV, + ARM64_INS_SMAX = AArch64_INS_SMAX, + ARM64_INS_SMC = AArch64_INS_SMC, + ARM64_INS_SMINP = AArch64_INS_SMINP, + ARM64_INS_SMINQV = AArch64_INS_SMINQV, + ARM64_INS_SMINV = AArch64_INS_SMINV, + ARM64_INS_SMIN = AArch64_INS_SMIN, + ARM64_INS_SMLALB = AArch64_INS_SMLALB, + ARM64_INS_SMLALL = AArch64_INS_SMLALL, + ARM64_INS_SMLALT = AArch64_INS_SMLALT, + ARM64_INS_SMLAL = AArch64_INS_SMLAL, + ARM64_INS_SMLAL2 = AArch64_INS_SMLAL2, + ARM64_INS_SMLSLB = AArch64_INS_SMLSLB, + ARM64_INS_SMLSLL = AArch64_INS_SMLSLL, + ARM64_INS_SMLSLT = AArch64_INS_SMLSLT, + ARM64_INS_SMLSL = AArch64_INS_SMLSL, + ARM64_INS_SMLSL2 = AArch64_INS_SMLSL2, + ARM64_INS_SMMLA = AArch64_INS_SMMLA, + ARM64_INS_SMOPA = AArch64_INS_SMOPA, + ARM64_INS_SMOPS = AArch64_INS_SMOPS, + ARM64_INS_SMOV = AArch64_INS_SMOV, + ARM64_INS_SMSUBL = AArch64_INS_SMSUBL, + ARM64_INS_SMULH = AArch64_INS_SMULH, + ARM64_INS_SMULLB = AArch64_INS_SMULLB, + ARM64_INS_SMULLT = AArch64_INS_SMULLT, + ARM64_INS_SMULL2 = AArch64_INS_SMULL2, + ARM64_INS_SMULL = AArch64_INS_SMULL, + ARM64_INS_SPLICE = AArch64_INS_SPLICE, + ARM64_INS_SQABS = AArch64_INS_SQABS, + ARM64_INS_SQADD = AArch64_INS_SQADD, + ARM64_INS_SQCADD = AArch64_INS_SQCADD, + ARM64_INS_SQCVTN = AArch64_INS_SQCVTN, + ARM64_INS_SQCVTUN = AArch64_INS_SQCVTUN, + ARM64_INS_SQCVTU = AArch64_INS_SQCVTU, + ARM64_INS_SQCVT = AArch64_INS_SQCVT, + ARM64_INS_SQDECB = AArch64_INS_SQDECB, + ARM64_INS_SQDECD = AArch64_INS_SQDECD, + ARM64_INS_SQDECH = AArch64_INS_SQDECH, + ARM64_INS_SQDECP = AArch64_INS_SQDECP, + ARM64_INS_SQDECW = AArch64_INS_SQDECW, + ARM64_INS_SQDMLALBT = AArch64_INS_SQDMLALBT, + ARM64_INS_SQDMLALB = AArch64_INS_SQDMLALB, + ARM64_INS_SQDMLALT = AArch64_INS_SQDMLALT, + ARM64_INS_SQDMLAL = AArch64_INS_SQDMLAL, + ARM64_INS_SQDMLAL2 = AArch64_INS_SQDMLAL2, + ARM64_INS_SQDMLSLBT = AArch64_INS_SQDMLSLBT, + ARM64_INS_SQDMLSLB = AArch64_INS_SQDMLSLB, + ARM64_INS_SQDMLSLT = AArch64_INS_SQDMLSLT, + ARM64_INS_SQDMLSL = AArch64_INS_SQDMLSL, + ARM64_INS_SQDMLSL2 = AArch64_INS_SQDMLSL2, + ARM64_INS_SQDMULH = AArch64_INS_SQDMULH, + ARM64_INS_SQDMULLB = AArch64_INS_SQDMULLB, + ARM64_INS_SQDMULLT = AArch64_INS_SQDMULLT, + ARM64_INS_SQDMULL = AArch64_INS_SQDMULL, + ARM64_INS_SQDMULL2 = AArch64_INS_SQDMULL2, + ARM64_INS_SQINCB = AArch64_INS_SQINCB, + ARM64_INS_SQINCD = AArch64_INS_SQINCD, + ARM64_INS_SQINCH = AArch64_INS_SQINCH, + ARM64_INS_SQINCP = AArch64_INS_SQINCP, + ARM64_INS_SQINCW = AArch64_INS_SQINCW, + ARM64_INS_SQNEG = AArch64_INS_SQNEG, + ARM64_INS_SQRDCMLAH = AArch64_INS_SQRDCMLAH, + ARM64_INS_SQRDMLAH = AArch64_INS_SQRDMLAH, + ARM64_INS_SQRDMLSH = AArch64_INS_SQRDMLSH, + ARM64_INS_SQRDMULH = AArch64_INS_SQRDMULH, + ARM64_INS_SQRSHLR = AArch64_INS_SQRSHLR, + ARM64_INS_SQRSHL = AArch64_INS_SQRSHL, + ARM64_INS_SQRSHRNB = AArch64_INS_SQRSHRNB, + ARM64_INS_SQRSHRNT = AArch64_INS_SQRSHRNT, + ARM64_INS_SQRSHRN = AArch64_INS_SQRSHRN, + ARM64_INS_SQRSHRN2 = AArch64_INS_SQRSHRN2, + ARM64_INS_SQRSHRUNB = AArch64_INS_SQRSHRUNB, + ARM64_INS_SQRSHRUNT = AArch64_INS_SQRSHRUNT, + ARM64_INS_SQRSHRUN = AArch64_INS_SQRSHRUN, + ARM64_INS_SQRSHRUN2 = AArch64_INS_SQRSHRUN2, + ARM64_INS_SQRSHRU = AArch64_INS_SQRSHRU, + ARM64_INS_SQRSHR = AArch64_INS_SQRSHR, + ARM64_INS_SQSHLR = AArch64_INS_SQSHLR, + ARM64_INS_SQSHLU = AArch64_INS_SQSHLU, + ARM64_INS_SQSHL = AArch64_INS_SQSHL, + ARM64_INS_SQSHRNB = AArch64_INS_SQSHRNB, + ARM64_INS_SQSHRNT = AArch64_INS_SQSHRNT, + ARM64_INS_SQSHRN = AArch64_INS_SQSHRN, + ARM64_INS_SQSHRN2 = AArch64_INS_SQSHRN2, + ARM64_INS_SQSHRUNB = AArch64_INS_SQSHRUNB, + ARM64_INS_SQSHRUNT = AArch64_INS_SQSHRUNT, + ARM64_INS_SQSHRUN = AArch64_INS_SQSHRUN, + ARM64_INS_SQSHRUN2 = AArch64_INS_SQSHRUN2, + ARM64_INS_SQSUBR = AArch64_INS_SQSUBR, + ARM64_INS_SQSUB = AArch64_INS_SQSUB, + ARM64_INS_SQXTNB = AArch64_INS_SQXTNB, + ARM64_INS_SQXTNT = AArch64_INS_SQXTNT, + ARM64_INS_SQXTN2 = AArch64_INS_SQXTN2, + ARM64_INS_SQXTN = AArch64_INS_SQXTN, + ARM64_INS_SQXTUNB = AArch64_INS_SQXTUNB, + ARM64_INS_SQXTUNT = AArch64_INS_SQXTUNT, + ARM64_INS_SQXTUN2 = AArch64_INS_SQXTUN2, + ARM64_INS_SQXTUN = AArch64_INS_SQXTUN, + ARM64_INS_SRHADD = AArch64_INS_SRHADD, + ARM64_INS_SRI = AArch64_INS_SRI, + ARM64_INS_SRSHLR = AArch64_INS_SRSHLR, + ARM64_INS_SRSHL = AArch64_INS_SRSHL, + ARM64_INS_SRSHR = AArch64_INS_SRSHR, + ARM64_INS_SRSRA = AArch64_INS_SRSRA, + ARM64_INS_SSHLLB = AArch64_INS_SSHLLB, + ARM64_INS_SSHLLT = AArch64_INS_SSHLLT, + ARM64_INS_SSHLL2 = AArch64_INS_SSHLL2, + ARM64_INS_SSHLL = AArch64_INS_SSHLL, + ARM64_INS_SSHL = AArch64_INS_SSHL, + ARM64_INS_SSHR = AArch64_INS_SSHR, + ARM64_INS_SSRA = AArch64_INS_SSRA, + ARM64_INS_ST1B = AArch64_INS_ST1B, + ARM64_INS_ST1D = AArch64_INS_ST1D, + ARM64_INS_ST1H = AArch64_INS_ST1H, + ARM64_INS_ST1Q = AArch64_INS_ST1Q, + ARM64_INS_ST1W = AArch64_INS_ST1W, + ARM64_INS_SSUBLBT = AArch64_INS_SSUBLBT, + ARM64_INS_SSUBLB = AArch64_INS_SSUBLB, + ARM64_INS_SSUBLTB = AArch64_INS_SSUBLTB, + ARM64_INS_SSUBLT = AArch64_INS_SSUBLT, + ARM64_INS_SSUBL2 = AArch64_INS_SSUBL2, + ARM64_INS_SSUBL = AArch64_INS_SSUBL, + ARM64_INS_SSUBWB = AArch64_INS_SSUBWB, + ARM64_INS_SSUBWT = AArch64_INS_SSUBWT, + ARM64_INS_SSUBW2 = AArch64_INS_SSUBW2, + ARM64_INS_SSUBW = AArch64_INS_SSUBW, + ARM64_INS_ST1 = AArch64_INS_ST1, + ARM64_INS_ST2B = AArch64_INS_ST2B, + ARM64_INS_ST2D = AArch64_INS_ST2D, + ARM64_INS_ST2G = AArch64_INS_ST2G, + ARM64_INS_ST2H = AArch64_INS_ST2H, + ARM64_INS_ST2Q = AArch64_INS_ST2Q, + ARM64_INS_ST2 = AArch64_INS_ST2, + ARM64_INS_ST2W = AArch64_INS_ST2W, + ARM64_INS_ST3B = AArch64_INS_ST3B, + ARM64_INS_ST3D = AArch64_INS_ST3D, + ARM64_INS_ST3H = AArch64_INS_ST3H, + ARM64_INS_ST3Q = AArch64_INS_ST3Q, + ARM64_INS_ST3 = AArch64_INS_ST3, + ARM64_INS_ST3W = AArch64_INS_ST3W, + ARM64_INS_ST4B = AArch64_INS_ST4B, + ARM64_INS_ST4D = AArch64_INS_ST4D, + ARM64_INS_ST4 = AArch64_INS_ST4, + ARM64_INS_ST4H = AArch64_INS_ST4H, + ARM64_INS_ST4Q = AArch64_INS_ST4Q, + ARM64_INS_ST4W = AArch64_INS_ST4W, + ARM64_INS_ST64B = AArch64_INS_ST64B, + ARM64_INS_ST64BV = AArch64_INS_ST64BV, + ARM64_INS_ST64BV0 = AArch64_INS_ST64BV0, + ARM64_INS_STGM = AArch64_INS_STGM, + ARM64_INS_STG = AArch64_INS_STG, + ARM64_INS_STGP = AArch64_INS_STGP, + ARM64_INS_STILP = AArch64_INS_STILP, + ARM64_INS_STL1 = AArch64_INS_STL1, + ARM64_INS_STLLRB = AArch64_INS_STLLRB, + ARM64_INS_STLLRH = AArch64_INS_STLLRH, + ARM64_INS_STLLR = AArch64_INS_STLLR, + ARM64_INS_STLRB = AArch64_INS_STLRB, + ARM64_INS_STLRH = AArch64_INS_STLRH, + ARM64_INS_STLR = AArch64_INS_STLR, + ARM64_INS_STLURB = AArch64_INS_STLURB, + ARM64_INS_STLURH = AArch64_INS_STLURH, + ARM64_INS_STLUR = AArch64_INS_STLUR, + ARM64_INS_STLXP = AArch64_INS_STLXP, + ARM64_INS_STLXRB = AArch64_INS_STLXRB, + ARM64_INS_STLXRH = AArch64_INS_STLXRH, + ARM64_INS_STLXR = AArch64_INS_STLXR, + ARM64_INS_STNP = AArch64_INS_STNP, + ARM64_INS_STNT1B = AArch64_INS_STNT1B, + ARM64_INS_STNT1D = AArch64_INS_STNT1D, + ARM64_INS_STNT1H = AArch64_INS_STNT1H, + ARM64_INS_STNT1W = AArch64_INS_STNT1W, + ARM64_INS_STP = AArch64_INS_STP, + ARM64_INS_STRB = AArch64_INS_STRB, + ARM64_INS_STR = AArch64_INS_STR, + ARM64_INS_STRH = AArch64_INS_STRH, + ARM64_INS_STTRB = AArch64_INS_STTRB, + ARM64_INS_STTRH = AArch64_INS_STTRH, + ARM64_INS_STTR = AArch64_INS_STTR, + ARM64_INS_STURB = AArch64_INS_STURB, + ARM64_INS_STUR = AArch64_INS_STUR, + ARM64_INS_STURH = AArch64_INS_STURH, + ARM64_INS_STXP = AArch64_INS_STXP, + ARM64_INS_STXRB = AArch64_INS_STXRB, + ARM64_INS_STXRH = AArch64_INS_STXRH, + ARM64_INS_STXR = AArch64_INS_STXR, + ARM64_INS_STZ2G = AArch64_INS_STZ2G, + ARM64_INS_STZGM = AArch64_INS_STZGM, + ARM64_INS_STZG = AArch64_INS_STZG, + ARM64_INS_SUBG = AArch64_INS_SUBG, + ARM64_INS_SUBHNB = AArch64_INS_SUBHNB, + ARM64_INS_SUBHNT = AArch64_INS_SUBHNT, + ARM64_INS_SUBHN = AArch64_INS_SUBHN, + ARM64_INS_SUBHN2 = AArch64_INS_SUBHN2, + ARM64_INS_SUBP = AArch64_INS_SUBP, + ARM64_INS_SUBPS = AArch64_INS_SUBPS, + ARM64_INS_SUBR = AArch64_INS_SUBR, + ARM64_INS_SUBS = AArch64_INS_SUBS, + ARM64_INS_SUB = AArch64_INS_SUB, + ARM64_INS_SUDOT = AArch64_INS_SUDOT, + ARM64_INS_SUMLALL = AArch64_INS_SUMLALL, + ARM64_INS_SUMOPA = AArch64_INS_SUMOPA, + ARM64_INS_SUMOPS = AArch64_INS_SUMOPS, + ARM64_INS_SUNPKHI = AArch64_INS_SUNPKHI, + ARM64_INS_SUNPKLO = AArch64_INS_SUNPKLO, + ARM64_INS_SUNPK = AArch64_INS_SUNPK, + ARM64_INS_SUQADD = AArch64_INS_SUQADD, + ARM64_INS_SUVDOT = AArch64_INS_SUVDOT, + ARM64_INS_SVC = AArch64_INS_SVC, + ARM64_INS_SVDOT = AArch64_INS_SVDOT, + ARM64_INS_SWPAB = AArch64_INS_SWPAB, + ARM64_INS_SWPAH = AArch64_INS_SWPAH, + ARM64_INS_SWPALB = AArch64_INS_SWPALB, + ARM64_INS_SWPALH = AArch64_INS_SWPALH, + ARM64_INS_SWPAL = AArch64_INS_SWPAL, + ARM64_INS_SWPA = AArch64_INS_SWPA, + ARM64_INS_SWPB = AArch64_INS_SWPB, + ARM64_INS_SWPH = AArch64_INS_SWPH, + ARM64_INS_SWPLB = AArch64_INS_SWPLB, + ARM64_INS_SWPLH = AArch64_INS_SWPLH, + ARM64_INS_SWPL = AArch64_INS_SWPL, + ARM64_INS_SWPP = AArch64_INS_SWPP, + ARM64_INS_SWPPA = AArch64_INS_SWPPA, + ARM64_INS_SWPPAL = AArch64_INS_SWPPAL, + ARM64_INS_SWPPL = AArch64_INS_SWPPL, + ARM64_INS_SWP = AArch64_INS_SWP, + ARM64_INS_SXTB = AArch64_INS_SXTB, + ARM64_INS_SXTH = AArch64_INS_SXTH, + ARM64_INS_SXTW = AArch64_INS_SXTW, + ARM64_INS_SYSL = AArch64_INS_SYSL, + ARM64_INS_SYSP = AArch64_INS_SYSP, + ARM64_INS_SYS = AArch64_INS_SYS, + ARM64_INS_TBLQ = AArch64_INS_TBLQ, + ARM64_INS_TBL = AArch64_INS_TBL, + ARM64_INS_TBNZ = AArch64_INS_TBNZ, + ARM64_INS_TBXQ = AArch64_INS_TBXQ, + ARM64_INS_TBX = AArch64_INS_TBX, + ARM64_INS_TBZ = AArch64_INS_TBZ, + ARM64_INS_TCANCEL = AArch64_INS_TCANCEL, + ARM64_INS_TCOMMIT = AArch64_INS_TCOMMIT, + ARM64_INS_TRCIT = AArch64_INS_TRCIT, + ARM64_INS_TRN1 = AArch64_INS_TRN1, + ARM64_INS_TRN2 = AArch64_INS_TRN2, + ARM64_INS_TSB = AArch64_INS_TSB, + ARM64_INS_TSTART = AArch64_INS_TSTART, + ARM64_INS_TTEST = AArch64_INS_TTEST, + ARM64_INS_UABALB = AArch64_INS_UABALB, + ARM64_INS_UABALT = AArch64_INS_UABALT, + ARM64_INS_UABAL2 = AArch64_INS_UABAL2, + ARM64_INS_UABAL = AArch64_INS_UABAL, + ARM64_INS_UABA = AArch64_INS_UABA, + ARM64_INS_UABDLB = AArch64_INS_UABDLB, + ARM64_INS_UABDLT = AArch64_INS_UABDLT, + ARM64_INS_UABDL2 = AArch64_INS_UABDL2, + ARM64_INS_UABDL = AArch64_INS_UABDL, + ARM64_INS_UABD = AArch64_INS_UABD, + ARM64_INS_UADALP = AArch64_INS_UADALP, + ARM64_INS_UADDLB = AArch64_INS_UADDLB, + ARM64_INS_UADDLP = AArch64_INS_UADDLP, + ARM64_INS_UADDLT = AArch64_INS_UADDLT, + ARM64_INS_UADDLV = AArch64_INS_UADDLV, + ARM64_INS_UADDL2 = AArch64_INS_UADDL2, + ARM64_INS_UADDL = AArch64_INS_UADDL, + ARM64_INS_UADDV = AArch64_INS_UADDV, + ARM64_INS_UADDWB = AArch64_INS_UADDWB, + ARM64_INS_UADDWT = AArch64_INS_UADDWT, + ARM64_INS_UADDW2 = AArch64_INS_UADDW2, + ARM64_INS_UADDW = AArch64_INS_UADDW, + ARM64_INS_UBFM = AArch64_INS_UBFM, + ARM64_INS_UCLAMP = AArch64_INS_UCLAMP, + ARM64_INS_UCVTF = AArch64_INS_UCVTF, + ARM64_INS_UDF = AArch64_INS_UDF, + ARM64_INS_UDIVR = AArch64_INS_UDIVR, + ARM64_INS_UDIV = AArch64_INS_UDIV, + ARM64_INS_UDOT = AArch64_INS_UDOT, + ARM64_INS_UHADD = AArch64_INS_UHADD, + ARM64_INS_UHSUBR = AArch64_INS_UHSUBR, + ARM64_INS_UHSUB = AArch64_INS_UHSUB, + ARM64_INS_UMADDL = AArch64_INS_UMADDL, + ARM64_INS_UMAXP = AArch64_INS_UMAXP, + ARM64_INS_UMAXQV = AArch64_INS_UMAXQV, + ARM64_INS_UMAXV = AArch64_INS_UMAXV, + ARM64_INS_UMAX = AArch64_INS_UMAX, + ARM64_INS_UMINP = AArch64_INS_UMINP, + ARM64_INS_UMINQV = AArch64_INS_UMINQV, + ARM64_INS_UMINV = AArch64_INS_UMINV, + ARM64_INS_UMIN = AArch64_INS_UMIN, + ARM64_INS_UMLALB = AArch64_INS_UMLALB, + ARM64_INS_UMLALL = AArch64_INS_UMLALL, + ARM64_INS_UMLALT = AArch64_INS_UMLALT, + ARM64_INS_UMLAL = AArch64_INS_UMLAL, + ARM64_INS_UMLAL2 = AArch64_INS_UMLAL2, + ARM64_INS_UMLSLB = AArch64_INS_UMLSLB, + ARM64_INS_UMLSLL = AArch64_INS_UMLSLL, + ARM64_INS_UMLSLT = AArch64_INS_UMLSLT, + ARM64_INS_UMLSL = AArch64_INS_UMLSL, + ARM64_INS_UMLSL2 = AArch64_INS_UMLSL2, + ARM64_INS_UMMLA = AArch64_INS_UMMLA, + ARM64_INS_UMOPA = AArch64_INS_UMOPA, + ARM64_INS_UMOPS = AArch64_INS_UMOPS, + ARM64_INS_UMOV = AArch64_INS_UMOV, + ARM64_INS_UMSUBL = AArch64_INS_UMSUBL, + ARM64_INS_UMULH = AArch64_INS_UMULH, + ARM64_INS_UMULLB = AArch64_INS_UMULLB, + ARM64_INS_UMULLT = AArch64_INS_UMULLT, + ARM64_INS_UMULL2 = AArch64_INS_UMULL2, + ARM64_INS_UMULL = AArch64_INS_UMULL, + ARM64_INS_UQADD = AArch64_INS_UQADD, + ARM64_INS_UQCVTN = AArch64_INS_UQCVTN, + ARM64_INS_UQCVT = AArch64_INS_UQCVT, + ARM64_INS_UQDECB = AArch64_INS_UQDECB, + ARM64_INS_UQDECD = AArch64_INS_UQDECD, + ARM64_INS_UQDECH = AArch64_INS_UQDECH, + ARM64_INS_UQDECP = AArch64_INS_UQDECP, + ARM64_INS_UQDECW = AArch64_INS_UQDECW, + ARM64_INS_UQINCB = AArch64_INS_UQINCB, + ARM64_INS_UQINCD = AArch64_INS_UQINCD, + ARM64_INS_UQINCH = AArch64_INS_UQINCH, + ARM64_INS_UQINCP = AArch64_INS_UQINCP, + ARM64_INS_UQINCW = AArch64_INS_UQINCW, + ARM64_INS_UQRSHLR = AArch64_INS_UQRSHLR, + ARM64_INS_UQRSHL = AArch64_INS_UQRSHL, + ARM64_INS_UQRSHRNB = AArch64_INS_UQRSHRNB, + ARM64_INS_UQRSHRNT = AArch64_INS_UQRSHRNT, + ARM64_INS_UQRSHRN = AArch64_INS_UQRSHRN, + ARM64_INS_UQRSHRN2 = AArch64_INS_UQRSHRN2, + ARM64_INS_UQRSHR = AArch64_INS_UQRSHR, + ARM64_INS_UQSHLR = AArch64_INS_UQSHLR, + ARM64_INS_UQSHL = AArch64_INS_UQSHL, + ARM64_INS_UQSHRNB = AArch64_INS_UQSHRNB, + ARM64_INS_UQSHRNT = AArch64_INS_UQSHRNT, + ARM64_INS_UQSHRN = AArch64_INS_UQSHRN, + ARM64_INS_UQSHRN2 = AArch64_INS_UQSHRN2, + ARM64_INS_UQSUBR = AArch64_INS_UQSUBR, + ARM64_INS_UQSUB = AArch64_INS_UQSUB, + ARM64_INS_UQXTNB = AArch64_INS_UQXTNB, + ARM64_INS_UQXTNT = AArch64_INS_UQXTNT, + ARM64_INS_UQXTN2 = AArch64_INS_UQXTN2, + ARM64_INS_UQXTN = AArch64_INS_UQXTN, + ARM64_INS_URECPE = AArch64_INS_URECPE, + ARM64_INS_URHADD = AArch64_INS_URHADD, + ARM64_INS_URSHLR = AArch64_INS_URSHLR, + ARM64_INS_URSHL = AArch64_INS_URSHL, + ARM64_INS_URSHR = AArch64_INS_URSHR, + ARM64_INS_URSQRTE = AArch64_INS_URSQRTE, + ARM64_INS_URSRA = AArch64_INS_URSRA, + ARM64_INS_USDOT = AArch64_INS_USDOT, + ARM64_INS_USHLLB = AArch64_INS_USHLLB, + ARM64_INS_USHLLT = AArch64_INS_USHLLT, + ARM64_INS_USHLL2 = AArch64_INS_USHLL2, + ARM64_INS_USHLL = AArch64_INS_USHLL, + ARM64_INS_USHL = AArch64_INS_USHL, + ARM64_INS_USHR = AArch64_INS_USHR, + ARM64_INS_USMLALL = AArch64_INS_USMLALL, + ARM64_INS_USMMLA = AArch64_INS_USMMLA, + ARM64_INS_USMOPA = AArch64_INS_USMOPA, + ARM64_INS_USMOPS = AArch64_INS_USMOPS, + ARM64_INS_USQADD = AArch64_INS_USQADD, + ARM64_INS_USRA = AArch64_INS_USRA, + ARM64_INS_USUBLB = AArch64_INS_USUBLB, + ARM64_INS_USUBLT = AArch64_INS_USUBLT, + ARM64_INS_USUBL2 = AArch64_INS_USUBL2, + ARM64_INS_USUBL = AArch64_INS_USUBL, + ARM64_INS_USUBWB = AArch64_INS_USUBWB, + ARM64_INS_USUBWT = AArch64_INS_USUBWT, + ARM64_INS_USUBW2 = AArch64_INS_USUBW2, + ARM64_INS_USUBW = AArch64_INS_USUBW, + ARM64_INS_USVDOT = AArch64_INS_USVDOT, + ARM64_INS_UUNPKHI = AArch64_INS_UUNPKHI, + ARM64_INS_UUNPKLO = AArch64_INS_UUNPKLO, + ARM64_INS_UUNPK = AArch64_INS_UUNPK, + ARM64_INS_UVDOT = AArch64_INS_UVDOT, + ARM64_INS_UXTB = AArch64_INS_UXTB, + ARM64_INS_UXTH = AArch64_INS_UXTH, + ARM64_INS_UXTW = AArch64_INS_UXTW, + ARM64_INS_UZP1 = AArch64_INS_UZP1, + ARM64_INS_UZP2 = AArch64_INS_UZP2, + ARM64_INS_UZPQ1 = AArch64_INS_UZPQ1, + ARM64_INS_UZPQ2 = AArch64_INS_UZPQ2, + ARM64_INS_UZP = AArch64_INS_UZP, + ARM64_INS_WFET = AArch64_INS_WFET, + ARM64_INS_WFIT = AArch64_INS_WFIT, + ARM64_INS_WHILEGE = AArch64_INS_WHILEGE, + ARM64_INS_WHILEGT = AArch64_INS_WHILEGT, + ARM64_INS_WHILEHI = AArch64_INS_WHILEHI, + ARM64_INS_WHILEHS = AArch64_INS_WHILEHS, + ARM64_INS_WHILELE = AArch64_INS_WHILELE, + ARM64_INS_WHILELO = AArch64_INS_WHILELO, + ARM64_INS_WHILELS = AArch64_INS_WHILELS, + ARM64_INS_WHILELT = AArch64_INS_WHILELT, + ARM64_INS_WHILERW = AArch64_INS_WHILERW, + ARM64_INS_WHILEWR = AArch64_INS_WHILEWR, + ARM64_INS_WRFFR = AArch64_INS_WRFFR, + ARM64_INS_XAFLAG = AArch64_INS_XAFLAG, + ARM64_INS_XAR = AArch64_INS_XAR, + ARM64_INS_XPACD = AArch64_INS_XPACD, + ARM64_INS_XPACI = AArch64_INS_XPACI, + ARM64_INS_XTN2 = AArch64_INS_XTN2, + ARM64_INS_XTN = AArch64_INS_XTN, + ARM64_INS_ZERO = AArch64_INS_ZERO, + ARM64_INS_ZIP1 = AArch64_INS_ZIP1, + ARM64_INS_ZIP2 = AArch64_INS_ZIP2, + ARM64_INS_ZIPQ1 = AArch64_INS_ZIPQ1, + ARM64_INS_ZIPQ2 = AArch64_INS_ZIPQ2, + ARM64_INS_ZIP = AArch64_INS_ZIP, + + + ARM64_INS_ENDING = AArch64_INS_ENDING, + + ARM64_INS_ALIAS_BEGIN = AArch64_INS_ALIAS_BEGIN, + + ARM64_INS_ALIAS_LDAPUR = AArch64_INS_ALIAS_LDAPUR, + ARM64_INS_ALIAS_STLLRB = AArch64_INS_ALIAS_STLLRB, + ARM64_INS_ALIAS_STLLRH = AArch64_INS_ALIAS_STLLRH, + ARM64_INS_ALIAS_STLLR = AArch64_INS_ALIAS_STLLR, + ARM64_INS_ALIAS_STLRB = AArch64_INS_ALIAS_STLRB, + ARM64_INS_ALIAS_STLRH = AArch64_INS_ALIAS_STLRH, + ARM64_INS_ALIAS_STLR = AArch64_INS_ALIAS_STLR, + ARM64_INS_ALIAS_STLUR = AArch64_INS_ALIAS_STLUR, + ARM64_INS_ALIAS_EOR = AArch64_INS_ALIAS_EOR, + ARM64_INS_ALIAS_AND = AArch64_INS_ALIAS_AND, + ARM64_INS_ALIAS_MOV = AArch64_INS_ALIAS_MOV, + ARM64_INS_ALIAS_LD1B = AArch64_INS_ALIAS_LD1B, + ARM64_INS_ALIAS_LD1SW = AArch64_INS_ALIAS_LD1SW, + ARM64_INS_ALIAS_LD1H = AArch64_INS_ALIAS_LD1H, + ARM64_INS_ALIAS_LD1SH = AArch64_INS_ALIAS_LD1SH, + ARM64_INS_ALIAS_LD1W = AArch64_INS_ALIAS_LD1W, + ARM64_INS_ALIAS_LD1SB = AArch64_INS_ALIAS_LD1SB, + ARM64_INS_ALIAS_LD1D = AArch64_INS_ALIAS_LD1D, + ARM64_INS_ALIAS_LD1RB = AArch64_INS_ALIAS_LD1RB, + ARM64_INS_ALIAS_LD1RSW = AArch64_INS_ALIAS_LD1RSW, + ARM64_INS_ALIAS_LD1RH = AArch64_INS_ALIAS_LD1RH, + ARM64_INS_ALIAS_LD1RSH = AArch64_INS_ALIAS_LD1RSH, + ARM64_INS_ALIAS_LD1RW = AArch64_INS_ALIAS_LD1RW, + ARM64_INS_ALIAS_LD1RSB = AArch64_INS_ALIAS_LD1RSB, + ARM64_INS_ALIAS_LD1RD = AArch64_INS_ALIAS_LD1RD, + ARM64_INS_ALIAS_LD1RQH = AArch64_INS_ALIAS_LD1RQH, + ARM64_INS_ALIAS_LD1RQW = AArch64_INS_ALIAS_LD1RQW, + ARM64_INS_ALIAS_LD1RQD = AArch64_INS_ALIAS_LD1RQD, + ARM64_INS_ALIAS_LDNF1B = AArch64_INS_ALIAS_LDNF1B, + ARM64_INS_ALIAS_LDNF1SW = AArch64_INS_ALIAS_LDNF1SW, + ARM64_INS_ALIAS_LDNF1H = AArch64_INS_ALIAS_LDNF1H, + ARM64_INS_ALIAS_LDNF1SH = AArch64_INS_ALIAS_LDNF1SH, + ARM64_INS_ALIAS_LDNF1W = AArch64_INS_ALIAS_LDNF1W, + ARM64_INS_ALIAS_LDNF1SB = AArch64_INS_ALIAS_LDNF1SB, + ARM64_INS_ALIAS_LDNF1D = AArch64_INS_ALIAS_LDNF1D, + ARM64_INS_ALIAS_LDFF1B = AArch64_INS_ALIAS_LDFF1B, + ARM64_INS_ALIAS_LDFF1SW = AArch64_INS_ALIAS_LDFF1SW, + ARM64_INS_ALIAS_LDFF1H = AArch64_INS_ALIAS_LDFF1H, + ARM64_INS_ALIAS_LDFF1SH = AArch64_INS_ALIAS_LDFF1SH, + ARM64_INS_ALIAS_LDFF1W = AArch64_INS_ALIAS_LDFF1W, + ARM64_INS_ALIAS_LDFF1SB = AArch64_INS_ALIAS_LDFF1SB, + ARM64_INS_ALIAS_LDFF1D = AArch64_INS_ALIAS_LDFF1D, + ARM64_INS_ALIAS_LD3B = AArch64_INS_ALIAS_LD3B, + ARM64_INS_ALIAS_LD4B = AArch64_INS_ALIAS_LD4B, + ARM64_INS_ALIAS_LD2H = AArch64_INS_ALIAS_LD2H, + ARM64_INS_ALIAS_LD3H = AArch64_INS_ALIAS_LD3H, + ARM64_INS_ALIAS_LD4H = AArch64_INS_ALIAS_LD4H, + ARM64_INS_ALIAS_LD2W = AArch64_INS_ALIAS_LD2W, + ARM64_INS_ALIAS_LD3W = AArch64_INS_ALIAS_LD3W, + ARM64_INS_ALIAS_LD4W = AArch64_INS_ALIAS_LD4W, + ARM64_INS_ALIAS_LD2D = AArch64_INS_ALIAS_LD2D, + ARM64_INS_ALIAS_LD3D = AArch64_INS_ALIAS_LD3D, + ARM64_INS_ALIAS_LD4D = AArch64_INS_ALIAS_LD4D, + ARM64_INS_ALIAS_LD2Q = AArch64_INS_ALIAS_LD2Q, + ARM64_INS_ALIAS_LD3Q = AArch64_INS_ALIAS_LD3Q, + ARM64_INS_ALIAS_LD4Q = AArch64_INS_ALIAS_LD4Q, + ARM64_INS_ALIAS_LDNT1H = AArch64_INS_ALIAS_LDNT1H, + ARM64_INS_ALIAS_LDNT1W = AArch64_INS_ALIAS_LDNT1W, + ARM64_INS_ALIAS_LDNT1D = AArch64_INS_ALIAS_LDNT1D, + ARM64_INS_ALIAS_ST1B = AArch64_INS_ALIAS_ST1B, + ARM64_INS_ALIAS_ST1H = AArch64_INS_ALIAS_ST1H, + ARM64_INS_ALIAS_ST1W = AArch64_INS_ALIAS_ST1W, + ARM64_INS_ALIAS_ST1D = AArch64_INS_ALIAS_ST1D, + ARM64_INS_ALIAS_ST3B = AArch64_INS_ALIAS_ST3B, + ARM64_INS_ALIAS_ST4B = AArch64_INS_ALIAS_ST4B, + ARM64_INS_ALIAS_ST2H = AArch64_INS_ALIAS_ST2H, + ARM64_INS_ALIAS_ST3H = AArch64_INS_ALIAS_ST3H, + ARM64_INS_ALIAS_ST4H = AArch64_INS_ALIAS_ST4H, + ARM64_INS_ALIAS_ST2W = AArch64_INS_ALIAS_ST2W, + ARM64_INS_ALIAS_ST3W = AArch64_INS_ALIAS_ST3W, + ARM64_INS_ALIAS_ST4W = AArch64_INS_ALIAS_ST4W, + ARM64_INS_ALIAS_ST2D = AArch64_INS_ALIAS_ST2D, + ARM64_INS_ALIAS_ST3D = AArch64_INS_ALIAS_ST3D, + ARM64_INS_ALIAS_ST4D = AArch64_INS_ALIAS_ST4D, + ARM64_INS_ALIAS_ST3Q = AArch64_INS_ALIAS_ST3Q, + ARM64_INS_ALIAS_ST4Q = AArch64_INS_ALIAS_ST4Q, + ARM64_INS_ALIAS_STNT1H = AArch64_INS_ALIAS_STNT1H, + ARM64_INS_ALIAS_STNT1W = AArch64_INS_ALIAS_STNT1W, + ARM64_INS_ALIAS_STNT1D = AArch64_INS_ALIAS_STNT1D, + ARM64_INS_ALIAS_PRFH = AArch64_INS_ALIAS_PRFH, + ARM64_INS_ALIAS_PRFW = AArch64_INS_ALIAS_PRFW, + ARM64_INS_ALIAS_PRFD = AArch64_INS_ALIAS_PRFD, + ARM64_INS_ALIAS_CNTH = AArch64_INS_ALIAS_CNTH, + ARM64_INS_ALIAS_CNTW = AArch64_INS_ALIAS_CNTW, + ARM64_INS_ALIAS_CNTD = AArch64_INS_ALIAS_CNTD, + ARM64_INS_ALIAS_DECB = AArch64_INS_ALIAS_DECB, + ARM64_INS_ALIAS_INCH = AArch64_INS_ALIAS_INCH, + ARM64_INS_ALIAS_DECH = AArch64_INS_ALIAS_DECH, + ARM64_INS_ALIAS_INCW = AArch64_INS_ALIAS_INCW, + ARM64_INS_ALIAS_DECW = AArch64_INS_ALIAS_DECW, + ARM64_INS_ALIAS_INCD = AArch64_INS_ALIAS_INCD, + ARM64_INS_ALIAS_DECD = AArch64_INS_ALIAS_DECD, + ARM64_INS_ALIAS_SQDECB = AArch64_INS_ALIAS_SQDECB, + ARM64_INS_ALIAS_UQDECB = AArch64_INS_ALIAS_UQDECB, + ARM64_INS_ALIAS_UQINCB = AArch64_INS_ALIAS_UQINCB, + ARM64_INS_ALIAS_SQINCH = AArch64_INS_ALIAS_SQINCH, + ARM64_INS_ALIAS_UQINCH = AArch64_INS_ALIAS_UQINCH, + ARM64_INS_ALIAS_SQDECH = AArch64_INS_ALIAS_SQDECH, + ARM64_INS_ALIAS_UQDECH = AArch64_INS_ALIAS_UQDECH, + ARM64_INS_ALIAS_SQINCW = AArch64_INS_ALIAS_SQINCW, + ARM64_INS_ALIAS_UQINCW = AArch64_INS_ALIAS_UQINCW, + ARM64_INS_ALIAS_SQDECW = AArch64_INS_ALIAS_SQDECW, + ARM64_INS_ALIAS_UQDECW = AArch64_INS_ALIAS_UQDECW, + ARM64_INS_ALIAS_SQINCD = AArch64_INS_ALIAS_SQINCD, + ARM64_INS_ALIAS_UQINCD = AArch64_INS_ALIAS_UQINCD, + ARM64_INS_ALIAS_SQDECD = AArch64_INS_ALIAS_SQDECD, + ARM64_INS_ALIAS_UQDECD = AArch64_INS_ALIAS_UQDECD, + ARM64_INS_ALIAS_MOVS = AArch64_INS_ALIAS_MOVS, + ARM64_INS_ALIAS_NOT = AArch64_INS_ALIAS_NOT, + ARM64_INS_ALIAS_NOTS = AArch64_INS_ALIAS_NOTS, + ARM64_INS_ALIAS_LD1ROH = AArch64_INS_ALIAS_LD1ROH, + ARM64_INS_ALIAS_LD1ROW = AArch64_INS_ALIAS_LD1ROW, + ARM64_INS_ALIAS_LD1ROD = AArch64_INS_ALIAS_LD1ROD, + ARM64_INS_ALIAS_BCAX = AArch64_INS_ALIAS_BCAX, + ARM64_INS_ALIAS_BSL = AArch64_INS_ALIAS_BSL, + ARM64_INS_ALIAS_BSL1N = AArch64_INS_ALIAS_BSL1N, + ARM64_INS_ALIAS_BSL2N = AArch64_INS_ALIAS_BSL2N, + ARM64_INS_ALIAS_NBSL = AArch64_INS_ALIAS_NBSL, + ARM64_INS_ALIAS_LDNT1B = AArch64_INS_ALIAS_LDNT1B, + ARM64_INS_ALIAS_LDNT1SH = AArch64_INS_ALIAS_LDNT1SH, + ARM64_INS_ALIAS_LDNT1SW = AArch64_INS_ALIAS_LDNT1SW, + ARM64_INS_ALIAS_STNT1B = AArch64_INS_ALIAS_STNT1B, + ARM64_INS_ALIAS_LD1Q = AArch64_INS_ALIAS_LD1Q, + ARM64_INS_ALIAS_ST1Q = AArch64_INS_ALIAS_ST1Q, + ARM64_INS_ALIAS_SMSTART = AArch64_INS_ALIAS_SMSTART, + ARM64_INS_ALIAS_SMSTOP = AArch64_INS_ALIAS_SMSTOP, + ARM64_INS_ALIAS_LDRAA = AArch64_INS_ALIAS_LDRAA, + ARM64_INS_ALIAS_ADD = AArch64_INS_ALIAS_ADD, + ARM64_INS_ALIAS_CMN = AArch64_INS_ALIAS_CMN, + ARM64_INS_ALIAS_ADDS = AArch64_INS_ALIAS_ADDS, + ARM64_INS_ALIAS_ANDS = AArch64_INS_ALIAS_ANDS, + ARM64_INS_ALIAS_LDR = AArch64_INS_ALIAS_LDR, + ARM64_INS_ALIAS_STR = AArch64_INS_ALIAS_STR, + ARM64_INS_ALIAS_LDRB = AArch64_INS_ALIAS_LDRB, + ARM64_INS_ALIAS_STRB = AArch64_INS_ALIAS_STRB, + ARM64_INS_ALIAS_LDRH = AArch64_INS_ALIAS_LDRH, + ARM64_INS_ALIAS_STRH = AArch64_INS_ALIAS_STRH, + ARM64_INS_ALIAS_PRFM = AArch64_INS_ALIAS_PRFM, + ARM64_INS_ALIAS_LDAPURB = AArch64_INS_ALIAS_LDAPURB, + ARM64_INS_ALIAS_STLURB = AArch64_INS_ALIAS_STLURB, + ARM64_INS_ALIAS_LDUR = AArch64_INS_ALIAS_LDUR, + ARM64_INS_ALIAS_STUR = AArch64_INS_ALIAS_STUR, + ARM64_INS_ALIAS_PRFUM = AArch64_INS_ALIAS_PRFUM, + ARM64_INS_ALIAS_LDTR = AArch64_INS_ALIAS_LDTR, + ARM64_INS_ALIAS_STTR = AArch64_INS_ALIAS_STTR, + ARM64_INS_ALIAS_LDP = AArch64_INS_ALIAS_LDP, + ARM64_INS_ALIAS_STGP = AArch64_INS_ALIAS_STGP, + ARM64_INS_ALIAS_LDNP = AArch64_INS_ALIAS_LDNP, + ARM64_INS_ALIAS_STNP = AArch64_INS_ALIAS_STNP, + ARM64_INS_ALIAS_STG = AArch64_INS_ALIAS_STG, + ARM64_INS_ALIAS_LD1 = AArch64_INS_ALIAS_LD1, + ARM64_INS_ALIAS_LD1R = AArch64_INS_ALIAS_LD1R, + ARM64_INS_ALIAS_STADDLB = AArch64_INS_ALIAS_STADDLB, + ARM64_INS_ALIAS_STADDLH = AArch64_INS_ALIAS_STADDLH, + ARM64_INS_ALIAS_STADDL = AArch64_INS_ALIAS_STADDL, + ARM64_INS_ALIAS_STADDB = AArch64_INS_ALIAS_STADDB, + ARM64_INS_ALIAS_STADDH = AArch64_INS_ALIAS_STADDH, + ARM64_INS_ALIAS_STADD = AArch64_INS_ALIAS_STADD, + ARM64_INS_ALIAS_PTRUE = AArch64_INS_ALIAS_PTRUE, + ARM64_INS_ALIAS_PTRUES = AArch64_INS_ALIAS_PTRUES, + ARM64_INS_ALIAS_CNTB = AArch64_INS_ALIAS_CNTB, + ARM64_INS_ALIAS_INCB = AArch64_INS_ALIAS_INCB, + ARM64_INS_ALIAS_SQINCB = AArch64_INS_ALIAS_SQINCB, + ARM64_INS_ALIAS_ORR = AArch64_INS_ALIAS_ORR, + ARM64_INS_ALIAS_DUPM = AArch64_INS_ALIAS_DUPM, + ARM64_INS_ALIAS_FMOV = AArch64_INS_ALIAS_FMOV, + ARM64_INS_ALIAS_EOR3 = AArch64_INS_ALIAS_EOR3, + ARM64_INS_ALIAS_ST2B = AArch64_INS_ALIAS_ST2B, + ARM64_INS_ALIAS_ST2Q = AArch64_INS_ALIAS_ST2Q, + ARM64_INS_ALIAS_LD1RQB = AArch64_INS_ALIAS_LD1RQB, + ARM64_INS_ALIAS_LD2B = AArch64_INS_ALIAS_LD2B, + ARM64_INS_ALIAS_PRFB = AArch64_INS_ALIAS_PRFB, + ARM64_INS_ALIAS_LDNT1SB = AArch64_INS_ALIAS_LDNT1SB, + ARM64_INS_ALIAS_LD1ROB = AArch64_INS_ALIAS_LD1ROB, + ARM64_INS_ALIAS_PMOV = AArch64_INS_ALIAS_PMOV, + ARM64_INS_ALIAS_ZERO = AArch64_INS_ALIAS_ZERO, + ARM64_INS_ALIAS_NOP = AArch64_INS_ALIAS_NOP, + ARM64_INS_ALIAS_YIELD = AArch64_INS_ALIAS_YIELD, + ARM64_INS_ALIAS_WFE = AArch64_INS_ALIAS_WFE, + ARM64_INS_ALIAS_WFI = AArch64_INS_ALIAS_WFI, + ARM64_INS_ALIAS_SEV = AArch64_INS_ALIAS_SEV, + ARM64_INS_ALIAS_SEVL = AArch64_INS_ALIAS_SEVL, + ARM64_INS_ALIAS_DGH = AArch64_INS_ALIAS_DGH, + ARM64_INS_ALIAS_ESB = AArch64_INS_ALIAS_ESB, + ARM64_INS_ALIAS_CSDB = AArch64_INS_ALIAS_CSDB, + ARM64_INS_ALIAS_BTI = AArch64_INS_ALIAS_BTI, + ARM64_INS_ALIAS_PSB = AArch64_INS_ALIAS_PSB, + ARM64_INS_ALIAS_PACIAZ = AArch64_INS_ALIAS_PACIAZ, + ARM64_INS_ALIAS_PACIBZ = AArch64_INS_ALIAS_PACIBZ, + ARM64_INS_ALIAS_AUTIAZ = AArch64_INS_ALIAS_AUTIAZ, + ARM64_INS_ALIAS_AUTIBZ = AArch64_INS_ALIAS_AUTIBZ, + ARM64_INS_ALIAS_PACIASP = AArch64_INS_ALIAS_PACIASP, + ARM64_INS_ALIAS_PACIBSP = AArch64_INS_ALIAS_PACIBSP, + ARM64_INS_ALIAS_AUTIASP = AArch64_INS_ALIAS_AUTIASP, + ARM64_INS_ALIAS_AUTIBSP = AArch64_INS_ALIAS_AUTIBSP, + ARM64_INS_ALIAS_PACIA1716 = AArch64_INS_ALIAS_PACIA1716, + ARM64_INS_ALIAS_PACIB1716 = AArch64_INS_ALIAS_PACIB1716, + ARM64_INS_ALIAS_AUTIA1716 = AArch64_INS_ALIAS_AUTIA1716, + ARM64_INS_ALIAS_AUTIB1716 = AArch64_INS_ALIAS_AUTIB1716, + ARM64_INS_ALIAS_XPACLRI = AArch64_INS_ALIAS_XPACLRI, + ARM64_INS_ALIAS_LDRAB = AArch64_INS_ALIAS_LDRAB, + ARM64_INS_ALIAS_CLREX = AArch64_INS_ALIAS_CLREX, + ARM64_INS_ALIAS_ISB = AArch64_INS_ALIAS_ISB, + ARM64_INS_ALIAS_SSBB = AArch64_INS_ALIAS_SSBB, + ARM64_INS_ALIAS_PSSBB = AArch64_INS_ALIAS_PSSBB, + ARM64_INS_ALIAS_DFB = AArch64_INS_ALIAS_DFB, + ARM64_INS_ALIAS_SYS = AArch64_INS_ALIAS_SYS, + ARM64_INS_ALIAS_MOVN = AArch64_INS_ALIAS_MOVN, + ARM64_INS_ALIAS_MOVZ = AArch64_INS_ALIAS_MOVZ, + ARM64_INS_ALIAS_NGC = AArch64_INS_ALIAS_NGC, + ARM64_INS_ALIAS_NGCS = AArch64_INS_ALIAS_NGCS, + ARM64_INS_ALIAS_SUB = AArch64_INS_ALIAS_SUB, + ARM64_INS_ALIAS_CMP = AArch64_INS_ALIAS_CMP, + ARM64_INS_ALIAS_SUBS = AArch64_INS_ALIAS_SUBS, + ARM64_INS_ALIAS_NEG = AArch64_INS_ALIAS_NEG, + ARM64_INS_ALIAS_NEGS = AArch64_INS_ALIAS_NEGS, + ARM64_INS_ALIAS_MUL = AArch64_INS_ALIAS_MUL, + ARM64_INS_ALIAS_MNEG = AArch64_INS_ALIAS_MNEG, + ARM64_INS_ALIAS_SMULL = AArch64_INS_ALIAS_SMULL, + ARM64_INS_ALIAS_SMNEGL = AArch64_INS_ALIAS_SMNEGL, + ARM64_INS_ALIAS_UMULL = AArch64_INS_ALIAS_UMULL, + ARM64_INS_ALIAS_UMNEGL = AArch64_INS_ALIAS_UMNEGL, + ARM64_INS_ALIAS_STCLRLB = AArch64_INS_ALIAS_STCLRLB, + ARM64_INS_ALIAS_STCLRLH = AArch64_INS_ALIAS_STCLRLH, + ARM64_INS_ALIAS_STCLRL = AArch64_INS_ALIAS_STCLRL, + ARM64_INS_ALIAS_STCLRB = AArch64_INS_ALIAS_STCLRB, + ARM64_INS_ALIAS_STCLRH = AArch64_INS_ALIAS_STCLRH, + ARM64_INS_ALIAS_STCLR = AArch64_INS_ALIAS_STCLR, + ARM64_INS_ALIAS_STEORLB = AArch64_INS_ALIAS_STEORLB, + ARM64_INS_ALIAS_STEORLH = AArch64_INS_ALIAS_STEORLH, + ARM64_INS_ALIAS_STEORL = AArch64_INS_ALIAS_STEORL, + ARM64_INS_ALIAS_STEORB = AArch64_INS_ALIAS_STEORB, + ARM64_INS_ALIAS_STEORH = AArch64_INS_ALIAS_STEORH, + ARM64_INS_ALIAS_STEOR = AArch64_INS_ALIAS_STEOR, + ARM64_INS_ALIAS_STSETLB = AArch64_INS_ALIAS_STSETLB, + ARM64_INS_ALIAS_STSETLH = AArch64_INS_ALIAS_STSETLH, + ARM64_INS_ALIAS_STSETL = AArch64_INS_ALIAS_STSETL, + ARM64_INS_ALIAS_STSETB = AArch64_INS_ALIAS_STSETB, + ARM64_INS_ALIAS_STSETH = AArch64_INS_ALIAS_STSETH, + ARM64_INS_ALIAS_STSET = AArch64_INS_ALIAS_STSET, + ARM64_INS_ALIAS_STSMAXLB = AArch64_INS_ALIAS_STSMAXLB, + ARM64_INS_ALIAS_STSMAXLH = AArch64_INS_ALIAS_STSMAXLH, + ARM64_INS_ALIAS_STSMAXL = AArch64_INS_ALIAS_STSMAXL, + ARM64_INS_ALIAS_STSMAXB = AArch64_INS_ALIAS_STSMAXB, + ARM64_INS_ALIAS_STSMAXH = AArch64_INS_ALIAS_STSMAXH, + ARM64_INS_ALIAS_STSMAX = AArch64_INS_ALIAS_STSMAX, + ARM64_INS_ALIAS_STSMINLB = AArch64_INS_ALIAS_STSMINLB, + ARM64_INS_ALIAS_STSMINLH = AArch64_INS_ALIAS_STSMINLH, + ARM64_INS_ALIAS_STSMINL = AArch64_INS_ALIAS_STSMINL, + ARM64_INS_ALIAS_STSMINB = AArch64_INS_ALIAS_STSMINB, + ARM64_INS_ALIAS_STSMINH = AArch64_INS_ALIAS_STSMINH, + ARM64_INS_ALIAS_STSMIN = AArch64_INS_ALIAS_STSMIN, + ARM64_INS_ALIAS_STUMAXLB = AArch64_INS_ALIAS_STUMAXLB, + ARM64_INS_ALIAS_STUMAXLH = AArch64_INS_ALIAS_STUMAXLH, + ARM64_INS_ALIAS_STUMAXL = AArch64_INS_ALIAS_STUMAXL, + ARM64_INS_ALIAS_STUMAXB = AArch64_INS_ALIAS_STUMAXB, + ARM64_INS_ALIAS_STUMAXH = AArch64_INS_ALIAS_STUMAXH, + ARM64_INS_ALIAS_STUMAX = AArch64_INS_ALIAS_STUMAX, + ARM64_INS_ALIAS_STUMINLB = AArch64_INS_ALIAS_STUMINLB, + ARM64_INS_ALIAS_STUMINLH = AArch64_INS_ALIAS_STUMINLH, + ARM64_INS_ALIAS_STUMINL = AArch64_INS_ALIAS_STUMINL, + ARM64_INS_ALIAS_STUMINB = AArch64_INS_ALIAS_STUMINB, + ARM64_INS_ALIAS_STUMINH = AArch64_INS_ALIAS_STUMINH, + ARM64_INS_ALIAS_STUMIN = AArch64_INS_ALIAS_STUMIN, + ARM64_INS_ALIAS_IRG = AArch64_INS_ALIAS_IRG, + ARM64_INS_ALIAS_LDG = AArch64_INS_ALIAS_LDG, + ARM64_INS_ALIAS_STZG = AArch64_INS_ALIAS_STZG, + ARM64_INS_ALIAS_ST2G = AArch64_INS_ALIAS_ST2G, + ARM64_INS_ALIAS_STZ2G = AArch64_INS_ALIAS_STZ2G, + ARM64_INS_ALIAS_BICS = AArch64_INS_ALIAS_BICS, + ARM64_INS_ALIAS_BIC = AArch64_INS_ALIAS_BIC, + ARM64_INS_ALIAS_EON = AArch64_INS_ALIAS_EON, + ARM64_INS_ALIAS_ORN = AArch64_INS_ALIAS_ORN, + ARM64_INS_ALIAS_MVN = AArch64_INS_ALIAS_MVN, + ARM64_INS_ALIAS_TST = AArch64_INS_ALIAS_TST, + ARM64_INS_ALIAS_ROR = AArch64_INS_ALIAS_ROR, + ARM64_INS_ALIAS_ASR = AArch64_INS_ALIAS_ASR, + ARM64_INS_ALIAS_SXTB = AArch64_INS_ALIAS_SXTB, + ARM64_INS_ALIAS_SXTH = AArch64_INS_ALIAS_SXTH, + ARM64_INS_ALIAS_SXTW = AArch64_INS_ALIAS_SXTW, + ARM64_INS_ALIAS_LSR = AArch64_INS_ALIAS_LSR, + ARM64_INS_ALIAS_UXTB = AArch64_INS_ALIAS_UXTB, + ARM64_INS_ALIAS_UXTH = AArch64_INS_ALIAS_UXTH, + ARM64_INS_ALIAS_UXTW = AArch64_INS_ALIAS_UXTW, + ARM64_INS_ALIAS_CSET = AArch64_INS_ALIAS_CSET, + ARM64_INS_ALIAS_CSETM = AArch64_INS_ALIAS_CSETM, + ARM64_INS_ALIAS_CINC = AArch64_INS_ALIAS_CINC, + ARM64_INS_ALIAS_CINV = AArch64_INS_ALIAS_CINV, + ARM64_INS_ALIAS_CNEG = AArch64_INS_ALIAS_CNEG, + ARM64_INS_ALIAS_RET = AArch64_INS_ALIAS_RET, + ARM64_INS_ALIAS_DCPS1 = AArch64_INS_ALIAS_DCPS1, + ARM64_INS_ALIAS_DCPS2 = AArch64_INS_ALIAS_DCPS2, + ARM64_INS_ALIAS_DCPS3 = AArch64_INS_ALIAS_DCPS3, + ARM64_INS_ALIAS_LDPSW = AArch64_INS_ALIAS_LDPSW, + ARM64_INS_ALIAS_LDRSH = AArch64_INS_ALIAS_LDRSH, + ARM64_INS_ALIAS_LDRSB = AArch64_INS_ALIAS_LDRSB, + ARM64_INS_ALIAS_LDRSW = AArch64_INS_ALIAS_LDRSW, + ARM64_INS_ALIAS_LDURH = AArch64_INS_ALIAS_LDURH, + ARM64_INS_ALIAS_LDURB = AArch64_INS_ALIAS_LDURB, + ARM64_INS_ALIAS_LDURSH = AArch64_INS_ALIAS_LDURSH, + ARM64_INS_ALIAS_LDURSB = AArch64_INS_ALIAS_LDURSB, + ARM64_INS_ALIAS_LDURSW = AArch64_INS_ALIAS_LDURSW, + ARM64_INS_ALIAS_LDTRH = AArch64_INS_ALIAS_LDTRH, + ARM64_INS_ALIAS_LDTRB = AArch64_INS_ALIAS_LDTRB, + ARM64_INS_ALIAS_LDTRSH = AArch64_INS_ALIAS_LDTRSH, + ARM64_INS_ALIAS_LDTRSB = AArch64_INS_ALIAS_LDTRSB, + ARM64_INS_ALIAS_LDTRSW = AArch64_INS_ALIAS_LDTRSW, + ARM64_INS_ALIAS_STP = AArch64_INS_ALIAS_STP, + ARM64_INS_ALIAS_STURH = AArch64_INS_ALIAS_STURH, + ARM64_INS_ALIAS_STURB = AArch64_INS_ALIAS_STURB, + ARM64_INS_ALIAS_STLURH = AArch64_INS_ALIAS_STLURH, + ARM64_INS_ALIAS_LDAPURSB = AArch64_INS_ALIAS_LDAPURSB, + ARM64_INS_ALIAS_LDAPURH = AArch64_INS_ALIAS_LDAPURH, + ARM64_INS_ALIAS_LDAPURSH = AArch64_INS_ALIAS_LDAPURSH, + ARM64_INS_ALIAS_LDAPURSW = AArch64_INS_ALIAS_LDAPURSW, + ARM64_INS_ALIAS_STTRH = AArch64_INS_ALIAS_STTRH, + ARM64_INS_ALIAS_STTRB = AArch64_INS_ALIAS_STTRB, + ARM64_INS_ALIAS_BIC_4H = AArch64_INS_ALIAS_BIC_4H, + ARM64_INS_ALIAS_BIC_8H = AArch64_INS_ALIAS_BIC_8H, + ARM64_INS_ALIAS_BIC_2S = AArch64_INS_ALIAS_BIC_2S, + ARM64_INS_ALIAS_BIC_4S = AArch64_INS_ALIAS_BIC_4S, + ARM64_INS_ALIAS_ORR_4H = AArch64_INS_ALIAS_ORR_4H, + ARM64_INS_ALIAS_ORR_8H = AArch64_INS_ALIAS_ORR_8H, + ARM64_INS_ALIAS_ORR_2S = AArch64_INS_ALIAS_ORR_2S, + ARM64_INS_ALIAS_ORR_4S = AArch64_INS_ALIAS_ORR_4S, + ARM64_INS_ALIAS_SXTL_8H = AArch64_INS_ALIAS_SXTL_8H, + ARM64_INS_ALIAS_SXTL = AArch64_INS_ALIAS_SXTL, + ARM64_INS_ALIAS_SXTL_4S = AArch64_INS_ALIAS_SXTL_4S, + ARM64_INS_ALIAS_SXTL_2D = AArch64_INS_ALIAS_SXTL_2D, + ARM64_INS_ALIAS_SXTL2_8H = AArch64_INS_ALIAS_SXTL2_8H, + ARM64_INS_ALIAS_SXTL2 = AArch64_INS_ALIAS_SXTL2, + ARM64_INS_ALIAS_SXTL2_4S = AArch64_INS_ALIAS_SXTL2_4S, + ARM64_INS_ALIAS_SXTL2_2D = AArch64_INS_ALIAS_SXTL2_2D, + ARM64_INS_ALIAS_UXTL_8H = AArch64_INS_ALIAS_UXTL_8H, + ARM64_INS_ALIAS_UXTL = AArch64_INS_ALIAS_UXTL, + ARM64_INS_ALIAS_UXTL_4S = AArch64_INS_ALIAS_UXTL_4S, + ARM64_INS_ALIAS_UXTL_2D = AArch64_INS_ALIAS_UXTL_2D, + ARM64_INS_ALIAS_UXTL2_8H = AArch64_INS_ALIAS_UXTL2_8H, + ARM64_INS_ALIAS_UXTL2 = AArch64_INS_ALIAS_UXTL2, + ARM64_INS_ALIAS_UXTL2_4S = AArch64_INS_ALIAS_UXTL2_4S, + ARM64_INS_ALIAS_UXTL2_2D = AArch64_INS_ALIAS_UXTL2_2D, + ARM64_INS_ALIAS_LD2 = AArch64_INS_ALIAS_LD2, + ARM64_INS_ALIAS_LD3 = AArch64_INS_ALIAS_LD3, + ARM64_INS_ALIAS_LD4 = AArch64_INS_ALIAS_LD4, + ARM64_INS_ALIAS_ST1 = AArch64_INS_ALIAS_ST1, + ARM64_INS_ALIAS_ST2 = AArch64_INS_ALIAS_ST2, + ARM64_INS_ALIAS_ST3 = AArch64_INS_ALIAS_ST3, + ARM64_INS_ALIAS_ST4 = AArch64_INS_ALIAS_ST4, + ARM64_INS_ALIAS_LD2R = AArch64_INS_ALIAS_LD2R, + ARM64_INS_ALIAS_LD3R = AArch64_INS_ALIAS_LD3R, + ARM64_INS_ALIAS_LD4R = AArch64_INS_ALIAS_LD4R, + ARM64_INS_ALIAS_CLRBHB = AArch64_INS_ALIAS_CLRBHB, + ARM64_INS_ALIAS_STILP = AArch64_INS_ALIAS_STILP, + ARM64_INS_ALIAS_STL1 = AArch64_INS_ALIAS_STL1, + ARM64_INS_ALIAS_SYSP = AArch64_INS_ALIAS_SYSP, + + + ARM64_INS_ALIAS_CFP = AArch64_INS_ALIAS_CFP, + ARM64_INS_ALIAS_DVP = AArch64_INS_ALIAS_DVP, + ARM64_INS_ALIAS_COSP = AArch64_INS_ALIAS_COSP, + ARM64_INS_ALIAS_CPP = AArch64_INS_ALIAS_CPP, + ARM64_INS_ALIAS_IC = AArch64_INS_ALIAS_IC, + ARM64_INS_ALIAS_DC = AArch64_INS_ALIAS_DC, + ARM64_INS_ALIAS_AT = AArch64_INS_ALIAS_AT, + ARM64_INS_ALIAS_TLBI = AArch64_INS_ALIAS_TLBI, + ARM64_INS_ALIAS_TLBIP = AArch64_INS_ALIAS_TLBIP, + ARM64_INS_ALIAS_RPRFM = AArch64_INS_ALIAS_RPRFM, + ARM64_INS_ALIAS_LSL = AArch64_INS_ALIAS_LSL, + ARM64_INS_ALIAS_SBFX = AArch64_INS_ALIAS_SBFX, + ARM64_INS_ALIAS_UBFX = AArch64_INS_ALIAS_UBFX, + ARM64_INS_ALIAS_SBFIZ = AArch64_INS_ALIAS_SBFIZ, + ARM64_INS_ALIAS_UBFIZ = AArch64_INS_ALIAS_UBFIZ, + ARM64_INS_ALIAS_BFC = AArch64_INS_ALIAS_BFC, + ARM64_INS_ALIAS_BFI = AArch64_INS_ALIAS_BFI, + ARM64_INS_ALIAS_BFXIL = AArch64_INS_ALIAS_BFXIL, + + ARM64_INS_ALIAS_END = AArch64_INS_ALIAS_END, +} arm64_insn; + +typedef enum { + ARM64_GRP_INVALID = AArch64_GRP_INVALID, + + ARM64_GRP_JUMP = AArch64_GRP_JUMP, + ARM64_GRP_CALL = AArch64_GRP_CALL, + ARM64_GRP_RET = AArch64_GRP_RET, + ARM64_GRP_INT = AArch64_GRP_INT, + ARM64_GRP_PRIVILEGE = AArch64_GRP_PRIVILEGE, + ARM64_GRP_BRANCH_RELATIVE = AArch64_GRP_BRANCH_RELATIVE, + + ARM64_FEATURE_HasV8_0a = AArch64_FEATURE_HasV8_0a, + ARM64_FEATURE_HasV8_1a = AArch64_FEATURE_HasV8_1a, + ARM64_FEATURE_HasV8_2a = AArch64_FEATURE_HasV8_2a, + ARM64_FEATURE_HasV8_3a = AArch64_FEATURE_HasV8_3a, + ARM64_FEATURE_HasV8_4a = AArch64_FEATURE_HasV8_4a, + ARM64_FEATURE_HasV8_5a = AArch64_FEATURE_HasV8_5a, + ARM64_FEATURE_HasV8_6a = AArch64_FEATURE_HasV8_6a, + ARM64_FEATURE_HasV8_7a = AArch64_FEATURE_HasV8_7a, + ARM64_FEATURE_HasV8_8a = AArch64_FEATURE_HasV8_8a, + ARM64_FEATURE_HasV8_9a = AArch64_FEATURE_HasV8_9a, + ARM64_FEATURE_HasV9_0a = AArch64_FEATURE_HasV9_0a, + ARM64_FEATURE_HasV9_1a = AArch64_FEATURE_HasV9_1a, + ARM64_FEATURE_HasV9_2a = AArch64_FEATURE_HasV9_2a, + ARM64_FEATURE_HasV9_3a = AArch64_FEATURE_HasV9_3a, + ARM64_FEATURE_HasV9_4a = AArch64_FEATURE_HasV9_4a, + ARM64_FEATURE_HasV8_0r = AArch64_FEATURE_HasV8_0r, + ARM64_FEATURE_HasEL2VMSA = AArch64_FEATURE_HasEL2VMSA, + ARM64_FEATURE_HasEL3 = AArch64_FEATURE_HasEL3, + ARM64_FEATURE_HasVH = AArch64_FEATURE_HasVH, + ARM64_FEATURE_HasLOR = AArch64_FEATURE_HasLOR, + ARM64_FEATURE_HasPAuth = AArch64_FEATURE_HasPAuth, + ARM64_FEATURE_HasJS = AArch64_FEATURE_HasJS, + ARM64_FEATURE_HasCCIDX = AArch64_FEATURE_HasCCIDX, + ARM64_FEATURE_HasComplxNum = AArch64_FEATURE_HasComplxNum, + ARM64_FEATURE_HasNV = AArch64_FEATURE_HasNV, + ARM64_FEATURE_HasMPAM = AArch64_FEATURE_HasMPAM, + ARM64_FEATURE_HasDIT = AArch64_FEATURE_HasDIT, + ARM64_FEATURE_HasTRACEV8_4 = AArch64_FEATURE_HasTRACEV8_4, + ARM64_FEATURE_HasAM = AArch64_FEATURE_HasAM, + ARM64_FEATURE_HasSEL2 = AArch64_FEATURE_HasSEL2, + ARM64_FEATURE_HasTLB_RMI = AArch64_FEATURE_HasTLB_RMI, + ARM64_FEATURE_HasFlagM = AArch64_FEATURE_HasFlagM, + ARM64_FEATURE_HasRCPC_IMMO = AArch64_FEATURE_HasRCPC_IMMO, + ARM64_FEATURE_HasFPARMv8 = AArch64_FEATURE_HasFPARMv8, + ARM64_FEATURE_HasNEON = AArch64_FEATURE_HasNEON, + ARM64_FEATURE_HasCrypto = AArch64_FEATURE_HasCrypto, + ARM64_FEATURE_HasSM4 = AArch64_FEATURE_HasSM4, + ARM64_FEATURE_HasSHA3 = AArch64_FEATURE_HasSHA3, + ARM64_FEATURE_HasSHA2 = AArch64_FEATURE_HasSHA2, + ARM64_FEATURE_HasAES = AArch64_FEATURE_HasAES, + ARM64_FEATURE_HasDotProd = AArch64_FEATURE_HasDotProd, + ARM64_FEATURE_HasCRC = AArch64_FEATURE_HasCRC, + ARM64_FEATURE_HasCSSC = AArch64_FEATURE_HasCSSC, + ARM64_FEATURE_HasLSE = AArch64_FEATURE_HasLSE, + ARM64_FEATURE_HasRAS = AArch64_FEATURE_HasRAS, + ARM64_FEATURE_HasRDM = AArch64_FEATURE_HasRDM, + ARM64_FEATURE_HasFullFP16 = AArch64_FEATURE_HasFullFP16, + ARM64_FEATURE_HasFP16FML = AArch64_FEATURE_HasFP16FML, + ARM64_FEATURE_HasSPE = AArch64_FEATURE_HasSPE, + ARM64_FEATURE_HasFuseAES = AArch64_FEATURE_HasFuseAES, + ARM64_FEATURE_HasSVE = AArch64_FEATURE_HasSVE, + ARM64_FEATURE_HasSVE2 = AArch64_FEATURE_HasSVE2, + ARM64_FEATURE_HasSVE2p1 = AArch64_FEATURE_HasSVE2p1, + ARM64_FEATURE_HasSVE2AES = AArch64_FEATURE_HasSVE2AES, + ARM64_FEATURE_HasSVE2SM4 = AArch64_FEATURE_HasSVE2SM4, + ARM64_FEATURE_HasSVE2SHA3 = AArch64_FEATURE_HasSVE2SHA3, + ARM64_FEATURE_HasSVE2BitPerm = AArch64_FEATURE_HasSVE2BitPerm, + ARM64_FEATURE_HasB16B16 = AArch64_FEATURE_HasB16B16, + ARM64_FEATURE_HasSME = AArch64_FEATURE_HasSME, + ARM64_FEATURE_HasSMEF64F64 = AArch64_FEATURE_HasSMEF64F64, + ARM64_FEATURE_HasSMEF16F16 = AArch64_FEATURE_HasSMEF16F16, + ARM64_FEATURE_HasSMEI16I64 = AArch64_FEATURE_HasSMEI16I64, + ARM64_FEATURE_HasSME2 = AArch64_FEATURE_HasSME2, + ARM64_FEATURE_HasSME2p1 = AArch64_FEATURE_HasSME2p1, + ARM64_FEATURE_HasSVEorSME = AArch64_FEATURE_HasSVEorSME, + ARM64_FEATURE_HasSVE2orSME = AArch64_FEATURE_HasSVE2orSME, + ARM64_FEATURE_HasSVE2p1_or_HasSME = AArch64_FEATURE_HasSVE2p1_or_HasSME, + ARM64_FEATURE_HasSVE2p1_or_HasSME2 = AArch64_FEATURE_HasSVE2p1_or_HasSME2, + ARM64_FEATURE_HasSVE2p1_or_HasSME2p1 = AArch64_FEATURE_HasSVE2p1_or_HasSME2p1, + ARM64_FEATURE_HasNEONorSME = AArch64_FEATURE_HasNEONorSME, + ARM64_FEATURE_HasRCPC = AArch64_FEATURE_HasRCPC, + ARM64_FEATURE_HasAltNZCV = AArch64_FEATURE_HasAltNZCV, + ARM64_FEATURE_HasFRInt3264 = AArch64_FEATURE_HasFRInt3264, + ARM64_FEATURE_HasSB = AArch64_FEATURE_HasSB, + ARM64_FEATURE_HasPredRes = AArch64_FEATURE_HasPredRes, + ARM64_FEATURE_HasCCDP = AArch64_FEATURE_HasCCDP, + ARM64_FEATURE_HasBTI = AArch64_FEATURE_HasBTI, + ARM64_FEATURE_HasMTE = AArch64_FEATURE_HasMTE, + ARM64_FEATURE_HasTME = AArch64_FEATURE_HasTME, + ARM64_FEATURE_HasETE = AArch64_FEATURE_HasETE, + ARM64_FEATURE_HasTRBE = AArch64_FEATURE_HasTRBE, + ARM64_FEATURE_HasBF16 = AArch64_FEATURE_HasBF16, + ARM64_FEATURE_HasMatMulInt8 = AArch64_FEATURE_HasMatMulInt8, + ARM64_FEATURE_HasMatMulFP32 = AArch64_FEATURE_HasMatMulFP32, + ARM64_FEATURE_HasMatMulFP64 = AArch64_FEATURE_HasMatMulFP64, + ARM64_FEATURE_HasXS = AArch64_FEATURE_HasXS, + ARM64_FEATURE_HasWFxT = AArch64_FEATURE_HasWFxT, + ARM64_FEATURE_HasLS64 = AArch64_FEATURE_HasLS64, + ARM64_FEATURE_HasBRBE = AArch64_FEATURE_HasBRBE, + ARM64_FEATURE_HasSPE_EEF = AArch64_FEATURE_HasSPE_EEF, + ARM64_FEATURE_HasHBC = AArch64_FEATURE_HasHBC, + ARM64_FEATURE_HasMOPS = AArch64_FEATURE_HasMOPS, + ARM64_FEATURE_HasCLRBHB = AArch64_FEATURE_HasCLRBHB, + ARM64_FEATURE_HasSPECRES2 = AArch64_FEATURE_HasSPECRES2, + ARM64_FEATURE_HasITE = AArch64_FEATURE_HasITE, + ARM64_FEATURE_HasTHE = AArch64_FEATURE_HasTHE, + ARM64_FEATURE_HasRCPC3 = AArch64_FEATURE_HasRCPC3, + ARM64_FEATURE_HasLSE128 = AArch64_FEATURE_HasLSE128, + ARM64_FEATURE_HasD128 = AArch64_FEATURE_HasD128, + ARM64_FEATURE_UseNegativeImmediates = AArch64_FEATURE_UseNegativeImmediates, + ARM64_FEATURE_HasCCPP = AArch64_FEATURE_HasCCPP, + ARM64_FEATURE_HasPAN = AArch64_FEATURE_HasPAN, + ARM64_FEATURE_HasPsUAO = AArch64_FEATURE_HasPsUAO, + ARM64_FEATURE_HasPAN_RWV = AArch64_FEATURE_HasPAN_RWV, + ARM64_FEATURE_HasCONTEXTIDREL2 = AArch64_FEATURE_HasCONTEXTIDREL2, + + + ARM64_GRP_ENDING = AArch64_GRP_ENDING, +} arm64_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 4fed66ef0..55610fbce 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -61,6 +61,7 @@ extern "C" { #define CS_VERSION_MINOR CS_API_MINOR #define CS_VERSION_EXTRA 0 +#ifndef CAPSTONE_AARCH64_COMPAT_HEADER /// Macro for meta programming. /// Meant for projects using Capstone and need to support multiple /// versions of it. @@ -119,6 +120,7 @@ extern "C" { #define CS_aarch64_shifter() aarch64_shifter #define CS_aarch64_vas() AArch64Layout_VectorLayout #endif +#endif // CAPSTONE_AARCH64_COMPAT_HEADER /// Macro to create combined version which can be compared to /// result of cs_version() API. @@ -133,7 +135,11 @@ typedef size_t csh; /// Architecture type typedef enum cs_arch { CS_ARCH_ARM = 0, ///< ARM architecture (including Thumb, Thumb-2) - CS_ARCH_AARCH64, ///< AArch64 +#ifdef CAPSTONE_AARCH64_COMPAT_HEADER + CS_ARCH_ARM64 = 1, ///< ARM64 +#else + CS_ARCH_AARCH64 = 1, ///< AArch64 +#endif CS_ARCH_MIPS, ///< Mips architecture CS_ARCH_X86, ///< X86 architecture (including x86 & x86-64) CS_ARCH_PPC, ///< PowerPC architecture @@ -358,7 +364,11 @@ typedef struct cs_opt_skipdata { #include "arm.h" +#ifdef CAPSTONE_AARCH64_COMPAT_HEADER +#include "arm64.h" +#else #include "aarch64.h" +#endif #include "m68k.h" #include "mips.h" #include "ppc.h" @@ -404,7 +414,11 @@ typedef struct cs_detail { /// Architecture-specific instruction info union { cs_x86 x86; ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode - cs_aarch64 aarch64; ///< AARCH64 architecture (aka AArch64) +#ifdef CAPSTONE_AARCH64_COMPAT_HEADER + cs_arm64 arm64; +#else + cs_aarch64 aarch64; ///< AArch6464 architecture (aka ARM64) +#endif cs_arm arm; ///< ARM architecture (including Thumb/Thumb2) cs_m68k m68k; ///< M68K architecture cs_mips mips; ///< MIPS architecture @@ -532,6 +546,9 @@ CAPSTONE_EXPORT void CAPSTONE_API cs_arch_register_arm(void); CAPSTONE_EXPORT void CAPSTONE_API cs_arch_register_aarch64(void); +#ifdef CAPSTONE_AARCH64_COMPAT_HEADER +#define cs_arch_register_aarch64 cs_arch_register_arm64 +#endif CAPSTONE_EXPORT void CAPSTONE_API cs_arch_register_mips(void); CAPSTONE_EXPORT diff --git a/suite/auto-sync/c_tests/README.md b/suite/auto-sync/c_tests/README.md new file mode 100644 index 000000000..8c8d8e14c --- /dev/null +++ b/suite/auto-sync/c_tests/README.md @@ -0,0 +1,6 @@ + + +Compilation tests for the generated source code. diff --git a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c b/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c new file mode 100644 index 000000000..4af052056 --- /dev/null +++ b/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c @@ -0,0 +1,40 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3.0-Clause + +#include +#include + +#define CAPSTONE_AARCH64_COMPAT_HEADER +#include + +int main(void) +{ + csh handle; + + if (cs_open(CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN, &handle) != CS_ERR_OK) { + printf("cs_open failed\n"); + return -1; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + cs_insn *insn; + uint8_t bytes[] = "0x1a,0x48,0xa0,0xf8"; + size_t count = cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn); + if (count > 0) { + printf("0x%" PRIx64 ":\t%s\t\t%s\n", insn[0].address, + insn[0].mnemonic, insn[0].op_str); + printf("A register = %s\n", cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg)); + printf("An imm = 0x%" PRIx64 "\n", insn[0].detail->arm64.operands[1].imm); + + cs_free(insn, count); + } else { + printf("ERROR: Failed to disassemble given code!\n"); + cs_close(&handle); + return -1; + } + + cs_close(&handle); + + return 0; +} diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py index 3a15c9d66..0826ef557 100755 --- a/suite/auto-sync/src/autosync/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -15,7 +15,7 @@ from pathlib import Path from autosync.cpptranslator.Configurator import Configurator from autosync.cpptranslator.CppTranslator import Translator -from autosync.HeaderPatcher import HeaderPatcher +from autosync.HeaderPatcher import CompatHeaderBuilder, HeaderPatcher from autosync.Helper import check_py_version, convert_loglevel, fail_exit, get_path from autosync.IncGenerator import IncGenerator @@ -88,6 +88,13 @@ class ASUpdater: if patcher.patch_header(): # Save the path. This file should not be moved. patched.append(file) + if self.arch == "AArch64": + # Update the compatibility header + builder = CompatHeaderBuilder( + aarch64_h=main_header, + arm64_h=get_path("{CS_INCLUDE_DIR}").joinpath(f"arm64.h"), + ) + builder.generate_aarch64_compat_header() return patched def copy_files(self, path: Path, dest: Path) -> None: diff --git a/suite/auto-sync/src/autosync/HeaderPatcher.py b/suite/auto-sync/src/autosync/HeaderPatcher.py index 502e38971..8b271eff6 100755 --- a/suite/auto-sync/src/autosync/HeaderPatcher.py +++ b/suite/auto-sync/src/autosync/HeaderPatcher.py @@ -15,11 +15,19 @@ def parse_args() -> argparse.Namespace: prog="PatchHeaders", description="Patches generated enums into the main arch header file.", ) + parser.add_argument("--header", dest="header", help="Path header file.", type=Path) + parser.add_argument("--inc", dest="inc", help="Path inc file.", type=Path) parser.add_argument( - "--header", dest="header", help="Path header file.", type=Path, required=True + "--aarch64", dest="aarch64", help="aarch64.h header file location", type=Path ) parser.add_argument( - "--inc", dest="inc", help="Path inc file.", type=Path, required=True + "--arm64", dest="arm64", help="arm64.h header file location", type=Path + ) + parser.add_argument( + "-c", dest="compat", help="Generate compatibility header", action="store_true" + ) + parser.add_argument( + "-p", dest="patch", help="Patch inc file into header", action="store_true" ) arguments = parser.parse_args() return arguments @@ -104,7 +112,147 @@ class HeaderPatcher: return True +class CompatHeaderBuilder: + + def __init__(self, aarch64_h: Path, arm64_h: Path): + self.aarch64_h = aarch64_h + self.arm64_h = arm64_h + + def replace_typedef_struct(self, aarch64_lines: list[str]) -> list[str]: + output = list() + typedef = "" + for line in aarch64_lines: + if typedef: + if not re.search(r"^}\s[\w_]+;", line): + # Skip struct content + continue + type_name = re.findall(r"[\w_]+", line)[0] + output.append( + f"typedef {type_name} {re.sub('aarch64','arm64', type_name)};\n" + ) + typedef = "" + continue + + if re.search(f"^typedef\s+(struct|union)", line): + typedef = line + continue + output.append(line) + return output + + def replace_typedef_enum(self, aarch64_lines: list[str]) -> list[str]: + output = list() + typedef = "" + for line in aarch64_lines: + if typedef: + if not re.search(r"^}\s[\w_]+;", line): + # Replace name + if "AArch64" not in line: + output.append(line) + continue + entry_name: str = re.findall(r"AArch64[\w_]+", line)[0] + arm64_name = entry_name.replace("AArch64", "ARM64") + patched_line = re.sub( + r"AArch64.+", f"{arm64_name} = {entry_name},", line + ) + output.append(patched_line) + continue + # We still have LLVM and CS naming conventions mixed + p = re.sub(r"aarch64", "arm64", line) + p = re.sub(r"AArch64", "ARM64", p) + output.append(p) + typedef = "" + continue + + if re.search(f"^typedef\s+enum", line): + typedef = line + output.append("typedef enum {\n") + continue + output.append(line) + return output + + def remove_comments(self, aarch64_lines: list[str]) -> list[str]: + output = list() + for line in aarch64_lines: + if re.search(r"^\s*//", line) and "// SPDX" not in line: + continue + output.append(line) + return output + + def replace_aarch64(self, aarch64_lines: list[str]) -> list[str]: + output = list() + in_typedef = False + for line in aarch64_lines: + if in_typedef: + if re.search(r"^}\s[\w_]+;", line): + in_typedef = False + output.append(line) + continue + + if re.search(f"^typedef", line): + in_typedef = True + output.append(line) + continue + output.append(re.sub(r"AArch64", "ARM64", line)) + return output + + def replace_include_guards(self, aarch64_lines: list[str]) -> list[str]: + output = list() + for line in aarch64_lines: + if not re.search(r"^#(ifndef|define)", line): + output.append(line) + continue + output.append(re.sub(r"AARCH64", "ARM64", line)) + return output + + def inject_aarch64_header(self, aarch64_lines: list[str]) -> list[str]: + output = list() + header_inserted = False + for line in aarch64_lines: + if re.search(r"^#include", line): + if not header_inserted: + output.append("#include \n") + header_inserted = True + output.append(line) + return output + + def generate_aarch64_compat_header(self) -> bool: + """ + Translates the aarch64.h header into the arm64.h header and renames all aarch64 occurrences. + It does simple regex matching and replacing. + """ + log.info("Generate compatibility header") + with open(self.aarch64_h) as f: + aarch64 = f.readlines() + + patched = self.replace_typedef_struct(aarch64) + patched = self.replace_typedef_enum(patched) + patched = self.remove_comments(patched) + patched = self.replace_aarch64(patched) + patched = self.replace_include_guards(patched) + patched = self.inject_aarch64_header(patched) + + with open(self.arm64_h, "w+") as f: + f.writelines(patched) + + if __name__ == "__main__": args = parse_args() - patcher = HeaderPatcher(args.header, args.inc) - patcher.patch_header() + if (not args.patch and not args.compat) or (args.patch and args.compat): + print("You need to specify either -c or -p") + exit(1) + if args.compat and not (args.aarch64 and args.arm64): + print( + "Generating the arm64 compatibility header requires --arm64 and --aarch64" + ) + exit(1) + if args.patch and not (args.inc and args.header): + print("Patching headers requires --inc and --header") + exit(1) + + if args.patch: + patcher = HeaderPatcher(args.header, args.inc) + patcher.patch_header() + exit(0) + + builder = CompatHeaderBuilder(args.aarch64, args.arm64) + builder.generate_aarch64_compat_header() diff --git a/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h b/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h new file mode 100644 index 000000000..f56de4149 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_aarch64_header.h @@ -0,0 +1,49 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef CAPSTONE_AARCH64_H +#define CAPSTONE_AARCH64_H + +#include "cs_operand.h" + +inline static unsigned AArch64CC_getNZCVToSatisfyCondCode(AArch64CC_CondCode Code) +{ + // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. + enum { N = 8, Z = 4, C = 2, V = 1 }; + switch (Code) { + default: + assert(0 && "Unknown condition code"); + case AArch64CC_EQ: + return Z; // Z == 1 + } +} + +typedef union { + aarch64_dbnxs dbnxs; + aarch64_exactfpimm exactfpimm; +} aarch64_sysop_imm; + +typedef enum aarch64_op_type { + AArch64_OP_SYSALIAS = CS_OP_SPECIAL + 27, // Equal Equal + AArch64_OP_SYSALIASI, + AArch64_OP_SYSALIASII = 0, + AArch64_OP_SYSALIASIII, // Comment +} aarch64_op_type; + +#define MAX_AARCH64_OPS 8 + +/// Instruction structure +typedef struct cs_aarch64 { + AArch64CC_CondCode cc; ///< conditional code for this insn + bool update_flags; ///< does this insn update flags? + bool post_index; ///< only set if writeback is 'True', if 'False' pre-index, otherwise post. + bool is_doing_sme; ///< True if a SME operand is currently edited. + + /// Number of operands of this instruction, + /// or 0 when instruction has no operand. + uint8_t op_count; + + cs_aarch64_op operands[MAX_AARCH64_OPS]; ///< operands for this instruction. +} cs_aarch64; + +#endif diff --git a/suite/auto-sync/src/autosync/Tests/test_arm64_header.h b/suite/auto-sync/src/autosync/Tests/test_arm64_header.h new file mode 100644 index 000000000..8d1c931d8 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_arm64_header.h @@ -0,0 +1,34 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifndef CAPSTONE_ARM64_H +#define CAPSTONE_ARM64_H + +#include +#include "cs_operand.h" + +inline static unsigned ARM64CC_getNZCVToSatisfyCondCode(ARM64CC_CondCode Code) +{ + enum { N = 8, Z = 4, C = 2, V = 1 }; + switch (Code) { + default: + assert(0 && "Unknown condition code"); + case ARM64CC_EQ: + return Z; // Z == 1 + } +} + +typedef aarch64_sysop_imm arm64_sysop_imm; + +typedef enum { + ARM64_OP_SYSALIAS = AArch64_OP_SYSALIAS, + ARM64_OP_SYSALIASI = AArch64_OP_SYSALIASI, + ARM64_OP_SYSALIASII = AArch64_OP_SYSALIASII, + ARM64_OP_SYSALIASIII = AArch64_OP_SYSALIASIII, +} arm64_op_type; + +#define MAX_ARM64_OPS 8 + +typedef cs_aarch64 cs_arm64; + +#endif diff --git a/suite/auto-sync/src/autosync/Tests/test_header_patcher.py b/suite/auto-sync/src/autosync/Tests/test_header_patcher.py index 6aef639ce..1e423ad47 100644 --- a/suite/auto-sync/src/autosync/Tests/test_header_patcher.py +++ b/suite/auto-sync/src/autosync/Tests/test_header_patcher.py @@ -3,7 +3,7 @@ import unittest -from autosync.HeaderPatcher import HeaderPatcher +from autosync.HeaderPatcher import CompatHeaderBuilder, HeaderPatcher from autosync.Helper import get_path @@ -15,6 +15,10 @@ class TestHeaderPatcher(unittest.TestCase): get_path("{HEADER_PATCHER_TEST_INC_FILE}"), write_file=False, ) + cls.compat_gen = CompatHeaderBuilder( + get_path("{HEADER_GEN_TEST_AARCH64_FILE}"), + get_path("{HEADER_GEN_TEST_ARM64_OUT_FILE}"), + ) def test_header_patching(self): self.hpatcher.patch_header() @@ -45,3 +49,10 @@ class TestHeaderPatcher(unittest.TestCase): "\n" ), ) + + def test_compat_header_gen(self): + self.compat_gen.generate_aarch64_compat_header() + with open(get_path("{HEADER_GEN_TEST_ARM64_FILE}")) as f: + correct = f.read() + with open(get_path("{HEADER_GEN_TEST_ARM64_OUT_FILE}")) as f: + self.assertEqual(f.read(), correct) diff --git a/suite/auto-sync/src/autosync/path_vars.json b/suite/auto-sync/src/autosync/path_vars.json index 498f1e451..cc949b06f 100644 --- a/suite/auto-sync/src/autosync/path_vars.json +++ b/suite/auto-sync/src/autosync/path_vars.json @@ -22,6 +22,9 @@ "{CS_CLANG_FORMAT_FILE}": "{CS_ROOT}/.clang-format", "{HEADER_PATCHER_TEST_HEADER_FILE}": "{AUTO_SYNC_SRC}/Tests/test_header.h", "{HEADER_PATCHER_TEST_INC_FILE}": "{AUTO_SYNC_SRC}/Tests/test_include.inc", + "{HEADER_GEN_TEST_AARCH64_FILE}": "{AUTO_SYNC_SRC}/Tests/test_aarch64_header.h", + "{HEADER_GEN_TEST_ARM64_FILE}": "{AUTO_SYNC_SRC}/Tests/test_arm64_header.h", + "{HEADER_GEN_TEST_ARM64_OUT_FILE}": "{AUTO_SYNC_SRC}/Tests/test_arm64_header.h.out", "{DIFFER_TEST_DIR}": "{CPP_TRANSLATOR_TEST_DIR}/Differ/", "{DIFFER_TEST_CONFIG_FILE}": "{DIFFER_TEST_DIR}/test_arch_config.json", "{DIFFER_TEST_OLD_SRC_DIR}": "{DIFFER_TEST_DIR}/old_src/", @@ -33,7 +36,8 @@ "{C_INC_OUT_DIR}", "{CPP_INC_OUT_DIR}", "{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}", - "{CPP_TRANSLATOR_DIFF_OUT_DIR}" + "{CPP_TRANSLATOR_DIFF_OUT_DIR}", + "{HEADER_GEN_TEST_ARM64_OUT_FILE}" ], "ignore_missing": [ "{DIFFER_TEST_PERSISTENCE_FILE}"