xtensa: update to espressif/llvm-project (#2533)

Mapping.h

@@ -33,6 +33,7 @@ typedef struct insn_map {
 		loongarch_suppl_info loongarch;
 		aarch64_suppl_info aarch64;
 		systemz_suppl_info systemz;
+		xtensa_suppl_info xtensa;
 	} suppl_info; // Supplementary information for each instruction.
 #endif
 } insn_map;

arch/Xtensa/XtensaDisassembler.c

@@ -37,6 +37,7 @@
 #include "../../SStream.h"
 #include "../../cs_priv.h"
 #include "../../utils.h"
+
 #include "priv.h"
 
 #define GET_INSTRINFO_MC_DESC
@@ -53,6 +54,40 @@ static const unsigned ARDecoderTable[] = {
 	Xtensa_A12, Xtensa_A13, Xtensa_A14, Xtensa_A15
 };
 
+static const unsigned AE_DRDecoderTable[] = {
+	Xtensa_AED0,  Xtensa_AED1,  Xtensa_AED2,  Xtensa_AED3,
+	Xtensa_AED4,  Xtensa_AED5,  Xtensa_AED6,  Xtensa_AED7,
+	Xtensa_AED8,  Xtensa_AED9,  Xtensa_AED10, Xtensa_AED11,
+	Xtensa_AED12, Xtensa_AED13, Xtensa_AED14, Xtensa_AED15
+};
+
+static const unsigned AE_VALIGNDecoderTable[] = { Xtensa_U0, Xtensa_U1,
+						  Xtensa_U2, Xtensa_U3 };
+
+static DecodeStatus DecodeAE_DRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					     uint64_t Address,
+					     const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(AE_DRDecoderTable))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = AE_DRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeAE_VALIGNRegisterClass(MCInst *Inst, uint64_t RegNo,
+						 uint64_t Address,
+						 const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(AE_VALIGNDecoderTable))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = AE_VALIGNDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeARRegisterClass(MCInst *Inst, uint64_t RegNo,
 					  uint64_t Address, const void *Decoder)
 {
@@ -64,17 +99,414 @@ static DecodeStatus DecodeARRegisterClass(MCInst *Inst, uint64_t RegNo,
 	return MCDisassembler_Success;
 }
 
-static const unsigned SRDecoderTable[] = { Xtensa_SAR, 3 };
+static const unsigned QRDecoderTable[] = { Xtensa_Q0, Xtensa_Q1, Xtensa_Q2,
+					   Xtensa_Q3, Xtensa_Q4, Xtensa_Q5,
+					   Xtensa_Q6, Xtensa_Q7 };
+
+static DecodeStatus DecodeQRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					  uint64_t Address, const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(QRDecoderTable))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = QRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static const unsigned FPRDecoderTable[] = {
+	Xtensa_F0,  Xtensa_F1,	Xtensa_F2,  Xtensa_F3, Xtensa_F4,  Xtensa_F5,
+	Xtensa_F6,  Xtensa_F7,	Xtensa_F8,  Xtensa_F9, Xtensa_F10, Xtensa_F11,
+	Xtensa_F12, Xtensa_F13, Xtensa_F14, Xtensa_F15
+};
+
+static DecodeStatus DecodeFPRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(FPRDecoderTable))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = FPRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static const unsigned BRDecoderTable[] = {
+	Xtensa_B0,  Xtensa_B1,	Xtensa_B2,  Xtensa_B3, Xtensa_B4,  Xtensa_B5,
+	Xtensa_B6,  Xtensa_B7,	Xtensa_B8,  Xtensa_B9, Xtensa_B10, Xtensa_B11,
+	Xtensa_B12, Xtensa_B13, Xtensa_B14, Xtensa_B15
+};
+
+static const unsigned BR2DecoderTable[] = { Xtensa_B0_B1,   Xtensa_B2_B3,
+					    Xtensa_B4_B5,   Xtensa_B6_B7,
+					    Xtensa_B8_B9,   Xtensa_B10_B11,
+					    Xtensa_B12_B13, Xtensa_B14_B15 };
+
+static const unsigned BR4DecoderTable[] = { Xtensa_B0_B1_B2_B3,
+					    Xtensa_B4_B5_B6_B7,
+					    Xtensa_B8_B9_B10_B11,
+					    Xtensa_B12_B13_B14_B15 };
+
+static DecodeStatus DecodeXtensaRegisterClass(MCInst *Inst, uint64_t RegNo,
+					      uint64_t Address,
+					      const void *Decoder,
+					      const unsigned *DecoderTable,
+					      size_t DecoderTableLen)
+{
+	if (RegNo >= DecoderTableLen)
+		return MCDisassembler_Fail;
+
+	unsigned Reg = DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBR2RegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	return DecodeXtensaRegisterClass(Inst, RegNo, Address, Decoder,
+					 BR2DecoderTable,
+					 ARR_SIZE(BR2DecoderTable));
+}
+
+static DecodeStatus DecodeBR4RegisterClass(MCInst *Inst, uint64_t RegNo,
+					   uint64_t Address,
+					   const void *Decoder)
+{
+	return DecodeXtensaRegisterClass(Inst, RegNo, Address, Decoder,
+					 BR4DecoderTable,
+					 ARR_SIZE(BR4DecoderTable));
+}
+
+static DecodeStatus DecodeBRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					  uint64_t Address, const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(BRDecoderTable))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = BRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static const unsigned MRDecoderTable[] = { Xtensa_M0, Xtensa_M1, Xtensa_M2,
+					   Xtensa_M3 };
+
+static DecodeStatus DecodeMRRegisterClass(MCInst *Inst, uint64_t RegNo,
+					  uint64_t Address, const void *Decoder)
+{
+	if (RegNo >= ARR_SIZE(MRDecoderTable))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = MRDecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static const unsigned MR01DecoderTable[] = { Xtensa_M0, Xtensa_M1 };
+
+static DecodeStatus DecodeMR01RegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	if (RegNo > 2)
+		return MCDisassembler_Fail;
+
+	unsigned Reg = MR01DecoderTable[RegNo];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+static const unsigned MR23DecoderTable[] = { Xtensa_M2, Xtensa_M3 };
+
+static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo,
+					    uint64_t Address,
+					    const void *Decoder)
+{
+	if ((RegNo < 2) || (RegNo > 3))
+		return MCDisassembler_Fail;
+
+	unsigned Reg = MR23DecoderTable[RegNo - 2];
+	MCOperand_CreateReg0(Inst, (Reg));
+	return MCDisassembler_Success;
+}
+
+bool Xtensa_getFeatureBits(unsigned int mode, unsigned int feature)
+{
+	// we support everything
+	return true;
+}
+
+// Verify SR and UR
+bool CheckRegister(MCInst *Inst, unsigned RegNo)
+{
+	unsigned NumIntLevels = 0;
+	unsigned NumTimers = 0;
+	unsigned NumMiscSR = 0;
+	bool IsESP32 = false;
+	bool IsESP32S2 = false;
+	bool Res = true;
+
+	// Assume that CPU is esp32 by default
+	if ((Inst->csh->mode & CS_MODE_XTENSA_ESP32)) {
+		NumIntLevels = 6;
+		NumTimers = 3;
+		NumMiscSR = 4;
+		IsESP32 = true;
+	} else if (Inst->csh->mode & CS_MODE_XTENSA_ESP32S2) {
+		NumIntLevels = 6;
+		NumTimers = 3;
+		NumMiscSR = 4;
+		IsESP32S2 = true;
+	} else if (Inst->csh->mode & CS_MODE_XTENSA_ESP8266) {
+		NumIntLevels = 2;
+		NumTimers = 1;
+	}
+
+	switch (RegNo) {
+	case Xtensa_LBEG:
+	case Xtensa_LEND:
+	case Xtensa_LCOUNT:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureLoop);
+		break;
+	case Xtensa_BREG:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureBoolean);
+		break;
+	case Xtensa_LITBASE:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureExtendedL32R);
+		break;
+	case Xtensa_SCOMPARE1:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureS32C1I);
+		break;
+	case Xtensa_ACCLO:
+	case Xtensa_ACCHI:
+	case Xtensa_M0:
+	case Xtensa_M1:
+	case Xtensa_M2:
+	case Xtensa_M3:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureMAC16);
+		break;
+	case Xtensa_WINDOWBASE:
+	case Xtensa_WINDOWSTART:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureWindowed);
+		break;
+	case Xtensa_IBREAKENABLE:
+	case Xtensa_IBREAKA0:
+	case Xtensa_IBREAKA1:
+	case Xtensa_DBREAKA0:
+	case Xtensa_DBREAKA1:
+	case Xtensa_DBREAKC0:
+	case Xtensa_DBREAKC1:
+	case Xtensa_DEBUGCAUSE:
+	case Xtensa_ICOUNT:
+	case Xtensa_ICOUNTLEVEL:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureDebug);
+		break;
+	case Xtensa_ATOMCTL:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureATOMCTL);
+		break;
+	case Xtensa_MEMCTL:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureMEMCTL);
+		break;
+	case Xtensa_EPC1:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureException);
+		break;
+	case Xtensa_EPC2:
+	case Xtensa_EPC3:
+	case Xtensa_EPC4:
+	case Xtensa_EPC5:
+	case Xtensa_EPC6:
+	case Xtensa_EPC7:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureHighPriInterrupts);
+		Res = Res & (NumIntLevels >= (RegNo - Xtensa_EPC1));
+		break;
+	case Xtensa_EPS2:
+	case Xtensa_EPS3:
+	case Xtensa_EPS4:
+	case Xtensa_EPS5:
+	case Xtensa_EPS6:
+	case Xtensa_EPS7:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureHighPriInterrupts);
+		Res = Res & (NumIntLevels > (RegNo - Xtensa_EPS2));
+		break;
+	case Xtensa_EXCSAVE1:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureException);
+		break;
+	case Xtensa_EXCSAVE2:
+	case Xtensa_EXCSAVE3:
+	case Xtensa_EXCSAVE4:
+	case Xtensa_EXCSAVE5:
+	case Xtensa_EXCSAVE6:
+	case Xtensa_EXCSAVE7:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureHighPriInterrupts);
+		Res = Res & (NumIntLevels >= (RegNo - Xtensa_EXCSAVE1));
+		break;
+	case Xtensa_DEPC:
+	case Xtensa_EXCCAUSE:
+	case Xtensa_EXCVADDR:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureException);
+		break;
+	case Xtensa_CPENABLE:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureCoprocessor);
+		break;
+	case Xtensa_VECBASE:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureRelocatableVector);
+		break;
+	case Xtensa_CCOUNT:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureTimerInt);
+		Res &= (NumTimers > 0);
+		break;
+	case Xtensa_CCOMPARE0:
+	case Xtensa_CCOMPARE1:
+	case Xtensa_CCOMPARE2:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureTimerInt);
+		Res &= (NumTimers > (RegNo - Xtensa_CCOMPARE0));
+		break;
+	case Xtensa_PRID:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeaturePRID);
+		break;
+	case Xtensa_INTERRUPT:
+	case Xtensa_INTCLEAR:
+	case Xtensa_INTENABLE:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureInterrupt);
+		break;
+	case Xtensa_MISC0:
+	case Xtensa_MISC1:
+	case Xtensa_MISC2:
+	case Xtensa_MISC3:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureMiscSR);
+		Res &= (NumMiscSR > (RegNo - Xtensa_MISC0));
+		break;
+	case Xtensa_THREADPTR:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureTHREADPTR);
+		break;
+	case Xtensa_GPIO_OUT:
+		Res = IsESP32S2;
+		break;
+	case Xtensa_EXPSTATE:
+		Res = IsESP32;
+		break;
+	case Xtensa_FCR:
+	case Xtensa_FSR:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureSingleFloat);
+		break;
+	case Xtensa_F64R_LO:
+	case Xtensa_F64R_HI:
+	case Xtensa_F64S:
+		Res = Xtensa_getFeatureBits(Inst->csh->mode,
+					    Xtensa_FeatureDFPAccel);
+		break;
+	}
+
+	return Res;
+}
+
+static const unsigned SRDecoderTable[] = {
+	Xtensa_LBEG,	    0,	 Xtensa_LEND,	      1,
+	Xtensa_LCOUNT,	    2,	 Xtensa_SAR,	      3,
+	Xtensa_BREG,	    4,	 Xtensa_LITBASE,      5,
+	Xtensa_SCOMPARE1,   12,	 Xtensa_ACCLO,	      16,
+	Xtensa_ACCHI,	    17,	 Xtensa_M0,	      32,
+	Xtensa_M1,	    33,	 Xtensa_M2,	      34,
+	Xtensa_M3,	    35,	 Xtensa_WINDOWBASE,   72,
+	Xtensa_WINDOWSTART, 73,	 Xtensa_IBREAKENABLE, 96,
+	Xtensa_MEMCTL,	    97,	 Xtensa_ATOMCTL,      99,
+	Xtensa_DDR,	    104, Xtensa_IBREAKA0,     128,
+	Xtensa_IBREAKA1,    129, Xtensa_DBREAKA0,     144,
+	Xtensa_DBREAKA1,    145, Xtensa_DBREAKC0,     160,
+	Xtensa_DBREAKC1,    161, Xtensa_CONFIGID0,    176,
+	Xtensa_EPC1,	    177, Xtensa_EPC2,	      178,
+	Xtensa_EPC3,	    179, Xtensa_EPC4,	      180,
+	Xtensa_EPC5,	    181, Xtensa_EPC6,	      182,
+	Xtensa_EPC7,	    183, Xtensa_DEPC,	      192,
+	Xtensa_EPS2,	    194, Xtensa_EPS3,	      195,
+	Xtensa_EPS4,	    196, Xtensa_EPS5,	      197,
+	Xtensa_EPS6,	    198, Xtensa_EPS7,	      199,
+	Xtensa_CONFIGID1,   208, Xtensa_EXCSAVE1,     209,
+	Xtensa_EXCSAVE2,    210, Xtensa_EXCSAVE3,     211,
+	Xtensa_EXCSAVE4,    212, Xtensa_EXCSAVE5,     213,
+	Xtensa_EXCSAVE6,    214, Xtensa_EXCSAVE7,     215,
+	Xtensa_CPENABLE,    224, Xtensa_INTERRUPT,    226,
+	Xtensa_INTCLEAR,    227, Xtensa_INTENABLE,    228,
+	Xtensa_PS,	    230, Xtensa_VECBASE,      231,
+	Xtensa_EXCCAUSE,    232, Xtensa_DEBUGCAUSE,   233,
+	Xtensa_CCOUNT,	    234, Xtensa_PRID,	      235,
+	Xtensa_ICOUNT,	    236, Xtensa_ICOUNTLEVEL,  237,
+	Xtensa_EXCVADDR,    238, Xtensa_CCOMPARE0,    240,
+	Xtensa_CCOMPARE1,   241, Xtensa_CCOMPARE2,    242,
+	Xtensa_MISC0,	    244, Xtensa_MISC1,	      245,
+	Xtensa_MISC2,	    246, Xtensa_MISC3,	      247
+};
 
 static DecodeStatus DecodeSRRegisterClass(MCInst *Inst, uint64_t RegNo,
 					  uint64_t Address, const void *Decoder)
+{
+	//	const llvm_MCSubtargetInfo STI =
+	//		((const MCDisassembler *)Decoder)->getSubtargetInfo();
+
+	if (RegNo > 255)
+		return MCDisassembler_Fail;
+
+	for (unsigned i = 0; i < ARR_SIZE(SRDecoderTable); i += 2) {
+		if (SRDecoderTable[i + 1] == RegNo) {
+			unsigned Reg = SRDecoderTable[i];
+
+			if (!CheckRegister(Inst, Reg))
+				return MCDisassembler_Fail;
+
+			MCOperand_CreateReg0(Inst, (Reg));
+			return MCDisassembler_Success;
+		}
+	}
+
+	return MCDisassembler_Fail;
+}
+
+static const unsigned URDecoderTable[] = {
+	Xtensa_GPIO_OUT, 0,   Xtensa_EXPSTATE, 230, Xtensa_THREADPTR, 231,
+	Xtensa_FCR,	 232, Xtensa_FSR,      233, Xtensa_F64R_LO,   234,
+	Xtensa_F64R_HI,	 235, Xtensa_F64S,     236
+};
+
+static DecodeStatus DecodeURRegisterClass(MCInst *Inst, uint64_t RegNo,
+					  uint64_t Address, const void *Decoder)
 {
 	if (RegNo > 255)
 		return MCDisassembler_Fail;
 
-	for (unsigned i = 0; i + 1 < ARR_SIZE(SRDecoderTable); i += 2) {
+	for (unsigned i = 0; i < ARR_SIZE(URDecoderTable); i += 2) {
-		if (SRDecoderTable[i + 1] == RegNo) {
+		if (URDecoderTable[i + 1] == RegNo) {
-			unsigned Reg = SRDecoderTable[i];
+			unsigned Reg = URDecoderTable[i];
+
+			if (!CheckRegister(Inst, Reg))
+				return MCDisassembler_Fail;
+
 			MCOperand_CreateReg0(Inst, (Reg));
 			return MCDisassembler_Success;
 		}
@@ -133,13 +565,21 @@ static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm,
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus decodeLoopOperand(MCInst *Inst, uint64_t Imm,
+				      int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	if (!tryAddingSymbolicOperand(Imm + 4 + Address, true, Address, 0, 3,
+				      Inst, Decoder))
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm,
 				      int64_t Address, const void *Decoder)
 {
 	CS_ASSERT(isUIntN(16, Imm) && "Invalid immediate");
-	MCOperand_CreateImm0(
+	MCOperand_CreateImm0(Inst, OneExtend64(Imm << 2, 18));
-		Inst,
-		(SignExtend64(((Imm << 2) + 0x40000 + (Address & 0x3)), 17)));
 	return MCDisassembler_Success;
 }
 
@@ -154,7 +594,8 @@ static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm,
 static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm,
 					  int64_t Address, const void *Decoder)
 {
-	CS_ASSERT(isUIntN(16, Imm) && "Invalid immediate");
+	CS_ASSERT(isUIntN(16, Imm) && ((Imm & 0xff) == 0) &&
+		  "Invalid immediate");
 	MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 16)));
 	return MCDisassembler_Success;
 }
@@ -191,6 +632,67 @@ static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm,
 	return MCDisassembler_Success;
 }
 
+static DecodeStatus decodeImm1n_15Operand(MCInst *Inst, uint64_t Imm,
+					  int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(4, Imm) && "Invalid immediate");
+	if (!Imm)
+		MCOperand_CreateImm0(Inst, (-1));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeImm32n_95Operand(MCInst *Inst, uint64_t Imm,
+					   int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(7, Imm) && "Invalid immediate");
+	if ((Imm & 0x60) == 0x60)
+		MCOperand_CreateImm0(Inst, ((~0x1f) | Imm));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeImm8n_7Operand(MCInst *Inst, uint64_t Imm,
+					 int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(4, Imm) && "Invalid immediate");
+	if (Imm > 7)
+		MCOperand_CreateImm0(Inst, (Imm - 16));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeImm64n_4nOperand(MCInst *Inst, uint64_t Imm,
+					   int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(6, Imm) && ((Imm & 0x3) == 0) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, ((~0x3f) | (Imm)));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset8m32Operand(MCInst *Inst, uint64_t Imm,
+					    int64_t Address,
+					    const void *Decoder)
+{
+	CS_ASSERT(isUIntN(10, Imm) && ((Imm & 0x3) == 0) &&
+		  "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeEntry_Imm12OpValue(MCInst *Inst, uint64_t Imm,
+					     int64_t Address,
+					     const void *Decoder)
+{
+	CS_ASSERT(isUIntN(15, Imm) && ((Imm & 0x7) == 0) &&
+		  "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm,
 					   int64_t Address, const void *Decoder)
 {
@@ -199,6 +701,144 @@ static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm,
 	return MCDisassembler_Success;
 }
 
+//static DecodeStatus decodeShimm0_31Operand(MCInst *Inst, uint64_t Imm,
+//					   int64_t Address, const void *Decoder)
+//{
+//	CS_ASSERT(isUIntN(5, Imm) && "Invalid immediate");
+//	MCOperand_CreateImm0(Inst, (32 - Imm));
+//	return MCDisassembler_Success;
+//}
+
+static DecodeStatus decodeImm7_22Operand(MCInst *Inst, uint64_t Imm,
+					 int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(4, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm + 7));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSelect_2Operand(MCInst *Inst, uint64_t Imm,
+					  int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSelect_4Operand(MCInst *Inst, uint64_t Imm,
+					  int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSelect_8Operand(MCInst *Inst, uint64_t Imm,
+					  int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSelect_16Operand(MCInst *Inst, uint64_t Imm,
+					   int64_t Address, const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeSelect_256Operand(MCInst *Inst, uint64_t Imm,
+					    int64_t Address,
+					    const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_16_16Operand(MCInst *Inst, uint64_t Imm,
+					      int64_t Address,
+					      const void *Decoder)
+{
+	CS_ASSERT(isIntN(Imm, 8) && "Invalid immediate");
+	if ((Imm & 0xf) != 0)
+		MCOperand_CreateImm0(Inst, (Imm << 4));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_256_8Operand(MCInst *Inst, uint64_t Imm,
+					      int64_t Address,
+					      const void *Decoder)
+{
+	CS_ASSERT(isIntN(16, Imm) && "Invalid immediate");
+	if ((Imm & 0x7) != 0)
+		MCOperand_CreateImm0(Inst, (Imm << 3));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_256_16Operand(MCInst *Inst, uint64_t Imm,
+					       int64_t Address,
+					       const void *Decoder)
+{
+	CS_ASSERT(isIntN(16, Imm) && "Invalid immediate");
+	if ((Imm & 0xf) != 0)
+		MCOperand_CreateImm0(Inst, (Imm << 4));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_256_4Operand(MCInst *Inst, uint64_t Imm,
+					      int64_t Address,
+					      const void *Decoder)
+{
+	CS_ASSERT(isIntN(16, Imm) && "Invalid immediate");
+	if ((Imm & 0x2) != 0)
+		MCOperand_CreateImm0(Inst, (Imm << 2));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_128_2Operand(MCInst *Inst, uint64_t Imm,
+					      int64_t Address,
+					      const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	if ((Imm & 0x1) != 0)
+		MCOperand_CreateImm0(Inst, (Imm << 1));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_128_1Operand(MCInst *Inst, uint64_t Imm,
+					      int64_t Address,
+					      const void *Decoder)
+{
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
+	MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus decodeOffset_64_16Operand(MCInst *Inst, uint64_t Imm,
+					      int64_t Address,
+					      const void *Decoder)
+{
+	CS_ASSERT(isIntN(16, Imm) && "Invalid immediate");
+	if ((Imm & 0xf) != 0)
+		MCOperand_CreateImm0(Inst, (Imm << 4));
+	else
+		MCOperand_CreateImm0(Inst, (Imm));
+	return MCDisassembler_Success;
+}
+
 static int64_t TableB4const[16] = { -1, 1,  2,	3,  4,	5,  6,	 7,
 				    8,	10, 12, 16, 32, 64, 128, 256 };
 static DecodeStatus decodeB4constOperand(MCInst *Inst, uint64_t Imm,
@@ -248,40 +888,202 @@ static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm,
 	return MCDisassembler_Success;
 }
 
-/// Read three bytes from the ArrayRef and return 24 bit data
+static DecodeStatus decodeMem32nOperand(MCInst *Inst, uint64_t Imm,
-static DecodeStatus readInstruction24(MCInst *MI, uint64_t *SizeOut,
+					int64_t Address, const void *Decoder)
-				      const uint8_t *Bytes,
-				      const unsigned BytesSize, uint32_t *Insn)
 {
-	// We want to read exactly 3 Bytes of data.
+	CS_ASSERT(isUIntN(8, Imm) && "Invalid immediate");
-	if (BytesSize < 3) {
+	DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
-		*SizeOut = 0;
+	MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3c));
+	return MCDisassembler_Success;
+}
+
+/// Read two bytes from the ArrayRef and return 16 bit data sorted
+/// according to the given endianness.
+static DecodeStatus readInstruction16(MCInst *MI, const uint8_t *Bytes,
+				      size_t BytesLen, uint64_t Address,
+				      uint64_t *Size, uint64_t *Insn,
+				      bool IsLittleEndian)
+{
+	// We want to read exactly 2 Bytes of data.
+	if (BytesLen < 2) {
+		*Size = 0;
 		return MCDisassembler_Fail;
 	}
 
+	*Insn = readBytes16(MI, Bytes);
+	*Size = 2;
+
+	return MCDisassembler_Success;
+}
+
+/// Read three bytes from the ArrayRef and return 24 bit data
+static DecodeStatus readInstruction24(MCInst *MI, const uint8_t *Bytes,
+				      size_t BytesLen, uint64_t Address,
+				      uint64_t *Size, uint64_t *Insn,
+				      bool IsLittleEndian, bool CheckTIE)
+{
+	// We want to read exactly 3 Bytes of data.
+	if (BytesLen < 3) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	if (CheckTIE && (Bytes[0] & 0x8) != 0)
+		return MCDisassembler_Fail;
 	*Insn = readBytes24(MI, Bytes);
-	*SizeOut = 3;
+	*Size = 3;
+
+	return MCDisassembler_Success;
+}
+
+/// Read three bytes from the ArrayRef and return 32 bit data
+static DecodeStatus readInstruction32(MCInst *MI, const uint8_t *Bytes,
+				      size_t BytesLen, uint64_t Address,
+				      uint64_t *Size, uint64_t *Insn,
+				      bool IsLittleEndian)
+{
+	// We want to read exactly 4 Bytes of data.
+	if (BytesLen < 4) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	if ((Bytes[0] & 0x8) == 0)
+		return MCDisassembler_Fail;
+	*Insn = readBytes32(MI, Bytes);
+	*Size = 4;
+
+	return MCDisassembler_Success;
+}
+
+/// Read InstSize bytes from the ArrayRef and return 24 bit data
+static DecodeStatus readInstructionN(const uint8_t *Bytes, size_t BytesLen,
+				     uint64_t Address, unsigned InstSize,
+				     uint64_t *Size, uint64_t *Insn,
+				     bool IsLittleEndian)
+{
+	// We want to read exactly 3 Bytes of data.
+	if (BytesLen < InstSize) {
+		*Size = 0;
+		return MCDisassembler_Fail;
+	}
+
+	*Insn = 0;
+	for (unsigned i = 0; i < InstSize; i++)
+		*Insn |= (Bytes[i] << 8 * i);
+
+	*Size = InstSize;
 	return MCDisassembler_Success;
 }
 
 #include "XtensaGenDisassemblerTables.inc"
 
-FieldFromInstruction(field_from_inst, uint32_t);
+FieldFromInstruction(fieldFromInstruction_2, uint64_t);
-DecodeToMCInst(decode_to_MCInst, field_from_inst, uint32_t);
+DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint64_t);
-DecodeInstruction(decodeInstruction, field_from_inst, decode_to_MCInst,
+DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2,
-		  uint32_t);
+		  uint64_t);
 
-static DecodeStatus getInstruction(MCInst *MI, uint64_t *SizeOut,
+FieldFromInstruction(fieldFromInstruction_4, uint64_t);
-				   const uint8_t *Bytes, unsigned BytesSize,
+DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint64_t);
+DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4,
+		  uint64_t);
+
+FieldFromInstruction(fieldFromInstruction_6, uint64_t);
+DecodeToMCInst(decodeToMCInst_6, fieldFromInstruction_6, uint64_t);
+DecodeInstruction(decodeInstruction_6, fieldFromInstruction_6, decodeToMCInst_6,
+		  uint64_t);
+
+static bool hasDensity()
+{
+	return true;
+}
+static bool hasESP32S3Ops()
+{
+	return true;
+}
+static bool hasHIFI3()
+{
+	return true;
+}
+
+static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size,
+				   const uint8_t *Bytes, size_t BytesLen,
 				   uint64_t Address)
 {
-	uint32_t Insn;
+	uint64_t Insn;
 	DecodeStatus Result;
+	bool IsLittleEndian = MI->csh->mode & CS_MODE_LITTLE_ENDIAN;
 
-	Result = readInstruction24(MI, SizeOut, Bytes, BytesSize, &Insn);
+	// Parse 16-bit instructions
+	if (hasDensity()) {
+		Result = readInstruction16(MI, Bytes, BytesLen, Address, Size,
+					   &Insn, IsLittleEndian);
+		if (Result == MCDisassembler_Fail)
+			return MCDisassembler_Fail;
+
+		Result = decodeInstruction_2(DecoderTable16, MI, Insn, Address,
+					     NULL);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 2;
+			return Result;
+		}
+	}
+
+	// Parse Core 24-bit instructions
+	Result = readInstruction24(MI, Bytes, BytesLen, Address, Size, &Insn,
+				   IsLittleEndian, false);
 	if (Result == MCDisassembler_Fail)
 		return MCDisassembler_Fail;
-	Result = decodeInstruction(DecoderTable24, MI, Insn, Address, NULL);
+
+	Result = decodeInstruction_3(DecoderTable24, MI, Insn, Address, NULL);
+	if (Result != MCDisassembler_Fail) {
+		*Size = 3;
+		return Result;
+	}
+
+	if (hasESP32S3Ops()) {
+		// Parse ESP32S3 24-bit instructions
+		Result = readInstruction24(MI, Bytes, BytesLen, Address, Size,
+					   &Insn, IsLittleEndian, true);
+		if (Result != MCDisassembler_Fail) {
+			Result = decodeInstruction_3(DecoderTableESP32S324, MI,
+						     Insn, Address, NULL);
+			if (Result != MCDisassembler_Fail) {
+				*Size = 3;
+				return Result;
+			}
+		}
+
+		// Parse ESP32S3 32-bit instructions
+		Result = readInstruction32(MI, Bytes, BytesLen, Address, Size,
+					   &Insn, IsLittleEndian);
+		if (Result == MCDisassembler_Fail)
+			return MCDisassembler_Fail;
+
+		Result = decodeInstruction_4(DecoderTableESP32S332, MI, Insn,
+					     Address, NULL);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
+		}
+	}
+
+	if (hasHIFI3()) {
+		Result = decodeInstruction_3(DecoderTableHIFI324, MI, Insn,
+					     Address, NULL);
+		if (Result != MCDisassembler_Fail)
+			return Result;
+
+		Result = readInstructionN(Bytes, BytesLen, Address, 48, Size,
+					  &Insn, IsLittleEndian);
+		if (Result == MCDisassembler_Fail)
+			return MCDisassembler_Fail;
+
+		Result = decodeInstruction_6(DecoderTableHIFI348, MI, Insn,
+					     Address, NULL);
+		if (Result != MCDisassembler_Fail)
+			return Result;
+	}
 	return Result;
 }
 

arch/Xtensa/XtensaGenCSFeatureName.inc

@@ -12,3 +12,36 @@
 /* https://github.com/capstone-engine/llvm-capstone */
 
 { XTENSA_FEATURE_HASDENSITY, "HasDensity" },
+{ XTENSA_FEATURE_HASSINGLEFLOAT, "HasSingleFloat" },
+{ XTENSA_FEATURE_HASWINDOWED, "HasWindowed" },
+{ XTENSA_FEATURE_HASBOOLEAN, "HasBoolean" },
+{ XTENSA_FEATURE_HASLOOP, "HasLoop" },
+{ XTENSA_FEATURE_HASSEXT, "HasSEXT" },
+{ XTENSA_FEATURE_HASCLAMPS, "HasCLAMPS" },
+{ XTENSA_FEATURE_HASNSA, "HasNSA" },
+{ XTENSA_FEATURE_HASMINMAX, "HasMINMAX" },
+{ XTENSA_FEATURE_HASMUL16, "HasMul16" },
+{ XTENSA_FEATURE_HASMUL32, "HasMul32" },
+{ XTENSA_FEATURE_HASMUL32HIGH, "HasMul32High" },
+{ XTENSA_FEATURE_HASDIV32, "HasDiv32" },
+{ XTENSA_FEATURE_HASMAC16, "HasMAC16" },
+{ XTENSA_FEATURE_HASDFPACCEL, "HasDFPAccel" },
+{ XTENSA_FEATURE_HASS32C1I, "HasS32C1I" },
+{ XTENSA_FEATURE_HASTHREADPTR, "HasTHREADPTR" },
+{ XTENSA_FEATURE_HASEXTENDEDL32R, "HasExtendedL32R" },
+{ XTENSA_FEATURE_HASATOMCTL, "HasATOMCTL" },
+{ XTENSA_FEATURE_HASMEMCTL, "HasMEMCTL" },
+{ XTENSA_FEATURE_HASDEBUG, "HasDebug" },
+{ XTENSA_FEATURE_HASEXCEPTION, "HasException" },
+{ XTENSA_FEATURE_HASHIGHPRIINTERRUPTS, "HasHighPriInterrupts" },
+{ XTENSA_FEATURE_HASCOPROCESSOR, "HasCoprocessor" },
+{ XTENSA_FEATURE_HASINTERRUPT, "HasInterrupt" },
+{ XTENSA_FEATURE_HASRELOCATABLEVECTOR, "HasRelocatableVector" },
+{ XTENSA_FEATURE_HASTIMERINT, "HasTimerInt" },
+{ XTENSA_FEATURE_HASPRID, "HasPRID" },
+{ XTENSA_FEATURE_HASREGIONPROTECTION, "HasRegionProtection" },
+{ XTENSA_FEATURE_HASMISCSR, "HasMiscSR" },
+{ XTENSA_FEATURE_HASESP32S2OPS, "HasESP32S2Ops" },
+{ XTENSA_FEATURE_HASESP32S3OPS, "HasESP32S3Ops" },
+{ XTENSA_FEATURE_HASHIFI3, "HasHIFI3" },
+{ XTENSA_FEATURE_HASFORCEDATOMICS, "HasForcedAtomics" },

arch/Xtensa/XtensaGenCSOpGroup.inc

@@ -11,18 +11,47 @@
 /* Capstone's LLVM TableGen Backends: */
 /* https://github.com/capstone-engine/llvm-capstone */
 
-  XTENSA_OP_GROUP_OPERAND = 0,
+  Xtensa_OP_GROUP_Operand = 0,
-  XTENSA_OP_GROUP_IMM8_ASMOPERAND = 1,
+  Xtensa_OP_GROUP_BranchTarget = 1,
-  XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND = 2,
+  Xtensa_OP_GROUP_Imm8_AsmOperand = 2,
-  XTENSA_OP_GROUP_BRANCHTARGET = 3,
+  Xtensa_OP_GROUP_Select_4_AsmOperand = 3,
-  XTENSA_OP_GROUP_UIMM5_ASMOPERAND = 4,
+  Xtensa_OP_GROUP_Select_2_AsmOperand = 4,
-  XTENSA_OP_GROUP_B4CONST_ASMOPERAND = 5,
+  Xtensa_OP_GROUP_Select_8_AsmOperand = 5,
-  XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND = 6,
+  Xtensa_OP_GROUP_Offset_16_16_AsmOperand = 6,
-  XTENSA_OP_GROUP_CALLOPERAND = 7,
+  Xtensa_OP_GROUP_Offset_256_8_AsmOperand = 7,
-  XTENSA_OP_GROUP_IMM1_16_ASMOPERAND = 8,
+  Xtensa_OP_GROUP_Offset_256_16_AsmOperand = 8,
-  XTENSA_OP_GROUP_JUMPTARGET = 9,
+  Xtensa_OP_GROUP_Offset_256_4_AsmOperand = 9,
-  XTENSA_OP_GROUP_MEMOPERAND = 10,
+  Xtensa_OP_GROUP_Select_16_AsmOperand = 10,
-  XTENSA_OP_GROUP_L32RTARGET = 11,
+  Xtensa_OP_GROUP_Offset_128_2_AsmOperand = 11,
-  XTENSA_OP_GROUP_IMM12M_ASMOPERAND = 12,
+  Xtensa_OP_GROUP_Offset_128_1_AsmOperand = 12,
-  XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND = 13,
+  Xtensa_OP_GROUP_Offset_64_16_AsmOperand = 13,
-  XTENSA_OP_GROUP_UIMM4_ASMOPERAND = 14,
+  Xtensa_OP_GROUP_MemOperand = 14,
+  Xtensa_OP_GROUP_Imm1n_15_AsmOperand = 15,
+  Xtensa_OP_GROUP_Imm8_sh8_AsmOperand = 16,
+  Xtensa_OP_GROUP_Imm1_16_AsmOperand = 17,
+  Xtensa_OP_GROUP_ImmOperand_minus16_14_2 = 18,
+  Xtensa_OP_GROUP_ImmOperand_minus32_28_4 = 19,
+  Xtensa_OP_GROUP_ImmOperand_minus64_56_8 = 20,
+  Xtensa_OP_GROUP_ImmOperand_0_56_8 = 21,
+  Xtensa_OP_GROUP_ImmOperand_minus16_47_1 = 22,
+  Xtensa_OP_GROUP_ImmOperand_0_3_1 = 23,
+  Xtensa_OP_GROUP_Uimm4_AsmOperand = 24,
+  Xtensa_OP_GROUP_Imm7_22_AsmOperand = 25,
+  Xtensa_OP_GROUP_Uimm5_AsmOperand = 26,
+  Xtensa_OP_GROUP_ImmOperand_0_63_1 = 27,
+  Xtensa_OP_GROUP_B4const_AsmOperand = 28,
+  Xtensa_OP_GROUP_B4constu_AsmOperand = 29,
+  Xtensa_OP_GROUP_CallOperand = 30,
+  Xtensa_OP_GROUP_Select_256_AsmOperand = 31,
+  Xtensa_OP_GROUP_Entry_Imm12_AsmOperand = 32,
+  Xtensa_OP_GROUP_JumpTarget = 33,
+  Xtensa_OP_GROUP_Imm64n_4n_AsmOperand = 34,
+  Xtensa_OP_GROUP_L32RTarget = 35,
+  Xtensa_OP_GROUP_LoopTarget = 36,
+  Xtensa_OP_GROUP_Offset8m32_AsmOperand = 37,
+  Xtensa_OP_GROUP_Imm12m_AsmOperand = 38,
+  Xtensa_OP_GROUP_Imm32n_95_AsmOperand = 39,
+  Xtensa_OP_GROUP_Imm8n_7_AsmOperand = 40,
+  Xtensa_OP_GROUP_Shimm0_31_AsmOperand = 41,
+  Xtensa_OP_GROUP_Imm12_AsmOperand = 42,
+  Xtensa_OP_GROUP_Shimm1_31_AsmOperand = 43,

arch/Xtensa/XtensaGenRegisterInfo.inc

@@ -3,33 +3,207 @@
 
 enum {
   Xtensa_NoRegister,
-  Xtensa_SAR = 1,
+  Xtensa_ACCHI = 1,
-  Xtensa_SP = 2,
+  Xtensa_ACCLO = 2,
-  Xtensa_A0 = 3,
+  Xtensa_ACCX = 3,
-  Xtensa_A2 = 4,
+  Xtensa_ATOMCTL = 4,
-  Xtensa_A3 = 5,
+  Xtensa_BREG = 5,
-  Xtensa_A4 = 6,
+  Xtensa_CCOUNT = 6,
-  Xtensa_A5 = 7,
+  Xtensa_CPENABLE = 7,
-  Xtensa_A6 = 8,
+  Xtensa_DDR = 8,
-  Xtensa_A7 = 9,
+  Xtensa_DEBUGCAUSE = 9,
-  Xtensa_A8 = 10,
+  Xtensa_DEPC = 10,
-  Xtensa_A9 = 11,
+  Xtensa_EXCCAUSE = 11,
-  Xtensa_A10 = 12,
+  Xtensa_EXCVADDR = 12,
-  Xtensa_A11 = 13,
+  Xtensa_EXPSTATE = 13,
-  Xtensa_A12 = 14,
+  Xtensa_FCR = 14,
-  Xtensa_A13 = 15,
+  Xtensa_FFT_BIT_WIDTH = 15,
-  Xtensa_A14 = 16,
+  Xtensa_FSR = 16,
-  Xtensa_A15 = 17,
+  Xtensa_GPIO_OUT = 17,
-  NUM_TARGET_REGS // 18
+  Xtensa_IBREAKENABLE = 18,
+  Xtensa_ICOUNT = 19,
+  Xtensa_ICOUNTLEVEL = 20,
+  Xtensa_INTCLEAR = 21,
+  Xtensa_INTENABLE = 22,
+  Xtensa_INTERRUPT = 23,
+  Xtensa_LBEG = 24,
+  Xtensa_LCOUNT = 25,
+  Xtensa_LEND = 26,
+  Xtensa_LITBASE = 27,
+  Xtensa_MEMCTL = 28,
+  Xtensa_PRID = 29,
+  Xtensa_PS = 30,
+  Xtensa_QACC = 31,
+  Xtensa_SAR = 32,
+  Xtensa_SAR_BYTE = 33,
+  Xtensa_SP = 34,
+  Xtensa_THREADPTR = 35,
+  Xtensa_UA_STATE = 36,
+  Xtensa_VECBASE = 37,
+  Xtensa_WINDOWBASE = 38,
+  Xtensa_WINDOWSTART = 39,
+  Xtensa_A0 = 40,
+  Xtensa_A2 = 41,
+  Xtensa_A3 = 42,
+  Xtensa_A4 = 43,
+  Xtensa_A5 = 44,
+  Xtensa_A6 = 45,
+  Xtensa_A7 = 46,
+  Xtensa_A8 = 47,
+  Xtensa_A9 = 48,
+  Xtensa_A10 = 49,
+  Xtensa_A11 = 50,
+  Xtensa_A12 = 51,
+  Xtensa_A13 = 52,
+  Xtensa_A14 = 53,
+  Xtensa_A15 = 54,
+  Xtensa_AED0 = 55,
+  Xtensa_AED1 = 56,
+  Xtensa_AED2 = 57,
+  Xtensa_AED3 = 58,
+  Xtensa_AED4 = 59,
+  Xtensa_AED5 = 60,
+  Xtensa_AED6 = 61,
+  Xtensa_AED7 = 62,
+  Xtensa_AED8 = 63,
+  Xtensa_AED9 = 64,
+  Xtensa_AED10 = 65,
+  Xtensa_AED11 = 66,
+  Xtensa_AED12 = 67,
+  Xtensa_AED13 = 68,
+  Xtensa_AED14 = 69,
+  Xtensa_AED15 = 70,
+  Xtensa_B0 = 71,
+  Xtensa_B1 = 72,
+  Xtensa_B2 = 73,
+  Xtensa_B3 = 74,
+  Xtensa_B4 = 75,
+  Xtensa_B5 = 76,
+  Xtensa_B6 = 77,
+  Xtensa_B7 = 78,
+  Xtensa_B8 = 79,
+  Xtensa_B9 = 80,
+  Xtensa_B10 = 81,
+  Xtensa_B11 = 82,
+  Xtensa_B12 = 83,
+  Xtensa_B13 = 84,
+  Xtensa_B14 = 85,
+  Xtensa_B15 = 86,
+  Xtensa_CCOMPARE0 = 87,
+  Xtensa_CCOMPARE1 = 88,
+  Xtensa_CCOMPARE2 = 89,
+  Xtensa_CONFIGID0 = 90,
+  Xtensa_CONFIGID1 = 91,
+  Xtensa_DBREAKA0 = 92,
+  Xtensa_DBREAKA1 = 93,
+  Xtensa_DBREAKC0 = 94,
+  Xtensa_DBREAKC1 = 95,
+  Xtensa_EPC1 = 96,
+  Xtensa_EPC2 = 97,
+  Xtensa_EPC3 = 98,
+  Xtensa_EPC4 = 99,
+  Xtensa_EPC5 = 100,
+  Xtensa_EPC6 = 101,
+  Xtensa_EPC7 = 102,
+  Xtensa_EPS2 = 103,
+  Xtensa_EPS3 = 104,
+  Xtensa_EPS4 = 105,
+  Xtensa_EPS5 = 106,
+  Xtensa_EPS6 = 107,
+  Xtensa_EPS7 = 108,
+  Xtensa_EXCSAVE1 = 109,
+  Xtensa_EXCSAVE2 = 110,
+  Xtensa_EXCSAVE3 = 111,
+  Xtensa_EXCSAVE4 = 112,
+  Xtensa_EXCSAVE5 = 113,
+  Xtensa_EXCSAVE6 = 114,
+  Xtensa_EXCSAVE7 = 115,
+  Xtensa_F0 = 116,
+  Xtensa_F1 = 117,
+  Xtensa_F2 = 118,
+  Xtensa_F3 = 119,
+  Xtensa_F4 = 120,
+  Xtensa_F5 = 121,
+  Xtensa_F6 = 122,
+  Xtensa_F7 = 123,
+  Xtensa_F8 = 124,
+  Xtensa_F9 = 125,
+  Xtensa_F10 = 126,
+  Xtensa_F11 = 127,
+  Xtensa_F12 = 128,
+  Xtensa_F13 = 129,
+  Xtensa_F14 = 130,
+  Xtensa_F15 = 131,
+  Xtensa_IBREAKA0 = 132,
+  Xtensa_IBREAKA1 = 133,
+  Xtensa_M0 = 134,
+  Xtensa_M1 = 135,
+  Xtensa_M2 = 136,
+  Xtensa_M3 = 137,
+  Xtensa_MISC0 = 138,
+  Xtensa_MISC1 = 139,
+  Xtensa_MISC2 = 140,
+  Xtensa_MISC3 = 141,
+  Xtensa_Q0 = 142,
+  Xtensa_Q1 = 143,
+  Xtensa_Q2 = 144,
+  Xtensa_Q3 = 145,
+  Xtensa_Q4 = 146,
+  Xtensa_Q5 = 147,
+  Xtensa_Q6 = 148,
+  Xtensa_Q7 = 149,
+  Xtensa_SCOMPARE1 = 150,
+  Xtensa_U0 = 151,
+  Xtensa_U1 = 152,
+  Xtensa_U2 = 153,
+  Xtensa_U3 = 154,
+  Xtensa_F64R_HI = 155,
+  Xtensa_F64R_LO = 156,
+  Xtensa_F64S = 157,
+  Xtensa_B0_B1 = 158,
+  Xtensa_B2_B3 = 159,
+  Xtensa_B4_B5 = 160,
+  Xtensa_B6_B7 = 161,
+  Xtensa_B8_B9 = 162,
+  Xtensa_B10_B11 = 163,
+  Xtensa_B12_B13 = 164,
+  Xtensa_B14_B15 = 165,
+  Xtensa_B0_B1_B2_B3 = 166,
+  Xtensa_B4_B5_B6_B7 = 167,
+  Xtensa_B8_B9_B10_B11 = 168,
+  Xtensa_B12_B13_B14_B15 = 169,
+  NUM_TARGET_REGS // 170
 };
 
 // Register classes
 
 enum {
-  Xtensa_ARRegClassID = 0,
+  Xtensa_BRRegClassID = 0,
-  Xtensa_SRRegClassID = 1,
+  Xtensa_BR2RegClassID = 1,
+  Xtensa_BR4RegClassID = 2,
+  Xtensa_SRRegClassID = 3,
+  Xtensa_ARRegClassID = 4,
+  Xtensa_FPRRegClassID = 5,
+  Xtensa_URRegClassID = 6,
+  Xtensa_MRRegClassID = 7,
+  Xtensa_MR01RegClassID = 8,
+  Xtensa_MR23RegClassID = 9,
+  Xtensa_AE_DRRegClassID = 10,
+  Xtensa_AE_VALIGNRegClassID = 11,
+  Xtensa_QRRegClassID = 12,
 
 };
+
+// Subregister indices
+
+enum {
+  Xtensa_NoSubRegister,
+  Xtensa_bsub0,	// 1
+  Xtensa_bsub1,	// 2
+  Xtensa_bsub2,	// 3
+  Xtensa_bsub3,	// 4
+  Xtensa_NUM_TARGET_SUBREGS
+};
 #endif // GET_REGINFO_ENUM
 
 /* Capstone Disassembly Engine, https://www.capstone-engine.org */
@@ -49,34 +223,251 @@ enum {
 #undef GET_REGINFO_MC_DESC
 
 static const MCPhysReg XtensaRegDiffLists[] = {
-  /* 0 */ 0,
+  /* 0 */ -87, 1, 0,
+  /* 3 */ -86, 1, 0,
+  /* 6 */ -85, 1, 0,
+  /* 9 */ -84, 1, 0,
+  /* 12 */ -83, 1, 0,
+  /* 15 */ -82, 1, 0,
+  /* 18 */ -81, 1, 0,
+  /* 21 */ -80, 1, 0,
+  /* 24 */ -95, 1, 1, 1, 0,
+  /* 29 */ -92, 1, 1, 1, 0,
+  /* 34 */ -89, 1, 1, 1, 0,
+  /* 39 */ -86, 1, 1, 1, 0,
+  /* 44 */ 79, 4, 0,
+  /* 47 */ 80, 4, 0,
+  /* 50 */ 80, 5, 0,
+  /* 53 */ 81, 5, 0,
+  /* 56 */ 82, 5, 0,
+  /* 59 */ 82, 6, 0,
+  /* 62 */ 83, 6, 0,
+  /* 65 */ 84, 6, 0,
+  /* 68 */ 84, 7, 0,
+  /* 71 */ 85, 7, 0,
+  /* 74 */ 86, 7, 0,
+  /* 77 */ 86, 8, 0,
+  /* 80 */ 87, 8, 0,
 };
 
 static const uint16_t XtensaSubRegIdxLists[] = {
-  /* 0 */ 0,
+  /* 0 */ 1, 2, 0,
+  /* 3 */ 1, 2, 3, 4, 0,
 };
 
 static const MCRegisterDesc XtensaRegDesc[] = { // Descriptors
   { 3, 0, 0, 0, 0, 0 },
-  { 54, 0, 0, 0, 0, 0 },
+  { 759, 2, 2, 2, 8192, 8 },
-  { 51, 0, 0, 0, 1, 0 },
+  { 800, 2, 2, 2, 8193, 8 },
-  { 4, 0, 0, 0, 2, 0 },
+  { 917, 2, 2, 2, 8194, 8 },
-  { 15, 0, 0, 0, 3, 0 },
+  { 792, 2, 2, 2, 8195, 8 },
-  { 22, 0, 0, 0, 4, 0 },
+  { 740, 2, 2, 2, 8196, 8 },
-  { 29, 0, 0, 0, 5, 0 },
+  { 865, 2, 2, 2, 8197, 8 },
-  { 36, 0, 0, 0, 6, 0 },
+  { 642, 2, 2, 2, 8198, 8 },
-  { 39, 0, 0, 0, 7, 0 },
+  { 839, 2, 2, 2, 8199, 8 },
-  { 42, 0, 0, 0, 8, 0 },
+  { 697, 2, 2, 2, 8200, 8 },
-  { 45, 0, 0, 0, 9, 0 },
+  { 614, 2, 2, 2, 8201, 8 },
-  { 48, 0, 0, 0, 10, 0 },
+  { 688, 2, 2, 2, 8202, 8 },
-  { 0, 0, 0, 0, 11, 0 },
+  { 834, 2, 2, 2, 8203, 8 },
-  { 7, 0, 0, 0, 12, 0 },
+  { 708, 2, 2, 2, 8204, 8 },
-  { 11, 0, 0, 0, 13, 0 },
+  { 830, 2, 2, 2, 8205, 8 },
-  { 18, 0, 0, 0, 14, 0 },
+  { 745, 2, 2, 2, 8206, 8 },
-  { 25, 0, 0, 0, 15, 0 },
+  { 843, 2, 2, 2, 8207, 8 },
-  { 32, 0, 0, 0, 16, 0 },
+  { 908, 2, 2, 2, 8208, 8 },
+  { 629, 2, 2, 2, 8209, 8 },
+  { 872, 2, 2, 2, 8210, 8 },
+  { 773, 2, 2, 2, 8211, 8 },
+  { 817, 2, 2, 2, 8212, 8 },
+  { 651, 2, 2, 2, 8213, 8 },
+  { 886, 2, 2, 2, 8214, 8 },
+  { 735, 2, 2, 2, 8215, 8 },
+  { 879, 2, 2, 2, 8216, 8 },
+  { 624, 2, 2, 2, 8217, 8 },
+  { 669, 2, 2, 2, 8218, 8 },
+  { 785, 2, 2, 2, 8219, 8 },
+  { 619, 2, 2, 2, 8220, 8 },
+  { 862, 2, 2, 2, 8221, 8 },
+  { 609, 2, 2, 2, 8222, 8 },
+  { 826, 2, 2, 2, 8223, 8 },
+  { 726, 2, 2, 2, 8224, 8 },
+  { 814, 2, 2, 2, 8225, 8 },
+  { 847, 2, 2, 2, 8226, 8 },
+  { 717, 2, 2, 2, 8227, 8 },
+  { 661, 2, 2, 2, 8228, 8 },
+  { 677, 2, 2, 2, 8229, 8 },
+  { 896, 2, 2, 2, 8230, 8 },
+  { 24, 2, 2, 2, 8231, 8 },
+  { 237, 2, 2, 2, 8232, 8 },
+  { 317, 2, 2, 2, 8233, 8 },
+  { 392, 2, 2, 2, 8234, 8 },
+  { 458, 2, 2, 2, 8235, 8 },
+  { 497, 2, 2, 2, 8236, 8 },
+  { 533, 2, 2, 2, 8237, 8 },
+  { 578, 2, 2, 2, 8238, 8 },
+  { 592, 2, 2, 2, 8239, 8 },
+  { 0, 2, 2, 2, 8240, 8 },
+  { 91, 2, 2, 2, 8241, 8 },
+  { 219, 2, 2, 2, 8242, 8 },
+  { 295, 2, 2, 2, 8243, 8 },
+  { 374, 2, 2, 2, 8244, 8 },
+  { 428, 2, 2, 2, 8245, 8 },
+  { 54, 2, 2, 2, 8246, 8 },
+  { 163, 2, 2, 2, 8247, 8 },
+  { 254, 2, 2, 2, 8248, 8 },
+  { 343, 2, 2, 2, 8249, 8 },
+  { 403, 2, 2, 2, 8250, 8 },
+  { 472, 2, 2, 2, 8251, 8 },
+  { 508, 2, 2, 2, 8252, 8 },
+  { 553, 2, 2, 2, 8253, 8 },
+  { 584, 2, 2, 2, 8254, 8 },
+  { 601, 2, 2, 2, 8255, 8 },
+  { 8, 2, 2, 2, 8256, 8 },
+  { 109, 2, 2, 2, 8257, 8 },
+  { 227, 2, 2, 2, 8258, 8 },
+  { 307, 2, 2, 2, 8259, 8 },
+  { 382, 2, 2, 2, 8260, 8 },
+  { 448, 2, 2, 2, 8261, 8 },
+  { 36, 2, 80, 2, 8262, 8 },
+  { 140, 2, 77, 2, 8263, 8 },
+  { 240, 2, 74, 2, 8264, 8 },
+  { 329, 2, 71, 2, 8265, 8 },
+  { 395, 2, 71, 2, 8266, 8 },
+  { 464, 2, 68, 2, 8267, 8 },
+  { 500, 2, 65, 2, 8268, 8 },
+  { 545, 2, 62, 2, 8269, 8 },
+  { 581, 2, 62, 2, 8270, 8 },
+  { 598, 2, 59, 2, 8271, 8 },
+  { 4, 2, 56, 2, 8272, 8 },
+  { 105, 2, 53, 2, 8273, 8 },
+  { 223, 2, 53, 2, 8274, 8 },
+  { 303, 2, 50, 2, 8275, 8 },
+  { 378, 2, 47, 2, 8276, 8 },
+  { 444, 2, 44, 2, 8277, 8 },
+  { 69, 2, 2, 2, 8278, 8 },
+  { 178, 2, 2, 2, 8279, 8 },
+  { 259, 2, 2, 2, 8280, 8 },
+  { 59, 2, 2, 2, 8281, 8 },
+  { 168, 2, 2, 2, 8282, 8 },
+  { 18, 2, 2, 2, 8283, 8 },
+  { 119, 2, 2, 2, 8284, 8 },
+  { 39, 2, 2, 2, 8285, 8 },
+  { 143, 2, 2, 2, 8286, 8 },
+  { 152, 2, 2, 2, 8287, 8 },
+  { 243, 2, 2, 2, 8288, 8 },
+  { 332, 2, 2, 2, 8289, 8 },
+  { 398, 2, 2, 2, 8290, 8 },
+  { 467, 2, 2, 2, 8291, 8 },
+  { 503, 2, 2, 2, 8292, 8 },
+  { 548, 2, 2, 2, 8293, 8 },
+  { 287, 2, 2, 2, 8294, 8 },
+  { 366, 2, 2, 2, 8295, 8 },
+  { 423, 2, 2, 2, 8296, 8 },
+  { 492, 2, 2, 2, 8297, 8 },
+  { 528, 2, 2, 2, 8298, 8 },
+  { 573, 2, 2, 2, 8299, 8 },
+  { 198, 2, 2, 2, 8300, 8 },
+  { 269, 2, 2, 2, 8301, 8 },
+  { 348, 2, 2, 2, 8302, 8 },
+  { 408, 2, 2, 2, 8303, 8 },
+  { 477, 2, 2, 2, 8304, 8 },
+  { 513, 2, 2, 2, 8305, 8 },
+  { 558, 2, 2, 2, 8306, 8 },
+  { 79, 2, 2, 2, 8307, 8 },
+  { 207, 2, 2, 2, 8308, 8 },
+  { 278, 2, 2, 2, 8309, 8 },
+  { 357, 2, 2, 2, 8310, 8 },
+  { 417, 2, 2, 2, 8311, 8 },
+  { 486, 2, 2, 2, 8312, 8 },
+  { 522, 2, 2, 2, 8313, 8 },
+  { 567, 2, 2, 2, 8314, 8 },
+  { 589, 2, 2, 2, 8315, 8 },
+  { 606, 2, 2, 2, 8316, 8 },
+  { 14, 2, 2, 2, 8317, 8 },
+  { 115, 2, 2, 2, 8318, 8 },
+  { 233, 2, 2, 2, 8319, 8 },
+  { 313, 2, 2, 2, 8320, 8 },
+  { 388, 2, 2, 2, 8321, 8 },
+  { 454, 2, 2, 2, 8322, 8 },
+  { 27, 2, 2, 2, 8323, 8 },
+  { 128, 2, 2, 2, 8324, 8 },
+  { 82, 2, 2, 2, 8325, 8 },
+  { 210, 2, 2, 2, 8326, 8 },
+  { 281, 2, 2, 2, 8327, 8 },
+  { 360, 2, 2, 2, 8328, 8 },
+  { 48, 2, 2, 2, 8329, 8 },
+  { 157, 2, 2, 2, 8330, 8 },
+  { 248, 2, 2, 2, 8331, 8 },
+  { 337, 2, 2, 2, 8332, 8 },
+  { 85, 2, 2, 2, 8333, 8 },
+  { 213, 2, 2, 2, 8334, 8 },
+  { 284, 2, 2, 2, 8335, 8 },
+  { 363, 2, 2, 2, 8336, 8 },
+  { 420, 2, 2, 2, 8337, 8 },
+  { 489, 2, 2, 2, 8338, 8 },
+  { 525, 2, 2, 2, 8339, 8 },
+  { 570, 2, 2, 2, 8340, 8 },
+  { 188, 2, 2, 2, 8341, 8 },
+  { 88, 2, 2, 2, 8342, 8 },
+  { 216, 2, 2, 2, 8343, 8 },
+  { 292, 2, 2, 2, 8344, 8 },
+  { 371, 2, 2, 2, 8345, 8 },
+  { 765, 2, 2, 2, 8346, 8 },
+  { 806, 2, 2, 2, 8347, 8 },
+  { 857, 2, 2, 2, 8348, 8 },
+  { 137, 0, 2, 0, 4166, 0 },
+  { 326, 3, 2, 0, 4168, 0 },
+  { 461, 6, 2, 0, 4170, 0 },
+  { 542, 9, 2, 0, 4172, 0 },
+  { 595, 12, 2, 0, 4174, 0 },
+  { 101, 15, 2, 0, 4176, 0 },
+  { 299, 18, 2, 0, 4178, 0 },
+  { 440, 21, 2, 0, 4180, 0 },
+  { 320, 24, 2, 3, 102470, 3 },
+  { 536, 29, 2, 3, 102474, 3 },
+  { 95, 34, 2, 3, 102478, 3 },
+  { 432, 39, 2, 3, 102482, 3 },
 };
 
+  // BR Register Class...
+  static const MCPhysReg BR[] = {
+    Xtensa_B0, Xtensa_B1, Xtensa_B2, Xtensa_B3, Xtensa_B4, Xtensa_B5, Xtensa_B6, Xtensa_B7, Xtensa_B8, Xtensa_B9, Xtensa_B10, Xtensa_B11, Xtensa_B12, Xtensa_B13, Xtensa_B14, Xtensa_B15, 
+  };
+
+  // BR Bit set.
+  static const uint8_t BRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
+  };
+
+  // BR2 Register Class...
+  static const MCPhysReg BR2[] = {
+    Xtensa_B0_B1, Xtensa_B2_B3, Xtensa_B4_B5, Xtensa_B6_B7, Xtensa_B8_B9, Xtensa_B10_B11, Xtensa_B12_B13, Xtensa_B14_B15, 
+  };
+
+  // BR2 Bit set.
+  static const uint8_t BR2Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
+  };
+
+  // BR4 Register Class...
+  static const MCPhysReg BR4[] = {
+    Xtensa_B0_B1_B2_B3, Xtensa_B4_B5_B6_B7, Xtensa_B8_B9_B10_B11, Xtensa_B12_B13_B14_B15, 
+  };
+
+  // BR4 Bit set.
+  static const uint8_t BR4Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
+  };
+
+  // SR Register Class...
+  static const MCPhysReg SR[] = {
+    Xtensa_LBEG, Xtensa_LEND, Xtensa_LCOUNT, Xtensa_SAR, Xtensa_BREG, Xtensa_LITBASE, Xtensa_SCOMPARE1, Xtensa_ACCLO, Xtensa_ACCHI, Xtensa_M0, Xtensa_M1, Xtensa_M2, Xtensa_M3, Xtensa_WINDOWBASE, Xtensa_WINDOWSTART, Xtensa_IBREAKENABLE, Xtensa_MEMCTL, Xtensa_ATOMCTL, Xtensa_DDR, Xtensa_IBREAKA0, Xtensa_IBREAKA1, Xtensa_DBREAKA0, Xtensa_DBREAKA1, Xtensa_DBREAKC0, Xtensa_DBREAKC1, Xtensa_CONFIGID0, Xtensa_EPC1, Xtensa_EPC2, Xtensa_EPC3, Xtensa_EPC4, Xtensa_EPC5, Xtensa_EPC6, Xtensa_EPC7, Xtensa_DEPC, Xtensa_EPS2, Xtensa_EPS3, Xtensa_EPS4, Xtensa_EPS5, Xtensa_EPS6, Xtensa_EPS7, Xtensa_CONFIGID1, Xtensa_EXCSAVE1, Xtensa_EXCSAVE2, Xtensa_EXCSAVE3, Xtensa_EXCSAVE4, Xtensa_EXCSAVE5, Xtensa_EXCSAVE6, Xtensa_EXCSAVE7, Xtensa_CPENABLE, Xtensa_INTERRUPT, Xtensa_INTCLEAR, Xtensa_INTENABLE, Xtensa_PS, Xtensa_VECBASE, Xtensa_EXCCAUSE, Xtensa_DEBUGCAUSE, Xtensa_CCOUNT, Xtensa_PRID, Xtensa_ICOUNT, Xtensa_ICOUNTLEVEL, Xtensa_EXCVADDR, Xtensa_CCOMPARE0, Xtensa_CCOMPARE1, Xtensa_CCOMPARE2, Xtensa_MISC0, Xtensa_MISC1, Xtensa_MISC2, Xtensa_MISC3, 
+  };
+
+  // SR Bit set.
+  static const uint8_t SRBits[] = {
+    0xf6, 0x1f, 0xfc, 0x7f, 0xe1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0x3f, 0x40, 
+  };
+
   // AR Register Class...
   static const MCPhysReg AR[] = {
     Xtensa_A8, Xtensa_A9, Xtensa_A10, Xtensa_A11, Xtensa_A12, Xtensa_A13, Xtensa_A14, Xtensa_A15, Xtensa_A7, Xtensa_A6, Xtensa_A5, Xtensa_A4, Xtensa_A3, Xtensa_A2, Xtensa_A0, Xtensa_SP, 
@@ -84,28 +475,146 @@ static const MCRegisterDesc XtensaRegDesc[] = { // Descriptors
 
   // AR Bit set.
   static const uint8_t ARBits[] = {
-    0xfc, 0xff, 0x03, 
+    0x00, 0x00, 0x00, 0x00, 0x04, 0xff, 0x7f, 
   };
 
-  // SR Register Class...
+  // FPR Register Class...
-  static const MCPhysReg SR[] = {
+  static const MCPhysReg FPR[] = {
-    Xtensa_SAR, 
+    Xtensa_F8, Xtensa_F9, Xtensa_F10, Xtensa_F11, Xtensa_F12, Xtensa_F13, Xtensa_F14, Xtensa_F15, Xtensa_F7, Xtensa_F6, Xtensa_F5, Xtensa_F4, Xtensa_F3, Xtensa_F2, Xtensa_F1, Xtensa_F0, 
   };
 
-  // SR Bit set.
+  // FPR Bit set.
-  static const uint8_t SRBits[] = {
+  static const uint8_t FPRBits[] = {
-    0x02, 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
+  };
+
+  // UR Register Class...
+  static const MCPhysReg UR[] = {
+    Xtensa_GPIO_OUT, Xtensa_EXPSTATE, Xtensa_THREADPTR, Xtensa_FCR, Xtensa_FSR, Xtensa_F64R_LO, Xtensa_F64R_HI, Xtensa_F64S, Xtensa_ACCX, Xtensa_QACC, Xtensa_FFT_BIT_WIDTH, Xtensa_SAR_BYTE, Xtensa_UA_STATE, 
+  };
+
+  // UR Bit set.
+  static const uint8_t URBits[] = {
+    0x08, 0xe0, 0x03, 0x80, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
+  };
+
+  // MR Register Class...
+  static const MCPhysReg MR[] = {
+    Xtensa_M0, Xtensa_M1, Xtensa_M2, Xtensa_M3, 
+  };
+
+  // MR Bit set.
+  static const uint8_t MRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 
+  };
+
+  // MR01 Register Class...
+  static const MCPhysReg MR01[] = {
+    Xtensa_M0, Xtensa_M1, 
+  };
+
+  // MR01 Bit set.
+  static const uint8_t MR01Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 
+  };
+
+  // MR23 Register Class...
+  static const MCPhysReg MR23[] = {
+    Xtensa_M2, Xtensa_M3, 
+  };
+
+  // MR23 Bit set.
+  static const uint8_t MR23Bits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 
+  };
+
+  // AE_DR Register Class...
+  static const MCPhysReg AE_DR[] = {
+    Xtensa_AED0, Xtensa_AED1, Xtensa_AED2, Xtensa_AED3, Xtensa_AED4, Xtensa_AED5, Xtensa_AED6, Xtensa_AED7, Xtensa_AED8, Xtensa_AED9, Xtensa_AED10, Xtensa_AED11, Xtensa_AED12, Xtensa_AED13, Xtensa_AED14, Xtensa_AED15, 
+  };
+
+  // AE_DR Bit set.
+  static const uint8_t AE_DRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
+  };
+
+  // AE_VALIGN Register Class...
+  static const MCPhysReg AE_VALIGN[] = {
+    Xtensa_U0, Xtensa_U1, Xtensa_U2, Xtensa_U3, 
+  };
+
+  // AE_VALIGN Bit set.
+  static const uint8_t AE_VALIGNBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, 
+  };
+
+  // QR Register Class...
+  static const MCPhysReg QR[] = {
+    Xtensa_Q0, Xtensa_Q1, Xtensa_Q2, Xtensa_Q3, Xtensa_Q4, Xtensa_Q5, Xtensa_Q6, Xtensa_Q7, 
+  };
+
+  // QR Bit set.
+  static const uint8_t QRBits[] = {
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
   };
 
 static const MCRegisterClass XtensaMCRegisterClasses[] = {
-  { AR, ARBits, sizeof(ARBits) },
+  { BR, BRBits, sizeof(BRBits) },
+  { BR2, BR2Bits, sizeof(BR2Bits) },
+  { BR4, BR4Bits, sizeof(BR4Bits) },
   { SR, SRBits, sizeof(SRBits) },
+  { AR, ARBits, sizeof(ARBits) },
+  { FPR, FPRBits, sizeof(FPRBits) },
+  { UR, URBits, sizeof(URBits) },
+  { MR, MRBits, sizeof(MRBits) },
+  { MR01, MR01Bits, sizeof(MR01Bits) },
+  { MR23, MR23Bits, sizeof(MR23Bits) },
+  { AE_DR, AE_DRBits, sizeof(AE_DRBits) },
+  { AE_VALIGN, AE_VALIGNBits, sizeof(AE_VALIGNBits) },
+  { QR, QRBits, sizeof(QRBits) },
 };
 
 static const uint16_t XtensaRegEncodingTable[] = {
   0,
-  3,
+  17,
+  16,
+  237,
+  99,
+  4,
+  234,
+  224,
+  104,
+  233,
+  192,
+  232,
+  238,
+  230,
+  232,
+  239,
+  233,
+  0,
+  96,
+  236,
+  237,
+  227,
+  228,
+  226,
+  0,
+  2,
   1,
+  5,
+  97,
+  235,
+  230,
+  238,
+  3,
+  240,
+  1,
+  231,
+  241,
+  231,
+  72,
+  73,
   0,
   2,
   3,
@@ -121,6 +630,121 @@ static const uint16_t XtensaRegEncodingTable[] = {
   13,
   14,
   15,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  240,
+  241,
+  242,
+  176,
+  208,
+  144,
+  145,
+  160,
+  161,
+  177,
+  178,
+  179,
+  180,
+  181,
+  182,
+  183,
+  194,
+  195,
+  196,
+  197,
+  198,
+  199,
+  209,
+  210,
+  211,
+  212,
+  213,
+  214,
+  215,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  8,
+  9,
+  10,
+  11,
+  12,
+  13,
+  14,
+  15,
+  128,
+  129,
+  32,
+  33,
+  34,
+  35,
+  244,
+  245,
+  246,
+  247,
+  0,
+  1,
+  2,
+  3,
+  4,
+  5,
+  6,
+  7,
+  12,
+  0,
+  1,
+  2,
+  3,
+  235,
+  234,
+  236,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
+  0,
 };
 #endif // GET_REGINFO_MC_DESC
 

arch/Xtensa/XtensaGenSubtargetInfo.inc

@@ -15,8 +15,41 @@
 #undef GET_SUBTARGETINFO_ENUM
 
 enum {
-  Xtensa_FeatureDensity = 0,
+  Xtensa_FeatureATOMCTL = 0,
-  Xtensa_NumSubtargetFeatures = 1
+  Xtensa_FeatureBoolean = 1,
+  Xtensa_FeatureCLAMPS = 2,
+  Xtensa_FeatureCoprocessor = 3,
+  Xtensa_FeatureDFPAccel = 4,
+  Xtensa_FeatureDebug = 5,
+  Xtensa_FeatureDensity = 6,
+  Xtensa_FeatureDiv32 = 7,
+  Xtensa_FeatureESP32S2Ops = 8,
+  Xtensa_FeatureESP32S3Ops = 9,
+  Xtensa_FeatureException = 10,
+  Xtensa_FeatureExtendedL32R = 11,
+  Xtensa_FeatureForcedAtomics = 12,
+  Xtensa_FeatureHIFI3 = 13,
+  Xtensa_FeatureHighPriInterrupts = 14,
+  Xtensa_FeatureInterrupt = 15,
+  Xtensa_FeatureLoop = 16,
+  Xtensa_FeatureMAC16 = 17,
+  Xtensa_FeatureMEMCTL = 18,
+  Xtensa_FeatureMINMAX = 19,
+  Xtensa_FeatureMiscSR = 20,
+  Xtensa_FeatureMul16 = 21,
+  Xtensa_FeatureMul32 = 22,
+  Xtensa_FeatureMul32High = 23,
+  Xtensa_FeatureNSA = 24,
+  Xtensa_FeaturePRID = 25,
+  Xtensa_FeatureRegionProtection = 26,
+  Xtensa_FeatureRelocatableVector = 27,
+  Xtensa_FeatureS32C1I = 28,
+  Xtensa_FeatureSEXT = 29,
+  Xtensa_FeatureSingleFloat = 30,
+  Xtensa_FeatureTHREADPTR = 31,
+  Xtensa_FeatureTimerInt = 32,
+  Xtensa_FeatureWindowed = 33,
+  Xtensa_NumSubtargetFeatures = 34
 };
 #endif // GET_SUBTARGETINFO_ENUM
 

arch/Xtensa/XtensaInstPrinter.c

@@ -35,6 +35,7 @@
 #include "../../SStream.h"
 #include "./priv.h"
 #include "../../Mapping.h"
+
 #include "XtensaMapping.h"
 #include "../../MathExtras.h"
 
@@ -45,32 +46,43 @@
 static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O);
 static const char *getRegisterName(unsigned RegNo);
 
-static void printOperand(MCInst *MI, int OpNum, SStream *O)
+typedef MCRegister Register;
+
+static void printRegName(SStream *O, MCRegister Reg)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_OPERAND, OpNum);
+	SStream_concat0(O, getRegisterName(Reg));
-	const MCOperand *MC = MCInst_getOperand(MI, (OpNum));
+}
-	if (MCOperand_isReg(MC)) {
+
+static void printOp(MCInst *MI, MCOperand *MC, SStream *O)
+{
+	if (MCOperand_isReg(MC))
 		SStream_concat0(O, getRegisterName(MCOperand_getReg(MC)));
-	} else if (MCOperand_isImm(MC)) {
+	else if (MCOperand_isImm(MC))
 		printInt64(O, MCOperand_getImm(MC));
-	} else if (MCOperand_isExpr(MC)) {
+	else if (MCOperand_isExpr(MC))
 		printExpr(MCOperand_getExpr(MC), O);
-	} else
+	else
 		CS_ASSERT("Invalid operand");
 }
 
+static void printOperand(MCInst *MI, const int op_num, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Operand, op_num);
+	printOp(MI, MCInst_getOperand(MI, op_num), O);
+}
+
 static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_MEMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_MemOperand, OpNum);
 	SStream_concat0(OS, getRegisterName(MCOperand_getReg(
 				    MCInst_getOperand(MI, (OpNum)))));
 	SStream_concat0(OS, ", ");
-	printInt64(OS, MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)));
+	printOp(MI, MCInst_getOperand(MI, OpNum + 1), OS);
 }
 
 static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_BRANCHTARGET, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_BranchTarget, OpNum);
 	MCOperand *MC = MCInst_getOperand(MI, (OpNum));
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Val = MCOperand_getImm(MC) + 4;
@@ -80,14 +92,31 @@ static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
 
 		printInt64(OS, Val);
 	} else if (MCOperand_isExpr(MC))
-		MCExpr_print(MCOperand_getExpr(MC), O, NULL, true);
+		CS_ASSERT_RET(0 && "unimplemented expr printing");
+	else
+		CS_ASSERT(0 && "Invalid operand");
+}
+
+static inline void printLoopTarget(MCInst *MI, int OpNum, SStream *OS)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_LoopTarget, OpNum);
+	MCOperand *MC = MCInst_getOperand(MI, (OpNum));
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Val = MCOperand_getImm(MC) + 4;
+		SStream_concat0(OS, ". ");
+		if (Val > 0)
+			SStream_concat0(OS, "+");
+
+		printInt64(OS, Val);
+	} else if (MCOperand_isExpr(MC))
+		CS_ASSERT_RET(0 && "unimplemented expr printing");
 	else
 		CS_ASSERT(0 && "Invalid operand");
 }
 
 static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_JUMPTARGET, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_JumpTarget, OpNum);
 	MCOperand *MC = MCInst_getOperand(MI, (OpNum));
 	if (MCOperand_isImm(MC)) {
 		int64_t Val = MCOperand_getImm(MC) + 4;
@@ -97,15 +126,15 @@ static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
 
 		printInt64(OS, Val);
 	} else if (MCOperand_isExpr(MC))
-		MCExpr_print(MCOperand_getExpr(MC), O, NULL, true);
+		CS_ASSERT_RET(0 && "unimplemented expr printing");
 	else
-		assert(0 && "Invalid operand");
+		CS_ASSERT(0 && "Invalid operand");
 	;
 }
 
 static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_CALLOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_CallOperand, OpNum);
 	MCOperand *MC = MCInst_getOperand(MI, (OpNum));
 	if (MCOperand_isImm(MC)) {
 		int64_t Val = MCOperand_getImm(MC) + 4;
@@ -115,38 +144,27 @@ static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
 
 		printInt64(OS, Val);
 	} else if (MCOperand_isExpr(MC))
-		MCExpr_print(MCOperand_getExpr(MC), O, NULL, true);
+		CS_ASSERT_RET(0 && "unimplemented expr printing");
 	else
-		assert(0 && "Invalid operand");
+		CS_ASSERT(0 && "Invalid operand");
 }
 
 static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_L32RTARGET, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_L32RTarget, OpNum);
 	MCOperand *MC = MCInst_getOperand(MI, (OpNum));
 	if (MCOperand_isImm(MC)) {
-		int64_t Value =
-			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
-		int32_t InstrOff = (uint32_t)OneExtend32(Value, 16) << 2;
-		CS_ASSERT(
-			(InstrOff >= -262144 && InstrOff <= -4) &&
-			"Invalid argument, value must be in ranges [-262144,-4]");
 		SStream_concat0(O, ". ");
-		if (MI->csh->LITBASE & 0x1) {
+		printInt64(O, Xtensa_L32R_Value(MI, OpNum));
-			Value = ((MI->csh->LITBASE & 0xfffff000) >> 12) + InstrOff;
-		} else {
-			Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff;
-		}
-		printInt64(O, Value);
 	} else if (MCOperand_isExpr(MC))
-		MCExpr_print(MCOperand_getExpr(MC), O, NULL, true);
+		CS_ASSERT_RET(0 && "unimplemented expr printing");
 	else
-		assert(0 && "Invalid operand");
+		CS_ASSERT(0 && "Invalid operand");
 }
 
 static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -161,7 +179,7 @@ static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 
 static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_sh8_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -174,9 +192,23 @@ static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 		printOperand(MI, OpNum, O);
 }
 
+static inline void printImm12_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -2048 && Value <= 2047) &&
+			"Invalid argument, value must be in ranges [-2048,2047]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
 static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_IMM12M_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12m_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -190,7 +222,7 @@ static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 
 static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_UIMM4_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm4_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -202,7 +234,7 @@ static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 
 static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_UIMM5_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm5_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -214,7 +246,7 @@ static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 
 static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm1_31_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -225,9 +257,22 @@ static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 		printOperand(MI, OpNum, O);
 }
 
+static inline void printShimm0_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm0_31_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 31) &&
+			  "Invalid argument, value must be in range [0,31]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
 static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_IMM1_16_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1_16_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -238,9 +283,95 @@ static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 		printOperand(MI, OpNum, O);
 }
 
+static inline void printImm1n_15_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1n_15_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -1 && (Value != 0) && Value <= 15) &&
+			"Invalid argument, value must be in ranges <-1,-1> or <1,15>");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printImm32n_95_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm32n_95_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= -32 && Value <= 95) &&
+			  "Invalid argument, value must be in ranges <-32,95>");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printImm8n_7_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8n_7_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= -8 && Value <= 7) &&
+			  "Invalid argument, value must be in ranges <-8,7>");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printImm64n_4n_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm64n_4n_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= -64 && Value <= -4) &
+				  ((Value & 0x3) == 0) &&
+			  "Invalid argument, value must be in ranges <-64,-4>");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printOffset8m32_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset8m32_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= 0 && Value <= 1020 && ((Value & 0x3) == 0)) &&
+			"Invalid argument, value must be multiples of four in range [0,1020]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printEntry_Imm12_AsmOperand(MCInst *MI, int OpNum,
+					       SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Entry_Imm12_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= 0 && Value <= 32760) &&
+			"Invalid argument, value must be multiples of eight in range "
+			"<0,32760>");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
 static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_B4CONST_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4const_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -273,7 +404,7 @@ static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 
 static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 {
-	add_cs_detail(MI, XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND, OpNum);
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4constu_AsmOperand, OpNum);
 	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
 		int64_t Value =
 			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
@@ -304,14 +435,266 @@ static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
 		printOperand(MI, OpNum, O);
 }
 
+static inline void printImm7_22_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm7_22_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 7 && Value <= 22) &&
+			  "Invalid argument, value must be in range <7,22>");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printSelect_2_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_2_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 1) &&
+			  "Invalid argument, value must be in range [0,1]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printSelect_4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_4_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 3) &&
+			  "Invalid argument, value must be in range [0,3]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printSelect_8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_8_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 7) &&
+			  "Invalid argument, value must be in range [0,7]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printSelect_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_16_AsmOperand, OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 15) &&
+			  "Invalid argument, value must be in range [0,15]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printSelect_256_AsmOperand(MCInst *MI, int OpNum, SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_256_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 255) &&
+			  "Invalid argument, value must be in range [0,255]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printOffset_16_16_AsmOperand(MCInst *MI, int OpNum,
+						SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_16_16_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -128 && Value <= 112 && (Value & 0xf) == 0) &&
+			"Invalid argument, value must be in range [-128,112], first 4 bits "
+			"should be zero");
+		printInt64(O, Value);
+	} else {
+		printOperand(MI, OpNum, O);
+	}
+}
+
+static inline void printOffset_256_8_AsmOperand(MCInst *MI, int OpNum,
+						SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_8_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -1024 && Value <= 1016 &&
+			 (Value & 0x7) == 0) &&
+			"Invalid argument, value must be in range [-1024,1016], first 3 "
+			"bits should be zero");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printOffset_256_16_AsmOperand(MCInst *MI, int OpNum,
+						 SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_16_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -2048 && Value <= 2032 &&
+			 (Value & 0xf) == 0) &&
+			"Invalid argument, value must be in range [-2048,2032], first 4 "
+			"bits should be zero");
+		printInt64(O, Value);
+	} else {
+		printOperand(MI, OpNum, O);
+	}
+}
+
+static inline void printOffset_256_4_AsmOperand(MCInst *MI, int OpNum,
+						SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_4_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -512 && Value <= 508 && (Value & 0x3) == 0) &&
+			"Invalid argument, value must be in range [-512,508], first 2 bits "
+			"should be zero");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printOffset_128_2_AsmOperand(MCInst *MI, int OpNum,
+						SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_2_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= 0 && Value <= 254 && (Value & 0x1) == 0) &&
+			"Invalid argument, value must be in range [0,254], first bit should "
+			"be zero");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printOffset_128_1_AsmOperand(MCInst *MI, int OpNum,
+						SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_1_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT((Value >= 0 && Value <= 127) &&
+			  "Invalid argument, value must be in range [0,127]");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+static inline void printOffset_64_16_AsmOperand(MCInst *MI, int OpNum,
+						SStream *O)
+{
+	Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_64_16_AsmOperand,
+			       OpNum);
+	if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
+		int64_t Value =
+			MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
+		CS_ASSERT(
+			(Value >= -512 && Value <= 496 && (Value & 0xf) == 0) &&
+			"Invalid argument, value must be in range [-512,496], first 4 bits "
+			"should be zero");
+		printInt64(O, Value);
+	} else
+		printOperand(MI, OpNum, O);
+}
+
+#define IMPL_printImmOperand(N, L, H, S) \
+	static void printImmOperand_##N(MCInst *MI, int OpNum, SStream *O) \
+	{ \
+		Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_ImmOperand_##N, \
+				       OpNum); \
+		MCOperand *MC = MCInst_getOperand(MI, (OpNum)); \
+		if (MCOperand_isImm(MC)) { \
+			int64_t Value = MCOperand_getImm(MC); \
+			CS_ASSERT((Value >= L && Value <= H && \
+				   ((Value % S) == 0)) && \
+				  "Invalid argument"); \
+			printInt64(O, Value); \
+		} else { \
+			printOperand(MI, OpNum, O); \
+		} \
+	}
+
+IMPL_printImmOperand(minus64_56_8, -64, 56, 8);
+IMPL_printImmOperand(minus32_28_4, -32, 28, 4);
+IMPL_printImmOperand(minus16_47_1, -16, 47, 1);
+IMPL_printImmOperand(minus16_14_2, -16, 14, 2);
+IMPL_printImmOperand(0_56_8, 0, 56, 8);
+IMPL_printImmOperand(0_3_1, 0, 3, 1);
+IMPL_printImmOperand(0_63_1, 0, 63, 1);
+
 #include "XtensaGenAsmWriter.inc"
 
+static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
+		      SStream *O)
+{
+	unsigned Opcode = MCInst_getOpcode(MI);
+
+	switch (Opcode) {
+	case Xtensa_WSR: {
+		// INTERRUPT mnemonic is read-only, so use INTSET mnemonic instead
+		Register SR = MCOperand_getReg(MCInst_getOperand(MI, (0)));
+		if (SR == Xtensa_INTERRUPT) {
+			Register Reg =
+				MCOperand_getReg(MCInst_getOperand(MI, (1)));
+			SStream_concat1(O, '\t');
+			SStream_concat(O, "%s", "wsr");
+			SStream_concat0(O, "\t");
+
+			printRegName(O, Reg);
+			SStream_concat(O, "%s", ", ");
+			SStream_concat0(O, "intset");
+			;
+			return;
+		}
+	}
+	}
+	printInstruction(MI, Address, O);
+}
+
+void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O)
+{
+	printInst(MI, Address, NULL, O);
+}
+
 const char *Xtensa_LLVM_getRegisterName(unsigned RegNo)
 {
 	return getRegisterName(RegNo);
 }
-
-void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O)
-{
-	printInstruction(MI, Address, O);
-}

arch/Xtensa/XtensaMapping.c

@@ -59,6 +59,12 @@ static void set_instr_map_data(MCInst *MI)
 	map_implicit_reads(MI, mapping_insns);
 	map_implicit_writes(MI, mapping_insns);
 	map_groups(MI, mapping_insns);
+
+	const xtensa_suppl_info *suppl_info =
+		map_get_suppl_info(MI, mapping_insns);
+	if (suppl_info) {
+		Xtensa_get_detail(MI)->format = suppl_info->form;
+	}
 #endif
 }
 
@@ -162,12 +168,29 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,
 }
 #endif
 
-void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args)
+int64_t Xtensa_L32R_Value(MCInst *MI, int op_num)
 {
-	int op_num = va_arg(args, int);
+	int64_t InstrOff = MCOperand_getImm(MCInst_getOperand(MI, (op_num)));
+	CS_ASSERT((InstrOff >= -262144 && InstrOff <= -4) &&
+		  "Invalid argument, value must be in ranges [-262144,-4]");
+	int64_t Value = 0;
+	if (MI->csh->LITBASE & 0x1) {
+		Value = (MI->csh->LITBASE & 0xfffff000) + InstrOff;
+	} else {
+		Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff;
+	}
+	return Value;
+}
+
+void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num)
+{
+	if (!detail_is_set(MI)) {
+		return;
+	}
+
 	cs_xtensa_op *xop = Xtensa_get_detail_op(MI, 0);
 	switch (op_group) {
-	case XTENSA_OP_GROUP_OPERAND: {
+	case Xtensa_OP_GROUP_Operand: {
 		const MCOperand *MC = MCInst_getOperand(MI, op_num);
 		if (MCOperand_isReg(MC)) {
 			xop->type = XTENSA_OP_REG;
@@ -177,50 +200,68 @@ void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args)
 			xop->imm = MC->ImmVal;
 		}
 	} break;
-	case XTENSA_OP_GROUP_IMM8_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm1_16_AsmOperand:
-	case XTENSA_OP_GROUP_IMM8_SH8_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm1n_15_AsmOperand:
-	case XTENSA_OP_GROUP_UIMM5_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm7_22_AsmOperand:
-	case XTENSA_OP_GROUP_B4CONST_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm8_AsmOperand:
-	case XTENSA_OP_GROUP_B4CONSTU_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm8_sh8_AsmOperand:
-	case XTENSA_OP_GROUP_IMM1_16_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm8n_7_AsmOperand:
-	case XTENSA_OP_GROUP_IMM12M_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm12_AsmOperand:
-	case XTENSA_OP_GROUP_SHIMM1_31_ASMOPERAND:
+	case Xtensa_OP_GROUP_Imm12m_AsmOperand:
-	case XTENSA_OP_GROUP_UIMM4_ASMOPERAND: {
+	case Xtensa_OP_GROUP_Imm32n_95_AsmOperand:
+	case Xtensa_OP_GROUP_Imm64n_4n_AsmOperand:
+	case Xtensa_OP_GROUP_ImmOperand_minus32_28_4:
+	case Xtensa_OP_GROUP_Uimm5_AsmOperand:
+	case Xtensa_OP_GROUP_Uimm4_AsmOperand:
+	case Xtensa_OP_GROUP_Shimm0_31_AsmOperand:
+	case Xtensa_OP_GROUP_Shimm1_31_AsmOperand:
+	case Xtensa_OP_GROUP_B4const_AsmOperand:
+	case Xtensa_OP_GROUP_B4constu_AsmOperand:
+	case Xtensa_OP_GROUP_ImmOperand_minus16_14_2:
+	case Xtensa_OP_GROUP_ImmOperand_minus64_56_8:
+	case Xtensa_OP_GROUP_ImmOperand_0_56_8:
+	case Xtensa_OP_GROUP_ImmOperand_minus16_47_1:
+	case Xtensa_OP_GROUP_ImmOperand_0_3_1:
+	case Xtensa_OP_GROUP_ImmOperand_0_63_1:
+	case Xtensa_OP_GROUP_Entry_Imm12_AsmOperand:
+	case Xtensa_OP_GROUP_Offset8m32_AsmOperand:
+	case Xtensa_OP_GROUP_Select_4_AsmOperand:
+	case Xtensa_OP_GROUP_Select_2_AsmOperand:
+	case Xtensa_OP_GROUP_Select_8_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_16_16_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_256_8_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_256_16_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_256_4_AsmOperand:
+	case Xtensa_OP_GROUP_Select_16_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_128_2_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_128_1_AsmOperand:
+	case Xtensa_OP_GROUP_Offset_64_16_AsmOperand:
+	case Xtensa_OP_GROUP_Select_256_AsmOperand: {
 		int64_t val = MCOperand_getImm(MCInst_getOperand(MI, op_num));
 		xop->type = XTENSA_OP_IMM;
 		xop->imm = (int32_t)val;
 	} break;
-	case XTENSA_OP_GROUP_BRANCHTARGET:
+	case Xtensa_OP_GROUP_BranchTarget:
-	case XTENSA_OP_GROUP_JUMPTARGET:
+	case Xtensa_OP_GROUP_JumpTarget:
-	case XTENSA_OP_GROUP_CALLOPERAND: {
+	case Xtensa_OP_GROUP_CallOperand:
+	case Xtensa_OP_GROUP_LoopTarget: {
 		int64_t val =
 			MCOperand_getImm(MCInst_getOperand(MI, op_num)) + 4;
 		xop->type = XTENSA_OP_IMM;
 		xop->imm = (int32_t)val;
 	} break;
-	case XTENSA_OP_GROUP_L32RTARGET: {
+	case Xtensa_OP_GROUP_L32RTarget: {
-		int64_t Value =
-			MCOperand_getImm(MCInst_getOperand(MI, (op_num)));
-		int32_t InstrOff = (uint32_t)OneExtend32(Value, 16) << 2;
-		CS_ASSERT(
-			(InstrOff >= -262144 && InstrOff <= -4) &&
-			"Invalid argument, value must be in ranges [-262144,-4]");
-		if (MI->csh->LITBASE & 0x1) {
-			Value = ((MI->csh->LITBASE & 0xfffff000) >> 12) + InstrOff;
-		} else {
-			Value = (((int64_t)MI->address + 3) & ~0x3) + InstrOff;
-		}
 		xop->type = XTENSA_OP_L32R;
-		xop->imm = (int32_t)Value;
+		xop->imm = (int32_t)Xtensa_L32R_Value(MI, op_num);
 	} break;
-	case XTENSA_OP_GROUP_MEMOPERAND: {
+	case Xtensa_OP_GROUP_MemOperand: {
 		unsigned reg =
 			MCOperand_getReg(MCInst_getOperand(MI, (op_num)));
 		int64_t imm8 =
 			MCOperand_getImm(MCInst_getOperand(MI, op_num + 1));
 		xop->type = XTENSA_OP_MEM;
 		xop->mem.base = reg;
-		xop->mem.disp = (uint8_t)imm8;
+		xop->mem.disp = (int32_t)imm8;
 	} break;
 	}
 

arch/Xtensa/XtensaMapping.h

@@ -10,6 +10,8 @@ typedef enum {
 #include "XtensaGenCSOpGroup.inc"
 } xtensa_op_group;
 
+int64_t Xtensa_L32R_Value(MCInst *MI, int op_num);
+
 void Xtensa_init_mri(MCRegisterInfo *mri);
 void Xtensa_printer(MCInst *MI, SStream *OS, void *info);
 bool Xtensa_disasm(csh handle, const uint8_t *code, size_t code_len,
@@ -24,16 +26,6 @@ void Xtensa_reg_access(const cs_insn *insn, cs_regs regs_read,
 		       uint8_t *regs_write_count);
 #endif
 
-void Xtensa_add_cs_detail(MCInst *MI, xtensa_op_group op_group, va_list args);
+void Xtensa_add_cs_detail_0(MCInst *MI, xtensa_op_group op_group, int op_num);
-
-static inline void add_cs_detail(MCInst *MI, xtensa_op_group op_group, ...)
-{
-	if (!detail_is_set(MI))
-		return;
-	va_list args;
-	va_start(args, op_group);
-	Xtensa_add_cs_detail(MI, op_group, args);
-	va_end(args);
-}
 
 #endif

arch/Xtensa/priv.h

@@ -14,4 +14,7 @@
 #define GET_INSTRINFO_ENUM
 #include "XtensaGenInstrInfo.inc"
 
+#define GET_SUBTARGETINFO_ENUM
+#include "XtensaGenSubtargetInfo.inc"
+
 #endif //CAPSTONE_PRIV_H

bindings/python/capstone/xtensa.py

@@ -8,7 +8,7 @@ from .xtensa_const import *
 class XtensaOpMem(ctypes.Structure):
     _fields_ = (
         ("base", ctypes.c_uint8),
-        ("disp", ctypes.c_uint8),
+        ("disp", ctypes.c_int32),
     )
 
 
@@ -45,6 +45,7 @@ class CsXtensa(ctypes.Structure):
     _fields_ = (
         ("op_count", ctypes.c_uint8),
         ("operands", XtensaOp * 8),
+        ("format", ctypes.c_uint32),
     )
 
 

cs.c

@@ -260,7 +260,8 @@ typedef struct cs_arch_config {
 	{ \
 		Xtensa_global_init, \
 		Xtensa_option, \
-		~(CS_MODE_XTENSA), \
+		~(CS_MODE_XTENSA_ESP32 | CS_MODE_XTENSA_ESP32S2 | \
+		  CS_MODE_XTENSA_ESP8266), \
 	}
 
 #ifdef CAPSTONE_USE_ARCH_REGISTRATION

cstool/cstool.c

@@ -221,8 +221,9 @@ static struct {
 
 	{ "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 },
 	{ "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 },
-	{ "xtensa", "Xtensa", CS_ARCH_XTENSA, CS_MODE_XTENSA },
+	{ "esp32", "Xtensa ESP32", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32 },
-	{ "xtensabe", "Xtensa, big endian", CS_ARCH_XTENSA, CS_MODE_XTENSA | CS_MODE_BIG_ENDIAN },
+	{ "esp32s2", "Xtensa ESP32S2", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S2 },
+	{ "esp8266", "Xtensa ESP8266", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP8266 },
 	{ NULL }
 };
 

cstool/cstool_xtensa.c

@@ -3,6 +3,23 @@
 
 #include <stdio.h>
 #include <capstone/capstone.h>
+#include <capstone/xtensa.h>
+
+static const char *xtensa_insn_form_strs[] = {
+	[XTENSA_INSN_FORM_INVALID] = "XTENSA_INSN_FORM_INVALID",
+	[XTENSA_INSN_FORM_RRR] = "XTENSA_INSN_FORM_RRR",
+	[XTENSA_INSN_FORM_RRI8] = "XTENSA_INSN_FORM_RRI8",
+	[XTENSA_INSN_FORM_RRRN] = "XTENSA_INSN_FORM_RRRN",
+	[XTENSA_INSN_FORM_AEINST24] = "XTENSA_INSN_FORM_AEINST24",
+	[XTENSA_INSN_FORM_BRI12] = "XTENSA_INSN_FORM_BRI12",
+	[XTENSA_INSN_FORM_CALL] = "XTENSA_INSN_FORM_CALL",
+	[XTENSA_INSN_FORM_CALLX] = "XTENSA_INSN_FORM_CALLX",
+	[XTENSA_INSN_FORM_EE_INST24] = "XTENSA_INSN_FORM_EE_INST24",
+	[XTENSA_INSN_FORM_RRI4] = "XTENSA_INSN_FORM_RRI4",
+	[XTENSA_INSN_FORM_RI16] = "XTENSA_INSN_FORM_RI16",
+	[XTENSA_INSN_FORM_RI7] = "XTENSA_INSN_FORM_RI7",
+	[XTENSA_INSN_FORM_RSR] = "XTENSA_INSN_FORM_RSR",
+};
 
 void print_insn_detail_xtensa(csh handle, cs_insn *ins)
 {
@@ -16,6 +33,10 @@ void print_insn_detail_xtensa(csh handle, cs_insn *ins)
 
 	cs_xtensa *detail = &(ins->detail->xtensa);
 
+	if (detail->format && detail->format < XTENSA_INSN_FORM_MAX) {
+		printf("\tformat: %s\n", xtensa_insn_form_strs[detail->format]);
+	}
+
 	if (detail->op_count)
 		printf("\top_count: %u\n", detail->op_count);
 
@@ -30,7 +51,7 @@ void print_insn_detail_xtensa(csh handle, cs_insn *ins)
 		else if (op->type == CS_OP_MEM)
 			printf("\t\toperands[%u].type: MEM\n"
 			       "\t\t\t.mem.base: REG = %s\n"
-			       "\t\t\t.mem.disp: 0x%" PRIx8 "\n",
+			       "\t\t\t.mem.disp: 0x%" PRIx32 "\n",
 			       i, cs_reg_name(handle, op->mem.base),
 			       op->mem.disp);
 		else if (op->type == XTENSA_OP_L32R) {

include/capstone/capstone.h

@@ -222,7 +222,9 @@ typedef enum cs_mode {
 	CS_MODE_SYSTEMZ_Z15 = 1 << 13, ///< Enables features of the Z15 processor
 	CS_MODE_SYSTEMZ_Z16 = 1 << 14, ///< Enables features of the Z16 processor
 	CS_MODE_SYSTEMZ_GENERIC = 1 << 15, ///< Enables features of the generic processor
-	CS_MODE_XTENSA = 1 << 1, ///< Xtensa
+	CS_MODE_XTENSA_ESP32 = 1 << 1,	 ///< Xtensa ESP32
+	CS_MODE_XTENSA_ESP32S2 = 1 << 2, ///< Xtensa ESP32S2
+	CS_MODE_XTENSA_ESP8266 = 1 << 3, ///< Xtensa ESP328266
 } cs_mode;
 
 typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);

suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py

@@ -50,6 +50,7 @@ from autosync.cpptranslator.patches.IsPredicate import IsPredicate
 from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm
 from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough
 from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable
+from autosync.cpptranslator.patches.LLVM_DEBUG import LLVM_DEBUG
 from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction
 from autosync.cpptranslator.patches.MethodTypeQualifier import MethodTypeQualifier
 from autosync.cpptranslator.patches.NamespaceAnon import NamespaceAnon
@@ -153,6 +154,7 @@ class Translator:
         Assert.__name__: 0,  # ◁─────────┐ The llvm_unreachable calls are replaced with asserts.
         LLVMUnreachable.__name__: 1,  # ─┘ Those assert should stay.
         LLVMFallThrough.__name__: 0,
+        LLVM_DEBUG.__name__: 0,
         DeclarationInConditionalClause.__name__: 0,
         StreamOperations.__name__: 0,
         OutStreamParam.__name__: 0,  # ◁──────┐ add_cs_detail() is added to printOperand functions with a certain
@@ -323,6 +325,8 @@ class Translator:
                     patch = ConstMCInstParameter(p)
                 case LLVMUnreachable.__name__:
                     patch = LLVMUnreachable(p)
+                case LLVM_DEBUG.__name__:
+                    patch = LLVM_DEBUG(p)
                 case ClassConstructorDef.__name__:
                     patch = ClassConstructorDef(p)
                 case ConstMCOperand.__name__:
@@ -434,7 +438,8 @@ class Translator:
                     else:
                         # A capture which is part of the main capture.
                         # Add it to the bundle.
-                        captures_bundle[-1].append(q)
+                        if len(captures_bundle) > 0:
+                            captures_bundle[-1].append(q)
 
                 log.debug(
                     f"Patch {patch.__class__.__name__} (to patch: {len(captures_bundle)})."

suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py

@@ -46,6 +46,7 @@ from autosync.cpptranslator.patches.IsOptionalDef import IsOptionalDef
 from autosync.cpptranslator.patches.IsPredicate import IsPredicate
 from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm
 from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough
+from autosync.cpptranslator.patches.LLVM_DEBUG import LLVM_DEBUG
 from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable
 from autosync.cpptranslator.patches.Override import Override
 from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction
@@ -413,7 +414,12 @@ public:
     def test_llvmunreachable(self):
         patch = LLVMUnreachable(0)
         syntax = b'llvm_unreachable("Error msg")'
-        self.check_patching_result(patch, syntax, b'assert(0 && "Error msg")')
+        self.check_patching_result(patch, syntax, b'CS_ASSERT(0 && "Error msg")')
+
+    def test_llvmdebug(self):
+        patch = LLVM_DEBUG(0)
+        syntax = b'LLVM_DEBUG(dbgs() << "Error msg")'
+        self.check_patching_result(patch, syntax, b"")
 
     def test_methodtofunctions(self):
         patch = MethodToFunction(0)

suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py

@@ -90,8 +90,6 @@ class AddCSDetail(Patch):
         op_group_enum = (
             self.arch.encode("utf8") + b"_OP_GROUP_" + fcn_id[5:]
         )  # Remove "print" from function id
-        if self.arch == "Xtensa":
-            op_group_enum = op_group_enum.upper()
 
         is_template = fcn_def.prev_sibling.type == "template_parameter_list"
         if b"OpNum" in params:

suite/auto-sync/src/autosync/cpptranslator/patches/LLVM_DEBUG.py

@@ -0,0 +1,36 @@
+# Copyright © 2022 Rot127 <unisono@quyllur.org>
+# Copyright © 2024 Billow <billow.fun@gmail.com>
+# SPDX-License-Identifier: BSD-3
+
+from tree_sitter import Node
+
+from autosync.cpptranslator.patches.Helper import get_text
+from autosync.cpptranslator.patches.Patch import Patch
+
+
+class LLVM_DEBUG(Patch):
+    """
+    Patch   LLVM_DEBUG(dbgs() << "Error msg")
+    to      ""
+    """
+
+    def __init__(self, priority: int):
+        super().__init__(priority)
+
+    def get_search_pattern(self) -> str:
+        return """
+            (call_expression (
+               (identifier) @fcn_name (#eq? @fcn_name "LLVM_DEBUG")
+               (argument_list (
+                   (binary_expression (
+                       (call_expression)
+                       (string_literal) @err_msg
+                   ))
+               ))
+            )) @llvm_debug"""
+
+    def get_main_capture_name(self) -> str:
+        return "llvm_debug"
+
+    def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
+        return b""

suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py

@@ -30,5 +30,5 @@ class LLVMUnreachable(Patch):
     def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
         err_msg = captures[2][0]
         err_msg = get_text(src, err_msg.start_byte, err_msg.end_byte).strip(b"()")
-        res = b"assert(0 && " + err_msg + b")"
+        res = b"CS_ASSERT(0 && " + err_msg + b")"
         return res

suite/auto-sync/src/autosync/cpptranslator/patches/isUInt.py

@@ -10,8 +10,8 @@ from autosync.cpptranslator.TemplateCollector import TemplateCollector
 
 class IsUInt(Patch):
     """
-    Patch   isUInt<N>(...)
+    Patch   isUInt|isInt<N>(...)
-    to      isUInt(..., N)
+    to      isUInt|isInt(..., N)
     """
 
     def __init__(self, priority: int):
@@ -21,7 +21,7 @@ class IsUInt(Patch):
         return (
             "(call_expression"
             "    (template_function"
-            '         ((identifier) @id (#eq? @id "isUInt"))'
+            '         ((identifier) @id (#match? @id "isUInt|isInt"))'
             "         ((template_argument_list) @templ_args)"
             "    )"
             "    ((argument_list) @arg_list)"

suite/auto-sync/src/autosync/cpptranslator/saved_patches.json

@@ -3292,77 +3292,125 @@
     }
   },
   "XtensaDisassembler.c": {
-    "\"../../SStream.h\"": {
+    "\"../../utils.h\"": {
       "apply_type": "OLD",
-      "old_hash": "2b45d68382f855f8fdc8a7cf177cda2d4dee75318bab9e1304026375ba05284f",
+      "old_hash": "bba3ceddc5b6ca88f7f5a17acc4d2545a08e4011ca8224462a64a30eff35e9eb",
       "new_hash": "",
       "edit": ""
     },
-    "\"../../cs_priv.h\"": {
+    "CheckRegister": {
       "apply_type": "OLD",
-      "old_hash": "9cf77913cc1ba047983eb15f5e6dce657fb26b09f32757f02de5df2cf4023d87",
+      "old_hash": "596295adf943c3f7beb2eb2897d51a34f839e0907e13e1df5a3b3f4b203a174b",
-      "new_hash": "",
+      "new_hash": "9fdad4704876c8820a8976e2bec1444690bd884ccab181e383666fc7d7f84f0d",
       "edit": ""
     },
-    "\"XtensaGenInstrInfo.inc\"": {
+    "DecodeARRegisterClass": {
       "apply_type": "OLD",
-      "old_hash": "7dada799dde9a9ea873fe6933799f19a60273bd85d56804c06e7e87b761c973d",
+      "old_hash": "0c96c29f2eb8b45ba4b68d3f8c4f2df555b547cee3038a3a9617de93ccbfe967",
-      "new_hash": "",
+      "new_hash": "7cb44a5bb5cc06edc8437fe201265278602fb87948b8ab93701dd9f33f890a72",
       "edit": ""
     },
-    "\"priv.h\"": {
+    "DecodeBR2RegisterClass": {
       "apply_type": "OLD",
-      "old_hash": "d09344b441eba2a943ba1323088ec14a8bad410b94e47900e170c51876794892",
+      "old_hash": "51bc3626c012a6b4d7e84600ef122db160953fa3bbf6923badae5db1c85363f3",
-      "new_hash": "",
+      "new_hash": "7afc1d1acd89fc07c9ee83ae16c748cab3bca9eddb51b3b37115bc4622b9fa73",
+      "edit": ""
+    },
+    "DecodeBR4RegisterClass": {
+      "apply_type": "OLD",
+      "old_hash": "926a2a86aa1d6b356005677a7ad17681ac931f3bc0ad69ad2eadea0e5f1f6648",
+      "new_hash": "76d79955326eecb2810b80ad8807be23ed0d9be1a60ac8147ba88a71ad44b016",
       "edit": ""
     },
     "DecodeSRRegisterClass": {
       "apply_type": "OLD",
-      "old_hash": "21ddebca1aac12b568bfba25e971d02c3166147ff2ba8308e7f95e07bc754e28",
+      "old_hash": "80e576fa30ce1f4b7c55ca8cb42a21b4eec277ae3516b96d7788b5e47da1be07",
-      "new_hash": "0bfba6491089483244f115b4130ebe5c03d5572c8267bf015f704bb5fd1526a7",
+      "new_hash": "9e92e95176f117b686e0f72c7b6bed53978ce2ced150d324fb4554dfcbea637a",
       "edit": ""
     },
-    "Xtensa_LLVM_getInstruction": {
+    "DecodeURRegisterClass": {
       "apply_type": "OLD",
-      "old_hash": "f62a9a80e3667fa51669fe7fa22da87b1c95bb1235e0840e5455069731ca42d1",
+      "old_hash": "05d1985ac2f309e25639427ae102789147c554e0ee87bb1a8d4872469f1e3f65",
+      "new_hash": "4698893380665bf15a83342ccd61df5c8d6b071f82cd5e8aea8a0e83d1c7cfe2",
+      "edit": ""
+    },
+    "Xtensa_getFeatureBits": {
+      "apply_type": "OLD",
+      "old_hash": "126cff581e1a79a655c62e3489e238f7bf00647749f619230ab77061d0423295",
       "new_hash": "",
       "edit": ""
     },
+    "decodeOffset_16_16Operand": {
+      "apply_type": "OLD",
+      "old_hash": "8e6af6081ce4bbfc7a8472e68608bd1ae9063ba4a2d47106b32f6963989cc32b",
+      "new_hash": "1eab39a0f5969551c19bf8c420d2a48ab451d4b25e6b571d1089b041288eb56e",
+      "edit": ""
+    },
     "getInstruction": {
       "apply_type": "OLD",
-      "old_hash": "50b6a904fc89bab054302112bd312dff8befdca7e0fdeebbfdc5d37cb49a2eeb",
+      "old_hash": "eb59acd833cc3a3d0a12d9171f81852c2064a72c464242ba589e7f44e5e67749",
-      "new_hash": "9215f65202a5f06de4718f9562adc149b5271358b49ce03be887dde2fdf03a25",
+      "new_hash": "bf7e383d6e9fb7856bae8663ba1dfeb0e855aa53a967c9d2dd31c0d32a5c5bad",
+      "edit": ""
+    },
+    "hasDensity": {
+      "apply_type": "OLD",
+      "old_hash": "da63483f075aba3c9f8937fb1900c646cb15f01b6b2e25568e6dcaa940b4798b",
+      "new_hash": "",
+      "edit": ""
+    },
+    "hasESP32S3Ops": {
+      "apply_type": "OLD",
+      "old_hash": "464131365b24dec185e04d43154a85d9765a50a18214888c26014d8d85165a99",
+      "new_hash": "",
+      "edit": ""
+    },
+    "hasHIFI3": {
+      "apply_type": "OLD",
+      "old_hash": "e1fcb3c8f47f38e571d1a81e7e522efb5c67e0aea05fd7b3980aa1eb3e71c9ff",
+      "new_hash": "",
+      "edit": ""
+    },
+    "readInstruction16": {
+      "apply_type": "OLD",
+      "old_hash": "f9e94bcdff23b60fcdcb7e4b7983533b656b65667e2bd94c0274b6fc3325db30",
+      "new_hash": "b820e77484d8c50eafd40fa47519ec6743915437b5a8ca111ad7c24c5488e24c",
       "edit": ""
     },
     "readInstruction24": {
       "apply_type": "OLD",
-      "old_hash": "496be4020feedac98bcb88b969c1e9a2013f664120193b45b76ff4a683e12d0d",
+      "old_hash": "23a22a31c202c67e794a924792ffc1260c34f43354c9cf383cbaf6de0789eef8",
-      "new_hash": "2c39773dba873ff597df8420c2a710ecd3604ecb232406dc8b2f20bc3a11e655",
+      "new_hash": "952f97406bc801d756f70dd847fe171de2c6aa57d1c4344b03afa39816c711f5",
+      "edit": ""
+    },
+    "readInstruction32": {
+      "apply_type": "OLD",
+      "old_hash": "51d1f0dc2aaa3538aadcc8f175c37b68a2c6df536d771f5a14eb51e780a70acf",
+      "new_hash": "c3bcb9bd57f518b1afb595452a1bd188a033ec0793a5b0006c8ef4b50f28b76c",
+      "edit": ""
+    },
+    "readInstructionN": {
+      "apply_type": "OLD",
+      "old_hash": "f8d33ddb78b23277a87d9e0ceeeaa2d2bdb2adcd512f4cc21551515c3a5a7460",
+      "new_hash": "04a7b2c47032634f0d761a06aeaf540b5bd62b5cf354d822c7b77442d3539709",
       "edit": ""
     },
     "tryAddingSymbolicOperand": {
       "apply_type": "OLD",
-      "old_hash": "abfdc1e7fb69748a05a49a9829618b7ff43e913c7a46476c5a5e69151e44872c",
+      "old_hash": "08ca716577811532149c71c55044a8ec960dbabbb680d654d730d82a6637fe66",
       "new_hash": "b1a20345c1f90c2ef792825a3ecd379a856dca51240a92c3b9ce3a3685f09e2a",
       "edit": ""
     }
   },
   "XtensaInstPrinter.c": {
-    "\"../../MCInstPrinter.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "ea06257675896d185a423f8471328a8b98e74c260aad3e2e614d0ef48a744004",
-      "new_hash": "",
-      "edit": ""
-    },
     "\"../../Mapping.h\"": {
       "apply_type": "OLD",
       "old_hash": "204ac68dcb32024c325b99a0843719c321ab57c60c41b12adbea497c20b7d436",
       "new_hash": "",
       "edit": ""
     },
-    "\"../../SStream.h\"": {
+    "\"../../MathExtras.h\"": {
       "apply_type": "OLD",
-      "old_hash": "2b45d68382f855f8fdc8a7cf177cda2d4dee75318bab9e1304026375ba05284f",
+      "old_hash": "c6ce14448320faf6eb6a6386c8917b014947f3ffe02d3741941e3acbb23f408d",
       "new_hash": "",
       "edit": ""
     },
@@ -3372,95 +3420,267 @@
       "new_hash": "",
       "edit": ""
     },
-    "\"XtensaMapping.h\"": {
+    "printB4const_AsmOperand": {
-      "apply_type": "OLD",
+      "apply_type": "NEW",
-      "old_hash": "5dc6afd5c4beb43ecf77407bd50c579ace7cc07013610ee1e72933981da27ee2",
+      "old_hash": "95286239018cc1f8996932911725a00cc1dbdacefd44100ffe9e85605855650a",
-      "new_hash": "",
+      "new_hash": "7f3c9f9daa044844c8cd6fd798b910d95f598c13d5dbe97e7e9ae523742d45c4",
       "edit": ""
     },
-    "Xtensa_LLVM_getRegisterName": {
+    "printB4constu_AsmOperand": {
-      "apply_type": "OLD",
+      "apply_type": "NEW",
-      "old_hash": "87e2ae763d6d60ffd9da21d1b70f147c552cb75960b11ae98b8b21fe58bb938c",
+      "old_hash": "0e0e48125625a4e4ff7c45621193c2ded8683d4f61171a6bca8583e94ecf2861",
-      "new_hash": "",
+      "new_hash": "38bf0f6e6f63456872580a8788a44c926ba23bca3d09d897531601d7c9ab28ef",
-      "edit": ""
-    },
-    "Xtensa_LLVM_printInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "1407d0fd0871a19025128731e3438bbff398ff173720e14f58cc1dbc781e5d51",
-      "new_hash": "",
       "edit": ""
     },
     "printBranchTarget": {
-      "apply_type": "NEW",
+      "apply_type": "OLD",
-      "old_hash": "c91f9d98415c1c413489ef360bc11ebb11b6f9e3b1564d4b57d0577c0a6feaa8",
+      "old_hash": "b44eac3a548beca2fc0dbab7136888a138bb82956939ee2d6775715e825d3ed8",
-      "new_hash": "760223784267d403ac29f9ed51c2a30ff2ef1ddf9679b59db71b741f23c03719",
+      "new_hash": "30a5c55b095e3d7d128f6764a44b3721c391120c1eebda142e8c48581a015c35",
       "edit": ""
     },
     "printCallOperand": {
+      "apply_type": "OLD",
+      "old_hash": "74c10cbd33480583bf9cb16cfeb0255f39f007cc2086d2d366198a6195a48193",
+      "new_hash": "e6f5a1baa3ab336e904439496e9ab427495257c30b5b4bf30c2e656d491912cc",
+      "edit": ""
+    },
+    "printEntry_Imm12_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "62f875bf3eae5d3502f03df40ff473ddd838e38c87711a1fb5922d41960e74ed",
+      "old_hash": "5f41a019e37134f392d97fcb5c7685212db7fe79b8644d1d2ff2c2838ec7645d",
-      "new_hash": "5e936d44076c6ab4dfb8bf579b368f7107954dd391ea5f82d489afbe26184985",
+      "new_hash": "af42cbcfa872eae69042234191eda86e144ab62dc045391ff000a0822b1cf5e8",
+      "edit": ""
+    },
+    "printExpr": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "072277ca408ccee54f26b0aa3868979167538935f6c896e0e0321989317acf95",
+      "edit": ""
+    },
+    "printImm12_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "b65a312bb8c2fb90abe11f34a53391187478da1903a63330880bc529d428eed4",
+      "new_hash": "5e05aa21fb248469596ad5b73098418b6022332293bb425cb5261c35dacb9a08",
       "edit": ""
     },
     "printImm12m_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "a656e5282b4444835dc20ffb645e92c51b5512ed43aabb7c9f2eafa1d2c81a76",
+      "old_hash": "95ec43b138b49b7c2b2b7b7f1e3c73e47567122aa05ba29006201b26e252aa9b",
-      "new_hash": "64a9511d7f18e2fce3b4d08179b8cb6681d1e5df195241706a30d00c3ea2288e",
+      "new_hash": "e1bc95caa665ca4d49daad0ae56c554947cd77248e7782d745f455986c6953c8",
       "edit": ""
     },
     "printImm1_16_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "4a34c1913614bdaee2795f1c94d395b78be60f4d1ae84a0f28ea0e8a573381f9",
+      "old_hash": "fef56d8f6470a8f1ee6b32ee041eda3d0fdbee9a54f6c6c4b18e9c13f4cf58ef",
-      "new_hash": "c9956b1881ed5107439d2e4606cec93870837a3390436264a6e0c66762b68a5c",
+      "new_hash": "1c01024d0b113c67c561b85102222a5216d398635b42f500bc1abf493a5a15d1",
+      "edit": ""
+    },
+    "printImm1n_15_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "639fb72b9e6f5b3f4e5d5684e81e159d1ca127d52ac50221edeb3cadd21af25d",
+      "new_hash": "046b29499e71c577300e51aec198c409462ac1e6f3b8139c2b9084a8c3d1322d",
+      "edit": ""
+    },
+    "printImm32n_95_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "2bb4ae32db9ff7b936d2a3c264770c2b709204638534391e6029f0144d5f57dd",
+      "new_hash": "baf6a152aed77994f9183f99bd79fef31a882f53f5b4e48fa8af7dd2bd7dda46",
+      "edit": ""
+    },
+    "printImm64n_4n_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "6e13be28e15c60c8e16bd781f6b1ba98d10f6a89c95b56427ba2a02bf83419c1",
+      "new_hash": "43096ff08b281574f97716b593c640fa07dda19a119759bdb66e1d804ec2341b",
+      "edit": ""
+    },
+    "printImm7_22_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "047f322b2ddc8bf95e856b216327440c254cc8b64e2e5af46bc8c7d786f0350b",
+      "new_hash": "0a3876fbfcd4b92249fd78ea0a89e3af7182b5fab9bcef0b6721157076c0b658",
+      "edit": ""
+    },
+    "printImm8_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "2d6c15b35ff2a38cb914f1285d771ff3932cb2da16c1cc229fe72e8a4f4b6a53",
+      "new_hash": "2b3e7f1edae120104093ff72e4ab896e94042faf61a8546c920721d975a0e60c",
       "edit": ""
     },
     "printImm8_sh8_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "9affee556485b99036667d0fde115610b9b67037c5ffdfedf9f5eb379b89c146",
+      "old_hash": "803e8a5d41a3d028f1d05cdb4ffa6e4f7b9c1ac0c47edb96b4c1787c8013973e",
-      "new_hash": "e4ab93bab36ba4c3436618523e3ff14b330819652e4cada4f19001ad63e92560",
+      "new_hash": "e821ebca538d1ca8585ba781563998f3e07c50fab68bb0c280f24f42eb9cbe6f",
+      "edit": ""
+    },
+    "printImm8n_7_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "e00a45dfe0b2a949b786c2527a35434c44992a633adad3e30810b4af09147cb0",
+      "new_hash": "d3cf28eb442b9eacc559751b2070a41250c7b17bc7af9f760e9bf81777b612ed",
+      "edit": ""
+    },
+    "printInst": {
+      "apply_type": "OLD",
+      "old_hash": "847b1638dc95faa0a1ec26726d737939555436b002a4e1c9a976402e190d901b",
+      "new_hash": "7f31dabd32046112fe19e125b98a28aef3ddd55fb89387414a3902dec7450cdb",
       "edit": ""
     },
     "printJumpTarget": {
-      "apply_type": "NEW",
+      "apply_type": "OLD",
-      "old_hash": "b3fb61b967ddbdcd4ba31c0d7f6cbdb5b52880eba2d0f3b6961cb8736d65e6e0",
+      "old_hash": "6f6b415c66f99c315ad194dd5baf40f43ad7cae2326ecc4e3bfb38c824f2aff2",
-      "new_hash": "0810cb753da2c503ec8cf969c4fa7bfb9f47fd6a9d66a83eb2c8b0166489512f",
+      "new_hash": "54fadd3e08a0846250448d4c5002689cc964b13737d9b9c282faeb3124338330",
       "edit": ""
     },
     "printL32RTarget": {
+      "apply_type": "OLD",
+      "old_hash": "60e841bb8af9939f55f126e972ed9ba8f251fe2d817aa8adde94765fb58cd77b",
+      "new_hash": "8a5e44a06861b439015f20cfac19090017738f307211042e63838e6d91099315",
+      "edit": ""
+    },
+    "printLoopTarget": {
+      "apply_type": "OLD",
+      "old_hash": "f3c1287796da8ce8515d78be3d6d817bf08a93a14b6bec7363b5823d34d5312c",
+      "new_hash": "e0cfc237a3f7589e29a888b9b87e7b337eb4084f865c4064266339979739a40a",
+      "edit": ""
+    },
+    "printMemOperand": {
       "apply_type": "NEW",
-      "old_hash": "518eb907a827efe2ae569b32ec9acfda29bd106c28f53a997fa40233c84f5433",
+      "old_hash": "18198ea8207fbbec48b29af09bbc9daafdf2b506b125ccabb1a742e5429486f8",
-      "new_hash": "66fcd5c6ce5d625014bffc3c23bdab57a78b467dabfe3bdcb5d67af2cdfc8192",
+      "new_hash": "ef6ee0c4c83058cf374ae9a75de6a7933b5376d9cb89b3672eaa9b70b4d88dab",
+      "edit": ""
+    },
+    "printOffset4m32_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "305876681b43dde9508a2727be55953d3faa4d61277604daaccd62ff025ba282",
+      "edit": ""
+    },
+    "printOffset8m16_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "7d1dc598131cde86738fba8a48b108d9ef47f8c1d7c0dfd4bd6c14630b937eea",
+      "edit": ""
+    },
+    "printOffset8m32_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "ba8f8b604595b5bb98cc727c973a6f0925dfb2b408befb9ac951979cb58e79fe",
+      "new_hash": "702162aeea83e18681291f067e7a9878c49382f8b347fdd56f922c46a6e78b97",
+      "edit": ""
+    },
+    "printOffset8m8_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "",
+      "new_hash": "ba9e749a819a45c761157999d8da64d0ce36d349e615ea0ee8557895514a7490",
+      "edit": ""
+    },
+    "printOffset_128_1_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "5a00f109b1bb46c17177951011194721e0010071e8fbf262c27a014d6874094d",
+      "new_hash": "e083c054f7d2d39dcc3edd655f1cf9cbfbf97c44f4be03324881c9c1e9a6a241",
+      "edit": ""
+    },
+    "printOffset_128_2_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "d3534318dbe7ec222182a39a710be343a70286ecdab1482bbc69ed0e0347c383",
+      "new_hash": "cb55083ff690e86c34460f70a8ddf795e5a544dad66ecab10215821939226a4e",
+      "edit": ""
+    },
+    "printOffset_16_16_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "dc3ccb4b6985b696f6a84bf9a2e8d6b8806e080d08e7b287209c0e79b8d5350b",
+      "new_hash": "475eea066d629ed7c81fb4e0d90d98e370dcea405d9920b9389a0b40a1296e2c",
+      "edit": ""
+    },
+    "printOffset_256_16_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "50ded4c517742aa807ee3706162e78968a3e2ec924cde15885ec9f2b3bccaae1",
+      "new_hash": "20932c1b9cfa9e6b63f9198d011a35e87c4985b548a656b6915ab6fb70343b41",
+      "edit": ""
+    },
+    "printOffset_256_4_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "fab624d2080e91d2e18fa28da6b5280d03f87eb7693c0feeccea275ba9eeca14",
+      "new_hash": "8d214fc301e0b3277783fd3259fa98edf62943e411ba7b51b60c1f31305107da",
+      "edit": ""
+    },
+    "printOffset_256_8_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "daacbf5252fd7aae372e3e389b73a2d8bb3c10c91cdc6f8ad1c16a61fe57ff2a",
+      "new_hash": "914ef7b678aa8dd9b61070362c3cd7cbfb00da95177fd66e22f8a6d6ee72d157",
+      "edit": ""
+    },
+    "printOffset_64_16_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "77b4694bf4e494cab65de3db4f59e30a5c25c5f42d7d31931af3f3a4d6a07a23",
+      "new_hash": "105f3eba991b1d5f871e4a66a8c8ea17096ec3abd5f9e049d75db8d654a0e294",
       "edit": ""
     },
     "printOperand": {
       "apply_type": "OLD",
-      "old_hash": "1c19f6735e6c56ef62a9ce8eabe0a2f50e530fc6efb505b30de99a28b8299f6c",
+      "old_hash": "73ffe28b1e49daebc32ee4bc16161eb26dbd5eba12b5e0d9d4277244eaa6ae83",
       "new_hash": "",
       "edit": ""
     },
+    "printRegName": {
+      "apply_type": "OLD",
+      "old_hash": "7339b26adb7b26b0aeb28115917a5f1d7d62f47b12329402d7e599a2655fac4f",
+      "new_hash": "e7c1b4d5e336f55c35e0ceae611df7c7977892c5b72906f5d4e6a45b688ad542",
+      "edit": ""
+    },
+    "printSelect_16_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "d088fba9434c96470ca5b156eef02cc87d62aa3ed70d5d23ba6749236e33ebde",
+      "new_hash": "a6bb330fa5d4a6c9f45d39782dff4d9d402ef34f06af93ca761097ea5b3366de",
+      "edit": ""
+    },
+    "printSelect_256_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "6ab19cb8f9da25045289638041c98246e9e3832cf2b3d7ae075dfc6c71114e3b",
+      "new_hash": "2d17c7bf71afb6d3fb30be5c994593c88d1792ea723eb72b6d390bb6cea27935",
+      "edit": ""
+    },
+    "printSelect_2_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "48a9a265f9af7dc477311003876ca1790349f297cbc1e381d35deb792c19c3aa",
+      "new_hash": "ca00be247d873a269fa8d9875e062fa579cc799e455da4dd157f0cffee407e39",
+      "edit": ""
+    },
+    "printSelect_4_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "aab5bb38ea56f27770d8b10d4e12f3275832d333d028e99b751d65d3ca4c3341",
+      "new_hash": "905740049261c4293578e8f55818fd9df7864b94b1ade5c05e294315795aca6b",
+      "edit": ""
+    },
+    "printSelect_8_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "4641912c97f0bac9e39d916f660332b52618e44ae6e109a04a0cb72f400d6b18",
+      "new_hash": "ab8cf975ad51335e804b3badf29cb548c69545f08a366825a679aefd9666db57",
+      "edit": ""
+    },
+    "printShimm0_31_AsmOperand": {
+      "apply_type": "NEW",
+      "old_hash": "ff5717b5e09680119a7badbeea5c314f3d4da52211d203546f4323e95db16c48",
+      "new_hash": "381ce321a92c147a2a1e2dac5365bf503bd8f0f0885a9b3211a41af04f4b0251",
+      "edit": ""
+    },
     "printShimm1_31_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "a87790f5ac96dd626e1ae77a2949ff6ca9f3ac042b4ec87069b5b20e5bc43ba6",
+      "old_hash": "2728d694c8c2d0692bb6dec5f3edcb66340a83813c1a0efa45d33b2760a06623",
-      "new_hash": "0a881b7568ff8a62cbf47caef513cabd32928af5cd182584da59a9be618b6c2e",
+      "new_hash": "7d2a06d0114f2cae0fd0cd5c62eb007c38d0f0fd8fc6511372d9b60e8d4cce28",
       "edit": ""
     },
     "printUimm4_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "d8dbc1a930c08cbb2047c4462f6102ce7a9dc516754ee06d69ed88ceb3624c64",
+      "old_hash": "6fc7dc9dc14c2ce05d8d8cd0c40b0048c09e62b914d48fde447c768e9eb89b4f",
-      "new_hash": "3ba7c11490ec5eacc67595df5d26db88c4db327dc12c06f91349a29b3a31320c",
+      "new_hash": "24c103d1b9410653ddfefb4e4a68d6b8736b10a68929bb21753cb522551f4a32",
       "edit": ""
     },
     "printUimm5_AsmOperand": {
       "apply_type": "NEW",
-      "old_hash": "0c4dd11b6282b42f5e08458fe206ef5f34e738626f5dbf57521355f96dd820a4",
+      "old_hash": "a030d6b8a00d4a7823586eda567a8b5033fcaa42d49ac4905755a86ac1e3cb63",
-      "new_hash": "5c8fe6e58c1463f1556d33c60896696340eb444e5938270d5e23c9df6a1ab4e8",
+      "new_hash": "70af971b7faf90e7127d09f60b897cae8eb097ffd8d1ed3e8c1bb53bd63410c5",
       "edit": ""
-    }
+    },
-  },
+    "Xtensa_LLVM_printInstruction": {
-  "XtensaInstPrinter.h": {
-    "\"priv.h\"": {
       "apply_type": "OLD",
-      "old_hash": "d09344b441eba2a943ba1323088ec14a8bad410b94e47900e170c51876794892",
+      "old_hash": "6ca58c91fb8b87d0eb7763591edd07ccc9a8b369cfdf4bb806507ff766ab0fb5",
       "new_hash": "",
       "edit": ""
     }

suite/cstest/include/test_detail.h

@@ -31,6 +31,7 @@
 #include "test_detail_wasm.h"
 #include "test_detail_x86.h"
 #include "test_detail_m68k.h"
+#include "test_detail_xtensa.h"
 #include "test_compare.h"
 #include <capstone/capstone.h>
 #include <cyaml/cyaml.h>
@@ -59,6 +60,7 @@ typedef struct {
 	TestDetailWASM *wasm;
 	TestDetailX86 *x86;
 	TestDetailM68K *m68k;
+	TestDetailXtensa *xtensa;
 
 	char **regs_read;
 	uint8_t regs_read_count;
@@ -145,6 +147,9 @@ static const cyaml_schema_field_t test_detail_mapping_schema[] = {
 	CYAML_FIELD_MAPPING_PTR(
 		"m68k", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
 		m68k, test_detail_m68k_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"xtensa", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		xtensa, test_detail_xtensa_mapping_schema),
 	CYAML_FIELD_SEQUENCE("regs_read",
 			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
 			     TestDetail, regs_read, &single_string_schema, 0, 255),

suite/cstest/include/test_detail_xtensa.h

@@ -0,0 +1,73 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// Copyright © 2024 Billow <billow.fun@gmail.com>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_XTENSA_H
+#define TEST_DETAIL_XTENSA_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int32_t imm;
+	char *mem_base;
+	int32_t mem_disp;
+} TestDetailXtensaOp;
+
+static const cyaml_schema_field_t test_detail_xtensa_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXtensaOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXtensaOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXtensaOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailXtensaOp, imm),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailXtensaOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailXtensaOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_xtensa_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailXtensaOp,
+			    test_detail_xtensa_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailXtensaOp **operands;
+	uint32_t operands_count;
+	char *format;
+} TestDetailXtensa;
+
+static const cyaml_schema_field_t test_detail_xtensa_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailXtensa, operands, &test_detail_xtensa_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_STRING_PTR("format",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXtensa, format, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_END
+};
+
+TestDetailXtensa *test_detail_xtensa_new();
+TestDetailXtensa *test_detail_xtensa_clone(const TestDetailXtensa *detail);
+void test_detail_xtensa_free(TestDetailXtensa *detail);
+
+TestDetailXtensaOp *test_detail_xtensa_op_new();
+TestDetailXtensaOp *
+test_detail_xtensa_op_clone(const TestDetailXtensaOp *detail);
+void test_detail_xtensa_op_free(TestDetailXtensaOp *detail);
+
+bool test_expected_xtensa(csh *handle, const cs_xtensa *actual,
+			  const TestDetailXtensa *expected);
+
+#endif // TEST_DETAIL_XTENSA_H

suite/cstest/include/test_mapping.h

@@ -169,7 +169,9 @@ static const cs_enum_id_map test_mode_map[] = {
 	{ .str = "CS_MODE_TRICORE_162", .val = CS_MODE_TRICORE_162 },
 	{ .str = "CS_MODE_V8", .val = CS_MODE_V8 },
 	{ .str = "CS_MODE_V9", .val = CS_MODE_V9 },
-	{ .str = "CS_MODE_XTENSA", .val = CS_MODE_XTENSA },
+	{ .str = "CS_MODE_XTENSA_ESP32", .val = CS_MODE_XTENSA_ESP32 },
+	{ .str = "CS_MODE_XTENSA_ESP32S2", .val = CS_MODE_XTENSA_ESP32S2 },
+	{ .str = "CS_MODE_XTENSA_ESP8266", .val = CS_MODE_XTENSA_ESP8266 },
 };
 
 static const TestOptionMapEntry test_option_map[] = {
@@ -1191,81 +1193,153 @@ static const cs_enum_id_map cs_enum_map[] = {
 	{ .str = "SYSTEMZ_INSN_FORM_INSTE", .val = SYSTEMZ_INSN_FORM_INSTE },
 	{ .str = "SYSTEMZ_INSN_FORM_INSTI", .val = SYSTEMZ_INSN_FORM_INSTI },
 	{ .str = "SYSTEMZ_INSN_FORM_INSTIE", .val = SYSTEMZ_INSN_FORM_INSTIE },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTMII", .val = SYSTEMZ_INSN_FORM_INSTMII },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTMII",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIA", .val = SYSTEMZ_INSN_FORM_INSTRIA },
+	  .val = SYSTEMZ_INSN_FORM_INSTMII },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIB", .val = SYSTEMZ_INSN_FORM_INSTRIB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIA",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIC", .val = SYSTEMZ_INSN_FORM_INSTRIC },
+	  .val = SYSTEMZ_INSN_FORM_INSTRIA },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEA", .val = SYSTEMZ_INSN_FORM_INSTRIEA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIB",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEB", .val = SYSTEMZ_INSN_FORM_INSTRIEB },
+	  .val = SYSTEMZ_INSN_FORM_INSTRIB },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEC", .val = SYSTEMZ_INSN_FORM_INSTRIEC },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIC",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIED", .val = SYSTEMZ_INSN_FORM_INSTRIED },
+	  .val = SYSTEMZ_INSN_FORM_INSTRIC },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEE", .val = SYSTEMZ_INSN_FORM_INSTRIEE },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEA",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEF", .val = SYSTEMZ_INSN_FORM_INSTRIEF },
+	  .val = SYSTEMZ_INSN_FORM_INSTRIEA },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEG", .val = SYSTEMZ_INSN_FORM_INSTRIEG },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEB",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRILA", .val = SYSTEMZ_INSN_FORM_INSTRILA },
+	  .val = SYSTEMZ_INSN_FORM_INSTRIEB },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRILB", .val = SYSTEMZ_INSN_FORM_INSTRILB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEC",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRILC", .val = SYSTEMZ_INSN_FORM_INSTRILC },
+	  .val = SYSTEMZ_INSN_FORM_INSTRIEC },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRIS", .val = SYSTEMZ_INSN_FORM_INSTRIS },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIED",
+	  .val = SYSTEMZ_INSN_FORM_INSTRIED },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEE",
+	  .val = SYSTEMZ_INSN_FORM_INSTRIEE },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEF",
+	  .val = SYSTEMZ_INSN_FORM_INSTRIEF },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIEG",
+	  .val = SYSTEMZ_INSN_FORM_INSTRIEG },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRILA",
+	  .val = SYSTEMZ_INSN_FORM_INSTRILA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRILB",
+	  .val = SYSTEMZ_INSN_FORM_INSTRILB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRILC",
+	  .val = SYSTEMZ_INSN_FORM_INSTRILC },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRIS",
+	  .val = SYSTEMZ_INSN_FORM_INSTRIS },
 	{ .str = "SYSTEMZ_INSN_FORM_INSTRR", .val = SYSTEMZ_INSN_FORM_INSTRR },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRD", .val = SYSTEMZ_INSN_FORM_INSTRRD },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRD",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRE", .val = SYSTEMZ_INSN_FORM_INSTRRE },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRD },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFA", .val = SYSTEMZ_INSN_FORM_INSTRRFA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRE",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFB", .val = SYSTEMZ_INSN_FORM_INSTRRFB },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRE },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFC", .val = SYSTEMZ_INSN_FORM_INSTRRFC },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFA",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFD", .val = SYSTEMZ_INSN_FORM_INSTRRFD },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRFA },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFE", .val = SYSTEMZ_INSN_FORM_INSTRRFE },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFB",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRRS", .val = SYSTEMZ_INSN_FORM_INSTRRS },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRFB },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSA", .val = SYSTEMZ_INSN_FORM_INSTRSA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFC",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSB", .val = SYSTEMZ_INSN_FORM_INSTRSB },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRFC },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSI", .val = SYSTEMZ_INSN_FORM_INSTRSI },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFD",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSLA", .val = SYSTEMZ_INSN_FORM_INSTRSLA },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRFD },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSLB", .val = SYSTEMZ_INSN_FORM_INSTRSLB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRFE",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSYA", .val = SYSTEMZ_INSN_FORM_INSTRSYA },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRFE },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRSYB", .val = SYSTEMZ_INSN_FORM_INSTRSYB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRRS",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRXA", .val = SYSTEMZ_INSN_FORM_INSTRXA },
+	  .val = SYSTEMZ_INSN_FORM_INSTRRS },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRXB", .val = SYSTEMZ_INSN_FORM_INSTRXB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSA",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRXE", .val = SYSTEMZ_INSN_FORM_INSTRXE },
+	  .val = SYSTEMZ_INSN_FORM_INSTRSA },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRXF", .val = SYSTEMZ_INSN_FORM_INSTRXF },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSB",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRXYA", .val = SYSTEMZ_INSN_FORM_INSTRXYA },
+	  .val = SYSTEMZ_INSN_FORM_INSTRSB },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTRXYB", .val = SYSTEMZ_INSN_FORM_INSTRXYB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSI",
+	  .val = SYSTEMZ_INSN_FORM_INSTRSI },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSLA",
+	  .val = SYSTEMZ_INSN_FORM_INSTRSLA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSLB",
+	  .val = SYSTEMZ_INSN_FORM_INSTRSLB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSYA",
+	  .val = SYSTEMZ_INSN_FORM_INSTRSYA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRSYB",
+	  .val = SYSTEMZ_INSN_FORM_INSTRSYB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRXA",
+	  .val = SYSTEMZ_INSN_FORM_INSTRXA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRXB",
+	  .val = SYSTEMZ_INSN_FORM_INSTRXB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRXE",
+	  .val = SYSTEMZ_INSN_FORM_INSTRXE },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRXF",
+	  .val = SYSTEMZ_INSN_FORM_INSTRXF },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRXYA",
+	  .val = SYSTEMZ_INSN_FORM_INSTRXYA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTRXYB",
+	  .val = SYSTEMZ_INSN_FORM_INSTRXYB },
 	{ .str = "SYSTEMZ_INSN_FORM_INSTS", .val = SYSTEMZ_INSN_FORM_INSTS },
 	{ .str = "SYSTEMZ_INSN_FORM_INSTSI", .val = SYSTEMZ_INSN_FORM_INSTSI },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSIL", .val = SYSTEMZ_INSN_FORM_INSTSIL },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSIL",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSIY", .val = SYSTEMZ_INSN_FORM_INSTSIY },
+	  .val = SYSTEMZ_INSN_FORM_INSTSIL },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSMI", .val = SYSTEMZ_INSN_FORM_INSTSMI },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSIY",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSSA", .val = SYSTEMZ_INSN_FORM_INSTSSA },
+	  .val = SYSTEMZ_INSN_FORM_INSTSIY },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSSB", .val = SYSTEMZ_INSN_FORM_INSTSSB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSMI",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSSC", .val = SYSTEMZ_INSN_FORM_INSTSSC },
+	  .val = SYSTEMZ_INSN_FORM_INSTSMI },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSSD", .val = SYSTEMZ_INSN_FORM_INSTSSD },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSSA",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSSE", .val = SYSTEMZ_INSN_FORM_INSTSSE },
+	  .val = SYSTEMZ_INSN_FORM_INSTSSA },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTSSF", .val = SYSTEMZ_INSN_FORM_INSTSSF },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSSB",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIA", .val = SYSTEMZ_INSN_FORM_INSTVRIA },
+	  .val = SYSTEMZ_INSN_FORM_INSTSSB },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIB", .val = SYSTEMZ_INSN_FORM_INSTVRIB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSSC",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIC", .val = SYSTEMZ_INSN_FORM_INSTVRIC },
+	  .val = SYSTEMZ_INSN_FORM_INSTSSC },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRID", .val = SYSTEMZ_INSN_FORM_INSTVRID },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSSD",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIE", .val = SYSTEMZ_INSN_FORM_INSTVRIE },
+	  .val = SYSTEMZ_INSN_FORM_INSTSSD },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIF", .val = SYSTEMZ_INSN_FORM_INSTVRIF },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSSE",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIG", .val = SYSTEMZ_INSN_FORM_INSTVRIG },
+	  .val = SYSTEMZ_INSN_FORM_INSTSSE },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIH", .val = SYSTEMZ_INSN_FORM_INSTVRIH },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTSSF",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRII", .val = SYSTEMZ_INSN_FORM_INSTVRII },
+	  .val = SYSTEMZ_INSN_FORM_INSTSSF },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRA", .val = SYSTEMZ_INSN_FORM_INSTVRRA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIA",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRB", .val = SYSTEMZ_INSN_FORM_INSTVRRB },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIA },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRC", .val = SYSTEMZ_INSN_FORM_INSTVRRC },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIB",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRD", .val = SYSTEMZ_INSN_FORM_INSTVRRD },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIB },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRE", .val = SYSTEMZ_INSN_FORM_INSTVRRE },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIC",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRF", .val = SYSTEMZ_INSN_FORM_INSTVRRF },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIC },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRG", .val = SYSTEMZ_INSN_FORM_INSTVRRG },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRID",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRH", .val = SYSTEMZ_INSN_FORM_INSTVRRH },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRID },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRI", .val = SYSTEMZ_INSN_FORM_INSTVRRI },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIE",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRJ", .val = SYSTEMZ_INSN_FORM_INSTVRRJ },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIE },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRK", .val = SYSTEMZ_INSN_FORM_INSTVRRK },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIF",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSA", .val = SYSTEMZ_INSN_FORM_INSTVRSA },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIF },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSB", .val = SYSTEMZ_INSN_FORM_INSTVRSB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIG",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSC", .val = SYSTEMZ_INSN_FORM_INSTVRSC },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIG },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSD", .val = SYSTEMZ_INSN_FORM_INSTVRSD },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRIH",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRV", .val = SYSTEMZ_INSN_FORM_INSTVRV },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRIH },
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVRX", .val = SYSTEMZ_INSN_FORM_INSTVRX },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRII",
-	{ .str = "SYSTEMZ_INSN_FORM_INSTVSI", .val = SYSTEMZ_INSN_FORM_INSTVSI },
+	  .val = SYSTEMZ_INSN_FORM_INSTVRII },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRA",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRB",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRC",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRC },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRD",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRD },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRE",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRE },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRF",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRF },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRG",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRG },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRH",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRH },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRI",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRI },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRJ",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRJ },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRRK",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRRK },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSA",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRSA },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSB",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRSB },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSC",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRSC },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRSD",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRSD },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRV",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRV },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVRX",
+	  .val = SYSTEMZ_INSN_FORM_INSTVRX },
+	{ .str = "SYSTEMZ_INSN_FORM_INSTVSI",
+	  .val = SYSTEMZ_INSN_FORM_INSTVSI },
 	{ .str = "SYSTEMZ_OP_IMM", .val = SYSTEMZ_OP_IMM },
 	{ .str = "SYSTEMZ_OP_MEM", .val = SYSTEMZ_OP_MEM },
 	{ .str = "SYSTEMZ_OP_REG", .val = SYSTEMZ_OP_REG },
@@ -1467,6 +1541,24 @@ static const cs_enum_id_map cs_enum_map[] = {
 	{ .str = "XCORE_OP_IMM", .val = XCORE_OP_IMM },
 	{ .str = "XCORE_OP_MEM", .val = XCORE_OP_MEM },
 	{ .str = "XCORE_OP_REG", .val = XCORE_OP_REG },
+	{ .str = "XTENSA_INSN_FORM_AEINST24",
+	  .val = XTENSA_INSN_FORM_AEINST24 },
+	{ .str = "XTENSA_INSN_FORM_BRI12", .val = XTENSA_INSN_FORM_BRI12 },
+	{ .str = "XTENSA_INSN_FORM_CALL", .val = XTENSA_INSN_FORM_CALL },
+	{ .str = "XTENSA_INSN_FORM_CALLX", .val = XTENSA_INSN_FORM_CALLX },
+	{ .str = "XTENSA_INSN_FORM_EE_INST24",
+	  .val = XTENSA_INSN_FORM_EE_INST24 },
+	{ .str = "XTENSA_INSN_FORM_RI16", .val = XTENSA_INSN_FORM_RI16 },
+	{ .str = "XTENSA_INSN_FORM_RI7", .val = XTENSA_INSN_FORM_RI7 },
+	{ .str = "XTENSA_INSN_FORM_RRI4", .val = XTENSA_INSN_FORM_RRI4 },
+	{ .str = "XTENSA_INSN_FORM_RRI8", .val = XTENSA_INSN_FORM_RRI8 },
+	{ .str = "XTENSA_INSN_FORM_RRR", .val = XTENSA_INSN_FORM_RRR },
+	{ .str = "XTENSA_INSN_FORM_RRRN", .val = XTENSA_INSN_FORM_RRRN },
+	{ .str = "XTENSA_INSN_FORM_RSR", .val = XTENSA_INSN_FORM_RSR },
+	{ .str = "XTENSA_OP_IMM", .val = XTENSA_OP_IMM },
+	{ .str = "XTENSA_OP_L32R", .val = XTENSA_OP_L32R },
+	{ .str = "XTENSA_OP_MEM", .val = XTENSA_OP_MEM },
+	{ .str = "XTENSA_OP_REG", .val = XTENSA_OP_REG },
 	{ .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzx",
 	  .val = 0xffffff }, // For testing
 	{ .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz",

suite/cstest/src/test_detail.c

@@ -127,6 +127,9 @@ TestDetail *test_detail_clone(TestDetail *detail)
 	if (detail->m68k) {
 		clone->m68k = test_detail_m68k_clone(detail->m68k);
 	}
+	if (detail->xtensa) {
+		clone->xtensa = test_detail_xtensa_clone(detail->xtensa);
+	}
 
 	return clone;
 }
@@ -225,7 +228,9 @@ void test_detail_free(TestDetail *detail)
 	if (detail->m68k) {
 		test_detail_m68k_free(detail->m68k);
 	}
-
+	if (detail->xtensa) {
+		test_detail_xtensa_free(detail->xtensa);
+	}
 	cs_mem_free(detail);
 }
 
@@ -404,5 +409,9 @@ bool test_expected_detail(csh *handle, const cs_insn *insn,
 		return test_expected_m68k(handle, &actual->m68k,
 					  expected->m68k);
 	}
+	if (expected->xtensa) {
+		return test_expected_xtensa(handle, &actual->xtensa,
+					    expected->xtensa);
+	}
 	return true;
 }

suite/cstest/src/test_detail_xtensa.c

@@ -0,0 +1,111 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// Copyright © 2024 Billow <billow.fun@gmail.com>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+#include <test_detail_xtensa.h>
+
+TestDetailXtensa *test_detail_xtensa_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailXtensa), 1);
+}
+
+void test_detail_xtensa_free(TestDetailXtensa *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_xtensa_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->format);
+	cs_mem_free(detail);
+}
+
+TestDetailXtensa *test_detail_xtensa_clone(const TestDetailXtensa *detail)
+{
+	TestDetailXtensa *clone = test_detail_xtensa_new();
+	clone->format = detail->format ? strdup(detail->format) : NULL;
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailXtensaOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_xtensa_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailXtensaOp *test_detail_xtensa_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailXtensaOp), 1);
+}
+
+TestDetailXtensaOp *test_detail_xtensa_op_clone(const TestDetailXtensaOp *op)
+{
+	TestDetailXtensaOp *clone = test_detail_xtensa_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_xtensa_op_free(TestDetailXtensaOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_xtensa(csh *handle, const cs_xtensa *actual,
+			  const TestDetailXtensa *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_enum_ret(actual->format, expected->format, false);
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_xtensa_op *op = &actual->operands[i];
+		TestDetailXtensaOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"xtensa op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case XTENSA_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case XTENSA_OP_L32R:
+		case XTENSA_OP_IMM:
+			compare_int32_ret(op->imm, eop->imm, false);
+			break;
+		case XTENSA_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_int32_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}

suite/fuzz/drivermc.c

@@ -91,10 +91,12 @@ int main(int argc, char** argv)
                 Data[0] = 24;
             } else if (strcmp(arch, "CS_ARCH_EVM") == 0 && strcmp(mode, "0") == 0) {
                 Data[0] = 25;
-            } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA") == 0) {
+            } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA_ESP32") == 0) {
                 Data[0] = 26;
-            } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA+CS_MODE_BIG_ENDIAN") == 0) {
+            } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA_ESP32S2") == 0) {
                 Data[0] = 27;
+            } else if (strcmp(arch, "CS_ARCH_XTENSA") == 0 && strcmp(mode, "CS_MODE_XTENSA_ESP8266") == 0) {
+                Data[0] = 28;
             } else if (strcmp(arch, "CS_ARCH_BPF") == 0 && strstr(mode, "CS_MODE_BPF_CLASSIC") != NULL) {
                 Data[0] = 29;
             } else if (strcmp(arch, "CS_ARCH_BPF") == 0 && strstr(mode, "CS_MODE_BPF_EXTENDED") != NULL) {

suite/fuzz/fuzz_diff.c

@@ -175,14 +175,20 @@ struct platform platforms[] = {
     {
         //item 26
         CS_ARCH_XTENSA,
-        (cs_mode)CS_MODE_XTENSA,
+        (cs_mode)CS_MODE_XTENSA_ESP32,
-        "Xtensa"
+        "Xtensa ESP32"
     },
     {
         //item 27
         CS_ARCH_XTENSA,
-        (cs_mode)CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN,
+        (cs_mode)CS_MODE_XTENSA_ESP32S2,
-        "Xtensa (Big-Endian)"
+        "Xtensa ESP32S2"
+    },
+    {
+        //item 28
+        CS_ARCH_XTENSA,
+        (cs_mode)CS_MODE_XTENSA_ESP8266,
+        "Xtensa ESP8266"
     },
 };
 

suite/fuzz/fuzz_harness.c

@@ -119,13 +119,18 @@ int main(int argc, char **argv)
     },
     {
         CS_ARCH_XTENSA,
-        (cs_mode)CS_MODE_XTENSA,
+        (cs_mode)CS_MODE_XTENSA_ESP32,
-        "Xtensa"
+        "Xtensa ESP32"
     },
     {
         CS_ARCH_XTENSA,
-        (cs_mode)CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN,
+        (cs_mode)CS_MODE_XTENSA_ESP32S2,
-        "Xtensa (Big-Endian)"
+        "Xtensa ESP32S2"
+    },
+    {
+        CS_ARCH_XTENSA,
+        (cs_mode)CS_MODE_XTENSA_ESP8266,
+        "Xtensa ESP8266"
     },
   };
 

suite/fuzz/platform.c

@@ -381,15 +381,21 @@ struct platform platforms[] = {
 		},
 		{
 				CS_ARCH_XTENSA,
-				CS_MODE_XTENSA,
+				CS_MODE_XTENSA_ESP32,
-				"XTENSA",
+				"XTENSA ESP32",
-				"xtensa"
+				"esp32"
 		},
 		{
 				CS_ARCH_XTENSA,
-				CS_MODE_XTENSA + CS_MODE_BIG_ENDIAN,
+				CS_MODE_XTENSA_ESP32S2,
-				"XTENSA (Big-Endian)",
+				"XTENSA ESP32S2",
-				"xtensabe"
+				"esp32s2"
+		},
+		{
+				CS_ARCH_XTENSA,
+				CS_MODE_XTENSA_ESP8266,
+				"XTENSA ESP8266",
+				"esp8266"
 		},
 	// dummy entry to mark the end of this array.
 		// DO NOT DELETE THIS

tests/MC/Xtensa/l32r.yaml

@@ -0,0 +1,25 @@
+test_cases:
+  - input:
+      bytes: [ 0x01,0x00,0x00 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "l32r a0, . -0x40000"
+  - input:
+      bytes: [ 0xf1,0x00,0x00 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "l32r a15, . -0x40000"
+  - input:
+      bytes: [ 0x01,0xff,0xff ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "l32r a0, . -0x4"

tests/details/xtensa.yaml

@@ -0,0 +1,67 @@
+test_cases:
+  - input:
+      bytes: [ 0x60, 0x51, 0x60, 0x1a, 0x23 ]
+      arch: "CS_ARCH_XTENSA"
+      options: [ CS_OPT_DETAIL ]
+    expected:
+      insns:
+        - asm_text: "abs a5, a6"
+          details:
+            xtensa:
+              format: XTENSA_INSN_FORM_RRR
+              operands:
+                - type: XTENSA_OP_REG
+                  reg: a5
+                  access: CS_AC_WRITE
+                - type: XTENSA_OP_REG
+                  reg: a6
+                  access: CS_AC_READ
+        - asm_text: "add.n a2, a3, a1"
+          details:
+            xtensa:
+              format: XTENSA_INSN_FORM_RRRN
+              operands:
+                - type: XTENSA_OP_REG
+                  reg: a2
+                  access: CS_AC_WRITE
+                - type: XTENSA_OP_REG
+                  reg: a3
+                  access: CS_AC_READ
+                - type: XTENSA_OP_REG
+                  reg: a1
+                  access: CS_AC_READ
+  - input:
+      bytes: [ 0x18, 0x23 ]
+      arch: "CS_ARCH_XTENSA"
+      options: [ CS_OPT_DETAIL ]
+    expected:
+      insns:
+        - asm_text: "l32i.n a1, a3, 8"
+          details:
+            xtensa:
+              format: XTENSA_INSN_FORM_RRRN
+              operands:
+                - type: XTENSA_OP_REG
+                  reg: a1
+                  access: CS_AC_WRITE
+                - type: XTENSA_OP_MEM
+                  mem_base: a3
+                  mem_disp: 8
+                  access: CS_AC_READ
+  - input:
+      bytes: [ 0x12, 0xaf, 0xff ]
+      arch: "CS_ARCH_XTENSA"
+      options: [ CS_OPT_DETAIL ]
+    expected:
+      insns:
+        - asm_text: "movi a1, -1"
+          details:
+            xtensa:
+              format: XTENSA_INSN_FORM_RRI8
+              operands:
+                - type: XTENSA_OP_REG
+                  reg: a1
+                  access: CS_AC_WRITE
+                - type: XTENSA_OP_IMM
+                  imm: -1
+                  access: CS_AC_READ

tests/integration/test_litbase.c

@@ -45,7 +45,7 @@ static void test()
 	csh handle;
 	cs_err err;
 
-	err = cs_open(CS_ARCH_XTENSA, CS_MODE_XTENSA, &handle);
+	err = cs_open(CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32, &handle);
 	if (err) {
 		if (cs_support(CS_ARCH_XTENSA)) {
 			printf("Failed on cs_open() with error returned: %u\n",
@@ -74,8 +74,8 @@ static void test()
 			  0x100000, 2, &insn);
 
 	// 2. Now print out the instruction in newly customized setup.
-	check_insn(insn, "l32r", "a1, . 0xbffff");
+	check_insn(insn, "l32r", "a1, . 0xfffbf000");
-	check_insn(insn + 1, "l32r", "a1, . 0xffffb");
+	check_insn(insn + 1, "l32r", "a1, . 0xffffeffc");
 	print_insn(insn, count);
 
 	// Done