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arm: support asm syntax CS_OPT_SYNTAX_NOREGNAME to print out registers with numbers (ex: 'r11' rather than 'fp')

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Nguyen Anh Quynh 2014-03-11 00:18:50 +08:00
parent 1a39bb59e1
commit 2ff665ad4a
7 changed files with 355 additions and 92 deletions
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232
arch/ARM/ARMGenAsmWriter.inc
View File

@ -8416,6 +8416,238 @@ static char *getRegisterName(unsigned RegNo)
#endif
}
// get registers with number only
static char *getRegisterName2(unsigned RegNo)
{
// assert(RegNo && RegNo < 289 && "Invalid register number!");
#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
/* 39 */ 'd', '1', '0', 0,
/* 43 */ 'q', '1', '0', 0,
/* 47 */ 'r', '1', '0', 0,
/* 51 */ 's', '1', '0', 0,
/* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
/* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
/* 87 */ 'd', '2', '0', 0,
/* 91 */ 's', '2', '0', 0,
/* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
/* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
/* 127 */ 'd', '3', '0', 0,
/* 131 */ 's', '3', '0', 0,
/* 135 */ 'd', '0', 0,
/* 138 */ 'q', '0', 0,
/* 141 */ 'm', 'v', 'f', 'r', '0', 0,
/* 147 */ 's', '0', 0,
/* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
/* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
/* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
/* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
/* 196 */ 'd', '1', '1', 0,
/* 200 */ 'q', '1', '1', 0,
/* 204 */ 'r', '1', '1', 0,
/* 208 */ 's', '1', '1', 0,
/* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
/* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
/* 240 */ 'd', '2', '1', 0,
/* 244 */ 's', '2', '1', 0,
/* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
/* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
/* 276 */ 'd', '3', '1', 0,
/* 280 */ 's', '3', '1', 0,
/* 284 */ 'Q', '0', '_', 'Q', '1', 0,
/* 290 */ 'R', '0', '_', 'R', '1', 0,
/* 296 */ 'd', '1', 0,
/* 299 */ 'q', '1', 0,
/* 302 */ 'm', 'v', 'f', 'r', '1', 0,
/* 308 */ 's', '1', 0,
/* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
/* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
/* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
/* 355 */ 'd', '1', '2', 0,
/* 359 */ 'q', '1', '2', 0,
/* 363 */ 'r', '1', '2', 0,
/* 367 */ 's', '1', '2', 0,
/* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
/* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
/* 403 */ 'd', '2', '2', 0,
/* 407 */ 's', '2', '2', 0,
/* 411 */ 'D', '0', '_', 'D', '2', 0,
/* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
/* 426 */ 'Q', '1', '_', 'Q', '2', 0,
/* 432 */ 'd', '2', 0,
/* 435 */ 'q', '2', 0,
/* 438 */ 'm', 'v', 'f', 'r', '2', 0,
/* 444 */ 's', '2', 0,
/* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
/* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
/* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
/* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
/* 497 */ 'd', '1', '3', 0,
/* 501 */ 'q', '1', '3', 0,
/* 505 */ 's', '1', '3', 0,
/* 509 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
/* 525 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
/* 537 */ 'd', '2', '3', 0,
/* 541 */ 's', '2', '3', 0,
/* 545 */ 'D', '1', '_', 'D', '3', 0,
/* 551 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
/* 560 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
/* 572 */ 'R', '2', '_', 'R', '3', 0,
/* 578 */ 'd', '3', 0,
/* 581 */ 'q', '3', 0,
/* 584 */ 'r', '3', 0,
/* 587 */ 's', '3', 0,
/* 590 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
/* 605 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
/* 621 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
/* 637 */ 'd', '1', '4', 0,
/* 641 */ 'q', '1', '4', 0,
/* 645 */ 's', '1', '4', 0,
/* 649 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
/* 665 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
/* 681 */ 'd', '2', '4', 0,
/* 685 */ 's', '2', '4', 0,
/* 689 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
/* 698 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
/* 710 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
/* 722 */ 'd', '4', 0,
/* 725 */ 'q', '4', 0,
/* 728 */ 'r', '4', 0,
/* 731 */ 's', '4', 0,
/* 734 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
/* 749 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
/* 761 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
/* 777 */ 'd', '1', '5', 0,
/* 781 */ 'q', '1', '5', 0,
/* 785 */ 's', '1', '5', 0,
/* 789 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
/* 805 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
/* 817 */ 'd', '2', '5', 0,
/* 821 */ 's', '2', '5', 0,
/* 825 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
/* 834 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
/* 843 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
/* 855 */ 'R', '4', '_', 'R', '5', 0,
/* 861 */ 'd', '5', 0,
/* 864 */ 'q', '5', 0,
/* 867 */ 'r', '5', 0,
/* 870 */ 's', '5', 0,
/* 873 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
/* 889 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
/* 905 */ 'd', '1', '6', 0,
/* 909 */ 's', '1', '6', 0,
/* 913 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
/* 929 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
/* 945 */ 'd', '2', '6', 0,
/* 949 */ 's', '2', '6', 0,
/* 953 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
/* 965 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
/* 977 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
/* 989 */ 'd', '6', 0,
/* 992 */ 'q', '6', 0,
/* 995 */ 'r', '6', 0,
/* 998 */ 's', '6', 0,
/* 1001 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
/* 1017 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
/* 1029 */ 'd', '1', '7', 0,
/* 1033 */ 's', '1', '7', 0,
/* 1037 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
/* 1053 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
/* 1065 */ 'd', '2', '7', 0,
/* 1069 */ 's', '2', '7', 0,
/* 1073 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
/* 1085 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
/* 1094 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
/* 1106 */ 'R', '6', '_', 'R', '7', 0,
/* 1112 */ 'd', '7', 0,
/* 1115 */ 'q', '7', 0,
/* 1118 */ 'r', '7', 0,
/* 1121 */ 's', '7', 0,
/* 1124 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
/* 1140 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
/* 1156 */ 'd', '1', '8', 0,
/* 1160 */ 's', '1', '8', 0,
/* 1164 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
/* 1180 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
/* 1196 */ 'd', '2', '8', 0,
/* 1200 */ 's', '2', '8', 0,
/* 1204 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
/* 1216 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
/* 1228 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
/* 1240 */ 'd', '8', 0,
/* 1243 */ 'q', '8', 0,
/* 1246 */ 'r', '8', 0,
/* 1249 */ 's', '8', 0,
/* 1252 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
/* 1268 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
/* 1280 */ 'd', '1', '9', 0,
/* 1284 */ 's', '1', '9', 0,
/* 1288 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
/* 1304 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
/* 1316 */ 'd', '2', '9', 0,
/* 1320 */ 's', '2', '9', 0,
/* 1324 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
/* 1336 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
/* 1345 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
/* 1357 */ 'R', '8', '_', 'R', '9', 0,
/* 1363 */ 'd', '9', 0,
/* 1366 */ 'q', '9', 0,
/* 1369 */ 'r', '9', 0,
/* 1372 */ 's', '9', 0,
/* 1375 */ 'R', '1', '2', '_', 'S', 'P', 0,
/* 1382 */ 'p', 'c', 0,
/* 1385 */ 'f', 'p', 'e', 'x', 'c', 0,
/* 1391 */ 'f', 'p', 's', 'i', 'd', 0,
/* 1397 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
/* 1405 */ 's', 'p', 0,
/* 1408 */ 'f', 'p', 's', 'c', 'r', 0,
/* 1414 */ 'l', 'r', 0,
/* 1417 */ 'a', 'p', 's', 'r', 0,
/* 1422 */ 'c', 'p', 's', 'r', 0,
/* 1427 */ 's', 'p', 's', 'r', 0,
/* 1432 */ 'f', 'p', 'i', 'n', 's', 't', 0,
/* 1439 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
/* 1450 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
};
static const uint32_t RegAsmOffset[] = {
1417, 1450, 1422, 1385, 1432, 1408, 1439, 1391, 1397, 1414, 1382, 1405, 1427, 135,
296, 432, 578, 722, 861, 989, 1112, 1240, 1363, 39, 196, 355, 497, 637,
777, 905, 1029, 1156, 1280, 87, 240, 403, 537, 681, 817, 945, 1065, 1196,
1316, 127, 276, 447, 141, 302, 438, 138, 299, 435, 581, 725, 864, 992,
1115, 1243, 1366, 43, 200, 359, 501, 641, 781, 144, 305, 441, 584, 728,
867, 995, 1118, 1246, 1369, 47, 204, 363, 147, 308, 444, 587, 731, 870,
998, 1121, 1249, 1372, 51, 208, 367, 505, 645, 785, 909, 1033, 1160, 1284,
91, 244, 407, 541, 685, 821, 949, 1069, 1200, 1320, 131, 280, 411, 545,
692, 828, 959, 1079, 1210, 1330, 6, 167, 317, 461, 597, 741, 881, 1009,
1132, 1260, 63, 232, 379, 517, 657, 797, 921, 1045, 1172, 1296, 103, 268,
284, 426, 566, 716, 849, 983, 1100, 1234, 1351, 32, 180, 347, 489, 629,
769, 560, 710, 843, 977, 1094, 1228, 1345, 26, 174, 340, 481, 621, 761,
1375, 290, 572, 855, 1106, 1357, 188, 417, 551, 701, 834, 968, 1085, 1219,
1336, 16, 150, 328, 469, 609, 749, 893, 1017, 1144, 1268, 75, 212, 391,
525, 669, 805, 933, 1053, 1184, 1304, 115, 248, 689, 825, 956, 1076, 1207,
1327, 3, 164, 314, 458, 593, 737, 877, 1005, 1128, 1256, 59, 228, 375,
513, 653, 793, 917, 1041, 1168, 1292, 99, 264, 953, 1073, 1204, 1324, 0,
161, 311, 455, 590, 734, 873, 1001, 1124, 1252, 55, 224, 371, 509, 649,
789, 913, 1037, 1164, 1288, 95, 260, 420, 704, 971, 1222, 19, 332, 613,
897, 1148, 79, 395, 673, 937, 1188, 119, 698, 965, 1216, 13, 325, 605,
889, 1140, 71, 387, 665, 929, 1180, 111,
};
//int i;
//for (i = 0; i < sizeof(RegAsmOffset)/4; i++)
// printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
//printf("*************************\n");
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;
#endif
}
#ifdef PRINT_ALIAS_INSTR
#undef PRINT_ALIAS_INSTR

176
arch/ARM/ARMInstPrinter.c
View File

@ -33,7 +33,7 @@
#define GET_SUBTARGETINFO_ENUM
#include "ARMGenSubtargetInfo.inc"
static void printRegName(SStream *OS, unsigned RegNo);
static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo);
// Autogenerated by tblgen.
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
@ -143,6 +143,14 @@ static void set_mem_access(MCInst *MI, bool status)
//#define PRINT_ALIAS_INSTR
#include "ARMGenAsmWriter.inc"
void ARM_getRegName(cs_struct *handle, int value)
{
if (value == CS_OPT_SYNTAX_NOREGNAME)
handle->get_regname = getRegisterName2;
else
handle->get_regname = getRegisterName;
}
#define UseMarkup false
#define markup(x) (UseMarkup? (x) : "")
@ -183,11 +191,13 @@ static void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc,
}
}
static void printRegName(SStream *OS, unsigned RegNo)
static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo)
{
#ifndef CAPSTONE_DIET
SStream_concat(OS, markup("<reg:"));
SStream_concat(OS, getRegisterName(RegNo));
SStream_concat(OS, h->get_regname(RegNo));
SStream_concat(OS, markup(">"));
#endif
}
static name_map insn_update_flgs[] = {
@ -306,7 +316,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
printPredicateOperand(MI, 4, O);
SStream_concat(O, "\t");
printRegName(O, MCOperand_getReg(Dst));
printRegName(MI->csh, O, MCOperand_getReg(Dst));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(Dst);
@ -314,7 +324,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
@ -323,7 +333,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO2);
@ -344,7 +354,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
printPredicateOperand(MI, 3, O);
SStream_concat(O, "\t");
printRegName(O, MCOperand_getReg(Dst));
printRegName(MI->csh, O, MCOperand_getReg(Dst));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(Dst);
@ -352,7 +362,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
@ -401,7 +411,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
SStream_concat(O, "push");
printPredicateOperand(MI, 4, O);
SStream_concat(O, "\t{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 1)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
@ -434,7 +444,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
SStream_concat(O, "pop");
printPredicateOperand(MI, 5, O);
SStream_concat(O, "\t{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, 0)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
@ -482,7 +492,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
printPredicateOperand(MI, 1, O);
SStream_concat(O, "\t");
printRegName(O, BaseReg);
printRegName(MI->csh, O, BaseReg);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = BaseReg;
@ -541,7 +551,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
MCOperand *Op = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(Op)) {
unsigned Reg = MCOperand_getReg(Op);
printRegName(O, Reg);
printRegName(MI->csh, O, Reg);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
if (MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base == ARM_REG_INVALID)
@ -629,7 +639,7 @@ static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
MCOperand *MO3 = MCInst_getOperand(MI, OpNum+2);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
@ -647,7 +657,7 @@ static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
return;
SStream_concat(O, " ");
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count - 1].shift.value = MCOperand_getReg(MO2);
//assert(ARM_AM_getSORegOffset(MO3.getImm()) == 0);
@ -658,7 +668,7 @@ static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
@ -685,7 +695,7 @@ static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
}
@ -711,7 +721,7 @@ static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O)
SStream_concat(O, ", ");
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO3))));
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
}
@ -728,11 +738,11 @@ static void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O)
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat(O, "]%s", markup(">"));
@ -745,11 +755,11 @@ static void printAddrModeTBH(MCInst *MI, unsigned Op, SStream *O)
MCOperand *MO2 = MCInst_getOperand(MI, Op+1);
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
SStream_concat(O, ", lsl %s #1%s]%s", markup("<imm:"), markup(">"), markup(">"));
@ -796,7 +806,7 @@ static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
}
SStream_concat(O, ARM_AM_getAddrOpcStr(getAM2Op((unsigned int)MCOperand_getImm(MO2))));
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
@ -820,7 +830,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, "], %s", markup(">"));
@ -828,7 +838,7 @@ static void printAM3PostIndexOp(MCInst *MI, unsigned Op, SStream *O)
if (MCOperand_getReg(MO2)) {
SStream_concat(O, "%c", (char)op);
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO2);
@ -869,13 +879,13 @@ static void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, SStream *O,
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
if (MCOperand_getReg(MO2)) {
SStream_concat(O, ", %s", ARM_AM_getAddrOpcStr(op));
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
if (op)
@ -937,7 +947,7 @@ static void printAddrMode3OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (MCOperand_getReg(MO1)) {
SStream_concat(O, ARM_AM_getAddrOpcStr(op));
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].imm = MCOperand_getReg(MO1);
@ -990,7 +1000,7 @@ static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
SStream_concat(O, (MCOperand_getImm(MO2) ? "" : "-"));
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO1);
@ -1022,7 +1032,7 @@ static void printAddrMode5Operand(MCInst *MI, unsigned OpNum, SStream *O,
}
SStream_concat(O, "%s[", markup("<mem:"));
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
unsigned ImmOffs = ARM_AM_getAM5Offset((unsigned int)MCOperand_getImm(MO2));
unsigned Op = ARM_AM_getAM5Op((unsigned int)MCOperand_getImm(MO2));
@ -1046,7 +1056,7 @@ static void printAddrMode6Operand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned tmp = (unsigned int)MCOperand_getImm(MO2);
@ -1067,7 +1077,7 @@ static void printAddrMode7Operand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *MO1 = MCInst_getOperand(MI, OpNum);
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
SStream_concat(O, "]%s", markup(">"));
@ -1081,7 +1091,7 @@ static void printAddrMode6OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O)
SStream_concat(O, "!");
else {
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO));
printRegName(MI->csh, O, MCOperand_getReg(MO));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MO);
@ -1200,7 +1210,7 @@ static void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O)
unsigned i, e;
for (i = OpNum, e = MCInst_getNumOperands(MI); i != e; ++i) {
if (i != OpNum) SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, i)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, i)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, i));
@ -1214,14 +1224,14 @@ static void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O,
MCRegisterInfo *MRI)
{
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
printRegName(O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_0);
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
printRegName(MI->csh, O, MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCRegisterInfo_getSubReg(MRI, Reg, ARM_gsub_1);
@ -1536,13 +1546,13 @@ static void printThumbAddrModeRROperand(MCInst *MI, unsigned Op, SStream *O)
SStream_concat(O, markup("<mem:"));
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned RegNum = MCOperand_getReg(MO2);
if (RegNum) {
SStream_concat(O, ", ");
printRegName(O, RegNum);
printRegName(MI->csh, O, RegNum);
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = RegNum;
}
@ -1565,7 +1575,7 @@ static void printThumbAddrModeImm5SOperand(MCInst *MI, unsigned Op, SStream *O,
SStream_concat(O, markup("<mem:"));
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
unsigned ImmOffs = (unsigned int)MCOperand_getImm(MO2);
@ -1615,7 +1625,7 @@ static void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O)
MCOperand *MO2 = MCInst_getOperand(MI, OpNum+1);
unsigned Reg = MCOperand_getReg(MO1);
printRegName(O, Reg);
printRegName(MI->csh, O, Reg);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg;
@ -1644,7 +1654,7 @@ static void printAddrModeImm12Operand(MCInst *MI, unsigned OpNum,
SStream_concat(O, markup("<mem:"));
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
@ -1679,7 +1689,7 @@ static void printT2AddrModeImm8Operand(MCInst *MI, unsigned OpNum, SStream *O,
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
@ -1720,7 +1730,7 @@ static void printT2AddrModeImm8s4Operand(MCInst *MI,
SStream_concat(O, markup("<mem:"));
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
@ -1755,7 +1765,7 @@ static void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStrea
SStream_concat(O, markup("<mem:"));
SStream_concat(O, "[");
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
if (MCOperand_getImm(MO2)) {
@ -1846,13 +1856,13 @@ static void printT2AddrModeSoRegOperand(MCInst *MI,
SStream_concat(O, "%s[", markup("<mem:"));
set_mem_access(MI, true);
printRegName(O, MCOperand_getReg(MO1));
printRegName(MI->csh, O, MCOperand_getReg(MO1));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.base = MCOperand_getReg(MO1);
//assert(MCOperand_getReg(MO2.getReg() && "Invalid so_reg load / store address!");
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MO2));
printRegName(MI->csh, O, MCOperand_getReg(MO2));
if (MI->csh->detail)
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].mem.index = MCOperand_getReg(MO2);
@ -1982,7 +1992,7 @@ static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O)
static void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
@ -1998,14 +2008,14 @@ static void printVectorListTwo(MCInst *MI, unsigned OpNum,
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
SStream_concat(O, "{");
printRegName(O, Reg0);
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, Reg1);
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
@ -2021,14 +2031,14 @@ static void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum,
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
SStream_concat(O, "{");
printRegName(O, Reg0);
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, Reg1);
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
@ -2043,21 +2053,21 @@ static void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O)
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
@ -2072,28 +2082,28 @@ static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
@ -2105,7 +2115,7 @@ static void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O)
static void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
{
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
@ -2121,14 +2131,14 @@ static void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum,
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_1);
SStream_concat(O, "{");
printRegName(O, Reg0);
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, Reg1);
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
@ -2143,21 +2153,21 @@ static void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
@ -2172,28 +2182,28 @@ static void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O)
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 1;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 3;
@ -2209,14 +2219,14 @@ static void printVectorListTwoSpacedAllLanes(MCInst *MI,
unsigned Reg0 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_0);
unsigned Reg1 = MCRegisterInfo_getSubReg(MRI, Reg, ARM_dsub_2);
SStream_concat(O, "{");
printRegName(O, Reg0);
printRegName(MI->csh, O, Reg0);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg0;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, Reg1);
printRegName(MI->csh, O, Reg1);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = Reg1;
@ -2232,21 +2242,21 @@ static void printVectorListThreeSpacedAllLanes(MCInst *MI,
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
@ -2262,28 +2272,28 @@ static void printVectorListFourSpacedAllLanes(MCInst *MI,
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, "[], ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;
@ -2298,21 +2308,21 @@ static void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O)
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
@ -2327,28 +2337,28 @@ static void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O)
// addition to get the next register, but for VFP registers, the
// sort order is guaranteed because they're all of the form D<n>.
SStream_concat(O, "{");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)));
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 2;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 4;
MI->flat_insn.arm.op_count++;
}
SStream_concat(O, ", ");
printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
printRegName(MI->csh, O, MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6);
if (MI->csh->detail) {
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].type = ARM_OP_REG;
MI->flat_insn.arm.operands[MI->flat_insn.arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + 6;

3
arch/ARM/ARMInstPrinter.h
View File

@ -24,4 +24,7 @@
void ARM_printInst(MCInst *MI, SStream *O, void *Info);
void ARM_post_printer(csh handle, cs_insn *pub_insn, char *mnem);
// setup handle->get_regname
void ARM_getRegName(cs_struct *handle, int value);
#endif

21
arch/ARM/ARMModule.c
View File

@ -19,6 +19,7 @@ static cs_err init(cs_struct *ud)
mri = cs_mem_malloc(sizeof(*mri));
ARM_init(mri);
ARM_getRegName(ud, 0); // use default get_regname
ud->printer = ARM_printInst;
ud->printer_info = mri;
@ -37,13 +38,21 @@ static cs_err init(cs_struct *ud)
static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_MODE) {
if (value & CS_MODE_THUMB)
handle->disasm = Thumb_getInstruction;
else
handle->disasm = ARM_getInstruction;
switch(type) {
case CS_OPT_MODE:
if (value & CS_MODE_THUMB)
handle->disasm = Thumb_getInstruction;
else
handle->disasm = ARM_getInstruction;
handle->mode = value;
handle->mode = value;
break;
case CS_OPT_SYNTAX:
ARM_getRegName(handle, (int)value);
handle->syntax = (int)value;
break;
default:
break;
}
return CS_ERR_OK;

6
cs_priv.h
View File

@ -25,6 +25,9 @@ typedef bool (*CheckCombineInsn_t)(cs_struct *h, cs_insn *insn);
typedef void (*CombineInsn_t)(cs_struct *h, cs_insn *insn, cs_insn *prev);
// return register name, given register ID
typedef char *(*GetRegisterName_t)(unsigned RegNo);
// for ARM only
typedef struct ARM_ITStatus {
unsigned char ITStates[128]; // FIXME
@ -46,11 +49,12 @@ struct cs_struct {
cs_err errnum;
ARM_ITStatus ITBlock; // for Arm only
cs_opt_value detail;
int syntax; // asm syntax for simple printer such as PPC
int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
bool doing_mem; // handling memory operand in InstPrinter code
unsigned short *insn_cache; // index caching for mapping.c
CheckCombineInsn_t check_combine;
CombineInsn_t combine;
GetRegisterName_t get_regname;
uint8_t prev_prefix; // save previous prefix for combining instructions - X86 only.
};

2
include/capstone.h
View File

@ -94,7 +94,7 @@ typedef enum cs_opt_value {
CS_OPT_SYNTAX_DEFAULT = 0, // Default asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_INTEL, // X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_ATT, // X86 ATT asm syntax (CS_OPT_SYNTAX).
CS_OPT_SYNTAX_NOREGNAME, // PPC asm syntax: Prints register name with only number (CS_OPT_SYNTAX)
CS_OPT_SYNTAX_NOREGNAME, // Prints register name with only number (CS_OPT_SYNTAX)
} cs_opt_value;

7
tests/test_arm.c
View File

@ -15,6 +15,7 @@ struct platform {
unsigned char *code;
size_t size;
char *comment;
int syntax;
};
static void print_string_hex(char *comment, unsigned char *str, int len)
@ -184,7 +185,8 @@ static void test()
.mode = CS_MODE_THUMB,
.code = (unsigned char *)THUMB_CODE2,
.size = sizeof(THUMB_CODE2) - 1,
.comment = "Thumb-2"
.comment = "Thumb-2 & register named with numbers",
.syntax = CS_OPT_SYNTAX_NOREGNAME
},
};
@ -201,6 +203,9 @@ static void test()
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
if (platforms[i].syntax)
cs_option(handle, CS_OPT_SYNTAX, platforms[i].syntax);
size_t count = cs_disasm_ex(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
if (count) {
printf("****************\n");