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update TriCore*.inc

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This commit is contained in:
billow 2023-03-23 20:17:04 +08:00
parent 1a148e2b65
commit 33080bb326
12 changed files with 11284 additions and 2908 deletions
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253
arch/TriCore/TriCoreDisassembler.c
View File

@ -273,7 +273,7 @@ static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
// Decode s1/d.
switch(MCInst_getOpcode(Inst)) {
case TriCore_ADDsrc:
case TriCore_ADD_src:
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
if (status == MCDisassembler_Success)
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
@ -304,14 +304,14 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
// Decode s1/d.
switch(MCInst_getOpcode(Inst)) {
case TriCore_MOV_AAsrr:
case TriCore_MOV_AA_srr:
status = DecodeAddrRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
case TriCore_ADDsrr:
case TriCore_MULsrr:
case TriCore_ANDsrr:
case TriCore_ORsrr:
case TriCore_XORsrr:
case TriCore_ADD_srr:
case TriCore_MUL_srr:
case TriCore_AND_srr:
case TriCore_OR_srr:
case TriCore_XOR_srr:
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
if (status == MCDisassembler_Success)
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
@ -326,7 +326,7 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
// Decode s2.
switch(MCInst_getOpcode(Inst)) {
case TriCore_MOV_AAsrr:
case TriCore_MOV_AA_srr:
status = DecodeAddrRegsRegisterClass(Inst, s2, Address, Decoder);
break;
default:
@ -359,16 +359,16 @@ static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
// Decode s1_d.
switch (MCInst_getOpcode(Inst)) {
case TriCore_LD_Aabs:
case TriCore_ST_Aabs:
case TriCore_LD_A_abs:
case TriCore_ST_A_abs:
status = DecodeAddrRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
case TriCore_LD_Dabs:
case TriCore_ST_Dabs:
case TriCore_LD_D_abs:
case TriCore_ST_D_abs:
status = DecodeExtRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
case TriCore_LD_DAabs:
case TriCore_ST_DAabs:
case TriCore_LD_DA_abs:
case TriCore_ST_DA_abs:
status = DecodePairAddrRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
default:
@ -420,40 +420,40 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
// Decode s1_d.
switch(MCInst_getOpcode(Inst)) {
case TriCore_LD_Abo:
case TriCore_LD_Apreincbo:
case TriCore_LD_Apostincbo:
case TriCore_LD_Acircbo:
case TriCore_LD_Abitrevbo:
case TriCore_ST_Abo:
case TriCore_ST_Apreincbo:
case TriCore_ST_Apostincbo:
case TriCore_ST_Acircbo:
case TriCore_ST_Abitrevbo:
case TriCore_LD_A_bo_bso:
case TriCore_LD_A_bo_pre:
case TriCore_LD_A_bo_pos:
case TriCore_LD_A_bo_c:
case TriCore_LD_A_bo_r:
case TriCore_ST_A_bo_bso:
case TriCore_ST_A_bo_pre:
case TriCore_ST_A_bo_pos:
case TriCore_ST_A_bo_c:
case TriCore_ST_A_bo_r:
status = DecodeAddrRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
case TriCore_LD_Dbo:
case TriCore_LD_Dpreincbo:
case TriCore_LD_Dpostincbo:
case TriCore_LD_Dcircbo:
case TriCore_LD_Dbitrevbo:
case TriCore_ST_Dbo:
case TriCore_ST_Dpreincbo:
case TriCore_ST_Dpostincbo:
case TriCore_ST_Dcircbo:
case TriCore_ST_Dbitrevbo:
case TriCore_LD_D_bo_bso:
case TriCore_LD_D_bo_pre:
case TriCore_LD_D_bo_pos:
case TriCore_LD_D_bo_c:
case TriCore_LD_D_bo_r:
case TriCore_ST_D_bo_bso:
case TriCore_ST_D_bo_pre:
case TriCore_ST_D_bo_pos:
case TriCore_ST_D_bo_c:
case TriCore_ST_D_bo_r:
status = DecodeExtRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
case TriCore_LD_DAbo:
case TriCore_LD_DApreincbo:
case TriCore_LD_DApostincbo:
case TriCore_LD_DAcircbo:
case TriCore_LD_DAbitrevbo:
case TriCore_ST_DAbo:
case TriCore_ST_DApreincbo:
case TriCore_ST_DApostincbo:
case TriCore_ST_DAcircbo:
case TriCore_ST_DAbitrevbo:
case TriCore_LD_DA_bo_bso:
case TriCore_LD_DA_bo_pre:
case TriCore_LD_DA_bo_pos:
case TriCore_LD_DA_bo_c:
case TriCore_LD_DA_bo_r:
case TriCore_ST_DA_bo_bso:
case TriCore_ST_DA_bo_pre:
case TriCore_ST_DA_bo_pos:
case TriCore_ST_DA_bo_c:
case TriCore_ST_DA_bo_r:
status = DecodePairAddrRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
default:
@ -465,36 +465,36 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
// Decode s2.
switch(MCInst_getOpcode(Inst)) {
case TriCore_LD_Bcircbo:
case TriCore_LD_BUcircbo:
case TriCore_LD_Hcircbo:
case TriCore_LD_HUcircbo:
case TriCore_LD_Wcircbo:
case TriCore_LD_Dcircbo:
case TriCore_LD_Acircbo:
case TriCore_LD_DAcircbo:
case TriCore_ST_Bcircbo:
case TriCore_ST_Hcircbo:
case TriCore_ST_Wcircbo:
case TriCore_ST_Dcircbo:
case TriCore_ST_Qcircbo:
case TriCore_ST_Acircbo:
case TriCore_ST_DAcircbo:
case TriCore_LD_Bbitrevbo:
case TriCore_LD_BUbitrevbo:
case TriCore_LD_Hbitrevbo:
case TriCore_LD_HUbitrevbo:
case TriCore_LD_Wbitrevbo:
case TriCore_LD_Dbitrevbo:
case TriCore_LD_Abitrevbo:
case TriCore_LD_DAbitrevbo:
case TriCore_ST_Bbitrevbo:
case TriCore_ST_Hbitrevbo:
case TriCore_ST_Wbitrevbo:
case TriCore_ST_Dbitrevbo:
case TriCore_ST_Qbitrevbo:
case TriCore_ST_Abitrevbo:
case TriCore_ST_DAbitrevbo:
case TriCore_LD_B_bo_c:
case TriCore_LD_BU_bo_c:
case TriCore_LD_H_bo_c:
case TriCore_LD_HU_bo_c:
case TriCore_LD_W_bo_c:
case TriCore_LD_D_bo_c:
case TriCore_LD_A_bo_c:
case TriCore_LD_DA_bo_c:
case TriCore_ST_B_bo_c:
case TriCore_ST_H_bo_c:
case TriCore_ST_W_bo_c:
case TriCore_ST_D_bo_c:
case TriCore_ST_Q_bo_c:
case TriCore_ST_A_bo_c:
case TriCore_ST_DA_bo_c:
case TriCore_LD_B_bo_r:
case TriCore_LD_BU_bo_r:
case TriCore_LD_H_bo_r:
case TriCore_LD_HU_bo_r:
case TriCore_LD_W_bo_r:
case TriCore_LD_D_bo_r:
case TriCore_LD_A_bo_r:
case TriCore_LD_DA_bo_r:
case TriCore_ST_B_bo_r:
case TriCore_ST_H_bo_r:
case TriCore_ST_W_bo_r:
case TriCore_ST_D_bo_r:
case TriCore_ST_Q_bo_r:
case TriCore_ST_A_bo_r:
case TriCore_ST_DA_bo_r:
status = DecodePairAddrRegsRegisterClass(Inst, s2, Address, Decoder);
break;
default:
@ -529,7 +529,7 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
// Decode s1_d.
switch(MCInst_getOpcode(Inst)) {
case TriCore_LD_Abol:
case TriCore_LD_A_bol:
status = DecodeAddrRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
default:
@ -565,24 +565,24 @@ static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
// Decode d.
switch(MCInst_getOpcode(Inst)) {
case TriCore_AND_EQrc:
case TriCore_AND_NErc:
case TriCore_AND_LTrc:
case TriCore_AND_LT_Urc:
case TriCore_AND_GErc:
case TriCore_AND_GE_Urc:
case TriCore_OR_EQrc:
case TriCore_OR_NErc:
case TriCore_OR_LTrc:
case TriCore_OR_LT_Urc:
case TriCore_OR_GErc:
case TriCore_OR_GE_Urc:
case TriCore_XOR_EQrc:
case TriCore_XOR_NErc:
case TriCore_XOR_LTrc:
case TriCore_XOR_LT_Urc:
case TriCore_XOR_GErc:
case TriCore_XOR_GE_Urc:
case TriCore_AND_EQ_rc:
case TriCore_AND_NE_rc:
case TriCore_AND_LT_rc:
case TriCore_AND_LT_U_rc:
case TriCore_AND_GE_rc:
case TriCore_AND_GE_U_rc:
case TriCore_OR_EQ_rc:
case TriCore_OR_NE_rc:
case TriCore_OR_LT_rc:
case TriCore_OR_LT_U_rc:
case TriCore_OR_GE_rc:
case TriCore_OR_GE_U_rc:
case TriCore_XOR_EQ_rc:
case TriCore_XOR_NE_rc:
case TriCore_XOR_LT_rc:
case TriCore_XOR_LT_U_rc:
case TriCore_XOR_GE_rc:
case TriCore_XOR_GE_U_rc:
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status == MCDisassembler_Success)
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
@ -665,9 +665,10 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
default:
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
break;
case TriCore_MOVrlc:
case TriCore_MOV_Urlc:
case TriCore_MOVHrlc:
case TriCore_MOV_rlcDc:
case TriCore_MOV_rlcEc:
case TriCore_MOV_U_rlc:
case TriCore_MOV_H_rlc:
break;
}
if (status != MCDisassembler_Success)
@ -695,30 +696,30 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
// Decode d.
switch(MCInst_getOpcode(Inst)) {
case TriCore_ADD_Arr:
case TriCore_SUB_Arr:
case TriCore_MOV_Arr:
case TriCore_MOV_AArr:
case TriCore_ADD_A_rr:
case TriCore_SUB_A_rr:
case TriCore_MOV_A_rr:
case TriCore_MOV_AA_rr:
status = DecodeAddrRegsRegisterClass(Inst, d, Address, Decoder);
break;
case TriCore_AND_EQrr:
case TriCore_AND_NErr:
case TriCore_AND_LTrr:
case TriCore_AND_LT_Urr:
case TriCore_AND_GErr:
case TriCore_AND_GE_Urr:
case TriCore_OR_EQrr:
case TriCore_OR_NErr:
case TriCore_OR_LTrr:
case TriCore_OR_LT_Urr:
case TriCore_OR_GErr:
case TriCore_OR_GE_Urr:
case TriCore_XOR_EQrr:
case TriCore_XOR_NErr:
case TriCore_XOR_LTrr:
case TriCore_XOR_LT_Urr:
case TriCore_XOR_GErr:
case TriCore_XOR_GE_Urr:
case TriCore_AND_EQ_rr:
case TriCore_AND_NE_rr:
case TriCore_AND_LT_rr:
case TriCore_AND_LT_U_rr:
case TriCore_AND_GE_rr:
case TriCore_AND_GE_U_rr:
case TriCore_OR_EQ_rr:
case TriCore_OR_NE_rr:
case TriCore_OR_LT_rr:
case TriCore_OR_LT_U_rr:
case TriCore_OR_GE_rr:
case TriCore_OR_GE_U_rr:
case TriCore_XOR_EQ_rr:
case TriCore_XOR_NE_rr:
case TriCore_XOR_LT_rr:
case TriCore_XOR_LT_U_rr:
case TriCore_XOR_GE_rr:
case TriCore_XOR_GE_U_rr:
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status == MCDisassembler_Success)
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
@ -732,8 +733,8 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
// Decode s1.
switch(MCInst_getOpcode(Inst)) {
case TriCore_ADD_Arr:
case TriCore_SUB_Arr:
case TriCore_ADD_A_rr:
case TriCore_SUB_A_rr:
status = DecodeAddrRegsRegisterClass(Inst, s1, Address, Decoder);
break;
default:
@ -745,10 +746,10 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
// Decode s2.
switch(MCInst_getOpcode(Inst)) {
case TriCore_ADD_Arr:
case TriCore_SUB_Arr:
case TriCore_MOV_Drr:
case TriCore_MOV_AArr:
case TriCore_ADD_A_rr:
case TriCore_SUB_A_rr:
case TriCore_MOV_D_rr:
case TriCore_MOV_AA_rr:
status = DecodeAddrRegsRegisterClass(Inst, s2, Address, Decoder);
break;
default:
@ -852,7 +853,7 @@ bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst
}
// Calling the auto-generated decoder function.
Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0);
Result = decodeInstruction_2(DecoderTable16, MI, insn16, address);
if (Result != MCDisassembler_Fail) {
*size = 2;
return true;
@ -863,7 +864,7 @@ bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst
}
// Calling the auto-generated decoder function.
Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0);
Result = decodeInstruction_4(DecoderTable32, MI, insn32, address);
if (Result != MCDisassembler_Fail) {
*size = 4;
return true;

146
arch/TriCore/TriCoreGenAsmWriter.inc
View File

@ -600,78 +600,80 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
static char *getRegisterName(unsigned RegNo)
{
// assert(RegNo && RegNo < 53 && "Invalid register number!");
static const char *getRegisterName(unsigned RegNo) {
// assert(RegNo && RegNo < 61 && "Invalid register number!");
#ifndef CAPSTONE_DIET
static char AsmStrs[] = {
/* 0 */ 'a', '1', '0', 0,
/* 4 */ 'd', '1', '0', 0,
/* 8 */ 'e', '1', '0', 0,
/* 12 */ 'a', '0', 0,
/* 15 */ 'd', '0', 0,
/* 18 */ 'e', '0', 0,
/* 21 */ 'A', '1', '0', '_', 'A', '1', '1', 0,
/* 29 */ 'a', '1', '1', 0,
/* 33 */ 'd', '1', '1', 0,
/* 37 */ 'A', '0', '_', 'A', '1', 0,
/* 43 */ 'a', '1', 0,
/* 46 */ 'd', '1', 0,
/* 49 */ 'a', '1', '2', 0,
/* 53 */ 'd', '1', '2', 0,
/* 57 */ 'e', '1', '2', 0,
/* 61 */ 'a', '2', 0,
/* 64 */ 'd', '2', 0,
/* 67 */ 'e', '2', 0,
/* 70 */ 'A', '1', '2', '_', 'A', '1', '3', 0,
/* 78 */ 'a', '1', '3', 0,
/* 82 */ 'd', '1', '3', 0,
/* 86 */ 'A', '2', '_', 'A', '3', 0,
/* 92 */ 'a', '3', 0,
/* 95 */ 'd', '3', 0,
/* 98 */ 'a', '1', '4', 0,
/* 102 */ 'd', '1', '4', 0,
/* 106 */ 'e', '1', '4', 0,
/* 110 */ 'a', '4', 0,
/* 113 */ 'd', '4', 0,
/* 116 */ 'e', '4', 0,
/* 119 */ 'A', '1', '4', '_', 'A', '1', '5', 0,
/* 127 */ 'a', '1', '5', 0,
/* 131 */ 'd', '1', '5', 0,
/* 135 */ 'A', '4', '_', 'A', '5', 0,
/* 141 */ 'a', '5', 0,
/* 144 */ 'd', '5', 0,
/* 147 */ 'a', '6', 0,
/* 150 */ 'd', '6', 0,
/* 153 */ 'e', '6', 0,
/* 156 */ 'A', '6', '_', 'A', '7', 0,
/* 162 */ 'a', '7', 0,
/* 165 */ 'd', '7', 0,
/* 168 */ 'a', '8', 0,
/* 171 */ 'd', '8', 0,
/* 174 */ 'e', '8', 0,
/* 177 */ 'A', '8', '_', 'A', '9', 0,
/* 183 */ 'a', '9', 0,
/* 186 */ 'd', '9', 0,
/* 189 */ 'p', 'c', 0,
/* 192 */ 'p', 'c', 'x', 'i', 0,
/* 197 */ 'p', 's', 'w', 0,
/* 201 */ 'f', 'c', 'x', 0,
};
static const char AsmStrs[] = {
/* 0 */ "a10\0"
/* 4 */ "d10\0"
/* 8 */ "e10\0"
/* 12 */ "p10\0"
/* 16 */ "a0\0"
/* 19 */ "d0\0"
/* 22 */ "e0\0"
/* 25 */ "p0\0"
/* 28 */ "A10_A11\0"
/* 36 */ "a11\0"
/* 40 */ "d11\0"
/* 44 */ "A0_A1\0"
/* 50 */ "a1\0"
/* 53 */ "d1\0"
/* 56 */ "a12\0"
/* 60 */ "d12\0"
/* 64 */ "e12\0"
/* 68 */ "p12\0"
/* 72 */ "a2\0"
/* 75 */ "d2\0"
/* 78 */ "e2\0"
/* 81 */ "p2\0"
/* 84 */ "A12_A13\0"
/* 92 */ "a13\0"
/* 96 */ "d13\0"
/* 100 */ "A2_A3\0"
/* 106 */ "a3\0"
/* 109 */ "d3\0"
/* 112 */ "a14\0"
/* 116 */ "d14\0"
/* 120 */ "e14\0"
/* 124 */ "p14\0"
/* 128 */ "a4\0"
/* 131 */ "d4\0"
/* 134 */ "e4\0"
/* 137 */ "p4\0"
/* 140 */ "A14_A15\0"
/* 148 */ "a15\0"
/* 152 */ "d15\0"
/* 156 */ "A4_A5\0"
/* 162 */ "a5\0"
/* 165 */ "d5\0"
/* 168 */ "a6\0"
/* 171 */ "d6\0"
/* 174 */ "e6\0"
/* 177 */ "p6\0"
/* 180 */ "A6_A7\0"
/* 186 */ "a7\0"
/* 189 */ "d7\0"
/* 192 */ "a8\0"
/* 195 */ "d8\0"
/* 198 */ "e8\0"
/* 201 */ "p8\0"
/* 204 */ "A8_A9\0"
/* 210 */ "a9\0"
/* 213 */ "d9\0"
/* 216 */ "pc\0"
/* 219 */ "pcxi\0"
/* 224 */ "psw\0"
/* 228 */ "fcx\0"
};
static const uint8_t RegAsmOffset[] = {
228, 216, 219, 224, 16, 50, 72, 106, 128, 162, 168, 186, 192, 210,
0, 36, 56, 92, 112, 148, 19, 53, 75, 109, 131, 165, 171, 189,
195, 213, 4, 40, 60, 96, 116, 152, 22, 78, 134, 174, 198, 8,
64, 120, 25, 81, 137, 177, 201, 12, 68, 124, 44, 100, 156, 180,
204, 28, 84, 140,
};
static const uint8_t RegAsmOffset[] = {
201, 189, 192, 197, 12, 43, 61, 92, 110, 141, 147, 162, 168, 183,
0, 29, 49, 78, 98, 127, 15, 46, 64, 95, 113, 144, 150, 165,
171, 186, 4, 33, 53, 82, 102, 131, 18, 67, 116, 153, 174, 8,
57, 106, 37, 86, 135, 156, 177, 21, 70, 119,
};
//assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
// "Invalid alt name index for register!");
return AsmStrs+RegAsmOffset[RegNo-1];
#else
return NULL;
#endif
// assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
// "Invalid alt name index for register!");
return AsmStrs+RegAsmOffset[RegNo-1];
}

3288
arch/TriCore/TriCoreGenDisassemblerTables.inc
View File

File diff suppressed because it is too large Load Diff

2519
arch/TriCore/TriCoreGenInstrInfo.inc
View File

File diff suppressed because it is too large Load Diff

352
arch/TriCore/TriCoreGenRegisterInfo.inc
View File

@ -1,13 +1,8 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*Target Register Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically generated file by the LLVM TableGen Disassembler Backend. */
/* Do not edit. */
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
@ -58,183 +53,236 @@ enum {
TriCore_E10 = 42,
TriCore_E12 = 43,
TriCore_E14 = 44,
TriCore_A0_A1 = 45,
TriCore_A2_A3 = 46,
TriCore_A4_A5 = 47,
TriCore_A6_A7 = 48,
TriCore_A8_A9 = 49,
TriCore_A10_A11 = 50,
TriCore_A12_A13 = 51,
TriCore_A14_A15 = 52,
TriCore_NUM_TARGET_REGS // 53
TriCore_P0 = 45,
TriCore_P2 = 46,
TriCore_P4 = 47,
TriCore_P6 = 48,
TriCore_P8 = 49,
TriCore_P10 = 50,
TriCore_P12 = 51,
TriCore_P14 = 52,
TriCore_A0_A1 = 53,
TriCore_A2_A3 = 54,
TriCore_A4_A5 = 55,
TriCore_A6_A7 = 56,
TriCore_A8_A9 = 57,
TriCore_A10_A11 = 58,
TriCore_A12_A13 = 59,
TriCore_A14_A15 = 60,
NUM_TARGET_REGS // 61
};
// Register classes
enum {
TriCore_AddrRegsRegClassID = 0,
TriCore_DataRegsRegClassID = 1,
TriCore_PSRegsRegClassID = 2,
TriCore_ExtRegsRegClassID = 3,
TriCore_PairAddrRegsRegClassID = 4
TriCore_AddrExtRegsRegClassID = 3,
TriCore_ExtRegsRegClassID = 4,
TriCore_PairAddrRegsRegClassID = 5,
};
// Subregister indices
enum {
TriCore_NoSubRegister,
TriCore_subreg_even, // 1
TriCore_subreg_odd, // 2
TriCore_subreg_even, // 1
TriCore_subreg_odd, // 2
TriCore_NUM_TARGET_SUBREGS
};
#endif // GET_REGINFO_ENUM
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|*MC Register Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static MCPhysReg TriCoreRegDiffLists[] = {
/* 0 */ 65450, 1, 0,
/* 3 */ 65482, 1, 0,
/* 6 */ 65496, 1, 0,
/* 9 */ 65497, 1, 0,
/* 12 */ 65498, 1, 0,
/* 15 */ 65499, 1, 0,
/* 18 */ 65500, 1, 0,
/* 21 */ 65501, 1, 0,
/* 24 */ 65502, 1, 0,
/* 27 */ 65503, 1, 0,
/* 30 */ 65520, 1, 0,
/* 33 */ 65521, 1, 0,
/* 36 */ 65522, 1, 0,
/* 39 */ 65523, 1, 0,
/* 42 */ 65524, 1, 0,
/* 45 */ 65525, 1, 0,
/* 48 */ 65526, 1, 0,
/* 51 */ 65527, 1, 0,
/* 54 */ 8, 0,
/* 56 */ 9, 0,
/* 58 */ 10, 0,
/* 60 */ 11, 0,
/* 62 */ 12, 0,
/* 64 */ 13, 0,
/* 66 */ 14, 0,
/* 68 */ 15, 0,
/* 70 */ 16, 0,
/* 72 */ 32, 0,
/* 74 */ 33, 0,
/* 76 */ 34, 0,
/* 78 */ 35, 0,
/* 80 */ 36, 0,
/* 82 */ 37, 0,
/* 84 */ 38, 0,
/* 86 */ 39, 0,
/* 88 */ 40, 0,
/* 90 */ 65535, 0,
static const MCPhysReg TriCoreRegDiffLists[] = {
/* 0 */ 65434, 1, 0,
/* 3 */ 65450, 1, 0,
/* 6 */ 65482, 1, 0,
/* 9 */ 65488, 1, 0,
/* 12 */ 65489, 1, 0,
/* 15 */ 65490, 1, 0,
/* 18 */ 65491, 1, 0,
/* 21 */ 65492, 1, 0,
/* 24 */ 65493, 1, 0,
/* 27 */ 65494, 1, 0,
/* 30 */ 65495, 1, 0,
/* 33 */ 65496, 1, 0,
/* 36 */ 65497, 1, 0,
/* 39 */ 65498, 1, 0,
/* 42 */ 65499, 1, 0,
/* 45 */ 65500, 1, 0,
/* 48 */ 65501, 1, 0,
/* 51 */ 65502, 1, 0,
/* 54 */ 65503, 1, 0,
/* 57 */ 65520, 1, 0,
/* 60 */ 65521, 1, 0,
/* 63 */ 65522, 1, 0,
/* 66 */ 65523, 1, 0,
/* 69 */ 65524, 1, 0,
/* 72 */ 65525, 1, 0,
/* 75 */ 65526, 1, 0,
/* 78 */ 65527, 1, 0,
/* 81 */ 32, 8, 0,
/* 84 */ 33, 8, 0,
/* 87 */ 34, 8, 0,
/* 90 */ 35, 8, 0,
/* 93 */ 36, 8, 0,
/* 96 */ 37, 8, 0,
/* 99 */ 38, 8, 0,
/* 102 */ 39, 8, 0,
/* 105 */ 40, 8, 0,
/* 108 */ 9, 0,
/* 110 */ 10, 0,
/* 112 */ 11, 0,
/* 114 */ 12, 0,
/* 116 */ 13, 0,
/* 118 */ 14, 0,
/* 120 */ 15, 0,
/* 122 */ 16, 0,
/* 124 */ 65535, 0,
};
static uint16_t TriCoreSubRegIdxLists[] = {
/* 0 */ 1,
2,
0,
static const uint16_t TriCoreSubRegIdxLists[] = {
/* 0 */ 1, 2, 0,
};
static MCRegisterDesc TriCoreRegDesc[] = {
// Descriptors
{3, 0, 0, 0, 0}, {174, 2, 2, 2, 1441}, {162, 2, 2, 2, 1441},
{165, 2, 2, 2, 1441}, {170, 2, 2, 2, 1441}, {12, 2, 88, 2, 1441},
{36, 2, 86, 2, 1441}, {54, 2, 86, 2, 1441}, {78, 2, 84, 2, 1441},
{96, 2, 84, 2, 1441}, {120, 2, 82, 2, 1441}, {126, 2, 82, 2, 1441},
{138, 2, 80, 2, 1441}, {144, 2, 80, 2, 1441}, {156, 2, 78, 2, 1441},
{0, 2, 78, 2, 1441}, {25, 2, 76, 2, 1441}, {42, 2, 76, 2, 1441},
{67, 2, 74, 2, 1441}, {84, 2, 74, 2, 1441}, {109, 2, 72, 2, 1441},
{15, 2, 70, 2, 1441}, {39, 2, 68, 2, 1441}, {57, 2, 68, 2, 1441},
{81, 2, 66, 2, 1441}, {99, 2, 66, 2, 1441}, {123, 2, 64, 2, 1441},
{129, 2, 64, 2, 1441}, {141, 2, 62, 2, 1441}, {147, 2, 62, 2, 1441},
{159, 2, 60, 2, 1441}, {4, 2, 60, 2, 1441}, {29, 2, 58, 2, 1441},
{46, 2, 58, 2, 1441}, {71, 2, 56, 2, 1441}, {88, 2, 56, 2, 1441},
{113, 2, 54, 2, 1441}, {18, 30, 2, 0, 50}, {60, 33, 2, 0, 50},
{102, 36, 2, 0, 50}, {132, 39, 2, 0, 50}, {150, 42, 2, 0, 50},
{8, 45, 2, 0, 50}, {50, 48, 2, 0, 50}, {92, 51, 2, 0, 50},
{33, 6, 2, 0, 2}, {75, 9, 2, 0, 2}, {117, 12, 2, 0, 2},
{135, 15, 2, 0, 2}, {153, 18, 2, 0, 2}, {21, 21, 2, 0, 2},
{63, 24, 2, 0, 2}, {105, 27, 2, 0, 2},
static const MCRegisterDesc TriCoreRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 201, 2, 2, 2, 1985, 0 },
{ 189, 2, 2, 2, 1985, 0 },
{ 192, 2, 2, 2, 1985, 0 },
{ 197, 2, 2, 2, 1985, 0 },
{ 16, 2, 105, 2, 1985, 0 },
{ 43, 2, 102, 2, 1985, 0 },
{ 65, 2, 102, 2, 1985, 0 },
{ 92, 2, 99, 2, 1985, 0 },
{ 114, 2, 99, 2, 1985, 0 },
{ 141, 2, 96, 2, 1985, 0 },
{ 147, 2, 96, 2, 1985, 0 },
{ 162, 2, 93, 2, 1985, 0 },
{ 168, 2, 93, 2, 1985, 0 },
{ 183, 2, 90, 2, 1985, 0 },
{ 0, 2, 90, 2, 1985, 0 },
{ 32, 2, 87, 2, 1985, 0 },
{ 49, 2, 87, 2, 1985, 0 },
{ 81, 2, 84, 2, 1985, 0 },
{ 98, 2, 84, 2, 1985, 0 },
{ 130, 2, 81, 2, 1985, 0 },
{ 19, 2, 122, 2, 1985, 0 },
{ 46, 2, 120, 2, 1985, 0 },
{ 68, 2, 120, 2, 1985, 0 },
{ 95, 2, 118, 2, 1985, 0 },
{ 117, 2, 118, 2, 1985, 0 },
{ 144, 2, 116, 2, 1985, 0 },
{ 150, 2, 116, 2, 1985, 0 },
{ 165, 2, 114, 2, 1985, 0 },
{ 171, 2, 114, 2, 1985, 0 },
{ 186, 2, 112, 2, 1985, 0 },
{ 4, 2, 112, 2, 1985, 0 },
{ 36, 2, 110, 2, 1985, 0 },
{ 53, 2, 110, 2, 1985, 0 },
{ 85, 2, 108, 2, 1985, 0 },
{ 102, 2, 108, 2, 1985, 0 },
{ 134, 2, 82, 2, 1985, 0 },
{ 22, 57, 2, 0, 98, 2 },
{ 71, 60, 2, 0, 98, 2 },
{ 120, 63, 2, 0, 98, 2 },
{ 153, 66, 2, 0, 98, 2 },
{ 174, 69, 2, 0, 98, 2 },
{ 8, 72, 2, 0, 98, 2 },
{ 57, 75, 2, 0, 98, 2 },
{ 106, 78, 2, 0, 98, 2 },
{ 25, 33, 2, 0, 50, 2 },
{ 74, 36, 2, 0, 50, 2 },
{ 123, 39, 2, 0, 50, 2 },
{ 156, 42, 2, 0, 50, 2 },
{ 177, 45, 2, 0, 50, 2 },
{ 12, 48, 2, 0, 50, 2 },
{ 61, 51, 2, 0, 50, 2 },
{ 110, 54, 2, 0, 50, 2 },
{ 40, 9, 2, 0, 2, 2 },
{ 89, 12, 2, 0, 2, 2 },
{ 138, 15, 2, 0, 2, 2 },
{ 159, 18, 2, 0, 2, 2 },
{ 180, 21, 2, 0, 2, 2 },
{ 28, 24, 2, 0, 2, 2 },
{ 77, 27, 2, 0, 2, 2 },
{ 126, 30, 2, 0, 2, 2 },
};
// AddrRegs Register Class...
static MCPhysReg AddrRegs[] = {
TriCore_A15, TriCore_A2, TriCore_A3, TriCore_A4,
TriCore_A5, TriCore_A6, TriCore_A7, TriCore_A12,
TriCore_A13, TriCore_A14, TriCore_A10, TriCore_A11,
TriCore_A0, TriCore_A1, TriCore_A8, TriCore_A9,
};
// AddrRegs Register Class...
static const MCPhysReg AddrRegs[] = {
TriCore_A15, TriCore_A2, TriCore_A3, TriCore_A4, TriCore_A5, TriCore_A6, TriCore_A7, TriCore_A12, TriCore_A13, TriCore_A14, TriCore_A10, TriCore_A11, TriCore_A0, TriCore_A1, TriCore_A8, TriCore_A9,
};
// AddrRegs Bit set.
static uint8_t AddrRegsBits[] = {
0xe0,
0xff,
0x1f,
};
// AddrRegs Bit set.
static const uint8_t AddrRegsBits[] = {
0xe0, 0xff, 0x1f,
};
// DataRegs Register Class...
static MCPhysReg DataRegs[] = {
TriCore_D15, TriCore_D2, TriCore_D3, TriCore_D4, TriCore_D5, TriCore_D6,
TriCore_D7, TriCore_D8, TriCore_D9, TriCore_D10, TriCore_D11, TriCore_D12,
TriCore_D13, TriCore_D14, TriCore_D0, TriCore_D1,
};
// DataRegs Register Class...
static const MCPhysReg DataRegs[] = {
TriCore_D15, TriCore_D2, TriCore_D3, TriCore_D4, TriCore_D5, TriCore_D6, TriCore_D7, TriCore_D8, TriCore_D9, TriCore_D10, TriCore_D11, TriCore_D12, TriCore_D13, TriCore_D14, TriCore_D0, TriCore_D1,
};
// DataRegs Bit set.
static uint8_t DataRegsBits[] = {
0x00, 0x00, 0xe0, 0xff, 0x1f,
};
// DataRegs Bit set.
static const uint8_t DataRegsBits[] = {
0x00, 0x00, 0xe0, 0xff, 0x1f,
};
// PSRegs Register Class...
static MCPhysReg PSRegs[] = {
TriCore_PSW,
TriCore_PCXI,
TriCore_PC,
TriCore_FCX,
};
// PSRegs Register Class...
static const MCPhysReg PSRegs[] = {
TriCore_PSW, TriCore_PCXI, TriCore_PC, TriCore_FCX,
};
// PSRegs Bit set.
static uint8_t PSRegsBits[] = {
0x1e,
};
// PSRegs Bit set.
static const uint8_t PSRegsBits[] = {
0x1e,
};
// ExtRegs Register Class...
static MCPhysReg ExtRegs[] = {
TriCore_E2, TriCore_E4, TriCore_E6, TriCore_E8,
TriCore_E10, TriCore_E12, TriCore_E14, TriCore_E0,
};
// AddrExtRegs Register Class...
static const MCPhysReg AddrExtRegs[] = {
TriCore_P2, TriCore_P4, TriCore_P6, TriCore_P8, TriCore_P10, TriCore_P12, TriCore_P14, TriCore_P0,
};
// ExtRegs Bit set.
static uint8_t ExtRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
};
// AddrExtRegs Bit set.
static const uint8_t AddrExtRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
};
// PairAddrRegs Register Class...
static MCPhysReg PairAddrRegs[] = {
TriCore_A0_A1, TriCore_A2_A3, TriCore_A4_A5, TriCore_A6_A7,
TriCore_A8_A9, TriCore_A10_A11, TriCore_A12_A13, TriCore_A14_A15,
};
// ExtRegs Register Class...
static const MCPhysReg ExtRegs[] = {
TriCore_E2, TriCore_E4, TriCore_E6, TriCore_E8, TriCore_E10, TriCore_E12, TriCore_E14, TriCore_E0,
};
// PairAddrRegs Bit set.
static uint8_t PairAddrRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
};
// ExtRegs Bit set.
static const uint8_t ExtRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
};
static MCRegisterClass TriCoreMCRegisterClasses[] = {
{AddrRegs, AddrRegsBits, sizeof(AddrRegsBits)},
{DataRegs, DataRegsBits, sizeof(DataRegsBits)},
{PSRegs, PSRegsBits, sizeof(PSRegsBits)},
{ExtRegs, ExtRegsBits, sizeof(ExtRegsBits)},
{PairAddrRegs, PairAddrRegsBits, sizeof(PairAddrRegsBits)},
// PairAddrRegs Register Class...
static const MCPhysReg PairAddrRegs[] = {
TriCore_A0_A1, TriCore_A2_A3, TriCore_A4_A5, TriCore_A6_A7, TriCore_A8_A9, TriCore_A10_A11, TriCore_A12_A13, TriCore_A14_A15,
};
// PairAddrRegs Bit set.
static const uint8_t PairAddrRegsBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
};
static const MCRegisterClass TriCoreMCRegisterClasses[] = {
{ AddrRegs, AddrRegsBits, sizeof(AddrRegsBits) },
{ DataRegs, DataRegsBits, sizeof(DataRegsBits) },
{ PSRegs, PSRegsBits, sizeof(PSRegsBits) },
{ AddrExtRegs, AddrExtRegsBits, sizeof(AddrExtRegsBits) },
{ ExtRegs, ExtRegsBits, sizeof(ExtRegsBits) },
{ PairAddrRegs, PairAddrRegsBits, sizeof(PairAddrRegsBits) },
};
#endif // GET_REGINFO_MC_DESC

228
arch/TriCore/TriCoreInstPrinter.c
View File

@ -29,7 +29,7 @@
#include "../../MathExtras.h"
#include "TriCoreMapping.h"
static char *getRegisterName(unsigned RegNo);
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
static void printOperand(MCInst *MI, int OpNum, SStream *O);
@ -307,119 +307,119 @@ void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
unsigned Opcode = MCInst_getOpcode(MI), i;
switch(Opcode) {
// Combine 2 AddrRegs from disassember into a PairAddrRegs to match
// with instr def. load/store require even/odd AddrReg pair. To enforce
// this constraint, a single PairAddrRegs reg operand is used in the .td
// file to replace the two AddrRegs. However, when decoding them, the two
// AddrRegs cannot be automatically expressed as a PairAddrRegs, so we
// have to manually merge them.
// FIXME: We would really like to be able to tablegen'erate this.
case TriCore_LD_DAabs:
case TriCore_LD_DAbo:
case TriCore_LD_DApreincbo:
case TriCore_LD_DApostincbo:
case TriCore_ST_Bcircbo:
case TriCore_ST_Hcircbo:
case TriCore_ST_Wcircbo:
case TriCore_ST_Dcircbo:
case TriCore_ST_Qcircbo:
case TriCore_ST_Acircbo:
case TriCore_ST_Bbitrevbo:
case TriCore_ST_Hbitrevbo:
case TriCore_ST_Wbitrevbo:
case TriCore_ST_Dbitrevbo:
case TriCore_ST_Qbitrevbo:
case TriCore_ST_Abitrevbo: {
const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
if (MCRegisterClass_contains(MRC, Reg)) {
MCInst NewMI;
MCInst_Init(&NewMI);
MCInst_setOpcode(&NewMI, Opcode);
MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
// Copy the rest operands into NewMI.
for(i = 2; i < MCInst_getNumOperands(MI); ++i)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
printInstruction(&NewMI, O, MRI);
return;
}
}
case TriCore_ST_DAabs:
case TriCore_ST_DAbo:
case TriCore_ST_DApreincbo:
case TriCore_ST_DApostincbo:
case TriCore_LD_Bcircbo:
case TriCore_LD_BUcircbo:
case TriCore_LD_Hcircbo:
case TriCore_LD_HUcircbo:
case TriCore_LD_Wcircbo:
case TriCore_LD_Dcircbo:
case TriCore_LD_Acircbo:
case TriCore_LD_Bbitrevbo:
case TriCore_LD_BUbitrevbo:
case TriCore_LD_Hbitrevbo:
case TriCore_LD_HUbitrevbo:
case TriCore_LD_Wbitrevbo:
case TriCore_LD_Dbitrevbo:
case TriCore_LD_Abitrevbo: {
const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
if (MCRegisterClass_contains(MRC, Reg)) {
MCInst NewMI;
MCInst_Init(&NewMI);
MCInst_setOpcode(&NewMI, Opcode);
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
// Copy the rest operands into NewMI.
for(i = 3; i < MCInst_getNumOperands(MI); ++i)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
printInstruction(&NewMI, O, MRI);
return;
}
}
case TriCore_LD_DAcircbo:
case TriCore_ST_DAcircbo:
case TriCore_LD_DAbitrevbo:
case TriCore_ST_DAbitrevbo: {
const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 0));
unsigned Reg2 = MCOperand_getReg(MCInst_getOperand(MI, 2));
if (MCRegisterClass_contains(MRC, Reg2)) {
MCInst NewMI;
MCInst_Init(&NewMI);
MCInst_setOpcode(&NewMI, Opcode);
MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg1, TriCore_subreg_even,
MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg2, TriCore_subreg_even,
MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
// Copy the rest operands into NewMI.
for(i = 4; i < MCInst_getNumOperands(MI); ++i)
MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
printInstruction(&NewMI, O, MRI);
return;
}
}
}
// switch(Opcode) {
// // Combine 2 AddrRegs from disassember into a PairAddrRegs to match
// // with instr def. load/store require even/odd AddrReg pair. To enforce
// // this constraint, a single PairAddrRegs reg operand is used in the .td
// // file to replace the two AddrRegs. However, when decoding them, the two
// // AddrRegs cannot be automatically expressed as a PairAddrRegs, so we
// // have to manually merge them.
// // FIXME: We would really like to be able to tablegen'erate this.
// case TriCore_LD_DAabs:
// case TriCore_LD_DAbo:
// case TriCore_LD_DApreincbo:
// case TriCore_LD_DApostincbo:
// case TriCore_ST_Bcircbo:
// case TriCore_ST_Hcircbo:
// case TriCore_ST_Wcircbo:
// case TriCore_ST_Dcircbo:
// case TriCore_ST_Qcircbo:
// case TriCore_ST_Acircbo:
// case TriCore_ST_Bbitrevbo:
// case TriCore_ST_Hbitrevbo:
// case TriCore_ST_Wbitrevbo:
// case TriCore_ST_Dbitrevbo:
// case TriCore_ST_Qbitrevbo:
// case TriCore_ST_Abitrevbo: {
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
//
// unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
// if (MCRegisterClass_contains(MRC, Reg)) {
// MCInst NewMI;
//
// MCInst_Init(&NewMI);
// MCInst_setOpcode(&NewMI, Opcode);
//
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
//
// // Copy the rest operands into NewMI.
// for(i = 2; i < MCInst_getNumOperands(MI); ++i)
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
//
// printInstruction(&NewMI, O, MRI);
// return;
// }
// }
// case TriCore_ST_DAabs:
// case TriCore_ST_DAbo:
// case TriCore_ST_DApreincbo:
// case TriCore_ST_DApostincbo:
// case TriCore_LD_Bcircbo:
// case TriCore_LD_BUcircbo:
// case TriCore_LD_Hcircbo:
// case TriCore_LD_HUcircbo:
// case TriCore_LD_Wcircbo:
// case TriCore_LD_Dcircbo:
// case TriCore_LD_Acircbo:
// case TriCore_LD_Bbitrevbo:
// case TriCore_LD_BUbitrevbo:
// case TriCore_LD_Hbitrevbo:
// case TriCore_LD_HUbitrevbo:
// case TriCore_LD_Wbitrevbo:
// case TriCore_LD_Dbitrevbo:
// case TriCore_LD_Abitrevbo: {
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
//
// unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
// if (MCRegisterClass_contains(MRC, Reg)) {
// MCInst NewMI;
//
// MCInst_Init(&NewMI);
// MCInst_setOpcode(&NewMI, Opcode);
//
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, 0));
//
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg, TriCore_subreg_even,
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
//
// // Copy the rest operands into NewMI.
// for(i = 3; i < MCInst_getNumOperands(MI); ++i)
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
//
// printInstruction(&NewMI, O, MRI);
// return;
// }
// }
// case TriCore_LD_DAcircbo:
// case TriCore_ST_DAcircbo:
// case TriCore_LD_DAbitrevbo:
// case TriCore_ST_DAbitrevbo: {
// const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, TriCore_AddrRegsRegClassID);
//
// unsigned Reg1 = MCOperand_getReg(MCInst_getOperand(MI, 0));
// unsigned Reg2 = MCOperand_getReg(MCInst_getOperand(MI, 2));
// if (MCRegisterClass_contains(MRC, Reg2)) {
// MCInst NewMI;
//
// MCInst_Init(&NewMI);
// MCInst_setOpcode(&NewMI, Opcode);
//
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg1, TriCore_subreg_even,
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
//
// MCOperand_CreateReg0(&NewMI, MCRegisterInfo_getMatchingSuperReg(MRI, Reg2, TriCore_subreg_even,
// MCRegisterInfo_getRegClass(MRI, TriCore_PairAddrRegsRegClassID)));
//
// // Copy the rest operands into NewMI.
// for(i = 4; i < MCInst_getNumOperands(MI); ++i)
// MCInst_addOperand2(&NewMI, MCInst_getOperand(MI, i));
//
// printInstruction(&NewMI, O, MRI);
// return;
// }
// }
// }
printInstruction(MI, O, Info);
}

18
arch/TriCore/TriCoreInstrInfo.td
View File

@ -1713,7 +1713,7 @@ def XOR_srr : ISRR<0xC6, "xor">;
def XOR_T : IBIT<0x07, 0x03, "xor.t">;
defm XOR_EQ : mIRR_RC<0x0B, 0x2F, 0x8B, 0x2F, "xor.eq">;
defm XOR_NE : mIRR_RC<0x0B, 0x30, 0x8B, 0x30, "xor.nq">;
defm XOR_NE : mIRR_RC<0x0B, 0x30, 0x8B, 0x30, "xor.ne">;
defm XOR_GE : mIRR_RC<0x0B, 0x33, 0x8B, 0x33, "xor.ge">;
defm XOR_GE_U : mIRR_RC<0x0B, 0x34, 0x8B, 0x34, "xor.ge.u">;
defm XOR_LT : mIRR_RC<0x0B, 0x31, 0x8B, 0x31, "xor.lt">;
@ -2491,14 +2491,14 @@ multiclass LOGIC_COMPARE_U<bits<8> op_u, string asmstring, PatLeaf PF>
//}// isBranch, isTerminator
let usesCustomInserter = 1 in {
def Select8 : Pseudo<(outs DataRegs:$dst),
(ins DataRegs:$src, DataRegs:$src2, i32imm:$cc, DataRegs:$src1 ),
"# Select8 PSEUDO",
[(set DataRegs:$dst,
(TriCoreSelectCC DataRegs:$src, DataRegs:$src2, imm:$cc,
DataRegs:$src1))]>;
}
// let usesCustomInserter = 1 in {
// def Select8 : Pseudo<(outs DataRegs:$dst),
// (ins DataRegs:$src, DataRegs:$src2, i32imm:$cc, DataRegs:$src1 ),
// "# Select8 PSEUDO",
// [(set DataRegs:$dst,
// (TriCoreSelectCC DataRegs:$src, DataRegs:$src2, imm:$cc,
// DataRegs:$src1))]>;
// }
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns

1668
arch/TriCore/TriCoreMapping.c
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File diff suppressed because it is too large Load Diff

4867
arch/TriCore/gen/TriCoreGenCSMappingInsn.inc Normal file
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File diff suppressed because it is too large Load Diff

331
arch/TriCore/gen/TriCoreGenCSMappingInsnName.inc Normal file
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@ -0,0 +1,331 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
/* By Rot127 <unisono@quyllur.org>, 2023 */
/* Auto generated file. Do not edit. */
/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
"absdifs.h", // TriCore_INS_ABSDIFS.H
"absdifs", // TriCore_INS_ABSDIFS
"absdif.b", // TriCore_INS_ABSDIF.B
"absdif.h", // TriCore_INS_ABSDIF.H
"absdif", // TriCore_INS_ABSDIF
"abss.h", // TriCore_INS_ABSS.H
"abss", // TriCore_INS_ABSS
"abs.b", // TriCore_INS_ABS.B
"abs.h", // TriCore_INS_ABS.H
"abs", // TriCore_INS_ABS
"addc", // TriCore_INS_ADDC
"addih.a", // TriCore_INS_ADDIH.A
"addih", // TriCore_INS_ADDIH
"addi", // TriCore_INS_ADDI
"addsc.at", // TriCore_INS_ADDSC.AT
"addsc.a", // TriCore_INS_ADDSC.A
"adds.h", // TriCore_INS_ADDS.H
"adds.hu", // TriCore_INS_ADDS.HU
"adds.u", // TriCore_INS_ADDS.U
"adds", // TriCore_INS_ADDS
"addx", // TriCore_INS_ADDX
"add.a", // TriCore_INS_ADD.A
"add.b", // TriCore_INS_ADD.B
"add.h", // TriCore_INS_ADD.H
"add", // TriCore_INS_ADD
"andn.t", // TriCore_INS_ANDN.T
"andn", // TriCore_INS_ANDN
"and.andn.t", // TriCore_INS_AND.ANDN.T
"and.and.t", // TriCore_INS_AND.AND.T
"and.eq", // TriCore_INS_AND.EQ
"and.ge.u", // TriCore_INS_AND.GE.U
"and.ge", // TriCore_INS_AND.GE
"and.lt.u", // TriCore_INS_AND.LT.U
"and.lt", // TriCore_INS_AND.LT
"and.ne", // TriCore_INS_AND.NE
"and.nor.t", // TriCore_INS_AND.NOR.T
"and.or.t", // TriCore_INS_AND.OR.T
"and.t", // TriCore_INS_AND.T
"and", // TriCore_INS_AND
"bisr", // TriCore_INS_BISR
"bmerge", // TriCore_INS_BMERGE
"bsplit", // TriCore_INS_BSPLIT
"cachei.i", // TriCore_INS_CACHEI.I
"cachei.wi", // TriCore_INS_CACHEI.WI
"cachei.w", // TriCore_INS_CACHEI.W
"cache.i", // TriCore_INS_CACHE.I
"cache.wi", // TriCore_INS_CACHE.WI
"cache.w", // TriCore_INS_CACHE.W
"caddn", // TriCore_INS_CADDN
"cadd", // TriCore_INS_CADD
"calla", // TriCore_INS_CALLA
"calli", // TriCore_INS_CALLI
"call", // TriCore_INS_CALL
"clo.h", // TriCore_INS_CLO.H
"clo", // TriCore_INS_CLO
"cls.h", // TriCore_INS_CLS.H
"cls", // TriCore_INS_CLS
"clz.h", // TriCore_INS_CLZ.H
"clz", // TriCore_INS_CLZ
"cmovn", // TriCore_INS_CMOVN
"cmov", // TriCore_INS_CMOV
"CMPSWAP.W", // TriCore_INS_CMPSWAP.W
"crc32b.w", // TriCore_INS_CRC32B.W
"crc32l.w", // TriCore_INS_CRC32L.W
"crc32.b", // TriCore_INS_CRC32.B
"crcn", // TriCore_INS_CRCN
"csub", // TriCore_INS_CSUB
"debug", // TriCore_INS_DEBUG
"dextr", // TriCore_INS_DEXTR
"disable", // TriCore_INS_DISABLE
"div.u", // TriCore_INS_DIV.U
"div", // TriCore_INS_DIV
"dsync", // TriCore_INS_DSYNC
"dvadj", // TriCore_INS_DVADJ
"dvinit.bu", // TriCore_INS_DVINIT.BU
"dvinit.b", // TriCore_INS_DVINIT.B
"dvinit.hu", // TriCore_INS_DVINIT.HU
"dvinit.h", // TriCore_INS_DVINIT.H
"dvinit.u", // TriCore_INS_DVINIT.U
"dvinit", // TriCore_INS_DVINIT
"dvstep.u", // TriCore_INS_DVSTEP.U
"dvstep", // TriCore_INS_DVSTEP
"enable", // TriCore_INS_ENABLE
"eqany.b", // TriCore_INS_EQANY.B
"eqany.h", // TriCore_INS_EQANY.H
"eqz.a", // TriCore_INS_EQZ.A
"eq.a", // TriCore_INS_EQ.A
"eq.b", // TriCore_INS_EQ.B
"eq.h", // TriCore_INS_EQ.H
"eq.w", // TriCore_INS_EQ.W
"eq", // TriCore_INS_EQ
"extr.u", // TriCore_INS_EXTR.U
"extr", // TriCore_INS_EXTR
"fcalla", // TriCore_INS_FCALLA
"fcalli", // TriCore_INS_FCALLI
"fcall", // TriCore_INS_FCALL
"fret", // TriCore_INS_FRET
"ge.a", // TriCore_INS_GE.A
"ge.u", // TriCore_INS_GE.U
"ge", // TriCore_INS_GE
"imask", // TriCore_INS_IMASK
"insert", // TriCore_INS_INSERT
"insn.t", // TriCore_INS_INSN.T
"ins.t", // TriCore_INS_INS.T
"isync", // TriCore_INS_ISYNC
"ixmax.u", // TriCore_INS_IXMAX.U
"ixmax", // TriCore_INS_IXMAX
"ixmin.u", // TriCore_INS_IXMIN.U
"ixmin", // TriCore_INS_IXMIN
"ja", // TriCore_INS_JA
"jeq.a", // TriCore_INS_JEQ.A
"jeq", // TriCore_INS_JEQ
"jgez", // TriCore_INS_JGEZ
"jge.u", // TriCore_INS_JGE.U
"jge", // TriCore_INS_JGE
"jgtz", // TriCore_INS_JGTZ
"ji", // TriCore_INS_JI
"jla", // TriCore_INS_JLA
"jlez", // TriCore_INS_JLEZ
"jli", // TriCore_INS_JLI
"jltz", // TriCore_INS_JLTZ
"jlt.u", // TriCore_INS_JLT.U
"jlt", // TriCore_INS_JLT
"jl", // TriCore_INS_JL
"jned", // TriCore_INS_JNED
"jnei", // TriCore_INS_JNEI
"jne.a", // TriCore_INS_JNE.A
"jne", // TriCore_INS_JNE
"jnz.a", // TriCore_INS_JNZ.A
"jnz.t", // TriCore_INS_JNZ.T
"jnz", // TriCore_INS_JNZ
"jz.a", // TriCore_INS_JZ.A
"jz.t", // TriCore_INS_JZ.T
"jz", // TriCore_INS_JZ
"j", // TriCore_INS_J
"ldlcx", // TriCore_INS_LDLCX
"ldmst", // TriCore_INS_LDMST
"lducx", // TriCore_INS_LDUCX
"ld.a", // TriCore_INS_LD.A
"ld.bu", // TriCore_INS_LD.BU
"ld.b", // TriCore_INS_LD.B
"ld.da", // TriCore_INS_LD.DA
"ld.d", // TriCore_INS_LD.D
"ld.hu", // TriCore_INS_LD.HU
"ld.h", // TriCore_INS_LD.H
"ld.q", // TriCore_INS_LD.Q
"ld.w", // TriCore_INS_LD.W
"lea", // TriCore_INS_LEA
"lha", // TriCore_INS_LHA
"loopu", // TriCore_INS_LOOPU
"loop", // TriCore_INS_LOOP
"lt.a", // TriCore_INS_LT.A
"lt.b", // TriCore_INS_LT.B
"lt.bu", // TriCore_INS_LT.BU
"lt.h", // TriCore_INS_LT.H
"lt.hu", // TriCore_INS_LT.HU
"lt.u", // TriCore_INS_LT.U
"lt.w", // TriCore_INS_LT.W
"lt.wu", // TriCore_INS_LT.WU
"lt", // TriCore_INS_LT
"maddms.h", // TriCore_INS_MADDMS.H
"maddm.h", // TriCore_INS_MADDM.H
"maddrs.h", // TriCore_INS_MADDRS.H
"maddrs.q", // TriCore_INS_MADDRS.Q
"maddr.h", // TriCore_INS_MADDR.H
"maddr.q", // TriCore_INS_MADDR.Q
"maddsums.h", // TriCore_INS_MADDSUMS.H
"maddsum.h", // TriCore_INS_MADDSUM.H
"maddsurs.h", // TriCore_INS_MADDSURS.H
"maddsur.h", // TriCore_INS_MADDSUR.H
"maddsus.h", // TriCore_INS_MADDSUS.H
"maddsu.h", // TriCore_INS_MADDSU.H
"madds.h", // TriCore_INS_MADDS.H
"madds.q", // TriCore_INS_MADDS.Q
"madds.u", // TriCore_INS_MADDS.U
"madds", // TriCore_INS_MADDS
"madd.h", // TriCore_INS_MADD.H
"madd.q", // TriCore_INS_MADD.Q
"madd.u", // TriCore_INS_MADD.U
"madd", // TriCore_INS_MADD
"max.b", // TriCore_INS_MAX.B
"max.bu", // TriCore_INS_MAX.BU
"max.h", // TriCore_INS_MAX.H
"max.hu", // TriCore_INS_MAX.HU
"max.u", // TriCore_INS_MAX.U
"max", // TriCore_INS_MAX
"mfcr", // TriCore_INS_MFCR
"min.b", // TriCore_INS_MIN.B
"min.bu", // TriCore_INS_MIN.BU
"min.h", // TriCore_INS_MIN.H
"min.hu", // TriCore_INS_MIN.HU
"min.u", // TriCore_INS_MIN.U
"min", // TriCore_INS_MIN
"movh.a", // TriCore_INS_MOVH.A
"mov.aa", // TriCore_INS_MOV.AA
"mov.a", // TriCore_INS_MOV.A
"mov.d", // TriCore_INS_MOV.D
"mov.h", // TriCore_INS_MOV.H
"mov.u", // TriCore_INS_MOV.U
"mov", // TriCore_INS_MOV
"msubadms.h", // TriCore_INS_MSUBADMS.H
"msubadm.h", // TriCore_INS_MSUBADM.H
"msubadrs.h", // TriCore_INS_MSUBADRS.H
"msubadr.h", // TriCore_INS_MSUBADR.H
"msubads.h", // TriCore_INS_MSUBADS.H
"msubad.h", // TriCore_INS_MSUBAD.H
"msubms.h", // TriCore_INS_MSUBMS.H
"msubm.h", // TriCore_INS_MSUBM.H
"msubrs.h", // TriCore_INS_MSUBRS.H
"msubrs.q", // TriCore_INS_MSUBRS.Q
"msubr.h", // TriCore_INS_MSUBR.H
"msubr.q", // TriCore_INS_MSUBR.Q
"msubs.h", // TriCore_INS_MSUBS.H
"msubs.q", // TriCore_INS_MSUBS.Q
"msubs", // TriCore_INS_MSUBS
"msub.h", // TriCore_INS_MSUB.H
"msub.q", // TriCore_INS_MSUB.Q
"msub", // TriCore_INS_MSUB
"mulm.h", // TriCore_INS_MULM.H
"mulr.h", // TriCore_INS_MULR.H
"mulr.q", // TriCore_INS_MULR.Q
"muls.u", // TriCore_INS_MULS.U
"muls", // TriCore_INS_MULS
"mul.h", // TriCore_INS_MUL.H
"mul.q", // TriCore_INS_MUL.Q
"mul.u", // TriCore_INS_MUL.U
"mul", // TriCore_INS_MUL
"nand.t", // TriCore_INS_NAND.T
"nand", // TriCore_INS_NAND
"nez.a", // TriCore_INS_NEZ.A
"ne.a", // TriCore_INS_NE.A
"ne", // TriCore_INS_NE
"nop", // TriCore_INS_NOP
"nor.t", // TriCore_INS_NOR.T
"nor", // TriCore_INS_NOR
"not", // TriCore_INS_NOT
"orn.t", // TriCore_INS_ORN.T
"orn", // TriCore_INS_ORN
"or.andn.t", // TriCore_INS_OR.ANDN.T
"or.and.t", // TriCore_INS_OR.AND.T
"or.eq", // TriCore_INS_OR.EQ
"or.ge.u", // TriCore_INS_OR.GE.U
"or.ge", // TriCore_INS_OR.GE
"or.lt.u", // TriCore_INS_OR.LT.U
"or.lt", // TriCore_INS_OR.LT
"or.ne", // TriCore_INS_OR.NE
"or.nor.t", // TriCore_INS_OR.NOR.T
"or.or.t", // TriCore_INS_OR.OR.T
"or.t", // TriCore_INS_OR.T
"or", // TriCore_INS_OR
"pack", // TriCore_INS_PACK
"parity", // TriCore_INS_PARITY
"popcnt.w", // TriCore_INS_POPCNT.W
"restore", // TriCore_INS_RESTORE
"ret", // TriCore_INS_RET
"rfe", // TriCore_INS_RFE
"rfm", // TriCore_INS_RFM
"relck", // TriCore_INS_RELCK
"rsubs.u", // TriCore_INS_RSUBS.U
"rsubs", // TriCore_INS_RSUBS
"rsub", // TriCore_INS_RSUB
"sat.bu", // TriCore_INS_SAT.BU
"sat.b", // TriCore_INS_SAT.B
"sat.hu", // TriCore_INS_SAT.HU
"sat.h", // TriCore_INS_SAT.H
"seln", // TriCore_INS_SELN
"sel", // TriCore_INS_SEL
"shas", // TriCore_INS_SHAS
"sha.h", // TriCore_INS_SHA.H
"sha", // TriCore_INS_SHA
"shuffle", // TriCore_INS_SHUFFLE
"sh.andn.t", // TriCore_INS_SH.ANDN.T
"sh.and.t", // TriCore_INS_SH.AND.T
"sh.eq", // TriCore_INS_SH.EQ
"sh.ge.u", // TriCore_INS_SH.GE.U
"sh.ge", // TriCore_INS_SH.GE
"sh.h", // TriCore_INS_SH.H
"sh.lt.u", // TriCore_INS_SH.LT.U
"sh.lt", // TriCore_INS_SH.LT
"sh.nand.t", // TriCore_INS_SH.NAND.T
"sh.nor.t", // TriCore_INS_SH.NOR.T
"sh.orn.t", // TriCore_INS_SH.ORN.T
"sh.or.t", // TriCore_INS_SH.OR.T
"sh.xnor.t", // TriCore_INS_SH.XNOR.T
"sh.xor.t", // TriCore_INS_SH.XOR.T
"sh", // TriCore_INS_SH
"stlcx", // TriCore_INS_STLCX
"stucx", // TriCore_INS_STUCX
"st.a", // TriCore_INS_ST.A
"st.b", // TriCore_INS_ST.B
"st.da", // TriCore_INS_ST.DA
"st.d", // TriCore_INS_ST.D
"st.h", // TriCore_INS_ST.H
"st.q", // TriCore_INS_ST.Q
"st.t", // TriCore_INS_ST.T
"st.w", // TriCore_INS_ST.W
"subc", // TriCore_INS_SUBC
"subs.hu", // TriCore_INS_SUBS.HU
"subs.h", // TriCore_INS_SUBS.H
"subs.u", // TriCore_INS_SUBS.U
"subs", // TriCore_INS_SUBS
"subx", // TriCore_INS_SUBX
"sub.a", // TriCore_INS_SUB.A
"sub.b", // TriCore_INS_SUB.B
"sub.h", // TriCore_INS_SUB.H
"sub", // TriCore_INS_SUB
"svlcx", // TriCore_INS_SVLCX
"swapmsk.w", // TriCore_INS_SWAPMSK.W
"swap.w", // TriCore_INS_SWAP.W
"syscall", // TriCore_INS_SYSCALL
"trapsv", // TriCore_INS_TRAPSV
"trapv", // TriCore_INS_TRAPV
"unpack", // TriCore_INS_UNPACK
"wait", // TriCore_INS_WAIT
"xnor.t", // TriCore_INS_XNOR.T
"xnor", // TriCore_INS_XNOR
"xor.eq", // TriCore_INS_XOR.EQ
"xor.ge.u", // TriCore_INS_XOR.GE.U
"xor.ge", // TriCore_INS_XOR.GE
"xor.lt.u", // TriCore_INS_XOR.LT.U
"xor.lt", // TriCore_INS_XOR.LT
"xor.ne", // TriCore_INS_XOR.NE
"xor.t", // TriCore_INS_XOR.T
"xor", // TriCore_INS_XOR

520
include/capstone/tricore.h
View File

@ -53,140 +53,406 @@ typedef struct cs_tricore {
//> TriCore registers
typedef enum tricore_reg {
TRICORE_REG_INVALID = 0,
TriCore_REG_INVALID = 0,
TriCore_REG_FCX = 1,
TriCore_REG_PC = 2,
TriCore_REG_PCXI = 3,
TriCore_REG_PSW = 4,
TriCore_REG_A0 = 5,
TriCore_REG_A1 = 6,
TriCore_REG_A2 = 7,
TriCore_REG_A3 = 8,
TriCore_REG_A4 = 9,
TriCore_REG_A5 = 10,
TriCore_REG_A6 = 11,
TriCore_REG_A7 = 12,
TriCore_REG_A8 = 13,
TriCore_REG_A9 = 14,
TriCore_REG_A10 = 15,
TriCore_REG_A11 = 16,
TriCore_REG_A12 = 17,
TriCore_REG_A13 = 18,
TriCore_REG_A14 = 19,
TriCore_REG_A15 = 20,
TriCore_REG_D0 = 21,
TriCore_REG_D1 = 22,
TriCore_REG_D2 = 23,
TriCore_REG_D3 = 24,
TriCore_REG_D4 = 25,
TriCore_REG_D5 = 26,
TriCore_REG_D6 = 27,
TriCore_REG_D7 = 28,
TriCore_REG_D8 = 29,
TriCore_REG_D9 = 30,
TriCore_REG_D10 = 31,
TriCore_REG_D11 = 32,
TriCore_REG_D12 = 33,
TriCore_REG_D13 = 34,
TriCore_REG_D14 = 35,
TriCore_REG_D15 = 36,
TriCore_REG_E0 = 37,
TriCore_REG_E2 = 38,
TriCore_REG_E4 = 39,
TriCore_REG_E6 = 40,
TriCore_REG_E8 = 41,
TriCore_REG_E10 = 42,
TriCore_REG_E12 = 43,
TriCore_REG_E14 = 44,
TriCore_REG_P0 = 45,
TriCore_REG_P2 = 46,
TriCore_REG_P4 = 47,
TriCore_REG_P6 = 48,
TriCore_REG_P8 = 49,
TriCore_REG_P10 = 50,
TriCore_REG_P12 = 51,
TriCore_REG_P14 = 52,
TriCore_REG_A0_A1 = 53,
TriCore_REG_A2_A3 = 54,
TriCore_REG_A4_A5 = 55,
TriCore_REG_A6_A7 = 56,
TriCore_REG_A8_A9 = 57,
TriCore_REG_A10_A11 = 58,
TriCore_REG_A12_A13 = 59,
TriCore_REG_A14_A15 = 60,
TRICORE_REG_D0,
TRICORE_REG_D1,
TRICORE_REG_D2,
TRICORE_REG_D3,
TRICORE_REG_D4,
TRICORE_REG_D5,
TRICORE_REG_D6,
TRICORE_REG_D7,
TRICORE_REG_D8,
TRICORE_REG_D9,
TRICORE_REG_D10,
TRICORE_REG_D11,
TRICORE_REG_D12,
TRICORE_REG_D13,
TRICORE_REG_D14,
TRICORE_REG_D15,
TRICORE_REG_A0,
TRICORE_REG_A1,
TRICORE_REG_A2,
TRICORE_REG_A3,
TRICORE_REG_A4,
TRICORE_REG_A5,
TRICORE_REG_A6,
TRICORE_REG_A7,
TRICORE_REG_A8,
TRICORE_REG_A9,
TRICORE_REG_A10,
TRICORE_REG_A11,
TRICORE_REG_A12,
TRICORE_REG_A13,
TRICORE_REG_A14,
TRICORE_REG_A15,
TRICORE_REG_E0,
TRICORE_REG_E2,
TRICORE_REG_E4,
TRICORE_REG_E6,
TRICORE_REG_E8,
TRICORE_REG_E10,
TRICORE_REG_E12,
TRICORE_REG_E14,
//> control registers
TRICORE_REG_PSW,
TRICORE_REG_PCXI,
TRICORE_REG_PC,
TRICORE_REG_FCX,
TRICORE_REG_ENDING, // <-- mark the end of the list of registers
TriCore_REG_ENDING, // <-- mark the end of the list of registers
} tricore_reg;
//> TriCore instruction
typedef enum tricore_insn {
TRICORE_INS_INVALID = 0,
TriCore_INS_INVALID = 0,
TRICORE_INS_ABS,
TRICORE_INS_ADDC,
TRICORE_INS_ADDI,
TRICORE_INS_ADDX,
TRICORE_INS_ADD_A,
TRICORE_INS_ADD,
TRICORE_INS_ANDN,
TRICORE_INS_AND_EQ,
TRICORE_INS_AND_GE_U,
TRICORE_INS_AND_GE,
TRICORE_INS_AND_LT_U,
TRICORE_INS_AND_LT,
TRICORE_INS_AND_NE,
TRICORE_INS_AND,
TRICORE_INS_CALL,
TRICORE_INS_DEXTR,
TRICORE_INS_EQ,
TRICORE_INS_EXTR,
TRICORE_INS_GE,
TRICORE_INS_IMASK,
TRICORE_INS_JNZ,
TRICORE_INS_JZ,
TRICORE_INS_J,
TRICORE_INS_LD_A,
TRICORE_INS_LD_BU,
TRICORE_INS_LD_B,
TRICORE_INS_LD_DA,
TRICORE_INS_LD_D,
TRICORE_INS_LD_HU,
TRICORE_INS_LD_H,
TRICORE_INS_LD_Q,
TRICORE_INS_LD_W,
TRICORE_INS_LT,
TRICORE_INS_MOVH,
TRICORE_INS_MOV_AA,
TRICORE_INS_MOV_A,
TRICORE_INS_MOV_D,
TRICORE_INS_MOV_U,
TRICORE_INS_MOV,
TRICORE_INS_MUL,
TRICORE_INS_NAND,
TRICORE_INS_NE,
TRICORE_INS_NOR,
TRICORE_INS_NOT,
TRICORE_INS_ORN,
TRICORE_INS_OR_EQ,
TRICORE_INS_OR_GE_U,
TRICORE_INS_OR_GE,
TRICORE_INS_OR_LT_U,
TRICORE_INS_OR_LT,
TRICORE_INS_OR_NE,
TRICORE_INS_OR,
TRICORE_INS_RET,
TRICORE_INS_RSUB,
TRICORE_INS_SHA,
TRICORE_INS_SH,
TRICORE_INS_ST_A,
TRICORE_INS_ST_B,
TRICORE_INS_ST_DA,
TRICORE_INS_ST_D,
TRICORE_INS_ST_H,
TRICORE_INS_ST_Q,
TRICORE_INS_ST_W,
TRICORE_INS_SUBC,
TRICORE_INS_SUBX,
TRICORE_INS_SUB_A,
TRICORE_INS_SUB,
TRICORE_INS_Select8,
TRICORE_INS_XNOR,
TRICORE_INS_XOR_EQ,
TRICORE_INS_XOR_GE_U,
TRICORE_INS_XOR_GE,
TRICORE_INS_XOR_LT_U,
TRICORE_INS_XOR_LT,
TRICORE_INS_XOR_NE,
TRICORE_INS_XOR,
TriCore_INS_ABSDIFS_H,
TriCore_INS_ABSDIFS,
TriCore_INS_ABSDIF_B,
TriCore_INS_ABSDIF_H,
TriCore_INS_ABSDIF,
TriCore_INS_ABSS_H,
TriCore_INS_ABSS,
TriCore_INS_ABS_B,
TriCore_INS_ABS_H,
TriCore_INS_ABS,
TriCore_INS_ADDC,
TriCore_INS_ADDIH_A,
TriCore_INS_ADDIH,
TriCore_INS_ADDI,
TriCore_INS_ADDSC_AT,
TriCore_INS_ADDSC_A,
TriCore_INS_ADDS_H,
TriCore_INS_ADDS_HU,
TriCore_INS_ADDS_U,
TriCore_INS_ADDS,
TriCore_INS_ADDX,
TriCore_INS_ADD_A,
TriCore_INS_ADD_B,
TriCore_INS_ADD_H,
TriCore_INS_ADD,
TriCore_INS_ANDN_T,
TriCore_INS_ANDN,
TriCore_INS_AND_ANDN_T,
TriCore_INS_AND_AND_T,
TriCore_INS_AND_EQ,
TriCore_INS_AND_GE_U,
TriCore_INS_AND_GE,
TriCore_INS_AND_LT_U,
TriCore_INS_AND_LT,
TriCore_INS_AND_NE,
TriCore_INS_AND_NOR_T,
TriCore_INS_AND_OR_T,
TriCore_INS_AND_T,
TriCore_INS_AND,
TriCore_INS_BISR,
TriCore_INS_BMERGE,
TriCore_INS_BSPLIT,
TriCore_INS_CACHEI_I,
TriCore_INS_CACHEI_WI,
TriCore_INS_CACHEI_W,
TriCore_INS_CACHE_I,
TriCore_INS_CACHE_WI,
TriCore_INS_CACHE_W,
TriCore_INS_CADDN,
TriCore_INS_CADD,
TriCore_INS_CALLA,
TriCore_INS_CALLI,
TriCore_INS_CALL,
TriCore_INS_CLO_H,
TriCore_INS_CLO,
TriCore_INS_CLS_H,
TriCore_INS_CLS,
TriCore_INS_CLZ_H,
TriCore_INS_CLZ,
TriCore_INS_CMOVN,
TriCore_INS_CMOV,
TriCore_INS_CMPSWAP_W,
TriCore_INS_CRC32B_W,
TriCore_INS_CRC32L_W,
TriCore_INS_CRC32_B,
TriCore_INS_CRCN,
TriCore_INS_CSUB,
TriCore_INS_DEBUG,
TriCore_INS_DEXTR,
TriCore_INS_DISABLE,
TriCore_INS_DIV_U,
TriCore_INS_DIV,
TriCore_INS_DSYNC,
TriCore_INS_DVADJ,
TriCore_INS_DVINIT_BU,
TriCore_INS_DVINIT_B,
TriCore_INS_DVINIT_HU,
TriCore_INS_DVINIT_H,
TriCore_INS_DVINIT_U,
TriCore_INS_DVINIT,
TriCore_INS_DVSTEP_U,
TriCore_INS_DVSTEP,
TriCore_INS_ENABLE,
TriCore_INS_EQANY_B,
TriCore_INS_EQANY_H,
TriCore_INS_EQZ_A,
TriCore_INS_EQ_A,
TriCore_INS_EQ_B,
TriCore_INS_EQ_H,
TriCore_INS_EQ_W,
TriCore_INS_EQ,
TriCore_INS_EXTR_U,
TriCore_INS_EXTR,
TriCore_INS_FCALLA,
TriCore_INS_FCALLI,
TriCore_INS_FCALL,
TriCore_INS_FRET,
TriCore_INS_GE_A,
TriCore_INS_GE_U,
TriCore_INS_GE,
TriCore_INS_IMASK,
TriCore_INS_INSERT,
TriCore_INS_INSN_T,
TriCore_INS_INS_T,
TriCore_INS_ISYNC,
TriCore_INS_IXMAX_U,
TriCore_INS_IXMAX,
TriCore_INS_IXMIN_U,
TriCore_INS_IXMIN,
TriCore_INS_JA,
TriCore_INS_JEQ_A,
TriCore_INS_JEQ,
TriCore_INS_JGEZ,
TriCore_INS_JGE_U,
TriCore_INS_JGE,
TriCore_INS_JGTZ,
TriCore_INS_JI,
TriCore_INS_JLA,
TriCore_INS_JLEZ,
TriCore_INS_JLI,
TriCore_INS_JLTZ,
TriCore_INS_JLT_U,
TriCore_INS_JLT,
TriCore_INS_JL,
TriCore_INS_JNED,
TriCore_INS_JNEI,
TriCore_INS_JNE_A,
TriCore_INS_JNE,
TriCore_INS_JNZ_A,
TriCore_INS_JNZ_T,
TriCore_INS_JNZ,
TriCore_INS_JZ_A,
TriCore_INS_JZ_T,
TriCore_INS_JZ,
TriCore_INS_J,
TriCore_INS_LDLCX,
TriCore_INS_LDMST,
TriCore_INS_LDUCX,
TriCore_INS_LD_A,
TriCore_INS_LD_BU,
TriCore_INS_LD_B,
TriCore_INS_LD_DA,
TriCore_INS_LD_D,
TriCore_INS_LD_HU,
TriCore_INS_LD_H,
TriCore_INS_LD_Q,
TriCore_INS_LD_W,
TriCore_INS_LEA,
TriCore_INS_LHA,
TriCore_INS_LOOPU,
TriCore_INS_LOOP,
TriCore_INS_LT_A,
TriCore_INS_LT_B,
TriCore_INS_LT_BU,
TriCore_INS_LT_H,
TriCore_INS_LT_HU,
TriCore_INS_LT_U,
TriCore_INS_LT_W,
TriCore_INS_LT_WU,
TriCore_INS_LT,
TriCore_INS_MADDMS_H,
TriCore_INS_MADDM_H,
TriCore_INS_MADDRS_H,
TriCore_INS_MADDRS_Q,
TriCore_INS_MADDR_H,
TriCore_INS_MADDR_Q,
TriCore_INS_MADDSUMS_H,
TriCore_INS_MADDSUM_H,
TriCore_INS_MADDSURS_H,
TriCore_INS_MADDSUR_H,
TriCore_INS_MADDSUS_H,
TriCore_INS_MADDSU_H,
TriCore_INS_MADDS_H,
TriCore_INS_MADDS_Q,
TriCore_INS_MADDS_U,
TriCore_INS_MADDS,
TriCore_INS_MADD_H,
TriCore_INS_MADD_Q,
TriCore_INS_MADD_U,
TriCore_INS_MADD,
TriCore_INS_MAX_B,
TriCore_INS_MAX_BU,
TriCore_INS_MAX_H,
TriCore_INS_MAX_HU,
TriCore_INS_MAX_U,
TriCore_INS_MAX,
TriCore_INS_MFCR,
TriCore_INS_MIN_B,
TriCore_INS_MIN_BU,
TriCore_INS_MIN_H,
TriCore_INS_MIN_HU,
TriCore_INS_MIN_U,
TriCore_INS_MIN,
TriCore_INS_MOVH_A,
TriCore_INS_MOV_AA,
TriCore_INS_MOV_A,
TriCore_INS_MOV_D,
TriCore_INS_MOV_H,
TriCore_INS_MOV_U,
TriCore_INS_MOV,
TriCore_INS_MSUBADMS_H,
TriCore_INS_MSUBADM_H,
TriCore_INS_MSUBADRS_H,
TriCore_INS_MSUBADR_H,
TriCore_INS_MSUBADS_H,
TriCore_INS_MSUBAD_H,
TriCore_INS_MSUBMS_H,
TriCore_INS_MSUBM_H,
TriCore_INS_MSUBRS_H,
TriCore_INS_MSUBRS_Q,
TriCore_INS_MSUBR_H,
TriCore_INS_MSUBR_Q,
TriCore_INS_MSUBS_H,
TriCore_INS_MSUBS_Q,
TriCore_INS_MSUBS,
TriCore_INS_MSUB_H,
TriCore_INS_MSUB_Q,
TriCore_INS_MSUB,
TriCore_INS_MULM_H,
TriCore_INS_MULR_H,
TriCore_INS_MULR_Q,
TriCore_INS_MULS_U,
TriCore_INS_MULS,
TriCore_INS_MUL_H,
TriCore_INS_MUL_Q,
TriCore_INS_MUL_U,
TriCore_INS_MUL,
TriCore_INS_NAND_T,
TriCore_INS_NAND,
TriCore_INS_NEZ_A,
TriCore_INS_NE_A,
TriCore_INS_NE,
TriCore_INS_NOP,
TriCore_INS_NOR_T,
TriCore_INS_NOR,
TriCore_INS_NOT,
TriCore_INS_ORN_T,
TriCore_INS_ORN,
TriCore_INS_OR_ANDN_T,
TriCore_INS_OR_AND_T,
TriCore_INS_OR_EQ,
TriCore_INS_OR_GE_U,
TriCore_INS_OR_GE,
TriCore_INS_OR_LT_U,
TriCore_INS_OR_LT,
TriCore_INS_OR_NE,
TriCore_INS_OR_NOR_T,
TriCore_INS_OR_OR_T,
TriCore_INS_OR_T,
TriCore_INS_OR,
TriCore_INS_PACK,
TriCore_INS_PARITY,
TriCore_INS_POPCNT_W,
TriCore_INS_RESTORE,
TriCore_INS_RET,
TriCore_INS_RFE,
TriCore_INS_RFM,
TriCore_INS_RELCK,
TriCore_INS_RSUBS_U,
TriCore_INS_RSUBS,
TriCore_INS_RSUB,
TriCore_INS_SAT_BU,
TriCore_INS_SAT_B,
TriCore_INS_SAT_HU,
TriCore_INS_SAT_H,
TriCore_INS_SELN,
TriCore_INS_SEL,
TriCore_INS_SHAS,
TriCore_INS_SHA_H,
TriCore_INS_SHA,
TriCore_INS_SHUFFLE,
TriCore_INS_SH_ANDN_T,
TriCore_INS_SH_AND_T,
TriCore_INS_SH_EQ,
TriCore_INS_SH_GE_U,
TriCore_INS_SH_GE,
TriCore_INS_SH_H,
TriCore_INS_SH_LT_U,
TriCore_INS_SH_LT,
TriCore_INS_SH_NAND_T,
TriCore_INS_SH_NOR_T,
TriCore_INS_SH_ORN_T,
TriCore_INS_SH_OR_T,
TriCore_INS_SH_XNOR_T,
TriCore_INS_SH_XOR_T,
TriCore_INS_SH,
TriCore_INS_STLCX,
TriCore_INS_STUCX,
TriCore_INS_ST_A,
TriCore_INS_ST_B,
TriCore_INS_ST_DA,
TriCore_INS_ST_D,
TriCore_INS_ST_H,
TriCore_INS_ST_Q,
TriCore_INS_ST_T,
TriCore_INS_ST_W,
TriCore_INS_SUBC,
TriCore_INS_SUBS_HU,
TriCore_INS_SUBS_H,
TriCore_INS_SUBS_U,
TriCore_INS_SUBS,
TriCore_INS_SUBX,
TriCore_INS_SUB_A,
TriCore_INS_SUB_B,
TriCore_INS_SUB_H,
TriCore_INS_SUB,
TriCore_INS_SVLCX,
TriCore_INS_SWAPMSK_W,
TriCore_INS_SWAP_W,
TriCore_INS_SYSCALL,
TriCore_INS_TRAPSV,
TriCore_INS_TRAPV,
TriCore_INS_UNPACK,
TriCore_INS_WAIT,
TriCore_INS_XNOR_T,
TriCore_INS_XNOR,
TriCore_INS_XOR_EQ,
TriCore_INS_XOR_GE_U,
TriCore_INS_XOR_GE,
TriCore_INS_XOR_LT_U,
TriCore_INS_XOR_LT,
TriCore_INS_XOR_NE,
TriCore_INS_XOR_T,
TriCore_INS_XOR,
TRICORE_INS_ENDING, // <-- mark the end of the list of instructions
TriCore_INS_ENDING, // <-- mark the end of the list of instructions
TriCore_GRP_CALL, ///< = CS_GRP_CALL
TriCore_GRP_JUMP, ///< = CS_GRP_JUMP
TriCore_GRP_INVALID, ///< = CS_GRP_INVALID
TriCore_GRP_ENDING, ///< = CS_GRP_ENDING
} tricore_insn;
//> Group of TriCore instructions

2
tests/test_tricore.c
View File

@ -54,7 +54,7 @@ static void print_insn_detail(cs_insn *ins)
break;
case TRICORE_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != TRICORE_REG_INVALID)
if (op->mem.base != TriCore_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.disp != 0)