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x86: quick fix for RCRm1 instruction - issue #1456

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This commit is contained in:
Nguyen Anh Quynh 2019-04-12 00:38:23 +08:00
parent 3d50d2cffd
commit 38d181d148
2 changed files with 32 additions and 0 deletions
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10
arch/X86/X86GenAsmWriter.inc
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@ -47558,6 +47558,16 @@ static void printInstruction(MCInst *MI, SStream *O)
Bits |= (uint64_t)OpInfo2[opcode] << 48;
SStream_concat0(O, AsmStrs+(Bits & 16383)-1);
// TODO: dirty quick hack. fix tablegen instead
switch(MCInst_getOpcode(MI)) {
default: break;
case X86_RCR8m1:
case X86_RCR16m1:
case X86_RCR32m1:
case X86_RCR64m1:
SStream_concat0(O, "\t$1, ");
break;
}
// Fragment 0 encoded into 7 bits for 103 unique commands.
// printf("Fragment 0: %"PRIu64"\n", ((Bits >> 14) & 127));

22
arch/X86/X86IntelInstPrinter.c
View File

@ -729,6 +729,28 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
if (MI->op1_size == 0 && reg)
MI->op1_size = MI->csh->regsize_map[reg];
// TODO: dirty quick hack. fix tablegen instead
// printf("opcode = %u\n", MCInst_getOpcode(MI));
switch(MCInst_getOpcode(MI)) {
default:
break;
case X86_RCR8m1:
case X86_RCR16m1:
case X86_RCR32m1:
case X86_RCR64m1:
SStream_concat0(O, ", 1");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[1].type = X86_OP_IMM;
MI->flat_insn->detail->x86.operands[1].imm = 1;
MI->flat_insn->detail->x86.operands[1].size = 1;
MI->flat_insn->detail->x86.op_count = 2;
}
break;
}
}
/// printPCRelImm - This is used to print an immediate value that ends up